1405 files changed, 36670 insertions, 19644 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 5b448a74d0f..a6f14f622d1 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -120,6 +120,9 @@ config HAVE_KRETPROBES
 
 config HAVE_OPTPROBES
         bool
+
+config HAVE_NMI_WATCHDOG
+        bool
 #
 # An arch should select this if it provides all these things:
 #
diff --git a/arch/alpha/include/asm/mman.h b/arch/alpha/include/asm/mman.h
index 72db984f878..cbeb3616a28 100644
--- a/arch/alpha/include/asm/mman.h
+++ b/arch/alpha/include/asm/mman.h
@@ -56,6 +56,10 @@
 #define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   16              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     17              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 
diff --git a/arch/alpha/include/asm/pci.h b/arch/alpha/include/asm/pci.h
index 28d0497fd3c..d01afb78919 100644
--- a/arch/alpha/include/asm/pci.h
+++ b/arch/alpha/include/asm/pci.h
@@ -7,6 +7,7 @@
 #include <linux/dma-mapping.h>
 #include <asm/scatterlist.h>
 #include <asm/machvec.h>
+#include <asm-generic/pci-bridge.h>
 
 /*
  * The following structure is used to manage multiple PCI busses.
@@ -99,12 +100,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
-extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
-                                    struct resource *);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 8c723c1b086..1a629636cc1 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -43,12 +43,10 @@ const char *const pci_mem_names[] = {
 
 const char pci_hae0_name[] = "HAE0";
 
-/* Indicate whether we respect the PCI setup left by console. */
 /*
- * Make this long-lived  so that we know when shutting down
- * whether we probed only or not.
+ * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
+ * assignments.
  */
-int pci_probe_only;
 
 /*
  * The PCI controller list.
@@ -215,7 +213,7 @@ pdev_save_srm_config(struct pci_dev *dev)
         struct pdev_srm_saved_conf *tmp;
         static int printed = 0;
 
-        if (!alpha_using_srm || pci_probe_only)
+        if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
                 return;
 
         if (!printed) {
@@ -242,7 +240,7 @@ pci_restore_srm_config(void)
         struct pdev_srm_saved_conf *tmp;
 
         /* No need to restore if probed only. */
-        if (pci_probe_only)
+        if (pci_has_flag(PCI_PROBE_ONLY))
                 return;
 
         /* Restore SRM config. */
@@ -253,46 +251,17 @@ pci_restore_srm_config(void)
 #endif
 
 void __devinit
-pcibios_fixup_resource(struct resource *res, struct resource *root)
-{
-        res->start += root->start;
-        res->end += root->start;
-}
-
-void __devinit
-pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        pcibios_fixup_resource(&dev->resource[i],
-                                               hose->io_space);
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        pcibios_fixup_resource(&dev->resource[i],
-                                               hose->mem_space);
-        }
-}
-
-void __devinit
 pcibios_fixup_bus(struct pci_bus *bus)
 {
         struct pci_dev *dev = bus->self;
 
-        if (pci_probe_only && dev &&
+        if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
                    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
                 pci_read_bridge_bases(bus);
-                pcibios_fixup_device_resources(dev, bus);
         } 
 
         list_for_each_entry(dev, &bus->devices, bus_list) {
                 pdev_save_srm_config(dev);
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
         }
 }
 
@@ -302,42 +271,6 @@ pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_space->start;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_space->start;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_space->start;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_space->start;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
-#ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-#endif
-
 int
 pcibios_enable_device(struct pci_dev *dev, int mask)
 {
@@ -374,7 +307,8 @@ pcibios_claim_one_bus(struct pci_bus *b)
 
                         if (r->parent || !r->start || !r->flags)
                                 continue;
-                        if (pci_probe_only || (r->flags & IORESOURCE_PCI_FIXED))
+                        if (pci_has_flag(PCI_PROBE_ONLY) ||
+                            (r->flags & IORESOURCE_PCI_FIXED))
                                 pci_claim_resource(dev, i);
                 }
         }
@@ -416,8 +350,10 @@ common_init_pci(void)
                         hose->mem_space->end = end;
 
                 INIT_LIST_HEAD(&resources);
-                pci_add_resource(&resources, hose->io_space);
-                pci_add_resource(&resources, hose->mem_space);
+                pci_add_resource_offset(&resources, hose->io_space,
+                                        hose->io_space->start);
+                pci_add_resource_offset(&resources, hose->mem_space,
+                                        hose->mem_space->start);
 
                 bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
                                         hose, &resources);
diff --git a/arch/alpha/kernel/pci_impl.h b/arch/alpha/kernel/pci_impl.h
index 85457b2d451..2b0ac429f5e 100644
--- a/arch/alpha/kernel/pci_impl.h
+++ b/arch/alpha/kernel/pci_impl.h
@@ -173,9 +173,6 @@ extern void pci_restore_srm_config(void);
 extern struct pci_controller *hose_head, **hose_tail;
 extern struct pci_controller *pci_isa_hose;
 
-/* Indicate that we trust the console to configure things properly.  */
-extern int pci_probe_only;
-
 extern unsigned long alpha_agpgart_size;
 
 extern void common_init_pci(void);
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index e8b4f6f8cbb..14a4b6a7cf5 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -383,7 +383,8 @@ marvel_init_pci(void)
 
         marvel_register_error_handlers();
 
-        pci_probe_only = 1;
+        /* Indicate that we trust the console to configure things properly */
+        pci_set_flags(PCI_PROBE_ONLY);
         common_init_pci();
         locate_and_init_vga(NULL);
 
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index 9de928c6ef9..2533db280d9 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -330,7 +330,8 @@ titan_init_pci(void)
          */
         titan_late_init();
  
-        pci_probe_only = 1;
+        /* Indicate that we trust the console to configure things properly */
+        pci_set_flags(PCI_PROBE_ONLY);
         common_init_pci();
         SMC669_Init(0);
         locate_and_init_vga(NULL);
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312f4e7..5098564d587 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -186,6 +186,9 @@ config GENERIC_ISA_DMA
 config FIQ
         bool
 
+config NEED_RET_TO_USER
+        bool
+
 config ARCH_MTD_XIP
         bool
 
@@ -322,9 +325,10 @@ config ARCH_AT91
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         select CLKDEV_LOOKUP
+        select IRQ_DOMAIN
         help
           This enables support for systems based on the Atmel AT91RM9200,
-          AT91SAM9 and AT91CAP9 processors.
+          AT91SAM9 processors.
 
 config ARCH_BCMRING
         bool "Broadcom BCMRING"
@@ -479,6 +483,7 @@ config ARCH_IOP13XX
         select ARCH_SUPPORTS_MSI
         select VMSPLIT_1G
         select NEED_MACH_MEMORY_H
+        select NEED_RET_TO_USER
         help
           Support for Intel's IOP13XX (XScale) family of processors.
 
@@ -486,6 +491,7 @@ config ARCH_IOP32X
         bool "IOP32x-based"
         depends on MMU
         select CPU_XSCALE
+        select NEED_RET_TO_USER
         select PLAT_IOP
         select PCI
         select ARCH_REQUIRE_GPIOLIB
@@ -497,6 +503,7 @@ config ARCH_IOP33X
         bool "IOP33x-based"
         depends on MMU
         select CPU_XSCALE
+        select NEED_RET_TO_USER
         select PLAT_IOP
         select PCI
         select ARCH_REQUIRE_GPIOLIB
@@ -731,7 +738,6 @@ config ARCH_RPC
         bool "RiscPC"
         select ARCH_ACORN
         select FIQ
-        select TIMER_ACORN
         select ARCH_MAY_HAVE_PC_FDC
         select HAVE_PATA_PLATFORM
         select ISA_DMA_API
@@ -754,31 +760,31 @@ config ARCH_SA1100
         select ARCH_HAS_CPUFREQ
         select CPU_FREQ
         select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
+        select CLKDEV_LOOKUP
         select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_IDE
         select NEED_MACH_MEMORY_H
+        select SPARSE_IRQ
         help
           Support for StrongARM 11x0 based boards.
 
-config ARCH_S3C2410
-        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
+config ARCH_S3C24XX
+        bool "Samsung S3C24XX SoCs"
         select GENERIC_GPIO
         select ARCH_HAS_CPUFREQ
         select HAVE_CLK
         select CLKDEV_LOOKUP
         select ARCH_USES_GETTIMEOFFSET
         select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C_RTC if RTC_CLASS
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
-          Samsung S3C2410X CPU based systems, such as the Simtec Electronics
-          BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
-          the Samsung SMDK2410 development board (and derivatives).
-
-          Note, the S3C2416 and the S3C2450 are so close that they even share
-          the same SoC ID code. This means that there is no separate machine
-          directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
+          Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
+          and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
+          (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
+          Samsung SMDK2410 development board (and derivatives).
 
 config ARCH_S3C64XX
         bool "Samsung S3C64XX"
@@ -901,6 +907,7 @@ config ARCH_U300
 
 config ARCH_U8500
         bool "ST-Ericsson U8500 Series"
+        depends on MMU
         select CPU_V7
         select ARM_AMBA
         select GENERIC_CLOCKEVENTS
@@ -1066,12 +1073,10 @@ source "arch/arm/plat-s5p/Kconfig"
 
 source "arch/arm/plat-spear/Kconfig"
 
-if ARCH_S3C2410
-source "arch/arm/mach-s3c2410/Kconfig"
+source "arch/arm/mach-s3c24xx/Kconfig"
+if ARCH_S3C24XX
 source "arch/arm/mach-s3c2412/Kconfig"
-source "arch/arm/mach-s3c2416/Kconfig"
 source "arch/arm/mach-s3c2440/Kconfig"
-source "arch/arm/mach-s3c2443/Kconfig"
 endif
 
 if ARCH_S3C64XX
@@ -1127,6 +1132,7 @@ config PLAT_VERSATILE
 config ARM_TIMER_SP804
         bool
         select CLKSRC_MMIO
+        select HAVE_SCHED_CLOCK
 
 source arch/arm/mm/Kconfig
 
@@ -1577,7 +1583,8 @@ config LOCAL_TIMERS
 config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
-        default 350 if ARCH_U8500
+        default 355 if ARCH_U8500
+        default 264 if MACH_H4700
         default 0
         help
           Maximum number of GPIOs in the system.
@@ -1588,7 +1595,7 @@ source kernel/Kconfig.preempt
 
 config HZ
         int
-        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
+        default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
                 ARCH_S5PV210 || ARCH_EXYNOS4
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
@@ -2114,7 +2121,7 @@ config CPU_FREQ_S3C
 
 config CPU_FREQ_S3C24XX
         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
-        depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
+        depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
         select CPU_FREQ_S3C
         help
           This enables the CPUfreq driver for the Samsung S3C24XX family
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e0d236d7ff7..66ca8014ff3 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -81,47 +81,14 @@ choice
         prompt "Kernel low-level debugging port"
         depends on DEBUG_LL
 
-        config DEBUG_LL_UART_NONE
-                bool "No low-level debugging UART"
-                help
-                  Say Y here if your platform doesn't provide a UART option
-                  below. This relies on your platform choosing the right UART
-                  definition internally in order for low-level debugging to
-                  work.
-
-        config DEBUG_ICEDCC
-                bool "Kernel low-level debugging via EmbeddedICE DCC channel"
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the EmbeddedICE macrocell's DCC channel using
-                  co-processor 14. This is known to work on the ARM9 style ICE
-                  channel and on the XScale with the PEEDI.
-
-                  Note that the system will appear to hang during boot if there
-                  is nothing connected to read from the DCC.
-
         config AT91_DEBUG_LL_DBGU0
                 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
                 depends on HAVE_AT91_DBGU0
 
         config AT91_DEBUG_LL_DBGU1
-                bool "Kernel low-level debugging on 9263, 9g45 and cap9"
+                bool "Kernel low-level debugging on 9263 and 9g45"
                 depends on HAVE_AT91_DBGU1
 
-        config DEBUG_FOOTBRIDGE_COM1
-                bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
-                depends on FOOTBRIDGE
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the 8250 at PCI COM1.
-
-        config DEBUG_DC21285_PORT
-                bool "Kernel low-level debugging messages via footbridge serial port"
-                depends on FOOTBRIDGE
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the serial port in the DC21285 (Footbridge).
-
         config DEBUG_CLPS711X_UART1
                 bool "Kernel low-level debugging messages via UART1"
                 depends on ARCH_CLPS711X
@@ -136,6 +103,20 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the second serial port on these devices.
 
+        config DEBUG_DC21285_PORT
+                bool "Kernel low-level debugging messages via footbridge serial port"
+                depends on FOOTBRIDGE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port in the DC21285 (Footbridge).
+
+        config DEBUG_FOOTBRIDGE_COM1
+                bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
+                depends on FOOTBRIDGE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the 8250 at PCI COM1.
+
         config DEBUG_HIGHBANK_UART
                 bool "Kernel low-level debugging messages via Highbank UART"
                 depends on ARCH_HIGHBANK
@@ -199,45 +180,49 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on i.MX50 or i.MX53.
 
-        config DEBUG_IMX6Q_UART
-                bool "i.MX6Q Debug UART"
+        config DEBUG_IMX6Q_UART4
+                bool "i.MX6Q Debug UART4"
                 depends on SOC_IMX6Q
                 help
                   Say Y here if you want kernel low-level debugging support
-                  on i.MX6Q.
+                  on i.MX6Q UART4.
 
-        config DEBUG_S3C_UART0
-                depends on PLAT_SAMSUNG
-                bool "Use S3C UART 0 for low-level debug"
+        config DEBUG_MSM_UART1
+                bool "Kernel low-level debugging messages via MSM UART1"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to UART 0. The port must have been initialised
-                  by the boot-loader before use.
-
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+                  their output to the first serial port on MSM devices.
 
-        config DEBUG_S3C_UART1
-                depends on PLAT_SAMSUNG
-                bool "Use S3C UART 1 for low-level debug"
+        config DEBUG_MSM_UART2
+                bool "Kernel low-level debugging messages via MSM UART2"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to UART 1. The port must have been initialised
-                  by the boot-loader before use.
+                  their output to the second serial port on MSM devices.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_MSM_UART3
+                bool "Kernel low-level debugging messages via MSM UART3"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the third serial port on MSM devices.
 
-        config DEBUG_S3C_UART2
-                depends on PLAT_SAMSUNG
-                bool "Use S3C UART 2 for low-level debug"
+        config DEBUG_MSM8660_UART
+                bool "Kernel low-level debugging messages via MSM 8660 UART"
+                depends on ARCH_MSM8X60
+                select MSM_HAS_DEBUG_UART_HS
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to UART 2. The port must have been initialised
-                  by the boot-loader before use.
+                  their output to the serial port on MSM 8660 devices.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_MSM8960_UART
+                bool "Kernel low-level debugging messages via MSM 8960 UART"
+                depends on ARCH_MSM8960
+                select MSM_HAS_DEBUG_UART_HS
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port on MSM 8960 devices.
 
         config DEBUG_REALVIEW_STD_PORT
                 bool "RealView Default UART"
@@ -255,42 +240,57 @@ choice
                   their output to the standard serial port on the RealView
                   PB1176 platform.
 
-        config DEBUG_MSM_UART1
-                bool "Kernel low-level debugging messages via MSM UART1"
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+        config DEBUG_S3C_UART0
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 0 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the first serial port on MSM devices.
+                  their output to UART 0. The port must have been initialised
+                  by the boot-loader before use.
 
-        config DEBUG_MSM_UART2
-                bool "Kernel low-level debugging messages via MSM UART2"
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+
+        config DEBUG_S3C_UART1
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 1 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the second serial port on MSM devices.
+                  their output to UART 1. The port must have been initialised
+                  by the boot-loader before use.
 
-        config DEBUG_MSM_UART3
-                bool "Kernel low-level debugging messages via MSM UART3"
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+
+        config DEBUG_S3C_UART2
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 2 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the third serial port on MSM devices.
+                  their output to UART 2. The port must have been initialised
+                  by the boot-loader before use.
 
-        config DEBUG_MSM8660_UART
-                bool "Kernel low-level debugging messages via MSM 8660 UART"
-                depends on ARCH_MSM8X60
-                select MSM_HAS_DEBUG_UART_HS
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+
+        config DEBUG_LL_UART_NONE
+                bool "No low-level debugging UART"
                 help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the serial port on MSM 8660 devices.
+                  Say Y here if your platform doesn't provide a UART option
+                  below. This relies on your platform choosing the right UART
+                  definition internally in order for low-level debugging to
+                  work.
 
-        config DEBUG_MSM8960_UART
-                bool "Kernel low-level debugging messages via MSM 8960 UART"
-                depends on ARCH_MSM8960
-                select MSM_HAS_DEBUG_UART_HS
+        config DEBUG_ICEDCC
+                bool "Kernel low-level debugging via EmbeddedICE DCC channel"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the serial port on MSM 8960 devices.
+                  their output to the EmbeddedICE macrocell's DCC channel using
+                  co-processor 14. This is known to work on the ARM9 style ICE
+                  channel and on the XScale with the PEEDI.
+
+                  Note that the system will appear to hang during boot if there
+                  is nothing connected to read from the DCC.
 
 endchoice
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb9166..dcb088e868f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -174,12 +174,13 @@ machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
 machine-$(CONFIG_ARCH_PXA)              := pxa
 machine-$(CONFIG_ARCH_REALVIEW)         := realview
 machine-$(CONFIG_ARCH_RPC)              := rpc
-machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2412 s3c2416 s3c2440 s3c2443
+machine-$(CONFIG_ARCH_S3C24XX)          := s3c24xx s3c2412 s3c2440
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)          := s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
 machine-$(CONFIG_ARCH_EXYNOS4)          := exynos
+machine-$(CONFIG_ARCH_EXYNOS5)          := exynos
 machine-$(CONFIG_ARCH_SA1100)           := sa1100
 machine-$(CONFIG_ARCH_SHARK)            := shark
 machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5d60250d43..5f6045f1766 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -58,7 +58,7 @@
                 add     \rb, \rb, #0x00010000   @ Ser1
 #endif
                 .endm
-#elif defined(CONFIG_ARCH_S3C2410)
+#elif defined(CONFIG_ARCH_S3C24XX)
                 .macro loadsp, rb, tmp
                 mov     \rb, #0x50000000
                 add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
new file mode 100644
index 00000000000..5eb26d7d9b4
--- /dev/null
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        model = "TeeJet Mt.Ventoux";
+        compatible = "teejet,mt_ventoux", "ti,omap3";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+
+        /* AM35xx doesn't have IVA */
+        soc {
+                iva {
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 07603b8c950..92f36627e7f 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -23,6 +23,11 @@
                 serial4 = &usart3;
                 serial5 = &usart4;
                 serial6 = &usart5;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
         };
         cpus {
                 cpu@0 {
@@ -47,24 +52,89 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 interrupt-parent;
                                 reg = <0xfffff000 0x200>;
                         };
 
+                        ramc0: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9260-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9260-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+                        tcb0: timer@fffa0000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa0000 0x100>;
+                                interrupts = <17 4 18 4 19 4>;
+                        };
+
+                        tcb1: timer@fffdc000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffdc000 0x100>;
+                                interrupts = <26 4 27 4 28 4>;
+                        };
+
+                        pioA: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1>;
+                                interrupts = <1 4>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fffb0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb0000 0x200>;
-                                interrupts = <6>;
+                                interrupts = <6 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -73,7 +143,7 @@
                         usart1: serial@fffb4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb4000 0x200>;
-                                interrupts = <7>;
+                                interrupts = <7 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -82,7 +152,7 @@
                         usart2: serial@fffb8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb8000 0x200>;
-                                interrupts = <8>;
+                                interrupts = <8 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -91,7 +161,7 @@
                         usart3: serial@fffd0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd0000 0x200>;
-                                interrupts = <23>;
+                                interrupts = <23 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -100,7 +170,7 @@
                         usart4: serial@fffd4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd4000 0x200>;
-                                interrupts = <24>;
+                                interrupts = <24 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -109,7 +179,7 @@
                         usart5: serial@fffd8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd8000 0x200>;
-                                interrupts = <25>;
+                                interrupts = <25 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -118,9 +188,52 @@
                         macb0: ethernet@fffc4000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffc4000 0x100>;
-                                interrupts = <21>;
+                                interrupts = <21 4>;
+                                status = "disabled";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                compatible = "atmel,at91rm9200-udc";
+                                reg = <0xfffa4000 0x4000>;
+                                interrupts = <10 4>;
                                 status = "disabled";
                         };
                 };
+
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000
+                               0xffffe800 0x200
+                              >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioC 13 0
+                                 &pioC 14 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+
+                usb0: ohci@00500000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00500000 0x100000>;
+                        interrupts = <20 4>;
+                        status = "disabled";
+                };
+        };
+
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 23 0 /* sda */
+                         &pioA 24 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
new file mode 100644
index 00000000000..ac0dc0031dd
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -0,0 +1,49 @@
+/*
+ * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x5.dtsi"
+/include/ "at91sam9x5cm.dtsi"
+
+/ {
+        model = "Atmel AT91SAM9G25-EK";
+        compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@f801c000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00600000 {
+                        status = "okay";
+                        num-ports = <2>;
+                        atmel,vbus-gpio = <&pioD 19 0
+                                           &pioD 20 0
+                                          >;
+                };
+
+                usb1: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index fffa005300a..3d0c32fb218 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -22,6 +22,13 @@
                 serial2 = &usart1;
                 serial3 = &usart2;
                 serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
         };
         cpus {
                 cpu@0 {
@@ -46,30 +53,115 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 interrupt-parent;
                                 reg = <0xfffff000 0x200>;
                         };
 
+                        ramc0: ramc@ffffe400 {
+                                compatible = "atmel,at91sam9g45-ddramc";
+                                reg = <0xffffe400 0x200
+                                       0xffffe600 0x200>;
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9g45-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9rl-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+
+                        tcb0: timer@fff7c000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfff7c000 0x100>;
+                                interrupts = <18 4>;
+                        };
+
+                        tcb1: timer@fffd4000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffd4000 0x100>;
+                                interrupts = <18 4>;
+                        };
+
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <21>;
+                                interrupts = <21 4>;
+                        };
+
+                        pioA: gpio@fffff200 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff200 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioD: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <5 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioE: gpio@fffffa00 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffffa00 0x100>;
+                                interrupts = <5 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
                         };
 
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1>;
+                                interrupts = <1 4>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7>;
+                                interrupts = <7 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -78,7 +170,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8>;
+                                interrupts = <8 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -87,7 +179,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9>;
+                                interrupts = <9 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -96,7 +188,7 @@
                         usart3: serial@fff98000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff98000 0x200>;
-                                interrupts = <10>;
+                                interrupts = <10 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -105,9 +197,52 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <25>;
+                                interrupts = <25 4>;
                                 status = "disabled";
                         };
                 };
+
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000
+                               0xffffe200 0x200
+                              >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioC 8 0
+                                 &pioC 14 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+
+                usb0: ohci@00700000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00700000 0x100000>;
+                        interrupts = <22 4>;
+                        status = "disabled";
+                };
+
+                usb1: ehci@00800000 {
+                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                        reg = <0x00800000 0x100000>;
+                        interrupts = <22 4>;
+                        status = "disabled";
+                };
+        };
+
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 20 0 /* sda */
+                         &pioA 21 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <5>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a387e7704ce..c4c8ae4123d 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -14,13 +14,24 @@
         compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
 
         chosen {
-                bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
         };
 
         memory@70000000 {
                 reg = <0x70000000 0x4000000>;
         };
 
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
         ahb {
                 apb {
                         dbgu: serial@ffffee00 {
@@ -36,5 +47,110 @@
                                 status = "okay";
                         };
                 };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        boot@0 {
+                                label = "bootstrap/uboot/kernel";
+                                reg = <0x0 0x400000>;
+                        };
+
+                        rootfs@400000 {
+                                label = "rootfs";
+                                reg = <0x400000 0x3C00000>;
+                        };
+
+                        data@4000000 {
+                                label = "data";
+                                reg = <0x4000000 0xC000000>;
+                        };
+                };
+
+                usb0: ohci@00700000 {
+                        status = "okay";
+                        num-ports = <2>;
+                        atmel,vbus-gpio = <&pioD 1 0
+                                           &pioD 3 0>;
+                };
+
+                usb1: ehci@00800000 {
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                d8 {
+                        label = "d8";
+                        gpios = <&pioD 30 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                d6 {
+                        label = "d6";
+                        gpios = <&pioD 0 1>;
+                        linux,default-trigger = "nand-disk";
+                };
+
+                d7 {
+                        label = "d7";
+                        gpios = <&pioD 31 1>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                left_click {
+                        label = "left_click";
+                        gpios = <&pioB 6 1>;
+                        linux,code = <272>;
+                        gpio-key,wakeup;
+                };
+
+                right_click {
+                        label = "right_click";
+                        gpios = <&pioB 7 1>;
+                        linux,code = <273>;
+                        gpio-key,wakeup;
+                };
+
+                left {
+                        label = "Joystick Left";
+                        gpios = <&pioB 14 1>;
+                        linux,code = <105>;
+                };
+
+                right {
+                        label = "Joystick Right";
+                        gpios = <&pioB 15 1>;
+                        linux,code = <106>;
+                };
+
+                up {
+                        label = "Joystick Up";
+                        gpios = <&pioB 16 1>;
+                        linux,code = <103>;
+                };
+
+                down {
+                        label = "Joystick Down";
+                        gpios = <&pioB 17 1>;
+                        linux,code = <108>;
+                };
+
+                enter {
+                        label = "Joystick Press";
+                        gpios = <&pioB 18 1>;
+                        linux,code = <28>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
new file mode 100644
index 00000000000..c111001f254
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -0,0 +1,264 @@
+/*
+ * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
+ *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
+ *                   AT91SAM9X25, AT91SAM9X35 SoC
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Atmel AT91SAM9x5 family SoC";
+        compatible = "atmel,at91sam9x5";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory@20000000 {
+                reg = <0x20000000 0x10000000>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <2>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                interrupt-parent;
+                                reg = <0xfffff000 0x200>;
+                        };
+
+                        ramc0: ramc@ffffe800 {
+                                compatible = "atmel,at91sam9g45-ddramc";
+                                reg = <0xffffe800 0x200>;
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+
+                        rstc@fffffe00 {
+                                compatible = "atmel,at91sam9g45-rstc";
+                                reg = <0xfffffe00 0x10>;
+                        };
+
+                        shdwc@fffffe10 {
+                                compatible = "atmel,at91sam9x5-shdwc";
+                                reg = <0xfffffe10 0x10>;
+                        };
+
+                        pit: timer@fffffe30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffe30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+                        tcb0: timer@f8008000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf8008000 0x100>;
+                                interrupts = <17 4>;
+                        };
+
+                        tcb1: timer@f800c000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf800c000 0x100>;
+                                interrupts = <17 4>;
+                        };
+
+                        dma0: dma-controller@ffffec00 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffec00 0x200>;
+                                interrupts = <20 4>;
+                        };
+
+                        dma1: dma-controller@ffffee00 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <21 4>;
+                        };
+
+                        pioA: gpio@fffff400 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff600 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff800 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioD: gpio@fffffa00 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffffa00 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 4>;
+                                status = "disabled";
+                        };
+
+                        usart0: serial@f801c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf801c000 0x200>;
+                                interrupts = <5 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart1: serial@f8020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8020000 0x200>;
+                                interrupts = <6 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart2: serial@f8024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8024000 0x200>;
+                                interrupts = <7 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        macb0: ethernet@f802c000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xf802c000 0x100>;
+                                interrupts = <24 4>;
+                                status = "disabled";
+                        };
+
+                        macb1: ethernet@f8030000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xf8030000 0x100>;
+                                interrupts = <27 4>;
+                                status = "disabled";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000
+                              >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioC 8 0
+                                 &pioC 14 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+
+                usb0: ohci@00600000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00600000 0x100000>;
+                        interrupts = <22 4>;
+                        status = "disabled";
+                };
+
+                usb1: ehci@00700000 {
+                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                        reg = <0x00700000 0x100000>;
+                        interrupts = <22 4>;
+                        status = "disabled";
+                };
+        };
+
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 30 0 /* sda */
+                         &pioA 31 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        i2c@1 {
+                compatible = "i2c-gpio";
+                gpios = <&pioC 0 0 /* sda */
+                         &pioC 1 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        i2c@2 {
+                compatible = "i2c-gpio";
+                gpios = <&pioB 4 0 /* sda */
+                         &pioB 5 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
new file mode 100644
index 00000000000..67936f83c69
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -0,0 +1,74 @@
+/*
+ * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        memory@20000000 {
+                reg = <0x20000000 0x8000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        uboot@40000 {
+                                label = "u-boot";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        ubootenv@c0000 {
+                                label = "U-Boot Env";
+                                reg = <0xc0000 0x140000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x1f800000>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                pb18 {
+                        label = "pb18";
+                        gpios = <&pioB 18 1>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                pd21 {
+                        label = "pd21";
+                        gpios = <&pioD 21 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
new file mode 100644
index 00000000000..d73dce64566
--- /dev/null
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -0,0 +1,275 @@
+/*
+ * Copyright 2012 Linaro Ltd
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        soc-u9500 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "stericsson,db8500";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                intc: interrupt-controller@a0411000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        interrupt-parent;
+                        reg = <0xa0411000 0x1000>,
+                              <0xa0410100 0x100>;
+                };
+
+                L2: l2-cache {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xa0412000 0x1000>;
+                        interrupts = <0 13 4>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 7 0x4>;
+                };
+
+                timer@a0410600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xa0410600 0x20>;
+                        interrupts = <1 13 0x304>;
+                };
+
+                rtc@80154000 {
+                        compatible = "stericsson,db8500-rtc";
+                        reg = <0x80154000 0x1000>;
+                        interrupts = <0 18 0x4>;
+                };
+
+                gpio0: gpio@8012e000 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8012e000 0x80>;
+                        interrupts = <0 119 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio1: gpio@8012e080 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8012e080 0x80>;
+                        interrupts = <0 120 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio2: gpio@8000e000 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8000e000 0x80>;
+                        interrupts = <0 121 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio3: gpio@8000e080 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8000e080 0x80>;
+                        interrupts = <0 122 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio4: gpio@8000e100 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8000e100 0x80>;
+                        interrupts = <0 123 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio5: gpio@8000e180 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8000e180 0x80>;
+                        interrupts = <0 124 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio6: gpio@8011e000 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8011e000 0x80>;
+                        interrupts = <0 125 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio7: gpio@8011e080 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0x8011e080 0x80>;
+                        interrupts = <0 126 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                gpio8: gpio@a03fe000 {
+                        compatible = "stericsson,db8500-gpio",
+                                "stmicroelectronics,nomadik-gpio";
+                        reg =  <0xa03fe000 0x80>;
+                        interrupts = <0 127 0x4>;
+                        supports-sleepmode;
+                        gpio-controller;
+                };
+
+                usb@a03e0000 {
+                        compatible = "stericsson,db8500-musb",
+                                "mentor,musb";
+                        reg = <0xa03e0000 0x10000>;
+                        interrupts = <0 23 0x4>;
+                };
+
+                dma-controller@801C0000 {
+                        compatible = "stericsson,db8500-dma40",
+                                        "stericsson,dma40";
+                        reg = <0x801C0000 0x1000 0x40010000 0x800>;
+                        interrupts = <0 25 0x4>;
+                };
+
+                prcmu@80157000 {
+                        compatible = "stericsson,db8500-prcmu";
+                        reg = <0x80157000 0x1000>;
+                        interrupts = <46 47>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        ab8500@5 {
+                                compatible = "stericsson,ab8500";
+                                reg = <5>; /* mailbox 5 is i2c */
+                                interrupts = <0 40 0x4>;
+                        };
+                };
+
+                i2c@80004000 {
+                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        reg = <0x80004000 0x1000>;
+                        interrupts = <0 21 0x4>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c@80122000 {
+                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        reg = <0x80122000 0x1000>;
+                        interrupts = <0 22 0x4>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c@80128000 {
+                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        reg = <0x80128000 0x1000>;
+                        interrupts = <0 55 0x4>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c@80110000 {
+                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        reg = <0x80110000 0x1000>;
+                        interrupts = <0 12 0x4>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c@8012a000 {
+                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        reg = <0x8012a000 0x1000>;
+                        interrupts = <0 51 0x4>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                ssp@80002000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <80002000 0x1000>;
+                        interrupts = <0 14 0x4>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                        // Add one of these for each child device
+                        cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>;
+
+                };
+
+                uart@80120000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x80120000 0x1000>;
+                        interrupts = <0 11 0x4>;
+                        status = "disabled";
+                };
+                uart@80121000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x80121000 0x1000>;
+                        interrupts = <0 19 0x4>;
+                        status = "disabled";
+                };
+                uart@80007000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x80007000 0x1000>;
+                        interrupts = <0 26 0x4>;
+                        status = "disabled";
+                };
+
+                sdi@80126000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x80126000 0x1000>;
+                        interrupts = <0 60 0x4>;
+                        status = "disabled";
+                };
+                sdi@80118000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x80118000 0x1000>;
+                        interrupts = <0 50 0x4>;
+                        status = "disabled";
+                };
+                sdi@80005000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x80005000 0x1000>;
+                        interrupts = <0 41 0x4>;
+                        status = "disabled";
+                };
+                sdi@80119000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x80119000 0x1000>;
+                        interrupts = <0 59 0x4>;
+                        status = "disabled";
+                };
+                sdi@80114000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x80114000 0x1000>;
+                        interrupts = <0 99 0x4>;
+                        status = "disabled";
+                };
+                sdi@80008000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x80114000 0x1000>;
+                        interrupts = <0 100 0x4>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644
index 00000000000..399d17b231d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,26 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+        model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+        compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644
index 00000000000..dfc43359943
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -0,0 +1,413 @@
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "samsung,exynos5250";
+        interrupt-parent = <&gic>;
+
+        gic:interrupt-controller@10490000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+        };
+
+        watchdog {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x101D0000 0x100>;
+                interrupts = <0 42 0>;
+        };
+
+        rtc {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x101E0000 0x100>;
+                interrupts = <0 43 0>, <0 44 0>;
+        };
+
+        sdhci@12200000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12200000 0x100>;
+                interrupts = <0 75 0>;
+        };
+
+        sdhci@12210000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12210000 0x100>;
+                interrupts = <0 76 0>;
+        };
+
+        sdhci@12220000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12220000 0x100>;
+                interrupts = <0 77 0>;
+        };
+
+        sdhci@12230000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12230000 0x100>;
+                interrupts = <0 78 0>;
+        };
+
+        serial@12C00000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C00000 0x100>;
+                interrupts = <0 51 0>;
+        };
+
+        serial@12C10000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C10000 0x100>;
+                interrupts = <0 52 0>;
+        };
+
+        serial@12C20000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C20000 0x100>;
+                interrupts = <0 53 0>;
+        };
+
+        serial@12C30000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C30000 0x100>;
+                interrupts = <0 54 0>;
+        };
+
+        i2c@12C60000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12C60000 0x100>;
+                interrupts = <0 56 0>;
+        };
+
+        i2c@12C70000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12C70000 0x100>;
+                interrupts = <0 57 0>;
+        };
+
+        i2c@12C80000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12C80000 0x100>;
+                interrupts = <0 58 0>;
+        };
+
+        i2c@12C90000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12C90000 0x100>;
+                interrupts = <0 59 0>;
+        };
+
+        i2c@12CA0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12CA0000 0x100>;
+                interrupts = <0 60 0>;
+        };
+
+        i2c@12CB0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12CB0000 0x100>;
+                interrupts = <0 61 0>;
+        };
+
+        i2c@12CC0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12CC0000 0x100>;
+                interrupts = <0 62 0>;
+        };
+
+        i2c@12CD0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x12CD0000 0x100>;
+                interrupts = <0 63 0>;
+        };
+
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                pdma0: pdma@121A0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121A0000 0x1000>;
+                        interrupts = <0 34 0>;
+                };
+
+                pdma1: pdma@121B0000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x121B0000 0x1000>;
+                        interrupts = <0 35 0>;
+                };
+
+                mdma0: pdma@10800000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x10800000 0x1000>;
+                        interrupts = <0 33 0>;
+                };
+
+                mdma1: pdma@11C10000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x11C10000 0x1000>;
+                        interrupts = <0 124 0>;
+                };
+        };
+
+        gpio-controllers {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                gpio-controller;
+                ranges;
+
+                gpa0: gpio-controller@11400000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400000 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpa1: gpio-controller@11400020 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400020 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpa2: gpio-controller@11400040 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400040 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpb0: gpio-controller@11400060 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400060 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpb1: gpio-controller@11400080 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400080 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpb2: gpio-controller@114000A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpb3: gpio-controller@114000C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpc0: gpio-controller@114000E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpc1: gpio-controller@11400100 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400100 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpc2: gpio-controller@11400120 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400120 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpc3: gpio-controller@11400140 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400140 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpd0: gpio-controller@11400160 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400160 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpd1: gpio-controller@11400180 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400180 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy0: gpio-controller@114001A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy1: gpio-controller@114001C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy2: gpio-controller@114001E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy3: gpio-controller@11400200 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400200 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy4: gpio-controller@11400220 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400220 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy5: gpio-controller@11400240 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400240 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpy6: gpio-controller@11400260 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400260 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx0: gpio-controller@11400C00 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400C00 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx1: gpio-controller@11400C20 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400C20 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx2: gpio-controller@11400C40 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400C40 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpx3: gpio-controller@11400C60 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400C60 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpe0: gpio-controller@13400000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x13400000 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpe1: gpio-controller@13400020 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x13400020 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpf0: gpio-controller@13400040 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x13400040 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpf1: gpio-controller@13400060 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x13400060 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpg0: gpio-controller@13400080 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x13400080 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpg1: gpio-controller@134000A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x134000A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpg2: gpio-controller@134000C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x134000C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gph0: gpio-controller@134000E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x134000E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gph1: gpio-controller@13400100 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x13400100 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpv0: gpio-controller@10D10000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x10D10000 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpv1: gpio-controller@10D10020 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x10D10020 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpv2: gpio-controller@10D10040 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x10D10040 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpv3: gpio-controller@10D10060 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x10D10060 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpv4: gpio-controller@10D10080 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x10D10080 0x20>;
+                        #gpio-cells = <4>;
+                };
+
+                gpz: gpio-controller@03860000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x03860000 0x20>;
+                        #gpio-cells = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 305635bd45c..37c0ff9c8b9 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -72,15 +72,15 @@
                 ranges;
 
                 timer@fff10600 {
-                        compatible = "arm,smp-twd";
+                        compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xfff10600 0x20>;
-                        interrupts = <1 13 0xf04>;
+                        interrupts = <1 13 0xf01>;
                 };
 
                 watchdog@fff10620 {
-                        compatible = "arm,cortex-a9-wdt";
+                        compatible = "arm,cortex-a9-twd-wdt";
                         reg = <0xfff10620 0x20>;
-                        interrupts = <1 14 0xf04>;
+                        interrupts = <1 14 0xf01>;
                 };
 
                 intc: interrupt-controller@fff11000 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
new file mode 100644
index 00000000000..a51a08fc2af
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx27.dtsi"
+
+/ {
+        model = "Phytec pcm038";
+        compatible = "phytec,imx27-pcm038", "fsl,imx27";
+
+        memory {
+                reg = <0x0 0x0>;
+        };
+
+        soc {
+                aipi@10000000 { /* aipi */
+
+                        wdog@10002000 {
+                                status = "okay";
+                        };
+
+                        uart@1000a000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        uart@1000b000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        uart@1000c000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        fec@1002b000 {
+                                status = "okay";
+                        };
+
+                        i2c@1001d000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                at24@4c {
+                                        compatible = "at,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x52>;
+                                };
+                                pcf8563@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+                                lm75@4a {
+                                        compatible = "national,lm75";
+                                        reg = <0x4a>;
+                                };
+                        };
+                };
+        };
+
+        nor_flash@c0000000 {
+                compatible = "cfi-flash";
+                bank-width = <2>;
+                reg = <0xc0000000 0x02000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
new file mode 100644
index 00000000000..bc5e7d5ddd5
--- /dev/null
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+        };
+
+        avic: avic-interrupt-controller@e0000000 {
+                compatible = "fsl,imx27-avic", "fsl,avic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x10040000 0x1000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc26m {
+                        compatible = "fsl,imx-osc26m", "fixed-clock";
+                        clock-frequency = <26000000>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&avic>;
+                ranges;
+
+                aipi@10000000 { /* AIPI1 */
+                        compatible = "fsl,aipi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x10000000 0x10000000>;
+                        ranges;
+
+                        wdog@10002000 {
+                                compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
+                                reg = <0x10002000 0x4000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+
+                        uart1: uart@1000a000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000a000 0x1000>;
+                                interrupts = <20>;
+                                status = "disabled";
+                        };
+
+                        uart2: uart@1000b000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000b000 0x1000>;
+                                interrupts = <19>;
+                                status = "disabled";
+                        };
+
+                        uart3: uart@1000c000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000c000 0x1000>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+
+                        uart4: uart@1000d000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000d000 0x1000>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
+
+                        cspi1: cspi@1000e000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-cspi";
+                                reg = <0x1000e000 0x1000>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+
+                        cspi2: cspi@1000f000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-cspi";
+                                reg = <0x1000f000 0x1000>;
+                                interrupts = <15>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@10012000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                                reg = <0x10012000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+
+                        gpio1: gpio@10015000 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015000 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio2: gpio@10015100 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015100 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio3: gpio@10015200 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015200 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio4: gpio@10015300 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015300 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio5: gpio@10015400 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015400 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio6: gpio@10015500 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015500 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        cspi3: cspi@10017000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-cspi";
+                                reg = <0x10017000 0x1000>;
+                                interrupts = <6>;
+                                status = "disabled";
+                        };
+
+                        uart5: uart@1001b000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1001b000 0x1000>;
+                                interrupts = <49>;
+                                status = "disabled";
+                        };
+
+                        uart6: uart@1001c000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1001c000 0x1000>;
+                                interrupts = <48>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@1001d000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                                reg = <0x1001d000 0x1000>;
+                                interrupts = <1>;
+                                status = "disabled";
+                        };
+
+                        fec: fec@1002b000 {
+                                compatible = "fsl,imx27-fec";
+                                reg = <0x1002b000 0x4000>;
+                                interrupts = <50>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 564cb8c19f1..9949e6060de 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -56,8 +56,95 @@
                                                 compatible = "fsl,mc13892";
                                                 spi-max-frequency = <6000000>;
                                                 reg = <0>;
-                                                mc13xxx-irq-gpios = <&gpio1 8 0>;
-                                                fsl,mc13xxx-uses-regulator;
+                                                interrupt-parent = <&gpio1>;
+                                                interrupts = <8>;
+
+                                                regulators {
+                                                        sw1_reg: sw1 {
+                                                                regulator-min-microvolt = <600000>;
+                                                                regulator-max-microvolt = <1375000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        sw2_reg: sw2 {
+                                                                regulator-min-microvolt = <900000>;
+                                                                regulator-max-microvolt = <1850000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        sw3_reg: sw3 {
+                                                                regulator-min-microvolt = <1100000>;
+                                                                regulator-max-microvolt = <1850000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        sw4_reg: sw4 {
+                                                                regulator-min-microvolt = <1100000>;
+                                                                regulator-max-microvolt = <1850000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vpll_reg: vpll {
+                                                                regulator-min-microvolt = <1050000>;
+                                                                regulator-max-microvolt = <1800000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vdig_reg: vdig {
+                                                                regulator-min-microvolt = <1650000>;
+                                                                regulator-max-microvolt = <1650000>;
+                                                                regulator-boot-on;
+                                                        };
+
+                                                        vsd_reg: vsd {
+                                                                regulator-min-microvolt = <1800000>;
+                                                                regulator-max-microvolt = <3150000>;
+                                                        };
+
+                                                        vusb2_reg: vusb2 {
+                                                                regulator-min-microvolt = <2400000>;
+                                                                regulator-max-microvolt = <2775000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vvideo_reg: vvideo {
+                                                                regulator-min-microvolt = <2775000>;
+                                                                regulator-max-microvolt = <2775000>;
+                                                        };
+
+                                                        vaudio_reg: vaudio {
+                                                                regulator-min-microvolt = <2300000>;
+                                                                regulator-max-microvolt = <3000000>;
+                                                        };
+
+                                                        vcam_reg: vcam {
+                                                                regulator-min-microvolt = <2500000>;
+                                                                regulator-max-microvolt = <3000000>;
+                                                        };
+
+                                                        vgen1_reg: vgen1 {
+                                                                regulator-min-microvolt = <1200000>;
+                                                                regulator-max-microvolt = <1200000>;
+                                                        };
+
+                                                        vgen2_reg: vgen2 {
+                                                                regulator-min-microvolt = <1200000>;
+                                                                regulator-max-microvolt = <3150000>;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vgen3_reg: vgen3 {
+                                                                regulator-min-microvolt = <1800000>;
+                                                                regulator-max-microvolt = <2900000>;
+                                                                regulator-always-on;
+                                                        };
+                                                };
                                         };
 
                                         flash: at45db321d@1 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index c3977e0478b..ce1c8238c89 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -36,11 +36,13 @@
                         usdhc@02198000 { /* uSDHC3 */
                                 cd-gpios = <&gpio6 11 0>;
                                 wp-gpios = <&gpio6 14 0>;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
                         usdhc@0219c000 { /* uSDHC4 */
                                 fsl,card-wired;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
@@ -50,6 +52,18 @@
                 };
         };
 
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
 
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 08d920de728..4663a4e5a28 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -32,18 +32,52 @@
                         usdhc@02198000 { /* uSDHC3 */
                                 cd-gpios = <&gpio7 0 0>;
                                 wp-gpios = <&gpio7 1 0>;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
                         usdhc@0219c000 { /* uSDHC4 */
                                 cd-gpios = <&gpio2 6 0>;
                                 wp-gpios = <&gpio2 7 0>;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
                         uart2: uart@021e8000 {
                                 status = "okay";
                         };
+
+                        i2c@021a0000 { /* I2C1 */
+                                status = "okay";
+                                clock-frequency = <100000>;
+
+                                codec: sgtl5000@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                        VDDA-supply = <&reg_2p5v>;
+                                        VDDIO-supply = <&reg_3p3v>;
+                                };
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_2p5v: 2p5v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                        regulator-always-on;
+                };
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 263e8f3664b..4905f51a106 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -88,9 +88,9 @@
                 ranges;
 
                 timer@00a00600 {
-                        compatible = "arm,smp-twd";
-                        reg = <0x00a00600 0x100>;
-                        interrupts = <1 13 0xf4>;
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x00a00600 0x20>;
+                        interrupts = <1 13 0xf01>;
                 };
 
                 L2: l2-cache@00a02000 {
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
new file mode 100644
index 00000000000..a5376b84227
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Globalscale Technologies Dreamplug";
+        compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
new file mode 100644
index 00000000000..3474ef89094
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -0,0 +1,36 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "mrvl,kirkwood";
+
+        ocp@f1000000 {
+                compatible = "simple-bus";
+                ranges = <0 0xf1000000 0x1000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                serial@12000 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <33>;
+                        /* set clock-frequency in board dts */
+                        status = "disabled";
+                };
+
+                serial@12100 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <34>;
+                        /* set clock-frequency in board dts */
+                        status = "disabled";
+                };
+
+                rtc@10300 {
+                        compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9486be62bcd..9f72cd4cf30 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -13,15 +13,6 @@
         model = "TI OMAP3 BeagleBoard";
         compatible = "ti,omap3-beagle", "ti,omap3";
 
-        /*
-         * Since the initial device tree board file does not create any
-         * devices (MMC, network...), the only way to boot is to provide a
-         * ramdisk.
-         */
-        chosen {
-                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
-        };
-
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x20000000>; /* 512 MB */
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
new file mode 100644
index 00000000000..2eee16ec59b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
+        compatible = "ti,omap3-evm", "ti,omap3";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 216c3317461..c6121357c1e 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,34 +61,57 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
-                intc: interrupt-controller@1 {
-                        compatible = "ti,omap3-intc";
+                intc: interrupt-controller@48200000 {
+                        compatible = "ti,omap2-intc";
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        ti,intc-size = <96>;
+                        reg = <0x48200000 0x1000>;
                 };
 
-                uart1: serial@0x4806a000 {
+                uart1: serial@4806a000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
 
-                uart2: serial@0x4806c000 {
+                uart2: serial@4806c000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
 
-                uart3: serial@0x49020000 {
+                uart3: serial@49020000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
 
-                uart4: serial@0x49042000 {
+                uart4: serial@49042000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
+
+                i2c1: i2c@48070000 {
+                        compatible = "ti,omap3-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@48072000 {
+                        compatible = "ti,omap3-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@48060000 {
+                        compatible = "ti,omap3-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index c7026578ce7..9755ad5917f 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -13,15 +13,6 @@
         model = "TI OMAP4 PandaBoard";
         compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
 
-        /*
-         * Since the initial device tree board file does not create any
-         * devices (MMC, network...), the only way to boot is to provide a
-         * ramdisk.
-         */
-        chosen {
-                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
-        };
-
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 066e28c9032..63c6b2b2bf4 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -13,15 +13,6 @@
         model = "TI OMAP4 SDP board";
         compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
 
-        /*
-         * Since the initial device tree board file does not create any
-         * devices (MMC, network...), the only way to boot is to provide a
-         * ramdisk.
-         */
-        chosen {
-                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
-        };
-
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index e8fe75fac7c..3d35559e77b 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -99,33 +99,61 @@
                 gic: interrupt-controller@48241000 {
                         compatible = "arm,cortex-a9-gic";
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <3>;
                         reg = <0x48241000 0x1000>,
                               <0x48240100 0x0100>;
                 };
 
-                uart1: serial@0x4806a000 {
+                uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
 
-                uart2: serial@0x4806c000 {
+                uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
 
-                uart3: serial@0x48020000 {
+                uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
 
-                uart4: serial@0x4806e000 {
+                uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
+
+                i2c1: i2c@48070000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@48072000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@48060000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
+
+                i2c4: i2c@48350000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c4";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
new file mode 100644
index 00000000000..e762facb3fa
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa168.dtsi"
+
+/ {
+        model = "Marvell PXA168 Aspenite Development Board";
+        compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+        };
+
+        memory {
+                reg = <0x00000000 0x04000000>;
+        };
+
+        soc {
+                apb@d4000000 {
+                        uart1: uart@d4017000 {
+                                status = "okay";
+                        };
+                        twsi1: i2c@d4011000 {
+                                status = "okay";
+                        };
+                        rtc: rtc@d4010000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
new file mode 100644
index 00000000000..d32d5128f22
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -0,0 +1,98 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                i2c0 = &twsi1;
+                i2c1 = &twsi2;
+        };
+
+        intc: intc-interrupt-controller@d4282000 {
+                compatible = "mrvl,mmp-intc", "mrvl,intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xd4282000 0x1000>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                apb@d4000000 {  /* APB */
+                        compatible = "mrvl,apb-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4000000 0x00200000>;
+                        ranges;
+
+                        uart1: uart@d4017000 {
+                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                reg = <0xd4017000 0x1000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+
+                        uart2: uart@d4018000 {
+                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                reg = <0xd4018000 0x1000>;
+                                interrupts = <28>;
+                                status = "disabled";
+                        };
+
+                        uart3: uart@d4026000 {
+                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                reg = <0xd4026000 0x1000>;
+                                interrupts = <29>;
+                                status = "disabled";
+                        };
+
+                        gpio: gpio@d4019000 {
+                                compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+                                reg = <0xd4019000 0x1000>;
+                                interrupts = <49>;
+                                interrupt-names = "gpio_mux";
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        twsi1: i2c@d4011000 {
+                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                reg = <0xd4011000 0x1000>;
+                                interrupts = <7>;
+                                mrvl,i2c-fast-mode;
+                                status = "disabled";
+                        };
+
+                        twsi2: i2c@d4025000 {
+                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                reg = <0xd4025000 0x1000>;
+                                interrupts = <58>;
+                                status = "disabled";
+                        };
+
+                        rtc: rtc@d4010000 {
+                                compatible = "mrvl,mmp-rtc";
+                                reg = <0xd4010000 0x1000>;
+                                interrupts = <5 6>;
+                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
new file mode 100644
index 00000000000..359c6d67915
--- /dev/null
+++ b/arch/arm/boot/dts/snowball.dts
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2011 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "db8500.dtsi"
+
+/ {
+        model = "Calao Systems Snowball platform with device tree";
+        compatible = "calaosystems,snowball-a9500";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        linux,code = <2>;
+                        label = "userpb";
+                        gpios = <&gpio1 0>;
+                };
+                button@2 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        linux,code = <3>;
+                        label = "userpb";
+                        gpios = <&gpio4 23>;
+                };
+                button@3 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        linux,code = <4>;
+                        label = "userpb";
+                        gpios = <&gpio4 23>;
+                };
+                button@4 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        linux,code = <5>;
+                        label = "userpb";
+                        gpios = <&gpio5 1>;
+                };
+                button@5 {
+                        debounce_interval = <50>;
+                        wakeup = <1>;
+                        linux,code = <6>;
+                        label = "userpb";
+                        gpios = <&gpio5 2>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                used-led {
+                        label = "user_led";
+                        gpios = <&gpio4 14>;
+                };
+        };
+
+        soc-u9500 {
+
+                external-bus@50000000 {
+                        compatible = "simple-bus";
+                        reg = <0x50000000 0x10000000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        ethernet@50000000 {
+                                compatible = "smsc,9111";
+                                reg = <0x50000000 0x10000>;
+                                interrupts = <12>;
+                                interrupt-parent = <&gpio4>;
+                        };
+                };
+
+                sdi@80126000 {
+                        status = "enabled";
+                        cd-gpios = <&gpio6 26>;
+                };
+
+                sdi@80114000 {
+                        status = "enabled";
+                };
+
+                uart@80120000 {
+                        status = "okay";
+                };
+
+                uart@80121000 {
+                        status = "okay";
+                };
+
+                uart@80007000 {
+                        status = "okay";
+                };
+
+                i2c@80004000 {
+                        tc3589x@42 {
+                                //compatible = "tc3589x";
+                                reg = <0x42>;
+                                interrupts = <25>;
+                                interrupt-parent = <&gpio6>;
+                        };
+                        tps61052@33 {
+                                //compatible = "tps61052";
+                                reg = <0x33>;
+                        };
+                };
+
+                i2c@80128000 {
+                        lp5521@0x33 {
+                                // compatible = "lp5521";
+                                reg = <0x33>;
+                        };
+                        lp5521@0x34 {
+                                // compatible = "lp5521";
+                                reg = <0x34>;
+                        };
+                        bh1780@0x29 {
+                                // compatible = "rohm,bh1780gli";
+                                reg = <0x33>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 00000000000..636292e18c9
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2012 Stefan Roese <sr@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+        model = "ST SPEAr600 Evaluation Board";
+        compatible = "st,spear600-evb", "st,spear600";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x10000000>;
+        };
+
+        ahb {
+                gmac: ethernet@e0800000 {
+                        phy-mode = "gmii";
+                        status = "okay";
+                };
+
+                apb {
+                        serial@d0000000 {
+                                status = "okay";
+                        };
+
+                        serial@d0080000 {
+                                status = "okay";
+                        };
+
+                        i2c@d0200000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 00000000000..ebe0885a2b9
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012 Stefan Roese <sr@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "st,spear600";
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                vic0: interrupt-controller@f1100000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xf1100000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                vic1: interrupt-controller@f1000000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xf1000000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                gmac: ethernet@e0800000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe0800000 0x8000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <24 23>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+
+                fsmc: flash@d1800000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd1800000 0x1000        /* FSMC Register */
+                               0xd2000000 0x4000>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                smi: flash@fc000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xfc000000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <12>;
+                        status = "disabled";
+                };
+
+                ehci@e1800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe1800000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <27>;
+                        status = "disabled";
+                };
+
+                ehci@e2000000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe2000000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+
+                ohci@e1900000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe1900000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <26>;
+                        status = "disabled";
+                };
+
+                ohci@e2100000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe2100000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <28>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                        serial@d0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xd0000000 0x1000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <24>;
+                                status = "disabled";
+                        };
+
+                        serial@d0080000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xd0080000 0x1000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <25>;
+                                status = "disabled";
+                        };
+
+                        /* local/cpu GPIO */
+                        gpio0: gpio@f0100000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xf0100000 0x1000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <18>;
+                        };
+
+                        /* basic GPIO */
+                        gpio1: gpio@fc980000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xfc980000 0x1000>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <19>;
+                        };
+
+                        /* appl GPIO */
+                        gpio2: gpio@d8100000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xd8100000 0x1000>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <4>;
+                        };
+
+                        i2c@d0200000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xd0200000 0x1000>;
+                                interrupt-parent = <&vic0>;
+                                interrupts = <28>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 70c41fc897d..ac3fb755845 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -14,6 +14,22 @@
                 clock-frequency = < 408000000 >;
         };
 
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
+        serial@70006300 {
+                status = "disable";
+        };
+
+        serial@70006400 {
+                status = "disable";
+        };
+
         i2c@7000c000 {
                 clock-frequency = <100000>;
         };
@@ -33,4 +49,22 @@
         i2c@7000d000 {
                 clock-frequency = <100000>;
         };
+
+        sdhci@78000000 {
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+        };
+
+        sdhci@78000200 {
+                status = "disable";
+        };
+
+        sdhci@78000400 {
+                status = "disable";
+        };
+
+        sdhci@78000400 {
+                support-8bit;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 80afa1b70b8..6e8447dc020 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,19 +10,25 @@
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        pmc@7000f400 {
+                nvidia,invert-interrupt;
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
 
-                codec: wm8903@1a {
+                wm8903: wm8903@1a {
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
-                        interrupts = < 347 >;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
 
                         gpio-controller;
                         #gpio-cells = <2>;
 
-                        /* 0x8000 = Not configured */
-                        gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >;
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
                 };
         };
 
@@ -38,13 +44,32 @@
                 clock-frequency = <400000>;
         };
 
-        sound {
-                compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903";
+        i2s@70002a00 {
+                status = "disable";
+        };
 
-                spkr-en-gpios = <&codec 2 0>;
-                hp-det-gpios = <&gpio 178 0>;
-                int-mic-en-gpios = <&gpio 184 0>;
-                ext-mic-en-gpios = <&gpio 185 0>;
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-harmony",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Harmony";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
         };
 
         serial@70006000 {
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 825d2957da0..6c02abb469d 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -12,6 +12,13 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                alc5632: alc5632@1e {
+                        compatible = "realtek,alc5632";
+                        reg = <0x1e>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
         };
 
         i2c@7000c400 {
@@ -35,6 +42,35 @@
 
         i2c@7000d000 {
                 clock-frequency = <400000>;
+
+                adt7461@4c {
+                        compatible = "adi,adt7461";
+                        reg = <0x4c>;
+                };
+        };
+
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-alc5632-paz00",
+                        "nvidia,tegra-audio-alc5632";
+
+                nvidia,model = "Compal PAZ00";
+
+                nvidia,audio-routing =
+                        "Int Spk", "SPKOUT",
+                        "Int Spk", "SPKOUTN",
+                        "Headset Mic", "MICBIAS1",
+                        "MIC1", "Headset Mic",
+                        "Headset Stereophone", "HPR",
+                        "Headset Stereophone", "HPL",
+                        "DMICDAT", "Digital Mic";
+
+                nvidia,audio-codec = <&alc5632>;
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
         };
 
         serial@70006000 {
@@ -74,4 +110,25 @@
         sdhci@c8000600 {
                 support-8bit;
         };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power {
+                        label = "Power";
+                        gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                wifi {
+                        label = "wifi-led";
+                        gpios = <&gpio 24 0>;
+                        linux,default-trigger = "rfkill0";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index b55a02e34ba..dbf1c5a171c 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -13,6 +13,20 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
+                };
         };
 
         i2c@7000c400 {
@@ -32,6 +46,32 @@
                 };
         };
 
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-seaboard",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Seaboard";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1R", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+        };
+
         serial@70006000 {
                 status = "disable";
         };
@@ -72,6 +112,7 @@
 
         usb@c5000000 {
                 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+                dr_mode = "otg";
         };
 
         gpio-keys {
@@ -93,4 +134,42 @@
                         gpio-key,wakeup;
                 };
         };
+
+        emc@7000f400 {
+                emc-table@190000 {
+                        reg = < 190000 >;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 190000 >;
+                        nvidia,emc-registers = < 0x0000000c 0x00000026
+                                0x00000009 0x00000003 0x00000004 0x00000004
+                                0x00000002 0x0000000c 0x00000003 0x00000003
+                                0x00000002 0x00000001 0x00000004 0x00000005
+                                0x00000004 0x00000009 0x0000000d 0x0000059f
+                                0x00000000 0x00000003 0x00000003 0x00000003
+                                0x00000003 0x00000001 0x0000000b 0x000000c8
+                                0x00000003 0x00000007 0x00000004 0x0000000f
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0xa06204ae
+                                0x007dc010 0x00000000 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000 >;
+                };
+
+                emc-table@380000 {
+                        reg = < 380000 >;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 380000 >;
+                        nvidia,emc-registers = < 0x00000017 0x0000004b
+                                0x00000012 0x00000006 0x00000004 0x00000005
+                                0x00000003 0x0000000c 0x00000006 0x00000006
+                                0x00000003 0x00000001 0x00000004 0x00000005
+                                0x00000004 0x00000009 0x0000000d 0x00000b5f
+                                0x00000000 0x00000003 0x00000003 0x00000006
+                                0x00000006 0x00000001 0x00000011 0x000000c8
+                                0x00000003 0x0000000e 0x00000007 0x0000000f
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0xe044048b
+                                0x007d8010 0x00000000 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000 >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 3b3ee7db99f..252476867b5 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -26,6 +26,18 @@
                 status = "disable";
         };
 
+        i2s@70002800 {
+                status = "disable";
+        };
+
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        das@70000c00 {
+                status = "disable";
+        };
+
         serial@70006000 {
                 clock-frequency = < 216000000 >;
         };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index c7d3b87f29d..2dcff8728e9 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -12,6 +12,20 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
+                };
         };
 
         i2c@7000c400 {
@@ -26,6 +40,34 @@
                 clock-frequency = <400000>;
         };
 
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-ventana",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Ventana";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+        };
+
         serial@70006000 {
                 status = "disable";
         };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3da7afd4532..108e894a892 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,11 @@
         compatible = "nvidia,tegra20";
         interrupt-parent = <&intc>;
 
+        pmc@7000f400 {
+                compatible = "nvidia,tegra20-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+
         intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -12,6 +17,33 @@
                       < 0x50040100 0x0100 >;
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 56 0x04
+                              0 57 0x04>;
+        };
+
+        apbdma: dma@6000a000 {
+                compatible = "nvidia,tegra20-apbdma";
+                reg = <0x6000a000 0x1200>;
+                interrupts = < 0 104 0x04
+                               0 105 0x04
+                               0 106 0x04
+                               0 107 0x04
+                               0 108 0x04
+                               0 109 0x04
+                               0 110 0x04
+                               0 111 0x04
+                               0 112 0x04
+                               0 113 0x04
+                               0 114 0x04
+                               0 115 0x04
+                               0 116 0x04
+                               0 117 0x04
+                               0 118 0x04
+                               0 119 0x04 >;
+        };
+
         i2c@7000c000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -44,18 +76,18 @@
                 interrupts = < 0 53 0x04 >;
         };
 
-        i2s@70002800 {
+        tegra_i2s1: i2s@70002800 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
                 interrupts = < 0 13 0x04 >;
-                dma-channel = < 2 >;
+                nvidia,dma-request-selector = < &apbdma 2 >;
         };
 
-        i2s@70002a00 {
+        tegra_i2s2: i2s@70002a00 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
                 interrupts = < 0 3 0x04 >;
-                dma-channel = < 1 >;
+                nvidia,dma-request-selector = < &apbdma 1 >;
         };
 
         das@70000c00 {
@@ -75,6 +107,8 @@
                                0 89 0x04 >;
                 #gpio-cells = <2>;
                 gpio-controller;
+                #interrupt-cells = <2>;
+                interrupt-controller;
         };
 
         pinmux: pinmux@70000000 {
@@ -120,6 +154,13 @@
                 interrupts = < 0 91 0x04 >;
         };
 
+        emc@7000f400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-emc";
+                reg = <0x7000f400 0x200>;
+        };
+
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
@@ -149,6 +190,7 @@
                 reg = <0xc5000000 0x4000>;
                 interrupts = < 0 20 0x04 >;
                 phy_type = "utmi";
+                nvidia,has-legacy-mode;
         };
 
         usb@c5004000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ee7db9892e0..62a7b39f1c9 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,11 @@
         compatible = "nvidia,tegra30";
         interrupt-parent = <&intc>;
 
+        pmc@7000f400 {
+                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+
         intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -12,6 +17,51 @@
                       < 0x50040100 0x0100 >;
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 144 0x04
+                              0 145 0x04
+                              0 146 0x04
+                              0 147 0x04>;
+        };
+
+        apbdma: dma@6000a000 {
+                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+                reg = <0x6000a000 0x1400>;
+                interrupts = < 0 104 0x04
+                               0 105 0x04
+                               0 106 0x04
+                               0 107 0x04
+                               0 108 0x04
+                               0 109 0x04
+                               0 110 0x04
+                               0 111 0x04
+                               0 112 0x04
+                               0 113 0x04
+                               0 114 0x04
+                               0 115 0x04
+                               0 116 0x04
+                               0 117 0x04
+                               0 118 0x04
+                               0 119 0x04
+                               0 128 0x04
+                               0 129 0x04
+                               0 130 0x04
+                               0 131 0x04
+                               0 132 0x04
+                               0 133 0x04
+                               0 134 0x04
+                               0 135 0x04
+                               0 136 0x04
+                               0 137 0x04
+                               0 138 0x04
+                               0 139 0x04
+                               0 140 0x04
+                               0 141 0x04
+                               0 142 0x04
+                               0 143 0x04 >;
+        };
+
         i2c@7000c000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -55,9 +105,18 @@
         gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
                 reg = < 0x6000d000 0x1000 >;
-                interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
+                interrupts = < 0 32 0x04
+                               0 33 0x04
+                               0 34 0x04
+                               0 35 0x04
+                               0 55 0x04
+                               0 87 0x04
+                               0 89 0x04
+                               0 125 0x04 >;
                 #gpio-cells = <2>;
                 gpio-controller;
+                #interrupt-cells = <2>;
+                interrupt-controller;
         };
 
         serial@70006000 {
diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
new file mode 100644
index 00000000000..ad3eca17c43
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
@@ -0,0 +1,96 @@
+/*
+ * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+        ahb {
+                apb {
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+
+                        usart3: serial@fffd0000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        i2c-gpio@0 {
+                status = "okay";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user_led1 {
+                        label = "user_led1";
+                        gpios = <&pioB 20 1>;
+                };
+
+/*
+* led already used by mother board but active as high
+*               user_led2 {
+*                       label = "user_led2";
+*                       gpios = <&pioB 21 1>;
+*               };
+*/
+                user_led3 {
+                        label = "user_led3";
+                        gpios = <&pioB 22 1>;
+                };
+
+                user_led4 {
+                        label = "user_led4";
+                        gpios = <&pioB 23 1>;
+                };
+
+                red {
+                        label = "red";
+                        gpios = <&pioB 24 1>;
+                };
+
+                orange {
+                        label = "orange";
+                        gpios = <&pioB 30 1>;
+                };
+
+                green {
+                        label = "green";
+                        gpios = <&pioB 31 1>;
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                user_pb1 {
+                        label = "user_pb1";
+                        gpios = <&pioB 25 1>;
+                        linux,code = <0x100>;
+                };
+
+                user_pb2 {
+                        label = "user_pb2";
+                        gpios = <&pioB 13 1>;
+                        linux,code = <0x101>;
+                };
+
+                user_pb3 {
+                        label = "user_pb3";
+                        gpios = <&pioA 26 1>;
+                        linux,code = <0x102>;
+                };
+
+                user_pb4 {
+                        label = "user_pb4";
+                        gpios = <&pioC 9 1>;
+                        linux,code = <0x103>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index f04b535477f..3b3c4e0fa79 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -13,13 +13,24 @@
         compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
 
         chosen {
-                bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data) root=/dev/mtdblock5 rw rootfstype=ubifs";
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
         };
 
         memory@20000000 {
                 reg = <0x20000000 0x4000000>;
         };
 
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
         ahb {
                 apb {
                         dbgu: serial@fffff200 {
@@ -30,6 +41,90 @@
                                 phy-mode = "rmii";
                                 status = "okay";
                         };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xa0000 0x400000>;
+                        };
+
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4a0000 0x7800000>;
+                        };
+
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7ca0000 0x8360000>;
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioB 21 1>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                user_pb {
+                        label = "user_pb";
+                        gpios = <&pioB 10 1>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+
+                rv3029c2@56 {
+                        compatible = "rv3029c2";
+                        reg = <0x56>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 00000000000..16076e2d093
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+        aliases {
+                arm,v2m_timer = &v2m_timer01;
+        };
+
+        motherboard {
+                compatible = "simple-bus";
+                arm,v2m-memory-map = "rs1";
+                #address-cells = <2>; /* SMB chipselect number and offset */
+                #size-cells = <1>;
+                #interrupt-cells = <1>;
+
+                flash@0,00000000 {
+                        compatible = "arm,vexpress-flash", "cfi-flash";
+                        reg = <0 0x00000000 0x04000000>,
+                              <4 0x00000000 0x04000000>;
+                        bank-width = <4>;
+                };
+
+                psram@1,00000000 {
+                        compatible = "arm,vexpress-psram", "mtd-ram";
+                        reg = <1 0x00000000 0x02000000>;
+                        bank-width = <4>;
+                };
+
+                vram@2,00000000 {
+                        compatible = "arm,vexpress-vram";
+                        reg = <2 0x00000000 0x00800000>;
+                };
+
+                ethernet@2,02000000 {
+                        compatible = "smsc,lan9118", "smsc,lan9115";
+                        reg = <2 0x02000000 0x10000>;
+                        interrupts = <15>;
+                        phy-mode = "mii";
+                        reg-io-width = <4>;
+                        smsc,irq-active-high;
+                        smsc,irq-push-pull;
+                };
+
+                usb@2,03000000 {
+                        compatible = "nxp,usb-isp1761";
+                        reg = <2 0x03000000 0x20000>;
+                        interrupts = <16>;
+                        port1-otg;
+                };
+
+                iofpga@3,00000000 {
+                        compatible = "arm,amba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 3 0 0x200000>;
+
+                        sysreg@010000 {
+                                compatible = "arm,vexpress-sysreg";
+                                reg = <0x010000 0x1000>;
+                        };
+
+                        sysctl@020000 {
+                                compatible = "arm,sp810", "arm,primecell";
+                                reg = <0x020000 0x1000>;
+                        };
+
+                        /* PCI-E I2C bus */
+                        v2m_i2c_pcie: i2c@030000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x030000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                pcie-switch@60 {
+                                        compatible = "idt,89hpes32h8";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        aaci@040000 {
+                                compatible = "arm,pl041", "arm,primecell";
+                                reg = <0x040000 0x1000>;
+                                interrupts = <11>;
+                        };
+
+                        mmci@050000 {
+                                compatible = "arm,pl180", "arm,primecell";
+                                reg = <0x050000 0x1000>;
+                                interrupts = <9 10>;
+                        };
+
+                        kmi@060000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x060000 0x1000>;
+                                interrupts = <12>;
+                        };
+
+                        kmi@070000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x070000 0x1000>;
+                                interrupts = <13>;
+                        };
+
+                        v2m_serial0: uart@090000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x090000 0x1000>;
+                                interrupts = <5>;
+                        };
+
+                        v2m_serial1: uart@0a0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0a0000 0x1000>;
+                                interrupts = <6>;
+                        };
+
+                        v2m_serial2: uart@0b0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0b0000 0x1000>;
+                                interrupts = <7>;
+                        };
+
+                        v2m_serial3: uart@0c0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0c0000 0x1000>;
+                                interrupts = <8>;
+                        };
+
+                        wdt@0f0000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0x0f0000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        v2m_timer01: timer@110000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x110000 0x1000>;
+                                interrupts = <2>;
+                        };
+
+                        v2m_timer23: timer@120000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x120000 0x1000>;
+                        };
+
+                        /* DVI I2C bus */
+                        v2m_i2c_dvi: i2c@160000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x160000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                dvi-transmitter@39 {
+                                        compatible = "sil,sii9022-tpi", "sil,sii9022";
+                                        reg = <0x39>;
+                                };
+
+                                dvi-transmitter@60 {
+                                        compatible = "sil,sii9022-cpi", "sil,sii9022";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        rtc@170000 {
+                                compatible = "arm,pl031", "arm,primecell";
+                                reg = <0x170000 0x1000>;
+                                interrupts = <4>;
+                        };
+
+                        compact-flash@1a0000 {
+                                compatible = "arm,vexpress-cf", "ata-generic";
+                                reg = <0x1a0000 0x100
+                                       0x1a0100 0xf00>;
+                                reg-shift = <2>;
+                        };
+
+                        clcd@1f0000 {
+                                compatible = "arm,pl111", "arm,primecell";
+                                reg = <0x1f0000 0x1000>;
+                                interrupts = <14>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644
index 00000000000..a6c9c7c82d5
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -0,0 +1,200 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+        aliases {
+                arm,v2m_timer = &v2m_timer01;
+        };
+
+        motherboard {
+                compatible = "simple-bus";
+                #address-cells = <2>; /* SMB chipselect number and offset */
+                #size-cells = <1>;
+                #interrupt-cells = <1>;
+
+                flash@0,00000000 {
+                        compatible = "arm,vexpress-flash", "cfi-flash";
+                        reg = <0 0x00000000 0x04000000>,
+                              <1 0x00000000 0x04000000>;
+                        bank-width = <4>;
+                };
+
+                psram@2,00000000 {
+                        compatible = "arm,vexpress-psram", "mtd-ram";
+                        reg = <2 0x00000000 0x02000000>;
+                        bank-width = <4>;
+                };
+
+                vram@3,00000000 {
+                        compatible = "arm,vexpress-vram";
+                        reg = <3 0x00000000 0x00800000>;
+                };
+
+                ethernet@3,02000000 {
+                        compatible = "smsc,lan9118", "smsc,lan9115";
+                        reg = <3 0x02000000 0x10000>;
+                        interrupts = <15>;
+                        phy-mode = "mii";
+                        reg-io-width = <4>;
+                        smsc,irq-active-high;
+                        smsc,irq-push-pull;
+                };
+
+                usb@3,03000000 {
+                        compatible = "nxp,usb-isp1761";
+                        reg = <3 0x03000000 0x20000>;
+                        interrupts = <16>;
+                        port1-otg;
+                };
+
+                iofpga@7,00000000 {
+                        compatible = "arm,amba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 7 0 0x20000>;
+
+                        sysreg@00000 {
+                                compatible = "arm,vexpress-sysreg";
+                                reg = <0x00000 0x1000>;
+                        };
+
+                        sysctl@01000 {
+                                compatible = "arm,sp810", "arm,primecell";
+                                reg = <0x01000 0x1000>;
+                        };
+
+                        /* PCI-E I2C bus */
+                        v2m_i2c_pcie: i2c@02000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x02000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                pcie-switch@60 {
+                                        compatible = "idt,89hpes32h8";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        aaci@04000 {
+                                compatible = "arm,pl041", "arm,primecell";
+                                reg = <0x04000 0x1000>;
+                                interrupts = <11>;
+                        };
+
+                        mmci@05000 {
+                                compatible = "arm,pl180", "arm,primecell";
+                                reg = <0x05000 0x1000>;
+                                interrupts = <9 10>;
+                        };
+
+                        kmi@06000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x06000 0x1000>;
+                                interrupts = <12>;
+                        };
+
+                        kmi@07000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x07000 0x1000>;
+                                interrupts = <13>;
+                        };
+
+                        v2m_serial0: uart@09000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x09000 0x1000>;
+                                interrupts = <5>;
+                        };
+
+                        v2m_serial1: uart@0a000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0a000 0x1000>;
+                                interrupts = <6>;
+                        };
+
+                        v2m_serial2: uart@0b000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0b000 0x1000>;
+                                interrupts = <7>;
+                        };
+
+                        v2m_serial3: uart@0c000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0c000 0x1000>;
+                                interrupts = <8>;
+                        };
+
+                        wdt@0f000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0x0f000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        v2m_timer01: timer@11000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x11000 0x1000>;
+                                interrupts = <2>;
+                        };
+
+                        v2m_timer23: timer@12000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x12000 0x1000>;
+                        };
+
+                        /* DVI I2C bus */
+                        v2m_i2c_dvi: i2c@16000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x16000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                dvi-transmitter@39 {
+                                        compatible = "sil,sii9022-tpi", "sil,sii9022";
+                                        reg = <0x39>;
+                                };
+
+                                dvi-transmitter@60 {
+                                        compatible = "sil,sii9022-cpi", "sil,sii9022";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        rtc@17000 {
+                                compatible = "arm,pl031", "arm,primecell";
+                                reg = <0x17000 0x1000>;
+                                interrupts = <4>;
+                        };
+
+                        compact-flash@1a000 {
+                                compatible = "arm,vexpress-cf", "ata-generic";
+                                reg = <0x1a000 0x100
+                                       0x1a100 0xf00>;
+                                reg-shift = <2>;
+                        };
+
+                        clcd@1f000 {
+                                compatible = "arm,pl111", "arm,primecell";
+                                reg = <0x1f000 0x1000>;
+                                interrupts = <14>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 00000000000..941b161ab78
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,157 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 (version with Test Chip 1)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ * HBI-0237A
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA15";
+        arm,hbi = <0x237>;
+        compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
+
+        hdlcd@2b000000 {
+                compatible = "arm,hdlcd";
+                reg = <0x2b000000 0x1000>;
+                interrupts = <0 85 4>;
+        };
+
+        memory-controller@2b0a0000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0x2b0a0000 0x1000>;
+        };
+
+        wdt@2b060000 {
+                compatible = "arm,sp805", "arm,primecell";
+                reg = <0x2b060000 0x1000>;
+                interrupts = <98>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x2c001000 0x1000>,
+                      <0x2c002000 0x100>;
+        };
+
+        memory-controller@7ffd0000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0x7ffd0000 0x1000>;
+                interrupts = <0 86 4>,
+                             <0 87 4>;
+        };
+
+        dma@7ffb0000 {
+                compatible = "arm,pl330", "arm,primecell";
+                reg = <0x7ffb0000 0x1000>;
+                interrupts = <0 92 4>,
+                             <0 88 4>,
+                             <0 89 4>,
+                             <0 90 4>,
+                             <0 91 4>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 68 4>,
+                             <0 69 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0x08000000 0x04000000>,
+                         <1 0 0x14000000 0x04000000>,
+                         <2 0 0x18000000 0x04000000>,
+                         <3 0 0x1c000000 0x04000000>,
+                         <4 0 0x0c000000 0x04000000>,
+                         <5 0 0x10000000 0x04000000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 00000000000..6905e66d474
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,162 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA5s";
+        arm,hbi = <0x225>;
+        compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a5";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a5";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
+
+        hdlcd@2a110000 {
+                compatible = "arm,hdlcd";
+                reg = <0x2a110000 0x1000>;
+                interrupts = <0 85 4>;
+        };
+
+        memory-controller@2a150000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0x2a150000 0x1000>;
+        };
+
+        memory-controller@2a190000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0x2a190000 0x1000>;
+                interrupts = <0 86 4>,
+                             <0 87 4>;
+        };
+
+        scu@2c000000 {
+                compatible = "arm,cortex-a5-scu";
+                reg = <0x2c000000 0x58>;
+        };
+
+        timer@2c000600 {
+                compatible = "arm,cortex-a5-twd-timer";
+                reg = <0x2c000600 0x38>;
+                interrupts = <1 2 0x304>,
+                             <1 3 0x304>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x2c001000 0x1000>,
+                      <0x2c000100 0x100>;
+        };
+
+        L2: cache-controller@2c0f0000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x2c0f0000 0x1000>;
+                interrupts = <0 84 4>;
+                cache-level = <2>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 68 4>,
+                             <0 69 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0x08000000 0x04000000>,
+                         <1 0 0x14000000 0x04000000>,
+                         <2 0 0x18000000 0x04000000>,
+                         <3 0 0x1c000000 0x04000000>,
+                         <4 0 0x0c000000 0x04000000>,
+                         <5 0 0x10000000 0x04000000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 00000000000..da778693be5
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,192 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA9";
+        arm,hbi = <0x191>;
+        compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory@60000000 {
+                device_type = "memory";
+                reg = <0x60000000 0x40000000>;
+        };
+
+        clcd@10020000 {
+                compatible = "arm,pl111", "arm,primecell";
+                reg = <0x10020000 0x1000>;
+                interrupts = <0 44 4>;
+        };
+
+        memory-controller@100e0000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0x100e0000 0x1000>;
+        };
+
+        memory-controller@100e1000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0x100e1000 0x1000>;
+                interrupts = <0 45 4>,
+                             <0 46 4>;
+        };
+
+        timer@100e4000 {
+                compatible = "arm,sp804", "arm,primecell";
+                reg = <0x100e4000 0x1000>;
+                interrupts = <0 48 4>,
+                             <0 49 4>;
+        };
+
+        watchdog@100e5000 {
+                compatible = "arm,sp805", "arm,primecell";
+                reg = <0x100e5000 0x1000>;
+                interrupts = <0 51 4>;
+        };
+
+        scu@1e000000 {
+                compatible = "arm,cortex-a9-scu";
+                reg = <0x1e000000 0x58>;
+        };
+
+        timer@1e000600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0x1e000600 0x20>;
+                interrupts = <1 2 0xf04>,
+                             <1 3 0xf04>;
+        };
+
+        gic: interrupt-controller@1e001000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x1e001000 0x1000>,
+                      <0x1e000100 0x100>;
+        };
+
+        L2: cache-controller@1e00a000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x1e00a000 0x1000>;
+                interrupts = <0 43 4>;
+                cache-level = <2>;
+                arm,data-latency = <1 1 1>;
+                arm,tag-latency = <1 1 1>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 60 4>,
+                             <0 61 4>,
+                             <0 62 4>,
+                             <0 63 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0x40000000 0x04000000>,
+                         <1 0 0x44000000 0x04000000>,
+                         <2 0 0x48000000 0x04000000>,
+                         <3 0 0x4c000000 0x04000000>,
+                         <7 0 0x10000000 0x00020000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 81a933eb090..3bb1d7589bd 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -35,9 +35,6 @@ config DMABOUNCE
         bool
         select ZONE_DMA
 
-config TIMER_ACORN
-        bool
-
 config SHARP_LOCOMO
         bool
 
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 6ea9b6f3607..69feafe7286 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_PL330)		+= pl330.o
 obj-$(CONFIG_SA1111)            += sa1111.o
 obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
 obj-$(CONFIG_DMABOUNCE)         += dmabounce.o
-obj-$(CONFIG_TIMER_ACORN)       += time-acorn.o
 obj-$(CONFIG_SHARP_LOCOMO)      += locomo.o
 obj-$(CONFIG_SHARP_PARAM)       += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)       += scoop.o
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index fb1f1cfce60..dcb13494ca0 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -299,8 +299,8 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
                 goto err1;
         }
 
-        pci_add_resource(&sys->resources, &it8152_io);
-        pci_add_resource(&sys->resources, &it8152_mem);
+        pci_add_resource_offset(&sys->resources, &it8152_io, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &it8152_mem, sys->mem_offset);
 
         if (platform_notify || platform_notify_remove) {
                 printk(KERN_ERR "PCI: Can't use platform_notify\n");
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 61691cdbdcf..9173d112ea0 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -16,6 +16,7 @@
  */
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
@@ -28,9 +29,8 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
 #include <asm/mach/irq.h>
+#include <asm/mach-types.h>
 #include <asm/sizes.h>
 
 #include <asm/hardware/sa1111.h>
@@ -86,8 +86,10 @@
 #define IRQ_S1_CD_VALID         (52)
 #define IRQ_S0_BVD1_STSCHG      (53)
 #define IRQ_S1_BVD1_STSCHG      (54)
+#define SA1111_IRQ_NR           (55)
 
-extern void __init sa1110_mb_enable(void);
+extern void sa1110_mb_enable(void);
+extern void sa1110_mb_disable(void);
 
 /*
  * We keep the following data for the overall SA1111.  Note that the
@@ -104,6 +106,7 @@ struct sa1111 {
         int             irq_base;       /* base for cascaded on-chip IRQs */
         spinlock_t      lock;
         void __iomem    *base;
+        struct sa1111_platform_data *pdata;
 #ifdef CONFIG_PM
         void            *saved_state;
 #endif
@@ -118,6 +121,7 @@ static struct sa1111 *g_sa1111;
 struct sa1111_dev_info {
         unsigned long   offset;
         unsigned long   skpcr_mask;
+        bool            dma;
         unsigned int    devid;
         unsigned int    irq[6];
 };
@@ -126,6 +130,7 @@ static struct sa1111_dev_info sa1111_devices[] = {
         {
                 .offset         = SA1111_USB,
                 .skpcr_mask     = SKPCR_UCLKEN,
+                .dma            = true,
                 .devid          = SA1111_DEVID_USB,
                 .irq = {
                         IRQ_USBPWR,
@@ -139,6 +144,7 @@ static struct sa1111_dev_info sa1111_devices[] = {
         {
                 .offset         = 0x0600,
                 .skpcr_mask     = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
+                .dma            = true,
                 .devid          = SA1111_DEVID_SAC,
                 .irq = {
                         AUDXMTDMADONEA,
@@ -155,7 +161,7 @@ static struct sa1111_dev_info sa1111_devices[] = {
         {
                 .offset         = SA1111_KBD,
                 .skpcr_mask     = SKPCR_PTCLKEN,
-                .devid          = SA1111_DEVID_PS2,
+                .devid          = SA1111_DEVID_PS2_KBD,
                 .irq = {
                         IRQ_TPRXINT,
                         IRQ_TPTXINT
@@ -164,7 +170,7 @@ static struct sa1111_dev_info sa1111_devices[] = {
         {
                 .offset         = SA1111_MSE,
                 .skpcr_mask     = SKPCR_PMCLKEN,
-                .devid          = SA1111_DEVID_PS2,
+                .devid          = SA1111_DEVID_PS2_MSE,
                 .irq = {
                         IRQ_MSRXINT,
                         IRQ_MSTXINT
@@ -434,16 +440,28 @@ static struct irq_chip sa1111_high_chip = {
         .irq_set_wake   = sa1111_wake_highirq,
 };
 
-static void sa1111_setup_irq(struct sa1111 *sachip)
+static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
 {
         void __iomem *irqbase = sachip->base + SA1111_INTC;
-        unsigned int irq;
+        unsigned i, irq;
+        int ret;
 
         /*
          * We're guaranteed that this region hasn't been taken.
          */
         request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
 
+        ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
+        if (ret <= 0) {
+                dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
+                        SA1111_IRQ_NR, ret);
+                if (ret == 0)
+                        ret = -EINVAL;
+                return ret;
+        }
+
+        sachip->irq_base = ret;
+
         /* disable all IRQs */
         sa1111_writel(0, irqbase + SA1111_INTEN0);
         sa1111_writel(0, irqbase + SA1111_INTEN1);
@@ -463,14 +481,16 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
         sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0);
         sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
 
-        for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
+        for (i = IRQ_GPAIN0; i <= SSPROR; i++) {
+                irq = sachip->irq_base + i;
                 irq_set_chip_and_handler(irq, &sa1111_low_chip,
                                          handle_edge_irq);
                 irq_set_chip_data(irq, sachip);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
+        for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) {
+                irq = sachip->irq_base + i;
                 irq_set_chip_and_handler(irq, &sa1111_high_chip,
                                          handle_edge_irq);
                 irq_set_chip_data(irq, sachip);
@@ -483,6 +503,11 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
         irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
         irq_set_handler_data(sachip->irq, sachip);
         irq_set_chained_handler(sachip->irq, sa1111_irq_handler);
+
+        dev_info(sachip->dev, "Providing IRQ%u-%u\n",
+                sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
+
+        return 0;
 }
 
 /*
@@ -581,41 +606,10 @@ sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
 }
 #endif
 
-#ifdef CONFIG_DMABOUNCE
-/*
- * According to the "Intel StrongARM SA-1111 Microprocessor Companion
- * Chip Specification Update" (June 2000), erratum #7, there is a
- * significant bug in the SA1111 SDRAM shared memory controller.  If
- * an access to a region of memory above 1MB relative to the bank base,
- * it is important that address bit 10 _NOT_ be asserted. Depending
- * on the configuration of the RAM, bit 10 may correspond to one
- * of several different (processor-relative) address bits.
- *
- * This routine only identifies whether or not a given DMA address
- * is susceptible to the bug.
- *
- * This should only get called for sa1111_device types due to the
- * way we configure our device dma_masks.
- */
-static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
-{
-        /*
-         * Section 4.6 of the "Intel StrongARM SA-1111 Development Module
-         * User's Guide" mentions that jumpers R51 and R52 control the
-         * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
-         * SDRAM bank 1 on Neponset). The default configuration selects
-         * Assabet, so any address in bank 1 is necessarily invalid.
-         */
-        return (machine_is_assabet() || machine_is_pfs168()) &&
-                (addr >= 0xc8000000 || (addr + size) >= 0xc8000000);
-}
-#endif
-
 static void sa1111_dev_release(struct device *_dev)
 {
         struct sa1111_dev *dev = SA1111_DEV(_dev);
 
-        release_resource(&dev->res);
         kfree(dev);
 }
 
@@ -624,67 +618,58 @@ sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
                       struct sa1111_dev_info *info)
 {
         struct sa1111_dev *dev;
+        unsigned i;
         int ret;
 
         dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
         if (!dev) {
                 ret = -ENOMEM;
-                goto out;
+                goto err_alloc;
         }
 
+        device_initialize(&dev->dev);
         dev_set_name(&dev->dev, "%4.4lx", info->offset);
         dev->devid       = info->devid;
         dev->dev.parent  = sachip->dev;
         dev->dev.bus     = &sa1111_bus_type;
         dev->dev.release = sa1111_dev_release;
-        dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
         dev->res.start   = sachip->phys + info->offset;
         dev->res.end     = dev->res.start + 511;
         dev->res.name    = dev_name(&dev->dev);
         dev->res.flags   = IORESOURCE_MEM;
         dev->mapbase     = sachip->base + info->offset;
         dev->skpcr_mask  = info->skpcr_mask;
-        memmove(dev->irq, info->irq, sizeof(dev->irq));
-
-        ret = request_resource(parent, &dev->res);
-        if (ret) {
-                printk("SA1111: failed to allocate resource for %s\n",
-                        dev->res.name);
-                dev_set_name(&dev->dev, NULL);
-                kfree(dev);
-                goto out;
-        }
-
 
-        ret = device_register(&dev->dev);
-        if (ret) {
-                release_resource(&dev->res);
-                kfree(dev);
-                goto out;
-        }
+        for (i = 0; i < ARRAY_SIZE(info->irq); i++)
+                dev->irq[i] = sachip->irq_base + info->irq[i];
 
-#ifdef CONFIG_DMABOUNCE
         /*
-         * If the parent device has a DMA mask associated with it,
-         * propagate it down to the children.
+         * If the parent device has a DMA mask associated with it, and
+         * this child supports DMA, propagate it down to the children.
          */
-        if (sachip->dev->dma_mask) {
+        if (info->dma && sachip->dev->dma_mask) {
                 dev->dma_mask = *sachip->dev->dma_mask;
                 dev->dev.dma_mask = &dev->dma_mask;
+                dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
+        }
 
-                if (dev->dma_mask != 0xffffffffUL) {
-                        ret = dmabounce_register_dev(&dev->dev, 1024, 4096,
-                                        sa1111_needs_bounce);
-                        if (ret) {
-                                dev_err(&dev->dev, "SA1111: Failed to register"
-                                        " with dmabounce\n");
-                                device_unregister(&dev->dev);
-                        }
-                }
+        ret = request_resource(parent, &dev->res);
+        if (ret) {
+                dev_err(sachip->dev, "failed to allocate resource for %s\n",
+                        dev->res.name);
+                goto err_resource;
         }
-#endif
 
-out:
+        ret = device_add(&dev->dev);
+        if (ret)
+                goto err_add;
+        return 0;
+
+ err_add:
+        release_resource(&dev->res);
+ err_resource:
+        put_device(&dev->dev);
+ err_alloc:
         return ret;
 }
 
@@ -698,16 +683,21 @@ out:
  *      Returns:
  *      %-ENODEV        device not found.
  *      %-EBUSY         physical address already marked in-use.
+ *      %-EINVAL        no platform data passed
  *      %0              successful.
  */
 static int __devinit
 __sa1111_probe(struct device *me, struct resource *mem, int irq)
 {
+        struct sa1111_platform_data *pd = me->platform_data;
         struct sa1111 *sachip;
         unsigned long id;
         unsigned int has_devs;
         int i, ret = -ENODEV;
 
+        if (!pd)
+                return -EINVAL;
+
         sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL);
         if (!sachip)
                 return -ENOMEM;
@@ -727,6 +717,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
         sachip->dev = me;
         dev_set_drvdata(sachip->dev, sachip);
 
+        sachip->pdata = pd;
         sachip->phys = mem->start;
         sachip->irq = irq;
 
@@ -759,6 +750,16 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
          */
         sa1111_wake(sachip);
 
+        /*
+         * The interrupt controller must be initialised before any
+         * other device to ensure that the interrupts are available.
+         */
+        if (sachip->irq != NO_IRQ) {
+                ret = sa1111_setup_irq(sachip, pd->irq_base);
+                if (ret)
+                        goto err_unmap;
+        }
+
 #ifdef CONFIG_ARCH_SA1100
         {
         unsigned int val;
@@ -789,24 +790,14 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
         }
 #endif
 
-        /*
-         * The interrupt controller must be initialised before any
-         * other device to ensure that the interrupts are available.
-         */
-        if (sachip->irq != NO_IRQ)
-                sa1111_setup_irq(sachip);
-
         g_sa1111 = sachip;
 
         has_devs = ~0;
-        if (machine_is_assabet() || machine_is_jornada720() ||
-            machine_is_badge4())
-                has_devs &= ~(1 << 4);
-        else
-                has_devs &= ~(1 << 1);
+        if (pd)
+                has_devs &= ~pd->disable_devs;
 
         for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
-                if (has_devs & (1 << i))
+                if (sa1111_devices[i].devid & has_devs)
                         sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
 
         return 0;
@@ -824,7 +815,10 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
 
 static int sa1111_remove_one(struct device *dev, void *data)
 {
-        device_unregister(dev);
+        struct sa1111_dev *sadev = SA1111_DEV(dev);
+        device_del(&sadev->dev);
+        release_resource(&sadev->res);
+        put_device(&sadev->dev);
         return 0;
 }
 
@@ -846,6 +840,7 @@ static void __sa1111_remove(struct sa1111 *sachip)
         if (sachip->irq != NO_IRQ) {
                 irq_set_chained_handler(sachip->irq, NULL);
                 irq_set_handler_data(sachip->irq, NULL);
+                irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
 
                 release_mem_region(sachip->phys + SA1111_INTC, 512);
         }
@@ -904,6 +899,9 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state)
         save->skpwm0   = sa1111_readl(base + SA1111_SKPWM0);
         save->skpwm1   = sa1111_readl(base + SA1111_SKPWM1);
 
+        sa1111_writel(0, sachip->base + SA1111_SKPWM0);
+        sa1111_writel(0, sachip->base + SA1111_SKPWM1);
+
         base = sachip->base + SA1111_INTC;
         save->intpol0  = sa1111_readl(base + SA1111_INTPOL0);
         save->intpol1  = sa1111_readl(base + SA1111_INTPOL1);
@@ -919,13 +917,15 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state)
          */
         val = sa1111_readl(sachip->base + SA1111_SKCR);
         sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
-        sa1111_writel(0, sachip->base + SA1111_SKPWM0);
-        sa1111_writel(0, sachip->base + SA1111_SKPWM1);
 
         clk_disable(sachip->clk);
 
         spin_unlock_irqrestore(&sachip->lock, flags);
 
+#ifdef CONFIG_ARCH_SA1100
+        sa1110_mb_disable();
+#endif
+
         return 0;
 }
 
@@ -966,6 +966,11 @@ static int sa1111_resume(struct platform_device *dev)
          */
         sa1111_wake(sachip);
 
+#ifdef CONFIG_ARCH_SA1100
+        /* Enable the memory bus request/grant signals */
+        sa1110_mb_enable();
+#endif
+
         /*
          * Only lock for write ops. Also, sa1111_wake must be called with
          * released spinlock!
@@ -1053,6 +1058,7 @@ static struct platform_driver sa1111_device_driver = {
         .resume         = sa1111_resume,
         .driver         = {
                 .name   = "sa1111",
+                .owner  = THIS_MODULE,
         },
 };
 
@@ -1238,16 +1244,23 @@ EXPORT_SYMBOL(sa1111_set_sleep_io);
  *      sa1111_enable_device - enable an on-chip SA1111 function block
  *      @sadev: SA1111 function block device to enable
  */
-void sa1111_enable_device(struct sa1111_dev *sadev)
+int sa1111_enable_device(struct sa1111_dev *sadev)
 {
         struct sa1111 *sachip = sa1111_chip_driver(sadev);
         unsigned long flags;
         unsigned int val;
+        int ret = 0;
 
-        spin_lock_irqsave(&sachip->lock, flags);
-        val = sa1111_readl(sachip->base + SA1111_SKPCR);
-        sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
-        spin_unlock_irqrestore(&sachip->lock, flags);
+        if (sachip->pdata && sachip->pdata->enable)
+                ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
+
+        if (ret == 0) {
+                spin_lock_irqsave(&sachip->lock, flags);
+                val = sa1111_readl(sachip->base + SA1111_SKPCR);
+                sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
+                spin_unlock_irqrestore(&sachip->lock, flags);
+        }
+        return ret;
 }
 EXPORT_SYMBOL(sa1111_enable_device);
 
@@ -1265,6 +1278,9 @@ void sa1111_disable_device(struct sa1111_dev *sadev)
         val = sa1111_readl(sachip->base + SA1111_SKPCR);
         sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
         spin_unlock_irqrestore(&sachip->lock, flags);
+
+        if (sachip->pdata && sachip->pdata->disable)
+                sachip->pdata->disable(sachip->pdata->data, sadev->devid);
 }
 EXPORT_SYMBOL(sa1111_disable_device);
 
@@ -1279,7 +1295,7 @@ static int sa1111_match(struct device *_dev, struct device_driver *_drv)
         struct sa1111_dev *dev = SA1111_DEV(_dev);
         struct sa1111_driver *drv = SA1111_DRV(_drv);
 
-        return dev->devid == drv->devid;
+        return dev->devid & drv->devid;
 }
 
 static int sa1111_bus_suspend(struct device *dev, pm_message_t state)
@@ -1304,6 +1320,14 @@ static int sa1111_bus_resume(struct device *dev)
         return ret;
 }
 
+static void sa1111_bus_shutdown(struct device *dev)
+{
+        struct sa1111_driver *drv = SA1111_DRV(dev->driver);
+
+        if (drv && drv->shutdown)
+                drv->shutdown(SA1111_DEV(dev));
+}
+
 static int sa1111_bus_probe(struct device *dev)
 {
         struct sa1111_dev *sadev = SA1111_DEV(dev);
@@ -1333,6 +1357,7 @@ struct bus_type sa1111_bus_type = {
         .remove         = sa1111_bus_remove,
         .suspend        = sa1111_bus_suspend,
         .resume         = sa1111_bus_resume,
+        .shutdown       = sa1111_bus_shutdown,
 };
 EXPORT_SYMBOL(sa1111_bus_type);
 
@@ -1349,9 +1374,70 @@ void sa1111_driver_unregister(struct sa1111_driver *driver)
 }
 EXPORT_SYMBOL(sa1111_driver_unregister);
 
+#ifdef CONFIG_DMABOUNCE
+/*
+ * According to the "Intel StrongARM SA-1111 Microprocessor Companion
+ * Chip Specification Update" (June 2000), erratum #7, there is a
+ * significant bug in the SA1111 SDRAM shared memory controller.  If
+ * an access to a region of memory above 1MB relative to the bank base,
+ * it is important that address bit 10 _NOT_ be asserted. Depending
+ * on the configuration of the RAM, bit 10 may correspond to one
+ * of several different (processor-relative) address bits.
+ *
+ * This routine only identifies whether or not a given DMA address
+ * is susceptible to the bug.
+ *
+ * This should only get called for sa1111_device types due to the
+ * way we configure our device dma_masks.
+ */
+static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
+{
+        /*
+         * Section 4.6 of the "Intel StrongARM SA-1111 Development Module
+         * User's Guide" mentions that jumpers R51 and R52 control the
+         * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
+         * SDRAM bank 1 on Neponset). The default configuration selects
+         * Assabet, so any address in bank 1 is necessarily invalid.
+         */
+        return (machine_is_assabet() || machine_is_pfs168()) &&
+                (addr >= 0xc8000000 || (addr + size) >= 0xc8000000);
+}
+
+static int sa1111_notifier_call(struct notifier_block *n, unsigned long action,
+        void *data)
+{
+        struct sa1111_dev *dev = SA1111_DEV(data);
+
+        switch (action) {
+        case BUS_NOTIFY_ADD_DEVICE:
+                if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) {
+                        int ret = dmabounce_register_dev(&dev->dev, 1024, 4096,
+                                        sa1111_needs_bounce);
+                        if (ret)
+                                dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret);
+                }
+                break;
+
+        case BUS_NOTIFY_DEL_DEVICE:
+                if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL)
+                        dmabounce_unregister_dev(&dev->dev);
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block sa1111_bus_notifier = {
+        .notifier_call = sa1111_notifier_call,
+};
+#endif
+
 static int __init sa1111_init(void)
 {
         int ret = bus_register(&sa1111_bus_type);
+#ifdef CONFIG_DMABOUNCE
+        if (ret == 0)
+                bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
+#endif
         if (ret == 0)
                 platform_driver_register(&sa1111_device_driver);
         return ret;
@@ -1360,6 +1446,9 @@ static int __init sa1111_init(void)
 static void __exit sa1111_exit(void)
 {
         platform_driver_unregister(&sa1111_device_driver);
+#ifdef CONFIG_DMABOUNCE
+        bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
+#endif
         bus_unregister(&sa1111_bus_type);
 }
 
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 8794a34eae6..df13a3ffff3 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
+#include <asm/sched_clock.h>
 #include <asm/hardware/arm_timer.h>
 
 static long __init sp804_get_clock_rate(const char *name)
@@ -67,7 +68,16 @@ static long __init sp804_get_clock_rate(const char *name)
         return rate;
 }
 
-void __init sp804_clocksource_init(void __iomem *base, const char *name)
+static void __iomem *sched_clock_base;
+
+static u32 sp804_read(void)
+{
+        return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
+}
+
+void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
+                                                     const char *name,
+                                                     int use_sched_clock)
 {
         long rate = sp804_get_clock_rate(name);
 
@@ -83,6 +93,11 @@ void __init sp804_clocksource_init(void __iomem *base, const char *name)
 
         clocksource_mmio_init(base + TIMER_VALUE, name,
                 rate, 200, 32, clocksource_mmio_readl_down);
+
+        if (use_sched_clock) {
+                sched_clock_base = base;
+                setup_sched_clock(sp804_read, 32, rate);
+        }
 }
 
 
diff --git a/arch/arm/configs/at91cap9_defconfig b/arch/arm/configs/at91cap9_defconfig
deleted file mode 100644
index 8826eb218e7..00000000000
--- a/arch/arm/configs/at91cap9_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91CAP9=y
-CONFIG_MACH_AT91CAP9ADK=y
-CONFIG_MTD_AT91_DATAFLASH_CARD=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_MMC=y
-CONFIG_MMC_AT91=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 9123568d9a8..994d331b231 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -74,6 +74,8 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
@@ -105,6 +107,7 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_EXT2_FS=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index a22e9307906..b5ac644e12a 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -45,6 +45,7 @@ CONFIG_FPE_NWFPE=y
 CONFIG_FPE_NWFPE_XP=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
+CONFIG_SMSC911X=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -68,6 +69,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
@@ -78,6 +80,8 @@ CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 CONFIG_NETDEVICES=y
+CONFIG_CS89x0=y
+CONFIG_CS89x0_PLATFORM=y
 CONFIG_DM9000=y
 CONFIG_SMC91X=y
 CONFIG_SMC911X=y
@@ -115,6 +119,21 @@ CONFIG_FB_IMX=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_MEDIA=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_OV2640=y
+CONFIG_VIDEO_MX2_HOSTSUPPORT=y
+CONFIG_VIDEO_MX2=y
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 3a4fb2e5fc6..dc6f6411bbf 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_CGROUPS=y
 CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_SLUB_DEBUG is not set
 # CONFIG_COMPAT_BRK is not set
@@ -12,7 +13,6 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_MX31LILLY=y
@@ -26,7 +26,6 @@ CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_KZM_ARM11_01=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
-CONFIG_MACH_EUKREA_CPUIMX35=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
@@ -82,8 +81,9 @@ CONFIG_PATA_IMX=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_CHELSIO is not set
+CONFIG_CS89x0=y
+CONFIG_CS89x0_PLATFORM=y
 # CONFIG_NET_VENDOR_FARADAY is not set
-CONFIG_FEC=y
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 # CONFIG_NET_VENDOR_MICREL is not set
@@ -126,7 +126,40 @@ CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
 CONFIG_MFD_MC13XXX=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_OV2640=y
+CONFIG_MX3_VIDEO=y
+CONFIG_VIDEO_MX3=y
+CONFIG_FB=y
+CONFIG_FB_MX3=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
new file mode 100644
index 00000000000..fb2088171ca
--- /dev/null
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -0,0 +1,145 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_LPC32XX=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
+CONFIG_CPU_IDLE=y
+CONFIG_FPE_NWFPE=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_AOUT=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_MUSEUM_IDS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_LPC32XX=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_PNX=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_PNX4008_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SOC=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_LPC32XX=y
+CONFIG_EXT2_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index 443675d317e..a691ef4c600 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -101,7 +101,7 @@ CONFIG_MFD_ASIC3=y
 CONFIG_HTC_EGPIO=y
 CONFIG_HTC_PASIC3=y
 CONFIG_REGULATOR=y
-CONFIG_REGULATOR_BQ24022=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_FB=y
 CONFIG_FB_PXA=y
 CONFIG_FB_PXA_OVERLAY=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 2472a958583..42da9183acc 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -13,7 +13,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_ARCH_S3C2410=y
+CONFIG_ARCH_S3C24XX=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
 CONFIG_MACH_MINI2440=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 6ee781bf6bf..1ebbf451c48 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -77,10 +77,10 @@ CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
+CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MXS=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MXS=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
 CONFIG_DEBUG_GPIO=y
@@ -90,6 +90,20 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_ARM=y
+CONFIG_SND_SOC=y
+CONFIG_SND_MXS_SOC=y
+CONFIG_SND_SOC_MXS_SGTL5000=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index f9096c1b0a6..193448f3128 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -3,40 +3,47 @@ CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=m
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S3C2410=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_ARCH_S3C24XX=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
-CONFIG_ARCH_SMDK2410=y
+CONFIG_CPU_S3C2412=y
+CONFIG_CPU_S3C2416=y
+CONFIG_CPU_S3C2440=y
+CONFIG_CPU_S3C2442=y
+CONFIG_CPU_S3C2443=y
+CONFIG_MACH_AML_M5900=y
+CONFIG_ARCH_BAST=y
 CONFIG_ARCH_H1940=y
 CONFIG_MACH_N30=y
-CONFIG_ARCH_BAST=y
 CONFIG_MACH_OTOM=y
-CONFIG_MACH_AML_M5900=y
+CONFIG_MACH_QT2410=y
+CONFIG_ARCH_SMDK2410=y
 CONFIG_MACH_TCT_HAMMER=y
 CONFIG_MACH_VR1000=y
-CONFIG_MACH_QT2410=y
 CONFIG_MACH_JIVE=y
 CONFIG_MACH_SMDK2412=y
 CONFIG_MACH_VSTMS=y
 CONFIG_MACH_SMDK2416=y
 CONFIG_MACH_ANUBIS=y
-CONFIG_MACH_NEO1973_GTA02=y
+CONFIG_MACH_AT2440EVB=y
+CONFIG_MACH_MINI2440=y
+CONFIG_MACH_NEXCODER_2440=y
 CONFIG_MACH_OSIRIS=y
 CONFIG_MACH_OSIRIS_DVS=m
 CONFIG_MACH_RX3715=y
 CONFIG_ARCH_S3C2440=y
-CONFIG_MACH_NEXCODER_2440=y
-CONFIG_SMDK2440_CPU2442=y
-CONFIG_MACH_AT2440EVB=y
-CONFIG_MACH_MINI2440=y
+CONFIG_MACH_NEO1973_GTA02=y
 CONFIG_MACH_RX1950=y
+CONFIG_SMDK2440_CPU2442=y
 CONFIG_MACH_SMDK2443=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -45,7 +52,6 @@ CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
 CONFIG_FPE_NWFPE=y
 CONFIG_FPE_NWFPE_XP=y
 CONFIG_BINFMT_AOUT=y
-CONFIG_PM=y
 CONFIG_APM_EMULATION=m
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -58,7 +64,6 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
@@ -80,7 +85,6 @@ CONFIG_IPV6_MIP6=m
 CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
 CONFIG_IPV6_TUNNEL=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
 CONFIG_NF_CONNTRACK_EVENTS=y
 CONFIG_NF_CT_PROTO_DCCP=m
@@ -138,7 +142,6 @@ CONFIG_IP_VS=m
 CONFIG_NF_CONNTRACK_IPV4=m
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
@@ -150,7 +153,6 @@ CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -177,8 +179,6 @@ CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
 CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
 CONFIG_BT_RFCOMM=m
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_BT_BNEP=m
@@ -199,7 +199,6 @@ CONFIG_MAC80211_MESH=y
 CONFIG_MAC80211_LEDS=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_REDBOOT_PARTS=y
 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
 CONFIG_MTD_CMDLINE_PARTS=y
@@ -221,9 +220,6 @@ CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_UB=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_ATA_OVER_ETH=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_93CX6=m
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_IDETAPE=m
@@ -240,7 +236,6 @@ CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_DM9000=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_MOUSE_APPLETOUCH=m
@@ -274,7 +269,6 @@ CONFIG_JOYSTICK_XPAD_LEDS=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
 CONFIG_INPUT_MISC=y
-CONFIG_INPUT_ATI_REMOTE=m
 CONFIG_INPUT_ATI_REMOTE2=m
 CONFIG_INPUT_KEYSPAN_REMOTE=m
 CONFIG_INPUT_POWERMATE=m
@@ -300,7 +294,6 @@ CONFIG_I2C_SIMTEC=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
 CONFIG_SPI_S3C24XX=m
-CONFIG_SPI_S3C24XX_GPIO=m
 CONFIG_SPI_SPIDEV=m
 CONFIG_SPI_TLE62X0=m
 CONFIG_SENSORS_LM75=m
@@ -315,7 +308,6 @@ CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_S3C2410=y
 CONFIG_FB_SM501=y
 CONFIG_BACKLIGHT_PWM=m
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -330,10 +322,6 @@ CONFIG_SND_VERBOSE_PRINTK=y
 CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_USB_CAIAQ=m
 CONFIG_SND_SOC=y
-CONFIG_SND_S3C24XX_SOC=y
-CONFIG_SND_S3C24XX_SOC_JIVE_WM8750=m
-CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710=m
-CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
@@ -387,9 +375,7 @@ CONFIG_MMC_TEST=m
 CONFIG_MMC_SDHCI=m
 CONFIG_MMC_SPI=m
 CONFIG_MMC_S3C=y
-CONFIG_LEDS_CLASS=m
 CONFIG_LEDS_S3C24XX=m
-CONFIG_LEDS_H1940=m
 CONFIG_LEDS_PCA9532=m
 CONFIG_LEDS_GPIO=m
 CONFIG_LEDS_PCA955X=m
@@ -410,8 +396,6 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT4_FS=m
 CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_ISO9660_FS=y
@@ -436,9 +420,6 @@ CONFIG_NFSD=m
 CONFIG_NFSD_V3_ACL=y
 CONFIG_NFSD_V4=y
 CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_SOLARIS_X86_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -481,9 +462,7 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 95c0f0d63db..1d24f8458be 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -14,7 +14,7 @@ CONFIG_SLOB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S3C2410=y
+CONFIG_ARCH_S3C24XX=y
 CONFIG_MACH_TCT_HAMMER=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index fd5d3041d71..351d6708c3a 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -11,11 +11,14 @@ CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_ELF_CORE is not set
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
@@ -27,18 +30,20 @@ CONFIG_MACH_PAZ00=y
 CONFIG_MACH_TRIMSLICE=y
 CONFIG_MACH_WARIO=y
 CONFIG_MACH_VENTANA=y
-CONFIG_TEGRA_DEBUG_UARTD=y
-CONFIG_ARM_ERRATA_742230=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
-CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -68,7 +73,6 @@ CONFIG_IPV6_MULTIPLE_TABLES=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
 CONFIG_ICS932S401=y
@@ -76,6 +80,7 @@ CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
@@ -85,8 +90,7 @@ CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 # CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
@@ -96,13 +100,15 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-# CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -116,11 +122,13 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
@@ -130,6 +138,11 @@ CONFIG_STAGING=y
 CONFIG_IIO=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_AK8975=y
+CONFIG_MFD_NVEC=y
+CONFIG_KEYBOARD_NVEC=y
+CONFIG_SERIO_NVEC_PS2=y
+CONFIG_TEGRA_IOMMU_GART=y
+CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -138,13 +151,12 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
@@ -162,9 +174,8 @@ CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_TWOFISH=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TEGRA_AES=y
 CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d7b6e7b727..889d73ac1ae 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -13,6 +13,7 @@ CONFIG_UX500_SOC_DB8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_U5500=y
+CONFIG_MACH_UX500_DT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7bf22d..d6030ff599d 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
  *
  * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
  * can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
  */
+#define TIMER_1_BASE    0x00
+#define TIMER_2_BASE    0x20
+
 #define TIMER_LOAD      0x00                    /* ACVR rw */
 #define TIMER_VALUE     0x04                    /* ACVR ro */
 #define TIMER_CTRL      0x08                    /* ACVR rw */
diff --git a/arch/arm/include/asm/hardware/entry-macro-iomd.S b/arch/arm/include/asm/hardware/entry-macro-iomd.S
index e0af4983723..8c215acd9b5 100644
--- a/arch/arm/include/asm/hardware/entry-macro-iomd.S
+++ b/arch/arm/include/asm/hardware/entry-macro-iomd.S
@@ -11,14 +11,6 @@
 /* IOC / IOMD based hardware */
 #include <asm/hardware/iomd.h>
 
-                .macro  disable_fiq
-                mov     r12, #ioc_base_high
-                .if     ioc_base_low
-                orr     r12, r12, #ioc_base_low
-                .endif
-                strb    r12, [r12, #0x38]       @ Disable FIQ register
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldrb    \irqstat, [\base, #IOMD_IRQREQB]        @ get high priority first
                 ldr     \tmp, =irq_prio_h
diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h
index 92ed254c175..7c2bbc7f0be 100644
--- a/arch/arm/include/asm/hardware/sa1111.h
+++ b/arch/arm/include/asm/hardware/sa1111.h
@@ -132,34 +132,10 @@
 #define SKPCR_DCLKEN    (1<<7)
 #define SKPCR_PWMCLKEN  (1<<8)
 
-/*
- * USB Host controller
- */
+/* USB Host controller */
 #define SA1111_USB              0x0400
 
 /*
- * Offsets from SA1111_USB_BASE
- */
-#define SA1111_USB_STATUS       0x0118
-#define SA1111_USB_RESET        0x011c
-#define SA1111_USB_IRQTEST      0x0120
-
-#define USB_RESET_FORCEIFRESET  (1 << 0)
-#define USB_RESET_FORCEHCRESET  (1 << 1)
-#define USB_RESET_CLKGENRESET   (1 << 2)
-#define USB_RESET_SIMSCALEDOWN  (1 << 3)
-#define USB_RESET_USBINTTEST    (1 << 4)
-#define USB_RESET_SLEEPSTBYEN   (1 << 5)
-#define USB_RESET_PWRSENSELOW   (1 << 6)
-#define USB_RESET_PWRCTRLLOW    (1 << 7)
-
-#define USB_STATUS_IRQHCIRMTWKUP  (1 <<  7)
-#define USB_STATUS_IRQHCIBUFFACC  (1 <<  8)
-#define USB_STATUS_NIRQHCIM       (1 <<  9)
-#define USB_STATUS_NHCIMFCLR      (1 << 10)
-#define USB_STATUS_USBPWRSENSE    (1 << 11)
-
-/*
  * Serial Audio Controller
  *
  * Registers
@@ -327,22 +303,6 @@
  *    PC_SSR            GPIO Block C Sleep State
  */
 
-#define _PA_DDR         _SA1111( 0x1000 )
-#define _PA_DRR         _SA1111( 0x1004 )
-#define _PA_DWR         _SA1111( 0x1004 )
-#define _PA_SDR         _SA1111( 0x1008 )
-#define _PA_SSR         _SA1111( 0x100c )
-#define _PB_DDR         _SA1111( 0x1010 )
-#define _PB_DRR         _SA1111( 0x1014 )
-#define _PB_DWR         _SA1111( 0x1014 )
-#define _PB_SDR         _SA1111( 0x1018 )
-#define _PB_SSR         _SA1111( 0x101c )
-#define _PC_DDR         _SA1111( 0x1020 )
-#define _PC_DRR         _SA1111( 0x1024 )
-#define _PC_DWR         _SA1111( 0x1024 )
-#define _PC_SDR         _SA1111( 0x1028 )
-#define _PC_SSR         _SA1111( 0x102c )
-
 #define SA1111_GPIO     0x1000
 
 #define SA1111_GPIO_PADDR       (0x000)
@@ -425,106 +385,30 @@
 #define SA1111_WAKEPOL0         0x0034
 #define SA1111_WAKEPOL1         0x0038
 
-/*
- * PS/2 Trackpad and Mouse Interfaces
- *
- * Registers
- *    PS2CR             Control Register
- *    PS2STAT           Status Register
- *    PS2DATA           Transmit/Receive Data register
- *    PS2CLKDIV         Clock Division Register
- *    PS2PRECNT         Clock Precount Register
- *    PS2TEST1          Test register 1
- *    PS2TEST2          Test register 2
- *    PS2TEST3          Test register 3
- *    PS2TEST4          Test register 4
- */
-
+/* PS/2 Trackpad and Mouse Interfaces */
 #define SA1111_KBD              0x0a00
 #define SA1111_MSE              0x0c00
 
-/*
- * These are offsets from the above bases.
- */
-#define SA1111_PS2CR            0x0000
-#define SA1111_PS2STAT          0x0004
-#define SA1111_PS2DATA          0x0008
-#define SA1111_PS2CLKDIV        0x000c
-#define SA1111_PS2PRECNT        0x0010
-
-#define PS2CR_ENA               0x08
-#define PS2CR_FKD               0x02
-#define PS2CR_FKC               0x01
-
-#define PS2STAT_STP             0x0100
-#define PS2STAT_TXE             0x0080
-#define PS2STAT_TXB             0x0040
-#define PS2STAT_RXF             0x0020
-#define PS2STAT_RXB             0x0010
-#define PS2STAT_ENA             0x0008
-#define PS2STAT_RXP             0x0004
-#define PS2STAT_KBD             0x0002
-#define PS2STAT_KBC             0x0001
+/* PCMCIA Interface */
+#define SA1111_PCMCIA           0x1600
 
-/*
- * PCMCIA Interface
- *
- * Registers
- *    PCSR      Status Register
- *    PCCR      Control Register
- *    PCSSR     Sleep State Register
- */
-
-#define SA1111_PCMCIA   0x1600
-
-/*
- * These are offsets from the above base.
- */
-#define SA1111_PCCR     0x0000
-#define SA1111_PCSSR    0x0004
-#define SA1111_PCSR     0x0008
-
-#define PCSR_S0_READY   (1<<0)
-#define PCSR_S1_READY   (1<<1)
-#define PCSR_S0_DETECT  (1<<2)
-#define PCSR_S1_DETECT  (1<<3)
-#define PCSR_S0_VS1     (1<<4)
-#define PCSR_S0_VS2     (1<<5)
-#define PCSR_S1_VS1     (1<<6)
-#define PCSR_S1_VS2     (1<<7)
-#define PCSR_S0_WP      (1<<8)
-#define PCSR_S1_WP      (1<<9)
-#define PCSR_S0_BVD1    (1<<10)
-#define PCSR_S0_BVD2    (1<<11)
-#define PCSR_S1_BVD1    (1<<12)
-#define PCSR_S1_BVD2    (1<<13)
-
-#define PCCR_S0_RST     (1<<0)
-#define PCCR_S1_RST     (1<<1)
-#define PCCR_S0_FLT     (1<<2)
-#define PCCR_S1_FLT     (1<<3)
-#define PCCR_S0_PWAITEN (1<<4)
-#define PCCR_S1_PWAITEN (1<<5)
-#define PCCR_S0_PSE     (1<<6)
-#define PCCR_S1_PSE     (1<<7)
-
-#define PCSSR_S0_SLEEP  (1<<0)
-#define PCSSR_S1_SLEEP  (1<<1)
 
 
 
 
 extern struct bus_type sa1111_bus_type;
 
-#define SA1111_DEVID_SBI        0
-#define SA1111_DEVID_SK         1
-#define SA1111_DEVID_USB        2
-#define SA1111_DEVID_SAC        3
-#define SA1111_DEVID_SSP        4
-#define SA1111_DEVID_PS2        5
-#define SA1111_DEVID_GPIO       6
-#define SA1111_DEVID_INT        7
-#define SA1111_DEVID_PCMCIA     8
+#define SA1111_DEVID_SBI        (1 << 0)
+#define SA1111_DEVID_SK         (1 << 1)
+#define SA1111_DEVID_USB        (1 << 2)
+#define SA1111_DEVID_SAC        (1 << 3)
+#define SA1111_DEVID_SSP        (1 << 4)
+#define SA1111_DEVID_PS2        (3 << 5)
+#define SA1111_DEVID_PS2_KBD    (1 << 5)
+#define SA1111_DEVID_PS2_MSE    (1 << 6)
+#define SA1111_DEVID_GPIO       (1 << 7)
+#define SA1111_DEVID_INT        (1 << 8)
+#define SA1111_DEVID_PCMCIA     (1 << 9)
 
 struct sa1111_dev {
         struct device   dev;
@@ -548,6 +432,7 @@ struct sa1111_driver {
         int (*remove)(struct sa1111_dev *);
         int (*suspend)(struct sa1111_dev *, pm_message_t);
         int (*resume)(struct sa1111_dev *);
+        void (*shutdown)(struct sa1111_dev *);
 };
 
 #define SA1111_DRV(_d)  container_of((_d), struct sa1111_driver, drv)
@@ -555,9 +440,10 @@ struct sa1111_driver {
 #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
 
 /*
- * These frob the SKPCR register.
+ * These frob the SKPCR register, and call platform specific
+ * enable/disable functions.
  */
-void sa1111_enable_device(struct sa1111_dev *);
+int sa1111_enable_device(struct sa1111_dev *);
 void sa1111_disable_device(struct sa1111_dev *);
 
 unsigned int sa1111_pll_clock(struct sa1111_dev *);
@@ -580,6 +466,10 @@ void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned i
 
 struct sa1111_platform_data {
         int     irq_base;       /* base for cascaded on-chip IRQs */
+        unsigned disable_devs;
+        void    *data;
+        int     (*enable)(void *, unsigned);
+        void    (*disable)(void *, unsigned);
 };
 
 #endif  /* _ASM_ARCH_SA1111 */
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 4384d81eee7..2dd9d3f83f2 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,2 +1,15 @@
-void sp804_clocksource_init(void __iomem *, const char *);
+void __sp804_clocksource_and_sched_clock_init(void __iomem *,
+                                              const char *, int);
+
+static inline void sp804_clocksource_init(void __iomem *base, const char *name)
+{
+        __sp804_clocksource_and_sched_clock_init(base, name, 0);
+}
+
+static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
+                                                          const char *name)
+{
+        __sp804_clocksource_and_sched_clock_init(base, name, 1);
+}
+
 void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index c6a18424888..f77ffc1eb0c 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -11,47 +11,24 @@
 #define __ASM_ARM_LOCALTIMER_H
 
 #include <linux/errno.h>
-#include <linux/interrupt.h>
 
 struct clock_event_device;
 
-/*
- * Setup a per-cpu timer, whether it be a local timer or dummy broadcast
- */
-void percpu_timer_setup(void);
+struct local_timer_ops {
+        int  (*setup)(struct clock_event_device *);
+        void (*stop)(struct clock_event_device *);
+};
 
 #ifdef CONFIG_LOCAL_TIMERS
-
-#ifdef CONFIG_HAVE_ARM_TWD
-
-#include "smp_twd.h"
-
-#define local_timer_stop(c)     twd_timer_stop((c))
-
-#else
-
-/*
- * Stop the local timer
- */
-void local_timer_stop(struct clock_event_device *);
-
-#endif
-
 /*
- * Setup a local timer interrupt for a CPU.
+ * Register a local timer driver
  */
-int local_timer_setup(struct clock_event_device *);
-
+int local_timer_register(struct local_timer_ops *);
 #else
-
-static inline int local_timer_setup(struct clock_event_device *evt)
+static inline int local_timer_register(struct local_timer_ops *ops)
 {
         return -ENXIO;
 }
-
-static inline void local_timer_stop(struct clock_event_device *evt)
-{
-}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index da337ba57ff..a98a2e112fa 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -57,14 +57,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state, int write_combine);
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 /*
  * Dummy implementation; always return 0.
  */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index ffc0e85775b..7ec60d6075b 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -79,7 +79,6 @@ extern unsigned int kobjsize(const void *objp);
  * No page table caches to initialise.
  */
 #define pgtable_cache_init()    do { } while (0)
-#define io_remap_page_range     remap_page_range
 #define io_remap_pfn_range      remap_pfn_range
 
 
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index ef9ffba97ad..0f01f4677bd 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -18,11 +18,28 @@
 #define TWD_TIMER_CONTROL_PERIODIC      (1 << 1)
 #define TWD_TIMER_CONTROL_IT_ENABLE     (1 << 2)
 
-struct clock_event_device;
+#include <linux/ioport.h>
 
-extern void __iomem *twd_base;
+struct twd_local_timer {
+        struct resource res[2];
+};
 
-void twd_timer_setup(struct clock_event_device *);
-void twd_timer_stop(struct clock_event_device *);
+#define DEFINE_TWD_LOCAL_TIMER(name,base,irq)   \
+struct twd_local_timer name __initdata = {      \
+        .res    = {                             \
+                DEFINE_RES_MEM(base, 0x10),     \
+                DEFINE_RES_IRQ(irq),            \
+        },                                      \
+};
+
+int twd_local_timer_register(struct twd_local_timer *);
+
+#ifdef CONFIG_HAVE_ARM_TWD
+void twd_local_timer_of_register(void);
+#else
+static inline void twd_local_timer_of_register(void)
+{
+}
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 9e65b23be14..5a85f148b60 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -11,6 +11,7 @@ extern void cpu_init(void);
 
 void soft_restart(unsigned long);
 extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED  (1 << 0)
 #define UDBG_SYSCALL    (1 << 1)
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 43b740d0e37..3a274878412 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_LEDS)		+= leds.o
 obj-$(CONFIG_OC_ETM)            += etm.o
 
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
-obj-$(CONFIG_ARCH_ACORN)        += ecard.o 
 obj-$(CONFIG_FIQ)               += fiq.o fiqasm.o
 obj-$(CONFIG_MODULES)           += armksyms.o module.o
 obj-$(CONFIG_ARTHUR)            += arthur.o
@@ -62,9 +61,6 @@ obj-$(CONFIG_SWP_EMULATE)	+= swp_emulate.o
 CFLAGS_swp_emulate.o            := -Wa,-march=armv7-a
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += hw_breakpoint.o
 
-obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
-AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
-
 obj-$(CONFIG_CPU_XSCALE)        += xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index f58ba358990..632df9a66f8 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -16,7 +16,6 @@
 #include <asm/mach/pci.h>
 
 static int debug_pci;
-static int use_firmware;
 
 /*
  * We can't use pci_find_device() here since we are
@@ -295,28 +294,6 @@ static inline int pdev_bad_for_parity(struct pci_dev *dev)
 }
 
 /*
- * Adjust the device resources from bus-centric to Linux-centric.
- */
-static void __devinit
-pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
-{
-        resource_size_t offset;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (dev->resource[i].start == 0)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = root->mem_offset;
-                else
-                        offset = root->io_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end   += offset;
-        }
-}
-
-/*
  * pcibios_fixup_bus - Called after each bus is probed,
  * but before its children are examined.
  */
@@ -333,8 +310,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
         list_for_each_entry(dev, &bus->devices, bus_list) {
                 u16 status;
 
-                pdev_fixup_device_resources(root, dev);
-
                 pci_read_config_word(dev, PCI_STATUS, &status);
 
                 /*
@@ -400,43 +375,6 @@ EXPORT_SYMBOL(pcibios_fixup_bus);
 #endif
 
 /*
- * Convert from Linux-centric to bus-centric addresses for bridge devices.
- */
-void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_sys_data *root = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = root->io_offset;
-        if (res->flags & IORESOURCE_MEM)
-                offset = root->mem_offset;
-
-        region->start = res->start - offset;
-        region->end   = res->end - offset;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void __devinit
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region)
-{
-        struct pci_sys_data *root = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = root->io_offset;
-        if (res->flags & IORESOURCE_MEM)
-                offset = root->mem_offset;
-
-        res->start = region->start + offset;
-        res->end   = region->end + offset;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/*
  * Swizzle the device pin each time we cross a bridge.
  * This might update pin and returns the slot number.
  */
@@ -497,10 +435,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
 
                 if (ret > 0) {
                         if (list_empty(&sys->resources)) {
-                                pci_add_resource(&sys->resources,
-                                                 &ioport_resource);
-                                pci_add_resource(&sys->resources,
-                                                 &iomem_resource);
+                                pci_add_resource_offset(&sys->resources,
+                                         &ioport_resource, sys->io_offset);
+                                pci_add_resource_offset(&sys->resources,
+                                         &iomem_resource, sys->mem_offset);
                         }
 
                         sys->bus = hw->scan(nr, sys);
@@ -525,6 +463,7 @@ void __init pci_common_init(struct hw_pci *hw)
 
         INIT_LIST_HEAD(&hw->buses);
 
+        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
         if (hw->preinit)
                 hw->preinit();
         pcibios_init_hw(hw);
@@ -536,7 +475,7 @@ void __init pci_common_init(struct hw_pci *hw)
         list_for_each_entry(sys, &hw->buses, node) {
                 struct pci_bus *bus = sys->bus;
 
-                if (!use_firmware) {
+                if (!pci_has_flag(PCI_PROBE_ONLY)) {
                         /*
                          * Size the bridge windows.
                          */
@@ -573,7 +512,7 @@ char * __init pcibios_setup(char *str)
                 debug_pci = 1;
                 return NULL;
         } else if (!strcmp(str, "firmware")) {
-                use_firmware = 1;
+                pci_add_flags(PCI_PROBE_ONLY);
                 return NULL;
         }
         return str;
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 093a415902c..8ec5eed55e3 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -19,7 +19,9 @@
 #include <asm/glue-df.h>
 #include <asm/glue-pf.h>
 #include <asm/vfpmacros.h>
+#ifndef CONFIG_MULTI_IRQ_HANDLER
 #include <mach/entry-macro.S>
+#endif
 #include <asm/thread_notify.h>
 #include <asm/unwind.h>
 #include <asm/unistd.h>
@@ -1101,7 +1103,6 @@ __stubs_start:
  * get out of that mode without clobbering one register.
  */
 vector_fiq:
-        disable_fiq
         subs    pc, lr, #4
 
 /*=============================================================================
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 9fd0ba90c1d..54ee265dd81 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -10,9 +10,15 @@
 
 #include <asm/unistd.h>
 #include <asm/ftrace.h>
-#include <mach/entry-macro.S>
 #include <asm/unwind.h>
 
+#ifdef CONFIG_NEED_RET_TO_USER
+#include <mach/entry-macro.S>
+#else
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+#endif
+
 #include "entry-header.S"
 
 
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 19917e89f13..7b9cddef6e5 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -60,8 +60,6 @@ extern void setup_mm_for_reboot(void);
 
 static volatile int hlt_counter;
 
-#include <mach/system.h>
-
 void disable_hlt(void)
 {
         hlt_counter++;
@@ -180,13 +178,17 @@ void cpu_idle_wait(void)
 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 
 /*
- * This is our default idle handler.  We need to disable
- * interrupts here to ensure we don't miss a wakeup call.
+ * This is our default idle handler.
  */
+
+void (*arm_pm_idle)(void);
+
 static void default_idle(void)
 {
-        if (!need_resched())
-                arch_idle();
+        if (arm_pm_idle)
+                arm_pm_idle();
+        else
+                cpu_do_idle();
         local_irq_enable();
 }
 
@@ -214,6 +216,10 @@ void cpu_idle(void)
                                 cpu_die();
 #endif
 
+                        /*
+                         * We need to disable interrupts here
+                         * to ensure we don't miss a wakeup call.
+                         */
                         local_irq_disable();
 #ifdef CONFIG_PL310_ERRATA_769419
                         wmb();
@@ -221,19 +227,18 @@ void cpu_idle(void)
                         if (hlt_counter) {
                                 local_irq_enable();
                                 cpu_relax();
-                        } else {
+                        } else if (!need_resched()) {
                                 stop_critical_timings();
                                 if (cpuidle_idle_call())
                                         pm_idle();
                                 start_critical_timings();
                                 /*
-                                 * This will eventually be removed - pm_idle
-                                 * functions should always return with IRQs
-                                 * enabled.
+                                 * pm_idle functions must always
+                                 * return with IRQs enabled.
                                  */
                                 WARN_ON(irqs_disabled());
+                        } else
                                 local_irq_enable();
-                        }
                 }
                 leds_event(led_idle_end);
                 rcu_idle_exit();
@@ -532,8 +537,7 @@ int vectors_user_mapping(void)
         struct mm_struct *mm = current->mm;
         return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
                                        VM_READ | VM_EXEC |
-                                       VM_MAYREAD | VM_MAYEXEC |
-                                       VM_ALWAYSDUMP | VM_RESERVED,
+                                       VM_MAYREAD | VM_MAYEXEC | VM_RESERVED,
                                        NULL);
 }
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d616ed51e7a..8f8cce2c46c 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -246,6 +246,8 @@ static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
         store_cpu_topology(cpuid);
 }
 
+static void percpu_timer_setup(void);
+
 /*
  * This is the secondary CPU boot entry.  We're using this CPUs
  * idle thread stack, but a set of temporary page tables.
@@ -452,7 +454,20 @@ static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
         clockevents_register_device(evt);
 }
 
-void __cpuinit percpu_timer_setup(void)
+static struct local_timer_ops *lt_ops;
+
+#ifdef CONFIG_LOCAL_TIMERS
+int local_timer_register(struct local_timer_ops *ops)
+{
+        if (lt_ops)
+                return -EBUSY;
+
+        lt_ops = ops;
+        return 0;
+}
+#endif
+
+static void __cpuinit percpu_timer_setup(void)
 {
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
@@ -460,7 +475,7 @@ void __cpuinit percpu_timer_setup(void)
         evt->cpumask = cpumask_of(cpu);
         evt->broadcast = smp_timer_broadcast;
 
-        if (local_timer_setup(evt))
+        if (!lt_ops || lt_ops->setup(evt))
                 broadcast_timer_setup(evt);
 }
 
@@ -475,7 +490,8 @@ static void percpu_timer_stop(void)
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 
-        local_timer_stop(evt);
+        if (lt_ops)
+                lt_ops->stop(evt);
 }
 #endif
 
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 7a79b24597b..fef42b21cec 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -18,20 +18,23 @@
 #include <linux/smp.h>
 #include <linux/jiffies.h>
 #include <linux/clockchips.h>
-#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
 #include <asm/hardware/gic.h>
 
 /* set up by the platform code */
-void __iomem *twd_base;
+static void __iomem *twd_base;
 
 static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
 
 static struct clock_event_device __percpu **twd_evt;
+static int twd_ppi;
 
 static void twd_set_mode(enum clock_event_mode mode,
                         struct clock_event_device *clk)
@@ -77,7 +80,7 @@ static int twd_set_next_event(unsigned long evt,
  * If a local timer interrupt has occurred, acknowledge and return 1.
  * Otherwise, return 0.
  */
-int twd_timer_ack(void)
+static int twd_timer_ack(void)
 {
         if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
                 __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
@@ -87,7 +90,7 @@ int twd_timer_ack(void)
         return 0;
 }
 
-void twd_timer_stop(struct clock_event_device *clk)
+static void twd_timer_stop(struct clock_event_device *clk)
 {
         twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
         disable_percpu_irq(clk->irq);
@@ -222,28 +225,10 @@ static struct clk *twd_get_clock(void)
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit twd_timer_setup(struct clock_event_device *clk)
+static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
 {
         struct clock_event_device **this_cpu_clk;
 
-        if (!twd_evt) {
-                int err;
-
-                twd_evt = alloc_percpu(struct clock_event_device *);
-                if (!twd_evt) {
-                        pr_err("twd: can't allocate memory\n");
-                        return;
-                }
-
-                err = request_percpu_irq(clk->irq, twd_handler,
-                                         "twd", twd_evt);
-                if (err) {
-                        pr_err("twd: can't register interrupt %d (%d)\n",
-                               clk->irq, err);
-                        return;
-                }
-        }
-
         if (!twd_clk)
                 twd_clk = twd_get_clock();
 
@@ -260,6 +245,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
         clk->rating = 350;
         clk->set_mode = twd_set_mode;
         clk->set_next_event = twd_set_next_event;
+        clk->irq = twd_ppi;
 
         this_cpu_clk = __this_cpu_ptr(twd_evt);
         *this_cpu_clk = clk;
@@ -267,4 +253,95 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
         clockevents_config_and_register(clk, twd_timer_rate,
                                         0xf, 0xffffffff);
         enable_percpu_irq(clk->irq, 0);
+
+        return 0;
+}
+
+static struct local_timer_ops twd_lt_ops __cpuinitdata = {
+        .setup  = twd_timer_setup,
+        .stop   = twd_timer_stop,
+};
+
+static int __init twd_local_timer_common_register(void)
+{
+        int err;
+
+        twd_evt = alloc_percpu(struct clock_event_device *);
+        if (!twd_evt) {
+                err = -ENOMEM;
+                goto out_free;
+        }
+
+        err = request_percpu_irq(twd_ppi, twd_handler, "twd", twd_evt);
+        if (err) {
+                pr_err("twd: can't register interrupt %d (%d)\n", twd_ppi, err);
+                goto out_free;
+        }
+
+        err = local_timer_register(&twd_lt_ops);
+        if (err)
+                goto out_irq;
+
+        return 0;
+
+out_irq:
+        free_percpu_irq(twd_ppi, twd_evt);
+out_free:
+        iounmap(twd_base);
+        twd_base = NULL;
+        free_percpu(twd_evt);
+
+        return err;
 }
+
+int __init twd_local_timer_register(struct twd_local_timer *tlt)
+{
+        if (twd_base || twd_evt)
+                return -EBUSY;
+
+        twd_ppi = tlt->res[1].start;
+
+        twd_base = ioremap(tlt->res[0].start, resource_size(&tlt->res[0]));
+        if (!twd_base)
+                return -ENOMEM;
+
+        return twd_local_timer_common_register();
+}
+
+#ifdef CONFIG_OF
+const static struct of_device_id twd_of_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-twd-timer",      },
+        { .compatible = "arm,cortex-a5-twd-timer",      },
+        { .compatible = "arm,arm11mp-twd-timer",        },
+        { },
+};
+
+void __init twd_local_timer_of_register(void)
+{
+        struct device_node *np;
+        int err;
+
+        np = of_find_matching_node(NULL, twd_of_match);
+        if (!np) {
+                err = -ENODEV;
+                goto out;
+        }
+
+        twd_ppi = irq_of_parse_and_map(np, 0);
+        if (!twd_ppi) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        twd_base = of_iomap(np, 0);
+        if (!twd_base) {
+                err = -ENOMEM;
+                goto out;
+        }
+
+        err = twd_local_timer_common_register();
+
+out:
+        WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
+}
+#endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 71feb00a1e9..45db05d8d94 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -20,9 +20,11 @@ config HAVE_AT91_USART5
 
 config AT91_SAM9_ALT_RESET
         bool
+        default !ARCH_AT91X40
 
 config AT91_SAM9G45_RESET
         bool
+        default !ARCH_AT91X40
 
 menu "Atmel AT91 System-on-Chip"
 
@@ -45,7 +47,6 @@ config ARCH_AT91SAM9260
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
         select HAVE_NET_MACB
-        select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261"
@@ -53,7 +54,6 @@ config ARCH_AT91SAM9261
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
         select HAVE_AT91_DBGU0
-        select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G10
         bool "AT91SAM9G10"
@@ -61,7 +61,6 @@ config ARCH_AT91SAM9G10
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_DBGU0
         select HAVE_FB_ATMEL
-        select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9263
         bool "AT91SAM9263"
@@ -70,7 +69,6 @@ config ARCH_AT91SAM9263
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
         select HAVE_AT91_DBGU1
-        select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
@@ -79,7 +77,6 @@ config ARCH_AT91SAM9RL
         select HAVE_AT91_USART3
         select HAVE_FB_ATMEL
         select HAVE_AT91_DBGU0
-        select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G20
         bool "AT91SAM9G20"
@@ -90,7 +87,6 @@ config ARCH_AT91SAM9G20
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
         select HAVE_NET_MACB
-        select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G45
         bool "AT91SAM9G45"
@@ -100,16 +96,14 @@ config ARCH_AT91SAM9G45
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
         select HAVE_AT91_DBGU1
-        select AT91_SAM9G45_RESET
 
-config ARCH_AT91CAP9
-        bool "AT91CAP9"
+config ARCH_AT91SAM9X5
+        bool "AT91SAM9x5 family"
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
-        select HAVE_AT91_DBGU1
-        select AT91_SAM9G45_RESET
+        select HAVE_AT91_DBGU0
 
 config ARCH_AT91X40
         bool "AT91x40"
@@ -447,21 +441,6 @@ endif
 
 # ----------------------------------------------------------
 
-if ARCH_AT91CAP9
-
-comment "AT91CAP9 Board Type"
-
-config MACH_AT91CAP9ADK
-        bool "Atmel AT91CAP9A-DK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
-
-endif
-
-# ----------------------------------------------------------
-
 if ARCH_AT91X40
 
 comment "AT91X40 Board Type"
@@ -544,7 +523,7 @@ config AT91_EARLY_DBGU0
         depends on HAVE_AT91_DBGU0
 
 config AT91_EARLY_DBGU1
-        bool "DBGU on 9263, 9g45 and cap9"
+        bool "DBGU on 9263 and 9g45"
         depends on HAVE_AT91_DBGU1
 
 config AT91_EARLY_USART0
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 705e1fbded3..8512e53bed9 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263.o at91sam926x_time.o at91sam9263_d
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9X5)   += at91sam9x5.o at91sam926x_time.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
@@ -81,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 # AT91SAM board with device-tree
 obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
 
-# AT91CAP9 board-specific support
-obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
-
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
 
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 8ddafadfdc7..0da66ca4a4f 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -3,11 +3,7 @@
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
 
-ifeq ($(CONFIG_ARCH_AT91CAP9),y)
-   zreladdr-y   += 0x70008000
-params_phys-y   := 0x70000100
-initrd_phys-y   := 0x70410000
-else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
+ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
    zreladdr-y   += 0x70008000
 params_phys-y   := 0x70000100
 initrd_phys-y   := 0x70410000
@@ -17,4 +13,10 @@ params_phys-y	:= 0x20000100
 initrd_phys-y   := 0x20410000
 endif
 
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
+# Keep dtb files sorted alphabetically for each SoC
+# sam9g20
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
+# sam9g45
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+# sam9x5
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
deleted file mode 100644
index fc460e96f1a..00000000000
--- a/arch/arm/mach-at91/at91cap9.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * arch/arm/mach-at91/at91cap9.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/module.h>
-
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/system_info.h>
-#include <asm/system_misc.h>
-
-#include <mach/cpu.h>
-#include <mach/at91cap9.h>
-#include <mach/at91_pmc.h>
-
-#include "soc.h"
-#include "generic.h"
-#include "clock.h"
-#include "sam9_smc.h"
-
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioABCD_clk = {
-        .name           = "pioABCD_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb0_clk = {
-        .name           = "mpb0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb1_clk = {
-        .name           = "mpb1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb2_clk = {
-        .name           = "mpb2_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb3_clk = {
-        .name           = "mpb3_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb4_clk = {
-        .name           = "mpb4_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
-        .name           = "mci0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
-        .name           = "mci1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can_clk = {
-        .name           = "can_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_CAN,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
-        .name           = "twi_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_TWI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
-        .name           = "ac97_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
-        .name           = "tcb_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_TCB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-        .name           = "pwm_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
-        .name           = "pclk",
-        .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk aestdes_clk = {
-        .name           = "aestdes_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
-        .name           = "adc_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_ADC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
-        .name           = "isi_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_ISI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
-        .name           = "dma_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_DMA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
-        .name           = "udphs_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
-        &pioABCD_clk,
-        &mpb0_clk,
-        &mpb1_clk,
-        &mpb2_clk,
-        &mpb3_clk,
-        &mpb4_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &mmc0_clk,
-        &mmc1_clk,
-        &can_clk,
-        &twi_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &ac97_clk,
-        &tcb_clk,
-        &pwm_clk,
-        &macb_clk,
-        &aestdes_clk,
-        &adc_clk,
-        &isi_clk,
-        &lcdc_clk,
-        &dma_clk,
-        &udphs_clk,
-        &ohci_clk,
-        // irq0 .. irq1
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* One additional fake clock for macb_hclk */
-        CLKDEV_CON_ID("hclk", &macb_clk),
-        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
-        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
-        /* fake hclk clock */
-        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
-        CLKDEV_CON_ID("pioA", &pioABCD_clk),
-        CLKDEV_CON_ID("pioB", &pioABCD_clk),
-        CLKDEV_CON_ID("pioC", &pioABCD_clk),
-        CLKDEV_CON_ID("pioD", &pioABCD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-};
-
-/*
- * The four programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static struct clk pck2 = {
-        .name           = "pck2",
-        .pmc_mask       = AT91_PMC_PCK2,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 2,
-};
-static struct clk pck3 = {
-        .name           = "pck3",
-        .pmc_mask       = AT91_PMC_PCK3,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 3,
-};
-
-static void __init at91cap9_register_clocks(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clk_register(&pck2);
-        clk_register(&pck3);
-}
-
-static struct clk_lookup console_clock_lookup;
-
-void __init at91cap9_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
-
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-
-static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
-        {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOA,
-        }, {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOB,
-        }, {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOC,
-        }, {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOD,
-        }
-};
-
-/* --------------------------------------------------------------------
- *  AT91CAP9 processor initialization
- * -------------------------------------------------------------------- */
-
-static void __init at91cap9_map_io(void)
-{
-        at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
-}
-
-static void __init at91cap9_ioremap_registers(void)
-{
-        at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
-        at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
-        at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
-        at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
-}
-
-static void __init at91cap9_initialize(void)
-{
-        arm_pm_restart = at91sam9g45_restart;
-        at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
-
-        /* Register GPIO subsystem */
-        at91_gpio_init(at91cap9_gpio, 4);
-
-        /* Remember the silicon revision */
-        if (cpu_is_at91cap9_revB())
-                system_rev = 0xB;
-        else if (cpu_is_at91cap9_revC())
-                system_rev = 0xC;
-}
-
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A, B, C and D */
-        0,      /* MP Block Peripheral 0 */
-        0,      /* MP Block Peripheral 1 */
-        0,      /* MP Block Peripheral 2 */
-        0,      /* MP Block Peripheral 3 */
-        0,      /* MP Block Peripheral 4 */
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        0,      /* Multimedia Card Interface 0 */
-        0,      /* Multimedia Card Interface 1 */
-        3,      /* CAN */
-        6,      /* Two-Wire Interface */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        4,      /* Serial Synchronous Controller 0 */
-        4,      /* Serial Synchronous Controller 1 */
-        5,      /* AC97 Controller */
-        0,      /* Timer Counter 0, 1 and 2 */
-        0,      /* Pulse Width Modulation Controller */
-        3,      /* Ethernet */
-        0,      /* Advanced Encryption Standard, Triple DES*/
-        0,      /* Analog-to-Digital Converter */
-        0,      /* Image Sensor Interface */
-        3,      /* LCD Controller */
-        0,      /* DMA Controller */
-        2,      /* USB Device Port */
-        2,      /* USB Host port */
-        0,      /* Advanced Interrupt Controller (IRQ0) */
-        0,      /* Advanced Interrupt Controller (IRQ1) */
-};
-
-struct at91_init_soc __initdata at91cap9_soc = {
-        .map_io = at91cap9_map_io,
-        .default_irq_priority = at91cap9_default_irq_priority,
-        .ioremap_registers = at91cap9_ioremap_registers,
-        .register_clocks = at91cap9_register_clocks,
-        .init = at91cap9_initialize,
-};
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
deleted file mode 100644
index d298fb7cb21..00000000000
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ /dev/null
@@ -1,1273 +0,0 @@
-/*
- * arch/arm/mach-at91/at91cap9_devices.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-
-#include <video/atmel_lcdc.h>
-
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91cap9.h>
-#include <mach/at91cap9_matrix.h>
-#include <mach/at91sam9_smc.h>
-
-#include "generic.h"
-
-
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-
-static struct resource usbh_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_UHP_BASE,
-                .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_UHP,
-                .end    = AT91CAP9_ID_UHP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91_usbh_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_data,
-        },
-        .resource       = usbh_resources,
-        .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-        int i;
-
-        if (!data)
-                return;
-
-        if (cpu_is_at91cap9_revB())
-                irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
-
-        /* Enable VBus control for UHP ports */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->vbus_pin[i]))
-                        at91_set_gpio_output(data->vbus_pin[i], 0);
-        }
-
-        /* Enable overcurrent notification */
-        for (i = 0; i < data->ports; i++) {
-                if (data->overcurrent_pin[i])
-                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
-        }
-
-        usbh_data = *data;
-        platform_device_register(&at91_usbh_device);
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  USB HS Device (Gadget)
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
-
-static struct resource usba_udc_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_UDPHS_FIFO,
-                .end    = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_BASE_UDPHS,
-                .end    = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = AT91CAP9_ID_UDPHS,
-                .end    = AT91CAP9_ID_UDPHS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
-        [idx] = {                                               \
-                .name           = nam,                          \
-                .index          = idx,                          \
-                .fifo_size      = maxpkt,                       \
-                .nr_banks       = maxbk,                        \
-                .can_dma        = dma,                          \
-                .can_isoc       = isoc,                         \
-        }
-
-static struct usba_ep_data usba_udc_ep[] = {
-        EP("ep0", 0,   64, 1, 0, 0),
-        EP("ep1", 1, 1024, 3, 1, 1),
-        EP("ep2", 2, 1024, 3, 1, 1),
-        EP("ep3", 3, 1024, 2, 1, 1),
-        EP("ep4", 4, 1024, 2, 1, 1),
-        EP("ep5", 5, 1024, 2, 1, 0),
-        EP("ep6", 6, 1024, 2, 1, 0),
-        EP("ep7", 7, 1024, 2, 0, 0),
-};
-
-#undef EP
-
-/*
- * pdata doesn't have room for any endpoints, so we need to
- * append room for the ones we need right after it.
- */
-static struct {
-        struct usba_platform_data pdata;
-        struct usba_ep_data ep[8];
-} usba_udc_data;
-
-static struct platform_device at91_usba_udc_device = {
-        .name           = "atmel_usba_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &usba_udc_data.pdata,
-        },
-        .resource       = usba_udc_resources,
-        .num_resources  = ARRAY_SIZE(usba_udc_resources),
-};
-
-void __init at91_add_device_usba(struct usba_platform_data *data)
-{
-        if (cpu_is_at91cap9_revB()) {
-                irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
-                at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
-                                                  AT91_MATRIX_UDPHS_BYPASS_LOCK);
-        }
-        else
-                at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
-
-        /*
-         * Invalid pins are 0 on AT91, but the usba driver is shared
-         * with AVR32, which use negative values instead. Once/if
-         * gpio_is_valid() is ported to AT91, revisit this code.
-         */
-        usba_udc_data.pdata.vbus_pin = -EINVAL;
-        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
-        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-
-        if (data && gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
-        }
-
-        /* Pullup pin is handled internally by USB device peripheral */
-
-        platform_device_register(&at91_usba_udc_device);
-}
-#else
-void __init at91_add_device_usba(struct usba_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct macb_platform_data eth_data;
-
-static struct resource eth_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_EMAC,
-                .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_EMAC,
-                .end    = AT91CAP9_ID_EMAC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_eth_device = {
-        .name           = "macb",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &eth_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &eth_data,
-        },
-        .resource       = eth_resources,
-        .num_resources  = ARRAY_SIZE(eth_resources),
-};
-
-void __init at91_add_device_eth(struct macb_platform_data *data)
-{
-        if (!data)
-                return;
-
-        if (gpio_is_valid(data->phy_irq_pin)) {
-                at91_set_gpio_input(data->phy_irq_pin, 0);
-                at91_set_deglitch(data->phy_irq_pin, 1);
-        }
-
-        /* Pins used for MII and RMII */
-        at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
-        at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
-        at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
-        at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
-        at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
-        at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
-        at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
-        at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
-        at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
-        at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
-
-        if (!data->is_rmii) {
-                at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
-                at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
-                at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
-                at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
-                at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
-                at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
-                at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
-                at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
-        }
-
-        eth_data = *data;
-        platform_device_register(&at91cap9_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct macb_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc0_data, mmc1_data;
-
-static struct resource mmc0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_MCI0,
-                .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_MCI0,
-                .end    = AT91CAP9_ID_MCI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_mmc0_device = {
-        .name           = "at91_mci",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc0_data,
-        },
-        .resource       = mmc0_resources,
-        .num_resources  = ARRAY_SIZE(mmc0_resources),
-};
-
-static struct resource mmc1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_MCI1,
-                .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_MCI1,
-                .end    = AT91CAP9_ID_MCI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_mmc1_device = {
-        .name           = "at91_mci",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc1_data,
-        },
-        .resource       = mmc1_resources,
-        .num_resources  = ARRAY_SIZE(mmc1_resources),
-};
-
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
-{
-        if (!data)
-                return;
-
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-
-        if (mmc_id == 0) {              /* MCI0 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA2, 0);
-
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA1, 1);
-
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA0, 1);
-                if (data->wire4) {
-                        at91_set_A_periph(AT91_PIN_PA3, 1);
-                        at91_set_A_periph(AT91_PIN_PA4, 1);
-                        at91_set_A_periph(AT91_PIN_PA5, 1);
-                }
-
-                mmc0_data = *data;
-                platform_device_register(&at91cap9_mmc0_device);
-        } else {                        /* MCI1 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA16, 0);
-
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA17, 1);
-
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA18, 1);
-                if (data->wire4) {
-                        at91_set_A_periph(AT91_PIN_PA19, 1);
-                        at91_set_A_periph(AT91_PIN_PA20, 1);
-                        at91_set_A_periph(AT91_PIN_PA21, 1);
-                }
-
-                mmc1_data = *data;
-                platform_device_register(&at91cap9_mmc1_device);
-        }
-}
-#else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-
-#define NAND_BASE       AT91_CHIPSELECT_3
-
-static struct resource nand_resources[] = {
-        [0] = {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_BASE_ECC,
-                .end    = AT91CAP9_BASE_ECC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at91cap9_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-
-        if (!data)
-                return;
-
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
-
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-
-        nand_data = *data;
-        platform_device_register(&at91cap9_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PB4,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PB5,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-
-static struct platform_device at91cap9_twi_device = {
-        .name                   = "i2c-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &pdata,
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PB4, 1);
-
-        at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PB5, 1);
-
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91cap9_twi_device);
-}
-
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-
-static struct resource twi_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_TWI,
-                .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_TWI,
-                .end    = AT91CAP9_ID_TWI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_twi_device = {
-        .name           = "at91_i2c",
-        .id             = -1,
-        .resource       = twi_resources,
-        .num_resources  = ARRAY_SIZE(twi_resources),
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* pins used for TWI interface */
-        at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
-        at91_set_multi_drive(AT91_PIN_PB4, 1);
-
-        at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PB5, 1);
-
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91cap9_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-static struct resource spi0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SPI0,
-                .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SPI0,
-                .end    = AT91CAP9_ID_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_spi0_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi0_resources,
-        .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
-
-static struct resource spi1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SPI1,
-                .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SPI1,
-                .end    = AT91CAP9_ID_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_spi1_device = {
-        .name           = "atmel_spi",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi1_resources,
-        .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
-
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        short enable_spi0 = 0;
-        short enable_spi1 = 0;
-
-        /* Choose SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else if (devices[i].bus_num == 0)
-                        cs_pin = spi0_standard_cs[devices[i].chip_select];
-                else
-                        cs_pin = spi1_standard_cs[devices[i].chip_select];
-
-                if (devices[i].bus_num == 0)
-                        enable_spi0 = 1;
-                else
-                        enable_spi1 = 1;
-
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-
-        spi_register_board_info(devices, nr_devices);
-
-        /* Configure SPI bus(es) */
-        if (enable_spi0) {
-                at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
-                at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
-                at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
-
-                platform_device_register(&at91cap9_spi0_device);
-        }
-        if (enable_spi1) {
-                at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
-                at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
-                at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
-
-                platform_device_register(&at91cap9_spi1_device);
-        }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Timer/Counter block
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_ATMEL_TCLIB
-
-static struct resource tcb_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_TCB0,
-                .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_TCB,
-                .end    = AT91CAP9_ID_TCB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_tcb_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb_resources,
-        .num_resources  = ARRAY_SIZE(tcb_resources),
-};
-
-static void __init at91_add_device_tc(void)
-{
-        platform_device_register(&at91cap9_tcb_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-
-
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-
-static struct resource rtt_resources[] = {
-        {
-                .start  = AT91CAP9_BASE_RTT,
-                .end    = AT91CAP9_BASE_RTT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at91cap9_rtt_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
-};
-
-static void __init at91_add_device_rtt(void)
-{
-        platform_device_register(&at91cap9_rtt_device);
-}
-
-
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-        {
-                .start  = AT91CAP9_BASE_WDT,
-                .end    = AT91CAP9_BASE_WDT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at91cap9_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .resource       = wdt_resources,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91cap9_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  PWM
- * --------------------------------------------------------------------*/
-
-#if defined(CONFIG_ATMEL_PWM)
-static u32 pwm_mask;
-
-static struct resource pwm_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_PWMC,
-                .end    = AT91CAP9_BASE_PWMC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_PWMC,
-                .end    = AT91CAP9_ID_PWMC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_pwm0_device = {
-        .name   = "atmel_pwm",
-        .id     = -1,
-        .dev    = {
-                .platform_data          = &pwm_mask,
-        },
-        .resource       = pwm_resources,
-        .num_resources  = ARRAY_SIZE(pwm_resources),
-};
-
-void __init at91_add_device_pwm(u32 mask)
-{
-        if (mask & (1 << AT91_PWM0))
-                at91_set_A_periph(AT91_PIN_PB19, 1);    /* enable PWM0 */
-
-        if (mask & (1 << AT91_PWM1))
-                at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM1 */
-
-        if (mask & (1 << AT91_PWM2))
-                at91_set_B_periph(AT91_PIN_PC29, 1);    /* enable PWM2 */
-
-        if (mask & (1 << AT91_PWM3))
-                at91_set_B_periph(AT91_PIN_PA11, 1);    /* enable PWM3 */
-
-        pwm_mask = mask;
-
-        platform_device_register(&at91cap9_pwm0_device);
-}
-#else
-void __init at91_add_device_pwm(u32 mask) {}
-#endif
-
-
-
-/* --------------------------------------------------------------------
- *  AC97
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
-static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct ac97c_platform_data ac97_data;
-
-static struct resource ac97_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_AC97C,
-                .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_AC97C,
-                .end    = AT91CAP9_ID_AC97C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_ac97_device = {
-        .name           = "atmel_ac97c",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &ac97_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &ac97_data,
-        },
-        .resource       = ac97_resources,
-        .num_resources  = ARRAY_SIZE(ac97_resources),
-};
-
-void __init at91_add_device_ac97(struct ac97c_platform_data *data)
-{
-        if (!data)
-                return;
-
-        at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
-        at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
-        at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
-        at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
-
-        /* reset */
-        if (gpio_is_valid(data->reset_pin))
-                at91_set_gpio_output(data->reset_pin, 0);
-
-        ac97_data = *data;
-        platform_device_register(&at91cap9_ac97_device);
-}
-#else
-void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  LCD Controller
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static u64 lcdc_dmamask = DMA_BIT_MASK(32);
-static struct atmel_lcdfb_info lcdc_data;
-
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_LCDC_BASE,
-                .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_LCDC,
-                .end    = AT91CAP9_ID_LCDC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &lcdc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &lcdc_data,
-        },
-        .resource       = lcdc_resources,
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-};
-
-void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
-{
-        if (!data)
-                return;
-
-        if (cpu_is_at91cap9_revB())
-                irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
-
-        at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
-        at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
-        at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
-        at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
-        at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
-        at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
-        at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
-        at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
-        at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
-        at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
-        at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
-        at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
-        at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
-        at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
-        at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
-        at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
-        at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
-        at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
-        at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
-        at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
-        at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
-        at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
-
-        lcdc_data = *data;
-        platform_device_register(&at91_lcdc_device);
-}
-#else
-void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-
-static struct resource ssc0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SSC0,
-                .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SSC0,
-                .end    = AT91CAP9_ID_SSC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_ssc0_device = {
-        .name   = "ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc0_resources,
-        .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-
-static inline void configure_ssc0_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB0, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB1, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB2, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB3, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB4, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB5, 1);
-}
-
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource ssc1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SSC1,
-                .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SSC1,
-                .end    = AT91CAP9_ID_SSC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_ssc1_device = {
-        .name   = "ssc",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ssc1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc1_resources,
-        .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-
-static inline void configure_ssc1_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB6, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB7, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB8, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB9, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB10, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB11, 1);
-}
-
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91CAP9_ID_SSC0:
-                pdev = &at91cap9_ssc0_device;
-                configure_ssc0_pins(pins);
-                break;
-        case AT91CAP9_ID_SSC1:
-                pdev = &at91cap9_ssc1_device;
-                configure_ssc1_pins(pins);
-                break;
-        default:
-                return;
-        }
-
-        platform_device_register(pdev);
-}
-
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_DBGU,
-                .end    = AT91CAP9_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
-        at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
-}
-
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_US0,
-                .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_US0,
-                .end    = AT91CAP9_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
-}
-
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_US1,
-                .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_US1,
-                .end    = AT91CAP9_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
-}
-
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_US2,
-                .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_US2,
-                .end    = AT91CAP9_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
-        at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
-}
-
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
-
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91cap9_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91CAP9_ID_US0:
-                        pdev = &at91cap9_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91CAP9_ID_US1:
-                        pdev = &at91cap9_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91CAP9_ID_US2:
-                        pdev = &at91cap9_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91cap9_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
-
-void __init at91_add_device_serial(void)
-{
-        int i;
-
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
-void __init at91_add_device_serial(void) {}
-#endif
-
-
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        at91_add_device_rtt();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 413c027ab85..364c19357e6 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -290,13 +290,22 @@ static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
         }
 };
 
+static void at91rm9200_idle(void)
+{
+        /*
+         * Disable the processor clock.  The processor will be automatically
+         * re-enabled by an interrupt or by a reset.
+         */
+        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+}
+
 static void at91rm9200_restart(char mode, const char *cmd)
 {
         /*
          * Perform a hardware reset with the use of the Watchdog timer.
          */
-        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+        at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+        at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 
 /* --------------------------------------------------------------------
@@ -311,10 +320,13 @@ static void __init at91rm9200_map_io(void)
 
 static void __init at91rm9200_ioremap_registers(void)
 {
+        at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
+        at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 }
 
 static void __init at91rm9200_initialize(void)
 {
+        arm_pm_idle = at91rm9200_idle;
         arm_pm_restart = at91rm9200_restart;
         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 97676bdae99..99ce5c955e3 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -21,6 +21,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
 
         /* CF takes over CS4, CS5, CS6 */
-        csa = at91_sys_read(AT91_EBI_CSA);
-        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+        csa = at91_ramc_read(0, AT91_EBI_CSA);
+        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
 
         /*
          * Static memory controller timing adjustments.
          * REVISIT:  these timings are in terms of MCK cycles, so
          * when MCK changes (cpufreq etc) so must these values...
          */
-        at91_sys_write(AT91_SMC_CSR(4),
+        at91_ramc_write(0, AT91_SMC_CSR(4),
                                   AT91_SMC_ACSS_STD
                                 | AT91_SMC_DBW_16
                                 | AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
                 return;
 
         /* enable the address range of CS3 */
-        csa = at91_sys_read(AT91_EBI_CSA);
-        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+        csa = at91_ramc_read(0, AT91_EBI_CSA);
+        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
+        at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
                 | AT91_SMC_NWS_(5)
                 | AT91_SMC_TDF_(1)
                 | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index a028cdf8f97..dd7f782b0b9 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
 {
         unsigned long x1, x2;
 
-        x1 = at91_sys_read(AT91_ST_CRTR);
+        x1 = at91_st_read(AT91_ST_CRTR);
         do {
-                x2 = at91_sys_read(AT91_ST_CRTR);
+                x2 = at91_st_read(AT91_ST_CRTR);
                 if (x1 == x2)
                         break;
                 x1 = x2;
@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
  */
 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 {
-        u32     sr = at91_sys_read(AT91_ST_SR) & irqmask;
+        u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
 
         /*
          * irqs should be disabled here, but as the irq is shared they are only
@@ -110,22 +110,22 @@ static void
 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
         /* Disable and flush pending timer interrupts */
-        at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
+        at91_st_read(AT91_ST_SR);
 
         last_crtr = read_CRTR();
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 /* PIT for periodic irqs; fixed rate of 1/HZ */
                 irqmask = AT91_ST_PITS;
-                at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
+                at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 /* ALM for oneshot irqs, set by next_event()
                  * before 32 seconds have passed
                  */
                 irqmask = AT91_ST_ALMS;
-                at91_sys_write(AT91_ST_RTAR, last_crtr);
+                at91_st_write(AT91_ST_RTAR, last_crtr);
                 break;
         case CLOCK_EVT_MODE_SHUTDOWN:
         case CLOCK_EVT_MODE_UNUSED:
@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                 irqmask = 0;
                 break;
         }
-        at91_sys_write(AT91_ST_IER, irqmask);
+        at91_st_write(AT91_ST_IER, irqmask);
 }
 
 static int
@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
         alm = read_CRTR();
 
         /* Cancel any pending alarm; flush any pending IRQ */
-        at91_sys_write(AT91_ST_RTAR, alm);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_write(AT91_ST_RTAR, alm);
+        at91_st_read(AT91_ST_SR);
 
         /* Schedule alarm by writing RTAR. */
         alm += delta;
-        at91_sys_write(AT91_ST_RTAR, alm);
+        at91_st_write(AT91_ST_RTAR, alm);
 
         return status;
 }
@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
         .set_mode       = clkevt32k_mode,
 };
 
+void __iomem *at91_st_base;
+
+void __init at91rm9200_ioremap_st(u32 addr)
+{
+        at91_st_base = ioremap(addr, 256);
+        if (!at91_st_base)
+                panic("Impossible to ioremap ST\n");
+}
+
 /*
  * ST (system timer) module supports both clockevents and clocksource.
  */
 void __init at91rm9200_timer_init(void)
 {
         /* Disable all timer interrupts, and clear any pending ones */
-        at91_sys_write(AT91_ST_IDR,
+        at91_st_write(AT91_ST_IDR,
                 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_read(AT91_ST_SR);
 
         /* Make IRQs happen for the system timer */
         setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
          * directly for the clocksource and all clockevents, after adjusting
          * its prescaler from the 1 Hz default.
          */
-        at91_sys_write(AT91_ST_RTMR, 1);
+        at91_st_write(AT91_ST_RTMR, 1);
 
         /* Setup timer clockevent, with minimum of two ticks (important!!) */
         clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 79f571842c2..46f77423329 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -209,6 +210,14 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
         CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
         CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -310,27 +319,27 @@ static void __init at91sam9xe_map_io(void)
 
 static void __init at91sam9260_map_io(void)
 {
-        if (cpu_is_at91sam9xe()) {
+        if (cpu_is_at91sam9xe())
                 at91sam9xe_map_io();
-        } else if (cpu_is_at91sam9g20()) {
-                at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
-                at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
-        } else {
-                at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
-                at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
-        }
+        else if (cpu_is_at91sam9g20())
+                at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
+        else
+                at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 }
 
 static void __init at91sam9260_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 }
 
 static void __init at91sam9260_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                         | (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 5a24f0b4554..7e5651ee9f8 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,6 +21,7 @@
 #include <mach/cpu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -641,7 +642,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 static struct resource tcb0_resources[] = {
         [0] = {
                 .start  = AT91SAM9260_BASE_TCB0,
-                .end    = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+                .end    = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -671,7 +672,7 @@ static struct platform_device at91sam9260_tcb0_device = {
 static struct resource tcb1_resources[] = {
         [0] = {
                 .start  = AT91SAM9260_BASE_TCB1,
-                .end    = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+                .end    = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -698,8 +699,25 @@ static struct platform_device at91sam9260_tcb1_device = {
         .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
+
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
+
         platform_device_register(&at91sam9260_tcb0_device);
         platform_device_register(&at91sam9260_tcb1_device);
 }
@@ -717,18 +735,42 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9260_BASE_RTT,
                 .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
-        }
+        }, {
+                .flags  = IORESOURCE_MEM,
+        },
 };
 
 static struct platform_device at91sam9260_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9260_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9260_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9260_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9260_rtt_device);
 }
 
@@ -1139,7 +1181,6 @@ static inline void configure_usart5_pins(void)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
@@ -1264,7 +1305,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
 
         switch (data->chipselect) {
         case 4:
@@ -1287,7 +1328,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                 return;
         }
 
-        at91_sys_write(AT91_MATRIX_EBICSA, csa);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa);
 
         if (gpio_is_valid(data->rst_pin)) {
                 at91_set_multi_drive(data->rst_pin, 0);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 62818b956ae..7de81e6222f 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -283,12 +284,15 @@ static void __init at91sam9261_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 }
 
 static void __init at91sam9261_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                         | (1 << AT91SAM9261_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 1e28bed8f42..096da87dc00 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,6 +24,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91sam9261_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9261_BASE_RTT,
                 .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9261_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9261_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9261_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9261_rtt_device);
 }
 
@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 722ee08e510..ef301be6657 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -303,13 +304,17 @@ static void __init at91sam9263_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
+        at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
         at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
         at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
+        at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
 }
 
 static void __init at91sam9263_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 366a7765635..53688c46f95 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -23,6 +23,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91sam9263_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
          * we assume SMC timings are configured by board code,
          * except True IDE where timings are controlled by driver
          */
-        ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+        ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
         switch (data->chipselect) {
         case 4:
                 at91_set_A_periph(AT91_PIN_PD6, 0);  /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                        data->chipselect);
                 return;
         }
-        at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
+        at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
 
         if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-        at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
+        at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -891,7 +892,8 @@ static struct platform_device at91sam9263_isi_device = {
         .num_resources  = ARRAY_SIZE(isi_resources),
 };
 
-void __init at91_add_device_isi(void)
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck)
 {
         at91_set_A_periph(AT91_PIN_PE0, 0);     /* ISI_D0 */
         at91_set_A_periph(AT91_PIN_PE1, 0);     /* ISI_D1 */
@@ -904,14 +906,20 @@ void __init at91_add_device_isi(void)
         at91_set_A_periph(AT91_PIN_PE8, 0);     /* ISI_PCK */
         at91_set_A_periph(AT91_PIN_PE9, 0);     /* ISI_HSYNC */
         at91_set_A_periph(AT91_PIN_PE10, 0);    /* ISI_VSYNC */
-        at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
         at91_set_B_periph(AT91_PIN_PE12, 0);    /* ISI_PD8 */
         at91_set_B_periph(AT91_PIN_PE13, 0);    /* ISI_PD9 */
         at91_set_B_periph(AT91_PIN_PE14, 0);    /* ISI_PD10 */
         at91_set_B_periph(AT91_PIN_PE15, 0);    /* ISI_PD11 */
+
+        if (use_pck_as_mck) {
+                at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
+
+                /* TODO: register the PCK for ISI_MCK and set its parent */
+        }
 }
 #else
-void __init at91_add_device_isi(void) {}
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck) {}
 #endif
 
 
@@ -959,6 +967,8 @@ static struct resource rtt0_resources[] = {
                 .start  = AT91SAM9263_BASE_RTT0,
                 .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -966,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt0_resources,
-        .num_resources  = ARRAY_SIZE(rtt0_resources),
 };
 
 static struct resource rtt1_resources[] = {
@@ -974,6 +983,8 @@ static struct resource rtt1_resources[] = {
                 .start  = AT91SAM9263_BASE_RTT1,
                 .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -981,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
         .name           = "at91_rtt",
         .id             = 1,
         .resource       = rtt1_resources,
-        .num_resources  = ARRAY_SIZE(rtt1_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        struct platform_device *pdev;
+        struct resource *r;
+
+        switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
+        case 0:
+                /*
+                 * The second resource is needed only for the chosen RTT:
+                 * GPBR will serve as the storage for RTC time offset
+                 */
+                at91sam9263_rtt0_device.num_resources = 2;
+                at91sam9263_rtt1_device.num_resources = 1;
+                pdev = &at91sam9263_rtt0_device;
+                r = rtt0_resources;
+                break;
+        case 1:
+                at91sam9263_rtt0_device.num_resources = 1;
+                at91sam9263_rtt1_device.num_resources = 2;
+                pdev = &at91sam9263_rtt1_device;
+                r = rtt1_resources;
+                break;
+        default:
+                pr_err("at91sam9263: only supports 2 RTT (%d)\n",
+                       CONFIG_RTC_DRV_AT91SAM9_RTT);
+                return;
+        }
+
+        pdev->name = "rtc-at91sam9";
+        r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        r[1].end = r[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9263_rtt0_device.num_resources = 1;
+        at91sam9263_rtt1_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9263_rtt0_device);
         platform_device_register(&at91sam9263_rtt1_device);
 }
@@ -1371,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead740a9..a94758b4273 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
         .name           = "at91_tick",
         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91sam926x_pit_interrupt
+        .handler        = at91sam926x_pit_interrupt,
+        .irq            = AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +153,51 @@ static void at91sam926x_pit_reset(void)
         pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pit_timer_ids[] = {
+        { .compatible = "atmel,at91sam9260-pit" },
+        { /* sentinel */ }
+};
+
+static int __init of_at91sam926x_pit_init(void)
+{
+        struct device_node      *np;
+        int                     ret;
+
+        np = of_find_matching_node(NULL, pit_timer_ids);
+        if (!np)
+                goto err;
+
+        pit_base_addr = of_iomap(np, 0);
+        if (!pit_base_addr)
+                goto node_err;
+
+        /* Get the interrupts property */
+        ret = irq_of_parse_and_map(np, 0);
+        if (!ret) {
+                pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+                goto ioremap_err;
+        }
+        at91sam926x_pit_irq.irq = ret;
+
+        of_node_put(np);
+
+        return 0;
+
+ioremap_err:
+        iounmap(pit_base_addr);
+node_err:
+        of_node_put(np);
+err:
+        return -EINVAL;
+}
+#else
+static int __init of_at91sam926x_pit_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -156,6 +205,10 @@ static void __init at91sam926x_pit_init(void)
 {
         unsigned long   pit_rate;
         unsigned        bits;
+        int             ret;
+
+        /* For device tree enabled device: initialize here */
+        of_at91sam926x_pit_init();
 
         /*
          * Use our actual MCK to figure out how many MCK/16 ticks per
@@ -177,7 +230,9 @@ static void __init at91sam926x_pit_init(void)
         clocksource_register_hz(&pit_clk, pit_rate);
 
         /* Set up irq handler */
-        setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+        ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
+        if (ret)
+                pr_crit("AT91: PIT: Unable to setup IRQ\n");
 
         /* Set up and register clockevents */
         pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +248,15 @@ static void at91sam926x_pit_suspend(void)
 
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np =
+                of_find_matching_node(NULL, pit_timer_ids);
+
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
         pit_base_addr = ioremap(addr, 16);
 
         if (!pit_base_addr)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 518e4237717..7af2e108b8a 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -15,16 +15,17 @@
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                         .arm
 
                         .globl  at91sam9_alt_restart
 
-at91sam9_alt_restart:   ldr     r0, .at91_va_base_sdramc        @ preload constants
-                        ldr     r1, =at91_rstc_base
-                        ldr     r1, [r1]
+at91sam9_alt_restart:   ldr     r0, =at91_ramc_base             @ preload constants
+                        ldr     r0, [r0]
+                        ldr     r4, =at91_rstc_base
+                        ldr     r1, [r4]
 
                         mov     r2, #1
                         mov     r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -37,6 +38,3 @@ at91sam9_alt_restart:	ldr	r0, .at91_va_base_sdramc	@ preload constants
                         str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                         b       .
-
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 47e8fdbed9c..d222f8333da 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -230,6 +230,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
         CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
         CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
         CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -332,12 +337,16 @@ static void __init at91sam9g45_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
+        at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
         at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
 }
 
 static void __init at91sam9g45_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9g45_restart;
         at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
 
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 96e2adcd5a8..4320b209678 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -14,6 +14,7 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
+#include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 #include <linux/atmel-mci.h>
@@ -24,11 +25,15 @@
 #include <mach/board.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 #include <mach/atmel-mci.h>
 
+#include <media/atmel-isi.h>
+
 #include "generic.h"
+#include "clock.h"
 
 
 /* --------------------------------------------------------------------
@@ -553,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -870,6 +875,96 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 #endif
 
+/* --------------------------------------------------------------------
+ *  Image Sensor Interface
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
+static u64 isi_dmamask = DMA_BIT_MASK(32);
+static struct isi_platform_data isi_data;
+
+struct resource isi_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_ISI,
+                .end    = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_ISI,
+                .end    = AT91SAM9G45_ID_ISI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_isi_device = {
+        .name           = "atmel_isi",
+        .id             = 0,
+        .dev            = {
+                        .dma_mask               = &isi_dmamask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+                        .platform_data          = &isi_data,
+        },
+        .resource       = isi_resources,
+        .num_resources  = ARRAY_SIZE(isi_resources),
+};
+
+static struct clk_lookup isi_mck_lookups[] = {
+        CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
+};
+
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck)
+{
+        struct clk *pck;
+        struct clk *parent;
+
+        if (!data)
+                return;
+        isi_data = *data;
+
+        at91_set_A_periph(AT91_PIN_PB20, 0);    /* ISI_D0 */
+        at91_set_A_periph(AT91_PIN_PB21, 0);    /* ISI_D1 */
+        at91_set_A_periph(AT91_PIN_PB22, 0);    /* ISI_D2 */
+        at91_set_A_periph(AT91_PIN_PB23, 0);    /* ISI_D3 */
+        at91_set_A_periph(AT91_PIN_PB24, 0);    /* ISI_D4 */
+        at91_set_A_periph(AT91_PIN_PB25, 0);    /* ISI_D5 */
+        at91_set_A_periph(AT91_PIN_PB26, 0);    /* ISI_D6 */
+        at91_set_A_periph(AT91_PIN_PB27, 0);    /* ISI_D7 */
+        at91_set_A_periph(AT91_PIN_PB28, 0);    /* ISI_PCK */
+        at91_set_A_periph(AT91_PIN_PB30, 0);    /* ISI_HSYNC */
+        at91_set_A_periph(AT91_PIN_PB29, 0);    /* ISI_VSYNC */
+        at91_set_B_periph(AT91_PIN_PB8, 0);     /* ISI_PD8 */
+        at91_set_B_periph(AT91_PIN_PB9, 0);     /* ISI_PD9 */
+        at91_set_B_periph(AT91_PIN_PB10, 0);    /* ISI_PD10 */
+        at91_set_B_periph(AT91_PIN_PB11, 0);    /* ISI_PD11 */
+
+        platform_device_register(&at91sam9g45_isi_device);
+
+        if (use_pck_as_mck) {
+                at91_set_B_periph(AT91_PIN_PB31, 0);    /* ISI_MCK (PCK1) */
+
+                pck = clk_get(NULL, "pck1");
+                parent = clk_get(NULL, "plla");
+
+                BUG_ON(IS_ERR(pck) || IS_ERR(parent));
+
+                if (clk_set_parent(pck, parent)) {
+                        pr_err("Failed to set PCK's parent\n");
+                } else {
+                        /* Register PCK as ISI_MCK */
+                        isi_mck_lookups[0].clk = pck;
+                        clkdev_add_table(isi_mck_lookups,
+                                        ARRAY_SIZE(isi_mck_lookups));
+                }
+
+                clk_put(pck);
+                clk_put(parent);
+        }
+}
+#else
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck) {}
+#endif
+
 
 /* --------------------------------------------------------------------
  *  LCD Controller
@@ -957,7 +1052,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 static struct resource tcb0_resources[] = {
         [0] = {
                 .start  = AT91SAM9G45_BASE_TCB0,
-                .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
+                .end    = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -978,7 +1073,7 @@ static struct platform_device at91sam9g45_tcb0_device = {
 static struct resource tcb1_resources[] = {
         [0] = {
                 .start  = AT91SAM9G45_BASE_TCB1,
-                .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
+                .end    = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -995,8 +1090,25 @@ static struct platform_device at91sam9g45_tcb1_device = {
         .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
+
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
+
         platform_device_register(&at91sam9g45_tcb0_device);
         platform_device_register(&at91sam9g45_tcb1_device);
 }
@@ -1099,6 +1211,8 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9G45_BASE_RTT,
                 .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -1106,11 +1220,32 @@ static struct platform_device at91sam9g45_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9g45_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9g45_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9g45_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9g45_rtt_device);
 }
 
@@ -1565,7 +1700,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 0468be10980..9d457182c86 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                         .arm
@@ -20,9 +20,10 @@
                         .globl  at91sam9g45_restart
 
 at91sam9g45_restart:
-                        ldr     r0, .at91_va_base_sdramc0       @ preload constants
-                        ldr     r1, =at91_rstc_base
-                        ldr     r1, [r1]
+                        ldr     r5, =at91_ramc_base             @ preload constants
+                        ldr     r0, [r5]
+                        ldr     r4, =at91_rstc_base
+                        ldr     r1, [r4]
 
                         mov     r2, #1
                         mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
@@ -35,6 +36,3 @@ at91sam9g45_restart:
                         str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                         b       .
-
-.at91_va_base_sdramc0:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 7ae499359d3..d9f2774f385 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -11,6 +11,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -288,12 +289,15 @@ static void __init at91sam9rl_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
 }
 
 static void __init at91sam9rl_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9be71c11d0f..eda72e83037 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,6 +20,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91sam9rl_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 
@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -682,6 +683,8 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9RL_BASE_RTT,
                 .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -689,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9rl_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9rl_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9rl_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9rl_rtt_device);
 }
 
@@ -1128,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
new file mode 100644
index 00000000000..b6831eeb7b7
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -0,0 +1,359 @@
+/*
+ *  Chip-specific setup code for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2010-2012 Atmel Corporation.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at91sam9x5.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+#include <mach/board.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioAB_clk = {
+        .name           = "pioAB_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_PIOAB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioCD_clk = {
+        .name           = "pioCD_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_PIOCD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk smd_clk = {
+        .name           = "smd_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SMD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* USART3 clock - Only for sam9g25/sam9x25 */
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi2_clk = {
+        .name           = "twi2_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc0_clk = {
+        .name           = "mci0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_MCI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart0_clk = {
+        .name           = "uart0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart1_clk = {
+        .name           = "uart1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb0_clk = {
+        .name           = "tcb0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TCB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_PWM,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_ADC,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma0_clk = {
+        .name           = "dma0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_DMA0,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma1_clk = {
+        .name           = "dma1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_DMA1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+        .name           = "uhphs",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UHPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+        .name           = "udphs_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UDPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
+static struct clk macb0_clk = {
+        .name           = "pclk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* isi clock - Only for sam9g25 */
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+        .name           = "mci1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_MCI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac1 clock - Only for sam9x25 */
+static struct clk macb1_clk = {
+        .name           = "pclk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc_clk = {
+        .name           = "ssc_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SSC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* can0 clock - Only for sam9x35 */
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* can1 clock - Only for sam9x35 */
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioAB_clk,
+        &pioCD_clk,
+        &smd_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &twi2_clk,
+        &mmc0_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &tcb0_clk,
+        &pwm_clk,
+        &adc_clk,
+        &dma0_clk,
+        &dma1_clk,
+        &uhphs_clk,
+        &udphs_clk,
+        &mmc1_clk,
+        &ssc_clk,
+        // irq0
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
+        CLKDEV_CON_ID("pioA", &pioAB_clk),
+        CLKDEV_CON_ID("pioB", &pioAB_clk),
+        CLKDEV_CON_ID("pioC", &pioCD_clk),
+        CLKDEV_CON_ID("pioD", &pioCD_clk),
+        /* additional fake clock for macb_hclk */
+        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+};
+
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static void __init at91sam9x5_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+
+        if (cpu_is_at91sam9g25()
+        || cpu_is_at91sam9x25())
+                clk_register(&usart3_clk);
+
+        if (cpu_is_at91sam9g25()
+        || cpu_is_at91sam9x25()
+        || cpu_is_at91sam9g35()
+        || cpu_is_at91sam9x35())
+                clk_register(&macb0_clk);
+
+        if (cpu_is_at91sam9g15()
+        || cpu_is_at91sam9g35()
+        || cpu_is_at91sam9x35())
+                clk_register(&lcdc_clk);
+
+        if (cpu_is_at91sam9g25())
+                clk_register(&isi_clk);
+
+        if (cpu_is_at91sam9x25())
+                clk_register(&macb1_clk);
+
+        if (cpu_is_at91sam9x25()
+        || cpu_is_at91sam9x35()) {
+                clk_register(&can0_clk);
+                clk_register(&can1_clk);
+        }
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init at91sam9x5_map_io(void)
+{
+        at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
+}
+
+void __init at91sam9x5_initialize(void)
+{
+        at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
+
+        /* Register GPIO subsystem (using DT) */
+        at91_gpio_init(NULL, 0);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller (FIQ) */
+        7,      /* System Peripherals */
+        1,      /* Parallel IO Controller A and B */
+        1,      /* Parallel IO Controller C and D */
+        4,      /* Soft Modem */
+        5,      /* USART 0 */
+        5,      /* USART 1 */
+        5,      /* USART 2 */
+        5,      /* USART 3 */
+        6,      /* Two-Wire Interface 0 */
+        6,      /* Two-Wire Interface 1 */
+        6,      /* Two-Wire Interface 2 */
+        0,      /* Multimedia Card Interface 0 */
+        5,      /* Serial Peripheral Interface 0 */
+        5,      /* Serial Peripheral Interface 1 */
+        5,      /* UART 0 */
+        5,      /* UART 1 */
+        0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+        0,      /* Pulse Width Modulation Controller */
+        0,      /* ADC Controller */
+        0,      /* DMA Controller 0 */
+        0,      /* DMA Controller 1 */
+        2,      /* USB Host High Speed port */
+        2,      /* USB Device High speed port */
+        3,      /* Ethernet MAC 0 */
+        3,      /* LDC Controller or Image Sensor Interface */
+        0,      /* Multimedia Card Interface 1 */
+        3,      /* Ethernet MAC 1 */
+        4,      /* Synchronous Serial Interface */
+        4,      /* CAN Controller 0 */
+        4,      /* CAN Controller 1 */
+        0,      /* Advanced Interrupt Controller (IRQ0) */
+};
+
+struct at91_init_soc __initdata at91sam9x5_soc = {
+        .map_io = at91sam9x5_map_io,
+        .default_irq_priority = at91sam9x5_default_irq_priority,
+        .register_clocks = at91sam9x5_register_clocks,
+        .init = at91sam9x5_initialize,
+};
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 56ba3bd035a..5400a1d6503 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <asm/proc-fns.h>
 #include <asm/mach/arch.h>
 #include <mach/at91x40.h>
 #include <mach/at91_st.h>
@@ -37,8 +38,19 @@ unsigned long clk_get_rate(struct clk *clk)
         return AT91X40_MASTER_CLOCK;
 }
 
+static void at91x40_idle(void)
+{
+        /*
+         * Disable the processor clock.  The processor will be automatically
+         * re-enabled by an interrupt or by a reset.
+         */
+        __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
+        cpu_do_idle();
+}
+
 void __init at91x40_initialize(unsigned long main_clock)
 {
+        arm_pm_idle = at91x40_idle;
         at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
                         | (1 << AT91X40_ID_IRQ2);
 }
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index dfff2895f4b..6ca680a1d5d 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -28,6 +28,12 @@
 #include <asm/mach/time.h>
 #include <mach/at91_tc.h>
 
+#define at91_tc_read(field) \
+        __raw_readl(AT91_TC + field)
+
+#define at91_tc_write(field, value) \
+        __raw_writel(value, AT91_TC + field);
+
 /*
  *      3 counter/timer units present.
  */
@@ -37,12 +43,12 @@
 
 static unsigned long at91x40_gettimeoffset(void)
 {
-        return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
+        return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
 }
 
 static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
 {
-        at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
+        at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
         timer_tick();
         return IRQ_HANDLED;
 }
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
 {
         unsigned int v;
 
-        at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
-        v = at91_sys_read(AT91_TC + AT91_TC_BMR);
+        at91_tc_write(AT91_TC_BCR, 0);
+        v = at91_tc_read(AT91_TC_BMR);
         v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
-        at91_sys_write(AT91_TC + AT91_TC_BMR, v);
+        at91_tc_write(AT91_TC_BMR, v);
 
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
 
         setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
 
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
 }
 
 struct sys_timer at91x40_timer = {
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 3bb40694b02..161efbaa102 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -138,6 +138,7 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .bus_width_16   = 0,
+        .ecc_mode       = NAND_ECC_SOFT,
         .parts          = afeb9260_nand_partition,
         .num_parts      = ARRAY_SIZE(afeb9260_nand_partition),
         .det_pin        = -EINVAL,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 8510e9e5498..c6d44ee0c77 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -140,6 +140,7 @@ static struct atmel_nand_data __initdata cam60_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PA9,
         .enable_pin     = AT91_PIN_PA7,
+        .ecc_mode       = NAND_ECC_SOFT,
         .parts          = cam60_nand_partition,
         .num_parts      = ARRAY_SIZE(cam60_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
deleted file mode 100644
index ac3de4f7c31..00000000000
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-cap9adk.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/fb.h>
-#include <linux/mtd/physmap.h>
-
-#include <video/atmel_lcdc.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/board.h>
-#include <mach/at91cap9_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init cap9adk_init_early(void)
-{
-        /* Initialize processor: 12 MHz crystal */
-        at91_initialize(12000000);
-
-        /* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
-        at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
-        /* ... POWER LED always on */
-        at91_set_gpio_output(AT91_PIN_PC29, 1);
-
-        /* Setup the serial ports and console */
-        at91_register_uart(0, 0, 0);            /* DBGU = ttyS0 */
-        at91_set_serial_console(0);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata cap9adk_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB HS Device port
- */
-static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
-        .vbus_pin       = AT91_PIN_PB31,
-};
-
-/*
- * ADS7846 Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PC4);      /* Touchscreen PENIRQ */
-}
-
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-        .x_plate_ohms           = 450,
-        .y_plate_ohms           = 250,
-        .pressure_max           = 15000,
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
-
-static void __init cap9adk_add_device_ts(void)
-{
-        at91_set_gpio_input(AT91_PIN_PC4, 1);   /* Touchscreen PENIRQ */
-        at91_set_gpio_input(AT91_PIN_PC5, 1);   /* Touchscreen BUSY */
-}
-#else
-static void __init cap9adk_add_device_ts(void) {}
-#endif
-
-
-/*
- * SPI devices.
- */
-static struct spi_board_info cap9adk_spi_devices[] = {
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {
-                .modalias       = "ads7846",
-                .chip_select    = 3,            /* can be 2 or 3, depending on J2 jumper */
-                .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
-                .bus_num        = 0,
-                .platform_data  = &ads_info,
-                .irq            = AT91_PIN_PC4,
-        },
-#endif
-};
-
-
-/*
- * MCI (SD/MMC)
- */
-static struct at91_mmc_data __initdata cap9adk_mmc_data = {
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata cap9adk_macb_data = {
-        .phy_irq_pin    = -EINVAL,
-        .is_rmii        = 1,
-};
-
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
-        {
-                .name   = "NAND partition",
-                .offset = 0,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct atmel_nand_data __initdata cap9adk_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = -EINVAL,
-        .enable_pin     = AT91_PIN_PD15,
-        .parts          = cap9adk_nand_partitions,
-        .num_parts      = ARRAY_SIZE(cap9adk_nand_partitions),
-};
-
-static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
-        .ncs_read_setup         = 1,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 1,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 6,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 6,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 8,
-        .write_cycle            = 8,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 1,
-};
-
-static void __init cap9adk_add_device_nand(void)
-{
-        unsigned long csa;
-
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
-
-        cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (cap9adk_nand_data.bus_width_16)
-                cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
-
-        at91_add_device_nand(&cap9adk_nand_data);
-}
-
-
-/*
- * NOR flash
- */
-static struct mtd_partition cap9adk_nor_partitions[] = {
-        {
-                .name           = "NOR partition",
-                .offset         = 0,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct physmap_flash_data cap9adk_nor_data = {
-        .width          = 2,
-        .parts          = cap9adk_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(cap9adk_nor_partitions),
-};
-
-#define NOR_BASE        AT91_CHIPSELECT_0
-#define NOR_SIZE        SZ_8M
-
-static struct resource nor_flash_resources[] = {
-        {
-                .start  = NOR_BASE,
-                .end    = NOR_BASE + NOR_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device cap9adk_nor_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &cap9adk_nor_data,
-        },
-        .resource       = nor_flash_resources,
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-};
-
-static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
-        .ncs_read_setup         = 2,
-        .nrd_setup              = 4,
-        .ncs_write_setup        = 2,
-        .nwe_setup              = 4,
-
-        .ncs_read_pulse         = 10,
-        .nrd_pulse              = 8,
-        .ncs_write_pulse        = 10,
-        .nwe_pulse              = 8,
-
-        .read_cycle             = 16,
-        .write_cycle            = 16,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
-        .tdf_cycles             = 1,
-};
-
-static __init void cap9adk_add_device_nor(void)
-{
-        unsigned long csa;
-
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
-
-        /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
-
-        platform_device_register(&cap9adk_nor_flash);
-}
-
-
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "TX09D50VM1CCA @ 60",
-                .refresh        = 60,
-                .xres           = 240,          .yres           = 320,
-                .pixclock       = KHZ2PICOS(4965),
-
-                .left_margin    = 1,            .right_margin   = 33,
-                .upper_margin   = 1,            .lower_margin   = 0,
-                .hsync_len      = 5,            .vsync_len      = 1,
-
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-
-static struct fb_monspecs at91fb_default_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "TX09D70VM1CCA",
-
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-
-#define AT91CAP9_DEFAULT_LCDCON2        (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT    \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-
-static void at91_lcdc_power_control(int on)
-{
-        if (on)
-                at91_set_gpio_value(AT91_PIN_PC0, 0);   /* power up */
-        else
-                at91_set_gpio_value(AT91_PIN_PC0, 1);   /* power down */
-}
-
-/* Driver datas */
-static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
-        .default_bpp                    = 16,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91CAP9_DEFAULT_LCDCON2,
-        .default_monspecs               = &at91fb_default_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_power_control,
-        .guard_time                     = 1,
-};
-
-#else
-static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
-#endif
-
-
-/*
- * AC97
- */
-static struct ac97c_platform_data cap9adk_ac97_data = {
-        .reset_pin      = -EINVAL,
-};
-
-
-static void __init cap9adk_board_init(void)
-{
-        /* Serial */
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&cap9adk_usbh_data);
-        /* USB HS */
-        at91_add_device_usba(&cap9adk_usba_udc_data);
-        /* SPI */
-        at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
-        /* Touchscreen */
-        cap9adk_add_device_ts();
-        /* MMC */
-        at91_add_device_mmc(1, &cap9adk_mmc_data);
-        /* Ethernet */
-        at91_add_device_eth(&cap9adk_macb_data);
-        /* NAND */
-        cap9adk_add_device_nand();
-        /* NOR Flash */
-        cap9adk_add_device_nor();
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* LCD Controller */
-        at91_add_device_lcdc(&cap9adk_lcdc_data);
-        /* AC97 */
-        at91_add_device_ac97(&cap9adk_ac97_data);
-}
-
-MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
-        /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
-        .timer          = &at91sam926x_timer,
-        .map_io         = at91_map_io,
-        .init_early     = cap9adk_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = cap9adk_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 9ab3d1ea326..5f3680e7c88 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,6 +43,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
@@ -116,6 +117,7 @@ static struct atmel_nand_data __initdata cpu9krea_nand_data = {
         .enable_pin     = AT91_PIN_PC14,
         .bus_width_16   = 0,
         .det_pin        = -EINVAL,
+        .ecc_mode       = NAND_ECC_SOFT,
 };
 
 #ifdef CONFIG_MACH_CPU9260
@@ -238,8 +240,8 @@ static __init void cpu9krea_add_device_nor(void)
 {
         unsigned long csa;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
 
         /* configure chip-select 0 (NOR) */
         sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 368e1427ad9..e094cc81fe2 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -38,6 +38,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index bb6b434ec0c..c18d4d30780 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,14 +15,11 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/gpio.h>
-#include <linux/irqdomain.h>
+#include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
-#include <mach/hardware.h>
 #include <mach/board.h>
-#include <mach/system_rev.h>
-#include <mach/at91sam9_smc.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -30,85 +27,30 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include "sam9_smc.h"
 #include "generic.h"
 
 
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.000 MHz crystal */
-        at91_initialize(12000000);
-
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-
-/* det_pin is not connected */
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PC8,
-        .enable_pin     = AT91_PIN_PC14,
-};
-
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 7,
-        .write_cycle            = 7,
+static const struct of_device_id irq_of_match[] __initconst = {
 
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 3,
-};
-
-static void __init ek_add_device_nand(void)
-{
-        ek_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &ek_nand_smc_config);
-
-        at91_add_device_nand(&ek_nand_data);
-}
-
-static const struct of_device_id aic_of_match[] __initconst = {
-        { .compatible = "atmel,at91rm9200-aic", },
-        {},
+        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
+        { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
+        { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
+        { /*sentinel*/ }
 };
 
 static void __init at91_dt_init_irq(void)
 {
-        irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
-        at91_init_irq_default();
+        of_irq_init(irq_of_match);
 }
 
 static void __init at91_dt_device_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-
-        /* NAND */
-        ek_add_device_nand();
 }
 
 static const char *at91_dt_board_compat[] __initdata = {
         "atmel,at91sam9m10g45ek",
+        "atmel,at91sam9x5ek",
         "calao,usb-a9g20",
         NULL
 };
@@ -117,7 +59,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
-        .init_early     = ek_init_early,
+        .init_early     = at91_dt_initialize,
         .init_irq       = at91_dt_init_irq,
         .init_machine   = at91_dt_device_init,
         .dt_compat      = at91_dt_board_compat,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 07ef35b0ec2..f23aabef855 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -26,6 +26,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
         at91_add_device_mmc(0, &eco920_mmc_data);
         platform_device_register(&eco920_flash);
 
-        at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
+        at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
                                 | AT91_SMC_RWSETUP_(1)
                                 | AT91_SMC_DBW_8
                                 | AT91_SMC_WSEN
@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
         at91_set_deglitch(AT91_PIN_PA23, 1);
 
 /* Initialization of the Static Memory Controller for Chip Select 3 */
-        at91_sys_write(AT91_SMC_CSR(3),
+        at91_ramc_write(0, AT91_SMC_CSR(3),
                 AT91_SMC_DBW_16  |      /* 16 bit */
                 AT91_SMC_WSEN    |
                 AT91_SMC_NWS_(5) |      /* wait states */
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index eec02cd57ce..1815152001f 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/mach-at91/board-flexibity.c
  *
- *  Copyright (C) 2010 Flexibity
+ *  Copyright (C) 2010-2011 Flexibity
  *  Copyright (C) 2005 SAN People
  *  Copyright (C) 2006 Atmel
  *
@@ -62,6 +62,13 @@ static struct at91_udc_data __initdata flexibity_udc_data = {
         .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
+/* I2C devices */
+static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("ds1307", 0x68),
+        },
+};
+
 /* SPI devices */
 static struct spi_board_info flexibity_spi_devices[] = {
         {       /* DataFlash chip */
@@ -141,6 +148,9 @@ static void __init flexibity_board_init(void)
         at91_add_device_usbh(&flexibity_usbh_data);
         /* USB Device */
         at91_add_device_udc(&flexibity_udc_data);
+        /* I2C */
+        at91_add_device_i2c(flexibity_i2c_devices,
+                ARRAY_SIZE(flexibity_i2c_devices));
         /* SPI */
         at91_add_device_spi(flexibity_spi_devices,
                 ARRAY_SIZE(flexibity_spi_devices));
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index d75a4a2ad9c..59b92aab9bc 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -38,6 +38,7 @@
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
@@ -107,6 +108,7 @@ static struct atmel_nand_data __initdata kb9202_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC29,
         .enable_pin     = AT91_PIN_PC28,
+        .ecc_mode       = NAND_ECC_SOFT,
         .parts          = kb9202_nand_partition,
         .num_parts      = ARRAY_SIZE(kb9202_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 3f8617c0e04..57d5f6a4726 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -190,6 +190,7 @@ static struct atmel_nand_data __initdata neocore926_nand_data = {
         .rdy_pin                = AT91_PIN_PB19,
         .rdy_pin_active_low     = 1,
         .enable_pin             = AT91_PIN_PD15,
+        .ecc_mode               = NAND_ECC_SOFT,
         .parts                  = neocore926_nand_partition,
         .num_parts              = ARRAY_SIZE(neocore926_nand_partition),
         .det_pin                = -EINVAL,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab024fa11d5..59e35dd1486 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -39,6 +39,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index e029d220cb8..b6ed5ed7081 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -138,6 +138,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 782f37946af..01332aa538b 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
@@ -149,6 +150,8 @@ static struct atmel_nand_data __initdata dk_nand_data = {
         .det_pin        = AT91_PIN_PB1,
         .rdy_pin        = AT91_PIN_PC2,
         .enable_pin     = -EINVAL,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = dk_nand_partition,
         .num_parts      = ARRAY_SIZE(dk_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index ef7c12a9224..11cbaa8946f 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 84bce587735..e8b116b6cba 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -139,6 +139,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
+        .ecc_mode       = NAND_ECC_SOFT,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index be8233bcabd..d5aec55b0eb 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -181,6 +181,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 40895072a1a..c3f99446286 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -187,6 +187,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC15,
         .enable_pin     = AT91_PIN_PC14,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 29f66052fe6..66f0ddf4b2a 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -187,6 +187,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PA22,
         .enable_pin     = AT91_PIN_PD15,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 843d6286c6f..8923ec9f583 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -166,6 +166,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .det_pin        = -EINVAL,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ea0d1b9c2b7..e1bea73e6b3 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -24,11 +24,13 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/leds.h>
-#include <linux/clk.h>
 #include <linux/atmel-mci.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <video/atmel_lcdc.h>
+#include <media/soc_camera.h>
+#include <media/atmel-isi.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -146,6 +148,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC8,
         .enable_pin     = AT91_PIN_PC14,
         .det_pin        = -EINVAL,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
@@ -185,6 +189,71 @@ static void __init ek_add_device_nand(void)
 
 
 /*
+ *  ISI
+ */
+static struct isi_platform_data __initdata isi_data = {
+        .frate                  = ISI_CFG1_FRATE_CAPTURE_ALL,
+        /* to use codec and preview path simultaneously */
+        .full_mode              = 1,
+        .data_width_flags       = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
+        /* ISI_MCK is provided by programmable clock or external clock */
+        .mck_hz                 = 25000000,
+};
+
+
+/*
+ * soc-camera OV2640
+ */
+#if defined(CONFIG_SOC_CAMERA_OV2640) || \
+        defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
+static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
+{
+        /* ISI board for ek using default 8-bits connection */
+        return SOCAM_DATAWIDTH_8;
+}
+
+static int i2c_camera_power(struct device *dev, int on)
+{
+        /* enable or disable the camera */
+        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+        at91_set_gpio_output(AT91_PIN_PD13, !on);
+
+        if (!on)
+                goto out;
+
+        /* If enabled, give a reset impulse */
+        at91_set_gpio_output(AT91_PIN_PD12, 0);
+        msleep(20);
+        at91_set_gpio_output(AT91_PIN_PD12, 1);
+        msleep(100);
+
+out:
+        return 0;
+}
+
+static struct i2c_board_info i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id                 = 0,
+        .board_info             = &i2c_camera,
+        .i2c_adapter_id         = 0,
+        .power                  = i2c_camera_power,
+        .query_bus_param        = isi_camera_query_bus_param,
+};
+
+static struct platform_device isi_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
+};
+#endif
+
+
+/*
  * LCD Controller
  */
 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
@@ -377,7 +446,12 @@ static struct gpio_led ek_pwm_led[] = {
 #endif
 };
 
-
+static struct platform_device *devices[] __initdata = {
+#if defined(CONFIG_SOC_CAMERA_OV2640) || \
+        defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
+        &isi_ov2640,
+#endif
+};
 
 static void __init ek_board_init(void)
 {
@@ -399,6 +473,8 @@ static void __init ek_board_init(void)
         ek_add_device_nand();
         /* I2C */
         at91_add_device_i2c(0, NULL, 0);
+        /* ISI, using programmable clock as ISI_MCK */
+        at91_add_device_isi(&isi_data, true);
         /* LCD Controller */
         at91_add_device_lcdc(&ek_lcdc_data);
         /* Touch Screen */
@@ -410,6 +486,8 @@ static void __init ek_board_init(void)
         /* LEDs */
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
         at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
+        /* Other platform devices */
+        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
 MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index c1366d0032b..b109ce2ba86 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -94,6 +94,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PD17,
         .enable_pin     = AT91_PIN_PB6,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 4770db08e5a..ebc9d01ce74 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -110,6 +110,7 @@ static struct atmel_nand_data __initdata snapper9260_nand_data = {
         .bus_width_16   = 0,
         .enable_pin     = -EINVAL,
         .det_pin        = -EINVAL,
+        .ecc_mode       = NAND_ECC_SOFT,
 };
 
 static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
@@ -145,11 +146,11 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
                 /* Audio codec */
                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
         },
-        {
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_isl1208 = {
                 /* RTC */
                 I2C_BOARD_INFO("isl1208", 0x6f),
-                .irq = gpio_to_irq(AT91_PIN_PA31),
-        },
 };
 
 static void __init snapper9260_add_device_nand(void)
@@ -163,6 +164,10 @@ static void __init snapper9260_board_init(void)
 {
         at91_add_device_i2c(snapper9260_i2c_devices,
                             ARRAY_SIZE(snapper9260_i2c_devices));
+
+        snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
+        i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
+
         at91_add_device_serial();
         at91_add_device_usbh(&snapper9260_usbh_data);
         at91_add_device_udc(&snapper9260_udc_data);
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 72eb3b4d9ab..7640049410a 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -86,6 +86,7 @@ static struct atmel_nand_data __initdata nand_data = {
         .enable_pin     = AT91_PIN_PC14,
         .bus_width_16   = 0,
         .det_pin        = -EINVAL,
+        .ecc_mode       = NAND_ECC_SOFT,
 };
 
 static struct sam9_smc_config __initdata nand_smc_config = {
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 26c36fc2d1e..b7483a3d098 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -198,6 +198,8 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PA22,
         .enable_pin     = AT91_PIN_PD15,
+        .ecc_mode       = NAND_ECC_SOFT,
+        .on_flash_bbt   = 1,
         .parts          = ek_nand_partition,
         .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index bbd553e1cd9..38dd279d30b 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -45,6 +45,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -181,6 +182,7 @@ static struct atmel_nand_data __initdata yl9200_nand_data = {
         .det_pin        = -EINVAL,
         .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
         .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
+        .ecc_mode       = NAND_ECC_SOFT,
         .parts          = yl9200_nand_partition,
         .num_parts      = ARRAY_SIZE(yl9200_nand_partition),
 };
@@ -393,7 +395,7 @@ static void yl9200_init_video(void)
         at91_set_A_periph(AT91_PIN_PC6, 0);
 
         /* Initialization of the Static Memory Controller for Chip Select 2 */
-        at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
+        at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
                         | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
                         | AT91_SMC_TDF_(0x100)                  /* float time */
         );
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 61873f3aa92..a0f4d7424cd 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -23,14 +23,18 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
+#include <asm/proc-fns.h>
+
 #include "clock.h"
 #include "generic.h"
 
+void __iomem *at91_pmc_base;
 
 /*
  * There's a lot more which can be done with clocks, including cpufreq
@@ -47,26 +51,38 @@
 /*
  * Chips have some kind of clocks : group them by functionality
  */
-#define cpu_has_utmi()          (  cpu_is_at91cap9() \
-                                || cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45())
+#define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
 
 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
-                                || cpu_is_at91sam9g45())
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
 
 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
 
 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45()))
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5()))
 
-#define cpu_has_upll()          (cpu_is_at91sam9g45())
+#define cpu_has_upll()          (cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
 
 /* USB host HS & FS */
 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
 
 /* USB device FS only */
 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45()))
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5()))
+
+#define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
+
+#define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
+
+#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -111,11 +127,11 @@ static void pllb_mode(struct clk *clk, int is_on)
                 value = 0;
 
         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
-        at91_sys_write(AT91_CKGR_PLLBR, value);
+        at91_pmc_write(AT91_CKGR_PLLBR, value);
 
         do {
                 cpu_relax();
-        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
+        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 }
 
 static struct clk pllb = {
@@ -130,31 +146,24 @@ static struct clk pllb = {
 static void pmc_sys_mode(struct clk *clk, int is_on)
 {
         if (is_on)
-                at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
         else
-                at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
 }
 
 static void pmc_uckr_mode(struct clk *clk, int is_on)
 {
-        unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
-
-        if (cpu_is_at91sam9g45()) {
-                if (is_on)
-                        uckr |= AT91_PMC_BIASEN;
-                else
-                        uckr &= ~AT91_PMC_BIASEN;
-        }
+        unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
 
         if (is_on) {
                 is_on = AT91_PMC_LOCKU;
-                at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+                at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
         } else
-                at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+                at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 
         do {
                 cpu_relax();
-        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 }
 
 /* USB function clocks (PLLB must be 48 MHz) */
@@ -190,9 +199,9 @@ struct clk mck = {
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
         if (is_on)
-                at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
         else
-                at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
 }
 
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -210,11 +219,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
                                 return &utmi_clk;
                         else if (cpu_has_pllb())
                                 return &pllb;
+                        break;
+                /* alternate PMC: can use master clock */
+                case AT91_PMC_CSS_MASTER:
+                        return &mck;
         }
 
         return NULL;
 }
 
+static int pmc_prescaler_divider(u32 reg)
+{
+        if (cpu_has_alt_prescaler()) {
+                return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
+        } else {
+                return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
+        }
+}
+
 static void __clk_enable(struct clk *clk)
 {
         if (clk->parent)
@@ -316,12 +338,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long   flags;
         unsigned        prescale;
+        unsigned long   prescale_offset, css_mask;
         unsigned long   actual;
 
         if (!clk_is_programmable(clk))
                 return -EINVAL;
         if (clk->users)
                 return -EBUSY;
+
+        if (cpu_has_alt_prescaler()) {
+                prescale_offset = PMC_ALT_PRES_OFFSET;
+                css_mask = AT91_PMC_ALT_PCKR_CSS;
+        } else {
+                prescale_offset = PMC_PRES_OFFSET;
+                css_mask = AT91_PMC_CSS;
+        }
+
         spin_lock_irqsave(&clk_lock, flags);
 
         actual = clk->parent->rate_hz;
@@ -329,10 +361,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
                 if (actual && actual <= rate) {
                         u32     pckr;
 
-                        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
-                        pckr &= AT91_PMC_CSS;   /* clock selection */
-                        pckr |= prescale << 2;
-                        at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+                        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
+                        pckr &= css_mask;       /* keep clock selection */
+                        pckr |= prescale << prescale_offset;
+                        at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
                         clk->rate_hz = actual;
                         break;
                 }
@@ -366,7 +398,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 
         clk->rate_hz = parent->rate_hz;
         clk->parent = parent;
-        at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
+        at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
 
         spin_unlock_irqrestore(&clk_lock, flags);
         return 0;
@@ -378,11 +410,17 @@ static void __init init_programmable_clock(struct clk *clk)
 {
         struct clk      *parent;
         u32             pckr;
+        unsigned int    css_mask;
+
+        if (cpu_has_alt_prescaler())
+                css_mask = AT91_PMC_ALT_PCKR_CSS;
+        else
+                css_mask = AT91_PMC_CSS;
 
-        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
-        parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
+        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
+        parent = at91_css_to_clk(pckr & css_mask);
         clk->parent = parent;
-        clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
+        clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
 }
 
 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -396,19 +434,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
         u32             scsr, pcsr, uckr = 0, sr;
         struct clk      *clk;
 
-        seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
-        seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
-        seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
-        seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
-        seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
+        scsr = at91_pmc_read(AT91_PMC_SCSR);
+        pcsr = at91_pmc_read(AT91_PMC_PCSR);
+        sr = at91_pmc_read(AT91_PMC_SR);
+        seq_printf(s, "SCSR = %8x\n", scsr);
+        seq_printf(s, "PCSR = %8x\n", pcsr);
+        seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
+        seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
+        seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
         if (cpu_has_pllb())
-                seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
-        if (cpu_has_utmi())
-                seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
-        seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
+                seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
+        if (cpu_has_utmi()) {
+                uckr = at91_pmc_read(AT91_CKGR_UCKR);
+                seq_printf(s, "UCKR = %8x\n", uckr);
+        }
+        seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
         if (cpu_has_upll())
-                seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
-        seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
+                seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
+        seq_printf(s, "SR   = %8x\n", sr);
 
         seq_printf(s, "\n");
 
@@ -596,16 +639,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
         if (cpu_is_at91rm9200()) {
                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
-                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+                at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
                    cpu_is_at91sam9g10()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-        } else if (cpu_is_at91cap9()) {
-                uhpck.pmc_mask = AT91CAP9_PMC_UHP;
         }
-        at91_sys_write(AT91_CKGR_PLLBR, 0);
+        at91_pmc_write(AT91_CKGR_PLLBR, 0);
 
         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -622,16 +663,16 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
         /* Setup divider by 10 to reach 48 MHz */
         usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 
-        at91_sys_write(AT91_PMC_USB, usbr);
+        at91_pmc_write(AT91_PMC_USB, usbr);
 
         /* Now set uhpck values */
         uhpck.parent = &utmi_clk;
         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
         uhpck.rate_hz = utmi_clk.rate_hz;
-        uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+        uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 
-int __init at91_clock_init(unsigned long main_clock)
+static int __init at91_pmc_init(unsigned long main_clock)
 {
         unsigned tmp, freq, mckr;
         int i;
@@ -645,14 +686,14 @@ int __init at91_clock_init(unsigned long main_clock)
          */
         if (!main_clock) {
                 do {
-                        tmp = at91_sys_read(AT91_CKGR_MCFR);
+                        tmp = at91_pmc_read(AT91_CKGR_MCFR);
                 } while (!(tmp & AT91_PMC_MAINRDY));
                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
         }
         main_clk.rate_hz = main_clock;
 
         /* report if PLLA is more than mildly overclocked */
-        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
         if (cpu_has_300M_plla()) {
                 if (plla.rate_hz > 300000000)
                         pll_overclock = true;
@@ -666,8 +707,8 @@ int __init at91_clock_init(unsigned long main_clock)
         if (pll_overclock)
                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
-        if (cpu_is_at91sam9g45()) {
-                mckr = at91_sys_read(AT91_PMC_MCKR);
+        if (cpu_has_plladiv2()) {
+                mckr = at91_pmc_read(AT91_PMC_MCKR);
                 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
         }
 
@@ -688,6 +729,10 @@ int __init at91_clock_init(unsigned long main_clock)
                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                  */
                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+
+                /* UTMI bias and PLL are managed at the same time */
+                if (cpu_has_upll())
+                        utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
         }
 
         /*
@@ -703,10 +748,10 @@ int __init at91_clock_init(unsigned long main_clock)
          * MCK and CPU derive from one of those primary clocks.
          * For now, assume this parentage won't change.
          */
-        mckr = at91_sys_read(AT91_PMC_MCKR);
+        mckr = at91_pmc_read(AT91_PMC_MCKR);
         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
         freq = mck.parent->rate_hz;
-        freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
+        freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
         if (cpu_is_at91rm9200()) {
                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
         } else if (cpu_is_at91sam9g20()) {
@@ -714,13 +759,19 @@ int __init at91_clock_init(unsigned long main_clock)
                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
                 if (mckr & AT91_PMC_PDIV)
                         freq /= 2;              /* processor clock division */
-        } else if (cpu_is_at91sam9g45()) {
+        } else if (cpu_has_mdiv3()) {
                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
         } else {
                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
         }
 
+        if (cpu_has_alt_prescaler()) {
+                /* Programmable clocks can use MCK */
+                mck.type |= CLK_TYPE_PRIMARY;
+                mck.id = 4;
+        }
+
         /* Register the PMC's standard clocks */
         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
                 at91_clk_add(standard_pmc_clocks[i]);
@@ -748,6 +799,55 @@ int __init at91_clock_init(unsigned long main_clock)
         return 0;
 }
 
+#if defined(CONFIG_OF)
+static struct of_device_id pmc_ids[] = {
+        { .compatible = "atmel,at91rm9200-pmc" },
+        { /*sentinel*/ }
+};
+
+static struct of_device_id osc_ids[] = {
+        { .compatible = "atmel,osc" },
+        { /*sentinel*/ }
+};
+
+int __init at91_dt_clock_init(void)
+{
+        struct device_node *np;
+        u32 main_clock = 0;
+
+        np = of_find_matching_node(NULL, pmc_ids);
+        if (!np)
+                panic("unable to find compatible pmc node in dtb\n");
+
+        at91_pmc_base = of_iomap(np, 0);
+        if (!at91_pmc_base)
+                panic("unable to map pmc cpu registers\n");
+
+        of_node_put(np);
+
+        /* retrieve the freqency of fixed clocks from device tree */
+        np = of_find_matching_node(NULL, osc_ids);
+        if (np) {
+                u32 rate;
+                if (!of_property_read_u32(np, "clock-frequency", &rate))
+                        main_clock = rate;
+        }
+
+        of_node_put(np);
+
+        return at91_pmc_init(main_clock);
+}
+#endif
+
+int __init at91_clock_init(unsigned long main_clock)
+{
+        at91_pmc_base = ioremap(AT91_PMC, 256);
+        if (!at91_pmc_base)
+                panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
+        return at91_pmc_init(main_clock);
+}
+
 /*
  * Several unused clocks may be active.  Turn them off.
  */
@@ -770,9 +870,15 @@ static int __init at91_clock_reset(void)
                 pr_debug("Clocks: disable unused %s\n", clk->name);
         }
 
-        at91_sys_write(AT91_PMC_PCDR, pcdr);
-        at91_sys_write(AT91_PMC_SCDR, scdr);
+        at91_pmc_write(AT91_PMC_PCDR, pcdr);
+        at91_pmc_write(AT91_PMC_SCDR, scdr);
 
         return 0;
 }
 late_initcall(at91_clock_reset);
+
+void at91sam9_idle(void)
+{
+        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+        cpu_do_idle();
+}
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index a851e6c9842..555d956b3a5 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -39,20 +39,15 @@ static int at91_enter_idle(struct cpuidle_device *dev,
 {
         struct timeval before, after;
         int idle_time;
-        u32 saved_lpr;
 
         local_irq_disable();
         do_gettimeofday(&before);
         if (index == 0)
                 /* Wait for interrupt state */
                 cpu_do_idle();
-        else if (index == 1) {
-                asm("b 1f; .align 5; 1:");
-                asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
-                saved_lpr = sdram_selfrefresh_enable();
-                cpu_do_idle();
-                sdram_selfrefresh_disable(saved_lpr);
-        }
+        else if (index == 1)
+                at91_standby();
+
         do_gettimeofday(&after);
         local_irq_enable();
         idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 594133451c0..dd9b346c451 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -9,6 +9,7 @@
  */
 
 #include <linux/clkdev.h>
+#include <linux/of.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -19,15 +20,20 @@ extern void __init at91_init_sram(int bank, unsigned long base,
 extern void __init at91rm9200_set_type(int type);
 extern void __init at91_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
+extern void __init at91_dt_initialize(void);
 
  /* Interrupts */
 extern void __init at91_init_irq_default(void);
 extern void __init at91_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
+extern int  __init at91_aic_of_init(struct device_node *node,
+                                    struct device_node *parent);
+
 
  /* Timer */
 struct sys_timer;
+extern void at91rm9200_ioremap_st(u32 addr);
 extern struct sys_timer at91rm9200_timer;
 extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
@@ -45,9 +51,9 @@ extern void __init at91sam9261_set_console_clock(int id);
 extern void __init at91sam9263_set_console_clock(int id);
 extern void __init at91sam9rl_set_console_clock(int id);
 extern void __init at91sam9g45_set_console_clock(int id);
-extern void __init at91cap9_set_console_clock(int id);
 #ifdef CONFIG_AT91_PMC_UNIT
 extern int __init at91_clock_init(unsigned long main_clock);
+extern int __init at91_dt_clock_init(void);
 #else
 static int inline at91_clock_init(unsigned long main_clock) { return 0; }
 #endif
@@ -57,6 +63,9 @@ struct device;
 extern void at91_irq_suspend(void);
 extern void at91_irq_resume(void);
 
+/* idle */
+extern void at91sam9_idle(void);
+
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
 extern void at91sam9_alt_restart(char, const char *);
@@ -65,6 +74,12 @@ extern void at91sam9g45_restart(char, const char *);
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
 
+/* Matrix */
+extern void at91_ioremap_matrix(u32 base_addr);
+
+/* Ram Controler */
+extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
+
  /* GPIO */
 #define AT91RM9200_PQFP         3       /* AT91RM9200 PQFP package has 3 banks */
 #define AT91RM9200_BGA          4       /* AT91RM9200 BGA package has 4 banks */
@@ -75,5 +90,7 @@ struct at91_gpio_bank {
 };
 extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
 extern void __init at91_gpio_irq_setup(void);
+extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
+                                          struct device_node *parent);
 
 extern int at91_extern_irq;
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 74d6783eeab..325837a264c 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -11,6 +11,7 @@
 
 #include <linux/clk.h>
 #include <linux/errno.h>
+#include <linux/device.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -20,6 +21,10 @@
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
@@ -29,9 +34,12 @@
 struct at91_gpio_chip {
         struct gpio_chip        chip;
         struct at91_gpio_chip   *next;          /* Bank sharing same clock */
-        int                     id;             /* ID of register bank */
-        void __iomem            *regbase;       /* Base of register bank */
+        int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
+        int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
+        int                     pioc_idx;       /* PIO bank index */
+        void __iomem            *regbase;       /* PIO bank virtual address */
         struct clk              *clock;         /* associated clock */
+        struct irq_domain       *domain;        /* associated irq domain */
 };
 
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
@@ -43,8 +51,9 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
                                          unsigned offset, int val);
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                         unsigned offset);
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 
-#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)                        \
+#define AT91_GPIO_CHIP(name, nr_gpio)                                   \
         {                                                               \
                 .chip = {                                               \
                         .label            = name,                       \
@@ -53,20 +62,28 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                         .get              = at91_gpiolib_get,           \
                         .set              = at91_gpiolib_set,           \
                         .dbg_show         = at91_gpiolib_dbg_show,      \
-                        .base             = base_gpio,                  \
+                        .to_irq           = at91_gpiolib_to_irq,        \
                         .ngpio            = nr_gpio,                    \
                 },                                                      \
         }
 
 static struct at91_gpio_chip gpio_chip[] = {
-        AT91_GPIO_CHIP("pioA", 0x00, 32),
-        AT91_GPIO_CHIP("pioB", 0x20, 32),
-        AT91_GPIO_CHIP("pioC", 0x40, 32),
-        AT91_GPIO_CHIP("pioD", 0x60, 32),
-        AT91_GPIO_CHIP("pioE", 0x80, 32),
+        AT91_GPIO_CHIP("pioA", 32),
+        AT91_GPIO_CHIP("pioB", 32),
+        AT91_GPIO_CHIP("pioC", 32),
+        AT91_GPIO_CHIP("pioD", 32),
+        AT91_GPIO_CHIP("pioE", 32),
 };
 
 static int gpio_banks;
+static unsigned long at91_gpio_caps;
+
+/* All PIO controllers support PIO3 features */
+#define AT91_GPIO_CAP_PIO3      (1 <<  0)
+
+#define has_pio3()      (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
+
+/*--------------------------------------------------------------------------*/
 
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
@@ -83,6 +100,25 @@ static inline unsigned pin_to_mask(unsigned pin)
 }
 
 
+static char peripheral_function(void __iomem *pio, unsigned mask)
+{
+        char    ret = 'X';
+        u8      select;
+
+        if (pio) {
+                if (has_pio3()) {
+                        select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
+                        select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
+                        ret = 'A' + select;
+                } else {
+                        ret = __raw_readl(pio + PIO_ABSR) & mask ?
+                                                        'B' : 'A';
+                }
+        }
+
+        return ret;
+}
+
 /*--------------------------------------------------------------------------*/
 
 /* Not all hardware capabilities are exposed through these calls; they
@@ -130,7 +166,14 @@ int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
 
         __raw_writel(mask, pio + PIO_IDR);
         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_ASR);
+        if (has_pio3()) {
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
+                                                        pio + PIO_ABCDSR1);
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                        pio + PIO_ABCDSR2);
+        } else {
+                __raw_writel(mask, pio + PIO_ASR);
+        }
         __raw_writel(mask, pio + PIO_PDR);
         return 0;
 }
@@ -150,7 +193,14 @@ int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
 
         __raw_writel(mask, pio + PIO_IDR);
         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_BSR);
+        if (has_pio3()) {
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+                                                        pio + PIO_ABCDSR1);
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                        pio + PIO_ABCDSR2);
+        } else {
+                __raw_writel(mask, pio + PIO_BSR);
+        }
         __raw_writel(mask, pio + PIO_PDR);
         return 0;
 }
@@ -158,8 +208,50 @@ EXPORT_SYMBOL(at91_set_B_periph);
 
 
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
- * configure it for an input.
+ * mux the pin to the "C" internal peripheral role.
+ */
+int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_C_periph);
+
+
+/*
+ * mux the pin to the "D" internal peripheral role.
+ */
+int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_D_periph);
+
+
+/*
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
+ * or "D" peripheral), and configure it for an input.
  */
 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
 {
@@ -179,8 +271,8 @@ EXPORT_SYMBOL(at91_set_gpio_input);
 
 
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
- * and configure it for an output.
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
+ * or "D" peripheral), and configure it for an output.
  */
 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
 {
@@ -210,12 +302,37 @@ int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
 
         if (!pio)
                 return -EINVAL;
+
+        if (has_pio3() && is_on)
+                __raw_writel(mask, pio + PIO_IFSCDR);
         __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
         return 0;
 }
 EXPORT_SYMBOL(at91_set_deglitch);
 
 /*
+ * enable/disable the debounce filter;
+ */
+int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        if (is_on) {
+                __raw_writel(mask, pio + PIO_IFSCER);
+                __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+                __raw_writel(mask, pio + PIO_IFER);
+        } else {
+                __raw_writel(mask, pio + PIO_IFDR);
+        }
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_debounce);
+
+/*
  * enable/disable the multi-driver; This is only valid for output and
  * allows the output pin to run as an open collector output.
  */
@@ -233,6 +350,41 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 EXPORT_SYMBOL(at91_set_multi_drive);
 
 /*
+ * enable/disable the pull-down.
+ * If pull-up already enabled while calling the function, we disable it.
+ */
+int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        /* Disable pull-up anyway */
+        __raw_writel(mask, pio + PIO_PUDR);
+        __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_pulldown);
+
+/*
+ * disable Schmitt trigger
+ */
+int __init_or_module at91_disable_schmitt_trig(unsigned pin)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+        return 0;
+}
+EXPORT_SYMBOL(at91_disable_schmitt_trig);
+
+/*
  * assuming the pin is muxed as a gpio output, set its value.
  */
 int at91_set_gpio_value(unsigned pin, int value)
@@ -273,9 +425,9 @@ static u32 backups[MAX_GPIO_BANKS];
 
 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
-        unsigned        mask = pin_to_mask(pin);
-        unsigned        bank = pin / 32;
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        unsigned        mask = 1 << d->hwirq;
+        unsigned        bank = at91_gpio->pioc_idx;
 
         if (unlikely(bank >= MAX_GPIO_BANKS))
                 return -EINVAL;
@@ -285,7 +437,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
         else
                 wakeups[bank] &= ~mask;
 
-        irq_set_irq_wake(gpio_chip[bank].id, state);
+        irq_set_irq_wake(at91_gpio->pioc_virq, state);
 
         return 0;
 }
@@ -301,9 +453,10 @@ void at91_gpio_suspend(void)
                 __raw_writel(backups[i], pio + PIO_IDR);
                 __raw_writel(wakeups[i], pio + PIO_IER);
 
-                if (!wakeups[i])
+                if (!wakeups[i]) {
+                        clk_unprepare(gpio_chip[i].clock);
                         clk_disable(gpio_chip[i].clock);
-                else {
+                } else {
 #ifdef CONFIG_PM_DEBUG
                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
 #endif
@@ -318,8 +471,10 @@ void at91_gpio_resume(void)
         for (i = 0; i < gpio_banks; i++) {
                 void __iomem    *pio = gpio_chip[i].regbase;
 
-                if (!wakeups[i])
-                        clk_enable(gpio_chip[i].clock);
+                if (!wakeups[i]) {
+                        if (clk_prepare(gpio_chip[i].clock) == 0)
+                                clk_enable(gpio_chip[i].clock);
+                }
 
                 __raw_writel(wakeups[i], pio + PIO_IDR);
                 __raw_writel(backups[i], pio + PIO_IER);
@@ -335,7 +490,10 @@ void at91_gpio_resume(void)
  * To use any AT91_PIN_* as an externally triggered IRQ, first call
  * at91_set_gpio_input() then maybe enable its glitch filter.
  * Then just request_irq() with the pin ID; it works like any ARM IRQ
- * handler, though it always triggers on rising and falling edges.
+ * handler.
+ * First implementation always triggers on rising and falling edges
+ * whereas the newer PIO3 can be additionally configured to trigger on
+ * level, edge with any polarity.
  *
  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
  * configuring them with at91_set_a_periph() or at91_set_b_periph().
@@ -344,9 +502,9 @@ void at91_gpio_resume(void)
 
 static void gpio_irq_mask(struct irq_data *d)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        void __iomem    *pio = at91_gpio->regbase;
+        unsigned        mask = 1 << d->hwirq;
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IDR);
@@ -354,9 +512,9 @@ static void gpio_irq_mask(struct irq_data *d)
 
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        void __iomem    *pio = at91_gpio->regbase;
+        unsigned        mask = 1 << d->hwirq;
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IER);
@@ -373,23 +531,66 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
         }
 }
 
+/* Alternate irq type for PIO3 support */
+static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
+{
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        void __iomem    *pio = at91_gpio->regbase;
+        unsigned        mask = 1 << d->hwirq;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                __raw_writel(mask, pio + PIO_ESR);
+                __raw_writel(mask, pio + PIO_REHLSR);
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                __raw_writel(mask, pio + PIO_ESR);
+                __raw_writel(mask, pio + PIO_FELLSR);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                __raw_writel(mask, pio + PIO_LSR);
+                __raw_writel(mask, pio + PIO_FELLSR);
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                __raw_writel(mask, pio + PIO_LSR);
+                __raw_writel(mask, pio + PIO_REHLSR);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                /*
+                 * disable additional interrupt modes:
+                 * fall back to default behavior
+                 */
+                __raw_writel(mask, pio + PIO_AIMDR);
+                return 0;
+        case IRQ_TYPE_NONE:
+        default:
+                pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
+                return -EINVAL;
+        }
+
+        /* enable additional interrupt modes */
+        __raw_writel(mask, pio + PIO_AIMER);
+
+        return 0;
+}
+
 static struct irq_chip gpio_irqchip = {
         .name           = "GPIO",
         .irq_disable    = gpio_irq_mask,
         .irq_mask       = gpio_irq_mask,
         .irq_unmask     = gpio_irq_unmask,
-        .irq_set_type   = gpio_irq_type,
+        /* .irq_set_type is set dynamically */
         .irq_set_wake   = gpio_irq_set_wake,
 };
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        unsigned        irq_pin;
         struct irq_data *idata = irq_desc_get_irq_data(desc);
         struct irq_chip *chip = irq_data_get_irq_chip(idata);
         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
         void __iomem    *pio = at91_gpio->regbase;
-        u32             isr;
+        unsigned long   isr;
+        int             n;
 
         /* temporarily mask (level sensitive) parent IRQ */
         chip->irq_ack(idata);
@@ -407,13 +608,10 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         continue;
                 }
 
-                irq_pin = gpio_to_irq(at91_gpio->chip.base);
-
-                while (isr) {
-                        if (isr & 1)
-                                generic_handle_irq(irq_pin);
-                        irq_pin++;
-                        isr >>= 1;
+                n = find_first_bit(&isr, BITS_PER_LONG);
+                while (n < BITS_PER_LONG) {
+                        generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
+                        n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
                 }
         }
         chip->irq_unmask(idata);
@@ -424,6 +622,33 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 #ifdef CONFIG_DEBUG_FS
 
+static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
+{
+        char    *trigger = NULL;
+        char    *polarity = NULL;
+
+        if (__raw_readl(pio + PIO_IMR) & mask) {
+                if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
+                        trigger = "edge";
+                        polarity = "both";
+                } else {
+                        if (__raw_readl(pio + PIO_ELSR) & mask) {
+                                trigger = "level";
+                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                        "high" : "low";
+                        } else {
+                                trigger = "edge";
+                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                                "rising" : "falling";
+                        }
+                }
+                seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
+        } else {
+                seq_printf(s, "GPIO:%s\t\t",
+                                __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+        }
+}
+
 static int at91_gpio_show(struct seq_file *s, void *unused)
 {
         int bank, j;
@@ -431,7 +656,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
         /* print heading */
         seq_printf(s, "Pin\t");
         for (bank = 0; bank < gpio_banks; bank++) {
-                seq_printf(s, "PIO%c\t", 'A' + bank);
+                seq_printf(s, "PIO%c\t\t", 'A' + bank);
         };
         seq_printf(s, "\n\n");
 
@@ -445,11 +670,10 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
                         unsigned        mask = pin_to_mask(pin);
 
                         if (__raw_readl(pio + PIO_PSR) & mask)
-                                seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+                                gpio_printf(s, pio, mask);
                         else
-                                seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
-
-                        seq_printf(s, "\t");
+                                seq_printf(s, "%c\t\t",
+                                                peripheral_function(pio, mask));
                 }
 
                 seq_printf(s, "\n");
@@ -488,46 +712,152 @@ postcore_initcall(at91_gpio_debugfs_init);
  */
 static struct lock_class_key gpio_lock_class;
 
+#if defined(CONFIG_OF)
+static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        struct at91_gpio_chip   *at91_gpio = h->host_data;
+
+        irq_set_lockdep_class(virq, &gpio_lock_class);
+
+        /*
+         * Can use the "simple" and not "edge" handler since it's
+         * shorter, and the AIC handles interrupts sanely.
+         */
+        irq_set_chip_and_handler(virq, &gpio_irqchip,
+                                 handle_simple_irq);
+        set_irq_flags(virq, IRQF_VALID);
+        irq_set_chip_data(virq, at91_gpio);
+
+        return 0;
+}
+
+static struct irq_domain_ops at91_gpio_ops = {
+        .map    = at91_gpio_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                     struct device_node *parent)
+{
+        struct at91_gpio_chip   *prev = NULL;
+        int                     alias_idx = of_alias_get_id(node, "gpio");
+        struct at91_gpio_chip   *at91_gpio = &gpio_chip[alias_idx];
+
+        /* Setup proper .irq_set_type function */
+        if (has_pio3())
+                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+        else
+                gpio_irqchip.irq_set_type = gpio_irq_type;
+
+        /* Disable irqs of this PIO controller */
+        __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
+
+        /* Setup irq domain */
+        at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
+                                                &at91_gpio_ops, at91_gpio);
+        if (!at91_gpio->domain)
+                panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
+                        at91_gpio->pioc_idx);
+
+        /* Setup chained handler */
+        if (at91_gpio->pioc_idx)
+                prev = &gpio_chip[at91_gpio->pioc_idx - 1];
+
+        /* The toplevel handler handles one bank of GPIOs, except
+         * on some SoC it can handles up to three...
+         * We only set up the handler for the first of the list.
+         */
+        if (prev && prev->next == at91_gpio)
+                return 0;
+
+        at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
+                                                        at91_gpio->pioc_hwirq);
+        irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
+        irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
+
+        return 0;
+}
+#else
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                     struct device_node *parent)
+{
+        return -EINVAL;
+}
+#endif
+
+/*
+ * irqdomain initialization: pile up irqdomains on top of AIC range
+ */
+static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
+{
+        int irq_base;
+
+        irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
+        if (irq_base < 0)
+                panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
+                        at91_gpio->pioc_idx, irq_base);
+        at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
+                                                  irq_base, 0,
+                                                  &irq_domain_simple_ops, NULL);
+        if (!at91_gpio->domain)
+                panic("at91_gpio.%d: couldn't allocate irq domain.\n",
+                        at91_gpio->pioc_idx);
+}
+
 /*
  * Called from the processor-specific init to enable GPIO interrupt support.
  */
 void __init at91_gpio_irq_setup(void)
 {
-        unsigned                pioc, irq = gpio_to_irq(0);
+        unsigned                pioc;
+        int                     gpio_irqnbr = 0;
         struct at91_gpio_chip   *this, *prev;
 
+        /* Setup proper .irq_set_type function */
+        if (has_pio3())
+                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+        else
+                gpio_irqchip.irq_set_type = gpio_irq_type;
+
         for (pioc = 0, this = gpio_chip, prev = NULL;
                         pioc++ < gpio_banks;
                         prev = this, this++) {
-                unsigned        id = this->id;
-                unsigned        i;
+                int offset;
 
                 __raw_writel(~0, this->regbase + PIO_IDR);
 
-                for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32;
-                     i++, irq++) {
-                        irq_set_lockdep_class(irq, &gpio_lock_class);
+                /* setup irq domain for this GPIO controller */
+                at91_gpio_irqdomain(this);
+
+                for (offset = 0; offset < this->chip.ngpio; offset++) {
+                        unsigned int virq = irq_find_mapping(this->domain, offset);
+                        irq_set_lockdep_class(virq, &gpio_lock_class);
 
                         /*
                          * Can use the "simple" and not "edge" handler since it's
                          * shorter, and the AIC handles interrupts sanely.
                          */
-                        irq_set_chip_and_handler(irq, &gpio_irqchip,
+                        irq_set_chip_and_handler(virq, &gpio_irqchip,
                                                  handle_simple_irq);
-                        set_irq_flags(irq, IRQF_VALID);
+                        set_irq_flags(virq, IRQF_VALID);
+                        irq_set_chip_data(virq, this);
+
+                        gpio_irqnbr++;
                 }
 
                 /* The toplevel handler handles one bank of GPIOs, except
-                 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
-                 * the list, so we only set up that handler.
+                 * on some SoC it can handles up to three...
+                 * We only set up the handler for the first of the list.
                  */
                 if (prev && prev->next == this)
                         continue;
 
-                irq_set_chip_data(id, this);
-                irq_set_chained_handler(id, gpio_irq_handler);
+                this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
+                irq_set_chip_data(this->pioc_virq, this);
+                irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
         }
-        pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
+        pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
 }
 
 /* gpiolib support */
@@ -593,48 +923,175 @@ static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                                            at91_get_gpio_value(pin) ?
                                            "set" : "clear");
                         else
-                                seq_printf(s, "[periph %s]\n",
-                                           __raw_readl(pio + PIO_ABSR) &
-                                           mask ? "B" : "A");
+                                seq_printf(s, "[periph %c]\n",
+                                           peripheral_function(pio, mask));
                 }
         }
 }
 
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        int virq;
+
+        if (offset < chip->ngpio)
+                virq = irq_create_mapping(at91_gpio->domain, offset);
+        else
+                virq = -ENXIO;
+
+        dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
+                                chip->label, offset + chip->base, virq);
+        return virq;
+}
+
+static int __init at91_gpio_setup_clk(int idx)
+{
+        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+
+        /* retreive PIO controller's clock */
+        at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
+        if (IS_ERR(at91_gpio->clock)) {
+                pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
+                goto err;
+        }
+
+        if (clk_prepare(at91_gpio->clock))
+                goto clk_prep_err;
+
+        /* enable PIO controller's clock */
+        if (clk_enable(at91_gpio->clock)) {
+                pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
+                goto clk_err;
+        }
+
+        return 0;
+
+clk_err:
+        clk_unprepare(at91_gpio->clock);
+clk_prep_err:
+        clk_put(at91_gpio->clock);
+err:
+        return -EINVAL;
+}
+
+#ifdef CONFIG_OF_GPIO
+static void __init of_at91_gpio_init_one(struct device_node *np)
+{
+        int alias_idx;
+        struct at91_gpio_chip *at91_gpio;
+
+        if (!np)
+                return;
+
+        alias_idx = of_alias_get_id(np, "gpio");
+        if (alias_idx >= MAX_GPIO_BANKS) {
+                pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
+                                                alias_idx, MAX_GPIO_BANKS);
+                return;
+        }
+
+        at91_gpio = &gpio_chip[alias_idx];
+        at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
+
+        at91_gpio->regbase = of_iomap(np, 0);
+        if (!at91_gpio->regbase) {
+                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
+                                                                alias_idx);
+                return;
+        }
+
+        /* Get the interrupts property */
+        if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
+                pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
+                                                                alias_idx);
+                goto ioremap_err;
+        }
+
+        /* Get capabilities from compatibility property */
+        if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
+                at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
+
+        /* Setup clock */
+        if (at91_gpio_setup_clk(alias_idx))
+                goto ioremap_err;
+
+        at91_gpio->chip.of_node = np;
+        gpio_banks = max(gpio_banks, alias_idx + 1);
+        at91_gpio->pioc_idx = alias_idx;
+        return;
+
+ioremap_err:
+        iounmap(at91_gpio->regbase);
+}
+
+static int __init of_at91_gpio_init(void)
+{
+        struct device_node *np = NULL;
+
+        /*
+         * This isn't ideal, but it gets things hooked up until this
+         * driver is converted into a platform_device
+         */
+        for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
+                of_at91_gpio_init_one(np);
+
+        return gpio_banks > 0 ? 0 : -EINVAL;
+}
+#else
+static int __init of_at91_gpio_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
+static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
+{
+        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+
+        at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
+        at91_gpio->pioc_hwirq = pioc_hwirq;
+        at91_gpio->pioc_idx = idx;
+
+        at91_gpio->regbase = ioremap(regbase, 512);
+        if (!at91_gpio->regbase) {
+                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
+                return;
+        }
+
+        if (at91_gpio_setup_clk(idx))
+                goto ioremap_err;
+
+        gpio_banks = max(gpio_banks, idx + 1);
+        return;
+
+ioremap_err:
+        iounmap(at91_gpio->regbase);
+}
+
 /*
  * Called from the processor-specific init to enable GPIO pin support.
  */
 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 {
-        unsigned                i;
+        unsigned i;
         struct at91_gpio_chip *at91_gpio, *last = NULL;
 
         BUG_ON(nr_banks > MAX_GPIO_BANKS);
 
-        gpio_banks = nr_banks;
+        if (of_at91_gpio_init() < 0) {
+                /* No GPIO controller found in device tree */
+                for (i = 0; i < nr_banks; i++)
+                        at91_gpio_init_one(i, data[i].regbase, data[i].id);
+        }
 
-        for (i = 0; i < nr_banks; i++) {
+        for (i = 0; i < gpio_banks; i++) {
                 at91_gpio = &gpio_chip[i];
 
-                at91_gpio->id = data[i].id;
-                at91_gpio->chip.base = i * 32;
-
-                at91_gpio->regbase = ioremap(data[i].regbase, 512);
-                if (!at91_gpio->regbase) {
-                        pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
-                        continue;
-                }
-
-                at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
-                if (!at91_gpio->clock) {
-                        pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
-                        continue;
-                }
-
-                /* enable PIO controller's clock */
-                clk_enable(at91_gpio->clock);
-
-                /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
-                if (last && last->id == at91_gpio->id)
+                /*
+                 * GPIO controller are grouped on some SoC:
+                 * PIOC, PIOD and PIOE can share the same IRQ line
+                 */
+                if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
                         last->next = at91_gpio;
                 last = at91_gpio;
 
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644
index 00000000000..02fae9de746
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __MACH_AT91_MATRIX_H__
+#define __MACH_AT91_MATRIX_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_matrix_base;
+
+#define at91_matrix_read(field) \
+        __raw_readl(at91_matrix_base + field)
+
+#define at91_matrix_write(field, value) \
+        __raw_writel(value, at91_matrix_base + field);
+
+#else
+.extern at91_matrix_base
+#endif
+
+#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index c6a31bf8a5c..732b11c37f1 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -40,10 +40,35 @@
 #define PIO_PUER        0x64    /* Pull-up Enable Register */
 #define PIO_PUSR        0x68    /* Pull-up Status Register */
 #define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_ABCDSR1     0x70    /* Peripheral ABCD Select Register 1 [some sam9 only] */
 #define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABCDSR2     0x74    /* Peripheral ABCD Select Register 2 [some sam9 only] */
 #define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_IFSCDR      0x80    /* Input Filter Slow Clock Disable Register */
+#define PIO_IFSCER      0x84    /* Input Filter Slow Clock Enable Register */
+#define PIO_IFSCSR      0x88    /* Input Filter Slow Clock Status Register */
+#define PIO_SCDR        0x8c    /* Slow Clock Divider Debouncing Register */
+#define         PIO_SCDR_DIV    (0x3fff <<  0)          /* Slow Clock Divider Mask */
+#define PIO_PPDDR       0x90    /* Pad Pull-down Disable Register */
+#define PIO_PPDER       0x94    /* Pad Pull-down Enable Register */
+#define PIO_PPDSR       0x98    /* Pad Pull-down Status Register */
 #define PIO_OWER        0xa0    /* Output Write Enable Register */
 #define PIO_OWDR        0xa4    /* Output Write Disable Register */
 #define PIO_OWSR        0xa8    /* Output Write Status Register */
+#define PIO_AIMER       0xb0    /* Additional Interrupt Modes Enable Register */
+#define PIO_AIMDR       0xb4    /* Additional Interrupt Modes Disable Register */
+#define PIO_AIMMR       0xb8    /* Additional Interrupt Modes Mask Register */
+#define PIO_ESR         0xc0    /* Edge Select Register */
+#define PIO_LSR         0xc4    /* Level Select Register */
+#define PIO_ELSR        0xc8    /* Edge/Level Status Register */
+#define PIO_FELLSR      0xd0    /* Falling Edge/Low Level Select Register */
+#define PIO_REHLSR      0xd4    /* Rising Edge/ High Level Select Register */
+#define PIO_FRLHSR      0xd8    /* Fall/Rise - Low/High Status Register */
+#define PIO_SCHMITT     0x100   /* Schmitt Trigger Register */
+
+#define ABCDSR_PERIPH_A 0x0
+#define ABCDSR_PERIPH_B 0x1
+#define ABCDSR_PERIPH_C 0x2
+#define ABCDSR_PERIPH_D 0x3
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index e46f93e34aa..36604782a78 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,17 +16,27 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
-#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
-#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_pmc_base;
 
-#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define at91_pmc_read(field) \
+        __raw_readl(at91_pmc_base + field)
+
+#define at91_pmc_write(field, value) \
+        __raw_writel(value, at91_pmc_base + field)
+#else
+.extern at91_aic_base
+#endif
+
+#define AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
+#define AT91_PMC_SCDR           0x04                    /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR           0x08                    /* System Clock Status Register */
 #define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
 #define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define         AT91CAP9_PMC_DDR        (1 <<  2)               /* DDR Clock [CAP9 revC & some SAM9 only] */
 #define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
-#define         AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
 #define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
 #define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
@@ -36,27 +46,31 @@
 #define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
-#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+#define AT91_PMC_PCER           0x10                    /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR           0x14                    /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR           0x18                    /* Peripheral Clock Status Register */
 
-#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [some SAM9, CAP9] */
+#define AT91_CKGR_UCKR          0x1C                    /* UTMI Clock Register [some SAM9] */
 #define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
 #define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
 #define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
 #define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI BIAS Start-up Time */
 
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
-#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
-#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+#define AT91_CKGR_MOR           0x20                    /* Main Oscillator Register [not on SAM9RL] */
+#define         AT91_PMC_MOSCEN         (1    <<  0)            /* Main Oscillator Enable */
+#define         AT91_PMC_OSCBYPASS      (1    <<  1)            /* Oscillator Bypass */
+#define         AT91_PMC_MOSCRCEN       (1    <<  3)            /* Main On-Chip RC Oscillator Enable [some SAM9] */
+#define         AT91_PMC_OSCOUNT        (0xff <<  8)            /* Main Oscillator Start-up Time */
+#define         AT91_PMC_KEY            (0x37 << 16)            /* MOR Writing Key */
+#define         AT91_PMC_MOSCSEL        (1    << 24)            /* Main Oscillator Selection [some SAM9] */
+#define         AT91_PMC_CFDEN          (1    << 25)            /* Clock Failure Detector Enable [some SAM9] */
 
-#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define AT91_CKGR_MCFR          0x24                    /* Main Clock Frequency Register */
 #define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
 #define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
 
-#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
-#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define AT91_CKGR_PLLAR         0x28                    /* PLL A Register */
+#define AT91_CKGR_PLLBR         0x2c                    /* PLL B Register */
 #define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
@@ -67,27 +81,37 @@
 #define                 AT91_PMC_USBDIV_4               (2 << 28)
 #define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
 
-#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define AT91_PMC_MCKR           0x30                    /* Master Clock Register */
 #define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
 #define                 AT91_PMC_CSS_SLOW               (0 << 0)
 #define                 AT91_PMC_CSS_MAIN               (1 << 0)
 #define                 AT91_PMC_CSS_PLLA               (2 << 0)
 #define                 AT91_PMC_CSS_PLLB               (3 << 0)
 #define                 AT91_PMC_CSS_UPLL               (3 << 0)        /* [some SAM9 only] */
-#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
-#define                 AT91_PMC_PRES_1                 (0 << 2)
-#define                 AT91_PMC_PRES_2                 (1 << 2)
-#define                 AT91_PMC_PRES_4                 (2 << 2)
-#define                 AT91_PMC_PRES_8                 (3 << 2)
-#define                 AT91_PMC_PRES_16                (4 << 2)
-#define                 AT91_PMC_PRES_32                (5 << 2)
-#define                 AT91_PMC_PRES_64                (6 << 2)
+#define         PMC_PRES_OFFSET         2
+#define         AT91_PMC_PRES           (7 <<  PMC_PRES_OFFSET)         /* Master Clock Prescaler */
+#define                 AT91_PMC_PRES_1                 (0 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_2                 (1 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_4                 (2 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_8                 (3 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_16                (4 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_32                (5 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_64                (6 << PMC_PRES_OFFSET)
+#define         PMC_ALT_PRES_OFFSET     4
+#define         AT91_PMC_ALT_PRES       (7 <<  PMC_ALT_PRES_OFFSET)             /* Master Clock Prescaler [alternate location] */
+#define                 AT91_PMC_ALT_PRES_1             (0 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_2             (1 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_4             (2 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_8             (3 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_16            (4 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_32            (5 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_64            (6 << PMC_ALT_PRES_OFFSET)
 #define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
 #define                 AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
 #define                 AT91RM9200_PMC_MDIV_2           (1 << 8)
 #define                 AT91RM9200_PMC_MDIV_3           (2 << 8)
 #define                 AT91RM9200_PMC_MDIV_4           (3 << 8)
-#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
+#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9 only] */
 #define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
 #define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
 #define                 AT91SAM9_PMC_MDIV_6             (3 << 8)        /* [some SAM9 only] */
@@ -99,35 +123,55 @@
 #define                 AT91_PMC_PLLADIV2_OFF           (0 << 12)
 #define                 AT91_PMC_PLLADIV2_ON            (1 << 12)
 
-#define AT91_PMC_USB            (AT91_PMC + 0x38)       /* USB Clock Register [some SAM9 only] */
+#define AT91_PMC_USB            0x38                    /* USB Clock Register [some SAM9 only] */
 #define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
 #define                 AT91_PMC_USBS_PLLA              (0 << 0)
 #define                 AT91_PMC_USBS_UPLL              (1 << 0)
 #define         AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
 
-#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-N Registers */
+#define AT91_PMC_SMD            0x3c                    /* Soft Modem Clock Register [some SAM9 only] */
+#define         AT91_PMC_SMDS           (0x1  <<  0)            /* SMD input clock selection */
+#define         AT91_PMC_SMD_DIV        (0x1f <<  8)            /* SMD input clock divider */
+#define         AT91_PMC_SMDDIV(n)      (((n) <<  8) & AT91_PMC_SMD_DIV)
+
+#define AT91_PMC_PCKR(n)        (0x40 + ((n) * 4))      /* Programmable Clock 0-N Registers */
+#define         AT91_PMC_ALT_PCKR_CSS   (0x7 <<  0)             /* Programmable Clock Source Selection [alternate length] */
+#define                 AT91_PMC_CSS_MASTER             (4 << 0)        /* [some SAM9 only] */
 #define         AT91_PMC_CSSMCK         (0x1 <<  8)             /* CSS or Master Clock Selection */
 #define                 AT91_PMC_CSSMCK_CSS             (0 << 8)
 #define                 AT91_PMC_CSSMCK_MCK             (1 << 8)
 
-#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
-#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
-#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define AT91_PMC_IER            0x60                    /* Interrupt Enable Register */
+#define AT91_PMC_IDR            0x64                    /* Interrupt Disable Register */
+#define AT91_PMC_SR             0x68                    /* Status Register */
 #define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
 #define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
 #define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9, AT91CAP9 only] */
-#define         AT91_PMC_OSCSEL         (1 <<  7)               /* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9] */
 #define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
 #define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
-#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+#define         AT91_PMC_MOSCSELS       (1 << 16)               /* Main Oscillator Selection [some SAM9] */
+#define         AT91_PMC_MOSCRCS        (1 << 17)               /* Main On-Chip RC [some SAM9] */
+#define         AT91_PMC_CFDEV          (1 << 18)               /* Clock Failure Detector Event [some SAM9] */
+#define AT91_PMC_IMR            0x6c                    /* Interrupt Mask Register */
+
+#define AT91_PMC_PROT           0xe4                    /* Write Protect Mode Register [some SAM9] */
+#define         AT91_PMC_WPEN           (0x1  <<  0)            /* Write Protect Enable */
+#define         AT91_PMC_WPKEY          (0xffffff << 8)         /* Write Protect Key */
+#define         AT91_PMC_PROTKEY        (0x504d43 << 8)         /* Activation Code */
 
-#define AT91_PMC_PROT           (AT91_PMC + 0xe4)       /* Protect Register [AT91CAP9 revC only] */
-#define         AT91_PMC_PROTKEY        0x504d4301      /* Activation Code */
+#define AT91_PMC_WPSR           0xe8                    /* Write Protect Status Register [some SAM9] */
+#define         AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
+#define         AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
 
-#define AT91_PMC_VER            (AT91_PMC + 0xfc)       /* PMC Module Version [AT91CAP9 only] */
+#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9] */
+#define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
+#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command */
+#define         AT91_PMC_PCR_DIV        (0x3  <<  16)           /* Divisor Value */
+#define         AT91_PMC_PCRDIV(n)      (((n) <<  16) & AT91_PMC_PCR_DIV)
+#define         AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
new file mode 100644
index 00000000000..d8aeb278614
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -0,0 +1,32 @@
+/*
+ * Header file for the Atmel RAM Controller
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_RAMC_H__
+#define __AT91_RAMC_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_ramc_base[];
+
+#define at91_ramc_read(id, field) \
+        __raw_readl(at91_ramc_base[id] + field)
+
+#define at91_ramc_write(id, field, value) \
+        __raw_writel(value, at91_ramc_base[id] + field)
+#else
+.extern at91_ramc_base
+#endif
+
+#define AT91_MEMCTRL_MC         0
+#define AT91_MEMCTRL_SDRAMC     1
+#define AT91_MEMCTRL_DDRSDR     2
+
+#include <mach/at91rm9200_sdramc.h>
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91sam9_sdramc.h>
+
+#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
index 1d4fe822c77..60478ea8bd4 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -36,9 +36,11 @@ extern void __iomem *at91_shdwc_base;
 #define                 AT91_SHDW_WKMODE0_HIGH          1
 #define                 AT91_SHDW_WKMODE0_LOW           2
 #define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
-#define         AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
+#define         AT91_SHDW_CPTWK0_MAX    0xf                     /* Maximum Counter On Wake Up 0 */
+#define         AT91_SHDW_CPTWK0        (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
 #define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
 #define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
+#define         AT91_SHDW_RTCWKEN       (1   << 17)             /* Real Time Clock Wake-up Enable */
 
 #define AT91_SHDW_SR            0x08                    /* Shut Down Status Register */
 #define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index 8847173e410..969aac27109 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -16,34 +16,46 @@
 #ifndef AT91_ST_H
 #define AT91_ST_H
 
-#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_st_base;
+
+#define at91_st_read(field) \
+        __raw_readl(at91_st_base + field)
+
+#define at91_st_write(field, value) \
+        __raw_writel(value, at91_st_base + field);
+#else
+.extern at91_st_base
+#endif
+
+#define AT91_ST_CR              0x00                    /* Control Register */
 #define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
 
-#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define AT91_ST_PIMR            0x04                    /* Period Interval Mode Register */
 #define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
 
-#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define AT91_ST_WDMR            0x08                    /* Watchdog Mode Register */
 #define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
 #define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
 #define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
 
-#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define AT91_ST_RTMR            0x0c                    /* Real-time Mode Register */
 #define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
 
-#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define AT91_ST_SR              0x10                    /* Status Register */
 #define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
 #define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
 #define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
 #define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
 
-#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
-#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
-#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+#define AT91_ST_IER             0x14                    /* Interrupt Enable Register */
+#define AT91_ST_IDR             0x18                    /* Interrupt Disable Register */
+#define AT91_ST_IMR             0x1c                    /* Interrupt Mask Register */
 
-#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define AT91_ST_RTAR            0x20                    /* Real-time Alarm Register */
 #define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
 
-#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define AT91_ST_CRTR            0x24                    /* Current Real-time Register */
 #define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
deleted file mode 100644
index 61d952902f2..00000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91CAP9_ID_PIOABCD     2       /* Parallel IO Controller A, B, C and D */
-#define AT91CAP9_ID_MPB0        3       /* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1        4       /* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2        5       /* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3        6       /* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4        7       /* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0         8       /* USART 0 */
-#define AT91CAP9_ID_US1         9       /* USART 1 */
-#define AT91CAP9_ID_US2         10      /* USART 2 */
-#define AT91CAP9_ID_MCI0        11      /* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1        12      /* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN         13      /* CAN */
-#define AT91CAP9_ID_TWI         14      /* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0        15      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1        16      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0        17      /* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1        18      /* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C       19      /* AC97 Controller */
-#define AT91CAP9_ID_TCB         20      /* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC        21      /* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC        22      /* Ethernet */
-#define AT91CAP9_ID_AESTDES     23      /* Advanced Encryption Standard, Triple DES */
-#define AT91CAP9_ID_ADC         24      /* Analog-to-Digital Converter */
-#define AT91CAP9_ID_ISI         25      /* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC        26      /* LCD Controller */
-#define AT91CAP9_ID_DMA         27      /* DMA Controller */
-#define AT91CAP9_ID_UDPHS       28      /* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP         29      /* USB Host Port */
-#define AT91CAP9_ID_IRQ0        30      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91CAP9_ID_IRQ1        31      /* Advanced Interrupt Controller (IRQ1) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91CAP9_BASE_UDPHS             0xfff78000
-#define AT91CAP9_BASE_TCB0              0xfff7c000
-#define AT91CAP9_BASE_TC0               0xfff7c000
-#define AT91CAP9_BASE_TC1               0xfff7c040
-#define AT91CAP9_BASE_TC2               0xfff7c080
-#define AT91CAP9_BASE_MCI0              0xfff80000
-#define AT91CAP9_BASE_MCI1              0xfff84000
-#define AT91CAP9_BASE_TWI               0xfff88000
-#define AT91CAP9_BASE_US0               0xfff8c000
-#define AT91CAP9_BASE_US1               0xfff90000
-#define AT91CAP9_BASE_US2               0xfff94000
-#define AT91CAP9_BASE_SSC0              0xfff98000
-#define AT91CAP9_BASE_SSC1              0xfff9c000
-#define AT91CAP9_BASE_AC97C             0xfffa0000
-#define AT91CAP9_BASE_SPI0              0xfffa4000
-#define AT91CAP9_BASE_SPI1              0xfffa8000
-#define AT91CAP9_BASE_CAN               0xfffac000
-#define AT91CAP9_BASE_PWMC              0xfffb8000
-#define AT91CAP9_BASE_EMAC              0xfffbc000
-#define AT91CAP9_BASE_ADC               0xfffc0000
-#define AT91CAP9_BASE_ISI               0xfffc4000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (cpu_is_at91cap9_revB() ?       \
-                        (0xfffffd50 - AT91_BASE_SYS) :  \
-                        (0xfffffd60 - AT91_BASE_SYS))
-
-#define AT91CAP9_BASE_ECC       0xffffe200
-#define AT91CAP9_BASE_DMA       0xffffec00
-#define AT91CAP9_BASE_SMC       0xffffe800
-#define AT91CAP9_BASE_DBGU      AT91_BASE_DBGU1
-#define AT91CAP9_BASE_PIOA      0xfffff200
-#define AT91CAP9_BASE_PIOB      0xfffff400
-#define AT91CAP9_BASE_PIOC      0xfffff600
-#define AT91CAP9_BASE_PIOD      0xfffff800
-#define AT91CAP9_BASE_RSTC      0xfffffd00
-#define AT91CAP9_BASE_SHDWC     0xfffffd10
-#define AT91CAP9_BASE_RTT       0xfffffd20
-#define AT91CAP9_BASE_PIT       0xfffffd30
-#define AT91CAP9_BASE_WDT       0xfffffd40
-
-#define AT91_USART0     AT91CAP9_BASE_US0
-#define AT91_USART1     AT91CAP9_BASE_US1
-#define AT91_USART2     AT91CAP9_BASE_US2
-
-
-/*
- * Internal Memory.
- */
-#define AT91CAP9_SRAM_BASE      0x00100000      /* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE      (32 * SZ_1K)    /* Internal SRAM size (32Kb) */
-
-#define AT91CAP9_ROM_BASE       0x00400000      /* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
-
-#define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
-#define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
deleted file mode 100644
index 4b9d4aff4b4..00000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_MATRIX_H
-#define AT91CAP9_MATRIX_H
-
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8       (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SCFG9       (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8       (AT91_MATRIX + 0xC0)    /* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8       (AT91_MATRIX + 0xC4)    /* Priority Register B for Slave 8 */
-#define AT91_MATRIX_PRAS9       (AT91_MATRIX + 0xC8)    /* Priority Register A for Slave 9 */
-#define AT91_MATRIX_PRBS9       (AT91_MATRIX + 0xCC)    /* Priority Register B for Slave 9 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
-#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
-#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
-#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
-#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-#define         AT91_MATRIX_RCB6                (1 << 6)
-#define         AT91_MATRIX_RCB7                (1 << 7)
-#define         AT91_MATRIX_RCB8                (1 << 8)
-#define         AT91_MATRIX_RCB9                (1 << 9)
-#define         AT91_MATRIX_RCB10               (1 << 10)
-#define         AT91_MATRIX_RCB11               (1 << 11)
-
-#define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
-#define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
-
-#define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
-#define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
-#define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
-#define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
-
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define                 AT91_MATRIX_EBI_CS1A_BCRAMC             (1 << 1)
-#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
-#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
-#define                 AT91_MATRIX_EBI_CS4A_SMC_CF1            (1 << 4)
-#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
-#define                 AT91_MATRIX_EBI_CS5A_SMC_CF2            (1 << 5)
-#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_EBI_DQSPDC          (1 << 9)        /* Data Qualifier Strobe Pull-Down Configuration */
-#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-
-#define AT91_MPBS2_SFR          (AT91_MATRIX + 0x12C)   /* MPBlock Slave 2 Special Function Register */
-#define AT91_MPBS3_SFR          (AT91_MATRIX + 0x130)   /* MPBlock Slave 3 Special Function Register */
-#define AT91_APB_SFR            (AT91_MATRIX + 0x134)   /* APB Bridge Special Function Register */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index bacb5114181..603e6aac2a4 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -77,26 +77,22 @@
 
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
-#define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
-#define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
-
 #define AT91RM9200_BASE_DBGU    AT91_BASE_DBGU0 /* Debug Unit */
 #define AT91RM9200_BASE_PIOA    0xfffff400      /* PIO Controller A */
 #define AT91RM9200_BASE_PIOB    0xfffff600      /* PIO Controller B */
 #define AT91RM9200_BASE_PIOC    0xfffff800      /* PIO Controller C */
 #define AT91RM9200_BASE_PIOD    0xfffffa00      /* PIO Controller D */
+#define AT91RM9200_BASE_ST      0xfffffd00      /* System Timer */
 #define AT91RM9200_BASE_RTC     0xfffffe00      /* Real-Time Clock */
+#define AT91RM9200_BASE_MC      0xffffff00      /* Memory Controllers */
 
 #define AT91_USART0     AT91RM9200_BASE_US0
 #define AT91_USART1     AT91RM9200_BASE_US1
 #define AT91_USART2     AT91RM9200_BASE_US2
 #define AT91_USART3     AT91RM9200_BASE_US3
 
-#define AT91_MATRIX     0       /* not supported */
-
 /*
  * Internal Memory.
  */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index d34e4ed8934..aeaadfb452a 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,10 +17,10 @@
 #define AT91RM9200_MC_H
 
 /* Memory Controller */
-#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define AT91_MC_RCR             0x00                    /* MC Remap Control Register */
 #define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
 
-#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define AT91_MC_ASR             0x04                    /* MC Abort Status Register */
 #define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
 #define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
 #define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
@@ -40,16 +40,16 @@
 #define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
 #define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
 
-#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+#define AT91_MC_AASR            0x08                    /* MC Abort Address Status Register */
 
-#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+#define AT91_MC_MPR             0x0c                    /* MC Master Priority Register */
 #define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
 #define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
 #define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
 #define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
 
 /* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define AT91_EBI_CSA            0x60                    /* Chip Select Assignment Register */
 #define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
 #define                 AT91_EBI_CS0A_SMC               (0 << 0)
 #define                 AT91_EBI_CS0A_BFC               (1 << 0)
@@ -66,7 +66,7 @@
 #define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
 
 /* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define AT91_SMC_CSR(n)         (0x70 + ((n) * 4))      /* SMC Chip Select Register */
 #define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
 #define                 AT91_SMC_NWS_(x)        ((x) << 0)
 #define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
@@ -87,52 +87,8 @@
 #define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
 #define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
 
-/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
-#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
-#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
-#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
-#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
-#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 4)
-#define                 AT91_SDRAMC_DBW_16      (1 << 4)
-
-#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
-#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
-#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
-#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
-
 /* Burst Flash Controller register */
-#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
+#define AT91_BFC_MR             0xc0                    /* Mode Register */
 #define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
 #define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
 #define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
new file mode 100644
index 00000000000..aa047f458f1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (SDRAMC only) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_SDRAMC_H
+#define AT91RM9200_SDRAMC_H
+
+/* SDRAM Controller registers */
+#define AT91RM9200_SDRAMC_MR            0x90                    /* Mode Register */
+#define         AT91RM9200_SDRAMC_MODE  (0xf << 0)              /* Command Mode */
+#define                 AT91RM9200_SDRAMC_MODE_NORMAL           (0 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_NOP              (1 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_PRECHARGE        (2 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_LMR              (3 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_REFRESH  (4 << 0)
+#define         AT91RM9200_SDRAMC_DBW           (1   << 4)              /* Data Bus Width */
+#define                 AT91RM9200_SDRAMC_DBW_32        (0 << 4)
+#define                 AT91RM9200_SDRAMC_DBW_16        (1 << 4)
+
+#define AT91RM9200_SDRAMC_TR            0x94                    /* Refresh Timer Register */
+#define         AT91RM9200_SDRAMC_COUNT (0xfff << 0)            /* Refresh Timer Count */
+
+#define AT91RM9200_SDRAMC_CR            0x98                    /* Configuration Register */
+#define         AT91RM9200_SDRAMC_NC            (3   <<  0)             /* Number of Column Bits */
+#define                 AT91RM9200_SDRAMC_NC_8  (0 << 0)
+#define                 AT91RM9200_SDRAMC_NC_9  (1 << 0)
+#define                 AT91RM9200_SDRAMC_NC_10 (2 << 0)
+#define                 AT91RM9200_SDRAMC_NC_11 (3 << 0)
+#define         AT91RM9200_SDRAMC_NR            (3   <<  2)             /* Number of Row Bits */
+#define                 AT91RM9200_SDRAMC_NR_11 (0 << 2)
+#define                 AT91RM9200_SDRAMC_NR_12 (1 << 2)
+#define                 AT91RM9200_SDRAMC_NR_13 (2 << 2)
+#define         AT91RM9200_SDRAMC_NB            (1   <<  4)             /* Number of Banks */
+#define                 AT91RM9200_SDRAMC_NB_2  (0 << 4)
+#define                 AT91RM9200_SDRAMC_NB_4  (1 << 4)
+#define         AT91RM9200_SDRAMC_CAS           (3   <<  5)             /* CAS Latency */
+#define                 AT91RM9200_SDRAMC_CAS_2 (2 << 5)
+#define         AT91RM9200_SDRAMC_TWR           (0xf <<  7)             /* Write Recovery Delay */
+#define         AT91RM9200_SDRAMC_TRC           (0xf << 11)             /* Row Cycle Delay */
+#define         AT91RM9200_SDRAMC_TRP           (0xf << 15)             /* Row Precharge Delay */
+#define         AT91RM9200_SDRAMC_TRCD  (0xf << 19)             /* Row to Column Delay */
+#define         AT91RM9200_SDRAMC_TRAS  (0xf << 23)             /* Active to Precharge Delay */
+#define         AT91RM9200_SDRAMC_TXSR  (0xf << 27)             /* Exit Self Refresh to Active Delay */
+
+#define AT91RM9200_SDRAMC_SRR           0x9c                    /* Self Refresh Register */
+#define AT91RM9200_SDRAMC_LPR           0xa0                    /* Low Power Register */
+#define AT91RM9200_SDRAMC_IER           0xa4                    /* Interrupt Enable Register */
+#define AT91RM9200_SDRAMC_IDR           0xa8                    /* Interrupt Disable Register */
+#define AT91RM9200_SDRAMC_IMR           0xac                    /* Interrupt Mask Register */
+#define AT91RM9200_SDRAMC_ISR           0xb0                    /* Interrupt Status Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index fa5ca278ade..08ae9afd00f 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -78,15 +78,12 @@
 #define AT91SAM9260_BASE_ADC            0xfffe0000
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
-
 #define AT91SAM9260_BASE_ECC    0xffffe800
+#define AT91SAM9260_BASE_SDRAMC 0xffffea00
 #define AT91SAM9260_BASE_SMC    0xffffec00
+#define AT91SAM9260_BASE_MATRIX 0xffffee00
 #define AT91SAM9260_BASE_DBGU   AT91_BASE_DBGU0
 #define AT91SAM9260_BASE_PIOA   0xfffff400
 #define AT91SAM9260_BASE_PIOB   0xfffff600
@@ -96,6 +93,7 @@
 #define AT91SAM9260_BASE_RTT    0xfffffd20
 #define AT91SAM9260_BASE_PIT    0xfffffd30
 #define AT91SAM9260_BASE_WDT    0xfffffd40
+#define AT91SAM9260_BASE_GPBR   0xfffffd50
 
 #define AT91_USART0     AT91SAM9260_BASE_US0
 #define AT91_USART1     AT91SAM9260_BASE_US1
@@ -115,6 +113,8 @@
 #define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
 #define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
 #define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
+#define AT91SAM9260_SRAM_BASE   0x002FF000      /* Internal SRAM base address */
+#define AT91SAM9260_SRAM_SIZE   SZ_8K           /* Internal SRAM size (8Kb) */
 
 #define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
 
@@ -128,6 +128,8 @@
 #define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
 #define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
 #define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+#define AT91SAM9G20_SRAM_BASE   0x002FC000      /* Internal SRAM base address */
+#define AT91SAM9G20_SRAM_SIZE   SZ_32K          /* Internal SRAM size (32Kb) */
 
 #define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
 
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02ed921..f459df42062 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,12 +15,12 @@
 #ifndef AT91SAM9260_MATRIX_H
 #define AT91SAM9260_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
 #define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -28,11 +28,11 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -43,11 +43,11 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -55,11 +55,11 @@
 #define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
 #define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x11C                   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 7cde2d36570..44fbdc12ee6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -63,14 +63,11 @@
 
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
-
 #define AT91SAM9261_BASE_SMC    0xffffec00
+#define AT91SAM9261_BASE_MATRIX 0xffffee00
+#define AT91SAM9261_BASE_SDRAMC 0xffffea00
 #define AT91SAM9261_BASE_DBGU   AT91_BASE_DBGU0
 #define AT91SAM9261_BASE_PIOA   0xfffff400
 #define AT91SAM9261_BASE_PIOB   0xfffff600
@@ -80,6 +77,7 @@
 #define AT91SAM9261_BASE_RTT    0xfffffd20
 #define AT91SAM9261_BASE_PIT    0xfffffd30
 #define AT91SAM9261_BASE_WDT    0xfffffd40
+#define AT91SAM9261_BASE_GPBR   0xfffffd50
 
 #define AT91_USART0     AT91SAM9261_BASE_US0
 #define AT91_USART1     AT91SAM9261_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 69c6501915d..a50cdf8b8ca 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,15 +15,15 @@
 #ifndef AT91SAM9261_MATRIX_H
 #define AT91SAM9261_MATRIX_H
 
-#define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
+#define AT91_MATRIX_MCFG        0x00                    /* Master Configuration Register */
 #define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG0       0x04                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x08                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x0C                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x10                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x14                    /* Slave Configuration Register 4 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -31,7 +31,7 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
 #define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
 
-#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
+#define AT91_MATRIX_TCR         0x24                    /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -43,7 +43,7 @@
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
 #define                 AT91_MATRIX_DTCM_64             (7 << 4)
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x30                    /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
@@ -58,7 +58,7 @@
 #define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
 #define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
 
-#define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
+#define AT91_MATRIX_USBPUCR     0x34                    /* USB Pad Pull-Up Control Register */
 #define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 5949abda962..d96cbb2e03c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -72,18 +72,15 @@
 #define AT91SAM9263_BASE_2DGE           0xfffc8000
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_SDRAMC0    (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SDRAMC1    (0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffec00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-
 #define AT91SAM9263_BASE_ECC0   0xffffe000
+#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
 #define AT91SAM9263_BASE_SMC0   0xffffe400
 #define AT91SAM9263_BASE_ECC1   0xffffe600
+#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
 #define AT91SAM9263_BASE_SMC1   0xffffea00
+#define AT91SAM9263_BASE_MATRIX 0xffffec00
 #define AT91SAM9263_BASE_DBGU   AT91_BASE_DBGU1
 #define AT91SAM9263_BASE_PIOA   0xfffff200
 #define AT91SAM9263_BASE_PIOB   0xfffff400
@@ -96,6 +93,7 @@
 #define AT91SAM9263_BASE_PIT    0xfffffd30
 #define AT91SAM9263_BASE_WDT    0xfffffd40
 #define AT91SAM9263_BASE_RTT1   0xfffffd50
+#define AT91SAM9263_BASE_GPBR   0xfffffd60
 
 #define AT91_USART0     AT91SAM9263_BASE_US0
 #define AT91_USART1     AT91SAM9263_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 9b3efd3eb2f..ebb5fdb565e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,15 +15,15 @@
 #ifndef AT91SAM9263_MATRIX_H
 #define AT91SAM9263_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -31,14 +31,14 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -49,22 +49,22 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -75,7 +75,7 @@
 #define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
 #define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -86,7 +86,7 @@
 #define         AT91_MATRIX_RCB7                (1 << 7)
 #define         AT91_MATRIX_RCB8                (1 << 8)
 
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -96,7 +96,7 @@
 #define                 AT91_MATRIX_DTCM_16             (5 << 4)
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
 
-#define AT91_MATRIX_EBI0CSA     (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI0CSA     0x120                   /* EBI0 Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI0_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI0_CS1A_SMC               (0 << 1)
 #define                 AT91_MATRIX_EBI0_CS1A_SDRAMC            (1 << 1)
@@ -114,7 +114,7 @@
 #define                 AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         (0 << 16)
 #define                 AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         (1 << 16)
 
-#define AT91_MATRIX_EBI1CSA     (AT91_MATRIX + 0x124)   /* EBI1 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI1CSA     0x124                   /* EBI1 Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI1_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI1_CS1A_SMC               (0 << 1)
 #define                 AT91_MATRIX_EBI1_CS1A_SDRAMC            (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index e2f8da8ce5b..0210797abf2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -59,7 +59,6 @@
 #define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
 #define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
 #define         AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
-#define         AT91CAP9_DDRSDRC_TWTR   (1   << 24)             /* Internal Write to Read delay */
 #define         AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay [SAM9 Only] */
 #define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
 
@@ -76,7 +75,6 @@
 #define         AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
 
 #define AT91_DDRSDRC_LPR        0x1C    /* Low Power Register */
-#define AT91CAP9_DDRSDRC_LPR    0x18    /* Low Power Register */
 #define         AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
 #define                 AT91_DDRSDRC_LPCB_DISABLE               0
 #define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
@@ -94,11 +92,9 @@
 #define         AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
 
 #define AT91_DDRSDRC_MDR        0x20    /* Memory Device Register */
-#define AT91CAP9_DDRSDRC_MDR    0x1C    /* Memory Device Register */
 #define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
 #define                 AT91_DDRSDRC_MD_SDR             0
 #define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
-#define                 AT91CAP9_DDRSDRC_MD_DDR         2
 #define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
 #define                 AT91_DDRSDRC_MD_DDR2            6       /* [SAM9 Only] */
 #define         AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
@@ -106,16 +102,10 @@
 #define                 AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
 
 #define AT91_DDRSDRC_DLL        0x24    /* DLL Information Register */
-#define AT91CAP9_DDRSDRC_DLL    0x20    /* DLL Information Register */
 #define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 #define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 #define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
-#define         AT91CAP9_DDRSDRC_SDCOVF (1 << 3)                /* Slave Delay Correction Overflow */
-#define         AT91CAP9_DDRSDRC_SDCUDF (1 << 4)                /* Slave Delay Correction Underflow */
-#define         AT91CAP9_DDRSDRC_SDERF  (1 << 5)                /* Slave Delay Correction error */
 #define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
-#define         AT91CAP9_DDRSDRC_SDVAL  (0xff << 16)            /* Slave Delay value */
-#define         AT91CAP9_DDRSDRC_SDCVAL (0xff << 24)            /* Slave Delay Correction value */
 
 #define AT91_DDRSDRC_HS         0x2C    /* High Speed Register [SAM9 Only] */
 #define         AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
@@ -131,10 +121,4 @@
 #define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
 #define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
 
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
-        at91_sys_read(AT91_DDRSDRC##num + reg)
-#define at91_ramc_write(num, reg, value) \
-        at91_sys_write(AT91_DDRSDRC##num + reg, value)
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 100f5a59292..3d085a9a745 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -82,10 +82,4 @@
 #define                 AT91_SDRAMC_MD_SDRAM            0
 #define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
-        at91_sys_read(AT91_SDRAMC##num + reg)
-#define at91_ramc_write(num, reg, value) \
-        at91_sys_write(AT91_SDRAMC##num + reg, value)
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index dd9c95ea086..d052abcff85 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -84,17 +84,14 @@
 #define AT91SAM9G45_BASE_TC5            0xfffd4080
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-
 #define AT91SAM9G45_BASE_ECC    0xffffe200
+#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
+#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
 #define AT91SAM9G45_BASE_DMA    0xffffec00
 #define AT91SAM9G45_BASE_SMC    0xffffe800
+#define AT91SAM9G45_BASE_MATRIX 0xffffea00
 #define AT91SAM9G45_BASE_DBGU   AT91_BASE_DBGU1
 #define AT91SAM9G45_BASE_PIOA   0xfffff200
 #define AT91SAM9G45_BASE_PIOB   0xfffff400
@@ -107,6 +104,7 @@
 #define AT91SAM9G45_BASE_PIT    0xfffffd30
 #define AT91SAM9G45_BASE_WDT    0xfffffd40
 #define AT91SAM9G45_BASE_RTC    0xfffffdb0
+#define AT91SAM9G45_BASE_GPBR   0xfffffd60
 
 #define AT91_USART0     AT91SAM9G45_BASE_US0
 #define AT91_USART1     AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60e0ae..b76e2ed2fbc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
 #ifndef AT91SAM9G45_MATRIX_H
 #define AT91SAM9G45_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9       0x24                    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10      0x28                    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11      0x2C                    /* Master Configuration Register 11 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -37,14 +37,14 @@
 #define                 AT91_MATRIX_ULBT_SIXTYFOUR      (6 << 0)
 #define                 AT91_MATRIX_ULBT_128            (7 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0x1ff << 0)    /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -52,22 +52,22 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
 #define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -81,7 +81,7 @@
 #define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
 #define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -95,7 +95,7 @@
 #define         AT91_MATRIX_RCB10               (1 << 10)
 #define         AT91_MATRIX_RCB11               (1 << 11)
 
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x110)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x110                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_32             (6 << 0)
@@ -107,12 +107,12 @@
 #define                 AT91_MATRIX_TCM_NO_WS           (0x0 << 11)
 #define                 AT91_MATRIX_TCM_ONE_WS          (0x1 << 11)
 
-#define AT91_MATRIX_VIDEO       (AT91_MATRIX + 0x118)   /* Video Mode Configuration Register */
+#define AT91_MATRIX_VIDEO       0x118                   /* Video Mode Configuration Register */
 #define         AT91C_VDEC_SEL                  (0x1 <<  0) /* Video Mode Selection */
 #define                 AT91C_VDEC_SEL_OFF              (0 << 0)
 #define                 AT91C_VDEC_SEL_ON               (1 << 0)
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x128)   /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x128                   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
 #define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
@@ -138,13 +138,13 @@
 #define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
 #define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
 
-#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define AT91_MATRIX_WPMR        0x1E4                   /* Write Protect Mode Register */
 #define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
 #define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
 #define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
 #define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
 
-#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define AT91_MATRIX_WPSR        0x1E8                   /* Write Protect Status Register */
 #define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
 #define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
 #define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index d7bead7118d..e0073eb1014 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,15 +69,13 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
 
 #define AT91SAM9RL_BASE_DMA     0xffffe600
 #define AT91SAM9RL_BASE_ECC     0xffffe800
+#define AT91SAM9RL_BASE_SDRAMC  0xffffea00
 #define AT91SAM9RL_BASE_SMC     0xffffec00
+#define AT91SAM9RL_BASE_MATRIX  0xffffee00
 #define AT91SAM9RL_BASE_DBGU    AT91_BASE_DBGU0
 #define AT91SAM9RL_BASE_PIOA    0xfffff400
 #define AT91SAM9RL_BASE_PIOB    0xfffff600
@@ -88,6 +86,7 @@
 #define AT91SAM9RL_BASE_RTT     0xfffffd20
 #define AT91SAM9RL_BASE_PIT     0xfffffd30
 #define AT91SAM9RL_BASE_WDT     0xfffffd40
+#define AT91SAM9RL_BASE_GPBR    0xfffffd60
 #define AT91SAM9RL_BASE_RTC     0xfffffe00
 
 #define AT91_USART0     AT91SAM9RL_BASE_US0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
index 5f9149071fe..6d160adadaf 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
@@ -14,12 +14,12 @@
 #ifndef AT91SAM9RL_MATRIX_H
 #define AT91SAM9RL_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -27,12 +27,12 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -43,12 +43,12 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -56,7 +56,7 @@
 #define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
 #define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -64,7 +64,7 @@
 #define         AT91_MATRIX_RCB4                (1 << 4)
 #define         AT91_MATRIX_RCB5                (1 << 5)
 
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -74,7 +74,7 @@
 #define                 AT91_MATRIX_DTCM_16             (5 << 4)
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x120                   /* EBI0 Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
new file mode 100644
index 00000000000..88e43d534cd
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -0,0 +1,74 @@
+/*
+ * Chip-specific header file for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2009-2012 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9x5 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef AT91SAM9X5_H
+#define AT91SAM9X5_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91SAM9X5_ID_PIOAB     2       /* Parallel I/O Controller A and B */
+#define AT91SAM9X5_ID_PIOCD     3       /* Parallel I/O Controller C and D */
+#define AT91SAM9X5_ID_SMD       4       /* SMD Soft Modem (SMD) */
+#define AT91SAM9X5_ID_USART0    5       /* USART 0 */
+#define AT91SAM9X5_ID_USART1    6       /* USART 1 */
+#define AT91SAM9X5_ID_USART2    7       /* USART 2 */
+#define AT91SAM9X5_ID_USART3    8       /* USART 3 */
+#define AT91SAM9X5_ID_TWI0      9       /* Two-Wire Interface 0 */
+#define AT91SAM9X5_ID_TWI1      10      /* Two-Wire Interface 1 */
+#define AT91SAM9X5_ID_TWI2      11      /* Two-Wire Interface 2 */
+#define AT91SAM9X5_ID_MCI0      12      /* High Speed Multimedia Card Interface 0 */
+#define AT91SAM9X5_ID_SPI0      13      /* Serial Peripheral Interface 0 */
+#define AT91SAM9X5_ID_SPI1      14      /* Serial Peripheral Interface 1 */
+#define AT91SAM9X5_ID_UART0     15      /* UART 0 */
+#define AT91SAM9X5_ID_UART1     16      /* UART 1 */
+#define AT91SAM9X5_ID_TCB       17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9X5_ID_PWM       18      /* Pulse Width Modulation Controller */
+#define AT91SAM9X5_ID_ADC       19      /* ADC Controller */
+#define AT91SAM9X5_ID_DMA0      20      /* DMA Controller 0 */
+#define AT91SAM9X5_ID_DMA1      21      /* DMA Controller 1 */
+#define AT91SAM9X5_ID_UHPHS     22      /* USB Host High Speed */
+#define AT91SAM9X5_ID_UDPHS     23      /* USB Device High Speed */
+#define AT91SAM9X5_ID_EMAC0     24      /* Ethernet MAC0 */
+#define AT91SAM9X5_ID_LCDC      25      /* LCD Controller */
+#define AT91SAM9X5_ID_ISI       25      /* Image Sensor Interface */
+#define AT91SAM9X5_ID_MCI1      26      /* High Speed Multimedia Card Interface 1 */
+#define AT91SAM9X5_ID_EMAC1     27      /* Ethernet MAC1 */
+#define AT91SAM9X5_ID_SSC       28      /* Synchronous Serial Controller */
+#define AT91SAM9X5_ID_CAN0      29      /* CAN Controller 0 */
+#define AT91SAM9X5_ID_CAN1      30      /* CAN Controller 1 */
+#define AT91SAM9X5_ID_IRQ0      31      /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9X5_BASE_USART0  0xf801c000
+#define AT91SAM9X5_BASE_USART1  0xf8020000
+#define AT91SAM9X5_BASE_USART2  0xf8024000
+
+/*
+ * Base addresses for early serial code (uncompress.h)
+ */
+#define AT91_DBGU       AT91_BASE_DBGU0
+#define AT91_USART0     AT91SAM9X5_BASE_USART0
+#define AT91_USART1     AT91SAM9X5_BASE_USART1
+#define AT91_USART2     AT91SAM9X5_BASE_USART2
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9X5_SRAM_BASE    0x00300000      /* Internal SRAM base address */
+#define AT91SAM9X5_SRAM_SIZE    SZ_32K          /* Internal SRAM size (32Kb) */
+
+#define AT91SAM9X5_ROM_BASE     0x00400000      /* Internal ROM base address */
+#define AT91SAM9X5_ROM_SIZE     SZ_64K          /* Internal ROM size (64Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
new file mode 100644
index 00000000000..a606d396647
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
@@ -0,0 +1,53 @@
+/*
+ * Matrix-centric header file for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2009-2012 Atmel Corporation.
+ *
+ * Only EBI related registers.
+ * Write Protect register definitions may be useful.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef AT91SAM9X5_MATRIX_H
+#define AT91SAM9X5_MATRIX_H
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH      (1 << 3)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+#define         AT91_MATRIX_NFD0_SELECT         (1 << 24)       /* NAND Flash Data Bus Selection */
+#define                 AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
+#define                 AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
+#define         AT91_MATRIX_DDR_MP_EN           (1 << 25)       /* DDR Multi-port Enable */
+#define                 AT91_MATRIX_MP_OFF                      (0 << 25)
+#define                 AT91_MATRIX_MP_ON                       (1 << 25)
+
+#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
+#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
+#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
+#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
+
+#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
+#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
+#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
+#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a57829f4fd1..90680217064 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -28,18 +28,18 @@
 #define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
 #define AT91_BASE_SYS   0xffc00000
 
-#define AT91_EBI        (0xffe00000 - AT91_BASE_SYS)    /* External Bus Interface */
-#define AT91_SF         (0xfff00000 - AT91_BASE_SYS)    /* Special Function */
-#define AT91_USART1     (0xfffcc000 - AT91_BASE_SYS)    /* USART 1 */
-#define AT91_USART0     (0xfffd0000 - AT91_BASE_SYS)    /* USART 0 */
-#define AT91_TC         (0xfffe0000 - AT91_BASE_SYS)    /* Timer Counter */
-#define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
-#define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
-#define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
+#define AT91_EBI        0xffe00000      /* External Bus Interface */
+#define AT91_SF         0xfff00000      /* Special Function */
+#define AT91_USART1     0xfffcc000      /* USART 1 */
+#define AT91_USART0     0xfffd0000      /* USART 0 */
+#define AT91_TC         0xfffe0000      /* Timer Counter */
+#define AT91_PIOA       0xffff0000      /* PIO Controller A */
+#define AT91_PS         0xffff4000      /* Power Save */
+#define AT91_WD         0xffff8000      /* Watchdog Timer */
 
 /*
  * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 3b33f07b1e1..544a5d5ce41 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -41,6 +41,7 @@
 #include <sound/atmel-ac97c.h>
 #include <linux/serial.h>
 #include <linux/platform_data/macb.h>
+#include <linux/platform_data/atmel.h>
 
  /* USB Device */
 struct at91_udc_data {
@@ -98,18 +99,6 @@ extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
 extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
 extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
 
- /* NAND / SmartMedia */
-struct atmel_nand_data {
-        int             enable_pin;     /* chip enable */
-        int             det_pin;        /* card detect */
-        int             rdy_pin;        /* ready/busy */
-        u8              rdy_pin_active_low;     /* rdy_pin value is inverted */
-        u8              ale;            /* address line number connected to ALE */
-        u8              cle;            /* address line number connected to CLE */
-        u8              bus_width_16;   /* buswidth is 16 bit */
-        struct mtd_partition *parts;
-        unsigned int    num_parts;
-};
 extern void __init at91_add_device_nand(struct atmel_nand_data *data);
 
  /* I2C*/
@@ -179,7 +168,9 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
 
  /* ISI */
-extern void __init at91_add_device_isi(void);
+struct isi_platform_data;
+extern void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck);
 
  /* Touchscreen Controller */
 struct at91_tsadcc_data {
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index f6ce936dba2..0118c333855 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,7 +25,6 @@
 #define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
 #define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
 #define ARCH_ID_AT91SAM9X5      0x819a05a0
-#define ARCH_ID_AT91CAP9        0x039A03A0
 
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
@@ -51,10 +50,6 @@
 #define ARCH_FAMILY_AT91SAM9    0x01900000
 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
 
-/* PMC revision */
-#define ARCH_REVISION_CAP9_B    0x399
-#define ARCH_REVISION_CAP9_C    0x601
-
 /* RM9200 type */
 #define ARCH_REVISON_9200_BGA   (0 << 0)
 #define ARCH_REVISON_9200_PQFP  (1 << 0)
@@ -63,9 +58,6 @@ enum at91_soc_type {
         /* 920T */
         AT91_SOC_RM9200,
 
-        /* CAP */
-        AT91_SOC_CAP9,
-
         /* SAM92xx */
         AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
 
@@ -86,9 +78,6 @@ enum at91_soc_subtype {
         /* RM9200 */
         AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
 
-        /* CAP9 */
-        AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
-
         /* SAM9260 */
         AT91_SOC_SAM9XE,
 
@@ -195,16 +184,6 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9x25()    (0)
 #endif
 
-#ifdef CONFIG_ARCH_AT91CAP9
-#define cpu_is_at91cap9()       (at91_soc_initdata.type == AT91_SOC_CAP9)
-#define cpu_is_at91cap9_revB()  (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
-#define cpu_is_at91cap9_revC()  (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
-#else
-#define cpu_is_at91cap9()       (0)
-#define cpu_is_at91cap9_revB()  (0)
-#define cpu_is_at91cap9_revC()  (0)
-#endif
-
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
index 423eea0ed74..903bf205a33 100644
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -13,17 +13,11 @@
 #include <mach/hardware.h>
 #include <mach/at91_aic.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =at91_aic_base           @ base virtual address of AIC peripheral
         ldr     \base, [\base]
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
         ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index e3fd225121c..eed465ab0dd 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -191,10 +191,15 @@
 extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
 extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
+extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
 extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
+extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
+extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
 
 /* callable at any time */
 extern int at91_set_gpio_value(unsigned pin, int value);
@@ -204,18 +209,6 @@ extern int at91_get_gpio_value(unsigned pin);
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
 
-/*-------------------------------------------------------------------------*/
-
-/* wrappers for "new style" GPIO calls. the old AT91-specific ones should
- * eventually be removed (along with this errno.h inclusion), and the
- * gpio request/free calls should probably be implemented.
- */
-
-#include <asm/errno.h>
-
-#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS)
-#define irq_to_gpio(irq)  (irq - NR_AIC_IRQS)
-
 #endif  /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 2d0e4e99856..e9e29a6c386 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,7 +19,7 @@
 /* DBGU base */
 /* rm9200, 9260/9g20, 9261/9g10, 9rl */
 #define AT91_BASE_DBGU0 0xfffff200
-/* 9263, 9g45, cap9 */
+/* 9263, 9g45 */
 #define AT91_BASE_DBGU1 0xffffee00
 
 #if defined(CONFIG_ARCH_AT91RM9200)
@@ -34,8 +34,8 @@
 #include <mach/at91sam9rl.h>
 #elif defined(CONFIG_ARCH_AT91SAM9G45)
 #include <mach/at91sam9g45.h>
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9.h>
+#elif defined(CONFIG_ARCH_AT91SAM9X5)
+#include <mach/at91sam9x5.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
 #else
@@ -59,9 +59,10 @@
 
 /*
  * On all at91 have the Advanced Interrupt Controller starts at address
- * 0xfffff000
+ * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
  */
 #define AT91_AIC        0xfffff000
+#define AT91_PMC        0xfffffc00
 
 /*
  * Peripheral identifiers/interrupts.
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 4ca09ef7ca2..4003001eca3 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -28,22 +28,4 @@
 #define __io(a)         __typesafe_io(a)
 #define __mem_pci(a)    (a)
 
-#ifndef __ASSEMBLY__
-
-static inline unsigned int at91_sys_read(unsigned int reg_offset)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-
-        return __raw_readl(addr + reg_offset);
-}
-
-static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-
-        __raw_writel(value, addr + reg_offset);
-}
-
-#endif
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
deleted file mode 100644
index cbd64f3bcec..00000000000
--- a/arch/arm/mach-at91/include/mach/system.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/system.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/hardware.h>
-#include <mach/at91_st.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * Disable the processor clock.  The processor will be automatically
-         * re-enabled by an interrupt or by a reset.
-         */
-#ifdef AT91_PS
-        at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
-#else
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-#endif
-#ifndef CONFIG_CPU_ARM920T
-        /*
-         * Set the processor (CP15) into 'Wait for Interrupt' mode.
-         * Post-RM9200 processors need this in conjunction with the above
-         * to save power when idle.
-         */
-        cpu_do_idle();
-#endif
-}
-
-#endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index be6b639ecd7..cfcfcbe3626 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -24,6 +24,12 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/types.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -34,22 +40,24 @@
 #include <asm/mach/map.h>
 
 void __iomem *at91_aic_base;
+static struct irq_domain *at91_aic_domain;
+static struct device_node *at91_aic_np;
 
 static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IDCR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
 }
 
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IECR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
 }
 
 unsigned int at91_extern_irq;
 
-#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
+#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
 
 static int at91_aic_set_type(struct irq_data *d, unsigned type)
 {
@@ -63,13 +71,13 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 srctype = AT91_AIC_SRCTYPE_RISING;
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
+                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_LOW;
                 else
                         return -EINVAL;
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
+                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_FALLING;
                 else
                         return -EINVAL;
@@ -78,8 +86,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 return -EINVAL;
         }
 
-        smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
-        at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype);
+        smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
+        at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
         return 0;
 }
 
@@ -90,13 +98,13 @@ static u32 backups;
 
 static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 {
-        if (unlikely(d->irq >= 32))
+        if (unlikely(d->hwirq >= NR_AIC_IRQS))
                 return -EINVAL;
 
         if (value)
-                wakeups |= (1 << d->irq);
+                wakeups |= (1 << d->hwirq);
         else
-                wakeups &= ~(1 << d->irq);
+                wakeups &= ~(1 << d->hwirq);
 
         return 0;
 }
@@ -127,46 +135,112 @@ static struct irq_chip at91_aic_chip = {
         .irq_set_wake   = at91_aic_set_wake,
 };
 
+static void __init at91_aic_hw_init(unsigned int spu_vector)
+{
+        int i;
+
+        /*
+         * Perform 8 End Of Interrupt Command to make sure AIC
+         * will not Lock out nIRQ
+         */
+        for (i = 0; i < 8; i++)
+                at91_aic_write(AT91_AIC_EOICR, 0);
+
+        /*
+         * Spurious Interrupt ID in Spurious Vector Register.
+         * When there is no current interrupt, the IRQ Vector Register
+         * reads the value stored in AIC_SPU
+         */
+        at91_aic_write(AT91_AIC_SPU, spu_vector);
+
+        /* No debugging in AIC: Debug (Protect) Control Register */
+        at91_aic_write(AT91_AIC_DCR, 0);
+
+        /* Disable and clear all interrupts initially */
+        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+}
+
+#if defined(CONFIG_OF)
+static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        /* Put virq number in Source Vector Register */
+        at91_aic_write(AT91_AIC_SVR(hw), virq);
+
+        /* Active Low interrupt, without priority */
+        at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
+
+        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static struct irq_domain_ops at91_aic_irq_ops = {
+        .map    = at91_aic_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+int __init at91_aic_of_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        at91_aic_base = of_iomap(node, 0);
+        at91_aic_np = node;
+
+        at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
+                                                &at91_aic_irq_ops, NULL);
+        if (!at91_aic_domain)
+                panic("Unable to add AIC irq domain (DT)\n");
+
+        irq_set_default_host(at91_aic_domain);
+
+        at91_aic_hw_init(NR_AIC_IRQS);
+
+        return 0;
+}
+#endif
+
 /*
  * Initialize the AIC interrupt controller.
  */
 void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 {
         unsigned int i;
+        int irq_base;
 
         at91_aic_base = ioremap(AT91_AIC, 512);
-
         if (!at91_aic_base)
-                panic("Impossible to ioremap AT91_AIC\n");
+                panic("Unable to ioremap AIC registers\n");
+
+        /* Add irq domain for AIC */
+        irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
+        if (irq_base < 0) {
+                WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
+                irq_base = 0;
+        }
+        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
+                                                irq_base, 0,
+                                                &irq_domain_simple_ops, NULL);
+
+        if (!at91_aic_domain)
+                panic("Unable to add AIC irq domain\n");
+
+        irq_set_default_host(at91_aic_domain);
 
         /*
          * The IVR is used by macro get_irqnr_and_base to read and verify.
          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
          */
         for (i = 0; i < NR_AIC_IRQS; i++) {
-                /* Put irq number in Source Vector Register: */
+                /* Put hardware irq number in Source Vector Register: */
                 at91_aic_write(AT91_AIC_SVR(i), i);
                 /* Active Low interrupt, with the specified priority */
                 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
 
                 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-
-                /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
-                if (i < 8)
-                        at91_aic_write(AT91_AIC_EOICR, 0);
         }
 
-        /*
-         * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
-         * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
-         */
-        at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS);
-
-        /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_aic_write(AT91_AIC_DCR, 0);
-
-        /* Disable and clear all interrupts initially */
-        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+        at91_aic_hw_init(NR_AIC_IRQS);
 }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 1606379ac28..f630250c6b8 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -136,7 +136,7 @@ static int at91_pm_verify_clocks(void)
         unsigned long scsr;
         int i;
 
-        scsr = at91_sys_read(AT91_PMC_SCSR);
+        scsr = at91_pmc_read(AT91_PMC_SCSR);
 
         /* USB must not be using PLLB */
         if (cpu_is_at91rm9200()) {
@@ -150,11 +150,6 @@ static int at91_pm_verify_clocks(void)
                         pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
                 }
-        } else if (cpu_is_at91cap9()) {
-                if ((scsr & AT91CAP9_PMC_UHP) != 0) {
-                        pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
-                        return 0;
-                }
         }
 
 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
@@ -165,7 +160,7 @@ static int at91_pm_verify_clocks(void)
                 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
                         continue;
 
-                css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
+                css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
                 if (css != AT91_PMC_CSS_SLOW) {
                         pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
                         return 0;
@@ -193,23 +188,23 @@ int at91_suspend_entering_slow_clock(void)
 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
 
 
-static void (*slow_clock)(void);
+static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
+                          void __iomem *ramc1, int memctrl);
 
 #ifdef CONFIG_AT91_SLOW_CLOCK
-extern void at91_slow_clock(void);
+extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
+                            void __iomem *ramc1, int memctrl);
 extern u32 at91_slow_clock_sz;
 #endif
 
-
 static int at91_pm_enter(suspend_state_t state)
 {
-        u32 saved_lpr;
         at91_gpio_suspend();
         at91_irq_suspend();
 
         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
                         /* remember all the always-wake irqs */
-                        (at91_sys_read(AT91_PMC_PCSR)
+                        (at91_pmc_read(AT91_PMC_PCSR)
                                         | (1 << AT91_ID_FIQ)
                                         | (1 << AT91_ID_SYS)
                                         | (at91_extern_irq))
@@ -234,11 +229,18 @@ static int at91_pm_enter(suspend_state_t state)
                          * turning off the main oscillator; reverse on wakeup.
                          */
                         if (slow_clock) {
+                                int memctrl = AT91_MEMCTRL_SDRAMC;
+
+                                if (cpu_is_at91rm9200())
+                                        memctrl = AT91_MEMCTRL_MC;
+                                else if (cpu_is_at91sam9g45())
+                                        memctrl = AT91_MEMCTRL_DDRSDR;
 #ifdef CONFIG_AT91_SLOW_CLOCK
                                 /* copy slow_clock handler to SRAM, and call it */
                                 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
 #endif
-                                slow_clock();
+                                slow_clock(at91_pmc_base, at91_ramc_base[0],
+                                           at91_ramc_base[1], memctrl);
                                 break;
                         } else {
                                 pr_info("AT91: PM - no slow clock mode enabled ...\n");
@@ -259,16 +261,7 @@ static int at91_pm_enter(suspend_state_t state)
                          * For ARM 926 based chips, this requirement is weaker
                          * as at91sam9 can access a RAM in self-refresh mode.
                          */
-                        asm volatile (  "mov r0, #0\n\t"
-                                        "b 1f\n\t"
-                                        ".align 5\n\t"
-                                        "1: mcr p15, 0, r0, c7, c10, 4\n\t"
-                                        : /* no output */
-                                        : /* no input */
-                                        : "r0");
-                        saved_lpr = sdram_selfrefresh_enable();
-                        wait_for_interrupt_enable();
-                        sdram_selfrefresh_disable(saved_lpr);
+                        at91_standby();
                         break;
 
                 case PM_SUSPEND_ON:
@@ -316,7 +309,7 @@ static int __init at91_pm_init(void)
 
 #ifdef CONFIG_ARCH_AT91RM9200
         /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
-        at91_sys_write(AT91_SDRAMC_LPR, 0);
+        at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
 #endif
 
         suspend_set_ops(&at91_pm_ops);
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 7eb40d24242..89f56f3a802 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -1,5 +1,19 @@
+/*
+ * AT91 Power Management
+ *
+ * Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ARCH_ARM_MACH_AT91_PM
+#define __ARCH_ARM_MACH_AT91_PM
+
+#include <mach/at91_ramc.h>
 #ifdef CONFIG_ARCH_AT91RM9200
-#include <mach/at91rm9200_mc.h>
+#include <mach/at91rm9200_sdramc.h>
 
 /*
  * The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -11,51 +25,37 @@
  * still in self-refresh is "not recommended", but seems to work.
  */
 
-static inline u32 sdram_selfrefresh_enable(void)
+static inline void at91rm9200_standby(void)
 {
-        u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
-
-        at91_sys_write(AT91_SDRAMC_LPR, 0);
-        at91_sys_write(AT91_SDRAMC_SRR, 1);
-        return saved_lpr;
+        u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
+
+        asm volatile(
+                "b    1f\n\t"
+                ".align    5\n\t"
+                "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
+                "    str    %0, [%1, %2]\n\t"
+                "    str    %3, [%1, %4]\n\t"
+                "    mcr    p15, 0, %0, c7, c0, 4\n\t"
+                "    str    %5, [%1, %2]"
+                :
+                : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
+                  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
+                  "r" (lpr));
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
-#define wait_for_interrupt_enable()             asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
-                                                                : : "r" (0))
-
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91sam9_ddrsdr.h>
-
-
-static inline u32 sdram_selfrefresh_enable(void)
-{
-        u32 saved_lpr, lpr;
-
-        saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
-
-        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-        at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
-        return saved_lpr;
-}
-
-#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
-#define wait_for_interrupt_enable()             cpu_do_idle()
+#define at91_standby at91rm9200_standby
 
 #elif defined(CONFIG_ARCH_AT91SAM9G45)
-#include <mach/at91sam9_ddrsdr.h>
 
 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  * remember.
  */
-static u32 saved_lpr1;
-
-static inline u32 sdram_selfrefresh_enable(void)
+static inline void at91sam9g45_standby(void)
 {
-        /* Those tow values allow us to delay self-refresh activation
+        /* Those two values allow us to delay self-refresh activation
          * to the maximum. */
         u32 lpr0, lpr1;
-        u32 saved_lpr0;
+        u32 saved_lpr0, saved_lpr1;
 
         saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
         lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
@@ -69,18 +69,15 @@ static inline u32 sdram_selfrefresh_enable(void)
         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
         at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
 
-        return saved_lpr0;
+        cpu_do_idle();
+
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
+        at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
 }
 
-#define sdram_selfrefresh_disable(saved_lpr0)   \
-        do { \
-                at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
-                at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
-        } while (0)
-#define wait_for_interrupt_enable()             cpu_do_idle()
+#define at91_standby at91sam9g45_standby
 
 #else
-#include <mach/at91sam9_sdramc.h>
 
 #ifdef CONFIG_ARCH_AT91SAM9263
 /*
@@ -90,18 +87,23 @@ static inline u32 sdram_selfrefresh_enable(void)
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
-static inline u32 sdram_selfrefresh_enable(void)
+static inline void at91sam9_standby(void)
 {
         u32 saved_lpr, lpr;
 
         saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 
         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
-        return saved_lpr;
+        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
+                        AT91_SDRAMC_LPCB_SELF_REFRESH);
+
+        cpu_do_idle();
+
+        at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
-#define wait_for_interrupt_enable()             cpu_do_idle()
+#define at91_standby at91sam9_standby
+
+#endif
 
 #endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 92dfb846139..db5452123f1 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -15,15 +15,7 @@
 #include <linux/linkage.h>
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
-
-#if defined(CONFIG_ARCH_AT91RM9200)
-#include <mach/at91rm9200_mc.h>
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
-#include <mach/at91sam9_ddrsdr.h>
-#else
-#include <mach/at91sam9_sdramc.h>
-#endif
+#include <mach/at91_ramc.h>
 
 
 #ifdef CONFIG_ARCH_AT91SAM9263
@@ -47,17 +39,23 @@
 #define PLLALOCK_TIMEOUT        1000
 #define PLLBLOCK_TIMEOUT        1000
 
+pmc     .req    r0
+sdramc  .req    r1
+ramc1   .req    r2
+memctrl .req    r3
+tmp1    .req    r4
+tmp2    .req    r5
 
 /*
  * Wait until master clock is ready (after switching master clock source)
  */
         .macro wait_mckrdy
-        mov     r4, #MCKRDY_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #MCKRDY_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_MCKRDY
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_MCKRDY
         beq     1b
 2:
         .endm
@@ -66,12 +64,12 @@
  * Wait until master oscillator has stabilized.
  */
         .macro wait_moscrdy
-        mov     r4, #MOSCRDY_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #MOSCRDY_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_MOSCS
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_MOSCS
         beq     1b
 2:
         .endm
@@ -80,12 +78,12 @@
  * Wait until PLLA has locked.
  */
         .macro wait_pllalock
-        mov     r4, #PLLALOCK_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #PLLALOCK_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_LOCKA
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_LOCKA
         beq     1b
 2:
         .endm
@@ -94,80 +92,98 @@
  * Wait until PLLB has locked.
  */
         .macro wait_pllblock
-        mov     r4, #PLLBLOCK_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #PLLBLOCK_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_LOCKB
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_LOCKB
         beq     1b
 2:
         .endm
 
         .text
 
+/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
+ *                      void __iomem *ramc1, int memctrl)
+ */
 ENTRY(at91_slow_clock)
         /* Save registers on stack */
-        stmfd   sp!, {r0 - r12, lr}
+        stmfd   sp!, {r4 - r12, lr}
 
         /*
          * Register usage:
-         *  R1 = Base address of AT91_PMC
-         *  R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
-         *  R3 = temporary register
+         *  R0 = Base address of AT91_PMC
+         *  R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+         *  R2 = Base address of second RAM Controller or 0 if not present
+         *  R3 = Memory controller
          *  R4 = temporary register
-         *  R5 = Base address of second RAM Controller or 0 if not present
+         *  R5 = temporary register
          */
-        ldr     r1, .at91_va_base_pmc
-        ldr     r2, .at91_va_base_sdramc
-        ldr     r5, .at91_va_base_ramc1
 
         /* Drain write buffer */
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c10, 4
+        mov     tmp1, #0
+        mcr     p15, 0, tmp1, c7, c10, 4
+
+        cmp     memctrl, #AT91_MEMCTRL_MC
+        bne     ddr_sr_enable
 
-#ifdef CONFIG_ARCH_AT91RM9200
+        /*
+         * at91rm9200 Memory controller
+         */
         /* Put SDRAM in self-refresh mode */
-        mov     r3, #1
-        str     r3, [r2, #AT91_SDRAMC_SRR]
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        mov     tmp1, #1
+        str     tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
+        b       sdr_sr_done
+
+        /*
+         * DDRSDR Memory controller
+         */
+ddr_sr_enable:
+        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
+        bne     sdr_sr_enable
 
         /* prepare for DDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_DDRSDRC_LPR]
-        str     r3, .saved_sam9_lpr
-        bic     r3, #AT91_DDRSDRC_LPCB
-        orr     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        ldr     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+        str     tmp1, .saved_sam9_lpr
+        bic     tmp1, #AT91_DDRSDRC_LPCB
+        orr     tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
 
         /* figure out if we use the second ram controller */
-        cmp     r5, #0
-        ldrne   r4, [r5, #AT91_DDRSDRC_LPR]
-        strne   r4, .saved_sam9_lpr1
-        bicne   r4, #AT91_DDRSDRC_LPCB
-        orrne   r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        cmp     ramc1, #0
+        ldrne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+        strne   tmp2, .saved_sam9_lpr1
+        bicne   tmp2, #AT91_DDRSDRC_LPCB
+        orrne   tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
 
         /* Enable DDRAM self-refresh mode */
-        str     r3, [r2, #AT91_DDRSDRC_LPR]
-        strne   r4, [r5, #AT91_DDRSDRC_LPR]
-#else
+        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+        strne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+
+        b       sdr_sr_done
+
+        /*
+         * SDRAMC Memory controller
+         */
+sdr_sr_enable:
         /* Enable SDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_SDRAMC_LPR]
-        str     r3, .saved_sam9_lpr
+        ldr     tmp1, [sdramc, #AT91_SDRAMC_LPR]
+        str     tmp1, .saved_sam9_lpr
 
-        bic     r3, #AT91_SDRAMC_LPCB
-        orr     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
-        str     r3, [r2, #AT91_SDRAMC_LPR]
-#endif
+        bic     tmp1, #AT91_SDRAMC_LPCB
+        orr     tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
+        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
 
+sdr_sr_done:
         /* Save Master clock setting */
-        ldr     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
-        str     r3, .saved_mckr
+        ldr     tmp1, [pmc, #AT91_PMC_MCKR]
+        str     tmp1, .saved_mckr
 
         /*
          * Set the Master clock source to slow clock
          */
-        bic     r3, r3, #AT91_PMC_CSS
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        bic     tmp1, tmp1, #AT91_PMC_CSS
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 
@@ -177,61 +193,61 @@ ENTRY(at91_slow_clock)
          *
          * See AT91RM9200 errata #27 and #28 for details.
          */
-        mov     r3, #0
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        mov     tmp1, #0
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 #endif
 
         /* Save PLLA setting and disable it */
-        ldr     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
-        str     r3, .saved_pllar
+        ldr     tmp1, [pmc, #AT91_CKGR_PLLAR]
+        str     tmp1, .saved_pllar
 
-        mov     r3, #AT91_PMC_PLLCOUNT
-        orr     r3, r3, #(1 << 29)              /* bit 29 always set */
-        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        mov     tmp1, #AT91_PMC_PLLCOUNT
+        orr     tmp1, tmp1, #(1 << 29)          /* bit 29 always set */
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
 
         /* Save PLLB setting and disable it */
-        ldr     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
-        str     r3, .saved_pllbr
+        ldr     tmp1, [pmc, #AT91_CKGR_PLLBR]
+        str     tmp1, .saved_pllbr
 
-        mov     r3, #AT91_PMC_PLLCOUNT
-        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        mov     tmp1, #AT91_PMC_PLLCOUNT
+        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
 
         /* Turn off the main oscillator */
-        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
-        bic     r3, r3, #AT91_PMC_MOSCEN
-        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+        bic     tmp1, tmp1, #AT91_PMC_MOSCEN
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
 
         /* Wait for interrupt */
-        mcr     p15, 0, r0, c7, c0, 4
+        mcr     p15, 0, tmp1, c7, c0, 4
 
         /* Turn on the main oscillator */
-        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
-        orr     r3, r3, #AT91_PMC_MOSCEN
-        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+        orr     tmp1, tmp1, #AT91_PMC_MOSCEN
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
 
         wait_moscrdy
 
         /* Restore PLLB setting */
-        ldr     r3, .saved_pllbr
-        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        ldr     tmp1, .saved_pllbr
+        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
 
-        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
         bne     1f
-        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
         beq     2f
 1:
         wait_pllblock
 2:
 
         /* Restore PLLA setting */
-        ldr     r3, .saved_pllar
-        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        ldr     tmp1, .saved_pllar
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
         bne     3f
-        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
         beq     4f
 3:
         wait_pllalock
@@ -244,11 +260,11 @@ ENTRY(at91_slow_clock)
          *
          * See AT91RM9200 errata #27 and #28 for details.
          */
-        ldr     r3, .saved_mckr
-        tst     r3, #AT91_PMC_PRES
+        ldr     tmp1, .saved_mckr
+        tst     tmp1, #AT91_PMC_PRES
         beq     2f
-        and     r3, r3, #AT91_PMC_PRES
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        and     tmp1, tmp1, #AT91_PMC_PRES
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 #endif
@@ -256,32 +272,45 @@ ENTRY(at91_slow_clock)
         /*
          * Restore master clock setting
          */
-2:      ldr     r3, .saved_mckr
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+2:      ldr     tmp1, .saved_mckr
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 
-#ifdef CONFIG_ARCH_AT91RM9200
-        /* Do nothing - self-refresh is automatically disabled. */
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        /*
+         * at91rm9200 Memory controller
+         * Do nothing - self-refresh is automatically disabled.
+         */
+        cmp     memctrl, #AT91_MEMCTRL_MC
+        beq     ram_restored
+
+        /*
+         * DDRSDR Memory controller
+         */
+        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
+        bne     sdr_en_restore
         /* Restore LPR on AT91 with DDRAM */
-        ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        ldr     tmp1, .saved_sam9_lpr
+        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
 
         /* if we use the second ram controller */
-        cmp     r5, #0
-        ldrne   r4, .saved_sam9_lpr1
-        strne   r4, [r5, #AT91_DDRSDRC_LPR]
+        cmp     ramc1, #0
+        ldrne   tmp2, .saved_sam9_lpr1
+        strne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+
+        b       ram_restored
 
-#else
+        /*
+         * SDRAMC Memory controller
+         */
+sdr_en_restore:
         /* Restore LPR on AT91 with SDRAM */
-        ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_SDRAMC_LPR]
-#endif
+        ldr     tmp1, .saved_sam9_lpr
+        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
 
+ram_restored:
         /* Restore registers, and return */
-        ldmfd   sp!, {r0 - r12, pc}
+        ldmfd   sp!, {r4 - r12, pc}
 
 
 .saved_mckr:
@@ -299,27 +328,5 @@ ENTRY(at91_slow_clock)
 .saved_sam9_lpr1:
         .word 0
 
-.at91_va_base_pmc:
-        .word AT91_VA_BASE_SYS + AT91_PMC
-
-#ifdef CONFIG_ARCH_AT91RM9200
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
-#else
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
-#endif
-
-.at91_va_base_ramc1:
-#if defined(CONFIG_ARCH_AT91SAM9G45)
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
-#else
-        .word 0
-#endif
-
 ENTRY(at91_slow_clock_sz)
         .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 69d3fc4c46f..1083739e306 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -9,6 +9,7 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/pm.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/map.h>
 
@@ -51,6 +52,19 @@ void __init at91_init_interrupts(unsigned int *priority)
         at91_gpio_irq_setup();
 }
 
+void __iomem *at91_ramc_base[2];
+
+void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
+{
+        if (id < 0 || id > 1) {
+                pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
+                BUG();
+        }
+        at91_ramc_base[id] = ioremap(addr, size);
+        if (!at91_ramc_base[id])
+                panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
+}
+
 static struct map_desc sram_desc[2] __initdata;
 
 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
@@ -86,20 +100,6 @@ static void __init soc_detect(u32 dbgu_base)
         socid = cidr & ~AT91_CIDR_VERSION;
 
         switch (socid) {
-        case ARCH_ID_AT91CAP9: {
-#ifdef CONFIG_AT91_PMC_UNIT
-                u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
-
-                if (pmc_ver == ARCH_REVISION_CAP9_B)
-                        at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
-                else if (pmc_ver == ARCH_REVISION_CAP9_C)
-                        at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
-#endif
-                at91_soc_initdata.type = AT91_SOC_CAP9;
-                at91_boot_soc = at91cap9_soc;
-                break;
-        }
-
         case ARCH_ID_AT91RM9200:
                 at91_soc_initdata.type = AT91_SOC_RM9200;
                 at91_boot_soc = at91rm9200_soc;
@@ -200,7 +200,6 @@ static void __init soc_detect(u32 dbgu_base)
 
 static const char *soc_name[] = {
         [AT91_SOC_RM9200]       = "at91rm9200",
-        [AT91_SOC_CAP9]         = "at91cap9",
         [AT91_SOC_SAM9260]      = "at91sam9260",
         [AT91_SOC_SAM9261]      = "at91sam9261",
         [AT91_SOC_SAM9263]      = "at91sam9263",
@@ -221,8 +220,6 @@ EXPORT_SYMBOL(at91_get_soc_type);
 static const char *soc_subtype_name[] = {
         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
-        [AT91_SOC_CAP9_REV_B]   = "at91cap9 revB",
-        [AT91_SOC_CAP9_REV_C]   = "at91cap9 revC",
         [AT91_SOC_SAM9XE]       = "at91sam9xe",
         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
         [AT91_SOC_SAM9M10]      = "at91sam9m10",
@@ -293,6 +290,159 @@ void __init at91_ioremap_rstc(u32 base_addr)
                 panic("Impossible to ioremap at91_rstc_base\n");
 }
 
+void __iomem *at91_matrix_base;
+
+void __init at91_ioremap_matrix(u32 base_addr)
+{
+        at91_matrix_base = ioremap(base_addr, 512);
+        if (!at91_matrix_base)
+                panic("Impossible to ioremap at91_matrix_base\n");
+}
+
+#if defined(CONFIG_OF)
+static struct of_device_id rstc_ids[] = {
+        { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
+        { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
+        { /*sentinel*/ }
+};
+
+static void at91_dt_rstc(void)
+{
+        struct device_node *np;
+        const struct of_device_id *of_id;
+
+        np = of_find_matching_node(NULL, rstc_ids);
+        if (!np)
+                panic("unable to find compatible rstc node in dtb\n");
+
+        at91_rstc_base = of_iomap(np, 0);
+        if (!at91_rstc_base)
+                panic("unable to map rstc cpu registers\n");
+
+        of_id = of_match_node(rstc_ids, np);
+        if (!of_id)
+                panic("AT91: rtsc no restart function availlable\n");
+
+        arm_pm_restart = of_id->data;
+
+        of_node_put(np);
+}
+
+static struct of_device_id ramc_ids[] = {
+        { .compatible = "atmel,at91sam9260-sdramc" },
+        { .compatible = "atmel,at91sam9g45-ddramc" },
+        { /*sentinel*/ }
+};
+
+static void at91_dt_ramc(void)
+{
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, ramc_ids);
+        if (!np)
+                panic("unable to find compatible ram conroller node in dtb\n");
+
+        at91_ramc_base[0] = of_iomap(np, 0);
+        if (!at91_ramc_base[0])
+                panic("unable to map ramc[0] cpu registers\n");
+        /* the controller may have 2 banks */
+        at91_ramc_base[1] = of_iomap(np, 1);
+
+        of_node_put(np);
+}
+
+static struct of_device_id shdwc_ids[] = {
+        { .compatible = "atmel,at91sam9260-shdwc", },
+        { .compatible = "atmel,at91sam9rl-shdwc", },
+        { .compatible = "atmel,at91sam9x5-shdwc", },
+        { /*sentinel*/ }
+};
+
+static const char *shdwc_wakeup_modes[] = {
+        [AT91_SHDW_WKMODE0_NONE]        = "none",
+        [AT91_SHDW_WKMODE0_HIGH]        = "high",
+        [AT91_SHDW_WKMODE0_LOW]         = "low",
+        [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
+};
+
+const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
+{
+        const char *pm;
+        int err, i;
+
+        err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
+        if (err < 0)
+                return AT91_SHDW_WKMODE0_ANYLEVEL;
+
+        for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
+                if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
+                        return i;
+
+        return -ENODEV;
+}
+
+static void at91_dt_shdwc(void)
+{
+        struct device_node *np;
+        int wakeup_mode;
+        u32 reg;
+        u32 mode = 0;
+
+        np = of_find_matching_node(NULL, shdwc_ids);
+        if (!np) {
+                pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
+                return;
+        }
+
+        at91_shdwc_base = of_iomap(np, 0);
+        if (!at91_shdwc_base)
+                panic("AT91: unable to map shdwc cpu registers\n");
+
+        wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
+        if (wakeup_mode < 0) {
+                pr_warn("AT91: shdwc unknown wakeup mode\n");
+                goto end;
+        }
+
+        if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
+                if (reg > AT91_SHDW_CPTWK0_MAX) {
+                        pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
+                                reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
+                        reg = AT91_SHDW_CPTWK0_MAX;
+                }
+                mode |= AT91_SHDW_CPTWK0_(reg);
+        }
+
+        if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
+                        mode |= AT91_SHDW_RTCWKEN;
+
+        if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
+                        mode |= AT91_SHDW_RTTWKEN;
+
+        at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
+
+end:
+        pm_power_off = at91sam9_poweroff;
+
+        of_node_put(np);
+}
+
+void __init at91_dt_initialize(void)
+{
+        at91_dt_rstc();
+        at91_dt_ramc();
+        at91_dt_shdwc();
+
+        /* Init clock subsystem */
+        at91_dt_clock_init();
+
+        /* Register the processor-specific clocks */
+        at91_boot_soc.register_clocks();
+
+        at91_boot_soc.init();
+}
+#endif
+
 void __init at91_initialize(unsigned long main_clock)
 {
         at91_boot_soc.ioremap_registers();
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 4588ae6f7ac..5db4aa45404 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -13,7 +13,6 @@ struct at91_init_soc {
 };
 
 extern struct at91_init_soc at91_boot_soc;
-extern struct at91_init_soc at91cap9_soc;
 extern struct at91_init_soc at91rm9200_soc;
 extern struct at91_init_soc at91sam9260_soc;
 extern struct at91_init_soc at91sam9261_soc;
@@ -27,10 +26,6 @@ static inline int at91_soc_is_enabled(void)
         return at91_boot_soc.init != NULL;
 }
 
-#if !defined(CONFIG_ARCH_AT91CAP9)
-#define at91cap9_soc    at91_boot_soc
-#endif
-
 #if !defined(CONFIG_ARCH_AT91RM9200)
 #define at91rm9200_soc  at91_boot_soc
 #endif
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 6b67b7e8426..22e4e0a28ad 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -52,27 +52,8 @@
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
 
-#define AMBA_DEVICE(name, initname, base, plat, size)       \
-static struct amba_device name##_device = {     \
-   .dev = {                                     \
-      .coherent_dma_mask = ~0,                  \
-      .init_name = initname,                    \
-      .platform_data = plat                     \
-   },                                           \
-   .res = {                                     \
-      .start = MM_ADDR_IO_##base,               \
-                .end = MM_ADDR_IO_##base + (size) - 1,    \
-      .flags = IORESOURCE_MEM                   \
-   },                                           \
-   .dma_mask = ~0,                              \
-   .irq = {                                     \
-      IRQ_##base                                \
-   }                                            \
-}
-
-
-AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
-AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
+static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
+static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
 
 static struct clk pll1_clk = {
         .name = "PLL1",
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
index 94c950d783b..2f316f0e6e6 100644
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S
@@ -21,9 +21,6 @@
 #include <mach/hardware.h>
 #include <mach/csp/mm_io.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \base, =(MM_IO_BASE_INTC0)
                 ldr     \irqstat, [\base, #0]           @ get status
@@ -77,6 +74,3 @@
 
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h
deleted file mode 100644
index cb78250db64..00000000000
--- a/arch/arm/mach-bcmring/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index ac84f925c79..3c5b5bbf24e 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -226,3 +226,19 @@ void clps711x_restart(char mode, const char *cmd)
 {
         soft_restart(0);
 }
+
+static void clps711x_idle(void)
+{
+        clps_writel(1, HALT);
+        __asm__ __volatile__(
+        "mov    r0, r0\n\
+        mov     r0, r0");
+}
+
+static int __init clps711x_idle_init(void)
+{
+        arm_pm_idle = clps711x_idle;
+        return 0;
+}
+
+arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S
index 90fa2f70489..125af59d7a2 100644
--- a/arch/arm/mach-clps711x/include/mach/entry-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/entry-macro.S
@@ -10,15 +10,9 @@
 #include <mach/hardware.h>
 #include <asm/hardware/clps7111.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
 #if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
 #error INTSR stride != INTMR stride
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
deleted file mode 100644
index 23d6ef8c84d..00000000000
--- a/arch/arm/mach-clps711x/include/mach/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/system.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/hardware/clps7111.h>
-
-static inline void arch_idle(void)
-{
-        clps_writel(1, HALT);
-        __asm__ __volatile__(
-        "mov    r0, r0\n\
-        mov     r0, r0");
-}
-
-#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
deleted file mode 100644
index 01c57df5f71..00000000000
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Low-level IRQ helper macros for Cavium Networks platforms
- *
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
deleted file mode 100644
index 9e56b7dc133..00000000000
--- a/arch/arm/mach-cns3xxx/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index e159d69967c..79d001f831e 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -155,8 +155,8 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
         BUG_ON(request_resource(&iomem_resource, res_io) ||
                request_resource(&iomem_resource, res_mem));
 
-        pci_add_resource(&sys->resources, res_io);
-        pci_add_resource(&sys->resources, res_mem);
+        pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 275341f159f..82ed753fb36 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -26,13 +26,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm355.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 /* NOTE:  this is geared for the standard config, with a socketed
  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
  * swap chips, maybe with a different block size, partitioning may
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index e99db28181a..d74a8b3445f 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -23,13 +23,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm355.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 /* NOTE:  this is geared for the standard config, with a socketed
  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
  * swap chips, maybe with a different block size, partitioning may
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 849311d3cb7..5bce2b83bb4 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -32,7 +32,6 @@
 #include <asm/mach/arch.h>
 
 #include <mach/mux.h>
-#include <mach/dm365.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
@@ -42,6 +41,8 @@
 
 #include <media/tvp514x.h>
 
+#include "davinci.h"
+
 static inline int have_imager(void)
 {
         /* REVISIT when it's supported, trigger via Kconfig */
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 1247ecdcf75..3683306e024 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -30,7 +30,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm644x.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
@@ -40,6 +39,8 @@
 #include <mach/usb.h>
 #include <mach/aemif.h>
 
+#include "davinci.h"
+
 #define DM644X_EVM_PHY_ID               "davinci_mdio-0:01"
 #define LXT971_PHY_ID   (0x001378e2)
 #define LXT971_PHY_MASK (0xfffffff0)
@@ -189,7 +190,7 @@ static struct platform_device davinci_fb_device = {
         .num_resources = 0,
 };
 
-static struct tvp514x_platform_data tvp5146_pdata = {
+static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
         .clk_polarity = 0,
         .hs_polarity = 1,
         .vs_polarity = 1
@@ -197,7 +198,7 @@ static struct tvp514x_platform_data tvp5146_pdata = {
 
 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
 /* Inputs available at the TVP5146 */
-static struct v4l2_input tvp5146_inputs[] = {
+static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
         {
                 .index = 0,
                 .name = "Composite",
@@ -217,7 +218,7 @@ static struct v4l2_input tvp5146_inputs[] = {
  * ouput that goes to vpfe. There is a one to one correspondence
  * with tvp5146_inputs
  */
-static struct vpfe_route tvp5146_routes[] = {
+static struct vpfe_route dm644xevm_tvp5146_routes[] = {
         {
                 .input = INPUT_CVBS_VI2B,
                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
@@ -228,13 +229,13 @@ static struct vpfe_route tvp5146_routes[] = {
         },
 };
 
-static struct vpfe_subdev_info vpfe_sub_devs[] = {
+static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
         {
                 .name = "tvp5146",
                 .grp_id = 0,
-                .num_inputs = ARRAY_SIZE(tvp5146_inputs),
-                .inputs = tvp5146_inputs,
-                .routes = tvp5146_routes,
+                .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
+                .inputs = dm644xevm_tvp5146_inputs,
+                .routes = dm644xevm_tvp5146_routes,
                 .can_route = 1,
                 .ccdc_if_params = {
                         .if_type = VPFE_BT656,
@@ -243,15 +244,15 @@ static struct vpfe_subdev_info vpfe_sub_devs[] = {
                 },
                 .board_info = {
                         I2C_BOARD_INFO("tvp5146", 0x5d),
-                        .platform_data = &tvp5146_pdata,
+                        .platform_data = &dm644xevm_tvp5146_pdata,
                 },
         },
 };
 
-static struct vpfe_config vpfe_cfg = {
-        .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+static struct vpfe_config dm644xevm_capture_cfg = {
+        .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
         .i2c_adapter_id = 1,
-        .sub_devs = vpfe_sub_devs,
+        .sub_devs = dm644xevm_vpfe_sub_devs,
         .card_name = "DM6446 EVM",
         .ccdc = "DM6446 CCDC",
 };
@@ -612,6 +613,113 @@ static void __init evm_init_i2c(void)
         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 }
 
+#define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
+
+/* venc standard timings */
+static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
+        {
+                .name           = "ntsc",
+                .timings_type   = VPBE_ENC_STD,
+                .timings        = {V4L2_STD_525_60},
+                .interlaced     = 1,
+                .xres           = 720,
+                .yres           = 480,
+                .aspect         = {11, 10},
+                .fps            = {30000, 1001},
+                .left_margin    = 0x79,
+                .upper_margin   = 0x10,
+        },
+        {
+                .name           = "pal",
+                .timings_type   = VPBE_ENC_STD,
+                .timings        = {V4L2_STD_625_50},
+                .interlaced     = 1,
+                .xres           = 720,
+                .yres           = 576,
+                .aspect         = {54, 59},
+                .fps            = {25, 1},
+                .left_margin    = 0x7e,
+                .upper_margin   = 0x16,
+        },
+};
+
+/* venc dv preset timings */
+static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
+        {
+                .name           = "480p59_94",
+                .timings_type   = VPBE_ENC_DV_PRESET,
+                .timings        = {V4L2_DV_480P59_94},
+                .interlaced     = 0,
+                .xres           = 720,
+                .yres           = 480,
+                .aspect         = {1, 1},
+                .fps            = {5994, 100},
+                .left_margin    = 0x80,
+                .upper_margin   = 0x20,
+        },
+        {
+                .name           = "576p50",
+                .timings_type   = VPBE_ENC_DV_PRESET,
+                .timings        = {V4L2_DV_576P50},
+                .interlaced     = 0,
+                .xres           = 720,
+                .yres           = 576,
+                .aspect         = {1, 1},
+                .fps            = {50, 1},
+                .left_margin    = 0x7e,
+                .upper_margin   = 0x30,
+        },
+};
+
+/*
+ * The outputs available from VPBE + encoders. Keep the order same
+ * as that of encoders. First those from venc followed by that from
+ * encoders. Index in the output refers to index on a particular encoder.
+ * Driver uses this index to pass it to encoder when it supports more
+ * than one output. Userspace applications use index of the array to
+ * set an output.
+ */
+static struct vpbe_output dm644xevm_vpbe_outputs[] = {
+        {
+                .output         = {
+                        .index          = 0,
+                        .name           = "Composite",
+                        .type           = V4L2_OUTPUT_TYPE_ANALOG,
+                        .std            = VENC_STD_ALL,
+                        .capabilities   = V4L2_OUT_CAP_STD,
+                },
+                .subdev_name    = VPBE_VENC_SUBDEV_NAME,
+                .default_mode   = "ntsc",
+                .num_modes      = ARRAY_SIZE(dm644xevm_enc_std_timing),
+                .modes          = dm644xevm_enc_std_timing,
+        },
+        {
+                .output         = {
+                        .index          = 1,
+                        .name           = "Component",
+                        .type           = V4L2_OUTPUT_TYPE_ANALOG,
+                        .capabilities   = V4L2_OUT_CAP_PRESETS,
+                },
+                .subdev_name    = VPBE_VENC_SUBDEV_NAME,
+                .default_mode   = "480p59_94",
+                .num_modes      = ARRAY_SIZE(dm644xevm_enc_preset_timing),
+                .modes          = dm644xevm_enc_preset_timing,
+        },
+};
+
+static struct vpbe_config dm644xevm_display_cfg = {
+        .module_name    = "dm644x-vpbe-display",
+        .i2c_adapter_id = 1,
+        .osd            = {
+                .module_name    = VPBE_OSD_SUBDEV_NAME,
+        },
+        .venc           = {
+                .module_name    = VPBE_VENC_SUBDEV_NAME,
+        },
+        .num_outputs    = ARRAY_SIZE(dm644xevm_vpbe_outputs),
+        .outputs        = dm644xevm_vpbe_outputs,
+};
+
 static struct platform_device *davinci_evm_devices[] __initdata = {
         &davinci_fb_device,
         &rtc_dev,
@@ -624,8 +732,6 @@ static struct davinci_uart_config uart_config __initdata = {
 static void __init
 davinci_evm_map_io(void)
 {
-        /* setup input configuration for VPFE input devices */
-        dm644x_set_vpfe_config(&vpfe_cfg);
         dm644x_init();
 }
 
@@ -697,6 +803,7 @@ static __init void davinci_evm_init(void)
         evm_init_i2c();
 
         davinci_setup_mmc(0, &dm6446evm_mmc_config);
+        dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
 
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_evm_snd_data);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 872ac69fa04..d72ab948d63 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -36,7 +36,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm646x.h>
 #include <mach/common.h>
 #include <mach/serial.h>
 #include <mach/i2c.h>
@@ -45,6 +44,7 @@
 #include <mach/cdce949.h>
 #include <mach/aemif.h>
 
+#include "davinci.h"
 #include "clock.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
@@ -410,8 +410,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_delay      = 0 /* usec */,
 };
 
-#define VIDCLKCTL_OFFSET        (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
-#define VSCLKDIS_OFFSET         (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
 #define VCH2CLK_MASK            (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
 #define VCH2CLK_SYSCLK8         (BIT(9))
 #define VCH2CLK_AUXCLK          (BIT(9) | BIT(8))
@@ -429,8 +427,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
 #define TVP5147_CH0             "tvp514x-0"
 #define TVP5147_CH1             "tvp514x-1"
 
-static void __iomem *vpif_vidclkctl_reg;
-static void __iomem *vpif_vsclkdis_reg;
 /* spin lock for updating above registers */
 static spinlock_t vpif_reg_lock;
 
@@ -441,14 +437,14 @@ static int set_vpif_clock(int mux_mode, int hd)
         int val = 0;
         int err = 0;
 
-        if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
+        if (!cpld_client)
                 return -ENXIO;
 
         /* disable the clock */
         spin_lock_irqsave(&vpif_reg_lock, flags);
-        value = __raw_readl(vpif_vsclkdis_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         value |= (VIDCH3CLK | VIDCH2CLK);
-        __raw_writel(value, vpif_vsclkdis_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         spin_unlock_irqrestore(&vpif_reg_lock, flags);
 
         val = i2c_smbus_read_byte(cpld_client);
@@ -464,7 +460,7 @@ static int set_vpif_clock(int mux_mode, int hd)
         if (err)
                 return err;
 
-        value = __raw_readl(vpif_vidclkctl_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
         value &= ~(VCH2CLK_MASK);
         value &= ~(VCH3CLK_MASK);
 
@@ -473,13 +469,13 @@ static int set_vpif_clock(int mux_mode, int hd)
         else
                 value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
 
-        __raw_writel(value, vpif_vidclkctl_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
 
         spin_lock_irqsave(&vpif_reg_lock, flags);
-        value = __raw_readl(vpif_vsclkdis_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         /* enable the clock */
         value &= ~(VIDCH3CLK | VIDCH2CLK);
-        __raw_writel(value, vpif_vsclkdis_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         spin_unlock_irqrestore(&vpif_reg_lock, flags);
 
         return 0;
@@ -564,7 +560,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
         int val;
         u32 value;
 
-        if (!vpif_vidclkctl_reg || !cpld_client)
+        if (!cpld_client)
                 return -ENXIO;
 
         val = i2c_smbus_read_byte(cpld_client);
@@ -572,7 +568,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
                 return val;
 
         spin_lock_irqsave(&vpif_reg_lock, flags);
-        value = __raw_readl(vpif_vidclkctl_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
         if (mux_mode) {
                 val &= VPIF_INPUT_TWO_CHANNEL;
                 value |= VIDCH1CLK;
@@ -580,7 +576,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
                 val |= VPIF_INPUT_ONE_CHANNEL;
                 value &= ~VIDCH1CLK;
         }
-        __raw_writel(value, vpif_vidclkctl_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
         spin_unlock_irqrestore(&vpif_reg_lock, flags);
 
         err = i2c_smbus_write_byte(cpld_client, val);
@@ -674,12 +670,6 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
 
 static void __init evm_init_video(void)
 {
-        vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
-        vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
-        if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
-                pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
-                return;
-        }
         spin_lock_init(&vpif_reg_lock);
 
         dm646x_setup_vpif(&dm646x_vpif_display_config,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 8d34f513d41..a772bb45570 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -30,7 +30,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm644x.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
@@ -39,6 +38,8 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 #define NEUROS_OSD2_PHY_ID              "davinci_mdio-0:01"
 #define LXT971_PHY_ID                   0x001378e2
 #define LXT971_PHY_MASK                 0xfffffff0
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 31da3c5b2ba..76e67509610 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -35,13 +35,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-#include <mach/dm644x.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 #define SFFSDR_PHY_ID           "davinci_mdio-0:01"
 static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
         /* U-Boot Environment: Block 0
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 5bba7070f27..031048fec9f 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -95,7 +95,7 @@ static int davinci_target(struct cpufreq_policy *policy,
         if (freqs.old == freqs.new)
                 return ret;
 
-        dev_dbg(&cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
+        dev_dbg(cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
 
         ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
                                                 freqs.new, relation, &idx);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 992c4c41018..b44dc844e15 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1026,7 +1026,7 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 }
 #endif
 
-int da850_register_pm(struct platform_device *pdev)
+int __init da850_register_pm(struct platform_device *pdev)
 {
         int ret;
         struct davinci_pm_config *pdata = pdev->dev.platform_data;
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
new file mode 100644
index 00000000000..3e519dad5bb
--- /dev/null
+++ b/arch/arm/mach-davinci/davinci.h
@@ -0,0 +1,102 @@
+/*
+ * This file contains the processor specific definitions
+ * of the TI DM644x, DM355, DM365, and DM646x.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ * Copyright (c) 2007 Deep Root Systems, LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DAVINCI_H
+#define __DAVINCI_H
+
+#include <linux/clk.h>
+#include <linux/videodev2.h>
+#include <linux/davinci_emac.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <mach/asp.h>
+#include <mach/keyscan.h>
+#include <mach/hardware.h>
+
+#include <media/davinci/vpfe_capture.h>
+#include <media/davinci/vpif_types.h>
+#include <media/davinci/vpss.h>
+#include <media/davinci/vpbe_types.h>
+#include <media/davinci/vpbe_venc.h>
+#include <media/davinci/vpbe.h>
+#include <media/davinci/vpbe_osd.h>
+
+#define DAVINCI_SYSTEM_MODULE_BASE      0x01c40000
+#define SYSMOD_VIDCLKCTL                0x38
+#define SYSMOD_VPSS_CLKCTL              0x44
+#define SYSMOD_VDD3P3VPWDN              0x48
+#define SYSMOD_VSCLKDIS                 0x6c
+#define SYSMOD_PUPDCTL1                 0x7c
+
+extern void __iomem *davinci_sysmod_base;
+#define DAVINCI_SYSMOD_VIRT(x)  (davinci_sysmod_base + (x))
+void davinci_map_sysmod(void);
+
+/* DM355 base addresses */
+#define DM355_ASYNC_EMIF_CONTROL_BASE   0x01e10000
+#define DM355_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
+
+#define ASP1_TX_EVT_EN  1
+#define ASP1_RX_EVT_EN  2
+
+/* DM365 base addresses */
+#define DM365_ASYNC_EMIF_CONTROL_BASE   0x01d10000
+#define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
+#define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
+
+/* DM644x base addresses */
+#define DM644X_ASYNC_EMIF_CONTROL_BASE  0x01e00000
+#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
+#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
+#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
+
+/* DM646x base addresses */
+#define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
+#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
+
+/* DM355 function declarations */
+void __init dm355_init(void);
+void dm355_init_spi0(unsigned chipselect_mask,
+                struct spi_board_info *info, unsigned len);
+void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
+void dm355_set_vpfe_config(struct vpfe_config *cfg);
+
+/* DM365 function declarations */
+void __init dm365_init(void);
+void __init dm365_init_asp(struct snd_platform_data *pdata);
+void __init dm365_init_vc(struct snd_platform_data *pdata);
+void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
+void __init dm365_init_rtc(void);
+void dm365_init_spi0(unsigned chipselect_mask,
+                        struct spi_board_info *info, unsigned len);
+void dm365_set_vpfe_config(struct vpfe_config *cfg);
+
+/* DM644x function declarations */
+void __init dm644x_init(void);
+void __init dm644x_init_asp(struct snd_platform_data *pdata);
+int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
+
+/* DM646x function declarations */
+void __init dm646x_init(void);
+void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
+void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
+int __init dm646x_init_edma(struct edma_rsv_info *rsv);
+void dm646x_video_init(void);
+void dm646x_setup_vpif(struct vpif_display_config *,
+                       struct vpif_capture_config *);
+#endif /*__DAVINCI_H */
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 50c0156b426..d2f9666284a 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,6 +23,7 @@
 #include <mach/mmc.h>
 #include <mach/time.h>
 
+#include "davinci.h"
 #include "clock.h"
 
 #define DAVINCI_I2C_BASE             0x01C21000
@@ -33,8 +34,19 @@
 #define DM365_MMCSD0_BASE            0x01D11000
 #define DM365_MMCSD1_BASE            0x01D00000
 
-/* System control register offsets */
-#define DM64XX_VDD3P3V_PWDN     0x48
+void __iomem  *davinci_sysmod_base;
+
+void davinci_map_sysmod(void)
+{
+        davinci_sysmod_base = ioremap_nocache(DAVINCI_SYSTEM_MODULE_BASE,
+                                              0x800);
+        /*
+         * Throw a bug since a lot of board initialization code depends
+         * on system module availability. ioremap() failing this early
+         * need careful looking into anyway.
+         */
+        BUG_ON(!davinci_sysmod_base);
+}
 
 static struct resource i2c_resources[] = {
         {
@@ -212,12 +224,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         davinci_cfg_reg(DM355_SD1_DATA2);
                         davinci_cfg_reg(DM355_SD1_DATA3);
                 } else if (cpu_is_davinci_dm365()) {
-                        void __iomem *pupdctl1 =
-                                IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
-
                         /* Configure pull down control */
-                        __raw_writel((__raw_readl(pupdctl1) & ~0xfc0),
-                                        pupdctl1);
+                        unsigned v;
+
+                        v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
+                        __raw_writel(v & ~0xfc0,
+                                        DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
 
                         mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
                         mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
@@ -246,11 +258,9 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
                 } else if (cpu_is_davinci_dm644x()) {
                         /* REVISIT: should this be in board-init code? */
-                        void __iomem *base =
-                                IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
-
                         /* Power-on 3.3V IO cells */
-                        __raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
+                        __raw_writel(0,
+                                DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
                         /*Set up the pull regiter for MMC */
                         davinci_cfg_reg(DM644X_MSTK);
                 }
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 19667cfc5de..fd3d09aa6cd 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -18,7 +18,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm355.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/psc.h>
@@ -31,6 +30,7 @@
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
@@ -871,6 +871,7 @@ void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
 void __init dm355_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm355);
+        davinci_map_sysmod();
 }
 
 static int __init dm355_init_devices(void)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f15b435cc65..1a2e953082b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -21,7 +21,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm365.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/psc.h>
@@ -35,11 +34,28 @@
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
 
+/* Base of key scan register bank */
+#define DM365_KEYSCAN_BASE              0x01c69400
+
+#define DM365_RTC_BASE                  0x01c69000
+
+#define DAVINCI_DM365_VC_BASE           0x01d0c000
+#define DAVINCI_DMA_VC_TX               2
+#define DAVINCI_DMA_VC_RX               3
+
+#define DM365_EMAC_BASE                 0x01d07000
+#define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
+#define DM365_EMAC_CNTRL_OFFSET         0x0000
+#define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
+#define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
+#define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
+
 static struct pll_data pll1_data = {
         .num            = 1,
         .phys_base      = DAVINCI_PLL1_BASE,
@@ -1122,6 +1138,7 @@ void __init dm365_init_rtc(void)
 void __init dm365_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm365);
+        davinci_map_sysmod();
 }
 
 static struct resource dm365_vpss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 43a48ee1917..c8b866657fc 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -15,7 +15,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm644x.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/irqs.h>
@@ -27,6 +26,7 @@
 #include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
@@ -35,6 +35,13 @@
  */
 #define DM644X_REF_FREQ         27000000
 
+#define DM644X_EMAC_BASE                0x01c80000
+#define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
+#define DM644X_EMAC_CNTRL_OFFSET        0x0000
+#define DM644X_EMAC_CNTRL_MOD_OFFSET    0x1000
+#define DM644X_EMAC_CNTRL_RAM_OFFSET    0x2000
+#define DM644X_EMAC_CNTRL_RAM_SIZE      0x2000
+
 static struct pll_data pll1_data = {
         .num       = 1,
         .phys_base = DAVINCI_PLL1_BASE,
@@ -587,13 +594,15 @@ static struct platform_device dm644x_asp_device = {
         .resource       = dm644x_asp_resources,
 };
 
+#define DM644X_VPSS_BASE        0x01c73400
+
 static struct resource dm644x_vpss_resources[] = {
         {
                 /* VPSS Base address */
                 .name           = "vpss",
-                .start          = 0x01c73400,
-                .end            = 0x01c73400 + 0xff,
-                .flags          = IORESOURCE_MEM,
+                .start          = DM644X_VPSS_BASE,
+                .end            = DM644X_VPSS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
         },
 };
 
@@ -605,7 +614,7 @@ static struct platform_device dm644x_vpss_device = {
         .resource               = dm644x_vpss_resources,
 };
 
-static struct resource vpfe_resources[] = {
+static struct resource dm644x_vpfe_resources[] = {
         {
                 .start          = IRQ_VDINT0,
                 .end            = IRQ_VDINT0,
@@ -618,7 +627,7 @@ static struct resource vpfe_resources[] = {
         },
 };
 
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
 static struct resource dm644x_ccdc_resource[] = {
         /* CCDC Base address */
         {
@@ -634,27 +643,149 @@ static struct platform_device dm644x_ccdc_dev = {
         .num_resources  = ARRAY_SIZE(dm644x_ccdc_resource),
         .resource       = dm644x_ccdc_resource,
         .dev = {
-                .dma_mask               = &vpfe_capture_dma_mask,
+                .dma_mask               = &dm644x_video_dma_mask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
 };
 
-static struct platform_device vpfe_capture_dev = {
+static struct platform_device dm644x_vpfe_dev = {
         .name           = CAPTURE_DRV_NAME,
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(vpfe_resources),
-        .resource       = vpfe_resources,
+        .num_resources  = ARRAY_SIZE(dm644x_vpfe_resources),
+        .resource       = dm644x_vpfe_resources,
         .dev = {
-                .dma_mask               = &vpfe_capture_dma_mask,
+                .dma_mask               = &dm644x_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+#define DM644X_OSD_BASE         0x01c72600
+
+static struct resource dm644x_osd_resources[] = {
+        {
+                .start  = DM644X_OSD_BASE,
+                .end    = DM644X_OSD_BASE + 0x1ff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct osd_platform_data dm644x_osd_data = {
+        .vpbe_type     = VPBE_VERSION_1,
+};
+
+static struct platform_device dm644x_osd_dev = {
+        .name           = VPBE_OSD_SUBDEV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm644x_osd_resources),
+        .resource       = dm644x_osd_resources,
+        .dev            = {
+                .dma_mask               = &dm644x_video_dma_mask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &dm644x_osd_data,
         },
 };
 
-void dm644x_set_vpfe_config(struct vpfe_config *cfg)
+#define DM644X_VENC_BASE                0x01c72400
+
+static struct resource dm644x_venc_resources[] = {
+        {
+                .start  = DM644X_VENC_BASE,
+                .end    = DM644X_VENC_BASE + 0x17f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+#define DM644X_VPSS_MUXSEL_PLL2_MODE          BIT(0)
+#define DM644X_VPSS_MUXSEL_VPBECLK_MODE       BIT(1)
+#define DM644X_VPSS_VENCLKEN                  BIT(3)
+#define DM644X_VPSS_DACCLKEN                  BIT(4)
+
+static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
+                                   unsigned int mode)
 {
-        vpfe_capture_dev.dev.platform_data = cfg;
+        int ret = 0;
+        u32 v = DM644X_VPSS_VENCLKEN;
+
+        switch (type) {
+        case VPBE_ENC_STD:
+                v |= DM644X_VPSS_DACCLKEN;
+                writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
+                break;
+        case VPBE_ENC_DV_PRESET:
+                switch (mode) {
+                case V4L2_DV_480P59_94:
+                case V4L2_DV_576P50:
+                        v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
+                             DM644X_VPSS_DACCLKEN;
+                        writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
+                        break;
+                case V4L2_DV_720P60:
+                case V4L2_DV_1080I60:
+                case V4L2_DV_1080P30:
+                        /*
+                         * For HD, use external clock source since
+                         * HD requires higher clock rate
+                         */
+                        v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
+                        writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
+                        break;
+                default:
+                        ret = -EINVAL;
+                        break;
+                }
+                break;
+        default:
+                ret  = -EINVAL;
+        }
+
+        return ret;
 }
 
+static struct resource dm644x_v4l2_disp_resources[] = {
+        {
+                .start  = IRQ_VENCINT,
+                .end    = IRQ_VENCINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dm644x_vpbe_display = {
+        .name           = "vpbe-v4l2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm644x_v4l2_disp_resources),
+        .resource       = dm644x_v4l2_disp_resources,
+        .dev            = {
+                .dma_mask               = &dm644x_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct venc_platform_data dm644x_venc_pdata = {
+        .venc_type      = VPBE_VERSION_1,
+        .setup_clock    = dm644x_venc_setup_clock,
+};
+
+static struct platform_device dm644x_venc_dev = {
+        .name           = VPBE_VENC_SUBDEV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm644x_venc_resources),
+        .resource       = dm644x_venc_resources,
+        .dev            = {
+                .dma_mask               = &dm644x_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &dm644x_venc_pdata,
+        },
+};
+
+static struct platform_device dm644x_vpbe_dev = {
+        .name           = "vpbe_controller",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &dm644x_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm644x_io_desc[] = {
@@ -779,6 +910,35 @@ void __init dm644x_init_asp(struct snd_platform_data *pdata)
 void __init dm644x_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm644x);
+        davinci_map_sysmod();
+}
+
+int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
+                                struct vpbe_config *vpbe_cfg)
+{
+        if (vpfe_cfg || vpbe_cfg)
+                platform_device_register(&dm644x_vpss_device);
+
+        if (vpfe_cfg) {
+                dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
+                platform_device_register(&dm644x_ccdc_dev);
+                platform_device_register(&dm644x_vpfe_dev);
+                /* Add ccdc clock aliases */
+                clk_add_alias("master", dm644x_ccdc_dev.name,
+                              "vpss_master", NULL);
+                clk_add_alias("slave", dm644x_ccdc_dev.name,
+                              "vpss_slave", NULL);
+        }
+
+        if (vpbe_cfg) {
+                dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
+                platform_device_register(&dm644x_osd_dev);
+                platform_device_register(&dm644x_venc_dev);
+                platform_device_register(&dm644x_vpbe_dev);
+                platform_device_register(&dm644x_vpbe_display);
+        }
+
+        return 0;
 }
 
 static int __init dm644x_init_devices(void)
@@ -786,9 +946,6 @@ static int __init dm644x_init_devices(void)
         if (!cpu_is_davinci_dm644x())
                 return 0;
 
-        /* Add ccdc clock aliases */
-        clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
-        clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
         platform_device_register(&dm644x_edma_device);
 
         platform_device_register(&dm644x_mdio_device);
@@ -796,10 +953,6 @@ static int __init dm644x_init_devices(void)
         clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
                       NULL, &dm644x_emac_device.dev);
 
-        platform_device_register(&dm644x_vpss_device);
-        platform_device_register(&dm644x_ccdc_dev);
-        platform_device_register(&vpfe_capture_dev);
-
         return 0;
 }
 postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 00f774394b1..9eb87c1d1ed 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -16,7 +16,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm646x.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/irqs.h>
@@ -28,12 +27,11 @@
 #include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
 #define DAVINCI_VPIF_BASE       (0x01C12000)
-#define VDD3P3V_PWDN_OFFSET     (0x48)
-#define VSCLKDIS_OFFSET         (0x6C)
 
 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
                                         BIT_MASK(0))
@@ -46,6 +44,13 @@
 #define DM646X_REF_FREQ         27000000
 #define DM646X_AUX_FREQ         24000000
 
+#define DM646X_EMAC_BASE                0x01c80000
+#define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
+#define DM646X_EMAC_CNTRL_OFFSET        0x0000
+#define DM646X_EMAC_CNTRL_MOD_OFFSET    0x1000
+#define DM646X_EMAC_CNTRL_RAM_OFFSET    0x2000
+#define DM646X_EMAC_CNTRL_RAM_SIZE      0x2000
+
 static struct pll_data pll1_data = {
         .num       = 1,
         .phys_base = DAVINCI_PLL1_BASE,
@@ -873,15 +878,14 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
                        struct vpif_capture_config *capture_config)
 {
         unsigned int value;
-        void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 
-        value = __raw_readl(base + VSCLKDIS_OFFSET);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         value &= ~VSCLKDIS_MASK;
-        __raw_writel(value, base + VSCLKDIS_OFFSET);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 
-        value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
         value &= ~VDD3P3V_VID_MASK;
-        __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 
         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
@@ -905,6 +909,7 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 void __init dm646x_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm646x);
+        davinci_map_sysmod();
 }
 
 static int __init dm646x_init_devices(void)
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index da90103a313..fd33919c95d 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1508,12 +1508,8 @@ static int __init edma_probe(struct platform_device *pdev)
                         goto fail;
                 }
 
-                /* Everything lives on transfer controller 1 until otherwise
-                 * specified. This way, long transfers on the low priority queue
-                 * started by the codec engine will not cause audio defects.
-                 */
                 for (i = 0; i < edma_cc[j]->num_channels; i++)
-                        map_dmach_queue(j, i, EVENTQ_1);
+                        map_dmach_queue(j, i, info[j]->default_queue);
 
                 queue_tc_mapping = info[j]->queue_tc_mapping;
                 queue_priority_mapping = info[j]->queue_priority_mapping;
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
deleted file mode 100644
index 36dff4a0ce3..00000000000
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Chip specific defines for DM355 SoC
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_DM355_H
-#define __ASM_ARCH_DM355_H
-
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <media/davinci/vpfe_capture.h>
-
-#define DM355_ASYNC_EMIF_CONTROL_BASE   0x01E10000
-#define DM355_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
-
-#define ASP1_TX_EVT_EN  1
-#define ASP1_RX_EVT_EN  2
-
-struct spi_board_info;
-
-void __init dm355_init(void);
-void dm355_init_spi0(unsigned chipselect_mask,
-                struct spi_board_info *info, unsigned len);
-void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
-void dm355_set_vpfe_config(struct vpfe_config *cfg);
-
-#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 2563bf4e93a..b9bf3d6a442 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -1,52 +1 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_DM365_H
-#define __ASM_ARCH_DM665_H
-
-#include <linux/platform_device.h>
-#include <linux/davinci_emac.h>
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <mach/keyscan.h>
-#include <media/davinci/vpfe_capture.h>
-
-#define DM365_EMAC_BASE                 (0x01D07000)
-#define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
-#define DM365_EMAC_CNTRL_OFFSET         (0x0000)
-#define DM365_EMAC_CNTRL_MOD_OFFSET     (0x3000)
-#define DM365_EMAC_CNTRL_RAM_OFFSET     (0x1000)
-#define DM365_EMAC_CNTRL_RAM_SIZE       (0x2000)
-
-/* Base of key scan register bank */
-#define DM365_KEYSCAN_BASE              (0x01C69400)
-
-#define DM365_RTC_BASE                  (0x01C69000)
-
-#define DAVINCI_DM365_VC_BASE           (0x01D0C000)
-#define DAVINCI_DMA_VC_TX               2
-#define DAVINCI_DMA_VC_RX               3
-
-#define DM365_ASYNC_EMIF_CONTROL_BASE   0x01D10000
-#define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
-#define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
-
-void __init dm365_init(void);
-void __init dm365_init_asp(struct snd_platform_data *pdata);
-void __init dm365_init_vc(struct snd_platform_data *pdata);
-void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
-void __init dm365_init_rtc(void);
-void dm365_init_spi0(unsigned chipselect_mask,
-                        struct spi_board_info *info, unsigned len);
-
-void dm365_set_vpfe_config(struct vpfe_config *cfg);
-#endif /* __ASM_ARCH_DM365_H */
+/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
deleted file mode 100644
index 5a1b26d4e68..00000000000
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file contains the processor specific definitions
- * of the TI DM644x.
- *
- * Copyright (C) 2008 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#ifndef __ASM_ARCH_DM644X_H
-#define __ASM_ARCH_DM644X_H
-
-#include <linux/davinci_emac.h>
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <media/davinci/vpfe_capture.h>
-
-#define DM644X_EMAC_BASE                (0x01C80000)
-#define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
-#define DM644X_EMAC_CNTRL_OFFSET        (0x0000)
-#define DM644X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
-#define DM644X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM644X_EMAC_CNTRL_RAM_SIZE      (0x2000)
-
-#define DM644X_ASYNC_EMIF_CONTROL_BASE  0x01E00000
-#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
-#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
-
-void __init dm644x_init(void);
-void __init dm644x_init_asp(struct snd_platform_data *pdata);
-void dm644x_set_vpfe_config(struct vpfe_config *cfg);
-
-#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index a8ee6c9f0bb..b9bf3d6a442 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -1,41 +1 @@
-/*
- * Chip specific defines for DM646x SoC
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_DM646X_H
-#define __ASM_ARCH_DM646X_H
-
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <linux/i2c.h>
-#include <linux/videodev2.h>
-#include <linux/davinci_emac.h>
-#include <media/davinci/vpif_types.h>
-
-#define DM646X_EMAC_BASE                (0x01C80000)
-#define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
-#define DM646X_EMAC_CNTRL_OFFSET        (0x0000)
-#define DM646X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
-#define DM646X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM646X_EMAC_CNTRL_RAM_SIZE      (0x2000)
-
-#define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
-#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
-
-void __init dm646x_init(void);
-void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
-void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
-int __init dm646x_init_edma(struct edma_rsv_info *rsv);
-
-void dm646x_video_init(void);
-
-void dm646x_setup_vpif(struct vpif_display_config *,
-                       struct vpif_capture_config *);
-
-#endif /* __ASM_ARCH_DM646X_H */
+/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index 20c77f29bf0..7e84c906cef 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -250,6 +250,11 @@ struct edma_soc_info {
         unsigned        n_slot;
         unsigned        n_tc;
         unsigned        n_cc;
+        /*
+         * Default queue is expected to be a low-priority queue.
+         * This way, long transfers on the default queue started
+         * by the codec engine will not cause audio defects.
+         */
         enum dma_event_q        default_queue;
 
         /* Resource reservation for other cores */
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index e14c0dc0e12..c1661d2feca 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -11,17 +11,11 @@
 #include <mach/io.h>
 #include <mach/irqs.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 ldr \base, =davinci_intc_base
                 ldr \base, [\base]
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 #if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
                 ldr \tmp, =davinci_intc_type
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 414e0b93e74..0209b1fc22a 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -19,8 +19,6 @@
  * and the chip/board init code should then explicitly include
  * <chipname>.h
  */
-#define DAVINCI_SYSTEM_MODULE_BASE        0x01C40000
-
 /*
  * I/O mapping
  */
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
deleted file mode 100644
index fcb7a015aba..00000000000
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * DaVinci system defines
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/common.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
index e84c78c2a8b..72d622baaad 100644
--- a/arch/arm/mach-dove/include/mach/entry-macro.S
+++ b/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IRQ_VIRT_BASE
         .endm
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
deleted file mode 100644
index 3027954f616..00000000000
--- a/arch/arm/mach-dove/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 52e96d397ba..48a032005ea 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -69,7 +69,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[0].flags = IORESOURCE_IO;
         if (request_resource(&ioport_resource, &pp->res[0]))
                 panic("Request PCIe IO resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[0]);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -88,7 +88,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[1].flags = IORESOURCE_MEM;
         if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[1]);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 0c40e59af73..8c9f56a3e8e 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -30,10 +30,7 @@
 
 #include <asm/mach/time.h>
 
-#define IRQ_MASK                0xfe000000      /* read */
-#define IRQ_MSET                0xfe000000      /* write */
-#define IRQ_STAT                0xff000000      /* read */
-#define IRQ_MCLR                0xff000000      /* write */
+#include "core.h"
 
 static void ebsa110_mask_irq(struct irq_data *d)
 {
@@ -79,22 +76,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = {
         {       /* IRQ_STAT/IRQ_MCLR */
                 .virtual        = IRQ_STAT,
                 .pfn            = __phys_to_pfn(TRICK4_PHYS),
-                .length         = PGDIR_SIZE,
+                .length         = TRICK4_SIZE,
                 .type           = MT_DEVICE
         }, {    /* IRQ_MASK/IRQ_MSET */
                 .virtual        = IRQ_MASK,
                 .pfn            = __phys_to_pfn(TRICK3_PHYS),
-                .length         = PGDIR_SIZE,
+                .length         = TRICK3_SIZE,
                 .type           = MT_DEVICE
         }, {    /* SOFT_BASE */
                 .virtual        = SOFT_BASE,
                 .pfn            = __phys_to_pfn(TRICK1_PHYS),
-                .length         = PGDIR_SIZE,
+                .length         = TRICK1_SIZE,
                 .type           = MT_DEVICE
         }, {    /* PIT_BASE */
                 .virtual        = PIT_BASE,
                 .pfn            = __phys_to_pfn(TRICK0_PHYS),
-                .length         = PGDIR_SIZE,
+                .length         = TRICK0_SIZE,
                 .type           = MT_DEVICE
         },
 
@@ -271,8 +268,33 @@ static struct platform_device *ebsa110_devices[] = {
         &am79c961_device,
 };
 
+/*
+ * EBSA110 idling methodology:
+ *
+ * We can not execute the "wait for interrupt" instruction since that
+ * will stop our MCLK signal (which provides the clock for the glue
+ * logic, and therefore the timer interrupt).
+ *
+ * Instead, we spin, polling the IRQ_STAT register for the occurrence
+ * of any interrupt with core clock down to the memory clock.
+ */
+static void ebsa110_idle(void)
+{
+        const char *irq_stat = (char *)0xff000000;
+
+        /* disable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
+
+        /* wait for an interrupt to occur */
+        while (!*irq_stat);
+
+        /* enable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
+}
+
 static int __init ebsa110_init(void)
 {
+        arm_pm_idle = ebsa110_idle;
         return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
 }
 
diff --git a/arch/arm/mach-ebsa110/core.h b/arch/arm/mach-ebsa110/core.h
new file mode 100644
index 00000000000..c93c9e43012
--- /dev/null
+++ b/arch/arm/mach-ebsa110/core.h
@@ -0,0 +1,41 @@
+/*
+ *  Copyright (C) 1996-2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the core hardware definitions of the EBSA-110.
+ */
+#ifndef CORE_H
+#define CORE_H
+
+/* Physical addresses/sizes */
+#define ISAMEM_PHYS             0xe0000000
+#define ISAMEM_SIZE             0x10000000
+
+#define ISAIO_PHYS              0xf0000000
+#define ISAIO_SIZE              PGDIR_SIZE
+
+#define TRICK0_PHYS             0xf2000000
+#define TRICK0_SIZE             PGDIR_SIZE
+#define TRICK1_PHYS             0xf2400000
+#define TRICK1_SIZE             PGDIR_SIZE
+#define TRICK2_PHYS             0xf2800000
+#define TRICK3_PHYS             0xf2c00000
+#define TRICK3_SIZE             PGDIR_SIZE
+#define TRICK4_PHYS             0xf3000000
+#define TRICK4_SIZE             PGDIR_SIZE
+#define TRICK5_PHYS             0xf3400000
+#define TRICK6_PHYS             0xf3800000
+#define TRICK7_PHYS             0xf3c00000
+
+/* Virtual addresses */
+#define PIT_BASE                0xfc000000      /* trick 0 */
+#define SOFT_BASE               0xfd000000      /* trick 1 */
+#define IRQ_MASK                0xfe000000      /* trick 3 - read */
+#define IRQ_MSET                0xfe000000      /* trick 3 - write */
+#define IRQ_STAT                0xff000000      /* trick 4 - read */
+#define IRQ_MCLR                0xff000000      /* trick 4 - write */
+
+#endif
diff --git a/arch/arm/mach-ebsa110/include/mach/entry-macro.S b/arch/arm/mach-ebsa110/include/mach/entry-macro.S
index cc3e5992f6b..14b110de78a 100644
--- a/arch/arm/mach-ebsa110/include/mach/entry-macro.S
+++ b/arch/arm/mach-ebsa110/include/mach/entry-macro.S
@@ -12,16 +12,10 @@
 
 #define IRQ_STAT                0xff000000      /* read */
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         mov     \base, #IRQ_STAT
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, stat, base, tmp
         ldrb    \stat, [\base]                  @ get interrupts
         mov     \irqnr, #0
diff --git a/arch/arm/mach-ebsa110/include/mach/hardware.h b/arch/arm/mach-ebsa110/include/mach/hardware.h
index 4b2fb774390..f4e5407bd00 100644
--- a/arch/arm/mach-ebsa110/include/mach/hardware.h
+++ b/arch/arm/mach-ebsa110/include/mach/hardware.h
@@ -12,48 +12,9 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-/*
- * The EBSA110 has a weird "ISA IO" region:
- *
- * Region 0 (addr = 0xf0000000 + io << 2)
- * --------------------------------------------------------
- * Physical region      IO region
- * f0000fe0 - f0000ffc  3f8 - 3ff  ttyS0
- * f0000e60 - f0000e64  398 - 399
- * f0000de0 - f0000dfc  378 - 37f  lp0
- * f0000be0 - f0000bfc  2f8 - 2ff  ttyS1
- *
- * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
- * --------------------------------------------------------
- * Physical region      IO region
- * f00014f1             a79        pnp write data
- * f00007c0 - f00007c1  3e0 - 3e1  pcmcia
- * f00004f1             279        pnp address
- * f0000440 - f000046c  220 - 236  eth0
- * f0000405             203        pnp read data
- */
-
-#define ISAMEM_PHYS             0xe0000000
-#define ISAMEM_SIZE             0x10000000
-
-#define ISAIO_PHYS              0xf0000000
-#define ISAIO_SIZE              PGDIR_SIZE
-
-#define TRICK0_PHYS             0xf2000000
-#define TRICK1_PHYS             0xf2400000
-#define TRICK2_PHYS             0xf2800000
-#define TRICK3_PHYS             0xf2c00000
-#define TRICK4_PHYS             0xf3000000
-#define TRICK5_PHYS             0xf3400000
-#define TRICK6_PHYS             0xf3800000
-#define TRICK7_PHYS             0xf3c00000
-
 #define ISAMEM_BASE             0xe0000000
 #define ISAIO_BASE              0xf0000000
 
-#define PIT_BASE                0xfc000000
-#define SOFT_BASE               0xfd000000
-
 /*
  * RAM definitions
  */
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
deleted file mode 100644
index 2e4af65edb6..00000000000
--- a/arch/arm/mach-ebsa110/include/mach/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  arch/arm/mach-ebsa110/include/mach/system.h
- *
- *  Copyright (C) 1996-2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-/*
- * EBSA110 idling methodology:
- *
- * We can not execute the "wait for interrupt" instruction since that
- * will stop our MCLK signal (which provides the clock for the glue
- * logic, and therefore the timer interrupt).
- *
- * Instead, we spin, polling the IRQ_STAT register for the occurrence
- * of any interrupt with core clock down to the memory clock.
- */
-static inline void arch_idle(void)
-{
-        const char *irq_stat = (char *)0xff000000;
-
-        /* disable clock switching */
-        asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
-
-        /* wait for an interrupt to occur */
-        while (!*irq_stat);
-
-        /* enable clock switching */
-        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
-}
-
-#endif
diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c
index c52e3047a7e..756cc377a73 100644
--- a/arch/arm/mach-ebsa110/io.c
+++ b/arch/arm/mach-ebsa110/io.c
@@ -177,6 +177,26 @@ void writesl(void __iomem *addr, const void *data, int len)
 }
 EXPORT_SYMBOL(writesl);
 
+/*
+ * The EBSA110 has a weird "ISA IO" region:
+ *
+ * Region 0 (addr = 0xf0000000 + io << 2)
+ * --------------------------------------------------------
+ * Physical region      IO region
+ * f0000fe0 - f0000ffc  3f8 - 3ff  ttyS0
+ * f0000e60 - f0000e64  398 - 399
+ * f0000de0 - f0000dfc  378 - 37f  lp0
+ * f0000be0 - f0000bfc  2f8 - 2ff  ttyS1
+ *
+ * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
+ * --------------------------------------------------------
+ * Physical region      IO region
+ * f00014f1             a79        pnp write data
+ * f00007c0 - f00007c1  3e0 - 3e1  pcmcia
+ * f00004f1             279        pnp address
+ * f0000440 - f000046c  220 - 236  eth0
+ * f0000405             203        pnp read data
+ */
 #define SUPERIO_PORT(p) \
         (((p) >> 3) == (0x3f8 >> 3) || \
          ((p) >> 3) == (0x2f8 >> 3) || \
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index 101a3204438..99e14e36250 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -19,6 +19,8 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
+#include "core.h"
+
 static spinlock_t leds_lock;
 
 static void ebsa110_leds_event(led_event_t ledevt)
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 574209d9e24..0dc51f9462d 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -8,6 +8,9 @@ obj-			:=
 
 obj-$(CONFIG_EP93XX_DMA)        += dma.o
 
+obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
+AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
+
 obj-$(CONFIG_MACH_ADSSPHERE)    += adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)      += edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)    += gesbc9312.o
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 681e939407d..2d45947a303 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -20,6 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
         .phy_id         = 1,
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index ca4de710509..c95dbce2468 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -25,6 +25,7 @@
 
 #include <asm/div64.h>
 
+#include "soc.h"
 
 struct clk {
         struct clk      *parent;
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index b5c1dae8327..8d258958871 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -46,6 +46,7 @@
 
 #include <asm/hardware/vic.h>
 
+#include "soc.h"
 
 /*************************************************************************
  * Static I/O mappings that are needed for all EP93xx platforms
@@ -204,7 +205,6 @@ void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
 
         spin_unlock_irqrestore(&syscon_swlock, flags);
 }
-EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
 
 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 {
@@ -221,7 +221,6 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 
         spin_unlock_irqrestore(&syscon_swlock, flags);
 }
-EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
 
 /**
  * ep93xx_chip_revision() - returns the EP93xx chip revision
@@ -279,48 +278,14 @@ static struct amba_pl010_data ep93xx_uart_data = {
         .set_mctrl      = ep93xx_uart_set_mctrl,
 };
 
-static struct amba_device uart1_device = {
-        .dev            = {
-                .init_name      = "apb:uart1",
-                .platform_data  = &ep93xx_uart_data,
-        },
-        .res            = {
-                .start  = EP93XX_UART1_PHYS_BASE,
-                .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
-        .periphid       = 0x00041010,
-};
-
-static struct amba_device uart2_device = {
-        .dev            = {
-                .init_name      = "apb:uart2",
-                .platform_data  = &ep93xx_uart_data,
-        },
-        .res            = {
-                .start  = EP93XX_UART2_PHYS_BASE,
-                .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
-        .periphid       = 0x00041010,
-};
+static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
+        { IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
 
-static struct amba_device uart3_device = {
-        .dev            = {
-                .init_name      = "apb:uart3",
-                .platform_data  = &ep93xx_uart_data,
-        },
-        .res            = {
-                .start  = EP93XX_UART3_PHYS_BASE,
-                .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
-        .periphid       = 0x00041010,
-};
+static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
+        { IRQ_EP93XX_UART2 }, &ep93xx_uart_data);
 
+static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
+        { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
 
 static struct resource ep93xx_rtc_resource[] = {
         {
@@ -682,9 +647,19 @@ static struct platform_device ep93xx_fb_device = {
         .resource               = ep93xx_fb_resource,
 };
 
+/* The backlight use a single register in the framebuffer's register space */
+#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
+
+static struct resource ep93xx_bl_resources[] = {
+        DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
+                       EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
+};
+
 static struct platform_device ep93xx_bl_device = {
         .name           = "ep93xx-bl",
         .id             = -1,
+        .num_resources  = ARRAY_SIZE(ep93xx_bl_resources),
+        .resource       = ep93xx_bl_resources,
 };
 
 /**
@@ -879,11 +854,32 @@ void __init ep93xx_register_ac97(void)
         platform_device_register(&ep93xx_pcm_device);
 }
 
+/*************************************************************************
+ * EP93xx Watchdog
+ *************************************************************************/
+static struct resource ep93xx_wdt_resources[] = {
+        DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
+};
+
+static struct platform_device ep93xx_wdt_device = {
+        .name           = "ep93xx-wdt",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ep93xx_wdt_resources),
+        .resource       = ep93xx_wdt_resources,
+};
+
 void __init ep93xx_init_devices(void)
 {
         /* Disallow access to MaverickCrunch initially */
         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
 
+        /* Default all ports to GPIO */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
+                               EP93XX_SYSCON_DEVCFG_GONK |
+                               EP93XX_SYSCON_DEVCFG_EONIDE |
+                               EP93XX_SYSCON_DEVCFG_GONIDE |
+                               EP93XX_SYSCON_DEVCFG_HONIDE);
+
         /* Get the GPIO working early, other devices need it */
         platform_device_register(&ep93xx_gpio_device);
 
@@ -894,6 +890,7 @@ void __init ep93xx_init_devices(void)
         platform_device_register(&ep93xx_rtc_device);
         platform_device_register(&ep93xx_ohci_device);
         platform_device_register(&ep93xx_leds);
+        platform_device_register(&ep93xx_wdt_device);
 }
 
 void ep93xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/kernel/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S
index 0ec9bb48fab..0ec9bb48fab 100644
--- a/arch/arm/kernel/crunch-bits.S
+++ b/arch/arm/mach-ep93xx/crunch-bits.S
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/mach-ep93xx/crunch.c
index 25ef223ba7f..74753e2df60 100644
--- a/arch/arm/kernel/crunch.c
+++ b/arch/arm/mach-ep93xx/crunch.c
@@ -16,9 +16,11 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <mach/ep93xx-regs.h>
+
 #include <asm/thread_notify.h>
 
+#include "soc.h"
+
 struct crunch_state *crunch_owner;
 
 void crunch_task_release(struct thread_info *thread)
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index 5a257088125..16976d7bdc8 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -28,6 +28,8 @@
 #include <mach/dma.h>
 #include <mach/hardware.h>
 
+#include "soc.h"
+
 #define DMA_CHANNEL(_name, _base, _irq) \
         { .name = (_name), .base = (_base), .irq = (_irq) }
 
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index d115653edca..da9047d726f 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -43,6 +43,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static void __init edb93xx_register_flash(void)
 {
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index af46970dc58..fcdffbe49dc 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -20,6 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
         .phy_id         = 1,
diff --git a/arch/arm/mach-ep93xx/include/mach/entry-macro.S b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
deleted file mode 100644
index 9be6edcf904..00000000000
--- a/arch/arm/mach-ep93xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/entry-macro.S
- * IRQ demultiplexing for EP93xx
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index c4a7b84ef06..c64d7424660 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,40 +6,6 @@
 #define __ASM_ARCH_EP93XX_REGS_H
 
 /*
- * EP93xx Physical Memory Map:
- *
- * The ASDO pin is sampled at system reset to select a synchronous or
- * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
- * the synchronous boot mode is selected.  When ASDO is "0" (i.e
- * pulled-down) the asynchronous boot mode is selected.
- *
- * In synchronous boot mode nSDCE3 is decoded starting at physical address
- * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
- * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
- * decoded at 0xf0000000.
- *
- * There is known errata for the EP93xx dealing with External Memory
- * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
- * Guidelines" for more information.  This document can be found at:
- *
- *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
- */
-
-#define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
-#define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
-#define EP93XX_CS1_PHYS_BASE            0x10000000
-#define EP93XX_CS2_PHYS_BASE            0x20000000
-#define EP93XX_CS3_PHYS_BASE            0x30000000
-#define EP93XX_PCMCIA_PHYS_BASE         0x40000000
-#define EP93XX_CS6_PHYS_BASE            0x60000000
-#define EP93XX_CS7_PHYS_BASE            0x70000000
-#define EP93XX_SDCE0_PHYS_BASE          0xc0000000
-#define EP93XX_SDCE1_PHYS_BASE          0xd0000000
-#define EP93XX_SDCE2_PHYS_BASE          0xe0000000
-#define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
-#define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
-
-/*
  * EP93xx linux memory map:
  *
  * virt         phys            size
@@ -62,58 +28,7 @@
 #define EP93XX_APB_PHYS(x)              (EP93XX_APB_PHYS_BASE + (x))
 #define EP93XX_APB_IOMEM(x)             IOMEM(EP93XX_APB_VIRT_BASE + (x))
 
-
-/* AHB peripherals */
-#define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
-
-#define EP93XX_ETHERNET_PHYS_BASE       EP93XX_AHB_PHYS(0x00010000)
-#define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
-
-#define EP93XX_USB_PHYS_BASE            EP93XX_AHB_PHYS(0x00020000)
-#define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
-
-#define EP93XX_RASTER_PHYS_BASE         EP93XX_AHB_PHYS(0x00030000)
-#define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
-
-#define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
-
-#define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
-
-#define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
-
-#define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
-
-#define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
-
-#define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
-
-#define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
-
-
-/* APB peripherals */
-#define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
-
-#define EP93XX_I2S_PHYS_BASE            EP93XX_APB_PHYS(0x00020000)
-#define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
-
-#define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
-
-#define EP93XX_GPIO_PHYS_BASE           EP93XX_APB_PHYS(0x00040000)
-#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
-#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
-#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
-#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
-#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
-#define EP93XX_GPIO_EEDRIVE             EP93XX_GPIO_REG(0xc8)
-
-#define EP93XX_AAC_PHYS_BASE            EP93XX_APB_PHYS(0x00080000)
-#define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
-
-#define EP93XX_SPI_PHYS_BASE            EP93XX_APB_PHYS(0x000a0000)
-#define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
-
-#define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
-
+/* APB UARTs */
 #define EP93XX_UART1_PHYS_BASE          EP93XX_APB_PHYS(0x000c0000)
 #define EP93XX_UART1_BASE               EP93XX_APB_IOMEM(0x000c0000)
 
@@ -123,108 +38,4 @@
 #define EP93XX_UART3_PHYS_BASE          EP93XX_APB_PHYS(0x000e0000)
 #define EP93XX_UART3_BASE               EP93XX_APB_IOMEM(0x000e0000)
 
-#define EP93XX_KEY_MATRIX_PHYS_BASE     EP93XX_APB_PHYS(0x000f0000)
-#define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
-
-#define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
-#define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
-
-#define EP93XX_PWM_PHYS_BASE            EP93XX_APB_PHYS(0x00110000)
-#define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
-
-#define EP93XX_RTC_PHYS_BASE            EP93XX_APB_PHYS(0x00120000)
-#define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
-
-#define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
-#define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
-#define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
-#define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_PWRCNT_FIR_EN     (1<<31)
-#define EP93XX_SYSCON_PWRCNT_UARTBAUD   (1<<29)
-#define EP93XX_SYSCON_PWRCNT_USH_EN     (1<<28)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M1   (1<<27)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M0   (1<<26)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P8   (1<<25)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P9   (1<<24)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P6   (1<<23)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P7   (1<<22)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P4   (1<<21)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P5   (1<<20)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P2   (1<<19)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P3   (1<<18)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P0   (1<<17)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
-#define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
-#define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
-#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
-#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
-#define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
-#define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
-#define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
-#define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
-#define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
-#define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
-#define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
-#define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
-#define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
-#define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
-#define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
-#define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
-#define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
-#define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
-#define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
-#define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
-#define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
-#define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
-#define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
-#define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
-#define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
-#define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
-#define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
-#define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
-#define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
-#define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
-#define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
-#define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
-#define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
-#define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
-#define EP93XX_SYSCON_VIDCLKDIV         EP93XX_SYSCON_REG(0x84)
-#define EP93XX_SYSCON_CLKDIV_ENABLE     (1<<15)
-#define EP93XX_SYSCON_CLKDIV_ESEL       (1<<14)
-#define EP93XX_SYSCON_CLKDIV_PSEL       (1<<13)
-#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
-#define EP93XX_SYSCON_I2SCLKDIV         EP93XX_SYSCON_REG(0x8c)
-#define EP93XX_SYSCON_I2SCLKDIV_SENA    (1<<31)
-#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
-#define EP93XX_SYSCON_I2SCLKDIV_SPOL    (1<<19)
-#define EP93XX_I2SCLKDIV_SDIV           (1 << 16)
-#define EP93XX_I2SCLKDIV_LRDIV32        (0 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV64        (1 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV128       (2 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV_MASK     (3 << 17)
-#define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
-#define EP93XX_SYSCON_SYSCFG            EP93XX_SYSCON_REG(0x9c)
-#define EP93XX_SYSCON_SYSCFG_REV_MASK   (0xf0000000)
-#define EP93XX_SYSCON_SYSCFG_REV_SHIFT  (28)
-#define EP93XX_SYSCON_SYSCFG_SBOOT      (1<<8)
-#define EP93XX_SYSCON_SYSCFG_LCSN7      (1<<7)
-#define EP93XX_SYSCON_SYSCFG_LCSN6      (1<<6)
-#define EP93XX_SYSCON_SYSCFG_LASDO      (1<<5)
-#define EP93XX_SYSCON_SYSCFG_LEEDA      (1<<4)
-#define EP93XX_SYSCON_SYSCFG_LEECLK     (1<<3)
-#define EP93XX_SYSCON_SYSCFG_LCSN2      (1<<1)
-#define EP93XX_SYSCON_SYSCFG_LCSN1      (1<<0)
-#define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
-
-#define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
-
-
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
index 8aff2ea3587..6d7c571a519 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
@@ -3,6 +3,16 @@
 #ifndef __GPIO_EP93XX_H
 #define __GPIO_EP93XX_H
 
+#include <mach/ep93xx-regs.h>
+
+#define EP93XX_GPIO_PHYS_BASE           EP93XX_APB_PHYS(0x00040000)
+#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
+#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
+#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
+#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
+#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
+#define EP93XX_GPIO_EEDRIVE             EP93XX_GPIO_REG(0xc8)
+
 /* GPIO port A.  */
 #define EP93XX_GPIO_LINE_A(x)           ((x) + 0)
 #define EP93XX_GPIO_LINE_EGPIO0         EP93XX_GPIO_LINE_A(0)
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 4df842897ea..efcd47815a9 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include <mach/ep93xx-regs.h>
 #include <mach/platform.h>
 
 /*
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index ad63d4be693..602bd87fd0a 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -21,20 +21,6 @@ struct ep93xx_eth_data
 void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 
-/* EP93xx System Controller software locked register write */
-void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
-void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
-
-static inline void ep93xx_devcfg_set_bits(unsigned int bits)
-{
-        ep93xx_devcfg_set_clear(bits, 0x00);
-}
-
-static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
-{
-        ep93xx_devcfg_set_clear(0x00, bits);
-}
-
 #define EP93XX_CHIP_REV_D0      3
 #define EP93XX_CHIP_REV_D1      4
 #define EP93XX_CHIP_REV_E0      5
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
deleted file mode 100644
index b5bec7cb9b5..00000000000
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/system.h
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 7b98084f0c9..dc431c5f04c 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 /*************************************************************************
  * Micro9 NOR Flash
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index f4e553eca21..f40c2987e54 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -29,6 +29,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 static struct ep93xx_eth_data __initdata simone_eth_data = {
         .phy_id         = 1,
 };
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index fd846331ddf..0c00852ef16 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -35,6 +35,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 #define SNAPPERCL15_NAND_BASE   (EP93XX_CS7_PHYS_BASE + SZ_16M)
 
 #define SNAPPERCL15_NAND_WPN    (1 << 8)  /* Write protect (active low) */
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
new file mode 100644
index 00000000000..979fba72292
--- /dev/null
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -0,0 +1,213 @@
+/*
+ * arch/arm/mach-ep93xx/soc.h
+ *
+ * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
+ * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#ifndef _EP93XX_SOC_H
+#define _EP93XX_SOC_H
+
+#include <mach/ep93xx-regs.h>
+
+/*
+ * EP93xx Physical Memory Map:
+ *
+ * The ASDO pin is sampled at system reset to select a synchronous or
+ * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
+ * the synchronous boot mode is selected.  When ASDO is "0" (i.e
+ * pulled-down) the asynchronous boot mode is selected.
+ *
+ * In synchronous boot mode nSDCE3 is decoded starting at physical address
+ * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
+ * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
+ * decoded at 0xf0000000.
+ *
+ * There is known errata for the EP93xx dealing with External Memory
+ * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
+ * Guidelines" for more information.  This document can be found at:
+ *
+ *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
+ */
+
+#define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
+#define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
+#define EP93XX_CS1_PHYS_BASE            0x10000000
+#define EP93XX_CS2_PHYS_BASE            0x20000000
+#define EP93XX_CS3_PHYS_BASE            0x30000000
+#define EP93XX_PCMCIA_PHYS_BASE         0x40000000
+#define EP93XX_CS6_PHYS_BASE            0x60000000
+#define EP93XX_CS7_PHYS_BASE            0x70000000
+#define EP93XX_SDCE0_PHYS_BASE          0xc0000000
+#define EP93XX_SDCE1_PHYS_BASE          0xd0000000
+#define EP93XX_SDCE2_PHYS_BASE          0xe0000000
+#define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
+#define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
+
+/* AHB peripherals */
+#define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
+
+#define EP93XX_ETHERNET_PHYS_BASE       EP93XX_AHB_PHYS(0x00010000)
+#define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
+
+#define EP93XX_USB_PHYS_BASE            EP93XX_AHB_PHYS(0x00020000)
+#define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
+
+#define EP93XX_RASTER_PHYS_BASE         EP93XX_AHB_PHYS(0x00030000)
+#define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
+
+#define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
+
+#define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
+
+#define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
+
+#define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
+
+#define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
+
+#define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
+
+#define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
+
+/* APB peripherals */
+#define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
+
+#define EP93XX_I2S_PHYS_BASE            EP93XX_APB_PHYS(0x00020000)
+#define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
+
+#define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
+
+#define EP93XX_AAC_PHYS_BASE            EP93XX_APB_PHYS(0x00080000)
+#define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
+
+#define EP93XX_SPI_PHYS_BASE            EP93XX_APB_PHYS(0x000a0000)
+#define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
+
+#define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
+
+#define EP93XX_KEY_MATRIX_PHYS_BASE     EP93XX_APB_PHYS(0x000f0000)
+#define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
+
+#define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
+#define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
+
+#define EP93XX_PWM_PHYS_BASE            EP93XX_APB_PHYS(0x00110000)
+#define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
+
+#define EP93XX_RTC_PHYS_BASE            EP93XX_APB_PHYS(0x00120000)
+#define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
+
+#define EP93XX_WATCHDOG_PHYS_BASE       EP93XX_APB_PHYS(0x00140000)
+#define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
+
+/* System controller */
+#define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
+#define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
+#define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
+#define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN     (1<<31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD   (1<<29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN     (1<<28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1   (1<<27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0   (1<<26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8   (1<<25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9   (1<<24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6   (1<<23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7   (1<<22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4   (1<<21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5   (1<<20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2   (1<<19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3   (1<<18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0   (1<<17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
+#define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
+#define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
+#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
+#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
+#define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
+#define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
+#define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
+#define EP93XX_SYSCON_VIDCLKDIV         EP93XX_SYSCON_REG(0x84)
+#define EP93XX_SYSCON_CLKDIV_ENABLE     (1<<15)
+#define EP93XX_SYSCON_CLKDIV_ESEL       (1<<14)
+#define EP93XX_SYSCON_CLKDIV_PSEL       (1<<13)
+#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
+#define EP93XX_SYSCON_I2SCLKDIV         EP93XX_SYSCON_REG(0x8c)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA    (1<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL    (1<<19)
+#define EP93XX_I2SCLKDIV_SDIV           (1 << 16)
+#define EP93XX_I2SCLKDIV_LRDIV32        (0 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV64        (1 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV128       (2 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV_MASK     (3 << 17)
+#define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
+#define EP93XX_SYSCON_SYSCFG            EP93XX_SYSCON_REG(0x9c)
+#define EP93XX_SYSCON_SYSCFG_REV_MASK   (0xf0000000)
+#define EP93XX_SYSCON_SYSCFG_REV_SHIFT  (28)
+#define EP93XX_SYSCON_SYSCFG_SBOOT      (1<<8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7      (1<<7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6      (1<<6)
+#define EP93XX_SYSCON_SYSCFG_LASDO      (1<<5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA      (1<<4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK     (1<<3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2      (1<<1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1      (1<<0)
+#define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
+
+/* EP93xx System Controller software locked register write */
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
+
+static inline void ep93xx_devcfg_set_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(bits, 0x00);
+}
+
+static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(0x00, bits);
+}
+
+#endif /* _EP93XX_SOC_H */
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 79f8ecf07a1..5ea790942e9 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -28,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct map_desc ts72xx_io_desc[] __initdata = {
         {
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index d67d0b4feb6..ba156eb225e 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -39,6 +39,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 /*************************************************************************
  * Static I/O mappings for the FPGA
  *************************************************************************/
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index dfad6538b27..0491ceef1cd 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
-choice
-        prompt "EXYNOS System Type"
-        default ARCH_EXYNOS4
-
 config ARCH_EXYNOS4
         bool "SAMSUNG EXYNOS4"
+        default y
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         help
           Samsung EXYNOS4 SoCs based systems
 
-endchoice
+config ARCH_EXYNOS5
+        bool "SAMSUNG EXYNOS5"
+        select HAVE_SMP
+        help
+          Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
 comment "EXYNOS SoCs"
 
@@ -42,6 +43,7 @@ config SOC_EXYNOS4212
         bool "SAMSUNG EXYNOS4212"
         default y
         depends on ARCH_EXYNOS4
+        select SAMSUNG_DMADEV
         select S5P_PM if PM
         select S5P_SLEEP if PM
         help
@@ -51,9 +53,17 @@ config SOC_EXYNOS4412
         bool "SAMSUNG EXYNOS4412"
         default y
         depends on ARCH_EXYNOS4
+        select SAMSUNG_DMADEV
         help
           Enable EXYNOS4412 SoC support
 
+config SOC_EXYNOS5250
+        bool "SAMSUNG EXYNOS5250"
+        default y
+        depends on ARCH_EXYNOS5
+        help
+          Enable EXYNOS5250 SoC support
+
 config EXYNOS4_MCT
         bool
         default y
@@ -179,7 +189,9 @@ config MACH_SMDKV310
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_G2D
         select S5P_DEV_I2C_HDMIPHY
+        select S5P_DEV_JPEG
         select S5P_DEV_MFC
         select S5P_DEV_TV
         select S5P_DEV_USB_EHCI
@@ -225,7 +237,9 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_G2D
         select S5P_DEV_CSIS0
+        select S5P_DEV_JPEG
         select S5P_DEV_FIMD0
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
@@ -262,11 +276,14 @@ config MACH_NURI
         select S3C_DEV_I2C1
         select S3C_DEV_I2C3
         select S3C_DEV_I2C5
+        select S3C_DEV_I2C6
         select S5P_DEV_CSIS0
+        select S5P_DEV_JPEG
         select S5P_DEV_FIMC0
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_G2D
         select S5P_DEV_MFC
         select S5P_DEV_USB_EHCI
         select S5P_SETUP_MIPIPHY
@@ -276,6 +293,7 @@ config MACH_NURI
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C5
+        select EXYNOS4_SETUP_I2C6
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select S5P_SETUP_MIPIPHY
@@ -296,7 +314,9 @@ config MACH_ORIGEN
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
         select S5P_DEV_FIMD0
+        select S5P_DEV_G2D
         select S5P_DEV_I2C_HDMIPHY
+        select S5P_DEV_JPEG
         select S5P_DEV_MFC
         select S5P_DEV_TV
         select S5P_DEV_USB_EHCI
@@ -325,6 +345,7 @@ config MACH_SMDK4212
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_KEYPAD
         select SAMSUNG_DEV_PWM
+        select EXYNOS4_DEV_DMA
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C7
@@ -343,7 +364,7 @@ config MACH_SMDK4412
           Machine support for Samsung SMDK4412
 endif
 
-comment "Flattened Device Tree based board for Exynos4 based SoC"
+comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
@@ -357,6 +378,15 @@ config MACH_EXYNOS4_DT
           Note: This is under development and not all peripherals can be supported
           with this machine file.
 
+config MACH_EXYNOS5_DT
+        bool "SAMSUNG EXYNOS5 Machine using device tree"
+        select SOC_EXYNOS5250
+        select USE_OF
+        select ARM_AMBA
+        help
+          Machine support for Samsung Exynos4 machine with device tree enabled.
+          Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+
 if ARCH_EXYNOS4
 
 comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index d9191f9a7af..8631840d1b5 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,7 +12,9 @@ obj-				:=
 
 # Core
 
-obj-$(CONFIG_ARCH_EXYNOS4)      += common.o clock.o
+obj-$(CONFIG_ARCH_EXYNOS)       += common.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS5)      += clock-exynos5.o
 obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
 
@@ -41,9 +43,11 @@ obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)           += mach-exynos4-dt.o
+obj-$(CONFIG_MACH_EXYNOS5_DT)           += mach-exynos5-dt.o
 
 # device support
 
+obj-y                                   += dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)        += dev-sysmmu.o
@@ -51,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)           += dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)              += setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)       += setup-fimd0.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 00000000000..df54c2a9222
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1581 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+#include "clock-exynos4.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4_clock_save[] = {
+        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
+};
+#endif
+
+static struct clk exynos4_clk_sclk_hdmi27m = {
+        .name           = "sclk_hdmi27m",
+        .rate           = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_hdmiphy = {
+        .name           = "sclk_hdmiphy",
+};
+
+static struct clk exynos4_clk_sclk_usbphy0 = {
+        .name           = "sclk_usbphy0",
+        .rate           = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_usbphy1 = {
+        .name           = "sclk_usbphy1",
+};
+
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
+}
+
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
+}
+
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
+}
+
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
+}
+
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos4_clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+        },
+        .sources = &clk_src_apll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_apll = {
+        .clk    = {
+                .name           = "sclk_apll",
+                .parent         = &exynos4_clk_mout_apll.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+        },
+        .sources = &clk_src_epll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+struct clksrc_clk exynos4_clk_mout_mpll = {
+        .clk    = {
+                .name           = "mout_mpll",
+        },
+        .sources = &clk_src_mpll,
+
+        /* reg_src will be added in each SoCs' clock */
+};
+
+static struct clk *exynos4_clkset_moutcore_list[] = {
+        [0] = &exynos4_clk_mout_apll.clk,
+        [1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_moutcore = {
+        .sources        = exynos4_clkset_moutcore_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
+};
+
+static struct clksrc_clk exynos4_clk_moutcore = {
+        .clk    = {
+                .name           = "moutcore",
+        },
+        .sources = &exynos4_clkset_moutcore,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_coreclk = {
+        .clk    = {
+                .name           = "core_clk",
+                .parent         = &exynos4_clk_moutcore.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_armclk = {
+        .clk    = {
+                .name           = "armclk",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
+        .clk    = {
+                .name           = "aclk_corem0",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cores = {
+        .clk    = {
+                .name           = "aclk_cores",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
+        .clk    = {
+                .name           = "aclk_corem1",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_periphclk = {
+        .clk    = {
+                .name           = "periphclk",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+static struct clk *exynos4_clkset_corebus_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+        .sources        = exynos4_clkset_corebus_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_corebus = {
+        .clk    = {
+                .name           = "mout_corebus",
+        },
+        .sources = &exynos4_clkset_mout_corebus,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
+        .clk    = {
+                .name           = "sclk_dmc",
+                .parent         = &exynos4_clk_mout_corebus.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cored = {
+        .clk    = {
+                .name           = "aclk_cored",
+                .parent         = &exynos4_clk_sclk_dmc.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corep = {
+        .clk    = {
+                .name           = "aclk_corep",
+                .parent         = &exynos4_clk_aclk_cored.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_acp = {
+        .clk    = {
+                .name           = "aclk_acp",
+                .parent         = &exynos4_clk_mout_corebus.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_pclk_acp = {
+        .clk    = {
+                .name           = "pclk_acp",
+                .parent         = &exynos4_clk_aclk_acp.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos4_clkset_aclk_top_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_aclk = {
+        .sources        = exynos4_clkset_aclk_top_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos4_clk_aclk_200 = {
+        .clk    = {
+                .name           = "aclk_200",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_100 = {
+        .clk    = {
+                .name           = "aclk_100",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_160 = {
+        .clk    = {
+                .name           = "aclk_160",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+struct clksrc_clk exynos4_clk_aclk_133 = {
+        .clk    = {
+                .name           = "aclk_133",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
+        [0] = &clk_fin_vpll,
+        [1] = &exynos4_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+        .sources        = exynos4_clkset_vpllsrc_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos4_clk_vpllsrc = {
+        .clk    = {
+                .name           = "vpll_src",
+                .enable         = exynos4_clksrc_mask_top_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_vpllsrc,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+        [0] = &exynos4_clk_vpllsrc.clk,
+        [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+        .sources        = exynos4_clkset_sclk_vpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
+        .clk    = {
+                .name           = "sclk_vpll",
+        },
+        .sources = &exynos4_clkset_sclk_vpll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static struct clk exynos4_init_clocks_off[] = {
+        {
+                .name           = "timers",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1<<24),
+        }, {
+                .name           = "csis",
+                .devname        = "s5p-mipi-csis.0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "csis",
+                .devname        = "s5p-mipi-csis.1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "jpeg",
+                .id             = 0,
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.2",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.3",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "dwmmc",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "dac",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "mixer",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "vp",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hdmi",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hdmiphy",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_hdmiphy_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "dacphy",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_dac_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "adc",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "keypad",
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "rtc",
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "watchdog",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "usbhost",
+                .enable         = exynos4_clk_ip_fsys_ctrl ,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "otg",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "ac97",
+                .devname        = "samsung-ac97",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "fimg2d",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "mfc",
+                .devname        = "s5p-mfc",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.0",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.1",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.2",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.3",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.4",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.5",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.6",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.7",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-hdmiphy-i2c",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "SYSMMU_MDMA",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "SYSMMU_FIMC0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "SYSMMU_FIMC1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "SYSMMU_FIMC2",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "SYSMMU_FIMC3",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "SYSMMU_JPEG",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "SYSMMU_FIMD0",
+                .enable         = exynos4_clk_ip_lcd0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_FIMD1",
+                .enable         = exynos4_clk_ip_lcd1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_PCIe",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "SYSMMU_G2D",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "SYSMMU_ROTATOR",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_TV",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_MFC_L",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "SYSMMU_MFC_R",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 2),
+        }
+};
+
+static struct clk exynos4_init_clocks_on[] = {
+        {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.3",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.4",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.5",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 5),
+        }
+};
+
+static struct clk exynos4_clk_pdma0 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.0",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+
+static struct clk exynos4_clk_pdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.1",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 1),
+};
+
+static struct clk exynos4_clk_mdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.2",
+        .enable         = exynos4_clk_ip_image_ctrl,
+        .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
+static struct clk exynos4_clk_fimd0 = {
+        .name           = "fimd",
+        .devname        = "exynos4-fb.0",
+        .enable         = exynos4_clk_ip_lcd0_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+
+struct clk *exynos4_clkset_group_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &clk_xusbxti,
+        [2] = &exynos4_clk_sclk_hdmi27m,
+        [3] = &exynos4_clk_sclk_usbphy0,
+        [4] = &exynos4_clk_sclk_usbphy1,
+        [5] = &exynos4_clk_sclk_hdmiphy,
+        [6] = &exynos4_clk_mout_mpll.clk,
+        [7] = &exynos4_clk_mout_epll.clk,
+        [8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_group = {
+        .sources        = exynos4_clkset_group_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
+};
+
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+        .sources        = exynos4_clkset_mout_g2d0_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d0 = {
+        .clk    = {
+                .name           = "mout_g2d0",
+        },
+        .sources = &exynos4_clkset_mout_g2d0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+        [0] = &exynos4_clk_mout_epll.clk,
+        [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+        .sources        = exynos4_clkset_mout_g2d1_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d1 = {
+        .clk    = {
+                .name           = "mout_g2d1",
+        },
+        .sources = &exynos4_clkset_mout_g2d1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+        [0] = &exynos4_clk_mout_g2d0.clk,
+        [1] = &exynos4_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+        .sources        = exynos4_clkset_mout_g2d_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
+};
+
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+        .sources        = exynos4_clkset_mout_mfc0_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
+        .clk    = {
+                .name           = "mout_mfc0",
+        },
+        .sources = &exynos4_clkset_mout_mfc0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+        [0] = &exynos4_clk_mout_epll.clk,
+        [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+        .sources        = exynos4_clkset_mout_mfc1_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
+        .clk    = {
+                .name           = "mout_mfc1",
+        },
+        .sources = &exynos4_clkset_mout_mfc1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+        [0] = &exynos4_clk_mout_mfc0.clk,
+        [1] = &exynos4_clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+        .sources        = exynos4_clkset_mout_mfc_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
+};
+
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+        [0] = &exynos4_clk_sclk_vpll.clk,
+        [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+        .sources        = exynos4_clkset_sclk_dac_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dac = {
+        .clk            = {
+                .name           = "sclk_dac",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &exynos4_clkset_sclk_dac,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
+        .clk            = {
+                .name           = "sclk_pixel",
+                .parent         = &exynos4_clk_sclk_vpll.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+        [0] = &exynos4_clk_sclk_pixel.clk,
+        [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+        .sources        = exynos4_clkset_sclk_hdmi_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
+        .clk            = {
+                .name           = "sclk_hdmi",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_sclk_hdmi,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+        [0] = &exynos4_clk_sclk_dac.clk,
+        [1] = &exynos4_clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+        .sources        = exynos4_clkset_sclk_mixer_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
+        .clk    = {
+                .name           = "sclk_mixer",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &exynos4_clkset_sclk_mixer,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+        &exynos4_clk_sclk_dac,
+        &exynos4_clk_sclk_pixel,
+        &exynos4_clk_sclk_hdmi,
+        &exynos4_clk_sclk_mixer,
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
+        .clk    = {
+                .name           = "dout_mmc0",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
+        .clk    = {
+                .name           = "dout_mmc1",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
+        .clk    = {
+                .name           = "dout_mmc2",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
+        .clk    = {
+                .name           = "dout_mmc3",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
+        .clk            = {
+                .name           = "dout_mmc4",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_pwm",
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_csis",
+                        .devname        = "s5p-mipi-csis.0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_csis",
+                        .devname        = "s5p-mipi-csis.1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 28),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 4),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.2",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 8),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.3",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimd",
+                        .devname        = "exynos4-fb.0",
+                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimg2d",
+                },
+                .sources = &exynos4_clkset_mout_g2d,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mfc",
+                        .devname        = "s5p-mfc",
+                },
+                .sources = &exynos4_clkset_mout_mfc,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dwmmc",
+                        .parent         = &exynos4_clk_dout_mmc4.clk,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+        }
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.0",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart1 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.1",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart2 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.2",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart3 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.3",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos4_clk_dout_mmc0.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos4_clk_dout_mmc1.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos4_clk_dout_mmc2.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos4_clk_dout_mmc3.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 16),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 20),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi2 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.2",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 24),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos4_sysclks[] = {
+        &exynos4_clk_mout_apll,
+        &exynos4_clk_sclk_apll,
+        &exynos4_clk_mout_epll,
+        &exynos4_clk_mout_mpll,
+        &exynos4_clk_moutcore,
+        &exynos4_clk_coreclk,
+        &exynos4_clk_armclk,
+        &exynos4_clk_aclk_corem0,
+        &exynos4_clk_aclk_cores,
+        &exynos4_clk_aclk_corem1,
+        &exynos4_clk_periphclk,
+        &exynos4_clk_mout_corebus,
+        &exynos4_clk_sclk_dmc,
+        &exynos4_clk_aclk_cored,
+        &exynos4_clk_aclk_corep,
+        &exynos4_clk_aclk_acp,
+        &exynos4_clk_pclk_acp,
+        &exynos4_clk_vpllsrc,
+        &exynos4_clk_sclk_vpll,
+        &exynos4_clk_aclk_200,
+        &exynos4_clk_aclk_100,
+        &exynos4_clk_aclk_160,
+        &exynos4_clk_aclk_133,
+        &exynos4_clk_dout_mmc0,
+        &exynos4_clk_dout_mmc1,
+        &exynos4_clk_dout_mmc2,
+        &exynos4_clk_dout_mmc3,
+        &exynos4_clk_dout_mmc4,
+        &exynos4_clk_mout_mfc0,
+        &exynos4_clk_mout_mfc1,
+};
+
+static struct clk *exynos4_clk_cdev[] = {
+        &exynos4_clk_pdma0,
+        &exynos4_clk_pdma1,
+        &exynos4_clk_mdma1,
+        &exynos4_clk_fimd0,
+};
+
+static struct clksrc_clk *exynos4_clksrc_cdev[] = {
+        &exynos4_clk_sclk_uart0,
+        &exynos4_clk_sclk_uart1,
+        &exynos4_clk_sclk_uart2,
+        &exynos4_clk_sclk_uart3,
+        &exynos4_clk_sclk_mmc0,
+        &exynos4_clk_sclk_mmc1,
+        &exynos4_clk_sclk_mmc2,
+        &exynos4_clk_sclk_mmc3,
+        &exynos4_clk_sclk_spi0,
+        &exynos4_clk_sclk_spi1,
+        &exynos4_clk_sclk_spi2,
+
+};
+
+static struct clk_lookup exynos4_clk_lookup[] = {
+        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
+        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
+        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
+        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
+        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+};
+
+static int xtal_rate;
+
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+        if (soc_is_exynos4210())
+                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
+                                        pll_4508);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
+        else
+                return 0;
+}
+
+static struct clk_ops exynos4_fout_apll_ops = {
+        .get_rate = exynos4_fout_apll_get_rate,
+};
+
+static u32 exynos4_vpll_div[][8] = {
+        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
+        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int vpll_con0, vpll_con1 = 0;
+        unsigned int i;
+
+        /* Return if nothing changed */
+        if (clk->rate == rate)
+                return 0;
+
+        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+        vpll_con0 &= ~(0x1 << 27 |                                      \
+                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
+                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
+                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
+                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
+                if (exynos4_vpll_div[i][0] == rate) {
+                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+
+        /* Wait for VPLL lock */
+        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+                continue;
+
+        clk->rate = rate;
+        return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+        .get_rate = exynos4_vpll_get_rate,
+        .set_rate = exynos4_vpll_set_rate,
+};
+
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+        unsigned long apll = 0;
+        unsigned long mpll = 0;
+        unsigned long epll = 0;
+        unsigned long vpll = 0;
+        unsigned long vpllsrc;
+        unsigned long xtal;
+        unsigned long armclk;
+        unsigned long sclk_dmc;
+        unsigned long aclk_200;
+        unsigned long aclk_100;
+        unsigned long aclk_160;
+        unsigned long aclk_133;
+        unsigned int ptr;
+
+        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+        xtal_clk = clk_get(NULL, "xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+
+        xtal_rate = xtal;
+
+        clk_put(xtal_clk);
+
+        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+        if (soc_is_exynos4210()) {
+                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
+                                        pll_4508);
+                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
+                                        pll_4508);
+                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
+
+                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                        __raw_readl(EXYNOS4_EPLL_CON1));
+
+                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                        __raw_readl(EXYNOS4_VPLL_CON1));
+        } else {
+                /* nothing */
+        }
+
+        clk_fout_apll.ops = &exynos4_fout_apll_ops;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_vpll.ops = &exynos4_vpll_ops;
+        clk_fout_vpll.rate = vpll;
+
+        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+                        apll, mpll, epll, vpll);
+
+        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
+
+        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
+
+        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+                        armclk, sclk_dmc, aclk_200,
+                        aclk_100, aclk_160, aclk_133);
+
+        clk_f.rate = armclk;
+        clk_h.rate = sclk_dmc;
+        clk_p.rate = aclk_100;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
+}
+
+static struct clk *exynos4_clks[] __initdata = {
+        &exynos4_clk_sclk_hdmi27m,
+        &exynos4_clk_sclk_hdmiphy,
+        &exynos4_clk_sclk_usbphy0,
+        &exynos4_clk_sclk_usbphy1,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+        return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos4_clock_syscore_ops = {
+        .suspend        = exynos4_clock_suspend,
+        .resume         = exynos4_clock_resume,
+};
+
+void __init exynos4_register_clocks(void)
+{
+        int ptr;
+
+        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
+                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
+
+        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
+
+        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
+                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
+
+        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
+
+        register_syscore_ops(&exynos4_clock_syscore_ops);
+        s3c24xx_register_clock(&dummy_apb_pclk);
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644
index 00000000000..cb71c29c14d
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
+
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+extern struct clksrc_sources exynos4_clkset_group;
+
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clk *exynos4_clkset_group_list[];
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 13312ccb2d9..3b131e4b6ef 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * EXYNOS4210 - Clock support
@@ -28,20 +26,20 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKSRC_LCD1),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
 };
 #endif
 
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
 
 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
 }
 
 static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
-                .sources = &clkset_mout_corebus,
-                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+                .sources = &exynos4_clkset_mout_corebus,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
         }, {
                 .clk            = {
                         .name           = "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
         },
 };
 
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
         {
                 .name           = "sataphy",
                 .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "sata",
                 .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
@@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
 #define exynos4210_clock_resume NULL
 #endif
 
-struct syscore_ops exynos4210_clock_syscore_ops = {
+static struct syscore_ops exynos4210_clock_syscore_ops = {
         .suspend        = exynos4210_clock_suspend,
         .resume         = exynos4210_clock_resume,
 };
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
 {
         int ptr;
 
-        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
-        clk_mout_mpll.reg_src.shift = 8;
-        clk_mout_mpll.reg_src.size = 1;
+        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+        exynos4_clk_mout_mpll.reg_src.shift = 8;
+        exynos4_clk_mout_mpll.reg_src.size = 1;
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 48af28566fa..3ecc01e06f7 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4212.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * EXYNOS4212 - Clock support
@@ -28,22 +26,22 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
+        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
 };
 #endif
 
 static struct clk *clk_src_mpll_user_list[] = {
         [0] = &clk_fin_mpll,
-        [1] = &clk_mout_mpll.clk,
+        [1] = &exynos4_clk_mout_mpll.clk,
 };
 
 static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
                 .name           = "mout_mpll_user",
         },
         .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 };
 
 static struct clksrc_clk *sysclks[] = {
@@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
 #define exynos4212_clock_resume NULL
 #endif
 
-struct syscore_ops exynos4212_clock_syscore_ops = {
+static struct syscore_ops exynos4212_clock_syscore_ops = {
         .suspend        = exynos4212_clock_suspend,
         .resume         = exynos4212_clock_resume,
 };
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
         int ptr;
 
         /* usbphy1 is removed */
-        clkset_group_list[4] = NULL;
+        exynos4_clkset_group_list[4] = NULL;
 
         /* mout_mpll_user is used */
-        clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
+        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 
-        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
-        clk_mout_mpll.reg_src.shift = 12;
-        clk_mout_mpll.reg_src.size = 1;
+        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+        exynos4_clk_mout_mpll.reg_src.shift = 12;
+        exynos4_clk_mout_mpll.reg_src.size = 1;
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 00000000000..d013982d0f8
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1247 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Clock support for EXYNOS5 SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+        /* will be implemented */
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+        .name           = "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+        .name           = "sclk_hdmi24m",
+        .rate           = 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+        .name           = "sclk_hdmi27m",
+        .rate           = 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+        .name           = "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+        .name           = "sclk_usbphy",
+        .rate           = 48000000,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+        },
+        .sources = &clk_src_apll,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+        .clk    = {
+                .name           = "sclk_apll",
+                .parent         = &exynos5_clk_mout_apll.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+        .clk    = {
+                .name           = "mout_bpll",
+        },
+        .sources = &clk_src_bpll,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+        .sources        = exynos5_clk_src_bpll_user_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+        .clk    = {
+                .name           = "mout_bpll_user",
+        },
+        .sources = &exynos5_clk_src_bpll_user,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+        .clk    = {
+                .name           = "mout_cpll",
+        },
+        .sources = &clk_src_cpll,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+        },
+        .sources = &clk_src_epll,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+struct clksrc_clk exynos5_clk_mout_mpll = {
+        .clk = {
+                .name           = "mout_mpll",
+        },
+        .sources = &clk_src_mpll,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos_clkset_vpllsrc_list[] = {
+        [0] = &clk_fin_vpll,
+        [1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_vpllsrc = {
+        .sources        = exynos_clkset_vpllsrc_list,
+        .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_vpllsrc = {
+        .clk    = {
+                .name           = "vpll_src",
+                .enable         = exynos5_clksrc_mask_top_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos5_clkset_vpllsrc,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+        [0] = &exynos5_clk_vpllsrc.clk,
+        [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+        .sources        = exynos5_clkset_sclk_vpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+        .clk    = {
+                .name           = "sclk_vpll",
+        },
+        .sources = &exynos5_clkset_sclk_vpll,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+        .clk    = {
+                .name           = "sclk_pixel",
+                .parent         = &exynos5_clk_sclk_vpll.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+        [0] = &exynos5_clk_sclk_pixel.clk,
+        [1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+        .sources        = exynos5_clkset_sclk_hdmi_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+        .clk    = {
+                .name           = "sclk_hdmi",
+                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+                .ctrlbit        = (1 << 20),
+        },
+        .sources = &exynos5_clkset_sclk_hdmi,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+        &exynos5_clk_sclk_pixel,
+        &exynos5_clk_sclk_hdmi,
+};
+
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+        .sources        = exynos5_clk_src_mpll_user_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+        .clk    = {
+                .name           = "mout_mpll_user",
+        },
+        .sources = &exynos5_clk_src_mpll_user,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+        [0] = &exynos5_clk_mout_apll.clk,
+        [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+        .sources        = exynos5_clkset_mout_cpu_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+        .clk    = {
+                .name           = "mout_cpu",
+        },
+        .sources = &exynos5_clkset_mout_cpu,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+        .clk    = {
+                .name           = "dout_armclk",
+                .parent         = &exynos5_clk_mout_cpu.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+        .clk    = {
+                .name           = "dout_arm2clk",
+                .parent         = &exynos5_clk_dout_armclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+        .name           = "armclk",
+        .parent         = &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+        [0] = &exynos5_clk_mout_mpll.clk,
+        [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_cdrex = {
+        .sources        = exynos5_clkset_cdrex_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_cdrex = {
+        .clk    = {
+                .name           = "clk_cdrex",
+        },
+        .sources = &exynos5_clkset_cdrex,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+        .clk    = {
+                .name           = "aclk_acp",
+                .parent         = &exynos5_clk_mout_mpll.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+        .clk    = {
+                .name           = "pclk_acp",
+                .parent         = &exynos5_clk_aclk_acp.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos5_clkset_aclk_top_list[] = {
+        [0] = &exynos5_clk_mout_mpll_user.clk,
+        [1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk = {
+        .sources        = exynos5_clkset_aclk_top_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+        .clk    = {
+                .name           = "aclk_400",
+        },
+        .sources = &exynos5_clkset_aclk,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+struct clk *exynos5_clkset_aclk_333_166_list[] = {
+        [0] = &exynos5_clk_mout_cpll.clk,
+        [1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+        .sources        = exynos5_clkset_aclk_333_166_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+        .clk    = {
+                .name           = "aclk_333",
+        },
+        .sources = &exynos5_clkset_aclk_333_166,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+        .clk    = {
+                .name           = "aclk_166",
+        },
+        .sources = &exynos5_clkset_aclk_333_166,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+        .clk    = {
+                .name           = "aclk_266",
+                .parent         = &exynos5_clk_mout_mpll_user.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+        .clk    = {
+                .name           = "aclk_200",
+        },
+        .sources = &exynos5_clkset_aclk,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66_pre = {
+        .clk    = {
+                .name           = "aclk_66_pre",
+                .parent         = &exynos5_clk_mout_mpll_user.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+        .clk    = {
+                .name           = "aclk_66",
+                .parent         = &exynos5_clk_aclk_66_pre.clk,
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+        {
+                .name           = "timers",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 24),
+        }, {
+                .name           = "rtc",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peris_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos5_clk_aclk_200.clk,
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos5_clk_aclk_200.clk,
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos5_clk_aclk_200.clk,
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos5_clk_aclk_200.clk,
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "dwmci",
+                .parent         = &exynos5_clk_aclk_200.clk,
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "sata",
+                .devname        = "ahci",
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "sata_phy",
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 24),
+        }, {
+                .name           = "sata_phy_i2c",
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "mfc",
+                .devname        = "s5p-mfc",
+                .enable         = exynos5_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hdmi",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos5_clk_ip_disp1_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "mixer",
+                .devname        = "s5p-mixer",
+                .enable         = exynos5_clk_ip_disp1_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "jpeg",
+                .enable         = exynos5_clk_ip_gen_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "dsim0",
+                .enable         = exynos5_clk_ip_disp1_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.1",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.2",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.1",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.2",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 23),
+        }, {
+                .name           = "spdif",
+                .devname        = "samsung-spdif",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
+                .name           = "ac97",
+                .devname        = "samsung-ac97",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "usbhost",
+                .enable         = exynos5_clk_ip_fsys_ctrl ,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "usbotg",
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "gps",
+                .enable         = exynos5_clk_ip_gps_ctrl,
+                .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
+        }, {
+                .name           = "nfcon",
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "iop",
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
+        }, {
+                .name           = "core_iop",
+                .enable         = exynos5_clk_ip_core_ctrl,
+                .ctrlbit        = ((1 << 21) | (1 << 3)),
+        }, {
+                .name           = "mcu_iop",
+                .enable         = exynos5_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.0",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.1",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.2",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.3",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.4",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.5",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.6",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.7",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-hdmiphy-i2c",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 14),
+        }
+};
+
+static struct clk exynos5_init_clocks_on[] = {
+        {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.0",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.1",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.2",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.3",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.4",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.5",
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 5),
+        }
+};
+
+static struct clk exynos5_clk_pdma0 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.0",
+        .enable         = exynos5_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 1),
+};
+
+static struct clk exynos5_clk_pdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.1",
+        .enable         = exynos5_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 1),
+};
+
+static struct clk exynos5_clk_mdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.2",
+        .enable         = exynos5_clk_ip_gen_ctrl,
+        .ctrlbit        = (1 << 4),
+};
+
+struct clk *exynos5_clkset_group_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = NULL,
+        [2] = &exynos5_clk_sclk_hdmi24m,
+        [3] = &exynos5_clk_sclk_dptxphy,
+        [4] = &exynos5_clk_sclk_usbphy,
+        [5] = &exynos5_clk_sclk_hdmiphy,
+        [6] = &exynos5_clk_mout_mpll_user.clk,
+        [7] = &exynos5_clk_mout_epll.clk,
+        [8] = &exynos5_clk_sclk_vpll.clk,
+        [9] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_group = {
+        .sources        = exynos5_clkset_group_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+        .sources        = clk_src_gscl_266_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc0 = {
+        .clk            = {
+                .name           = "dout_mmc0",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc1 = {
+        .clk            = {
+                .name           = "dout_mmc1",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc2 = {
+        .clk            = {
+                .name           = "dout_mmc2",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc3 = {
+        .clk            = {
+                .name           = "dout_mmc3",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc4 = {
+        .clk            = {
+                .name           = "dout_mmc4",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.0",
+                .enable         = exynos5_clksrc_mask_peric0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart1 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.1",
+                .enable         = exynos5_clksrc_mask_peric0_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart2 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.2",
+                .enable         = exynos5_clksrc_mask_peric0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart3 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.3",
+                .enable         = exynos5_clksrc_mask_peric0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos5_clk_dout_mmc0.clk,
+                .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos5_clk_dout_mmc1.clk,
+                .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos5_clk_dout_mmc2.clk,
+                .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos5_clk_dout_mmc3.clk,
+                .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_dwmci",
+                        .parent         = &exynos5_clk_dout_mmc4.clk,
+                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimd",
+                        .devname        = "s3cfb.1",
+                        .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &exynos5_clkset_group,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "aclk_266_gscl",
+                },
+                .sources = &clk_src_gscl_266,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_g3d",
+                        .devname        = "mali-t604.0",
+                        .enable         = exynos5_clk_block_ctrl,
+                        .ctrlbit        = (1 << 1),
+                },
+                .sources = &exynos5_clkset_aclk,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_gscl_wrap",
+                        .devname        = "s5p-mipi-csis.0",
+                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos5_clkset_group,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_gscl_wrap",
+                        .devname        = "s5p-mipi-csis.1",
+                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                        .ctrlbit        = (1 << 28),
+                },
+                .sources = &exynos5_clkset_group,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam0",
+                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &exynos5_clkset_group,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam1",
+                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &exynos5_clkset_group,
+                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_jpeg",
+                        .parent         = &exynos5_clk_mout_cpll.clk,
+                },
+                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+        },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+        &exynos5_clk_mout_apll,
+        &exynos5_clk_sclk_apll,
+        &exynos5_clk_mout_bpll,
+        &exynos5_clk_mout_bpll_user,
+        &exynos5_clk_mout_cpll,
+        &exynos5_clk_mout_epll,
+        &exynos5_clk_mout_mpll,
+        &exynos5_clk_mout_mpll_user,
+        &exynos5_clk_vpllsrc,
+        &exynos5_clk_sclk_vpll,
+        &exynos5_clk_mout_cpu,
+        &exynos5_clk_dout_armclk,
+        &exynos5_clk_dout_arm2clk,
+        &exynos5_clk_cdrex,
+        &exynos5_clk_aclk_400,
+        &exynos5_clk_aclk_333,
+        &exynos5_clk_aclk_266,
+        &exynos5_clk_aclk_200,
+        &exynos5_clk_aclk_166,
+        &exynos5_clk_aclk_66_pre,
+        &exynos5_clk_aclk_66,
+        &exynos5_clk_dout_mmc0,
+        &exynos5_clk_dout_mmc1,
+        &exynos5_clk_dout_mmc2,
+        &exynos5_clk_dout_mmc3,
+        &exynos5_clk_dout_mmc4,
+        &exynos5_clk_aclk_acp,
+        &exynos5_clk_pclk_acp,
+};
+
+static struct clk *exynos5_clk_cdev[] = {
+        &exynos5_clk_pdma0,
+        &exynos5_clk_pdma1,
+        &exynos5_clk_mdma1,
+};
+
+static struct clksrc_clk *exynos5_clksrc_cdev[] = {
+        &exynos5_clk_sclk_uart0,
+        &exynos5_clk_sclk_uart1,
+        &exynos5_clk_sclk_uart2,
+        &exynos5_clk_sclk_uart3,
+        &exynos5_clk_sclk_mmc0,
+        &exynos5_clk_sclk_mmc1,
+        &exynos5_clk_sclk_mmc2,
+        &exynos5_clk_sclk_mmc3,
+};
+
+static struct clk_lookup exynos5_clk_lookup[] = {
+        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
+        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
+        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
+        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
+        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+        &exynos5_clk_sclk_hdmi27m,
+        &exynos5_clk_sclk_hdmiphy,
+        &clk_fout_bpll,
+        &clk_fout_cpll,
+        &exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+        { 192000000, 0, 48, 3, 1, 0 },
+        { 180000000, 0, 45, 3, 1, 0 },
+        {  73728000, 1, 73, 3, 3, 47710 },
+        {  67737600, 1, 90, 4, 3, 20762 },
+        {  49152000, 0, 49, 3, 3, 9961 },
+        {  45158400, 0, 45, 3, 3, 10381 },
+        { 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+        unsigned int tmp;
+        unsigned int epll_rate;
+        unsigned int locktime;
+        unsigned int lockcnt;
+
+        /* Return if nothing changed */
+        if (clk->rate == rate)
+                return 0;
+
+        if (clk->parent)
+                epll_rate = clk_get_rate(clk->parent);
+        else
+                epll_rate = clk_ext_xtal_mux.rate;
+
+        if (epll_rate != 24000000) {
+                pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+                return -EINVAL;
+        }
+
+        epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+        epll_con &= ~(0x1 << 27 | \
+                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                if (epll_div[i][0] == rate) {
+                        epll_con_k = epll_div[i][5] << 0;
+                        epll_con |= epll_div[i][1] << 27;
+                        epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                        epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+                        epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        epll_rate /= 1000000;
+
+        /* 3000 max_cycls : specification data */
+        locktime = 3000 / epll_rate * epll_div[i][3];
+        lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+        __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+        __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+        __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+        do {
+                tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+        } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+        .get_rate = exynos5_epll_get_rate,
+        .set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+        return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+        .get_rate = exynos5_fout_apll_get_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+        return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+struct syscore_ops exynos5_clock_syscore_ops = {
+        .suspend        = exynos5_clock_suspend,
+        .resume         = exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+        unsigned long apll;
+        unsigned long bpll;
+        unsigned long cpll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned long vpll;
+        unsigned long vpllsrc;
+        unsigned long xtal;
+        unsigned long armclk;
+        unsigned long mout_cdrex;
+        unsigned long aclk_400;
+        unsigned long aclk_333;
+        unsigned long aclk_266;
+        unsigned long aclk_200;
+        unsigned long aclk_166;
+        unsigned long aclk_66;
+        unsigned int ptr;
+
+        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+        xtal_clk = clk_get(NULL, "xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+
+        xtal_rate = xtal;
+
+        clk_put(xtal_clk);
+
+        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+        apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+        bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+        cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+        mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+        epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+                        __raw_readl(EXYNOS5_EPLL_CON1));
+
+        vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
+        vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+                        __raw_readl(EXYNOS5_VPLL_CON1));
+
+        clk_fout_apll.ops = &exynos5_fout_apll_ops;
+        clk_fout_bpll.rate = bpll;
+        clk_fout_cpll.rate = cpll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_vpll.rate = vpll;
+
+        printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+                        "M=%ld, E=%ld V=%ld",
+                        apll, bpll, cpll, mpll, epll, vpll);
+
+        armclk = clk_get_rate(&exynos5_clk_armclk);
+        mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
+
+        aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+        aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+        aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+        aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+        aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+        aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+        printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+                        "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+                        "ACLK166=%ld, ACLK66=%ld\n",
+                        armclk, mout_cdrex, aclk_400,
+                        aclk_333, aclk_266, aclk_200,
+                        aclk_166, aclk_66);
+
+
+        clk_fout_epll.ops = &exynos5_epll_ops;
+
+        if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+                printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+                                clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+        clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+        clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+        clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+        clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+                s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+        int ptr;
+
+        s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+                s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+                s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
+                s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
+
+        s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+        s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
+
+        s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
+                s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
+
+        s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+        s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+        clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
+
+        register_syscore_ops(&exynos5_clock_syscore_ops);
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
deleted file mode 100644
index 187287aa57a..00000000000
--- a/arch/arm/mach-exynos/clock.c
+++ /dev/null
@@ -1,1564 +0,0 @@
-/* linux/arch/arm/mach-exynos4/clock.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
-#include <mach/exynos4-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKSRC_TOP0),
-        SAVE_ITEM(S5P_CLKSRC_TOP1),
-        SAVE_ITEM(S5P_CLKSRC_CAM),
-        SAVE_ITEM(S5P_CLKSRC_TV),
-        SAVE_ITEM(S5P_CLKSRC_MFC),
-        SAVE_ITEM(S5P_CLKSRC_G3D),
-        SAVE_ITEM(S5P_CLKSRC_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_CAM),
-        SAVE_ITEM(S5P_CLKDIV_TV),
-        SAVE_ITEM(S5P_CLKDIV_MFC),
-        SAVE_ITEM(S5P_CLKDIV_G3D),
-        SAVE_ITEM(S5P_CLKDIV_LCD0),
-        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-        SAVE_ITEM(S5P_CLKDIV_FSYS0),
-        SAVE_ITEM(S5P_CLKDIV_FSYS1),
-        SAVE_ITEM(S5P_CLKDIV_FSYS2),
-        SAVE_ITEM(S5P_CLKDIV_FSYS3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL0),
-        SAVE_ITEM(S5P_CLKDIV_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_PERIL2),
-        SAVE_ITEM(S5P_CLKDIV_PERIL3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL4),
-        SAVE_ITEM(S5P_CLKDIV_PERIL5),
-        SAVE_ITEM(S5P_CLKDIV_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV2_RATIO),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_TV),
-        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-        SAVE_ITEM(S5P_CLKGATE_BLOCK),
-        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-        SAVE_ITEM(S5P_CLKSRC_DMC),
-        SAVE_ITEM(S5P_CLKDIV_DMC0),
-        SAVE_ITEM(S5P_CLKDIV_DMC1),
-        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-        SAVE_ITEM(S5P_CLKSRC_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-};
-#endif
-
-struct clk clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-struct clk clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-struct clk clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-
-struct clk clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-struct clksrc_clk clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &clk_mout_apll.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources        = &clk_src_mpll,
-
-        /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *clkset_moutcore_list[] = {
-        [0] = &clk_mout_apll.clk,
-        [1] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_moutcore = {
-        .sources        = clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
-};
-
-static struct clksrc_clk clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources        = &clkset_moutcore,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &clk_moutcore.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &clk_coreclk.clk,
-        },
-};
-
-static struct clksrc_clk clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-struct clk *clkset_corebus_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_mout_corebus = {
-        .sources        = clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
-};
-
-static struct clksrc_clk clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources        = &clkset_mout_corebus,
-        .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &clk_mout_corebus.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &clk_sclk_dmc.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &clk_aclk_cored.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &clk_mout_corebus.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &clk_aclk_acp.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *clkset_aclk_top_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_aclk = {
-        .sources        = clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
-static struct clksrc_clk clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources clkset_vpllsrc = {
-        .sources        = clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources        = &clkset_vpllsrc,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_vpll_list[] = {
-        [0] = &clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources clkset_sclk_vpll = {
-        .sources        = clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
-};
-
-struct clksrc_clk clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources        = &clkset_sclk_vpll,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.0",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "dwmmc",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "SYSMMU_MDMA",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "SYSMMU_FIMC0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "SYSMMU_FIMC1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "SYSMMU_FIMC2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "SYSMMU_FIMC3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "SYSMMU_JPEG",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "SYSMMU_FIMD0",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_FIMD1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_PCIe",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "SYSMMU_G2D",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "SYSMMU_ROTATOR",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_TV",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_MFC_L",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "SYSMMU_MFC_R",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }
-};
-
-static struct clk init_clocks[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-struct clk *clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &clk_sclk_hdmi27m,
-        [3] = &clk_sclk_usbphy0,
-        [4] = &clk_sclk_usbphy1,
-        [5] = &clk_sclk_hdmiphy,
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-        [8] = &clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources clkset_group = {
-        .sources        = clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group_list),
-};
-
-static struct clk *clkset_mout_g2d0_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d0 = {
-        .sources        = clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
-};
-
-static struct clksrc_clk clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources        = &clkset_mout_g2d0,
-        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d1 = {
-        .sources        = clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
-};
-
-static struct clksrc_clk clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources        = &clkset_mout_g2d1,
-        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d_list[] = {
-        [0] = &clk_mout_g2d0.clk,
-        [1] = &clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d = {
-        .sources        = clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
-};
-
-static struct clk *clkset_mout_mfc0_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc0 = {
-        .sources        = clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources        = &clkset_mout_mfc0,
-        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc1 = {
-        .sources        = clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources        = &clkset_mout_mfc1,
-        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc_list[] = {
-        [0] = &clk_mout_mfc0.clk,
-        [1] = &clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc = {
-        .sources        = clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
-};
-
-static struct clk *clkset_sclk_dac_list[] = {
-        [0] = &clk_sclk_vpll.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_dac = {
-        .sources        = clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &clkset_sclk_dac,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent = &clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *clkset_sclk_hdmi_list[] = {
-        [0] = &clk_sclk_pixel.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_hdmi = {
-        .sources        = clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &clkset_sclk_hdmi,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_mixer_list[] = {
-        [0] = &clk_sclk_dac.clk,
-        [1] = &clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources clkset_sclk_mixer = {
-        .sources        = clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk clk_sclk_mixer = {
-        .clk            = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &clkset_sclk_mixer,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *sclk_tv[] = {
-        &clk_sclk_dac,
-        &clk_sclk_pixel,
-        &clk_sclk_hdmi,
-        &clk_sclk_mixer,
-};
-
-static struct clksrc_clk clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &clkset_mout_g2d,
-                .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &clkset_mout_mfc,
-                .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_dwmmc",
-                        .parent         = &clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-
-static struct clksrc_clk clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart1 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart2 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart3 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc3 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.0",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 16),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.1",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 20),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi2 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.2",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 24),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_sclk_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_moutcore,
-        &clk_coreclk,
-        &clk_armclk,
-        &clk_aclk_corem0,
-        &clk_aclk_cores,
-        &clk_aclk_corem1,
-        &clk_periphclk,
-        &clk_mout_corebus,
-        &clk_sclk_dmc,
-        &clk_aclk_cored,
-        &clk_aclk_corep,
-        &clk_aclk_acp,
-        &clk_pclk_acp,
-        &clk_vpllsrc,
-        &clk_sclk_vpll,
-        &clk_aclk_200,
-        &clk_aclk_100,
-        &clk_aclk_160,
-        &clk_aclk_133,
-        &clk_dout_mmc0,
-        &clk_dout_mmc1,
-        &clk_dout_mmc2,
-        &clk_dout_mmc3,
-        &clk_dout_mmc4,
-        &clk_mout_mfc0,
-        &clk_mout_mfc1,
-};
-
-static struct clk *clk_cdev[] = {
-        &clk_pdma0,
-        &clk_pdma1,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uart0,
-        &clk_sclk_uart1,
-        &clk_sclk_uart2,
-        &clk_sclk_uart3,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_sclk_mmc3,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-        &clk_sclk_spi2,
-
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
-        else
-                return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con0 = __raw_readl(S5P_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        vpll_con1 = __raw_readl(S5P_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
-                if (vpll_div[i][0] == rate) {
-                        vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con0, S5P_VPLL_CON0);
-        __raw_writel(vpll_con1, S5P_VPLL_CON1);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                        __raw_readl(S5P_EPLL_CON1), pll_4600);
-
-                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                        __raw_readl(S5P_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                        __raw_readl(S5P_EPLL_CON1));
-
-                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                        __raw_readl(S5P_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
-
-        aclk_200 = clk_get_rate(&clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&clk_aclk_133.clk);
-
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_sclk_hdmi27m,
-        &clk_sclk_hdmiphy,
-        &clk_sclk_usbphy0,
-        &clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
-                s3c_register_clksrc(sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-                s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
-                s3c_disable_clocks(clk_cdev[ptr], 1);
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 6de298c5d2d..e6cc50e94a5 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -26,10 +26,12 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/cacheflush.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
+#include <mach/pmu.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -45,10 +47,20 @@
 #include <plat/regs-serial.h>
 
 #include "common.h"
+#define L2_AUX_VAL 0x7C470001
+#define L2_AUX_MASK 0xC200ffff
 
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
+static const char name_exynos5250[] = "EXYNOS5250";
+
+static void exynos4_map_io(void);
+static void exynos5_map_io(void);
+static void exynos4_init_clocks(int xtal);
+static void exynos5_init_clocks(int xtal);
+static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static int exynos_init(void);
 
 static struct cpu_table cpu_ids[] __initdata = {
         {
@@ -56,7 +68,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
                 .init_clocks    = exynos4_init_clocks,
-                .init_uarts     = exynos4_init_uarts,
+                .init_uarts     = exynos_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
         }, {
@@ -64,7 +76,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
                 .init_clocks    = exynos4_init_clocks,
-                .init_uarts     = exynos4_init_uarts,
+                .init_uarts     = exynos_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
         }, {
@@ -72,9 +84,17 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
                 .init_clocks    = exynos4_init_clocks,
-                .init_uarts     = exynos4_init_uarts,
+                .init_uarts     = exynos_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
+        }, {
+                .idcode         = EXYNOS5250_SOC_ID,
+                .idmask         = EXYNOS5_SOC_MASK,
+                .map_io         = exynos5_map_io,
+                .init_clocks    = exynos5_init_clocks,
+                .init_uarts     = exynos_init_uarts,
+                .init           = exynos_init,
+                .name           = name_exynos5250,
         },
 };
 
@@ -83,10 +103,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 static struct map_desc exynos_iodesc[] __initdata = {
         {
                 .virtual        = (unsigned long)S5P_VA_CHIPID,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
+                .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
-        }, {
+        },
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+        {
                 .virtual        = (unsigned long)S3C_VA_SYS,
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
                 .length         = SZ_64K,
@@ -136,11 +160,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
-        },
-};
-
-static struct map_desc exynos4_iodesc[] __initdata = {
-        {
+        }, {
                 .virtual        = (unsigned long)S5P_VA_CMU,
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                 .length         = SZ_128K,
@@ -156,24 +176,14 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO1,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO2,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO3,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
-                .length         = SZ_256,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_DMC0,
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
-                .length         = SZ_4K,
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_DMC1,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
+                .length         = SZ_64K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
@@ -201,19 +211,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
         },
 };
 
-static void exynos_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-
-        local_irq_enable();
-}
+static struct map_desc exynos5_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_SYS,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_TIMER,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_CMU,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
+                .length         = 144 * SZ_1K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_PMU,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_COMBINER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+                .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        },
+};
 
 void exynos4_restart(char mode, const char *cmd)
 {
         __raw_writel(0x1, S5P_SWRESET);
 }
 
+void exynos5_restart(char mode, const char *cmd)
+{
+        __raw_writel(0x1, EXYNOS_SWRESET);
+}
+
 /*
  * exynos_map_io
  *
@@ -233,7 +304,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 
-void __init exynos4_map_io(void)
+static void __init exynos4_map_io(void)
 {
         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
@@ -264,7 +335,22 @@ void __init exynos4_map_io(void)
         s5p_hdmi_setname("exynos4-hdmi");
 }
 
-void __init exynos4_init_clocks(int xtal)
+static void __init exynos5_map_io(void)
+{
+        iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+        s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
+        s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
+        s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
+        s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
+
+        /* The I2C bus controllers are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+        s3c_i2c2_setname("s3c2440-i2c");
+}
+
+static void __init exynos4_init_clocks(int xtal)
 {
         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 
@@ -280,6 +366,17 @@ void __init exynos4_init_clocks(int xtal)
         exynos4_setup_clocks();
 }
 
+static void __init exynos5_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+
+        exynos5_register_clocks();
+        exynos5_setup_clocks();
+}
+
 #define COMBINER_ENABLE_SET     0x0
 #define COMBINER_ENABLE_CLEAR   0x4
 #define COMBINER_INT_STATUS     0xC
@@ -353,7 +450,14 @@ static struct irq_chip combiner_chip = {
 
 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 {
-        if (combiner_nr >= MAX_COMBINER_NR)
+        unsigned int max_nr;
+
+        if (soc_is_exynos5250())
+                max_nr = EXYNOS5_MAX_COMBINER_NR;
+        else
+                max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+        if (combiner_nr >= max_nr)
                 BUG();
         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
                 BUG();
@@ -364,8 +468,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
                           unsigned int irq_start)
 {
         unsigned int i;
+        unsigned int max_nr;
 
-        if (combiner_nr >= MAX_COMBINER_NR)
+        if (soc_is_exynos5250())
+                max_nr = EXYNOS5_MAX_COMBINER_NR;
+        else
+                max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+        if (combiner_nr >= max_nr)
                 BUG();
 
         combiner_data[combiner_nr].base = base;
@@ -408,7 +518,7 @@ void __init exynos4_init_irq(void)
                 of_irq_init(exynos4_dt_irq_match);
 #endif
 
-        for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+        for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
 
                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
                                 COMBINER_IRQ(irq, 0));
@@ -423,60 +533,144 @@ void __init exynos4_init_irq(void)
         s5p_init_irq(NULL, 0);
 }
 
+void __init exynos5_init_irq(void)
+{
+        int irq;
+
+        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+
+        for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
+                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+                                COMBINER_IRQ(irq, 0));
+                combiner_cascade_irq(irq, IRQ_SPI(irq));
+        }
+
+        /*
+         * The parameters of s5p_init_irq() are for VIC init.
+         * Theses parameters should be NULL and 0 because EXYNOS4
+         * uses GIC instead of VIC.
+         */
+        s5p_init_irq(NULL, 0);
+}
+
 struct bus_type exynos4_subsys = {
         .name           = "exynos4-core",
         .dev_name       = "exynos4-core",
 };
 
+struct bus_type exynos5_subsys = {
+        .name           = "exynos5-core",
+        .dev_name       = "exynos5-core",
+};
+
 static struct device exynos4_dev = {
         .bus    = &exynos4_subsys,
 };
 
-static int __init exynos4_core_init(void)
+static struct device exynos5_dev = {
+        .bus    = &exynos5_subsys,
+};
+
+static int __init exynos_core_init(void)
 {
-        return subsys_system_register(&exynos4_subsys, NULL);
+        if (soc_is_exynos5250())
+                return subsys_system_register(&exynos5_subsys, NULL);
+        else
+                return subsys_system_register(&exynos4_subsys, NULL);
 }
-core_initcall(exynos4_core_init);
+core_initcall(exynos_core_init);
 
 #ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
-        /* TAG, Data Latency Control: 2cycle */
-        __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+        if (soc_is_exynos5250())
+                return 0;
+
+        int ret;
+        ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
+        if (!ret) {
+                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+                return 0;
+        }
 
-        if (soc_is_exynos4210())
-                __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
+                l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
+                /* TAG, Data Latency Control: 2 cycles */
+                l2x0_saved_regs.tag_latency = 0x110;
+
+                if (soc_is_exynos4212() || soc_is_exynos4412())
+                        l2x0_saved_regs.data_latency = 0x120;
+                else
+                        l2x0_saved_regs.data_latency = 0x110;
 
-        /* L2X0 Prefetch Control */
-        __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+                l2x0_saved_regs.prefetch_ctrl = 0x30000007;
+                l2x0_saved_regs.pwr_ctrl =
+                        (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 
-        /* L2X0 Power Control */
-        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
-                     S5P_VA_L2CC + L2X0_POWER_CTRL);
+                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 
-        l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
+                __raw_writel(l2x0_saved_regs.tag_latency,
+                                S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+                __raw_writel(l2x0_saved_regs.data_latency,
+                                S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 
+                /* L2X0 Prefetch Control */
+                __raw_writel(l2x0_saved_regs.prefetch_ctrl,
+                                S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+
+                /* L2X0 Power Control */
+                __raw_writel(l2x0_saved_regs.pwr_ctrl,
+                                S5P_VA_L2CC + L2X0_POWER_CTRL);
+
+                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+                clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
+        }
+
+        l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
         return 0;
 }
-
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-int __init exynos_init(void)
+static int __init exynos5_l2_cache_init(void)
 {
-        printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+        unsigned int val;
+
+        if (!soc_is_exynos5250())
+                return 0;
+
+        asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+                     "bic %0, %0, #(1 << 2)\n"  /* cache disable */
+                     "mcr p15, 0, %0, c1, c0, 0\n"
+                     "mrc p15, 1, %0, c9, c0, 2\n"
+                     : "=r"(val));
+
+        val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
+
+        asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+        asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+                     "orr %0, %0, #(1 << 2)\n"  /* cache enable */
+                     "mcr p15, 0, %0, c1, c0, 0\n"
+                     : : "r"(val));
+
+        return 0;
+}
+early_initcall(exynos5_l2_cache_init);
 
-        /* set idle function */
-        pm_idle = exynos_idle;
+static int __init exynos_init(void)
+{
+        printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-        return device_register(&exynos4_dev);
+        if (soc_is_exynos5250())
+                return device_register(&exynos5_dev);
+        else
+                return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
 
-void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
         struct s3c2410_uartcfg *tcfg = cfg;
         u32 ucnt;
@@ -484,69 +678,138 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
                 tcfg->has_fracval = 1;
 
-        s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+        if (soc_is_exynos5250())
+                s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
+        else
+                s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 
+static void __iomem *exynos_eint_base;
+
 static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
-static unsigned int exynos4_get_irq_nr(unsigned int number)
+static inline int exynos4_irq_to_gpio(unsigned int irq)
 {
-        u32 ret = 0;
+        if (irq < IRQ_EINT(0))
+                return -EINVAL;
 
-        switch (number) {
-        case 0 ... 3:
-                ret = (number + IRQ_EINT0);
-                break;
-        case 4 ... 7:
-                ret = (number + (IRQ_EINT4 - 4));
-                break;
-        case 8 ... 15:
-                ret = (number + (IRQ_EINT8 - 8));
-                break;
-        default:
-                printk(KERN_ERR "number available : %d\n", number);
-        }
+        irq -= IRQ_EINT(0);
+        if (irq < 8)
+                return EXYNOS4_GPX0(irq);
+
+        irq -= 8;
+        if (irq < 8)
+                return EXYNOS4_GPX1(irq);
+
+        irq -= 8;
+        if (irq < 8)
+                return EXYNOS4_GPX2(irq);
 
-        return ret;
+        irq -= 8;
+        if (irq < 8)
+                return EXYNOS4_GPX3(irq);
+
+        return -EINVAL;
 }
 
-static inline void exynos4_irq_eint_mask(struct irq_data *data)
+static inline int exynos5_irq_to_gpio(unsigned int irq)
+{
+        if (irq < IRQ_EINT(0))
+                return -EINVAL;
+
+        irq -= IRQ_EINT(0);
+        if (irq < 8)
+                return EXYNOS5_GPX0(irq);
+
+        irq -= 8;
+        if (irq < 8)
+                return EXYNOS5_GPX1(irq);
+
+        irq -= 8;
+        if (irq < 8)
+                return EXYNOS5_GPX2(irq);
+
+        irq -= 8;
+        if (irq < 8)
+                return EXYNOS5_GPX3(irq);
+
+        return -EINVAL;
+}
+
+static unsigned int exynos4_eint0_15_src_int[16] = {
+        EXYNOS4_IRQ_EINT0,
+        EXYNOS4_IRQ_EINT1,
+        EXYNOS4_IRQ_EINT2,
+        EXYNOS4_IRQ_EINT3,
+        EXYNOS4_IRQ_EINT4,
+        EXYNOS4_IRQ_EINT5,
+        EXYNOS4_IRQ_EINT6,
+        EXYNOS4_IRQ_EINT7,
+        EXYNOS4_IRQ_EINT8,
+        EXYNOS4_IRQ_EINT9,
+        EXYNOS4_IRQ_EINT10,
+        EXYNOS4_IRQ_EINT11,
+        EXYNOS4_IRQ_EINT12,
+        EXYNOS4_IRQ_EINT13,
+        EXYNOS4_IRQ_EINT14,
+        EXYNOS4_IRQ_EINT15,
+};
+
+static unsigned int exynos5_eint0_15_src_int[16] = {
+        EXYNOS5_IRQ_EINT0,
+        EXYNOS5_IRQ_EINT1,
+        EXYNOS5_IRQ_EINT2,
+        EXYNOS5_IRQ_EINT3,
+        EXYNOS5_IRQ_EINT4,
+        EXYNOS5_IRQ_EINT5,
+        EXYNOS5_IRQ_EINT6,
+        EXYNOS5_IRQ_EINT7,
+        EXYNOS5_IRQ_EINT8,
+        EXYNOS5_IRQ_EINT9,
+        EXYNOS5_IRQ_EINT10,
+        EXYNOS5_IRQ_EINT11,
+        EXYNOS5_IRQ_EINT12,
+        EXYNOS5_IRQ_EINT13,
+        EXYNOS5_IRQ_EINT14,
+        EXYNOS5_IRQ_EINT15,
+};
+static inline void exynos_irq_eint_mask(struct irq_data *data)
 {
         u32 mask;
 
         spin_lock(&eint_lock);
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        mask |= eint_irq_to_bit(data->irq);
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+        mask |= EINT_OFFSET_BIT(data->irq);
+        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
         spin_unlock(&eint_lock);
 }
 
-static void exynos4_irq_eint_unmask(struct irq_data *data)
+static void exynos_irq_eint_unmask(struct irq_data *data)
 {
         u32 mask;
 
         spin_lock(&eint_lock);
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        mask &= ~(eint_irq_to_bit(data->irq));
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+        mask &= ~(EINT_OFFSET_BIT(data->irq));
+        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
         spin_unlock(&eint_lock);
 }
 
-static inline void exynos4_irq_eint_ack(struct irq_data *data)
+static inline void exynos_irq_eint_ack(struct irq_data *data)
 {
-        __raw_writel(eint_irq_to_bit(data->irq),
-                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+        __raw_writel(EINT_OFFSET_BIT(data->irq),
+                     EINT_PEND(exynos_eint_base, data->irq));
 }
 
-static void exynos4_irq_eint_maskack(struct irq_data *data)
+static void exynos_irq_eint_maskack(struct irq_data *data)
 {
-        exynos4_irq_eint_mask(data);
-        exynos4_irq_eint_ack(data);
+        exynos_irq_eint_mask(data);
+        exynos_irq_eint_ack(data);
 }
 
-static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
         int offs = EINT_OFFSET(data->irq);
         int shift;
@@ -583,39 +846,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
         mask = 0x7 << shift;
 
         spin_lock(&eint_lock);
-        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+        ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
         ctrl &= ~mask;
         ctrl |= newvalue << shift;
-        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+        __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
         spin_unlock(&eint_lock);
 
-        switch (offs) {
-        case 0 ... 7:
-                s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
-                break;
-        case 8 ... 15:
-                s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
-                break;
-        case 16 ... 23:
-                s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
-                break;
-        case 24 ... 31:
-                s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
-                break;
-        default:
-                printk(KERN_ERR "No such irq number %d", offs);
-        }
+        if (soc_is_exynos5250())
+                s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
+        else
+                s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 
         return 0;
 }
 
-static struct irq_chip exynos4_irq_eint = {
-        .name           = "exynos4-eint",
-        .irq_mask       = exynos4_irq_eint_mask,
-        .irq_unmask     = exynos4_irq_eint_unmask,
-        .irq_mask_ack   = exynos4_irq_eint_maskack,
-        .irq_ack        = exynos4_irq_eint_ack,
-        .irq_set_type   = exynos4_irq_eint_set_type,
+static struct irq_chip exynos_irq_eint = {
+        .name           = "exynos-eint",
+        .irq_mask       = exynos_irq_eint_mask,
+        .irq_unmask     = exynos_irq_eint_unmask,
+        .irq_mask_ack   = exynos_irq_eint_maskack,
+        .irq_ack        = exynos_irq_eint_ack,
+        .irq_set_type   = exynos_irq_eint_set_type,
 #ifdef CONFIG_PM
         .irq_set_wake   = s3c_irqext_wake,
 #endif
@@ -630,12 +881,12 @@ static struct irq_chip exynos4_irq_eint = {
  *
  * Each EINT pend/mask registers handle eight of them.
  */
-static inline void exynos4_irq_demux_eint(unsigned int start)
+static inline void exynos_irq_demux_eint(unsigned int start)
 {
         unsigned int irq;
 
-        u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-        u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+        u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
+        u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 
         status &= ~mask;
         status &= 0xff;
@@ -647,16 +898,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
         }
 }
 
-static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
         struct irq_chip *chip = irq_get_chip(irq);
         chained_irq_enter(chip, desc);
-        exynos4_irq_demux_eint(IRQ_EINT(16));
-        exynos4_irq_demux_eint(IRQ_EINT(24));
+        exynos_irq_demux_eint(IRQ_EINT(16));
+        exynos_irq_demux_eint(IRQ_EINT(24));
         chained_irq_exit(chip, desc);
 }
 
-static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
         u32 *irq_data = irq_get_handler_data(irq);
         struct irq_chip *chip = irq_get_chip(irq);
@@ -673,27 +924,44 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
         chained_irq_exit(chip, desc);
 }
 
-int __init exynos4_init_irq_eint(void)
+static int __init exynos_init_irq_eint(void)
 {
         int irq;
 
+        if (soc_is_exynos5250())
+                exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
+        else
+                exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
+
+        if (exynos_eint_base == NULL) {
+                pr_err("unable to ioremap for EINT base address\n");
+                return -ENOMEM;
+        }
+
         for (irq = 0 ; irq <= 31 ; irq++) {
-                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
                                          handle_level_irq);
                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
         }
 
-        irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+        irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
         for (irq = 0 ; irq <= 15 ; irq++) {
                 eint0_15_data[irq] = IRQ_EINT(irq);
 
-                irq_set_handler_data(exynos4_get_irq_nr(irq),
-                                     &eint0_15_data[irq]);
-                irq_set_chained_handler(exynos4_get_irq_nr(irq),
-                                        exynos4_irq_eint0_15);
+                if (soc_is_exynos5250()) {
+                        irq_set_handler_data(exynos5_eint0_15_src_int[irq],
+                                             &eint0_15_data[irq]);
+                        irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
+                                                exynos_irq_eint0_15);
+                } else {
+                        irq_set_handler_data(exynos4_eint0_15_src_int[irq],
+                                             &eint0_15_data[irq]);
+                        irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
+                                                exynos_irq_eint0_15);
+                }
         }
 
         return 0;
 }
-arch_initcall(exynos4_init_irq_eint);
+arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ac49de0f39..677b5467df1 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,30 +12,44 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+extern struct sys_timer exynos4_timer;
+
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos5_init_irq(void);
+void exynos4_restart(char mode, const char *cmd);
+void exynos5_restart(char mode, const char *cmd);
 
+#ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 
-void exynos4210_register_clocks(void);
-void exynos4212_register_clocks(void);
+#else
+#define exynos4_register_clocks()
+#define exynos4_setup_clocks()
+#endif
 
-void exynos4_restart(char mode, const char *cmd);
+#ifdef CONFIG_ARCH_EXYNOS5
+void exynos5_register_clocks(void);
+void exynos5_setup_clocks(void);
 
-extern struct sys_timer exynos4_timer;
+#else
+#define exynos5_register_clocks()
+#define exynos5_setup_clocks()
+#endif
+
+#ifdef CONFIG_CPU_EXYNOS4210
+void exynos4210_register_clocks(void);
 
-#ifdef CONFIG_ARCH_EXYNOS
-extern  int exynos_init(void);
-extern void exynos4_map_io(void);
-extern void exynos4_init_clocks(int xtal);
-extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define exynos4210_register_clocks()
+#endif
+
+#ifdef CONFIG_SOC_EXYNOS4212
+void exynos4212_register_clocks(void);
 
 #else
-#define exynos4_init_clocks NULL
-#define exynos4_init_uarts NULL
-#define exynos4_map_io NULL
-#define exynos_init NULL
+#define exynos4212_register_clocks()
 #endif
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4ebb382c597..33ab4e7558a 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -11,25 +11,53 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
 #include <linux/io.h>
 #include <linux/export.h>
 #include <linux/time.h>
 
 #include <asm/proc-fns.h>
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include <asm/unified.h>
+#include <mach/regs-pmu.h>
+#include <mach/pmu.h>
+
+#include <plat/cpu.h>
+
+#define REG_DIRECTGO_ADDR       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                        S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+#define REG_DIRECTGO_FLAG       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                        S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+
+#define S5P_CHECK_AFTR          0xFCBA0D10
 
 static int exynos4_enter_idle(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                               int index);
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index);
 
-static struct cpuidle_state exynos4_cpuidle_set[] = {
+static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
         [0] = {
                 .enter                  = exynos4_enter_idle,
                 .exit_latency           = 1,
                 .target_residency       = 100000,
                 .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "IDLE",
+                .name                   = "C0",
                 .desc                   = "ARM clock gating(WFI)",
         },
+        [1] = {
+                .enter                  = exynos4_enter_lowpower,
+                .exit_latency           = 300,
+                .target_residency       = 100000,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "C1",
+                .desc                   = "ARM power down",
+        },
 };
 
 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
@@ -39,9 +67,102 @@ static struct cpuidle_driver exynos4_idle_driver = {
         .owner          = THIS_MODULE,
 };
 
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos4_set_wakeupmask(void)
+{
+        __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
+}
+
+static unsigned int g_pwr_ctrl, g_diag_reg;
+
+static void save_cpu_arch_register(void)
+{
+        /*read power control register*/
+        asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
+        /*read diagnostic register*/
+        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
+        return;
+}
+
+static void restore_cpu_arch_register(void)
+{
+        /*write power control register*/
+        asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
+        /*write diagnostic register*/
+        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
+        return;
+}
+
+static int idle_finisher(unsigned long flags)
+{
+        cpu_do_idle();
+        return 1;
+}
+
+static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index)
+{
+        struct timeval before, after;
+        int idle_time;
+        unsigned long tmp;
+
+        local_irq_disable();
+        do_gettimeofday(&before);
+
+        exynos4_set_wakeupmask();
+
+        /* Set value of power down register for aftr mode */
+        exynos4_sys_powerdown_conf(SYS_AFTR);
+
+        __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+        __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+
+        save_cpu_arch_register();
+
+        /* Setting Central Sequence Register for power down mode */
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+        cpu_pm_enter();
+        cpu_suspend(0, idle_finisher);
+
+#ifdef CONFIG_SMP
+        scu_enable(S5P_VA_SCU);
+#endif
+        cpu_pm_exit();
+
+        restore_cpu_arch_register();
+
+        /*
+         * If PMU failed while entering sleep mode, WFI will be
+         * ignored by PMU and then exiting cpu_do_idle().
+         * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+         * in this situation.
+         */
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+                tmp |= S5P_CENTRAL_LOWPWR_CFG;
+                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+        }
+
+        /* Clear wakeup state register */
+        __raw_writel(0x0, S5P_WAKEUP_STAT);
+
+        do_gettimeofday(&after);
+
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                    (after.tv_usec - before.tv_usec);
+
+        dev->last_residency = idle_time;
+        return index;
+}
+
 static int exynos4_enter_idle(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
-                              int index)
+                                int index)
 {
         struct timeval before, after;
         int idle_time;
@@ -60,6 +181,22 @@ static int exynos4_enter_idle(struct cpuidle_device *dev,
         return index;
 }
 
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index)
+{
+        int new_index = index;
+
+        /* This mode only can be entered when other core's are offline */
+        if (num_online_cpus() > 1)
+                new_index = drv->safe_state_index;
+
+        if (new_index == 0)
+                return exynos4_enter_idle(dev, drv, new_index);
+        else
+                return exynos4_enter_core0_aftr(dev, drv, new_index);
+}
+
 static int __init exynos4_init_cpuidle(void)
 {
         int i, max_cpuidle_state, cpu_id;
@@ -74,19 +211,25 @@ static int __init exynos4_init_cpuidle(void)
                 memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
                                 sizeof(struct cpuidle_state));
         }
+        drv->safe_state_index = 0;
         cpuidle_register_driver(&exynos4_idle_driver);
 
         for_each_cpu(cpu_id, cpu_online_mask) {
                 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
                 device->cpu = cpu_id;
 
-                device->state_count = drv->state_count;
+                if (cpu_id == 0)
+                        device->state_count = (sizeof(exynos4_cpuidle_set) /
+                                               sizeof(struct cpuidle_state));
+                else
+                        device->state_count = 1;        /* Support IDLE only */
 
                 if (cpuidle_register_device(device)) {
                         printk(KERN_ERR "CPUidle register device failed\n,");
                         return -EIO;
                 }
         }
+
         return 0;
 }
 device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index f57a3de8e1d..50ce5b0adcf 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_SATA,
-                .end    = IRQ_SATA,
+                .start  = EXYNOS4_IRQ_SATA,
+                .end    = EXYNOS4_IRQ_SATA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 5a9f9c2e53b..7199e1ae79b 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
                 .flags  = IORESOURCE_DMA,
         },
         [4] = {
-                .start  = IRQ_AC97,
-                .end    = IRQ_AC97,
+                .start  = EXYNOS4_IRQ_AC97,
+                .end    = EXYNOS4_IRQ_AC97,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 00000000000..2e85c022fd1
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Base EXYNOS UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+#define EXYNOS_UART_RESOURCE(_series, _nr)      \
+static struct resource exynos##_series##_uart##_nr##_resource[] = {     \
+        [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),        \
+        [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),  \
+};
+
+EXYNOS_UART_RESOURCE(4, 0)
+EXYNOS_UART_RESOURCE(4, 1)
+EXYNOS_UART_RESOURCE(4, 2)
+EXYNOS_UART_RESOURCE(4, 3)
+
+struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
+        [0] = {
+                .resources      = exynos4_uart0_resource,
+                .nr_resources   = ARRAY_SIZE(exynos4_uart0_resource),
+        },
+        [1] = {
+                .resources      = exynos4_uart1_resource,
+                .nr_resources   = ARRAY_SIZE(exynos4_uart1_resource),
+        },
+        [2] = {
+                .resources      = exynos4_uart2_resource,
+                .nr_resources   = ARRAY_SIZE(exynos4_uart2_resource),
+        },
+        [3] = {
+                .resources      = exynos4_uart3_resource,
+                .nr_resources   = ARRAY_SIZE(exynos4_uart3_resource),
+        },
+};
+
+EXYNOS_UART_RESOURCE(5, 0)
+EXYNOS_UART_RESOURCE(5, 1)
+EXYNOS_UART_RESOURCE(5, 2)
+EXYNOS_UART_RESOURCE(5, 3)
+
+struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
+        [0] = {
+                .resources      = exynos5_uart0_resource,
+                .nr_resources   = ARRAY_SIZE(exynos5_uart0_resource),
+        },
+        [1] = {
+                .resources      = exynos5_uart1_resource,
+                .nr_resources   = ARRAY_SIZE(exynos5_uart0_resource),
+        },
+        [2] = {
+                .resources      = exynos5_uart2_resource,
+                .nr_resources   = ARRAY_SIZE(exynos5_uart2_resource),
+        },
+        [3] = {
+                .resources      = exynos5_uart3_resource,
+                .nr_resources   = ARRAY_SIZE(exynos5_uart3_resource),
+        },
+};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index b10fcd270f0..3983abee426 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -29,6 +29,7 @@
 #include <asm/irq.h>
 #include <plat/devs.h>
 #include <plat/irqs.h>
+#include <plat/cpu.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
@@ -36,7 +37,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 pdma0_peri[] = {
+static u8 exynos4210_pdma0_peri[] = {
         DMACH_PCM0_RX,
         DMACH_PCM0_TX,
         DMACH_PCM2_RX,
@@ -69,28 +70,47 @@ u8 pdma0_peri[] = {
         DMACH_AC97_PCMOUT,
 };
 
-struct dma_pl330_platdata exynos4_pdma0_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri_id = pdma0_peri,
+static u8 exynos4212_pdma0_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM2_RX,
+        DMACH_PCM2_TX,
+        DMACH_MIPI_HSI0,
+        DMACH_MIPI_HSI1,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_SLIMBUS0_RX,
+        DMACH_SLIMBUS0_TX,
+        DMACH_SLIMBUS2_RX,
+        DMACH_SLIMBUS2_TX,
+        DMACH_SLIMBUS4_RX,
+        DMACH_SLIMBUS4_TX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
+        DMACH_MIPI_HSI4,
+        DMACH_MIPI_HSI5,
 };
 
-struct amba_device exynos4_device_pdma0 = {
-        .dev = {
-                .init_name = "dma-pl330.0",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &exynos4_pdma0_pdata,
-        },
-        .res = {
-                .start = EXYNOS4_PA_PDMA0,
-                .end = EXYNOS4_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+struct dma_pl330_platdata exynos4_pdma0_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
+        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
 
-u8 pdma1_peri[] = {
+static u8 exynos4210_pdma1_peri[] = {
         DMACH_PCM0_RX,
         DMACH_PCM0_TX,
         DMACH_PCM1_RX,
@@ -118,39 +138,94 @@ u8 pdma1_peri[] = {
         DMACH_SLIMBUS5_TX,
 };
 
-struct dma_pl330_platdata exynos4_pdma1_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri_id = pdma1_peri,
+static u8 exynos4212_pdma1_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM1_TX,
+        DMACH_MIPI_HSI2,
+        DMACH_MIPI_HSI3,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_SLIMBUS1_RX,
+        DMACH_SLIMBUS1_TX,
+        DMACH_SLIMBUS3_RX,
+        DMACH_SLIMBUS3_TX,
+        DMACH_SLIMBUS5_RX,
+        DMACH_SLIMBUS5_TX,
+        DMACH_SLIMBUS0AUX_RX,
+        DMACH_SLIMBUS0AUX_TX,
+        DMACH_SPDIF,
+        DMACH_MIPI_HSI6,
+        DMACH_MIPI_HSI7,
 };
 
-struct amba_device exynos4_device_pdma1 = {
-        .dev = {
-                .init_name = "dma-pl330.1",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &exynos4_pdma1_pdata,
-        },
-        .res = {
-                .start = EXYNOS4_PA_PDMA1,
-                .end = EXYNOS4_PA_PDMA1 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA1, NO_IRQ},
-        .periphid = 0x00041330,
+static struct dma_pl330_platdata exynos4_pdma1_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
+        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
+
+static u8 mdma_peri[] = {
+        DMACH_MTOM_0,
+        DMACH_MTOM_1,
+        DMACH_MTOM_2,
+        DMACH_MTOM_3,
+        DMACH_MTOM_4,
+        DMACH_MTOM_5,
+        DMACH_MTOM_6,
+        DMACH_MTOM_7,
+};
+
+static struct dma_pl330_platdata exynos4_mdma1_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(mdma_peri),
+        .peri_id = mdma_peri,
 };
 
+static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
+        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
+
 static int __init exynos4_dma_init(void)
 {
         if (of_have_populated_dt())
                 return 0;
 
+        if (soc_is_exynos4210()) {
+                exynos4_pdma0_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4210_pdma0_peri);
+                exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+                exynos4_pdma1_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4210_pdma1_peri);
+                exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                exynos4_pdma0_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4212_pdma0_peri);
+                exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+                exynos4_pdma1_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4212_pdma1_peri);
+                exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+        }
+
         dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
-        amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+        amba_device_register(&exynos4_pdma0_device, &iomem_resource);
 
         dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
-        amba_device_register(&exynos4_device_pdma1, &iomem_resource);
+        amba_device_register(&exynos4_pdma1_device, &iomem_resource);
+
+        dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
+        amba_device_register(&exynos4_mdma1_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
index 3df27f2d503..7517c3f417a 100644
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -32,3 +32,5 @@ struct exynos_dvfs_info {
 };
 
 extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16a67a..6c857ff0b5d 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
          */
 
         .macro addruart, rp, rv, tmp
-                ldr     \rp, = S3C_PA_UART
-                ldr     \rv, = S3C_VA_UART
+                mov     \rp, #0x10000000
+                ldr     \rp, [\rp, #0x0]
+                and     \rp, \rp, #0xf00000
+                teq     \rp, #0x500000          @@ EXYNOS5
+                ldreq   \rp, =EXYNOS5_PA_UART
+                movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
+                ldr     \rv, =S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
                 add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
                 add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
deleted file mode 100644
index 3ba4f547534..00000000000
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/entry-macro.S
- *
- * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for EXYNOS4 platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
deleted file mode 100644
index a07fcbf5525..00000000000
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clk clk_sclk_hdmi27m;
-extern struct clk clk_sclk_usbphy0;
-extern struct clk clk_sclk_usbphy1;
-extern struct clk clk_sclk_hdmiphy;
-
-extern struct clksrc_clk clk_sclk_apll;
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_aclk_133;
-extern struct clksrc_clk clk_mout_epll;
-extern struct clksrc_clk clk_sclk_vpll;
-
-extern struct clk *clkset_corebus_list[];
-extern struct clksrc_sources clkset_mout_corebus;
-
-extern struct clk *clkset_aclk_top_list[];
-extern struct clksrc_sources clkset_aclk;
-
-extern struct clk *clkset_group_list[];
-extern struct clksrc_sources clkset_group;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 80523ca9bb4..d7498afe036 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4 - GPIO lib support
+ * EXYNOS - GPIO lib support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,9 +12,13 @@
 #ifndef __ASM_ARCH_GPIO_H
 #define __ASM_ARCH_GPIO_H __FILE__
 
-/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
+/* Macro for EXYNOS GPIO numbering */
+
+#define EXYNOS_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+/* EXYNOS4 GPIO bank sizes */
 
-/* GPIO bank sizes */
 #define EXYNOS4_GPIO_A0_NR      (8)
 #define EXYNOS4_GPIO_A1_NR      (6)
 #define EXYNOS4_GPIO_B_NR       (8)
@@ -54,52 +57,50 @@
 #define EXYNOS4_GPIO_Y6_NR      (8)
 #define EXYNOS4_GPIO_Z_NR       (7)
 
-/* GPIO bank numbers */
-
-#define EXYNOS4_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+/* EXYNOS4 GPIO bank numbers */
 
-enum s5p_gpio_number {
+enum exynos4_gpio_number {
         EXYNOS4_GPIO_A0_START   = 0,
-        EXYNOS4_GPIO_A1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
-        EXYNOS4_GPIO_B_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
-        EXYNOS4_GPIO_C0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
-        EXYNOS4_GPIO_C1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
-        EXYNOS4_GPIO_D0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
-        EXYNOS4_GPIO_D1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
-        EXYNOS4_GPIO_E0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
-        EXYNOS4_GPIO_E1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
-        EXYNOS4_GPIO_E2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
-        EXYNOS4_GPIO_E3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
-        EXYNOS4_GPIO_E4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
-        EXYNOS4_GPIO_F0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
-        EXYNOS4_GPIO_F1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
-        EXYNOS4_GPIO_F2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
-        EXYNOS4_GPIO_F3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
-        EXYNOS4_GPIO_J0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
-        EXYNOS4_GPIO_J1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
-        EXYNOS4_GPIO_K0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
-        EXYNOS4_GPIO_K1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
-        EXYNOS4_GPIO_K2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
-        EXYNOS4_GPIO_K3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
-        EXYNOS4_GPIO_L0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
-        EXYNOS4_GPIO_L1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
-        EXYNOS4_GPIO_L2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
-        EXYNOS4_GPIO_X0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
-        EXYNOS4_GPIO_X1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
-        EXYNOS4_GPIO_X2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
-        EXYNOS4_GPIO_X3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
-        EXYNOS4_GPIO_Y0_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
-        EXYNOS4_GPIO_Y1_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
-        EXYNOS4_GPIO_Y2_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
-        EXYNOS4_GPIO_Y3_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
-        EXYNOS4_GPIO_Y4_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
-        EXYNOS4_GPIO_Y5_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
-        EXYNOS4_GPIO_Y6_START   = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
-        EXYNOS4_GPIO_Z_START    = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
+        EXYNOS4_GPIO_A1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
+        EXYNOS4_GPIO_B_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
+        EXYNOS4_GPIO_C0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
+        EXYNOS4_GPIO_C1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
+        EXYNOS4_GPIO_D0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
+        EXYNOS4_GPIO_D1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
+        EXYNOS4_GPIO_E0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+        EXYNOS4_GPIO_E1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
+        EXYNOS4_GPIO_E2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
+        EXYNOS4_GPIO_E3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
+        EXYNOS4_GPIO_E4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
+        EXYNOS4_GPIO_F0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
+        EXYNOS4_GPIO_F1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
+        EXYNOS4_GPIO_F2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
+        EXYNOS4_GPIO_F3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
+        EXYNOS4_GPIO_J0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
+        EXYNOS4_GPIO_J1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
+        EXYNOS4_GPIO_K0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
+        EXYNOS4_GPIO_K1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
+        EXYNOS4_GPIO_K2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
+        EXYNOS4_GPIO_K3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
+        EXYNOS4_GPIO_L0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
+        EXYNOS4_GPIO_L1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
+        EXYNOS4_GPIO_L2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
+        EXYNOS4_GPIO_X0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
+        EXYNOS4_GPIO_X1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
+        EXYNOS4_GPIO_X2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
+        EXYNOS4_GPIO_X3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
+        EXYNOS4_GPIO_Y0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
+        EXYNOS4_GPIO_Y1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
+        EXYNOS4_GPIO_Y2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
+        EXYNOS4_GPIO_Y3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
+        EXYNOS4_GPIO_Y4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
+        EXYNOS4_GPIO_Y5_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
+        EXYNOS4_GPIO_Y6_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
+        EXYNOS4_GPIO_Z_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
 };
 
 /* EXYNOS4 GPIO number definitions */
+
 #define EXYNOS4_GPA0(_nr)       (EXYNOS4_GPIO_A0_START + (_nr))
 #define EXYNOS4_GPA1(_nr)       (EXYNOS4_GPIO_A1_START + (_nr))
 #define EXYNOS4_GPB(_nr)        (EXYNOS4_GPIO_B_START + (_nr))
@@ -139,11 +140,147 @@ enum s5p_gpio_number {
 #define EXYNOS4_GPZ(_nr)        (EXYNOS4_GPIO_Z_START + (_nr))
 
 /* the end of the EXYNOS4 specific gpios */
+
 #define EXYNOS4_GPIO_END        (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
-#define S3C_GPIO_END            EXYNOS4_GPIO_END
 
-/* define the number of gpios we need to the one after the GPZ() range */
-#define ARCH_NR_GPIOS           (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +       \
-                                 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
+/* EXYNOS5 GPIO bank sizes */
+
+#define EXYNOS5_GPIO_A0_NR      (8)
+#define EXYNOS5_GPIO_A1_NR      (6)
+#define EXYNOS5_GPIO_A2_NR      (8)
+#define EXYNOS5_GPIO_B0_NR      (5)
+#define EXYNOS5_GPIO_B1_NR      (5)
+#define EXYNOS5_GPIO_B2_NR      (4)
+#define EXYNOS5_GPIO_B3_NR      (4)
+#define EXYNOS5_GPIO_C0_NR      (7)
+#define EXYNOS5_GPIO_C1_NR      (7)
+#define EXYNOS5_GPIO_C2_NR      (7)
+#define EXYNOS5_GPIO_C3_NR      (7)
+#define EXYNOS5_GPIO_D0_NR      (8)
+#define EXYNOS5_GPIO_D1_NR      (8)
+#define EXYNOS5_GPIO_Y0_NR      (6)
+#define EXYNOS5_GPIO_Y1_NR      (4)
+#define EXYNOS5_GPIO_Y2_NR      (6)
+#define EXYNOS5_GPIO_Y3_NR      (8)
+#define EXYNOS5_GPIO_Y4_NR      (8)
+#define EXYNOS5_GPIO_Y5_NR      (8)
+#define EXYNOS5_GPIO_Y6_NR      (8)
+#define EXYNOS5_GPIO_X0_NR      (8)
+#define EXYNOS5_GPIO_X1_NR      (8)
+#define EXYNOS5_GPIO_X2_NR      (8)
+#define EXYNOS5_GPIO_X3_NR      (8)
+#define EXYNOS5_GPIO_E0_NR      (8)
+#define EXYNOS5_GPIO_E1_NR      (2)
+#define EXYNOS5_GPIO_F0_NR      (4)
+#define EXYNOS5_GPIO_F1_NR      (4)
+#define EXYNOS5_GPIO_G0_NR      (8)
+#define EXYNOS5_GPIO_G1_NR      (8)
+#define EXYNOS5_GPIO_G2_NR      (2)
+#define EXYNOS5_GPIO_H0_NR      (4)
+#define EXYNOS5_GPIO_H1_NR      (8)
+#define EXYNOS5_GPIO_V0_NR      (8)
+#define EXYNOS5_GPIO_V1_NR      (8)
+#define EXYNOS5_GPIO_V2_NR      (8)
+#define EXYNOS5_GPIO_V3_NR      (8)
+#define EXYNOS5_GPIO_V4_NR      (2)
+#define EXYNOS5_GPIO_Z_NR       (7)
+
+/* EXYNOS5 GPIO bank numbers */
+
+enum exynos5_gpio_number {
+        EXYNOS5_GPIO_A0_START           = 0,
+        EXYNOS5_GPIO_A1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
+        EXYNOS5_GPIO_A2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
+        EXYNOS5_GPIO_B0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
+        EXYNOS5_GPIO_B1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
+        EXYNOS5_GPIO_B2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
+        EXYNOS5_GPIO_B3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
+        EXYNOS5_GPIO_C0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
+        EXYNOS5_GPIO_C1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
+        EXYNOS5_GPIO_C2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
+        EXYNOS5_GPIO_C3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
+        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+        EXYNOS5_GPIO_D1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
+        EXYNOS5_GPIO_Y0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
+        EXYNOS5_GPIO_Y1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
+        EXYNOS5_GPIO_Y2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
+        EXYNOS5_GPIO_Y3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
+        EXYNOS5_GPIO_Y4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
+        EXYNOS5_GPIO_Y5_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
+        EXYNOS5_GPIO_Y6_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
+        EXYNOS5_GPIO_X0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
+        EXYNOS5_GPIO_X1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
+        EXYNOS5_GPIO_X2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
+        EXYNOS5_GPIO_X3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
+        EXYNOS5_GPIO_E0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
+        EXYNOS5_GPIO_E1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
+        EXYNOS5_GPIO_F0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
+        EXYNOS5_GPIO_F1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
+        EXYNOS5_GPIO_G0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
+        EXYNOS5_GPIO_G1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
+        EXYNOS5_GPIO_G2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
+        EXYNOS5_GPIO_H0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
+        EXYNOS5_GPIO_H1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
+        EXYNOS5_GPIO_V0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
+        EXYNOS5_GPIO_V1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
+        EXYNOS5_GPIO_V2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
+        EXYNOS5_GPIO_V3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
+        EXYNOS5_GPIO_V4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
+        EXYNOS5_GPIO_Z_START            = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
+};
+
+/* EXYNOS5 GPIO number definitions */
+
+#define EXYNOS5_GPA0(_nr)       (EXYNOS5_GPIO_A0_START + (_nr))
+#define EXYNOS5_GPA1(_nr)       (EXYNOS5_GPIO_A1_START + (_nr))
+#define EXYNOS5_GPA2(_nr)       (EXYNOS5_GPIO_A2_START + (_nr))
+#define EXYNOS5_GPB0(_nr)       (EXYNOS5_GPIO_B0_START + (_nr))
+#define EXYNOS5_GPB1(_nr)       (EXYNOS5_GPIO_B1_START + (_nr))
+#define EXYNOS5_GPB2(_nr)       (EXYNOS5_GPIO_B2_START + (_nr))
+#define EXYNOS5_GPB3(_nr)       (EXYNOS5_GPIO_B3_START + (_nr))
+#define EXYNOS5_GPC0(_nr)       (EXYNOS5_GPIO_C0_START + (_nr))
+#define EXYNOS5_GPC1(_nr)       (EXYNOS5_GPIO_C1_START + (_nr))
+#define EXYNOS5_GPC2(_nr)       (EXYNOS5_GPIO_C2_START + (_nr))
+#define EXYNOS5_GPC3(_nr)       (EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPD0(_nr)       (EXYNOS5_GPIO_D0_START + (_nr))
+#define EXYNOS5_GPD1(_nr)       (EXYNOS5_GPIO_D1_START + (_nr))
+#define EXYNOS5_GPY0(_nr)       (EXYNOS5_GPIO_Y0_START + (_nr))
+#define EXYNOS5_GPY1(_nr)       (EXYNOS5_GPIO_Y1_START + (_nr))
+#define EXYNOS5_GPY2(_nr)       (EXYNOS5_GPIO_Y2_START + (_nr))
+#define EXYNOS5_GPY3(_nr)       (EXYNOS5_GPIO_Y3_START + (_nr))
+#define EXYNOS5_GPY4(_nr)       (EXYNOS5_GPIO_Y4_START + (_nr))
+#define EXYNOS5_GPY5(_nr)       (EXYNOS5_GPIO_Y5_START + (_nr))
+#define EXYNOS5_GPY6(_nr)       (EXYNOS5_GPIO_Y6_START + (_nr))
+#define EXYNOS5_GPX0(_nr)       (EXYNOS5_GPIO_X0_START + (_nr))
+#define EXYNOS5_GPX1(_nr)       (EXYNOS5_GPIO_X1_START + (_nr))
+#define EXYNOS5_GPX2(_nr)       (EXYNOS5_GPIO_X2_START + (_nr))
+#define EXYNOS5_GPX3(_nr)       (EXYNOS5_GPIO_X3_START + (_nr))
+#define EXYNOS5_GPE0(_nr)       (EXYNOS5_GPIO_E0_START + (_nr))
+#define EXYNOS5_GPE1(_nr)       (EXYNOS5_GPIO_E1_START + (_nr))
+#define EXYNOS5_GPF0(_nr)       (EXYNOS5_GPIO_F0_START + (_nr))
+#define EXYNOS5_GPF1(_nr)       (EXYNOS5_GPIO_F1_START + (_nr))
+#define EXYNOS5_GPG0(_nr)       (EXYNOS5_GPIO_G0_START + (_nr))
+#define EXYNOS5_GPG1(_nr)       (EXYNOS5_GPIO_G1_START + (_nr))
+#define EXYNOS5_GPG2(_nr)       (EXYNOS5_GPIO_G2_START + (_nr))
+#define EXYNOS5_GPH0(_nr)       (EXYNOS5_GPIO_H0_START + (_nr))
+#define EXYNOS5_GPH1(_nr)       (EXYNOS5_GPIO_H1_START + (_nr))
+#define EXYNOS5_GPV0(_nr)       (EXYNOS5_GPIO_V0_START + (_nr))
+#define EXYNOS5_GPV1(_nr)       (EXYNOS5_GPIO_V1_START + (_nr))
+#define EXYNOS5_GPV2(_nr)       (EXYNOS5_GPIO_V2_START + (_nr))
+#define EXYNOS5_GPV3(_nr)       (EXYNOS5_GPIO_V3_START + (_nr))
+#define EXYNOS5_GPV4(_nr)       (EXYNOS5_GPIO_V4_START + (_nr))
+#define EXYNOS5_GPZ(_nr)        (EXYNOS5_GPIO_Z_START + (_nr))
+
+/* the end of the EXYNOS5 specific gpios */
+
+#define EXYNOS5_GPIO_END        (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
+
+/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
+
+#define S3C_GPIO_END            (EXYNOS5_GPIO_END)
+
+/* define the number of gpios */
+
+#define ARCH_NR_GPIOS           (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f77bce04789..9bee8535d9e 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4 - IRQ definitions
+ * EXYNOS - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,158 +16,450 @@
 
 /* PPI: Private Peripheral Interrupt */
 
-#define IRQ_PPI(x)              (x+16)
-
-#define IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
+#define IRQ_PPI(x)                      (x + 16)
 
 /* SPI: Shared Peripheral Interrupt */
 
-#define IRQ_SPI(x)              (x+32)
-
-#define IRQ_EINT0               IRQ_SPI(16)
-#define IRQ_EINT1               IRQ_SPI(17)
-#define IRQ_EINT2               IRQ_SPI(18)
-#define IRQ_EINT3               IRQ_SPI(19)
-#define IRQ_EINT4               IRQ_SPI(20)
-#define IRQ_EINT5               IRQ_SPI(21)
-#define IRQ_EINT6               IRQ_SPI(22)
-#define IRQ_EINT7               IRQ_SPI(23)
-#define IRQ_EINT8               IRQ_SPI(24)
-#define IRQ_EINT9               IRQ_SPI(25)
-#define IRQ_EINT10              IRQ_SPI(26)
-#define IRQ_EINT11              IRQ_SPI(27)
-#define IRQ_EINT12              IRQ_SPI(28)
-#define IRQ_EINT13              IRQ_SPI(29)
-#define IRQ_EINT14              IRQ_SPI(30)
-#define IRQ_EINT15              IRQ_SPI(31)
-#define IRQ_EINT16_31           IRQ_SPI(32)
-
-#define IRQ_PDMA0               IRQ_SPI(35)
-#define IRQ_PDMA1               IRQ_SPI(36)
-#define IRQ_TIMER0_VIC          IRQ_SPI(37)
-#define IRQ_TIMER1_VIC          IRQ_SPI(38)
-#define IRQ_TIMER2_VIC          IRQ_SPI(39)
-#define IRQ_TIMER3_VIC          IRQ_SPI(40)
-#define IRQ_TIMER4_VIC          IRQ_SPI(41)
-#define IRQ_MCT_L0              IRQ_SPI(42)
-#define IRQ_WDT                 IRQ_SPI(43)
-#define IRQ_RTC_ALARM           IRQ_SPI(44)
-#define IRQ_RTC_TIC             IRQ_SPI(45)
-#define IRQ_GPIO_XB             IRQ_SPI(46)
-#define IRQ_GPIO_XA             IRQ_SPI(47)
-#define IRQ_MCT_L1              IRQ_SPI(48)
-
-#define IRQ_UART0               IRQ_SPI(52)
-#define IRQ_UART1               IRQ_SPI(53)
-#define IRQ_UART2               IRQ_SPI(54)
-#define IRQ_UART3               IRQ_SPI(55)
-#define IRQ_UART4               IRQ_SPI(56)
-#define IRQ_MCT_G0              IRQ_SPI(57)
-#define IRQ_IIC                 IRQ_SPI(58)
-#define IRQ_IIC1                IRQ_SPI(59)
-#define IRQ_IIC2                IRQ_SPI(60)
-#define IRQ_IIC3                IRQ_SPI(61)
-#define IRQ_IIC4                IRQ_SPI(62)
-#define IRQ_IIC5                IRQ_SPI(63)
-#define IRQ_IIC6                IRQ_SPI(64)
-#define IRQ_IIC7                IRQ_SPI(65)
-#define IRQ_SPI0                IRQ_SPI(66)
-#define IRQ_SPI1                IRQ_SPI(67)
-#define IRQ_SPI2                IRQ_SPI(68)
-
-#define IRQ_USB_HOST            IRQ_SPI(70)
-#define IRQ_USB_HSOTG           IRQ_SPI(71)
-#define IRQ_MODEM_IF            IRQ_SPI(72)
-#define IRQ_HSMMC0              IRQ_SPI(73)
-#define IRQ_HSMMC1              IRQ_SPI(74)
-#define IRQ_HSMMC2              IRQ_SPI(75)
-#define IRQ_HSMMC3              IRQ_SPI(76)
-#define IRQ_DWMCI               IRQ_SPI(77)
-
-#define IRQ_MIPI_CSIS0          IRQ_SPI(78)
-#define IRQ_MIPI_CSIS1          IRQ_SPI(80)
-
-#define IRQ_ONENAND_AUDI        IRQ_SPI(82)
-#define IRQ_ROTATOR             IRQ_SPI(83)
-#define IRQ_FIMC0               IRQ_SPI(84)
-#define IRQ_FIMC1               IRQ_SPI(85)
-#define IRQ_FIMC2               IRQ_SPI(86)
-#define IRQ_FIMC3               IRQ_SPI(87)
-#define IRQ_JPEG                IRQ_SPI(88)
-#define IRQ_2D                  IRQ_SPI(89)
-#define IRQ_PCIE                IRQ_SPI(90)
-
-#define IRQ_MIXER               IRQ_SPI(91)
-#define IRQ_HDMI                IRQ_SPI(92)
-#define IRQ_IIC_HDMIPHY         IRQ_SPI(93)
-#define IRQ_MFC                 IRQ_SPI(94)
-#define IRQ_SDO                 IRQ_SPI(95)
-
-#define IRQ_AUDIO_SS            IRQ_SPI(96)
-#define IRQ_I2S0                IRQ_SPI(97)
-#define IRQ_I2S1                IRQ_SPI(98)
-#define IRQ_I2S2                IRQ_SPI(99)
-#define IRQ_AC97                IRQ_SPI(100)
-
-#define IRQ_SPDIF               IRQ_SPI(104)
-#define IRQ_ADC0                IRQ_SPI(105)
-#define IRQ_PEN0                IRQ_SPI(106)
-#define IRQ_ADC1                IRQ_SPI(107)
-#define IRQ_PEN1                IRQ_SPI(108)
-#define IRQ_KEYPAD              IRQ_SPI(109)
-#define IRQ_PMU                 IRQ_SPI(110)
-#define IRQ_GPS                 IRQ_SPI(111)
-#define IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define IRQ_SLIMBUS             IRQ_SPI(113)
-
-#define IRQ_TSI                 IRQ_SPI(115)
-#define IRQ_SATA                IRQ_SPI(116)
-
-#define MAX_IRQ_IN_COMBINER     8
-#define COMBINER_GROUP(x)       ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)      (COMBINER_GROUP(x) + y)
-
-#define IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
-
-#define IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
-#define IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
-#define IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
-
-#define MAX_COMBINER_NR         16
-
-#define IRQ_ADC                 IRQ_ADC0
-#define IRQ_TC                  IRQ_PEN0
-
-#define S5P_IRQ_EINT_BASE       COMBINER_IRQ(MAX_COMBINER_NR, 0)
-
-#define S5P_EINT_BASE1          (S5P_IRQ_EINT_BASE + 0)
-#define S5P_EINT_BASE2          (S5P_IRQ_EINT_BASE + 16)
-
-/* optional GPIO interrupts */
-#define S5P_GPIOINT_BASE        (S5P_IRQ_EINT_BASE + 32)
-#define IRQ_GPIO1_NR_GROUPS     16
-#define IRQ_GPIO2_NR_GROUPS     9
-#define IRQ_GPIO_END            (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-
-#define IRQ_TIMER_BASE          (IRQ_GPIO_END + 64)
+#define IRQ_SPI(x)                      (x + 32)
+
+/* COMBINER */
+
+#define MAX_IRQ_IN_COMBINER             8
+#define COMBINER_GROUP(x)               ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)              (COMBINER_GROUP(x) + y)
+
+/* For EXYNOS4 and EXYNOS5 */
+
+#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
+
+#define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
+
+/* For EXYNOS4 SoCs */
+
+#define EXYNOS4_IRQ_EINT0               IRQ_SPI(16)
+#define EXYNOS4_IRQ_EINT1               IRQ_SPI(17)
+#define EXYNOS4_IRQ_EINT2               IRQ_SPI(18)
+#define EXYNOS4_IRQ_EINT3               IRQ_SPI(19)
+#define EXYNOS4_IRQ_EINT4               IRQ_SPI(20)
+#define EXYNOS4_IRQ_EINT5               IRQ_SPI(21)
+#define EXYNOS4_IRQ_EINT6               IRQ_SPI(22)
+#define EXYNOS4_IRQ_EINT7               IRQ_SPI(23)
+#define EXYNOS4_IRQ_EINT8               IRQ_SPI(24)
+#define EXYNOS4_IRQ_EINT9               IRQ_SPI(25)
+#define EXYNOS4_IRQ_EINT10              IRQ_SPI(26)
+#define EXYNOS4_IRQ_EINT11              IRQ_SPI(27)
+#define EXYNOS4_IRQ_EINT12              IRQ_SPI(28)
+#define EXYNOS4_IRQ_EINT13              IRQ_SPI(29)
+#define EXYNOS4_IRQ_EINT14              IRQ_SPI(30)
+#define EXYNOS4_IRQ_EINT15              IRQ_SPI(31)
+
+#define EXYNOS4_IRQ_MDMA0               IRQ_SPI(33)
+#define EXYNOS4_IRQ_MDMA1               IRQ_SPI(34)
+#define EXYNOS4_IRQ_PDMA0               IRQ_SPI(35)
+#define EXYNOS4_IRQ_PDMA1               IRQ_SPI(36)
+#define EXYNOS4_IRQ_TIMER0_VIC          IRQ_SPI(37)
+#define EXYNOS4_IRQ_TIMER1_VIC          IRQ_SPI(38)
+#define EXYNOS4_IRQ_TIMER2_VIC          IRQ_SPI(39)
+#define EXYNOS4_IRQ_TIMER3_VIC          IRQ_SPI(40)
+#define EXYNOS4_IRQ_TIMER4_VIC          IRQ_SPI(41)
+#define EXYNOS4_IRQ_MCT_L0              IRQ_SPI(42)
+#define EXYNOS4_IRQ_WDT                 IRQ_SPI(43)
+#define EXYNOS4_IRQ_RTC_ALARM           IRQ_SPI(44)
+#define EXYNOS4_IRQ_RTC_TIC             IRQ_SPI(45)
+#define EXYNOS4_IRQ_GPIO_XB             IRQ_SPI(46)
+#define EXYNOS4_IRQ_GPIO_XA             IRQ_SPI(47)
+#define EXYNOS4_IRQ_MCT_L1              IRQ_SPI(48)
+
+#define EXYNOS4_IRQ_UART0               IRQ_SPI(52)
+#define EXYNOS4_IRQ_UART1               IRQ_SPI(53)
+#define EXYNOS4_IRQ_UART2               IRQ_SPI(54)
+#define EXYNOS4_IRQ_UART3               IRQ_SPI(55)
+#define EXYNOS4_IRQ_UART4               IRQ_SPI(56)
+#define EXYNOS4_IRQ_MCT_G0              IRQ_SPI(57)
+#define EXYNOS4_IRQ_IIC                 IRQ_SPI(58)
+#define EXYNOS4_IRQ_IIC1                IRQ_SPI(59)
+#define EXYNOS4_IRQ_IIC2                IRQ_SPI(60)
+#define EXYNOS4_IRQ_IIC3                IRQ_SPI(61)
+#define EXYNOS4_IRQ_IIC4                IRQ_SPI(62)
+#define EXYNOS4_IRQ_IIC5                IRQ_SPI(63)
+#define EXYNOS4_IRQ_IIC6                IRQ_SPI(64)
+#define EXYNOS4_IRQ_IIC7                IRQ_SPI(65)
+#define EXYNOS4_IRQ_SPI0                IRQ_SPI(66)
+#define EXYNOS4_IRQ_SPI1                IRQ_SPI(67)
+#define EXYNOS4_IRQ_SPI2                IRQ_SPI(68)
+
+#define EXYNOS4_IRQ_USB_HOST            IRQ_SPI(70)
+#define EXYNOS4_IRQ_USB_HSOTG           IRQ_SPI(71)
+#define EXYNOS4_IRQ_MODEM_IF            IRQ_SPI(72)
+#define EXYNOS4_IRQ_HSMMC0              IRQ_SPI(73)
+#define EXYNOS4_IRQ_HSMMC1              IRQ_SPI(74)
+#define EXYNOS4_IRQ_HSMMC2              IRQ_SPI(75)
+#define EXYNOS4_IRQ_HSMMC3              IRQ_SPI(76)
+#define EXYNOS4_IRQ_DWMCI               IRQ_SPI(77)
+
+#define EXYNOS4_IRQ_MIPI_CSIS0          IRQ_SPI(78)
+#define EXYNOS4_IRQ_MIPI_CSIS1          IRQ_SPI(80)
+
+#define EXYNOS4_IRQ_ONENAND_AUDI        IRQ_SPI(82)
+#define EXYNOS4_IRQ_ROTATOR             IRQ_SPI(83)
+#define EXYNOS4_IRQ_FIMC0               IRQ_SPI(84)
+#define EXYNOS4_IRQ_FIMC1               IRQ_SPI(85)
+#define EXYNOS4_IRQ_FIMC2               IRQ_SPI(86)
+#define EXYNOS4_IRQ_FIMC3               IRQ_SPI(87)
+#define EXYNOS4_IRQ_JPEG                IRQ_SPI(88)
+#define EXYNOS4_IRQ_2D                  IRQ_SPI(89)
+#define EXYNOS4_IRQ_PCIE                IRQ_SPI(90)
+
+#define EXYNOS4_IRQ_MIXER               IRQ_SPI(91)
+#define EXYNOS4_IRQ_HDMI                IRQ_SPI(92)
+#define EXYNOS4_IRQ_IIC_HDMIPHY         IRQ_SPI(93)
+#define EXYNOS4_IRQ_MFC                 IRQ_SPI(94)
+#define EXYNOS4_IRQ_SDO                 IRQ_SPI(95)
+
+#define EXYNOS4_IRQ_AUDIO_SS            IRQ_SPI(96)
+#define EXYNOS4_IRQ_I2S0                IRQ_SPI(97)
+#define EXYNOS4_IRQ_I2S1                IRQ_SPI(98)
+#define EXYNOS4_IRQ_I2S2                IRQ_SPI(99)
+#define EXYNOS4_IRQ_AC97                IRQ_SPI(100)
+
+#define EXYNOS4_IRQ_SPDIF               IRQ_SPI(104)
+#define EXYNOS4_IRQ_ADC0                IRQ_SPI(105)
+#define EXYNOS4_IRQ_PEN0                IRQ_SPI(106)
+#define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
+#define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
+#define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
+#define EXYNOS4_IRQ_PMU                 IRQ_SPI(110)
+#define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
+#define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
+#define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
+
+#define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
+#define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
+
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
+#define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
+#define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
+
+#define EXYNOS4_MAX_COMBINER_NR         16
+
+#define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
+#define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
+
+/*
+ * For Compatibility:
+ * the default is for EXYNOS4, and
+ * for exynos5, should be re-mapped at function
+ */
+
+#define IRQ_TIMER0_VIC                  EXYNOS4_IRQ_TIMER0_VIC
+#define IRQ_TIMER1_VIC                  EXYNOS4_IRQ_TIMER1_VIC
+#define IRQ_TIMER2_VIC                  EXYNOS4_IRQ_TIMER2_VIC
+#define IRQ_TIMER3_VIC                  EXYNOS4_IRQ_TIMER3_VIC
+#define IRQ_TIMER4_VIC                  EXYNOS4_IRQ_TIMER4_VIC
+
+#define IRQ_WDT                         EXYNOS4_IRQ_WDT
+#define IRQ_RTC_ALARM                   EXYNOS4_IRQ_RTC_ALARM
+#define IRQ_RTC_TIC                     EXYNOS4_IRQ_RTC_TIC
+#define IRQ_GPIO_XB                     EXYNOS4_IRQ_GPIO_XB
+#define IRQ_GPIO_XA                     EXYNOS4_IRQ_GPIO_XA
+
+#define IRQ_IIC                         EXYNOS4_IRQ_IIC
+#define IRQ_IIC1                        EXYNOS4_IRQ_IIC1
+#define IRQ_IIC3                        EXYNOS4_IRQ_IIC3
+#define IRQ_IIC5                        EXYNOS4_IRQ_IIC5
+#define IRQ_IIC6                        EXYNOS4_IRQ_IIC6
+#define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
+
+#define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
+
+#define IRQ_HSMMC0                      EXYNOS4_IRQ_HSMMC0
+#define IRQ_HSMMC1                      EXYNOS4_IRQ_HSMMC1
+#define IRQ_HSMMC2                      EXYNOS4_IRQ_HSMMC2
+#define IRQ_HSMMC3                      EXYNOS4_IRQ_HSMMC3
+
+#define IRQ_MIPI_CSIS0                  EXYNOS4_IRQ_MIPI_CSIS0
+
+#define IRQ_ONENAND_AUDI                EXYNOS4_IRQ_ONENAND_AUDI
+
+#define IRQ_FIMC0                       EXYNOS4_IRQ_FIMC0
+#define IRQ_FIMC1                       EXYNOS4_IRQ_FIMC1
+#define IRQ_FIMC2                       EXYNOS4_IRQ_FIMC2
+#define IRQ_FIMC3                       EXYNOS4_IRQ_FIMC3
+#define IRQ_JPEG                        EXYNOS4_IRQ_JPEG
+#define IRQ_2D                          EXYNOS4_IRQ_2D
+
+#define IRQ_MIXER                       EXYNOS4_IRQ_MIXER
+#define IRQ_HDMI                        EXYNOS4_IRQ_HDMI
+#define IRQ_IIC_HDMIPHY                 EXYNOS4_IRQ_IIC_HDMIPHY
+#define IRQ_MFC                         EXYNOS4_IRQ_MFC
+#define IRQ_SDO                         EXYNOS4_IRQ_SDO
+
+#define IRQ_ADC                         EXYNOS4_IRQ_ADC0
+#define IRQ_TC                          EXYNOS4_IRQ_PEN0
+
+#define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
+#define IRQ_PMU                         EXYNOS4_IRQ_PMU
+
+#define IRQ_SYSMMU_MDMA0_0              EXYNOS4_IRQ_SYSMMU_MDMA0_0
+#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
+#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
+#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
+#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
+#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
+#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
+#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
+
+#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
+#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
+#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
+#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
+#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
+#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
+#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
+#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
+
+#define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
+#define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
+#define IRQ_FIMD0_SYSTEM                EXYNOS4_IRQ_FIMD0_SYSTEM
+
+#define IRQ_GPIO1_NR_GROUPS             EXYNOS4_IRQ_GPIO1_NR_GROUPS
+#define IRQ_GPIO2_NR_GROUPS             EXYNOS4_IRQ_GPIO2_NR_GROUPS
+
+/* For EXYNOS5 SoCs */
+
+#define EXYNOS5_IRQ_MDMA0               IRQ_SPI(33)
+#define EXYNOS5_IRQ_PDMA0               IRQ_SPI(34)
+#define EXYNOS5_IRQ_PDMA1               IRQ_SPI(35)
+#define EXYNOS5_IRQ_TIMER0_VIC          IRQ_SPI(36)
+#define EXYNOS5_IRQ_TIMER1_VIC          IRQ_SPI(37)
+#define EXYNOS5_IRQ_TIMER2_VIC          IRQ_SPI(38)
+#define EXYNOS5_IRQ_TIMER3_VIC          IRQ_SPI(39)
+#define EXYNOS5_IRQ_TIMER4_VIC          IRQ_SPI(40)
+#define EXYNOS5_IRQ_RTIC                IRQ_SPI(41)
+#define EXYNOS5_IRQ_WDT                 IRQ_SPI(42)
+#define EXYNOS5_IRQ_RTC_ALARM           IRQ_SPI(43)
+#define EXYNOS5_IRQ_RTC_TIC             IRQ_SPI(44)
+#define EXYNOS5_IRQ_GPIO_XB             IRQ_SPI(45)
+#define EXYNOS5_IRQ_GPIO_XA             IRQ_SPI(46)
+#define EXYNOS5_IRQ_GPIO                IRQ_SPI(47)
+#define EXYNOS5_IRQ_IEM_IEC             IRQ_SPI(48)
+#define EXYNOS5_IRQ_IEM_APC             IRQ_SPI(49)
+#define EXYNOS5_IRQ_GPIO_C2C            IRQ_SPI(50)
+#define EXYNOS5_IRQ_UART0               IRQ_SPI(51)
+#define EXYNOS5_IRQ_UART1               IRQ_SPI(52)
+#define EXYNOS5_IRQ_UART2               IRQ_SPI(53)
+#define EXYNOS5_IRQ_UART3               IRQ_SPI(54)
+#define EXYNOS5_IRQ_UART4               IRQ_SPI(55)
+#define EXYNOS5_IRQ_IIC                 IRQ_SPI(56)
+#define EXYNOS5_IRQ_IIC1                IRQ_SPI(57)
+#define EXYNOS5_IRQ_IIC2                IRQ_SPI(58)
+#define EXYNOS5_IRQ_IIC3                IRQ_SPI(59)
+#define EXYNOS5_IRQ_IIC4                IRQ_SPI(60)
+#define EXYNOS5_IRQ_IIC5                IRQ_SPI(61)
+#define EXYNOS5_IRQ_IIC6                IRQ_SPI(62)
+#define EXYNOS5_IRQ_IIC7                IRQ_SPI(63)
+#define EXYNOS5_IRQ_IIC_HDMIPHY         IRQ_SPI(64)
+#define EXYNOS5_IRQ_TMU                 IRQ_SPI(65)
+#define EXYNOS5_IRQ_FIQ_0               IRQ_SPI(66)
+#define EXYNOS5_IRQ_FIQ_1               IRQ_SPI(67)
+#define EXYNOS5_IRQ_SPI0                IRQ_SPI(68)
+#define EXYNOS5_IRQ_SPI1                IRQ_SPI(69)
+#define EXYNOS5_IRQ_SPI2                IRQ_SPI(70)
+#define EXYNOS5_IRQ_USB_HOST            IRQ_SPI(71)
+#define EXYNOS5_IRQ_USB3_DRD            IRQ_SPI(72)
+#define EXYNOS5_IRQ_MIPI_HSI            IRQ_SPI(73)
+#define EXYNOS5_IRQ_USB_HSOTG           IRQ_SPI(74)
+#define EXYNOS5_IRQ_HSMMC0              IRQ_SPI(75)
+#define EXYNOS5_IRQ_HSMMC1              IRQ_SPI(76)
+#define EXYNOS5_IRQ_HSMMC2              IRQ_SPI(77)
+#define EXYNOS5_IRQ_HSMMC3              IRQ_SPI(78)
+#define EXYNOS5_IRQ_MIPICSI0            IRQ_SPI(79)
+#define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
+#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
+#define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
+#define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
+#define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
+#define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
+#define EXYNOS5_IRQ_GSC2                IRQ_SPI(87)
+#define EXYNOS5_IRQ_GSC3                IRQ_SPI(88)
+#define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
+#define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
+#define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
+#define EXYNOS5_IRQ_SFMC0               IRQ_SPI(92)
+#define EXYNOS5_IRQ_SFMC1               IRQ_SPI(93)
+#define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
+#define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
+#define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
+#define EXYNOS5_IRQ_AUDIO_SS            IRQ_SPI(97)
+#define EXYNOS5_IRQ_I2S0                IRQ_SPI(98)
+#define EXYNOS5_IRQ_I2S1                IRQ_SPI(99)
+#define EXYNOS5_IRQ_I2S2                IRQ_SPI(100)
+#define EXYNOS5_IRQ_AC97                IRQ_SPI(101)
+#define EXYNOS5_IRQ_PCM0                IRQ_SPI(102)
+#define EXYNOS5_IRQ_PCM1                IRQ_SPI(103)
+#define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
+#define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
+#define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
+
+#define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
+#define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
+#define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
+#define EXYNOS5_IRQ_EAGLE_PMU           IRQ_SPI(111)
+#define EXYNOS5_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
+#define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
+#define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
+#define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
+#define EXYNOS5_IRQ_NFCON               IRQ_SPI(116)
+
+#define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
+#define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
+#define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
+#define EXYNOS5_IRQ_FIMC_LITE1          IRQ_SPI(126)
+#define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
+
+#define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
+#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(1, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0       COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1       COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0       COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1       COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1      COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1    COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1       COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0         COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1         COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0     COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1     COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0       COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1       COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1        COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1      COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0       COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1       COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
+
+#define EXYNOS5_IRQ_DP                  COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0       COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1       COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0        COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1        COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0        COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1        COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
+
+#define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
+#define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
+#define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
+
+#define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
+#define EXYNOS5_IRQ_MCT_L0              COMBINER_IRQ(23, 1)
+#define EXYNOS5_IRQ_MCT_L1              COMBINER_IRQ(23, 2)
+#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
+#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
+#define EXYNOS5_IRQ_MCT_G2              COMBINER_IRQ(23, 5)
+#define EXYNOS5_IRQ_MCT_G3              COMBINER_IRQ(23, 6)
+
+#define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1      COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0         COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1         COMBINER_IRQ(24, 6)
+
+#define EXYNOS5_IRQ_EINT2               COMBINER_IRQ(25, 0)
+#define EXYNOS5_IRQ_EINT3               COMBINER_IRQ(25, 1)
+
+#define EXYNOS5_IRQ_EINT4               COMBINER_IRQ(26, 0)
+#define EXYNOS5_IRQ_EINT5               COMBINER_IRQ(26, 1)
+
+#define EXYNOS5_IRQ_EINT6               COMBINER_IRQ(27, 0)
+#define EXYNOS5_IRQ_EINT7               COMBINER_IRQ(27, 1)
+
+#define EXYNOS5_IRQ_EINT8               COMBINER_IRQ(28, 0)
+#define EXYNOS5_IRQ_EINT9               COMBINER_IRQ(28, 1)
+
+#define EXYNOS5_IRQ_EINT10              COMBINER_IRQ(29, 0)
+#define EXYNOS5_IRQ_EINT11              COMBINER_IRQ(29, 1)
+
+#define EXYNOS5_IRQ_EINT12              COMBINER_IRQ(30, 0)
+#define EXYNOS5_IRQ_EINT13              COMBINER_IRQ(30, 1)
+
+#define EXYNOS5_IRQ_EINT14              COMBINER_IRQ(31, 0)
+#define EXYNOS5_IRQ_EINT15              COMBINER_IRQ(31, 1)
+
+#define EXYNOS5_MAX_COMBINER_NR         32
+
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     13
+#define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
+#define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
+#define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
+
+#define MAX_COMBINER_NR                 (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
+                                        EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
+
+#define S5P_EINT_BASE1                  COMBINER_IRQ(MAX_COMBINER_NR, 0)
+#define S5P_EINT_BASE2                  (S5P_EINT_BASE1 + 16)
+#define S5P_GPIOINT_BASE                (S5P_EINT_BASE1 + 32)
+#define IRQ_GPIO_END                    (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+#define IRQ_TIMER_BASE                  (IRQ_GPIO_END + 64)
 
 /* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
+#define NR_IRQS                         (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c754a22a2bb..024d38ff171 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,12 +25,17 @@
 
 #define EXYNOS4_PA_SYSRAM0              0x02025000
 #define EXYNOS4_PA_SYSRAM1              0x02020000
+#define EXYNOS5_PA_SYSRAM               0x02020000
 
 #define EXYNOS4_PA_FIMC0                0x11800000
 #define EXYNOS4_PA_FIMC1                0x11810000
 #define EXYNOS4_PA_FIMC2                0x11820000
 #define EXYNOS4_PA_FIMC3                0x11830000
 
+#define EXYNOS4_PA_JPEG                 0x11840000
+
+#define EXYNOS4_PA_G2D                  0x12800000
+
 #define EXYNOS4_PA_I2S0                 0x03830000
 #define EXYNOS4_PA_I2S1                 0xE3100000
 #define EXYNOS4_PA_I2S2                 0xE2A00000
@@ -44,30 +49,44 @@
 #define EXYNOS4_PA_ONENAND              0x0C000000
 #define EXYNOS4_PA_ONENAND_DMA          0x0C600000
 
-#define EXYNOS4_PA_CHIPID               0x10000000
+#define EXYNOS_PA_CHIPID                0x10000000
 
 #define EXYNOS4_PA_SYSCON               0x10010000
+#define EXYNOS5_PA_SYSCON               0x10050100
+
 #define EXYNOS4_PA_PMU                  0x10020000
+#define EXYNOS5_PA_PMU                  0x10040000
+
 #define EXYNOS4_PA_CMU                  0x10030000
+#define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
+#define EXYNOS5_PA_SYSTIMER             0x101C0000
+
 #define EXYNOS4_PA_WATCHDOG             0x10060000
+#define EXYNOS5_PA_WATCHDOG             0x101D0000
+
 #define EXYNOS4_PA_RTC                  0x10070000
 
 #define EXYNOS4_PA_KEYPAD               0x100A0000
 
 #define EXYNOS4_PA_DMC0                 0x10400000
+#define EXYNOS4_PA_DMC1                 0x10410000
 
 #define EXYNOS4_PA_COMBINER             0x10440000
+#define EXYNOS5_PA_COMBINER             0x10440000
 
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
+#define EXYNOS5_PA_GIC_CPU              0x10480000
+#define EXYNOS5_PA_GIC_DIST             0x10490000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
 #define EXYNOS4_PA_L2CC                 0x10502000
 
-#define EXYNOS4_PA_MDMA                 0x10810000
+#define EXYNOS4_PA_MDMA0                0x10810000
+#define EXYNOS4_PA_MDMA1                0x12840000
 #define EXYNOS4_PA_PDMA0                0x12680000
 #define EXYNOS4_PA_PDMA1                0x12690000
 
@@ -91,10 +110,13 @@
 #define EXYNOS4_PA_SPI1                 0x13930000
 #define EXYNOS4_PA_SPI2                 0x13940000
 
-
 #define EXYNOS4_PA_GPIO1                0x11400000
 #define EXYNOS4_PA_GPIO2                0x11000000
 #define EXYNOS4_PA_GPIO3                0x03860000
+#define EXYNOS5_PA_GPIO1                0x11400000
+#define EXYNOS5_PA_GPIO2                0x13400000
+#define EXYNOS5_PA_GPIO3                0x10D10000
+#define EXYNOS5_PA_GPIO4                0x03860000
 
 #define EXYNOS4_PA_MIPI_CSIS0           0x11880000
 #define EXYNOS4_PA_MIPI_CSIS1           0x11890000
@@ -109,6 +131,7 @@
 #define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
 
 #define EXYNOS4_PA_SROMC                0x12570000
+#define EXYNOS5_PA_SROMC                0x12250000
 
 #define EXYNOS4_PA_EHCI                 0x12580000
 #define EXYNOS4_PA_OHCI                 0x12590000
@@ -116,6 +139,7 @@
 #define EXYNOS4_PA_MFC                  0x13400000
 
 #define EXYNOS4_PA_UART                 0x13800000
+#define EXYNOS5_PA_UART                 0x12C00000
 
 #define EXYNOS4_PA_VP                   0x12C00000
 #define EXYNOS4_PA_MIXER                0x12C10000
@@ -124,6 +148,7 @@
 #define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
 
 #define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
+#define EXYNOS5_PA_IIC(x)               (0x12C60000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC                  0x13910000
 #define EXYNOS4_PA_ADC1                 0x13911000
@@ -133,8 +158,10 @@
 #define EXYNOS4_PA_SPDIF                0x139B0000
 
 #define EXYNOS4_PA_TIMER                0x139D0000
+#define EXYNOS5_PA_TIMER                0x12DD0000
 
 #define EXYNOS4_PA_SDRAM                0x40000000
+#define EXYNOS5_PA_SDRAM                0x40000000
 
 /* Compatibiltiy Defines */
 
@@ -152,7 +179,6 @@
 #define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
 #define S3C_PA_RTC                      EXYNOS4_PA_RTC
 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
-#define S3C_PA_UART                     EXYNOS4_PA_UART
 #define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
 #define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
@@ -162,6 +188,8 @@
 #define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
 #define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
 #define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
+#define S5P_PA_JPEG                     EXYNOS4_PA_JPEG
+#define S5P_PA_G2D                      EXYNOS4_PA_G2D
 #define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
 #define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
 #define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
@@ -181,15 +209,18 @@
 
 /* Compatibility UART */
 
-#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define EXYNOS4_PA_UART0                0x13800000
+#define EXYNOS4_PA_UART1                0x13810000
+#define EXYNOS4_PA_UART2                0x13820000
+#define EXYNOS4_PA_UART3                0x13830000
+#define EXYNOS4_SZ_UART                 SZ_256
 
-#define S5P_PA_UART(x)                  (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                    S5P_PA_UART(0)
-#define S5P_PA_UART1                    S5P_PA_UART(1)
-#define S5P_PA_UART2                    S5P_PA_UART(2)
-#define S5P_PA_UART3                    S5P_PA_UART(3)
-#define S5P_PA_UART4                    S5P_PA_UART(4)
+#define EXYNOS5_PA_UART0                0x12C00000
+#define EXYNOS5_PA_UART1                0x12C10000
+#define EXYNOS5_PA_UART2                0x12C20000
+#define EXYNOS5_PA_UART3                0x12C30000
+#define EXYNOS5_SZ_UART                 SZ_256
 
-#define S5P_SZ_UART                     SZ_256
+#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
index 632dd563013..e76b7faba66 100644
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -22,11 +22,13 @@ enum sys_powerdown {
         NUM_SYS_POWERDOWN,
 };
 
+extern unsigned long l2x0_regs_phys;
 struct exynos4_pmu_conf {
         void __iomem *reg;
         unsigned int val[NUM_SYS_POWERDOWN];
 };
 
 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+extern void s3c_cpu_resume(void);
 
 #endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 6c37ebe9482..e141c1fd68d 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,195 +16,309 @@
 #include <plat/cpu.h>
 #include <mach/map.h>
 
-#define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
-
-#define S5P_CLKDIV_LEFTBUS              S5P_CLKREG(0x04500)
-#define S5P_CLKDIV_STAT_LEFTBUS         S5P_CLKREG(0x04600)
-#define S5P_CLKGATE_IP_LEFTBUS          S5P_CLKREG(0x04800)
-
-#define S5P_CLKDIV_RIGHTBUS             S5P_CLKREG(0x08500)
-#define S5P_CLKDIV_STAT_RIGHTBUS        S5P_CLKREG(0x08600)
-#define S5P_CLKGATE_IP_RIGHTBUS         S5P_CLKREG(0x08800)
-
-#define S5P_EPLL_LOCK                   S5P_CLKREG(0x0C010)
-#define S5P_VPLL_LOCK                   S5P_CLKREG(0x0C020)
-
-#define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
-#define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
-#define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
-#define S5P_VPLL_CON1                   S5P_CLKREG(0x0C124)
-
-#define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
-#define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
-#define S5P_CLKSRC_CAM                  S5P_CLKREG(0x0C220)
-#define S5P_CLKSRC_TV                   S5P_CLKREG(0x0C224)
-#define S5P_CLKSRC_MFC                  S5P_CLKREG(0x0C228)
-#define S5P_CLKSRC_G3D                  S5P_CLKREG(0x0C22C)
-#define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
-#define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_MAUDIO               S5P_CLKREG(0x0C23C)
-#define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
-#define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
-#define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
-
-#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
-
-#define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
-#define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
-#define S5P_CLKDIV_TV                   S5P_CLKREG(0x0C524)
-#define S5P_CLKDIV_MFC                  S5P_CLKREG(0x0C528)
-#define S5P_CLKDIV_G3D                  S5P_CLKREG(0x0C52C)
-#define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
-#define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_MAUDIO               S5P_CLKREG(0x0C53C)
-#define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
-#define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
-#define S5P_CLKDIV_FSYS2                S5P_CLKREG(0x0C548)
-#define S5P_CLKDIV_FSYS3                S5P_CLKREG(0x0C54C)
-#define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x0C550)
-#define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x0C554)
-#define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x0C558)
-#define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x0C55C)
-#define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
-#define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
-#define S5P_CLKDIV2_RATIO               S5P_CLKREG(0x0C580)
-
-#define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
-
-#define S5P_CLKGATE_SCLKCAM             S5P_CLKREG(0x0C820)
-#define S5P_CLKGATE_IP_CAM              S5P_CLKREG(0x0C920)
-#define S5P_CLKGATE_IP_TV               S5P_CLKREG(0x0C924)
-#define S5P_CLKGATE_IP_MFC              S5P_CLKREG(0x0C928)
-#define S5P_CLKGATE_IP_G3D              S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE            (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x0C930) : \
-                                        S5P_CLKREG(0x04930))
-#define S5P_CLKGATE_IP_IMAGE_4210       S5P_CLKREG(0x0C930)
-#define S5P_CLKGATE_IP_IMAGE_4212       S5P_CLKREG(0x04930)
-#define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
-#define S5P_CLKGATE_IP_GPS              S5P_CLKREG(0x0C94C)
-#define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR            (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x0C960) : \
-                                        S5P_CLKREG(0x08960))
-#define S5P_CLKGATE_IP_PERIR_4210       S5P_CLKREG(0x0C960)
-#define S5P_CLKGATE_IP_PERIR_4212       S5P_CLKREG(0x08960)
-#define S5P_CLKGATE_BLOCK               S5P_CLKREG(0x0C970)
-
-#define S5P_CLKSRC_MASK_DMC             S5P_CLKREG(0x10300)
-#define S5P_CLKSRC_DMC                  S5P_CLKREG(0x10200)
-#define S5P_CLKDIV_DMC0                 S5P_CLKREG(0x10500)
-#define S5P_CLKDIV_DMC1                 S5P_CLKREG(0x10504)
-#define S5P_CLKDIV_STAT_DMC0            S5P_CLKREG(0x10600)
-#define S5P_CLKGATE_IP_DMC              S5P_CLKREG(0x10900)
-
-#define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK                   (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x14004) :  \
-                                        S5P_CLKREG(0x10008))
-#define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
-#define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0                   (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x14108) : \
-                                        S5P_CLKREG(0x10108))
-#define S5P_MPLL_CON1                   (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x1410C) : \
-                                        S5P_CLKREG(0x1010C))
-
-#define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
-#define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
-
-#define S5P_CLKDIV_CPU                  S5P_CLKREG(0x14500)
-#define S5P_CLKDIV_CPU1                 S5P_CLKREG(0x14504)
-#define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x14600)
-#define S5P_CLKDIV_STATCPU1             S5P_CLKREG(0x14604)
-
-#define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
-#define S5P_CLKGATE_IP_CPU              S5P_CLKREG(0x14900)
-
-#define S5P_APLL_LOCKTIME               (0x1C20)        /* 300us */
-
-#define S5P_APLLCON0_ENABLE_SHIFT       (31)
-#define S5P_APLLCON0_LOCKED_SHIFT       (29)
-#define S5P_APLL_VAL_1000               ((250 << 16) | (6 << 8) | 1)
-#define S5P_APLL_VAL_800                ((200 << 16) | (6 << 8) | 1)
-
-#define S5P_EPLLCON0_ENABLE_SHIFT       (31)
-#define S5P_EPLLCON0_LOCKED_SHIFT       (29)
-
-#define S5P_VPLLCON0_ENABLE_SHIFT       (31)
-#define S5P_VPLLCON0_LOCKED_SHIFT       (29)
-
-#define S5P_CLKSRC_CPU_MUXCORE_SHIFT    (16)
-#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
-
-#define S5P_CLKDIV_CPU0_CORE_SHIFT      (0)
-#define S5P_CLKDIV_CPU0_CORE_MASK       (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM0_SHIFT    (4)
-#define S5P_CLKDIV_CPU0_COREM0_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM1_SHIFT    (8)
-#define S5P_CLKDIV_CPU0_COREM1_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
-#define S5P_CLKDIV_CPU0_PERIPH_SHIFT    (12)
-#define S5P_CLKDIV_CPU0_PERIPH_MASK     (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
-#define S5P_CLKDIV_CPU0_ATB_SHIFT       (16)
-#define S5P_CLKDIV_CPU0_ATB_MASK        (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
-#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT   (20)
-#define S5P_CLKDIV_CPU0_PCLKDBG_MASK    (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define S5P_CLKDIV_CPU0_APLL_SHIFT      (24)
-#define S5P_CLKDIV_CPU0_APLL_MASK       (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
-
-#define S5P_CLKDIV_DMC0_ACP_SHIFT       (0)
-#define S5P_CLKDIV_DMC0_ACP_MASK        (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
-#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT   (4)
-#define S5P_CLKDIV_DMC0_ACPPCLK_MASK    (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define S5P_CLKDIV_DMC0_DPHY_SHIFT      (8)
-#define S5P_CLKDIV_DMC0_DPHY_MASK       (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
-#define S5P_CLKDIV_DMC0_DMC_SHIFT       (12)
-#define S5P_CLKDIV_DMC0_DMC_MASK        (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCD_SHIFT      (16)
-#define S5P_CLKDIV_DMC0_DMCD_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCP_SHIFT      (20)
-#define S5P_CLKDIV_DMC0_DMCP_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
-#define S5P_CLKDIV_DMC0_COPY2_SHIFT     (24)
-#define S5P_CLKDIV_DMC0_COPY2_MASK      (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
-#define S5P_CLKDIV_DMC0_CORETI_SHIFT    (28)
-#define S5P_CLKDIV_DMC0_CORETI_MASK     (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define S5P_CLKDIV_TOP_ACLK200_SHIFT    (0)
-#define S5P_CLKDIV_TOP_ACLK200_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK100_SHIFT    (4)
-#define S5P_CLKDIV_TOP_ACLK100_MASK     (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK160_SHIFT    (8)
-#define S5P_CLKDIV_TOP_ACLK160_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK133_SHIFT    (12)
-#define S5P_CLKDIV_TOP_ACLK133_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
-#define S5P_CLKDIV_TOP_ONENAND_SHIFT    (16)
-#define S5P_CLKDIV_TOP_ONENAND_MASK     (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
-
-#define S5P_CLKDIV_BUS_GDLR_SHIFT       (0)
-#define S5P_CLKDIV_BUS_GDLR_MASK        (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
-#define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
-#define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+#define EXYNOS_CLKREG(x)                        (S5P_VA_CMU + (x))
+
+#define EXYNOS4_CLKDIV_LEFTBUS                  EXYNOS_CLKREG(0x04500)
+#define EXYNOS4_CLKDIV_STAT_LEFTBUS             EXYNOS_CLKREG(0x04600)
+#define EXYNOS4_CLKGATE_IP_LEFTBUS              EXYNOS_CLKREG(0x04800)
+
+#define EXYNOS4_CLKDIV_RIGHTBUS                 EXYNOS_CLKREG(0x08500)
+#define EXYNOS4_CLKDIV_STAT_RIGHTBUS            EXYNOS_CLKREG(0x08600)
+#define EXYNOS4_CLKGATE_IP_RIGHTBUS             EXYNOS_CLKREG(0x08800)
+
+#define EXYNOS4_EPLL_LOCK                       EXYNOS_CLKREG(0x0C010)
+#define EXYNOS4_VPLL_LOCK                       EXYNOS_CLKREG(0x0C020)
+
+#define EXYNOS4_EPLL_CON0                       EXYNOS_CLKREG(0x0C110)
+#define EXYNOS4_EPLL_CON1                       EXYNOS_CLKREG(0x0C114)
+#define EXYNOS4_VPLL_CON0                       EXYNOS_CLKREG(0x0C120)
+#define EXYNOS4_VPLL_CON1                       EXYNOS_CLKREG(0x0C124)
+
+#define EXYNOS4_CLKSRC_TOP0                     EXYNOS_CLKREG(0x0C210)
+#define EXYNOS4_CLKSRC_TOP1                     EXYNOS_CLKREG(0x0C214)
+#define EXYNOS4_CLKSRC_CAM                      EXYNOS_CLKREG(0x0C220)
+#define EXYNOS4_CLKSRC_TV                       EXYNOS_CLKREG(0x0C224)
+#define EXYNOS4_CLKSRC_MFC                      EXYNOS_CLKREG(0x0C228)
+#define EXYNOS4_CLKSRC_G3D                      EXYNOS_CLKREG(0x0C22C)
+#define EXYNOS4_CLKSRC_IMAGE                    EXYNOS_CLKREG(0x0C230)
+#define EXYNOS4_CLKSRC_LCD0                     EXYNOS_CLKREG(0x0C234)
+#define EXYNOS4_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x0C23C)
+#define EXYNOS4_CLKSRC_FSYS                     EXYNOS_CLKREG(0x0C240)
+#define EXYNOS4_CLKSRC_PERIL0                   EXYNOS_CLKREG(0x0C250)
+#define EXYNOS4_CLKSRC_PERIL1                   EXYNOS_CLKREG(0x0C254)
+
+#define EXYNOS4_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x0C310)
+#define EXYNOS4_CLKSRC_MASK_CAM                 EXYNOS_CLKREG(0x0C320)
+#define EXYNOS4_CLKSRC_MASK_TV                  EXYNOS_CLKREG(0x0C324)
+#define EXYNOS4_CLKSRC_MASK_LCD0                EXYNOS_CLKREG(0x0C334)
+#define EXYNOS4_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x0C33C)
+#define EXYNOS4_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x0C340)
+#define EXYNOS4_CLKSRC_MASK_PERIL0              EXYNOS_CLKREG(0x0C350)
+#define EXYNOS4_CLKSRC_MASK_PERIL1              EXYNOS_CLKREG(0x0C354)
+
+#define EXYNOS4_CLKDIV_TOP                      EXYNOS_CLKREG(0x0C510)
+#define EXYNOS4_CLKDIV_CAM                      EXYNOS_CLKREG(0x0C520)
+#define EXYNOS4_CLKDIV_TV                       EXYNOS_CLKREG(0x0C524)
+#define EXYNOS4_CLKDIV_MFC                      EXYNOS_CLKREG(0x0C528)
+#define EXYNOS4_CLKDIV_G3D                      EXYNOS_CLKREG(0x0C52C)
+#define EXYNOS4_CLKDIV_IMAGE                    EXYNOS_CLKREG(0x0C530)
+#define EXYNOS4_CLKDIV_LCD0                     EXYNOS_CLKREG(0x0C534)
+#define EXYNOS4_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x0C53C)
+#define EXYNOS4_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x0C540)
+#define EXYNOS4_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x0C544)
+#define EXYNOS4_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x0C548)
+#define EXYNOS4_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x0C54C)
+#define EXYNOS4_CLKDIV_PERIL0                   EXYNOS_CLKREG(0x0C550)
+#define EXYNOS4_CLKDIV_PERIL1                   EXYNOS_CLKREG(0x0C554)
+#define EXYNOS4_CLKDIV_PERIL2                   EXYNOS_CLKREG(0x0C558)
+#define EXYNOS4_CLKDIV_PERIL3                   EXYNOS_CLKREG(0x0C55C)
+#define EXYNOS4_CLKDIV_PERIL4                   EXYNOS_CLKREG(0x0C560)
+#define EXYNOS4_CLKDIV_PERIL5                   EXYNOS_CLKREG(0x0C564)
+#define EXYNOS4_CLKDIV2_RATIO                   EXYNOS_CLKREG(0x0C580)
+
+#define EXYNOS4_CLKDIV_STAT_TOP                 EXYNOS_CLKREG(0x0C610)
+#define EXYNOS4_CLKDIV_STAT_MFC                 EXYNOS_CLKREG(0x0C628)
+
+#define EXYNOS4_CLKGATE_SCLKCAM                 EXYNOS_CLKREG(0x0C820)
+#define EXYNOS4_CLKGATE_IP_CAM                  EXYNOS_CLKREG(0x0C920)
+#define EXYNOS4_CLKGATE_IP_TV                   EXYNOS_CLKREG(0x0C924)
+#define EXYNOS4_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x0C928)
+#define EXYNOS4_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x0C92C)
+#define EXYNOS4_CLKGATE_IP_IMAGE                (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x0C930) : \
+                                                EXYNOS_CLKREG(0x04930))
+#define EXYNOS4210_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x0C930)
+#define EXYNOS4212_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x04930)
+#define EXYNOS4_CLKGATE_IP_LCD0                 EXYNOS_CLKREG(0x0C934)
+#define EXYNOS4_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x0C940)
+#define EXYNOS4_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x0C94C)
+#define EXYNOS4_CLKGATE_IP_PERIL                EXYNOS_CLKREG(0x0C950)
+#define EXYNOS4_CLKGATE_IP_PERIR                (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x0C960) : \
+                                                EXYNOS_CLKREG(0x08960))
+#define EXYNOS4210_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x0C960)
+#define EXYNOS4212_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x08960)
+#define EXYNOS4_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x0C970)
+
+#define EXYNOS4_CLKSRC_MASK_DMC                 EXYNOS_CLKREG(0x10300)
+#define EXYNOS4_CLKSRC_DMC                      EXYNOS_CLKREG(0x10200)
+#define EXYNOS4_CLKDIV_DMC0                     EXYNOS_CLKREG(0x10500)
+#define EXYNOS4_CLKDIV_DMC1                     EXYNOS_CLKREG(0x10504)
+#define EXYNOS4_CLKDIV_STAT_DMC0                EXYNOS_CLKREG(0x10600)
+#define EXYNOS4_CLKDIV_STAT_DMC1                EXYNOS_CLKREG(0x10604)
+#define EXYNOS4_CLKGATE_IP_DMC                  EXYNOS_CLKREG(0x10900)
+
+#define EXYNOS4_DMC_PAUSE_CTRL                  EXYNOS_CLKREG(0x11094)
+#define EXYNOS4_DMC_PAUSE_ENABLE                (1 << 0)
+
+#define EXYNOS4_APLL_LOCK                       EXYNOS_CLKREG(0x14000)
+#define EXYNOS4_MPLL_LOCK                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x14004) :  \
+                                                EXYNOS_CLKREG(0x10008))
+#define EXYNOS4_APLL_CON0                       EXYNOS_CLKREG(0x14100)
+#define EXYNOS4_APLL_CON1                       EXYNOS_CLKREG(0x14104)
+#define EXYNOS4_MPLL_CON0                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x14108) : \
+                                                EXYNOS_CLKREG(0x10108))
+#define EXYNOS4_MPLL_CON1                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x1410C) : \
+                                                EXYNOS_CLKREG(0x1010C))
+
+#define EXYNOS4_CLKSRC_CPU                      EXYNOS_CLKREG(0x14200)
+#define EXYNOS4_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x14400)
+
+#define EXYNOS4_CLKDIV_CPU                      EXYNOS_CLKREG(0x14500)
+#define EXYNOS4_CLKDIV_CPU1                     EXYNOS_CLKREG(0x14504)
+#define EXYNOS4_CLKDIV_STATCPU                  EXYNOS_CLKREG(0x14600)
+#define EXYNOS4_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x14604)
+
+#define EXYNOS4_CLKGATE_SCLKCPU                 EXYNOS_CLKREG(0x14800)
+#define EXYNOS4_CLKGATE_IP_CPU                  EXYNOS_CLKREG(0x14900)
+
+#define EXYNOS4_APLL_LOCKTIME                   (0x1C20)        /* 300us */
+
+#define EXYNOS4_APLLCON0_ENABLE_SHIFT           (31)
+#define EXYNOS4_APLLCON0_LOCKED_SHIFT           (29)
+#define EXYNOS4_APLL_VAL_1000                   ((250 << 16) | (6 << 8) | 1)
+#define EXYNOS4_APLL_VAL_800                    ((200 << 16) | (6 << 8) | 1)
+
+#define EXYNOS4_EPLLCON0_ENABLE_SHIFT           (31)
+#define EXYNOS4_EPLLCON0_LOCKED_SHIFT           (29)
+
+#define EXYNOS4_VPLLCON0_ENABLE_SHIFT           (31)
+#define EXYNOS4_VPLLCON0_LOCKED_SHIFT           (29)
+
+#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT        (16)
+#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK     (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CPU0_CORE_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT        (4)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT        (8)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT        (12)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT           (16)
+#define EXYNOS4_CLKDIV_CPU0_ATB_MASK            (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT       (20)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK        (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT          (24)
+#define EXYNOS4_CLKDIV_CPU0_APLL_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT         28
+#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK          (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT          0
+#define EXYNOS4_CLKDIV_CPU1_COPY_MASK           (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT           4
+#define EXYNOS4_CLKDIV_CPU1_HPM_MASK            (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT         8
+#define EXYNOS4_CLKDIV_CPU1_CORES_MASK          (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT           (0)
+#define EXYNOS4_CLKDIV_DMC0_ACP_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT       (4)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT          (8)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT           (12)
+#define EXYNOS4_CLKDIV_DMC0_DMC_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT          (16)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT          (20)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT         (24)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK          (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT        (28)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK         (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT       (0)
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK        (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT           (4)
+#define EXYNOS4_CLKDIV_DMC1_C2C_MASK            (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT           (8)
+#define EXYNOS4_CLKDIV_DMC1_PWI_MASK            (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT       (12)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT         (16)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK          (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT           (24)
+#define EXYNOS4_CLKDIV_DMC1_DPM_MASK            (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
+
+#define EXYNOS4_CLKDIV_MFC_SHIFT                (0)
+#define EXYNOS4_CLKDIV_MFC_MASK                 (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
+
+#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT        (0)
+#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT        (4)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK         (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT        (8)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT        (12)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT        (16)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT    (20)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK     (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK  (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
+
+#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT           (0)
+#define EXYNOS4_CLKDIV_BUS_GDLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
+#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT           (4)
+#define EXYNOS4_CLKDIV_BUS_GPLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
+
+#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT          (4)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT          (8)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT          (12)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
 
 /* Only for EXYNOS4210 */
 
-#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
-#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
-#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
-#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
+#define EXYNOS4210_CLKSRC_LCD1                  EXYNOS_CLKREG(0x0C238)
+#define EXYNOS4210_CLKSRC_MASK_LCD1             EXYNOS_CLKREG(0x0C338)
+#define EXYNOS4210_CLKDIV_LCD1                  EXYNOS_CLKREG(0x0C538)
+#define EXYNOS4210_CLKGATE_IP_LCD1              EXYNOS_CLKREG(0x0C938)
+
+/* Only for EXYNOS4212 */
+
+#define EXYNOS4_CLKDIV_CAM1                     EXYNOS_CLKREG(0x0C568)
+
+#define EXYNOS4_CLKDIV_STAT_CAM1                EXYNOS_CLKREG(0x0C668)
+
+#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK           (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
+
+/* For EXYNOS5250 */
+
+#define EXYNOS5_APLL_CON0                       EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_CLKSRC_CPU                      EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKDIV_CPU0                     EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKGATE_IP_CORE                 EXYNOS_CLKREG(0x04900)
+
+#define EXYNOS5_CLKDIV_ACP                      EXYNOS_CLKREG(0x08500)
+
+#define EXYNOS5_CLKSRC_TOP2                     EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_EPLL_CON0                       EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1                       EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_VPLL_CON0                       EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1                       EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_CPLL_CON0                       EXYNOS_CLKREG(0x10120)
+
+#define EXYNOS5_CLKSRC_TOP0                     EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP3                     EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL                     EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0                  EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_FSYS                     EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_PERIC0                   EXYNOS_CLKREG(0x10250)
+
+#define EXYNOS5_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL                EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0             EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_PERIC0              EXYNOS_CLKREG(0x10350)
+
+#define EXYNOS5_CLKDIV_TOP0                     EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1                     EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL                     EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0                  EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN                      EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0                   EXYNOS_CLKREG(0x10558)
+
+#define EXYNOS5_CLKGATE_IP_ACP                  EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_GSCL                 EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1                EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_GEN                  EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC                EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS                EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x10980)
+
+#define EXYNOS5_BPLL_CON0                       EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
+#define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
+
+#define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
 
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
 
-#define S5P_EPLL_CON                    S5P_EPLL_CON0
+#define S5P_EPLL_CON                            EXYNOS4_EPLL_CON0
 
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21663a..e4b5b60dcb8 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
 
+#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
+#define EINT_CON(b, x)                  (b + 0xE00 + (EINT_REG_NR(x) * 4))
+#define EINT_FLTCON(b, x)               (b + 0xE80 + (EINT_REG_NR(x) * 4))
+#define EINT_MASK(b, x)                 (b + 0xF00 + (EINT_REG_NR(x) * 4))
+#define EINT_PEND(b, x)                 (b + 0xF40 + (EINT_REG_NR(x) * 4))
+
+#define EINT_OFFSET_BIT(x)              (1 << (EINT_OFFSET(x) & 0x7))
+
+/* compatibility for plat-s5p/irq-pm.c */
 #define EXYNOS4_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
 #define S5P_EINT_CON(x)                 (EXYNOS4_EINT40CON + ((x) * 0x4))
 
@@ -28,15 +37,4 @@
 #define EXYNOS4_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
 #define S5P_EINT_PEND(x)                (EXYNOS4_EINT40PEND + ((x) * 0x4))
 
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE                       S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x)                  EXYNOS4_GPX0(x)
-#define EINT_GPIO_1(x)                  EXYNOS4_GPX1(x)
-#define EINT_GPIO_2(x)                  EXYNOS4_GPX2(x)
-#define EINT_GPIO_3(x)                  EXYNOS4_GPX3(x)
-
 #endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e938fe..4c53f38b5a9 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
 #define S5P_USE_STANDBYWFE_ISP_ARM              (1 << 26)
 
 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
+#define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
 
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
deleted file mode 100644
index 0063a6de3dc..00000000000
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/system.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bcd9ac..493f4f365dd 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4 - uncompress code
+ * EXYNOS - uncompress code
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H __FILE__
 
+#include <asm/mach-types.h>
+
 #include <mach/map.h>
+
+volatile u8 *uart_base;
+
 #include <plat/uncompress.h>
 
 static void arch_detect_cpu(void)
 {
-        /* we do not need to do any cpu detection here at the moment. */
+        if (machine_is_smdk5250())
+                uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+        else
+                uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 
         /*
          * For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e6b02fdf1b0..8245f1c761d 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -37,13 +37,13 @@
  * data from the device tree.
  */
 static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0,
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
                                 "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1,
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
                                 "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2,
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
                                 "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3,
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
                                 "exynos4210-uart.3", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
                                 "exynos4-sdhci.0", NULL),
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 00000000000..0d26f50081a
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
+/*
+ * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+
+#include "common.h"
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the EXYNOS5 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
+                                "exynos4210-uart.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
+                                "exynos4210-uart.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
+                                "exynos4210-uart.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
+                                "exynos4210-uart.3", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
+        {},
+};
+
+static void __init exynos5250_dt_map_io(void)
+{
+        exynos_init_io(NULL, 0);
+        s3c24xx_init_clocks(24000000);
+}
+
+static void __init exynos5250_dt_machine_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                                exynos5250_auxdata_lookup, NULL);
+}
+
+static char const *exynos5250_dt_compat[] __initdata = {
+        "samsung,exynos5250",
+        NULL
+};
+
+DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .init_irq       = exynos5_init_irq,
+        .map_io         = exynos5250_dt_map_io,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = exynos5250_dt_machine_init,
+        .timer          = &exynos4_timer,
+        .dt_compat      = exynos5250_dt_compat,
+        .restart        = exynos5_restart,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index aa37179d776..82ea6fccfb3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -28,6 +28,7 @@
 
 #include <video/platform_lcd.h>
 #include <media/m5mols.h>
+#include <media/s5k6aa.h>
 #include <media/s5p_fimc.h>
 #include <media/v4l2-mediabus.h>
 
@@ -75,6 +76,7 @@ enum fixed_regulator_id {
         FIXED_REG_ID_MAX8903,
         FIXED_REG_ID_CAM_A28V,
         FIXED_REG_ID_CAM_12V,
+        FIXED_REG_ID_CAM_VT_15V,
 };
 
 static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -115,7 +117,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
 };
 
 static struct regulator_consumer_supply emmc_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
         REGULATOR_SUPPLY("vmmc", "dw_mmc"),
 };
 
@@ -399,6 +401,9 @@ static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
 static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
         REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
 };
+static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
+        REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
+};
 static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
         REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
 };
@@ -413,7 +418,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
         REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
+        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
         REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
@@ -431,7 +436,7 @@ static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
         REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
 };
 static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
-        REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+        REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
 };
 static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
         REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
@@ -546,6 +551,8 @@ static struct regulator_init_data __initdata max8997_ldo6_data = {
                         .enabled        = 1,
                 },
         },
+        .num_consumer_supplies  = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
+        .consumer_supplies      = nuri_max8997_ldo6_consumer,
 };
 
 static struct regulator_init_data __initdata max8997_ldo7_data = {
@@ -742,7 +749,7 @@ static struct regulator_init_data __initdata max8997_buck2_data = {
         .constraints    = {
                 .name           = "VINT_1.1V_C210",
                 .min_uV         = 900000,
-                .max_uV         = 1100000,
+                .max_uV         = 1200000,
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
                 .always_on      = 1,
                 .state_mem      = {
@@ -957,7 +964,6 @@ static struct max8997_platform_data __initdata nuri_max8997_pdata = {
         .regulators             = nuri_max8997_regulators,
 
         .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
-        .buck2_gpiodvs = true,
 
         .buck1_voltage[0] = 1350000, /* 1.35V */
         .buck1_voltage[1] = 1300000, /* 1.3V */
@@ -1116,7 +1122,30 @@ static void __init nuri_ehci_init(void)
 }
 
 /* CAMERA */
+static struct regulator_consumer_supply cam_vt_cam15_supply =
+        REGULATOR_SUPPLY("vdd_core", "6-003c");
+
+static struct regulator_init_data cam_vt_cam15_reg_init_data = {
+        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &cam_vt_cam15_supply,
+};
+
+static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
+        .supply_name    = "VT_CAM_1.5V",
+        .microvolts     = 1500000,
+        .gpio           = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
+        .enable_high    = 1,
+        .init_data      = &cam_vt_cam15_reg_init_data,
+};
+
+static struct platform_device cam_vt_cam15_fixed_rdev = {
+        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
+        .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
+};
+
 static struct regulator_consumer_supply cam_vdda_supply[] = {
+        REGULATOR_SUPPLY("vdda", "6-003c"),
         REGULATOR_SUPPLY("a_sensor", "0-001f"),
 };
 
@@ -1173,6 +1202,21 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
 
 #define GPIO_CAM_MEGA_RST       EXYNOS4_GPY3(7) /* ISP_RESET */
 #define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPL2(5)
+#define GPIO_CAM_VT_NSTBY       EXYNOS4_GPL2(0)
+#define GPIO_CAM_VT_NRST        EXYNOS4_GPL2(1)
+
+static struct s5k6aa_platform_data s5k6aa_pldata = {
+        .mclk_frequency = 24000000UL,
+        .gpio_reset     = { GPIO_CAM_VT_NRST, 0 },
+        .gpio_stby      = { GPIO_CAM_VT_NSTBY, 0 },
+        .bus_type       = V4L2_MBUS_PARALLEL,
+        .horiz_flip     = 1,
+};
+
+static struct i2c_board_info s5k6aa_board_info = {
+        I2C_BOARD_INFO("S5K6AA", 0x3c),
+        .platform_data = &s5k6aa_pldata,
+};
 
 static struct m5mols_platform_data m5mols_platdata = {
         .gpio_reset = GPIO_CAM_MEGA_RST,
@@ -1185,6 +1229,13 @@ static struct i2c_board_info m5mols_board_info = {
 
 static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
         {
+                .flags          = V4L2_MBUS_PCLK_SAMPLE_RISING |
+                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
+                .bus_type       = FIMC_ITU_601,
+                .board_info     = &s5k6aa_board_info,
+                .clk_frequency  = 24000000UL,
+                .i2c_bus_num    = 6,
+        }, {
                 .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                   V4L2_MBUS_VSYNC_ACTIVE_LOW,
                 .bus_type       = FIMC_MIPI_CSI2,
@@ -1200,11 +1251,13 @@ static struct s5p_platform_fimc fimc_md_platdata = {
 };
 
 static struct gpio nuri_camera_gpios[] = {
+        { GPIO_CAM_VT_NSTBY,    GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
+        { GPIO_CAM_VT_NRST,     GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST"  },
         { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
         { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
 };
 
-static void nuri_camera_init(void)
+static void __init nuri_camera_init(void)
 {
         s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
                          &s5p_device_mipi_csis0);
@@ -1224,6 +1277,8 @@ static void nuri_camera_init(void)
                 pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
 
         /* Free GPIOs controlled directly by the sensor drivers. */
+        gpio_free(GPIO_CAM_VT_NRST);
+        gpio_free(GPIO_CAM_VT_NSTBY);
         gpio_free(GPIO_CAM_MEGA_RST);
 
         if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
@@ -1234,15 +1289,27 @@ static void nuri_camera_init(void)
         s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
 }
 
+static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
+        .frequency      = 400000U,
+        .sda_delay      = 200,
+        .bus_num        = 6,
+};
+
 static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
         .frequency      = 400000U,
         .sda_delay      = 200,
 };
 
+/* DEVFREQ controlling memory/bus */
+static struct platform_device exynos4_bus_devfreq = {
+        .name                   = "exynos4210-busfreq",
+};
+
 static struct platform_device *nuri_devices[] __initdata = {
         /* Samsung Platform Devices */
         &s3c_device_i2c5, /* PMIC should initialize first */
         &s3c_device_i2c0,
+        &s3c_device_i2c6,
         &emmc_fixed_voltage,
         &s5p_device_mipi_csis0,
         &s5p_device_fimc0,
@@ -1259,6 +1326,8 @@ static struct platform_device *nuri_devices[] __initdata = {
         &s3c_device_i2c3,
         &i2c9_gpio,
         &s3c_device_adc,
+        &s5p_device_g2d,
+        &s5p_device_jpeg,
         &s3c_device_rtc,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
@@ -1271,8 +1340,10 @@ static struct platform_device *nuri_devices[] __initdata = {
         &nuri_backlight_device,
         &max8903_fixed_reg_dev,
         &nuri_max8903_device,
+        &cam_vt_cam15_fixed_rdev,
         &cam_vdda_fixed_rdev,
         &cam_8m_12v_fixed_rdev,
+        &exynos4_bus_devfreq,
 };
 
 static void __init nuri_map_io(void)
@@ -1302,6 +1373,7 @@ static void __init nuri_machine_init(void)
         i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
         i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
         i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
+        s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
 
         s5p_fimd0_set_platdata(&nuri_fb_pdata);
 
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index fa5c4a59b0a..878d4c99142 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -20,6 +20,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/max8997.h>
 #include <linux/lcd.h>
+#include <linux/rfkill-gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -235,6 +236,7 @@ static struct regulator_init_data __initdata max8997_ldo9_data = {
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
+                .always_on      = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 .state_mem      = {
                         .disabled       = 1,
@@ -278,6 +280,7 @@ static struct regulator_init_data __initdata max8997_ldo14_data = {
                 .min_uV         = 1800000,
                 .max_uV         = 1800000,
                 .apply_uV       = 1,
+                .always_on      = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 .state_mem      = {
                         .disabled       = 1,
@@ -293,6 +296,7 @@ static struct regulator_init_data __initdata max8997_ldo17_data = {
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
+                .always_on      = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 .state_mem      = {
                         .disabled       = 1,
@@ -412,7 +416,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
         { MAX8997_BUCK7,        &max8997_buck7_data },
 };
 
-struct max8997_platform_data __initdata origen_max8997_pdata = {
+static struct max8997_platform_data __initdata origen_max8997_pdata = {
         .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
         .regulators     = origen_max8997_regulators,
 
@@ -602,6 +606,23 @@ static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
         .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
 
+/* Bluetooth rfkill gpio platform data */
+struct rfkill_gpio_platform_data origen_bt_pdata = {
+        .reset_gpio     = EXYNOS4_GPX2(2),
+        .shutdown_gpio  = -1,
+        .type           = RFKILL_TYPE_BLUETOOTH,
+        .name           = "origen-bt",
+};
+
+/* Bluetooth Platform device */
+static struct platform_device origen_device_bluetooth = {
+        .name           = "rfkill_gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &origen_bt_pdata,
+        },
+};
+
 static struct platform_device *origen_devices[] __initdata = {
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc0,
@@ -613,9 +634,12 @@ static struct platform_device *origen_devices[] __initdata = {
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5p_device_fimc3,
+        &s5p_device_fimc_md,
         &s5p_device_fimd0,
+        &s5p_device_g2d,
         &s5p_device_hdmi,
         &s5p_device_i2c_hdmiphy,
+        &s5p_device_jpeg,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
@@ -623,6 +647,7 @@ static struct platform_device *origen_devices[] __initdata = {
         &exynos4_device_ohci,
         &origen_device_gpiokeys,
         &origen_lcd_hv070wsa,
+        &origen_device_bluetooth,
 };
 
 /* LCD Backlight data */
@@ -636,6 +661,16 @@ static struct platform_pwm_backlight_data origen_bl_data = {
         .pwm_period_ns  = 1000,
 };
 
+static void __init origen_bt_setup(void)
+{
+        gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
+        /* 4 UART Pins configuration */
+        s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
+        /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
+        s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
+        s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
+}
+
 static void s5p_tv_setup(void)
 {
         /* Direct HPD to HDMI chip */
@@ -689,6 +724,8 @@ static void __init origen_machine_init(void)
         platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
 
         samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
+
+        origen_bt_setup();
 }
 
 MACHINE_START(ORIGEN, "ORIGEN")
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 5258b856367..83b91fa777c 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -270,6 +270,9 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5p_device_fimc3,
+        &s5p_device_fimc_md,
+        &s5p_device_g2d,
+        &s5p_device_jpeg,
         &exynos4_device_ac97,
         &exynos4_device_i2s0,
         &exynos4_device_ohci,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index b2d495b3109..28658da9f42 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -47,6 +47,7 @@
 #include <media/v4l2-mediabus.h>
 #include <media/s5p_fimc.h>
 #include <media/m5mols.h>
+#include <media/s5k6aa.h>
 
 #include "common.h"
 
@@ -123,8 +124,10 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
 static struct regulator_consumer_supply lp3974_buck2_consumer =
         REGULATOR_SUPPLY("vddg3d", NULL);
 
-static struct regulator_consumer_supply lp3974_buck3_consumer =
-        REGULATOR_SUPPLY("vdet", "s5p-sdo");
+static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
+        REGULATOR_SUPPLY("vdet", "s5p-sdo"),
+        REGULATOR_SUPPLY("vdd_reg", "0-003c"),
+};
 
 static struct regulator_init_data lp3974_buck1_data = {
         .constraints    = {
@@ -169,8 +172,8 @@ static struct regulator_init_data lp3974_buck3_data = {
                         .enabled        = 1,
                 },
         },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck3_consumer,
+        .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
+        .consumer_supplies = lp3974_buck3_consumer,
 };
 
 static struct regulator_init_data lp3974_buck4_data = {
@@ -303,6 +306,9 @@ static struct regulator_init_data lp3974_ldo8_data = {
         .consumer_supplies = lp3974_ldo8_consumer,
 };
 
+static struct regulator_consumer_supply lp3974_ldo9_consumer =
+        REGULATOR_SUPPLY("vddio", "0-003c");
+
 static struct regulator_init_data lp3974_ldo9_data = {
         .constraints    = {
                 .name           = "VCC_2.8V",
@@ -314,6 +320,8 @@ static struct regulator_init_data lp3974_ldo9_data = {
                         .enabled        = 1,
                 },
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &lp3974_ldo9_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo10_data = {
@@ -412,6 +420,7 @@ static struct regulator_init_data lp3974_ldo15_data = {
 };
 
 static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
+        REGULATOR_SUPPLY("vdda", "0-003c"),
         REGULATOR_SUPPLY("a_sensor", "0-001f"),
 };
 
@@ -743,7 +752,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
 };
 
 static struct regulator_consumer_supply mmc0_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
 };
 
 static struct regulator_init_data mmc0_fixed_voltage_init_data = {
@@ -819,6 +828,8 @@ static struct s3c_fb_pd_win universal_fb_win0 = {
         },
         .max_bpp        = 32,
         .default_bpp    = 16,
+        .virtual_x      = 480,
+        .virtual_y      = 2 * 800,
 };
 
 static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
@@ -830,6 +841,28 @@ static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
         .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
 
+static struct regulator_consumer_supply cam_vt_dio_supply =
+        REGULATOR_SUPPLY("vdd_core", "0-003c");
+
+static struct regulator_init_data cam_vt_dio_reg_init_data = {
+        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &cam_vt_dio_supply,
+};
+
+static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
+        .supply_name    = "CAM_VT_D_IO",
+        .microvolts     = 2800000,
+        .gpio           = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
+        .enable_high    = 1,
+        .init_data      = &cam_vt_dio_reg_init_data,
+};
+
+static struct platform_device cam_vt_dio_fixed_reg_dev = {
+        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
+        .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
+};
+
 static struct regulator_consumer_supply cam_i_core_supply =
         REGULATOR_SUPPLY("core", "0-001f");
 
@@ -885,6 +918,28 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
 #define GPIO_CAM_LEVEL_EN(n)    EXYNOS4_GPE4(n + 3)
 #define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPX1(5) /* XEINT_13 */
 #define GPIO_CAM_MEGA_nRST      EXYNOS4_GPE2(5)
+#define GPIO_CAM_VGA_NRST       EXYNOS4_GPE4(7)
+#define GPIO_CAM_VGA_NSTBY      EXYNOS4_GPE4(6)
+
+static int s5k6aa_set_power(int on)
+{
+        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
+        return 0;
+}
+
+static struct s5k6aa_platform_data s5k6aa_platdata = {
+        .mclk_frequency = 21600000UL,
+        .gpio_reset     = { GPIO_CAM_VGA_NRST, 0 },
+        .gpio_stby      = { GPIO_CAM_VGA_NSTBY, 0 },
+        .bus_type       = V4L2_MBUS_PARALLEL,
+        .horiz_flip     = 1,
+        .set_power      = s5k6aa_set_power,
+};
+
+static struct i2c_board_info s5k6aa_board_info = {
+        I2C_BOARD_INFO("S5K6AA", 0x3C),
+        .platform_data = &s5k6aa_platdata,
+};
 
 static int m5mols_set_power(struct device *dev, int on)
 {
@@ -909,6 +964,14 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
                 .mux_id         = 0,
                 .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                   V4L2_MBUS_VSYNC_ACTIVE_LOW,
+                .bus_type       = FIMC_ITU_601,
+                .board_info     = &s5k6aa_board_info,
+                .i2c_bus_num    = 0,
+                .clk_frequency  = 24000000UL,
+        }, {
+                .mux_id         = 0,
+                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
                 .bus_type       = FIMC_MIPI_CSI2,
                 .board_info     = &m5mols_board_info,
                 .i2c_bus_num    = 0,
@@ -927,9 +990,11 @@ static struct gpio universal_camera_gpios[] = {
         { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
         { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
         { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
+        { GPIO_CAM_VGA_NRST,    GPIOF_OUT_INIT_LOW,  "CAM_VGA_NRST"  },
+        { GPIO_CAM_VGA_NSTBY,   GPIOF_OUT_INIT_LOW,  "CAM_VGA_NSTBY" },
 };
 
-static void universal_camera_init(void)
+static void __init universal_camera_init(void)
 {
         s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
                          &s5p_device_mipi_csis0);
@@ -950,6 +1015,8 @@ static void universal_camera_init(void)
         /* Free GPIOs controlled directly by the sensor drivers. */
         gpio_free(GPIO_CAM_MEGA_nRST);
         gpio_free(GPIO_CAM_8M_ISP_INT);
+        gpio_free(GPIO_CAM_VGA_NRST);
+        gpio_free(GPIO_CAM_VGA_NSTBY);
 
         if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
                 pr_err("Camera port A setup failed\n");
@@ -962,6 +1029,7 @@ static struct platform_device *universal_devices[] __initdata = {
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5p_device_fimc3,
+        &s5p_device_g2d,
         &mmc0_fixed_voltage,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc2,
@@ -980,9 +1048,11 @@ static struct platform_device *universal_devices[] __initdata = {
         &universal_gpio_keys,
         &s5p_device_onenand,
         &s5p_device_fimd0,
+        &s5p_device_jpeg,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
+        &cam_vt_dio_fixed_reg_dev,
         &cam_i_core_fixed_reg_dev,
         &cam_s_if_fixed_reg_dev,
         &s5p_device_fimc_md,
@@ -995,7 +1065,7 @@ static void __init universal_map_io(void)
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
 }
 
-void s5p_tv_setup(void)
+static void s5p_tv_setup(void)
 {
         /* direct HPD to HDMI chip */
         gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 85b5527d091..897d9a9cf22 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -21,6 +21,7 @@
 #include <linux/percpu.h>
 
 #include <asm/hardware/gic.h>
+#include <asm/localtimer.h>
 
 #include <plat/cpu.h>
 
@@ -29,12 +30,13 @@
 #include <mach/regs-mct.h>
 #include <asm/mach/time.h>
 
+#define TICK_BASE_CNT   1
+
 enum {
         MCT_INT_SPI,
         MCT_INT_PPI
 };
 
-static unsigned long clk_cnt_per_tick;
 static unsigned long clk_rate;
 static unsigned int mct_int_type;
 
@@ -205,11 +207,14 @@ static int exynos4_comp_set_next_event(unsigned long cycles,
 static void exynos4_comp_set_mode(enum clock_event_mode mode,
                                   struct clock_event_device *evt)
 {
+        unsigned long cycles_per_jiffy;
         exynos4_mct_comp0_stop();
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
+                cycles_per_jiffy =
+                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
+                exynos4_mct_comp0_start(mode, cycles_per_jiffy);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -248,9 +253,7 @@ static struct irqaction mct_comp_event_irq = {
 
 static void exynos4_clockevent_init(void)
 {
-        clk_cnt_per_tick = clk_rate / 2 / HZ;
-
-        clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
+        clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
         mct_comp_device.max_delta_ns =
                 clockevent_delta2ns(0xffffffff, &mct_comp_device);
         mct_comp_device.min_delta_ns =
@@ -258,7 +261,10 @@ static void exynos4_clockevent_init(void)
         mct_comp_device.cpumask = cpumask_of(0);
         clockevents_register_device(&mct_comp_device);
 
-        setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+        if (soc_is_exynos5250())
+                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
+        else
+                setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
@@ -314,12 +320,15 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
                                          struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
+        unsigned long cycles_per_jiffy;
 
         exynos4_mct_tick_stop(mevt);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
+                cycles_per_jiffy =
+                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
+                exynos4_mct_tick_start(cycles_per_jiffy, mevt);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -375,7 +384,7 @@ static struct irqaction mct_tick1_event_irq = {
         .handler        = exynos4_mct_tick_isr,
 };
 
-static void exynos4_mct_tick_init(struct clock_event_device *evt)
+static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
@@ -393,7 +402,7 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
         evt->rating = 450;
 
-        clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
+        clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
         evt->max_delta_ns =
                 clockevent_delta2ns(0x7fffffff, evt);
         evt->min_delta_ns =
@@ -401,33 +410,27 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
         clockevents_register_device(evt);
 
-        exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
+        exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
                         mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = IRQ_MCT_L0;
-                        setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+                        evt->irq = EXYNOS4_IRQ_MCT_L0;
+                        setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
                 } else {
                         mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = IRQ_MCT_L1;
-                        setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
-                        irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+                        evt->irq = EXYNOS4_IRQ_MCT_L1;
+                        setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
+                        irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
                 }
         } else {
-                enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
+                enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
         }
-}
-
-/* Setup the local clock events for a CPU */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        exynos4_mct_tick_init(evt);
 
         return 0;
 }
 
-void local_timer_stop(struct clock_event_device *evt)
+static void exynos4_local_timer_stop(struct clock_event_device *evt)
 {
         unsigned int cpu = smp_processor_id();
         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
@@ -437,8 +440,13 @@ void local_timer_stop(struct clock_event_device *evt)
                 else
                         remove_irq(evt->irq, &mct_tick1_event_irq);
         else
-                disable_percpu_irq(IRQ_MCT_LOCALTIMER);
+                disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
 }
+
+static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
+        .setup  = exynos4_local_timer_setup,
+        .stop   = exynos4_local_timer_stop,
+};
 #endif /* CONFIG_LOCAL_TIMERS */
 
 static void __init exynos4_timer_resources(void)
@@ -452,12 +460,14 @@ static void __init exynos4_timer_resources(void)
         if (mct_int_type == MCT_INT_PPI) {
                 int err;
 
-                err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
+                err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
                                          exynos4_mct_tick_isr, "MCT",
                                          &percpu_mct_tick);
                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                     IRQ_MCT_LOCALTIMER, err);
+                     EXYNOS_IRQ_MCT_LOCALTIMER, err);
         }
+
+        local_timer_register(&exynos4_mct_tick_ops);
 #endif /* CONFIG_LOCAL_TIMERS */
 }
 
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0f2035a1eb6..36c3984aaa4 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
         void __iomem *scu_base = scu_base_addr();
         unsigned int i, ncores;
 
-        ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+        if (soc_is_exynos5250())
+                ncores = 2;
+        else
+                ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
         if (ncores > nr_cpu_ids) {
@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-
-        scu_enable(scu_base_addr());
+        if (!soc_is_exynos5250())
+                scu_enable(scu_base_addr());
 
         /*
          * Write the address of secondary startup into the
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e1901305177..428cfeb5772 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,29 +38,29 @@
 #include <mach/pmu.h>
 
 static struct sleep_save exynos4_set_clksrc[] = {
-        { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
-        { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
-        { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
-        { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
-        { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
-        { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
-        { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
-        { .reg = S5P_CLKSRC_MASK_PERIL1                 , .val = 0x01110111, },
-        { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
+        { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
+        { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
+        { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
 };
 
 static struct sleep_save exynos4210_set_clksrc[] = {
-        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+        { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
 };
 
 static struct sleep_save exynos4_epll_save[] = {
-        SAVE_ITEM(S5P_EPLL_CON0),
-        SAVE_ITEM(S5P_EPLL_CON1),
+        SAVE_ITEM(EXYNOS4_EPLL_CON0),
+        SAVE_ITEM(EXYNOS4_EPLL_CON1),
 };
 
 static struct sleep_save exynos4_vpll_save[] = {
-        SAVE_ITEM(S5P_VPLL_CON0),
-        SAVE_ITEM(S5P_VPLL_CON1),
+        SAVE_ITEM(EXYNOS4_VPLL_CON0),
+        SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 
 static struct sleep_save exynos4_core_save[] = {
@@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_SROM_BC3),
 };
 
-static struct sleep_save exynos4_l2cc_save[] = {
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
-};
 
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
@@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void)
         u32 tmp;
 
         s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
-        s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
         s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
         s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
@@ -239,7 +231,7 @@ static void exynos4_restore_pll(void)
                 locktime = (3000 / pll_in_rate) * p_div;
                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 
-                __raw_writel(lockcnt, S5P_EPLL_LOCK);
+                __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
 
                 s3c_pm_do_restore_core(exynos4_epll_save,
                                         ARRAY_SIZE(exynos4_epll_save));
@@ -257,7 +249,7 @@ static void exynos4_restore_pll(void)
                 locktime = 750;
                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 
-                __raw_writel(lockcnt, S5P_VPLL_LOCK);
+                __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
 
                 s3c_pm_do_restore_core(exynos4_vpll_save,
                                         ARRAY_SIZE(exynos4_vpll_save));
@@ -268,14 +260,14 @@ static void exynos4_restore_pll(void)
 
         do {
                 if (epll_wait) {
-                        pll_con = __raw_readl(S5P_EPLL_CON0);
-                        if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+                        pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+                        if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
                                 epll_wait = 0;
                 }
 
                 if (vpll_wait) {
-                        pll_con = __raw_readl(S5P_VPLL_CON0);
-                        if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+                        pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
+                        if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
                                 vpll_wait = 0;
                 }
         } while (epll_wait || vpll_wait);
@@ -388,13 +380,6 @@ static void exynos4_pm_resume(void)
         scu_enable(S5P_VA_SCU);
 #endif
 
-#ifdef CONFIG_CACHE_L2X0
-        s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
-        outer_inv_all();
-        /* enable L2X0*/
-        writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
-#endif
-
 early_wakeup:
         return;
 }
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 0b04af2b13c..13b306808b4 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -183,6 +183,12 @@ static __init int exynos4_pm_init_power_domain(void)
 #ifdef CONFIG_S5P_DEV_CSIS1
         exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
 #endif
+#ifdef CONFIG_S5P_DEV_G2D
+        exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
+#endif
+#ifdef CONFIG_S5P_DEV_JPEG
+        exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
+#endif
         return 0;
 }
 arch_initcall(exynos4_pm_init_power_domain);
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd17c38..b90d94c17f7 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
+        if (soc_is_exynos5250())
+                /* will be implemented with gpio function */
+                return;
+
         s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 94a7087a610..e17e11de4f5 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -274,11 +274,13 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
         allocate_resource(&iomem_resource, &res[0], 0x40000000,
                           0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
 
-        pci_add_resource(&sys->resources, &ioport_resource);
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
         sys->mem_offset  = DC21285_PCI_MEM;
 
+        pci_add_resource_offset(&sys->resources,
+                                &ioport_resource, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+
         return 1;
 }
 
diff --git a/arch/arm/mach-footbridge/include/mach/entry-macro.S b/arch/arm/mach-footbridge/include/mach/entry-macro.S
index d3847be0c66..dabbd5c54a7 100644
--- a/arch/arm/mach-footbridge/include/mach/entry-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/entry-macro.S
@@ -14,9 +14,6 @@
                 .equ    dc21285_high, ARMCSR_BASE & 0xff000000
                 .equ    dc21285_low, ARMCSR_BASE & 0x00ffffff
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 mov     \base, #dc21285_high
                 .if     dc21285_low
@@ -24,9 +21,6 @@
                 .endif
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, [\base, #0x180]       @ get interrupts
 
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
deleted file mode 100644
index a174a5841bc..00000000000
--- a/arch/arm/mach-footbridge/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- *  arch/arm/mach-footbridge/include/mach/system.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
index c5b24b95a76..7355c0bbcb5 100644
--- a/arch/arm/mach-gemini/Makefile
+++ b/arch/arm/mach-gemini/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := irq.o mm.o time.o devices.o gpio.o
+obj-y                   := irq.o mm.o time.o devices.o gpio.o idle.o
 
 # Board-specific support
 obj-$(CONFIG_MACH_NAS4220B)     += board-nas4220b.o
diff --git a/arch/arm/mach-gemini/idle.c b/arch/arm/mach-gemini/idle.c
new file mode 100644
index 00000000000..92bbd6bb600
--- /dev/null
+++ b/arch/arm/mach-gemini/idle.c
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-gemini/idle.c
+ */
+
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/proc-fns.h>
+
+static void gemini_idle(void)
+{
+        /*
+         * Because of broken hardware we have to enable interrupts or the CPU
+         * will never wakeup... Acctualy it is not very good to enable
+         * interrupts first since scheduler can miss a tick, but there is
+         * no other way around this. Platforms that needs it for power saving
+         * should call enable_hlt() in init code, since by default it is
+         * disabled.
+         */
+        local_irq_enable();
+        cpu_do_idle();
+}
+
+static int __init gemini_idle_init(void)
+{
+        arm_pm_idle = gemini_idle;
+        return 0;
+}
+
+arch_initcall(gemini_idle_init);
diff --git a/arch/arm/mach-gemini/include/mach/entry-macro.S b/arch/arm/mach-gemini/include/mach/entry-macro.S
index 1624f91a2b8..f044e430bfa 100644
--- a/arch/arm/mach-gemini/include/mach/entry-macro.S
+++ b/arch/arm/mach-gemini/include/mach/entry-macro.S
@@ -12,15 +12,9 @@
 
 #define IRQ_STATUS      0x14
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS)
         ldr     \irqnr, [\irqstat]
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/include/mach/system.h
index 4d9c1f87247..a33b5a1f8ab 100644
--- a/arch/arm/mach-gemini/include/mach/system.h
+++ b/arch/arm/mach-gemini/include/mach/system.h
@@ -14,20 +14,6 @@
 #include <mach/hardware.h>
 #include <mach/global_reg.h>
 
-static inline void arch_idle(void)
-{
-        /*
-         * Because of broken hardware we have to enable interrupts or the CPU
-         * will never wakeup... Acctualy it is not very good to enable
-         * interrupts here since scheduler can miss a tick, but there is
-         * no other way around this. Platforms that needs it for power saving
-         * should call enable_hlt() in init code, since by default it is
-         * disabled.
-         */
-        local_irq_enable();
-        cpu_do_idle();
-}
-
 static inline void arch_reset(char mode, const char *cmd)
 {
         __raw_writel(RESET_GLOBAL | RESET_CPU1,
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 9485a8fdf85..ca70e5fcc7a 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -73,8 +73,8 @@ void __init gemini_init_irq(void)
         unsigned int i, mode = 0, level = 0;
 
         /*
-         * Disable arch_idle() by default since it is buggy
-         * For more info see arch/arm/mach-gemini/include/mach/system.h
+         * Disable the idle handler by default since it is buggy
+         * For more info see arch/arm/mach-gemini/idle.c
          */
         disable_hlt();
 
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index f8a2f6bb548..e756d1ac00c 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -247,3 +247,21 @@ void h720x_restart(char mode, const char *cmd)
 {
         CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
 }
+
+static void h720x__idle(void)
+{
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
+        nop();
+        nop();
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
+        nop();
+        nop();
+}
+
+static int __init h720x_idle_init(void)
+{
+        arm_pm_idle = h720x__idle;
+        return 0;
+}
+
+arch_initcall(h720x_idle_init);
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
index c3948e5ba4a..75267fad701 100644
--- a/arch/arm/mach-h720x/include/mach/entry-macro.S
+++ b/arch/arm/mach-h720x/include/mach/entry-macro.S
@@ -8,15 +8,9 @@
  * warranty of any kind, whether express or implied.
  */
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
                 @ we could use the id register on H7202, but this is not
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h
deleted file mode 100644
index 16ac46e239a..00000000000
--- a/arch/arm/mach-h720x/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/system.h
- *
- * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * arch/arm/mach-h720x/include/mach/system.h
- *
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-#include <mach/hardware.h>
-
-static void arch_idle(void)
-{
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
-        nop();
-        nop();
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
-        nop();
-        nop();
-}
-
-#endif
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 986958a5a72..f8437dd238c 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -1,6 +1,5 @@
 obj-y                                   := clock.o highbank.o system.o
 obj-$(CONFIG_DEBUG_HIGHBANK_UART)       += lluart.o
 obj-$(CONFIG_SMP)                       += platsmp.o
-obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_PM_SLEEP)                  += pm.o
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8394d512a40..808b055289b 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -27,6 +27,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/gic.h>
@@ -109,8 +110,10 @@ static void __init highbank_timer_init(void)
 
         highbank_clocks_init();
 
-        sp804_clocksource_init(timer_base + 0x20, "timer1");
+        sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
         sp804_clockevents_init(timer_base, irq, "timer0");
+
+        twd_local_timer_of_register();
 }
 
 static struct sys_timer highbank_timer = {
diff --git a/arch/arm/mach-highbank/include/mach/entry-macro.S b/arch/arm/mach-highbank/include/mach/entry-macro.S
deleted file mode 100644
index a14f9e62ca9..00000000000
--- a/arch/arm/mach-highbank/include/mach/entry-macro.S
+++ /dev/null
@@ -1,5 +0,0 @@
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-highbank/include/mach/memory.h b/arch/arm/mach-highbank/include/mach/memory.h
deleted file mode 100644
index 40a8c178f10..00000000000
--- a/arch/arm/mach-highbank/include/mach/memory.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-highbank/localtimer.c b/arch/arm/mach-highbank/localtimer.c
deleted file mode 100644
index 5a00e7945fd..00000000000
--- a/arch/arm/mach-highbank/localtimer.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- * Based on localtimer.c, Copyright (C) 2002 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/init.h>
-#include <linux/clockchips.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <asm/smp_twd.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        struct device_node *np;
-
-        np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
-        if (!twd_base) {
-                twd_base = of_iomap(np, 0);
-                WARN_ON(!twd_base);
-        }
-        evt->irq = irq_of_parse_and_map(np, 0);
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3919fba52ac..52359f80c42 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -298,6 +298,7 @@ config MACH_MX27_3DS
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MX2_CAMERA
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
@@ -314,8 +315,10 @@ config MACH_IMX27_VISSTRIM_M10
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_MX2_CAMERA
         select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select LEDS_GPIO_REGISTER
         help
           Include support for Visstrim_m10 platform and its different variants.
           This includes specific configurations for the board and its
@@ -370,6 +373,14 @@ config MACH_IMX27IPCAM
           Include support for IMX27 IPCAM platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_IMX27_DT
+        bool "Support i.MX27 platforms from device tree"
+        select SOC_IMX27
+        select USE_OF
+        help
+          Include support for Freescale i.MX27 based platforms
+          using the device tree for discovery
+
 endif
 
 if ARCH_IMX_V6_V7
@@ -486,6 +497,7 @@ config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
         select SOC_IMX31
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IPU_CORE
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 55db9c488f2..35fc450fa26 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -8,8 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o
 
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
 
@@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
 obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
+obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
 
 # i.MX31 based machines
 obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
@@ -71,7 +72,6 @@ obj-$(CONFIG_CPU_V7) += head-v7.o
 AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
 
 ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 6dfdbcc83af..3851d8a2787 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -38,5 +38,8 @@ zreladdr-$(CONFIG_SOC_IMX6Q)	+= 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
 
+dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
+dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
+                               imx53-qsb.dtb imx53-smd.dtb
 dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
                            imx6q-sabrelite.dtb
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 88fe00a146e..b9a95ed7555 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/clkdev.h>
+#include <linux/of.h>
 
 #include <asm/div64.h>
 
@@ -661,7 +662,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "dma", dma_clk)
         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
         _REGISTER_CLOCK(NULL, "brom", brom_clk)
-        _REGISTER_CLOCK(NULL, "emma", emma_clk)
+        _REGISTER_CLOCK("m2m-emmaprp.0", NULL, emma_clk)
         _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
         _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
@@ -764,3 +765,20 @@ int __init mx27_clocks_init(unsigned long fref)
         return 0;
 }
 
+#ifdef CONFIG_OF
+int __init mx27_clocks_init_dt(void)
+{
+        struct device_node *np;
+        u32 fref = 26000000; /* default */
+
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+                        continue;
+
+                if (!of_property_read_u32(np, "clock-frequency", &fref))
+                        break;
+        }
+
+        return mx27_clocks_init(fref);
+}
+#endif
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
index 988a28178d4..3a943cd4159 100644
--- a/arch/arm/mach-imx/clock-imx31.c
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -32,7 +32,7 @@
 #include <mach/mx31.h>
 #include <mach/common.h>
 
-#include "crmregs-imx31.h"
+#include "crmregs-imx3.h"
 
 #define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
 
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index ac8238caecb..1e279af656a 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -27,23 +27,7 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 
-#define CCM_BASE        MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
-
-#define CCM_CCMR        0x00
-#define CCM_PDR0        0x04
-#define CCM_PDR1        0x08
-#define CCM_PDR2        0x0C
-#define CCM_PDR3        0x10
-#define CCM_PDR4        0x14
-#define CCM_RCSR        0x18
-#define CCM_MPCTL       0x1C
-#define CCM_PPCTL       0x20
-#define CCM_ACMR        0x24
-#define CCM_COSR        0x28
-#define CCM_CGR0        0x2C
-#define CCM_CGR1        0x30
-#define CCM_CGR2        0x34
-#define CCM_CGR3        0x38
+#include "crmregs-imx3.h"
 
 #ifdef HAVE_SET_RATE_SUPPORT
 static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
@@ -111,14 +95,14 @@ static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
 
 static unsigned long get_rate_mpll(void)
 {
-        ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
+        ulong mpctl = __raw_readl(MX35_CCM_MPCTL);
 
         return mxc_decode_pll(mpctl, 24000000);
 }
 
 static unsigned long get_rate_ppll(void)
 {
-        ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
+        ulong ppctl = __raw_readl(MX35_CCM_PPCTL);
 
         return mxc_decode_pll(ppctl, 24000000);
 }
@@ -148,7 +132,7 @@ static struct arm_ahb_div clk_consumer[] = {
 
 static unsigned long get_rate_arm(void)
 {
-        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
         struct arm_ahb_div *aad;
         unsigned long fref = get_rate_mpll();
 
@@ -161,7 +145,7 @@ static unsigned long get_rate_arm(void)
 
 static unsigned long get_rate_ahb(struct clk *clk)
 {
-        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
         struct arm_ahb_div *aad;
         unsigned long fref = get_rate_arm();
 
@@ -177,8 +161,8 @@ static unsigned long get_rate_ipg(struct clk *clk)
 
 static unsigned long get_rate_uart(struct clk *clk)
 {
-        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
-        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
+        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
         unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
 
         if (pdr3 & (1 << 14))
@@ -189,7 +173,7 @@ static unsigned long get_rate_uart(struct clk *clk)
 
 static unsigned long get_rate_sdhc(struct clk *clk)
 {
-        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+        unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
         unsigned long div, rate;
 
         if (pdr3 & (1 << 6))
@@ -215,7 +199,7 @@ static unsigned long get_rate_sdhc(struct clk *clk)
 
 static unsigned long get_rate_mshc(struct clk *clk)
 {
-        unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
+        unsigned long pdr1 = __raw_readl(MXC_CCM_PDR1);
         unsigned long div1, div2, rate;
 
         if (pdr1 & (1 << 7))
@@ -231,7 +215,7 @@ static unsigned long get_rate_mshc(struct clk *clk)
 
 static unsigned long get_rate_ssi(struct clk *clk)
 {
-        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
         unsigned long div1, div2, rate;
 
         if (pdr2 & (1 << 6))
@@ -256,7 +240,7 @@ static unsigned long get_rate_ssi(struct clk *clk)
 
 static unsigned long get_rate_csi(struct clk *clk)
 {
-        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
         unsigned long rate;
 
         if (pdr2 & (1 << 7))
@@ -269,7 +253,7 @@ static unsigned long get_rate_csi(struct clk *clk)
 
 static unsigned long get_rate_otg(struct clk *clk)
 {
-        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
         unsigned long rate;
 
         if (pdr4 & (1 << 9))
@@ -282,8 +266,8 @@ static unsigned long get_rate_otg(struct clk *clk)
 
 static unsigned long get_rate_ipg_per(struct clk *clk)
 {
-        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
-        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
+        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
         unsigned long div;
 
         if (pdr0 & (1 << 26)) {
@@ -297,7 +281,7 @@ static unsigned long get_rate_ipg_per(struct clk *clk)
 
 static unsigned long get_rate_hsp(struct clk *clk)
 {
-        unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+        unsigned long hsp_podf = (__raw_readl(MXC_CCM_PDR0) >> 20) & 0x03;
         unsigned long fref = get_rate_mpll();
 
         if (fref > 400 * 1000 * 1000) {
@@ -345,7 +329,7 @@ static void clk_cgr_disable(struct clk *clk)
 #define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
         static struct clk name = {                      \
                 .id             = i,                    \
-                .enable_reg     = CCM_BASE + er,        \
+                .enable_reg     = er,                   \
                 .enable_shift   = es,                   \
                 .get_rate       = gr,                   \
                 .set_rate       = sr,                   \
@@ -353,59 +337,59 @@ static void clk_cgr_disable(struct clk *clk)
                 .disable        = clk_cgr_disable,      \
         }
 
-DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
-DEFINE_CLOCK(pata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
-/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
-DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
-DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi1_clk,  0, CCM_CGR0, 10, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi2_clk,  1, CCM_CGR0, 12, get_rate_ipg, NULL);
-DEFINE_CLOCK(ect_clk,    0, CCM_CGR0, 14, get_rate_ipg, NULL);
-DEFINE_CLOCK(edio_clk,   0, CCM_CGR0, 16, NULL, NULL);
-DEFINE_CLOCK(emi_clk,    0, CCM_CGR0, 18, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg, NULL);
-DEFINE_CLOCK(esai_clk,   0, CCM_CGR0, 24, NULL, NULL);
-DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
-
-DEFINE_CLOCK(fec_clk,    0, CCM_CGR1,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(gpio1_clk,  0, CCM_CGR1,  2, NULL, NULL);
-DEFINE_CLOCK(gpio2_clk,  1, CCM_CGR1,  4, NULL, NULL);
-DEFINE_CLOCK(gpio3_clk,  2, CCM_CGR1,  6, NULL, NULL);
-DEFINE_CLOCK(gpt_clk,    0, CCM_CGR1,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_hsp, NULL);
-DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
-DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
-DEFINE_CLOCK(owire_clk,  0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(pwm_clk,    0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(rngc_clk,   0, CCM_CGR1, 30, get_rate_ipg, NULL);
-
-DEFINE_CLOCK(rtc_clk,    0, CCM_CGR2,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(rtic_clk,   0, CCM_CGR2,  2, get_rate_ahb, NULL);
-DEFINE_CLOCK(scc_clk,    0, CCM_CGR2,  4, get_rate_ipg, NULL);
-DEFINE_CLOCK(sdma_clk,   0, CCM_CGR2,  6, NULL, NULL);
-DEFINE_CLOCK(spba_clk,   0, CCM_CGR2,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(spdif_clk,  0, CCM_CGR2, 10, NULL, NULL);
-DEFINE_CLOCK(ssi1_clk,   0, CCM_CGR2, 12, get_rate_ssi, NULL);
-DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
-DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
-DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
-DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
-DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
-DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
-DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
-
-DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
-DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
-DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
+DEFINE_CLOCK(asrc_clk,   0, MX35_CCM_CGR0,  0, NULL, NULL);
+DEFINE_CLOCK(pata_clk,    0, MX35_CCM_CGR0,  2, get_rate_ipg, NULL);
+/* DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR0,  4, NULL, NULL); */
+DEFINE_CLOCK(can1_clk,   0, MX35_CCM_CGR0,  6, get_rate_ipg, NULL);
+DEFINE_CLOCK(can2_clk,   1, MX35_CCM_CGR0,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk,  1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL);
+DEFINE_CLOCK(ect_clk,    0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL);
+DEFINE_CLOCK(edio_clk,   0, MX35_CCM_CGR0, 16, NULL, NULL);
+DEFINE_CLOCK(emi_clk,    0, MX35_CCM_CGR0, 18, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit1_clk,  0, MX35_CCM_CGR0, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit2_clk,  1, MX35_CCM_CGR0, 22, get_rate_ipg, NULL);
+DEFINE_CLOCK(esai_clk,   0, MX35_CCM_CGR0, 24, NULL, NULL);
+DEFINE_CLOCK(esdhc1_clk, 0, MX35_CCM_CGR0, 26, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc2_clk, 1, MX35_CCM_CGR0, 28, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc3_clk, 2, MX35_CCM_CGR0, 30, get_rate_sdhc, NULL);
+
+DEFINE_CLOCK(fec_clk,    0, MX35_CCM_CGR1,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(gpio1_clk,  0, MX35_CCM_CGR1,  2, NULL, NULL);
+DEFINE_CLOCK(gpio2_clk,  1, MX35_CCM_CGR1,  4, NULL, NULL);
+DEFINE_CLOCK(gpio3_clk,  2, MX35_CCM_CGR1,  6, NULL, NULL);
+DEFINE_CLOCK(gpt_clk,    0, MX35_CCM_CGR1,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c1_clk,   0, MX35_CCM_CGR1, 10, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c2_clk,   1, MX35_CCM_CGR1, 12, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c3_clk,   2, MX35_CCM_CGR1, 14, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(iomuxc_clk, 0, MX35_CCM_CGR1, 16, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, MX35_CCM_CGR1, 18, get_rate_hsp, NULL);
+DEFINE_CLOCK(kpp_clk,    0, MX35_CCM_CGR1, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(mlb_clk,    0, MX35_CCM_CGR1, 22, get_rate_ahb, NULL);
+DEFINE_CLOCK(mshc_clk,   0, MX35_CCM_CGR1, 24, get_rate_mshc, NULL);
+DEFINE_CLOCK(owire_clk,  0, MX35_CCM_CGR1, 26, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(pwm_clk,    0, MX35_CCM_CGR1, 28, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(rngc_clk,   0, MX35_CCM_CGR1, 30, get_rate_ipg, NULL);
+
+DEFINE_CLOCK(rtc_clk,    0, MX35_CCM_CGR2,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(rtic_clk,   0, MX35_CCM_CGR2,  2, get_rate_ahb, NULL);
+DEFINE_CLOCK(scc_clk,    0, MX35_CCM_CGR2,  4, get_rate_ipg, NULL);
+DEFINE_CLOCK(sdma_clk,   0, MX35_CCM_CGR2,  6, NULL, NULL);
+DEFINE_CLOCK(spba_clk,   0, MX35_CCM_CGR2,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(spdif_clk,  0, MX35_CCM_CGR2, 10, NULL, NULL);
+DEFINE_CLOCK(ssi1_clk,   0, MX35_CCM_CGR2, 12, get_rate_ssi, NULL);
+DEFINE_CLOCK(ssi2_clk,   1, MX35_CCM_CGR2, 14, get_rate_ssi, NULL);
+DEFINE_CLOCK(uart1_clk,  0, MX35_CCM_CGR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk,  1, MX35_CCM_CGR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk,  2, MX35_CCM_CGR2, 20, get_rate_uart, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, MX35_CCM_CGR2, 22, get_rate_otg, NULL);
+DEFINE_CLOCK(wdog_clk,   0, MX35_CCM_CGR2, 24, NULL, NULL);
+DEFINE_CLOCK(max_clk,    0, MX35_CCM_CGR2, 26, NULL, NULL);
+DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR2, 30, NULL, NULL);
+
+DEFINE_CLOCK(csi_clk,    0, MX35_CCM_CGR3,  0, get_rate_csi, NULL);
+DEFINE_CLOCK(iim_clk,    0, MX35_CCM_CGR3,  2, NULL, NULL);
+DEFINE_CLOCK(gpu2d_clk,  0, MX35_CCM_CGR3,  4, NULL, NULL);
 
 DEFINE_CLOCK(usbahb_clk, 0, 0,         0, get_rate_ahb, NULL);
 
@@ -422,7 +406,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
 {
         unsigned long div1;
 
-        div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
+        div1 = (__raw_readl(MX35_CCM_PDR4) >> 28) + 1;
 
         return get_rate_ahb(NULL) / div1;
 }
@@ -518,11 +502,11 @@ int __init mx35_clocks_init()
         /* Turn off all clocks except the ones we need to survive, namely:
          * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
          */
-        __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
+        __raw_writel((3 << 18), MX35_CCM_CGR0);
         __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
-                        CCM_BASE + CCM_CGR1);
-        __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
-        __raw_writel(0, CCM_BASE + CCM_CGR3);
+                        MX35_CCM_CGR1);
+        __raw_writel(cgr2, MX35_CCM_CGR2);
+        __raw_writel(0, MX35_CCM_CGR3);
 
         clk_enable(&iim_clk);
         imx_print_silicon_rev("i.MX35", mx35_revision());
@@ -533,7 +517,7 @@ int __init mx35_clocks_init()
          * extra clocks turned on, otherwise the MX35 boot ROM code will
          * hang after a watchdog reset.
          */
-        if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
+        if (!(__raw_readl(MX35_CCM_RCSR) & (3 << 10))) {
                 /* Additionally turn on UART1, SCC, and IIM clocks */
                 clk_enable(&iim_clk);
                 clk_enable(&uart1_clk);
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 2d88f8b9a45..111c328f542 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -329,6 +329,12 @@
 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
 
+#define BP_CCOSR_CKO1_EN                7
+#define BP_CCOSR_CKO1_PODF              4
+#define BM_CCOSR_CKO1_PODF              (0x7 << 4)
+#define BP_CCOSR_CKO1_SEL               0
+#define BM_CCOSR_CKO1_SEL               (0xf << 0)
+
 #define FREQ_480M       480000000
 #define FREQ_528M       528000000
 #define FREQ_594M       594000000
@@ -393,6 +399,7 @@ static struct clk ipu1_di1_clk;
 static struct clk ipu2_di0_clk;
 static struct clk ipu2_di1_clk;
 static struct clk enfc_clk;
+static struct clk cko1_clk;
 static struct clk dummy_clk = {};
 
 static unsigned long external_high_reference;
@@ -938,6 +945,24 @@ static void _clk_disable(struct clk *clk)
         writel_relaxed(reg, clk->enable_reg);
 }
 
+static int _clk_enable_1b(struct clk *clk)
+{
+        u32 reg;
+        reg = readl_relaxed(clk->enable_reg);
+        reg |= 0x1 << clk->enable_shift;
+        writel_relaxed(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable_1b(struct clk *clk)
+{
+        u32 reg;
+        reg = readl_relaxed(clk->enable_reg);
+        reg &= ~(0x1 << clk->enable_shift);
+        writel_relaxed(reg, clk->enable_reg);
+}
+
 struct divider {
         struct clk *clk;
         void __iomem *reg;
@@ -983,6 +1008,7 @@ DEF_CLK_DIV1(ipu2_di0_pre_div,	&ipu2_di0_pre_clk,	CSCDR2,	IPU2_DI0_PRE);
 DEF_CLK_DIV1(ipu2_di1_pre_div,  &ipu2_di1_pre_clk,      CSCDR2, IPU2_DI1_PRE);
 DEF_CLK_DIV1(ipu1_div,          &ipu1_clk,              CSCDR3, IPU1_HSP);
 DEF_CLK_DIV1(ipu2_div,          &ipu2_clk,              CSCDR3, IPU2_HSP);
+DEF_CLK_DIV1(cko1_div,          &cko1_clk,              CCOSR, CKO1);
 
 #define DEF_CLK_DIV2(d, c, r, b)                                \
         static struct divider d = {                             \
@@ -1038,6 +1064,7 @@ static struct divider *dividers[] = {
         &enfc_div,
         &spdif_div,
         &asrc_serial_div,
+        &cko1_div,
 };
 
 static unsigned long ldb_di_clk_get_rate(struct clk *clk)
@@ -1625,6 +1652,32 @@ DEF_IPU_DI_MUX(CSCDR2, 2, 1);
 DEF_IPU_MUX(1);
 DEF_IPU_MUX(2);
 
+static struct multiplexer cko1_mux = {
+        .clk = &cko1_clk,
+        .reg = CCOSR,
+        .bp = BP_CCOSR_CKO1_SEL,
+        .bm = BM_CCOSR_CKO1_SEL,
+        .parents = {
+                &pll3_usb_otg,
+                &pll2_bus,
+                &pll1_sys,
+                &pll5_video,
+                &dummy_clk,
+                &axi_clk,
+                &enfc_clk,
+                &ipu1_di0_clk,
+                &ipu1_di1_clk,
+                &ipu2_di0_clk,
+                &ipu2_di1_clk,
+                &ahb_clk,
+                &ipg_clk,
+                &ipg_perclk,
+                &ckil_clk,
+                &pll4_audio,
+                NULL
+        },
+};
+
 static struct multiplexer *multiplexers[] = {
         &axi_mux,
         &periph_mux,
@@ -1667,6 +1720,7 @@ static struct multiplexer *multiplexers[] = {
         &ipu2_di1_mux,
         &ipu1_mux,
         &ipu2_mux,
+        &cko1_mux,
 };
 
 static int _clk_set_parent(struct clk *clk, struct clk *parent)
@@ -1690,7 +1744,7 @@ static int _clk_set_parent(struct clk *clk, struct clk *parent)
                         break;
                 i++;
         }
-        if (!m->parents[i])
+        if (!m->parents[i] || m->parents[i] == &dummy_clk)
                 return -EINVAL;
 
         val = readl_relaxed(m->reg);
@@ -1745,6 +1799,20 @@ DEF_NG_CLK(asrc_serial_clk,	&pll3_usb_otg);
                 .secondary      = s,                    \
         }
 
+#define DEF_CLK_1B(name, er, es, p, s)                  \
+        static struct clk name = {                      \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .enable         = _clk_enable_1b,       \
+                .disable        = _clk_disable_1b,      \
+                .get_rate       = _clk_get_rate,        \
+                .set_rate       = _clk_set_rate,        \
+                .round_rate     = _clk_round_rate,      \
+                .set_parent     = _clk_set_parent,      \
+                .parent         = p,                    \
+                .secondary      = s,                    \
+        }
+
 DEF_CLK(aips_tz1_clk,     CCGR0, CG0,  &ahb_clk,          NULL);
 DEF_CLK(aips_tz2_clk,     CCGR0, CG1,  &ahb_clk,          NULL);
 DEF_CLK(apbh_dma_clk,     CCGR0, CG2,  &ahb_clk,          NULL);
@@ -1811,6 +1879,7 @@ DEF_CLK(usdhc4_clk,	  CCGR6, CG4,  &pll2_pfd_400m,	  NULL);
 DEF_CLK(emi_slow_clk,     CCGR6, CG5,  &axi_clk,          NULL);
 DEF_CLK(vdo_axi_clk,      CCGR6, CG6,  &axi_clk,          NULL);
 DEF_CLK(vpu_clk,          CCGR6, CG7,  &axi_clk,          NULL);
+DEF_CLK_1B(cko1_clk,      CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
 
 static int pcie_clk_enable(struct clk *clk)
 {
@@ -1922,6 +1991,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
         _REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
+        _REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk),
 };
 
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
@@ -2029,6 +2099,8 @@ int __init mx6q_clocks_init(void)
         clk_set_rate(&usdhc3_clk, 49500000);
         clk_set_rate(&usdhc4_clk, 49500000);
 
+        clk_set_parent(&cko1_clk, &ahb_clk);
+
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
         base = of_iomap(np, 0);
         WARN_ON(!base);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 5e2e7a84386..aa15c517d06 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -149,39 +149,3 @@ int mx50_revision(void)
         return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx50_revision);
-
-static int __init post_cpu_init(void)
-{
-        unsigned int reg;
-        void __iomem *base;
-
-        if (cpu_is_mx51() || cpu_is_mx53()) {
-                if (cpu_is_mx51())
-                        base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
-                else
-                        base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
-
-                __raw_writel(0x0, base + 0x40);
-                __raw_writel(0x0, base + 0x44);
-                __raw_writel(0x0, base + 0x48);
-                __raw_writel(0x0, base + 0x4C);
-                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-                __raw_writel(reg, base + 0x50);
-
-                if (cpu_is_mx51())
-                        base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
-                else
-                        base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
-
-                __raw_writel(0x0, base + 0x40);
-                __raw_writel(0x0, base + 0x44);
-                __raw_writel(0x0, base + 0x48);
-                __raw_writel(0x0, base + 0x4C);
-                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-                __raw_writel(reg, base + 0x50);
-        }
-
-        return 0;
-}
-
-postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
index 9d34c3d4c02..7b92cd6da6d 100644
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ b/arch/arm/mach-imx/cpu_op-mx51.c
@@ -11,6 +11,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/bug.h>
 #include <linux/types.h>
 #include <mach/hardware.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-imx/crmregs-imx31.h b/arch/arm/mach-imx/crmregs-imx3.h
index 37a8a07beda..53141273df4 100644
--- a/arch/arm/mach-imx/crmregs-imx31.h
+++ b/arch/arm/mach-imx/crmregs-imx3.h
@@ -24,23 +24,36 @@
 #define CKIH_CLK_FREQ_27MHZ     27000000
 #define CKIL_CLK_FREQ           32768
 
-#define MXC_CCM_BASE            MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
+#define MXC_CCM_BASE            (cpu_is_mx31() ? \
+MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR))
 
 /* Register addresses */
 #define MXC_CCM_CCMR            (MXC_CCM_BASE + 0x00)
 #define MXC_CCM_PDR0            (MXC_CCM_BASE + 0x04)
 #define MXC_CCM_PDR1            (MXC_CCM_BASE + 0x08)
+#define MX35_CCM_PDR2           (MXC_CCM_BASE + 0x0C)
 #define MXC_CCM_RCSR            (MXC_CCM_BASE + 0x0C)
+#define MX35_CCM_PDR3           (MXC_CCM_BASE + 0x10)
 #define MXC_CCM_MPCTL           (MXC_CCM_BASE + 0x10)
+#define MX35_CCM_PDR4           (MXC_CCM_BASE + 0x14)
 #define MXC_CCM_UPCTL           (MXC_CCM_BASE + 0x14)
+#define MX35_CCM_RCSR           (MXC_CCM_BASE + 0x18)
 #define MXC_CCM_SRPCTL          (MXC_CCM_BASE + 0x18)
+#define MX35_CCM_MPCTL          (MXC_CCM_BASE + 0x1C)
 #define MXC_CCM_COSR            (MXC_CCM_BASE + 0x1C)
+#define MX35_CCM_PPCTL          (MXC_CCM_BASE + 0x20)
 #define MXC_CCM_CGR0            (MXC_CCM_BASE + 0x20)
+#define MX35_CCM_ACMR           (MXC_CCM_BASE + 0x24)
 #define MXC_CCM_CGR1            (MXC_CCM_BASE + 0x24)
+#define MX35_CCM_COSR           (MXC_CCM_BASE + 0x28)
 #define MXC_CCM_CGR2            (MXC_CCM_BASE + 0x28)
+#define MX35_CCM_CGR0           (MXC_CCM_BASE + 0x2C)
 #define MXC_CCM_WIMR            (MXC_CCM_BASE + 0x2C)
+#define MX35_CCM_CGR1           (MXC_CCM_BASE + 0x30)
 #define MXC_CCM_LDC             (MXC_CCM_BASE + 0x30)
+#define MX35_CCM_CGR2           (MXC_CCM_BASE + 0x34)
 #define MXC_CCM_DCVR0           (MXC_CCM_BASE + 0x34)
+#define MX35_CCM_CGR3           (MXC_CCM_BASE + 0x38)
 #define MXC_CCM_DCVR1           (MXC_CCM_BASE + 0x38)
 #define MXC_CCM_DCVR2           (MXC_CCM_BASE + 0x3C)
 #define MXC_CCM_DCVR3           (MXC_CCM_BASE + 0x40)
@@ -64,6 +77,7 @@
 #define MXC_CCM_CCMR_SSI2S_MASK                 (0x3 << 21)
 #define MXC_CCM_CCMR_LPM_OFFSET                 14
 #define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
+#define MXC_CCM_CCMR_LPM_WAIT_MX35              (0x1 << 14)
 #define MXC_CCM_CCMR_FIRS_OFFSET                11
 #define MXC_CCM_CCMR_FIRS_MASK                  (0x3 << 11)
 #define MXC_CCM_CCMR_UPE                        (1 << 9)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 2f727d7c380..28537a5d904 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -50,6 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
 extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
+#define imx27_add_mx2_emmaprp(pdata)    \
+        imx_add_mx2_emmaprp(&imx27_mx2_camera_data)
 
 extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
 #define imx27_add_mxc_ehci_otg(pdata)   \
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
new file mode 100644
index 00000000000..861ceb8232d
--- /dev/null
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx27.h>
+
+static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
+        { /* sentinel */ }
+};
+
+static int __init imx27_avic_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        irq_domain_add_simple(np, 0);
+        return 0;
+}
+
+static int __init imx27_gpio_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
+
+        irq_domain_add_simple(np, gpio_irq_base);
+
+        return 0;
+}
+
+static const struct of_device_id imx27_irq_match[] __initconst = {
+        { .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
+        { .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, },
+        { /* sentinel */ }
+};
+
+static void __init imx27_dt_init(void)
+{
+        of_irq_init(imx27_irq_match);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             imx27_auxdata_lookup, NULL);
+}
+
+static void __init imx27_timer_init(void)
+{
+        mx27_clocks_init_dt();
+}
+
+static struct sys_timer imx27_timer = {
+        .init = imx27_timer_init,
+};
+
+static const char *imx27_dt_board_compat[] __initdata = {
+        "fsl,imx27",
+        NULL
+};
+
+DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
+        .map_io         = mx27_map_io,
+        .init_early     = imx27_init_early,
+        .init_irq       = mx27_init_irq,
+        .handle_irq     = imx27_handle_irq,
+        .timer          = &imx27_timer,
+        .init_machine   = imx27_dt_init,
+        .dt_compat      = imx27_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 1e03ef42faa..5cca573964f 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -104,6 +104,7 @@ static struct sys_timer imx51_timer = {
 
 static const char *imx51_dt_board_compat[] __initdata = {
         "fsl,imx51-babbage",
+        "fsl,imx51",
         NULL
 };
 
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index fd5be0f20fb..4172279b390 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -114,6 +114,7 @@ static const char *imx53_dt_board_compat[] __initdata = {
         "fsl,imx53-evk",
         "fsl,imx53-qsb",
         "fsl,imx53-smd",
+        "fsl,imx53",
         NULL
 };
 
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index d4ab6f29a76..0213f8dcee8 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -17,7 +17,7 @@
 #include <mach/hardware.h>
 
 static struct map_desc imx_lluart_desc = {
-#ifdef CONFIG_DEBUG_IMX6Q_UART
+#ifdef CONFIG_DEBUG_IMX6Q_UART4
         .virtual        = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
         .pfn            = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
         .length         = MX6Q_UART4_SIZE,
diff --git a/arch/arm/mach-imx/localtimer.c b/arch/arm/mach-imx/localtimer.c
deleted file mode 100644
index 3a163515d41..00000000000
--- a/arch/arm/mach-imx/localtimer.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/clockchips.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/smp_twd.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        struct device_node *np;
-
-        np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
-        if (!twd_base) {
-                twd_base = of_iomap(np, 0);
-                WARN_ON(!twd_base);
-        }
-        evt->irq = irq_of_parse_and_map(np, 0);
-        twd_timer_setup(evt);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index e4f426a0989..27bc27e6ea4 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -51,7 +51,7 @@
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "crmregs-imx31.h"
+#include "crmregs-imx3.h"
 
 static int armadillo5x0_pins[] = {
         /* UART1 */
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 428459fbca4..f7b074f496f 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,6 +30,10 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/leds.h>
+#include <linux/memblock.h>
+#include <media/soc_camera.h>
 #include <sound/tlv320aic32x4.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,6 +43,8 @@
 
 #include "devices-imx27.h"
 
+#define TVP5150_RSTN (GPIO_PORTC + 18)
+#define TVP5150_PWDN (GPIO_PORTC + 19)
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ IRQ_GPIOB(25)
 
@@ -100,8 +106,99 @@ static const int visstrim_m10_pins[] __initconst = {
         PE1_PF_USBOTG_STP,
         PB23_PF_USB_PWR,
         PB24_PF_USB_OC,
+        /* CSI */
+        PB10_PF_CSI_D0,
+        PB11_PF_CSI_D1,
+        PB12_PF_CSI_D2,
+        PB13_PF_CSI_D3,
+        PB14_PF_CSI_D4,
+        PB15_PF_CSI_MCLK,
+        PB16_PF_CSI_PIXCLK,
+        PB17_PF_CSI_D5,
+        PB18_PF_CSI_D6,
+        PB19_PF_CSI_D7,
+        PB20_PF_CSI_VSYNC,
+        PB21_PF_CSI_HSYNC,
 };
 
+/* Camera */
+static int visstrim_camera_power(struct device *dev, int on)
+{
+        gpio_set_value(TVP5150_PWDN, on);
+
+        return 0;
+};
+
+static int visstrim_camera_reset(struct device *dev)
+{
+        gpio_set_value(TVP5150_RSTN, 0);
+        ndelay(500);
+        gpio_set_value(TVP5150_RSTN, 1);
+
+        return 0;
+};
+
+static struct i2c_board_info visstrim_i2c_camera =  {
+        I2C_BOARD_INFO("tvp5150", 0x5d),
+};
+
+static struct soc_camera_link iclink_tvp5150 = {
+        .bus_id         = 0,
+        .board_info     = &visstrim_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power = visstrim_camera_power,
+        .reset = visstrim_camera_reset,
+};
+
+static struct mx2_camera_platform_data visstrim_camera = {
+        .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE |
+                        MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING,
+        .clk = 100000,
+};
+
+static phys_addr_t mx2_camera_base __initdata;
+#define MX2_CAMERA_BUF_SIZE SZ_8M
+
+static void __init visstrim_camera_init(void)
+{
+        struct platform_device *pdev;
+        int dma;
+
+        /* Initialize tvp5150 gpios */
+        mxc_gpio_mode(TVP5150_RSTN | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(TVP5150_PWDN | GPIO_GPIO | GPIO_OUT);
+        gpio_set_value(TVP5150_RSTN, 1);
+        gpio_set_value(TVP5150_PWDN, 0);
+        ndelay(1);
+
+        gpio_set_value(TVP5150_PWDN, 1);
+        ndelay(1);
+        gpio_set_value(TVP5150_RSTN, 0);
+        ndelay(500);
+        gpio_set_value(TVP5150_RSTN, 1);
+        ndelay(200000);
+
+        pdev = imx27_add_mx2_camera(&visstrim_camera);
+        if (IS_ERR(pdev))
+                return;
+
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                mx2_camera_base, mx2_camera_base,
+                                MX2_CAMERA_BUF_SIZE,
+                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+
+static void __init visstrim_reserve(void)
+{
+        /* reserve 4 MiB for mx2-camera */
+        mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE,
+                        MX2_CAMERA_BUF_SIZE);
+        memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
+        memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
+}
+
 /* GPIOs used as events for applications */
 static struct gpio_keys_button visstrim_gpio_keys[] = {
         {
@@ -136,6 +233,35 @@ static const struct gpio_keys_platform_data
         .nbuttons       = ARRAY_SIZE(visstrim_gpio_keys),
 };
 
+/* led */
+static const struct gpio_led visstrim_m10_leds[] __initconst = {
+        {
+                .name = "visstrim:ld0",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 29),
+        },
+        {
+                .name = "visstrim:ld1",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 24),
+        },
+        {
+                .name = "visstrim:ld2",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 28),
+        },
+        {
+                .name = "visstrim:ld3",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 25),
+        },
+};
+
+static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = {
+        .leds = visstrim_m10_leds,
+        .num_leds = ARRAY_SIZE(visstrim_m10_leds),
+};
+
 /* Visstrim_SM10 has a microSD slot connected to sdhc1 */
 static int visstrim_m10_sdhc1_init(struct device *dev,
                 irq_handler_t detect_irq, void *data)
@@ -216,6 +342,9 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("tlv320aic32x4", 0x18),
                 .platform_data = &visstrim_m10_aic32x4_pdata,
+        },
+        {
+                 I2C_BOARD_INFO("m41t00", 0x68),
         }
 };
 
@@ -254,16 +383,21 @@ static void __init visstrim_m10_board_init(void)
         imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
         imx27_add_imx_uart0(&uart_pdata);
 
-        i2c_register_board_info(0, visstrim_m10_i2c_devices,
-                                ARRAY_SIZE(visstrim_m10_i2c_devices));
         imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
         imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
+        i2c_register_board_info(0, visstrim_m10_i2c_devices,
+                                ARRAY_SIZE(visstrim_m10_i2c_devices));
+
         imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
         imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
         imx27_add_fec(NULL);
         imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
         imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0);
+        platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
+                                      &iclink_tvp5150, sizeof(iclink_tvp5150));
+        gpio_led_register_device(0, &visstrim_m10_led_data);
+        visstrim_camera_init();
 }
 
 static void __init visstrim_m10_timer_init(void)
@@ -277,6 +411,7 @@ static struct sys_timer visstrim_m10_timer = {
 
 MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
         .atag_offset = 0x100,
+        .reserve = visstrim_reserve,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index e4bbd4f0294..da6c1d9af76 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -21,6 +21,7 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
@@ -121,6 +122,7 @@ static void __init imx6q_init_irq(void)
 static void __init imx6q_timer_init(void)
 {
         mx6q_clocks_init();
+        twd_local_timer_of_register();
 }
 
 static struct sys_timer imx6q_timer = {
@@ -130,6 +132,7 @@ static struct sys_timer imx6q_timer = {
 static const char *imx6q_dt_compat[] __initdata = {
         "fsl,imx6q-arm2",
         "fsl,imx6q-sabrelite",
+        "fsl,imx6q",
         NULL,
 };
 
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 8d9f95514b1..e432d4acee1 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -37,8 +37,8 @@
 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
                 (MX21ADS_MMIO_BASE_ADDR + (offset))
 
+#define MX21ADS_CS8900A_MMIO_SIZE   0x200000
 #define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
-#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
 #define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
@@ -159,6 +159,18 @@ static struct platform_device mx21ads_nor_mtd_device = {
         .resource = &mx21ads_flash_resource,
 };
 
+static const struct resource mx21ads_cs8900_resources[] __initconst = {
+        DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
+        DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ),
+};
+
+static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
+        .name = "cs89x0",
+        .id = 0,
+        .res = mx21ads_cs8900_resources,
+        .num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
+};
+
 static const struct imxuart_platform_data uart_pdata_rts __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -292,6 +304,8 @@ static void __init mx21ads_board_init(void)
         imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        platform_device_register_full(
+                        (struct platform_device_info *)&mx21ads_cs8900_devinfo);
 }
 
 static void __init mx21ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 18f35816706..c6d385c5225 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -31,6 +31,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/spi/l4f00242t03.h>
 
+#include <media/soc_camera.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -52,6 +54,8 @@
 #define SD1_CD                  IMX_GPIO_NR(2, 26)
 #define LCD_RESET               IMX_GPIO_NR(1, 3)
 #define LCD_ENABLE              IMX_GPIO_NR(1, 31)
+#define CSI_PWRDWN              IMX_GPIO_NR(4, 19)
+#define CSI_RESET               IMX_GPIO_NR(3, 6)
 
 static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
@@ -141,6 +145,26 @@ static const int mx27pdk_pins[] __initconst = {
         PA30_PF_CONTRAST,
         LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
         LCD_RESET | GPIO_GPIO | GPIO_OUT,
+        /* CSI */
+        PB10_PF_CSI_D0,
+        PB11_PF_CSI_D1,
+        PB12_PF_CSI_D2,
+        PB13_PF_CSI_D3,
+        PB14_PF_CSI_D4,
+        PB15_PF_CSI_MCLK,
+        PB16_PF_CSI_PIXCLK,
+        PB17_PF_CSI_D5,
+        PB18_PF_CSI_D6,
+        PB19_PF_CSI_D7,
+        PB20_PF_CSI_VSYNC,
+        PB21_PF_CSI_HSYNC,
+        CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
+        CSI_RESET | GPIO_GPIO | GPIO_OUT,
+};
+
+static struct gpio mx27_3ds_camera_gpios[] = {
+        { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" },
+        { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" },
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -242,6 +266,7 @@ static struct regulator_init_data gpo_init = {
 
 static struct regulator_consumer_supply vmmc1_consumers[] = {
         REGULATOR_SUPPLY("vcore", "spi0.0"),
+        REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
 };
 
 static struct regulator_init_data vmmc1_init = {
@@ -270,6 +295,22 @@ static struct regulator_init_data vgen_init = {
         .consumer_supplies = vgen_consumers,
 };
 
+static struct regulator_consumer_supply vvib_consumers[] = {
+        REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data vvib_init = {
+        .constraints = {
+                .min_uV = 1300000,
+                .max_uV = 1300000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
+        .consumer_supplies = vvib_consumers,
+};
+
 static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
         {
                 .id = MC13783_REG_VMMC1,
@@ -283,6 +324,9 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
         }, {
                 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
                 .init_data = &gpo_init,
+        }, {
+                .id = MC13783_REG_VVIB,  /* Power OV2640 */
+                .init_data = &vvib_init,
         },
 };
 
@@ -311,6 +355,51 @@ static const struct spi_imx_master spi2_pdata __initconst = {
         .num_chipselect = ARRAY_SIZE(spi2_chipselect),
 };
 
+static int mx27_3ds_camera_power(struct device *dev, int on)
+{
+        /* enable or disable the camera */
+        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+        gpio_set_value(CSI_PWRDWN, on ? 0 : 1);
+
+        if (!on)
+                goto out;
+
+        /* If enabled, give a reset impulse */
+        gpio_set_value(CSI_RESET, 0);
+        msleep(20);
+        gpio_set_value(CSI_RESET, 1);
+        msleep(100);
+
+out:
+        return 0;
+}
+
+static struct i2c_board_info mx27_3ds_i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct regulator_bulk_data mx27_3ds_camera_regs[] = {
+        { .supply = "cmos_vcore" },
+        { .supply = "cmos_2v8" },
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id         = 0,
+        .board_info     = &mx27_3ds_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power          = mx27_3ds_camera_power,
+        .regulators     = mx27_3ds_camera_regs,
+        .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs),
+};
+
+static struct platform_device mx27_3ds_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
+};
+
 static struct imx_fb_videomode mx27_3ds_modes[] = {
         {       /* 480x640 @ 60 Hz */
                 .mode = {
@@ -367,12 +456,21 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
         },
 };
 
+static struct platform_device *devices[] __initdata = {
+        &mx27_3ds_ov2640,
+};
+
+static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = {
+        .clk = 26000000,
+};
+
 static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
         .bitrate = 100000,
 };
 
 static void __init mx27pdk_init(void)
 {
+        int ret;
         imx27_soc_init();
 
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@@ -404,7 +502,17 @@ static void __init mx27pdk_init(void)
         if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
         imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
         imx27_add_imx_fb(&mx27_3ds_fb_data);
+
+        ret = gpio_request_array(mx27_3ds_camera_gpios,
+                                 ARRAY_SIZE(mx27_3ds_camera_gpios));
+        if (ret) {
+                pr_err("Failed to request camera gpios");
+                iclink_ov2640.power = NULL;
+        }
+
+        imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 4917aab0e25..4518e544822 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -28,7 +28,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31ads.h>
 #include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -39,6 +38,9 @@
 
 #include "devices-imx31.h"
 
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
+
 /* PBC Board interrupt status register */
 #define PBC_INTSTATUS           0x000016
 
@@ -62,6 +64,7 @@
 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
+#define MXC_EXP_IO_BASE         MXC_BOARD_IRQ_START
 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
 
 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
@@ -69,6 +72,10 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
+/* CS8900 */
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define CS4_CS8900_MMIO_START   0x20000
+
 /*
  * The serial port definition structure.
  */
@@ -101,11 +108,29 @@ static struct platform_device serial_device = {
         },
 };
 
+static const struct resource mx31ads_cs8900_resources[] __initconst = {
+        DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
+        DEFINE_RES_IRQ(EXPIO_INT_ENET_INT),
+};
+
+static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
+        .name = "cs89x0",
+        .id = 0,
+        .res = mx31ads_cs8900_resources,
+        .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
+};
+
 static int __init mxc_init_extuart(void)
 {
         return platform_device_register(&serial_device);
 }
 
+static void __init mxc_init_ext_ethernet(void)
+{
+        platform_device_register_full(
+                (struct platform_device_info *)&mx31ads_cs8900_devinfo);
+}
+
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -492,12 +517,15 @@ static void __init mxc_init_audio(void)
         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
 
-/* static mappings */
+/*
+ * Static mappings, starting from the CS4 start address up to the start address
+ * of the CS8900.
+ */
 static struct map_desc mx31ads_io_desc[] __initdata = {
         {
                 .virtual        = MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
-                .length         = MX31_CS4_SIZE / 2,
+                .length         = CS4_CS8900_MMIO_START,
                 .type           = MT_DEVICE
         },
 };
@@ -522,6 +550,7 @@ static void __init mx31ads_init(void)
         mxc_init_imx_uart();
         mxc_init_i2c();
         mxc_init_audio();
+        mxc_init_ext_ethernet();
 }
 
 static void __init mx31ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index f225262b5c3..f17a15f2831 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -507,7 +507,7 @@ static void mx31moboard_poweroff(void)
         struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
 
         if (!IS_ERR(clk))
-                clk_enable(clk);
+                clk_prepare_enable(clk);
 
         mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
 
@@ -530,6 +530,8 @@ static void __init mx31moboard_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
         gpio_led_register_device(-1, &mx31moboard_led_pdata);
 
+        imx31_add_imx2_wdt(NULL);
+
         imx31_add_imx_uart0(&uart0_pdata);
         imx31_add_imx_uart4(&uart4_pdata);
 
@@ -590,7 +592,7 @@ static void __init mx31moboard_reserve(void)
 }
 
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
-        /* Maintainer: Valentin Longchamp, EPFL Mobots group */
+        /* Maintainer: Philippe Retornaz, EPFL Mobots group */
         .atag_offset = 0x100,
         .reserve = mx31moboard_reserve,
         .map_io = mx31_map_io,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c5b3f..e14291d89e4 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -4,6 +4,11 @@
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
+ * Copyright (C) 2011 Meprolight, Ltd.
+ * Alex Gershgorin <alexg@meprolight.com>
+ *
+ * Modified from i.MX31 3-Stack Development System
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -34,15 +39,102 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
+#include <video/platform_lcd.h>
+
+#include <media/soc_camera.h>
 
 #include "devices-imx35.h"
 
+#define GPIO_MC9S08DZ60_GPS_ENABLE 0
+#define GPIO_MC9S08DZ60_HDD_ENABLE 4
+#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
+#define GPIO_MC9S08DZ60_LCD_ENABLE 6
+#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8
+
+static const struct fb_videomode fb_modedb[] = {
+        {
+                 /* 800x480 @ 55 Hz */
+                .name = "Ceramate-CLAA070VC01",
+                .refresh = 55,
+                .xres = 800,
+                .yres = 480,
+                .pixclock = 40000,
+                .left_margin = 40,
+                .right_margin = 40,
+                .upper_margin = 5,
+                .lower_margin = 5,
+                .hsync_len = 20,
+                .vsync_len = 10,
+                .sync = FB_SYNC_OE_ACT_HIGH,
+                .vmode = FB_VMODE_NONINTERLACED,
+                .flag = 0,
+         },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+        .name = "Ceramate-CLAA070VC01",
+        .mode = fb_modedb,
+        .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct i2c_board_info __initdata i2c_devices_3ds[] = {
+        {
+                I2C_BOARD_INFO("mc9s08dz60", 0x69),
+        },
+};
+
+static int lcd_power_gpio = -ENXIO;
+
+static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
+                                                     void *data)
+{
+        return !strcmp(chip->label, data);
+}
+
+static void mx35_3ds_lcd_set_power(
+                                struct plat_lcd_data *pd, unsigned int power)
+{
+        struct gpio_chip *chip;
+
+        if (!gpio_is_valid(lcd_power_gpio)) {
+                chip = gpiochip_find(
+                                "mc9s08dz60", mc9s08dz60_gpiochip_match);
+                if (chip) {
+                        lcd_power_gpio =
+                                chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
+                        if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
+                                pr_err("error: gpio already requested!\n");
+                                lcd_power_gpio = -ENXIO;
+                        }
+                } else {
+                        pr_err("error: didn't find mc9s08dz60 gpio chip\n");
+                }
+        }
+
+        if (gpio_is_valid(lcd_power_gpio))
+                gpio_set_value_cansleep(lcd_power_gpio, power);
+}
+
+static struct plat_lcd_data mx35_3ds_lcd_data = {
+        .set_power = mx35_3ds_lcd_set_power,
+};
+
+static struct platform_device mx35_3ds_lcd = {
+        .name = "platform-lcd",
+        .dev.platform_data = &mx35_3ds_lcd_data,
+};
+
 #define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +212,109 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
         /* I2C1 */
         MX35_PAD_I2C1_CLK__I2C1_SCL,
         MX35_PAD_I2C1_DAT__I2C1_SDA,
+        /* Display */
+        MX35_PAD_LD0__IPU_DISPB_DAT_0,
+        MX35_PAD_LD1__IPU_DISPB_DAT_1,
+        MX35_PAD_LD2__IPU_DISPB_DAT_2,
+        MX35_PAD_LD3__IPU_DISPB_DAT_3,
+        MX35_PAD_LD4__IPU_DISPB_DAT_4,
+        MX35_PAD_LD5__IPU_DISPB_DAT_5,
+        MX35_PAD_LD6__IPU_DISPB_DAT_6,
+        MX35_PAD_LD7__IPU_DISPB_DAT_7,
+        MX35_PAD_LD8__IPU_DISPB_DAT_8,
+        MX35_PAD_LD9__IPU_DISPB_DAT_9,
+        MX35_PAD_LD10__IPU_DISPB_DAT_10,
+        MX35_PAD_LD11__IPU_DISPB_DAT_11,
+        MX35_PAD_LD12__IPU_DISPB_DAT_12,
+        MX35_PAD_LD13__IPU_DISPB_DAT_13,
+        MX35_PAD_LD14__IPU_DISPB_DAT_14,
+        MX35_PAD_LD15__IPU_DISPB_DAT_15,
+        MX35_PAD_LD16__IPU_DISPB_DAT_16,
+        MX35_PAD_LD17__IPU_DISPB_DAT_17,
+        MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+        MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+        MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+        MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
+        /* CSI */
+        MX35_PAD_TX1__IPU_CSI_D_6,
+        MX35_PAD_TX0__IPU_CSI_D_7,
+        MX35_PAD_CSI_D8__IPU_CSI_D_8,
+        MX35_PAD_CSI_D9__IPU_CSI_D_9,
+        MX35_PAD_CSI_D10__IPU_CSI_D_10,
+        MX35_PAD_CSI_D11__IPU_CSI_D_11,
+        MX35_PAD_CSI_D12__IPU_CSI_D_12,
+        MX35_PAD_CSI_D13__IPU_CSI_D_13,
+        MX35_PAD_CSI_D14__IPU_CSI_D_14,
+        MX35_PAD_CSI_D15__IPU_CSI_D_15,
+        MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
+        MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
+        MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
+        MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
+};
+
+/*
+ * Camera support
+*/
+static phys_addr_t mx3_camera_base __initdata;
+#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
+
+static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
+        .flags = MX3_CAMERA_DATAWIDTH_8,
+        .mclk_10khz = 2000,
+};
+
+static int __init imx35_3ds_init_camera(void)
+{
+        int dma, ret = -ENOMEM;
+        struct platform_device *pdev =
+                imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
+
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        if (!mx3_camera_base)
+                goto err;
+
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                        mx3_camera_base, mx3_camera_base,
+                                        MX35_3DS_CAMERA_BUF_SIZE,
+                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+
+        if (!(dma & DMA_MEMORY_MAP))
+                goto err;
+
+        ret = platform_device_add(pdev);
+        if (ret)
+err:
+                platform_device_put(pdev);
+
+        return ret;
+}
+
+static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct i2c_board_info mx35_3ds_i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id         = 0,
+        .board_info     = &mx35_3ds_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power          = NULL,
+};
+
+static struct platform_device mx35_3ds_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +374,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+        struct platform_device *imx35_fb_pdev;
+
         imx35_soc_init();
 
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +401,17 @@ static void __init mx35_3ds_init(void)
                 pr_warn("Init of the debugboard failed, all "
                                 "devices on the debugboard are unusable.\n");
         imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+
+        i2c_register_board_info(
+                0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
+
+        imx35_add_ipu_core(&mx35_3ds_ipu_data);
+        platform_device_register(&mx35_3ds_ov2640);
+        imx35_3ds_init_camera();
+
+        imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+        mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
+        platform_device_register(&mx35_3ds_lcd);
 }
 
 static void __init mx35pdk_timer_init(void)
@@ -215,6 +423,13 @@ struct sys_timer mx35pdk_timer = {
         .init   = mx35pdk_timer_init,
 };
 
+static void __init mx35_3ds_reserve(void)
+{
+        /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
+        mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
+                                         MX35_3DS_CAMERA_BUF_SIZE);
+}
+
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         /* Maintainer: Freescale Semiconductor, Inc */
         .atag_offset = 0x100,
@@ -224,5 +439,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         .handle_irq = imx35_handle_irq,
         .timer = &mx35pdk_timer,
         .init_machine = mx35_3ds_init,
+        .reserve = mx35_3ds_reserve,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 16f126da9f8..2f3debe2a11 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -233,7 +233,7 @@ static struct regulator_init_data sdhc1_data = {
 
 static struct regulator_consumer_supply cam_consumers[] = {
         {
-                .dev    = NULL,
+                .dev_name = NULL,
                 .supply = "imx_cam_vcc",
         },
 };
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 2530c151b7b..f8ca96c354f 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -34,31 +34,31 @@ static void imx3_idle(void)
 {
         unsigned long reg = 0;
 
-        if (!need_resched())
-                __asm__ __volatile__(
-                        /* disable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "bic %0, %0, #0x00001000\n"
-                        "bic %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        /* invalidate I cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c5, 0\n"
-                        /* clear and invalidate D cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c14, 0\n"
-                        /* WFI */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c0, 4\n"
-                        "nop\n" "nop\n" "nop\n" "nop\n"
-                        "nop\n" "nop\n" "nop\n"
-                        /* enable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "orr %0, %0, #0x00001000\n"
-                        "orr %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        : "=r" (reg));
-        local_irq_enable();
+        mx3_cpu_lp_set(MX3_WAIT);
+
+        __asm__ __volatile__(
+                /* disable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "bic %0, %0, #0x00001000\n"
+                "bic %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                /* invalidate I cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c5, 0\n"
+                /* clear and invalidate D cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c14, 0\n"
+                /* WFI */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c0, 4\n"
+                "nop\n" "nop\n" "nop\n" "nop\n"
+                "nop\n" "nop\n" "nop\n"
+                /* enable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "orr %0, %0, #0x00001000\n"
+                "orr %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                : "=r" (reg));
 }
 
 static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -78,7 +78,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
         return __arm_ioremap(phys_addr, size, mtype);
 }
 
-void imx3_init_l2x0(void)
+void __init imx3_init_l2x0(void)
 {
         void __iomem *l2x0_base;
         void __iomem *clkctl_base;
@@ -134,8 +134,8 @@ void __init imx31_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX31);
         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-        pm_idle = imx3_idle;
         imx_ioremap = imx3_ioremap;
+        arm_pm_idle = imx3_idle;
 }
 
 void __init mx31_init_irq(void)
@@ -179,6 +179,10 @@ void __init imx31_soc_init(void)
         }
 
         imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+
+        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
+        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
+
         platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
                                         ARRAY_SIZE(imx31_audmux_res));
 }
@@ -203,7 +207,7 @@ void __init imx35_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX35);
         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-        pm_idle = imx3_idle;
+        arm_pm_idle = imx3_idle;
         imx_ioremap = imx3_ioremap;
 }
 
@@ -269,6 +273,11 @@ void __init imx35_soc_init(void)
         }
 
         imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+
+        /* Setup AIPS registers */
+        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
+        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
+
         /* i.mx35 has the i.mx31 type audmux */
         platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
                                         ARRAY_SIZE(imx35_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 90d7880bb37..51af9fa5694 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -26,23 +26,17 @@ static struct clk *gpc_dvfs_clk;
 
 static void imx5_idle(void)
 {
-        if (!need_resched()) {
-                /* gpc clock is needed for SRPG */
-                if (gpc_dvfs_clk == NULL) {
-                        gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-                        if (IS_ERR(gpc_dvfs_clk))
-                                goto err0;
-                }
-                clk_enable(gpc_dvfs_clk);
-                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-                if (tzic_enable_wake())
-                        goto err1;
-                cpu_do_idle();
-err1:
-                clk_disable(gpc_dvfs_clk);
+        /* gpc clock is needed for SRPG */
+        if (gpc_dvfs_clk == NULL) {
+                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+                if (IS_ERR(gpc_dvfs_clk))
+                        return;
         }
-err0:
-        local_irq_enable();
+        clk_enable(gpc_dvfs_clk);
+        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+        if (tzic_enable_wake() != 0)
+                cpu_do_idle();
+        clk_disable(gpc_dvfs_clk);
 }
 
 /*
@@ -108,7 +102,7 @@ void __init imx51_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        pm_idle = imx5_idle;
+        arm_pm_idle = imx5_idle;
 }
 
 void __init imx53_init_early(void)
@@ -207,6 +201,11 @@ void __init imx51_soc_init(void)
 
         /* i.mx51 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+
+        /* Setup AIPS registers */
+        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
+        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
+
         /* i.mx51 has the i.mx31 type audmux */
         platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
                                         ARRAY_SIZE(imx51_audmux_res));
@@ -225,6 +224,11 @@ void __init imx53_soc_init(void)
 
         /* i.mx53 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+
+        /* Setup AIPS registers */
+        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
+        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
+
         /* i.mx53 has the i.mx31 type audmux */
         platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
                                         ARRAY_SIZE(imx53_audmux_res));
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index e455d2f855b..6fcffa7db97 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -10,7 +10,6 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/io.h>
-#include <mach/system.h>
 #include <mach/hardware.h>
 
 static int mx27_suspend_enter(suspend_state_t state)
@@ -23,7 +22,7 @@ static int mx27_suspend_enter(suspend_state_t state)
                 cscr &= 0xFFFFFFFC;
                 __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
                 /* Executes WFI */
-                arch_idle();
+                cpu_do_idle();
                 break;
 
         default:
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
new file mode 100644
index 00000000000..b3752439632
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/io.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include "crmregs-imx3.h"
+
+/*
+ * Set cpu low power mode before WFI instruction. This function is called
+ * mx3 because it can be used for mx31 and mx35.
+ * Currently only WAIT_MODE is supported.
+ */
+void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
+{
+        int reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_LPM_MASK;
+
+        switch (mode) {
+        case MX3_WAIT:
+                if (cpu_is_mx35())
+                        reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
+                __raw_writel(reg, MXC_CCM_CCMR);
+                break;
+        default:
+                pr_err("Unknown cpu power mode: %d\n", mode);
+                return;
+        }
+}
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 6dc09344805..e26a9cb05ed 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -89,7 +89,7 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 
 static int mx5_suspend_prepare(void)
 {
-        return clk_enable(gpc_dvfs_clk);
+        return clk_prepare_enable(gpc_dvfs_clk);
 }
 
 static int mx5_suspend_enter(suspend_state_t state)
@@ -119,7 +119,7 @@ static int mx5_suspend_enter(suspend_state_t state)
 
 static void mx5_suspend_finish(void)
 {
-        clk_disable(gpc_dvfs_clk);
+        clk_disable_unprepare(gpc_dvfs_clk);
 }
 
 static int mx5_pm_valid(suspend_state_t state)
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index d2fd9f33e6f..1a65d77bd55 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -34,67 +34,23 @@
 
 static struct amba_pl010_data integrator_uart_data;
 
-static struct amba_device rtc_device = {
-        .dev            = {
-                .init_name = "mb:15",
-        },
-        .res            = {
-                .start  = INTEGRATOR_RTC_BASE,
-                .end    = INTEGRATOR_RTC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_RTCINT, NO_IRQ },
-};
+#define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
+#define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
+#define INTEGRATOR_UART1_IRQ    { IRQ_UARTINT1 }
+#define KMI0_IRQ                { IRQ_KMIINT0 }
+#define KMI1_IRQ                { IRQ_KMIINT1 }
 
-static struct amba_device uart0_device = {
-        .dev            = {
-                .init_name = "mb:16",
-                .platform_data = &integrator_uart_data,
-        },
-        .res            = {
-                .start  = INTEGRATOR_UART0_BASE,
-                .end    = INTEGRATOR_UART0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_UARTINT0, NO_IRQ },
-};
+static AMBA_APB_DEVICE(rtc, "mb:15", 0,
+        INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
 
-static struct amba_device uart1_device = {
-        .dev            = {
-                .init_name = "mb:17",
-                .platform_data = &integrator_uart_data,
-        },
-        .res            = {
-                .start  = INTEGRATOR_UART1_BASE,
-                .end    = INTEGRATOR_UART1_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_UARTINT1, NO_IRQ },
-};
+static AMBA_APB_DEVICE(uart0, "mb:16", 0,
+        INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
 
-static struct amba_device kmi0_device = {
-        .dev            = {
-                .init_name = "mb:18",
-        },
-        .res            = {
-                .start  = KMI0_BASE,
-                .end    = KMI0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_KMIINT0, NO_IRQ },
-};
+static AMBA_APB_DEVICE(uart1, "mb:17", 0,
+        INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
 
-static struct amba_device kmi1_device = {
-        .dev            = {
-                .init_name = "mb:19",
-        },
-        .res            = {
-                .start  = KMI1_BASE,
-                .end    = KMI1_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_KMIINT1, NO_IRQ },
-};
+static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
+static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &rtc_device,
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 8cbb75a96bd..3e538da6cb1 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -401,24 +401,21 @@ static int impd1_probe(struct lm_device *dev)
 
                 pc_base = dev->resource.start + idev->offset;
 
-                d = kzalloc(sizeof(struct amba_device), GFP_KERNEL);
+                d = amba_device_alloc(NULL, pc_base, SZ_4K);
                 if (!d)
                         continue;
 
                 dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
                 d->dev.parent   = &dev->dev;
-                d->res.start    = dev->resource.start + idev->offset;
-                d->res.end      = d->res.start + SZ_4K - 1;
-                d->res.flags    = IORESOURCE_MEM;
                 d->irq[0]       = dev->irq;
                 d->irq[1]       = dev->irq;
                 d->periphid     = idev->id;
                 d->dev.platform_data = idev->platform_data;
 
-                ret = amba_device_register(d, &dev->resource);
+                ret = amba_device_add(d, &dev->resource);
                 if (ret) {
                         dev_err(&d->dev, "unable to register device: %d\n", ret);
-                        kfree(d);
+                        amba_device_put(d);
                 }
         }
 
diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S
index 3d029c9f3ef..5cc7b85ad9d 100644
--- a/arch/arm/mach-integrator/include/mach/entry-macro.S
+++ b/arch/arm/mach-integrator/include/mach/entry-macro.S
@@ -11,15 +11,9 @@
 #include <mach/platform.h>
 #include <mach/irqs.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 /* FIXME: should not be using soo many LDRs here */
                 ldr     \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h
deleted file mode 100644
index 901514eba4a..00000000000
--- a/arch/arm/mach-integrator/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/system.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a8b6aa6003f..be9ead4a3bc 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -347,32 +347,14 @@ static struct mmci_platform_data mmc_data = {
         .gpio_cd        = -1,
 };
 
-static struct amba_device mmc_device = {
-        .dev            = {
-                .init_name = "mb:1c",
-                .platform_data = &mmc_data,
-        },
-        .res            = {
-                .start  = INTEGRATOR_CP_MMC_BASE,
-                .end    = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
-        .periphid       = 0,
-};
+#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
+#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
 
-static struct amba_device aaci_device = {
-        .dev            = {
-                .init_name = "mb:1d",
-        },
-        .res            = {
-                .start  = INTEGRATOR_CP_AACI_BASE,
-                .end    = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_CP_AACIINT, NO_IRQ },
-        .periphid       = 0,
-};
+static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE,
+        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
+
+static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE,
+        INTEGRATOR_CP_AACI_IRQS, NULL);
 
 
 /*
@@ -425,21 +407,8 @@ static struct clcd_board clcd_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-static struct amba_device clcd_device = {
-        .dev            = {
-                .init_name = "mb:c0",
-                .coherent_dma_mask = ~0,
-                .platform_data = &clcd_data,
-        },
-        .res            = {
-                .start  = INTCP_PA_CLCD_BASE,
-                .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .dma_mask       = ~0,
-        .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
-        .periphid       = 0,
-};
+static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE,
+        { IRQ_CP_CLCDCINT }, &clcd_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &mmc_device,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 9d47b4c6762..4be172c3cbe 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -377,9 +377,10 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
          * the mem resource for this bus
          * the prefetch mem resource for this bus
          */
-        pci_add_resource(&sys->resources, &ioport_resource);
-        pci_add_resource(&sys->resources, &non_mem);
-        pci_add_resource(&sys->resources, &pre_mem);
+        pci_add_resource_offset(&sys->resources,
+                                &ioport_resource, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/entry-macro.S b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
index a624a7870c6..1a2d603488d 100644
--- a/arch/arm/mach-iop13xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
@@ -16,9 +16,6 @@
  * Place - Suite 330, Boston, MA 02111-1307 USA.
  *
  */
-        .macro  disable_fiq
-        .endm
-
         .macro get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c15, c1, 0
         orr     \tmp, \tmp, #(1 << 6)
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h
deleted file mode 100644
index 1f31ed3f8ae..00000000000
--- a/arch/arm/mach-iop13xx/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-iop13xx/include/mach/system.h
- *
- *  Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index b8f5a873651..861cb12ef43 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -1084,8 +1084,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
         request_resource(&ioport_resource, &res[0]);
         request_resource(&iomem_resource, &res[1]);
 
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-iop32x/include/mach/entry-macro.S b/arch/arm/mach-iop32x/include/mach/entry-macro.S
index b02fb56bafc..ea13ae02d9b 100644
--- a/arch/arm/mach-iop32x/include/mach/entry-macro.S
+++ b/arch/arm/mach-iop32x/include/mach/entry-macro.S
@@ -9,9 +9,6 @@
  */
 #include <mach/iop32x.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c15, c1, 0
         orr     \tmp, \tmp, #(1 << 6)
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
deleted file mode 100644
index 4a88727bca9..00000000000
--- a/arch/arm/mach-iop32x/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/system.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-iop33x/include/mach/entry-macro.S b/arch/arm/mach-iop33x/include/mach/entry-macro.S
index 4e1f7282b35..0a398fe1fba 100644
--- a/arch/arm/mach-iop33x/include/mach/entry-macro.S
+++ b/arch/arm/mach-iop33x/include/mach/entry-macro.S
@@ -9,9 +9,6 @@
  */
 #include <mach/iop33x.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c15, c1, 0
         orr     \tmp, \tmp, #(1 << 6)
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
deleted file mode 100644
index 4f98e765397..00000000000
--- a/arch/arm/mach-iop33x/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/system.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
index 5850ffc8c75..c4444dff920 100644
--- a/arch/arm/mach-ixp2000/include/mach/entry-macro.S
+++ b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
@@ -9,15 +9,9 @@
  */
 #include <mach/irqs.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \irqnr, #0x0              @clear out irqnr as default
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
deleted file mode 100644
index a7fb08b2b8e..00000000000
--- a/arch/arm/mach-ixp2000/include/mach/system.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/system.h
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyricht (C) 2003-2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index 558f5f81f02..915ad49e3b8 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -133,11 +133,11 @@ static void ixdp2400_pci_postinit(void)
 
         if (ixdp2x00_master_npu()) {
                 dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN);
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
         } else {
                 dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN);
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
 
                 ixdp2x00_slave_pci_postinit();
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 33c6d5f3fda..a9f1819ea04 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -261,14 +261,14 @@ int __init ixdp2800_pci_init(void)
                 pci_common_init(&ixdp2800_pci);
                 if (ixdp2x00_master_npu()) {
                         dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
-                        pci_remove_bus_device(dev);
+                        pci_stop_and_remove_bus_device(dev);
                         pci_dev_put(dev);
 
                         ixdp2800_master_enable_slave();
                         ixdp2800_master_wait_for_slave_bus_scan();
                 } else {
                         dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN);
-                        pci_remove_bus_device(dev);
+                        pci_stop_and_remove_bus_device(dev);
                         pci_dev_put(dev);
                 }
         }
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 910426a6ffd..421e38dc0fa 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -238,12 +238,12 @@ void ixdp2x00_slave_pci_postinit(void)
          * Remove PMC device is there is one
          */
         if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) {
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
         }
 
         dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN);
-        pci_remove_bus_device(dev);
+        pci_stop_and_remove_bus_device(dev);
         pci_dev_put(dev);
 }
 
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 7e9a1f31a83..9c02de932fa 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -242,8 +242,10 @@ int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
         if (nr >= 1)
                 return 0;
 
-        pci_add_resource(&sys->resources, &ixp2000_pci_io_space);
-        pci_add_resource(&sys->resources, &ixp2000_pci_mem_space);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp2000_pci_io_space, sys->io_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp2000_pci_mem_space, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index ccdec42af70..d2c2dc35cbd 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -440,6 +440,9 @@ static struct platform_device *ixp23xx_devices[] __initdata = {
 
 void __init ixp23xx_sys_init(void)
 {
+        /* by default, the idle code is disabled */
+        disable_hlt();
+
         *IXP23XX_EXP_UNIT_FUSE |= 0xf;
         platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
 }
diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
index 3f5338a7bbd..3fd2cb984e4 100644
--- a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
@@ -2,15 +2,9 @@
  * arch/arm/mach-ixp23xx/include/mach/entry-macro.S
  */
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
                 ldr     \irqnr, [\irqnr]        @ get interrupt number
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h
deleted file mode 100644
index 277dda7334b..00000000000
--- a/arch/arm/mach-ixp23xx/include/mach/system.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/system.h
- *
- * Copyright (C) 2003 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-#if 0
-        if (!hlt_counter)
-                cpu_do_idle();
-#endif
-}
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index bdf2866a02a..911f5a58e00 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -280,8 +280,10 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
         if (nr >= 1)
                 return 0;
 
-        pci_add_resource(&sys->resources, &ixp23xx_pci_io_space);
-        pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp23xx_pci_io_space, sys->io_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp23xx_pci_mem_space, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 0f445d3f0fa..d5719eb4259 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -471,8 +471,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
         request_resource(&ioport_resource, &res[0]);
         request_resource(&iomem_resource, &res[1]);
 
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         platform_notify = ixp4xx_pci_platform_notify;
         platform_notify_remove = ixp4xx_pci_platform_notify_remove;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 3841ab4146b..a6329a0a8ec 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -236,6 +236,12 @@ void __init ixp4xx_init_irq(void)
 {
         int i = 0;
 
+        /*
+         * ixp4xx does not implement the XScale PWRMODE register
+         * so it must not call cpu_do_idle().
+         */
+        disable_hlt();
+
         /* Route all sources to IRQ instead of FIQ */
         *IXP4XX_ICLR = 0x0;
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
index f2e14e94ed1..79adf83e2c3 100644
--- a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
@@ -9,15 +9,9 @@
  */
 #include <mach/hardware.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
                 ldr     \irqstat, [\irqstat]            @ get interrupts
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
deleted file mode 100644
index 140a9bef446..00000000000
--- a/arch/arm/mach-ixp4xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/system.h
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-static inline void arch_idle(void)
-{
-        /* ixp4xx does not implement the XScale PWRMODE register,
-         * so it must not call cpu_do_idle() here.
-         */
-#if 0
-        cpu_do_idle();
-#endif
-}
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7fc603b4689..90ceab76192 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -44,6 +44,20 @@ config MACH_GURUPLUG
           Say 'Y' here if you want your kernel to support the
           Marvell GuruPlug Reference Board.
 
+config ARCH_KIRKWOOD_DT
+        bool "Marvell Kirkwood Flattened Device Tree"
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Kirkwood using flattened device tree.
+
+config MACH_DREAMPLUG_DT
+        bool "Marvell DreamPlug (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DreamPlug (Flattened Device Tree).
+
 config MACH_TS219
         bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 5dcaa81a2ec..e299a9576bf 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -20,3 +20,5 @@ obj-$(CONFIG_MACH_NET5BIG_V2)		+= netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
+obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
+obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 760a0efe758..16f93852230 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -1,3 +1,5 @@
    zreladdr-y   += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
new file mode 100644
index 00000000000..985453994dd
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-dreamplug.c
+ *
+ * Marvell DreamPlug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+struct mtd_partition dreamplug_partitions[] = {
+        {
+                .name   = "u-boot",
+                .size   = SZ_512K,
+                .offset = 0,
+        },
+        {
+                .name   = "u-boot env",
+                .size   = SZ_64K,
+                .offset = SZ_512K + SZ_512K,
+        },
+        {
+                .name   = "dtb",
+                .size   = SZ_64K,
+                .offset = SZ_512K + SZ_512K + SZ_512K,
+        },
+};
+
+static const struct flash_platform_data dreamplug_spi_slave_data = {
+        .type           = "mx25l1606e",
+        .name           = "spi_flash",
+        .parts          = dreamplug_partitions,
+        .nr_parts       = ARRAY_SIZE(dreamplug_partitions),
+};
+
+static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &dreamplug_spi_slave_data,
+                .irq            = -1,
+                .max_speed_hz   = 50000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
+};
+
+static struct mv_sata_platform_data dreamplug_sata_data = {
+        .n_ports        = 1,
+};
+
+static struct mvsdio_platform_data dreamplug_mvsdio_data = {
+        /* unfortunately the CD signal has not been connected */
+};
+
+static struct gpio_led dreamplug_led_pins[] = {
+        {
+                .name                   = "dreamplug:blue:bluetooth",
+                .gpio                   = 47,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "dreamplug:green:wifi",
+                .gpio                   = 48,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "dreamplug:green:wifi_ap",
+                .gpio                   = 49,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data dreamplug_led_data = {
+        .leds           = dreamplug_led_pins,
+        .num_leds       = ARRAY_SIZE(dreamplug_led_pins),
+};
+
+static struct platform_device dreamplug_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &dreamplug_led_data,
+        }
+};
+
+static unsigned int dreamplug_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP47_GPIO,     /* Bluetooth LED */
+        MPP48_GPIO,     /* Wifi LED */
+        MPP49_GPIO,     /* Wifi AP LED */
+        0
+};
+
+void __init dreamplug_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(dreamplug_mpp_config);
+
+        spi_register_board_info(dreamplug_spi_slave_info,
+                                ARRAY_SIZE(dreamplug_spi_slave_info));
+        kirkwood_spi_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&dreamplug_ge00_data);
+        kirkwood_ge01_init(&dreamplug_ge01_data);
+        kirkwood_sata_init(&dreamplug_sata_data);
+        kirkwood_sdio_init(&dreamplug_mvsdio_data);
+
+        platform_device_register(&dreamplug_leds);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
new file mode 100644
index 00000000000..1c672d9e665
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-dt.c
+ *
+ * Flattened Device Tree board initialization
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+
+static struct of_device_id kirkwood_dt_match_table[] __initdata = {
+        { .compatible = "simple-bus", },
+        { }
+};
+
+static void __init kirkwood_dt_init(void)
+{
+        pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
+
+        /*
+         * Disable propagation of mbus errors to the CPU local bus,
+         * as this causes mbus errors (which can occur for example
+         * for PCI aborts) to throw CPU aborts, which we're not set
+         * up to deal with.
+         */
+        writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
+
+        kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        kirkwood_l2_init();
+#endif
+
+        /* internal devices that every board has */
+        kirkwood_wdt_init();
+        kirkwood_xor0_init();
+        kirkwood_xor1_init();
+        kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC
+        kexec_reinit = kirkwood_enable_pcie;
+#endif
+
+        if (of_machine_is_compatible("globalscale,dreamplug"))
+                dreamplug_init();
+
+        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+}
+
+static const char *kirkwood_dt_board_compat[] = {
+        "globalscale,dreamplug",
+        NULL
+};
+
+DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
+        /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
+        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+        .init_machine   = kirkwood_dt_init,
+        .restart        = kirkwood_restart,
+        .dt_compat      = kirkwood_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 77d4852e19f..a02cae881f2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -279,7 +279,7 @@ void __init kirkwood_crypto_init(void)
 /*****************************************************************************
  * XOR0
  ****************************************************************************/
-static void __init kirkwood_xor0_init(void)
+void __init kirkwood_xor0_init(void)
 {
         kirkwood_clk_ctrl |= CGC_XOR0;
 
@@ -291,7 +291,7 @@ static void __init kirkwood_xor0_init(void)
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static void __init kirkwood_xor1_init(void)
+void __init kirkwood_xor1_init(void)
 {
         kirkwood_clk_ctrl |= CGC_XOR1;
 
@@ -303,7 +303,7 @@ static void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static void __init kirkwood_wdt_init(void)
+void __init kirkwood_wdt_init(void)
 {
         orion_wdt_init(kirkwood_tclk);
 }
@@ -392,7 +392,7 @@ void __init kirkwood_audio_init(void)
 /*
  * Identify device ID and revision.
  */
-static char * __init kirkwood_id(void)
+char * __init kirkwood_id(void)
 {
         u32 dev, rev;
 
@@ -435,7 +435,7 @@ static char * __init kirkwood_id(void)
         }
 }
 
-static void __init kirkwood_l2_init(void)
+void __init kirkwood_l2_init(void)
 {
 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
         writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
@@ -450,7 +450,6 @@ void __init kirkwood_init(void)
 {
         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
                 kirkwood_id(), kirkwood_tclk);
-        kirkwood_i2s_data.tclk = kirkwood_tclk;
 
         /*
          * Disable propagation of mbus errors to the CPU local bus,
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 9071a397136..fa8e7689c43 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,21 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 
+/* board init functions for boards not fully converted to fdt */
+#ifdef CONFIG_MACH_DREAMPLUG_DT
+void dreamplug_init(void);
+#else
+static inline void dreamplug_init(void) {};
+#endif
+
+/* early init functions not converted to fdt yet */
+char *kirkwood_id(void);
+void kirkwood_l2_init(void);
+void kirkwood_wdt_init(void);
+void kirkwood_xor0_init(void);
+void kirkwood_xor1_init(void);
+void kirkwood_crypto_init(void);
+
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
diff --git a/arch/arm/mach-kirkwood/include/mach/entry-macro.S b/arch/arm/mach-kirkwood/include/mach/entry-macro.S
index 8939d36f893..82db29f7af8 100644
--- a/arch/arm/mach-kirkwood/include/mach/entry-macro.S
+++ b/arch/arm/mach-kirkwood/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IRQ_VIRT_BASE
         .endm
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h
deleted file mode 100644
index 5fddde002b5..00000000000
--- a/arch/arm/mach-kirkwood/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index a066a6d8d9d..f56a0118c1b 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -198,9 +198,9 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
         if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe%d Memory resource failed\n", index);
 
-        pci_add_resource(&sys->resources, &pp->res[0]);
-        pci_add_resource(&sys->resources, &pp->res[1]);
         sys->io_offset = 0;
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         /*
          * Generic PCIe unit setup.
diff --git a/arch/arm/mach-ks8695/include/mach/entry-macro.S b/arch/arm/mach-ks8695/include/mach/entry-macro.S
index b4fe0c11c6c..8315b34f32f 100644
--- a/arch/arm/mach-ks8695/include/mach/entry-macro.S
+++ b/arch/arm/mach-ks8695/include/mach/entry-macro.S
@@ -14,16 +14,10 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
                 ldr     \base, =KS8695_IRQ_VA                   @ Base address of interrupt controller
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, [\base, #KS8695_INTMS]        @ Mask Status register
 
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
deleted file mode 100644
index 59fe992395b..00000000000
--- a/arch/arm/mach-ks8695/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-s3c2410/include/mach/system.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * KS8695 - System function defines and includes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks,
-         */
-        cpu_do_idle();
-
-}
-
-#endif
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index b26f992071d..acc70143581 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -169,8 +169,8 @@ static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys)
         request_resource(&iomem_resource, &pci_mem);
         request_resource(&ioport_resource, &pci_io);
 
-        pci_add_resource(&sys->resources, &pci_io);
-        pci_add_resource(&sys->resources, &pci_mem);
+        pci_add_resource_offset(&sys->resources, &pci_io, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pci_mem, sys->mem_offset);
 
         /* Assign and enable processor bridge */
         ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA);
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index fde66350869..75946ac89ee 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -29,5 +29,30 @@ config ARCH_LPC32XX_UART6_SELECT
 
 endmenu
 
+menu "LPC32XX chip components"
+
+config ARCH_LPC32XX_IRAM_FOR_NET
+        bool "Use IRAM for network buffers"
+        default y
+        help
+          Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
+          network buffer.  If the total combined required buffer sizes is
+          larger than the size of IRAM, then SDRAM will be used instead.
+
+          This can be enabled safely if the IRAM is not intended for other
+          uses.
+
+config ARCH_LPC32XX_MII_SUPPORT
+        bool "Check to enable MII support or leave disabled for RMII support"
+        help
+          Say Y here to enable MII support, or N for RMII support. Regardless of
+          which support is selected, the ethernet interface driver needs to be
+          selected in the device driver networking section.
+
+          The PHY3250 reference board uses RMII, so users of this board should
+          say N.
+
+endmenu
+
 endif
 
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 1e027514096..b7ef51119d3 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -82,10 +82,12 @@
  *   will also impact the individual peripheral rates.
  */
 
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/device.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/amba/bus.h>
@@ -97,9 +99,12 @@
 #include "clock.h"
 #include "common.h"
 
+static DEFINE_SPINLOCK(global_clkregs_lock);
+
+static int usb_pll_enable, usb_pll_valid;
+
 static struct clk clk_armpll;
 static struct clk clk_usbpll;
-static DEFINE_MUTEX(clkm_lock);
 
 /*
  * Post divider values for PLLs based on selected register value
@@ -127,7 +132,7 @@ static struct clk osc_32KHz = {
 static int local_pll397_enable(struct clk *clk, int enable)
 {
         u32 reg;
-        unsigned long timeout = 1 + msecs_to_jiffies(10);
+        unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
         reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
 
@@ -142,7 +147,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
                 /* Wait for PLL397 lock */
                 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
-                        (timeout > jiffies))
+                        time_before(jiffies, timeout))
                         cpu_relax();
 
                 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
@@ -156,7 +161,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
 static int local_oscmain_enable(struct clk *clk, int enable)
 {
         u32 reg;
-        unsigned long timeout = 1 + msecs_to_jiffies(10);
+        unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
         reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 
@@ -171,7 +176,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
                 /* Wait for main oscillator to start */
                 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
-                        (timeout > jiffies))
+                        time_before(jiffies, timeout))
                         cpu_relax();
 
                 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
@@ -382,30 +387,62 @@ static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
 static int local_usbpll_enable(struct clk *clk, int enable)
 {
         u32 reg;
-        int ret = -ENODEV;
-        unsigned long timeout = 1 + msecs_to_jiffies(10);
+        int ret = 0;
+        unsigned long timeout = jiffies + msecs_to_jiffies(20);
 
         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 
-        if (enable == 0) {
-                reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
-                        LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
-                __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
-        } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
+        __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
+                LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
+                LPC32XX_CLKPWR_USB_CTRL);
+        __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
+                LPC32XX_CLKPWR_USB_CTRL);
+
+        if (enable && usb_pll_valid && usb_pll_enable) {
+                ret = -ENODEV;
+                /*
+                 * If the PLL rate has been previously set, then the rate
+                 * in the PLL register is valid and can be enabled here.
+                 * Otherwise, it needs to be enabled as part of setrate.
+                 */
+
+                /*
+                 * Gate clock into PLL
+                 */
                 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 
-                /* Wait for PLL lock */
-                while ((timeout > jiffies) & (ret == -ENODEV)) {
+                /*
+                 * Enable PLL
+                 */
+                reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
+                __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+                /*
+                 * Wait for PLL to lock
+                 */
+                while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
                         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
                         if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
                                 ret = 0;
+                        else
+                                udelay(10);
                 }
 
+                /*
+                 * Gate clock from PLL if PLL is locked
+                 */
                 if (ret == 0) {
-                        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
-                        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+                        __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
+                                LPC32XX_CLKPWR_USB_CTRL);
+                } else {
+                        __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
+                                LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
+                                LPC32XX_CLKPWR_USB_CTRL);
                 }
+        } else if ((enable == 0) && usb_pll_valid  && usb_pll_enable) {
+                usb_pll_valid = 0;
+                usb_pll_enable = 0;
         }
 
         return ret;
@@ -423,7 +460,7 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
          */
         rate = rate * 1000;
 
-        clkin = clk->parent->rate;
+        clkin = clk->get_rate(clk);
         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
         clkin = clkin / usbdiv;
@@ -437,7 +474,8 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
 
 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
 {
-        u32 clkin, reg, usbdiv;
+        int ret = -ENODEV;
+        u32 clkin, usbdiv;
         struct clk_pll_setup pllsetup;
 
         /*
@@ -446,7 +484,7 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
          */
         rate = rate * 1000;
 
-        clkin = clk->get_rate(clk);
+        clkin = clk->get_rate(clk->parent);
         usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
                 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
         clkin = clkin / usbdiv;
@@ -455,22 +493,25 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
         if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
                 return -EINVAL;
 
+        /*
+         * Disable PLL clocks during PLL change
+         */
         local_usbpll_enable(clk, 0);
-
-        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
-        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
-        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
-
-        pllsetup.analog_on = 1;
+        pllsetup.analog_on = 0;
         local_clk_usbpll_setup(&pllsetup);
 
-        clk->rate = clk_check_pll_setup(clkin, &pllsetup);
+        /*
+         * Start USB PLL and check PLL status
+         */
+
+        usb_pll_valid = 1;
+        usb_pll_enable = 1;
 
-        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
-        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
-        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+        ret = local_usbpll_enable(clk, 1);
+        if (ret >= 0)
+                clk->rate = clk_check_pll_setup(clkin, &pllsetup);
 
-        return 0;
+        return ret;
 }
 
 static struct clk clk_usbpll = {
@@ -719,6 +760,41 @@ static struct clk clk_tsc = {
         .get_rate       = local_return_parent_rate,
 };
 
+static int adc_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+        u32 divider;
+
+        /* Use PERIPH_CLOCK */
+        tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+        tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+        /*
+         * Set clock divider so that we have equal to or less than
+         * 4.5MHz clock at ADC
+         */
+        divider = clk->get_rate(clk) / 4500000 + 1;
+        tmp |= divider;
+        __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+
+        /* synchronize rate of this clock w/ actual HW setting */
+        clk->rate = clk->get_rate(clk->parent) / divider;
+
+        if (enable == 0)
+                __raw_writel(0, clk->enable_reg);
+        else
+                __raw_writel(clk->enable_mask, clk->enable_reg);
+
+        return 0;
+}
+
+static struct clk clk_adc = {
+        .parent         = &clk_pclk,
+        .enable         = adc_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
 static int mmc_onoff_enable(struct clk *clk, int enable)
 {
         u32 tmp;
@@ -891,20 +967,8 @@ static struct clk clk_lcd = {
         .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 };
 
-static inline void clk_lock(void)
-{
-        mutex_lock(&clkm_lock);
-}
-
-static inline void clk_unlock(void)
-{
-        mutex_unlock(&clkm_lock);
-}
-
 static void local_clk_disable(struct clk *clk)
 {
-        WARN_ON(clk->usecount == 0);
-
         /* Don't attempt to disable clock if it has no users */
         if (clk->usecount > 0) {
                 clk->usecount--;
@@ -947,10 +1011,11 @@ static int local_clk_enable(struct clk *clk)
 int clk_enable(struct clk *clk)
 {
         int ret;
+        unsigned long flags;
 
-        clk_lock();
+        spin_lock_irqsave(&global_clkregs_lock, flags);
         ret = local_clk_enable(clk);
-        clk_unlock();
+        spin_unlock_irqrestore(&global_clkregs_lock, flags);
 
         return ret;
 }
@@ -961,9 +1026,11 @@ EXPORT_SYMBOL(clk_enable);
  */
 void clk_disable(struct clk *clk)
 {
-        clk_lock();
+        unsigned long flags;
+
+        spin_lock_irqsave(&global_clkregs_lock, flags);
         local_clk_disable(clk);
-        clk_unlock();
+        spin_unlock_irqrestore(&global_clkregs_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
@@ -972,13 +1039,7 @@ EXPORT_SYMBOL(clk_disable);
  */
 unsigned long clk_get_rate(struct clk *clk)
 {
-        unsigned long rate;
-
-        clk_lock();
-        rate = clk->get_rate(clk);
-        clk_unlock();
-
-        return rate;
+        return clk->get_rate(clk);
 }
 EXPORT_SYMBOL(clk_get_rate);
 
@@ -994,11 +1055,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
          * the actual rate set as part of the peripheral dividers
          * instead of high level clock control
          */
-        if (clk->set_rate) {
-                clk_lock();
+        if (clk->set_rate)
                 ret = clk->set_rate(clk, rate);
-                clk_unlock();
-        }
 
         return ret;
 }
@@ -1009,15 +1067,11 @@ EXPORT_SYMBOL(clk_set_rate);
  */
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        clk_lock();
-
         if (clk->round_rate)
                 rate = clk->round_rate(clk, rate);
         else
                 rate = clk->get_rate(clk);
 
-        clk_unlock();
-
         return rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
@@ -1075,10 +1129,11 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
         _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
         _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
-        _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
-        _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
+        _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
+        _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
+        _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
         _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
-        _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
+        _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
         _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
         _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
         _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 369b152896c..bbbf063a74c 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -138,6 +138,75 @@ struct platform_device lpc32xx_rtc_device = {
 };
 
 /*
+ * ADC support
+ */
+static struct resource adc_resources[] = {
+        {
+                .start = LPC32XX_ADC_BASE,
+                .end = LPC32XX_ADC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = IRQ_LPC32XX_TS_IRQ,
+                .end = IRQ_LPC32XX_TS_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device lpc32xx_adc_device = {
+        .name =  "lpc32xx-adc",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(adc_resources),
+        .resource = adc_resources,
+};
+
+/*
+ * USB support
+ */
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32) 0;
+static struct resource ohci_resources[] = {
+        {
+                .start = IO_ADDRESS(LPC32XX_USB_BASE),
+                .end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = IRQ_LPC32XX_USB_HOST,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device lpc32xx_ohci_device = {
+        .name = "usb-ohci",
+        .id = -1,
+        .dev = {
+                .dma_mask = &ohci_dmamask,
+                .coherent_dma_mask = 0xFFFFFFFF,
+        },
+        .num_resources = ARRAY_SIZE(ohci_resources),
+        .resource = ohci_resources,
+};
+
+/*
+ * Network Support
+ */
+static struct resource net_resources[] = {
+        [0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K),
+        [1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K),
+        [2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET),
+};
+
+static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
+struct platform_device lpc32xx_net_device = {
+        .name = "lpc-eth",
+        .id = 0,
+        .dev = {
+                .dma_mask = &lpc32xx_mac_dma_mask,
+                .coherent_dma_mask = 0xffffffffUL,
+        },
+        .num_resources = ARRAY_SIZE(net_resources),
+        .resource = net_resources,
+};
+
+/*
  * Returns the unique ID for the device
  */
 void lpc32xx_get_uid(u32 devid[4])
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 4b4e700343c..68e45e8c948 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -19,6 +19,7 @@
 #ifndef __LPC32XX_COMMON_H
 #define __LPC32XX_COMMON_H
 
+#include <mach/board.h>
 #include <linux/platform_device.h>
 
 /*
@@ -29,7 +30,10 @@ extern struct platform_device lpc32xx_i2c0_device;
 extern struct platform_device lpc32xx_i2c1_device;
 extern struct platform_device lpc32xx_i2c2_device;
 extern struct platform_device lpc32xx_tsc_device;
+extern struct platform_device lpc32xx_adc_device;
 extern struct platform_device lpc32xx_rtc_device;
+extern struct platform_device lpc32xx_ohci_device;
+extern struct platform_device lpc32xx_net_device;
 
 /*
  * Other arch specific structures and functions
@@ -65,9 +69,7 @@ extern u32 clk_get_pclk_div(void);
  */
 extern void lpc32xx_get_uid(u32 devid[4]);
 
-extern void lpc32xx_watchdog_reset(void);
 extern u32 lpc32xx_return_iram_size(void);
-
 /*
  * Pointers used for sizing and copying suspend function data
  */
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/board.h
index bf176c99152..52531ca7bd1 100644
--- a/arch/arm/mach-lpc32xx/include/mach/system.h
+++ b/arch/arm/mach-lpc32xx/include/mach/board.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-lpc32xx/include/mach/system.h
+ * arm/arch/mach-lpc32xx/include/mach/board.h
  *
  * Author: Kevin Wells <kevin.wells@nxp.com>
  *
@@ -16,12 +16,9 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
 
-static void arch_idle(void)
-{
-        cpu_do_idle();
-}
+extern u32 lpc32xx_return_iram_size(void);
 
-#endif
+#endif  /* __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index b725f6c9397..24ca11b377c 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -21,16 +21,10 @@
 
 #define LPC32XX_INTC_MASKED_STATUS_OFS  0x8
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
 /*
  * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
  * as set if an interrupt is pending.
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 14ea8d1aadb..c584f5bb164 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -591,42 +591,42 @@
 /*
  * Timer/counter register offsets
  */
-#define LCP32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
-#define LCP32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
-#define LCP32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
-#define LCP32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
-#define LCP32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
-#define LCP32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
-#define LCP32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
-#define LCP32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
-#define LCP32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
-#define LCP32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
-#define LCP32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
-#define LCP32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
-#define LCP32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
-#define LCP32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
-#define LCP32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
-#define LCP32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
-#define LCP32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
+#define LPC32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
+#define LPC32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
+#define LPC32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
+#define LPC32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
+#define LPC32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
+#define LPC32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
+#define LPC32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
+#define LPC32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
+#define LPC32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
+#define LPC32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
+#define LPC32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
+#define LPC32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
+#define LPC32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
+#define LPC32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
+#define LPC32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
+#define LPC32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
+#define LPC32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
 
 /*
  * ir register definitions
  */
-#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
-#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
+#define LPC32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
+#define LPC32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
 
 /*
  * tcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_TCR_EN               0x1
-#define LCP32XX_TIMER_CNTR_TCR_RESET            0x2
+#define LPC32XX_TIMER_CNTR_TCR_EN               0x1
+#define LPC32XX_TIMER_CNTR_TCR_RESET            0x2
 
 /*
  * mcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
-#define LCP32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
-#define LCP32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
+#define LPC32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
+#define LPC32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
+#define LPC32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
 
 /*
  * Standard UART register offsets
@@ -690,5 +690,8 @@
 #define LPC32XX_GPIO_P1_MUX_SET                 _GPREG(0x130)
 #define LPC32XX_GPIO_P1_MUX_CLR                 _GPREG(0x134)
 #define LPC32XX_GPIO_P1_MUX_STATE               _GPREG(0x138)
+#define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
 
 #endif
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index c74de01ab5b..d080cb1123d 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -150,6 +150,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
                 .event_group = &lpc32xx_event_int_regs,
                 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
         },
+        [IRQ_LPC32XX_ETHERNET] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
+        },
         [IRQ_LPC32XX_USB_OTG_ATX] = {
                 .event_group = &lpc32xx_event_int_regs,
                 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bfee5b45510..7f7401ec748 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -37,6 +37,7 @@
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
+#include <mach/board.h>
 #include <mach/gpio-lpc32xx.h>
 #include "common.h"
 
@@ -149,20 +150,8 @@ static struct clcd_board lpc32xx_clcd_data = {
         .remove         = lpc32xx_clcd_remove,
 };
 
-static struct amba_device lpc32xx_clcd_device = {
-        .dev                            = {
-                .coherent_dma_mask      = ~0,
-                .init_name              = "dev:clcd",
-                .platform_data          = &lpc32xx_clcd_data,
-        },
-        .res                            = {
-                .start                  = LPC32XX_LCD_BASE,
-                .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
-                .flags                  = IORESOURCE_MEM,
-        },
-        .dma_mask                       = ~0,
-        .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
-};
+static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
+        LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
 
 /*
  * AMBA SSP (SPI)
@@ -191,20 +180,8 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
         .enable_dma             = 0,
 };
 
-static struct amba_device lpc32xx_ssp0_device = {
-        .dev                            = {
-                .coherent_dma_mask      = ~0,
-                .init_name              = "dev:ssp0",
-                .platform_data          = &lpc32xx_ssp0_data,
-        },
-        .res                            = {
-                .start                  = LPC32XX_SSP0_BASE,
-                .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
-                .flags                  = IORESOURCE_MEM,
-        },
-        .dma_mask                       = ~0,
-        .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
-};
+static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0,
+        LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data);
 
 /* AT25 driver registration */
 static int __init phy3250_spi_board_register(void)
@@ -271,11 +248,16 @@ static struct platform_device lpc32xx_gpio_led_device = {
 };
 
 static struct platform_device *phy3250_devs[] __initdata = {
+        &lpc32xx_rtc_device,
+        &lpc32xx_tsc_device,
         &lpc32xx_i2c0_device,
         &lpc32xx_i2c1_device,
         &lpc32xx_i2c2_device,
         &lpc32xx_watchdog_device,
         &lpc32xx_gpio_led_device,
+        &lpc32xx_adc_device,
+        &lpc32xx_ohci_device,
+        &lpc32xx_net_device,
 };
 
 static struct amba_device *amba_devs[] __initdata = {
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index b9c80597b7b..207e81275ff 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -13,7 +13,7 @@
 /*
  * LPC32XX CPU and system power management
  *
- * The LCP32XX has three CPU modes for controlling system power: run,
+ * The LPC32XX has three CPU modes for controlling system power: run,
  * direct-run, and halt modes. When switching between halt and run modes,
  * the CPU transistions through direct-run mode. For Linux, direct-run
  * mode is not used in normal operation. Halt mode is used when the
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index b42c909bbee..c40667c3316 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -34,11 +34,11 @@
 static int lpc32xx_clkevt_next_event(unsigned long delta,
     struct clock_event_device *dev)
 {
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-        __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 
         return 0;
 }
@@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
                  * disable the timer to wait for the first call to
                  * set_next_event().
                  */
-                __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+                __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
                 break;
 
         case CLOCK_EVT_MODE_UNUSED:
@@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
         struct clock_event_device *evt = &lpc32xx_clkevt;
 
         /* Clear match */
-        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+                LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 
         evt->event_handler(evt);
 
@@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void)
         clkrate = clkrate / clk_get_pclk_div();
 
         /* Initial timer setup */
-        __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
-        __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
-                LCP32XX_TIMER_CNTR_MCR_STOP(0) |
-                LCP32XX_TIMER_CNTR_MCR_RESET(0),
-                LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+                LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+        __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
+                LPC32XX_TIMER_CNTR_MCR_STOP(0) |
+                LPC32XX_TIMER_CNTR_MCR_RESET(0),
+                LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 
         /* Setup tick interrupt */
         setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
@@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void)
         clockevents_register_device(&lpc32xx_clkevt);
 
         /* Use timer1 as clock source. */
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-        __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
-        __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-
-        clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+
+        clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
                 "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
 }
 
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 323d4c9e9f4..5a90b9a3ab6 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,6 +2,16 @@ if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
 
+config MACH_MMP_DT
+        bool "Support MMP2 platforms from device tree"
+        select CPU_PXA168
+        select CPU_PXA910
+        select USE_OF
+        help
+          Include support for Marvell MMP2 based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_MMP_DT is enabled.
+
 config MACH_ASPENITE
         bool "Marvell's PXA168 Aspenite Development Board"
         select CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index ba254a71691..4fc0ff5dc96 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_MACH_TTC_DKB)	+= ttc_dkb.o
 obj-$(CONFIG_MACH_BROWNSTONE)   += brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
+obj-$(CONFIG_MACH_MMP_DT)       += mmp-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)       += gplugd.o
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index c42d9d4e892..9cff9e7a2b2 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -8,12 +8,6 @@
 
 #include <mach/regs-icu.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
         and     \tmp, \tmp, #0xff00
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 4de13abef7b..e2e1f1e5e12 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -22,6 +22,7 @@ extern struct pxa_device_desc pxa910_device_pwm4;
 extern struct pxa_device_desc pxa910_device_nand;
 
 extern struct platform_device pxa910_device_gpio;
+extern struct platform_device pxa910_device_rtc;
 
 static inline int pxa910_add_uart(int id)
 {
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 1a96585336b..8a37fb00365 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -57,6 +57,7 @@
 #define APBC_PXA910_SSP1        APBC_REG(0x01c)
 #define APBC_PXA910_SSP2        APBC_REG(0x020)
 #define APBC_PXA910_IPC         APBC_REG(0x024)
+#define APBC_PXA910_RTC         APBC_REG(0x028)
 #define APBC_PXA910_TWSI0       APBC_REG(0x02c)
 #define APBC_PXA910_KPC         APBC_REG(0x030)
 #define APBC_PXA910_TIMERS      APBC_REG(0x034)
diff --git a/arch/arm/mach-mmp/include/mach/regs-rtc.h b/arch/arm/mach-mmp/include/mach/regs-rtc.h
new file mode 100644
index 00000000000..5bff886a394
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-rtc.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_REGS_RTC_H
+#define __ASM_MACH_REGS_RTC_H
+
+#include <mach/addr-map.h>
+
+#define RTC_VIRT_BASE   (APB_VIRT_BASE + 0x10000)
+#define RTC_REG(x)      (*((volatile u32 __iomem *)(RTC_VIRT_BASE + (x))))
+
+/*
+ * Real Time Clock
+ */
+
+#define RCNR            RTC_REG(0x00)   /* RTC Count Register */
+#define RTAR            RTC_REG(0x04)   /* RTC Alarm Register */
+#define RTSR            RTC_REG(0x08)   /* RTC Status Register */
+#define RTTR            RTC_REG(0x0C)   /* RTC Timer Trim Register */
+
+#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
+#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
+#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
+#define RTSR_AL         (1 << 0)        /* RTC alarm detected */
+
+#endif /* __ASM_MACH_REGS_RTC_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
deleted file mode 100644
index 1d001eab81e..00000000000
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/system.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_SYSTEM_H
-#define __ASM_MACH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
new file mode 100644
index 00000000000..67075395e40
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+extern struct sys_timer pxa168_timer;
+extern void __init icu_init_irq(void);
+
+static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+        {}
+};
+
+static int __init mmp_intc_add_irq_domain(struct device_node *np,
+                                           struct device_node *parent)
+{
+        irq_domain_add_simple(np, 0);
+        return 0;
+}
+
+static int __init mmp_gpio_add_irq_domain(struct device_node *np,
+                                           struct device_node *parent)
+{
+        irq_domain_add_simple(np, IRQ_GPIO_START);
+        return 0;
+}
+
+static const struct of_device_id mmp_irq_match[] __initconst = {
+        { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
+        { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
+        {}
+};
+
+static void __init mmp_dt_init(void)
+{
+
+        of_irq_init(mmp_irq_match);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             mmp_auxdata_lookup, NULL);
+}
+
+static const char *pxa168_dt_board_compat[] __initdata = {
+        "mrvl,pxa168-aspenite",
+        NULL,
+};
+
+DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
+        .map_io         = mmp_map_io,
+        .init_irq       = icu_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = mmp_dt_init,
+        .dt_compat      = pxa168_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 617c60a170a..c709a24a9d2 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -223,6 +223,7 @@ struct resource mmp2_resource_gpio[] = {
         }, {
                 .start  = IRQ_MMP2_GPIO,
                 .end    = IRQ_MMP2_GPIO,
+                .name   = "gpio_mux",
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 520f39dc321..b24d2c32cba 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -65,6 +65,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
 static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
+static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(lcd, LCD, 0x7f, 312000000);
@@ -93,6 +94,7 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
         INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
 
 static int __init pxa168_init(void)
@@ -167,6 +169,7 @@ struct resource pxa168_resource_gpio[] = {
         }, {
                 .start  = IRQ_PXA168_GPIOX,
                 .end    = IRQ_PXA168_GPIOX,
+                .name   = "gpio_mux",
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 3241a25784d..43f8bcc29b6 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -92,6 +92,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
 static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
+static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(u2o, USB, 0x1b, 480000000);
@@ -109,6 +110,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
         INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
 
 static int __init pxa910_init(void)
@@ -173,6 +175,7 @@ struct resource pxa910_resource_gpio[] = {
         }, {
                 .start  = IRQ_PXA910_AP_GPIO,
                 .end    = IRQ_PXA910_AP_GPIO,
+                .name   = "gpio_mux",
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -183,3 +186,28 @@ struct platform_device pxa910_device_gpio = {
         .num_resources  = ARRAY_SIZE(pxa910_resource_gpio),
         .resource       = pxa910_resource_gpio,
 };
+
+static struct resource pxa910_resource_rtc[] = {
+        {
+                .start  = 0xd4010000,
+                .end    = 0xd401003f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PXA910_RTC_INT,
+                .end    = IRQ_PXA910_RTC_INT,
+                .name   = "rtc 1Hz",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_PXA910_RTC_ALARM,
+                .end    = IRQ_PXA910_RTC_ALARM,
+                .name   = "rtc alarm",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa910_device_rtc = {
+        .name           = "sa1100-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa910_resource_rtc),
+        .resource       = pxa910_resource_rtc,
+};
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 5ac5d5832e4..e72c709da44 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -124,6 +124,7 @@ static struct platform_device ttc_dkb_device_onenand = {
 
 static struct platform_device *ttc_dkb_devices[] = {
         &pxa910_device_gpio,
+        &pxa910_device_rtc,
         &ttc_dkb_device_onenand,
 };
 
diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
deleted file mode 100644
index 6a94f052713..00000000000
--- a/arch/arm/mach-msm/idle.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/* arch/arm/mach-msm/include/mach/idle.S
- *
- * Idle processing for MSM7K - work around bugs with SWFI.
- *
- * Copyright (c) 2007 QUALCOMM Incorporated.
- * Copyright (C) 2007 Google, Inc. 
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */ 
-                
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-ENTRY(arch_idle)
-#ifdef CONFIG_MSM7X00A_IDLE
-        mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */
-        bic     r0, r1, #(1 << 2)        /* clear dcache bit   */
-        bic     r0, r0, #(1 << 12)       /* clear icache bit   */
-        mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */
-
-        mov     r0, #0                   /* prepare wfi value  */
-        mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */
-        mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */
-        mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */
-
-        mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */
-#endif
-        mov     pc, lr
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
new file mode 100644
index 00000000000..0c9e13c6574
--- /dev/null
+++ b/arch/arm/mach-msm/idle.c
@@ -0,0 +1,49 @@
+/* arch/arm/mach-msm/idle.c
+ *
+ * Idle processing for MSM7K - work around bugs with SWFI.
+ *
+ * Copyright (c) 2007 QUALCOMM Incorporated.
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <asm/system.h>
+
+static void msm_idle(void)
+{
+#ifdef CONFIG_MSM7X00A_IDLE
+        asm volatile (
+
+        "mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */ \n\t"
+        "bic     r0, r1, #(1 << 2)        /* clear dcache bit   */ \n\t"
+        "bic     r0, r0, #(1 << 12)       /* clear icache bit   */ \n\t"
+        "mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */ \n\t"
+
+        "mov     r0, #0                   /* prepare wfi value  */ \n\t"
+        "mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */ \n\t"
+        "mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */ \n\t"
+        "mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */ \n\t"
+
+        "mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */ \n\t"
+
+        : : : "r0","r1" );
+#endif
+}
+
+static int __init msm_idle_init(void)
+{
+        arm_pm_idle = msm_idle;
+        return 0;
+}
+
+arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index 41f7003ef34..f2ae9087f65 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -16,12 +16,6 @@
  *
  */
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
 #if !defined(CONFIG_ARM_GIC)
 #include <mach/msm_iomap.h>
 
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
index 311db2b35da..f5fb2ec87ff 100644
--- a/arch/arm/mach-msm/include/mach/system.h
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -12,7 +12,6 @@
  * GNU General Public License for more details.
  *
  */
-void arch_idle(void);
 
 /* low level hardware reset hook -- for example, hitting the
  * PSHOLD line on the PMIC to hard reset the system
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 11d0d8f2656..75f4be40b3e 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -127,6 +127,45 @@ static struct clocksource msm_clocksource = {
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+#ifdef CONFIG_LOCAL_TIMERS
+static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
+{
+        /* Use existing clock_event for cpu 0 */
+        if (!smp_processor_id())
+                return 0;
+
+        writel_relaxed(0, event_base + TIMER_ENABLE);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
+        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
+        evt->irq = msm_clockevent.irq;
+        evt->name = "local_timer";
+        evt->features = msm_clockevent.features;
+        evt->rating = msm_clockevent.rating;
+        evt->set_mode = msm_timer_set_mode;
+        evt->set_next_event = msm_timer_set_next_event;
+        evt->shift = msm_clockevent.shift;
+        evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
+        evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
+        evt->min_delta_ns = clockevent_delta2ns(4, evt);
+
+        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
+        clockevents_register_device(evt);
+        enable_percpu_irq(evt->irq, 0);
+        return 0;
+}
+
+static void msm_local_timer_stop(struct clock_event_device *evt)
+{
+        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+        disable_percpu_irq(evt->irq);
+}
+
+static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
+        .setup  = msm_local_timer_setup,
+        .stop   = msm_local_timer_stop,
+};
+#endif /* CONFIG_LOCAL_TIMERS */
+
 static void __init msm_timer_init(void)
 {
         struct clock_event_device *ce = &msm_clockevent;
@@ -173,8 +212,12 @@ static void __init msm_timer_init(void)
                 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
                                          ce->name, msm_evt.percpu_evt);
-                if (!res)
+                if (!res) {
                         enable_percpu_irq(ce->irq, 0);
+#ifdef CONFIG_LOCAL_TIMERS
+                        local_timer_register(&msm_local_timer_ops);
+#endif
+                }
         } else {
                 msm_evt.evt = ce;
                 res = request_irq(ce->irq, msm_timer_interrupt,
@@ -191,40 +234,6 @@ err:
                 pr_err("clocksource_register failed\n");
 }
 
-#ifdef CONFIG_LOCAL_TIMERS
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        /* Use existing clock_event for cpu 0 */
-        if (!smp_processor_id())
-                return 0;
-
-        writel_relaxed(0, event_base + TIMER_ENABLE);
-        writel_relaxed(0, event_base + TIMER_CLEAR);
-        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
-        evt->irq = msm_clockevent.irq;
-        evt->name = "local_timer";
-        evt->features = msm_clockevent.features;
-        evt->rating = msm_clockevent.rating;
-        evt->set_mode = msm_timer_set_mode;
-        evt->set_next_event = msm_timer_set_next_event;
-        evt->shift = msm_clockevent.shift;
-        evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
-        evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
-        evt->min_delta_ns = clockevent_delta2ns(4, evt);
-
-        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
-        clockevents_register_device(evt);
-        enable_percpu_irq(evt->irq, 0);
-        return 0;
-}
-
-void local_timer_stop(struct clock_event_device *evt)
-{
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-        disable_percpu_irq(evt->irq);
-}
-#endif /* CONFIG_LOCAL_TIMERS */
-
 struct sys_timer msm_timer = {
         .init = msm_timer_init
 };
diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
index 66ae2d29e77..6b1f088e059 100644
--- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
+++ b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IRQ_VIRT_BASE
         .endm
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h
deleted file mode 100644
index 8c3a5387cec..00000000000
--- a/arch/arm/mach-mv78xx0/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 8459f6d7d8c..df3e38055a2 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -155,8 +155,8 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
         orion_pcie_setup(pp->base);
 
-        pci_add_resource(&sys->resources, &pp->res[0]);
-        pci_add_resource(&sys->resources, &pp->res[1]);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index cf00b3e3be8..c57f9964a71 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -83,6 +83,18 @@ config MODULE_M28
         select MXS_HAVE_PLATFORM_MXSFB
         select MXS_OCOTP
 
+config MODULE_APX4
+        bool
+        select SOC_IMX28
+        select LEDS_GPIO_REGISTER
+        select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
+        select MXS_HAVE_PLATFORM_FEC
+        select MXS_HAVE_PLATFORM_MXS_I2C
+        select MXS_HAVE_PLATFORM_MXS_MMC
+        select MXS_HAVE_PLATFORM_MXS_SAIF
+        select MXS_OCOTP
+
 config MACH_TX28
         bool "Ka-Ro TX28 module"
         select MODULE_TX28
@@ -91,4 +103,8 @@ config MACH_M28EVK
         bool "Support DENX M28EVK Platform"
         select MODULE_M28
 
+config MACH_APX4DEVKIT
+        bool "Support Bluegiga APX4 Development Kit"
+        select MODULE_APX4
+
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 8c93b24896b..908bf9a567f 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
 obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
+obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o
 obj-$(CONFIG_MODULE_TX28) += module-tx28.o
 obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
 
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index e12e11231dc..e3ac52c3401 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -223,7 +223,6 @@ static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 reg, bm_busy, div_max, d, f, div, frac;
         unsigned long diff, parent_rate, calc_rate;
-        int i;
 
         parent_rate = clk_get_rate(clk->parent);
 
@@ -275,14 +274,7 @@ static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
         reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
 
-        for (i = 10000; i; i--)
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
-                                        HW_CLKCTRL_CPU) & bm_busy))
-                        break;
-        if (!i) {
-                pr_err("%s: divider writing timeout\n", __func__);
-                return -ETIMEDOUT;
-        }
+        mxs_clkctrl_timeout(HW_CLKCTRL_CPU, bm_busy);
 
         return 0;
 }
@@ -292,7 +284,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
 {                                                                       \
         u32 reg, div_max, div;                                          \
         unsigned long parent_rate;                                      \
-        int i;                                                          \
                                                                         \
         parent_rate = clk_get_rate(clk->parent);                        \
         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
@@ -310,15 +301,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         }                                                               \
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
                                                                         \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
-        }                                                               \
-                                                                        \
+        mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);   \
         return 0;                                                       \
 }
 
@@ -456,12 +439,13 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
         _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
         _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
+        _REGISTER_CLOCK("imx23-gpmi-nand", NULL, gpmi_clk)
 };
 
 static int clk_misc_init(void)
 {
         u32 reg;
-        int i;
+        int ret;
 
         /* Fix up parent per register setting */
         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
@@ -510,14 +494,7 @@ static int clk_misc_init(void)
         reg |= 3 << BP_CLKCTRL_HBUS_DIV;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 
-        for (i = 10000; i; i--)
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
-                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
-                        break;
-        if (!i) {
-                pr_err("%s: divider writing timeout\n", __func__);
-                return -ETIMEDOUT;
-        }
+        ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_BUSY);
 
         /* Gate off cpu clock in WFI for power saving */
         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
@@ -532,7 +509,7 @@ static int clk_misc_init(void)
         reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
 
-        return 0;
+        return ret;
 }
 
 int __init mx23_clocks_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5d68e415222..cea29c99e21 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -322,7 +322,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
 {                                                                       \
         u32 reg, bm_busy, div_max, d, f, div, frac;                     \
         unsigned long diff, parent_rate, calc_rate;                     \
-        int i;                                                          \
                                                                         \
         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
         bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
@@ -396,16 +395,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         }                                                               \
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
                                                                         \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##dr) & bm_busy))                    \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
-        }                                                               \
-                                                                        \
-        return 0;                                                       \
+        return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, bm_busy);           \
 }
 
 _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
@@ -421,7 +411,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
 {                                                                       \
         u32 reg, div_max, div;                                          \
         unsigned long parent_rate;                                      \
-        int i;                                                          \
                                                                         \
         parent_rate = clk_get_rate(clk->parent);                        \
         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
@@ -439,16 +428,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         }                                                               \
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
                                                                         \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
-        }                                                               \
-                                                                        \
-        return 0;                                                       \
+        return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);\
 }
 
 _CLK_SET_RATE1(xbus_clk, XBUS)
@@ -461,7 +441,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         u32 reg;                                                        \
         u64 lrate;                                                      \
         unsigned long parent_rate;                                      \
-        int i;                                                          \
                                                                         \
         parent_rate = clk_get_rate(clk->parent);                        \
         if (rate > parent_rate)                                         \
@@ -477,18 +456,13 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
         reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
         reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                        \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY))     \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
+        if (reg & (1 << clk->enable_shift)) {                           \
+                pr_err("%s: clock is gated\n", __func__);               \
+                return -EINVAL;                                         \
         }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
                                                                         \
-        return 0;                                                       \
+        return mxs_clkctrl_timeout(HW_CLKCTRL_##rs, BM_CLKCTRL_##rs##_BUSY);\
 }
 
 _CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
@@ -643,6 +617,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("duart", NULL, uart_clk)
         _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
         _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
+        _REGISTER_CLOCK("imx28-gpmi-nand", NULL, gpmi_clk)
         _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
         _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
         _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
@@ -654,6 +629,8 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
         _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
         _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
+        _REGISTER_CLOCK("mxs-mmc.2", NULL, ssp2_clk)
+        _REGISTER_CLOCK("mxs-mmc.3", NULL, ssp3_clk)
         _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
         _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
         _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
@@ -676,7 +653,7 @@ static struct clk_lookup lookups[] = {
 static int clk_misc_init(void)
 {
         u32 reg;
-        int i;
+        int ret;
 
         /* Fix up parent per register setting */
         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
@@ -756,14 +733,7 @@ static int clk_misc_init(void)
         reg |= 3 << BP_CLKCTRL_HBUS_DIV;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 
-        for (i = 10000; i; i--)
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
-                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
-                        break;
-        if (!i) {
-                pr_err("%s: divider writing timeout\n", __func__);
-                return -ETIMEDOUT;
-        }
+        ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_ASM_BUSY);
 
         /* Gate off cpu clock in WFI for power saving */
         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
@@ -790,7 +760,7 @@ static int clk_misc_init(void)
         reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
 
-        return 0;
+        return ret;
 }
 
 int __init mx28_clocks_init(void)
@@ -803,6 +773,8 @@ int __init mx28_clocks_init(void)
          */
         clk_set_parent(&ssp0_clk, &ref_io0_clk);
         clk_set_parent(&ssp1_clk, &ref_io0_clk);
+        clk_set_parent(&ssp2_clk, &ref_io1_clk);
+        clk_set_parent(&ssp3_clk, &ref_io1_clk);
 
         clk_prepare_enable(&cpu_clk);
         clk_prepare_enable(&hbus_clk);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 3fa651d2c99..4d1329d5928 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -21,6 +21,10 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst;
 #define mx23_add_auart0()               mx23_add_auart(0)
 #define mx23_add_auart1()               mx23_add_auart(1)
 
+extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst;
+#define mx23_add_gpmi_nand(pdata)       \
+        mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data)
+
 extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
 #define mx23_add_mxs_mmc(id, pdata) \
         mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 4f50094e293..9dbeae13084 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -34,6 +34,10 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
 #define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
 #define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
 
+extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst;
+#define mx28_add_gpmi_nand(pdata)       \
+        mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data)
+
 extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
 #define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
 
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index fe3e847930c..01faffec306 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -77,16 +77,18 @@ err:
 
 int __init mxs_add_amba_device(const struct amba_device *dev)
 {
-        struct amba_device *adev = kmalloc(sizeof(*adev), GFP_KERNEL);
+        struct amba_device *adev = amba_device_alloc(dev->dev.init_name,
+                dev->res.start, resource_size(&dev->res));
 
         if (!adev) {
                 pr_err("%s: failed to allocate memory", __func__);
                 return -ENOMEM;
         }
 
-        *adev = *dev;
+        adev->irq[0] = dev->irq[0];
+        adev->irq[1] = dev->irq[1];
 
-        return amba_device_register(adev, &iomem_resource);
+        return amba_device_add(adev, &iomem_resource);
 }
 
 struct device mxs_apbh_bus = {
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 18b6bf526a2..b8913df4cfa 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -12,6 +12,9 @@ config MXS_HAVE_PLATFORM_FLEXCAN
         select HAVE_CAN_FLEXCAN if CAN
         bool
 
+config MXS_HAVE_PLATFORM_GPMI_NAND
+        bool
+
 config MXS_HAVE_PLATFORM_MXS_I2C
         bool
 
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index f52e3e53bae..c8f5c9541a3 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
 obj-y += platform-dma.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c
index a559db09b49..a5479f76604 100644
--- a/arch/arm/mach-mxs/devices/amba-duart.c
+++ b/arch/arm/mach-mxs/devices/amba-duart.c
@@ -23,7 +23,7 @@ const struct amba_device name##_device __initconst = {		\
                 .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1,   \
                 .flags = IORESOURCE_MEM,                        \
         },                                                      \
-        .irq = {soc ## _INT_DUART, NO_IRQ},                     \
+        .irq = {soc ## _INT_DUART},                             \
 }
 
 #ifdef CONFIG_SOC_IMX23
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
new file mode 100644
index 00000000000..3e22df5944a
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#include <linux/dma-mapping.h>
+
+#ifdef CONFIG_SOC_IMX23
+const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
+        .devid = "imx23-gpmi-nand",
+        .res = {
+                /* GPMI */
+                DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
+                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
+                /* BCH */
+                DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
+                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
+                /* DMA */
+                DEFINE_RES_NAMED(MX23_DMA_GPMI0,
+                                        MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
+                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
+                                        IORESOURCE_DMA),
+                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
+                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
+        },
+};
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
+        .devid = "imx28-gpmi-nand",
+        .res = {
+                /* GPMI */
+                DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
+                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
+                /* BCH */
+                DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
+                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
+                /* DMA */
+                DEFINE_RES_NAMED(MX28_DMA_GPMI0,
+                                        MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
+                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
+                                        IORESOURCE_DMA),
+                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
+                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
+        },
+};
+#endif
+
+struct platform_device *__init
+mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
+                const struct mxs_gpmi_nand_data *data)
+{
+        return mxs_add_platform_device_dmamask(data->devid, -1,
+                                data->res, GPMI_NAND_RES_SIZE,
+                                pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
index 382dacbeca2..bef9d923f54 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
@@ -41,6 +41,8 @@ const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
 const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
         mxs_mxs_mmc_data_entry(MX28, 0, 0),
         mxs_mxs_mmc_data_entry(MX28, 1, 1),
+        mxs_mxs_mmc_data_entry(MX28, 2, 2),
+        mxs_mxs_mmc_data_entry(MX28, 3, 3),
 };
 #endif
 
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index e1237ab2586..c50c3ea28a9 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -31,4 +31,6 @@ extern void mx28_init_irq(void);
 
 extern void icoll_init_irq(void);
 
+extern int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask);
+
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index dc369c1239f..f2e383955d8 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -66,6 +66,16 @@ struct platform_device *__init mxs_add_flexcan(
                 const struct mxs_flexcan_data *data,
                 const struct flexcan_platform_data *pdata);
 
+/* gpmi-nand */
+#include <linux/mtd/gpmi-nand.h>
+struct mxs_gpmi_nand_data {
+        const char *devid;
+        const struct resource res[GPMI_NAND_RES_SIZE];
+};
+struct platform_device *__init
+mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
+                const struct mxs_gpmi_nand_data *data);
+
 /* i2c */
 struct mxs_mxs_i2c_data {
         int id;
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h
index 49a888c65d6..17964066303 100644
--- a/arch/arm/mach-mxs/include/mach/digctl.h
+++ b/arch/arm/mach-mxs/include/mach/digctl.h
@@ -18,4 +18,5 @@
 #define HW_DIGCTL_CTRL                  0x0
 #define  BP_DIGCTL_CTRL_SAIF_CLKMUX     10
 #define  BM_DIGCTL_CTRL_SAIF_CLKMUX     (0x3 << 10)
+#define HW_DIGCTL_CHIPID                0x310
 #endif
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S
index 9f0da12e657..0c14259705b 100644
--- a/arch/arm/mach-mxs/include/mach/entry-macro.S
+++ b/arch/arm/mach-mxs/include/mach/entry-macro.S
@@ -23,9 +23,6 @@
 #define MXS_ICOLL_VBASE         MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
 #define HW_ICOLL_STAT_OFFSET    0x70
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
         cmp     \irqnr, #0x7F
@@ -36,6 +33,3 @@
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =MXS_ICOLL_VBASE
         .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index bde5f663474..7d4fb6d0afd 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -23,22 +23,10 @@
 #include <linux/io.h>
 #endif
 #include <asm/mach-types.h>
+#include <mach/digctl.h>
 #include <mach/hardware.h>
 
 /*
- * MXS CPU types
- */
-#define cpu_is_mx23()           (                                       \
-                machine_is_mx23evk() ||                                 \
-                machine_is_stmp378x() ||                                \
-                0)
-#define cpu_is_mx28()           (                                       \
-                machine_is_mx28evk() ||                                 \
-                machine_is_m28evk() ||                                  \
-                machine_is_tx28() ||                                    \
-                0)
-
-/*
  * IO addresses common to MXS-based
  */
 #define MXS_IO_BASE_ADDR                0x80000000
@@ -109,6 +97,21 @@ static inline void __mxs_togl(u32 mask, void __iomem *reg)
 {
         __raw_writel(mask, reg + MXS_TOG_ADDR);
 }
+
+/*
+ * MXS CPU types
+ */
+#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID)
+
+static inline int cpu_is_mx23(void)
+{
+        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780);
+}
+
+static inline int cpu_is_mx28(void)
+{
+        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800);
+}
 #endif
 
 #endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h
deleted file mode 100644
index e7ad1bb2942..00000000000
--- a/arch/arm/mach-mxs/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_MXS_SYSTEM_H__
-#define __MACH_MXS_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif /* __MACH_MXS_SYSTEM_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index 67776746f14..ef281149544 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -18,8 +18,6 @@
 #ifndef __MACH_MXS_UNCOMPRESS_H__
 #define __MACH_MXS_UNCOMPRESS_H__
 
-#include <asm/mach-types.h>
-
 unsigned long mxs_duart_base;
 
 #define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
@@ -55,16 +53,17 @@ static inline void flush(void)
 
 #define MX23_DUART_BASE_ADDR    0x80070000
 #define MX28_DUART_BASE_ADDR    0x80074000
+#define MXS_DIGCTL_CHIPID       0x8001c310
 
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
-        switch (arch_id) {
-        case MACH_TYPE_MX23EVK:
+        u16 chipid = (*(volatile unsigned long *) MXS_DIGCTL_CHIPID) >> 16;
+
+        switch (chipid) {
+        case 0x3780:
                 mxs_duart_base = MX23_DUART_BASE_ADDR;
                 break;
-        case MACH_TYPE_MX28EVK:
-        case MACH_TYPE_M28EVK:
-        case MACH_TYPE_TX28:
+        case 0x2800:
                 mxs_duart_base = MX28_DUART_BASE_ADDR;
                 break;
         default:
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
new file mode 100644
index 00000000000..48a7fab571a
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2011-2012
+ * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com>
+ * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com>
+ *
+ * based on: mach-mx28evk.c
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/micrel_phy.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/digctl.h>
+#include <mach/iomux-mx28.h>
+
+#include "devices-mx28.h"
+
+#define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28)
+
+static const iomux_cfg_t apx4devkit_pads[] __initconst = {
+        /* duart */
+        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
+        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+
+        /* auart0 */
+        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
+
+        /* auart1 */
+        MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
+
+        /* auart2 */
+        MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL,
+        MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL,
+
+        /* auart3 */
+        MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL,
+        MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL,
+
+#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
+        /* fec0 */
+        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
+
+        /* i2c */
+        MX28_PAD_I2C0_SCL__I2C0_SCL,
+        MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+        /* mmc0 */
+        MX28_PAD_SSP0_DATA0__SSP0_D0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA1__SSP0_D1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA2__SSP0_D2 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA3__SSP0_D3 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA4__SSP0_D4 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA5__SSP0_D5 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA6__SSP0_D6 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA7__SSP0_D7 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_CMD__SSP0_CMD |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_SSP0_SCK__SSP0_SCK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+        /* led */
+        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
+
+        /* saif0 & saif1 */
+        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+};
+
+/* led */
+static const struct gpio_led apx4devkit_leds[] __initconst = {
+        {
+                .name = "user-led",
+                .default_trigger = "heartbeat",
+                .gpio = APX4DEVKIT_GPIO_USERLED,
+        },
+};
+
+static const struct gpio_led_platform_data apx4devkit_led_data __initconst = {
+        .leds = apx4devkit_leds,
+        .num_leds = ARRAY_SIZE(apx4devkit_leds),
+};
+
+static const struct fec_platform_data mx28_fec_pdata __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = {
+        .wp_gpio = -EINVAL,
+        .flags = SLOTF_4_BIT_CAPABLE,
+};
+
+static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = {
+        { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */
+        { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */
+};
+
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \
+                defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = {
+        REGULATOR_SUPPLY("VDDA", "0-000a"),
+        REGULATOR_SUPPLY("VDDIO", "0-000a"),
+};
+
+static struct regulator_init_data apx4devkit_vdd_reg_init_data = {
+        .constraints    = {
+                .name   = "3V3",
+                .always_on = 1,
+        },
+        .consumer_supplies = apx4devkit_audio_consumer_supplies,
+        .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config apx4devkit_vdd_pdata = {
+        .supply_name    = "board-3V3",
+        .microvolts     = 3300000,
+        .gpio           = -EINVAL,
+        .enabled_at_boot = 1,
+        .init_data      = &apx4devkit_vdd_reg_init_data,
+};
+
+static struct platform_device apx4devkit_voltage_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &apx4devkit_vdd_pdata,
+        },
+};
+
+static void __init apx4devkit_add_regulators(void)
+{
+        platform_device_register(&apx4devkit_voltage_regulator);
+}
+#else
+static void __init apx4devkit_add_regulators(void) {}
+#endif
+
+static const struct mxs_saif_platform_data
+                        apx4devkit_mxs_saif_pdata[] __initconst = {
+        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
+        {
+                .master_mode = 1,
+                .master_id = 0,
+        }, {
+                .master_mode = 0,
+                .master_id = 0,
+        },
+};
+
+static int apx4devkit_phy_fixup(struct phy_device *phy)
+{
+        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
+        return 0;
+}
+
+static void __init apx4devkit_init(void)
+{
+        mxs_iomux_setup_multiple_pads(apx4devkit_pads,
+                        ARRAY_SIZE(apx4devkit_pads));
+
+        mx28_add_duart();
+        mx28_add_auart0();
+        mx28_add_auart1();
+        mx28_add_auart2();
+        mx28_add_auart3();
+
+        /*
+         * Register fixup for the Micrel KS8031 PHY clock
+         * (shares same ID with KS8051)
+         */
+        phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
+                        apx4devkit_phy_fixup);
+
+        mx28_add_fec(0, &mx28_fec_pdata);
+
+        mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata);
+
+        gpio_led_register_device(0, &apx4devkit_led_data);
+
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
+        mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]);
+        mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]);
+
+        apx4devkit_add_regulators();
+
+        mx28_add_mxs_i2c(0);
+        i2c_register_board_info(0, apx4devkit_i2c_boardinfo,
+                        ARRAY_SIZE(apx4devkit_i2c_boardinfo));
+
+        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0);
+}
+
+static void __init apx4devkit_timer_init(void)
+{
+        mx28_clocks_init();
+}
+
+static struct sys_timer apx4devkit_timer = {
+        .init   = apx4devkit_timer_init,
+};
+
+MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit")
+        .map_io         = mx28_map_io,
+        .init_irq       = mx28_init_irq,
+        .timer          = &apx4devkit_timer,
+        .init_machine   = apx4devkit_init,
+        .restart        = mxs_restart,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 2f2758230ed..06d79963611 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -247,18 +247,15 @@ static int __init m28evk_fec_get_mac(void)
         u32 val;
         const u32 *ocotp = mxs_get_ocotp();
 
-        if (!ocotp) {
-                pr_err("%s: timeout when reading fec mac from OCOTP\n",
-                        __func__);
+        if (!ocotp)
                 return -ETIMEDOUT;
-        }
 
         /*
          * OCOTP only stores the last 4 octets for each mac address,
          * so hard-code DENX OUI (C0:E5:4E) here.
          */
         for (i = 0; i < 2; i++) {
-                val = ocotp[i * 4];
+                val = ocotp[i];
                 mx28_fec_pdata[i].mac[0] = 0xC0;
                 mx28_fec_pdata[i].mac[1] = 0xE5;
                 mx28_fec_pdata[i].mac[2] = 0x4E;
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index fdb0a5664dd..e386c142f93 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -223,7 +223,6 @@ static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
 /* fec */
 static void __init mx28evk_fec_reset(void)
 {
-        int ret;
         struct clk *clk;
 
         /* Enable fec phy clock */
@@ -231,32 +230,7 @@ static void __init mx28evk_fec_reset(void)
         if (!IS_ERR(clk))
                 clk_prepare_enable(clk);
 
-        /* Power up fec phy */
-        ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
-        if (ret) {
-                pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret);
-                return;
-        }
-
-        ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0);
-        if (ret) {
-                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret);
-                return;
-        }
-
-        /* Reset fec phy */
-        ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset");
-        if (ret) {
-                pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret);
-                return;
-        }
-
-        gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0);
-        if (ret) {
-                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret);
-                return;
-        }
-
+        gpio_set_value(MX28EVK_FEC_PHY_RESET, 0);
         mdelay(1);
         gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
 }
@@ -278,14 +252,14 @@ static int __init mx28evk_fec_get_mac(void)
         const u32 *ocotp = mxs_get_ocotp();
 
         if (!ocotp)
-                goto error;
+                return -ETIMEDOUT;
 
         /*
          * OCOTP only stores the last 4 octets for each mac address,
          * so hard-code Freescale OUI (00:04:9f) here.
          */
         for (i = 0; i < 2; i++) {
-                val = ocotp[i * 4];
+                val = ocotp[i];
                 mx28_fec_pdata[i].mac[0] = 0x00;
                 mx28_fec_pdata[i].mac[1] = 0x04;
                 mx28_fec_pdata[i].mac[2] = 0x9f;
@@ -295,10 +269,6 @@ static int __init mx28evk_fec_get_mac(void)
         }
 
         return 0;
-
-error:
-        pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
-        return -ETIMEDOUT;
 }
 
 /*
@@ -417,9 +387,14 @@ static void __init mx28evk_add_regulators(void)
 static void __init mx28evk_add_regulators(void) {}
 #endif
 
-static struct gpio mx28evk_lcd_gpios[] = {
+static const struct gpio mx28evk_gpios[] __initconst = {
         { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
         { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
+        { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" },
+        { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" },
+        { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" },
+        { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
+        { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" },
 };
 
 static const struct mxs_saif_platform_data
@@ -447,25 +422,18 @@ static void __init mx28evk_init(void)
         if (mx28evk_fec_get_mac())
                 pr_warn("%s: failed on fec mac setup\n", __func__);
 
+        ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios));
+        if (ret)
+                pr_err("One or more GPIOs failed to be requested: %d\n", ret);
+
         mx28evk_fec_reset();
         mx28_add_fec(0, &mx28_fec_pdata[0]);
         mx28_add_fec(1, &mx28_fec_pdata[1]);
 
-        ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
-                                "flexcan-switch");
-        if (ret) {
-                pr_err("failed to request gpio flexcan-switch: %d\n", ret);
-        } else {
-                mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
-                mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
-        }
+        mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
+        mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
 
-        ret = gpio_request_array(mx28evk_lcd_gpios,
-                                 ARRAY_SIZE(mx28evk_lcd_gpios));
-        if (ret)
-                pr_warn("failed to request gpio pins for lcd: %d\n", ret);
-        else
-                mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
+        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
 
         mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
         mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
@@ -480,20 +448,8 @@ static void __init mx28evk_init(void)
         mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0,
                         NULL, 0);
 
-        /* power on mmc slot by writing 0 to the gpio */
-        ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-                               "mmc0-slot-power");
-        if (ret)
-                pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
-        else
-                mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
-
-        ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-                               "mmc1-slot-power");
-        if (ret)
-                pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
-        else
-                mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
+        mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
+        mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
 
         mx28_add_rtc_stmp3xxx();
 
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
index fb042da29bd..a9b4bbcdafb 100644
--- a/arch/arm/mach-mxs/pm.c
+++ b/arch/arm/mach-mxs/pm.c
@@ -15,13 +15,12 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/io.h>
-#include <mach/system.h>
 
 static int mxs_suspend_enter(suspend_state_t state)
 {
         switch (state) {
         case PM_SUSPEND_MEM:
-                arch_idle();
+                cpu_do_idle();
                 break;
 
         default:
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 30042e23bfa..80ac1fca8a0 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -37,6 +37,8 @@
 #define MXS_MODULE_CLKGATE              (1 << 30)
 #define MXS_MODULE_SFTRST               (1 << 31)
 
+#define CLKCTRL_TIMEOUT         10      /* 10 ms */
+
 static void __iomem *mxs_clkctrl_reset_addr;
 
 /*
@@ -137,3 +139,17 @@ error:
         return -ETIMEDOUT;
 }
 EXPORT_SYMBOL(mxs_reset_block);
+
+int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(CLKCTRL_TIMEOUT);
+        while (readl_relaxed(MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR)
+                                                + reg_offset) & mask) {
+                if (time_after(jiffies, timeout)) {
+                        pr_err("Timeout at CLKCTRL + 0x%x\n", reg_offset);
+                        return -ETIMEDOUT;
+                }
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index b9913234bbf..2cdf6ef69be 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -92,18 +92,7 @@ void clk_put(struct clk *clk)
 {
 }
 
-static struct amba_device fb_device = {
-        .dev            = {
-                .init_name = "fb",
-                .coherent_dma_mask = ~0,
-        },
-        .res            = {
-                .start  = 0x00104000,
-                .end    = 0x00104fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { NETX_IRQ_LCD, NO_IRQ },
-};
+static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL);
 
 int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
 {
diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
deleted file mode 100644
index 6e9f1cbe163..00000000000
--- a/arch/arm/mach-netx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-netx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Hilscher netX based platforms
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h
deleted file mode 100644
index b38fa36d58c..00000000000
--- a/arch/arm/mach-netx/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-netx/include/mach/system.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
-
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 7c878bf0034..58cacafcf66 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -27,11 +27,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
+#include <asm/mach/time.h>
 
 #include <plat/gpio-nomadik.h>
 #include <plat/mtu.h>
 
-#include <mach/setup.h>
 #include <mach/nand.h>
 #include <mach/fsmc.h>
 
@@ -185,20 +185,11 @@ static void __init nhk8815_onenand_init(void)
 #endif
 }
 
-#define __MEM_4K_RESOURCE(x) \
-        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE,
+        { IRQ_UART0 }, NULL);
 
-static struct amba_device uart0_device = {
-        .dev = { .init_name = "uart0" },
-        __MEM_4K_RESOURCE(NOMADIK_UART0_BASE),
-        .irq = {IRQ_UART0, NO_IRQ},
-};
-
-static struct amba_device uart1_device = {
-        .dev = { .init_name = "uart1" },
-        __MEM_4K_RESOURCE(NOMADIK_UART1_BASE),
-        .irq = {IRQ_UART1, NO_IRQ},
-};
+static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE,
+        { IRQ_UART1 }, NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
@@ -255,10 +246,7 @@ static void __init nomadik_timer_init(void)
         src_cr |= SRC_CR_INIT_VAL;
         writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
 
-        /* Save global pointer to mtu, used by platform timer code */
-        mtu_base = io_p2v(NOMADIK_MTU0_BASE);
-
-        nmdk_timer_init();
+        nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE));
 }
 
 static struct sys_timer nomadik_timer = {
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 65df7b4fdd3..27f43a46985 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -97,12 +97,7 @@ static struct platform_device cpu8815_platform_gpio[] = {
         GPIO_DEVICE(3),
 };
 
-static struct amba_device cpu8815_amba_rng = {
-        .dev = {
-                .init_name = "rng",
-        },
-        __MEM_4K_RESOURCE(NOMADIK_RNG_BASE),
-};
+static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL);
 
 static struct platform_device *platform_devs[] __initdata = {
         cpu8815_platform_gpio + 0,
@@ -112,7 +107,7 @@ static struct platform_device *platform_devs[] __initdata = {
 };
 
 static struct amba_device *amba_devs[] __initdata = {
-        &cpu8815_amba_rng
+        &cpu8815_amba_rng_device
 };
 
 static int __init cpu8815_init(void)
diff --git a/arch/arm/mach-nomadik/include/mach/entry-macro.S b/arch/arm/mach-nomadik/include/mach/entry-macro.S
deleted file mode 100644
index 98ea1c1fbba..00000000000
--- a/arch/arm/mach-nomadik/include/mach/entry-macro.S
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Low-level IRQ helper macros for Nomadik platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-nomadik/include/mach/setup.h b/arch/arm/mach-nomadik/include/mach/setup.h
deleted file mode 100644
index bcaeaf41c05..00000000000
--- a/arch/arm/mach-nomadik/include/mach/setup.h
+++ /dev/null
@@ -1,19 +0,0 @@
-
-/*
- * These symbols are needed for board-specific files to call their
- * own cpu-specific files
- */
-
-#ifndef __ASM_ARCH_SETUP_H
-#define __ASM_ARCH_SETUP_H
-
-#include <asm/mach/time.h>
-#include <linux/init.h>
-
-#ifdef CONFIG_NOMADIK_8815
-
-extern void nmdk_timer_init(void);
-
-#endif /* NOMADIK_8815 */
-
-#endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-nomadik/include/mach/system.h b/arch/arm/mach-nomadik/include/mach/system.h
deleted file mode 100644
index 25e198b8976..00000000000
--- a/arch/arm/mach-nomadik/include/mach/system.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  mach-nomadik/include/mach/system.h
- *
- *  Copyright (C) 2008 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 922ab0dc2bc..dfab466ebd1 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -152,6 +152,10 @@ config MACH_AMS_DELTA
         bool "Amstrad E3 (Delta)"
         depends on ARCH_OMAP1 && ARCH_OMAP15XX
         select FIQ
+        select GPIO_GENERIC_PLATFORM
+        select LEDS_GPIO_REGISTER
+        select REGULATOR
+        select REGULATOR_FIXED_VOLTAGE
         help
           Support for the Amstrad E3 (codename Delta) videophone. Say Y here
           if you have such a device.
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index c1c5fb6a5b4..399c4c49722 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -15,11 +15,12 @@
 
 #include <linux/linkage.h>
 
-#include <plat/io.h>
 #include <plat/board-ams-delta.h>
 
 #include <mach/ams-delta-fiq.h>
 
+#include "iomap.h"
+
 /*
  * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c.
  * Unfortunately, those were not placed in a separate header file.
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 152b32c15e2..fcce7ff3763 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -22,6 +22,7 @@
 #include <plat/board-ams-delta.h>
 
 #include <asm/fiq.h>
+
 #include <mach/ams-delta-fiq.h>
 
 static struct fiq_handler fh = {
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index e0e8245f3c9..c1b681ef4cb 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -11,6 +11,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/basic_mmio_gpio.h>
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -18,31 +19,33 @@
 #include <linux/interrupt.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/serial_8250.h>
 #include <linux/export.h>
 #include <linux/omapfb.h>
+#include <linux/io.h>
 
 #include <media/soc_camera.h>
 
 #include <asm/serial.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/io.h>
 #include <plat/board-ams-delta.h>
 #include <plat/keypad.h>
 #include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include "common.h"
-#include <mach/camera.h>
 
+#include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
+#include <mach/camera.h>
 
-static u8 ams_delta_latch1_reg;
-static u16 ams_delta_latch2_reg;
+#include "iomap.h"
+#include "common.h"
 
 static const unsigned int ams_delta_keymap[] = {
         KEY(0, 0, KEY_F1),              /* Advert    */
@@ -122,54 +125,188 @@ static const unsigned int ams_delta_keymap[] = {
         KEY(7, 3, KEY_LEFTCTRL),        /* Vol down  */
 };
 
-void ams_delta_latch1_write(u8 mask, u8 value)
-{
-        ams_delta_latch1_reg &= ~mask;
-        ams_delta_latch1_reg |= value;
-        *(volatile __u8 *) AMS_DELTA_LATCH1_VIRT = ams_delta_latch1_reg;
-}
-
-void ams_delta_latch2_write(u16 mask, u16 value)
-{
-        ams_delta_latch2_reg &= ~mask;
-        ams_delta_latch2_reg |= value;
-        *(volatile __u16 *) AMS_DELTA_LATCH2_VIRT = ams_delta_latch2_reg;
-}
+#define LATCH1_PHYS     0x01000000
+#define LATCH1_VIRT     0xEA000000
+#define MODEM_PHYS      0x04000000
+#define MODEM_VIRT      0xEB000000
+#define LATCH2_PHYS     0x08000000
+#define LATCH2_VIRT     0xEC000000
 
 static struct map_desc ams_delta_io_desc[] __initdata = {
         /* AMS_DELTA_LATCH1 */
         {
-                .virtual        = AMS_DELTA_LATCH1_VIRT,
-                .pfn            = __phys_to_pfn(AMS_DELTA_LATCH1_PHYS),
+                .virtual        = LATCH1_VIRT,
+                .pfn            = __phys_to_pfn(LATCH1_PHYS),
                 .length         = 0x01000000,
                 .type           = MT_DEVICE
         },
         /* AMS_DELTA_LATCH2 */
         {
-                .virtual        = AMS_DELTA_LATCH2_VIRT,
-                .pfn            = __phys_to_pfn(AMS_DELTA_LATCH2_PHYS),
+                .virtual        = LATCH2_VIRT,
+                .pfn            = __phys_to_pfn(LATCH2_PHYS),
                 .length         = 0x01000000,
                 .type           = MT_DEVICE
         },
         /* AMS_DELTA_MODEM */
         {
-                .virtual        = AMS_DELTA_MODEM_VIRT,
-                .pfn            = __phys_to_pfn(AMS_DELTA_MODEM_PHYS),
+                .virtual        = MODEM_VIRT,
+                .pfn            = __phys_to_pfn(MODEM_PHYS),
                 .length         = 0x01000000,
                 .type           = MT_DEVICE
         }
 };
 
-static struct omap_lcd_config ams_delta_lcd_config = {
+static struct omap_lcd_config ams_delta_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_usb_config ams_delta_usb_config __initdata = {
+static struct omap_usb_config ams_delta_usb_config = {
         .register_host  = 1,
         .hmc_mode       = 16,
         .pins[0]        = 2,
 };
 
+#define LATCH1_GPIO_BASE        232
+#define LATCH1_NGPIO            8
+
+static struct resource latch1_resources[] = {
+        [0] = {
+                .name   = "dat",
+                .start  = LATCH1_PHYS,
+                .end    = LATCH1_PHYS + (LATCH1_NGPIO - 1) / 8,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct bgpio_pdata latch1_pdata = {
+        .base   = LATCH1_GPIO_BASE,
+        .ngpio  = LATCH1_NGPIO,
+};
+
+static struct platform_device latch1_gpio_device = {
+        .name           = "basic-mmio-gpio",
+        .id             = 0,
+        .resource       = latch1_resources,
+        .num_resources  = ARRAY_SIZE(latch1_resources),
+        .dev            = {
+                .platform_data  = &latch1_pdata,
+        },
+};
+
+static struct resource latch2_resources[] = {
+        [0] = {
+                .name   = "dat",
+                .start  = LATCH2_PHYS,
+                .end    = LATCH2_PHYS + (AMS_DELTA_LATCH2_NGPIO - 1) / 8,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct bgpio_pdata latch2_pdata = {
+        .base   = AMS_DELTA_LATCH2_GPIO_BASE,
+        .ngpio  = AMS_DELTA_LATCH2_NGPIO,
+};
+
+static struct platform_device latch2_gpio_device = {
+        .name           = "basic-mmio-gpio",
+        .id             = 1,
+        .resource       = latch2_resources,
+        .num_resources  = ARRAY_SIZE(latch2_resources),
+        .dev            = {
+                .platform_data  = &latch2_pdata,
+        },
+};
+
+static const struct gpio latch_gpios[] __initconst = {
+        {
+                .gpio   = LATCH1_GPIO_BASE + 6,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "dockit1",
+        },
+        {
+                .gpio   = LATCH1_GPIO_BASE + 7,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "dockit2",
+        },
+        {
+                .gpio   = AMS_DELTA_GPIO_PIN_SCARD_RSTIN,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "scard_rstin",
+        },
+        {
+                .gpio   = AMS_DELTA_GPIO_PIN_SCARD_CMDVCC,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "scard_cmdvcc",
+        },
+        {
+                .gpio   = AMS_DELTA_GPIO_PIN_MODEM_CODEC,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "modem_codec",
+        },
+        {
+                .gpio   = AMS_DELTA_LATCH2_GPIO_BASE + 14,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "hookflash1",
+        },
+        {
+                .gpio   = AMS_DELTA_LATCH2_GPIO_BASE + 15,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "hookflash2",
+        },
+};
+
+static struct regulator_consumer_supply modem_nreset_consumers[] = {
+        REGULATOR_SUPPLY("RESET#", "serial8250.1"),
+        REGULATOR_SUPPLY("POR", "cx20442-codec"),
+};
+
+static struct regulator_init_data modem_nreset_data = {
+        .constraints            = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+                .boot_on                = 1,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(modem_nreset_consumers),
+        .consumer_supplies      = modem_nreset_consumers,
+};
+
+static struct fixed_voltage_config modem_nreset_config = {
+        .supply_name            = "modem_nreset",
+        .microvolts             = 3300000,
+        .gpio                   = AMS_DELTA_GPIO_PIN_MODEM_NRESET,
+        .startup_delay          = 25000,
+        .enable_high            = 1,
+        .enabled_at_boot        = 1,
+        .init_data              = &modem_nreset_data,
+};
+
+static struct platform_device modem_nreset_device = {
+        .name   = "reg-fixed-voltage",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &modem_nreset_config,
+        },
+};
+
+struct modem_private_data {
+        struct regulator *regulator;
+};
+
+static struct modem_private_data modem_priv;
+
+void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
+{
+        int bit = 0;
+        u16 bitpos = 1 << bit;
+
+        for (; bit < ngpio; bit++, bitpos = bitpos << 1) {
+                if (!(mask & bitpos))
+                        continue;
+                else
+                        gpio_set_value(base + bit, (value & bitpos) != 0);
+        }
+}
+EXPORT_SYMBOL(ams_delta_latch_write);
+
 static struct resource ams_delta_nand_resources[] = {
         [0] = {
                 .start  = OMAP1_MPUIO_BASE,
@@ -199,7 +336,7 @@ static const struct matrix_keymap_data ams_delta_keymap_data = {
         .keymap_size    = ARRAY_SIZE(ams_delta_keymap),
 };
 
-static struct omap_kp_platform_data ams_delta_kp_data __initdata = {
+static struct omap_kp_platform_data ams_delta_kp_data = {
         .rows           = 8,
         .cols           = 8,
         .keymap_data    = &ams_delta_keymap_data,
@@ -221,9 +358,45 @@ static struct platform_device ams_delta_lcd_device = {
         .id     = -1,
 };
 
-static struct platform_device ams_delta_led_device = {
-        .name   = "ams-delta-led",
-        .id     = -1
+static const struct gpio_led gpio_leds[] __initconst = {
+        {
+                .name            = "camera",
+                .gpio            = LATCH1_GPIO_BASE + 0,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+#ifdef CONFIG_LEDS_TRIGGERS
+                .default_trigger = "ams_delta_camera",
+#endif
+        },
+        {
+                .name            = "advert",
+                .gpio            = LATCH1_GPIO_BASE + 1,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "email",
+                .gpio            = LATCH1_GPIO_BASE + 2,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "handsfree",
+                .gpio            = LATCH1_GPIO_BASE + 3,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "voicemail",
+                .gpio            = LATCH1_GPIO_BASE + 4,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "voice",
+                .gpio            = LATCH1_GPIO_BASE + 5,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+};
+
+static const struct gpio_led_platform_data leds_pdata __initconst = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
 };
 
 static struct i2c_board_info ams_delta_camera_board_info[] = {
@@ -272,13 +445,17 @@ static struct omap1_cam_platform_data ams_delta_camera_platform_data = {
 };
 
 static struct platform_device *ams_delta_devices[] __initdata = {
-        &ams_delta_nand_device,
+        &latch1_gpio_device,
+        &latch2_gpio_device,
         &ams_delta_kp_device,
-        &ams_delta_lcd_device,
-        &ams_delta_led_device,
         &ams_delta_camera_device,
 };
 
+static struct platform_device *late_devices[] __initdata = {
+        &ams_delta_nand_device,
+        &ams_delta_lcd_device,
+};
+
 static void __init ams_delta_init(void)
 {
         /* mux pins for uarts */
@@ -302,15 +479,13 @@ static void __init ams_delta_init(void)
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
 
-        /* Clear latch2 (NAND, LCD, modem enable) */
-        ams_delta_latch2_write(~0, 0);
-
         omap1_usb_init(&ams_delta_usb_config);
         omap1_set_camera_info(&ams_delta_camera_platform_data);
 #ifdef CONFIG_LEDS_TRIGGERS
         led_trigger_register_simple("ams_delta_camera",
                         &ams_delta_camera_led_trigger);
 #endif
+        gpio_led_register_device(-1, &leds_pdata);
         platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 
         ams_delta_init_fiq();
@@ -320,16 +495,34 @@ static void __init ams_delta_init(void)
         omapfb_set_lcd_config(&ams_delta_lcd_config);
 }
 
+static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
+{
+        struct modem_private_data *priv = port->private_data;
+
+        if (IS_ERR(priv->regulator))
+                return;
+
+        if (state == old)
+                return;
+
+        if (state == 0)
+                regulator_enable(priv->regulator);
+        else if (old == 0)
+                regulator_disable(priv->regulator);
+}
+
 static struct plat_serial8250_port ams_delta_modem_ports[] = {
         {
-                .membase        = IOMEM(AMS_DELTA_MODEM_VIRT),
-                .mapbase        = AMS_DELTA_MODEM_PHYS,
+                .membase        = IOMEM(MODEM_VIRT),
+                .mapbase        = MODEM_PHYS,
                 .irq            = -EINVAL, /* changed later */
                 .flags          = UPF_BOOT_AUTOCONF,
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .iotype         = UPIO_MEM,
                 .regshift       = 1,
                 .uartclk        = BASE_BAUD * 16,
+                .pm             = modem_pm,
+                .private_data   = &modem_priv,
         },
         { },
 };
@@ -342,13 +535,27 @@ static struct platform_device ams_delta_modem_device = {
         },
 };
 
-static int __init ams_delta_modem_init(void)
+static int __init late_init(void)
 {
         int err;
 
         if (!machine_is_ams_delta())
                 return -ENODEV;
 
+        err = gpio_request_array(latch_gpios, ARRAY_SIZE(latch_gpios));
+        if (err) {
+                pr_err("Couldn't take over latch1/latch2 GPIO pins\n");
+                return err;
+        }
+
+        platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
+
+        err = platform_device_register(&modem_nreset_device);
+        if (err) {
+                pr_err("Couldn't register the modem regulator device\n");
+                return err;
+        }
+
         omap_cfg_reg(M14_1510_GPIO2);
         ams_delta_modem_ports[0].irq =
                         gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
@@ -360,13 +567,35 @@ static int __init ams_delta_modem_init(void)
         }
         gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
 
-        ams_delta_latch2_write(
-                AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC,
-                AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC);
+        /* Initialize the modem_nreset regulator consumer before use */
+        modem_priv.regulator = ERR_PTR(-ENODEV);
+
+        ams_delta_latch2_write(AMS_DELTA_LATCH2_MODEM_CODEC,
+                        AMS_DELTA_LATCH2_MODEM_CODEC);
 
-        return platform_device_register(&ams_delta_modem_device);
+        err = platform_device_register(&ams_delta_modem_device);
+        if (err)
+                goto gpio_free;
+
+        /*
+         * Once the modem device is registered, the modem_nreset
+         * regulator can be requested on behalf of that device.
+         */
+        modem_priv.regulator = regulator_get(&ams_delta_modem_device.dev,
+                        "RESET#");
+        if (IS_ERR(modem_priv.regulator)) {
+                err = PTR_ERR(modem_priv.regulator);
+                goto unregister;
+        }
+        return 0;
+
+unregister:
+        platform_device_unregister(&ams_delta_modem_device);
+gpio_free:
+        gpio_free(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
+        return err;
 }
-arch_initcall(ams_delta_modem_init);
+late_initcall(late_init);
 
 static void __init ams_delta_map_io(void)
 {
@@ -385,6 +614,3 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
         .timer          = &omap1_timer,
         .restart        = omap1_restart,
 MACHINE_END
-
-EXPORT_SYMBOL(ams_delta_latch1_write);
-EXPORT_SYMBOL(ams_delta_latch2_write);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 7afaf3c5bdc..80bd43c7f4e 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -23,7 +23,6 @@
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -33,9 +32,13 @@
 #include <plat/flash.h>
 #include <plat/fpga.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/board.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+#include "common.h"
+
 /* fsample is pretty close to p2-sample */
 
 #define fsample_cpld_read(reg) __raw_readb(reg)
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index af2be8c12c0..c3068622fdc 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -32,8 +32,6 @@
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -44,9 +42,11 @@
 #include <plat/irda.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/flash.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
 #include "board-h2.h"
 
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 7cfd25b9073..64b8584f64c 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -34,21 +34,21 @@
 
 #include <asm/setup.h>
 #include <asm/page.h>
-#include <mach/hardware.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
-#include "common.h"
 #include <plat/flash.h>
 
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#include "common.h"
 #include "board-h3.h"
 
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index af2afcf24f7..827d83a96af 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -27,7 +27,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
-#include <linux/io.h>
+#include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/i2c.h>
@@ -42,7 +42,6 @@
 #include <asm/mach/arch.h>
 
 #include <plat/omap7xx.h>
-#include "common.h"
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/usb.h>
@@ -50,7 +49,7 @@
 
 #include <mach/irqs.h>
 
-#include <linux/delay.h>
+#include "common.h"
 
 /* LCD register definition */
 #define       OMAP_LCDC_CONTROL               (0xfffec000 + 0x00)
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 1d5ab6606b9..61219182d16 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -27,7 +27,6 @@
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -38,9 +37,13 @@
 #include <plat/tc.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/mmc.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+#include "common.h"
+
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define INNOVATOR1610_ETHR_START        0x04000300
 
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 9b6332a31fb..fe95ec5f6f0 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -21,7 +21,6 @@
 #include <linux/workqueue.h>
 #include <linux/delay.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -30,11 +29,14 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/lcd_mipid.h>
 #include <plat/mmc.h>
 #include <plat/clock.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 #define ADS7846_PENDOWN_GPIO    15
 
 static const unsigned int nokia770_keymap[] = {
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index ef874655fbd..1fe347396f4 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -35,15 +35,11 @@
 #include <linux/leds.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
-
 #include <linux/i2c/tps65010.h>
 
-#include <mach/hardware.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -52,6 +48,9 @@
 #include <plat/usb.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
+
+#include <mach/hardware.h>
+
 #include "common.h"
 
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 612342cb2a2..0863d8e2bdf 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -29,7 +29,6 @@
 #include <linux/apm-emulation.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -42,6 +41,9 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
+
+#include <mach/hardware.h>
+
 #include "common.h"
 
 #define PALMTE_USBDETECT_GPIO   0
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index b63350bc88f..4ff699c509c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -25,8 +25,9 @@
 #include <linux/mtd/physmap.h>
 #include <linux/leds.h>
 #include <linux/omapfb.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -40,10 +41,10 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include "common.h"
 
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
+#include <mach/hardware.h>
+
+#include "common.h"
 
 #define PALMTT_USBDETECT_GPIO   0
 #define PALMTT_CABLE_GPIO       1
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 9924c70af09..abcbbd339ae 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -28,8 +28,9 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/omapfb.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -42,10 +43,10 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include "common.h"
 
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
+#include <mach/hardware.h>
+
+#include "common.h"
 
 #define PALMZ71_USBDETECT_GPIO  0
 #define PALMZ71_PENIRQ_GPIO     6
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 8e0153447c6..76d4ee05a81 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -23,7 +23,6 @@
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -33,9 +32,13 @@
 #include <plat/fpga.h>
 #include <plat/flash.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/board.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+#include "common.h"
+
 static const unsigned int p2_keymap[] = {
         KEY(0, 0, KEY_UP),
         KEY(1, 0, KEY_RIGHT),
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0c76e12337d..f34cb74a9f4 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -29,7 +29,6 @@
 #include <linux/export.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -41,10 +40,13 @@
 #include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/board.h>
-#include "common.h"
 #include <plat/keypad.h>
 #include <plat/board-sx1.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
 {
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index f83a502dc93..659d0f75de2 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -27,18 +27,20 @@
 #include <linux/smc91x.h>
 #include <linux/export.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/board-voiceblue.h>
-#include "common.h"
 #include <plat/flash.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
 #include <plat/usb.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 static struct plat_serial8250_port voiceblue_ports[] = {
         {
                 .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x40000),
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 0c50df05d13..67382ddd8c8 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -15,8 +15,8 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
-#include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 #include <linux/clkdev.h>
 
 #include <asm/mach-types.h>
@@ -27,6 +27,9 @@
 #include <plat/sram.h>
 #include <plat/clkdev_omap.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
 #include "clock.h"
 #include "opp.h"
 
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 94699a82a73..c6ce93f71d0 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -15,10 +15,10 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
-#include <linux/io.h>
 
 #include <asm/mach-types.h>  /* for machine_is_* */
 
@@ -28,6 +28,9 @@
 #include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
 #include <plat/usb.h>   /* for OTG_BASE */
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
 #include "clock.h"
 
 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index a9a5146dd2d..af658ad338e 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -58,5 +58,6 @@ void omap1_restart(char, const char *);
 
 extern struct sys_timer omap1_timer;
 extern bool omap_32k_timer_init(void);
+extern void __init omap_init_consistent_dma_size(void);
 
 #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 187b2fe132e..dcd8ddbec2b 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -15,20 +15,20 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
 #include <linux/spi/spi.h>
 
-#include <mach/camera.h>
-#include <mach/hardware.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/mux.h>
 #include <plat/mmc.h>
 #include <plat/omap7xx.h>
 
+#include <mach/camera.h>
+#include <mach/hardware.h>
+
+#include "common.h"
 #include "clock.h"
 
 /*-------------------------------------------------------------------------*/
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index f5a52204b89..3ef7d52316b 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -19,11 +19,11 @@
  */
 
 #include <linux/err.h>
-#include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/io.h>
 
 #include <plat/dma.h>
 #include <plat/tc.h>
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 1749cb37dda..f9bf78d4fdf 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -6,13 +6,15 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 
-#include <plat/io.h>
 #include <plat/tc.h>
 #include <plat/flash.h>
 
+#include <mach/hardware.h>
+
 void omap1_set_vpp(struct platform_device *pdev, int enable)
 {
         static int count;
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 0a17a1a7e00..76c67b3f9f6 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -24,12 +24,15 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
 #include <plat/fpga.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+
 static void fpga_mask_irq(struct irq_data *d)
 {
         unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 399da4ce017..634903ef829 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -42,11 +42,12 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
         .irqstatus      = OMAP_MPUIO_GPIO_INT,
         .irqenable      = OMAP_MPUIO_GPIO_MASKIT,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP_MPUIO_GPIO_INT_EDGE,
 };
 
 static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
-        .bank_type              = METHOD_MPUIO,
+        .is_mpuio               = true,
         .bank_width             = 16,
         .bank_stride            = 1,
         .regs                   = &omap15xx_mpuio_regs,
@@ -83,11 +84,12 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
         .irqstatus      = OMAP1510_GPIO_INT_STATUS,
         .irqenable      = OMAP1510_GPIO_INT_MASK,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP1510_GPIO_INT_CONTROL,
+        .pinctrl        = OMAP1510_GPIO_PIN_CONTROL,
 };
 
 static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
-        .bank_type              = METHOD_GPIO_1510,
         .bank_width             = 16,
         .regs                   = &omap15xx_gpio_regs,
 };
@@ -115,7 +117,6 @@ static int __init omap15xx_gpio_init(void)
         platform_device_register(&omap15xx_mpu_gpio);
         platform_device_register(&omap15xx_gpio);
 
-        gpio_bank_count = 2;
         return 0;
 }
 postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 0f399bd0e70..1fb3b9ad496 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -24,6 +24,9 @@
 #define OMAP1610_GPIO4_BASE             0xfffbbc00
 #define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
 
+/* smart idle, enable wakeup */
+#define SYSCONFIG_WORD                  0x14
+
 /* mpu gpio */
 static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
         {
@@ -45,11 +48,12 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
         .irqstatus      = OMAP_MPUIO_GPIO_INT,
         .irqenable      = OMAP_MPUIO_GPIO_MASKIT,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP_MPUIO_GPIO_INT_EDGE,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
-        .bank_type              = METHOD_MPUIO,
+        .is_mpuio               = true,
         .bank_width             = 16,
         .bank_stride            = 1,
         .regs                   = &omap16xx_mpuio_regs,
@@ -89,11 +93,13 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
         .irqenable      = OMAP1610_GPIO_IRQENABLE1,
         .set_irqenable  = OMAP1610_GPIO_SET_IRQENABLE1,
         .clr_irqenable  = OMAP1610_GPIO_CLEAR_IRQENABLE1,
+        .wkup_en        = OMAP1610_GPIO_WAKEUPENABLE,
+        .edgectrl1      = OMAP1610_GPIO_EDGE_CTRL1,
+        .edgectrl2      = OMAP1610_GPIO_EDGE_CTRL2,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -123,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 16,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -153,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 32,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -183,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 48,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -214,14 +217,42 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {
 static int __init omap16xx_gpio_init(void)
 {
         int i;
+        void __iomem *base;
+        struct resource *res;
+        struct platform_device *pdev;
+        struct omap_gpio_platform_data *pdata;
 
         if (!cpu_is_omap16xx())
                 return -EINVAL;
 
-        for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
-                platform_device_register(omap16xx_gpio_dev[i]);
+        /*
+         * Enable system clock for GPIO module.
+         * The CAM_CLK_CTRL *is* really the right place.
+         */
+        omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
+                                        ULPD_CAM_CLK_CTRL);
+
+        for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
+                pdev = omap16xx_gpio_dev[i];
+                pdata = pdev->dev.platform_data;
+
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (unlikely(!res)) {
+                        dev_err(&pdev->dev, "Invalid mem resource.\n");
+                        return -ENODEV;
+                }
 
-        gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
+                base = ioremap(res->start, resource_size(res));
+                if (unlikely(!base)) {
+                        dev_err(&pdev->dev, "ioremap failed.\n");
+                        return -ENOMEM;
+                }
+
+                __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
+                iounmap(base);
+
+                platform_device_register(omap16xx_gpio_dev[i]);
+        }
 
         return 0;
 }
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 5ab63eab0ff..4771d6b68b9 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -47,12 +47,13 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
         .irqstatus      = OMAP_MPUIO_GPIO_INT / 2,
         .irqenable      = OMAP_MPUIO_GPIO_MASKIT / 2,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
 };
 
 static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
-        .bank_type              = METHOD_MPUIO,
-        .bank_width             = 32,
+        .is_mpuio               = true,
+        .bank_width             = 16,
         .bank_stride            = 2,
         .regs                   = &omap7xx_mpuio_regs,
 };
@@ -88,11 +89,11 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
         .irqstatus      = OMAP7XX_GPIO_INT_STATUS,
         .irqenable      = OMAP7XX_GPIO_INT_MASK,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP7XX_GPIO_INT_CONTROL,
 };
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -122,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 32,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -152,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 64,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -182,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 96,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -212,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 128,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -242,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 160,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -282,8 +278,6 @@ static int __init omap7xx_gpio_init(void)
         for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
                 platform_device_register(omap7xx_gpio_dev[i]);
 
-        gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
-
         return 0;
 }
 postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index b3f3363cd45..2b28e1da14b 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -16,8 +16,11 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <asm/system_info.h>
+
 #include <plat/cpu.h>
 
+#include <mach/hardware.h>
+
 #define OMAP_DIE_ID_0           0xfffe1800
 #define OMAP_DIE_ID_1           0xfffe1804
 #define OMAP_PRODUCTION_ID_0    0xfffe2000
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index bfb4fb1d738..fa0f32a686a 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -9,20 +9,16 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
+
 #include <mach/hardware.h>
 #include <mach/io.h>
 #include <mach/irqs.h>
-#include <asm/hardware/gic.h>
 
-                .macro  disable_fiq
-                .endm
+#include "../../iomap.h"
 
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
                 ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index a3f6287b200..01e35fa106b 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -2,4 +2,40 @@
  * arch/arm/mach-omap1/include/mach/hardware.h
  */
 
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#ifndef __ASSEMBLER__
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+extern u8 omap_readb(u32 pa);
+extern u16 omap_readw(u32 pa);
+extern u32 omap_readl(u32 pa);
+extern void omap_writeb(u8 v, u32 pa);
+extern void omap_writew(u16 v, u32 pa);
+extern void omap_writel(u32 v, u32 pa);
+
+#include <plat/tc.h>
+
+/* Almost all documentation for chip and board memory maps assumes
+ * BM is clear.  Most devel boards have a switch to control booting
+ * from NOR flash (using external chipselect 3) rather than mask ROM,
+ * which uses BM to interchange the physical CS0 and CS3 addresses.
+ */
+static inline u32 omap_cs0m_phys(void)
+{
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
+                        ?  OMAP_CS3_PHYS : 0;
+}
+
+static inline u32 omap_cs3_phys(void)
+{
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
+                        ? 0 : OMAP_CS3_PHYS;
+}
+
+#endif
+#endif
+
 #include <plat/hardware.h>
diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h
index 57bdf74a3e6..37b12e1fd02 100644
--- a/arch/arm/mach-omap1/include/mach/io.h
+++ b/arch/arm/mach-omap1/include/mach/io.h
@@ -1,5 +1,46 @@
 /*
  * arch/arm/mach-omap1/include/mach/io.h
+ *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
  */
 
-#include <plat/io.h>
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
index c6337645ba8..901082def9b 100644
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ b/arch/arm/mach-omap1/include/mach/memory.h
@@ -18,7 +18,8 @@
  * Note that the is_lbus_device() test is not very efficient on 1510
  * because of the strncmp().
  */
-#ifdef CONFIG_ARCH_OMAP15XX
+#if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__)
+#include <plat/cpu.h>
 
 /*
  * OMAP-1510 Local Bus address offset
diff --git a/arch/arm/mach-omap1/include/mach/system.h b/arch/arm/mach-omap1/include/mach/system.h
deleted file mode 100644
index a6c1b3a16df..00000000000
--- a/arch/arm/mach-omap1/include/mach/system.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/system.h
- */
-
-#include <plat/system.h>
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 8e55b6fb347..d969a7203d1 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -15,9 +15,12 @@
 
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
+
 #include <plat/mux.h>
 #include <plat/tc.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "clock.h"
 
 extern void omap_check_revision(void);
@@ -118,7 +121,7 @@ void __init omap16xx_map_io(void)
 /*
  * Common low-level hardware init for omap1.
  */
-void omap1_init_early(void)
+void __init omap1_init_early(void)
 {
         omap_check_revision();
 
diff --git a/arch/arm/mach-omap1/iomap.h b/arch/arm/mach-omap1/iomap.h
new file mode 100644
index 00000000000..d68175761c3
--- /dev/null
+++ b/arch/arm/mach-omap1/iomap.h
@@ -0,0 +1,42 @@
+/*
+ * IO mappings for OMAP1
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x)                (x)
+#else
+#define IOMEM(x)                ((void __force __iomem *)(x))
+#endif
+
+#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
+#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Omap1 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1_IO_PHYS           0xFFFB0000
+#define OMAP1_IO_SIZE           0x40000
+#define OMAP1_IO_VIRT           (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index e5b104b7fce..4448114fab7 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -42,11 +42,13 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
+
 #include <plat/cpu.h>
 
+#include <mach/hardware.h>
+
 #define IRQ_BANK(irq) ((irq) >> 5)
 #define IRQ_BIT(irq)  ((irq) & 0x1f)
 
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 4c5ce7d829c..86ace9aaa66 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -27,9 +27,10 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 
+#include <plat/dma.h>
+
 #include <mach/hardware.h>
 #include <mach/lcdc.h>
-#include <plat/dma.h>
 
 int omap_lcd_dma_running(void)
 {
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 3e8410a9999..adf00975b9b 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -19,12 +19,15 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <mach/irqs.h>
 #include <plat/dma.h>
 #include <plat/mux.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
 
+#include <mach/irqs.h>
+
+#include "iomap.h"
+
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
 
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 89ea20ca0cc..306beaca14c 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -42,14 +42,13 @@
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/atomic.h>
 
 #include <asm/irq.h>
-#include <linux/atomic.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
 #include <plat/cpu.h>
-#include <mach/irqs.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/tc.h>
@@ -57,6 +56,9 @@
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 
+#include <mach/irqs.h>
+
+#include "iomap.h"
 #include "pm.h"
 
 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
@@ -108,13 +110,7 @@ void omap1_pm_idle(void)
         __u32 use_idlect1 = arm_idlect1_mask;
         int do_sleep = 0;
 
-        local_irq_disable();
         local_fiq_disable();
-        if (need_resched()) {
-                local_fiq_enable();
-                local_irq_enable();
-                return;
-        }
 
 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
 #warning Enable 32kHz OS timer in order to allow sleep states in idle
@@ -157,14 +153,12 @@ void omap1_pm_idle(void)
                 omap_writel(saved_idlect1, ARM_IDLECT1);
 
                 local_fiq_enable();
-                local_irq_enable();
                 return;
         }
         omap_sram_suspend(omap_readl(ARM_IDLECT1),
                           omap_readl(ARM_IDLECT2));
 
         local_fiq_enable();
-        local_irq_enable();
 }
 
 /*
@@ -583,8 +577,6 @@ static void omap_pm_init_proc(void)
 
 #endif /* DEBUG && CONFIG_PROC_FS */
 
-static void (*saved_idle)(void) = NULL;
-
 /*
  *      omap_pm_prepare - Do preliminary suspend work.
  *
@@ -592,8 +584,7 @@ static void (*saved_idle)(void) = NULL;
 static int omap_pm_prepare(void)
 {
         /* We cannot sleep in idle until we have resumed */
-        saved_idle = pm_idle;
-        pm_idle = NULL;
+        disable_hlt();
 
         return 0;
 }
@@ -630,7 +621,7 @@ static int omap_pm_enter(suspend_state_t state)
 
 static void omap_pm_finish(void)
 {
-        pm_idle = saved_idle;
+        enable_hlt();
 }
 
 
@@ -687,7 +678,7 @@ static int __init omap_pm_init(void)
                 return -ENODEV;
         }
 
-        pm_idle = omap1_pm_idle;
+        arm_pm_idle = omap1_pm_idle;
 
         if (cpu_is_omap7xx())
                 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 91d199b6497..f255b153b86 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -4,9 +4,10 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <plat/prcm.h>
 
+#include <mach/hardware.h>
+
 void omap1_restart(char mode, const char *cmd)
 {
         /*
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index c875bdc902c..0779db150da 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -33,8 +33,12 @@
  */
 
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
+
 #include <mach/io.h>
+
+#include "iomap.h"
 #include "pm.h"
 
                 .text
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 692587d07ea..2ce0b9ab20e 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -9,10 +9,14 @@
  */
 
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
+
 #include <mach/io.h>
 #include <mach/hardware.h>
 
+#include "iomap.h"
+
         .text
 
 /*
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 7595e0ac225..4d8dd9a1b04 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -44,14 +44,15 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/sched_clock.h>
 
+#include <mach/hardware.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
+#include "iomap.h"
 #include "common.h"
 
 #ifdef CONFIG_OMAP_MPU_TIMER
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 10bcd1364cd..325b9a0aa4a 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,14 +46,17 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include "common.h"
+
 #include <plat/dmtimer.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 /*
  * ---------------------------------------------------------------------------
  * 32KHz OS timer
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e20c8ab80b0..8141b76283a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -32,7 +32,7 @@ config ARCH_OMAP3
         depends on ARCH_OMAP2PLUS
         default y
         select CPU_V7
-        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARCH_HAS_OPP
         select PM_OPP if PM
         select ARM_CPU_SUSPEND if PM
@@ -52,7 +52,7 @@ config ARCH_OMAP4
         select ARM_ERRATA_720789
         select ARCH_HAS_OPP
         select PM_OPP if PM
-        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
 
 comment "OMAP Core Type"
@@ -117,7 +117,6 @@ comment "OMAP Board Type"
 config MACH_OMAP_GENERIC
         bool "Generic OMAP2+ board"
         depends on ARCH_OMAP2PLUS
-        select USE_OF
         default y
         help
           Support for generic TI OMAP2+ boards using Flattened Device Tree.
@@ -245,10 +244,11 @@ config MACH_NOKIA_N8X0
         select MACH_NOKIA_N810_WIMAX
 
 config MACH_NOKIA_RM680
-        bool "Nokia RM-680 board"
+        bool "Nokia RM-680/696 board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select MACH_NOKIA_RM696
 
 config MACH_NOKIA_RX51
         bool "Nokia RX-51 board"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 06326a6e460..49f92bc1c31 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o
 
 omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
@@ -25,7 +25,6 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 
 # SMP support ONLY available for OMAP4
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
-obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o \
                                            sleep44xx.o
@@ -184,9 +183,6 @@ obj-$(CONFIG_OMAP_IOMMU)		+= iommu2.o
 iommu-$(CONFIG_OMAP_IOMMU)              := omap-iommu.o
 obj-y                                   += $(iommu-m) $(iommu-y)
 
-i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
-obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
-
 ifneq ($(CONFIG_TIDSPBRIDGE),)
 obj-y                                   += dsp.o
 endif
@@ -270,6 +266,11 @@ obj-y					+= $(smc91x-m) $(smc91x-y)
 
 smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
 obj-y                                   += $(smsc911x-m) $(smsc911x-y)
-obj-$(CONFIG_ARCH_OMAP4)                += hwspinlock.o
+ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
+obj-y                                   += hwspinlock.o
+endif
+
+emac-$(CONFIG_TI_DAVINCI_EMAC)          := am35xx-emac.o
+obj-y                                   += $(emac-m) $(emac-y)
 
 obj-y                                   += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
new file mode 100644
index 00000000000..1f97e747520
--- /dev/null
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on mach-omap2/board-am3517evm.c
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ * Author: Ranjith Lohithakshan <ranjithl@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/davinci_emac.h>
+#include <linux/platform_device.h>
+#include <plat/irqs.h>
+#include <mach/am35xx.h>
+
+#include "control.h"
+
+static struct mdio_platform_data am35xx_emac_mdio_pdata;
+
+static struct resource am35xx_emac_mdio_resources[] = {
+        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
+};
+
+static struct platform_device am35xx_emac_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(am35xx_emac_mdio_resources),
+        .resource       = am35xx_emac_mdio_resources,
+        .dev.platform_data = &am35xx_emac_mdio_pdata,
+};
+
+static void am35xx_enable_emac_int(void)
+{
+        u32 regval;
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_RX_THRESH_CLR);
+        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+static void am35xx_disable_emac_int(void)
+{
+        u32 regval;
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+static struct emac_platform_data am35xx_emac_pdata = {
+        .ctrl_reg_offset        = AM35XX_EMAC_CNTRL_OFFSET,
+        .ctrl_mod_reg_offset    = AM35XX_EMAC_CNTRL_MOD_OFFSET,
+        .ctrl_ram_offset        = AM35XX_EMAC_CNTRL_RAM_OFFSET,
+        .ctrl_ram_size          = AM35XX_EMAC_CNTRL_RAM_SIZE,
+        .hw_ram_addr            = AM35XX_EMAC_HW_RAM_ADDR,
+        .version                = EMAC_VERSION_2,
+        .interrupt_enable       = am35xx_enable_emac_int,
+        .interrupt_disable      = am35xx_disable_emac_int,
+};
+
+static struct resource am35xx_emac_resources[] = {
+        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
+};
+
+static struct platform_device am35xx_emac_device = {
+        .name           = "davinci_emac",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(am35xx_emac_resources),
+        .resource       = am35xx_emac_resources,
+        .dev            = {
+                .platform_data  = &am35xx_emac_pdata,
+        },
+};
+
+void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
+{
+        unsigned int regval;
+        int err;
+
+        am35xx_emac_pdata.rmii_en = rmii_en;
+        am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
+        err = platform_device_register(&am35xx_emac_device);
+        if (err) {
+                pr_err("AM35x: failed registering EMAC device: %d\n", err);
+                return;
+        }
+
+        err = platform_device_register(&am35xx_emac_mdio_device);
+        if (err) {
+                pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
+                platform_device_unregister(&am35xx_emac_device);
+                return;
+        }
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+        regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+}
diff --git a/arch/arm/mach-omap2/am35xx-emac.h b/arch/arm/mach-omap2/am35xx-emac.h
new file mode 100644
index 00000000000..15c6f9ce59a
--- /dev/null
+++ b/arch/arm/mach-omap2/am35xx-emac.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define AM35XX_DEFAULT_MDIO_FREQUENCY   1000000
+
+#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
+void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en);
+#else
+static inline void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) {}
+#endif
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983f809..c8bda62900d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -279,7 +279,7 @@ static void __init omap_2430sdp_init(void)
         platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
         omap2_usbfs_init(&sdp2430_usb_config);
 
         omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 383717ba63b..da75f239873 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -232,11 +232,13 @@ static struct omap2_hsmmc_info mmc[] = {
                  */
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 4,
+                .deferred       = true,
         },
         {
                 .mmc            = 2,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 7,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -249,7 +251,7 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
          */
         mmc[0].gpio_cd = gpio + 0;
         mmc[1].gpio_cd = gpio + 1;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
         gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
@@ -606,6 +608,7 @@ static void __init omap_3430sdp_init(void)
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_board_config = sdp3430_config;
         omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+        omap_hsmmc_init(mmc);
         omap3430_i2c_init();
         omap_display_init(&sdp3430_dss_data);
         if (omap_rev() > OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 44cf1893829..37dcb1bc025 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -324,7 +324,10 @@ static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
                 .bus_num                = 1,
                 .chip_select            = 0,
                 .max_speed_hz           = 24000000,
-                .irq                    = ETH_KS8851_IRQ,
+                /*
+                 * .irq is set to gpio_to_irq(ETH_KS8851_IRQ)
+                 * in omap_4430sdp_init
+                 */
         },
 };
 
@@ -487,21 +490,22 @@ static struct platform_device omap_vwlan_device = {
 
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
-        int ret = 0;
+        int irq = 0;
         struct platform_device *pdev = container_of(dev,
                                 struct platform_device, dev);
         struct omap_mmc_platform_data *pdata = dev->platform_data;
 
         /* Setting MMC1 Card detect Irq */
         if (pdev->id == 0) {
-                ret = twl6030_mmc_card_detect_config();
-                if (ret)
+                irq = twl6030_mmc_card_detect_config();
+                if (irq < 0) {
                         pr_err("Failed configuring MMC1 card detect\n");
-                pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
-                                                MMCDETECT_INTR_OFFSET;
+                        return irq;
+                }
+                pdata->slots[0].card_detect_irq = irq;
                 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
         }
-        return ret;
+        return 0;
 }
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
@@ -521,9 +525,9 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
         struct omap2_hsmmc_info *c;
 
-        omap2_hsmmc_init(controllers);
+        omap_hsmmc_init(controllers);
         for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(c->dev);
+                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4b1cfe32e6b..3645285a3e2 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -39,124 +39,11 @@
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-dvi.h>
 
+#include "am35xx-emac.h"
 #include "mux.h"
 #include "control.h"
 #include "hsmmc.h"
 
-#define AM35XX_EVM_MDIO_FREQUENCY       (1000000)
-
-static struct mdio_platform_data am3517_evm_mdio_pdata = {
-        .bus_freq       = AM35XX_EVM_MDIO_FREQUENCY,
-};
-
-static struct resource am3517_mdio_resources[] = {
-        {
-                .start  = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET,
-                .end    = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET +
-                          SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device am3517_mdio_device = {
-        .name           = "davinci_mdio",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(am3517_mdio_resources),
-        .resource       = am3517_mdio_resources,
-        .dev.platform_data = &am3517_evm_mdio_pdata,
-};
-
-static struct emac_platform_data am3517_evm_emac_pdata = {
-        .rmii_en        = 1,
-};
-
-static struct resource am3517_emac_resources[] = {
-        {
-                .start  = AM35XX_IPSS_EMAC_BASE,
-                .end    = AM35XX_IPSS_EMAC_BASE + 0x2FFFF,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
-                .end    = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
-                .end    = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
-                .end    = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
-                .end    = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device am3517_emac_device = {
-        .name           = "davinci_emac",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(am3517_emac_resources),
-        .resource       = am3517_emac_resources,
-};
-
-static void am3517_enable_ethernet_int(void)
-{
-        u32 regval;
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-                AM35XX_CPGMAC_C0_TX_PULSE_CLR |
-                AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
-                AM35XX_CPGMAC_C0_RX_THRESH_CLR);
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-static void am3517_disable_ethernet_int(void)
-{
-        u32 regval;
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-                AM35XX_CPGMAC_C0_TX_PULSE_CLR);
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
-{
-        unsigned int regval;
-
-        pdata->ctrl_reg_offset          = AM35XX_EMAC_CNTRL_OFFSET;
-        pdata->ctrl_mod_reg_offset      = AM35XX_EMAC_CNTRL_MOD_OFFSET;
-        pdata->ctrl_ram_offset          = AM35XX_EMAC_CNTRL_RAM_OFFSET;
-        pdata->ctrl_ram_size            = AM35XX_EMAC_CNTRL_RAM_SIZE;
-        pdata->version                  = EMAC_VERSION_2;
-        pdata->hw_ram_addr              = AM35XX_EMAC_HW_RAM_ADDR;
-        pdata->interrupt_enable         = am3517_enable_ethernet_int;
-        pdata->interrupt_disable        = am3517_disable_ethernet_int;
-        am3517_emac_device.dev.platform_data    = pdata;
-        platform_device_register(&am3517_emac_device);
-        platform_device_register(&am3517_mdio_device);
-        clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev),
-                      NULL, &am3517_emac_device.dev);
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-        regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
-        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
-        return ;
-}
-
-
-
 #define LCD_PANEL_PWR           176
 #define LCD_PANEL_BKLIGHT_PWR   182
 #define LCD_PANEL_PWM           181
@@ -498,13 +385,13 @@ static void __init am3517_evm_init(void)
         i2c_register_board_info(1, am3517evm_i2c1_boardinfo,
                                 ARRAY_SIZE(am3517evm_i2c1_boardinfo));
         /*Ethernet*/
-        am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
+        am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 
         /* MUSB */
         am3517_evm_musb_init();
 
         /* MMC init function */
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
 }
 
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index d73316ed420..41b0a2fe0b0 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -280,7 +280,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
 
 static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
 };
 
 static struct tdo24m_platform_data tdo24m_config = {
@@ -413,7 +412,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
-
+                .deferred       = true,
         },
         {
                 .mmc            = 2,
@@ -471,7 +470,7 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         return 0;
 }
@@ -639,6 +638,7 @@ static void __init cm_t3x_common_init(void)
         omap_serial_init();
         omap_sdrc_init(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
+        omap_hsmmc_init(mmc);
         cm_t35_init_i2c();
         omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
         cm_t35_init_ethernet();
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index f36d694d215..9e66e167e4f 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -49,6 +49,7 @@
 #include "mux.h"
 #include "control.h"
 #include "common-board-devices.h"
+#include "am35xx-emac.h"
 
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 static struct gpio_led cm_t3517_leds[] = {
@@ -291,6 +292,7 @@ static void __init cm_t3517_init(void)
         cm_t3517_init_rtc();
         cm_t3517_init_usbh();
         cm_t3517_init_hecc();
+        am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
 
 MACHINE_START(CM_T3517, "Compulab CM-T3517")
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index e873063f4fd..11cd2a80609 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -100,6 +100,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .mmc            = 1,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -228,7 +229,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -636,6 +637,7 @@ static void __init devkit8000_init(void)
 
         omap_dm9000_init();
 
+        omap_hsmmc_init(mmc);
         devkit8000_i2c_init();
         platform_add_devices(devkit8000_devices,
                         ARRAY_SIZE(devkit8000_devices));
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 30a6f527510..0349fd2b68d 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -189,7 +189,7 @@ unmap:
  *
  * @return - void.
  */
-void board_flash_init(struct flash_partitions partition_info[],
+void __init board_flash_init(struct flash_partitions partition_info[],
                         char chip_sel_board[][GPMC_CS_NUM], int nand_type)
 {
         u8              cs = 0;
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 45fdfe2bd9d..74e1687b517 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/io.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>
@@ -24,33 +25,23 @@
 #include "common.h"
 #include "common-board-devices.h"
 
-/*
- * XXX: Still needed to boot until the i2c & twl driver is adapted to
- * device-tree
- */
-#ifdef CONFIG_ARCH_OMAP4
-static struct twl4030_platform_data sdp4430_twldata = {
-        .irq_base       = TWL6030_IRQ_BASE,
-        .irq_end        = TWL6030_IRQ_END,
-};
-
-static void __init omap4_i2c_init(void)
-{
-        omap4_pmic_init("twl6030", &sdp4430_twldata);
-}
+#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+#define omap_intc_of_init       NULL
+#endif
+#ifndef CONFIG_ARCH_OMAP4
+#define gic_of_init             NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct twl4030_platform_data beagle_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
+static struct of_device_id irq_match[] __initdata = {
+        { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { }
 };
 
-static void __init omap3_i2c_init(void)
+static void __init omap_init_irq(void)
 {
-        omap3_pmic_init("twl4030", &beagle_twldata);
+        of_irq_init(irq_match);
 }
-#endif
 
 static struct of_device_id omap_dt_match_table[] __initdata = {
         { .compatible = "simple-bus", },
@@ -58,51 +49,24 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
         { }
 };
 
-static struct of_device_id intc_match[] __initdata = {
-        { .compatible = "ti,omap3-intc", },
-        { .compatible = "arm,cortex-a9-gic", },
-        { }
-};
-
 static void __init omap_generic_init(void)
 {
-        struct device_node *node = of_find_matching_node(NULL, intc_match);
-        if (node)
-                irq_domain_add_legacy(node, 32, 0, 0, &irq_domain_simple_ops, NULL);
-
         omap_sdrc_init(NULL, NULL);
 
         of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
 }
 
-#ifdef CONFIG_ARCH_OMAP4
-static void __init omap4_init(void)
-{
-        omap4_i2c_init();
-        omap_generic_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static void __init omap3_init(void)
-{
-        omap3_i2c_init();
-        omap_generic_init();
-}
-#endif
-
-#if defined(CONFIG_SOC_OMAP2420)
+#ifdef CONFIG_SOC_OMAP2420
 static const char *omap242x_boards_compat[] __initdata = {
         "ti,omap2420",
         NULL,
 };
 
 DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap242x_map_io,
         .init_early     = omap2420_init_early,
-        .init_irq       = omap2_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -111,18 +75,17 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
-#if defined(CONFIG_SOC_OMAP2430)
+#ifdef CONFIG_SOC_OMAP2430
 static const char *omap243x_boards_compat[] __initdata = {
         "ti,omap2430",
         NULL,
 };
 
 DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap243x_map_io,
         .init_early     = omap2430_init_early,
-        .init_irq       = omap2_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -131,18 +94,33 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
-#if defined(CONFIG_ARCH_OMAP3)
+#ifdef CONFIG_ARCH_OMAP3
+static struct twl4030_platform_data beagle_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+};
+
+static void __init omap3_i2c_init(void)
+{
+        omap3_pmic_init("twl4030", &beagle_twldata);
+}
+
+static void __init omap3_init(void)
+{
+        omap3_i2c_init();
+        omap_generic_init();
+}
+
 static const char *omap3_boards_compat[] __initdata = {
         "ti,omap3",
         NULL,
 };
 
 DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
-        .init_irq       = omap3_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap3_init,
         .timer          = &omap3_timer,
@@ -151,18 +129,33 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
-#if defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP4
+static struct twl4030_platform_data sdp4430_twldata = {
+        .irq_base       = TWL6030_IRQ_BASE,
+        .irq_end        = TWL6030_IRQ_END,
+};
+
+static void __init omap4_i2c_init(void)
+{
+        omap4_pmic_init("twl6030", &sdp4430_twldata);
+}
+
+static void __init omap4_init(void)
+{
+        omap4_i2c_init();
+        omap_generic_init();
+}
+
 static const char *omap4_boards_compat[] __initdata = {
         "ti,omap4",
         NULL,
 };
 
 DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
-        .init_irq       = gic_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = omap4_init,
         .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index a59ace0ed56..e558800adfd 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -295,6 +295,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
+                .deferred       = true,
         },
 #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
         {
@@ -402,7 +403,7 @@ static int igep_twl_gpio_setup(struct device *dev,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
 #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
@@ -639,6 +640,9 @@ static void __init igep_init(void)
 
         /* Get IGEP2 hardware revision */
         igep2_get_revision();
+
+        omap_hsmmc_init(mmc);
+
         /* Register I2C busses and drivers */
         igep_i2c_init();
         platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 2d2a61f7dcb..d50a562adfa 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -27,7 +27,6 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
-#include <linux/gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -424,7 +423,7 @@ static void __init omap_ldp_init(void)
         board_nand_init(ldp_nand_partitions,
                 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
 
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
         ldp_display_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 67226271760..518091c5f77 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -36,10 +36,6 @@
 
 #include "mux.h"
 
-static int slot1_cover_open;
-static int slot2_cover_open;
-static struct device *mmc_device;
-
 #define TUSB6010_ASYNC_CS       1
 #define TUSB6010_SYNC_CS        4
 #define TUSB6010_GPIO_INT       58
@@ -137,7 +133,6 @@ static void __init n8x0_usb_init(void) {}
 
 static struct omap2_mcspi_device_config p54spi_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct spi_board_info n800_spi_board_info[] __initdata = {
@@ -211,6 +206,10 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
 #define N810_EMMC_VSD_GPIO      23
 #define N810_EMMC_VIO_GPIO      9
 
+static int slot1_cover_open;
+static int slot2_cover_open;
+static struct device *mmc_device;
+
 static int n8x0_mmc_switch_slot(struct device *dev, int slot)
 {
 #ifdef CONFIG_MMC_DEBUG
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7ffcd2839e7..7be8d659d91 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -253,6 +253,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .mmc            = 1,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -272,12 +273,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
 {
         int r;
 
-        if (beagle_config.mmc1_gpio_wp != -EINVAL)
-                omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
         mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /*
          * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
@@ -521,6 +520,11 @@ static void __init omap3_beagle_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3_beagle_init_rev();
+
+        if (beagle_config.mmc1_gpio_wp != -EINVAL)
+                omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+        omap_hsmmc_init(mmc);
+
         omap3_beagle_i2c_init();
 
         gpio_buttons[0].gpio = beagle_config.usr_button_gpio;
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236a844..a659e198892 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -317,6 +317,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 63,
+                .deferred       = true,
         },
 #ifdef CONFIG_WL12XX_PLATFORM_DATA
         {
@@ -361,9 +362,8 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
         int r, lcd_bl_en;
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /*
          * Most GPIOs are for USB OTG.  Some are mostly sent to
@@ -644,6 +644,9 @@ static void __init omap3_evm_init(void)
         omap_board_config = omap3_evm_config;
         omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
 
+        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
+        omap_hsmmc_init(mmc);
+
         omap3_evm_i2c_init();
 
         omap_display_init(&omap3_evm_dss_data);
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 4198dd017d8..4a7d8c8a75d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -128,7 +128,7 @@ static void __init board_mmc_init(void)
                 return;
         }
 
-        omap2_hsmmc_init(board_mmc_info);
+        omap_hsmmc_init(board_mmc_info);
 }
 
 static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
@@ -205,6 +205,7 @@ static void __init omap3logic_init(void)
 
 MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
         .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
@@ -216,6 +217,7 @@ MACHINE_END
 
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
         .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 1644b73017f..33d995d0f07 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -121,6 +121,11 @@ static struct platform_device pandora_leds_gpio = {
         },
 };
 
+static struct platform_device pandora_backlight = {
+        .name   = "pandora-backlight",
+        .id     = -1,
+};
+
 #define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr) \
 {                                                               \
         .gpio           = gpio_num,                             \
@@ -273,6 +278,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 126,
                 .ext_clock      = 0,
+                .deferred       = true,
         },
         {
                 .mmc            = 2,
@@ -281,6 +287,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
                 .gpio_wp        = 127,
                 .ext_clock      = 1,
                 .transceiver    = true,
+                .deferred       = true,
         },
         {
                 .mmc            = 3,
@@ -300,7 +307,7 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
         /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
         omap3pandora_mmc[0].gpio_cd = gpio + 0;
         omap3pandora_mmc[1].gpio_cd = gpio + 1;
-        omap2_hsmmc_init(omap3pandora_mmc);
+        omap_hsmmc_late_init(omap3pandora_mmc);
 
         /* gpio + 13 drives 32kHz buffer for wifi module */
         gpio_32khz = gpio + 13;
@@ -343,7 +350,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
 };
 
 static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
-        REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
+        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
 };
 
 /* ads7846 on SPI and 2 nub controllers on I2C */
@@ -476,6 +483,10 @@ static struct platform_device pandora_vwlan_device = {
 
 static struct twl4030_bci_platform_data pandora_bci_data;
 
+static struct twl4030_power_data pandora_power_data = {
+        .use_poweroff   = true,
+};
+
 static struct twl4030_platform_data omap3pandora_twldata = {
         .gpio           = &omap3pandora_gpio_data,
         .vmmc1          = &pandora_vmmc1,
@@ -486,6 +497,7 @@ static struct twl4030_platform_data omap3pandora_twldata = {
         .vsim           = &pandora_vsim,
         .keypad         = &pandora_kp_data,
         .bci            = &pandora_bci_data,
+        .power          = &pandora_power_data,
 };
 
 static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
@@ -557,17 +569,18 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
         &pandora_vwlan_device,
+        &pandora_backlight,
 };
 
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
-        .reset_gpio_port[0]  = 16,
-        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = 16,
         .reset_gpio_port[2]  = -EINVAL
 };
 
@@ -580,6 +593,7 @@ static struct omap_board_mux board_mux[] __initdata = {
 static void __init omap3pandora_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_hsmmc_init(omap3pandora_mmc);
         omap3pandora_i2c_init();
         pandora_wl1251_init();
         platform_add_devices(omap3pandora_devices,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index cb089a46f62..64100438079 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -209,10 +209,11 @@ static struct regulator_init_data omap3stalker_vsim = {
 
 static struct omap2_hsmmc_info mmc[] = {
         {
-         .mmc           = 1,
-         .caps          = MMC_CAP_4_BIT_DATA,
-         .gpio_cd       = -EINVAL,
-         .gpio_wp       = 23,
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = 23,
+                .deferred       = true,
          },
         {}                      /* Terminator */
 };
@@ -282,9 +283,8 @@ omap3stalker_twl_gpio_setup(struct device *dev,
                             unsigned gpio, unsigned ngpio)
 {
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        omap_mux_init_gpio(23, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /*
          * Most GPIOs are for USB OTG.  Some are mostly sent to
@@ -425,6 +425,9 @@ static void __init omap3_stalker_init(void)
         omap_board_config = omap3_stalker_config;
         omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
 
+        omap_mux_init_gpio(23, OMAP_PIN_INPUT);
+        omap_hsmmc_init(mmc);
+
         omap3_stalker_i2c_init();
 
         platform_add_devices(omap3_stalker_devices,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index c4f55a8cc71..ae2251fa4a6 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -101,6 +101,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .mmc            = 1,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -118,15 +119,9 @@ static struct gpio_led gpio_leds[];
 static int touchbook_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
-                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
-                mmc[0].gpio_wp = 23;
-        } else {
-                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
-        }
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* REVISIT: need ehci-omap hooks for external VBUS
          * power switch and overcurrent detect
@@ -352,6 +347,14 @@ static void __init omap3_touchbook_init(void)
 
         pm_power_off = omap3_touchbook_poweroff;
 
+        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
+                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
+                mmc[0].gpio_wp = 23;
+        } else {
+                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
+        }
+        omap_hsmmc_init(mmc);
+
         omap3_touchbook_i2c_init();
         platform_add_devices(omap3_touchbook_devices,
                         ARRAY_SIZE(omap3_touchbook_devices));
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index e4415917693..8bf8e99c358 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -116,10 +116,16 @@ static struct platform_device panda_abe_audio = {
         },
 };
 
+static struct platform_device btwilink_device = {
+        .name   = "btwilink",
+        .id     = -1,
+};
+
 static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
         &wl1271_device,
         &panda_abe_audio,
+        &btwilink_device,
 };
 
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
@@ -232,7 +238,7 @@ struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
 
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
-        int ret = 0;
+        int irq = 0;
         struct platform_device *pdev = container_of(dev,
                                 struct platform_device, dev);
         struct omap_mmc_platform_data *pdata = dev->platform_data;
@@ -243,14 +249,15 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
         }
         /* Setting MMC1 Card detect Irq */
         if (pdev->id == 0) {
-                ret = twl6030_mmc_card_detect_config();
-                 if (ret)
+                irq = twl6030_mmc_card_detect_config();
+                if (irq < 0) {
                         dev_err(dev, "%s: Error card detect config(%d)\n",
-                                __func__, ret);
-                 else
-                        pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+                                __func__, irq);
+                        return irq;
+                }
+                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
         }
-        return ret;
+        return 0;
 }
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
@@ -271,9 +278,9 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
         struct omap2_hsmmc_info *c;
 
-        omap2_hsmmc_init(controllers);
+        omap_hsmmc_init(controllers);
         for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(c->dev);
+                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
 
         return 0;
 }
@@ -504,7 +511,7 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
         .default_device = &omap4_panda_dvi_device,
 };
 
-void omap4_panda_display_init(void)
+void __init omap4_panda_display_init(void)
 {
         int r;
 
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 52c0cef7716..668533e2a37 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -407,8 +407,6 @@ static inline void __init overo_init_keys(void) { return; }
 static int overo_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        omap2_hsmmc_init(mmc);
-
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -505,6 +503,7 @@ static void __init overo_init(void)
         int ret;
 
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_hsmmc_init(mmc);
         overo_i2c_init();
         omap_display_init(&overo_dss_data);
         omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 8678b386c6a..ae53d71f0ce 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -1,5 +1,5 @@
 /*
- * Board support file for Nokia RM-680.
+ * Board support file for Nokia RM-680/696.
  *
  * Copyright (C) 2010 Nokia
  *
@@ -120,7 +120,7 @@ static void __init rm680_peripherals_init(void)
                                 ARRAY_SIZE(rm680_peripherals_devices));
         rm680_i2c_init();
         gpmc_onenand_init(board_onenand_data);
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -154,3 +154,15 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
         .timer          = &omap3_timer,
         .restart        = omap_prcm_restart,
 MACHINE_END
+
+MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
+        .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3630_init_early,
+        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
+        .init_machine   = rm680_init,
+        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 2bf84fda181..f120997309a 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -139,17 +139,14 @@ static struct lp5523_platform_data rx51_lp5523_platform_data = {
 
 static struct omap2_mcspi_device_config wl1251_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct omap2_mcspi_device_config mipid_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
@@ -1106,6 +1103,11 @@ static struct tsc2005_platform_data tsc2005_pdata = {
         .esd_timeout_ms         = 8000,
 };
 
+static struct gpio rx51_tsc2005_gpios[] __initdata = {
+        { RX51_TSC2005_IRQ_GPIO,   GPIOF_IN,            "tsc2005 IRQ"   },
+        { RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "tsc2005 reset" },
+};
+
 static void rx51_tsc2005_set_reset(bool enable)
 {
         gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
@@ -1115,20 +1117,18 @@ static void __init rx51_init_tsc2005(void)
 {
         int r;
 
-        r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
-        if (r < 0) {
-                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
-                rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
-        }
+        omap_mux_init_gpio(RX51_TSC2005_RESET_GPIO, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(RX51_TSC2005_IRQ_GPIO, OMAP_PIN_INPUT_PULLUP);
 
-        r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
-                "tsc2005 reset");
-        if (r >= 0) {
-                tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
-        } else {
-                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
+        r = gpio_request_array(rx51_tsc2005_gpios,
+                               ARRAY_SIZE(rx51_tsc2005_gpios));
+        if (r < 0) {
+                printk(KERN_ERR "tsc2005 board initialization failed\n");
                 tsc2005_pdata.esd_timeout_ms = 0;
+                return;
         }
+
+        tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
 }
 
 void __init rx51_peripherals_init(void)
@@ -1146,7 +1146,7 @@ void __init rx51_peripherals_init(void)
 
         partition = omap_mux_get("core");
         if (partition)
-                omap2_hsmmc_init(mmc);
+                omap_hsmmc_init(mmc);
 
         rx51_charger_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index d4683ba5f72..a43a765dd09 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -55,6 +55,7 @@ static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
 
 static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
 {
+#ifdef CONFIG_TWL4030_CORE
         unsigned char c;
         u8 mux_pwm, enb_pwm;
 
@@ -90,6 +91,9 @@ static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
         c = ((50 * (100 - level)) / 100) + 1;
         twl_i2c_write_u8(TWL4030_MODULE_PWM1, 0x7F, TWL_LED_PWMOFF);
         twl_i2c_write_u8(TWL4030_MODULE_PWM1, c, TWL_LED_PWMON);
+#else
+        pr_warn("Backlight not enabled\n");
+#endif
 
         return 0;
 }
@@ -117,7 +121,6 @@ static struct omap_dss_board_info zoom_dss_data = {
 
 static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
         .turbo_mode             = 1,
-        .single_channel = 1,  /* 0: slave, 1: master */
 };
 
 static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c126461836a..3d39cdb2e25 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -205,6 +205,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_wp        = -EINVAL,
                 .power_saving   = true,
+                .deferred       = true,
         },
         {
                 .name           = "internal",
@@ -233,7 +234,7 @@ static int zoom_twl_gpio_setup(struct device *dev,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
                                "lcd enable");
@@ -301,6 +302,7 @@ void __init zoom_peripherals_init(void)
         if (ret)
                 pr_err("error setting wl12xx data: %d\n", ret);
 
+        omap_hsmmc_init(mmc);
         omap_i2c_init();
         platform_device_register(&omap_vwlan_device);
         usb_musb_init(NULL);
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 39f9d5a58d0..7072e0d651b 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -33,6 +33,7 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 
+#include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index e25364de028..04d551b1f7f 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -43,6 +43,7 @@
 #include <linux/errno.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/bug.h>
 
 #include <plat/clock.h>
 
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index e069a9be93d..cd7fd0f9114 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -22,6 +22,7 @@
 #include <asm/div64.h>
 
 #include <plat/clock.h>
+#include <plat/cpu.h>
 
 #include "clock.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 61ad3855f10..bace9308a4d 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -14,11 +14,14 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/list.h>
 
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index d87bc9cb2a3..dfda9a3f2cb 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -21,8 +21,10 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0cc12879e7b..3b4d09a5039 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -17,8 +17,10 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 80bb0f0e92e..12500097378 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <plat/cpu.h>
 #include <plat/clock.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 952c3e01c9e..794d82702c8 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -21,6 +21,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <plat/hardware.h>
 #include <plat/clock.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index d75e5f6b8a0..981b9f9111a 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -20,14 +20,15 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock3xxx.h"
 #include "clock34xx.h"
 #include "clock36xx.h"
 #include "clock3517.h"
-
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 08e86d793a1..79b98f22f20 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -26,8 +26,11 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/clk.h>
+
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 04d39cdd211..389f9f8b570 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,8 +18,10 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "cm.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 6a836303252..535d66e2822 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,8 +18,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 6204deaf85b..bd8810c3753 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -20,8 +20,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index bcb0c581716..9498b0f5fbd 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -33,7 +33,6 @@
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
 };
 
 static struct ads7846_platform_data ads7846_config = {
@@ -76,13 +75,15 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
                         gpio_set_debounce(gpio_pendown, gpio_debounce);
         }
 
-        ads7846_config.gpio_pendown = gpio_pendown;
-
         spi_bi->bus_num = bus_num;
         spi_bi->irq     = OMAP_GPIO_IRQ(gpio_pendown);
 
-        if (board_pdata)
+        if (board_pdata) {
+                board_pdata->gpio_pendown = gpio_pendown;
                 spi_bi->platform_data = board_pdata;
+        } else {
+                ads7846_config.gpio_pendown = gpio_pendown;
+        }
 
         spi_register_board_info(&ads7846_spi_board_info, 1);
 }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index aaf421178c9..1549c11000d 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,12 +17,13 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 #include <plat/board.h>
 #include <plat/mux.h>
-
 #include <plat/clock.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "sdrc.h"
 #include "control.h"
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7e9338e8d68..57da7f406e2 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -134,6 +134,8 @@ void omap4_map_io(void);
 void ti81xx_map_io(void);
 void omap_barriers_init(void);
 
+extern void __init omap_init_consistent_dma_size(void);
+
 /**
  * omap_test_timeout - busy-loop, testing a condition
  * @cond: condition to test until it evaluates to true
@@ -175,6 +177,18 @@ void omap3_intc_handle_irq(struct pt_regs *regs);
 extern void __iomem *omap4_get_l2cache_base(void);
 #endif
 
+struct device_node;
+#ifdef CONFIG_OF
+int __init omap_intc_of_init(struct device_node *node,
+                             struct device_node *parent);
+#else
+int __init omap_intc_of_init(struct device_node *node,
+                             struct device_node *parent)
+{
+        return 0;
+}
+#endif
+
 #ifdef CONFIG_SMP
 extern void __iomem *omap4_get_scu_base(void);
 #else
@@ -236,5 +250,10 @@ static inline u32 omap4_mpuss_read_prev_context_state(void)
         return 0;
 }
 #endif
+
+struct omap_sdrc_params;
+extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                      struct omap_sdrc_params *sdrc_cs1);
+
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 114c037e433..08e674bb041 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,9 +15,11 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 #include <plat/sdrc.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 0ba68d3764b..a406fd045ce 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,7 +16,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 
-#include <mach/io.h>
 #include <mach/ctrl_module_core_44xx.h>
 #include <mach/ctrl_module_wkup_44xx.h>
 #include <mach/ctrl_module_pad_core_44xx.h>
@@ -339,6 +338,11 @@
 #define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
 
 /*
+ * CONTROL AM33XX STATUS register
+ */
+#define AM33XX_CONTROL_STATUS           0x040
+
+/*
  * CONTROL OMAP STATUS register to identify OMAP3 features
  */
 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index f713818be06..e4336035c0e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -25,7 +25,7 @@
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
 
-#include <plat/tc.h>
+#include "iomap.h"
 #include <plat/board.h>
 #include <plat/mmc.h>
 #include <plat/dma.h>
@@ -276,7 +276,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
 }
 
 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-static inline void omap_init_mbox(void)
+static inline void __init omap_init_mbox(void)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -316,7 +316,7 @@ static inline void omap_init_audio(void) {}
 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
 
-static void omap_init_mcpdm(void)
+static void __init omap_init_mcpdm(void)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -337,7 +337,7 @@ static inline void omap_init_mcpdm(void) {}
 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
 
-static void omap_init_dmic(void)
+static void __init omap_init_dmic(void)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -359,7 +359,7 @@ static inline void omap_init_dmic(void) {}
 
 #include <plat/mcspi.h>
 
-static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
+static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
         struct platform_device *pdev;
         char *name = "omap2_mcspi";
@@ -633,9 +633,7 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 /*-------------------------------------------------------------------------*/
 
 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
 #define OMAP_HDQ_BASE   0x480B2000
-#endif
 static struct resource omap_hdq_resources[] = {
         {
                 .start          = OMAP_HDQ_BASE,
@@ -658,7 +656,10 @@ static struct platform_device omap_hdq_dev = {
 };
 static inline void omap_hdq_init(void)
 {
-        (void) platform_device_register(&omap_hdq_dev);
+        if (cpu_is_omap2420())
+                return;
+
+        platform_device_register(&omap_hdq_dev);
 }
 #else
 static inline void omap_hdq_init(void) {}
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 3677b1f58b8..9706c648bc1 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -30,6 +30,7 @@
 #include <plat/omap-pm.h>
 #include "common.h"
 
+#include "iomap.h"
 #include "mux.h"
 #include "control.h"
 #include "display.h"
@@ -124,7 +125,7 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
         }
 }
 
-static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
+static int __init omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
         u32 enable_mask, enable_shift;
         u32 pipd_mask, pipd_shift;
@@ -157,7 +158,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
         return 0;
 }
 
-int omap_hdmi_init(enum omap_hdmi_flags flags)
+int __init omap_hdmi_init(enum omap_hdmi_flags flags)
 {
         if (cpu_is_omap44xx())
                 omap4_hdmi_mux_pads(flags);
@@ -165,7 +166,7 @@ int omap_hdmi_init(enum omap_hdmi_flags flags)
         return 0;
 }
 
-static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
+static int __init omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 {
         if (cpu_is_omap44xx())
                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
@@ -173,7 +174,7 @@ static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
         return 0;
 }
 
-static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
+static void __init omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 {
         if (cpu_is_omap44xx())
                 omap4_dsi_mux_pads(dsi_id, 0);
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index a59a45a0096..b19d8496c16 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -227,7 +227,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 
         dma_stride              = OMAP2_DMA_STRIDE;
         dma_common_ch_start     = CSDP;
-        if (cpu_is_omap3630() || cpu_is_omap4430())
+        if (cpu_is_omap3630() || cpu_is_omap44xx())
                 dma_common_ch_end = CCDN;
         else
                 dma_common_ch_end = CCFN;
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index 9c442e290cc..e28e761b7ab 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -21,6 +21,10 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Alexander Shishkin");
 
@@ -30,29 +34,8 @@ MODULE_AUTHOR("Alexander Shishkin");
 #define ETB_BASE        (L4_EMU_34XX_PHYS + 0x1b000)
 #define DAPCTL          (L4_EMU_34XX_PHYS + 0x1d000)
 
-static struct amba_device omap3_etb_device = {
-        .dev            = {
-                .init_name = "etb",
-        },
-        .res            = {
-                .start  = ETB_BASE,
-                .end    = ETB_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .periphid       = 0x000bb907,
-};
-
-static struct amba_device omap3_etm_device = {
-        .dev            = {
-                .init_name = "etm",
-        },
-        .res            = {
-                .start  = ETM_BASE,
-                .end    = ETM_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .periphid       = 0x102bb921,
-};
+static AMBA_APB_DEVICE(omap3_etb, "etb", 0x000bb907, ETB_BASE, { }, NULL);
+static AMBA_APB_DEVICE(omap3_etm, "etm", 0x102bb921, ETM_BASE, { }, NULL);
 
 static int __init emu_init(void)
 {
@@ -66,4 +49,3 @@ static int __init emu_init(void)
 }
 
 subsys_initcall(emu_init);
-
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 8cbfbc2918c..2f994e5194e 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,14 +23,18 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap-pm.h>
 
-static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
+#include "powerdomain.h"
+
+static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 {
         struct platform_device *pdev;
         struct omap_gpio_platform_data *pdata;
         struct omap_gpio_dev_attr *dev_attr;
         char *name = "omap_gpio";
         int id;
+        struct powerdomain *pwrdm;
 
         /*
          * extract the device id from name field available in the
@@ -52,7 +56,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
         pdata->bank_width = dev_attr->bank_width;
         pdata->dbck_flag = dev_attr->dbck_flag;
         pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
-
+        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
         pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
         if (!pdata) {
                 pr_err("gpio%d: Memory allocation failed\n", id);
@@ -61,8 +65,15 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 
         switch (oh->class->rev) {
         case 0:
+                if (id == 1)
+                        /* non-wakeup GPIO pins for OMAP2 Bank1 */
+                        pdata->non_wakeup_gpios = 0xe203ffc0;
+                else if (id == 2)
+                        /* non-wakeup GPIO pins for OMAP2 Bank2 */
+                        pdata->non_wakeup_gpios = 0x08700040;
+                /* fall through */
+
         case 1:
-                pdata->bank_type = METHOD_GPIO_24XX;
                 pdata->regs->revision = OMAP24XX_GPIO_REVISION;
                 pdata->regs->direction = OMAP24XX_GPIO_OE;
                 pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
@@ -72,13 +83,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
                 pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
                 pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
+                pdata->regs->irqenable2 = OMAP24XX_GPIO_IRQENABLE2;
                 pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
                 pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
                 pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
                 pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
+                pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
+                pdata->regs->wkup_en = OMAP24XX_GPIO_WAKE_EN;
+                pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
+                pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
+                pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
+                pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
                 break;
         case 2:
-                pdata->bank_type = METHOD_GPIO_44XX;
                 pdata->regs->revision = OMAP4_GPIO_REVISION;
                 pdata->regs->direction = OMAP4_GPIO_OE;
                 pdata->regs->datain = OMAP4_GPIO_DATAIN;
@@ -88,10 +105,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
                 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
                 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+                pdata->regs->irqenable2 = OMAP4_GPIO_IRQSTATUSSET1;
                 pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
                 pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
                 pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
                 pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
+                pdata->regs->ctrl = OMAP4_GPIO_CTRL;
+                pdata->regs->wkup_en = OMAP4_GPIO_IRQWAKEN0;
+                pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
+                pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
+                pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
+                pdata->regs->fallingdetect = OMAP4_GPIO_FALLINGDETECT;
                 break;
         default:
                 WARN(1, "Invalid gpio bank_type\n");
@@ -99,6 +123,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 return -EINVAL;
         }
 
+        pwrdm = omap_hwmod_get_pwrdm(oh);
+        pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+
         pdev = omap_device_build(name, id - 1, oh, pdata,
                                 sizeof(*pdata), NULL, 0, false);
         kfree(pdata);
@@ -109,9 +136,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 return PTR_ERR(pdev);
         }
 
-        omap_device_disable_idle_on_suspend(pdev);
-
-        gpio_bank_count++;
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 8ad210bda9a..386dec8d235 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -16,6 +16,7 @@
 
 #include <asm/mach/flash.h>
 
+#include <plat/cpu.h>
 #include <plat/nand.h>
 #include <plat/board.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 5cdce10d618..385b3e02c4a 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -18,6 +18,7 @@
 
 #include <asm/mach/flash.h>
 
+#include <plat/cpu.h>
 #include <plat/onenand.h>
 #include <plat/board.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index bbb870c04a5..5e5880d6d09 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -101,10 +101,13 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
 
         gpmc_cfg = board_data;
 
-        ret = platform_device_register(&gpmc_smsc911x_regulator);
-        if (ret < 0) {
-                pr_err("Unable to register smsc911x regulators: %d\n", ret);
-                return;
+        if (!gpmc_cfg->id) {
+                ret = platform_device_register(&gpmc_smsc911x_regulator);
+                if (ret < 0) {
+                        pr_err("Unable to register smsc911x regulators: %d\n",
+                               ret);
+                        return;
+                }
         }
 
         if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index dfffbbf4c00..00d510858e2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -888,6 +888,7 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
         gpmc_write_reg(GPMC_ECC_CONFIG, val);
         return 0;
 }
+EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
 
 /**
  * gpmc_calculate_ecc - generate non-inverted ecc bytes
@@ -918,3 +919,4 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
         gpmc_ecc_used = -EINVAL;
         return 0;
 }
+EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 19dd1657245..8121720e942 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -293,8 +293,8 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
         }
 }
 
-static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
-                                 struct omap_mmc_platform_data *mmc)
+static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
+                                        struct omap_mmc_platform_data *mmc)
 {
         char *hc_name;
 
@@ -429,66 +429,131 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 }
 
 static int omap_hsmmc_done;
+
+void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
+{
+        struct platform_device *pdev;
+        struct omap_mmc_platform_data *mmc_pdata;
+        int res;
+
+        if (omap_hsmmc_done != 1)
+                return;
+
+        omap_hsmmc_done++;
+
+        for (; c->mmc; c++) {
+                if (!c->deferred)
+                        continue;
+
+                pdev = c->pdev;
+                if (!pdev)
+                        continue;
+
+                mmc_pdata = pdev->dev.platform_data;
+                if (!mmc_pdata)
+                        continue;
+
+                mmc_pdata->slots[0].switch_pin = c->gpio_cd;
+                mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
+
+                res = omap_device_register(pdev);
+                if (res)
+                        pr_err("Could not late init MMC %s\n",
+                               c->name);
+        }
+}
+
 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 
-void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
+static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
+                                        int ctrl_nr)
 {
         struct omap_hwmod *oh;
+        struct omap_hwmod *ohs[1];
+        struct omap_device *od;
         struct platform_device *pdev;
         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
         struct omap_mmc_platform_data *mmc_data;
         struct omap_mmc_dev_attr *mmc_dev_attr;
         char *name;
-        int l;
+        int res;
 
         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
         if (!mmc_data) {
                 pr_err("Cannot allocate memory for mmc device!\n");
-                goto done;
+                return;
         }
 
-        if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
-                pr_err("%s fails!\n", __func__);
-                goto done;
-        }
+        res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
+        if (res < 0)
+                goto free_mmc;
+
         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 
         name = "omap_hsmmc";
-
-        l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
+        res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
                      "mmc%d", ctrl_nr);
-        WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
+        WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
+
         oh = omap_hwmod_lookup(oh_name);
         if (!oh) {
                 pr_err("Could not look up %s\n", oh_name);
-                kfree(mmc_data->slots[0].name);
-                goto done;
+                goto free_name;
         }
-
+        ohs[0] = oh;
         if (oh->dev_attr != NULL) {
                 mmc_dev_attr = oh->dev_attr;
                 mmc_data->controller_flags = mmc_dev_attr->flags;
         }
 
-        pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
-                sizeof(struct omap_mmc_platform_data), NULL, 0, false);
-        if (IS_ERR(pdev)) {
-                WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
-                kfree(mmc_data->slots[0].name);
-                goto done;
+        pdev = platform_device_alloc(name, ctrl_nr - 1);
+        if (!pdev) {
+                pr_err("Could not allocate pdev for %s\n", name);
+                goto free_name;
         }
-        /*
-         * return device handle to board setup code
-         * required to populate for regulator framework structure
-         */
-        hsmmcinfo->dev = &pdev->dev;
+        dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
+
+        od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
+        if (!od) {
+                pr_err("Could not allocate od for %s\n", name);
+                goto put_pdev;
+        }
+
+        res = platform_device_add_data(pdev, mmc_data,
+                              sizeof(struct omap_mmc_platform_data));
+        if (res) {
+                pr_err("Could not add pdata for %s\n", name);
+                goto put_pdev;
+        }
+
+        hsmmcinfo->pdev = pdev;
+
+        if (hsmmcinfo->deferred)
+                goto free_mmc;
+
+        res = omap_device_register(pdev);
+        if (res) {
+                pr_err("Could not register od for %s\n", name);
+                goto free_od;
+        }
+
+        goto free_mmc;
+
+free_od:
+        omap_device_delete(od);
+
+put_pdev:
+        platform_device_put(pdev);
+
+free_name:
+        kfree(mmc_data->slots[0].name);
 
-done:
+free_mmc:
         kfree(mmc_data);
 }
 
-void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
         u32 reg;
 
@@ -521,7 +586,7 @@ void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
         }
 
         for (; controllers->mmc; controllers++)
-                omap_init_hsmmc(controllers, controllers->mmc);
+                omap_hsmmc_init_one(controllers, controllers->mmc);
 
 }
 
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index c4409730c4b..07831cc3c17 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -21,10 +21,11 @@ struct omap2_hsmmc_info {
         bool    no_off;         /* power_saving and power is not to go off */
         bool    no_off_init;    /* no power off when not in MMC sleep state */
         bool    vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
+        bool    deferred;       /* mmc needs a deferred probe */
         int     gpio_cd;        /* or -EINVAL */
         int     gpio_wp;        /* or -EINVAL */
         char    *name;          /* or NULL for default */
-        struct device *dev;     /* returned: pointer to mmc adapter */
+        struct platform_device *pdev;   /* mmc controller instance */
         int     ocr_mask;       /* temporary HACK */
         /* Remux (pad configuration) when powering on/off */
         void (*remux)(struct device *dev, int slot, int power_on);
@@ -34,11 +35,16 @@ struct omap2_hsmmc_info {
 
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
-void omap2_hsmmc_init(struct omap2_hsmmc_info *);
+void omap_hsmmc_init(struct omap2_hsmmc_info *);
+void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
 
 #else
 
-static inline void omap2_hsmmc_init(struct omap2_hsmmc_info *info)
+static inline void omap_hsmmc_init(struct omap2_hsmmc_info *info)
+{
+}
+
+static inline void omap_hsmmc_late_init(struct omap2_hsmmc_info *info)
 {
 }
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 719ee423abe..0e79b7bc6aa 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -29,7 +29,7 @@
 #include "control.h"
 
 static unsigned int omap_revision;
-
+static const char *cpu_rev;
 u32 omap_features;
 
 unsigned int omap_rev(void)
@@ -44,6 +44,8 @@ int omap_type(void)
 
         if (cpu_is_omap24xx()) {
                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
+        } else if (cpu_is_am33xx()) {
+                val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
@@ -112,7 +114,7 @@ void omap_get_die_id(struct omap_die_id *odi)
         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 }
 
-static void __init omap24xx_check_revision(void)
+void __init omap2xxx_check_revision(void)
 {
         int i, j;
         u32 idcode, prod_id;
@@ -166,13 +168,63 @@ static void __init omap24xx_check_revision(void)
         pr_info("\n");
 }
 
+#define OMAP3_SHOW_FEATURE(feat)                \
+        if (omap3_has_ ##feat())                \
+                printk(#feat" ");
+
+static void __init omap3_cpuinfo(void)
+{
+        const char *cpu_name;
+
+        /*
+         * OMAP3430 and OMAP3530 are assumed to be same.
+         *
+         * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
+         * on available features. Upon detection, update the CPU id
+         * and CPU class bits.
+         */
+        if (cpu_is_omap3630()) {
+                cpu_name = "OMAP3630";
+        } else if (cpu_is_omap3517()) {
+                /* AM35xx devices */
+                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
+        } else if (cpu_is_ti816x()) {
+                cpu_name = "TI816X";
+        } else if (cpu_is_am335x()) {
+                cpu_name =  "AM335X";
+        } else if (cpu_is_ti814x()) {
+                cpu_name = "TI814X";
+        } else if (omap3_has_iva() && omap3_has_sgx()) {
+                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
+                cpu_name = "OMAP3430/3530";
+        } else if (omap3_has_iva()) {
+                cpu_name = "OMAP3525";
+        } else if (omap3_has_sgx()) {
+                cpu_name = "OMAP3515";
+        } else {
+                cpu_name = "OMAP3503";
+        }
+
+        /* Print verbose information */
+        pr_info("%s ES%s (", cpu_name, cpu_rev);
+
+        OMAP3_SHOW_FEATURE(l2cache);
+        OMAP3_SHOW_FEATURE(iva);
+        OMAP3_SHOW_FEATURE(sgx);
+        OMAP3_SHOW_FEATURE(neon);
+        OMAP3_SHOW_FEATURE(isp);
+        OMAP3_SHOW_FEATURE(192mhz_clk);
+
+        printk(")\n");
+}
+
 #define OMAP3_CHECK_FEATURE(status,feat)                                \
         if (((status & OMAP3_ ##feat## _MASK)                           \
                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
                 omap_features |= OMAP3_HAS_ ##feat;                     \
         }
 
-static void __init omap3_check_features(void)
+void __init omap3xxx_check_features(void)
 {
         u32 status;
 
@@ -199,9 +251,11 @@ static void __init omap3_check_features(void)
          * TODO: Get additional info (where applicable)
          *       e.g. Size of L2 cache.
          */
+
+        omap3_cpuinfo();
 }
 
-static void __init omap4_check_features(void)
+void __init omap4xxx_check_features(void)
 {
         u32 si_type;
 
@@ -226,12 +280,13 @@ static void __init omap4_check_features(void)
         }
 }
 
-static void __init ti81xx_check_features(void)
+void __init ti81xx_check_features(void)
 {
         omap_features = OMAP3_HAS_NEON;
+        omap3_cpuinfo();
 }
 
-static void __init omap3_check_revision(const char **cpu_rev)
+void __init omap3xxx_check_revision(void)
 {
         u32 cpuid, idcode;
         u16 hawkeye;
@@ -245,7 +300,7 @@ static void __init omap3_check_revision(const char **cpu_rev)
         cpuid = read_cpuid(CPUID_ID);
         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                 omap_revision = OMAP3430_REV_ES1_0;
-                *cpu_rev = "1.0";
+                cpu_rev = "1.0";
                 return;
         }
 
@@ -266,26 +321,26 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 case 0: /* Take care of early samples */
                 case 1:
                         omap_revision = OMAP3430_REV_ES2_0;
-                        *cpu_rev = "2.0";
+                        cpu_rev = "2.0";
                         break;
                 case 2:
                         omap_revision = OMAP3430_REV_ES2_1;
-                        *cpu_rev = "2.1";
+                        cpu_rev = "2.1";
                         break;
                 case 3:
                         omap_revision = OMAP3430_REV_ES3_0;
-                        *cpu_rev = "3.0";
+                        cpu_rev = "3.0";
                         break;
                 case 4:
                         omap_revision = OMAP3430_REV_ES3_1;
-                        *cpu_rev = "3.1";
+                        cpu_rev = "3.1";
                         break;
                 case 7:
                 /* FALLTHROUGH */
                 default:
                         /* Use the latest known revision as default */
                         omap_revision = OMAP3430_REV_ES3_1_2;
-                        *cpu_rev = "3.1.2";
+                        cpu_rev = "3.1.2";
                 }
                 break;
         case 0xb868:
@@ -298,13 +353,13 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 switch (rev) {
                 case 0:
                         omap_revision = OMAP3517_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 1:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = OMAP3517_REV_ES1_1;
-                        *cpu_rev = "1.1";
+                        cpu_rev = "1.1";
                 }
                 break;
         case 0xb891:
@@ -313,36 +368,36 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 switch(rev) {
                 case 0: /* Take care of early samples */
                         omap_revision = OMAP3630_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 1:
                         omap_revision = OMAP3630_REV_ES1_1;
-                        *cpu_rev = "1.1";
+                        cpu_rev = "1.1";
                         break;
                 case 2:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = OMAP3630_REV_ES1_2;
-                        *cpu_rev = "1.2";
+                        cpu_rev = "1.2";
                 }
                 break;
         case 0xb81e:
                 switch (rev) {
                 case 0:
                         omap_revision = TI8168_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 1:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = TI8168_REV_ES1_1;
-                        *cpu_rev = "1.1";
+                        cpu_rev = "1.1";
                         break;
                 }
                 break;
         case 0xb944:
                 omap_revision = AM335X_REV_ES1_0;
-                *cpu_rev = "1.0";
+                cpu_rev = "1.0";
                 break;
         case 0xb8f2:
                 switch (rev) {
@@ -350,29 +405,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 /* FALLTHROUGH */
                 case 1:
                         omap_revision = TI8148_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 2:
                         omap_revision = TI8148_REV_ES2_0;
-                        *cpu_rev = "2.0";
+                        cpu_rev = "2.0";
                         break;
                 case 3:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = TI8148_REV_ES2_1;
-                        *cpu_rev = "2.1";
+                        cpu_rev = "2.1";
                         break;
                 }
                 break;
         default:
                 /* Unknown default to latest silicon rev as default */
                 omap_revision = OMAP3630_REV_ES1_2;
-                *cpu_rev = "1.2";
+                cpu_rev = "1.2";
                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
         }
 }
 
-static void __init omap4_check_revision(void)
+void __init omap4xxx_check_revision(void)
 {
         u32 idcode;
         u16 hawkeye;
@@ -445,89 +500,6 @@ static void __init omap4_check_revision(void)
                 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
-#define OMAP3_SHOW_FEATURE(feat)                \
-        if (omap3_has_ ##feat())                \
-                printk(#feat" ");
-
-static void __init omap3_cpuinfo(const char *cpu_rev)
-{
-        const char *cpu_name;
-
-        /*
-         * OMAP3430 and OMAP3530 are assumed to be same.
-         *
-         * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
-         * on available features. Upon detection, update the CPU id
-         * and CPU class bits.
-         */
-        if (cpu_is_omap3630()) {
-                cpu_name = "OMAP3630";
-        } else if (cpu_is_omap3517()) {
-                /* AM35xx devices */
-                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
-        } else if (cpu_is_ti816x()) {
-                cpu_name = "TI816X";
-        } else if (cpu_is_am335x()) {
-                cpu_name =  "AM335X";
-        } else if (cpu_is_ti814x()) {
-                cpu_name = "TI814X";
-        } else if (omap3_has_iva() && omap3_has_sgx()) {
-                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
-                cpu_name = "OMAP3430/3530";
-        } else if (omap3_has_iva()) {
-                cpu_name = "OMAP3525";
-        } else if (omap3_has_sgx()) {
-                cpu_name = "OMAP3515";
-        } else {
-                cpu_name = "OMAP3503";
-        }
-
-        /* Print verbose information */
-        pr_info("%s ES%s (", cpu_name, cpu_rev);
-
-        OMAP3_SHOW_FEATURE(l2cache);
-        OMAP3_SHOW_FEATURE(iva);
-        OMAP3_SHOW_FEATURE(sgx);
-        OMAP3_SHOW_FEATURE(neon);
-        OMAP3_SHOW_FEATURE(isp);
-        OMAP3_SHOW_FEATURE(192mhz_clk);
-
-        printk(")\n");
-}
-
-/*
- * Try to detect the exact revision of the omap we're running on
- */
-void __init omap2_check_revision(void)
-{
-        const char *cpu_rev;
-
-        /*
-         * At this point we have an idea about the processor revision set
-         * earlier with omap2_set_globals_tap().
-         */
-        if (cpu_is_omap24xx()) {
-                omap24xx_check_revision();
-        } else if (cpu_is_omap34xx()) {
-                omap3_check_revision(&cpu_rev);
-
-                /* TI81XX doesn't have feature register */
-                if (!cpu_is_ti81xx())
-                        omap3_check_features();
-                else
-                        ti81xx_check_features();
-
-                omap3_cpuinfo(cpu_rev);
-                return;
-        } else if (cpu_is_omap44xx()) {
-                omap4_check_revision();
-                omap4_check_features();
-                return;
-        } else {
-                pr_err("OMAP revision unknown, please fix!\n");
-        }
-}
-
 /*
  * Set up things for map_io and processor detection later on. Gets called
  * pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
deleted file mode 100644
index 56964a0c4c7..00000000000
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for OMAP-based platforms
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
index fd78f31aa1a..b8758c8a939 100644
--- a/arch/arm/mach-omap2/include/mach/io.h
+++ b/arch/arm/mach-omap2/include/mach/io.h
@@ -1,5 +1,49 @@
 /*
  * arch/arm/mach-omap2/include/mach/io.h
+ *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
  */
 
-#include <plat/io.h>
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h
deleted file mode 100644
index d488721ab90..00000000000
--- a/arch/arm/mach-omap2/include/mach/system.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/system.h
- */
-
-#include <plat/system.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e501b4972a6..065bd768987 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -23,33 +23,30 @@
 #include <linux/clk.h>
 
 #include <asm/tlb.h>
-
 #include <asm/mach/map.h>
 
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 #include <plat/serial.h>
-
-#include "clock2xxx.h"
-#include "clock3xxx.h"
-#include "clock44xx.h"
-
-#include "common.h"
 #include <plat/omap-pm.h>
+#include <plat/omap_hwmod.h>
+#include <plat/multi.h>
+
+#include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
-
 #include "clockdomain.h"
-#include <plat/omap_hwmod.h>
-#include <plat/multi.h>
 #include "common.h"
+#include "clock2xxx.h"
+#include "clock3xxx.h"
+#include "clock44xx.h"
 
 /*
  * The machine specific code may provide the extra mapping besides the
  * default mapping provided here.
  */
 
-#ifdef CONFIG_ARCH_OMAP2
+#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
 static struct map_desc omap24xx_io_desc[] __initdata = {
         {
                 .virtual        = L3_24XX_VIRT,
@@ -351,7 +348,6 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 
 static void __init omap_common_init_early(void)
 {
-        omap2_check_revision();
         omap_init_consistent_dma_size();
 }
 
@@ -392,6 +388,7 @@ static void __init omap_hwmod_init_postsetup(void)
 void __init omap2420_init_early(void)
 {
         omap2_set_globals_242x();
+        omap2xxx_check_revision();
         omap_common_init_early();
         omap2xxx_voltagedomains_init();
         omap242x_powerdomains_init();
@@ -406,6 +403,7 @@ void __init omap2420_init_early(void)
 void __init omap2430_init_early(void)
 {
         omap2_set_globals_243x();
+        omap2xxx_check_revision();
         omap_common_init_early();
         omap2xxx_voltagedomains_init();
         omap243x_powerdomains_init();
@@ -424,6 +422,8 @@ void __init omap2430_init_early(void)
 void __init omap3_init_early(void)
 {
         omap2_set_globals_3xxx();
+        omap3xxx_check_revision();
+        omap3xxx_check_features();
         omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
@@ -456,6 +456,8 @@ void __init am35xx_init_early(void)
 void __init ti81xx_init_early(void)
 {
         omap2_set_globals_ti81xx();
+        omap3xxx_check_revision();
+        ti81xx_check_features();
         omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
@@ -470,6 +472,8 @@ void __init ti81xx_init_early(void)
 void __init omap4430_init_early(void)
 {
         omap2_set_globals_443x();
+        omap4xxx_check_revision();
+        omap4xxx_check_features();
         omap_common_init_early();
         omap44xx_voltagedomains_init();
         omap44xx_powerdomains_init();
@@ -490,43 +494,3 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                 _omap2_init_reprogram_sdrc();
         }
 }
-
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-
-u8 omap_readb(u32 pa)
-{
-        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readb);
-
-u16 omap_readw(u32 pa)
-{
-        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readw);
-
-u32 omap_readl(u32 pa)
-{
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readl);
-
-void omap_writeb(u8 v, u32 pa)
-{
-        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writeb);
-
-void omap_writew(u16 v, u32 pa)
-{
-        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writew);
-
-void omap_writel(u32 v, u32 pa)
-{
-        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/mach-omap2/iomap.h
index 0696bae1818..e6f95816529 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -1,13 +1,5 @@
 /*
- * arch/arm/plat-omap/include/mach/io.h
- *
- * IO definitions for TI OMAP processors and boards
- *
- * Copied from arch/arm/mach-sa1100/include/mach/io.h
- * Copyright (C) 1997-1999 Russell King
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * IO mappings for OMAP2+
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -25,33 +17,9 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
  * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Modifications:
- *  06-12-1997  RMK     Created.
- *  07-04-1999  RMK     Major cleanup
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-/*
- * ----------------------------------------------------------------------------
- * I/O mapping
- * ----------------------------------------------------------------------------
  */
 
 #ifdef __ASSEMBLER__
@@ -60,13 +28,9 @@
 #define IOMEM(x)                ((void __force __iomem *)(x))
 #endif
 
-#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
-#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
-
 #define OMAP2_L3_IO_OFFSET      0x90000000
 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
 
-
 #define OMAP2_L4_IO_OFFSET      0xb2000000
 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
 
@@ -87,16 +51,6 @@
 
 /*
  * ----------------------------------------------------------------------------
- * Omap1 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-#define OMAP1_IO_PHYS           0xFFFB0000
-#define OMAP1_IO_SIZE           0x40000
-#define OMAP1_IO_VIRT           (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
-
-/*
- * ----------------------------------------------------------------------------
  * Omap2 specific IO mapping
  * ----------------------------------------------------------------------------
  */
@@ -247,31 +201,3 @@
                                                 /* 0x4e000000 --> 0xfd300000 */
 #define OMAP44XX_DMM_SIZE       SZ_1M
 #define OMAP44XX_DMM_VIRT       (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
-/*
- * ----------------------------------------------------------------------------
- * Omap specific register access
- * ----------------------------------------------------------------------------
- */
-
-#ifndef __ASSEMBLER__
-
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-
-extern u8 omap_readb(u32 pa);
-extern u16 omap_readw(u32 pa);
-extern u32 omap_readl(u32 pa);
-extern void omap_writeb(u8 v, u32 pa);
-extern void omap_writew(u16 v, u32 pa);
-extern void omap_writel(u32 v, u32 pa);
-
-struct omap_sdrc_params;
-extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                                      struct omap_sdrc_params *sdrc_cs1);
-
-extern void __init omap_init_consistent_dma_size(void);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 1fef061f792..65f0d2571c9 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -11,13 +11,20 @@
  * for more details.
  */
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
+
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
 
 /* selected INTC register offsets */
 
@@ -57,6 +64,8 @@ static struct omap_irq_bank {
         },
 };
 
+static struct irq_domain *domain;
+
 /* Structure to save interrupt controller context */
 struct omap3_intc_regs {
         u32 sysconfig;
@@ -147,17 +156,27 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-static void __init omap_init_irq(u32 base, int nr_irqs)
+static void __init omap_init_irq(u32 base, int nr_irqs,
+                                 struct device_node *node)
 {
         void __iomem *omap_irq_base;
         unsigned long nr_of_irqs = 0;
         unsigned int nr_banks = 0;
-        int i, j;
+        int i, j, irq_base;
 
         omap_irq_base = ioremap(base, SZ_4K);
         if (WARN_ON(!omap_irq_base))
                 return;
 
+        irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+        if (irq_base < 0) {
+                pr_warn("Couldn't allocate IRQ numbers\n");
+                irq_base = 0;
+        }
+
+        domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
+                                       &irq_domain_simple_ops, NULL);
+
         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
                 struct omap_irq_bank *bank = irq_banks + i;
 
@@ -166,36 +185,36 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
                 /* Static mapping, never released */
                 bank->base_reg = ioremap(base, SZ_4K);
                 if (!bank->base_reg) {
-                        printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+                        pr_err("Could not ioremap irq bank%i\n", i);
                         continue;
                 }
 
                 omap_irq_bank_init_one(bank);
 
                 for (j = 0; j < bank->nr_irqs; j += 32)
-                        omap_alloc_gc(bank->base_reg + j, j, 32);
+                        omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
 
                 nr_of_irqs += bank->nr_irqs;
                 nr_banks++;
         }
 
-        printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-               nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+        pr_info("Total of %ld interrupts on %d active controller%s\n",
+                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 }
 
 void __init omap2_init_irq(void)
 {
-        omap_init_irq(OMAP24XX_IC_BASE, 96);
+        omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
 }
 
 void __init omap3_init_irq(void)
 {
-        omap_init_irq(OMAP34XX_IC_BASE, 96);
+        omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
 }
 
 void __init ti81xx_init_irq(void)
 {
-        omap_init_irq(OMAP34XX_IC_BASE, 128);
+        omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
 }
 
 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
@@ -225,8 +244,10 @@ out:
                 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
                 irqnr &= ACTIVEIRQ_MASK;
 
-                if (irqnr)
+                if (irqnr) {
+                        irqnr = irq_find_mapping(domain, irqnr);
                         handle_IRQ(irqnr, regs);
+                }
         } while (irqnr);
 }
 
@@ -236,6 +257,28 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
         omap_intc_handle_irq(base_addr, regs);
 }
 
+int __init omap_intc_of_init(struct device_node *node,
+                             struct device_node *parent)
+{
+        struct resource res;
+        u32 nr_irqs = 96;
+
+        if (WARN_ON(!node))
+                return -ENODEV;
+
+        if (of_address_to_resource(node, 0, &res)) {
+                WARN(1, "unable to get intc registers\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
+                pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
+
+        omap_init_irq(res.start, nr_irqs, of_node_get(node));
+
+        return 0;
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index ecc039e794d..577cb77db26 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -158,7 +158,7 @@ static int omap3_enable_st_clock(unsigned int id, bool enable)
         return 0;
 }
 
-static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
+static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 {
         int id, count = 1;
         char *name = "omap-mcbsp";
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index e974d339a35..65c33911341 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -99,8 +99,8 @@ void omap_mux_write_array(struct omap_mux_partition *partition,
 
 static char *omap_mux_options;
 
-static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
-                               int gpio, int val)
+static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
+                                      int gpio, int val)
 {
         struct omap_mux_entry *e;
         struct omap_mux *gpio_mux = NULL;
@@ -144,7 +144,7 @@ static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
         return 0;
 }
 
-int omap_mux_init_gpio(int gpio, int val)
+int __init omap_mux_init_gpio(int gpio, int val)
 {
         struct omap_mux_partition *partition;
         int ret;
@@ -158,9 +158,9 @@ int omap_mux_init_gpio(int gpio, int val)
         return -ENODEV;
 }
 
-static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
-                                 const char *muxname,
-                                 struct omap_mux **found_mux)
+static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
+                                        const char *muxname,
+                                        struct omap_mux **found_mux)
 {
         struct omap_mux *mux = NULL;
         struct omap_mux_entry *e;
@@ -217,7 +217,7 @@ static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
         return -ENODEV;
 }
 
-static int
+static int __init
 omap_mux_get_by_name(const char *muxname,
                         struct omap_mux_partition **found_partition,
                         struct omap_mux **found_mux)
@@ -239,7 +239,7 @@ omap_mux_get_by_name(const char *muxname,
         return -ENODEV;
 }
 
-int omap_mux_init_signal(const char *muxname, int val)
+int __init omap_mux_init_signal(const char *muxname, int val)
 {
         struct omap_mux_partition *partition = NULL;
         struct omap_mux *mux = NULL;
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 2132308ad1e..69fe060a0b7 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -246,7 +246,7 @@ static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
 {
 }
 
-static struct omap_board_mux *board_mux __initdata __maybe_unused;
+static struct omap_board_mux *board_mux __maybe_unused;
 
 #endif
 
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index adbe4d8c7ca..56c345b8b93 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -33,7 +33,7 @@ int platform_cpu_kill(unsigned int cpu)
  * platform-specific code to shutdown a CPU
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref platform_cpu_die(unsigned int cpu)
 {
         unsigned int this_cpu;
 
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 069f8fc99d1..13670aa84e5 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -262,12 +262,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
          * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
          */
         mpuss_clear_prev_logic_pwrst();
-        pwrdm_clear_all_prev_pwrst(mpuss_pd);
         if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
                 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
                 save_state = 2;
 
-        clear_cpu_prev_pwrst(cpu);
         cpu_clear_prev_logic_pwrst(cpu);
         set_cpu_next_pwrst(cpu, power_state);
         set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
@@ -299,7 +297,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
  * @cpu : CPU ID
  * @power_state: CPU low power state.
  */
-int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 {
         unsigned int cpu_state = 0;
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index c1bf3ef0ba0..deffbf1c962 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -23,11 +23,12 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
+
 #include <mach/hardware.h>
 #include <mach/omap-secure.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "clockdomain.h"
 
 /* SCU base address */
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index d3d8971d7f3..42cd7fb5241 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -43,7 +43,6 @@
 
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
-static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
 static DEFINE_SPINLOCK(wakeupgen_lock);
 static unsigned int irq_target_cpu[NR_IRQS];
 
@@ -67,14 +66,6 @@ static inline void sar_writel(u32 val, u32 offset, u8 idx)
         __raw_writel(val, sar_base + offset + (idx * 4));
 }
 
-static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
-{
-        u8 i;
-
-        for (i = 0; i < NR_REG_BANKS; i++)
-                wakeupgen_writel(reg, i, cpu);
-}
-
 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
 {
         unsigned int spi_irq;
@@ -130,22 +121,6 @@ static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
         wakeupgen_writel(val, i, cpu);
 }
 
-static void _wakeupgen_save_masks(unsigned int cpu)
-{
-        u8 i;
-
-        for (i = 0; i < NR_REG_BANKS; i++)
-                per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
-}
-
-static void _wakeupgen_restore_masks(unsigned int cpu)
-{
-        u8 i;
-
-        for (i = 0; i < NR_REG_BANKS; i++)
-                wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
-}
-
 /*
  * Architecture specific Mask extension
  */
@@ -170,6 +145,33 @@ static void wakeupgen_unmask(struct irq_data *d)
         spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+
+static void _wakeupgen_save_masks(unsigned int cpu)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
+}
+
+static void _wakeupgen_restore_masks(unsigned int cpu)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
+}
+
+static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(reg, i, cpu);
+}
+
 /*
  * Mask or unmask all interrupts on given CPU.
  *      0 = Mask all interrupts on the 'cpu'
@@ -191,6 +193,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
         }
         spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
+#endif
 
 #ifdef CONFIG_CPU_PM
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3c8dd928628..34b9766d1d2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,6 +29,7 @@
 
 #include "omap_hwmod_common_data.h"
 
+#include "smartreflex.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
@@ -376,6 +377,16 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
+        { .irq = 18},
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
+        { .irq = 19},
+        { .irq = -1 }
+};
+
 /* L4 CORE -> SR1 interface */
 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
         {
@@ -2664,6 +2675,10 @@ static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
 };
 
 /* SR1 */
+static struct omap_smartreflex_dev_attr sr1_dev_attr = {
+        .sensor_voltdm_name   = "mpu_iva",
+};
+
 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
         &omap3_l4_core__sr1,
 };
@@ -2672,7 +2687,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
         .name           = "sr1_hwmod",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
-        .vdd_name       = "mpu_iva",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2684,6 +2698,8 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
         },
         .slaves         = omap3_sr1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .dev_attr       = &sr1_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_mpu_irqs,
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
@@ -2691,7 +2707,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
         .name           = "sr1_hwmod",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
-        .vdd_name       = "mpu_iva",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2703,9 +2718,15 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
         },
         .slaves         = omap3_sr1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .dev_attr       = &sr1_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_mpu_irqs,
 };
 
 /* SR2 */
+static struct omap_smartreflex_dev_attr sr2_dev_attr = {
+        .sensor_voltdm_name     = "core",
+};
+
 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
         &omap3_l4_core__sr2,
 };
@@ -2714,7 +2735,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
         .name           = "sr2_hwmod",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
-        .vdd_name       = "core",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2726,6 +2746,8 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
         },
         .slaves         = omap3_sr2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .dev_attr       = &sr2_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_core_irqs,
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
@@ -2733,7 +2755,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
         .name           = "sr2_hwmod",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
-        .vdd_name       = "core",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2745,6 +2766,8 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
         },
         .slaves         = omap3_sr2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .dev_attr       = &sr2_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_core_irqs,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ef0524c10a8..08daa5e0eb5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -28,12 +28,12 @@
 #include <plat/mcspi.h>
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
-#include <plat/i2c.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
 
 #include "omap_hwmod_common_data.h"
 
+#include "smartreflex.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "prm44xx.h"
@@ -3963,6 +3963,10 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
 };
 
 /* smartreflex_core */
+static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
+        .sensor_voltdm_name   = "core",
+};
+
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
@@ -3999,7 +4003,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
 
         .main_clk       = "smartreflex_core_fck",
-        .vdd_name       = "core",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
@@ -4009,9 +4012,14 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+        .dev_attr       = &smartreflex_core_dev_attr,
 };
 
 /* smartreflex_iva */
+static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
+        .sensor_voltdm_name     = "iva",
+};
+
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
@@ -4047,7 +4055,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         .clkdm_name     = "l4_ao_clkdm",
         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
         .main_clk       = "smartreflex_iva_fck",
-        .vdd_name       = "iva",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
@@ -4057,9 +4064,14 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_iva_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+        .dev_attr       = &smartreflex_iva_dev_attr,
 };
 
 /* smartreflex_mpu */
+static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
+        .sensor_voltdm_name     = "mpu",
+};
+
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
@@ -4095,7 +4107,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         .clkdm_name     = "l4_ao_clkdm",
         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
         .main_clk       = "smartreflex_mpu_fck",
-        .vdd_name       = "mpu",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
@@ -4105,6 +4116,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_mpu_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+        .dev_attr       = &smartreflex_mpu_dev_attr,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
index e6dda694fd5..5037e76e4e2 100644
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -28,6 +28,8 @@
  *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
  */
 
+#include <plat/hardware.h>
+
 #include "opp2xxx.h"
 #include "sdrc.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index 1b9596ae201..750805c528d 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -26,6 +26,8 @@
  * This is technically part of the OMAP2xxx clock code.
  */
 
+#include <plat/hardware.h>
+
 #include "opp2xxx.h"
 #include "sdrc.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 4411163e012..814bcd90159 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -220,8 +220,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
                 return 0;
 
         d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
-
-        (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
+        if (!(IS_ERR_OR_NULL(d)))
+                (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
                         (void *)pwrdm, &pwrdm_suspend_fops);
 
         return 0;
@@ -264,7 +264,7 @@ static int __init pm_dbg_init(void)
                 return 0;
 
         d = debugfs_create_dir("pm_debug", NULL);
-        if (IS_ERR(d))
+        if (IS_ERR_OR_NULL(d))
                 return PTR_ERR(d);
 
         (void) debugfs_create_file("count", S_IRUGO,
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 5a65dd04aa3..a7bdec69a2b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -15,11 +15,13 @@
 #include <linux/err.h>
 #include <linux/opp.h>
 #include <linux/export.h>
+#include <linux/suspend.h>
 
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 #include "common.h"
 
+#include "prcm-common.h"
 #include "voltage.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
@@ -28,7 +30,13 @@
 
 static struct omap_device_pm_latency *pm_lats;
 
-static int _init_omap_device(char *name)
+/*
+ * omap_pm_suspend: points to a function that does the SoC-specific
+ * suspend work
+ */
+int (*omap_pm_suspend)(void);
+
+static int __init _init_omap_device(char *name)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -49,7 +57,7 @@ static int _init_omap_device(char *name)
 /*
  * Build omap_devices for processors and bus.
  */
-static void omap2_init_processor_devices(void)
+static void __init omap2_init_processor_devices(void)
 {
         _init_omap_device("mpu");
         if (omap3_has_iva())
@@ -68,32 +76,41 @@ static void omap2_init_processor_devices(void)
 #define FORCEWAKEUP_SWITCH      0
 #define LOWPOWERSTATE_SWITCH    1
 
+int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
+{
+        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+                clkdm_allow_idle(clkdm);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+                 atomic_read(&clkdm->usecount) == 0)
+                clkdm_sleep(clkdm);
+        return 0;
+}
+
 /*
  * This sets pwrdm state (other than mpu & core. Currently only ON &
  * RET are supported.
  */
-int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)
 {
-        u32 cur_state;
-        int sleep_switch = -1;
-        int ret = 0;
-        int hwsup = 0;
+        u8 curr_pwrst, next_pwrst;
+        int sleep_switch = -1, ret = 0, hwsup = 0;
 
-        if (pwrdm == NULL || IS_ERR(pwrdm))
+        if (!pwrdm || IS_ERR(pwrdm))
                 return -EINVAL;
 
-        while (!(pwrdm->pwrsts & (1 << state))) {
-                if (state == PWRDM_POWER_OFF)
+        while (!(pwrdm->pwrsts & (1 << pwrst))) {
+                if (pwrst == PWRDM_POWER_OFF)
                         return ret;
-                state--;
+                pwrst--;
         }
 
-        cur_state = pwrdm_read_next_pwrst(pwrdm);
-        if (cur_state == state)
+        next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+        if (next_pwrst == pwrst)
                 return ret;
 
-        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
-                if ((pwrdm_read_pwrst(pwrdm) > state) &&
+        curr_pwrst = pwrdm_read_pwrst(pwrdm);
+        if (curr_pwrst < PWRDM_POWER_ON) {
+                if ((curr_pwrst > pwrst) &&
                         (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
                         sleep_switch = LOWPOWERSTATE_SWITCH;
                 } else {
@@ -103,12 +120,10 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                 }
         }
 
-        ret = pwrdm_set_next_pwrst(pwrdm, state);
-        if (ret) {
-                pr_err("%s: unable to set state of powerdomain: %s\n",
+        ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
+        if (ret)
+                pr_err("%s: unable to set power state of powerdomain: %s\n",
                        __func__, pwrdm->name);
-                goto err;
-        }
 
         switch (sleep_switch) {
         case FORCEWAKEUP_SWITCH:
@@ -119,16 +134,16 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                 break;
         case LOWPOWERSTATE_SWITCH:
                 pwrdm_set_lowpwrstchange(pwrdm);
+                pwrdm_wait_transition(pwrdm);
+                pwrdm_state_switch(pwrdm);
                 break;
-        default:
-                return ret;
         }
 
-        pwrdm_state_switch(pwrdm);
-err:
         return ret;
 }
 
+
+
 /*
  * This API is to be called during init to set the various voltage
  * domains to the voltage as per the opp table. Typically we boot up
@@ -199,6 +214,56 @@ exit:
         return -EINVAL;
 }
 
+#ifdef CONFIG_SUSPEND
+static int omap_pm_enter(suspend_state_t suspend_state)
+{
+        int ret = 0;
+
+        if (!omap_pm_suspend)
+                return -ENOENT; /* XXX doublecheck */
+
+        switch (suspend_state) {
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                ret = omap_pm_suspend();
+                break;
+        default:
+                ret = -EINVAL;
+        }
+
+        return ret;
+}
+
+static int omap_pm_begin(suspend_state_t state)
+{
+        disable_hlt();
+        if (cpu_is_omap34xx())
+                omap_prcm_irq_prepare();
+        return 0;
+}
+
+static void omap_pm_end(void)
+{
+        enable_hlt();
+        return;
+}
+
+static void omap_pm_finish(void)
+{
+        if (cpu_is_omap34xx())
+                omap_prcm_irq_complete();
+}
+
+static const struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap_pm_begin,
+        .end            = omap_pm_end,
+        .enter          = omap_pm_enter,
+        .finish         = omap_pm_finish,
+        .valid          = suspend_valid_only_mem,
+};
+
+#endif /* CONFIG_SUSPEND */
+
 static void __init omap3_init_voltages(void)
 {
         if (!cpu_is_omap34xx())
@@ -230,6 +295,14 @@ postcore_initcall(omap2_common_pm_init);
 
 static int __init omap2_common_pm_late_init(void)
 {
+        /*
+         * In the case of DT, the PMIC and SR initialization will be done using
+         * a completely different mechanism.
+         * Disable this part if a DT blob is available.
+         */
+        if (of_have_populated_dt())
+                return 0;
+
         /* Init the voltage layer */
         omap_pmic_late_init();
         omap_voltage_late_init();
@@ -241,6 +314,10 @@ static int __init omap2_common_pm_late_init(void)
         /* Smartreflex device init */
         omap_devinit_smartreflex();
 
+#ifdef CONFIG_SUSPEND
+        suspend_set_ops(&omap_pm_ops);
+#endif
+
         return 0;
 }
 late_initcall(omap2_common_pm_late_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index b737b11e449..36fa90b6ece 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -18,10 +18,11 @@
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
-extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 extern int omap4_idle_init(void);
+extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
+extern int (*omap_pm_suspend)(void);
 
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 730bb009587..95442b69ae2 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -26,7 +26,6 @@
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
@@ -36,12 +35,13 @@
 #include <asm/mach-types.h>
 #include <asm/system_misc.h>
 
-#include <mach/irqs.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/dma.h>
 #include <plat/board.h>
 
+#include <mach/irqs.h>
+
 #include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
@@ -50,23 +50,9 @@
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
-
 #include "powerdomain.h"
 #include "clockdomain.h"
 
-#ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state = PM_SUSPEND_ON;
-static inline bool is_suspending(void)
-{
-        return (suspend_state != PM_SUSPEND_ON);
-}
-#else
-static inline bool is_suspending(void)
-{
-        return false;
-}
-#endif
-
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
                                   void __iomem *sdrc_power);
@@ -86,7 +72,7 @@ static int omap2_fclks_active(void)
         return (f1 | f2) ? 1 : 0;
 }
 
-static void omap2_enter_full_retention(void)
+static int omap2_enter_full_retention(void)
 {
         u32 l;
 
@@ -149,6 +135,8 @@ no_sleep:
 
         /* Mask future PRCM-to-MPU interrupts */
         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+
+        return 0;
 }
 
 static int omap2_i2c_active(void)
@@ -227,7 +215,6 @@ static int omap2_can_sleep(void)
 
 static void omap2_pm_idle(void)
 {
-        local_irq_disable();
         local_fiq_disable();
 
         if (!omap2_can_sleep()) {
@@ -244,78 +231,6 @@ static void omap2_pm_idle(void)
 
 out:
         local_fiq_enable();
-        local_irq_enable();
-}
-
-#ifdef CONFIG_SUSPEND
-static int omap2_pm_begin(suspend_state_t state)
-{
-        disable_hlt();
-        suspend_state = state;
-        return 0;
-}
-
-static int omap2_pm_suspend(void)
-{
-        u32 wken_wkup, mir1;
-
-        wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-        wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
-        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
-
-        /* Mask GPT1 */
-        mir1 = omap_readl(0x480fe0a4);
-        omap_writel(1 << 5, 0x480fe0ac);
-
-        omap2_enter_full_retention();
-
-        omap_writel(mir1, 0x480fe0a4);
-        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
-
-        return 0;
-}
-
-static int omap2_pm_enter(suspend_state_t state)
-{
-        int ret = 0;
-
-        switch (state) {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                ret = omap2_pm_suspend();
-                break;
-        default:
-                ret = -EINVAL;
-        }
-
-        return ret;
-}
-
-static void omap2_pm_end(void)
-{
-        suspend_state = PM_SUSPEND_ON;
-        enable_hlt();
-}
-
-static const struct platform_suspend_ops omap_pm_ops = {
-        .begin          = omap2_pm_begin,
-        .enter          = omap2_pm_enter,
-        .end            = omap2_pm_end,
-        .valid          = suspend_valid_only_mem,
-};
-#else
-static const struct platform_suspend_ops __initdata omap_pm_ops;
-#endif /* CONFIG_SUSPEND */
-
-/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
-static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-{
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                clkdm_allow_idle(clkdm);
-        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-                 atomic_read(&clkdm->usecount) == 0)
-                clkdm_sleep(clkdm);
-        return 0;
 }
 
 static void __init prcm_setup_regs(void)
@@ -359,9 +274,13 @@ static void __init prcm_setup_regs(void)
         clkdm_sleep(gfx_clkdm);
 
         /* Enable hardware-supervised idle for all clkdms */
-        clkdm_for_each(clkdms_setup, NULL);
+        clkdm_for_each(omap_pm_clkdms_setup, NULL);
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
+#ifdef CONFIG_SUSPEND
+        omap_pm_suspend = omap2_enter_full_retention;
+#endif
+
         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
          * stabilisation */
         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
@@ -462,8 +381,7 @@ static int __init omap2_pm_init(void)
                                                     omap24xx_cpu_suspend_sz);
         }
 
-        suspend_set_ops(&omap_pm_ops);
-        pm_idle = omap2_pm_idle;
+        arm_pm_idle = omap2_pm_idle;
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 64d95e69bc5..238defc6f6d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -51,10 +51,6 @@
 #include "sdrc.h"
 #include "control.h"
 
-#ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state = PM_SUSPEND_ON;
-#endif
-
 /* pm34xx errata defined in pm.h */
 u16 pm34xx_errata;
 
@@ -76,16 +72,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
 static struct powerdomain *cam_pwrdm;
 
-static inline void omap3_per_save_context(void)
-{
-        omap_gpio_save_context();
-}
-
-static inline void omap3_per_restore_context(void)
-{
-        omap_gpio_restore_context();
-}
-
 static void omap3_enable_io_chain(void)
 {
         int timeout = 0;
@@ -291,11 +277,6 @@ void omap_sram_idle(void)
         int core_prev_state, per_prev_state;
         u32 sdrc_pwr = 0;
 
-        pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
-        pwrdm_clear_all_prev_pwrst(neon_pwrdm);
-        pwrdm_clear_all_prev_pwrst(core_pwrdm);
-        pwrdm_clear_all_prev_pwrst(per_pwrdm);
-
         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
         switch (mpu_next_state) {
         case PWRDM_POWER_ON:
@@ -333,8 +314,6 @@ void omap_sram_idle(void)
         if (per_next_state < PWRDM_POWER_ON) {
                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
                 omap2_gpio_prepare_for_idle(per_going_off);
-                if (per_next_state == PWRDM_POWER_OFF)
-                                omap3_per_save_context();
         }
 
         /* CORE */
@@ -400,8 +379,6 @@ void omap_sram_idle(void)
         if (per_next_state < PWRDM_POWER_ON) {
                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
                 omap2_gpio_resume_after_idle();
-                if (per_prev_state == PWRDM_POWER_OFF)
-                        omap3_per_restore_context();
         }
 
         /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -419,10 +396,9 @@ void omap_sram_idle(void)
 
 static void omap3_pm_idle(void)
 {
-        local_irq_disable();
         local_fiq_disable();
 
-        if (omap_irq_pending() || need_resched())
+        if (omap_irq_pending())
                 goto out;
 
         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
@@ -435,7 +411,6 @@ static void omap3_pm_idle(void)
 
 out:
         local_fiq_enable();
-        local_irq_enable();
 }
 
 #ifdef CONFIG_SUSPEND
@@ -480,50 +455,6 @@ restore:
         return ret;
 }
 
-static int omap3_pm_enter(suspend_state_t unused)
-{
-        int ret = 0;
-
-        switch (suspend_state) {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                ret = omap3_pm_suspend();
-                break;
-        default:
-                ret = -EINVAL;
-        }
-
-        return ret;
-}
-
-/* Hooks to enable / disable UART interrupts during suspend */
-static int omap3_pm_begin(suspend_state_t state)
-{
-        disable_hlt();
-        suspend_state = state;
-        omap_prcm_irq_prepare();
-        return 0;
-}
-
-static void omap3_pm_end(void)
-{
-        suspend_state = PM_SUSPEND_ON;
-        enable_hlt();
-        return;
-}
-
-static void omap3_pm_finish(void)
-{
-        omap_prcm_irq_complete();
-}
-
-static const struct platform_suspend_ops omap_pm_ops = {
-        .begin          = omap3_pm_begin,
-        .end            = omap3_pm_end,
-        .enter          = omap3_pm_enter,
-        .finish         = omap3_pm_finish,
-        .valid          = suspend_valid_only_mem,
-};
 #endif /* CONFIG_SUSPEND */
 
 
@@ -744,21 +675,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 }
 
 /*
- * Enable hw supervised mode for all clockdomains if it's
- * supported. Initiate sleep transition for other clockdomains, if
- * they are not used
- */
-static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-{
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                clkdm_allow_idle(clkdm);
-        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-                 atomic_read(&clkdm->usecount) == 0)
-                clkdm_sleep(clkdm);
-        return 0;
-}
-
-/*
  * Push functions to SRAM
  *
  * The minimum set of functions is pushed to SRAM for execution:
@@ -827,7 +743,7 @@ static int __init omap3_pm_init(void)
                 goto err2;
         }
 
-        (void) clkdm_for_each(clkdms_setup, NULL);
+        (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 
         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
         if (mpu_pwrdm == NULL) {
@@ -846,10 +762,10 @@ static int __init omap3_pm_init(void)
         core_clkdm = clkdm_lookup("core_clkdm");
 
 #ifdef CONFIG_SUSPEND
-        suspend_set_ops(&omap_pm_ops);
-#endif /* CONFIG_SUSPEND */
+        omap_pm_suspend = omap3_pm_suspend;
+#endif
 
-        pm_idle = omap3_pm_idle;
+        arm_pm_idle = omap3_pm_idle;
         omap3_idle_init();
 
         /*
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index a73e3255417..9ccaadc2cf0 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -84,59 +84,8 @@ static int omap4_pm_suspend(void)
 
         return 0;
 }
-
-static int omap4_pm_enter(suspend_state_t suspend_state)
-{
-        int ret = 0;
-
-        switch (suspend_state) {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                ret = omap4_pm_suspend();
-                break;
-        default:
-                ret = -EINVAL;
-        }
-
-        return ret;
-}
-
-static int omap4_pm_begin(suspend_state_t state)
-{
-        disable_hlt();
-        return 0;
-}
-
-static void omap4_pm_end(void)
-{
-        enable_hlt();
-        return;
-}
-
-static const struct platform_suspend_ops omap_pm_ops = {
-        .begin          = omap4_pm_begin,
-        .end            = omap4_pm_end,
-        .enter          = omap4_pm_enter,
-        .valid          = suspend_valid_only_mem,
-};
 #endif /* CONFIG_SUSPEND */
 
-/*
- * Enable hardware supervised mode for all clockdomains if it's
- * supported. Initiate sleep transition for other clockdomains, if
- * they are not used
- */
-static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-{
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                clkdm_allow_idle(clkdm);
-        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-                        atomic_read(&clkdm->usecount) == 0)
-                clkdm_sleep(clkdm);
-        return 0;
-}
-
-
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 {
         struct power_state *pwrst;
@@ -174,18 +123,16 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  * omap_default_idle - OMAP4 default ilde routine.'
  *
  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
- * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
+ * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
  * by secondary CPU with CONFIG_CPUIDLE.
  */
 static void omap_default_idle(void)
 {
-        local_irq_disable();
         local_fiq_disable();
 
         omap_do_wfi();
 
         local_fiq_enable();
-        local_irq_enable();
 }
 
 /**
@@ -250,14 +197,14 @@ static int __init omap4_pm_init(void)
                 goto err2;
         }
 
-        (void) clkdm_for_each(clkdms_setup, NULL);
+        (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 
 #ifdef CONFIG_SUSPEND
-        suspend_set_ops(&omap_pm_ops);
-#endif /* CONFIG_SUSPEND */
+        omap_pm_suspend = omap4_pm_suspend;
+#endif
 
-        /* Overwrite the default arch_idle() */
-        pm_idle = omap_default_idle;
+        /* Overwrite the default cpu_do_idle() */
+        arm_pm_idle = omap_default_idle;
 
         omap4_idle_init();
 
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index f97afff68d6..c0aeabfcf00 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -13,6 +13,7 @@
 
 #include <linux/errno.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "pm.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 6a17e4ca1d7..0f0a9f1592f 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/bug.h>
 
 #include <plat/prcm.h>
 
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index a7880af4b3d..601325b852a 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/bug.h>
 
 #include "powerdomain.h"
 #include <plat/prcm.h>
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 8ef26daeed6..b7ea468eea3 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index ca669b50f39..928dbd4f20e 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -15,8 +15,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "prcm_mpu44xx.h"
 #include "cm-regbits-44xx.h"
 
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a1d6154dc12..eac623c7c3d 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,11 +17,12 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
 #include <plat/cpu.h>
 #include <plat/irqs.h>
 #include <plat/prcm.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "vp.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 860118ab43e..873b51d494e 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -24,7 +24,6 @@
 #include <linux/interrupt.h>
 #include <linux/slab.h>
 
-#include <mach/system.h>
 #include <plat/common.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index f6de5bc6b12..9b3898a3ac9 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -16,8 +16,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index 7479d7ea137..845c4fd2b12 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -17,7 +17,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/io.h>
 #include "common.h"
 #include <plat/clock.h>
 #include <plat/sdrc.h>
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 791a63cdceb..1133bb2f632 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,13 +24,15 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
+#include <plat/sdrc.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "clock.h"
-#include <plat/sdrc.h>
 #include "sdrc.h"
 
 /* Memory timing, DLL mode flags */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f590afc1f67..0cdd359a128 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -54,11 +54,9 @@
 
 struct omap_uart_state {
         int num;
-        int can_sleep;
 
         struct list_head node;
         struct omap_hwmod *oh;
-        struct platform_device *pdev;
 };
 
 static LIST_HEAD(uart_list);
@@ -381,8 +379,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 
         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 
-        uart->pdev = pdev;
-
         oh->dev_attr = uart;
 
         if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index b5071a47ec3..d4bf904d84a 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -27,7 +27,6 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <mach/io.h>
 
 #include <plat/omap24xx.h>
 
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index f2ea1bd1c69..1f62f23673f 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -23,10 +23,13 @@
  * MA 02111-1307 USA
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
+
+#include <plat/hardware.h>
 #include <plat/sram.h>
-#include <mach/io.h>
 
+#include "iomap.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 53d9d0a5b39..955566eefac 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -29,6 +29,7 @@ static int sr_class3_enable(struct voltagedomain *voltdm)
 
 static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
 {
+        sr_disable_errgen(voltdm);
         omap_vp_disable(voltdm);
         sr_disable(voltdm);
         if (is_volt_reset)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 7e755bb0ffc..008fbd7b935 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -36,6 +36,12 @@
 #define SR_DISABLE_TIMEOUT      200
 
 struct omap_sr {
+        struct list_head                node;
+        struct platform_device          *pdev;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+        struct dentry                   *dbg_dir;
+        unsigned int                    irq;
         int                             srid;
         int                             ip_type;
         int                             nvalue_count;
@@ -49,13 +55,7 @@ struct omap_sr {
         u32                             senp_avgweight;
         u32                             senp_mod;
         u32                             senn_mod;
-        unsigned int                    irq;
         void __iomem                    *base;
-        struct platform_device          *pdev;
-        struct list_head                node;
-        struct omap_sr_nvalue_table     *nvalue_table;
-        struct voltagedomain            *voltdm;
-        struct dentry                   *dbg_dir;
 };
 
 /* sr_list contains all the instances of smartreflex module */
@@ -74,10 +74,6 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
                                         u32 value)
 {
         u32 reg_val;
-        u32 errconfig_offs = 0, errconfig_mask = 0;
-
-        reg_val = __raw_readl(sr->base + offset);
-        reg_val &= ~mask;
 
         /*
          * Smartreflex error config register is special as it contains
@@ -88,16 +84,15 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
          * if they are currently set, but does allow the caller to write
          * those bits.
          */
-        if (sr->ip_type == SR_TYPE_V1) {
-                errconfig_offs = ERRCONFIG_V1;
-                errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
-        } else if (sr->ip_type == SR_TYPE_V2) {
-                errconfig_offs = ERRCONFIG_V2;
-                errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
-        }
+        if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
+                mask |= ERRCONFIG_STATUS_V1_MASK;
+        else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
+                mask |= ERRCONFIG_VPBOUNDINTST_V2;
+
+        reg_val = __raw_readl(sr->base + offset);
+        reg_val &= ~mask;
 
-        if (offset == errconfig_offs)
-                reg_val &= ~errconfig_mask;
+        value &= mask;
 
         reg_val |= value;
 
@@ -128,21 +123,28 @@ static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
 
 static irqreturn_t sr_interrupt(int irq, void *data)
 {
-        struct omap_sr *sr_info = (struct omap_sr *)data;
+        struct omap_sr *sr_info = data;
         u32 status = 0;
 
-        if (sr_info->ip_type == SR_TYPE_V1) {
+        switch (sr_info->ip_type) {
+        case SR_TYPE_V1:
                 /* Read the status bits */
                 status = sr_read_reg(sr_info, ERRCONFIG_V1);
 
                 /* Clear them by writing back */
                 sr_write_reg(sr_info, ERRCONFIG_V1, status);
-        } else if (sr_info->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 /* Read the status bits */
                 status = sr_read_reg(sr_info, IRQSTATUS);
 
                 /* Clear them by writing back */
                 sr_write_reg(sr_info, IRQSTATUS, status);
+                break;
+        default:
+                dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
+                        sr_info->ip_type);
+                return IRQ_NONE;
         }
 
         if (sr_class->notify)
@@ -166,6 +168,7 @@ static void sr_set_clk_length(struct omap_sr *sr)
                         __func__);
                 return;
         }
+
         sys_clk_speed = clk_get_rate(sys_ck);
         clk_put(sys_ck);
 
@@ -267,7 +270,7 @@ static int sr_late_init(struct omap_sr *sr_info)
                         goto error;
                 }
                 ret = request_irq(sr_info->irq, sr_interrupt,
-                                0, name, (void *)sr_info);
+                                0, name, sr_info);
                 if (ret)
                         goto error;
                 disable_irq(sr_info->irq);
@@ -288,12 +291,15 @@ error:
                 "not function as desired\n", __func__);
         kfree(name);
         kfree(sr_info);
+
         return ret;
 }
 
 static void sr_v1_disable(struct omap_sr *sr)
 {
         int timeout = 0;
+        int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+                        ERRCONFIG_MCUBOUNDINTST;
 
         /* Enable MCUDisableAcknowledge interrupt */
         sr_modify_reg(sr, ERRCONFIG_V1,
@@ -302,13 +308,13 @@ static void sr_v1_disable(struct omap_sr *sr)
         /* SRCONFIG - disable SR */
         sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
 
-        /* Disable all other SR interrupts and clear the status */
+        /* Disable all other SR interrupts and clear the status as needed */
+        if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
+                errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
         sr_modify_reg(sr, ERRCONFIG_V1,
                         (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
                         ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
-                        (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
-                        ERRCONFIG_MCUBOUNDINTST |
-                        ERRCONFIG_VPBOUNDINTST_V1));
+                        errconf_val);
 
         /*
          * Wait for SR to be disabled.
@@ -337,9 +343,17 @@ static void sr_v2_disable(struct omap_sr *sr)
         /* SRCONFIG - disable SR */
         sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
 
-        /* Disable all other SR interrupts and clear the status */
-        sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+        /*
+         * Disable all other SR interrupts and clear the status
+         * write to status register ONLY on need basis - only if status
+         * is set.
+         */
+        if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
+                sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
                         ERRCONFIG_VPBOUNDINTST_V2);
+        else
+                sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+                                0x0);
         sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
                         IRQENABLE_MCUVALIDINT |
                         IRQENABLE_MCUBOUNDSINT));
@@ -398,15 +412,16 @@ static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
  */
 int sr_configure_errgen(struct voltagedomain *voltdm)
 {
-        u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en;
-        u32 vpboundint_st, senp_en = 0, senn_en = 0;
+        u32 sr_config, sr_errconfig, errconfig_offs;
+        u32 vpboundint_en, vpboundint_st;
+        u32 senp_en = 0, senn_en = 0;
         u8 senp_shift, senn_shift;
         struct omap_sr *sr = _sr_lookup(voltdm);
 
         if (IS_ERR(sr)) {
                 pr_warning("%s: omap_sr struct for sr_%s not found\n",
                         __func__, voltdm->name);
-                return -EINVAL;
+                return PTR_ERR(sr);
         }
 
         if (!sr->clk_length)
@@ -418,20 +433,23 @@ int sr_configure_errgen(struct voltagedomain *voltdm)
         sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
                 SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
 
-        if (sr->ip_type == SR_TYPE_V1) {
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
                 sr_config |= SRCONFIG_DELAYCTRL;
                 senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
                 errconfig_offs = ERRCONFIG_V1;
                 vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
                 vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-        } else if (sr->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
                 errconfig_offs = ERRCONFIG_V2;
                 vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
                 vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-        } else {
+                break;
+        default:
                 dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
                         "module without specifying the ip\n", __func__);
                 return -EINVAL;
@@ -447,8 +465,55 @@ int sr_configure_errgen(struct voltagedomain *voltdm)
                 sr_errconfig);
 
         /* Enabling the interrupts if the ERROR module is used */
-        sr_modify_reg(sr, errconfig_offs,
-                vpboundint_en, (vpboundint_en | vpboundint_st));
+        sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
+                      vpboundint_en);
+
+        return 0;
+}
+
+/**
+ * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable the error generator module inside the smartreflex module.
+ *
+ * Returns 0 on success and error value in case of failure.
+ */
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+        u32 errconfig_offs;
+        u32 vpboundint_en, vpboundint_st;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return PTR_ERR(sr);
+        }
+
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
+                errconfig_offs = ERRCONFIG_V1;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+                break;
+        case SR_TYPE_V2:
+                errconfig_offs = ERRCONFIG_V2;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+                break;
+        default:
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Disable the interrupts of ERROR module */
+        sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
+
+        /* Disable the Sensor and errorgen */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
 
         return 0;
 }
@@ -475,7 +540,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
         if (IS_ERR(sr)) {
                 pr_warning("%s: omap_sr struct for sr_%s not found\n",
                         __func__, voltdm->name);
-                return -EINVAL;
+                return PTR_ERR(sr);
         }
 
         if (!sr->clk_length)
@@ -488,14 +553,17 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
                 SRCONFIG_SENENABLE |
                 (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
 
-        if (sr->ip_type == SR_TYPE_V1) {
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
                 sr_config |= SRCONFIG_DELAYCTRL;
                 senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-        } else if (sr->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-        } else {
+                break;
+        default:
                 dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
                         "module without specifying the ip\n", __func__);
                 return -EINVAL;
@@ -511,20 +579,27 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
          * Enabling the interrupts if MINMAXAVG module is used.
          * TODO: check if all the interrupts are mandatory
          */
-        if (sr->ip_type == SR_TYPE_V1) {
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
                 sr_modify_reg(sr, ERRCONFIG_V1,
                         (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
                         ERRCONFIG_MCUBOUNDINTEN),
                         (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
                          ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
                          ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
-        } else if (sr->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 sr_write_reg(sr, IRQSTATUS,
                         IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
                         IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
                 sr_write_reg(sr, IRQENABLE_SET,
                         IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
                         IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+                break;
+        default:
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
         }
 
         return 0;
@@ -543,15 +618,15 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
  */
 int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 {
-        u32 nvalue_reciprocal;
         struct omap_volt_data *volt_data;
         struct omap_sr *sr = _sr_lookup(voltdm);
+        u32 nvalue_reciprocal;
         int ret;
 
         if (IS_ERR(sr)) {
                 pr_warning("%s: omap_sr struct for sr_%s not found\n",
                         __func__, voltdm->name);
-                return -EINVAL;
+                return PTR_ERR(sr);
         }
 
         volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
@@ -559,7 +634,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
         if (IS_ERR(volt_data)) {
                 dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
                         "for nominal voltage %ld\n", __func__, volt);
-                return -ENODATA;
+                return PTR_ERR(volt_data);
         }
 
         nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
@@ -617,10 +692,17 @@ void sr_disable(struct voltagedomain *voltdm)
          * disable the clocks.
          */
         if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
-                if (sr->ip_type == SR_TYPE_V1)
+                switch (sr->ip_type) {
+                case SR_TYPE_V1:
                         sr_v1_disable(sr);
-                else if (sr->ip_type == SR_TYPE_V2)
+                        break;
+                case SR_TYPE_V2:
                         sr_v2_disable(sr);
+                        break;
+                default:
+                        dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
+                                sr->ip_type);
+                }
         }
 
         pm_runtime_put_sync_suspend(&sr->pdev->dev);
@@ -779,10 +861,10 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
         sr_pmic_data = pmic_data;
 }
 
-/* PM Debug Fs enteries to enable disable smartreflex. */
+/* PM Debug FS entries to enable and disable smartreflex. */
 static int omap_sr_autocomp_show(void *data, u64 *val)
 {
-        struct omap_sr *sr_info = (struct omap_sr *) data;
+        struct omap_sr *sr_info = data;
 
         if (!sr_info) {
                 pr_warning("%s: omap_sr struct not found\n", __func__);
@@ -796,7 +878,7 @@ static int omap_sr_autocomp_show(void *data, u64 *val)
 
 static int omap_sr_autocomp_store(void *data, u64 val)
 {
-        struct omap_sr *sr_info = (struct omap_sr *) data;
+        struct omap_sr *sr_info = data;
 
         if (!sr_info) {
                 pr_warning("%s: omap_sr struct not found\n", __func__);
@@ -804,7 +886,7 @@ static int omap_sr_autocomp_store(void *data, u64 val)
         }
 
         /* Sanity check */
-        if (val && (val != 1)) {
+        if (val > 1) {
                 pr_warning("%s: Invalid argument %lld\n", __func__, val);
                 return -EINVAL;
         }
@@ -821,11 +903,11 @@ static int omap_sr_autocomp_store(void *data, u64 val)
 }
 
 DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
-                omap_sr_autocomp_store, "%llu\n");
+                        omap_sr_autocomp_store, "%llu\n");
 
 static int __init omap_sr_probe(struct platform_device *pdev)
 {
-        struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+        struct omap_sr *sr_info;
         struct omap_sr_data *pdata = pdev->dev.platform_data;
         struct resource *mem, *irq;
         struct dentry *nvalue_dir;
@@ -833,12 +915,15 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         int i, ret = 0;
         char *name;
 
+        sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
         if (!sr_info) {
                 dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
                         __func__);
                 return -ENOMEM;
         }
 
+        platform_set_drvdata(pdev, sr_info);
+
         if (!pdata) {
                 dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
                 ret = -EINVAL;
@@ -904,7 +989,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
         if (!sr_dbg_dir) {
                 sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
-                if (!sr_dbg_dir) {
+                if (IS_ERR_OR_NULL(sr_dbg_dir)) {
                         ret = PTR_ERR(sr_dbg_dir);
                         pr_err("%s:sr debugfs dir creation failed(%d)\n",
                                 __func__, ret);
@@ -921,7 +1006,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         }
         sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
         kfree(name);
-        if (IS_ERR(sr_info->dbg_dir)) {
+        if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
                         __func__);
                 ret = PTR_ERR(sr_info->dbg_dir);
@@ -938,7 +1023,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                         &sr_info->err_minlimit);
 
         nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
-        if (IS_ERR(nvalue_dir)) {
+        if (IS_ERR_OR_NULL(nvalue_dir)) {
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
                         "for n-values\n", __func__);
                 ret = PTR_ERR(nvalue_dir);
@@ -994,7 +1079,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
         if (IS_ERR(sr_info)) {
                 dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
                         __func__);
-                return -EINVAL;
+                return PTR_ERR(sr_info);
         }
 
         if (sr_info->autocomp_active)
@@ -1011,8 +1096,32 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
         return 0;
 }
 
+static void __devexit omap_sr_shutdown(struct platform_device *pdev)
+{
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct omap_sr *sr_info;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                return;
+        }
+
+        sr_info = _sr_lookup(pdata->voltdm);
+        if (IS_ERR(sr_info)) {
+                dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+                        __func__);
+                return;
+        }
+
+        if (sr_info->autocomp_active)
+                sr_stop_vddautocomp(sr_info);
+
+        return;
+}
+
 static struct platform_driver smartreflex_driver = {
-        .remove         = omap_sr_remove,
+        .remove         = __devexit_p(omap_sr_remove),
+        .shutdown       = __devexit_p(omap_sr_shutdown),
         .driver         = {
                 .name   = "smartreflex",
         },
@@ -1042,12 +1151,12 @@ static int __init sr_init(void)
 
         return 0;
 }
+late_initcall(sr_init);
 
 static void __exit sr_exit(void)
 {
         platform_driver_unregister(&smartreflex_driver);
 }
-late_initcall(sr_init);
 module_exit(sr_exit);
 
 MODULE_DESCRIPTION("OMAP Smartreflex Driver");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 5f35b9e2555..5809141171f 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -152,6 +152,15 @@ struct omap_sr_pmic_data {
         void (*sr_pmic_init) (void);
 };
 
+/**
+ * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
+ *
+ * @sensor_voltdm_name:       Name of voltdomain of SR instance
+ */
+struct omap_smartreflex_dev_attr {
+        const char      *sensor_voltdm_name;
+};
+
 #ifdef CONFIG_OMAP_SMARTREFLEX
 /*
  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
@@ -231,6 +240,7 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
 int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
 void sr_disable(struct voltagedomain *voltdm);
 int sr_configure_errgen(struct voltagedomain *voltdm);
+int sr_disable_errgen(struct voltagedomain *voltdm);
 int sr_configure_minmax(struct voltagedomain *voltdm);
 
 /* API to register the smartreflex class driver with the smartreflex driver */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 9f43fcc05d3..a503e1e8358 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -69,11 +69,12 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
         sr_data->nvalue_count = count;
 }
 
-static int sr_dev_init(struct omap_hwmod *oh, void *user)
+static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 {
         struct omap_sr_data *sr_data;
         struct platform_device *pdev;
         struct omap_volt_data *volt_data;
+        struct omap_smartreflex_dev_attr *sr_dev_attr;
         char *name = "smartreflex";
         static int i;
 
@@ -84,9 +85,11 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
                 return -ENOMEM;
         }
 
-        if (!oh->vdd_name) {
+        sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
+        if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
                 pr_err("%s: No voltage domain specified for %s."
-                        "Cannot initialize\n", __func__, oh->name);
+                                "Cannot initialize\n", __func__,
+                                        oh->name);
                 goto exit;
         }
 
@@ -94,10 +97,10 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
         sr_data->senn_mod = 0x1;
         sr_data->senp_mod = 0x1;
 
-        sr_data->voltdm = voltdm_lookup(oh->vdd_name);
+        sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
         if (IS_ERR(sr_data->voltdm)) {
                 pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
-                        __func__, oh->vdd_name);
+                        __func__, sr_dev_attr->sensor_voltdm_name);
                 goto exit;
         }
 
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index ff9b9dbcb30..ee0bfcc1410 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -29,10 +29,12 @@
  * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
-#include <mach/io.h>
+
 #include <mach/hardware.h>
 
+#include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index 76730209fa0..d4d39ef0476 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -29,10 +29,12 @@
  * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
-#include <mach/io.h>
+
 #include <mach/hardware.h>
 
+#include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 6f5849aaa7c..df5a21322b0 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -26,11 +26,12 @@
  * MA 02111-1307 USA
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
-#include <mach/hardware.h>
 
-#include <mach/io.h>
+#include <mach/hardware.h>
 
+#include "iomap.h"
 #include "sdrc.h"
 #include "cm2xxx_3xxx.h"
 
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
deleted file mode 100644
index 31c0ac4cd66..00000000000
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * The MPU local timer source file. In OMAP4, both cortex-a9 cores have
- * own timer in it's MPU domain. These timers will be driving the
- * linux kernel SMP tick framework when active. These timers are not
- * part of the wake up domain.
- *
- * Copyright (C) 2009 Texas Instruments, Inc.
- *
- * Author:
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is based on arm realview smp platform file.
- * Copyright (C) 2002 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        /* Local timers are not supprted on OMAP4430 ES1.0 */
-        if (omap_rev() == OMAP4430_REV_ES1_0)
-                return -ENXIO;
-
-        evt->irq = OMAP44XX_IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
-
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5c9acea9576..c512bac69ec 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -39,7 +39,7 @@
 
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
@@ -324,14 +324,26 @@ OMAP_SYS_TIMER(3_secure)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-static void __init omap4_timer_init(void)
-{
 #ifdef CONFIG_LOCAL_TIMERS
-        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-        BUG_ON(!twd_base);
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              OMAP44XX_LOCAL_TWD_BASE,
+                              OMAP44XX_IRQ_LOCALTIMER);
 #endif
+
+static void __init omap4_timer_init(void)
+{
         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
         omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
+#ifdef CONFIG_LOCAL_TIMERS
+        /* Local timers are not supprted on OMAP4430 ES1.0 */
+        if (omap_rev() != OMAP4430_REV_ES1_0) {
+                int err;
+
+                err = twd_local_timer_register(&twd_local_timer);
+                if (err)
+                        pr_err("twd_local_timer_register failed %d\n", err);
+        }
+#endif
 }
 OMAP_SYS_TIMER(4)
 #endif
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 175b7d86d86..84da34f9a7c 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -10,6 +10,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 0df88820978..f95c1bad9dc 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -61,8 +61,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
         vddmin = voltdm->pmic->vp_vddmin;
         vddmax = voltdm->pmic->vp_vddmax;
 
-        waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
-                    sys_clk_rate) / 1000;
+        waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
+                                1000 * voltdm->pmic->slew_rate);
         vstepmin = voltdm->pmic->vp_vstepmin;
         vstepmax = voltdm->pmic->vp_vstepmax;
 
diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S
index d658992e540..79eb502a1e6 100644
--- a/arch/arm/mach-orion5x/include/mach/entry-macro.S
+++ b/arch/arm/mach-orion5x/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =MAIN_IRQ_CAUSE
         .endm
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
deleted file mode 100644
index 825a2650cef..00000000000
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/system.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 09a045f0c40..d6a91948e4d 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -171,13 +171,14 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         /*
          * IORESOURCE_IO
          */
+        sys->io_offset = 0;
         res[0].name = "PCIe I/O Space";
         res[0].flags = IORESOURCE_IO;
         res[0].start = ORION5X_PCIE_IO_BUS_BASE;
         res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
         if (request_resource(&ioport_resource, &res[0]))
                 panic("Request PCIe IO resource failed\n");
-        pci_add_resource(&sys->resources, &res[0]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -188,9 +189,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
         if (request_resource(&iomem_resource, &res[1]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource(&sys->resources, &res[1]);
-
-        sys->io_offset = 0;
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
@@ -499,13 +498,14 @@ static int __init pci_setup(struct pci_sys_data *sys)
         /*
          * IORESOURCE_IO
          */
+        sys->io_offset = 0;
         res[0].name = "PCI I/O Space";
         res[0].flags = IORESOURCE_IO;
         res[0].start = ORION5X_PCI_IO_BUS_BASE;
         res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
         if (request_resource(&ioport_resource, &res[0]))
                 panic("Request PCI IO resource failed\n");
-        pci_add_resource(&sys->resources, &res[0]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -516,9 +516,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
         res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
         if (request_resource(&iomem_resource, &res[1]))
                 panic("Request PCI Memory resource failed\n");
-        pci_add_resource(&sys->resources, &res[1]);
-
-        sys->io_offset = 0;
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
deleted file mode 100644
index 9b505ac00be..00000000000
--- a/arch/arm/mach-picoxcell/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * entry-macro.S
- *
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * Low-level IRQ helper macros for picoXcell platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
deleted file mode 100644
index 1a5d8cb57df..00000000000
--- a/arch/arm/mach-picoxcell/include/mach/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching and wait for interrupt
-         * tricks.
-         */
-        cpu_do_idle();
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
index db7eeebf30d..77a55584671 100644
--- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
@@ -25,15 +25,9 @@
 #define SIC1_BASE_INT   32
 #define SIC2_BASE_INT   64
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 /* decode the MIC interrupt numbers */
                 ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
deleted file mode 100644
index 60cfe718809..00000000000
--- a/arch/arm/mach-pnx4008/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/system.h
- *
- * Copyright (C) 2003 Philips Semiconductors
- * Copyright (C) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
index 1c8a50f102a..86434e7a5be 100644
--- a/arch/arm/mach-prima2/include/mach/entry-macro.S
+++ b/arch/arm/mach-prima2/include/mach/entry-macro.S
@@ -20,10 +20,3 @@
         cmp \irqnr, #0x40                       @ the irq num can't be larger than 0x3f
         movges \irqnr, #0
         .endm
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
diff --git a/arch/arm/mach-prima2/include/mach/system.h b/arch/arm/mach-prima2/include/mach/system.h
deleted file mode 100644
index 2c7d2a9d0c9..00000000000
--- a/arch/arm/mach-prima2/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/system.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_SYSTEM_H__
-#define __MACH_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 5bc13121eac..84f2d7015cf 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -406,20 +406,17 @@ static struct resource pxa_rtc_resources[] = {
         [1] = {
                 .start  = IRQ_RTC1Hz,
                 .end    = IRQ_RTC1Hz,
+                .name   = "rtc 1Hz",
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
                 .start  = IRQ_RTCAlrm,
                 .end    = IRQ_RTCAlrm,
+                .name   = "rtc alarm",
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-struct platform_device sa1100_device_rtc = {
-        .name           = "sa1100-rtc",
-        .id             = -1,
-};
-
 struct platform_device pxa_device_rtc = {
         .name           = "pxa-rtc",
         .id             = -1,
@@ -427,6 +424,27 @@ struct platform_device pxa_device_rtc = {
         .resource       = pxa_rtc_resources,
 };
 
+static struct resource sa1100_rtc_resources[] = {
+        {
+                .start  = IRQ_RTC1Hz,
+                .end    = IRQ_RTC1Hz,
+                .name   = "rtc 1Hz",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_RTCAlrm,
+                .end    = IRQ_RTCAlrm,
+                .name   = "rtc alarm",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device sa1100_device_rtc = {
+        .name           = "sa1100-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
+        .resource       = sa1100_rtc_resources,
+};
+
 static struct resource pxa_ac97_resources[] = {
         [0] = {
                 .start  = 0x40500000,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 208eef1c048..3fa929d4a4f 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -28,7 +28,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
-#include <linux/regulator/bq24022.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max1586.h>
 #include <linux/spi/ads7846.h>
@@ -97,9 +98,9 @@ static unsigned long hx4700_pin_config[] __initdata = {
 
         /* BTUART */
         GPIO42_BTUART_RXD,
-        GPIO43_BTUART_TXD,
+        GPIO43_BTUART_TXD_LPM_LOW,
         GPIO44_BTUART_CTS,
-        GPIO45_BTUART_RTS,
+        GPIO45_BTUART_RTS_LPM_LOW,
 
         /* PWM 1 (Backlight) */
         GPIO17_PWM1_OUT,
@@ -245,6 +246,21 @@ static u16 asic3_gpio_config[] = {
         ASIC3_GPIOD15_nPIOW,
 };
 
+static struct asic3_led asic3_leds[ASIC3_NUM_LEDS] = {
+        [0] = {
+                .name = "hx4700:amber",
+                .default_trigger = "ds2760-battery.0-charging-blink-full-solid",
+        },
+        [1] = {
+                .name = "hx4700:green",
+                .default_trigger = "unused",
+        },
+        [2] = {
+                .name = "hx4700:blue",
+                .default_trigger = "hx4700-radio",
+        },
+};
+
 static struct resource asic3_resources[] = {
         /* GPIO part */
         [0] = {
@@ -275,6 +291,7 @@ static struct asic3_platform_data asic3_platform_data = {
         .gpio_config_num = ARRAY_SIZE(asic3_gpio_config),
         .irq_base        = IRQ_BOARD_START,
         .gpio_base       = HX4700_ASIC3_GPIO_BASE,
+        .leds            = asic3_leds,
 };
 
 static struct platform_device asic3 = {
@@ -682,14 +699,34 @@ static struct regulator_init_data bq24022_init_data = {
         .consumer_supplies      = bq24022_consumers,
 };
 
-static struct bq24022_mach_info bq24022_info = {
-        .gpio_nce   = GPIO72_HX4700_BQ24022_nCHARGE_EN,
-        .gpio_iset2 = GPIO96_HX4700_BQ24022_ISET2,
-        .init_data  = &bq24022_init_data,
+static struct gpio bq24022_gpios[] = {
+        { GPIO96_HX4700_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
+};
+
+static struct gpio_regulator_state bq24022_states[] = {
+        { .value = 100000, .gpios = (0 << 0) },
+        { .value = 500000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config bq24022_info = {
+        .supply_name = "bq24022",
+
+        .enable_gpio = GPIO72_HX4700_BQ24022_nCHARGE_EN,
+        .enable_high = 0,
+        .enabled_at_boot = 0,
+
+        .gpios = bq24022_gpios,
+        .nr_gpios = ARRAY_SIZE(bq24022_gpios),
+
+        .states = bq24022_states,
+        .nr_states = ARRAY_SIZE(bq24022_states),
+
+        .type = REGULATOR_CURRENT,
+        .init_data = &bq24022_init_data,
 };
 
 static struct platform_device bq24022 = {
-        .name = "bq24022",
+        .name = "gpio-regulator",
         .id   = -1,
         .dev  = {
                 .platform_data = &bq24022_info,
@@ -705,10 +742,9 @@ static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
         gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
 }
 
-static struct resource strataflash_resource = {
-        .start = PXA_CS0_PHYS,
-        .end   = PXA_CS0_PHYS + SZ_128M - 1,
-        .flags = IORESOURCE_MEM,
+static struct resource strataflash_resource[] = {
+        [0] = DEFINE_RES_MEM(PXA_CS0_PHYS, SZ_64M),
+        [1] = DEFINE_RES_MEM(PXA_CS0_PHYS + SZ_64M, SZ_64M),
 };
 
 static struct physmap_flash_data strataflash_data = {
@@ -719,8 +755,8 @@ static struct physmap_flash_data strataflash_data = {
 static struct platform_device strataflash = {
         .name          = "physmap-flash",
         .id            = -1,
-        .resource      = &strataflash_resource,
-        .num_resources = 1,
+        .resource      = strataflash_resource,
+        .num_resources = ARRAY_SIZE(strataflash_resource),
         .dev = {
                 .platform_data = &strataflash_data,
         },
@@ -788,17 +824,6 @@ static struct platform_device audio = {
 
 
 /*
- * PCMCIA
- */
-
-static struct platform_device pcmcia = {
-        .name = "hx4700-pcmcia",
-        .dev  = {
-                .parent = &asic3.dev,
-        },
-};
-
-/*
  * Platform devices
  */
 
@@ -814,7 +839,6 @@ static struct platform_device *devices[] __initdata = {
         &power_supply,
         &strataflash,
         &audio,
-        &pcmcia,
 };
 
 static struct gpio global_gpios[] = {
@@ -830,7 +854,6 @@ static struct gpio global_gpios[] = {
         { GPIO32_HX4700_RS232_ON,         GPIOF_OUT_INIT_HIGH, "RS232_ON" },
         { GPIO71_HX4700_ASIC3_nRESET,     GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
         { GPIO82_HX4700_EUART_RESET,      GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
-        { GPIO105_HX4700_nIR_ON,          GPIOF_OUT_INIT_HIGH, "nIR_EN" },
 };
 
 static void __init hx4700_init(void)
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index f02fa1e6ba8..954641e6c8b 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -174,7 +174,6 @@ enum balloon3_features {
 
 #define BALLOON3_AUX_NIRQ       PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
 #define BALLOON3_CODEC_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
-#define BALLOON3_S0_CD_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_S0_CD)
 
 #define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 16)
 
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
deleted file mode 100644
index 260c0c17692..00000000000
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PXA-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index ec0f0b0b674..a65867209aa 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -158,7 +158,9 @@
 #define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
 #define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
 #define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+#define GPIO45_BTUART_RTS_LPM_LOW       MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW)
 #define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+#define GPIO43_BTUART_TXD_LPM_LOW       MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW)
 
 /* STUART */
 #define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
deleted file mode 100644
index c5afacd3cc0..00000000000
--- a/arch/arm/mach-pxa/include/mach/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/system.h
- *
- * Author:      Nicolas Pitre
- * Created:     Jun 15, 2001
- * Copyright:   MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 6ebd276aebe..6bb3f47b1f1 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -223,6 +223,7 @@ static struct resource sa1111_resources[] = {
 
 static struct sa1111_platform_data sa1111_info = {
         .irq_base       = LUBBOCK_SA1111_IRQ_BASE,
+        .disable_devs   = SA1111_DEVID_SAC,
 };
 
 static struct platform_device sa1111_device = {
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index d4ab515dc5b..6f4785b347c 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -25,7 +25,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
-#include <linux/regulator/bq24022.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -597,14 +598,34 @@ static struct regulator_init_data bq24022_init_data = {
         .consumer_supplies      = bq24022_consumers,
 };
 
-static struct bq24022_mach_info bq24022_info = {
-        .gpio_nce   = GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
-        .gpio_iset2 = EGPIO_MAGICIAN_BQ24022_ISET2,
-        .init_data  = &bq24022_init_data,
+static struct gpio bq24022_gpios[] = {
+        { EGPIO_MAGICIAN_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
+};
+
+static struct gpio_regulator_state bq24022_states[] = {
+        { .value = 100000, .gpios = (0 << 0) },
+        { .value = 500000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config bq24022_info = {
+        .supply_name = "bq24022",
+
+        .enable_gpio = GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
+        .enable_high = 0,
+        .enabled_at_boot = 0,
+
+        .gpios = bq24022_gpios,
+        .nr_gpios = ARRAY_SIZE(bq24022_gpios),
+
+        .states = bq24022_states,
+        .nr_states = ARRAY_SIZE(bq24022_states),
+
+        .type = REGULATOR_CURRENT,
+        .init_data = &bq24022_init_data,
 };
 
 static struct platform_device bq24022 = {
-        .name = "bq24022",
+        .name = "gpio-regulator",
         .id   = -1,
         .dev  = {
                 .platform_data = &bq24022_info,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 3918a672238..1570d457fea 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -89,6 +89,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
         INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index 5ce434b95e8..47601f80e6e 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -231,6 +231,7 @@ static struct clk_lookup pxa95x_clkregs[] = {
         INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
         INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
         INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 void __init pxa95x_init_irq(void)
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 735b57aaf2d..f8f2c0ac4c0 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -28,21 +28,11 @@
 #include <asm/setup.h>
 #include <asm/leds.h>
 
-#define AMBA_DEVICE(name,busid,base,plat)                       \
-static struct amba_device name##_device = {                     \
-        .dev            = {                                     \
-                .coherent_dma_mask = ~0,                        \
-                .init_name = busid,                             \
-                .platform_data = plat,                          \
-        },                                                      \
-        .res            = {                                     \
-                .start  = REALVIEW_##base##_BASE,               \
-                .end    = (REALVIEW_##base##_BASE) + SZ_4K - 1, \
-                .flags  = IORESOURCE_MEM,                       \
-        },                                                      \
-        .dma_mask       = ~0,                                   \
-        .irq            = base##_IRQ,                           \
-}
+#define APB_DEVICE(name, busid, base, plat)                     \
+static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
+
+#define AHB_DEVICE(name, busid, base, plat)                     \
+static AMBA_AHB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
 
 struct machine_desc;
 
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
deleted file mode 100644
index e8a5179c265..00000000000
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-realview/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for RealView platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
index 204d5378f30..d6b5073692d 100644
--- a/arch/arm/mach-realview/include/mach/irqs-eb.h
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -96,16 +96,19 @@
 #define IRQ_EB11MP_L220_SLAVE   (IRQ_EB_GIC_START + 30)
 #define IRQ_EB11MP_L220_DECODE  (IRQ_EB_GIC_START + 31)
 
-#define IRQ_EB11MP_UART2        -1
-#define IRQ_EB11MP_UART3        -1
-#define IRQ_EB11MP_CLCD         -1
-#define IRQ_EB11MP_DMA          -1
-#define IRQ_EB11MP_WDOG         -1
-#define IRQ_EB11MP_GPIO0        -1
-#define IRQ_EB11MP_GPIO1        -1
-#define IRQ_EB11MP_GPIO2        -1
-#define IRQ_EB11MP_SCI          -1
-#define IRQ_EB11MP_SSP          -1
+/*
+ * The 11MPcore tile leaves the following unconnected.
+ */
+#define IRQ_EB11MP_UART2        0
+#define IRQ_EB11MP_UART3        0
+#define IRQ_EB11MP_CLCD         0
+#define IRQ_EB11MP_DMA          0
+#define IRQ_EB11MP_WDOG         0
+#define IRQ_EB11MP_GPIO0        0
+#define IRQ_EB11MP_GPIO1        0
+#define IRQ_EB11MP_GPIO2        0
+#define IRQ_EB11MP_SCI          0
+#define IRQ_EB11MP_SSP          0
 
 #define NR_GIC_EB11MP           2
 
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 5c3c625e3e0..708f84156f2 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -40,6 +40,7 @@
 #define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
 #define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
 #define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_GPIO0        (IRQ_DC1176_GIC_START + 16)
 #define IRQ_DC1176_SSP          (IRQ_DC1176_GIC_START + 17)     /* SSP port */
 #define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
 #define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
@@ -73,7 +74,6 @@
 #define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
 #define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
 
-#define IRQ_PB1176_GPIO0        -1
 #define IRQ_PB1176_SCTL         -1
 
 #define NR_GIC_PB1176           2
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
deleted file mode 100644
index 471b671159c..00000000000
--- a/arch/arm/mach-realview/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-realview/include/mach/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 9578145f2df..baf382c5e77 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -36,7 +36,7 @@
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -135,63 +135,63 @@ static struct pl022_ssp_controller ssp0_plat_data = {
 /*
  * These devices are connected via the core APB bridge
  */
-#define GPIO2_IRQ       { IRQ_EB_GPIO2, NO_IRQ }
-#define GPIO3_IRQ       { IRQ_EB_GPIO3, NO_IRQ }
+#define GPIO2_IRQ       { IRQ_EB_GPIO2 }
+#define GPIO3_IRQ       { IRQ_EB_GPIO3 }
 
-#define AACI_IRQ        { IRQ_EB_AACI, NO_IRQ }
+#define AACI_IRQ        { IRQ_EB_AACI }
 #define MMCI0_IRQ       { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
-#define KMI0_IRQ        { IRQ_EB_KMI0, NO_IRQ }
-#define KMI1_IRQ        { IRQ_EB_KMI1, NO_IRQ }
+#define KMI0_IRQ        { IRQ_EB_KMI0 }
+#define KMI1_IRQ        { IRQ_EB_KMI1 }
 
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
-#define EB_SMC_IRQ      { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define EB_CLCD_IRQ     { IRQ_EB_CLCD, NO_IRQ }
-#define DMAC_IRQ        { IRQ_EB_DMA, NO_IRQ }
+#define EB_SMC_IRQ      { }
+#define MPMC_IRQ        { }
+#define EB_CLCD_IRQ     { IRQ_EB_CLCD }
+#define DMAC_IRQ        { IRQ_EB_DMA }
 
 /*
  * These devices are connected via the core APB bridge
  */
-#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
-#define EB_GPIO0_IRQ    { IRQ_EB_GPIO0, NO_IRQ }
-#define GPIO1_IRQ       { IRQ_EB_GPIO1, NO_IRQ }
-#define EB_RTC_IRQ      { IRQ_EB_RTC, NO_IRQ }
+#define SCTL_IRQ        { }
+#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG }
+#define EB_GPIO0_IRQ    { IRQ_EB_GPIO0 }
+#define GPIO1_IRQ       { IRQ_EB_GPIO1 }
+#define EB_RTC_IRQ      { IRQ_EB_RTC }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
-#define SCI_IRQ         { IRQ_EB_SCI, NO_IRQ }
-#define EB_UART0_IRQ    { IRQ_EB_UART0, NO_IRQ }
-#define EB_UART1_IRQ    { IRQ_EB_UART1, NO_IRQ }
-#define EB_UART2_IRQ    { IRQ_EB_UART2, NO_IRQ }
-#define EB_UART3_IRQ    { IRQ_EB_UART3, NO_IRQ }
-#define EB_SSP_IRQ      { IRQ_EB_SSP, NO_IRQ }
+#define SCI_IRQ         { IRQ_EB_SCI }
+#define EB_UART0_IRQ    { IRQ_EB_UART0 }
+#define EB_UART1_IRQ    { IRQ_EB_UART1 }
+#define EB_UART2_IRQ    { IRQ_EB_UART2 }
+#define EB_UART3_IRQ    { IRQ_EB_UART3 }
+#define EB_SSP_IRQ      { IRQ_EB_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,  "fpga:aaci",  AACI,     NULL);
-AMBA_DEVICE(mmc0,  "fpga:mmc0",  MMCI0,    &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,  "fpga:kmi0",  KMI0,     NULL);
-AMBA_DEVICE(kmi1,  "fpga:kmi1",  KMI1,     NULL);
-AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
+APB_DEVICE(aaci,  "fpga:aaci",  AACI,     NULL);
+APB_DEVICE(mmc0,  "fpga:mmc0",  MMCI0,    &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,  "fpga:kmi0",  KMI0,     NULL);
+APB_DEVICE(kmi1,  "fpga:kmi1",  KMI1,     NULL);
+APB_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,   "dev:smc",   EB_SMC,   NULL);
-AMBA_DEVICE(clcd,  "dev:clcd",  EB_CLCD,  &clcd_plat_data);
-AMBA_DEVICE(dmac,  "dev:dmac",  DMAC,     NULL);
-AMBA_DEVICE(sctl,  "dev:sctl",  SCTL,     NULL);
-AMBA_DEVICE(wdog,  "dev:wdog",  EB_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
-AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1,    &gpio1_plat_data);
-AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2,    &gpio2_plat_data);
-AMBA_DEVICE(rtc,   "dev:rtc",   EB_RTC,   NULL);
-AMBA_DEVICE(sci0,  "dev:sci0",  SCI,      NULL);
-AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
-AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
-AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
-AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   &ssp0_plat_data);
+AHB_DEVICE(smc,   "dev:smc",   EB_SMC,   NULL);
+AHB_DEVICE(clcd,  "dev:clcd",  EB_CLCD,  &clcd_plat_data);
+AHB_DEVICE(dmac,  "dev:dmac",  DMAC,     NULL);
+AHB_DEVICE(sctl,  "dev:sctl",  SCTL,     NULL);
+APB_DEVICE(wdog,  "dev:wdog",  EB_WATCHDOG, NULL);
+APB_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
+APB_DEVICE(gpio1, "dev:gpio1", GPIO1,    &gpio1_plat_data);
+APB_DEVICE(gpio2, "dev:gpio2", GPIO2,    &gpio2_plat_data);
+APB_DEVICE(rtc,   "dev:rtc",   EB_RTC,   NULL);
+APB_DEVICE(sci0,  "dev:sci0",  SCI,      NULL);
+APB_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
+APB_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
+APB_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
+APB_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -383,6 +383,23 @@ static void realview_eb11mp_fixup(void)
         realview_eb_isp1761_resources[1].end    = IRQ_EB11MP_USB;
 }
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              REALVIEW_EB11MP_TWD_BASE,
+                              IRQ_LOCALTIMER);
+
+static void __init realview_eb_twd_init(void)
+{
+        if (core_tile_eb11mp() || core_tile_a9mp()) {
+                int err = twd_local_timer_register(&twd_local_timer);
+                if (err)
+                        pr_err("twd_local_timer_register failed %d\n", err);
+        }
+}
+#else
+#define realview_eb_twd_init()  do { } while(0)
+#endif
+
 static void __init realview_eb_timer_init(void)
 {
         unsigned int timer_irq;
@@ -392,15 +409,13 @@ static void __init realview_eb_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
 
-        if (core_tile_eb11mp() || core_tile_a9mp()) {
-#ifdef CONFIG_LOCAL_TIMERS
-                twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE);
-#endif
+        if (core_tile_eb11mp() || core_tile_a9mp())
                 timer_irq = IRQ_EB11MP_TIMER0_1;
-        } else
+        else
                 timer_irq = IRQ_EB_TIMER0_1;
 
         realview_timer_init(timer_irq);
+        realview_eb_twd_init();
 }
 
 static struct sys_timer realview_eb_timer = {
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index e4abe94fb11..b1d7cafa1a6 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -132,50 +132,50 @@ static struct pl022_ssp_controller ssp0_plat_data = {
 /*
  * RealView PB1176 AMBA devices
  */
-#define GPIO2_IRQ       { IRQ_PB1176_GPIO2, NO_IRQ }
-#define GPIO3_IRQ       { IRQ_PB1176_GPIO3, NO_IRQ }
-#define AACI_IRQ        { IRQ_PB1176_AACI, NO_IRQ }
+#define GPIO2_IRQ       { IRQ_PB1176_GPIO2 }
+#define GPIO3_IRQ       { IRQ_PB1176_GPIO3 }
+#define AACI_IRQ        { IRQ_PB1176_AACI }
 #define MMCI0_IRQ       { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
-#define KMI0_IRQ        { IRQ_PB1176_KMI0, NO_IRQ }
-#define KMI1_IRQ        { IRQ_PB1176_KMI1, NO_IRQ }
-#define PB1176_SMC_IRQ  { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
-#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
-#define PB1176_GPIO0_IRQ        { IRQ_PB1176_GPIO0, NO_IRQ }
-#define GPIO1_IRQ       { IRQ_PB1176_GPIO1, NO_IRQ }
-#define PB1176_RTC_IRQ  { IRQ_DC1176_RTC, NO_IRQ }
-#define SCI_IRQ         { IRQ_PB1176_SCI, NO_IRQ }
-#define PB1176_UART0_IRQ        { IRQ_DC1176_UART0, NO_IRQ }
-#define PB1176_UART1_IRQ        { IRQ_DC1176_UART1, NO_IRQ }
-#define PB1176_UART2_IRQ        { IRQ_DC1176_UART2, NO_IRQ }
-#define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
-#define PB1176_UART4_IRQ        { IRQ_PB1176_UART4, NO_IRQ }
-#define PB1176_SSP_IRQ          { IRQ_DC1176_SSP, NO_IRQ }
+#define KMI0_IRQ        { IRQ_PB1176_KMI0 }
+#define KMI1_IRQ        { IRQ_PB1176_KMI1 }
+#define PB1176_SMC_IRQ  { }
+#define MPMC_IRQ        { }
+#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD }
+#define SCTL_IRQ        { }
+#define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG }
+#define PB1176_GPIO0_IRQ        { IRQ_DC1176_GPIO0 }
+#define GPIO1_IRQ       { IRQ_PB1176_GPIO1 }
+#define PB1176_RTC_IRQ  { IRQ_DC1176_RTC }
+#define SCI_IRQ         { IRQ_PB1176_SCI }
+#define PB1176_UART0_IRQ        { IRQ_DC1176_UART0 }
+#define PB1176_UART1_IRQ        { IRQ_DC1176_UART1 }
+#define PB1176_UART2_IRQ        { IRQ_DC1176_UART2 }
+#define PB1176_UART3_IRQ        { IRQ_DC1176_UART3 }
+#define PB1176_UART4_IRQ        { IRQ_PB1176_UART4 }
+#define PB1176_SSP_IRQ          { IRQ_DC1176_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart4,      "fpga:uart4",   PB1176_UART4,   NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart4,       "fpga:uart4",   PB1176_UART4,   NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PB1176_SMC,     NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PB1176_WATCHDOG,        NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PB1176_GPIO0,   &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PB1176_RTC,     NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PB1176_UART0,   NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PB1176_UART1,   NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PB1176_UART2,   NULL);
-AMBA_DEVICE(uart3,      "dev:uart3",    PB1176_UART3,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB1176_SSP,     &ssp0_plat_data);
-AMBA_DEVICE(clcd,       "dev:clcd",     PB1176_CLCD,    &clcd_plat_data);
+AHB_DEVICE(smc,         "dev:smc",      PB1176_SMC,     NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PB1176_WATCHDOG,        NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PB1176_GPIO0,   &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PB1176_RTC,     NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PB1176_UART0,   NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PB1176_UART1,   NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PB1176_UART2,   NULL);
+APB_DEVICE(uart3,       "dev:uart3",    PB1176_UART3,   NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PB1176_SSP,     &ssp0_plat_data);
+AHB_DEVICE(clcd,        "dev:clcd",     PB1176_CLCD,    &clcd_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 2147335f66f..a98c536e332 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -36,7 +36,7 @@
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -127,52 +127,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PB11MPCore AMBA devices
  */
 
-#define GPIO2_IRQ               { IRQ_PB11MP_GPIO2, NO_IRQ }
-#define GPIO3_IRQ               { IRQ_PB11MP_GPIO3, NO_IRQ }
-#define AACI_IRQ                { IRQ_TC11MP_AACI, NO_IRQ }
+#define GPIO2_IRQ               { IRQ_PB11MP_GPIO2 }
+#define GPIO3_IRQ               { IRQ_PB11MP_GPIO3 }
+#define AACI_IRQ                { IRQ_TC11MP_AACI }
 #define MMCI0_IRQ               { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
-#define KMI0_IRQ                { IRQ_TC11MP_KMI0, NO_IRQ }
-#define KMI1_IRQ                { IRQ_TC11MP_KMI1, NO_IRQ }
-#define PB11MP_SMC_IRQ          { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD, NO_IRQ }
-#define DMAC_IRQ                { IRQ_PB11MP_DMAC, NO_IRQ }
-#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG, NO_IRQ }
-#define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0, NO_IRQ }
-#define GPIO1_IRQ               { IRQ_PB11MP_GPIO1, NO_IRQ }
-#define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC, NO_IRQ }
-#define SCI_IRQ                 { IRQ_PB11MP_SCI, NO_IRQ }
-#define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0, NO_IRQ }
-#define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1, NO_IRQ }
-#define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2, NO_IRQ }
-#define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3, NO_IRQ }
-#define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP, NO_IRQ }
+#define KMI0_IRQ                { IRQ_TC11MP_KMI0 }
+#define KMI1_IRQ                { IRQ_TC11MP_KMI1 }
+#define PB11MP_SMC_IRQ          { }
+#define MPMC_IRQ                { }
+#define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD }
+#define DMAC_IRQ                { IRQ_PB11MP_DMAC }
+#define SCTL_IRQ                { }
+#define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG }
+#define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0 }
+#define GPIO1_IRQ               { IRQ_PB11MP_GPIO1 }
+#define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC }
+#define SCI_IRQ                 { IRQ_PB11MP_SCI }
+#define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0 }
+#define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1 }
+#define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2 }
+#define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3 }
+#define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PB11MP_UART3,   NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart3,       "fpga:uart3",   PB11MP_UART3,   NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PB11MP_SMC,     NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PB11MP_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PB11MP_GPIO0,   &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PB11MP_RTC,     NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PB11MP_UART0,   NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PB11MP_UART1,   NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PB11MP_UART2,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
+AHB_DEVICE(smc,         "dev:smc",      PB11MP_SMC,     NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PB11MP_WATCHDOG, NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PB11MP_GPIO0,   &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PB11MP_RTC,     NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PB11MP_UART0,   NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PB11MP_UART1,   NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PB11MP_UART2,   NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);
-AMBA_DEVICE(dmac,       "issp:dmac",    DMAC,           NULL);
+AHB_DEVICE(clcd,        "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);
+AHB_DEVICE(dmac,        "issp:dmac",    DMAC,           NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -290,6 +290,21 @@ static void __init gic_init_irq(void)
         gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
 }
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              REALVIEW_TC11MP_TWD_BASE,
+                              IRQ_LOCALTIMER);
+
+static void __init realview_pb11mp_twd_init(void)
+{
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+}
+#else
+#define realview_pb11mp_twd_init()      do {} while(0)
+#endif
+
 static void __init realview_pb11mp_timer_init(void)
 {
         timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
@@ -297,10 +312,8 @@ static void __init realview_pb11mp_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
 
-#ifdef CONFIG_LOCAL_TIMERS
-        twd_base = __io_address(REALVIEW_TC11MP_TWD_BASE);
-#endif
         realview_timer_init(IRQ_TC11MP_TIMER0_1);
+        realview_pb11mp_twd_init();
 }
 
 static struct sys_timer realview_pb11mp_timer = {
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 25b2e59296f..59650174e6e 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -122,52 +122,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PBA8Core AMBA devices
  */
 
-#define GPIO2_IRQ               { IRQ_PBA8_GPIO2, NO_IRQ }
-#define GPIO3_IRQ               { IRQ_PBA8_GPIO3, NO_IRQ }
-#define AACI_IRQ                { IRQ_PBA8_AACI, NO_IRQ }
+#define GPIO2_IRQ               { IRQ_PBA8_GPIO2 }
+#define GPIO3_IRQ               { IRQ_PBA8_GPIO3 }
+#define AACI_IRQ                { IRQ_PBA8_AACI }
 #define MMCI0_IRQ               { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
-#define KMI0_IRQ                { IRQ_PBA8_KMI0, NO_IRQ }
-#define KMI1_IRQ                { IRQ_PBA8_KMI1, NO_IRQ }
-#define PBA8_SMC_IRQ            { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define PBA8_CLCD_IRQ           { IRQ_PBA8_CLCD, NO_IRQ }
-#define DMAC_IRQ                { IRQ_PBA8_DMAC, NO_IRQ }
-#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define PBA8_WATCHDOG_IRQ       { IRQ_PBA8_WATCHDOG, NO_IRQ }
-#define PBA8_GPIO0_IRQ          { IRQ_PBA8_GPIO0, NO_IRQ }
-#define GPIO1_IRQ               { IRQ_PBA8_GPIO1, NO_IRQ }
-#define PBA8_RTC_IRQ            { IRQ_PBA8_RTC, NO_IRQ }
-#define SCI_IRQ                 { IRQ_PBA8_SCI, NO_IRQ }
-#define PBA8_UART0_IRQ          { IRQ_PBA8_UART0, NO_IRQ }
-#define PBA8_UART1_IRQ          { IRQ_PBA8_UART1, NO_IRQ }
-#define PBA8_UART2_IRQ          { IRQ_PBA8_UART2, NO_IRQ }
-#define PBA8_UART3_IRQ          { IRQ_PBA8_UART3, NO_IRQ }
-#define PBA8_SSP_IRQ            { IRQ_PBA8_SSP, NO_IRQ }
+#define KMI0_IRQ                { IRQ_PBA8_KMI0 }
+#define KMI1_IRQ                { IRQ_PBA8_KMI1 }
+#define PBA8_SMC_IRQ            { }
+#define MPMC_IRQ                { }
+#define PBA8_CLCD_IRQ           { IRQ_PBA8_CLCD }
+#define DMAC_IRQ                { IRQ_PBA8_DMAC }
+#define SCTL_IRQ                { }
+#define PBA8_WATCHDOG_IRQ       { IRQ_PBA8_WATCHDOG }
+#define PBA8_GPIO0_IRQ          { IRQ_PBA8_GPIO0 }
+#define GPIO1_IRQ               { IRQ_PBA8_GPIO1 }
+#define PBA8_RTC_IRQ            { IRQ_PBA8_RTC }
+#define SCI_IRQ                 { IRQ_PBA8_SCI }
+#define PBA8_UART0_IRQ          { IRQ_PBA8_UART0 }
+#define PBA8_UART1_IRQ          { IRQ_PBA8_UART1 }
+#define PBA8_UART2_IRQ          { IRQ_PBA8_UART2 }
+#define PBA8_UART3_IRQ          { IRQ_PBA8_UART3 }
+#define PBA8_SSP_IRQ            { IRQ_PBA8_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PBA8_UART3,     NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart3,       "fpga:uart3",   PBA8_UART3,     NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PBA8_SMC,       NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PBA8_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PBA8_GPIO0,     &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PBA8_RTC,       NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PBA8_UART0,     NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PBA8_UART1,     NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PBA8_UART2,     NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBA8_SSP,       &ssp0_plat_data);
+AHB_DEVICE(smc,         "dev:smc",      PBA8_SMC,       NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PBA8_WATCHDOG, NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PBA8_GPIO0,     &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PBA8_RTC,       NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PBA8_UART0,     NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PBA8_UART1,     NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PBA8_UART2,     NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PBA8_SSP,       &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PBA8_CLCD,      &clcd_plat_data);
-AMBA_DEVICE(dmac,       "issp:dmac",    DMAC,           NULL);
+AHB_DEVICE(clcd,        "issp:clcd",    PBA8_CLCD,      &clcd_plat_data);
+AHB_DEVICE(dmac,        "issp:dmac",    DMAC,           NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index ac715645b86..3f2f605624e 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -144,52 +144,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PBXCore AMBA devices
  */
 
-#define GPIO2_IRQ               { IRQ_PBX_GPIO2, NO_IRQ }
-#define GPIO3_IRQ               { IRQ_PBX_GPIO3, NO_IRQ }
-#define AACI_IRQ                { IRQ_PBX_AACI, NO_IRQ }
+#define GPIO2_IRQ               { IRQ_PBX_GPIO2 }
+#define GPIO3_IRQ               { IRQ_PBX_GPIO3 }
+#define AACI_IRQ                { IRQ_PBX_AACI }
 #define MMCI0_IRQ               { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
-#define KMI0_IRQ                { IRQ_PBX_KMI0, NO_IRQ }
-#define KMI1_IRQ                { IRQ_PBX_KMI1, NO_IRQ }
-#define PBX_SMC_IRQ             { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define PBX_CLCD_IRQ            { IRQ_PBX_CLCD, NO_IRQ }
-#define DMAC_IRQ                { IRQ_PBX_DMAC, NO_IRQ }
-#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define PBX_WATCHDOG_IRQ        { IRQ_PBX_WATCHDOG, NO_IRQ }
-#define PBX_GPIO0_IRQ           { IRQ_PBX_GPIO0, NO_IRQ }
-#define GPIO1_IRQ               { IRQ_PBX_GPIO1, NO_IRQ }
-#define PBX_RTC_IRQ             { IRQ_PBX_RTC, NO_IRQ }
-#define SCI_IRQ                 { IRQ_PBX_SCI, NO_IRQ }
-#define PBX_UART0_IRQ           { IRQ_PBX_UART0, NO_IRQ }
-#define PBX_UART1_IRQ           { IRQ_PBX_UART1, NO_IRQ }
-#define PBX_UART2_IRQ           { IRQ_PBX_UART2, NO_IRQ }
-#define PBX_UART3_IRQ           { IRQ_PBX_UART3, NO_IRQ }
-#define PBX_SSP_IRQ             { IRQ_PBX_SSP, NO_IRQ }
+#define KMI0_IRQ                { IRQ_PBX_KMI0 }
+#define KMI1_IRQ                { IRQ_PBX_KMI1 }
+#define PBX_SMC_IRQ             { }
+#define MPMC_IRQ                { }
+#define PBX_CLCD_IRQ            { IRQ_PBX_CLCD }
+#define DMAC_IRQ                { IRQ_PBX_DMAC }
+#define SCTL_IRQ                { }
+#define PBX_WATCHDOG_IRQ        { IRQ_PBX_WATCHDOG }
+#define PBX_GPIO0_IRQ           { IRQ_PBX_GPIO0 }
+#define GPIO1_IRQ               { IRQ_PBX_GPIO1 }
+#define PBX_RTC_IRQ             { IRQ_PBX_RTC }
+#define SCI_IRQ                 { IRQ_PBX_SCI }
+#define PBX_UART0_IRQ           { IRQ_PBX_UART0 }
+#define PBX_UART1_IRQ           { IRQ_PBX_UART1 }
+#define PBX_UART2_IRQ           { IRQ_PBX_UART2 }
+#define PBX_UART3_IRQ           { IRQ_PBX_UART3 }
+#define PBX_SSP_IRQ             { IRQ_PBX_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PBX_UART3,      NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart3,       "fpga:uart3",   PBX_UART3,      NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PBX_SMC,        NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PBX_WATCHDOG,   NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PBX_GPIO0,      &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PBX_RTC,        NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PBX_UART0,      NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PBX_UART1,      NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PBX_UART2,      NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBX_SSP,        &ssp0_plat_data);
+AHB_DEVICE(smc, "dev:smc",      PBX_SMC,        NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PBX_WATCHDOG,   NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PBX_GPIO0,      &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PBX_RTC,        NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PBX_UART0,      NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PBX_UART1,      NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PBX_UART2,      NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PBX_SSP,        &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PBX_CLCD,       &clcd_plat_data);
-AMBA_DEVICE(dmac,       "issp:dmac",    DMAC,           NULL);
+AHB_DEVICE(clcd,        "issp:clcd",    PBX_CLCD,       &clcd_plat_data);
+AHB_DEVICE(dmac,        "issp:dmac",    DMAC,           NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -298,6 +298,21 @@ static void __init gic_init_irq(void)
         }
 }
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              REALVIEW_PBX_TILE_TWD_BASE,
+                              IRQ_LOCALTIMER);
+
+static void __init realview_pbx_twd_init(void)
+{
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+}
+#else
+#define realview_pbx_twd_init() do { } while(0)
+#endif
+
 static void __init realview_pbx_timer_init(void)
 {
         timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE);
@@ -305,11 +320,8 @@ static void __init realview_pbx_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
 
-#ifdef CONFIG_LOCAL_TIMERS
-        if (core_tile_pbx11mp() || core_tile_pbxa9mp())
-                twd_base = __io_address(REALVIEW_PBX_TILE_TWD_BASE);
-#endif
         realview_timer_init(IRQ_PBX_TIMER0_1);
+        realview_pbx_twd_init();
 }
 
 static struct sys_timer realview_pbx_timer = {
diff --git a/arch/arm/mach-rpc/Makefile b/arch/arm/mach-rpc/Makefile
index aa77bc9efbb..992e28b4ae9 100644
--- a/arch/arm/mach-rpc/Makefile
+++ b/arch/arm/mach-rpc/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := dma.o irq.o riscpc.o
+obj-y                   := dma.o ecard.o fiq.o irq.o riscpc.o time.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/mach-rpc/ecard.c
index 1651d495074..b91bc87b3dc 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/mach-rpc/ecard.c
@@ -42,6 +42,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 #include <linux/kthread.h>
+#include <linux/irq.h>
 #include <linux/io.h>
 
 #include <asm/dma.h>
@@ -54,10 +55,6 @@
 
 #include "ecard.h"
 
-#ifndef CONFIG_ARCH_RPC
-#define HAVE_EXPMASK
-#endif
-
 struct ecard_request {
         void            (*fn)(struct ecard_request *);
         ecard_t         *ec;
@@ -77,9 +74,6 @@ struct expcard_blacklist {
 static ecard_t *cards;
 static ecard_t *slot_to_expcard[MAX_ECARDS];
 static unsigned int ectcr;
-#ifdef HAS_EXPMASK
-static unsigned int have_expmask;
-#endif
 
 /* List of descriptions of cards which don't have an extended
  * identification, or chunk directories containing a description.
@@ -391,22 +385,10 @@ int ecard_readchunk(struct in_chunk_dir *cd, ecard_t *ec, int id, int num)
 
 static void ecard_def_irq_enable(ecard_t *ec, int irqnr)
 {
-#ifdef HAS_EXPMASK
-        if (irqnr < 4 && have_expmask) {
-                have_expmask |= 1 << irqnr;
-                __raw_writeb(have_expmask, EXPMASK_ENABLE);
-        }
-#endif
 }
 
 static void ecard_def_irq_disable(ecard_t *ec, int irqnr)
 {
-#ifdef HAS_EXPMASK
-        if (irqnr < 4 && have_expmask) {
-                have_expmask &= ~(1 << irqnr);
-                __raw_writeb(have_expmask, EXPMASK_ENABLE);
-        }
-#endif
 }
 
 static int ecard_def_irq_pending(ecard_t *ec)
@@ -446,7 +428,7 @@ static expansioncard_ops_t ecard_default_ops = {
  */
 static void ecard_irq_unmask(struct irq_data *d)
 {
-        ecard_t *ec = slot_to_ecard(d->irq - 32);
+        ecard_t *ec = irq_data_get_irq_chip_data(d);
 
         if (ec) {
                 if (!ec->ops)
@@ -462,7 +444,7 @@ static void ecard_irq_unmask(struct irq_data *d)
 
 static void ecard_irq_mask(struct irq_data *d)
 {
-        ecard_t *ec = slot_to_ecard(d->irq - 32);
+        ecard_t *ec = irq_data_get_irq_chip_data(d);
 
         if (ec) {
                 if (!ec->ops)
@@ -579,7 +561,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
         for (ec = cards; ec; ec = ec->next) {
                 int pending;
 
-                if (!ec->claimed || ec->irq == NO_IRQ || ec->slot_no == 8)
+                if (!ec->claimed || !ec->irq || ec->slot_no == 8)
                         continue;
 
                 if (ec->ops && ec->ops->irqpending)
@@ -598,83 +580,6 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
                 ecard_check_lockup(desc);
 }
 
-#ifdef HAS_EXPMASK
-static unsigned char priority_masks[] =
-{
-        0xf0, 0xf1, 0xf3, 0xf7, 0xff, 0xff, 0xff, 0xff
-};
-
-static unsigned char first_set[] =
-{
-        0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00,
-        0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00
-};
-
-static void
-ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
-{
-        const unsigned int statusmask = 15;
-        unsigned int status;
-
-        status = __raw_readb(EXPMASK_STATUS) & statusmask;
-        if (status) {
-                unsigned int slot = first_set[status];
-                ecard_t *ec = slot_to_ecard(slot);
-
-                if (ec->claimed) {
-                        /*
-                         * this ugly code is so that we can operate a
-                         * prioritorising system:
-                         *
-                         * Card 0       highest priority
-                         * Card 1
-                         * Card 2
-                         * Card 3       lowest priority
-                         *
-                         * Serial cards should go in 0/1, ethernet/scsi in 2/3
-                         * otherwise you will lose serial data at high speeds!
-                         */
-                        generic_handle_irq(ec->irq);
-                } else {
-                        printk(KERN_WARNING "card%d: interrupt from unclaimed "
-                               "card???\n", slot);
-                        have_expmask &= ~(1 << slot);
-                        __raw_writeb(have_expmask, EXPMASK_ENABLE);
-                }
-        } else
-                printk(KERN_WARNING "Wild interrupt from backplane (masks)\n");
-}
-
-static int __init ecard_probeirqhw(void)
-{
-        ecard_t *ec;
-        int found;
-
-        __raw_writeb(0x00, EXPMASK_ENABLE);
-        __raw_writeb(0xff, EXPMASK_STATUS);
-        found = (__raw_readb(EXPMASK_STATUS) & 15) == 0;
-        __raw_writeb(0xff, EXPMASK_ENABLE);
-
-        if (found) {
-                printk(KERN_DEBUG "Expansion card interrupt "
-                       "management hardware found\n");
-
-                /* for each card present, set a bit to '1' */
-                have_expmask = 0x80000000;
-
-                for (ec = cards; ec; ec = ec->next)
-                        have_expmask |= 1 << ec->slot_no;
-
-                __raw_writeb(have_expmask, EXPMASK_ENABLE);
-        }
-
-        return found;
-}
-#else
-#define ecard_irqexp_handler NULL
-#define ecard_probeirqhw() (0)
-#endif
-
 static void __iomem *__ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
 {
         void __iomem *address = NULL;
@@ -806,8 +711,8 @@ static struct expansion_card *__init ecard_alloc_card(int type, int slot)
 
         ec->slot_no = slot;
         ec->easi = type == ECARD_EASI;
-        ec->irq = NO_IRQ;
-        ec->fiq = NO_IRQ;
+        ec->irq = 0;
+        ec->fiq = 0;
         ec->dma = NO_DMA;
         ec->ops = &ecard_default_ops;
 
@@ -978,8 +883,7 @@ EXPORT_SYMBOL(ecardm_iomap);
  * If bit 1 of the first byte of the card is set, then the
  * card does not exist.
  */
-static int __init
-ecard_probe(int slot, card_type_t type)
+static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
 {
         ecard_t **ecp;
         ecard_t *ec;
@@ -1033,18 +937,18 @@ ecard_probe(int slot, card_type_t type)
                         break;
                 }
 
+        ec->irq = irq;
+
         /*
          * hook the interrupt handlers
          */
         if (slot < 8) {
-                ec->irq = 32 + slot;
                 irq_set_chip_and_handler(ec->irq, &ecard_chip,
                                          handle_level_irq);
+                irq_set_chip_data(ec->irq, ec);
                 set_irq_flags(ec->irq, IRQF_VALID);
         }
 
-        if (slot == 8)
-                ec->irq = 11;
 #ifdef CONFIG_ARCH_RPC
         /* On RiscPC, only first two slots have DMA capability */
         if (slot < 2)
@@ -1074,28 +978,30 @@ ecard_probe(int slot, card_type_t type)
 static int __init ecard_init(void)
 {
         struct task_struct *task;
-        int slot, irqhw;
+        int slot, irqbase;
+
+        irqbase = irq_alloc_descs(-1, 0, 8, -1);
+        if (irqbase < 0)
+                return irqbase;
 
         task = kthread_run(ecard_task, NULL, "kecardd");
         if (IS_ERR(task)) {
                 printk(KERN_ERR "Ecard: unable to create kernel thread: %ld\n",
                        PTR_ERR(task));
+                irq_free_descs(irqbase, 8);
                 return PTR_ERR(task);
         }
 
         printk("Probing expansion cards\n");
 
         for (slot = 0; slot < 8; slot ++) {
-                if (ecard_probe(slot, ECARD_EASI) == -ENODEV)
-                        ecard_probe(slot, ECARD_IOC);
+                if (ecard_probe(slot, irqbase + slot, ECARD_EASI) == -ENODEV)
+                        ecard_probe(slot, irqbase + slot, ECARD_IOC);
         }
 
-        ecard_probe(8, ECARD_IOC);
-
-        irqhw = ecard_probeirqhw();
+        ecard_probe(8, 11, ECARD_IOC);
 
-        irq_set_chained_handler(IRQ_EXPANSIONCARD,
-                                irqhw ? ecard_irqexp_handler : ecard_irq_handler);
+        irq_set_chained_handler(IRQ_EXPANSIONCARD, ecard_irq_handler);
 
         ecard_proc_init();
 
diff --git a/arch/arm/kernel/ecard.h b/arch/arm/mach-rpc/ecard.h
index 4642d436be2..4642d436be2 100644
--- a/arch/arm/kernel/ecard.h
+++ b/arch/arm/mach-rpc/ecard.h
diff --git a/arch/arm/mach-rpc/fiq.S b/arch/arm/mach-rpc/fiq.S
new file mode 100644
index 00000000000..48ddd57db16
--- /dev/null
+++ b/arch/arm/mach-rpc/fiq.S
@@ -0,0 +1,16 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <mach/entry-macro.S>
+
+        .text
+
+        .global rpc_default_fiq_end
+ENTRY(rpc_default_fiq_start)
+        mov     r12, #ioc_base_high
+        .if     ioc_base_low
+        orr     r12, r12, #ioc_base_low
+        .endif
+        strb    r12, [r12, #0x38]       @ Disable FIQ register
+        subs    pc, lr, #4
+rpc_default_fiq_end:
diff --git a/arch/arm/mach-rpc/include/mach/entry-macro.S b/arch/arm/mach-rpc/include/mach/entry-macro.S
index 4e7e5414409..7178368d706 100644
--- a/arch/arm/mach-rpc/include/mach/entry-macro.S
+++ b/arch/arm/mach-rpc/include/mach/entry-macro.S
@@ -10,7 +10,3 @@
         orr     \base, \base, #ioc_base_low
         .endif
         .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
index 3d2037496e3..6868e178274 100644
--- a/arch/arm/mach-rpc/include/mach/irqs.h
+++ b/arch/arm/mach-rpc/include/mach/irqs.h
@@ -42,6 +42,4 @@
  */
 #define FIQ_START               64
 
-#define IRQ_TIMER               IRQ_TIMER0
-
 #define NR_IRQS                 128
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
deleted file mode 100644
index 359bab94b6a..00000000000
--- a/arch/arm/mach-rpc/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- *  arch/arm/mach-rpc/include/mach/system.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 2e1b5309fba..cf0e669eaf1 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -5,6 +5,7 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/iomd.h>
 #include <asm/irq.h>
+#include <asm/fiq.h>
 
 static void iomd_ack_irq_a(struct irq_data *d)
 {
@@ -112,6 +113,8 @@ static struct irq_chip iomd_fiq_chip = {
         .irq_unmask     = iomd_unmask_irq_fiq,
 };
 
+extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
+
 void __init rpc_init_irq(void)
 {
         unsigned int irq, flags;
@@ -121,6 +124,9 @@ void __init rpc_init_irq(void)
         iomd_writeb(0, IOMD_FIQMASK);
         iomd_writeb(0, IOMD_DMAMASK);
 
+        set_fiq_handler(&rpc_default_fiq_start,
+                &rpc_default_fiq_end - &rpc_default_fiq_start);
+
         for (irq = 0; irq < NR_IRQS; irq++) {
                 flags = IRQF_VALID;
 
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index e95859748fa..f3fa259ce01 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -99,15 +99,9 @@ static void __init rpc_map_io(void)
 }
 
 static struct resource acornfb_resources[] = {
-        {       /* VIDC */
-                .start          = 0x03400000,
-                .end            = 0x035fffff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_VSYNCPULSE,
-                .end            = IRQ_VSYNCPULSE,
-                .flags          = IORESOURCE_IRQ,
-        },
+        /* VIDC */
+        DEFINE_RES_MEM(0x03400000, 0x00200000),
+        DEFINE_RES_IRQ(IRQ_VSYNCPULSE),
 };
 
 static struct platform_device acornfb_device = {
@@ -121,11 +115,7 @@ static struct platform_device acornfb_device = {
 };
 
 static struct resource iomd_resources[] = {
-        {
-                .start          = 0x03200000,
-                .end            = 0x0320ffff,
-                .flags          = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0x03200000, 0x10000),
 };
 
 static struct platform_device iomd_device = {
@@ -135,18 +125,25 @@ static struct platform_device iomd_device = {
         .resource               = iomd_resources,
 };
 
+static struct resource iomd_kart_resources[] = {
+        DEFINE_RES_IRQ(IRQ_KEYBOARDRX),
+        DEFINE_RES_IRQ(IRQ_KEYBOARDTX),
+};
+
 static struct platform_device kbd_device = {
         .name                   = "kart",
         .id                     = -1,
         .dev                    = {
                 .parent         = &iomd_device.dev,
         },
+        .num_resources          = ARRAY_SIZE(iomd_kart_resources),
+        .resource               = iomd_kart_resources,
 };
 
 static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .mapbase        = 0x03010fe0,
-                .irq            = 10,
+                .irq            = IRQ_SERIALPORT,
                 .uartclk        = 1843200,
                 .regshift       = 2,
                 .iotype         = UPIO_MEM,
@@ -168,21 +165,9 @@ static struct pata_platform_info pata_platform_data = {
 };
 
 static struct resource pata_resources[] = {
-        [0] = {
-                .start          = 0x030107c0,
-                .end            = 0x030107df,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = 0x03010fd8,
-                .end            = 0x03010fdb,
-                .flags          = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start          = IRQ_HARDDISK,
-                .end            = IRQ_HARDDISK,
-                .flags          = IORESOURCE_IRQ,
-        },
+        DEFINE_RES_MEM(0x030107c0, 0x20),
+        DEFINE_RES_MEM(0x03010fd8, 0x04),
+        DEFINE_RES_IRQ(IRQ_HARDDISK),
 };
 
 static struct platform_device pata_device = {
diff --git a/arch/arm/common/time-acorn.c b/arch/arm/mach-rpc/time.c
index deeed561b16..581fca934bb 100644
--- a/arch/arm/common/time-acorn.c
+++ b/arch/arm/mach-rpc/time.c
@@ -85,7 +85,7 @@ static struct irqaction ioc_timer_irq = {
 static void __init ioc_timer_init(void)
 {
         ioctime_init();
-        setup_irq(IRQ_TIMER, &ioc_timer_irq);
+        setup_irq(IRQ_TIMER0, &ioc_timer_irq);
 }
 
 struct sys_timer ioc_timer = {
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 5261a7ed099..68d89cb96af 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -2,42 +2,6 @@
 #
 # Licensed under GPLv2
 
-config CPU_S3C2410
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM920T
-        select S3C2410_CLOCK
-        select CPU_LLSERIAL_S3C2410
-        select S3C2410_PM if PM
-        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
-        help
-          Support for S3C2410 and S3C2410A family from the S3C24XX line
-          of Samsung Mobile CPUs.
-
-config CPU_S3C2410_DMA
-        bool
-        depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442)
-        default y if CPU_S3C2410 || CPU_S3C2442
-        help
-          DMA device selection for S3C2410 and compatible CPUs
-
-config S3C2410_PM
-        bool
-        help
-          Power Management code common to S3C2410 and better
-
-config SIMTEC_NOR
-        bool
-        help
-          Internal node to specify machine has simtec NOR mapping
-
-config MACH_BAST_IDE
-        bool
-        select HAVE_PATA_PLATFORM
-        help
-          Internal node for machines with an BAST style IDE
-          interface
-
 # cpu frequency scaling support
 
 config S3C2410_CPUFREQ
@@ -54,121 +18,3 @@ config S3C2410_PLLTABLE
         help
           Select the PLL table for the S3C2410
 
-menu "S3C2410 Machines"
-
-config ARCH_SMDK2410
-        bool "SMDK2410/A9M2410"
-        select CPU_S3C2410
-        select MACH_SMDK
-        help
-           Say Y here if you are using the SMDK2410 or the derived module A9M2410
-           <http://www.fsforth.de>
-
-config ARCH_H1940
-        bool "IPAQ H1940"
-        select CPU_S3C2410
-        select PM_H1940 if PM
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        select S3C2410_SETUP_TS
-        help
-          Say Y here if you are using the HP IPAQ H1940
-
-config H1940BT
-        tristate "Control the state of H1940 bluetooth chip"
-        depends on ARCH_H1940
-        select RFKILL
-        help
-          This is a simple driver that is able to control
-          the state of built in bluetooth chip on h1940.
-
-config PM_H1940
-        bool
-        help
-          Internal node for H1940 and related PM
-
-config MACH_N30
-        bool "Acer N30 family"
-        select CPU_S3C2410
-        select MACH_N35
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you want suppt for the Acer N30, Acer N35,
-          Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
-
-config MACH_N35
-        bool
-        help
-          Internal node in order to enable support for Acer N35 if Acer N30 is
-          selected.
-
-config ARCH_BAST
-        bool "Simtec Electronics BAST (EB2410ITX)"
-        select CPU_S3C2410
-        select S3C2410_IOTIMING if S3C2410_CPUFREQ
-        select PM_SIMTEC if PM
-        select SIMTEC_NOR
-        select MACH_BAST_IDE
-        select S3C24XX_DCLK
-        select ISA
-        select S3C_DEV_HWMON
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Simtec Electronics EB2410ITX
-          development board (also known as BAST)
-
-config MACH_OTOM
-        bool "NexVision OTOM Board"
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Nex Vision OTOM board
-
-config MACH_AML_M5900
-        bool "AML M5900 Series"
-        select CPU_S3C2410
-        select PM_SIMTEC if PM
-        select S3C_DEV_USB_HOST
-        help
-           Say Y here if you are using the American Microsystems M5900 Series
-           <http://www.amltd.com>
-
-config BAST_PC104_IRQ
-        bool "BAST PC104 IRQ support"
-        depends on ARCH_BAST
-        default y
-        help
-          Say Y here to enable the PC104 IRQ routing on the
-          Simtec BAST (EB2410ITX)
-
-config MACH_TCT_HAMMER
-        bool "TCT Hammer Board"
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        help
-           Say Y here if you are using the TinCanTools Hammer Board
-           <http://www.tincantools.com>
-
-config MACH_VR1000
-        bool "Thorcom VR1000"
-        select PM_SIMTEC if PM
-        select S3C24XX_DCLK
-        select SIMTEC_NOR
-        select MACH_BAST_IDE
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        help
-          Say Y here if you are using the Thorcom VR1000 board.
-
-config MACH_QT2410
-        bool "QT2410"
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-           Say Y here if you are using the Armzone QT2410
-
-endmenu
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 782fd81144e..6b9a316e004 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -9,32 +9,6 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
 
-obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
-obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
-obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
-obj-$(CONFIG_S3C2410_PM)        += pm.o sleep.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
 obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
 
-# Machine support
-
-obj-$(CONFIG_ARCH_SMDK2410)     += mach-smdk2410.o
-obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o
-obj-$(CONFIG_H1940BT)           += h1940-bluetooth.o
-obj-$(CONFIG_PM_H1940)          += pm-h1940.o
-obj-$(CONFIG_MACH_N30)          += mach-n30.o
-obj-$(CONFIG_ARCH_BAST)         += mach-bast.o usb-simtec.o
-obj-$(CONFIG_MACH_OTOM)         += mach-otom.o
-obj-$(CONFIG_MACH_AML_M5900)    += mach-amlm5900.o
-obj-$(CONFIG_BAST_PC104_IRQ)    += bast-irq.o
-obj-$(CONFIG_MACH_TCT_HAMMER)   += mach-tct_hammer.o
-obj-$(CONFIG_MACH_VR1000)       += mach-vr1000.o usb-simtec.o
-obj-$(CONFIG_MACH_QT2410)       += mach-qt2410.o
-
-# Common bits of machine support
-
-obj-$(CONFIG_SIMTEC_NOR)        += nor-simtec.o
-
-# machine additions
-
-obj-$(CONFIG_MACH_BAST_IDE)     += bast-ide.o
diff --git a/arch/arm/mach-s3c2410/common.h b/arch/arm/mach-s3c2410/common.h
deleted file mode 100644
index f65dc806296..00000000000
--- a/arch/arm/mach-s3c2410/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Header for S3C2410 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_S3C2410_COMMON_H
-#define __ARCH_ARM_MACH_S3C2410_COMMON_H
-
-void s3c2410_restart(char mode, const char *cmd);
-
-#endif /* __ARCH_ARM_MACH_S3C2410_COMMON_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
deleted file mode 100644
index 4d9588373aa..00000000000
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/spi.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - SPI Controller platform_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SPI_H
-#define __ASM_ARCH_SPI_H __FILE__
-
-struct s3c2410_spi_info {
-        int                      pin_cs;        /* simple gpio cs */
-        unsigned int             num_cs;        /* total chipselects */
-        int                      bus_num;       /* bus number to use. */
-
-        unsigned int             use_fiq:1;     /* use fiq */
-
-        void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
-        void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
-};
-
-/* Standard setup / suspend routines for SPI GPIO pins. */
-
-extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
-                                                 int enable);
-
-extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
-                                              int enable);
-
-extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
-                                               int enable);
-
-#endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h
deleted file mode 100644
index 5e215c1a5c8..00000000000
--- a/arch/arm/mach-s3c2410/include/mach/system.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/system.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - System function defines and includes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-#include <mach/map.h>
-#include <mach/idle.h>
-
-#include <mach/regs-clock.h>
-
-void (*s3c24xx_idle)(void);
-
-void s3c24xx_default_idle(void)
-{
-        unsigned long tmp;
-        int i;
-
-        /* idle the system by using the idle mode which will wait for an
-         * interrupt to happen before restarting the system.
-         */
-
-        /* Warning: going into idle state upsets jtag scanning */
-
-        __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
-                     S3C2410_CLKCON);
-
-        /* the samsung port seems to do a loop and then unset idle.. */
-        for (i = 0; i < 50; i++) {
-                tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
-        }
-
-        /* this bit is not cleared on re-start... */
-
-        __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
-                     S3C2410_CLKCON);
-}
-
-static void arch_idle(void)
-{
-        if (s3c24xx_idle != NULL)
-                (s3c24xx_idle)();
-        else
-                s3c24xx_default_idle();
-}
diff --git a/arch/arm/mach-s3c2410/usb-simtec.h b/arch/arm/mach-s3c2410/usb-simtec.h
deleted file mode 100644
index 03842ede9e7..00000000000
--- a/arch/arm/mach-s3c2410/usb-simtec.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/usb-simtec.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *   Ben Dooks <ben@simtec.co.uk>
- *
- * http://www.simtec.co.uk/products/EB2410ITX/
- *
- * Simtec BAST and Thorcom VR1000 USB port support functions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern int usb_simtec_init(void);
-
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index b8b9029e9f2..c5256f4e90b 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -2,41 +2,6 @@
 #
 # Licensed under GPLv2
 
-config CPU_S3C2412
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM926T
-        select CPU_LLSERIAL_S3C2440
-        select S3C2412_PM if PM
-        select S3C2412_DMA if S3C2410_DMA
-        help
-          Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
-
-config CPU_S3C2412_ONLY
-        bool
-        depends on ARCH_S3C2410 && !CPU_S3C2410 && \
-                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
-                   !CPU_S3C2443 && CPU_S3C2412
-        default y if CPU_S3C2412
-
-config S3C2412_DMA
-        bool
-        depends on CPU_S3C2412
-        help
-          Internal config node for S3C2412 DMA support
-
-config S3C2412_PM
-        bool
-        select S3C2412_PM_SLEEP
-        help
-          Internal config node to apply S3C2412 power management
-
-config S3C2412_PM_SLEEP
-        bool
-        help
-          Internal config node to apply sleep for S3C2412 power management.
-          Can be selected by another SoCs with similar sleep procedure.
-
 # Note, the S3C2412 IOtiming support is in plat-s3c24xx
 
 config S3C2412_CPUFREQ
@@ -46,53 +11,3 @@ config S3C2412_CPUFREQ
         default y
         help
           CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
-
-menu "S3C2412 Machines"
-
-config MACH_JIVE
-        bool "Logitech Jive"
-        select CPU_S3C2412
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Logitech Jive.
-
-config MACH_JIVE_SHOW_BOOTLOADER
-        bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
-        depends on MACH_JIVE && EXPERIMENTAL
-
-config MACH_SMDK2413
-        bool "SMDK2413"
-        select CPU_S3C2412
-        select MACH_S3C2413
-        select MACH_SMDK
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using an SMDK2413
-
-config MACH_S3C2413
-        bool
-        help
-          Internal node for S3C2413 version of SMDK2413, so that
-          machine_is_s3c2413() will work when MACH_SMDK2413 is
-          selected
-
-config MACH_SMDK2412
-        bool "SMDK2412"
-        select MACH_SMDK2413
-        help
-          Say Y here if you are using an SMDK2412
-
-          Note, this shares support with SMDK2413, so will automatically
-          select MACH_SMDK2413.
-
-config MACH_VSTMS
-        bool "VMSTMS"
-        select CPU_S3C2412
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using an VSTMS board
-
-endmenu
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 7e4d95fa8a9..41a6c279fb2 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -9,16 +9,4 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
 
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
-obj-$(CONFIG_CPU_S3C2412)       += irq.o
-obj-$(CONFIG_CPU_S3C2412)       += clock.o
-obj-$(CONFIG_S3C2412_DMA)       += dma.o
-obj-$(CONFIG_S3C2412_PM)        += pm.o
-obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_JIVE)         += mach-jive.o
-obj-$(CONFIG_MACH_SMDK2413)     += mach-smdk2413.o
-obj-$(CONFIG_MACH_VSTMS)        += mach-vstms.o
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
deleted file mode 100644
index 84c7b03e5a3..00000000000
--- a/arch/arm/mach-s3c2416/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-# arch/arm/mach-s3c2416/Kconfig
-#
-# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
-#
-# Licensed under GPLv2
-
-# note, this also supports the S3C2450 which is so similar it has the same
-# ID code as the S3C2416.
-
-config CPU_S3C2416
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM926T
-        select S3C2416_DMA if S3C2410_DMA
-        select CPU_LLSERIAL_S3C2440
-        select SAMSUNG_CLKSRC
-        select S3C2443_CLOCK
-        help
-          Support for the S3C2416 SoC from the S3C24XX line
-
-config S3C2416_DMA
-        bool
-        depends on CPU_S3C2416
-        help
-          Internal config node for S3C2416 DMA support
-
-config S3C2416_PM
-        bool
-        select S3C2412_PM_SLEEP
-        help
-          Internal config node to apply S3C2416 power management
-
-config S3C2416_SETUP_SDHCI
-        bool
-        select S3C2416_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for S3C2416 based SDHCI systems
-
-config S3C2416_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-menu "S3C2416 Machines"
-
-config MACH_SMDK2416
-        bool "SMDK2416"
-        select CPU_S3C2416
-        select MACH_SMDK
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_NAND
-        select S3C_DEV_USB_HOST
-        select S3C2416_SETUP_SDHCI
-        select S3C2416_PM if PM
-        help
-          Say Y here if you are using an SMDK2416
-
-endmenu
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
deleted file mode 100644
index ca0cd227f87..00000000000
--- a/arch/arm/mach-s3c2416/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# arch/arm/mach-s3c2416/Makefile
-#
-# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock.o
-obj-$(CONFIG_CPU_S3C2416)       += irq.o
-obj-$(CONFIG_S3C2416_PM)        += pm.o
-#obj-$(CONFIG_S3C2416_DMA)      += dma.o
-
-# Device setup
-obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_SMDK2416)     += mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 914e620f125..ece7a10fe3c 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -2,35 +2,6 @@
 #
 # Licensed under GPLv2
 
-config CPU_S3C2440
-        bool
-        select CPU_ARM920T
-        select S3C2410_CLOCK
-        select S3C2410_PM if PM
-        select S3C2440_DMA if S3C2410_DMA
-        select CPU_S3C244X
-        select CPU_LLSERIAL_S3C2440
-        help
-          Support for S3C2440 Samsung Mobile CPU based systems.
-
-config CPU_S3C2442
-        bool
-        select CPU_ARM920T
-        select S3C2410_CLOCK
-        select S3C2410_PM if PM
-        select CPU_S3C244X
-        select CPU_LLSERIAL_S3C2440
-        help
-          Support for S3C2442 Samsung Mobile CPU based systems.
-
-config CPU_S3C244X
-        bool
-        depends on CPU_S3C2440 || CPU_S3C2442
-        help
-          Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
-
-
-
 config S3C2440_CPUFREQ
         bool "S3C2440/S3C2442 CPU Frequency scaling support"
         depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
@@ -64,139 +35,3 @@ config S3C2440_PLL_16934400
         default y if CPU_FREQ_S3C24XX_PLL
         help
           PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
-
-config S3C2440_DMA
-        bool
-        depends on CPU_S3C2440
-        help
-          Support for S3C2440 specific DMA code5A
-
-menu "S3C2440 and S3C2442 Machines"
-
-config MACH_ANUBIS
-        bool "Simtec Electronics ANUBIS"
-        select CPU_S3C2440
-        select S3C24XX_DCLK
-        select PM_SIMTEC if PM
-        select HAVE_PATA_PLATFORM
-        select S3C24XX_GPIO_EXTRA64
-        select S3C2440_XTAL_12000000
-        select S3C_DEV_USB_HOST
-        help
-          Say Y here if you are using the Simtec Electronics ANUBIS
-          development system
-
-config MACH_NEO1973_GTA02
-        bool "Openmoko GTA02 / Freerunner phone"
-        select CPU_S3C2442
-        select MFD_PCF50633
-        select PCF50633_GPIO
-        select I2C
-        select POWER_SUPPLY
-        select MACH_NEO1973
-        select S3C2410_PWM
-        select S3C_DEV_USB_HOST
-        help
-           Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
-
-config MACH_OSIRIS
-        bool "Simtec IM2440D20 (OSIRIS) module"
-        select CPU_S3C2440
-        select S3C24XX_DCLK
-        select PM_SIMTEC if PM
-        select S3C24XX_GPIO_EXTRA128
-        select S3C2440_XTAL_12000000
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Simtec IM2440D20 module, also
-          known as the Osiris.
-
-config MACH_OSIRIS_DVS
-        tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
-        depends on MACH_OSIRIS
-        select TPS65010
-        help
-          Say Y/M here if you want to have dynamic voltage scaling support
-          on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
-
-          The DVS driver alters the voltage supplied to the ARM core
-          depending on the frequency it is running at. The driver itself
-          does not do any of the frequency alteration, which is left up
-          to the cpufreq driver.
-
-config MACH_RX3715
-        bool "HP iPAQ rx3715"
-        select CPU_S3C2440
-        select S3C2440_XTAL_16934400
-        select PM_H1940 if PM
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the HP iPAQ rx3715.
-
-config ARCH_S3C2440
-        bool "SMDK2440"
-        select CPU_S3C2440
-        select S3C2440_XTAL_16934400
-        select MACH_SMDK
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the SMDK2440.
-
-config MACH_NEXCODER_2440
-        bool "NexVision NEXCODER 2440 Light Board"
-        select CPU_S3C2440
-        select S3C2440_XTAL_12000000
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
-
-config SMDK2440_CPU2440
-        bool "SMDK2440 with S3C2440 CPU module"
-        default y if ARCH_S3C2440
-        select S3C2440_XTAL_16934400
-        select CPU_S3C2440
-
-config SMDK2440_CPU2442
-        bool "SMDM2440 with S3C2442 CPU module"
-        select CPU_S3C2442
-
-config MACH_AT2440EVB
-        bool "Avantech AT2440EVB development board"
-        select CPU_S3C2440
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the AT2440EVB development board
-
-config MACH_MINI2440
-        bool "MINI2440 development board"
-        select CPU_S3C2440
-        select EEPROM_AT24
-        select NEW_LEDS
-        select LEDS_CLASS
-        select LEDS_TRIGGER
-        select LEDS_TRIGGER_BACKLIGHT
-        select S3C_DEV_NAND
-        select S3C_DEV_USB_HOST
-        help
-          Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
-          available via various sources. It can come with a 3.5" or 7" touch LCD.
-
-config MACH_RX1950
-        bool "HP iPAQ rx1950"
-        select CPU_S3C2442
-        select S3C24XX_DCLK
-        select PM_H1940 if PM
-        select I2C
-        select S3C2410_PWM
-        select S3C_DEV_NAND
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
-        select S3C2440_XTAL_16934400
-        help
-           Say Y here if you're using HP iPAQ rx1950
-
-endmenu
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index d5440fa34b0..c4609243981 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -9,33 +9,9 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
 
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o dsc.o
-obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
+obj-$(CONFIG_CPU_S3C2440)       += dsc.o
 
-obj-$(CONFIG_CPU_S3C2440)       += irq.o
-obj-$(CONFIG_CPU_S3C2440)       += clock.o
-obj-$(CONFIG_S3C2440_DMA)       += dma.o
-
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x-irq.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x-clock.o
 obj-$(CONFIG_S3C2440_CPUFREQ)   += s3c2440-cpufreq.o
 
 obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_ANUBIS)       += mach-anubis.o
-obj-$(CONFIG_MACH_OSIRIS)       += mach-osiris.o
-obj-$(CONFIG_MACH_RX3715)       += mach-rx3715.o
-obj-$(CONFIG_ARCH_S3C2440)      += mach-smdk2440.o
-obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
-obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
-obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
-obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
-obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
-
-# extra machine support
-
-obj-$(CONFIG_MACH_OSIRIS_DVS)   += mach-osiris-dvs.o
diff --git a/arch/arm/mach-s3c2440/common.h b/arch/arm/mach-s3c2440/common.h
deleted file mode 100644
index 0c1eb1dfc53..00000000000
--- a/arch/arm/mach-s3c2440/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Header for S3C2440 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_S3C2440_COMMON_H
-#define __ARCH_ARM_MACH_S3C2440_COMMON_H
-
-void s3c244x_restart(char mode, const char *cmd);
-
-#endif /* __ARCH_ARM_MACH_S3C2440_COMMON_H */
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
deleted file mode 100644
index 8814031516c..00000000000
--- a/arch/arm/mach-s3c2443/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-
-config CPU_S3C2443
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM920T
-        select S3C2443_DMA if S3C2410_DMA
-        select CPU_LLSERIAL_S3C2440
-        select SAMSUNG_CLKSRC
-        select S3C2443_CLOCK
-        help
-          Support for the S3C2443 SoC from the S3C24XX line
-
-config S3C2443_DMA
-        bool
-        depends on CPU_S3C2443
-        help
-          Internal config node for S3C2443 DMA support
-
-menu "S3C2443 Machines"
-
-config MACH_SMDK2443
-        bool "SMDK2443"
-        select CPU_S3C2443
-        select MACH_SMDK
-        select S3C_DEV_HSMMC1
-        help
-          Say Y here if you are using an SMDK2443
-
-endmenu
diff --git a/arch/arm/mach-s3c2443/Makefile b/arch/arm/mach-s3c2443/Makefile
deleted file mode 100644
index d1843c9eb8b..00000000000
--- a/arch/arm/mach-s3c2443/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-# arch/arm/mach-s3c2443/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o
-obj-$(CONFIG_CPU_S3C2443)       += irq.o
-obj-$(CONFIG_CPU_S3C2443)       += clock.o
-
-obj-$(CONFIG_S3C2443_DMA)       += dma.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_SMDK2443)     += mach-smdk2443.o
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
new file mode 100644
index 00000000000..0f3a327ebca
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -0,0 +1,538 @@
+# arch/arm/mach-s3c24xx/Kconfig
+#
+# Copyright (c) 2012 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+if ARCH_S3C24XX
+
+menu "SAMSUNG S3C24XX SoCs Support"
+
+comment "S3C24XX SoCs"
+
+config CPU_S3C2410
+        bool "SAMSUNG S3C2410"
+        default y
+        select CPU_ARM920T
+        select S3C2410_CLOCK
+        select CPU_LLSERIAL_S3C2410
+        select S3C2410_PM if PM
+        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
+        help
+          Support for S3C2410 and S3C2410A family from the S3C24XX line
+          of Samsung Mobile CPUs.
+
+config CPU_S3C2412
+        bool "SAMSUNG S3C2412"
+        depends on ARCH_S3C24XX
+        select CPU_ARM926T
+        select CPU_LLSERIAL_S3C2440
+        select S3C2412_PM if PM
+        select S3C2412_DMA if S3C24XX_DMA
+        help
+          Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
+
+config CPU_S3C2416
+        bool "SAMSUNG S3C2416/S3C2450"
+        depends on ARCH_S3C24XX
+        select CPU_ARM926T
+        select CPU_LLSERIAL_S3C2440
+        select SAMSUNG_CLKSRC
+        select S3C2443_COMMON
+        select S3C2443_DMA if S3C24XX_DMA
+        select S3C2416_PM if PM
+        help
+          Support for the S3C2416 SoC from the S3C24XX line
+
+config CPU_S3C2440
+        bool "SAMSUNG S3C2440"
+        select CPU_ARM920T
+        select CPU_LLSERIAL_S3C2440
+        select S3C2410_CLOCK
+        select S3C2410_PM if PM
+        select S3C2440_DMA if S3C24XX_DMA
+        help
+          Support for S3C2440 Samsung Mobile CPU based systems.
+
+config CPU_S3C2442
+        bool "SAMSUNG S3C2442"
+        select CPU_ARM920T
+        select CPU_LLSERIAL_S3C2440
+        select S3C2410_CLOCK
+        select S3C2410_PM if PM
+        help
+          Support for S3C2442 Samsung Mobile CPU based systems.
+
+config CPU_S3C244X
+        def_bool y
+        depends on CPU_S3C2440 || CPU_S3C2442
+
+config CPU_S3C2443
+        bool "SAMSUNG S3C2443"
+        depends on ARCH_S3C24XX
+        select CPU_ARM920T
+        select CPU_LLSERIAL_S3C2440
+        select SAMSUNG_CLKSRC
+        select S3C2443_COMMON
+        select S3C2443_DMA if S3C24XX_DMA
+        help
+          Support for the S3C2443 SoC from the S3C24XX line
+
+# common code
+
+config S3C24XX_SMDK
+        bool
+        help
+          Common machine code for SMDK2410 and SMDK2440
+
+config S3C24XX_SIMTEC_AUDIO
+        bool
+        depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
+        default y
+        help
+          Add audio devices for common Simtec S3C24XX boards
+
+config S3C24XX_SIMTEC_PM
+        bool
+        help
+          Common power management code for systems that are
+          compatible with the Simtec style of power management
+
+config S3C24XX_SIMTEC_USB
+        bool
+        help
+          USB management code for common Simtec S3C24XX boards
+
+config S3C24XX_SETUP_TS
+        bool
+        help
+          Compile in platform device definition for Samsung TouchScreen.
+
+# cpu-specific sections
+
+if CPU_S3C2410
+
+config S3C2410_DMA
+        bool
+        depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
+        default y if CPU_S3C2410 || CPU_S3C2442
+        help
+          DMA device selection for S3C2410 and compatible CPUs
+
+config S3C2410_PM
+        bool
+        help
+          Power Management code common to S3C2410 and better
+
+config S3C24XX_SIMTEC_NOR
+        bool
+        help
+          Internal node to specify machine has simtec NOR mapping
+
+config MACH_BAST_IDE
+        bool
+        select HAVE_PATA_PLATFORM
+        help
+          Internal node for machines with an BAST style IDE
+          interface
+
+comment "S3C2410 Boards"
+
+#
+# The "S3C2410 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_AML_M5900
+        bool "AML M5900 Series"
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here if you are using the American Microsystems M5900 Series
+          <http://www.amltd.com>
+
+config ARCH_BAST
+        bool "Simtec Electronics BAST (EB2410ITX)"
+        select S3C2410_IOTIMING if S3C2410_CPUFREQ
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C24XX_SIMTEC_NOR
+        select S3C24XX_SIMTEC_USB
+        select MACH_BAST_IDE
+        select S3C24XX_DCLK
+        select ISA
+        select S3C_DEV_HWMON
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Simtec Electronics EB2410ITX
+          development board (also known as BAST)
+
+config BAST_PC104_IRQ
+        bool "BAST PC104 IRQ support"
+        depends on ARCH_BAST
+        default y
+        help
+          Say Y here to enable the PC104 IRQ routing on the
+          Simtec BAST (EB2410ITX)
+
+config ARCH_H1940
+        bool "IPAQ H1940"
+        select PM_H1940 if PM
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        select S3C24XX_SETUP_TS
+        help
+          Say Y here if you are using the HP IPAQ H1940
+
+config H1940BT
+        tristate "Control the state of H1940 bluetooth chip"
+        depends on ARCH_H1940
+        select RFKILL
+        help
+          This is a simple driver that is able to control
+          the state of built in bluetooth chip on h1940.
+
+config PM_H1940
+        bool
+        help
+          Internal node for H1940 and related PM
+
+config MACH_N30
+        bool "Acer N30 family"
+        select MACH_N35
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you want suppt for the Acer N30, Acer N35,
+          Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
+
+config MACH_OTOM
+        bool "NexVision OTOM Board"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Nex Vision OTOM board
+
+config MACH_QT2410
+        bool "QT2410"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Armzone QT2410
+
+config ARCH_SMDK2410
+        bool "SMDK2410/A9M2410"
+        select S3C24XX_SMDK
+        help
+          Say Y here if you are using the SMDK2410 or the derived module A9M2410
+          <http://www.fsforth.de>
+
+config MACH_TCT_HAMMER
+        bool "TCT Hammer Board"
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here if you are using the TinCanTools Hammer Board
+          <http://www.tincantools.com>
+
+config MACH_VR1000
+        bool "Thorcom VR1000"
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C24XX_DCLK
+        select S3C24XX_SIMTEC_NOR
+        select MACH_BAST_IDE
+        select S3C_DEV_USB_HOST
+        select S3C24XX_SIMTEC_USB
+        help
+          Say Y here if you are using the Thorcom VR1000 board.
+
+endif   # CPU_S3C2410
+
+config S3C2412_PM_SLEEP
+        bool
+        help
+          Internal config node to apply sleep for S3C2412 power management.
+          Can be selected by another SoCs such as S3C2416 with similar
+          sleep procedure.
+
+if CPU_S3C2412
+
+config CPU_S3C2412_ONLY
+        bool
+        depends on ARCH_S3C24XX && !CPU_S3C2410 && \
+                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
+                   !CPU_S3C2443 && CPU_S3C2412
+        default y
+
+config S3C2412_DMA
+        bool
+        help
+          Internal config node for S3C2412 DMA support
+
+config S3C2412_PM
+        bool
+        help
+          Internal config node to apply S3C2412 power management
+
+comment "S3C2412 Boards"
+
+#
+# The "S3C2412 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_JIVE
+        bool "Logitech Jive"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Logitech Jive.
+
+config MACH_JIVE_SHOW_BOOTLOADER
+        bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
+        depends on MACH_JIVE && EXPERIMENTAL
+
+config MACH_S3C2413
+        bool
+        help
+          Internal node for S3C2413 version of SMDK2413, so that
+          machine_is_s3c2413() will work when MACH_SMDK2413 is
+          selected
+
+config MACH_SMDK2412
+        bool "SMDK2412"
+        select MACH_SMDK2413
+        help
+          Say Y here if you are using an SMDK2412
+
+          Note, this shares support with SMDK2413, so will automatically
+          select MACH_SMDK2413.
+
+config MACH_SMDK2413
+        bool "SMDK2413"
+        select MACH_S3C2413
+        select S3C24XX_SMDK
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using an SMDK2413
+
+config MACH_VSTMS
+        bool "VMSTMS"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using an VSTMS board
+
+endif   # CPU_S3C2412
+
+if CPU_S3C2416
+
+config S3C2416_PM
+        bool
+        select S3C2412_PM_SLEEP
+        help
+          Internal config node to apply S3C2416 power management
+
+config S3C2416_SETUP_SDHCI
+        bool
+        select S3C2416_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S3C2416 based SDHCI systems
+
+config S3C2416_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
+comment "S3C2416 Boards"
+
+config MACH_SMDK2416
+        bool "SMDK2416"
+        select S3C24XX_SMDK
+        select S3C_DEV_FB
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_NAND
+        select S3C_DEV_USB_HOST
+        select S3C2416_SETUP_SDHCI
+        help
+          Say Y here if you are using an SMDK2416
+
+endif   # CPU_S3C2416
+
+if CPU_S3C2440
+
+config S3C2440_DMA
+        bool
+        help
+          Support for S3C2440 specific DMA code5A
+
+comment "S3C2440 Boards"
+
+#
+# The "S3C2440 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_ANUBIS
+        bool "Simtec Electronics ANUBIS"
+        select S3C24XX_DCLK
+        select S3C24XX_SIMTEC_PM if PM
+        select HAVE_PATA_PLATFORM
+        select S3C24XX_GPIO_EXTRA64
+        select S3C2440_XTAL_12000000
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here if you are using the Simtec Electronics ANUBIS
+          development system
+
+config MACH_AT2440EVB
+        bool "Avantech AT2440EVB development board"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the AT2440EVB development board
+
+config MACH_MINI2440
+        bool "MINI2440 development board"
+        select EEPROM_AT24
+        select NEW_LEDS
+        select LEDS_CLASS
+        select LEDS_TRIGGER
+        select LEDS_TRIGGER_BACKLIGHT
+        select S3C_DEV_NAND
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
+          available via various sources. It can come with a 3.5" or 7" touch LCD.
+
+config MACH_NEXCODER_2440
+        bool "NexVision NEXCODER 2440 Light Board"
+        select S3C2440_XTAL_12000000
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
+
+config MACH_OSIRIS
+        bool "Simtec IM2440D20 (OSIRIS) module"
+        select S3C24XX_DCLK
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C24XX_GPIO_EXTRA128
+        select S3C2440_XTAL_12000000
+        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Simtec IM2440D20 module, also
+          known as the Osiris.
+
+config MACH_OSIRIS_DVS
+        tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
+        depends on MACH_OSIRIS
+        select TPS65010
+        help
+          Say Y/M here if you want to have dynamic voltage scaling support
+          on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
+
+          The DVS driver alters the voltage supplied to the ARM core
+          depending on the frequency it is running at. The driver itself
+          does not do any of the frequency alteration, which is left up
+          to the cpufreq driver.
+
+config MACH_RX3715
+        bool "HP iPAQ rx3715"
+        select S3C2440_XTAL_16934400
+        select PM_H1940 if PM
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the HP iPAQ rx3715.
+
+config ARCH_S3C2440
+        bool "SMDK2440"
+        select S3C2440_XTAL_16934400
+        select S3C24XX_SMDK
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the SMDK2440.
+
+config SMDK2440_CPU2440
+        bool "SMDK2440 with S3C2440 CPU module"
+        default y if ARCH_S3C2440
+        select S3C2440_XTAL_16934400
+
+endif   # CPU_S3C2440
+
+if CPU_S3C2442
+
+comment "S3C2442 Boards"
+
+#
+# The "S3C2442 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_NEO1973_GTA02
+        bool "Openmoko GTA02 / Freerunner phone"
+        select MFD_PCF50633
+        select PCF50633_GPIO
+        select I2C
+        select POWER_SUPPLY
+        select MACH_NEO1973
+        select S3C2410_PWM
+        select S3C_DEV_USB_HOST
+        help
+           Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
+
+config MACH_RX1950
+        bool "HP iPAQ rx1950"
+        select S3C24XX_DCLK
+        select PM_H1940 if PM
+        select I2C
+        select S3C2410_PWM
+        select S3C_DEV_NAND
+        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C2440_XTAL_16934400
+        help
+           Say Y here if you're using HP iPAQ rx1950
+
+config SMDK2440_CPU2442
+        bool "SMDM2440 with S3C2442 CPU module"
+
+endif   # CPU_S3C2440
+
+if CPU_S3C2443 || CPU_S3C2416
+
+config S3C2443_COMMON
+        bool
+        help
+          Common code for the S3C2443 and similar processors, which includes
+          the S3C2416 and S3C2450.
+
+config S3C2443_DMA
+        bool
+        help
+          Internal config node for S3C2443 DMA support
+
+endif   # CPU_S3C2443 || CPU_S3C2416
+
+if CPU_S3C2443
+
+comment "S3C2443 Boards"
+
+config MACH_SMDK2443
+        bool "SMDK2443"
+        select S3C24XX_SMDK
+        select S3C_DEV_HSMMC1
+        help
+          Say Y here if you are using an SMDK2443
+
+endif   # CPU_S3C2443
+
+endmenu # SAMSUNG S3C24XX SoCs Support
+
+endif   # ARCH_S3C24XX
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
new file mode 100644
index 00000000000..3518fe812d5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -0,0 +1,95 @@
+# arch/arm/mach-s3c24xx/Makefile
+#
+# Copyright (c) 2012 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# core
+
+obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
+obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
+obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
+
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
+obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
+obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
+
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o irq-s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
+
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
+
+obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o irq-s3c2443.o clock-s3c2443.o
+
+# common code
+
+obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
+obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
+
+#
+# machine support
+# following is ordered alphabetically by option text.
+#
+
+obj-$(CONFIG_MACH_AML_M5900)            += mach-amlm5900.o
+obj-$(CONFIG_ARCH_BAST)                 += mach-bast.o
+obj-$(CONFIG_BAST_PC104_IRQ)            += bast-irq.o
+obj-$(CONFIG_ARCH_H1940)                += mach-h1940.o
+obj-$(CONFIG_H1940BT)                   += h1940-bluetooth.o
+obj-$(CONFIG_PM_H1940)                  += pm-h1940.o
+obj-$(CONFIG_MACH_N30)                  += mach-n30.o
+obj-$(CONFIG_MACH_OTOM)                 += mach-otom.o
+obj-$(CONFIG_MACH_QT2410)               += mach-qt2410.o
+obj-$(CONFIG_ARCH_SMDK2410)             += mach-smdk2410.o
+obj-$(CONFIG_MACH_TCT_HAMMER)           += mach-tct_hammer.o
+obj-$(CONFIG_MACH_VR1000)               += mach-vr1000.o
+
+obj-$(CONFIG_MACH_JIVE)                 += mach-jive.o
+obj-$(CONFIG_MACH_SMDK2413)             += mach-smdk2413.o
+obj-$(CONFIG_MACH_VSTMS)                += mach-vstms.o
+
+obj-$(CONFIG_MACH_SMDK2416)             += mach-smdk2416.o
+
+obj-$(CONFIG_MACH_ANUBIS)               += mach-anubis.o
+obj-$(CONFIG_MACH_AT2440EVB)            += mach-at2440evb.o
+obj-$(CONFIG_MACH_MINI2440)             += mach-mini2440.o
+obj-$(CONFIG_MACH_NEXCODER_2440)        += mach-nexcoder.o
+obj-$(CONFIG_MACH_OSIRIS)               += mach-osiris.o
+obj-$(CONFIG_MACH_RX3715)               += mach-rx3715.o
+obj-$(CONFIG_ARCH_S3C2440)              += mach-smdk2440.o
+
+obj-$(CONFIG_MACH_NEO1973_GTA02)        += mach-gta02.o
+obj-$(CONFIG_MACH_RX1950)               += mach-rx1950.o
+
+obj-$(CONFIG_MACH_SMDK2443)             += mach-smdk2443.o
+
+# common bits of machine support
+
+obj-$(CONFIG_S3C24XX_SMDK)              += common-smdk.o
+obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)      += simtec-audio.o
+obj-$(CONFIG_S3C24XX_SIMTEC_NOR)        += simtec-nor.o
+obj-$(CONFIG_S3C24XX_SIMTEC_PM)         += simtec-pm.o
+obj-$(CONFIG_S3C24XX_SIMTEC_USB)        += simtec-usb.o
+
+# machine additions
+
+obj-$(CONFIG_MACH_BAST_IDE)             += bast-ide.o
+obj-$(CONFIG_MACH_OSIRIS_DVS)           += mach-osiris-dvs.o
+
+# device setup
+
+obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_ARCH_S3C24XX)              += setup-i2c.o
+obj-$(CONFIG_S3C24XX_SETUP_TS)          += setup-ts.o
diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c24xx/Makefile.boot
index 4457605ba04..4457605ba04 100644
--- a/arch/arm/mach-s3c2410/Makefile.boot
+++ b/arch/arm/mach-s3c24xx/Makefile.boot
diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c
index 298ececfa36..298ececfa36 100644
--- a/arch/arm/mach-s3c2410/bast-ide.c
+++ b/arch/arm/mach-s3c24xx/bast-ide.c
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index ac7b2ad5c40..ac7b2ad5c40 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index d10b695a906..d10b695a906 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 59f54d1d7f8..dbc9ab4aaca 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -15,7 +15,6 @@
 #include <linux/clk.h>
 
 #include <plat/s3c2416.h>
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
@@ -132,12 +131,6 @@ static struct clk hsmmc0_clk = {
         .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 };
 
-void __init_or_cpufreq s3c2416_setup_clocks(void)
-{
-        s3c2443_common_setup_clocks(s3c2416_get_pll);
-}
-
-
 static struct clksrc_clk *clksrcs[] __initdata = {
         &hsspi_eplldiv,
         &hsspi_mux,
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 414364eb426..414364eb426 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 6dde2696f8f..efb3ac35956 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,11 +179,6 @@ static struct clk *clks[] __initdata = {
         &clk_hsmmc,
 };
 
-void __init_or_cpufreq s3c2443_setup_clocks(void)
-{
-        s3c2443_common_setup_clocks(s3c2443_get_mpll);
-}
-
 void __init s3c2443_init_clocks(int xtal)
 {
         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -196,8 +191,6 @@ void __init s3c2443_init_clocks(int xtal)
                                    armdiv, ARRAY_SIZE(armdiv),
                                    S3C2443_CLKDIV0_ARMDIV_MASK);
 
-        s3c2443_setup_clocks();
-
         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c24xx/clock-s3c244x.c
index 6d9b688c442..6d9b688c442 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c244x.c
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 95e68190d59..460431589f3 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -1,9 +1,18 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
+/*
+ * Common code for SoCs starting with the S3C2443
  *
  * Copyright (c) 2007, 2010 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * S3C2443 Clock control suport - common code
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #include <linux/init.h>
@@ -12,7 +21,6 @@
 
 #include <mach/regs-s3c2443-clock.h>
 
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
@@ -53,7 +61,7 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
  * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
  * such directly equating the two source clocks is impossible.
  */
-struct clk clk_mpllref = {
+static struct clk clk_mpllref = {
         .name           = "mpllref",
         .parent         = &clk_xtal,
 };
@@ -160,6 +168,44 @@ static struct clk clk_prediv = {
         },
 };
 
+/* hclk divider
+ *
+ * divides the prediv and provides the hclk.
+ */
+
+static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk_ops clk_h_ops = {
+        .get_rate       = s3c2443_hclkdiv_getrate,
+};
+
+/* pclk divider
+ *
+ * divides the hclk and provides the pclk.
+ */
+
+static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk_ops clk_p_ops = {
+        .get_rate       = s3c2443_pclkdiv_getrate,
+};
+
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
@@ -516,26 +562,15 @@ static struct clk hsmmc1_clk = {
         .ctrlbit        = S3C2443_HCLKCON_HSMMC,
 };
 
-static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
-{
-        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
-
-        return clkcon0 + 1;
-}
-
 /* EPLLCON compatible enough to get on/off information */
 
 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 {
         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
         unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
         struct clk *xtal_clk;
         unsigned long xtal;
         unsigned long pll;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
         int ptr;
 
         xtal_clk = clk_get(NULL, "xtal");
@@ -544,18 +579,13 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 
         pll = get_mpll(mpllcon, xtal);
         clk_msysclk.clk.rate = pll;
-
-        fclk = clk_get_rate(&clk_armdiv);
-        hclk = s3c2443_prediv_getrate(&clk_prediv);
-        hclk /= s3c2443_get_hdiv(clkdiv0);
-        pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
+        clk_mpll.rate = pll;
 
         printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
-               (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
-               print_mhz(pll), print_mhz(fclk),
-               print_mhz(hclk), print_mhz(pclk));
+               (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
+               print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
+               print_mhz(clk_get_rate(&clk_h)),
+               print_mhz(clk_get_rate(&clk_p)));
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
                 s3c_set_clksrc(&clksrc_clks[ptr], true);
@@ -568,7 +598,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
         }
 
         printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+               (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
                print_mhz(clk_get_rate(&clk_epll)),
                print_mhz(clk_get_rate(&clk_usb_bus)));
 }
@@ -611,9 +641,13 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
         nr_armdiv = nr_divs;
         armdivmask = divmask;
 
-        /* s3c2443 parents h and p clocks from prediv */
+        /* s3c2443 parents h clock from prediv */
         clk_h.parent = &clk_prediv;
-        clk_p.parent = &clk_prediv;
+        clk_h.ops = &clk_h_ops;
+
+        /* and p clock from h clock */
+        clk_p.parent = &clk_h;
+        clk_p.ops = &clk_p_ops;
 
         clk_usb_bus.parent = &clk_usb_bus_host.clk;
         clk_epll.parent = &clk_epllref.clk;
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 084604be6ad..084604be6ad 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 4803338cf56..4803338cf56 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index 38472ac920f..38472ac920f 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 5f0a0c8ef84..5f0a0c8ef84 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 14224517e62..e227c472a40 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -51,7 +51,7 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "xdreq1",
                 .channels       = MAP(S3C2443_DMAREQSEL_XDREQ1),
         },
-        [DMACH_SDI] = {
+        [DMACH_SDI] = { /* only on S3C2443 */
                 .name           = "sdi",
                 .channels       = MAP(S3C2443_DMAREQSEL_SDI),
         },
@@ -59,7 +59,7 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "spi0",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI0TX),
         },
-        [DMACH_SPI1] = {
+        [DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
                 .name           = "spi1",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI1TX),
         },
@@ -71,11 +71,11 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_0),
         },
-        [DMACH_UART2] = {
+        [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_0),
         },
-        [DMACH_UART3] = {
+        [DMACH_UART3] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_0),
         },
@@ -87,11 +87,11 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_1),
         },
-        [DMACH_UART2_SRC2] = {
+        [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_1),
         },
-        [DMACH_UART3_SRC2] = {
+        [DMACH_UART3_SRC2] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_1),
         },
@@ -142,6 +142,23 @@ static int __init s3c2443_dma_add(struct device *dev,
         return s3c24xx_dma_init_map(&s3c2443_dma_sel);
 }
 
+#ifdef CONFIG_CPU_S3C2416
+/* S3C2416 DMA contains the same selection table as the S3C2443 */
+static struct subsys_interface s3c2416_dma_interface = {
+        .name           = "s3c2416_dma",
+        .subsys         = &s3c2416_subsys,
+        .add_dev        = s3c2443_dma_add,
+};
+
+static int __init s3c2416_dma_init(void)
+{
+        return subsys_interface_register(&s3c2416_dma_interface);
+}
+
+arch_initcall(s3c2416_dma_init);
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
 static struct subsys_interface s3c2443_dma_interface = {
         .name           = "s3c2443_dma",
         .subsys         = &s3c2443_subsys,
@@ -154,3 +171,4 @@ static int __init s3c2443_dma_init(void)
 }
 
 arch_initcall(s3c2443_dma_init);
+#endif
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index a5eeb62ce1c..a5eeb62ce1c 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
index 1b614d5a81f..1b614d5a81f 100644
--- a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
index a2a328134e3..a2a328134e3 100644
--- a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-map.h b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
index c9deb3a5b2c..c9deb3a5b2c 100644
--- a/arch/arm/mach-s3c2410/include/mach/anubis-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
index bee2a7a932a..bee2a7a932a 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
index cac428c42e7..cac428c42e7 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
index 6e7dc9d0cf0..6e7dc9d0cf0 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
index 4c38b39b741..4c38b39b741 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 4135de87d1f..4135de87d1f 100644
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index acbdfecd418..acbdfecd418 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
diff --git a/arch/arm/mach-s3c2410/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
index 473b3cd37d9..7615a14773f 100644
--- a/arch/arm/mach-s3c2410/include/mach/entry-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
@@ -25,9 +25,6 @@
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \base, #S3C24XX_VA_IRQ
@@ -71,8 +68,3 @@
                 @@ exit here, Z flag unset if IRQ
 
         .endm
-
-                /* currently don't need an disable_fiq macro */
-
-                .macro  disable_fiq
-                .endm
diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c24xx/include/mach/fb.h
index a957bc8ed44..a957bc8ed44 100644
--- a/arch/arm/mach-s3c2410/include/mach/fb.h
+++ b/arch/arm/mach-s3c24xx/include/mach/fb.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
index c53ad34c657..c53ad34c657 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
index 019ea86057f..019ea86057f 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
index c410a078622..c410a078622 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
index 6fac70f3484..6fac70f3484 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h
diff --git a/arch/arm/mach-s3c2440/include/mach/gta02.h b/arch/arm/mach-s3c24xx/include/mach/gta02.h
index 3a56a229cac..3a56a229cac 100644
--- a/arch/arm/mach-s3c2440/include/mach/gta02.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gta02.h
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
index fc897d3a056..fc897d3a056 100644
--- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+++ b/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c24xx/include/mach/h1940.h
index 2aa683c8d3d..2aa683c8d3d 100644
--- a/arch/arm/mach-s3c2410/include/mach/h1940.h
+++ b/arch/arm/mach-s3c24xx/include/mach/h1940.h
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index aef5631eac5..aef5631eac5 100644
--- a/arch/arm/mach-s3c2410/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
diff --git a/arch/arm/mach-s3c2410/include/mach/idle.h b/arch/arm/mach-s3c24xx/include/mach/idle.h
index e9ddd706b16..e9ddd706b16 100644
--- a/arch/arm/mach-s3c2410/include/mach/idle.h
+++ b/arch/arm/mach-s3c24xx/include/mach/idle.h
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c24xx/include/mach/io.h
index 118749f37c4..118749f37c4 100644
--- a/arch/arm/mach-s3c2410/include/mach/io.h
+++ b/arch/arm/mach-s3c24xx/include/mach/io.h
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index e53b2177319..e53b2177319 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
diff --git a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h b/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
index d8a7672519b..d8a7672519b 100644
--- a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 78ae807f128..78ae807f128 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
index e9e36b0abba..e9e36b0abba 100644
--- a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
index 17380f84842..17380f84842 100644
--- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/otom-map.h b/arch/arm/mach-s3c24xx/include/mach/otom-map.h
index f9277a52c14..f9277a52c14 100644
--- a/arch/arm/mach-s3c2410/include/mach/otom-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/otom-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
index 2eef7e6f767..2eef7e6f767 100644
--- a/arch/arm/mach-s3c2410/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
index 3415b60082d..3415b60082d 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
index 98fd4a05587..98fd4a05587 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index cac1ad6b582..cac1ad6b582 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
index 19575e06111..19575e06111 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c24xx/include/mach/regs-irq.h
index 0f07ba30b1f..0f07ba30b1f 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
index ee8f040aff5..ee8f040aff5 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
index e0c67b0163d..e0c67b0163d 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
index 4932b87bdf3..4932b87bdf3 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-power.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
index fb635251509..fb635251509 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
index aa69dc79bc3..aa69dc79bc3 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
index 2f31b74974a..2f31b74974a 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
index e443167efb8..e443167efb8 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
index c3feff3c048..c3feff3c048 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
index cbf2d8884e3..cbf2d8884e3 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c24xx/include/mach/tick.h
index 544da41979d..544da41979d 100644
--- a/arch/arm/mach-s3c2410/include/mach/tick.h
+++ b/arch/arm/mach-s3c24xx/include/mach/tick.h
diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c24xx/include/mach/timex.h
index fe9ca1ffd51..fe9ca1ffd51 100644
--- a/arch/arm/mach-s3c2410/include/mach/timex.h
+++ b/arch/arm/mach-s3c24xx/include/mach/timex.h
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
index 8b283f847da..8b283f847da 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
index e4119913d7c..e4119913d7c 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
index 47add133b8e..47add133b8e 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
index 99612fcc4eb..99612fcc4eb 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
index e65619ddbcc..e65619ddbcc 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2412.c
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
index fd49f35e448..fd49f35e448 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2440.c
index 4a18cde439c..4a18cde439c 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2440.c
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
index ac2829f56d1..ac2829f56d1 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c24xx/irq-s3c244x.c
index 5fe8e58d3af..5fe8e58d3af 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c244x.c
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 4220cc60de3..4220cc60de3 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 19b577bc09b..60c72c54c21 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -55,6 +55,7 @@
 #include <plat/cpu.h>
 #include <plat/audio-simtec.h>
 
+#include "simtec.h"
 #include "common.h"
 
 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index d7ae49c9011..d7ae49c9011 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index feeaf73933d..53219c02eca 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -64,8 +64,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/audio-simtec.h>
 
-#include "usb-simtec.h"
-#include "nor-simtec.h"
+#include "simtec.h"
 #include "common.h"
 
 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 9a4a5bc008e..ba5d8539410 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -38,6 +38,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/s3c24xx.h>
 
 #include <linux/mmc/host.h>
 
@@ -73,7 +74,6 @@
 #include <mach/regs-gpioj.h>
 #include <mach/fb.h>
 
-#include <mach/spi.h>
 #include <plat/usb-control.h>
 #include <mach/regs-mem.h>
 #include <mach/hardware.h>
@@ -258,7 +258,7 @@ static struct pcf50633_bl_platform_data gta02_backlight_data = {
         .ramp_time = 5,
 };
 
-struct pcf50633_platform_data gta02_pcf_pdata = {
+static struct pcf50633_platform_data gta02_pcf_pdata = {
         .resumers = {
                 [0] =   PCF50633_INT1_USBINS |
                         PCF50633_INT1_USBREM |
@@ -404,7 +404,7 @@ static struct platform_device gta02_nor_flash = {
 };
 
 
-struct platform_device s3c24xx_pwm_device = {
+static struct platform_device s3c24xx_pwm_device = {
         .name           = "s3c24xx_pwm",
         .num_resources  = 0,
 };
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 41245a60398..6b21ba107ea 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -162,7 +162,7 @@ static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
         return (latch_state >> (offset + 16)) & 1;
 }
 
-struct gpio_chip h1940_latch_gpiochip = {
+static struct gpio_chip h1940_latch_gpiochip = {
         .base                   = H1940_LATCH_GPIO(0),
         .owner                  = THIS_MODULE,
         .label                  = "H1940_LATCH",
@@ -304,7 +304,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
         { .volt = 3841, .cur = 0, .level = 0},
 };
 
-int h1940_bat_init(void)
+static int h1940_bat_init(void)
 {
         int ret;
 
@@ -317,17 +317,17 @@ int h1940_bat_init(void)
 
 }
 
-void h1940_bat_exit(void)
+static void h1940_bat_exit(void)
 {
         gpio_free(H1940_LATCH_SM803_ENABLE);
 }
 
-void h1940_enable_charger(void)
+static void h1940_enable_charger(void)
 {
         gpio_set_value(H1940_LATCH_SM803_ENABLE, 1);
 }
 
-void h1940_disable_charger(void)
+static void h1940_disable_charger(void)
 {
         gpio_set_value(H1940_LATCH_SM803_ENABLE, 0);
 }
@@ -364,7 +364,7 @@ static struct platform_device h1940_battery = {
         },
 };
 
-DEFINE_SPINLOCK(h1940_blink_spin);
+static DEFINE_SPINLOCK(h1940_blink_spin);
 
 int h1940_led_blink_set(unsigned gpio, int state,
         unsigned long *delay_on, unsigned long *delay_off)
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ae73ba34ecc..ae73ba34ecc 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 5d66fb218a4..5d66fb218a4 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 383d00ca8f6..383d00ca8f6 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 5198e3e1c5b..5198e3e1c5b 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
diff --git a/arch/arm/mach-s3c2440/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index ad2792dfbee..ad2792dfbee 100644
--- a/arch/arm/mach-s3c2440/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index c5daeb612a8..c5daeb612a8 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 5f1e0eeb38a..5f1e0eeb38a 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 91c16d9d245..91c16d9d245 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 6f68abf44fa..200debb4c72 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -217,7 +217,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
         { .volt = 3820, .cur = 0, .level = 0},
 };
 
-int rx1950_bat_init(void)
+static int rx1950_bat_init(void)
 {
         int ret;
 
@@ -236,25 +236,25 @@ err_gpio1:
         return ret;
 }
 
-void rx1950_bat_exit(void)
+static void rx1950_bat_exit(void)
 {
         gpio_free(S3C2410_GPJ(2));
         gpio_free(S3C2410_GPJ(3));
 }
 
-void rx1950_enable_charger(void)
+static void rx1950_enable_charger(void)
 {
         gpio_direction_output(S3C2410_GPJ(2), 1);
         gpio_direction_output(S3C2410_GPJ(3), 1);
 }
 
-void rx1950_disable_charger(void)
+static void rx1950_disable_charger(void)
 {
         gpio_direction_output(S3C2410_GPJ(2), 0);
         gpio_direction_output(S3C2410_GPJ(3), 0);
 }
 
-DEFINE_SPINLOCK(rx1950_blink_spin);
+static DEFINE_SPINLOCK(rx1950_blink_spin);
 
 static int rx1950_led_blink_set(unsigned gpio, int state,
         unsigned long *delay_on, unsigned long *delay_off)
@@ -382,7 +382,7 @@ static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
 
 static struct pwm_device *lcd_pwm;
 
-void rx1950_lcd_power(int enable)
+static void rx1950_lcd_power(int enable)
 {
         int i;
         static int enabled;
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 56af3544759..56af3544759 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index bdc27e77287..bdc27e77287 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index b11451b853d..b11451b853d 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index eebe1e72b93..30a44f806e0 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -125,7 +125,7 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
         }
 };
 
-void smdk2416_hsudc_gpio_init(void)
+static void smdk2416_hsudc_gpio_init(void)
 {
         s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP);
         s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE);
@@ -133,20 +133,20 @@ void smdk2416_hsudc_gpio_init(void)
         s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0);
 }
 
-void smdk2416_hsudc_gpio_uninit(void)
+static void smdk2416_hsudc_gpio_uninit(void)
 {
         s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1);
         s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE);
         s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0));
 }
 
-struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
+static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
         .epnum = 9,
         .gpio_init = smdk2416_hsudc_gpio_init,
         .gpio_uninit = smdk2416_hsudc_gpio_uninit,
 };
 
-struct s3c_fb_pd_win smdk2416_fb_win[] = {
+static struct s3c_fb_pd_win smdk2416_fb_win[] = {
         [0] = {
                 /* think this is the same as the smdk6410 */
                 .win_mode       = {
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 83a1036d7dc..83a1036d7dc 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 20923695622..20923695622 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 1114666f0ef..1114666f0ef 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index dbe668a803e..87608d45dac 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -51,8 +51,7 @@
 #include <plat/iic.h>
 #include <plat/audio-simtec.h>
 
-#include "usb-simtec.h"
-#include "nor-simtec.h"
+#include "simtec.h"
 #include "common.h"
 
 /* macros for virtual address mods for the io space entries */
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 94bfaa1fb14..94bfaa1fb14 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c24xx/pm-h1940.S
index c93bf2db9f4..c93bf2db9f4 100644
--- a/arch/arm/mach-s3c2410/pm-h1940.S
+++ b/arch/arm/mach-s3c24xx/pm-h1940.S
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 03f706dd600..03f706dd600 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index d04588506ec..d04588506ec 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index 1bd4817b8eb..1bd4817b8eb 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index a3c5cb086ee..a3c5cb086ee 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 100ef1c320e..d4bc7f960bb 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -33,8 +33,6 @@
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 
-#include <mach/idle.h>
-
 #include <plat/cpu-freq.h>
 
 #include <mach/regs-clock.h>
@@ -165,7 +163,7 @@ void __init s3c2412_map_io(void)
 
         /* set our idle function */
 
-        s3c24xx_idle = s3c2412_idle;
+        arm_pm_idle = s3c2412_idle;
 
         /* register our io-tables */
 
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index ed67ec9c83d..7743fade50d 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -45,7 +45,6 @@
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 
-#include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
 
 #include <plat/gpio-core.h>
@@ -61,6 +60,7 @@
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
 #include <plat/adc-core.h>
+#include <plat/rtc-core.h>
 
 static struct map_desc s3c2416_iodesc[] __initdata = {
         IODESC_ENT(WATCHDOG),
@@ -89,8 +89,6 @@ int __init s3c2416_init(void)
 {
         printk(KERN_INFO "S3C2416: Initializing architecture\n");
 
-        /* s3c24xx_idle = s3c2416_idle; */
-
         /* change WDT IRQ number */
         s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
         s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;
@@ -102,6 +100,7 @@ int __init s3c2416_init(void)
         s3c_fb_setname("s3c2443-fb");
 
         s3c_adc_setname("s3c2416-adc");
+        s3c_rtc_setname("s3c2416-rtc");
 
 #ifdef CONFIG_PM
         register_syscore_ops(&s3c2416_pm_syscore_ops);
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 2b3dddb49af..2b3dddb49af 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 22cb7c94a8c..22cb7c94a8c 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 9318847bdc3..ab648ad8fa5 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -42,6 +42,7 @@
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
 #include <plat/adc-core.h>
+#include <plat/rtc-core.h>
 
 static struct map_desc s3c2443_iodesc[] __initdata = {
         IODESC_ENT(WATCHDOG),
@@ -74,6 +75,7 @@ int __init s3c2443_init(void)
         s3c_fb_setname("s3c2443-fb");
 
         s3c_adc_setname("s3c2443-adc");
+        s3c_rtc_setname("s3c2443-rtc");
 
         /* change WDT IRQ number */
         s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 6f74118f60c..6f74118f60c 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c24xx/setup-i2c.c
index 9e90a7cbd1d..9e90a7cbd1d 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/mach-s3c24xx/setup-i2c.c
diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
index f65cb3ef16c..f65cb3ef16c 100644
--- a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
diff --git a/arch/arm/plat-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c
index ed263866367..ed263866367 100644
--- a/arch/arm/plat-s3c24xx/setup-ts.c
+++ b/arch/arm/mach-s3c24xx/setup-ts.c
diff --git a/arch/arm/plat-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index 6bc832e0d8e..11881c9a38c 100644
--- a/arch/arm/plat-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -27,6 +27,8 @@
 #include <plat/audio-simtec.h>
 #include <plat/devs.h>
 
+#include "simtec.h"
+
 /* platform ops for audio */
 
 static void simtec_audio_startup_lrroute(void)
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c24xx/simtec-nor.c
index ad9f750f1e5..2119ca6a73b 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -30,7 +30,7 @@
 #include <mach/bast-map.h>
 #include <mach/bast-cpld.h>
 
-#include "nor-simtec.h"
+#include "simtec.h"
 
 static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
 {
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/mach-s3c24xx/simtec-pm.c
index 699f9317129..699f9317129 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-pm.c
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index 29bd3d987be..d91c1a72513 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -37,7 +37,7 @@
 #include <plat/usb-control.h>
 #include <plat/devs.h>
 
-#include "usb-simtec.h"
+#include "simtec.h"
 
 /* control power and monitor over-current events on various Simtec
  * designed boards.
diff --git a/arch/arm/mach-s3c2410/nor-simtec.h b/arch/arm/mach-s3c24xx/simtec.h
index f619c1e0d0c..ae8f4f9ad2e 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.h
+++ b/arch/arm/mach-s3c24xx/simtec.h
@@ -4,11 +4,18 @@
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * Simtec NOR mapping
+ * Simtec common functions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
+struct s3c24xx_audio_simtec_pdata;
+
 extern void nor_simtec_init(void);
+
+extern int usb_simtec_init(void);
+
+extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
+                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a..dd5b6388a5a 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
diff --git a/arch/arm/mach-s3c2412/sleep.S b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
index c82418ed714..c82418ed714 100644
--- a/arch/arm/mach-s3c2412/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index dd20c66cd70..82c0915729e 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -83,6 +83,11 @@ config S3C64XX_SETUP_SPI
         help
          Common setup code for SPI GPIO configurations
 
+config S3C64XX_SETUP_USB_PHY
+        bool
+        help
+          Common setup code for USB PHY controller
+
 # S36400 Macchine support
 
 config MACH_SMDK6400
@@ -157,6 +162,7 @@ config MACH_SMDK6410
         select S3C64XX_SETUP_IDE
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
+        select S3C64XX_SETUP_USB_PHY
         help
           Machine support for the Samsung SMDK6410
 
@@ -256,6 +262,7 @@ config MACH_SMARTQ
         select S3C_DEV_USB_HOST
         select S3C64XX_SETUP_SDHCI
         select S3C64XX_SETUP_FB_24BPP
+        select S3C64XX_SETUP_USB_PHY
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
@@ -283,6 +290,7 @@ config MACH_WLF_CRAGG_6410
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
         select S3C64XX_SETUP_SPI
+        select S3C64XX_SETUP_USB_PHY
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_KEYPAD
         select S3C_DEV_USB_HOST
@@ -296,5 +304,6 @@ config MACH_WLF_CRAGG_6410
         select S3C64XX_DEV_SPI0
         select SAMSUNG_GPIO_EXTRA128
         select I2C
+        select LEDS_GPIO_REGISTER
         help
           Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 1822ac2eba3..f9ce1dc28ce 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_CPU_S3C6410)	+= s3c6410.o
 # PM
 
 obj-$(CONFIG_PM)                += pm.o irq-pm.o sleep.o
+obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
 # DMA support
 
@@ -42,6 +43,7 @@ obj-$(CONFIG_S3C64XX_SETUP_IDE)		+= setup-ide.o
 obj-$(CONFIG_S3C64XX_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_S3C64XX_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index aebbcc291b4..52f079a691c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -207,6 +207,15 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c64xx_sclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
         }, {
+                .name           = "ac97",
+                .parent         = &clk_p,
+                .ctrlbit        = S3C_CLKCON_PCLK_AC97,
+        }, {
+                .name           = "cfcon",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
+        }, {
                 .name           = "dma0",
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
@@ -216,6 +225,107 @@ static struct clk init_clocks_off[] = {
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
+        }, {
+                .name           = "3dse",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_3DSE,
+        }, {
+                .name           = "hclk_secur",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SECUR,
+        }, {
+                .name           = "sdma1",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SDMA1,
+        }, {
+                .name           = "sdma0",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SDMA0,
+        }, {
+                .name           = "hclk_jpeg",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_JPEG,
+        }, {
+                .name           = "camif",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_CAMIF,
+        }, {
+                .name           = "hclk_scaler",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SCALER,
+        }, {
+                .name           = "2d",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_2D,
+        }, {
+                .name           = "tv",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_TV,
+        }, {
+                .name           = "post0",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_POST0,
+        }, {
+                .name           = "rot",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_ROT,
+        }, {
+                .name           = "hclk_mfc",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_MFC,
+        }, {
+                .name           = "pclk_mfc",
+                .parent         = &clk_p,
+                .enable         = s3c64xx_pclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_PCLK_MFC,
+        }, {
+                .name           = "dac27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_DAC27,
+        }, {
+                .name           = "tv27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_TV27,
+        }, {
+                .name           = "scaler27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SCALER27,
+        }, {
+                .name           = "sclk_scaler",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SCALER,
+        }, {
+                .name           = "post0_27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_POST0_27,
+        }, {
+                .name           = "secur",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SECUR,
+        }, {
+                .name           = "sclk_mfc",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_MFC,
+        }, {
+                .name           = "cam",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_CAM,
+        }, {
+                .name           = "sclk_jpeg",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_JPEG,
         },
 };
 
@@ -289,16 +399,7 @@ static struct clk init_clocks[] = {
                 .name           = "watchdog",
                 .parent         = &clk_p,
                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
-        }, {
-                .name           = "ac97",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C_CLKCON_PCLK_AC97,
-        }, {
-                .name           = "cfcon",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
-        }
+        },
 };
 
 static struct clk clk_hsmmc0 = {
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 5eb9c9a7d73..7a10be629ab 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -25,8 +25,6 @@ void s3c64xx_setup_clocks(void);
 
 void s3c64xx_restart(char mode, const char *cmd);
 
-extern struct syscore_ops s3c64xx_irq_syscore_ops;
-
 #ifdef CONFIG_CPU_S3C6400
 
 extern  int s3c6400_init(void);
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
new file mode 100644
index 00000000000..179460f38db
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -0,0 +1,91 @@
+/* linux/arch/arm/mach-s3c64xx/cpuidle.c
+ *
+ * Copyright (c) 2011 Wolfson Microelectronics, plc
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+#include <linux/export.h>
+#include <linux/time.h>
+
+#include <asm/proc-fns.h>
+
+#include <mach/map.h>
+
+#include <mach/regs-sys.h>
+#include <mach/regs-syscon-power.h>
+
+static int s3c64xx_enter_idle(struct cpuidle_device *dev,
+                              struct cpuidle_driver *drv,
+                              int index)
+{
+        struct timeval before, after;
+        unsigned long tmp;
+        int idle_time;
+
+        local_irq_disable();
+        do_gettimeofday(&before);
+
+        /* Setup PWRCFG to enter idle mode */
+        tmp = __raw_readl(S3C64XX_PWR_CFG);
+        tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+        tmp |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
+        __raw_writel(tmp, S3C64XX_PWR_CFG);
+
+        cpu_do_idle();
+
+        do_gettimeofday(&after);
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                    (after.tv_usec - before.tv_usec);
+
+        dev->last_residency = idle_time;
+        return index;
+}
+
+static struct cpuidle_state s3c64xx_cpuidle_set[] = {
+        [0] = {
+                .enter                  = s3c64xx_enter_idle,
+                .exit_latency           = 1,
+                .target_residency       = 1,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "IDLE",
+                .desc                   = "System active, ARM gated",
+        },
+};
+
+static struct cpuidle_driver s3c64xx_cpuidle_driver = {
+        .name           = "s3c64xx_cpuidle",
+        .owner          = THIS_MODULE,
+        .state_count    = ARRAY_SIZE(s3c64xx_cpuidle_set),
+};
+
+static struct cpuidle_device s3c64xx_cpuidle_device = {
+        .state_count    = ARRAY_SIZE(s3c64xx_cpuidle_set),
+};
+
+static int __init s3c64xx_init_cpuidle(void)
+{
+        int ret;
+
+        memcpy(s3c64xx_cpuidle_driver.states, s3c64xx_cpuidle_set,
+               sizeof(s3c64xx_cpuidle_set));
+        cpuidle_register_driver(&s3c64xx_cpuidle_driver);
+
+        ret = cpuidle_register_device(&s3c64xx_cpuidle_device);
+        if (ret) {
+                pr_err("Failed to register cpuidle device: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+device_initcall(s3c64xx_init_cpuidle);
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
deleted file mode 100644
index dc2bc15142c..00000000000
--- a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Low-level IRQ helper macros for the Samsung S3C64XX series
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
deleted file mode 100644
index 353ed4389ae..00000000000
--- a/arch/arm/mach-s3c64xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-s3c6400/include/mach/system.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C6400 - system implementation
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index 8bec61e242c..0c7e1d960ca 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -96,7 +96,7 @@ static void s3c64xx_irq_pm_resume(void)
         S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
 }
 
-struct syscore_ops s3c64xx_irq_syscore_ops = {
+static struct syscore_ops s3c64xx_irq_syscore_ops = {
         .suspend = s3c64xx_irq_pm_suspend,
         .resume  = s3c64xx_irq_pm_resume,
 };
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 32a30f38ba0..0ace108c3e3 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -11,18 +11,38 @@
 #include <linux/export.h>
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
+#include <linux/spi/spi.h>
 
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
 #include <linux/mfd/wm8994/pdata.h>
 
+#include <linux/regulator/machine.h>
+
 #include <sound/wm5100.h>
 #include <sound/wm8996.h>
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
 
+#include <plat/s3c64xx-spi.h>
+
 #include <mach/crag6410.h>
 
+static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
+        .set_level = gpio_set_value,
+        .line = S3C64XX_GPC(3),
+};
+
+static struct spi_board_info wm1253_devs[] = {
+        [0] = {
+                .modalias       = "wm0010",
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+                .controller_data = &wm0010_spi_csinfo,
+        },
+};
+
 static struct wm5100_pdata wm5100_pdata = {
         .ldo_ena = S3C64XX_GPN(7),
         .irq_flags = IRQF_TRIGGER_HIGH,
@@ -135,6 +155,14 @@ static const struct i2c_board_info wm1259_devs[] = {
         },
 };
 
+static struct regulator_init_data wm8994_ldo1 = {
+        .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data wm8994_ldo2 = {
+        .supply_regulator = "WALLVDD",
+};
+
 static struct wm8994_pdata wm8994_pdata = {
         .gpio_base = CODEC_GPIO_BASE,
         .gpio_defaults = {
@@ -142,8 +170,8 @@ static struct wm8994_pdata wm8994_pdata = {
         },
         .irq_base = CODEC_IRQ_BASE,
         .ldo = {
-                { .supply = "WALLVDD" },
-                { .supply = "WALLVDD" },
+                 { .init_data = &wm8994_ldo1, },
+                 { .init_data = &wm8994_ldo2, },
         },
 };
 
@@ -159,14 +187,21 @@ static __devinitdata const struct {
         const char *name;
         const struct i2c_board_info *i2c_devs;
         int num_i2c_devs;
+        const struct spi_board_info *spi_devs;
+        int num_spi_devs;
 } gf_mods[] = {
         { .id = 0x01, .name = "1250-EV1 Springbank" },
         { .id = 0x02, .name = "1251-EV1 Jura" },
         { .id = 0x03, .name = "1252-EV1 Glenlivet" },
         { .id = 0x11, .name = "6249-EV2 Glenfarclas", },
+        { .id = 0x14, .name = "6271-EV1 Lochnagar" },
+        { .id = 0x15, .name = "XXXX-EV1 Bells" },
         { .id = 0x21, .name = "1275-EV1 Mortlach" },
         { .id = 0x25, .name = "1274-EV1 Glencadam" },
-        { .id = 0x31, .name = "1253-EV1 Tomatin", },
+        { .id = 0x31, .name = "1253-EV1 Tomatin",
+          .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
+        { .id = 0x32, .name = "XXXX-EV1 Caol Illa" },
+        { .id = 0x33, .name = "XXXX-EV1 Oban" },
         { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
           .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
         { .id = 0x3a, .name = "1259-EV1 Tobermory",
@@ -198,12 +233,16 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
         if (i < ARRAY_SIZE(gf_mods)) {
                 dev_info(&i2c->dev, "%s revision %d\n",
                          gf_mods[i].name, rev + 1);
+
                 for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
                         if (!i2c_new_device(i2c->adapter,
                                             &(gf_mods[i].i2c_devs[j])))
                                 dev_err(&i2c->dev,
                                         "Failed to register dev: %d\n", ret);
                 }
+
+                spi_register_board_info(gf_mods[i].spi_devs,
+                                        gf_mods[i].num_spi_devs);
         } else {
                 dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
                          id, rev + 1);
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 8077f650eb0..e20bf583536 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -19,7 +19,9 @@
 #include <linux/io.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
 #include <linux/delay.h>
+#include <linux/mmc/host.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/pwm_backlight.h>
@@ -59,6 +61,7 @@
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
 #include <plat/s3c64xx-spi.h>
+#include <plat/udc-hs.h>
 
 #include <plat/keypad.h>
 #include <plat/clock.h>
@@ -298,6 +301,7 @@ static struct platform_device littlemill_device = {
 };
 
 static struct regulator_consumer_supply wallvdd_consumers[] = {
+        REGULATOR_SUPPLY("SPKVDD", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
         REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
@@ -574,11 +578,19 @@ static struct s3c2410_platform_i2c i2c0_pdata = {
         .frequency = 400000,
 };
 
+static struct regulator_consumer_supply pvdd_1v2_consumers[] __initdata = {
+        REGULATOR_SUPPLY("DCVDD", "spi0.0"),
+        REGULATOR_SUPPLY("AVDD", "spi0.0"),
+};
+
 static struct regulator_init_data pvdd_1v2 __initdata = {
         .constraints = {
                 .name = "PVDD_1V2",
-                .always_on = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
+
+        .consumer_supplies = pvdd_1v2_consumers,
+        .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
 };
 
 static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
@@ -592,6 +604,7 @@ static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
         REGULATOR_SUPPLY("AVDD2", "1-001a"),
         REGULATOR_SUPPLY("DCVDD", "1-001a"),
         REGULATOR_SUPPLY("AVDD", "1-001a"),
+        REGULATOR_SUPPLY("DBVDD", "spi0.0"),
 };
 
 static struct regulator_init_data pvdd_1v8 __initdata = {
@@ -681,6 +694,7 @@ static void __init crag6410_map_io(void)
 static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
         .max_width              = 4,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
+        .host_caps              = MMC_CAP_POWER_OFF_CARD,
 };
 
 static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
@@ -696,8 +710,59 @@ static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
         .max_width              = 4,
         .cd_type                = S3C_SDHCI_CD_INTERNAL,
         .cfg_gpio               = crag6410_cfg_sdhci0,
+        .host_caps              = MMC_CAP_POWER_OFF_CARD,
+};
+
+static const struct gpio_led gpio_leds[] = {
+        {
+                .name = "d13:green:",
+                .gpio = MMGPIO_GPIO_BASE + 0,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d14:green:",
+                .gpio = MMGPIO_GPIO_BASE + 1,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d15:green:",
+                .gpio = MMGPIO_GPIO_BASE + 2,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d16:green:",
+                .gpio = MMGPIO_GPIO_BASE + 3,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d17:green:",
+                .gpio = MMGPIO_GPIO_BASE + 4,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d18:green:",
+                .gpio = MMGPIO_GPIO_BASE + 5,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d19:green:",
+                .gpio = MMGPIO_GPIO_BASE + 6,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d20:green:",
+                .gpio = MMGPIO_GPIO_BASE + 7,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
 };
 
+static const struct gpio_led_platform_data gpio_leds_pdata = {
+        .leds = gpio_leds,
+        .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct s3c_hsotg_plat crag6410_hsotg_pdata;
+
 static void __init crag6410_machine_init(void)
 {
         /* Open drain IRQs need pullups */
@@ -722,14 +787,18 @@ static void __init crag6410_machine_init(void)
         s3c_i2c0_set_platdata(&i2c0_pdata);
         s3c_i2c1_set_platdata(&i2c1_pdata);
         s3c_fb_set_platdata(&crag6410_lcd_pdata);
+        s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
         samsung_keypad_set_platdata(&crag6410_keypad_data);
+        s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
 
         platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
 
+        gpio_led_register_device(-1, &gpio_leds_pdata);
+
         regulator_has_full_constraints();
 
         s3c64xx_pm_init();
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ce31db13623..ce745e19aa2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -187,6 +187,8 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
         },
 };
 
+static struct s3c_hsotg_plat smartq_hsotg_pdata;
+
 static int __init smartq_lcd_setup_gpio(void)
 {
         int ret;
@@ -383,6 +385,7 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
+        s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
         s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
         s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
         s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ca6fc204f0e..d55bc96d958 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -72,6 +72,7 @@
 #include <plat/keypad.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include <plat/udc-hs.h>
 
 #include "common.h"
 
@@ -631,6 +632,8 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
         .pwm_id = 1,
 };
 
+static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
+
 static void __init smdk6410_map_io(void)
 {
         u32 tmp;
@@ -659,6 +662,7 @@ static void __init smdk6410_machine_init(void)
         s3c_i2c0_set_platdata(NULL);
         s3c_i2c1_set_platdata(NULL);
         s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+        s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
         samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
new file mode 100644
index 00000000000..f6757e02d7d
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+#include <plat/cpu.h>
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/usb-phy.h>
+
+static int s3c_usb_otgphy_init(struct platform_device *pdev)
+{
+        struct clk *xusbxti;
+        u32 phyclk;
+
+        writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+        /* set clock frequency for PLL */
+        phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
+
+        xusbxti = clk_get(&pdev->dev, "xusbxti");
+        if (xusbxti && !IS_ERR(xusbxti)) {
+                switch (clk_get_rate(xusbxti)) {
+                case 12 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_12M;
+                        break;
+                case 24 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_24M;
+                        break;
+                default:
+                case 48 * MHZ:
+                        /* default reference clock */
+                        break;
+                }
+                clk_put(xusbxti);
+        }
+
+        /* TODO: select external clock/oscillator */
+        writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
+
+        /* set to normal OTG PHY */
+        writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
+        mdelay(1);
+
+        /* reset OTG PHY and Link */
+        writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
+                        S3C_RSTCON);
+        udelay(20);     /* at-least 10uS */
+        writel(0, S3C_RSTCON);
+
+        return 0;
+}
+
+static int s3c_usb_otgphy_exit(struct platform_device *pdev)
+{
+        writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
+                                S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
+
+        writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+        return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s3c_usb_otgphy_init(pdev);
+
+        return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s3c_usb_otgphy_exit(pdev);
+
+        return -EINVAL;
+}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index 241d0e645c8..57e718957ef 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -73,7 +73,7 @@ static const u32 clock_table[][3] = {
         {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
 };
 
-unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
+static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
 {
         unsigned long rate = clk_get_rate(clk->parent);
         u32 clkdiv;
@@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
         return rate / (clkdiv + 1);
 }
 
-unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
+                                               unsigned long rate)
 {
         u32 iter;
 
@@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
         return clock_table[ARRAY_SIZE(clock_table) - 1][0];
 }
 
-int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
+static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 round_tmp;
         u32 iter;
@@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-struct clk_ops s5p64x0_clkarm_ops = {
+static struct clk_ops s5p64x0_clkarm_ops = {
         .get_rate       = s5p64x0_armclk_get_rate,
         .set_rate       = s5p64x0_armclk_set_rate,
         .round_rate     = s5p64x0_armclk_round_rate,
@@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = {
         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
 };
 
-struct clk *clkset_hclk_low_list[] = {
+static struct clk *clkset_hclk_low_list[] = {
         &clk_mout_apll.clk,
         &clk_mout_mpll.clk,
 };
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 4325b93940a..6e6a0a9d677 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -147,15 +147,12 @@ static void s5p64x0_idle(void)
 {
         unsigned long val;
 
-        if (!need_resched()) {
-                val = __raw_readl(S5P64X0_PWR_CFG);
-                val &= ~(0x3 << 5);
-                val |= (0x1 << 5);
-                __raw_writel(val, S5P64X0_PWR_CFG);
+        val = __raw_readl(S5P64X0_PWR_CFG);
+        val &= ~(0x3 << 5);
+        val |= (0x1 << 5);
+        __raw_writel(val, S5P64X0_PWR_CFG);
 
-                cpu_do_idle();
-        }
-        local_irq_enable();
+        cpu_do_idle();
 }
 
 /*
@@ -287,7 +284,7 @@ int __init s5p64x0_init(void)
         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 
         /* set idle function */
-        pm_idle = s5p64x0_idle;
+        arm_pm_idle = s5p64x0_idle;
 
         return device_register(&s5p64x0_dev);
 }
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index f820c074440..2ee5dc069b3 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,7 +38,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 s5p6440_pdma_peri[] = {
+static u8 s5p6440_pdma_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -63,12 +63,12 @@ u8 s5p6440_pdma_peri[] = {
         DMACH_SPI1_RX,
 };
 
-struct dma_pl330_platdata s5p6440_pdma_pdata = {
+static struct dma_pl330_platdata s5p6440_pdma_pdata = {
         .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
         .peri_id = s5p6440_pdma_peri,
 };
 
-u8 s5p6450_pdma_peri[] = {
+static u8 s5p6450_pdma_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -103,39 +103,27 @@ u8 s5p6450_pdma_peri[] = {
         DMACH_UART5_TX,
 };
 
-struct dma_pl330_platdata s5p6450_pdma_pdata = {
+static struct dma_pl330_platdata s5p6450_pdma_pdata = {
         .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
         .peri_id = s5p6450_pdma_peri,
 };
 
-struct amba_device s5p64x0_device_pdma = {
-        .dev = {
-                .init_name = "dma-pl330",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-        .res = {
-                .start = S5P64X0_PA_PDMA,
-                .end = S5P64X0_PA_PDMA + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_DMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
+        S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
 
 static int __init s5p64x0_dma_init(void)
 {
         if (soc_is_s5p6450()) {
                 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
                 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
-                s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
+                s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata;
         } else {
                 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
                 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
-                s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
+                s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata;
         }
 
-        amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
+        amba_device_register(&s5p64x0_pdma_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
deleted file mode 100644
index fbb246d0a3d..00000000000
--- a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Low-level IRQ helper macros for the Samsung S5P64X0
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
index ff85b4b6e8d..0ef47d1b767 100644
--- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -22,16 +22,9 @@ extern struct clksrc_clk clk_mout_epll;
 extern int s5p64x0_epll_enable(struct clk *clk, int enable);
 extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
 
-extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
-extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
-extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
-
-extern struct clk_ops s5p64x0_clkarm_ops;
-
 extern struct clksrc_clk clk_armclk;
 extern struct clksrc_clk clk_dout_mpll;
 
-extern struct clk *clkset_hclk_low_list[];
 extern struct clksrc_sources clkset_hclk_low;
 
 extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
diff --git a/arch/arm/mach-s5p64x0/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
deleted file mode 100644
index cf26e0954a2..00000000000
--- a/arch/arm/mach-s5p64x0/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 247194dd366..16eca4ea201 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -170,7 +170,7 @@ static struct clk *clk_src_mout_am_list[] = {
         [1] = &clk_div_apll2.clk,
 };
 
-struct clksrc_sources clk_src_mout_am = {
+static struct clksrc_sources clk_src_mout_am = {
         .sources        = clk_src_mout_am_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mout_am_list),
 };
@@ -212,7 +212,7 @@ static struct clk *clk_src_mout_onenand_list[] = {
         [1] = &clk_div_d1_bus.clk,
 };
 
-struct clksrc_sources clk_src_mout_onenand = {
+static struct clksrc_sources clk_src_mout_onenand = {
         .sources        = clk_src_mout_onenand_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mout_onenand_list),
 };
@@ -756,7 +756,7 @@ static struct clk *clk_src_group1_list[] = {
         [3] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group1 = {
+static struct clksrc_sources clk_src_group1 = {
         .sources        = clk_src_group1_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group1_list),
 };
@@ -766,7 +766,7 @@ static struct clk *clk_src_group2_list[] = {
         [1] = &clk_div_mpll.clk,
 };
 
-struct clksrc_sources clk_src_group2 = {
+static struct clksrc_sources clk_src_group2 = {
         .sources        = clk_src_group2_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group2_list),
 };
@@ -780,7 +780,7 @@ static struct clk *clk_src_group3_list[] = {
         [5] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group3 = {
+static struct clksrc_sources clk_src_group3 = {
         .sources        = clk_src_group3_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
 };
@@ -806,7 +806,7 @@ static struct clk *clk_src_group4_list[] = {
         [5] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group4 = {
+static struct clksrc_sources clk_src_group4 = {
         .sources        = clk_src_group4_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
 };
@@ -831,7 +831,7 @@ static struct clk *clk_src_group5_list[] = {
         [4] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group5 = {
+static struct clksrc_sources clk_src_group5 = {
         .sources        = clk_src_group5_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
 };
@@ -854,7 +854,7 @@ static struct clk *clk_src_group6_list[] = {
         [2] = &clk_div_hdmi.clk,
 };
 
-struct clksrc_sources clk_src_group6 = {
+static struct clksrc_sources clk_src_group6 = {
         .sources        = clk_src_group6_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group6_list),
 };
@@ -866,7 +866,7 @@ static struct clk *clk_src_group7_list[] = {
         [3] = &clk_vclk54m,
 };
 
-struct clksrc_sources clk_src_group7 = {
+static struct clksrc_sources clk_src_group7 = {
         .sources        = clk_src_group7_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group7_list),
 };
@@ -877,7 +877,7 @@ static struct clk *clk_src_mmc0_list[] = {
         [2] = &clk_fin_epll,
 };
 
-struct clksrc_sources clk_src_mmc0 = {
+static struct clksrc_sources clk_src_mmc0 = {
         .sources        = clk_src_mmc0_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mmc0_list),
 };
@@ -889,7 +889,7 @@ static struct clk *clk_src_mmc12_list[] = {
         [3] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_mmc12 = {
+static struct clksrc_sources clk_src_mmc12 = {
         .sources        = clk_src_mmc12_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mmc12_list),
 };
@@ -901,7 +901,7 @@ static struct clk *clk_src_irda_usb_list[] = {
         [3] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_irda_usb = {
+static struct clksrc_sources clk_src_irda_usb = {
         .sources        = clk_src_irda_usb_list,
         .nr_sources     = ARRAY_SIZE(clk_src_irda_usb_list),
 };
@@ -912,7 +912,7 @@ static struct clk *clk_src_pwi_list[] = {
         [2] = &clk_div_mpll.clk,
 };
 
-struct clksrc_sources clk_src_pwi = {
+static struct clksrc_sources clk_src_pwi = {
         .sources        = clk_src_pwi_list,
         .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
 };
@@ -923,7 +923,7 @@ static struct clk *clk_sclk_spdif_list[] = {
         [2] = &clk_sclk_audio2.clk,
 };
 
-struct clksrc_sources clk_src_sclk_spdif = {
+static struct clksrc_sources clk_src_sclk_spdif = {
         .sources        = clk_sclk_spdif_list,
         .nr_sources     = ARRAY_SIZE(clk_sclk_spdif_list),
 };
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index df3a41e8bb0..62190865886 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -130,14 +130,6 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
         }
 };
 
-static void s5pc100_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-
-        local_irq_enable();
-}
-
 /*
  * s5pc100_map_io
  *
@@ -211,10 +203,6 @@ core_initcall(s5pc100_core_init);
 int __init s5pc100_init(void)
 {
         printk(KERN_INFO "S5PC100: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = s5pc100_idle;
-
         return device_register(&s5pc100_dev);
 }
 
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index c841f4d313f..afd8db2d599 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -35,7 +35,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 pdma0_peri[] = {
+static u8 pdma0_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -68,28 +68,15 @@ u8 pdma0_peri[] = {
         DMACH_HSI_TX,
 };
 
-struct dma_pl330_platdata s5pc100_pdma0_pdata = {
+static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
         .peri_id = pdma0_peri,
 };
 
-struct amba_device s5pc100_device_pdma0 = {
-        .dev = {
-                .init_name = "dma-pl330.0",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_pdma0_pdata,
-        },
-        .res = {
-                .start = S5PC100_PA_PDMA0,
-                .end = S5PC100_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pc100_pdma0,  "dma-pl330.0", 0x00041330,
+        S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
 
-u8 pdma1_peri[] = {
+static u8 pdma1_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -122,36 +109,23 @@ u8 pdma1_peri[] = {
         DMACH_MSM_REQ3,
 };
 
-struct dma_pl330_platdata s5pc100_pdma1_pdata = {
+static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
         .peri_id = pdma1_peri,
 };
 
-struct amba_device s5pc100_device_pdma1 = {
-        .dev = {
-                .init_name = "dma-pl330.1",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_pdma1_pdata,
-        },
-        .res = {
-                .start = S5PC100_PA_PDMA1,
-                .end = S5PC100_PA_PDMA1 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA1, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
+        S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
 
 static int __init s5pc100_dma_init(void)
 {
         dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
-        amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
+        amba_device_register(&s5pc100_pdma0_device, &iomem_resource);
 
         dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
-        amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
+        amba_device_register(&s5pc100_pdma1_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index b8c242edfa2..bad0700457d 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -12,14 +12,8 @@
  * warranty of any kind, whether express or implied.
 */
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
deleted file mode 100644
index afc96c29851..00000000000
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/system.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - system implementation
- *
- * Based on mach-s3c6400/include/mach/system.h
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 2cdc42e838b..29594fc4fdf 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -65,6 +65,11 @@ config S5PV210_SETUP_SPI
         help
           Common setup code for SPI GPIO configurations.
 
+config S5PV210_SETUP_USB_PHY
+        bool
+        help
+          Common setup code for USB PHY controller
+
 menu "S5PC110 Machines"
 
 config MACH_AQUILA
@@ -107,6 +112,7 @@ config MACH_GONI
         select S5PV210_SETUP_KEYPAD
         select S5PV210_SETUP_SDHCI
         select S5PV210_SETUP_FIMC
+        select S5PV210_SETUP_USB_PHY
         help
           Machine support for Samsung GONI board
           S5PC110(MCP) is one of package option of S5PV210
@@ -118,6 +124,10 @@ config MACH_SMDKC110
         select S3C_DEV_I2C2
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_MFC
         select SAMSUNG_DEV_IDE
         select S5PV210_SETUP_I2C1
         select S5PV210_SETUP_I2C2
@@ -142,6 +152,11 @@ config MACH_SMDKV210
         select S3C_DEV_I2C2
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_JPEG
+        select S5P_DEV_MFC
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_IDE
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 76a121dd52b..1c4e41998a1 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_S5PV210_SETUP_IDE)		+= setup-ide.o
 obj-$(CONFIG_S5PV210_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_S5PV210_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index b9ec0c35379..09609d50961 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -340,6 +340,11 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1 << 26),
         }, {
+                .name           = "jpeg",
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
                 .name           = "mfc",
                 .devname        = "s5p-mfc",
                 .parent         = &clk_pclk_psys.clk,
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9c1bcdcc12c..4c9e9027df9 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -142,14 +142,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
         }
 };
 
-static void s5pv210_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-
-        local_irq_enable();
-}
-
 void s5pv210_restart(char mode, const char *cmd)
 {
         __raw_writel(0x1, S5P_SWRESET);
@@ -247,10 +239,6 @@ core_initcall(s5pv210_core_init);
 int __init s5pv210_init(void)
 {
         printk(KERN_INFO "S5PV210: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = s5pv210_idle;
-
         return device_register(&s5pv210_dev);
 }
 
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index a6113e0267f..86ce62f6619 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -35,7 +35,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 pdma0_peri[] = {
+static u8 pdma0_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -66,28 +66,15 @@ u8 pdma0_peri[] = {
         DMACH_SPDIF,
 };
 
-struct dma_pl330_platdata s5pv210_pdma0_pdata = {
+static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
         .peri_id = pdma0_peri,
 };
 
-struct amba_device s5pv210_device_pdma0 = {
-        .dev = {
-                .init_name = "dma-pl330.0",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_pdma0_pdata,
-        },
-        .res = {
-                .start = S5PV210_PA_PDMA0,
-                .end = S5PV210_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
+        S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
 
-u8 pdma1_peri[] = {
+static u8 pdma1_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -122,36 +109,23 @@ u8 pdma1_peri[] = {
         DMACH_PCM2_TX,
 };
 
-struct dma_pl330_platdata s5pv210_pdma1_pdata = {
+static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
         .peri_id = pdma1_peri,
 };
 
-struct amba_device s5pv210_device_pdma1 = {
-        .dev = {
-                .init_name = "dma-pl330.1",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_pdma1_pdata,
-        },
-        .res = {
-                .start = S5PV210_PA_PDMA1,
-                .end = S5PV210_PA_PDMA1 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA1, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
+        S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
 
 static int __init s5pv210_dma_init(void)
 {
         dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
-        amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
+        amba_device_register(&s5pv210_pdma0_device, &iomem_resource);
 
         dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
-        amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
+        amba_device_register(&s5pv210_pdma1_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pv210/include/mach/entry-macro.S b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
deleted file mode 100644
index bebca1b5d0b..00000000000
--- a/arch/arm/mach-s5pv210/include/mach/entry-macro.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/entry-macro.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Low-level IRQ helper macros for the Samsung S5PV210
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 89c34b8f73b..b7c8a1917ff 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -90,6 +90,8 @@
 #define S5PV210_PA_FIMC1                0xFB300000
 #define S5PV210_PA_FIMC2                0xFB400000
 
+#define S5PV210_PA_JPEG                 0xFB600000
+
 #define S5PV210_PA_SDO                  0xF9000000
 #define S5PV210_PA_VP                   0xF9100000
 #define S5PV210_PA_MIXER                0xF9200000
@@ -132,6 +134,8 @@
 #define S5P_PA_SYSCON                   S5PV210_PA_SYSCON
 #define S5P_PA_TIMER                    S5PV210_PA_TIMER
 
+#define S5P_PA_JPEG                     S5PV210_PA_JPEG
+
 #define SAMSUNG_PA_ADC                  S5PV210_PA_ADC
 #define SAMSUNG_PA_CFCON                S5PV210_PA_CFCON
 #define SAMSUNG_PA_KEYPAD               S5PV210_PA_KEYPAD
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-sys.h b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
index 26691d39d0f..cccb1eddaa3 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-sys.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
@@ -13,7 +13,3 @@
 #define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
 #define S5PV210_USB_PHY0_EN     (1 << 0)
 #define S5PV210_USB_PHY1_EN     (1 << 1)
-
-/* compatibility defines for s3c-hsotg driver */
-#define S3C64XX_OTHERS          S5PV210_USB_PHY_CON
-#define S3C64XX_OTHERS_USBMASK  S5PV210_USB_PHY0_EN
diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h
deleted file mode 100644
index bf288ced860..00000000000
--- a/arch/arm/mach-s5pv210/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/system.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 5e734d025a6..a9ea64e0da0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -616,6 +616,7 @@ static struct platform_device *aquila_devices[] __initdata = {
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
+        &s5p_device_fimc_md,
         &s5pv210_device_iis0,
         &wm8994_fixed_voltage0,
         &wm8994_fixed_voltage1,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index ff915261043..2cf5ed75f39 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -844,7 +844,7 @@ static struct s5p_fimc_isp_info goni_camera_sensors[] = {
         },
 };
 
-struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
+static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
         .isp_info       = goni_camera_sensors,
         .num_clients    = ARRAY_SIZE(goni_camera_sensors),
 };
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index b323983b2c5..dfc29236321 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -31,6 +31,7 @@
 #include <plat/iic.h>
 #include <plat/pm.h>
 #include <plat/s5p-time.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
@@ -94,6 +95,13 @@ static struct platform_device *smdkc110_devices[] __initdata = {
         &s3c_device_i2c2,
         &s3c_device_rtc,
         &s3c_device_wdt,
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc_md,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
 };
 
 static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
@@ -117,6 +125,11 @@ static void __init smdkc110_map_io(void)
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
+static void __init smdkc110_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init smdkc110_machine_init(void)
 {
         s3c_pm_init();
@@ -145,4 +158,5 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_machine   = smdkc110_machine_init,
         .timer          = &s5p_timer,
         .restart        = s5pv210_restart,
+        .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index dff9ea7b5bb..91d4ad8bcc7 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -46,6 +46,7 @@
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
@@ -140,7 +141,7 @@ static struct dm9000_plat_data smdkv210_dm9000_platdata = {
         .dev_addr       = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
 };
 
-struct platform_device smdkv210_dm9000 = {
+static struct platform_device smdkv210_dm9000 = {
         .name           = "dm9000",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(smdkv210_dm9000_resources),
@@ -223,6 +224,14 @@ static struct platform_device *smdkv210_devices[] __initdata = {
         &s3c_device_rtc,
         &s3c_device_ts,
         &s3c_device_wdt,
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc_md,
+        &s5p_device_jpeg,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
         &s5pv210_device_ac97,
         &s5pv210_device_iis0,
         &s5pv210_device_spdif,
@@ -282,6 +291,11 @@ static void __init smdkv210_map_io(void)
         s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
 }
 
+static void __init smdkv210_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init smdkv210_machine_init(void)
 {
         s3c_pm_init();
@@ -319,4 +333,5 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_machine   = smdkv210_machine_init,
         .timer          = &s5p_timer,
         .restart        = s5pv210_restart,
+        .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
new file mode 100644
index 00000000000..be39cf4aa91
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-usb-phy.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundationr
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+#include <plat/cpu.h>
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/usb-phy.h>
+
+static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
+{
+        struct clk *xusbxti;
+        u32 phyclk;
+
+        writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
+                        S5PV210_USB_PHY_CON);
+
+        /* set clock frequency for PLL */
+        phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
+
+        xusbxti = clk_get(&pdev->dev, "xusbxti");
+        if (xusbxti && !IS_ERR(xusbxti)) {
+                switch (clk_get_rate(xusbxti)) {
+                case 12 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_12M;
+                        break;
+                case 24 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_24M;
+                        break;
+                default:
+                case 48 * MHZ:
+                        /* default reference clock */
+                        break;
+                }
+                clk_put(xusbxti);
+        }
+
+        /* TODO: select external clock/oscillator */
+        writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
+
+        /* set to normal OTG PHY */
+        writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
+        mdelay(1);
+
+        /* reset OTG PHY and Link */
+        writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
+                        S3C_RSTCON);
+        udelay(20);     /* at-least 10uS */
+        writel(0, S3C_RSTCON);
+
+        return 0;
+}
+
+static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
+{
+        writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
+                                S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
+
+        writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
+                        S5PV210_USB_PHY_CON);
+
+        return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s5pv210_usb_otgphy_init(pdev);
+
+        return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s5pv210_usb_otgphy_exit(pdev);
+
+        return -EINVAL;
+}
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index ed7408d3216..60b97ec0167 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o
+obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 0c4b76ab4d8..375d3f779a8 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -15,14 +15,16 @@
 #include <linux/errno.h>
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
+#include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
 
+#include <video/sa1100fb.h>
+
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/pgtable-hwdef.h>
@@ -36,17 +38,18 @@
 #include <asm/mach/serial_sa1100.h>
 #include <mach/assabet.h>
 #include <mach/mcp.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
 #define ASSABET_BCR_DB1110 \
-        (ASSABET_BCR_SPK_OFF    | ASSABET_BCR_QMUTE     | \
+        (ASSABET_BCR_SPK_OFF    | \
          ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
          ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
          ASSABET_BCR_IRDA_MD0)
 
 #define ASSABET_BCR_DB1111 \
-        (ASSABET_BCR_SPK_OFF    | ASSABET_BCR_QMUTE     | \
+        (ASSABET_BCR_SPK_OFF    | \
          ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
          ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
          ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
@@ -69,31 +72,10 @@ void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
 
 EXPORT_SYMBOL(ASSABET_BCR_frob);
 
-static void assabet_backlight_power(int on)
-{
-#ifndef ASSABET_PAL_VIDEO
-        if (on)
-                ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
-        else
-#endif
-                ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
-}
-
-/*
- * Turn on/off the backlight.  When turning the backlight on,
- * we wait 500us after turning it on so we don't cause the
- * supplies to droop when we enable the LCD controller (and
- * cause a hard reset.)
- */
-static void assabet_lcd_power(int on)
+static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
 {
-#ifndef ASSABET_PAL_VIDEO
-        if (on) {
-                ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
-                udelay(500);
-        } else
-#endif
-                ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
+        if (state == UCB_RST_PROBE)
+                ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
 }
 
 
@@ -152,15 +134,8 @@ static struct flash_platform_data assabet_flash_data = {
 };
 
 static struct resource assabet_flash_resources[] = {
-        {
-                .start  = SA1100_CS0_PHYS,
-                .end    = SA1100_CS0_PHYS + SZ_32M - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = SA1100_CS1_PHYS,
-                .end    = SA1100_CS1_PHYS + SZ_32M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
+        DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
 };
 
 
@@ -199,18 +174,126 @@ static struct irda_platform_data assabet_irda_data = {
         .set_speed      = assabet_irda_set_speed,
 };
 
+static struct ucb1x00_plat_data assabet_ucb1x00_data = {
+        .reset          = assabet_ucb1x00_reset,
+        .gpio_base      = -1,
+};
+
 static struct mcp_plat_data assabet_mcp_data = {
         .mccr0          = MCCR0_ADM,
         .sclk_rate      = 11981000,
+        .codec_pdata    = &assabet_ucb1x00_data,
+};
+
+static void assabet_lcd_set_visual(u32 visual)
+{
+        u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
+
+        if (machine_is_assabet()) {
+#if 1           // phase 4 or newer Assabet's
+                if (is_true_color)
+                        ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
+                else
+                        ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
+#else
+                // older Assabet's
+                if (is_true_color)
+                        ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
+                else
+                        ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
+#endif
+        }
+}
+
+#ifndef ASSABET_PAL_VIDEO
+static void assabet_lcd_backlight_power(int on)
+{
+        if (on)
+                ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
+        else
+                ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
+}
+
+/*
+ * Turn on/off the backlight.  When turning the backlight on, we wait
+ * 500us after turning it on so we don't cause the supplies to droop
+ * when we enable the LCD controller (and cause a hard reset.)
+ */
+static void assabet_lcd_power(int on)
+{
+        if (on) {
+                ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
+                udelay(500);
+        } else
+                ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
+}
+
+/*
+ * The assabet uses a sharp LQ039Q2DS54 LCD module.  It is actually
+ * takes an RGB666 signal, but we provide it with an RGB565 signal
+ * instead (def_rgb_16).
+ */
+static struct sa1100fb_mach_info lq039q2ds54_info = {
+        .pixclock       = 171521,       .bpp            = 16,
+        .xres           = 320,          .yres           = 240,
+
+        .hsync_len      = 5,            .vsync_len      = 1,
+        .left_margin    = 61,           .upper_margin   = 3,
+        .right_margin   = 9,            .lower_margin   = 0,
+
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
+
+        .backlight_power = assabet_lcd_backlight_power,
+        .lcd_power = assabet_lcd_power,
+        .set_visual = assabet_lcd_set_visual,
+};
+#else
+static void assabet_pal_backlight_power(int on)
+{
+        ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
+}
+
+static void assabet_pal_power(int on)
+{
+        ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
+}
+
+static struct sa1100fb_mach_info pal_info = {
+        .pixclock       = 67797,        .bpp            = 16,
+        .xres           = 640,          .yres           = 512,
+
+        .hsync_len      = 64,           .vsync_len      = 6,
+        .left_margin    = 125,          .upper_margin   = 70,
+        .right_margin   = 115,          .lower_margin   = 36,
+
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
+
+        .backlight_power = assabet_pal_backlight_power,
+        .lcd_power = assabet_pal_power,
+        .set_visual = assabet_lcd_set_visual,
 };
+#endif
+
+#ifdef CONFIG_ASSABET_NEPONSET
+static struct resource neponset_resources[] = {
+        DEFINE_RES_MEM(0x10000000, 0x08000000),
+        DEFINE_RES_MEM(0x18000000, 0x04000000),
+        DEFINE_RES_MEM(0x40000000, SZ_8K),
+        DEFINE_RES_IRQ(IRQ_GPIO25),
+};
+#endif
 
 static void __init assabet_init(void)
 {
         /*
          * Ensure that the power supply is in "high power" mode.
          */
-        GPDR |= GPIO_GPIO16;
         GPSR = GPIO_GPIO16;
+        GPDR |= GPIO_GPIO16;
 
         /*
          * Ensure that these pins are set as outputs and are driving
@@ -218,8 +301,16 @@ static void __init assabet_init(void)
          * the WS latch in the CPLD, and we don't float causing
          * excessive power drain.  --rmk
          */
-        GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
         GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
+        GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
+
+        /*
+         * Also set GPIO27 as an output; this is used to clock UART3
+         * via the FPGA and as otherwise has no pullups or pulldowns,
+         * so stop it floating.
+         */
+        GPCR = GPIO_GPIO27;
+        GPDR |= GPIO_GPIO27;
 
         /*
          * Set up registers for sleep mode.
@@ -231,8 +322,7 @@ static void __init assabet_init(void)
         PPDR |= PPC_TXD3 | PPC_TXD1;
         PPSR |= PPC_TXD3 | PPC_TXD1;
 
-        sa1100fb_lcd_power = assabet_lcd_power;
-        sa1100fb_backlight_power = assabet_backlight_power;
+        sa11x0_ppc_configure_mcp();
 
         if (machine_has_neponset()) {
                 /*
@@ -246,9 +336,17 @@ static void __init assabet_init(void)
 #ifndef CONFIG_ASSABET_NEPONSET
                 printk( "Warning: Neponset detected but full support "
                         "hasn't been configured in the kernel\n" );
+#else
+                platform_device_register_simple("neponset", 0,
+                        neponset_resources, ARRAY_SIZE(neponset_resources));
 #endif
         }
 
+#ifndef ASSABET_PAL_VIDEO
+        sa11x0_register_lcd(&lq039q2ds54_info);
+#else
+        sa11x0_register_lcd(&pal_video);
+#endif
         sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
                             ARRAY_SIZE(assabet_flash_resources));
         sa11x0_register_irda(&assabet_irda_data);
@@ -412,21 +510,8 @@ static void __init assabet_map_io(void)
          */
         Ser1SDCR0 |= SDCR0_SUS;
 
-        if (machine_has_neponset()) {
-#ifdef CONFIG_ASSABET_NEPONSET
-                extern void neponset_map_io(void);
-
-                /*
-                 * We map Neponset registers even if it isn't present since
-                 * many drivers will try to probe their stuff (and fail).
-                 * This is still more friendly than a kernel paging request
-                 * crash.
-                 */
-                neponset_map_io();
-#endif
-        } else {
+        if (!machine_has_neponset())
                 sa1100_register_uart_fns(&assabet_port_fns);
-        }
 
         /*
          * When Neponset is attached, the first UART should be
@@ -449,6 +534,7 @@ MACHINE_START(ASSABET, "Intel-Assabet")
         .atag_offset    = 0x100,
         .fixup          = fixup_assabet,
         .map_io         = assabet_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = assabet_init,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b07a2c024cb..e0f0c030258 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -39,20 +39,27 @@
 #include "generic.h"
 
 static struct resource sa1111_resources[] = {
-        [0] = {
-                .start          = BADGE4_SA1111_BASE,
-                .end            = BADGE4_SA1111_BASE + 0x00001fff,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = BADGE4_IRQ_GPIO_SA1111,
-                .end            = BADGE4_IRQ_GPIO_SA1111,
-                .flags          = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(BADGE4_SA1111_BASE, 0x2000),
+        [1] = DEFINE_RES_IRQ(BADGE4_IRQ_GPIO_SA1111),
 };
 
+static int badge4_sa1111_enable(void *data, unsigned devid)
+{
+        if (devid == SA1111_DEVID_USB)
+                badge4_set_5V(BADGE4_5V_USB, 1);
+        return 0;
+}
+
+static void badge4_sa1111_disable(void *data, unsigned devid)
+{
+        if (devid == SA1111_DEVID_USB)
+                badge4_set_5V(BADGE4_5V_USB, 0);
+}
+
 static struct sa1111_platform_data sa1111_info = {
-        .irq_base       = IRQ_BOARD_END,
+        .disable_devs   = SA1111_DEVID_PS2_MSE,
+        .enable         = badge4_sa1111_enable,
+        .disable        = badge4_sa1111_disable,
 };
 
 static u64 sa1111_dmamask = 0xffffffffUL;
@@ -121,11 +128,8 @@ static struct flash_platform_data badge4_flash_data = {
         .nr_parts       = ARRAY_SIZE(badge4_partitions),
 };
 
-static struct resource badge4_flash_resource = {
-        .start          = SA1100_CS0_PHYS,
-        .end            = SA1100_CS0_PHYS + SZ_64M - 1,
-        .flags          = IORESOURCE_MEM,
-};
+static struct resource badge4_flash_resource =
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_64M);
 
 static int five_v_on __initdata = 0;
 
@@ -269,11 +273,6 @@ static struct map_desc badge4_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(0x10000000),
                 .length         = 0x00100000,
                 .type           = MT_DEVICE
-        }, {    /* SA-1111      */
-                .virtual        = 0xf4000000,
-                .pfn            = __phys_to_pfn(0x48000000),
-                .length         = 0x00100000,
-                .type           = MT_DEVICE
         }
 };
 
@@ -304,6 +303,7 @@ static void __init badge4_map_io(void)
 MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
         .atag_offset    = 0x100,
         .map_io         = badge4_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
 #ifdef CONFIG_SA1111
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 11bb6d0b9be..4a61f60e050 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -18,7 +18,6 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 
-#include <asm/irq.h>
 #include <mach/hardware.h>
 #include <asm/setup.h>
 
@@ -30,14 +29,11 @@
 
 #include <mach/cerf.h>
 #include <mach/mcp.h>
+#include <mach/irqs.h>
 #include "generic.h"
 
 static struct resource cerfuart2_resources[] = {
-        [0] = {
-                .start  = 0x80030000,
-                .end    = 0x8003ffff,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM(0x80030000, SZ_64K),
 };
 
 static struct platform_device cerfuart2_device = {
@@ -87,11 +83,8 @@ static struct flash_platform_data cerf_flash_data = {
         .nr_parts       = ARRAY_SIZE(cerf_partitions),
 };
 
-static struct resource cerf_flash_resource = {
-        .start          = SA1100_CS0_PHYS,
-        .end            = SA1100_CS0_PHYS + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
+static struct resource cerf_flash_resource =
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
 
 static void __init cerf_init_irq(void)
 {
@@ -128,6 +121,7 @@ static struct mcp_plat_data cerf_mcp_data = {
 
 static void __init cerf_init(void)
 {
+        sa11x0_ppc_configure_mcp();
         platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
         sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
         sa11x0_register_mcp(&cerf_mcp_data);
@@ -136,6 +130,7 @@ static void __init cerf_init(void)
 MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
         /* Maintainer: support@intrinsyc.com */
         .map_io         = cerf_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = cerf_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = cerf_init,
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index dab3c6347a8..172ebd0ee0a 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,17 +11,29 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/mutex.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 
 #include <mach/hardware.h>
 
-/*
- * Very simple clock implementation - we only have one clock to deal with.
- */
+struct clkops {
+        void                    (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+};
+
 struct clk {
+        const struct clkops     *ops;
         unsigned int            enabled;
 };
 
-static void clk_gpio27_enable(void)
+#define DEFINE_CLK(_name, _ops)                         \
+struct clk clk_##_name = {                              \
+                .ops    = _ops,                         \
+        }
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+static void clk_gpio27_enable(struct clk *clk)
 {
         /*
          * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -32,38 +44,24 @@ static void clk_gpio27_enable(void)
         TUCR = TUCR_3_6864MHz;
 }
 
-static void clk_gpio27_disable(void)
+static void clk_gpio27_disable(struct clk *clk)
 {
         TUCR = 0;
         GPDR &= ~GPIO_32_768kHz;
         GAFR &= ~GPIO_32_768kHz;
 }
 
-static struct clk clk_gpio27;
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        const char *devname = dev_name(dev);
-
-        return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (clk->enabled++ == 0)
-                clk_gpio27_enable();
-        spin_unlock_irqrestore(&clocks_lock, flags);
+        if (clk) {
+                spin_lock_irqsave(&clocks_lock, flags);
+                if (clk->enabled++ == 0)
+                        clk->ops->enable(clk);
+                spin_unlock_irqrestore(&clocks_lock, flags);
+        }
+
         return 0;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -72,17 +70,31 @@ void clk_disable(struct clk *clk)
 {
         unsigned long flags;
 
-        WARN_ON(clk->enabled == 0);
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (--clk->enabled == 0)
-                clk_gpio27_disable();
-        spin_unlock_irqrestore(&clocks_lock, flags);
+        if (clk) {
+                WARN_ON(clk->enabled == 0);
+                spin_lock_irqsave(&clocks_lock, flags);
+                if (--clk->enabled == 0)
+                        clk->ops->disable(clk);
+                spin_unlock_irqrestore(&clocks_lock, flags);
+        }
 }
 EXPORT_SYMBOL(clk_disable);
 
-unsigned long clk_get_rate(struct clk *clk)
+const struct clkops clk_gpio27_ops = {
+        .enable         = clk_gpio27_enable,
+        .disable        = clk_gpio27_disable,
+};
+
+static DEFINE_CLK(gpio27, &clk_gpio27_ops);
+
+static struct clk_lookup sa11xx_clkregs[] = {
+        CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
+        CLKDEV_INIT("sa1100-rtc", NULL, NULL),
+};
+
+static int __init sa11xx_clk_init(void)
 {
-        return 3686400;
+        clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
+        return 0;
 }
-EXPORT_SYMBOL(clk_get_rate);
+core_initcall(sa11xx_clk_init);
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index fd5652118ed..48885b7efd6 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -22,15 +22,17 @@
 #include <linux/tty.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/timer.h>
 #include <linux/gpio.h>
 #include <linux/pda_power.h>
 
+#include <video/sa1100fb.h>
+
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/irq.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <mach/collie.h>
@@ -44,15 +46,12 @@
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/locomo.h>
 #include <mach/mcp.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
 static struct resource collie_scoop_resources[] = {
-        [0] = {
-                .start          = 0x40800000,
-                .end            = 0x40800fff,
-                .flags          = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM(0x40800000, SZ_4K),
 };
 
 static struct scoop_config collie_scoop_setup = {
@@ -85,10 +84,14 @@ static struct scoop_pcmcia_config collie_pcmcia_config = {
         .num_devs       = 1,
 };
 
+static struct ucb1x00_plat_data collie_ucb1x00_data = {
+        .gpio_base      = COLLIE_TC35143_GPIO_BASE,
+};
+
 static struct mcp_plat_data collie_mcp_data = {
         .mccr0          = MCCR0_ADM | MCCR0_ExtClk,
         .sclk_rate      = 9216000,
-        .gpio_base      = COLLIE_TC35143_GPIO_BASE,
+        .codec_pdata    = &collie_ucb1x00_data,
 };
 
 /*
@@ -221,16 +224,8 @@ device_initcall(collie_uart_init);
 
 
 static struct resource locomo_resources[] = {
-        [0] = {
-                .start          = 0x40000000,
-                .end            = 0x40001fff,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = IRQ_GPIO25,
-                .end            = IRQ_GPIO25,
-                .flags          = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(0x40000000, SZ_8K),
+        [1] = DEFINE_RES_IRQ(IRQ_GPIO25),
 };
 
 static struct locomo_platform_data locomo_info = {
@@ -303,11 +298,21 @@ static struct flash_platform_data collie_flash_data = {
 };
 
 static struct resource collie_flash_resources[] = {
-        {
-                .start  = SA1100_CS0_PHYS,
-                .end    = SA1100_CS0_PHYS + SZ_32M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
+};
+
+static struct sa1100fb_mach_info collie_lcd_info = {
+        .pixclock       = 171521,       .bpp            = 16,
+        .xres           = 320,          .yres           = 240,
+
+        .hsync_len      = 5,            .vsync_len      = 1,
+        .left_margin    = 11,           .upper_margin   = 2,
+        .right_margin   = 30,           .lower_margin   = 0,
+
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
 };
 
 static void __init collie_init(void)
@@ -341,6 +346,10 @@ static void __init collie_init(void)
 
         collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
         collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
+
+        sa11x0_ppc_configure_mcp();
+
+
         platform_scoop_config = &collie_pcmcia_config;
 
         ret = platform_add_devices(devices, ARRAY_SIZE(devices));
@@ -348,6 +357,7 @@ static void __init collie_init(void)
                 printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
         }
 
+        sa11x0_register_lcd(&collie_lcd_info);
         sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
                             ARRAY_SIZE(collie_flash_resources));
         sa11x0_register_mcp(&collie_mcp_data);
@@ -383,6 +393,7 @@ static void __init collie_map_io(void)
 
 MACHINE_START(COLLIE, "Sharp-Collie")
         .map_io         = collie_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = collie_init,
diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c
deleted file mode 100644
index 56e13333512..00000000000
--- a/arch/arm/mach-sa1100/dma.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * arch/arm/mach-sa1100/dma.c
- *
- * Support functions for the SA11x0 internal DMA channels.
- *
- * Copyright (C) 2000, 2001 by Nicolas Pitre
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma.h>
-
-
-#undef DEBUG
-#ifdef DEBUG
-#define DPRINTK( s, arg... )  printk( "dma<%p>: " s, regs , ##arg )
-#else
-#define DPRINTK( x... )
-#endif
-
-
-typedef struct {
-        const char *device_id;          /* device name */
-        u_long device;                  /* this channel device, 0  if unused*/
-        dma_callback_t callback;        /* to call when DMA completes */
-        void *data;                     /* ... with private data ptr */
-} sa1100_dma_t;
-
-static sa1100_dma_t dma_chan[SA1100_DMA_CHANNELS];
-
-static DEFINE_SPINLOCK(dma_list_lock);
-
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-        dma_regs_t *dma_regs = dev_id;
-        sa1100_dma_t *dma = dma_chan + (((u_int)dma_regs >> 5) & 7);
-        int status = dma_regs->RdDCSR;
-
-        if (status & (DCSR_ERROR)) {
-                printk(KERN_CRIT "DMA on \"%s\" caused an error\n", dma->device_id);
-                dma_regs->ClrDCSR = DCSR_ERROR;
-        }
-
-        dma_regs->ClrDCSR = status & (DCSR_DONEA | DCSR_DONEB);
-        if (dma->callback) {
-                if (status & DCSR_DONEA)
-                        dma->callback(dma->data);
-                if (status & DCSR_DONEB)
-                        dma->callback(dma->data);
-        }
-        return IRQ_HANDLED;
-}
-
-
-/**
- *      sa1100_request_dma - allocate one of the SA11x0's DMA channels
- *      @device: The SA11x0 peripheral targeted by this request
- *      @device_id: An ascii name for the claiming device
- *      @callback: Function to be called when the DMA completes
- *      @data: A cookie passed back to the callback function
- *      @dma_regs: Pointer to the location of the allocated channel's identifier
- *
- *      This function will search for a free DMA channel and returns the
- *      address of the hardware registers for that channel as the channel
- *      identifier. This identifier is written to the location pointed by
- *      @dma_regs. The list of possible values for @device are listed into
- *      arch/arm/mach-sa1100/include/mach/dma.h as a dma_device_t enum.
- *
- *      Note that reading from a port and writing to the same port are
- *      actually considered as two different streams requiring separate
- *      DMA registrations.
- *
- *      The @callback function is called from interrupt context when one
- *      of the two possible DMA buffers in flight has terminated. That
- *      function has to be small and efficient while posponing more complex
- *      processing to a lower priority execution context.
- *
- *      If no channels are available, or if the desired @device is already in
- *      use by another DMA channel, then an error code is returned.  This
- *      function must be called before any other DMA calls.
- **/
-
-int sa1100_request_dma (dma_device_t device, const char *device_id,
-                        dma_callback_t callback, void *data,
-                        dma_regs_t **dma_regs)
-{
-        sa1100_dma_t *dma = NULL;
-        dma_regs_t *regs;
-        int i, err;
-
-        *dma_regs = NULL;
-
-        err = 0;
-        spin_lock(&dma_list_lock);
-        for (i = 0; i < SA1100_DMA_CHANNELS; i++) {
-                if (dma_chan[i].device == device) {
-                        err = -EBUSY;
-                        break;
-                } else if (!dma_chan[i].device && !dma) {
-                        dma = &dma_chan[i];
-                }
-        }
-        if (!err) {
-                if (dma)
-                        dma->device = device;
-                else
-                        err = -ENOSR;
-        }
-        spin_unlock(&dma_list_lock);
-        if (err)
-                return err;
-
-        i = dma - dma_chan;
-        regs = (dma_regs_t *)&DDAR(i);
-        err = request_irq(IRQ_DMA0 + i, dma_irq_handler, IRQF_DISABLED,
-                          device_id, regs);
-        if (err) {
-                printk(KERN_ERR
-                       "%s: unable to request IRQ %d for %s\n",
-                       __func__, IRQ_DMA0 + i, device_id);
-                dma->device = 0;
-                return err;
-        }
-
-        *dma_regs = regs;
-        dma->device_id = device_id;
-        dma->callback = callback;
-        dma->data = data;
-
-        regs->ClrDCSR =
-                (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
-                 DCSR_IE | DCSR_ERROR | DCSR_RUN);
-        regs->DDAR = device;
-
-        return 0;
-}
-
-
-/**
- *      sa1100_free_dma - free a SA11x0 DMA channel
- *      @regs: identifier for the channel to free
- *
- *      This clears all activities on a given DMA channel and releases it
- *      for future requests.  The @regs identifier is provided by a
- *      successful call to sa1100_request_dma().
- **/
-
-void sa1100_free_dma(dma_regs_t *regs)
-{
-        int i;
-
-        for (i = 0; i < SA1100_DMA_CHANNELS; i++)
-                if (regs == (dma_regs_t *)&DDAR(i))
-                        break;
-        if (i >= SA1100_DMA_CHANNELS) {
-                printk(KERN_ERR "%s: bad DMA identifier\n", __func__);
-                return;
-        }
-
-        if (!dma_chan[i].device) {
-                printk(KERN_ERR "%s: Trying to free free DMA\n", __func__);
-                return;
-        }
-
-        regs->ClrDCSR =
-                (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
-                 DCSR_IE | DCSR_ERROR | DCSR_RUN);
-        free_irq(IRQ_DMA0 + i, regs);
-        dma_chan[i].device = 0;
-}
-
-
-/**
- *      sa1100_start_dma - submit a data buffer for DMA
- *      @regs: identifier for the channel to use
- *      @dma_ptr: buffer physical (or bus) start address
- *      @size: buffer size
- *
- *      This function hands the given data buffer to the hardware for DMA
- *      access. If another buffer is already in flight then this buffer
- *      will be queued so the DMA engine will switch to it automatically
- *      when the previous one is done.  The DMA engine is actually toggling
- *      between two buffers so at most 2 successful calls can be made before
- *      one of them terminates and the callback function is called.
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- *
- *      The @size must not be larger than %MAX_DMA_SIZE.  If a given buffer
- *      is larger than that then it's the caller's responsibility to split
- *      it into smaller chunks and submit them separately. If this is the
- *      case then a @size of %CUT_DMA_SIZE is recommended to avoid ending
- *      up with too small chunks. The callback function can be used to chain
- *      submissions of buffer chunks.
- *
- *      Error return values:
- *      %-EOVERFLOW:    Given buffer size is too big.
- *      %-EBUSY:        Both DMA buffers are already in use.
- *      %-EAGAIN:       Both buffers were busy but one of them just completed
- *                      but the interrupt handler has to execute first.
- *
- *      This function returs 0 on success.
- **/
-
-int sa1100_start_dma(dma_regs_t *regs, dma_addr_t dma_ptr, u_int size)
-{
-        unsigned long flags;
-        u_long status;
-        int ret;
-
-        if (dma_ptr & 3)
-                printk(KERN_WARNING "DMA: unaligned start address (0x%08lx)\n",
-                       (unsigned long)dma_ptr);
-
-        if (size > MAX_DMA_SIZE)
-                return -EOVERFLOW;
-
-        local_irq_save(flags);
-        status = regs->RdDCSR;
-
-        /* If both DMA buffers are started, there's nothing else we can do. */
-        if ((status & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB)) {
-                DPRINTK("start: st %#x busy\n", status);
-                ret = -EBUSY;
-                goto out;
-        }
-
-        if (((status & DCSR_BIU) && (status & DCSR_STRTB)) ||
-            (!(status & DCSR_BIU) && !(status & DCSR_STRTA))) {
-                if (status & DCSR_DONEA) {
-                        /* give a chance for the interrupt to be processed */
-                        ret = -EAGAIN;
-                        goto out;
-                }
-                regs->DBSA = dma_ptr;
-                regs->DBTA = size;
-                regs->SetDCSR = DCSR_STRTA | DCSR_IE | DCSR_RUN;
-                DPRINTK("start a=%#x s=%d on A\n", dma_ptr, size);
-        } else {
-                if (status & DCSR_DONEB) {
-                        /* give a chance for the interrupt to be processed */
-                        ret = -EAGAIN;
-                        goto out;
-                }
-                regs->DBSB = dma_ptr;
-                regs->DBTB = size;
-                regs->SetDCSR = DCSR_STRTB | DCSR_IE | DCSR_RUN;
-                DPRINTK("start a=%#x s=%d on B\n", dma_ptr, size);
-        }
-        ret = 0;
-
-out:
-        local_irq_restore(flags);
-        return ret;
-}
-
-
-/**
- *      sa1100_get_dma_pos - return current DMA position
- *      @regs: identifier for the channel to use
- *
- *      This function returns the current physical (or bus) address for the
- *      given DMA channel.  If the channel is running i.e. not in a stopped
- *      state then the caller must disable interrupts prior calling this
- *      function and process the returned value before re-enabling them to
- *      prevent races with the completion interrupt handler and the callback
- *      function. The validation of the returned value is the caller's
- *      responsibility as well -- the hardware seems to return out of range
- *      values when the DMA engine completes a buffer.
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs)
-{
-        int status;
-
-        /*
-         * We must determine whether buffer A or B is active.
-         * Two possibilities: either we are in the middle of
-         * a buffer, or the DMA controller just switched to the
-         * next toggle but the interrupt hasn't been serviced yet.
-         * The former case is straight forward.  In the later case,
-         * we'll do like if DMA is just at the end of the previous
-         * toggle since all registers haven't been reset yet.
-         * This goes around the edge case and since we're always
-         * a little behind anyways it shouldn't make a big difference.
-         * If DMA has been stopped prior calling this then the
-         * position is exact.
-         */
-        status = regs->RdDCSR;
-        if ((!(status & DCSR_BIU) &&  (status & DCSR_STRTA)) ||
-            ( (status & DCSR_BIU) && !(status & DCSR_STRTB)))
-                return regs->DBSA;
-        else
-                return regs->DBSB;
-}
-
-
-/**
- *      sa1100_reset_dma - reset a DMA channel
- *      @regs: identifier for the channel to use
- *
- *      This function resets and reconfigure the given DMA channel. This is
- *      particularly useful after a sleep/wakeup event.
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-void sa1100_reset_dma(dma_regs_t *regs)
-{
-        int i;
-
-        for (i = 0; i < SA1100_DMA_CHANNELS; i++)
-                if (regs == (dma_regs_t *)&DDAR(i))
-                        break;
-        if (i >= SA1100_DMA_CHANNELS) {
-                printk(KERN_ERR "%s: bad DMA identifier\n", __func__);
-                return;
-        }
-
-        regs->ClrDCSR =
-                (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
-                 DCSR_IE | DCSR_ERROR | DCSR_RUN);
-        regs->DDAR = dma_chan[i].device;
-}
-
-
-EXPORT_SYMBOL(sa1100_request_dma);
-EXPORT_SYMBOL(sa1100_free_dma);
-EXPORT_SYMBOL(sa1100_start_dma);
-EXPORT_SYMBOL(sa1100_get_dma_pos);
-EXPORT_SYMBOL(sa1100_reset_dma);
-
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9ad94691743..7c524b4e415 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -14,18 +14,23 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/pm.h>
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
 
+#include <video/sa1100fb.h>
+
 #include <asm/div64.h>
-#include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
 #include "generic.h"
 
 unsigned int reset_status;
@@ -149,16 +154,8 @@ static void sa11x0_register_device(struct platform_device *dev, void *data)
 
 
 static struct resource sa11x0udc_resources[] = {
-        [0] = {
-                .start  = __PREG(Ser0UDCCR),
-                .end    = __PREG(Ser0UDCCR) + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_Ser0UDC,
-                .end    = IRQ_Ser0UDC,
-                .flags  = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
+        [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
 };
 
 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
@@ -175,16 +172,8 @@ static struct platform_device sa11x0udc_device = {
 };
 
 static struct resource sa11x0uart1_resources[] = {
-        [0] = {
-                .start  = __PREG(Ser1UTCR0),
-                .end    = __PREG(Ser1UTCR0) + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_Ser1UART,
-                .end    = IRQ_Ser1UART,
-                .flags  = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
+        [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
 };
 
 static struct platform_device sa11x0uart1_device = {
@@ -195,16 +184,8 @@ static struct platform_device sa11x0uart1_device = {
 };
 
 static struct resource sa11x0uart3_resources[] = {
-        [0] = {
-                .start  = __PREG(Ser3UTCR0),
-                .end    = __PREG(Ser3UTCR0) + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_Ser3UART,
-                .end    = IRQ_Ser3UART,
-                .flags  = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
+        [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
 };
 
 static struct platform_device sa11x0uart3_device = {
@@ -215,16 +196,9 @@ static struct platform_device sa11x0uart3_device = {
 };
 
 static struct resource sa11x0mcp_resources[] = {
-        [0] = {
-                .start  = __PREG(Ser4MCCR0),
-                .end    = __PREG(Ser4MCCR0) + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_Ser4MCP,
-                .end    = IRQ_Ser4MCP,
-                .flags  = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
+        [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
+        [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
 };
 
 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
@@ -240,22 +214,24 @@ static struct platform_device sa11x0mcp_device = {
         .resource       = sa11x0mcp_resources,
 };
 
+void __init sa11x0_ppc_configure_mcp(void)
+{
+        /* Setup the PPC unit for the MCP */
+        PPDR &= ~PPC_RXD4;
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PSDR |= PPC_RXD4;
+        PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+}
+
 void sa11x0_register_mcp(struct mcp_plat_data *data)
 {
         sa11x0_register_device(&sa11x0mcp_device, data);
 }
 
 static struct resource sa11x0ssp_resources[] = {
-        [0] = {
-                .start  = 0x80070000,
-                .end    = 0x8007ffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_Ser4SSP,
-                .end    = IRQ_Ser4SSP,
-                .flags  = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
+        [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
 };
 
 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
@@ -272,16 +248,8 @@ static struct platform_device sa11x0ssp_device = {
 };
 
 static struct resource sa11x0fb_resources[] = {
-        [0] = {
-                .start  = 0xb0100000,
-                .end    = 0xb010ffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_LCD,
-                .end    = IRQ_LCD,
-                .flags  = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
+        [1] = DEFINE_RES_IRQ(IRQ_LCD),
 };
 
 static struct platform_device sa11x0fb_device = {
@@ -294,6 +262,11 @@ static struct platform_device sa11x0fb_device = {
         .resource       = sa11x0fb_resources,
 };
 
+void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
+{
+        sa11x0_register_device(&sa11x0fb_device, inf);
+}
+
 static struct platform_device sa11x0pcmcia_device = {
         .name           = "sa11x0-pcmcia",
         .id             = -1,
@@ -314,23 +287,10 @@ void sa11x0_register_mtd(struct flash_platform_data *flash,
 }
 
 static struct resource sa11x0ir_resources[] = {
-        {
-                .start  = __PREG(Ser2UTCR0),
-                .end    = __PREG(Ser2UTCR0) + 0x24 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = __PREG(Ser2HSCR0),
-                .end    = __PREG(Ser2HSCR0) + 0x1c - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = __PREG(Ser2HSCR2),
-                .end    = __PREG(Ser2HSCR2) + 0x04 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_Ser2ICP,
-                .end    = IRQ_Ser2ICP,
-                .flags  = IORESOURCE_IRQ,
-        }
+        DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
+        DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
+        DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
+        DEFINE_RES_IRQ(IRQ_Ser2ICP),
 };
 
 static struct platform_device sa11x0ir_device = {
@@ -345,9 +305,40 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
         sa11x0_register_device(&sa11x0ir_device, irda);
 }
 
+static struct resource sa1100_rtc_resources[] = {
+        DEFINE_RES_MEM(0x90010000, 0x9001003f),
+        DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
+        DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
+};
+
 static struct platform_device sa11x0rtc_device = {
         .name           = "sa1100-rtc",
         .id             = -1,
+        .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
+        .resource       = sa1100_rtc_resources,
+};
+
+static struct resource sa11x0dma_resources[] = {
+        DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
+        DEFINE_RES_IRQ(IRQ_DMA0),
+        DEFINE_RES_IRQ(IRQ_DMA1),
+        DEFINE_RES_IRQ(IRQ_DMA2),
+        DEFINE_RES_IRQ(IRQ_DMA3),
+        DEFINE_RES_IRQ(IRQ_DMA4),
+        DEFINE_RES_IRQ(IRQ_DMA5),
+};
+
+static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device sa11x0dma_device = {
+        .name           = "sa11x0-dma",
+        .id             = -1,
+        .dev = {
+                .dma_mask = &sa11x0dma_dma_mask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(sa11x0dma_resources),
+        .resource       = sa11x0dma_resources,
 };
 
 static struct platform_device *sa11x0_devices[] __initdata = {
@@ -356,8 +347,8 @@ static struct platform_device *sa11x0_devices[] __initdata = {
         &sa11x0uart3_device,
         &sa11x0ssp_device,
         &sa11x0pcmcia_device,
-        &sa11x0fb_device,
         &sa11x0rtc_device,
+        &sa11x0dma_device,
 };
 
 static int __init sa1100_init(void)
@@ -368,12 +359,6 @@ static int __init sa1100_init(void)
 
 arch_initcall(sa1100_init);
 
-void (*sa1100fb_backlight_power)(int on);
-void (*sa1100fb_lcd_power)(int on);
-
-EXPORT_SYMBOL(sa1100fb_backlight_power);
-EXPORT_SYMBOL(sa1100fb_lcd_power);
-
 
 /*
  * Common I/O mapping:
@@ -428,7 +413,7 @@ void __init sa1100_map_io(void)
  * the MBGNT signal false to ensure the SA1111 doesn't own the
  * SDRAM bus.
  */
-void __init sa1110_mb_disable(void)
+void sa1110_mb_disable(void)
 {
         unsigned long flags;
 
@@ -447,7 +432,7 @@ void __init sa1110_mb_disable(void)
  * If the system is going to use the SA-1111 DMA engines, set up
  * the memory bus request/grant pins.
  */
-void __devinit sa1110_mb_enable(void)
+void sa1110_mb_enable(void)
 {
         unsigned long flags;
 
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 33268cf6be3..9eb3b3cd5a6 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -16,9 +16,6 @@ extern void sa11x0_restart(char, const char *);
         mi->bank[__nr].start = (__start), \
         mi->bank[__nr].size = (__size)
 
-extern void (*sa1100fb_backlight_power)(int on);
-extern void (*sa1100fb_lcd_power)(int on);
-
 extern void sa1110_mb_enable(void);
 extern void sa1110_mb_disable(void);
 
@@ -39,4 +36,8 @@ struct irda_platform_data;
 void sa11x0_register_irda(struct irda_platform_data *irda);
 
 struct mcp_plat_data;
+void sa11x0_ppc_configure_mcp(void);
 void sa11x0_register_mcp(struct mcp_plat_data *data);
+
+struct sa1100fb_mach_info;
+void sa11x0_register_lcd(struct sa1100fb_mach_info *inf);
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index 1e6b3c105ba..b2e8d0f418e 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -14,11 +14,14 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 
+#include <video/sa1100fb.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irda.h>
 
 #include <mach/h3xxx.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
@@ -36,13 +39,28 @@ static void h3100_lcd_power(int enable)
         }
 }
 
+static struct sa1100fb_mach_info h3100_lcd_info = {
+        .pixclock       = 406977,       .bpp            = 4,
+        .xres           = 320,          .yres           = 240,
+
+        .hsync_len      = 26,           .vsync_len      = 41,
+        .left_margin    = 4,            .upper_margin   = 0,
+        .right_margin   = 4,            .lower_margin   = 0,
+
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+        .cmap_greyscale = 1,
+        .cmap_inverse   = 1,
+
+        .lccr0          = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
+
+        .lcd_power = h3100_lcd_power,
+};
 
 static void __init h3100_map_io(void)
 {
         h3xxx_map_io();
 
-        sa1100fb_lcd_power = h3100_lcd_power;
-
         /* Older bootldrs put GPIO2-9 in alternate mode on the
            assumption that they are used for video */
         GAFR &= ~0x000001fb;
@@ -80,12 +98,15 @@ static void __init h3100_mach_init(void)
 {
         h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio));
         h3xxx_mach_init();
+
+        sa11x0_register_lcd(&h3100_lcd_info);
         sa11x0_register_irda(&h3100_irda_data);
 }
 
 MACHINE_START(H3100, "Compaq iPAQ H3100")
         .atag_offset    = 0x100,
         .map_io         = h3100_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = h3100_mach_init,
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 6b58e7460ec..cb6659f294f 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -14,11 +14,14 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 
+#include <video/sa1100fb.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irda.h>
 
 #include <mach/h3xxx.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
@@ -56,11 +59,35 @@ err2:	gpio_free(H3XXX_EGPIO_LCD_ON);
 err1:   return;
 }
 
+static const struct sa1100fb_rgb h3600_rgb_16 = {
+        .red    = { .offset = 12, .length = 4, },
+        .green  = { .offset = 7,  .length = 4, },
+        .blue   = { .offset = 1,  .length = 4, },
+        .transp = { .offset = 0,  .length = 0, },
+};
+
+static struct sa1100fb_mach_info h3600_lcd_info = {
+        .pixclock       = 174757,       .bpp            = 16,
+        .xres           = 320,          .yres           = 240,
+
+        .hsync_len      = 3,            .vsync_len      = 3,
+        .left_margin    = 12,           .upper_margin   = 10,
+        .right_margin   = 17,           .lower_margin   = 1,
+
+        .cmap_static    = 1,
+
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
+
+        .rgb[RGB_16] = &h3600_rgb_16,
+
+        .lcd_power = h3600_lcd_power,
+};
+
+
 static void __init h3600_map_io(void)
 {
         h3xxx_map_io();
-
-        sa1100fb_lcd_power = h3600_lcd_power;
 }
 
 /*
@@ -121,12 +148,15 @@ static void __init h3600_mach_init(void)
 {
         h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio));
         h3xxx_mach_init();
+
+        sa11x0_register_lcd(&h3600_lcd_info);
         sa11x0_register_irda(&h3600_irda_data);
 }
 
 MACHINE_START(H3600, "Compaq iPAQ H3600")
         .atag_offset    = 0x100,
         .map_io         = h3600_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = h3600_mach_init,
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index b0784c974c2..63150e1ffe9 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -109,11 +109,8 @@ static struct flash_platform_data h3xxx_flash_data = {
         .nr_parts       = ARRAY_SIZE(h3xxx_partitions),
 };
 
-static struct resource h3xxx_flash_resource = {
-        .start          = SA1100_CS0_PHYS,
-        .end            = SA1100_CS0_PHYS + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
+static struct resource h3xxx_flash_resource =
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
 
 
 /*
@@ -186,11 +183,7 @@ static struct sa1100_port_fns h3xxx_port_fns __initdata = {
  */
 
 static struct resource egpio_resources[] = {
-        [0] = {
-                .start  = H3600_EGPIO_PHYS,
-                .end    = H3600_EGPIO_PHYS + 0x4 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4),
 };
 
 static struct htc_egpio_chip egpio_chips[] = {
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index c01bb36db94..5535475bf58 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -22,12 +22,10 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/irq.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -35,6 +33,9 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/serial_sa1100.h>
 
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
 #include "generic.h"
 
 /**********************************************************************
@@ -179,11 +180,8 @@ static struct flash_platform_data hackkit_flash_data = {
         .nr_parts       = ARRAY_SIZE(hackkit_partitions),
 };
 
-static struct resource hackkit_flash_resource = {
-        .start          = SA1100_CS0_PHYS,
-        .end            = SA1100_CS0_PHYS + SZ_32M,
-        .flags          = IORESOURCE_MEM,
-};
+static struct resource hackkit_flash_resource =
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
 
 static void __init hackkit_init(void)
 {
@@ -197,6 +195,7 @@ static void __init hackkit_init(void)
 MACHINE_START(HACKKIT, "HackKit Cpu Board")
         .atag_offset    = 0x100,
         .map_io         = hackkit_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = hackkit_init,
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index bae8296f5db..3f2d1b60188 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -1590,224 +1590,9 @@
 
 /*
  * Direct Memory Access (DMA) control registers
- *
- * Registers
- *    DDAR0             Direct Memory Access (DMA) Device Address Register
- *                      channel 0 (read/write).
- *    DCSR0             Direct Memory Access (DMA) Control and Status
- *                      Register channel 0 (read/write).
- *    DBSA0             Direct Memory Access (DMA) Buffer Start address
- *                      register A channel 0 (read/write).
- *    DBTA0             Direct Memory Access (DMA) Buffer Transfer count
- *                      register A channel 0 (read/write).
- *    DBSB0             Direct Memory Access (DMA) Buffer Start address
- *                      register B channel 0 (read/write).
- *    DBTB0             Direct Memory Access (DMA) Buffer Transfer count
- *                      register B channel 0 (read/write).
- *
- *    DDAR1             Direct Memory Access (DMA) Device Address Register
- *                      channel 1 (read/write).
- *    DCSR1             Direct Memory Access (DMA) Control and Status
- *                      Register channel 1 (read/write).
- *    DBSA1             Direct Memory Access (DMA) Buffer Start address
- *                      register A channel 1 (read/write).
- *    DBTA1             Direct Memory Access (DMA) Buffer Transfer count
- *                      register A channel 1 (read/write).
- *    DBSB1             Direct Memory Access (DMA) Buffer Start address
- *                      register B channel 1 (read/write).
- *    DBTB1             Direct Memory Access (DMA) Buffer Transfer count
- *                      register B channel 1 (read/write).
- *
- *    DDAR2             Direct Memory Access (DMA) Device Address Register
- *                      channel 2 (read/write).
- *    DCSR2             Direct Memory Access (DMA) Control and Status
- *                      Register channel 2 (read/write).
- *    DBSA2             Direct Memory Access (DMA) Buffer Start address
- *                      register A channel 2 (read/write).
- *    DBTA2             Direct Memory Access (DMA) Buffer Transfer count
- *                      register A channel 2 (read/write).
- *    DBSB2             Direct Memory Access (DMA) Buffer Start address
- *                      register B channel 2 (read/write).
- *    DBTB2             Direct Memory Access (DMA) Buffer Transfer count
- *                      register B channel 2 (read/write).
- *
- *    DDAR3             Direct Memory Access (DMA) Device Address Register
- *                      channel 3 (read/write).
- *    DCSR3             Direct Memory Access (DMA) Control and Status
- *                      Register channel 3 (read/write).
- *    DBSA3             Direct Memory Access (DMA) Buffer Start address
- *                      register A channel 3 (read/write).
- *    DBTA3             Direct Memory Access (DMA) Buffer Transfer count
- *                      register A channel 3 (read/write).
- *    DBSB3             Direct Memory Access (DMA) Buffer Start address
- *                      register B channel 3 (read/write).
- *    DBTB3             Direct Memory Access (DMA) Buffer Transfer count
- *                      register B channel 3 (read/write).
- *
- *    DDAR4             Direct Memory Access (DMA) Device Address Register
- *                      channel 4 (read/write).
- *    DCSR4             Direct Memory Access (DMA) Control and Status
- *                      Register channel 4 (read/write).
- *    DBSA4             Direct Memory Access (DMA) Buffer Start address
- *                      register A channel 4 (read/write).
- *    DBTA4             Direct Memory Access (DMA) Buffer Transfer count
- *                      register A channel 4 (read/write).
- *    DBSB4             Direct Memory Access (DMA) Buffer Start address
- *                      register B channel 4 (read/write).
- *    DBTB4             Direct Memory Access (DMA) Buffer Transfer count
- *                      register B channel 4 (read/write).
- *
- *    DDAR5             Direct Memory Access (DMA) Device Address Register
- *                      channel 5 (read/write).
- *    DCSR5             Direct Memory Access (DMA) Control and Status
- *                      Register channel 5 (read/write).
- *    DBSA5             Direct Memory Access (DMA) Buffer Start address
- *                      register A channel 5 (read/write).
- *    DBTA5             Direct Memory Access (DMA) Buffer Transfer count
- *                      register A channel 5 (read/write).
- *    DBSB5             Direct Memory Access (DMA) Buffer Start address
- *                      register B channel 5 (read/write).
- *    DBTB5             Direct Memory Access (DMA) Buffer Transfer count
- *                      register B channel 5 (read/write).
  */
-
-#define DMASp           0x00000020      /* DMA control reg. Space [byte]   */
-
-#define DDAR(Nb)        __REG(0xB0000000 + (Nb)*DMASp)  /* DMA Device Address Reg. channel [0..5] */
-#define SetDCSR(Nb)     __REG(0xB0000004 + (Nb)*DMASp)  /* Set DMA Control & Status Reg. channel [0..5] (write) */
-#define ClrDCSR(Nb)     __REG(0xB0000008 + (Nb)*DMASp)  /* Clear DMA Control & Status Reg. channel [0..5] (write) */
-#define RdDCSR(Nb)      __REG(0xB000000C + (Nb)*DMASp)  /* Read DMA Control & Status Reg. channel [0..5] (read) */
-#define DBSA(Nb)        __REG(0xB0000010 + (Nb)*DMASp)  /* DMA Buffer Start address reg. A channel [0..5] */
-#define DBTA(Nb)        __REG(0xB0000014 + (Nb)*DMASp)  /* DMA Buffer Transfer count reg. A channel [0..5] */
-#define DBSB(Nb)        __REG(0xB0000018 + (Nb)*DMASp)  /* DMA Buffer Start address reg. B channel [0..5] */
-#define DBTB(Nb)        __REG(0xB000001C + (Nb)*DMASp)  /* DMA Buffer Transfer count reg. B channel [0..5] */
-
-#define DDAR_RW         0x00000001      /* device data Read/Write          */
-#define DDAR_DevWr      (DDAR_RW*0)     /*  Device data Write              */
-                                        /*  (memory -> device)             */
-#define DDAR_DevRd      (DDAR_RW*1)     /*  Device data Read               */
-                                        /*  (device -> memory)             */
-#define DDAR_E          0x00000002      /* big/little Endian device        */
-#define DDAR_LtlEnd     (DDAR_E*0)      /*  Little Endian device           */
-#define DDAR_BigEnd     (DDAR_E*1)      /*  Big Endian device              */
-#define DDAR_BS         0x00000004      /* device Burst Size               */
-#define DDAR_Brst4      (DDAR_BS*0)     /*  Burst-of-4 device              */
-#define DDAR_Brst8      (DDAR_BS*1)     /*  Burst-of-8 device              */
-#define DDAR_DW         0x00000008      /* device Data Width               */
-#define DDAR_8BitDev    (DDAR_DW*0)     /*  8-Bit Device                   */
-#define DDAR_16BitDev   (DDAR_DW*1)     /*  16-Bit Device                  */
-#define DDAR_DS         Fld (4, 4)      /* Device Select                   */
-#define DDAR_Ser0UDCTr                  /*  Ser. port 0 UDC Transmit       */ \
-                        (0x0 << FShft (DDAR_DS))
-#define DDAR_Ser0UDCRc                  /*  Ser. port 0 UDC Receive        */ \
-                        (0x1 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCTr                 /*  Ser. port 1 SDLC Transmit      */ \
-                        (0x2 << FShft (DDAR_DS))
-#define DDAR_Ser1SDLCRc                 /*  Ser. port 1 SDLC Receive       */ \
-                        (0x3 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTTr                 /*  Ser. port 1 UART Transmit      */ \
-                        (0x4 << FShft (DDAR_DS))
-#define DDAR_Ser1UARTRc                 /*  Ser. port 1 UART Receive       */ \
-                        (0x5 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPTr                  /*  Ser. port 2 ICP Transmit       */ \
-                        (0x6 << FShft (DDAR_DS))
-#define DDAR_Ser2ICPRc                  /*  Ser. port 2 ICP Receive        */ \
-                        (0x7 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTTr                 /*  Ser. port 3 UART Transmit      */ \
-                        (0x8 << FShft (DDAR_DS))
-#define DDAR_Ser3UARTRc                 /*  Ser. port 3 UART Receive       */ \
-                        (0x9 << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Tr                 /*  Ser. port 4 MCP 0 Transmit     */ \
-                                        /*  (audio)                        */ \
-                        (0xA << FShft (DDAR_DS))
-#define DDAR_Ser4MCP0Rc                 /*  Ser. port 4 MCP 0 Receive      */ \
-                                        /*  (audio)                        */ \
-                        (0xB << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Tr                 /*  Ser. port 4 MCP 1 Transmit     */ \
-                                        /*  (telecom)                      */ \
-                        (0xC << FShft (DDAR_DS))
-#define DDAR_Ser4MCP1Rc                 /*  Ser. port 4 MCP 1 Receive      */ \
-                                        /*  (telecom)                      */ \
-                        (0xD << FShft (DDAR_DS))
-#define DDAR_Ser4SSPTr                  /*  Ser. port 4 SSP Transmit       */ \
-                        (0xE << FShft (DDAR_DS))
-#define DDAR_Ser4SSPRc                  /*  Ser. port 4 SSP Receive        */ \
-                        (0xF << FShft (DDAR_DS))
-#define DDAR_DA         Fld (24, 8)     /* Device Address                  */
-#define DDAR_DevAdd(Add)                /*  Device Address                 */ \
-                        (((Add) & 0xF0000000) | \
-                         (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
-#define DDAR_Ser0UDCWr                  /* Ser. port 0 UDC Write           */ \
-                        (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
-                         DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
-#define DDAR_Ser0UDCRd                  /* Ser. port 0 UDC Read            */ \
-                        (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
-                         DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
-#define DDAR_Ser1UARTWr                 /* Ser. port 1 UART Write          */ \
-                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
-#define DDAR_Ser1UARTRd                 /* Ser. port 1 UART Read           */ \
-                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
-#define DDAR_Ser1SDLCWr                 /* Ser. port 1 SDLC Write          */ \
-                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
-#define DDAR_Ser1SDLCRd                 /* Ser. port 1 SDLC Read           */ \
-                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
-#define DDAR_Ser2UARTWr                 /* Ser. port 2 UART Write          */ \
-                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
-#define DDAR_Ser2UARTRd                 /* Ser. port 2 UART Read           */ \
-                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
-#define DDAR_Ser2HSSPWr                 /* Ser. port 2 HSSP Write          */ \
-                        (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
-                         DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
-#define DDAR_Ser2HSSPRd                 /* Ser. port 2 HSSP Read           */ \
-                        (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
-                         DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
-#define DDAR_Ser3UARTWr                 /* Ser. port 3 UART Write          */ \
-                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
-#define DDAR_Ser3UARTRd                 /* Ser. port 3 UART Read           */ \
-                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
-                         DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
-#define DDAR_Ser4MCP0Wr                 /* Ser. port 4 MCP 0 Write (audio) */ \
-                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
-                         DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
-#define DDAR_Ser4MCP0Rd                 /* Ser. port 4 MCP 0 Read (audio)  */ \
-                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
-                         DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
-#define DDAR_Ser4MCP1Wr                 /* Ser. port 4 MCP 1 Write         */ \
-                                        /* (telecom)                       */ \
-                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
-                         DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
-#define DDAR_Ser4MCP1Rd                 /* Ser. port 4 MCP 1 Read          */ \
-                                        /* (telecom)                       */ \
-                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
-                         DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
-#define DDAR_Ser4SSPWr                  /* Ser. port 4 SSP Write (16 bits) */ \
-                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
-                         DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
-#define DDAR_Ser4SSPRd                  /* Ser. port 4 SSP Read (16 bits)  */ \
-                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
-                         DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
-
-#define DCSR_RUN        0x00000001      /* DMA running                     */
-#define DCSR_IE         0x00000002      /* DMA Interrupt Enable            */
-#define DCSR_ERROR      0x00000004      /* DMA ERROR                       */
-#define DCSR_DONEA      0x00000008      /* DONE DMA transfer buffer A      */
-#define DCSR_STRTA      0x00000010      /* STaRTed DMA transfer buffer A   */
-#define DCSR_DONEB      0x00000020      /* DONE DMA transfer buffer B      */
-#define DCSR_STRTB      0x00000040      /* STaRTed DMA transfer buffer B   */
-#define DCSR_BIU        0x00000080      /* DMA Buffer In Use               */
-#define DCSR_BufA       (DCSR_BIU*0)    /*  DMA Buffer A in use            */
-#define DCSR_BufB       (DCSR_BIU*1)    /*  DMA Buffer B in use            */
-
-#define DBT_TC          Fld (13, 0)     /* Transfer Count                  */
-#define DBTA_TCA        DBT_TC          /* Transfer Count buffer A         */
-#define DBTB_TCB        DBT_TC          /* Transfer Count buffer B         */
+#define DMA_SIZE        (6 * 0x20)
+#define DMA_PHYS        0xb0000000
 
 
 /*
@@ -1903,16 +1688,6 @@
 #define LCD_Int100_0A   0xF             /* LCD Intensity = 100.0% =  1     */
                                         /* (Alternative)                   */
 
-#define LCCR0           __REG(0xB0100000)  /* LCD Control Reg. 0 */
-#define LCSR            __REG(0xB0100004)  /* LCD Status Reg. */
-#define DBAR1           __REG(0xB0100010)  /* LCD DMA Base Address Reg. channel 1 */
-#define DCAR1           __REG(0xB0100014)  /* LCD DMA Current Address Reg. channel 1 */
-#define DBAR2           __REG(0xB0100018)  /* LCD DMA Base Address Reg.  channel 2 */
-#define DCAR2           __REG(0xB010001C)  /* LCD DMA Current Address Reg. channel 2 */
-#define LCCR1           __REG(0xB0100020)  /* LCD Control Reg. 1 */
-#define LCCR2           __REG(0xB0100024)  /* LCD Control Reg. 2 */
-#define LCCR3           __REG(0xB0100028)  /* LCD Control Reg. 3 */
-
 #define LCCR0_LEN       0x00000001      /* LCD ENable                      */
 #define LCCR0_CMS       0x00000002      /* Color/Monochrome display Select */
 #define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display                  */
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 28c2cf50c25..307391488c2 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -85,21 +85,18 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
 #define ASSABET_BSR_RAD_RI      (1 << 31)
 
 
-/* GPIOs for which the generic definition doesn't say much */
+/* GPIOs (bitmasks) for which the generic definition doesn't say much */
 #define ASSABET_GPIO_RADIO_IRQ          GPIO_GPIO (14)  /* Radio interrupt request  */
 #define ASSABET_GPIO_PS_MODE_SYNC       GPIO_GPIO (16)  /* Power supply mode/sync   */
 #define ASSABET_GPIO_STEREO_64FS_CLK    GPIO_GPIO (19)  /* SSP UDA1341 clock input  */
-#define ASSABET_GPIO_CF_IRQ             GPIO_GPIO (21)  /* CF IRQ   */
-#define ASSABET_GPIO_CF_CD              GPIO_GPIO (22)  /* CF CD */
-#define ASSABET_GPIO_CF_BVD2            GPIO_GPIO (24)  /* CF BVD */
 #define ASSABET_GPIO_GFX_IRQ            GPIO_GPIO (24)  /* Graphics IRQ */
-#define ASSABET_GPIO_CF_BVD1            GPIO_GPIO (25)  /* CF BVD */
 #define ASSABET_GPIO_BATT_LOW           GPIO_GPIO (26)  /* Low battery */
 #define ASSABET_GPIO_RCLK               GPIO_GPIO (26)  /* CCLK/2  */
 
-#define ASSABET_IRQ_GPIO_CF_IRQ         IRQ_GPIO21
-#define ASSABET_IRQ_GPIO_CF_CD          IRQ_GPIO22
-#define ASSABET_IRQ_GPIO_CF_BVD2        IRQ_GPIO24
-#define ASSABET_IRQ_GPIO_CF_BVD1        IRQ_GPIO25
+/* These are gpiolib GPIO numbers, not bitmasks */
+#define ASSABET_GPIO_CF_IRQ             21      /* CF IRQ */
+#define ASSABET_GPIO_CF_CD              22      /* CF CD  */
+#define ASSABET_GPIO_CF_BVD2            24      /* CF BVD / IOSPKR */
+#define ASSABET_GPIO_CF_BVD1            25      /* CF BVD / IOSTSCHG */
 
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h
index c3ac3d0f946..88fd9c006ce 100644
--- a/arch/arm/mach-sa1100/include/mach/cerf.h
+++ b/arch/arm/mach-sa1100/include/mach/cerf.h
@@ -14,15 +14,10 @@
 #define CERF_ETH_IO                     0xf0000000
 #define CERF_ETH_IRQ IRQ_GPIO26
 
-#define CERF_GPIO_CF_BVD2               GPIO_GPIO (19)
-#define CERF_GPIO_CF_BVD1               GPIO_GPIO (20)
-#define CERF_GPIO_CF_RESET              GPIO_GPIO (21)
-#define CERF_GPIO_CF_IRQ                GPIO_GPIO (22)
-#define CERF_GPIO_CF_CD                 GPIO_GPIO (23)
-
-#define CERF_IRQ_GPIO_CF_BVD2           IRQ_GPIO19
-#define CERF_IRQ_GPIO_CF_BVD1           IRQ_GPIO20
-#define CERF_IRQ_GPIO_CF_IRQ            IRQ_GPIO22
-#define CERF_IRQ_GPIO_CF_CD             IRQ_GPIO23
+#define CERF_GPIO_CF_BVD2               19
+#define CERF_GPIO_CF_BVD1               20
+#define CERF_GPIO_CF_RESET              21
+#define CERF_GPIO_CF_IRQ                22
+#define CERF_GPIO_CF_CD                 23
 
 #endif // _INCLUDE_CERF_H_
diff --git a/arch/arm/mach-sa1100/include/mach/dma.h b/arch/arm/mach-sa1100/include/mach/dma.h
deleted file mode 100644
index dda1b351310..00000000000
--- a/arch/arm/mach-sa1100/include/mach/dma.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/dma.h
- *
- * Generic SA1100 DMA support
- *
- * Copyright (C) 2000 Nicolas Pitre
- *
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "hardware.h"
-
-
-/*
- * The SA1100 has six internal DMA channels.
- */
-#define SA1100_DMA_CHANNELS     6
-
-/*
- * Maximum physical DMA buffer size
- */
-#define MAX_DMA_SIZE            0x1fff
-#define CUT_DMA_SIZE            0x1000
-
-/*
- * All possible SA1100 devices a DMA channel can be attached to.
- */
-typedef enum {
-        DMA_Ser0UDCWr  = DDAR_Ser0UDCWr,   /* Ser. port 0 UDC Write */
-        DMA_Ser0UDCRd  = DDAR_Ser0UDCRd,   /* Ser. port 0 UDC Read */
-        DMA_Ser1UARTWr = DDAR_Ser1UARTWr,  /* Ser. port 1 UART Write */
-        DMA_Ser1UARTRd = DDAR_Ser1UARTRd,  /* Ser. port 1 UART Read */
-        DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr,  /* Ser. port 1 SDLC Write */
-        DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd,  /* Ser. port 1 SDLC Read */
-        DMA_Ser2UARTWr = DDAR_Ser2UARTWr,  /* Ser. port 2 UART Write */
-        DMA_Ser2UARTRd = DDAR_Ser2UARTRd,  /* Ser. port 2 UART Read */
-        DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr,  /* Ser. port 2 HSSP Write */
-        DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd,  /* Ser. port 2 HSSP Read */
-        DMA_Ser3UARTWr = DDAR_Ser3UARTWr,  /* Ser. port 3 UART Write */
-        DMA_Ser3UARTRd = DDAR_Ser3UARTRd,  /* Ser. port 3 UART Read */
-        DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr,  /* Ser. port 4 MCP 0 Write (audio) */
-        DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd,  /* Ser. port 4 MCP 0 Read (audio) */
-        DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr,  /* Ser. port 4 MCP 1 Write */
-        DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd,  /* Ser. port 4 MCP 1 Read */
-        DMA_Ser4SSPWr  = DDAR_Ser4SSPWr,   /* Ser. port 4 SSP Write (16 bits) */
-        DMA_Ser4SSPRd  = DDAR_Ser4SSPRd    /* Ser. port 4 SSP Read (16 bits) */
-} dma_device_t;
-
-typedef struct {
-        volatile u_long DDAR;
-        volatile u_long SetDCSR;
-        volatile u_long ClrDCSR;
-        volatile u_long RdDCSR;
-        volatile dma_addr_t DBSA;
-        volatile u_long DBTA;
-        volatile dma_addr_t DBSB;
-        volatile u_long DBTB;
-} dma_regs_t;
-
-typedef void (*dma_callback_t)(void *data);
-
-/*
- * DMA function prototypes
- */
-
-extern int sa1100_request_dma( dma_device_t device, const char *device_id,
-                               dma_callback_t callback, void *data,
-                               dma_regs_t **regs );
-extern void sa1100_free_dma( dma_regs_t *regs );
-extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
-extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
-extern void sa1100_reset_dma(dma_regs_t *regs);
-
-/**
- *      sa1100_stop_dma - stop DMA in progress
- *      @regs: identifier for the channel to use
- *
- *      This stops DMA without clearing buffer pointers. Unlike
- *      sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
- *      or sa1100_get_dma_pos().
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-#define sa1100_stop_dma(regs)   ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
-
-/**
- *      sa1100_resume_dma - resume DMA on a stopped channel
- *      @regs: identifier for the channel to use
- *
- *      This resumes DMA on a channel previously stopped with
- *      sa1100_stop_dma().
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
-
-/**
- *      sa1100_clear_dma - clear DMA pointers
- *      @regs: identifier for the channel to use
- *
- *      This clear any DMA state so the DMA engine is ready to restart
- *      with new buffers through sa1100_start_dma(). Any buffers in flight
- *      are discarded.
- *
- *      The @regs identifier is provided by a successful call to
- *      sa1100_request_dma().
- **/
-
-#define sa1100_clear_dma(regs)  ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
index 6aa13c46c5d..8cf7630bf02 100644
--- a/arch/arm/mach-sa1100/include/mach/entry-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S
@@ -8,17 +8,11 @@
  * warranty of any kind, whether express or implied.
  */
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 mov     \base, #0xfa000000              @ ICIP = 0xfa050000
                 add     \base, \base, #0x00050000
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, [\base]               @ get irqs
                 ldr     \irqnr, [\base, #4]             @ ICMR = 0xfa050004
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index d18f21abef8..3790298b714 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -71,22 +71,19 @@
 /*
  * Figure out the MAX IRQ number.
  *
- * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
- * If we have an LoCoMo, the max IRQ is IRQ_BOARD_START + 4
- * Otherwise, we have the standard IRQs only.
+ * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically
+ * allocate their IRQs above NR_IRQS.
+ *
+ * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
+ * to be included in the NR_IRQS calculation.
  */
-#ifdef CONFIG_SA1111
-#define NR_IRQS                 (IRQ_BOARD_END + 55)
-#elif defined(CONFIG_SHARP_LOCOMO)
-#define NR_IRQS                 (IRQ_BOARD_START + 4)
+#ifdef CONFIG_SHARP_LOCOMO
+#define NR_IRQS_LOCOMO          4
 #else
-#define NR_IRQS                 (IRQ_BOARD_START)
+#define NR_IRQS_LOCOMO          0
 #endif
 
-/*
- * Board specific IRQs.  Define them here.
- * Do not surround them with ifdefs.
- */
-#define IRQ_NEPONSET_SMC9196    (IRQ_BOARD_START + 0)
-#define IRQ_NEPONSET_USAR       (IRQ_BOARD_START + 1)
-#define IRQ_NEPONSET_SA1111     (IRQ_BOARD_START + 2)
+#ifndef NR_IRQS
+#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
+#endif
+#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h
index ed1a331508a..4b2860ae382 100644
--- a/arch/arm/mach-sa1100/include/mach/mcp.h
+++ b/arch/arm/mach-sa1100/include/mach/mcp.h
@@ -16,7 +16,7 @@ struct mcp_plat_data {
         u32 mccr0;
         u32 mccr1;
         unsigned int sclk_rate;
-        int gpio_base;
+        void *codec_pdata;
 };
 
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
index 14f8382d066..5ebd469a31f 100644
--- a/arch/arm/mach-sa1100/include/mach/nanoengine.h
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -16,12 +16,12 @@
 
 #include <mach/irqs.h>
 
-#define GPIO_PC_READY0  GPIO_GPIO(11) /* ready for socket 0 (active high)*/
-#define GPIO_PC_READY1  GPIO_GPIO(12) /* ready for socket 1 (active high) */
-#define GPIO_PC_CD0     GPIO_GPIO(13) /* detect for socket 0 (active low) */
-#define GPIO_PC_CD1     GPIO_GPIO(14) /* detect for socket 1 (active low) */
-#define GPIO_PC_RESET0  GPIO_GPIO(15) /* reset socket 0 */
-#define GPIO_PC_RESET1  GPIO_GPIO(16) /* reset socket 1 */
+#define GPIO_PC_READY0  11 /* ready for socket 0 (active high)*/
+#define GPIO_PC_READY1  12 /* ready for socket 1 (active high) */
+#define GPIO_PC_CD0     13 /* detect for socket 0 (active low) */
+#define GPIO_PC_CD1     14 /* detect for socket 1 (active low) */
+#define GPIO_PC_RESET0  15 /* reset socket 0 */
+#define GPIO_PC_RESET1  16 /* reset socket 1 */
 
 #define NANOENGINE_IRQ_GPIO_PCI         IRQ_GPIO0
 #define NANOENGINE_IRQ_GPIO_PC_READY0   IRQ_GPIO11
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
index ffe2bc45eed..5516a52a329 100644
--- a/arch/arm/mach-sa1100/include/mach/neponset.h
+++ b/arch/arm/mach-sa1100/include/mach/neponset.h
@@ -15,54 +15,6 @@
 /*
  * Neponset definitions: 
  */
-
-#define NEPONSET_CPLD_BASE      (0x10000000)
-#define Nep_p2v( x )            ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
-#define Nep_v2p( x )            ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
-
-#define _IRR                    0x10000024      /* Interrupt Reason Register */
-#define _AUD_CTL                0x100000c0      /* Audio controls (RW)       */
-#define _MDM_CTL_0              0x100000b0      /* Modem control 0 (RW)      */
-#define _MDM_CTL_1              0x100000b4      /* Modem control 1 (RW)      */
-#define _NCR_0                  0x100000a0      /* Control Register (RW)     */
-#define _KP_X_OUT               0x10000090      /* Keypad row write (RW)     */
-#define _KP_Y_IN                0x10000080      /* Keypad column read (RO)   */
-#define _SWPK                   0x10000020      /* Switch pack (RO)          */
-#define _WHOAMI                 0x10000000      /* System ID Register (RO)   */
-
-#define _LEDS                   0x10000010      /* LEDs [31:0] (WO)          */
-
-#define IRR                     (*((volatile u_char *) Nep_p2v(_IRR)))
-#define AUD_CTL                 (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
-#define MDM_CTL_0               (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
-#define MDM_CTL_1               (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
-#define NCR_0                   (*((volatile u_char *) Nep_p2v(_NCR_0)))
-#define KP_X_OUT                (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
-#define KP_Y_IN                 (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
-#define SWPK                    (*((volatile u_char *) Nep_p2v(_SWPK)))
-#define WHOAMI                  (*((volatile u_char *) Nep_p2v(_WHOAMI)))
-
-#define LEDS                    (*((volatile Word   *) Nep_p2v(_LEDS)))
-
-#define IRR_ETHERNET            (1<<0)
-#define IRR_USAR                (1<<1)
-#define IRR_SA1111              (1<<2)
-
-#define AUD_SEL_1341            (1<<0)
-#define AUD_MUTE_1341           (1<<1)
-
-#define MDM_CTL0_RTS1           (1 << 0)
-#define MDM_CTL0_DTR1           (1 << 1)
-#define MDM_CTL0_RTS2           (1 << 2)
-#define MDM_CTL0_DTR2           (1 << 3)
-
-#define MDM_CTL1_CTS1           (1 << 0)
-#define MDM_CTL1_DSR1           (1 << 1)
-#define MDM_CTL1_DCD1           (1 << 2)
-#define MDM_CTL1_CTS2           (1 << 3)
-#define MDM_CTL1_DSR2           (1 << 4)
-#define MDM_CTL1_DCD2           (1 << 5)
-
 #define NCR_GP01_OFF            (1<<0)
 #define NCR_TP_PWR_EN           (1<<1)
 #define NCR_MS_PWR_EN           (1<<2)
@@ -71,4 +23,8 @@
 #define NCR_A0VPP               (1<<5)
 #define NCR_A1VPP               (1<<6)
 
+void neponset_ncr_frob(unsigned int, unsigned int);
+#define neponset_ncr_set(v)     neponset_ncr_frob(0, v)
+#define neponset_ncr_clear(v)   neponset_ncr_frob(v, 0)
+
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index ec27d6e1214..fff39e02b49 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -21,16 +21,12 @@
 #define SHANNON_GPIO_U3_RTS             GPIO_GPIO (19)  /* ?? */
 #define SHANNON_GPIO_U3_CTS             GPIO_GPIO (20)  /* ?? */
 #define SHANNON_GPIO_SENSE_12V          GPIO_GPIO (21)  /* Input, 12v flash unprotect detected */
-#define SHANNON_GPIO_DISP_EN            GPIO_GPIO (22)  /* out */
+#define SHANNON_GPIO_DISP_EN            22              /* out */
 /* XXX GPIO 23 unaccounted for */
-#define SHANNON_GPIO_EJECT_0            GPIO_GPIO (24)  /* in */
-#define SHANNON_IRQ_GPIO_EJECT_0        IRQ_GPIO24
-#define SHANNON_GPIO_EJECT_1            GPIO_GPIO (25)  /* in */
-#define SHANNON_IRQ_GPIO_EJECT_1        IRQ_GPIO25
-#define SHANNON_GPIO_RDY_0              GPIO_GPIO (26)  /* in */
-#define SHANNON_IRQ_GPIO_RDY_0          IRQ_GPIO26
-#define SHANNON_GPIO_RDY_1              GPIO_GPIO (27)  /* in */
-#define SHANNON_IRQ_GPIO_RDY_1          IRQ_GPIO27
+#define SHANNON_GPIO_EJECT_0            24              /* in */
+#define SHANNON_GPIO_EJECT_1            25              /* in */
+#define SHANNON_GPIO_RDY_0              26              /* in */
+#define SHANNON_GPIO_RDY_1              27              /* in */
 
 /* MCP UCB codec GPIO pins... */
 
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index db28118103e..cdea671e893 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -39,10 +39,8 @@
 
 
 /*---  PCMCIA  ---*/
-#define GPIO_CF_CD              GPIO_GPIO24
-#define GPIO_CF_IRQ             GPIO_GPIO1
-#define IRQ_GPIO_CF_IRQ         IRQ_GPIO1
-#define IRQ_GPIO_CF_CD          IRQ_GPIO24
+#define GPIO_CF_CD              24
+#define GPIO_CF_IRQ             1
 
 /*--- SmartCard ---*/
 #define GPIO_SMART_CARD         GPIO_GPIO10
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
deleted file mode 100644
index e17b208f76d..00000000000
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/system.h
- *
- * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index dfbf824a69f..516ccc25d7f 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -17,6 +17,7 @@
 #include <linux/syscore_ops.h>
 
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 #include <asm/mach/irq.h>
 
 #include "generic.h"
@@ -221,11 +222,8 @@ static struct irq_chip sa1100_normal_chip = {
         .irq_set_wake   = sa1100_set_wake,
 };
 
-static struct resource irq_resource = {
-        .name   = "irqs",
-        .start  = 0x90050000,
-        .end    = 0x9005ffff,
-};
+static struct resource irq_resource =
+        DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
 
 static struct sa1100irq_state {
         unsigned int    saved;
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index ee121d6f048..ca7a7e83472 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -23,9 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <video/s1d13xxxfb.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/sa1111.h>
-#include <asm/irq.h>
 #include <asm/page.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
@@ -34,6 +32,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
 
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
 #include "generic.h"
 
 /*
@@ -46,7 +47,7 @@
 
 /* memory space (line 52 of HP's doc) */
 #define SA1111REGSTART  0x40000000
-#define SA1111REGLEN    0x00001fff
+#define SA1111REGLEN    0x00002000
 #define EPSONREGSTART   0x48000000
 #define EPSONREGLEN     0x00100000
 #define EPSONFBSTART    0x48200000
@@ -174,16 +175,8 @@ static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
 };
 
 static struct resource s1d13xxxfb_resources[] = {
-        [0] = {
-                .start  = EPSONFBSTART,
-                .end    = EPSONFBSTART + EPSONFBLEN,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = EPSONREGSTART,
-                .end    = EPSONREGSTART + EPSONREGLEN,
-                .flags  = IORESOURCE_MEM,
-        }
+        [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
+        [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
 };
 
 static struct platform_device s1d13xxxfb_device = {
@@ -197,20 +190,12 @@ static struct platform_device s1d13xxxfb_device = {
 };
 
 static struct resource sa1111_resources[] = {
-        [0] = {
-                .start          = SA1111REGSTART,
-                .end            = SA1111REGSTART + SA1111REGLEN,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = IRQ_GPIO1,
-                .end            = IRQ_GPIO1,
-                .flags          = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
+        [1] = DEFINE_RES_IRQ(IRQ_GPIO1),
 };
 
 static struct sa1111_platform_data sa1111_info = {
-        .irq_base       = IRQ_BOARD_END,
+        .disable_devs   = SA1111_DEVID_PS2_MSE,
 };
 
 static u64 sa1111_dmamask = 0xffffffffUL;
@@ -284,11 +269,6 @@ static struct map_desc jornada720_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(EPSONFBSTART),
                 .length         = EPSONFBLEN,
                 .type           = MT_DEVICE
-        }, {    /* SA-1111 */
-                .virtual        = 0xf4000000,
-                .pfn            = __phys_to_pfn(SA1111REGSTART),
-                .length         = SA1111REGLEN,
-                .type           = MT_DEVICE
         }
 };
 
@@ -352,11 +332,8 @@ static struct flash_platform_data jornada720_flash_data = {
         .nr_parts       = ARRAY_SIZE(jornada720_partitions),
 };
 
-static struct resource jornada720_flash_resource = {
-        .start          = SA1100_CS0_PHYS,
-        .end            = SA1100_CS0_PHYS + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
+static struct resource jornada720_flash_resource =
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
 
 static void __init jornada720_mach_init(void)
 {
@@ -367,6 +344,7 @@ MACHINE_START(JORNADA720, "HP Jornada 720")
         /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
         .atag_offset    = 0x100,
         .map_io         = jornada720_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = jornada720_mach_init,
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index af4e2761f3d..eb6534e0b0d 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -6,6 +6,8 @@
 #include <linux/kernel.h>
 #include <linux/tty.h>
 
+#include <video/sa1100fb.h>
+
 #include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -15,6 +17,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/serial_sa1100.h>
 #include <mach/mcp.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
@@ -26,8 +29,86 @@ static struct mcp_plat_data lart_mcp_data = {
         .sclk_rate      = 11981000,
 };
 
+#ifdef LART_GREY_LCD
+static struct sa1100fb_mach_info lart_grey_info = {
+        .pixclock       = 150000,       .bpp            = 4,
+        .xres           = 320,          .yres           = 240,
+
+        .hsync_len      = 1,            .vsync_len      = 1,
+        .left_margin    = 4,            .upper_margin   = 0,
+        .right_margin   = 2,            .lower_margin   = 0,
+
+        .cmap_greyscale = 1,
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+
+        .lccr0          = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
+};
+#endif
+#ifdef LART_COLOR_LCD
+static struct sa1100fb_mach_info lart_color_info = {
+        .pixclock       = 150000,       .bpp            = 16,
+        .xres           = 320,          .yres           = 240,
+
+        .hsync_len      = 2,            .vsync_len      = 3,
+        .left_margin    = 69,           .upper_margin   = 14,
+        .right_margin   = 8,            .lower_margin   = 4,
+
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
+};
+#endif
+#ifdef LART_VIDEO_OUT
+static struct sa1100fb_mach_info lart_video_info = {
+        .pixclock       = 39721,        .bpp            = 16,
+        .xres           = 640,          .yres           = 480,
+
+        .hsync_len      = 95,           .vsync_len      = 2,
+        .left_margin    = 40,           .upper_margin   = 32,
+        .right_margin   = 24,           .lower_margin   = 11,
+
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
+};
+#endif
+
+#ifdef LART_KIT01_LCD
+static struct sa1100fb_mach_info lart_kit01_info = {
+        .pixclock       = 63291,        .bpp            = 16,
+        .xres           = 640,          .yres           = 480,
+
+        .hsync_len      = 64,           .vsync_len      = 3,
+        .left_margin    = 122,          .upper_margin   = 45,
+        .right_margin   = 10,           .lower_margin   = 10,
+
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = LCCR3_OutEnH | LCCR3_PixFlEdg
+};
+#endif
+
 static void __init lart_init(void)
 {
+        struct sa1100fb_mach_info *inf = NULL;
+
+#ifdef LART_GREY_LCD
+        inf = &lart_grey_info;
+#endif
+#ifdef LART_COLOR_LCD
+        inf = &lart_color_info;
+#endif
+#ifdef LART_VIDEO_OUT
+        inf = &lart_video_info;
+#endif
+#ifdef LART_KIT01_LCD
+        inf = &lart_kit01_info;
+#endif
+
+        if (inf)
+                sa11x0_register_lcd(inf);
+
+        sa11x0_ppc_configure_mcp();
         sa11x0_register_mcp(&lart_mcp_data);
 }
 
@@ -63,6 +144,7 @@ static void __init lart_map_io(void)
 MACHINE_START(LART, "LART")
         .atag_offset    = 0x100,
         .map_io         = lart_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .init_machine   = lart_init,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 85f6ee67222..8f6446b9f02 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -28,6 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/nanoengine.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
@@ -58,15 +59,8 @@ static struct flash_platform_data nanoengine_flash_data = {
 };
 
 static struct resource nanoengine_flash_resources[] = {
-        {
-                .start  = SA1100_CS0_PHYS,
-                .end    = SA1100_CS0_PHYS + SZ_32M - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = SA1100_CS1_PHYS,
-                .end    = SA1100_CS1_PHYS + SZ_32M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
+        DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
 };
 
 static struct map_desc nanoengine_io_desc[] __initdata = {
@@ -114,6 +108,7 @@ static void __init nanoengine_init(void)
 MACHINE_START(NANOENGINE, "BSE nanoEngine")
         .atag_offset    = 0x100,
         .map_io         = nanoengine_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = nanoengine_init,
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index b4fa53a1427..6c58f01b358 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -1,89 +1,104 @@
 /*
  * linux/arch/arm/mach-sa1100/neponset.c
- *
  */
-#include <linux/kernel.h>
+#include <linux/err.h>
 #include <linux/init.h>
-#include <linux/tty.h>
 #include <linux/ioport.h>
-#include <linux/serial_core.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/serial_core.h>
+#include <linux/slab.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/irq.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
 #include <asm/mach/serial_sa1100.h>
-#include <mach/assabet.h>
-#include <mach/neponset.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/sizes.h>
 
-/*
- * Install handler for Neponset IRQ.  Note that we have to loop here
- * since the ETHERNET and USAR IRQs are level based, and we need to
- * ensure that the IRQ signal is deasserted before returning.  This
- * is rather unfortunate.
- */
-static void
-neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int irr;
-
-        while (1) {
-                /*
-                 * Acknowledge the parent IRQ.
-                 */
-                desc->irq_data.chip->irq_ack(&desc->irq_data);
-
-                /*
-                 * Read the interrupt reason register.  Let's have all
-                 * active IRQ bits high.  Note: there is a typo in the
-                 * Neponset user's guide for the SA1111 IRR level.
-                 */
-                irr = IRR ^ (IRR_ETHERNET | IRR_USAR);
-
-                if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
-                        break;
-
-                /*
-                 * Since there is no individual mask, we have to
-                 * mask the parent IRQ.  This is safe, since we'll
-                 * recheck the register for any pending IRQs.
-                 */
-                if (irr & (IRR_ETHERNET | IRR_USAR)) {
-                        desc->irq_data.chip->irq_mask(&desc->irq_data);
-
-                        /*
-                         * Ack the interrupt now to prevent re-entering
-                         * this neponset handler.  Again, this is safe
-                         * since we'll check the IRR register prior to
-                         * leaving.
-                         */
-                        desc->irq_data.chip->irq_ack(&desc->irq_data);
+#include <mach/hardware.h>
+#include <mach/assabet.h>
+#include <mach/neponset.h>
+#include <mach/irqs.h>
+
+#define NEP_IRQ_SMC91X  0
+#define NEP_IRQ_USAR    1
+#define NEP_IRQ_SA1111  2
+#define NEP_IRQ_NR      3
+
+#define WHOAMI          0x00
+#define LEDS            0x10
+#define SWPK            0x20
+#define IRR             0x24
+#define KP_Y_IN         0x80
+#define KP_X_OUT        0x90
+#define NCR_0           0xa0
+#define MDM_CTL_0       0xb0
+#define MDM_CTL_1       0xb4
+#define AUD_CTL         0xc0
+
+#define IRR_ETHERNET    (1 << 0)
+#define IRR_USAR        (1 << 1)
+#define IRR_SA1111      (1 << 2)
+
+#define MDM_CTL0_RTS1   (1 << 0)
+#define MDM_CTL0_DTR1   (1 << 1)
+#define MDM_CTL0_RTS2   (1 << 2)
+#define MDM_CTL0_DTR2   (1 << 3)
+
+#define MDM_CTL1_CTS1   (1 << 0)
+#define MDM_CTL1_DSR1   (1 << 1)
+#define MDM_CTL1_DCD1   (1 << 2)
+#define MDM_CTL1_CTS2   (1 << 3)
+#define MDM_CTL1_DSR2   (1 << 4)
+#define MDM_CTL1_DCD2   (1 << 5)
+
+#define AUD_SEL_1341    (1 << 0)
+#define AUD_MUTE_1341   (1 << 1)
 
-                        if (irr & IRR_ETHERNET) {
-                                generic_handle_irq(IRQ_NEPONSET_SMC9196);
-                        }
+extern void sa1110_mb_disable(void);
 
-                        if (irr & IRR_USAR) {
-                                generic_handle_irq(IRQ_NEPONSET_USAR);
-                        }
+struct neponset_drvdata {
+        void __iomem *base;
+        struct platform_device *sa1111;
+        struct platform_device *smc91x;
+        unsigned irq_base;
+#ifdef CONFIG_PM_SLEEP
+        u32 ncr0;
+        u32 mdm_ctl_0;
+#endif
+};
 
-                        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-                }
+static void __iomem *nep_base;
 
-                if (irr & IRR_SA1111) {
-                        generic_handle_irq(IRQ_NEPONSET_SA1111);
-                }
+void neponset_ncr_frob(unsigned int mask, unsigned int val)
+{
+        void __iomem *base = nep_base;
+
+        if (base) {
+                unsigned long flags;
+                unsigned v;
+
+                local_irq_save(flags);
+                v = readb_relaxed(base + NCR_0);
+                writeb_relaxed((v & ~mask) | val, base + NCR_0);
+                local_irq_restore(flags);
+        } else {
+                WARN(1, "nep_base unset\n");
         }
 }
 
 static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
 {
-        u_int mdm_ctl0 = MDM_CTL_0;
+        void __iomem *base = nep_base;
+        u_int mdm_ctl0;
 
+        if (!base)
+                return;
+
+        mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
         if (port->mapbase == _Ser1UTCR0) {
                 if (mctrl & TIOCM_RTS)
                         mdm_ctl0 &= ~MDM_CTL0_RTS2;
@@ -106,14 +121,19 @@ static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
                         mdm_ctl0 |= MDM_CTL0_DTR1;
         }
 
-        MDM_CTL_0 = mdm_ctl0;
+        writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
 }
 
 static u_int neponset_get_mctrl(struct uart_port *port)
 {
+        void __iomem *base = nep_base;
         u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
-        u_int mdm_ctl1 = MDM_CTL_1;
+        u_int mdm_ctl1;
+
+        if (!base)
+                return ret;
 
+        mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
         if (port->mapbase == _Ser1UTCR0) {
                 if (mdm_ctl1 & MDM_CTL1_DCD2)
                         ret &= ~TIOCM_CD;
@@ -138,209 +158,278 @@ static struct sa1100_port_fns neponset_port_fns __devinitdata = {
         .get_mctrl      = neponset_get_mctrl,
 };
 
-static int __devinit neponset_probe(struct platform_device *dev)
+/*
+ * Install handler for Neponset IRQ.  Note that we have to loop here
+ * since the ETHERNET and USAR IRQs are level based, and we need to
+ * ensure that the IRQ signal is deasserted before returning.  This
+ * is rather unfortunate.
+ */
+static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        sa1100_register_uart_fns(&neponset_port_fns);
+        struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
+        unsigned int irr;
 
-        /*
-         * Install handler for GPIO25.
-         */
-        irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
-        irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler);
+        while (1) {
+                /*
+                 * Acknowledge the parent IRQ.
+                 */
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
 
-        /*
-         * We would set IRQ_GPIO25 to be a wake-up IRQ, but
-         * unfortunately something on the Neponset activates
-         * this IRQ on sleep (ethernet?)
-         */
-#if 0
-        enable_irq_wake(IRQ_GPIO25);
-#endif
+                /*
+                 * Read the interrupt reason register.  Let's have all
+                 * active IRQ bits high.  Note: there is a typo in the
+                 * Neponset user's guide for the SA1111 IRR level.
+                 */
+                irr = readb_relaxed(d->base + IRR);
+                irr ^= IRR_ETHERNET | IRR_USAR;
 
-        /*
-         * Setup other Neponset IRQs.  SA1111 will be done by the
-         * generic SA1111 code.
-         */
-        irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
-        set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
-        irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
-        set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
+                if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
+                        break;
 
-        /*
-         * Disable GPIO 0/1 drivers so the buttons work on the module.
-         */
-        NCR_0 = NCR_GP01_OFF;
+                /*
+                 * Since there is no individual mask, we have to
+                 * mask the parent IRQ.  This is safe, since we'll
+                 * recheck the register for any pending IRQs.
+                 */
+                if (irr & (IRR_ETHERNET | IRR_USAR)) {
+                        desc->irq_data.chip->irq_mask(&desc->irq_data);
 
-        return 0;
-}
+                        /*
+                         * Ack the interrupt now to prevent re-entering
+                         * this neponset handler.  Again, this is safe
+                         * since we'll check the IRR register prior to
+                         * leaving.
+                         */
+                        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
-#ifdef CONFIG_PM
+                        if (irr & IRR_ETHERNET)
+                                generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
 
-/*
- * LDM power management.
- */
-static unsigned int neponset_saved_state;
+                        if (irr & IRR_USAR)
+                                generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
 
-static int neponset_suspend(struct platform_device *dev, pm_message_t state)
-{
-        /*
-         * Save state.
-         */
-        neponset_saved_state = NCR_0;
+                        desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                }
 
-        return 0;
+                if (irr & IRR_SA1111)
+                        generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
+        }
 }
 
-static int neponset_resume(struct platform_device *dev)
+/* Yes, we really do not have any kind of masking or unmasking */
+static void nochip_noop(struct irq_data *irq)
 {
-        NCR_0 = neponset_saved_state;
-
-        return 0;
 }
 
-#else
-#define neponset_suspend NULL
-#define neponset_resume  NULL
-#endif
-
-static struct platform_driver neponset_device_driver = {
-        .probe          = neponset_probe,
-        .suspend        = neponset_suspend,
-        .resume         = neponset_resume,
-        .driver         = {
-                .name   = "neponset",
-        },
-};
-
-static struct resource neponset_resources[] = {
-        [0] = {
-                .start  = 0x10000000,
-                .end    = 0x17ffffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device neponset_device = {
-        .name           = "neponset",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(neponset_resources),
-        .resource       = neponset_resources,
-};
-
-static struct resource sa1111_resources[] = {
-        [0] = {
-                .start  = 0x40000000,
-                .end    = 0x40001fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_NEPONSET_SA1111,
-                .end    = IRQ_NEPONSET_SA1111,
-                .flags  = IORESOURCE_IRQ,
-        },
+static struct irq_chip nochip = {
+        .name = "neponset",
+        .irq_ack = nochip_noop,
+        .irq_mask = nochip_noop,
+        .irq_unmask = nochip_noop,
 };
 
 static struct sa1111_platform_data sa1111_info = {
-        .irq_base       = IRQ_BOARD_END,
+        .disable_devs   = SA1111_DEVID_PS2_MSE,
 };
 
-static u64 sa1111_dmamask = 0xffffffffUL;
+static int __devinit neponset_probe(struct platform_device *dev)
+{
+        struct neponset_drvdata *d;
+        struct resource *nep_res, *sa1111_res, *smc91x_res;
+        struct resource sa1111_resources[] = {
+                DEFINE_RES_MEM(0x40000000, SZ_8K),
+                { .flags = IORESOURCE_IRQ },
+        };
+        struct platform_device_info sa1111_devinfo = {
+                .parent = &dev->dev,
+                .name = "sa1111",
+                .id = 0,
+                .res = sa1111_resources,
+                .num_res = ARRAY_SIZE(sa1111_resources),
+                .data = &sa1111_info,
+                .size_data = sizeof(sa1111_info),
+                .dma_mask = 0xffffffffUL,
+        };
+        struct resource smc91x_resources[] = {
+                DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
+                        0x02000000, "smc91x-regs"),
+                DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
+                        0x02000000, "smc91x-attrib"),
+                { .flags = IORESOURCE_IRQ },
+        };
+        struct platform_device_info smc91x_devinfo = {
+                .parent = &dev->dev,
+                .name = "smc91x",
+                .id = 0,
+                .res = smc91x_resources,
+                .num_res = ARRAY_SIZE(smc91x_resources),
+        };
+        int ret, irq;
+
+        if (nep_base)
+                return -EBUSY;
+
+        irq = ret = platform_get_irq(dev, 0);
+        if (ret < 0)
+                goto err_alloc;
+
+        nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+        smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
+        sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
+        if (!nep_res || !smc91x_res || !sa1111_res) {
+                ret = -ENXIO;
+                goto err_alloc;
+        }
 
-static struct platform_device sa1111_device = {
-        .name           = "sa1111",
-        .id             = 0,
-        .dev            = {
-                .dma_mask = &sa1111_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-                .platform_data = &sa1111_info,
-        },
-        .num_resources  = ARRAY_SIZE(sa1111_resources),
-        .resource       = sa1111_resources,
-};
+        d = kzalloc(sizeof(*d), GFP_KERNEL);
+        if (!d) {
+                ret = -ENOMEM;
+                goto err_alloc;
+        }
 
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .name   = "smc91x-regs",
-                .start  = SA1100_CS3_PHYS,
-                .end    = SA1100_CS3_PHYS + 0x01ffffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_NEPONSET_SMC9196,
-                .end    = IRQ_NEPONSET_SMC9196,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .name   = "smc91x-attrib",
-                .start  = SA1100_CS3_PHYS + 0x02000000,
-                .end    = SA1100_CS3_PHYS + 0x03ffffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
+        d->base = ioremap(nep_res->start, SZ_4K);
+        if (!d->base) {
+                ret = -ENOMEM;
+                goto err_ioremap;
+        }
 
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-};
+        if (readb_relaxed(d->base + WHOAMI) != 0x11) {
+                dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
+                         readb_relaxed(d->base + WHOAMI));
+                ret = -ENODEV;
+                goto err_id;
+        }
 
-static struct platform_device *devices[] __initdata = {
-        &neponset_device,
-        &sa1111_device,
-        &smc91x_device,
-};
+        ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
+        if (ret <= 0) {
+                dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
+                        NEP_IRQ_NR, ret);
+                if (ret == 0)
+                        ret = -ENOMEM;
+                goto err_irq_alloc;
+        }
 
-extern void sa1110_mb_disable(void);
+        d->irq_base = ret;
 
-static int __init neponset_init(void)
-{
-        platform_driver_register(&neponset_device_driver);
+        irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
+                handle_simple_irq);
+        set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
+        irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
+                handle_simple_irq);
+        set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
+        irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
 
-        /*
-         * The Neponset is only present on the Assabet machine type.
-         */
-        if (!machine_is_assabet())
-                return -ENODEV;
+        irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
+        irq_set_handler_data(irq, d);
+        irq_set_chained_handler(irq, neponset_irq_handler);
 
         /*
-         * Ensure that the memory bus request/grant signals are setup,
-         * and the grant is held in its inactive state, whether or not
-         * we actually have a Neponset attached.
+         * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
+         * something on the Neponset activates this IRQ on sleep (eth?)
          */
+#if 0
+        enable_irq_wake(irq);
+#endif
+
+        dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
+                 d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
+        nep_base = d->base;
+
+        sa1100_register_uart_fns(&neponset_port_fns);
+
+        /* Ensure that the memory bus request/grant signals are setup */
         sa1110_mb_disable();
 
-        if (!machine_has_neponset()) {
-                printk(KERN_DEBUG "Neponset expansion board not present\n");
-                return -ENODEV;
-        }
+        /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
+        writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
 
-        if (WHOAMI != 0x11) {
-                printk(KERN_WARNING "Neponset board detected, but "
-                        "wrong ID: %02x\n", WHOAMI);
-                return -ENODEV;
-        }
+        sa1111_resources[0].parent = sa1111_res;
+        sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
+        sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
+        d->sa1111 = platform_device_register_full(&sa1111_devinfo);
+
+        smc91x_resources[0].parent = smc91x_res;
+        smc91x_resources[1].parent = smc91x_res;
+        smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
+        smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
+        d->smc91x = platform_device_register_full(&smc91x_devinfo);
+
+        platform_set_drvdata(dev, d);
 
-        return platform_add_devices(devices, ARRAY_SIZE(devices));
+        return 0;
+
+ err_irq_alloc:
+ err_id:
+        iounmap(d->base);
+ err_ioremap:
+        kfree(d);
+ err_alloc:
+        return ret;
 }
 
-subsys_initcall(neponset_init);
+static int __devexit neponset_remove(struct platform_device *dev)
+{
+        struct neponset_drvdata *d = platform_get_drvdata(dev);
+        int irq = platform_get_irq(dev, 0);
+
+        if (!IS_ERR(d->sa1111))
+                platform_device_unregister(d->sa1111);
+        if (!IS_ERR(d->smc91x))
+                platform_device_unregister(d->smc91x);
+        irq_set_chained_handler(irq, NULL);
+        irq_free_descs(d->irq_base, NEP_IRQ_NR);
+        nep_base = NULL;
+        iounmap(d->base);
+        kfree(d);
 
-static struct map_desc neponset_io_desc[] __initdata = {
-        {       /* System Registers */
-                .virtual        =  0xf3000000,
-                .pfn            = __phys_to_pfn(0x10000000),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }, {    /* SA-1111 */
-                .virtual        =  0xf4000000,
-                .pfn            = __phys_to_pfn(0x40000000),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }
+        return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int neponset_suspend(struct device *dev)
+{
+        struct neponset_drvdata *d = dev_get_drvdata(dev);
+
+        d->ncr0 = readb_relaxed(d->base + NCR_0);
+        d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);
+
+        return 0;
+}
+
+static int neponset_resume(struct device *dev)
+{
+        struct neponset_drvdata *d = dev_get_drvdata(dev);
+
+        writeb_relaxed(d->ncr0, d->base + NCR_0);
+        writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);
+
+        return 0;
+}
+
+static const struct dev_pm_ops neponset_pm_ops = {
+        .suspend_noirq = neponset_suspend,
+        .resume_noirq = neponset_resume,
+        .freeze_noirq = neponset_suspend,
+        .restore_noirq = neponset_resume,
+};
+#define PM_OPS &neponset_pm_ops
+#else
+#define PM_OPS NULL
+#endif
+
+static struct platform_driver neponset_device_driver = {
+        .probe          = neponset_probe,
+        .remove         = __devexit_p(neponset_remove),
+        .driver         = {
+                .name   = "neponset",
+                .owner  = THIS_MODULE,
+                .pm     = PM_OPS,
+        },
 };
 
-void __init neponset_map_io(void)
+static int __init neponset_init(void)
 {
-        iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc));
+        return platform_driver_register(&neponset_device_driver);
 }
+
+subsys_initcall(neponset_init);
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index 0d01ca78892..b49108b890a 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -135,12 +135,8 @@ struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys
                                  &sys->resources);
 }
 
-static struct resource pci_io_ports = {
-        .name   = "PCI IO",
-        .start  = 0x400,
-        .end    = 0x7FF,
-        .flags  = IORESOURCE_IO,
-};
+static struct resource pci_io_ports =
+        DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
 
 static struct resource pci_non_prefetchable_memory = {
         .name   = "PCI non-prefetchable",
@@ -244,9 +240,11 @@ static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
                 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
                 return -EBUSY;
         }
-        pci_add_resource(&sys->resources, &pci_io_ports);
-        pci_add_resource(&sys->resources, &pci_non_prefetchable_memory);
-        pci_add_resource(&sys->resources, &pci_prefetchable_memory);
+        pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &pci_non_prefetchable_memory, sys->mem_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &pci_prefetchable_memory, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 9307df05353..1602575a0d5 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -37,17 +37,9 @@
 #define IRQ_GPIO_ETH0_IRQ       IRQ_GPIO21
 
 static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = PLEB_ETH0_P,
-                .end    = PLEB_ETH0_P | 0x03ffffff,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM(PLEB_ETH0_P, 0x04000000),
 #if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */
-        [1] = {
-                .start  = IRQ_GPIO_ETH0_IRQ,
-                .end    = IRQ_GPIO_ETH0_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
+        [1] = DEFINE_RES_IRQ(IRQ_GPIO_ETH0_IRQ),
 #endif
 };
 
@@ -70,16 +62,8 @@ static struct platform_device *devices[] __initdata = {
  * the two SA1100 lowest chip select outputs.
  */
 static struct resource pleb_flash_resources[] = {
-        [0] = {
-                .start = SA1100_CS0_PHYS,
-                .end   = SA1100_CS0_PHYS + SZ_8M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = SA1100_CS1_PHYS,
-                .end   = SA1100_CS1_PHYS + SZ_8M - 1,
-                .flags = IORESOURCE_MEM,
-        }
+        [0] = DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_8M),
+        [1] = DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_8M),
 };
 
 
@@ -147,6 +131,7 @@ static void __init pleb_map_io(void)
 
 MACHINE_START(PLEB, "PLEB")
         .map_io         = pleb_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = pleb_init,
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 318b2b766a0..ca8bf59b904 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -9,6 +9,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 
+#include <video/sa1100fb.h>
+
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
@@ -19,6 +21,7 @@
 #include <asm/mach/serial_sa1100.h>
 #include <mach/mcp.h>
 #include <mach/shannon.h>
+#include <mach/irqs.h>
 
 #include "generic.h"
 
@@ -46,19 +49,32 @@ static struct flash_platform_data shannon_flash_data = {
         .nr_parts       = ARRAY_SIZE(shannon_partitions),
 };
 
-static struct resource shannon_flash_resource = {
-        .start          = SA1100_CS0_PHYS,
-        .end            = SA1100_CS0_PHYS + SZ_4M - 1,
-        .flags          = IORESOURCE_MEM,
-};
+static struct resource shannon_flash_resource =
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_4M);
 
 static struct mcp_plat_data shannon_mcp_data = {
         .mccr0          = MCCR0_ADM,
         .sclk_rate      = 11981000,
 };
 
+static struct sa1100fb_mach_info shannon_lcd_info = {
+        .pixclock       = 152500,       .bpp            = 8,
+        .xres           = 640,          .yres           = 480,
+
+        .hsync_len      = 4,            .vsync_len      = 3,
+        .left_margin    = 2,            .upper_margin   = 0,
+        .right_margin   = 1,            .lower_margin   = 0,
+
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+
+        .lccr0          = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
+        .lccr3          = LCCR3_ACBsDiv(512),
+};
+
 static void __init shannon_init(void)
 {
+        sa11x0_ppc_configure_mcp();
+        sa11x0_register_lcd(&shannon_lcd_info);
         sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
         sa11x0_register_mcp(&shannon_mcp_data);
 }
@@ -84,6 +100,7 @@ static void __init shannon_map_io(void)
 MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
         .atag_offset    = 0x100,
         .map_io         = shannon_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .init_machine   = shannon_init,
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index e17c04d6e32..3efae03cb3d 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -7,15 +7,15 @@
 #include <linux/kernel.h>
 #include <linux/tty.h>
 #include <linux/proc_fs.h>
-#include <linux/string.h> 
+#include <linux/string.h>
 #include <linux/pm.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/ucb1x00.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <asm/irq.h>
 #include <mach/hardware.h>
 #include <asm/setup.h>
 
@@ -26,6 +26,7 @@
 #include <asm/mach/serial_sa1100.h>
 #include <mach/mcp.h>
 #include <mach/simpad.h>
+#include <mach/irqs.h>
 
 #include <linux/serial_core.h>
 #include <linux/ioport.h>
@@ -176,21 +177,18 @@ static struct flash_platform_data simpad_flash_data = {
 
 
 static struct resource simpad_flash_resources [] = {
-        {
-                .start     = SA1100_CS0_PHYS,
-                .end       = SA1100_CS0_PHYS + SZ_16M -1,
-                .flags     = IORESOURCE_MEM,
-        }, {
-                .start     = SA1100_CS1_PHYS,
-                .end       = SA1100_CS1_PHYS + SZ_16M -1,
-                .flags     = IORESOURCE_MEM,
-        }
+        DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_16M),
+        DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_16M),
+};
+
+static struct ucb1x00_plat_data simpad_ucb1x00_data = {
+        .gpio_base      = SIMPAD_UCB1X00_GPIO_BASE,
 };
 
 static struct mcp_plat_data simpad_mcp_data = {
         .mccr0          = MCCR0_ADM,
         .sclk_rate      = 11981000,
-        .gpio_base      = SIMPAD_UCB1X00_GPIO_BASE,
+        .codec_pdata    = &simpad_ucb1x00_data,
 };
 
 
@@ -376,6 +374,7 @@ static int __init simpad_init(void)
 
         pm_power_off = simpad_power_off;
 
+        sa11x0_ppc_configure_mcp();
         sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
                               ARRAY_SIZE(simpad_flash_resources));
         sa11x0_register_mcp(&simpad_mcp_data);
@@ -394,6 +393,7 @@ MACHINE_START(SIMPAD, "Simpad")
         /* Maintainer: Holger Freyther */
         .atag_offset    = 0x100,
         .map_io         = simpad_map_io,
+        .nr_irqs        = SA1100_NR_IRQS,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
         .restart        = sa11x0_restart,
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index e8223315b44..30cc6721665 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -26,27 +26,36 @@
  *
  * Causes sa11x0 to enter sleep state
  *
+ * Must be aligned to a cacheline.
  */
-
+        .balign 32
 ENTRY(sa1100_finish_suspend)
         @ disable clock switching
         mcr     p15, 0, r1, c15, c2, 2
 
-        @ Adjust memory timing before lowering CPU clock
-        @ Clock speed adjustment without changing memory timing makes
-        @ CPU hang in some cases
-        ldr     r0, =MDREFR
-        ldr     r1, [r0]
-        orr     r1, r1, #MDREFR_K1DB2
-        str     r1, [r0]
+        ldr     r6, =MDREFR
+        ldr     r4, [r6]
+        orr     r4, r4, #MDREFR_K1DB2
+        ldr     r5, =PPCR
+
+        @ Pre-load __udelay into the I-cache
+        mov     r0, #1
+        bl      __udelay
+        mov     r0, r0
+
+        @ The following must all exist in a single cache line to
+        @ avoid accessing memory until this sequence is complete,
+        @ otherwise we occasionally hang.
+
+        @ Adjust memory timing before lowering CPU clock
+        str     r4, [r6]
 
         @ delay 90us and set CPU PLL to lowest speed
         @ fixes resume problem on high speed SA1110
         mov     r0, #90
         bl      __udelay
-        ldr     r0, =PPCR
         mov     r1, #0
-        str     r1, [r0]
+        str     r1, [r5]
         mov     r0, #90
         bl      __udelay
 
@@ -85,12 +94,10 @@ ENTRY(sa1100_finish_suspend)
         bic     r5, r5, #FMsk(MSC_RT)
         bic     r5, r5, #FMsk(MSC_RT)<<16
 
-        ldr     r6, =MDREFR
-
         ldr     r7, [r6]
-bic     r7, r7, #0x0000FF00
-bic     r7, r7, #0x000000F0
-orr     r8, r7, #MDREFR_SLFRSH
+        bic     r7, r7, #0x0000FF00
+        bic     r7, r7, #0x000000F0
+        orr     r8, r7, #MDREFR_SLFRSH
 
         ldr     r9, =MDCNFG
         ldr     r10, [r9]
diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c
index b20ff93b84a..e22fca9ad5e 100644
--- a/arch/arm/mach-sa1100/ssp.c
+++ b/arch/arm/mach-sa1100/ssp.c
@@ -19,8 +19,8 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-#include <asm/irq.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 #include <asm/hardware/ssp.h>
 
 #define TIMEOUT 100000
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 69e33535dee..6af26e8d55e 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -18,6 +18,7 @@
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 
 static u32 notrace sa1100_read_sched_clock(void)
 {
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index a851c254ad6..6a2a7f2c255 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -149,10 +149,16 @@ static struct sys_timer shark_timer = {
         .init           = shark_timer_init,
 };
 
+static void shark_init_early(void)
+{
+        disable_hlt();
+}
+
 MACHINE_START(SHARK, "Shark")
         /* Maintainer: Alexander Schulz */
         .atag_offset    = 0x3000,
         .map_io         = shark_map_io,
+        .init_early     = shark_init_early,
         .init_irq       = shark_init_irq,
         .timer          = &shark_timer,
         .dma_zone_size  = SZ_4M,
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index 0bb6cc626eb..5901b09fc96 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -7,16 +7,10 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 mov     \base, #0xe0000000
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \irqstat, #0x0C
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h
deleted file mode 100644
index 1b2f2c5050a..00000000000
--- a/arch/arm/mach-shark/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/system.h
- *
- * by Alexander Schulz
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 7ad6954c46c..e7c2590b75d 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_R8A7779)	+= setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-smp-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
 
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 12c431f3443..f50d7c8b122 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -47,8 +47,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/traps.h>
@@ -477,27 +475,6 @@ static struct platform_device *ag5evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
-static struct map_desc ag5evm_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init ag5evm_map_io(void)
-{
-        iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
-
-        /* setup early devices and console here as well */
-        sh73a0_add_early_devices();
-        shmobile_setup_console();
-}
-
 static void __init ag5evm_init(void)
 {
         sh73a0_pinmux_init();
@@ -613,22 +590,12 @@ static void __init ag5evm_init(void)
         platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
 }
 
-static void __init ag5evm_timer_init(void)
-{
-        sh73a0_clock_init();
-        shmobile_timer.init();
-        return;
-}
-
-struct sys_timer ag5evm_timer = {
-        .init   = ag5evm_timer_init,
-};
-
 MACHINE_START(AG5EVM, "ag5evm")
-        .map_io         = ag5evm_map_io,
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = sh73a0_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = ag5evm_init,
-        .timer          = &ag5evm_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f90ba5b850a..b56dde2732b 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -61,8 +61,6 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/setup.h>
 
 /*
@@ -1188,26 +1186,6 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
-static struct map_desc ap4evb_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init ap4evb_map_io(void)
-{
-        iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
-
-        /* setup early devices and console here as well */
-        sh7372_add_early_devices();
-        shmobile_setup_console();
-}
 
 #define GPIO_PORT9CR    0xE6051009
 #define GPIO_PORT10CR   0xE605100A
@@ -1217,6 +1195,9 @@ static void __init ap4evb_init(void)
         u32 srcr4;
         struct clk *clk;
 
+        /* External clock source */
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1453,23 +1434,11 @@ static void __init ap4evb_init(void)
         pm_clk_add(&lcdc1_device.dev, "hdmi");
 }
 
-static void __init ap4evb_timer_init(void)
-{
-        sh7372_clock_init();
-        shmobile_timer.init();
-
-        /* External clock source */
-        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
-}
-
-static struct sys_timer ap4evb_timer = {
-        .init           = ap4evb_timer_init,
-};
-
 MACHINE_START(AP4EVB, "ap4evb")
-        .map_io         = ap4evb_map_io,
+        .map_io         = sh7372_map_io,
+        .init_early     = sh7372_add_early_devices,
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = ap4evb_init,
-        .timer          = &ap4evb_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index c79baa9ef61..8b2124da245 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -328,28 +328,6 @@ static struct platform_device *bonito_base_devices[] __initdata = {
  * map I/O
  */
 static struct map_desc bonito_io_desc[] __initdata = {
-         /*
-          * for CPGA/INTC/PFC
-          * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
-          */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 160 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-#ifdef CONFIG_CACHE_L2X0
-        /*
-         * for l2x0_init()
-         * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
-         */
-        {
-                .virtual        = 0xf0002000,
-                .pfn            = __phys_to_pfn(0xf0100000),
-                .length         = PAGE_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        },
-#endif
         /*
          * for FPGA (0x1800000-0x19ffffff)
          * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
@@ -364,11 +342,8 @@ static struct map_desc bonito_io_desc[] __initdata = {
 
 static void __init bonito_map_io(void)
 {
+        r8a7740_map_io();
         iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
-
-        /* setup early devices and console here as well */
-        r8a7740_add_early_devices();
-        shmobile_setup_console();
 }
 
 /*
@@ -492,7 +467,7 @@ static void __init bonito_init(void)
         }
 }
 
-static void __init bonito_timer_init(void)
+static void __init bonito_earlytimer_init(void)
 {
         u16 val;
         u8 md_ck = 0;
@@ -507,17 +482,22 @@ static void __init bonito_timer_init(void)
                 md_ck |= MD_CK0;
 
         r8a7740_clock_init(md_ck);
-        shmobile_timer.init();
+        shmobile_earlytimer_init();
 }
 
-struct sys_timer bonito_timer = {
-        .init   = bonito_timer_init,
-};
+void __init bonito_add_early_devices(void)
+{
+        r8a7740_add_early_devices();
+
+        /* override timer setup with board-specific code */
+        shmobile_timer.init = bonito_earlytimer_init;
+}
 
 MACHINE_START(BONITO, "bonito")
         .map_io         = bonito_map_io,
+        .init_early     = bonito_add_early_devices,
         .init_irq       = r8a7740_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = bonito_init,
-        .timer          = &bonito_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 72d557281b1..b627e89037f 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -37,8 +37,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 
 /*
  * IrDA
@@ -246,27 +244,6 @@ static struct platform_device *g3evm_devices[] __initdata = {
         &irda_device,
 };
 
-static struct map_desc g3evm_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init g3evm_map_io(void)
-{
-        iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
-
-        /* setup early devices and console here as well */
-        sh7367_add_early_devices();
-        shmobile_setup_console();
-}
-
 static void __init g3evm_init(void)
 {
         sh7367_pinmux_init();
@@ -354,20 +331,11 @@ static void __init g3evm_init(void)
         platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
 }
 
-static void __init g3evm_timer_init(void)
-{
-        sh7367_clock_init();
-        shmobile_timer.init();
-}
-
-static struct sys_timer g3evm_timer = {
-        .init           = g3evm_timer_init,
-};
-
 MACHINE_START(G3EVM, "g3evm")
-        .map_io         = g3evm_map_io,
+        .map_io         = sh7367_map_io,
+        .init_early     = sh7367_add_early_devices,
         .init_irq       = sh7367_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = g3evm_init,
-        .timer          = &g3evm_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 2220b885cff..46d757d2759 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -38,8 +38,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 
 /*
  * SDHI
@@ -260,27 +258,6 @@ static struct platform_device *g4evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
-static struct map_desc g4evm_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init g4evm_map_io(void)
-{
-        iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
-
-        /* setup early devices and console here as well */
-        sh7377_add_early_devices();
-        shmobile_setup_console();
-}
-
 #define GPIO_SDHID0_D0  0xe60520fc
 #define GPIO_SDHID0_D1  0xe60520fd
 #define GPIO_SDHID0_D2  0xe60520fe
@@ -397,20 +374,11 @@ static void __init g4evm_init(void)
         platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
 }
 
-static void __init g4evm_timer_init(void)
-{
-        sh7377_clock_init();
-        shmobile_timer.init();
-}
-
-static struct sys_timer g4evm_timer = {
-        .init           = g4evm_timer_init,
-};
-
 MACHINE_START(G4EVM, "g4evm")
-        .map_io         = g4evm_map_io,
+        .map_io         = sh7377_map_io,
+        .init_early     = sh7377_add_early_devices,
         .init_irq       = sh7377_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = g4evm_init,
-        .timer          = &g4evm_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index c8e7ca23fc0..61c06729466 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -43,7 +43,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -409,27 +408,6 @@ static struct platform_device *kota2_devices[] __initdata = {
         &sdhi1_device,
 };
 
-static struct map_desc kota2_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init kota2_map_io(void)
-{
-        iotable_init(kota2_io_desc, ARRAY_SIZE(kota2_io_desc));
-
-        /* setup early devices and console here as well */
-        sh73a0_add_early_devices();
-        shmobile_setup_console();
-}
-
 static void __init kota2_init(void)
 {
         sh73a0_pinmux_init();
@@ -535,22 +513,12 @@ static void __init kota2_init(void)
         platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
 }
 
-static void __init kota2_timer_init(void)
-{
-        sh73a0_clock_init();
-        shmobile_timer.init();
-        return;
-}
-
-struct sys_timer kota2_timer = {
-        .init   = kota2_timer_init,
-};
-
 MACHINE_START(KOTA2, "kota2")
-        .map_io         = kota2_map_io,
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = sh73a0_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = kota2_init,
-        .timer          = &kota2_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 865d56d9629..ca609502d6c 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -57,8 +57,6 @@
 #include <mach/sh7372.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 
 /*
@@ -1329,31 +1327,6 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
-static struct map_desc mackerel_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init mackerel_map_io(void)
-{
-        iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
-        /* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
-         * enough to allocate the frame buffer memory.
-         */
-        init_consistent_dma_size(12 << 20);
-
-        /* setup early devices and console here as well */
-        sh7372_add_early_devices();
-        shmobile_setup_console();
-}
-
 #define GPIO_PORT9CR    0xE6051009
 #define GPIO_PORT10CR   0xE605100A
 #define GPIO_PORT167CR  0xE60520A7
@@ -1366,6 +1339,9 @@ static void __init mackerel_init(void)
         struct clk *clk;
         int ret;
 
+        /* External clock source */
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1569,23 +1545,11 @@ static void __init mackerel_init(void)
         pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
 }
 
-static void __init mackerel_timer_init(void)
-{
-        sh7372_clock_init();
-        shmobile_timer.init();
-
-        /* External clock source */
-        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
-}
-
-static struct sys_timer mackerel_timer = {
-        .init           = mackerel_timer_init,
-};
-
 MACHINE_START(MACKEREL, "mackerel")
-        .map_io         = mackerel_map_io,
+        .map_io         = sh7372_map_io,
+        .init_early     = sh7372_add_early_devices,
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = mackerel_init,
-        .timer          = &mackerel_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index f0e02c0ce99..cbd5e4cd06d 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -33,8 +33,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/traps.h>
 
@@ -72,49 +70,6 @@ static struct platform_device *marzen_devices[] __initdata = {
         &eth_device,
 };
 
-static struct map_desc marzen_io_desc[] __initdata = {
-        /* 2M entity map for 0xf0000000 (MPCORE) */
-        {
-                .virtual        = 0xf0000000,
-                .pfn            = __phys_to_pfn(0xf0000000),
-                .length         = SZ_2M,
-                .type           = MT_DEVICE_NONSHARED
-        },
-        /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
-        {
-                .virtual        = 0xfe000000,
-                .pfn            = __phys_to_pfn(0xfe000000),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init marzen_map_io(void)
-{
-        iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
-}
-
-static void __init marzen_init_early(void)
-{
-        r8a7779_add_early_devices();
-
-        /* Early serial console setup is not included here due to
-         * memory map collisions. The SCIF serial ports in r8a7779
-         * are difficult to entity map 1:1 due to collision with the
-         * virtual memory range used by the coherent DMA code on ARM.
-         *
-         * Anyone wanting to debug early can remove UPF_IOREMAP from
-         * the sh-sci serial console platform data, adjust mapbase
-         * to a static M:N virt:phys mapping that needs to be added to
-         * the mappings passed with iotable_init() above.
-         *
-         * Then add a call to shmobile_setup_console() from this function.
-         *
-         * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
-         * command line.
-         */
-}
-
 static void __init marzen_init(void)
 {
         r8a7779_pinmux_init();
@@ -135,23 +90,12 @@ static void __init marzen_init(void)
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
 
-static void __init marzen_timer_init(void)
-{
-        r8a7779_clock_init();
-        shmobile_timer.init();
-        return;
-}
-
-struct sys_timer marzen_timer = {
-        .init   = marzen_timer_init,
-};
-
 MACHINE_START(MARZEN, "marzen")
-        .map_io         = marzen_map_io,
-        .init_early     = marzen_init_early,
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = marzen_init,
-        .timer          = &marzen_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 3b35b9afc00..99c4d743a99 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -93,7 +93,7 @@ static unsigned long div_recalc(struct clk *clk)
         return clk->parent->rate / (int)(clk->priv);
 }
 
-static struct clk_ops div_clk_ops = {
+static struct sh_clk_ops div_clk_ops = {
         .recalc = div_recalc,
 };
 
@@ -125,7 +125,7 @@ static struct clk extal2_div2_clk = {
         .parent = &extal2_clk,
 };
 
-static struct clk_ops followparent_clk_ops = {
+static struct sh_clk_ops followparent_clk_ops = {
         .recalc = followparent_recalc,
 };
 
@@ -156,7 +156,7 @@ static unsigned long pllc01_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc01_clk_ops = {
+static struct sh_clk_ops pllc01_clk_ops = {
         .recalc         = pllc01_recalc,
 };
 
@@ -376,7 +376,7 @@ void __init r8a7740_clock_init(u8 md_ck)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup r8a7740 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b4b0e8cd096..7d6e9fe47b5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -107,7 +107,7 @@ static unsigned long mul4_recalc(struct clk *clk)
         return clk->parent->rate * 4;
 }
 
-static struct clk_ops mul4_clk_ops = {
+static struct sh_clk_ops mul4_clk_ops = {
         .recalc         = mul4_recalc,
 };
 
@@ -170,7 +170,7 @@ void __init r8a7779_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup r8a7779 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 5218c34a9cc..006e7b5d304 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -74,7 +74,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -101,7 +101,7 @@ static unsigned long pllc1_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc1_clk_ops = {
+static struct sh_clk_ops pllc1_clk_ops = {
         .recalc         = pllc1_recalc,
 };
 
@@ -128,7 +128,7 @@ static unsigned long pllc2_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc2_clk_ops = {
+static struct sh_clk_ops pllc2_clk_ops = {
         .recalc         = pllc2_recalc,
 };
 
@@ -349,7 +349,7 @@ void __init sh7367_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh7367 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 293456d8dcf..de243e3c839 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -89,7 +89,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -128,7 +128,7 @@ static unsigned long pllc01_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc01_clk_ops = {
+static struct sh_clk_ops pllc01_clk_ops = {
         .recalc         = pllc01_recalc,
 };
 
@@ -276,7 +276,7 @@ static int pllc2_set_parent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
-static struct clk_ops pllc2_clk_ops = {
+static struct sh_clk_ops pllc2_clk_ops = {
         .recalc         = pllc2_recalc,
         .round_rate     = pllc2_round_rate,
         .set_rate       = pllc2_set_rate,
@@ -468,7 +468,7 @@ static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops fsidiv_clk_ops = {
+static struct sh_clk_ops fsidiv_clk_ops = {
         .recalc         = fsidiv_recalc,
         .round_rate     = fsidiv_round_rate,
         .set_rate       = fsidiv_set_rate,
@@ -710,7 +710,7 @@ void __init sh7372_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh7372 clocks\n");
 
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 8cee7b151ae..0798a15936c 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -77,7 +77,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -110,7 +110,7 @@ static unsigned long pllc1_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc1_clk_ops = {
+static struct sh_clk_ops pllc1_clk_ops = {
         .recalc         = pllc1_recalc,
 };
 
@@ -137,7 +137,7 @@ static unsigned long pllc2_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc2_clk_ops = {
+static struct sh_clk_ops pllc2_clk_ops = {
         .recalc         = pllc2_recalc,
 };
 
@@ -360,7 +360,7 @@ void __init sh7377_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh7377 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7727cca6136..472d1f5361e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -88,7 +88,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -97,7 +97,7 @@ static unsigned long div7_recalc(struct clk *clk)
         return clk->parent->rate / 7;
 }
 
-static struct clk_ops div7_clk_ops = {
+static struct sh_clk_ops div7_clk_ops = {
         .recalc         = div7_recalc,
 };
 
@@ -106,7 +106,7 @@ static unsigned long div13_recalc(struct clk *clk)
         return clk->parent->rate / 13;
 }
 
-static struct clk_ops div13_clk_ops = {
+static struct sh_clk_ops div13_clk_ops = {
         .recalc         = div13_recalc,
 };
 
@@ -122,7 +122,7 @@ static struct clk extal2_div2_clk = {
         .parent         = &sh73a0_extal2_clk,
 };
 
-static struct clk_ops main_clk_ops = {
+static struct sh_clk_ops main_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
@@ -156,7 +156,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
@@ -438,7 +438,7 @@ static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops dsiphy_clk_ops = {
+static struct sh_clk_ops dsiphy_clk_ops = {
         .recalc         = dsiphy_recalc,
         .round_rate     = dsiphy_round_rate,
         .set_rate       = dsiphy_set_rate,
@@ -620,7 +620,7 @@ void __init sh73a0_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh73a0 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index 31654d78b96..e816ca9bd21 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -24,7 +24,7 @@
 #include <linux/sh_clk.h>
 #include <linux/export.h>
 
-int __init clk_init(void)
+int __init shmobile_clk_init(void)
 {
         /* Kick the child clocks.. */
         recalculate_root_clocks();
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e4b945e271e..83ad3fe0a75 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -1,12 +1,15 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
+extern void shmobile_earlytimer_init(void);
 extern struct sys_timer shmobile_timer;
+struct twd_local_timer;
+void shmobile_twd_init(struct twd_local_timer *twd_local_timer);
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
 extern int shmobile_platform_cpu_kill(unsigned int cpu);
 struct clk;
-extern int clk_init(void);
+extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_driver;
@@ -14,6 +17,7 @@ extern void (*shmobile_cpuidle_modes[])(void);
 extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
 
 extern void sh7367_init_irq(void);
+extern void sh7367_map_io(void);
 extern void sh7367_add_early_devices(void);
 extern void sh7367_add_standard_devices(void);
 extern void sh7367_clock_init(void);
@@ -22,6 +26,7 @@ extern struct clk sh7367_extalb1_clk;
 extern struct clk sh7367_extal2_clk;
 
 extern void sh7377_init_irq(void);
+extern void sh7377_map_io(void);
 extern void sh7377_add_early_devices(void);
 extern void sh7377_add_standard_devices(void);
 extern void sh7377_clock_init(void);
@@ -30,6 +35,7 @@ extern struct clk sh7377_extalc1_clk;
 extern struct clk sh7377_extal2_clk;
 
 extern void sh7372_init_irq(void);
+extern void sh7372_map_io(void);
 extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
 extern void sh7372_clock_init(void);
@@ -41,6 +47,7 @@ extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
 extern void sh73a0_init_irq(void);
+extern void sh73a0_map_io(void);
 extern void sh73a0_add_early_devices(void);
 extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_clock_init(void);
@@ -56,12 +63,14 @@ extern int sh73a0_boot_secondary(unsigned int cpu);
 extern void sh73a0_smp_prepare_cpus(void);
 
 extern void r8a7740_init_irq(void);
+extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 
 extern void r8a7779_init_irq(void);
+extern void r8a7779_map_io(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_clock_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
deleted file mode 100644
index 2a57b2964ee..00000000000
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010  Paul Mundt
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 92042703b94..540eaff08f3 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -3,11 +3,6 @@
 
 #include <asm/system_misc.h>
 
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
 static inline void arch_reset(char mode, const char *cmd)
 {
         soft_restart(0);
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
deleted file mode 100644
index ad9ccc9900c..00000000000
--- a/arch/arm/mach-shmobile/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * SMP support for R-Mobile / SH-Mobile - local timer portion
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = 29;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 993381257f6..45fa3924c6a 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -17,7 +17,6 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/hardware/gic.h>
-#include <asm/localtimer.h>
 #include <asm/mach-types.h>
 #include <mach/common.h>
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 986dca6b3fa..74e52341dd1 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -25,8 +25,41 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
 #include <mach/r8a7740.h>
+#include <mach/common.h>
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc r8a7740_io_desc[] __initdata = {
+         /*
+          * for CPGA/INTC/PFC
+          * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
+          */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 160 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * for l2x0_init()
+         * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
+         */
+        {
+                .virtual        = 0xf0002000,
+                .pfn            = __phys_to_pfn(0xf0100000),
+                .length         = PAGE_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        },
+#endif
+};
+
+void __init r8a7740_map_io(void)
+{
+        iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -345,8 +378,20 @@ void __init r8a7740_add_standard_devices(void)
                              ARRAY_SIZE(r8a7740_late_devices));
 }
 
+static void __init r8a7740_earlytimer_init(void)
+{
+        r8a7740_clock_init(0);
+        shmobile_earlytimer_init();
+}
+
 void __init r8a7740_add_early_devices(void)
 {
         early_platform_add_devices(r8a7740_early_devices,
                                    ARRAY_SIZE(r8a7740_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = r8a7740_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 4725663bd03..6820d785493 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -33,6 +33,31 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static struct map_desc r8a7779_io_desc[] __initdata = {
+        /* 2M entity map for 0xf0000000 (MPCORE) */
+        {
+                .virtual        = 0xf0000000,
+                .pfn            = __phys_to_pfn(0xf0000000),
+                .length         = SZ_2M,
+                .type           = MT_DEVICE_NONSHARED
+        },
+        /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
+        {
+                .virtual        = 0xfe000000,
+                .pfn            = __phys_to_pfn(0xfe000000),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init r8a7779_map_io(void)
+{
+        iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
+}
 
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe40000,
@@ -219,6 +244,10 @@ static struct platform_device *r8a7779_late_devices[] __initdata = {
 
 void __init r8a7779_add_standard_devices(void)
 {
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 64K*16way */
+        l2x0_init((void __iomem __force *)(0xf0100000), 0x40470000, 0x82000fff);
+#endif
         r8a7779_pm_init();
 
         r8a7779_init_pm_domain(&r8a7779_sh4a);
@@ -232,8 +261,33 @@ void __init r8a7779_add_standard_devices(void)
                             ARRAY_SIZE(r8a7779_late_devices));
 }
 
+static void __init r8a7779_earlytimer_init(void)
+{
+        r8a7779_clock_init();
+        shmobile_earlytimer_init();
+}
+
 void __init r8a7779_add_early_devices(void)
 {
         early_platform_add_devices(r8a7779_early_devices,
                                    ARRAY_SIZE(r8a7779_early_devices));
+
+        /* Early serial console setup is not included here due to
+         * memory map collisions. The SCIF serial ports in r8a7779
+         * are difficult to entity map 1:1 due to collision with the
+         * virtual memory range used by the coherent DMA code on ARM.
+         *
+         * Anyone wanting to debug early can remove UPF_IOREMAP from
+         * the sh-sci serial console platform data, adjust mapbase
+         * to a static M:N virt:phys mapping that needs to be added to
+         * the mappings passed with iotable_init() above.
+         *
+         * Then add a call to shmobile_setup_console() from this function.
+         *
+         * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
+         * command line in case of the marzen board.
+         */
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = r8a7779_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index e546017f15d..a51e1a1e699 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -29,8 +29,28 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh7367_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh7367_map_io(void)
+{
+        iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -435,6 +455,12 @@ void __init sh7367_add_standard_devices(void)
                             ARRAY_SIZE(sh7367_devices));
 }
 
+static void __init sh7367_earlytimer_init(void)
+{
+        sh7367_clock_init();
+        shmobile_earlytimer_init();
+}
+
 #define SYMSTPCR2 0xe6158048
 #define SYMSTPCR2_CMT1 (1 << 29)
 
@@ -445,4 +471,10 @@ void __init sh7367_add_early_devices(void)
 
         early_platform_add_devices(sh7367_early_devices,
                                    ARRAY_SIZE(sh7367_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh7367_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index cccf91b8fae..4e818b7de78 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -31,10 +31,37 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/pm_domain.h>
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/sh7372.h>
+#include <mach/common.h>
+#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh7372_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh7372_map_io(void)
+{
+        iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
+
+        /*
+         * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
+         * enough to allocate the frame buffer memory.
+         */
+        init_consistent_dma_size(12 << 20);
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -1047,8 +1074,20 @@ void __init sh7372_add_standard_devices(void)
         sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
 }
 
+static void __init sh7372_earlytimer_init(void)
+{
+        sh7372_clock_init();
+        shmobile_earlytimer_init();
+}
+
 void __init sh7372_add_early_devices(void)
 {
         early_platform_add_devices(sh7372_early_devices,
                                    ARRAY_SIZE(sh7372_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh7372_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index bb405b8e459..9f146095098 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -30,8 +30,28 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh7377_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh7377_map_io(void)
+{
+        iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -456,6 +476,12 @@ void __init sh7377_add_standard_devices(void)
                             ARRAY_SIZE(sh7377_devices));
 }
 
+static void __init sh7377_earlytimer_init(void)
+{
+        sh7377_clock_init();
+        shmobile_earlytimer_init();
+}
+
 #define SMSTPCR3 0xe615013c
 #define SMSTPCR3_CMT1 (1 << 29)
 
@@ -466,4 +492,10 @@ void __init sh7377_add_early_devices(void)
 
         early_platform_add_devices(sh7377_early_devices,
                                    ARRAY_SIZE(sh7377_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh7377_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 20e71e5cace..b6a0734a738 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -32,8 +32,28 @@
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
 #include <mach/sh73a0.h>
+#include <mach/common.h>
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh73a0_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh73a0_map_io(void)
+{
+        iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
+}
 
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xe6c40000,
@@ -667,8 +687,20 @@ void __init sh73a0_add_standard_devices(void)
                             ARRAY_SIZE(sh73a0_late_devices));
 }
 
+static void __init sh73a0_earlytimer_init(void)
+{
+        sh73a0_clock_init();
+        shmobile_earlytimer_init();
+}
+
 void __init sh73a0_add_early_devices(void)
 {
         early_platform_add_devices(sh73a0_early_devices,
                                    ARRAY_SIZE(sh73a0_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh73a0_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 4fe2e9eaf50..9bb7b8575a1 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -64,6 +64,8 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(scu_lock);
 static unsigned long tmp;
 
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
         void __iomem *scu_base = scu_base_addr();
@@ -82,11 +84,7 @@ unsigned int __init r8a7779_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
 
-#ifdef CONFIG_HAVE_ARM_TWD
-        /* twd_base needs to be initialized before percpu_timer_setup() */
-        twd_base = (void __iomem *)0xf0000600;
-#endif
-
+        shmobile_twd_init(&twd_local_timer);
         return scu_get_core_count(scu_base);
 }
 
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 2d0d4212be4..c0a9093ba3a 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -42,6 +42,8 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(scu_lock);
 static unsigned long tmp;
 
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
         void __iomem *scu_base = scu_base_addr();
@@ -60,11 +62,7 @@ unsigned int __init sh73a0_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
 
-#ifdef CONFIG_HAVE_ARM_TWD
-        /* twd_base needs to be initialized before percpu_timer_setup() */
-        twd_base = (void __iomem *)0xf0000600;
-#endif
-
+        shmobile_twd_init(&twd_local_timer);
         return scu_get_core_count(scu_base);
 }
 
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 895794b543c..2fba5f3d1c8 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -20,6 +20,7 @@
  */
 #include <linux/platform_device.h>
 #include <asm/mach/time.h>
+#include <asm/smp_twd.h>
 
 static void __init shmobile_late_time_init(void)
 {
@@ -36,11 +37,24 @@ static void __init shmobile_late_time_init(void)
         early_platform_driver_probe("earlytimer", 2, 0);
 }
 
-static void __init shmobile_timer_init(void)
+void __init shmobile_earlytimer_init(void)
 {
         late_time_init = shmobile_late_time_init;
 }
 
+static void __init shmobile_timer_init(void)
+{
+}
+
+void __init shmobile_twd_init(struct twd_local_timer *twd_local_timer)
+{
+#ifdef CONFIG_HAVE_ARM_TWD
+        int err = twd_local_timer_register(twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+#endif
+}
+
 struct sys_timer shmobile_timer = {
         .init           = shmobile_timer_init,
 };
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
deleted file mode 100644
index de3bb41c8e9..00000000000
--- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h
deleted file mode 100644
index 92cee6335c9..00000000000
--- a/arch/arm/mach-spear3xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/system.h
- *
- * SPEAr3xx Machine family specific architecture functions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
-
-#include <plat/system.h>
-
-#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 4f7f5182dd4..f7db66812ab 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -430,18 +430,8 @@ static struct pl061_platform_data gpio1_plat_data = {
         .irq_base       = SPEAR300_GPIO1_INT_BASE,
 };
 
-struct amba_device spear300_gpio1_device = {
-        .dev = {
-                .init_name = "gpio1",
-                .platform_data = &gpio1_plat_data,
-        },
-        .res = {
-                .start = SPEAR300_GPIO_BASE,
-                .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
-};
+AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
+        {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
 
 /* spear300 routines */
 void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 10af45da86a..b1733c37f20 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -28,31 +28,12 @@ static struct pl061_platform_data gpio_plat_data = {
         .irq_base       = SPEAR3XX_GPIO_INT_BASE,
 };
 
-struct amba_device spear3xx_gpio_device = {
-        .dev = {
-                .init_name = "gpio",
-                .platform_data = &gpio_plat_data,
-        },
-        .res = {
-                .start = SPEAR3XX_ICM3_GPIO_BASE,
-                .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
-};
+AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
+        {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
 
 /* uart device registration */
-struct amba_device spear3xx_uart_device = {
-        .dev = {
-                .init_name = "uart",
-        },
-        .res = {
-                .start = SPEAR3XX_ICM1_UART_BASE,
-                .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
-};
+AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
+        {SPEAR3XX_IRQ_UART}, NULL);
 
 /* Do spear3xx familiy common initialization part here */
 void __init spear3xx_init(void)
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index ff4ae5ba00f..fbe298bd1d9 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -5,11 +5,12 @@
 if ARCH_SPEAR6XX
 
 menu "SPEAr6xx Implementations"
-config BOARD_SPEAR600_EVB
-        bool "SPEAr600 Evaluation Board"
+config BOARD_SPEAR600_DT
+        bool "SPEAr600 generic board configured via device-tree"
         select MACH_SPEAR600
+        select USE_OF
         help
-          Supports ST SPEAr600 Evaluation Board
+          Supports ST SPEAr600 boards configured via the device-tree
 
 endmenu
 
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index cc1a4d82d45..76e5750552f 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -4,9 +4,3 @@
 
 # common files
 obj-y   += clock.o spear6xx.o
-
-# spear600 specific files
-obj-$(CONFIG_MACH_SPEAR600) += spear600.o
-
-# spear600 boards files
-obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index ac70e0d88fe..358f2800f17 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
         { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
         { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
         { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
-        { .dev_id = "uart0",            .clk = &uart0_clk},
-        { .dev_id = "uart1",            .clk = &uart1_clk},
+        { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
+        { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
         { .dev_id = "firda",            .clk = &firda_clk},
         { .dev_id = "clcd",             .clk = &clcd_clk},
         { .dev_id = "gpt0",             .clk = &gpt0_clk},
@@ -655,20 +655,20 @@ static struct clk_lookup spear_clk_lookups[] = {
         { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
         /* clock derived from ahb clk */
         { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
+        { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
         { .dev_id = "dma",              .clk = &dma_clk},
         { .dev_id = "jpeg",             .clk = &jpeg_clk},
         { .dev_id = "gmac",             .clk = &gmac_clk},
         { .dev_id = "smi",              .clk = &smi_clk},
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
+        { .dev_id = "fsmc-nand",        .clk = &fsmc_clk},
         /* clock derived from apb clk */
         { .dev_id = "adc",              .clk = &adc_clk},
         { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
         { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
         { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-        { .dev_id = "gpio0",            .clk = &gpio0_clk},
-        { .dev_id = "gpio1",            .clk = &gpio1_clk},
-        { .dev_id = "gpio2",            .clk = &gpio2_clk},
+        { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
+        { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
+        { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
 };
 
 void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
deleted file mode 100644
index d490a910d92..00000000000
--- a/arch/arm/mach-spear6xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-spear6xx/include/mach/system.h b/arch/arm/mach-spear6xx/include/mach/system.h
deleted file mode 100644
index 0b1d2be81cf..00000000000
--- a/arch/arm/mach-spear6xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/system.h
- *
- * SPEAr6xx Machine family specific architecture functions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
-
-#include <plat/system.h>
-
-#endif  /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c
deleted file mode 100644
index d0e6eeae9b0..00000000000
--- a/arch/arm/mach-spear6xx/spear600.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600.c
- *
- * SPEAr600 machine source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/ptrace.h>
-#include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear600 specific devices here */
-
-void __init spear600_init(void)
-{
-        /* call spear6xx family common init function */
-        spear6xx_init();
-}
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
deleted file mode 100644
index c6e4254741c..00000000000
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600_evb.c
- *
- * SPEAr600 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-static struct amba_device *amba_devs[] __initdata = {
-        &gpio_device[0],
-        &gpio_device[1],
-        &gpio_device[2],
-        &uart_device[0],
-        &uart_device[1],
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-};
-
-static void __init spear600_evb_init(void)
-{
-        unsigned int i;
-
-        /* call spear600 machine init function */
-        spear600_init();
-
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear6xx_map_io,
-        .init_irq       =       spear6xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear6xx_timer,
-        .init_machine   =       spear600_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628c8b2..2ed8b14c82c 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -6,111 +6,21 @@
  * Copyright (C) 2009 ST Microelectronics
  * Rajeev Kumar<rajeev-dlh.kumar@st.com>
  *
+ * Copyright 2012 Stefan Roese <sr@denx.de>
+ *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
-#include <mach/irqs.h>
-
-/* Add spear6xx machines common devices here */
-/* uart device registration */
-struct amba_device uart_device[] = {
-        {
-                .dev = {
-                        .init_name = "uart0",
-                },
-                .res = {
-                        .start = SPEAR6XX_ICM1_UART0_BASE,
-                        .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-                .irq = {IRQ_UART_0, NO_IRQ},
-        }, {
-                .dev = {
-                        .init_name = "uart1",
-                },
-                .res = {
-                        .start = SPEAR6XX_ICM1_UART1_BASE,
-                        .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-                .irq = {IRQ_UART_1, NO_IRQ},
-        }
-};
-
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data[] = {
-        {
-                .gpio_base      = 0,
-                .irq_base       = SPEAR_GPIO0_INT_BASE,
-        }, {
-                .gpio_base      = 8,
-                .irq_base       = SPEAR_GPIO1_INT_BASE,
-        }, {
-                .gpio_base      = 16,
-                .irq_base       = SPEAR_GPIO2_INT_BASE,
-        },
-};
-
-struct amba_device gpio_device[] = {
-        {
-                .dev = {
-                        .init_name = "gpio0",
-                        .platform_data = &gpio_plat_data[0],
-                },
-                .res = {
-                        .start = SPEAR6XX_CPU_GPIO_BASE,
-                        .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-                .irq = {IRQ_LOCAL_GPIO, NO_IRQ},
-        }, {
-                .dev = {
-                        .init_name = "gpio1",
-                        .platform_data = &gpio_plat_data[1],
-                },
-                .res = {
-                        .start = SPEAR6XX_ICM3_GPIO_BASE,
-                        .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-                .irq = {IRQ_BASIC_GPIO, NO_IRQ},
-        }, {
-                .dev = {
-                        .init_name = "gpio2",
-                        .platform_data = &gpio_plat_data[2],
-                },
-                .res = {
-                        .start = SPEAR6XX_ICM2_GPIO_BASE,
-                        .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-                .irq = {IRQ_APPL_GPIO, NO_IRQ},
-        }
-};
-
-/* This will add devices, and do machine specific tasks */
-void __init spear6xx_init(void)
-{
-        /* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear6xx_init_irq(void)
-{
-        vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0);
-        vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0);
-}
 
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
@@ -181,3 +91,33 @@ static void __init spear6xx_timer_init(void)
 struct sys_timer spear6xx_timer = {
         .init = spear6xx_timer_init,
 };
+
+static void __init spear600_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *spear600_dt_board_compat[] = {
+        "st,spear600",
+        NULL
+};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+        { /* Sentinel */ }
+};
+
+static void __init spear6xx_dt_init_irq(void)
+{
+        of_irq_init(vic_of_match);
+}
+
+DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
+        .map_io         =       spear6xx_map_io,
+        .init_irq       =       spear6xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear6xx_timer,
+        .init_machine   =       spear600_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear600_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 32b420a90c3..d0f2546706c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,8 +10,16 @@ config ARCH_TEGRA_2x_SOC
         select PINCTRL
         select PINCTRL_TEGRA20
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB_SUPPORT
+        select USB_ULPI if USB
         select USB_ULPI_VIEWPORT if USB_SUPPORT
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_742230
+        select ARM_ERRATA_751472
+        select ARM_ERRATA_754327
+        select ARM_ERRATA_764369
+        select PL310_ERRATA_727915 if CACHE_L2X0
+        select PL310_ERRATA_769419 if CACHE_L2X0
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Support for NVIDIA Tegra AP20 and T20 processors, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -24,9 +32,15 @@ config ARCH_TEGRA_3x_SOC
         select PINCTRL
         select PINCTRL_TEGRA30
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB_SUPPORT
+        select USB_ULPI if USB
         select USB_ULPI_VIEWPORT if USB_SUPPORT
         select USE_OF
+        select ARM_ERRATA_743622
+        select ARM_ERRATA_751472
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_764369
+        select PL310_ERRATA_769419 if CACHE_L2X0
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Support for NVIDIA Tegra T30 processor family, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e120ff54f66..d87d968115e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,15 +7,21 @@ obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += pinmux.o
 obj-y                                   += fuse.o
+obj-y                                   += pmc.o
+obj-y                                   += flowctrl.o
+obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
+obj-$(CONFIG_CPU_IDLE)                  += sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
-obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
+obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
+obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
+obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o apbio.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
new file mode 100644
index 00000000000..e75451e517b
--- /dev/null
+++ b/arch/arm/mach-tegra/apbio.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2010 NVIDIA Corporation.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/sched.h>
+#include <linux/mutex.h>
+
+#include <mach/dma.h>
+#include <mach/iomap.h>
+
+#include "apbio.h"
+
+static DEFINE_MUTEX(tegra_apb_dma_lock);
+
+static struct tegra_dma_channel *tegra_apb_dma;
+static u32 *tegra_apb_bb;
+static dma_addr_t tegra_apb_bb_phys;
+static DECLARE_COMPLETION(tegra_apb_wait);
+
+bool tegra_apb_init(void)
+{
+        struct tegra_dma_channel *ch;
+
+        mutex_lock(&tegra_apb_dma_lock);
+
+        /* Check to see if we raced to setup */
+        if (tegra_apb_dma)
+                goto out;
+
+        ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
+                TEGRA_DMA_SHARED);
+
+        if (!ch)
+                goto out_fail;
+
+        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
+                &tegra_apb_bb_phys, GFP_KERNEL);
+        if (!tegra_apb_bb) {
+                pr_err("%s: can not allocate bounce buffer\n", __func__);
+                tegra_dma_free_channel(ch);
+                goto out_fail;
+        }
+
+        tegra_apb_dma = ch;
+out:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return true;
+
+out_fail:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return false;
+}
+
+static void apb_dma_complete(struct tegra_dma_req *req)
+{
+        complete(&tegra_apb_wait);
+}
+
+u32 tegra_apb_readl(unsigned long offset)
+{
+        struct tegra_dma_req req;
+        int ret;
+
+        if (!tegra_apb_dma && !tegra_apb_init())
+                return readl(IO_TO_VIRT(offset));
+
+        mutex_lock(&tegra_apb_dma_lock);
+        req.complete = apb_dma_complete;
+        req.to_memory = 1;
+        req.dest_addr = tegra_apb_bb_phys;
+        req.dest_bus_width = 32;
+        req.dest_wrap = 1;
+        req.source_addr = offset;
+        req.source_bus_width = 32;
+        req.source_wrap = 4;
+        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
+        req.size = 4;
+
+        INIT_COMPLETION(tegra_apb_wait);
+
+        tegra_dma_enqueue_req(tegra_apb_dma, &req);
+
+        ret = wait_for_completion_timeout(&tegra_apb_wait,
+                msecs_to_jiffies(50));
+
+        if (WARN(ret == 0, "apb read dma timed out")) {
+                tegra_dma_dequeue_req(tegra_apb_dma, &req);
+                *(u32 *)tegra_apb_bb = 0;
+        }
+
+        mutex_unlock(&tegra_apb_dma_lock);
+        return *((u32 *)tegra_apb_bb);
+}
+
+void tegra_apb_writel(u32 value, unsigned long offset)
+{
+        struct tegra_dma_req req;
+        int ret;
+
+        if (!tegra_apb_dma && !tegra_apb_init()) {
+                writel(value, IO_TO_VIRT(offset));
+                return;
+        }
+
+        mutex_lock(&tegra_apb_dma_lock);
+        *((u32 *)tegra_apb_bb) = value;
+        req.complete = apb_dma_complete;
+        req.to_memory = 0;
+        req.dest_addr = offset;
+        req.dest_wrap = 4;
+        req.dest_bus_width = 32;
+        req.source_addr = tegra_apb_bb_phys;
+        req.source_bus_width = 32;
+        req.source_wrap = 1;
+        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
+        req.size = 4;
+
+        INIT_COMPLETION(tegra_apb_wait);
+
+        tegra_dma_enqueue_req(tegra_apb_dma, &req);
+
+        ret = wait_for_completion_timeout(&tegra_apb_wait,
+                msecs_to_jiffies(50));
+
+        if (WARN(ret == 0, "apb write dma timed out"))
+                tegra_dma_dequeue_req(tegra_apb_dma, &req);
+
+        mutex_unlock(&tegra_apb_dma_lock);
+}
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/apbio.h
index a312988bf6f..8b49e8c89a6 100644
--- a/arch/arm/mach-tegra/include/mach/system.h
+++ b/arch/arm/mach-tegra/apbio.h
@@ -1,12 +1,7 @@
 /*
- * arch/arm/mach-tegra/include/mach/system.h
- *
+ * Copyright (C) 2010 NVIDIA Corporation.
  * Copyright (C) 2010 Google, Inc.
  *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
@@ -18,11 +13,27 @@
  *
  */
 
-#ifndef __MACH_TEGRA_SYSTEM_H
-#define __MACH_TEGRA_SYSTEM_H
+#ifndef __MACH_TEGRA_APBIO_H
+#define __MACH_TEGRA_APBIO_H
+
+#ifdef CONFIG_TEGRA_SYSTEM_DMA
+
+u32 tegra_apb_readl(unsigned long offset);
+void tegra_apb_writel(u32 value, unsigned long offset);
+
+#else
+#include <asm/io.h>
+#include <mach/io.h>
 
-static inline void arch_idle(void)
+static inline u32 tegra_apb_readl(unsigned long offset)
 {
+        return readl(IO_TO_VIRT(offset));
 }
 
+static inline void tegra_apb_writel(u32 value, unsigned long offset)
+{
+        writel(value, IO_TO_VIRT(offset));
+}
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 7a95e0bc4ab..e20b419d598 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -131,11 +131,7 @@ static void __init tegra_dt_init(void)
 }
 
 static const char *tegra20_dt_board_compat[] = {
-        "compulab,trimslice",
-        "nvidia,harmony",
-        "compal,paz00",
-        "nvidia,seaboard",
-        "nvidia,ventana",
+        "nvidia,tegra20",
         NULL
 };
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 3c197e2440b..5f7c03e972f 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -34,20 +34,42 @@
 #include <asm/hardware/gic.h>
 
 #include "board.h"
+#include "clock.h"
 
 static struct of_device_id tegra_dt_match_table[] __initdata = {
         { .compatible = "simple-bus", },
         {}
 };
 
+struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
+        {}
+};
+
+static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
+        /* name         parent          rate            enabled */
+        { "uarta",      "pll_p",        408000000,      true },
+        { NULL,         NULL,           0,              0},
+};
+
 static void __init tegra30_dt_init(void)
 {
+        tegra_clk_init_from_table(tegra_dt_clk_init_table);
+
         of_platform_populate(NULL, tegra_dt_match_table,
-                                NULL, NULL);
+                                tegra30_auxdata_lookup, NULL);
 }
 
 static const char *tegra30_dt_board_compat[] = {
-        "nvidia,cardhu",
+        "nvidia,tegra30",
         NULL
 };
 
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c8ac0..1af85bccc0f 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -53,7 +53,7 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
@@ -112,10 +112,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
index 21d1285731b..82f32300796 100644
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ b/arch/arm/mach-tegra/board-harmony-power.c
@@ -18,31 +18,27 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/io.h>
 #include <linux/regulator/machine.h>
 #include <linux/mfd/tps6586x.h>
 
-#include <mach/iomap.h>
 #include <mach/irqs.h>
 
 #include "board-harmony.h"
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_INTR_LOW       (1 << 17)
-
 static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
         REGULATOR_SUPPLY("pex_clk", NULL),
 };
 
 static struct regulator_init_data ldo0_data = {
         .constraints = {
-                .min_uV = 1250 * 1000,
+                .min_uV = 3300 * 1000,
                 .max_uV = 3300 * 1000,
                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
                                      REGULATOR_MODE_STANDBY),
                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
                                    REGULATOR_CHANGE_STATUS |
                                    REGULATOR_CHANGE_VOLTAGE),
+                .apply_uV = 1,
         },
         .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
         .consumer_supplies = tps658621_ldo0_supply,
@@ -114,16 +110,6 @@ static struct i2c_board_info __initdata harmony_regulators[] = {
 
 int __init harmony_regulator_init(void)
 {
-        void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-        u32 pmc_ctrl;
-
-        /*
-         * Configure the power management controller to trigger PMU
-         * interrupts when low
-         */
-        pmc_ctrl = readl(pmc + PMC_CTRL);
-        writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
-
         i2c_register_board_info(3, harmony_regulators, 1);
 
         return 0;
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 789bdc9e8f9..c00aadb01e0 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -101,7 +101,6 @@ static struct wm8903_platform_data harmony_wm8903_pdata = {
 static struct i2c_board_info __initdata wm8903_board_info = {
         I2C_BOARD_INFO("wm8903", 0x1a),
         .platform_data = &harmony_wm8903_pdata,
-        .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
 };
 
 static void __init harmony_i2c_init(void)
@@ -111,6 +110,7 @@ static void __init harmony_i2c_init(void)
         platform_device_register(&tegra_i2c_device3);
         platform_device_register(&tegra_i2c_device4);
 
+        wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
         i2c_register_board_info(0, &wm8903_board_info, 1);
 }
 
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index ebac65f5251..d669847f048 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -159,7 +159,6 @@ static struct platform_device *seaboard_devices[] __initdata = {
 
 static struct i2c_board_info __initdata isl29018_device = {
         I2C_BOARD_INFO("isl29018", 0x44),
-        .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_ISL29018_IRQ),
 };
 
 static struct i2c_board_info __initdata adt7461_device = {
@@ -183,7 +182,6 @@ static struct wm8903_platform_data wm8903_pdata = {
 static struct i2c_board_info __initdata wm8903_device = {
         I2C_BOARD_INFO("wm8903", 0x1a),
         .platform_data = &wm8903_pdata,
-        .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
 };
 
 static int seaboard_ehci_init(void)
@@ -214,7 +212,10 @@ static void __init seaboard_i2c_init(void)
         gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
         gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
 
+        isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
         i2c_register_board_info(0, &isl29018_device, 1);
+
+        wm8903_device.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
         i2c_register_board_info(0, &wm8903_device, 1);
 
         i2c_register_board_info(3, &adt7461_device, 1);
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 8337068a4ab..8dad8d18cb4 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -399,6 +399,28 @@ void tegra_periph_reset_assert(struct clk *c)
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
+/* Several extended clock configuration bits (e.g., clock routing, clock
+ * phase control) are included in PLL and peripheral clock source
+ * registers. */
+int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&c->spinlock, flags);
+
+        if (!c->ops || !c->ops->clk_cfg_ex) {
+                ret = -ENOSYS;
+                goto out;
+        }
+        ret = c->ops->clk_cfg_ex(c, p, setting);
+
+out:
+        spin_unlock_irqrestore(&c->spinlock, flags);
+
+        return ret;
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 static int __clk_lock_all_spinlocks(void)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 5c44106616c..bc300657deb 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -24,6 +24,8 @@
 #include <linux/list.h>
 #include <linux/spinlock.h>
 
+#include <mach/clk.h>
+
 #define DIV_BUS                 (1 << 0)
 #define DIV_U71                 (1 << 1)
 #define DIV_U71_FIXED           (1 << 2)
@@ -39,7 +41,16 @@
 #define PERIPH_MANUAL_RESET     (1 << 12)
 #define PLL_ALT_MISC_REG        (1 << 13)
 #define PLLU                    (1 << 14)
+#define PLLX                    (1 << 15)
+#define MUX_PWM                 (1 << 16)
+#define MUX8                    (1 << 17)
+#define DIV_U71_UART            (1 << 18)
+#define MUX_CLK_OUT             (1 << 19)
+#define PLLM                    (1 << 20)
+#define DIV_U71_INT             (1 << 21)
+#define DIV_U71_IDLE            (1 << 22)
 #define ENABLE_ON_INIT          (1 << 28)
+#define PERIPH_ON_APB           (1 << 29)
 
 struct clk;
 
@@ -65,6 +76,8 @@ struct clk_ops {
         int             (*set_rate)(struct clk *, unsigned long);
         long            (*round_rate)(struct clk *, unsigned long);
         void            (*reset)(struct clk *, bool);
+        int             (*clk_cfg_ex)(struct clk *,
+                                enum tegra_clk_ex_param, u32);
 };
 
 enum clk_state {
@@ -114,6 +127,7 @@ struct clk {
                         unsigned long                   vco_max;
                         const struct clk_pll_freq_table *freq_table;
                         int                             lock_delay;
+                        unsigned long                   fixed_rate;
                 } pll;
                 struct {
                         u32                             sel;
@@ -146,6 +160,7 @@ struct tegra_clk_init_table {
 };
 
 void tegra2_init_clocks(void);
+void tegra30_init_clocks(void);
 void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
 int clk_reparent(struct clk *c, struct clk *parent);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index a2eb90169ae..22df10fb997 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -27,11 +27,29 @@
 #include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
-#include <mach/system.h>
+#include <mach/powergate.h>
 
 #include "board.h"
 #include "clock.h"
 #include "fuse.h"
+#include "pmc.h"
+
+/*
+ * Storage for debug-macro.S's state.
+ *
+ * This must be in .data not .bss so that it gets initialized each time the
+ * kernel is loaded. The data is declared here rather than debug-macro.S so
+ * that multiple inclusions of debug-macro.S point at the same data.
+ */
+#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
+u32 tegra_uart_config[3] = {
+        /* Debug UART initialization required */
+        1,
+        /* Debug UART physical address */
+        (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
+        /* Debug UART virtual address */
+        (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
+};
 
 #ifdef CONFIG_OF
 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
@@ -100,11 +118,17 @@ void __init tegra20_init_early(void)
         tegra2_init_clocks();
         tegra_clk_init_from_table(tegra20_clk_init_table);
         tegra_init_cache(0x331, 0x441);
+        tegra_pmc_init();
+        tegra_powergate_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 void __init tegra30_init_early(void)
 {
+        tegra_init_fuse();
+        tegra30_init_clocks();
         tegra_init_cache(0x441, 0x551);
+        tegra_pmc_init();
+        tegra_powergate_init();
 }
 #endif
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
new file mode 100644
index 00000000000..d83a8c0296f
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -0,0 +1,107 @@
+/*
+ * arch/arm/mach-tegra/cpuidle.c
+ *
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpuidle.h>
+#include <linux/hrtimer.h>
+
+#include <mach/iomap.h>
+
+extern void tegra_cpu_wfi(void);
+
+static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv, int index);
+
+struct cpuidle_driver tegra_idle_driver = {
+        .name = "tegra_idle",
+        .owner = THIS_MODULE,
+        .state_count = 1,
+        .states = {
+                [0] = {
+                        .enter                  = tegra_idle_enter_lp3,
+                        .exit_latency           = 10,
+                        .target_residency       = 10,
+                        .power_usage            = 600,
+                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                        .name                   = "LP3",
+                        .desc                   = "CPU flow-controlled",
+                },
+        },
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+
+static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
+        struct cpuidle_driver *drv, int index)
+{
+        ktime_t enter, exit;
+        s64 us;
+
+        local_irq_disable();
+        local_fiq_disable();
+
+        enter = ktime_get();
+
+        tegra_cpu_wfi();
+
+        exit = ktime_sub(ktime_get(), enter);
+        us = ktime_to_us(exit);
+
+        local_fiq_enable();
+        local_irq_enable();
+
+        dev->last_residency = us;
+
+        return index;
+}
+
+static int __init tegra_cpuidle_init(void)
+{
+        int ret;
+        unsigned int cpu;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &tegra_idle_driver;
+
+        ret = cpuidle_register_driver(&tegra_idle_driver);
+        if (ret) {
+                pr_err("CPUidle driver registration failed\n");
+                return ret;
+        }
+
+        for_each_possible_cpu(cpu) {
+                dev = &per_cpu(tegra_idle_device, cpu);
+                dev->cpu = cpu;
+
+                dev->state_count = drv->state_count;
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("CPU%u: CPUidle device registration failed\n",
+                                cpu);
+                        return ret;
+                }
+        }
+        return 0;
+}
+device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index c0cf967e47d..abea4f6e2dd 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -33,6 +33,8 @@
 #include <mach/iomap.h>
 #include <mach/suspend.h>
 
+#include "apbio.h"
+
 #define APB_DMA_GEN                             0x000
 #define GEN_ENABLE                              (1<<31)
 
@@ -50,8 +52,6 @@
 #define CSR_ONCE                                (1<<27)
 #define CSR_FLOW                                (1<<21)
 #define CSR_REQ_SEL_SHIFT                       16
-#define CSR_REQ_SEL_MASK                        (0x1F<<CSR_REQ_SEL_SHIFT)
-#define CSR_REQ_SEL_INVALID                     (31<<CSR_REQ_SEL_SHIFT)
 #define CSR_WCOUNT_SHIFT                        2
 #define CSR_WCOUNT_MASK                         0xFFFC
 
@@ -133,6 +133,7 @@ struct tegra_dma_channel {
 
 static bool tegra_dma_initialized;
 static DEFINE_MUTEX(tegra_dma_lock);
+static DEFINE_SPINLOCK(enable_lock);
 
 static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
 static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
@@ -180,36 +181,94 @@ static void tegra_dma_stop(struct tegra_dma_channel *ch)
 
 static int tegra_dma_cancel(struct tegra_dma_channel *ch)
 {
-        u32 csr;
         unsigned long irq_flags;
 
         spin_lock_irqsave(&ch->lock, irq_flags);
         while (!list_empty(&ch->list))
                 list_del(ch->list.next);
 
-        csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_REQ_SEL_MASK;
-        csr |= CSR_REQ_SEL_INVALID;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
         tegra_dma_stop(ch);
 
         spin_unlock_irqrestore(&ch->lock, irq_flags);
         return 0;
 }
 
+static unsigned int get_channel_status(struct tegra_dma_channel *ch,
+                        struct tegra_dma_req *req, bool is_stop_dma)
+{
+        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
+        unsigned int status;
+
+        if (is_stop_dma) {
+                /*
+                 * STOP the DMA and get the transfer count.
+                 * Getting the transfer count is tricky.
+                 *  - Globally disable DMA on all channels
+                 *  - Read the channel's status register to know the number
+                 *    of pending bytes to be transfered.
+                 *  - Stop the dma channel
+                 *  - Globally re-enable DMA to resume other transfers
+                 */
+                spin_lock(&enable_lock);
+                writel(0, addr + APB_DMA_GEN);
+                udelay(20);
+                status = readl(ch->addr + APB_DMA_CHAN_STA);
+                tegra_dma_stop(ch);
+                writel(GEN_ENABLE, addr + APB_DMA_GEN);
+                spin_unlock(&enable_lock);
+                if (status & STA_ISE_EOC) {
+                        pr_err("Got Dma Int here clearing");
+                        writel(status, ch->addr + APB_DMA_CHAN_STA);
+                }
+                req->status = TEGRA_DMA_REQ_ERROR_ABORTED;
+        } else {
+                status = readl(ch->addr + APB_DMA_CHAN_STA);
+        }
+        return status;
+}
+
+/* should be called with the channel lock held */
+static unsigned int dma_active_count(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req, unsigned int status)
+{
+        unsigned int to_transfer;
+        unsigned int req_transfer_count;
+        unsigned int bytes_transferred;
+
+        to_transfer = ((status & STA_COUNT_MASK) >> STA_COUNT_SHIFT) + 1;
+        req_transfer_count = ch->req_transfer_count + 1;
+        bytes_transferred = req_transfer_count;
+        if (status & STA_BUSY)
+                bytes_transferred -= to_transfer;
+        /*
+         * In continuous transfer mode, DMA only tracks the count of the
+         * half DMA buffer. So, if the DMA already finished half the DMA
+         * then add the half buffer to the completed count.
+         */
+        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) {
+                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
+                        bytes_transferred += req_transfer_count;
+                if (status & STA_ISE_EOC)
+                        bytes_transferred += req_transfer_count;
+        }
+        bytes_transferred *= 4;
+        return bytes_transferred;
+}
+
 int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
         struct tegra_dma_req *_req)
 {
-        unsigned int csr;
         unsigned int status;
         struct tegra_dma_req *req = NULL;
         int found = 0;
         unsigned long irq_flags;
-        int to_transfer;
-        int req_transfer_count;
+        int stop = 0;
 
         spin_lock_irqsave(&ch->lock, irq_flags);
+
+        if (list_entry(ch->list.next, struct tegra_dma_req, node) == _req)
+                stop = 1;
+
         list_for_each_entry(req, &ch->list, node) {
                 if (req == _req) {
                         list_del(&req->node);
@@ -222,47 +281,12 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
                 return 0;
         }
 
-        /* STOP the DMA and get the transfer count.
-         * Getting the transfer count is tricky.
-         *  - Change the source selector to invalid to stop the DMA from
-         *    FIFO to memory.
-         *  - Read the status register to know the number of pending
-         *    bytes to be transferred.
-         *  - Finally stop or program the DMA to the next buffer in the
-         *    list.
-         */
-        csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_REQ_SEL_MASK;
-        csr |= CSR_REQ_SEL_INVALID;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        /* Get the transfer count */
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        to_transfer = (status & STA_COUNT_MASK) >> STA_COUNT_SHIFT;
-        req_transfer_count = ch->req_transfer_count;
-        req_transfer_count += 1;
-        to_transfer += 1;
-
-        req->bytes_transferred = req_transfer_count;
-
-        if (status & STA_BUSY)
-                req->bytes_transferred -= to_transfer;
-
-        /* In continuous transfer mode, DMA only tracks the count of the
-         * half DMA buffer. So, if the DMA already finished half the DMA
-         * then add the half buffer to the completed count.
-         *
-         *      FIXME: There can be a race here. What if the req to
-         *      dequue happens at the same time as the DMA just moved to
-         *      the new buffer and SW didn't yet received the interrupt?
-         */
-        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS)
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
-                        req->bytes_transferred += req_transfer_count;
+        if (!stop)
+                goto skip_stop_dma;
 
-        req->bytes_transferred *= 4;
+        status = get_channel_status(ch, req, true);
+        req->bytes_transferred = dma_active_count(ch, req, status);
 
-        tegra_dma_stop(ch);
         if (!list_empty(&ch->list)) {
                 /* if the list is not empty, queue the next request */
                 struct tegra_dma_req *next_req;
@@ -270,6 +294,8 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
                         typeof(*next_req), node);
                 tegra_dma_update_hw(ch, next_req);
         }
+
+skip_stop_dma:
         req->status = -TEGRA_DMA_REQ_ERROR_ABORTED;
 
         spin_unlock_irqrestore(&ch->lock, irq_flags);
@@ -357,7 +383,7 @@ struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
         int channel;
         struct tegra_dma_channel *ch = NULL;
 
-        if (WARN_ON(!tegra_dma_initialized))
+        if (!tegra_dma_initialized)
                 return NULL;
 
         mutex_lock(&tegra_dma_lock);
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
new file mode 100644
index 00000000000..fef66a7486e
--- /dev/null
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-tegra/flowctrl.c
+ *
+ * functions and macros to control the flowcontroller
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+
+#include "flowctrl.h"
+
+u8 flowctrl_offset_halt_cpu[] = {
+        FLOW_CTRL_HALT_CPU0_EVENTS,
+        FLOW_CTRL_HALT_CPU1_EVENTS,
+        FLOW_CTRL_HALT_CPU1_EVENTS + 8,
+        FLOW_CTRL_HALT_CPU1_EVENTS + 16,
+};
+
+u8 flowctrl_offset_cpu_csr[] = {
+        FLOW_CTRL_CPU0_CSR,
+        FLOW_CTRL_CPU1_CSR,
+        FLOW_CTRL_CPU1_CSR + 8,
+        FLOW_CTRL_CPU1_CSR + 16,
+};
+
+static void flowctrl_update(u8 offset, u32 value)
+{
+        void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
+
+        writel(value, addr);
+
+        /* ensure the update has reached the flow controller */
+        wmb();
+        readl_relaxed(addr);
+}
+
+void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
+{
+        return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
+}
+
+void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
+{
+        return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
+}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
new file mode 100644
index 00000000000..19428173855
--- /dev/null
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-tegra/flowctrl.h
+ *
+ * functions and macros to control the flowcontroller
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_FLOWCTRL_H
+#define __MACH_TEGRA_FLOWCTRL_H
+
+#define FLOW_CTRL_HALT_CPU0_EVENTS      0x0
+#define FLOW_CTRL_WAITEVENT             (2 << 29)
+#define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
+#define FLOW_CTRL_JTAG_RESUME           (1 << 28)
+#define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
+#define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
+#define FLOW_CTRL_CPU0_CSR              0x8
+#define FLOW_CTRL_CSR_INTR_FLAG         (1 << 15)
+#define FLOW_CTRL_CSR_EVENT_FLAG        (1 << 14)
+#define FLOW_CTRL_CSR_ENABLE            (1 << 0)
+#define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
+#define FLOW_CTRL_CPU1_CSR              0x18
+
+#ifndef __ASSEMBLY__
+void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
+void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index ea49bd93c6b..f946d129423 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -19,68 +19,113 @@
 
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/module.h>
+#include <linux/export.h>
 
 #include <mach/iomap.h>
 
 #include "fuse.h"
+#include "apbio.h"
 
 #define FUSE_UID_LOW            0x108
 #define FUSE_UID_HIGH           0x10c
 #define FUSE_SKU_INFO           0x110
 #define FUSE_SPARE_BIT          0x200
 
-static inline u32 fuse_readl(unsigned long offset)
+int tegra_sku_id;
+int tegra_cpu_process_id;
+int tegra_core_process_id;
+int tegra_chip_id;
+enum tegra_revision tegra_revision;
+
+/* The BCT to use at boot is specified by board straps that can be read
+ * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
+ */
+int tegra_bct_strapping;
+
+#define STRAP_OPT 0x008
+#define GMI_AD0 (1 << 4)
+#define GMI_AD1 (1 << 5)
+#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
+#define RAM_CODE_SHIFT 4
+
+static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
+        [TEGRA_REVISION_UNKNOWN] = "unknown",
+        [TEGRA_REVISION_A01]     = "A01",
+        [TEGRA_REVISION_A02]     = "A02",
+        [TEGRA_REVISION_A03]     = "A03",
+        [TEGRA_REVISION_A03p]    = "A03 prime",
+        [TEGRA_REVISION_A04]     = "A04",
+};
+
+static inline u32 tegra_fuse_readl(unsigned long offset)
 {
-        return readl(IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
+        return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
 }
 
-static inline void fuse_writel(u32 value, unsigned long offset)
+static inline bool get_spare_fuse(int bit)
 {
-        writel(value, IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
+        return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
+}
+
+static enum tegra_revision tegra_get_revision(u32 id)
+{
+        u32 minor_rev = (id >> 16) & 0xf;
+
+        switch (minor_rev) {
+        case 1:
+                return TEGRA_REVISION_A01;
+        case 2:
+                return TEGRA_REVISION_A02;
+        case 3:
+                if (tegra_chip_id == TEGRA20 &&
+                        (get_spare_fuse(18) || get_spare_fuse(19)))
+                        return TEGRA_REVISION_A03p;
+                else
+                        return TEGRA_REVISION_A03;
+        case 4:
+                return TEGRA_REVISION_A04;
+        default:
+                return TEGRA_REVISION_UNKNOWN;
+        }
 }
 
 void tegra_init_fuse(void)
 {
+        u32 id;
+
         u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
         reg |= 1 << 28;
         writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
 
-        pr_info("Tegra SKU: %d CPU Process: %d Core Process: %d\n",
-                tegra_sku_id(), tegra_cpu_process_id(),
-                tegra_core_process_id());
+        reg = tegra_fuse_readl(FUSE_SKU_INFO);
+        tegra_sku_id = reg & 0xFF;
+
+        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
+        tegra_cpu_process_id = (reg >> 6) & 3;
+
+        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
+        tegra_core_process_id = (reg >> 12) & 3;
+
+        reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
+        tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
+
+        id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+        tegra_chip_id = (id >> 8) & 0xff;
+
+        tegra_revision = tegra_get_revision(id);
+
+        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
+                tegra_revision_name[tegra_revision],
+                tegra_sku_id, tegra_cpu_process_id,
+                tegra_core_process_id);
 }
 
 unsigned long long tegra_chip_uid(void)
 {
         unsigned long long lo, hi;
 
-        lo = fuse_readl(FUSE_UID_LOW);
-        hi = fuse_readl(FUSE_UID_HIGH);
+        lo = tegra_fuse_readl(FUSE_UID_LOW);
+        hi = tegra_fuse_readl(FUSE_UID_HIGH);
         return (hi << 32ull) | lo;
 }
 EXPORT_SYMBOL(tegra_chip_uid);
-
-int tegra_sku_id(void)
-{
-        int sku_id;
-        u32 reg = fuse_readl(FUSE_SKU_INFO);
-        sku_id = reg & 0xFF;
-        return sku_id;
-}
-
-int tegra_cpu_process_id(void)
-{
-        int cpu_process_id;
-        u32 reg = fuse_readl(FUSE_SPARE_BIT);
-        cpu_process_id = (reg >> 6) & 3;
-        return cpu_process_id;
-}
-
-int tegra_core_process_id(void)
-{
-        int core_process_id;
-        u32 reg = fuse_readl(FUSE_SPARE_BIT);
-        core_process_id = (reg >> 12) & 3;
-        return core_process_id;
-}
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index 584b2e27dbd..d2107b2cb85 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/mach-tegra/fuse.c
- *
  * Copyright (C) 2010 Google, Inc.
  *
  * Author:
@@ -17,8 +15,38 @@
  *
  */
 
+#ifndef __MACH_TEGRA_FUSE_H
+#define __MACH_TEGRA_FUSE_H
+
+enum tegra_revision {
+        TEGRA_REVISION_UNKNOWN = 0,
+        TEGRA_REVISION_A01,
+        TEGRA_REVISION_A02,
+        TEGRA_REVISION_A03,
+        TEGRA_REVISION_A03p,
+        TEGRA_REVISION_A04,
+        TEGRA_REVISION_MAX,
+};
+
+#define SKU_ID_T20      8
+#define SKU_ID_T25SE    20
+#define SKU_ID_AP25     23
+#define SKU_ID_T25      24
+#define SKU_ID_AP25E    27
+#define SKU_ID_T25E     28
+
+#define TEGRA20         0x20
+#define TEGRA30         0x30
+
+extern int tegra_sku_id;
+extern int tegra_cpu_process_id;
+extern int tegra_core_process_id;
+extern int tegra_chip_id;
+extern enum tegra_revision tegra_revision;
+
+extern int tegra_bct_strapping;
+
 unsigned long long tegra_chip_uid(void);
-int tegra_sku_id(void);
-int tegra_cpu_process_id(void);
-int tegra_core_process_id(void);
 void tegra_init_fuse(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index b5349b2f13d..fef9c2c5137 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -1,6 +1,23 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/cache.h>
+
+#include <mach/iomap.h>
+
+#include "flowctrl.h"
+#include "reset.h"
+
+#define APB_MISC_GP_HIDREV      0x804
+#define PMC_SCRATCH41   0x140
+
+#define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
+
+        .macro mov32, reg, val
+        movw    \reg, #:lower16:\val
+        movt    \reg, #:upper16:\val
+        .endm
+
         .section ".text.head", "ax"
         __CPUINIT
 
@@ -47,15 +64,149 @@ ENTRY(v7_invalidate_l1)
         mov     pc, lr
 ENDPROC(v7_invalidate_l1)
 
+
 ENTRY(tegra_secondary_startup)
-        msr     cpsr_fsxc, #0xd3
         bl      v7_invalidate_l1
-        mrc     p15, 0, r0, c0, c0, 5
-        and     r0, r0, #15
-        ldr     r1, =0x6000f100
-        str     r0, [r1]
-1:      ldr     r2, [r1]
-        cmp     r0, r2
-        beq     1b
+        /* Enable coresight */
+        mov32   r0, 0xC5ACCE55
+        mcr     p14, 0, r0, c7, c12, 6
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)
+
+        .align L1_CACHE_SHIFT
+ENTRY(__tegra_cpu_reset_handler_start)
+
+/*
+ * __tegra_cpu_reset_handler:
+ *
+ * Common handler for all CPU reset events.
+ *
+ * Register usage within the reset handler:
+ *
+ *      R7  = CPU present (to the OS) mask
+ *      R8  = CPU in LP1 state mask
+ *      R9  = CPU in LP2 state mask
+ *      R10 = CPU number
+ *      R11 = CPU mask
+ *      R12 = pointer to reset handler data
+ *
+ * NOTE: This code is copied to IRAM. All code and data accesses
+ *       must be position-independent.
+ */
+
+        .align L1_CACHE_SHIFT
+ENTRY(__tegra_cpu_reset_handler)
+
+        cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
+        mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
+        and     r10, r10, #0x3                  @ R10 = CPU number
+        mov     r11, #1
+        mov     r11, r11, lsl r10               @ R11 = CPU mask
+        adr     r12, __tegra_cpu_reset_handler_data
+
+#ifdef CONFIG_SMP
+        /* Does the OS know about this CPU? */
+        ldr     r7, [r12, #RESET_DATA(MASK_PRESENT)]
+        tst     r7, r11                         @ if !present
+        bleq    __die                           @ CPU not present (to OS)
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        /* Are we on Tegra20? */
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
+        and     r0, r0, #0xff00
+        cmp     r0, #(0x20 << 8)
+        bne     1f
+        /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
+        mov32   r6, TEGRA_PMC_BASE
+        mov     r0, #0
+        cmp     r10, #0
+        strne   r0, [r6, #PMC_SCRATCH41]
+1:
+#endif
+
+#ifdef CONFIG_SMP
+        /*
+         * Can only be secondary boot (initial or hotplug) but CPU 0
+         * cannot be here.
+         */
+        cmp     r10, #0
+        bleq    __die                           @ CPU0 cannot be here
+        ldr     lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
+        cmp     lr, #0
+        bleq    __die                           @ no secondary startup handler
+        bx      lr
+#endif
+
+/*
+ * We don't know why the CPU reset. Just kill it.
+ * The LR register will contain the address we died at + 4.
+ */
+
+__die:
+        sub     lr, lr, #4
+        mov32   r7, TEGRA_PMC_BASE
+        str     lr, [r7, #PMC_SCRATCH41]
+
+        mov32   r7, TEGRA_CLK_RESET_BASE
+
+        /* Are we on Tegra20? */
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
+        and     r0, r0, #0xff00
+        cmp     r0, #(0x20 << 8)
+        bne     1f
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        mov32   r0, 0x1111
+        mov     r1, r0, lsl r10
+        str     r1, [r7, #0x340]                @ CLK_RST_CPU_CMPLX_SET
+#endif
+1:
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        mov32   r6, TEGRA_FLOW_CTRL_BASE
+
+        cmp     r10, #0
+        moveq   r1, #FLOW_CTRL_HALT_CPU0_EVENTS
+        moveq   r2, #FLOW_CTRL_CPU0_CSR
+        movne   r1, r10, lsl #3
+        addne   r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
+        addne   r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
+
+        /* Clear CPU "event" and "interrupt" flags and power gate
+           it when halting but not before it is in the "WFI" state. */
+        ldr     r0, [r6, +r2]
+        orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
+        str     r0, [r6, +r2]
+
+        /* Unconditionally halt this CPU */
+        mov     r0, #FLOW_CTRL_WAITEVENT
+        str     r0, [r6, +r1]
+        ldr     r0, [r6, +r1]                   @ memory barrier
+
+        dsb
+        isb
+        wfi                                     @ CPU should be power gated here
+
+        /* If the CPU didn't power gate above just kill it's clock. */
+
+        mov     r0, r11, lsl #8
+        str     r0, [r7, #348]                  @ CLK_CPU_CMPLX_SET
+#endif
+
+        /* If the CPU still isn't dead, just spin here. */
+        b       .
+ENDPROC(__tegra_cpu_reset_handler)
+
+        .align L1_CACHE_SHIFT
+        .type   __tegra_cpu_reset_handler_data, %object
+        .globl  __tegra_cpu_reset_handler_data
+__tegra_cpu_reset_handler_data:
+        .rept   TEGRA_RESET_DATA_SIZE
+        .long   0
+        .endr
+        .align L1_CACHE_SHIFT
+
+ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index fc3ecb66de0..d97e403303a 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -22,10 +22,20 @@
 
 struct clk;
 
+enum tegra_clk_ex_param {
+        TEGRA_CLK_VI_INP_SEL,
+        TEGRA_CLK_DTV_INVERT,
+        TEGRA_CLK_NAND_PAD_DIV2_ENB,
+        TEGRA_CLK_PLLD_CSI_OUT_ENB,
+        TEGRA_CLK_PLLD_DSI_OUT_ENB,
+        TEGRA_CLK_PLLD_MIPI_MUX_SEL,
+};
+
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
 unsigned long clk_get_rate_all_locked(struct clk *c);
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
+int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 619abc63aee..90069abd37b 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -1,11 +1,17 @@
 /*
  * arch/arm/mach-tegra/include/mach/debug-macro.S
  *
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
  *      Erik Gilling <konkers@google.com>
+ *      Doug Anderson <dianders@chromium.org>
+ *      Stephen Warren <swarren@nvidia.com>
+ *
+ * Portions based on mach-omap2's debug-macro.S
+ * Copyright (C) 1994-1999 Russell King
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -18,18 +24,78 @@
  *
  */
 
+#include <linux/serial_reg.h>
+
 #include <mach/io.h>
 #include <mach/iomap.h>
+#include <mach/irammap.h>
+
+                .macro  addruart, rp, rv, tmp
+                adr     \rp, 99f                @ actual addr of 99f
+                ldr     \rv, [\rp]              @ linked addr is stored there
+                sub     \rv, \rv, \rp           @ offset between the two
+                ldr     \rp, [\rp, #4]          @ linked tegra_uart_config
+                sub     \tmp, \rp, \rv          @ actual tegra_uart_config
+                ldr     \rp, [\tmp]             @ Load tegra_uart_config
+                cmp     \rp, #1                 @ needs intitialization?
+                bne     100f                    @ no; go load the addresses
+                mov     \rv, #0                 @ yes; record init is done
+                str     \rv, [\tmp]
+                mov     \rp, #TEGRA_IRAM_BASE   @ See if cookie is in IRAM
+                ldr     \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
+                movw    \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
+                movt    \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
+                cmp     \rv, \rp                @ Cookie present?
+                bne     100f                    @ No, use default UART
+                mov     \rp, #TEGRA_IRAM_BASE   @ Load UART address from IRAM
+                ldr     \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
+                str     \rv, [\tmp, #4]         @ Store in tegra_uart_phys
+                sub     \rv, \rv, #IO_APB_PHYS  @ Calculate virt address
+                add     \rv, \rv, #IO_APB_VIRT
+                str     \rv, [\tmp, #8]         @ Store in tegra_uart_virt
+                b       100f
+
+                .align
+99:             .word   .
+                .word   tegra_uart_config
+                .ltorg
+
+100:            ldr     \rp, [\tmp, #4]         @ Load tegra_uart_phys
+                ldr     \rv, [\tmp, #8]         @ Load tegra_uart_virt
+                .endm
+
+#define UART_SHIFT 2
+
+/*
+ * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
+ * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
+ * We use the fact that all 5 valid UART addresses all have something in the
+ * 2nd-to-lowest byte.
+ */
 
-        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =IO_APB_PHYS       @ physical
-        ldr     \rv, =IO_APB_VIRT        @ virtual
-        orr     \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF)
-        orr     \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
-        orr     \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF)
-        orr     \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
-        .endm
+                .macro  senduart, rd, rx
+                tst     \rx, #0x0000ff00
+                strneb  \rd, [\rx, #UART_TX << UART_SHIFT]
+1001:
+                .endm
 
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
+                .macro  busyuart, rd, rx
+                tst     \rx, #0x0000ff00
+                beq     1002f
+1001:           ldrb    \rd, [\rx, #UART_LSR << UART_SHIFT]
+                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                bne     1001b
+1002:
+                .endm
 
+                .macro  waituart, rd, rx
+#ifdef FLOW_CONTROL
+                tst     \rx, #0x0000ff00
+                beq     1002f
+1001:           ldrb    \rd, [\rx, #UART_MSR << UART_SHIFT]
+                tst     \rd, #UART_MSR_CTS
+                beq     1001b
+1002:
+#endif
+                .endm
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
deleted file mode 100644
index e577cfe27e7..00000000000
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-tegra/include/mach/entry-macro.S
- *
- * Copyright (C) 2009 Palm, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 87d37fdf508..6140820555e 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,8 +25,6 @@
 
 #define TEGRA_NR_GPIOS          INT_GPIO_NR
 
-#define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio))
-
 struct tegra_gpio_table {
         int     gpio;   /* GPIO number */
         bool    enable; /* Enable for GPIO at init? */
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 19dec3ac085..cff672a344f 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -74,6 +74,9 @@
 #define TEGRA_QUATERNARY_ICTLR_BASE     0x60004300
 #define TEGRA_QUATERNARY_ICTLR_SIZE     SZ_64
 
+#define TEGRA_QUINARY_ICTLR_BASE        0x60004400
+#define TEGRA_QUINARY_ICTLR_SIZE        SZ_64
+
 #define TEGRA_TMR1_BASE                 0x60005000
 #define TEGRA_TMR1_SIZE                 SZ_8
 
@@ -110,6 +113,9 @@
 #define TEGRA_AHB_GIZMO_BASE            0x6000C004
 #define TEGRA_AHB_GIZMO_SIZE            0x10C
 
+#define TEGRA_SB_BASE                   0x6000C200
+#define TEGRA_SB_SIZE                   256
+
 #define TEGRA_STATMON_BASE              0x6000C400
 #define TEGRA_STATMON_SIZE              SZ_1K
 
diff --git a/arch/arm/mach-tegra/include/mach/irammap.h b/arch/arm/mach-tegra/include/mach/irammap.h
new file mode 100644
index 00000000000..0cbe6326185
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/irammap.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_IRAMMAP_H
+#define __MACH_TEGRA_IRAMMAP_H
+
+#include <asm/sizes.h>
+
+/* The first 1K of IRAM is permanently reserved for the CPU reset handler */
+#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
+#define TEGRA_IRAM_RESET_HANDLER_SIZE   SZ_1K
+
+/*
+ * These locations are written to by uncompress.h, and read by debug-macro.S.
+ * The first word holds the cookie value if the data is valid. The second
+ * word holds the UART physical address.
+ */
+#define TEGRA_IRAM_DEBUG_UART_OFFSET    SZ_1K
+#define TEGRA_IRAM_DEBUG_UART_SIZE      8
+#define TEGRA_IRAM_DEBUG_UART_COOKIE    0x55415254
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index a2146cd6867..aad1a2c1d71 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -165,11 +165,12 @@
 #define INT_QUAD_RES_30                 (INT_QUAD_BASE + 30)
 #define INT_QUAD_RES_31                 (INT_QUAD_BASE + 31)
 
-#define INT_MAIN_NR                     (INT_QUAD_BASE + 32 - INT_PRI_BASE)
-
+/* Tegra30 has 5 banks of 32 IRQs */
+#define INT_MAIN_NR                     (32 * 5)
 #define INT_GPIO_BASE                   (INT_PRI_BASE + INT_MAIN_NR)
 
-#define INT_GPIO_NR                     (28 * 8)
+/* Tegra30 has 8 banks of 32 GPIOs */
+#define INT_GPIO_NR                     (32 * 8)
 
 #define TEGRA_NR_IRQS                   (INT_GPIO_BASE + INT_GPIO_NR)
 
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 39c396d2ddb..4752b1a68f3 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -27,8 +27,21 @@
 #define TEGRA_POWERGATE_VDEC    4
 #define TEGRA_POWERGATE_L2      5
 #define TEGRA_POWERGATE_MPE     6
-#define TEGRA_NUM_POWERGATE     7
+#define TEGRA_POWERGATE_HEG     7
+#define TEGRA_POWERGATE_SATA    8
+#define TEGRA_POWERGATE_CPU1    9
+#define TEGRA_POWERGATE_CPU2    10
+#define TEGRA_POWERGATE_CPU3    11
+#define TEGRA_POWERGATE_CELP    12
+#define TEGRA_POWERGATE_3D1     13
 
+#define TEGRA_POWERGATE_CPU0    TEGRA_POWERGATE_CPU
+#define TEGRA_POWERGATE_3D0     TEGRA_POWERGATE_3D
+
+int  __init tegra_powergate_init(void);
+
+int tegra_cpu_powergate_id(int cpuid);
+int tegra_powergate_is_powered(int id);
 int tegra_powergate_power_on(int id);
 int tegra_powergate_power_off(int id);
 int tegra_powergate_remove_clamping(int id);
diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h
new file mode 100644
index 00000000000..dad403a9cf0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/smmu.h
@@ -0,0 +1,63 @@
+/*
+ * IOMMU API for SMMU in Tegra30
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef MACH_SMMU_H
+#define MACH_SMMU_H
+
+enum smmu_hwgrp {
+        HWGRP_AFI,
+        HWGRP_AVPC,
+        HWGRP_DC,
+        HWGRP_DCB,
+        HWGRP_EPP,
+        HWGRP_G2,
+        HWGRP_HC,
+        HWGRP_HDA,
+        HWGRP_ISP,
+        HWGRP_MPE,
+        HWGRP_NV,
+        HWGRP_NV2,
+        HWGRP_PPCS,
+        HWGRP_SATA,
+        HWGRP_VDE,
+        HWGRP_VI,
+
+        HWGRP_COUNT,
+
+        HWGRP_END = ~0,
+};
+
+#define HWG_AFI         (1 << HWGRP_AFI)
+#define HWG_AVPC        (1 << HWGRP_AVPC)
+#define HWG_DC          (1 << HWGRP_DC)
+#define HWG_DCB         (1 << HWGRP_DCB)
+#define HWG_EPP         (1 << HWGRP_EPP)
+#define HWG_G2          (1 << HWGRP_G2)
+#define HWG_HC          (1 << HWGRP_HC)
+#define HWG_HDA         (1 << HWGRP_HDA)
+#define HWG_ISP         (1 << HWGRP_ISP)
+#define HWG_MPE         (1 << HWGRP_MPE)
+#define HWG_NV          (1 << HWGRP_NV)
+#define HWG_NV2         (1 << HWGRP_NV2)
+#define HWG_PPCS        (1 << HWGRP_PPCS)
+#define HWG_SATA        (1 << HWGRP_SATA)
+#define HWG_VDE         (1 << HWGRP_VDE)
+#define HWG_VI          (1 << HWGRP_VI)
+
+#endif  /* MACH_SMMU_H */
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 4e8323770c7..5a440f315e5 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -2,10 +2,14 @@
  * arch/arm/mach-tegra/include/mach/uncompress.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
  *      Erik Gilling <konkers@google.com>
+ *      Doug Anderson <dianders@chromium.org>
+ *      Stephen Warren <swarren@nvidia.com>
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -25,36 +29,130 @@
 #include <linux/serial_reg.h>
 
 #include <mach/iomap.h>
+#include <mach/irammap.h>
+
+#define BIT(x) (1 << (x))
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+#define DEBUG_UART_SHIFT 2
+
+volatile u8 *uart;
 
 static void putc(int c)
 {
-        volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
-        int shift = 2;
-
         if (uart == NULL)
                 return;
 
-        while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+        while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
                 barrier();
-        uart[UART_TX << shift] = c;
+        uart[UART_TX << DEBUG_UART_SHIFT] = c;
 }
 
 static inline void flush(void)
 {
 }
 
+static inline void save_uart_address(void)
+{
+        u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
+
+        if (uart) {
+                buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
+                buf[1] = (u32)uart;
+        } else
+                buf[0] = 0;
+}
+
+/*
+ * Setup before decompression.  This is where we do UART selection for
+ * earlyprintk and init the uart_base register.
+ */
 static inline void arch_decomp_setup(void)
 {
-        volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
-        int shift = 2;
+        static const struct {
+                u32 base;
+                u32 reset_reg;
+                u32 clock_reg;
+                u32 bit;
+        } uarts[] = {
+                {
+                        TEGRA_UARTA_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x04,
+                        TEGRA_CLK_RESET_BASE + 0x10,
+                        6,
+                },
+                {
+                        TEGRA_UARTB_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x04,
+                        TEGRA_CLK_RESET_BASE + 0x10,
+                        7,
+                },
+                {
+                        TEGRA_UARTC_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x08,
+                        TEGRA_CLK_RESET_BASE + 0x14,
+                        23,
+                },
+                {
+                        TEGRA_UARTD_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x0c,
+                        TEGRA_CLK_RESET_BASE + 0x18,
+                        1,
+                },
+                {
+                        TEGRA_UARTE_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x0c,
+                        TEGRA_CLK_RESET_BASE + 0x18,
+                        2,
+                },
+        };
+        int i;
+        volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
+        u32 chip, div;
+
+        /*
+         * Look for the first UART that:
+         * a) Is not in reset.
+         * b) Is clocked.
+         * c) Has a 'D' in the scratchpad register.
+         *
+         * Note that on Tegra30, the first two conditions are required, since
+         * if not true, accesses to the UART scratch register will hang.
+         * Tegra20 doesn't have this issue.
+         *
+         * The intent is that the bootloader will tell the kernel which UART
+         * to use by setting up those conditions. If nothing found, we'll fall
+         * back to what's specified in TEGRA_DEBUG_UART_BASE.
+         */
+        for (i = 0; i < ARRAY_SIZE(uarts); i++) {
+                if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit))
+                        continue;
 
+                if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit)))
+                        continue;
+
+                uart = (volatile u8 *)uarts[i].base;
+                if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
+                        continue;
+
+                break;
+        }
+        if (i == ARRAY_SIZE(uarts))
+                uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
+        save_uart_address();
         if (uart == NULL)
                 return;
 
-        uart[UART_LCR << shift] |= UART_LCR_DLAB;
-        uart[UART_DLL << shift] = 0x75;
-        uart[UART_DLM << shift] = 0x0;
-        uart[UART_LCR << shift] = 3;
+        chip = (apb_misc[0x804 / 4] >> 8) & 0xff;
+        if (chip == 0x20)
+                div = 0x0075;
+        else
+                div = 0x00dd;
+
+        uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
+        uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff;
+        uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8;
+        uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
 }
 
 static inline void arch_decomp_wdog(void)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4e1afcd54fa..2f5bd2db8e1 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -44,14 +44,16 @@
 #define ICTLR_COP_IER_CLR       0x38
 #define ICTLR_COP_IEP_CLASS     0x3c
 
-#define NUM_ICTLRS 4
 #define FIRST_LEGACY_IRQ 32
 
+static int num_ictlrs;
+
 static void __iomem *ictlr_reg_base[] = {
         IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
         IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
         IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
         IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
 static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
@@ -60,7 +62,7 @@ static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
         u32 mask;
 
         BUG_ON(irq < FIRST_LEGACY_IRQ ||
-                irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
+                irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32);
 
         base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
         mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
@@ -113,8 +115,18 @@ static int tegra_retrigger(struct irq_data *d)
 void __init tegra_init_irq(void)
 {
         int i;
+        void __iomem *distbase;
+
+        distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
+        num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;
+
+        if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
+                WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
+                        num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
+                num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
+        }
 
-        for (i = 0; i < NUM_ICTLRS; i++) {
+        for (i = 0; i < num_ictlrs; i++) {
                 void __iomem *ictlr = ictlr_reg_base[i];
                 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
                 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
@@ -131,6 +143,6 @@ void __init tegra_init_irq(void)
          * initialized elsewhere under DT.
          */
         if (!of_have_populated_dt())
-                gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
+                gic_init(0, 29, distbase,
                         IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 }
diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c
deleted file mode 100644
index e91d681d45a..00000000000
--- a/arch/arm/mach-tegra/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  arch/arm/mach-tegra/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index af8b6343572..54a816ff384 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -408,7 +408,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[0].flags = IORESOURCE_IO;
         if (request_resource(&ioport_resource, &pp->res[0]))
                 panic("Request PCIe IO resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[0]);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -427,7 +427,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[1].flags = IORESOURCE_MEM;
         if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[1]);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         /*
          * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -446,7 +446,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
         if (request_resource(&iomem_resource, &pp->res[2]))
                 panic("Request PCIe Prefetch Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[2]);
+        pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset);
 
         return 1;
 }
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
         afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
         u32 val, reg;
-        int i;
+        int i, timeout;
 
         /* Enable slot clock and pulse the reset signals */
         for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
         pads_writel(0xfa5cfa5c, 0xc8);
 
         /* Wait for the PLL to lock */
+        timeout = 300;
         do {
                 val = pads_readl(PADS_PLL_CTL);
+                usleep_range(1000, 1000);
+                if (--timeout == 0) {
+                        pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+                        return -EBUSY;
+                }
         } while (!(val & PADS_PLL_CTL_LOCKDET));
 
         /* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
         /* Disable all execptions */
         afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-        return;
+        return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
         if (err)
                 return err;
 
-        tegra_pcie_enable_controller();
+        err = tegra_pcie_enable_controller();
+        if (err)
+                return err;
 
         /* setup the AFI address translations */
         tegra_pcie_setup_translations();
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 7d2b5d03c1d..1a208dbf682 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,19 +24,31 @@
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
 
+#include <mach/clk.h>
 #include <mach/iomap.h>
+#include <mach/powergate.h>
+
+#include "fuse.h"
+#include "flowctrl.h"
+#include "reset.h"
 
 extern void tegra_secondary_startup(void);
 
-static DEFINE_SPINLOCK(boot_lock);
 static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 #define EVP_CPU_RESET_VECTOR \
         (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
+        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
+        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
+
+#define CPU_CLOCK(cpu)  (0x1<<(8+cpu))
+#define CPU_RESET(cpu)  (0x1111ul<<(cpu))
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
@@ -47,63 +59,106 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          */
         gic_secondary_init(0);
 
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int tegra20_power_up_cpu(unsigned int cpu)
 {
-        unsigned long old_boot_vector;
-        unsigned long boot_vector;
-        unsigned long timeout;
         u32 reg;
 
-        /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
+        /* Enable the CPU clock. */
+        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        barrier();
+        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
 
+        /* Clear flow controller CSR. */
+        flowctrl_write_cpu_csr(cpu, 0);
 
-        /* set the reset vector to point to the secondary_startup routine */
+        return 0;
+}
 
-        boot_vector = virt_to_phys(tegra_secondary_startup);
-        old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
-        writel(boot_vector, EVP_CPU_RESET_VECTOR);
+static int tegra30_power_up_cpu(unsigned int cpu)
+{
+        u32 reg;
+        int ret, pwrgateid;
+        unsigned long timeout;
 
-        /* enable cpu clock on cpu1 */
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        pwrgateid = tegra_cpu_powergate_id(cpu);
+        if (pwrgateid < 0)
+                return pwrgateid;
+
+        /* If this is the first boot, toggle powergates directly. */
+        if (!tegra_powergate_is_powered(pwrgateid)) {
+                ret = tegra_powergate_power_on(pwrgateid);
+                if (ret)
+                        return ret;
+
+                /* Wait for the power to come up. */
+                timeout = jiffies + 10*HZ;
+                while (tegra_powergate_is_powered(pwrgateid)) {
+                        if (time_after(jiffies, timeout))
+                                return -ETIMEDOUT;
+                        udelay(10);
+                }
+        }
 
-        reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
-        writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        /* CPU partition is powered. Enable the CPU clock. */
+        writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        udelay(10);
 
-        smp_wmb();
-        flush_cache_all();
+        /* Remove I/O clamps. */
+        ret = tegra_powergate_remove_clamping(pwrgateid);
+        udelay(10);
 
-        /* unhalt the cpu */
-        writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
+        /* Clear flow controller CSR. */
+        flowctrl_write_cpu_csr(cpu, 0);
 
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout)) {
-                if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
-                        break;
-                udelay(10);
-        }
+        return 0;
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        int status;
 
-        /* put the old boot vector back */
-        writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
+        /*
+         * Force the CPU into reset. The CPU must remain in reset when the
+         * flow controller state is cleared (which will cause the flow
+         * controller to stop driving reset if the CPU has been power-gated
+         * via the flow controller). This will have no effect on first boot
+         * of the CPU since it should already be in reset.
+         */
+        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
 
         /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
+         * Unhalt the CPU. If the flow controller was used to power-gate the
+         * CPU this will cause the flow controller to stop driving reset.
+         * The CPU will remain in reset because the clock and reset block
+         * is now driving reset.
          */
-        spin_unlock(&boot_lock);
+        flowctrl_write_cpu_halt(cpu, 0);
+
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                status = tegra20_power_up_cpu(cpu);
+                break;
+        case TEGRA30:
+                status = tegra30_power_up_cpu(cpu);
+                break;
+        default:
+                status = -EINVAL;
+                break;
+        }
 
-        return 0;
+        if (status)
+                goto done;
+
+        /* Take the CPU out of reset. */
+        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        wmb();
+done:
+        return status;
 }
 
 /*
@@ -128,6 +183,6 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-
+        tegra_cpu_reset_handler_init();
         scu_enable(scu_base);
 }
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
new file mode 100644
index 00000000000..7af6a54404b
--- /dev/null
+++ b/arch/arm/mach-tegra/pmc.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <mach/iomap.h>
+
+#define PMC_CTRL                0x0
+#define PMC_CTRL_INTR_LOW       (1 << 17)
+
+static inline u32 tegra_pmc_readl(u32 reg)
+{
+        return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
+}
+
+static inline void tegra_pmc_writel(u32 val, u32 reg)
+{
+        writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg));
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra20-pmc" },
+        { }
+};
+#endif
+
+void __init tegra_pmc_init(void)
+{
+        /*
+         * For now, Harmony is the only board that uses the PMC, and it wants
+         * the signal inverted. Seaboard would too if it used the PMC.
+         * Hopefully by the time other boards want to use the PMC, everything
+         * will be device-tree, or they also want it inverted.
+         */
+        bool invert_interrupt = true;
+        u32 val;
+
+#ifdef CONFIG_OF
+        if (of_have_populated_dt()) {
+                struct device_node *np;
+
+                invert_interrupt = false;
+
+                np = of_find_matching_node(NULL, matches);
+                if (np) {
+                        if (of_find_property(np, "nvidia,invert-interrupt",
+                                                NULL))
+                                invert_interrupt = true;
+                }
+        }
+#endif
+
+        val = tegra_pmc_readl(PMC_CTRL);
+        if (invert_interrupt)
+                val |= PMC_CTRL_INTR_LOW;
+        else
+                val &= ~PMC_CTRL_INTR_LOW;
+        tegra_pmc_writel(val, PMC_CTRL);
+}
diff --git a/arch/arm/mach-highbank/include/mach/system.h b/arch/arm/mach-tegra/pmc.h
index b1d8b5fbe37..8995ee4a876 100644
--- a/arch/arm/mach-highbank/include/mach/system.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010-2011 Calxeda, Inc.
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -10,15 +10,14 @@
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
  */
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
 
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
+#ifndef __MACH_TEGRA_PMC_H
+#define __MACH_TEGRA_PMC_H
+
+void tegra_pmc_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 948306491a5..c238699ae86 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -31,6 +31,8 @@
 #include <mach/iomap.h>
 #include <mach/powergate.h>
 
+#include "fuse.h"
+
 #define PWRGATE_TOGGLE          0x30
 #define  PWRGATE_TOGGLE_START   (1 << 8)
 
@@ -38,6 +40,16 @@
 
 #define PWRGATE_STATUS          0x38
 
+static int tegra_num_powerdomains;
+static int tegra_num_cpu_domains;
+static u8 *tegra_cpu_domains;
+static u8 tegra30_cpu_domains[] = {
+        TEGRA_POWERGATE_CPU0,
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+
 static DEFINE_SPINLOCK(tegra_powergate_lock);
 
 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
@@ -75,7 +87,7 @@ static int tegra_powergate_set(int id, bool new_state)
 
 int tegra_powergate_power_on(int id)
 {
-        if (id < 0 || id >= TEGRA_NUM_POWERGATE)
+        if (id < 0 || id >= tegra_num_powerdomains)
                 return -EINVAL;
 
         return tegra_powergate_set(id, true);
@@ -83,17 +95,18 @@ int tegra_powergate_power_on(int id)
 
 int tegra_powergate_power_off(int id)
 {
-        if (id < 0 || id >= TEGRA_NUM_POWERGATE)
+        if (id < 0 || id >= tegra_num_powerdomains)
                 return -EINVAL;
 
         return tegra_powergate_set(id, false);
 }
 
-static bool tegra_powergate_is_powered(int id)
+int tegra_powergate_is_powered(int id)
 {
         u32 status;
 
-        WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE);
+        if (id < 0 || id >= tegra_num_powerdomains)
+                return -EINVAL;
 
         status = pmc_read(PWRGATE_STATUS) & (1 << id);
         return !!status;
@@ -103,7 +116,7 @@ int tegra_powergate_remove_clamping(int id)
 {
         u32 mask;
 
-        if (id < 0 || id >= TEGRA_NUM_POWERGATE)
+        if (id < 0 || id >= tegra_num_powerdomains)
                 return -EINVAL;
 
         /*
@@ -156,6 +169,34 @@ err_power:
         return ret;
 }
 
+int tegra_cpu_powergate_id(int cpuid)
+{
+        if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
+                return tegra_cpu_domains[cpuid];
+
+        return -EINVAL;
+}
+
+int __init tegra_powergate_init(void)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                tegra_num_powerdomains = 7;
+                break;
+        case TEGRA30:
+                tegra_num_powerdomains = 14;
+                tegra_num_cpu_domains = 4;
+                tegra_cpu_domains = tegra30_cpu_domains;
+                break;
+        default:
+                /* Unknown Tegra variant. Disable powergating */
+                tegra_num_powerdomains = 0;
+                break;
+        }
+
+        return 0;
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 static const char * const powergate_name[] = {
@@ -175,7 +216,7 @@ static int powergate_show(struct seq_file *s, void *data)
         seq_printf(s, " powergate powered\n");
         seq_printf(s, "------------------\n");
 
-        for (i = 0; i < TEGRA_NUM_POWERGATE; i++)
+        for (i = 0; i < tegra_num_powerdomains; i++)
                 seq_printf(s, " %9s %7s\n", powergate_name[i],
                         tegra_powergate_is_powered(i) ? "yes" : "no");
         return 0;
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
new file mode 100644
index 00000000000..4d6a2ee99c3
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.c
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/mach-tegra/reset.c
+ *
+ * Copyright (C) 2011,2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/bitops.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/iomap.h>
+#include <mach/irammap.h>
+
+#include "reset.h"
+#include "fuse.h"
+
+#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
+                                TEGRA_IRAM_RESET_HANDLER_OFFSET)
+
+static bool is_enabled;
+
+static void tegra_cpu_reset_handler_enable(void)
+{
+        void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
+        void __iomem *evp_cpu_reset =
+                IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
+        void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
+        u32 reg;
+
+        BUG_ON(is_enabled);
+        BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
+
+        memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
+                        tegra_cpu_reset_handler_size);
+
+        /*
+         * NOTE: This must be the one and only write to the EVP CPU reset
+         *       vector in the entire system.
+         */
+        writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
+                        evp_cpu_reset);
+        wmb();
+        reg = readl(evp_cpu_reset);
+
+        /*
+         * Prevent further modifications to the physical reset vector.
+         *  NOTE: Has no effect on chips prior to Tegra30.
+         */
+        if (tegra_chip_id != TEGRA20) {
+                reg = readl(sb_ctrl);
+                reg |= 2;
+                writel(reg, sb_ctrl);
+                wmb();
+        }
+
+        is_enabled = true;
+}
+
+void __init tegra_cpu_reset_handler_init(void)
+{
+
+#ifdef CONFIG_SMP
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
+                *((u32 *)cpu_present_mask);
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
+                virt_to_phys((void *)tegra_secondary_startup);
+#endif
+
+        tegra_cpu_reset_handler_enable();
+}
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
new file mode 100644
index 00000000000..de88bf851dd
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-tegra/reset.h
+ *
+ * CPU reset dispatcher.
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_RESET_H
+#define __MACH_TEGRA_RESET_H
+
+#define TEGRA_RESET_MASK_PRESENT        0
+#define TEGRA_RESET_MASK_LP1            1
+#define TEGRA_RESET_MASK_LP2            2
+#define TEGRA_RESET_STARTUP_SECONDARY   3
+#define TEGRA_RESET_STARTUP_LP2         4
+#define TEGRA_RESET_STARTUP_LP1         5
+#define TEGRA_RESET_DATA_SIZE           6
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
+
+void __tegra_cpu_reset_handler_start(void);
+void __tegra_cpu_reset_handler(void);
+void __tegra_cpu_reset_handler_end(void);
+void tegra_secondary_startup(void);
+
+#define tegra_cpu_reset_handler_offset \
+                ((u32)__tegra_cpu_reset_handler - \
+                 (u32)__tegra_cpu_reset_handler_start)
+
+#define tegra_cpu_reset_handler_size \
+                (__tegra_cpu_reset_handler_end - \
+                 __tegra_cpu_reset_handler_start)
+
+void __init tegra_cpu_reset_handler_init(void);
+
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
new file mode 100644
index 00000000000..8f9fde161c3
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.S
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-tegra/sleep.S
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/linkage.h>
+#include <mach/io.h>
+#include <mach/iomap.h>
+
+#include "flowctrl.h"
+
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x14
+        moveq   \rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x18
+        moveq   \rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+        mrc     p15, 0, \rd, c0, c0, 5
+        and     \rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+        movw    \reg, #:lower16:\val
+        movt    \reg, #:upper16:\val
+.endm
+
+/*
+ * tegra_cpu_wfi
+ *
+ * puts current CPU in clock-gated wfi using the flow controller
+ *
+ * corrupts r0-r3
+ * must be called with MMU on
+ */
+
+ENTRY(tegra_cpu_wfi)
+        cpu_id  r0
+        cpu_to_halt_reg r1, r0
+        cpu_to_csr_reg r2, r0
+        mov32   r0, TEGRA_FLOW_CTRL_VIRT
+        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        str     r3, [r0, r2]    @ clear event & interrupt status
+        mov     r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
+        str     r3, [r0, r1]    @ put flow controller in wait irq mode
+        dsb
+        wfi
+        mov     r3, #0
+        str     r3, [r0, r1]    @ clear flow controller halt status
+        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        str     r3, [r0, r2]    @ clear event & interrupt status
+        dsb
+        mov     pc, lr
+ENDPROC(tegra_cpu_wfi)
+
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index ff9e6b6c046..592a4eeb532 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -720,7 +720,7 @@ static void tegra2_pllx_clk_init(struct clk *c)
 {
         tegra2_pll_clk_init(c);
 
-        if (tegra_sku_id() == 7)
+        if (tegra_sku_id == 7)
                 c->max_rate = 750000000;
 }
 
@@ -1143,15 +1143,35 @@ static void tegra2_emc_clk_init(struct clk *c)
 
 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
 {
-        long new_rate = rate;
+        long emc_rate;
+        long clk_rate;
 
-        new_rate = tegra_emc_round_rate(new_rate);
-        if (new_rate < 0)
+        /*
+         * The slowest entry in the EMC clock table that is at least as
+         * fast as rate.
+         */
+        emc_rate = tegra_emc_round_rate(rate);
+        if (emc_rate < 0)
                 return c->max_rate;
 
-        BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate));
+        /*
+         * The fastest rate the PLL will generate that is at most the
+         * requested rate.
+         */
+        clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
+
+        /*
+         * If this fails, and emc_rate > clk_rate, it's because the maximum
+         * rate in the EMC tables is larger than the maximum rate of the EMC
+         * clock. The EMC clock's max rate is the rate it was running when the
+         * kernel booted. Such a mismatch is probably due to using the wrong
+         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
+         */
+        WARN_ONCE(emc_rate != clk_rate,
+                "emc_rate %ld != clk_rate %ld",
+                emc_rate, clk_rate);
 
-        return new_rate;
+        return emc_rate;
 }
 
 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 0f7ae6e90b5..5070d833bdd 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -16,14 +16,19 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/tegra_emc.h>
 
 #include <mach/iomap.h>
 
 #include "tegra2_emc.h"
+#include "fuse.h"
 
 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
 static bool emc_enable = true;
@@ -32,18 +37,17 @@ static bool emc_enable;
 #endif
 module_param(emc_enable, bool, 0644);
 
-static void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
-static const struct tegra_emc_table *tegra_emc_table;
-static int tegra_emc_table_size;
+static struct platform_device *emc_pdev;
+static void __iomem *emc_regbase;
 
 static inline void emc_writel(u32 val, unsigned long addr)
 {
-        writel(val, emc + addr);
+        writel(val, emc_regbase + addr);
 }
 
 static inline u32 emc_readl(unsigned long addr)
 {
-        return readl(emc + addr);
+        return readl(emc_regbase + addr);
 }
 
 static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
@@ -98,15 +102,15 @@ static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
 /* Select the closest EMC rate that is higher than the requested rate */
 long tegra_emc_round_rate(unsigned long rate)
 {
+        struct tegra_emc_pdata *pdata;
         int i;
         int best = -1;
         unsigned long distance = ULONG_MAX;
 
-        if (!tegra_emc_table)
+        if (!emc_pdev)
                 return -EINVAL;
 
-        if (!emc_enable)
-                return -EINVAL;
+        pdata = emc_pdev->dev.platform_data;
 
         pr_debug("%s: %lu\n", __func__, rate);
 
@@ -116,10 +120,10 @@ long tegra_emc_round_rate(unsigned long rate)
          */
         rate = rate / 2 / 1000;
 
-        for (i = 0; i < tegra_emc_table_size; i++) {
-                if (tegra_emc_table[i].rate >= rate &&
-                    (tegra_emc_table[i].rate - rate) < distance) {
-                        distance = tegra_emc_table[i].rate - rate;
+        for (i = 0; i < pdata->num_tables; i++) {
+                if (pdata->tables[i].rate >= rate &&
+                    (pdata->tables[i].rate - rate) < distance) {
+                        distance = pdata->tables[i].rate - rate;
                         best = i;
                 }
         }
@@ -127,9 +131,9 @@ long tegra_emc_round_rate(unsigned long rate)
         if (best < 0)
                 return -EINVAL;
 
-        pr_debug("%s: using %lu\n", __func__, tegra_emc_table[best].rate);
+        pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate);
 
-        return tegra_emc_table[best].rate * 2 * 1000;
+        return pdata->tables[best].rate * 2 * 1000;
 }
 
 /*
@@ -142,37 +146,211 @@ long tegra_emc_round_rate(unsigned long rate)
  */
 int tegra_emc_set_rate(unsigned long rate)
 {
+        struct tegra_emc_pdata *pdata;
         int i;
         int j;
 
-        if (!tegra_emc_table)
+        if (!emc_pdev)
                 return -EINVAL;
 
+        pdata = emc_pdev->dev.platform_data;
+
         /*
          * The EMC clock rate is twice the bus rate, and the bus rate is
          * measured in kHz
          */
         rate = rate / 2 / 1000;
 
-        for (i = 0; i < tegra_emc_table_size; i++)
-                if (tegra_emc_table[i].rate == rate)
+        for (i = 0; i < pdata->num_tables; i++)
+                if (pdata->tables[i].rate == rate)
                         break;
 
-        if (i >= tegra_emc_table_size)
+        if (i >= pdata->num_tables)
                 return -EINVAL;
 
         pr_debug("%s: setting to %lu\n", __func__, rate);
 
         for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
-                emc_writel(tegra_emc_table[i].regs[j], emc_reg_addr[j]);
+                emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]);
 
-        emc_readl(tegra_emc_table[i].regs[TEGRA_EMC_NUM_REGS - 1]);
+        emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]);
 
         return 0;
 }
 
-void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
+#ifdef CONFIG_OF
+static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
+{
+        struct device_node *iter;
+        u32 reg;
+
+        for_each_child_of_node(np, iter) {
+                if (of_property_read_u32(np, "nvidia,ram-code", &reg))
+                        continue;
+                if (reg == tegra_bct_strapping)
+                        return of_node_get(iter);
+        }
+
+        return NULL;
+}
+
+static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
+                struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *tnp, *iter;
+        struct tegra_emc_pdata *pdata;
+        int ret, i, num_tables;
+
+        if (!np)
+                return NULL;
+
+        if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
+                tnp = tegra_emc_ramcode_devnode(np);
+                if (!tnp)
+                        dev_warn(&pdev->dev,
+                                 "can't find emc table for ram-code 0x%02x\n",
+                                 tegra_bct_strapping);
+        } else
+                tnp = of_node_get(np);
+
+        if (!tnp)
+                return NULL;
+
+        num_tables = 0;
+        for_each_child_of_node(tnp, iter)
+                if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table"))
+                        num_tables++;
+
+        if (!num_tables) {
+                pdata = NULL;
+                goto out;
+        }
+
+        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+        pdata->tables = devm_kzalloc(&pdev->dev,
+                                     sizeof(*pdata->tables) * num_tables,
+                                     GFP_KERNEL);
+
+        i = 0;
+        for_each_child_of_node(tnp, iter) {
+                u32 prop;
+
+                ret = of_property_read_u32(iter, "clock-frequency", &prop);
+                if (ret) {
+                        dev_err(&pdev->dev, "no clock-frequency in %s\n",
+                                iter->full_name);
+                        continue;
+                }
+                pdata->tables[i].rate = prop;
+
+                ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
+                                                 pdata->tables[i].regs,
+                                                 TEGRA_EMC_NUM_REGS);
+                if (ret) {
+                        dev_err(&pdev->dev,
+                                "malformed emc-registers property in %s\n",
+                                iter->full_name);
+                        continue;
+                }
+
+                i++;
+        }
+        pdata->num_tables = i;
+
+out:
+        of_node_put(tnp);
+        return pdata;
+}
+#else
+static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
+                struct platform_device *pdev)
+{
+        return NULL;
+}
+#endif
+
+static struct tegra_emc_pdata __devinit *tegra_emc_fill_pdata(struct platform_device *pdev)
+{
+        struct clk *c = clk_get_sys(NULL, "emc");
+        struct tegra_emc_pdata *pdata;
+        unsigned long khz;
+        int i;
+
+        WARN_ON(pdev->dev.platform_data);
+        BUG_ON(IS_ERR_OR_NULL(c));
+
+        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+        pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
+                                     GFP_KERNEL);
+
+        pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000;
+
+        for (i = 0; i < TEGRA_EMC_NUM_REGS; i++)
+                pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]);
+
+        pdata->num_tables = 1;
+
+        khz = pdata->tables[0].rate;
+        dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, "
+                 "%ld kHz mem\n", khz * 2, khz);
+
+        return pdata;
+}
+
+static int __devinit tegra_emc_probe(struct platform_device *pdev)
+{
+        struct tegra_emc_pdata *pdata;
+        struct resource *res;
+
+        if (!emc_enable) {
+                dev_err(&pdev->dev, "disabled per module parameter\n");
+                return -ENODEV;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "missing register base\n");
+                return -ENOMEM;
+        }
+
+        emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
+        if (!emc_regbase) {
+                dev_err(&pdev->dev, "failed to remap registers\n");
+                return -ENOMEM;
+        }
+
+        pdata = pdev->dev.platform_data;
+
+        if (!pdata)
+                pdata = tegra_emc_dt_parse_pdata(pdev);
+
+        if (!pdata)
+                pdata = tegra_emc_fill_pdata(pdev);
+
+        pdev->dev.platform_data = pdata;
+
+        emc_pdev = pdev;
+
+        return 0;
+}
+
+static struct of_device_id tegra_emc_of_match[] __devinitdata = {
+        { .compatible = "nvidia,tegra20-emc", },
+        { },
+};
+
+static struct platform_driver tegra_emc_driver = {
+        .driver         = {
+                .name   = "tegra-emc",
+                .owner  = THIS_MODULE,
+                .of_match_table = tegra_emc_of_match,
+        },
+        .probe          = tegra_emc_probe,
+};
+
+static int __init tegra_emc_init(void)
 {
-        tegra_emc_table = table;
-        tegra_emc_table_size = table_size;
+        return platform_driver_register(&tegra_emc_driver);
 }
+device_initcall(tegra_emc_init);
diff --git a/arch/arm/mach-tegra/tegra2_emc.h b/arch/arm/mach-tegra/tegra2_emc.h
index 19f08cb3160..f61409b54cb 100644
--- a/arch/arm/mach-tegra/tegra2_emc.h
+++ b/arch/arm/mach-tegra/tegra2_emc.h
@@ -15,13 +15,10 @@
  *
  */
 
-#define TEGRA_EMC_NUM_REGS 46
-
-struct tegra_emc_table {
-        unsigned long rate;
-        u32 regs[TEGRA_EMC_NUM_REGS];
-};
+#ifndef __MACH_TEGRA_TEGRA2_EMC_H_
+#define __MACH_TEGRA_TEGRA2_EMC_H
 
 int tegra_emc_set_rate(unsigned long rate);
 long tegra_emc_round_rate(unsigned long rate);
-void tegra_init_emc(const struct tegra_emc_table *table, int table_size);
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
new file mode 100644
index 00000000000..6d08b53f92d
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -0,0 +1,3099 @@
+/*
+ * arch/arm/mach-tegra/tegra30_clocks.c
+ *
+ * Copyright (c) 2010-2011 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/syscore_ops.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/iomap.h>
+
+#include "clock.h"
+#include "fuse.h"
+
+#define USE_PLL_LOCK_BITS 0
+
+#define RST_DEVICES_L                   0x004
+#define RST_DEVICES_H                   0x008
+#define RST_DEVICES_U                   0x00C
+#define RST_DEVICES_V                   0x358
+#define RST_DEVICES_W                   0x35C
+#define RST_DEVICES_SET_L               0x300
+#define RST_DEVICES_CLR_L               0x304
+#define RST_DEVICES_SET_V               0x430
+#define RST_DEVICES_CLR_V               0x434
+#define RST_DEVICES_NUM                 5
+
+#define CLK_OUT_ENB_L                   0x010
+#define CLK_OUT_ENB_H                   0x014
+#define CLK_OUT_ENB_U                   0x018
+#define CLK_OUT_ENB_V                   0x360
+#define CLK_OUT_ENB_W                   0x364
+#define CLK_OUT_ENB_SET_L               0x320
+#define CLK_OUT_ENB_CLR_L               0x324
+#define CLK_OUT_ENB_SET_V               0x440
+#define CLK_OUT_ENB_CLR_V               0x444
+#define CLK_OUT_ENB_NUM                 5
+
+#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
+#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN  (0x1 << 1)
+
+#define PERIPH_CLK_TO_BIT(c)            (1 << (c->u.periph.clk_num % 32))
+#define PERIPH_CLK_TO_RST_REG(c)        \
+        periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
+#define PERIPH_CLK_TO_RST_SET_REG(c)    \
+        periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
+#define PERIPH_CLK_TO_RST_CLR_REG(c)    \
+        periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
+
+#define PERIPH_CLK_TO_ENB_REG(c)        \
+        periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c)    \
+        periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
+#define PERIPH_CLK_TO_ENB_CLR_REG(c)    \
+        periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
+
+#define CLK_MASK_ARM                    0x44
+#define MISC_CLK_ENB                    0x48
+
+#define OSC_CTRL                        0x50
+#define OSC_CTRL_OSC_FREQ_MASK          (0xF<<28)
+#define OSC_CTRL_OSC_FREQ_13MHZ         (0x0<<28)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ       (0x4<<28)
+#define OSC_CTRL_OSC_FREQ_12MHZ         (0x8<<28)
+#define OSC_CTRL_OSC_FREQ_26MHZ         (0xC<<28)
+#define OSC_CTRL_OSC_FREQ_16_8MHZ       (0x1<<28)
+#define OSC_CTRL_OSC_FREQ_38_4MHZ       (0x5<<28)
+#define OSC_CTRL_OSC_FREQ_48MHZ         (0x9<<28)
+#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+
+#define OSC_CTRL_PLL_REF_DIV_MASK       (3<<26)
+#define OSC_CTRL_PLL_REF_DIV_1          (0<<26)
+#define OSC_CTRL_PLL_REF_DIV_2          (1<<26)
+#define OSC_CTRL_PLL_REF_DIV_4          (2<<26)
+
+#define OSC_FREQ_DET                    0x58
+#define OSC_FREQ_DET_TRIG               (1<<31)
+
+#define OSC_FREQ_DET_STATUS             0x5C
+#define OSC_FREQ_DET_BUSY               (1<<31)
+#define OSC_FREQ_DET_CNT_MASK           0xFFFF
+
+#define PERIPH_CLK_SOURCE_I2S1          0x100
+#define PERIPH_CLK_SOURCE_EMC           0x19c
+#define PERIPH_CLK_SOURCE_OSC           0x1fc
+#define PERIPH_CLK_SOURCE_NUM1 \
+        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
+
+#define PERIPH_CLK_SOURCE_G3D2          0x3b0
+#define PERIPH_CLK_SOURCE_SE            0x42c
+#define PERIPH_CLK_SOURCE_NUM2 \
+        ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
+
+#define AUDIO_DLY_CLK                   0x49c
+#define AUDIO_SYNC_CLK_SPDIF            0x4b4
+#define PERIPH_CLK_SOURCE_NUM3 \
+        ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
+
+#define PERIPH_CLK_SOURCE_NUM           (PERIPH_CLK_SOURCE_NUM1 + \
+                                         PERIPH_CLK_SOURCE_NUM2 + \
+                                         PERIPH_CLK_SOURCE_NUM3)
+
+#define CPU_SOFTRST_CTRL                0x380
+
+#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
+#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
+#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
+#define PERIPH_CLK_SOURCE_DIVIDLE_VAL   50
+#define PERIPH_CLK_UART_DIV_ENB         (1<<24)
+#define PERIPH_CLK_VI_SEL_EX_SHIFT      24
+#define PERIPH_CLK_VI_SEL_EX_MASK       (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
+#define PERIPH_CLK_NAND_DIV_EX_ENB      (1<<8)
+#define PERIPH_CLK_DTV_POLARITY_INV     (1<<25)
+
+#define AUDIO_SYNC_SOURCE_MASK          0x0F
+#define AUDIO_SYNC_DISABLE_BIT          0x10
+#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c)  ((c->reg_shift - 24) * 4)
+
+#define PLL_BASE                        0x0
+#define PLL_BASE_BYPASS                 (1<<31)
+#define PLL_BASE_ENABLE                 (1<<30)
+#define PLL_BASE_REF_ENABLE             (1<<29)
+#define PLL_BASE_OVERRIDE               (1<<28)
+#define PLL_BASE_LOCK                   (1<<27)
+#define PLL_BASE_DIVP_MASK              (0x7<<20)
+#define PLL_BASE_DIVP_SHIFT             20
+#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT             8
+#define PLL_BASE_DIVM_MASK              (0x1F)
+#define PLL_BASE_DIVM_SHIFT             0
+
+#define PLL_OUT_RATIO_MASK              (0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT             8
+#define PLL_OUT_OVERRIDE                (1<<2)
+#define PLL_OUT_CLKEN                   (1<<1)
+#define PLL_OUT_RESET_DISABLE           (1<<0)
+
+#define PLL_MISC(c)                     \
+        (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+#define PLL_MISC_LOCK_ENABLE(c) \
+        (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
+
+#define PLL_MISC_DCCON_SHIFT            20
+#define PLL_MISC_CPCON_SHIFT            8
+#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT            4
+#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT           0
+#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
+#define PLLD_MISC_CLKENABLE             (1<<30)
+
+#define PLLU_BASE_POST_DIV              (1<<20)
+
+#define PLLD_BASE_DSIB_MUX_SHIFT        25
+#define PLLD_BASE_DSIB_MUX_MASK         (1<<PLLD_BASE_DSIB_MUX_SHIFT)
+#define PLLD_BASE_CSI_CLKENABLE         (1<<26)
+#define PLLD_MISC_DSI_CLKENABLE         (1<<30)
+#define PLLD_MISC_DIV_RST               (1<<23)
+#define PLLD_MISC_DCCON_SHIFT           12
+
+#define PLLDU_LFCON_SET_DIVN            600
+
+/* FIXME: OUT_OF_TABLE_CPCON per pll */
+#define OUT_OF_TABLE_CPCON              0x8
+
+#define SUPER_CLK_MUX                   0x00
+#define SUPER_STATE_SHIFT               28
+#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
+#define SUPER_LP_DIV2_BYPASS            (0x1 << 16)
+#define SUPER_SOURCE_MASK               0xF
+#define SUPER_FIQ_SOURCE_SHIFT          12
+#define SUPER_IRQ_SOURCE_SHIFT          8
+#define SUPER_RUN_SOURCE_SHIFT          4
+#define SUPER_IDLE_SOURCE_SHIFT         0
+
+#define SUPER_CLK_DIVIDER               0x04
+#define SUPER_CLOCK_DIV_U71_SHIFT       16
+#define SUPER_CLOCK_DIV_U71_MASK        (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
+/* guarantees safe cpu backup */
+#define SUPER_CLOCK_DIV_U71_MIN         0x2
+
+#define BUS_CLK_DISABLE                 (1<<3)
+#define BUS_CLK_DIV_MASK                0x3
+
+#define PMC_CTRL                        0x0
+ #define PMC_CTRL_BLINK_ENB             (1 << 7)
+
+#define PMC_DPD_PADS_ORIDE              0x1c
+ #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
+
+#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
+#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
+#define PMC_BLINK_TIMER_ENB             (1 << 15)
+#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
+#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
+
+#define PMC_PLLP_WB0_OVERRIDE                           0xf8
+#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE               (1 << 12)
+
+#define UTMIP_PLL_CFG2                                  0x488
+#define UTMIP_PLL_CFG2_STABLE_COUNT(x)                  (((x) & 0xfff) << 6)
+#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x)              (((x) & 0x3f) << 18)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN        (1 << 0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN        (1 << 2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN        (1 << 4)
+
+#define UTMIP_PLL_CFG1                                  0x484
+#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x)              (((x) & 0x1f) << 27)
+#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x)               (((x) & 0xfff) << 0)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN       (1 << 14)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN       (1 << 12)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN             (1 << 16)
+
+#define PLLE_BASE_CML_ENABLE            (1<<31)
+#define PLLE_BASE_ENABLE                (1<<30)
+#define PLLE_BASE_DIVCML_SHIFT          24
+#define PLLE_BASE_DIVCML_MASK           (0xf<<PLLE_BASE_DIVCML_SHIFT)
+#define PLLE_BASE_DIVP_SHIFT            16
+#define PLLE_BASE_DIVP_MASK             (0x3f<<PLLE_BASE_DIVP_SHIFT)
+#define PLLE_BASE_DIVN_SHIFT            8
+#define PLLE_BASE_DIVN_MASK             (0xFF<<PLLE_BASE_DIVN_SHIFT)
+#define PLLE_BASE_DIVM_SHIFT            0
+#define PLLE_BASE_DIVM_MASK             (0xFF<<PLLE_BASE_DIVM_SHIFT)
+#define PLLE_BASE_DIV_MASK              \
+        (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
+         PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
+#define PLLE_BASE_DIV(m, n, p, cml)             \
+         (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
+          ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
+
+#define PLLE_MISC_SETUP_BASE_SHIFT      16
+#define PLLE_MISC_SETUP_BASE_MASK       (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
+#define PLLE_MISC_READY                 (1<<15)
+#define PLLE_MISC_LOCK                  (1<<11)
+#define PLLE_MISC_LOCK_ENABLE           (1<<9)
+#define PLLE_MISC_SETUP_EX_SHIFT        2
+#define PLLE_MISC_SETUP_EX_MASK         (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
+#define PLLE_MISC_SETUP_MASK            \
+          (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
+#define PLLE_MISC_SETUP_VALUE           \
+          ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
+
+#define PLLE_SS_CTRL                    0x68
+#define PLLE_SS_INCINTRV_SHIFT          24
+#define PLLE_SS_INCINTRV_MASK           (0x3f<<PLLE_SS_INCINTRV_SHIFT)
+#define PLLE_SS_INC_SHIFT               16
+#define PLLE_SS_INC_MASK                (0xff<<PLLE_SS_INC_SHIFT)
+#define PLLE_SS_MAX_SHIFT               0
+#define PLLE_SS_MAX_MASK                (0x1ff<<PLLE_SS_MAX_SHIFT)
+#define PLLE_SS_COEFFICIENTS_MASK       \
+        (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
+#define PLLE_SS_COEFFICIENTS_12MHZ      \
+        ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
+         (0x24<<PLLE_SS_MAX_SHIFT))
+#define PLLE_SS_DISABLE                 ((1<<12) | (1<<11) | (1<<10))
+
+#define PLLE_AUX                        0x48c
+#define PLLE_AUX_PLLP_SEL               (1<<2)
+#define PLLE_AUX_CML_SATA_ENABLE        (1<<1)
+#define PLLE_AUX_CML_PCIE_ENABLE        (1<<0)
+
+#define PMC_SATA_PWRGT                  0x1ac
+#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE  (1<<5)
+#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL  (1<<4)
+
+#define ROUND_DIVIDER_UP        0
+#define ROUND_DIVIDER_DOWN      1
+
+/* FIXME: recommended safety delay after lock is detected */
+#define PLL_POST_LOCK_DELAY             100
+
+/**
+* Structure defining the fields for USB UTMI clocks Parameters.
+*/
+struct utmi_clk_param {
+        /* Oscillator Frequency in KHz */
+        u32 osc_frequency;
+        /* UTMIP PLL Enable Delay Count  */
+        u8 enable_delay_count;
+        /* UTMIP PLL Stable count */
+        u8 stable_count;
+        /*  UTMIP PLL Active delay count */
+        u8 active_delay_count;
+        /* UTMIP PLL Xtal frequency count */
+        u8 xtal_freq_count;
+};
+
+static const struct utmi_clk_param utmi_parameters[] = {
+        {
+                .osc_frequency = 13000000,
+                .enable_delay_count = 0x02,
+                .stable_count = 0x33,
+                .active_delay_count = 0x05,
+                .xtal_freq_count = 0x7F
+        },
+        {
+                .osc_frequency = 19200000,
+                .enable_delay_count = 0x03,
+                .stable_count = 0x4B,
+                .active_delay_count = 0x06,
+                .xtal_freq_count = 0xBB},
+        {
+                .osc_frequency = 12000000,
+                .enable_delay_count = 0x02,
+                .stable_count = 0x2F,
+                .active_delay_count = 0x04,
+                .xtal_freq_count = 0x76
+        },
+        {
+                .osc_frequency = 26000000,
+                .enable_delay_count = 0x04,
+                .stable_count = 0x66,
+                .active_delay_count = 0x09,
+                .xtal_freq_count = 0xFE
+        },
+        {
+                .osc_frequency = 16800000,
+                .enable_delay_count = 0x03,
+                .stable_count = 0x41,
+                .active_delay_count = 0x0A,
+                .xtal_freq_count = 0xA4
+        },
+};
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+
+#define MISC_GP_HIDREV                  0x804
+
+/*
+ * Some peripheral clocks share an enable bit, so refcount the enable bits
+ * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
+ */
+static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
+
+#define clk_writel(value, reg) \
+        __raw_writel(value, (u32)reg_clk_base + (reg))
+#define clk_readl(reg) \
+        __raw_readl((u32)reg_clk_base + (reg))
+#define pmc_writel(value, reg) \
+        __raw_writel(value, (u32)reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+        __raw_readl((u32)reg_pmc_base + (reg))
+#define chipid_readl() \
+        __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
+
+#define clk_writel_delay(value, reg)                                    \
+        do {                                                            \
+                __raw_writel((value), (u32)reg_clk_base + (reg));       \
+                udelay(2);                                              \
+        } while (0)
+
+
+static inline int clk_set_div(struct clk *c, u32 n)
+{
+        return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
+}
+
+static inline u32 periph_clk_to_reg(
+        struct clk *c, u32 reg_L, u32 reg_V, int offs)
+{
+        u32 reg = c->u.periph.clk_num / 32;
+        BUG_ON(reg >= RST_DEVICES_NUM);
+        if (reg < 3)
+                reg = reg_L + (reg * offs);
+        else
+                reg = reg_V + ((reg - 3) * offs);
+        return reg;
+}
+
+static unsigned long clk_measure_input_freq(void)
+{
+        u32 clock_autodetect;
+        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
+        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
+                return 12000000;
+        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
+                return 13000000;
+        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
+                return 19200000;
+        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
+                return 26000000;
+        } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
+                return 16800000;
+        } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
+                return 38400000;
+        } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
+                return 48000000;
+        } else {
+                pr_err("%s: Unexpected clock autodetect value %d", __func__,
+                        clock_autodetect);
+                BUG();
+                return 0;
+        }
+}
+
+static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
+                                 u32 flags, u32 round_mode)
+{
+        s64 divider_u71 = parent_rate;
+        if (!rate)
+                return -EINVAL;
+
+        if (!(flags & DIV_U71_INT))
+                divider_u71 *= 2;
+        if (round_mode == ROUND_DIVIDER_UP)
+                divider_u71 += rate - 1;
+        do_div(divider_u71, rate);
+        if (flags & DIV_U71_INT)
+                divider_u71 *= 2;
+
+        if (divider_u71 - 2 < 0)
+                return 0;
+
+        if (divider_u71 - 2 > 255)
+                return -EINVAL;
+
+        return divider_u71 - 2;
+}
+
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u16;
+
+        divider_u16 = parent_rate;
+        if (!rate)
+                return -EINVAL;
+        divider_u16 += rate - 1;
+        do_div(divider_u16, rate);
+
+        if (divider_u16 - 1 < 0)
+                return 0;
+
+        if (divider_u16 - 1 > 0xFFFF)
+                return -EINVAL;
+
+        return divider_u16 - 1;
+}
+
+/* clk_m functions */
+static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
+{
+        u32 osc_ctrl = clk_readl(OSC_CTRL);
+        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
+        u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
+
+        c->rate = clk_measure_input_freq();
+        switch (c->rate) {
+        case 12000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 13000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 19200000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 26000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 16800000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 38400000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
+                break;
+        case 48000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
+                break;
+        default:
+                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+                BUG();
+        }
+        clk_writel(auto_clock_control, OSC_CTRL);
+        return c->rate;
+}
+
+static void tegra30_clk_m_init(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        tegra30_clk_m_autodetect_rate(c);
+}
+
+static int tegra30_clk_m_enable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        return 0;
+}
+
+static void tegra30_clk_m_disable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        WARN(1, "Attempting to disable main SoC clock\n");
+}
+
+static struct clk_ops tegra_clk_m_ops = {
+        .init           = tegra30_clk_m_init,
+        .enable         = tegra30_clk_m_enable,
+        .disable        = tegra30_clk_m_disable,
+};
+
+static struct clk_ops tegra_clk_m_div_ops = {
+        .enable         = tegra30_clk_m_enable,
+};
+
+/* PLL reference divider functions */
+static void tegra30_pll_ref_init(struct clk *c)
+{
+        u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        switch (pll_ref_div) {
+        case OSC_CTRL_PLL_REF_DIV_1:
+                c->div = 1;
+                break;
+        case OSC_CTRL_PLL_REF_DIV_2:
+                c->div = 2;
+                break;
+        case OSC_CTRL_PLL_REF_DIV_4:
+                c->div = 4;
+                break;
+        default:
+                pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
+                BUG();
+        }
+        c->mul = 1;
+        c->state = ON;
+}
+
+static struct clk_ops tegra_pll_ref_ops = {
+        .init           = tegra30_pll_ref_init,
+        .enable         = tegra30_clk_m_enable,
+        .disable        = tegra30_clk_m_disable,
+};
+
+/* super clock functions */
+/* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
+ * clock skipping super divider.  We will ignore the clock skipping divider,
+ * since we can't lower the voltage when using the clock skip, but we can if
+ * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
+ * only when its parent is a fixed rate PLL, since we can't change PLL rate
+ * in this case.
+ */
+static void tegra30_super_clk_init(struct clk *c)
+{
+        u32 val;
+        int source;
+        int shift;
+        const struct clk_mux_sel *sel;
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        c->state = ON;
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        if (c->flags & DIV_2)
+                source |= val & SUPER_LP_DIV2_BYPASS;
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->value == source)
+                        break;
+        }
+        BUG_ON(sel->input == NULL);
+        c->parent = sel->input;
+
+        if (c->flags & DIV_U71) {
+                /* Init safe 7.1 divider value (does not affect PLLX path) */
+                clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
+                           c->reg + SUPER_CLK_DIVIDER);
+                c->mul = 2;
+                c->div = 2;
+                if (!(c->parent->flags & PLLX))
+                        c->div += SUPER_CLOCK_DIV_U71_MIN;
+        } else
+                clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+}
+
+static int tegra30_super_clk_enable(struct clk *c)
+{
+        return 0;
+}
+
+static void tegra30_super_clk_disable(struct clk *c)
+{
+        /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
+           geared up g-mode super clock - mode switch may request to disable
+           either of them; accept request with no affect on h/w */
+}
+
+static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        const struct clk_mux_sel *sel;
+        int shift;
+
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        /* For LP mode super-clock switch between PLLX direct
+                           and divided-by-2 outputs is allowed only when other
+                           than PLLX clock source is current parent */
+                        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
+                            ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
+                                if (c->parent->flags & PLLX)
+                                        return -EINVAL;
+                                val ^= SUPER_LP_DIV2_BYPASS;
+                                clk_writel_delay(val, c->reg);
+                        }
+                        val &= ~(SUPER_SOURCE_MASK << shift);
+                        val |= (sel->value & SUPER_SOURCE_MASK) << shift;
+
+                        /* 7.1 divider for CPU super-clock does not affect
+                           PLLX path */
+                        if (c->flags & DIV_U71) {
+                                u32 div = 0;
+                                if (!(p->flags & PLLX)) {
+                                        div = clk_readl(c->reg +
+                                                        SUPER_CLK_DIVIDER);
+                                        div &= SUPER_CLOCK_DIV_U71_MASK;
+                                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
+                                }
+                                c->div = div + 2;
+                                c->mul = 2;
+                        }
+
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        clk_writel_delay(val, c->reg);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+/*
+ * Do not use super clocks "skippers", since dividing using a clock skipper
+ * does not allow the voltage to be scaled down. Instead adjust the rate of
+ * the parent clock. This requires that the parent of a super clock have no
+ * other children, otherwise the rate will change underneath the other
+ * children. Special case: if fixed rate PLL is CPU super clock parent the
+ * rate of this PLL can't be changed, and it has many other children. In
+ * this case use 7.1 fractional divider to adjust the super clock rate.
+ */
+static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
+                int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
+                                        rate, c->flags, ROUND_DIVIDER_DOWN);
+                div = max(div, SUPER_CLOCK_DIV_U71_MIN);
+
+                clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
+                           c->reg + SUPER_CLK_DIVIDER);
+                c->div = div + 2;
+                c->mul = 2;
+                return 0;
+        }
+        return clk_set_rate(c->parent, rate);
+}
+
+static struct clk_ops tegra_super_ops = {
+        .init                   = tegra30_super_clk_init,
+        .enable                 = tegra30_super_clk_enable,
+        .disable                = tegra30_super_clk_disable,
+        .set_parent             = tegra30_super_clk_set_parent,
+        .set_rate               = tegra30_super_clk_set_rate,
+};
+
+static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        /* The input value 'rate' is the clock rate of the CPU complex. */
+        c->rate = (rate * c->mul) / c->div;
+        return 0;
+}
+
+static struct clk_ops tegra30_twd_ops = {
+        .set_rate       = tegra30_twd_clk_set_rate,
+};
+
+/* Blink output functions */
+
+static void tegra30_blink_clk_init(struct clk *c)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
+        c->mul = 1;
+        val = pmc_readl(c->reg);
+
+        if (val & PMC_BLINK_TIMER_ENB) {
+                unsigned int on_off;
+
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                c->div = on_off * 4;
+        } else {
+                c->div = 1;
+        }
+}
+
+static int tegra30_blink_clk_enable(struct clk *c)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        return 0;
+}
+
+static void tegra30_blink_clk_disable(struct clk *c)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+}
+
+static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        if (rate >= parent_rate) {
+                c->div = 1;
+                pmc_writel(0, c->reg);
+        } else {
+                unsigned int on_off;
+                u32 val;
+
+                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
+                c->div = on_off * 8;
+
+                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
+                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
+                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val |= on_off;
+                val |= PMC_BLINK_TIMER_ENB;
+                pmc_writel(val, c->reg);
+        }
+
+        return 0;
+}
+
+static struct clk_ops tegra_blink_clk_ops = {
+        .init                   = &tegra30_blink_clk_init,
+        .enable                 = &tegra30_blink_clk_enable,
+        .disable                = &tegra30_blink_clk_disable,
+        .set_rate               = &tegra30_blink_clk_set_rate,
+};
+
+/* PLL Functions */
+static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
+                                         u32 lock_bit)
+{
+#if USE_PLL_LOCK_BITS
+        int i;
+        for (i = 0; i < c->u.pll.lock_delay; i++) {
+                if (clk_readl(lock_reg) & lock_bit) {
+                        udelay(PLL_POST_LOCK_DELAY);
+                        return 0;
+                }
+                udelay(2);              /* timeout = 2 * lock time */
+        }
+        pr_err("Timed out waiting for lock bit on pll %s", c->name);
+        return -1;
+#endif
+        udelay(c->u.pll.lock_delay);
+
+        return 0;
+}
+
+
+static void tegra30_utmi_param_configure(struct clk *c)
+{
+        u32 reg;
+        int i;
+        unsigned long main_rate =
+                clk_get_rate(c->parent->parent);
+
+        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
+                if (main_rate == utmi_parameters[i].osc_frequency)
+                        break;
+        }
+
+        if (i >= ARRAY_SIZE(utmi_parameters)) {
+                pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
+                return;
+        }
+
+        reg = clk_readl(UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL stable and active counts */
+        /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
+        reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
+        reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
+                        utmi_parameters[i].stable_count);
+
+        reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
+                        utmi_parameters[i].active_delay_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+
+        clk_writel(reg, UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL delay and oscillator frequency counts */
+        reg = clk_readl(UTMIP_PLL_CFG1);
+        reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
+                utmi_parameters[i].enable_delay_count);
+
+        reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
+        reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
+                utmi_parameters[i].xtal_freq_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
+
+        clk_writel(reg, UTMIP_PLL_CFG1);
+}
+
+static void tegra30_pll_clk_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg + PLL_BASE);
+
+        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                unsigned long input_rate = clk_get_rate(c->parent);
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == input_rate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                return;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n", c->name);
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
+                                        PLL_BASE_DIVP_SHIFT));
+                if (c->flags & PLL_FIXED) {
+                        unsigned long rate = clk_get_rate_locked(c);
+                        BUG_ON(rate != c->u.pll.fixed_rate);
+                }
+        }
+
+        if (c->flags & PLLU)
+                tegra30_utmi_param_configure(c);
+}
+
+static int tegra30_pll_clk_enable(struct clk *c)
+{
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+#if USE_PLL_LOCK_BITS
+        val = clk_readl(c->reg + PLL_MISC(c));
+        val |= PLL_MISC_LOCK_ENABLE(c);
+        clk_writel(val, c->reg + PLL_MISC(c));
+#endif
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~PLL_BASE_BYPASS;
+        val |= PLL_BASE_ENABLE;
+        clk_writel(val, c->reg + PLL_BASE);
+
+        if (c->flags & PLLM) {
+                val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
+                val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
+                pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
+        }
+
+        tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
+
+        return 0;
+}
+
+static void tegra30_pll_clk_disable(struct clk *c)
+{
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        val = clk_readl(c->reg);
+        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        clk_writel(val, c->reg);
+
+        if (c->flags & PLLM) {
+                val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
+                val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
+                pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
+        }
+}
+
+static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val, p_div, old_base;
+        unsigned long input_rate;
+        const struct clk_pll_freq_table *sel;
+        struct clk_pll_freq_table cfg;
+
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & PLL_FIXED) {
+                int ret = 0;
+                if (rate != c->u.pll.fixed_rate) {
+                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
+                               __func__, c->name, c->u.pll.fixed_rate, rate);
+                        ret = -EINVAL;
+                }
+                return ret;
+        }
+
+        if (c->flags & PLLM) {
+                if (rate != clk_get_rate_locked(c)) {
+                        pr_err("%s: Can not change memory %s rate in flight\n",
+                               __func__, c->name);
+                        return -EINVAL;
+                }
+                return 0;
+        }
+
+        p_div = 0;
+        input_rate = clk_get_rate(c->parent);
+
+        /* Check if the target rate is tabulated */
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        if (c->flags & PLLU) {
+                                BUG_ON(sel->p < 1 || sel->p > 2);
+                                if (sel->p == 1)
+                                        p_div = PLLU_BASE_POST_DIV;
+                        } else {
+                                BUG_ON(sel->p < 1);
+                                for (val = sel->p; val > 1; val >>= 1)
+                                        p_div++;
+                                p_div <<= PLL_BASE_DIVP_SHIFT;
+                        }
+                        break;
+                }
+        }
+
+        /* Configure out-of-table rate */
+        if (sel->input_rate == 0) {
+                unsigned long cfreq;
+                BUG_ON(c->flags & PLLU);
+                sel = &cfg;
+
+                switch (input_rate) {
+                case 12000000:
+                case 26000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+                        break;
+                case 13000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+                        break;
+                case 16800000:
+                case 19200000:
+                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+                        break;
+                default:
+                        pr_err("%s: Unexpected reference rate %lu\n",
+                               __func__, input_rate);
+                        BUG();
+                }
+
+                /* Raise VCO to guarantee 0.5% accuracy */
+                for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
+                      cfg.output_rate <<= 1)
+                        p_div++;
+
+                cfg.p = 0x1 << p_div;
+                cfg.m = input_rate / cfreq;
+                cfg.n = cfg.output_rate / cfreq;
+                cfg.cpcon = OUT_OF_TABLE_CPCON;
+
+                if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
+                    (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
+                    (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
+                    (cfg.output_rate > c->u.pll.vco_max)) {
+                        pr_err("%s: Failed to set %s out-of-table rate %lu\n",
+                               __func__, c->name, rate);
+                        return -EINVAL;
+                }
+                p_div <<= PLL_BASE_DIVP_SHIFT;
+        }
+
+        c->mul = sel->n;
+        c->div = sel->m * sel->p;
+
+        old_base = val = clk_readl(c->reg + PLL_BASE);
+        val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
+                 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
+        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+                (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
+        if (val == old_base)
+                return 0;
+
+        if (c->state == ON) {
+                tegra30_pll_clk_disable(c);
+                val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        }
+        clk_writel(val, c->reg + PLL_BASE);
+
+        if (c->flags & PLL_HAS_CPCON) {
+                val = clk_readl(c->reg + PLL_MISC(c));
+                val &= ~PLL_MISC_CPCON_MASK;
+                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
+                if (c->flags & (PLLU | PLLD)) {
+                        val &= ~PLL_MISC_LFCON_MASK;
+                        if (sel->n >= PLLDU_LFCON_SET_DIVN)
+                                val |= 0x1 << PLL_MISC_LFCON_SHIFT;
+                } else if (c->flags & (PLLX | PLLM)) {
+                        val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
+                        if (rate >= (c->u.pll.vco_max >> 1))
+                                val |= 0x1 << PLL_MISC_DCCON_SHIFT;
+                }
+                clk_writel(val, c->reg + PLL_MISC(c));
+        }
+
+        if (c->state == ON)
+                tegra30_pll_clk_enable(c);
+
+        return 0;
+}
+
+static struct clk_ops tegra_pll_ops = {
+        .init                   = tegra30_pll_clk_init,
+        .enable                 = tegra30_pll_clk_enable,
+        .disable                = tegra30_pll_clk_disable,
+        .set_rate               = tegra30_pll_clk_set_rate,
+};
+
+static int
+tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        u32 val, mask, reg;
+
+        switch (p) {
+        case TEGRA_CLK_PLLD_CSI_OUT_ENB:
+                mask = PLLD_BASE_CSI_CLKENABLE;
+                reg = c->reg + PLL_BASE;
+                break;
+        case TEGRA_CLK_PLLD_DSI_OUT_ENB:
+                mask = PLLD_MISC_DSI_CLKENABLE;
+                reg = c->reg + PLL_MISC(c);
+                break;
+        case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
+                if (!(c->flags & PLL_ALT_MISC_REG)) {
+                        mask = PLLD_BASE_DSIB_MUX_MASK;
+                        reg = c->reg + PLL_BASE;
+                        break;
+                }
+        /* fall through - error since PLLD2 does not have MUX_SEL control */
+        default:
+                return -EINVAL;
+        }
+
+        val = clk_readl(reg);
+        if (setting)
+                val |= mask;
+        else
+                val &= ~mask;
+        clk_writel(val, reg);
+        return 0;
+}
+
+static struct clk_ops tegra_plld_ops = {
+        .init                   = tegra30_pll_clk_init,
+        .enable                 = tegra30_pll_clk_enable,
+        .disable                = tegra30_pll_clk_disable,
+        .set_rate               = tegra30_pll_clk_set_rate,
+        .clk_cfg_ex             = tegra30_plld_clk_cfg_ex,
+};
+
+static void tegra30_plle_clk_init(struct clk *c)
+{
+        u32 val;
+
+        val = clk_readl(PLLE_AUX);
+        c->parent = (val & PLLE_AUX_PLLP_SEL) ?
+                tegra_get_clock_by_name("pll_p") :
+                tegra_get_clock_by_name("pll_ref");
+
+        val = clk_readl(c->reg + PLL_BASE);
+        c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
+        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
+        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+}
+
+static void tegra30_plle_clk_disable(struct clk *c)
+{
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
+        clk_writel(val, c->reg + PLL_BASE);
+}
+
+static void tegra30_plle_training(struct clk *c)
+{
+        u32 val;
+
+        /* PLLE is already disabled, and setup cleared;
+         * create falling edge on PLLE IDDQ input */
+        val = pmc_readl(PMC_SATA_PWRGT);
+        val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
+        pmc_writel(val, PMC_SATA_PWRGT);
+
+        val = pmc_readl(PMC_SATA_PWRGT);
+        val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
+        pmc_writel(val, PMC_SATA_PWRGT);
+
+        val = pmc_readl(PMC_SATA_PWRGT);
+        val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
+        pmc_writel(val, PMC_SATA_PWRGT);
+
+        do {
+                val = clk_readl(c->reg + PLL_MISC(c));
+        } while (!(val & PLLE_MISC_READY));
+}
+
+static int tegra30_plle_configure(struct clk *c, bool force_training)
+{
+        u32 val;
+        const struct clk_pll_freq_table *sel;
+        unsigned long rate = c->u.pll.fixed_rate;
+        unsigned long input_rate = clk_get_rate(c->parent);
+
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate)
+                        break;
+        }
+
+        if (sel->input_rate == 0)
+                return -ENOSYS;
+
+        /* disable PLLE, clear setup fiels */
+        tegra30_plle_clk_disable(c);
+
+        val = clk_readl(c->reg + PLL_MISC(c));
+        val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
+        clk_writel(val, c->reg + PLL_MISC(c));
+
+        /* training */
+        val = clk_readl(c->reg + PLL_MISC(c));
+        if (force_training || (!(val & PLLE_MISC_READY)))
+                tegra30_plle_training(c);
+
+        /* configure dividers, setup, disable SS */
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~PLLE_BASE_DIV_MASK;
+        val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
+        clk_writel(val, c->reg + PLL_BASE);
+        c->mul = sel->n;
+        c->div = sel->m * sel->p;
+
+        val = clk_readl(c->reg + PLL_MISC(c));
+        val |= PLLE_MISC_SETUP_VALUE;
+        val |= PLLE_MISC_LOCK_ENABLE;
+        clk_writel(val, c->reg + PLL_MISC(c));
+
+        val = clk_readl(PLLE_SS_CTRL);
+        val |= PLLE_SS_DISABLE;
+        clk_writel(val, PLLE_SS_CTRL);
+
+        /* enable and lock PLLE*/
+        val = clk_readl(c->reg + PLL_BASE);
+        val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
+        clk_writel(val, c->reg + PLL_BASE);
+
+        tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
+
+        return 0;
+}
+
+static int tegra30_plle_clk_enable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        return tegra30_plle_configure(c, !c->set);
+}
+
+static struct clk_ops tegra_plle_ops = {
+        .init                   = tegra30_plle_clk_init,
+        .enable                 = tegra30_plle_clk_enable,
+        .disable                = tegra30_plle_clk_disable,
+};
+
+/* Clock divider ops */
+static void tegra30_pll_div_clk_init(struct clk *c)
+{
+        if (c->flags & DIV_U71) {
+                u32 divu71;
+                u32 val = clk_readl(c->reg);
+                val >>= c->reg_shift;
+                c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+                if (!(val & PLL_OUT_RESET_DISABLE))
+                        c->state = OFF;
+
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                c->state = ON;
+                if (c->flags & (PLLD | PLLX)) {
+                        c->div = 2;
+                        c->mul = 1;
+                } else
+                        BUG();
+        } else {
+                c->state = ON;
+                c->div = 1;
+                c->mul = 1;
+        }
+}
+
+static int tegra30_pll_div_clk_enable(struct clk *c)
+{
+        u32 val;
+        u32 new_val;
+
+        pr_debug("%s: %s\n", __func__, c->name);
+        if (c->flags & DIV_U71) {
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel_delay(val, c->reg);
+                return 0;
+        } else if (c->flags & DIV_2) {
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static void tegra30_pll_div_clk_disable(struct clk *c)
+{
+        u32 val;
+        u32 new_val;
+
+        pr_debug("%s: %s\n", __func__, c->name);
+        if (c->flags & DIV_U71) {
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel_delay(val, c->reg);
+        }
+}
+
+static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val;
+        u32 new_val;
+        int divider_u71;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+        if (c->flags & DIV_U71) {
+                divider_u71 = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider_u71 >= 0) {
+                        val = clk_readl(c->reg);
+                        new_val = val >> c->reg_shift;
+                        new_val &= 0xFFFF;
+                        if (c->flags & DIV_U71_FIXED)
+                                new_val |= PLL_OUT_OVERRIDE;
+                        new_val &= ~PLL_OUT_RATIO_MASK;
+                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+
+                        val &= ~(0xFFFF << c->reg_shift);
+                        val |= new_val << c->reg_shift;
+                        clk_writel_delay(val, c->reg);
+                        c->div = divider_u71 + 2;
+                        c->mul = 2;
+                        return 0;
+                }
+        } else if (c->flags & DIV_2)
+                return clk_set_rate(c->parent, rate * 2);
+
+        return -EINVAL;
+}
+
+static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+{
+        int divider;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_2)
+                /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
+                return rate;
+
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_pll_div_ops = {
+        .init                   = tegra30_pll_div_clk_init,
+        .enable                 = tegra30_pll_div_clk_enable,
+        .disable                = tegra30_pll_div_clk_disable,
+        .set_rate               = tegra30_pll_div_clk_set_rate,
+        .round_rate             = tegra30_pll_div_clk_round_rate,
+};
+
+/* Periph clk ops */
+static inline u32 periph_clk_source_mask(struct clk *c)
+{
+        if (c->flags & MUX8)
+                return 7 << 29;
+        else if (c->flags & MUX_PWM)
+                return 3 << 28;
+        else if (c->flags & MUX_CLK_OUT)
+                return 3 << (c->u.periph.clk_num + 4);
+        else if (c->flags & PLLD)
+                return PLLD_BASE_DSIB_MUX_MASK;
+        else
+                return 3 << 30;
+}
+
+static inline u32 periph_clk_source_shift(struct clk *c)
+{
+        if (c->flags & MUX8)
+                return 29;
+        else if (c->flags & MUX_PWM)
+                return 28;
+        else if (c->flags & MUX_CLK_OUT)
+                return c->u.periph.clk_num + 4;
+        else if (c->flags & PLLD)
+                return PLLD_BASE_DSIB_MUX_SHIFT;
+        else
+                return 30;
+}
+
+static void tegra30_periph_clk_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        const struct clk_mux_sel *mux = 0;
+        const struct clk_mux_sel *sel;
+        if (c->flags & MUX) {
+                for (sel = c->inputs; sel->input != NULL; sel++) {
+                        if (((val & periph_clk_source_mask(c)) >>
+                            periph_clk_source_shift(c)) == sel->value)
+                                mux = sel;
+                }
+                BUG_ON(!mux);
+
+                c->parent = mux->input;
+        } else {
+                c->parent = c->inputs[0].input;
+        }
+
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                if ((c->flags & DIV_U71_UART) &&
+                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
+                        divu71 = 0;
+                }
+                if (c->flags & DIV_U71_IDLE) {
+                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        clk_writel(val, c->reg);
+                }
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+
+        c->state = ON;
+        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
+                c->state = OFF;
+        if (!(c->flags & PERIPH_NO_RESET))
+                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
+                        c->state = OFF;
+}
+
+static int tegra30_periph_clk_enable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
+                return 0;
+
+        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (!(c->flags & PERIPH_NO_RESET) &&
+                 !(c->flags & PERIPH_MANUAL_RESET)) {
+                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
+                         PERIPH_CLK_TO_BIT(c)) {
+                        udelay(5);      /* reset propagation delay */
+                        clk_writel(PERIPH_CLK_TO_BIT(c),
+                                 PERIPH_CLK_TO_RST_CLR_REG(c));
+                }
+        }
+        return 0;
+}
+
+static void tegra30_periph_clk_disable(struct clk *c)
+{
+        unsigned long val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        if (c->refcnt)
+                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
+                /* If peripheral is in the APB bus then read the APB bus to
+                 * flush the write operation in apb bus. This will avoid the
+                 * peripheral access after disabling clock*/
+                if (c->flags & PERIPH_ON_APB)
+                        val = chipid_readl();
+
+                clk_writel_delay(
+                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
+        }
+}
+
+static void tegra30_periph_clk_reset(struct clk *c, bool assert)
+{
+        unsigned long val;
+        pr_debug("%s %s on clock %s\n", __func__,
+                 assert ? "assert" : "deassert", c->name);
+
+        if (!(c->flags & PERIPH_NO_RESET)) {
+                if (assert) {
+                        /* If peripheral is in the APB bus then read the APB
+                         * bus to flush the write operation in apb bus. This
+                         * will avoid the peripheral access after disabling
+                         * clock */
+                        if (c->flags & PERIPH_ON_APB)
+                                val = chipid_readl();
+
+                        clk_writel(PERIPH_CLK_TO_BIT(c),
+                                   PERIPH_CLK_TO_RST_SET_REG(c));
+                } else
+                        clk_writel(PERIPH_CLK_TO_BIT(c),
+                                   PERIPH_CLK_TO_RST_CLR_REG(c));
+        }
+}
+
+static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        const struct clk_mux_sel *sel;
+        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+        if (!(c->flags & MUX))
+                return (p == c->parent) ? 0 : (-EINVAL);
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        val = clk_readl(c->reg);
+                        val &= ~periph_clk_source_mask(c);
+                        val |= (sel->value << periph_clk_source_shift(c));
+
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        clk_writel_delay(val, c->reg);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val;
+        int divider;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
+                        val |= divider;
+                        if (c->flags & DIV_U71_UART) {
+                                if (divider)
+                                        val |= PERIPH_CLK_UART_DIV_ENB;
+                                else
+                                        val &= ~PERIPH_CLK_UART_DIV_ENB;
+                        }
+                        clk_writel_delay(val, c->reg);
+                        c->div = divider + 2;
+                        c->mul = 2;
+                        return 0;
+                }
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
+                        val |= divider;
+                        clk_writel_delay(val, c->reg);
+                        c->div = divider + 1;
+                        c->mul = 1;
+                        return 0;
+                }
+        } else if (parent_rate <= rate) {
+                c->div = 1;
+                c->mul = 1;
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static long tegra30_periph_clk_round_rate(struct clk *c,
+        unsigned long rate)
+{
+        int divider;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider < 0)
+                        return divider;
+
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate, divider + 1);
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_periph_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+
+/* Periph extended clock configuration ops */
+static int
+tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        if (p == TEGRA_CLK_VI_INP_SEL) {
+                u32 val = clk_readl(c->reg);
+                val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
+                val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
+                        PERIPH_CLK_VI_SEL_EX_MASK;
+                clk_writel(val, c->reg);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_vi_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .clk_cfg_ex             = &tegra30_vi_clk_cfg_ex,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+static int
+tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
+                u32 val = clk_readl(c->reg);
+                if (setting)
+                        val |= PERIPH_CLK_NAND_DIV_EX_ENB;
+                else
+                        val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
+                clk_writel(val, c->reg);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_nand_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .clk_cfg_ex             = &tegra30_nand_clk_cfg_ex,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+
+static int
+tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        if (p == TEGRA_CLK_DTV_INVERT) {
+                u32 val = clk_readl(c->reg);
+                if (setting)
+                        val |= PERIPH_CLK_DTV_POLARITY_INV;
+                else
+                        val &= ~PERIPH_CLK_DTV_POLARITY_INV;
+                clk_writel(val, c->reg);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_dtv_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .clk_cfg_ex             = &tegra30_dtv_clk_cfg_ex,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
+{
+        const struct clk_mux_sel *sel;
+        struct clk *d = tegra_get_clock_by_name("pll_d");
+
+        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        /* The DSIB parent selection bit is in PLLD base
+                           register - can not do direct r-m-w, must be
+                           protected by PLLD lock */
+                        tegra_clk_cfg_ex(
+                                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_dsib_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_dsib_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+/* pciex clock support only reset function */
+static struct clk_ops tegra_pciex_clk_ops = {
+        .reset    = tegra30_periph_clk_reset,
+};
+
+/* Output clock ops */
+
+static DEFINE_SPINLOCK(clk_out_lock);
+
+static void tegra30_clk_out_init(struct clk *c)
+{
+        const struct clk_mux_sel *mux = 0;
+        const struct clk_mux_sel *sel;
+        u32 val = pmc_readl(c->reg);
+
+        c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
+        c->mul = 1;
+        c->div = 1;
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (((val & periph_clk_source_mask(c)) >>
+                     periph_clk_source_shift(c)) == sel->value)
+                        mux = sel;
+        }
+        BUG_ON(!mux);
+        c->parent = mux->input;
+}
+
+static int tegra30_clk_out_enable(struct clk *c)
+{
+        u32 val;
+        unsigned long flags;
+
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        spin_lock_irqsave(&clk_out_lock, flags);
+        val = pmc_readl(c->reg);
+        val |= (0x1 << c->u.periph.clk_num);
+        pmc_writel(val, c->reg);
+        spin_unlock_irqrestore(&clk_out_lock, flags);
+
+        return 0;
+}
+
+static void tegra30_clk_out_disable(struct clk *c)
+{
+        u32 val;
+        unsigned long flags;
+
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        spin_lock_irqsave(&clk_out_lock, flags);
+        val = pmc_readl(c->reg);
+        val &= ~(0x1 << c->u.periph.clk_num);
+        pmc_writel(val, c->reg);
+        spin_unlock_irqrestore(&clk_out_lock, flags);
+}
+
+static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        unsigned long flags;
+        const struct clk_mux_sel *sel;
+
+        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        spin_lock_irqsave(&clk_out_lock, flags);
+                        val = pmc_readl(c->reg);
+                        val &= ~periph_clk_source_mask(c);
+                        val |= (sel->value << periph_clk_source_shift(c));
+                        pmc_writel(val, c->reg);
+                        spin_unlock_irqrestore(&clk_out_lock, flags);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_clk_out_ops = {
+        .init                   = &tegra30_clk_out_init,
+        .enable                 = &tegra30_clk_out_enable,
+        .disable                = &tegra30_clk_out_disable,
+        .set_parent             = &tegra30_clk_out_set_parent,
+};
+
+
+/* Clock doubler ops */
+static void tegra30_clk_double_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
+        c->div = 1;
+        c->state = ON;
+        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
+                c->state = OFF;
+};
+
+static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        if (rate == parent_rate) {
+                val = clk_readl(c->reg) | (0x1 << c->reg_shift);
+                clk_writel(val, c->reg);
+                c->mul = 1;
+                c->div = 1;
+                return 0;
+        } else if (rate == 2 * parent_rate) {
+                val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
+                clk_writel(val, c->reg);
+                c->mul = 2;
+                c->div = 1;
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_clk_double_ops = {
+        .init                   = &tegra30_clk_double_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_rate               = &tegra30_clk_double_set_rate,
+};
+
+/* Audio sync clock ops */
+static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
+{
+        c->rate = rate;
+        return 0;
+}
+
+static struct clk_ops tegra_sync_source_ops = {
+        .set_rate               = &tegra30_sync_source_set_rate,
+};
+
+static void tegra30_audio_sync_clk_init(struct clk *c)
+{
+        int source;
+        const struct clk_mux_sel *sel;
+        u32 val = clk_readl(c->reg);
+        c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
+        source = val & AUDIO_SYNC_SOURCE_MASK;
+        for (sel = c->inputs; sel->input != NULL; sel++)
+                if (sel->value == source)
+                        break;
+        BUG_ON(sel->input == NULL);
+        c->parent = sel->input;
+}
+
+static int tegra30_audio_sync_clk_enable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
+        return 0;
+}
+
+static void tegra30_audio_sync_clk_disable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
+}
+
+static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        const struct clk_mux_sel *sel;
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        val = clk_readl(c->reg);
+                        val &= ~AUDIO_SYNC_SOURCE_MASK;
+                        val |= sel->value;
+
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        clk_writel(val, c->reg);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_audio_sync_clk_ops = {
+        .init       = tegra30_audio_sync_clk_init,
+        .enable     = tegra30_audio_sync_clk_enable,
+        .disable    = tegra30_audio_sync_clk_disable,
+        .set_parent = tegra30_audio_sync_clk_set_parent,
+};
+
+/* cml0 (pcie), and cml1 (sata) clock ops */
+static void tegra30_cml_clk_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
+}
+
+static int tegra30_cml_clk_enable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        val |= (0x1 << c->u.periph.clk_num);
+        clk_writel(val, c->reg);
+        return 0;
+}
+
+static void tegra30_cml_clk_disable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        val &= ~(0x1 << c->u.periph.clk_num);
+        clk_writel(val, c->reg);
+}
+
+static struct clk_ops tegra_cml_clk_ops = {
+        .init                   = &tegra30_cml_clk_init,
+        .enable                 = &tegra30_cml_clk_enable,
+        .disable                = &tegra30_cml_clk_disable,
+};
+
+/* Clock definitions */
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .rate = 32768,
+        .ops  = NULL,
+        .max_rate = 32768,
+};
+
+static struct clk tegra_clk_m = {
+        .name      = "clk_m",
+        .flags     = ENABLE_ON_INIT,
+        .ops       = &tegra_clk_m_ops,
+        .reg       = 0x1fc,
+        .reg_shift = 28,
+        .max_rate  = 48000000,
+};
+
+static struct clk tegra_clk_m_div2 = {
+        .name      = "clk_m_div2",
+        .ops       = &tegra_clk_m_div_ops,
+        .parent    = &tegra_clk_m,
+        .mul       = 1,
+        .div       = 2,
+        .state     = ON,
+        .max_rate  = 24000000,
+};
+
+static struct clk tegra_clk_m_div4 = {
+        .name      = "clk_m_div4",
+        .ops       = &tegra_clk_m_div_ops,
+        .parent    = &tegra_clk_m,
+        .mul       = 1,
+        .div       = 4,
+        .state     = ON,
+        .max_rate  = 12000000,
+};
+
+static struct clk tegra_pll_ref = {
+        .name      = "pll_ref",
+        .flags     = ENABLE_ON_INIT,
+        .ops       = &tegra_pll_ref_ops,
+        .parent    = &tegra_clk_m,
+        .max_rate  = 26000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 1040000000, 520,  6, 1, 8},
+        { 13000000, 1040000000, 480,  6, 1, 8},
+        { 16800000, 1040000000, 495,  8, 1, 8},         /* actual: 1039.5 MHz */
+        { 19200000, 1040000000, 325,  6, 1, 6},
+        { 26000000, 1040000000, 520, 13, 1, 8},
+
+        { 12000000, 832000000, 416,  6, 1, 8},
+        { 13000000, 832000000, 832, 13, 1, 8},
+        { 16800000, 832000000, 396,  8, 1, 8},          /* actual: 831.6 MHz */
+        { 19200000, 832000000, 260,  6, 1, 8},
+        { 26000000, 832000000, 416, 13, 1, 8},
+
+        { 12000000, 624000000, 624, 12, 1, 8},
+        { 13000000, 624000000, 624, 13, 1, 8},
+        { 16800000, 600000000, 520, 14, 1, 8},
+        { 19200000, 624000000, 520, 16, 1, 8},
+        { 26000000, 624000000, 624, 26, 1, 8},
+
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+
+        { 12000000, 520000000, 520, 12, 1, 8},
+        { 13000000, 520000000, 520, 13, 1, 8},
+        { 16800000, 520000000, 495, 16, 1, 8},          /* actual: 519.75 MHz */
+        { 19200000, 520000000, 325, 12, 1, 6},
+        { 26000000, 520000000, 520, 26, 1, 8},
+
+        { 12000000, 416000000, 416, 12, 1, 8},
+        { 13000000, 416000000, 416, 13, 1, 8},
+        { 16800000, 416000000, 396, 16, 1, 8},          /* actual: 415.8 MHz */
+        { 19200000, 416000000, 260, 12, 1, 6},
+        { 26000000, 416000000, 416, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_c = {
+        .name      = "pll_c",
+        .flags     = PLL_HAS_CPCON,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0x80,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1400000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1400000000,
+                .freq_table = tegra_pll_c_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_c_out1 = {
+        .name      = "pll_c_out1",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_U71,
+        .parent    = &tegra_pll_c,
+        .reg       = 0x84,
+        .reg_shift = 0,
+        .max_rate  = 700000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 16800000, 666000000, 555, 14, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_m = {
+        .name      = "pll_m",
+        .flags     = PLL_HAS_CPCON | PLLM,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0x90,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 800000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1200000000,
+                .freq_table = tegra_pll_m_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_m_out1 = {
+        .name      = "pll_m_out1",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_U71,
+        .parent    = &tegra_pll_m,
+        .reg       = 0x94,
+        .reg_shift = 0,
+        .max_rate  = 600000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 16800000, 216000000, 360, 14, 2, 8},
+        { 19200000, 216000000, 360, 16, 2, 8},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_p = {
+        .name      = "pll_p",
+        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xa0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 432000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1400000000,
+                .freq_table = tegra_pll_p_freq_table,
+                .lock_delay = 300,
+                .fixed_rate = 408000000,
+        },
+};
+
+static struct clk tegra_pll_p_out1 = {
+        .name      = "pll_p_out1",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa4,
+        .reg_shift = 0,
+        .max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out2 = {
+        .name      = "pll_p_out2",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa4,
+        .reg_shift = 16,
+        .max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out3 = {
+        .name      = "pll_p_out3",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa8,
+        .reg_shift = 0,
+        .max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out4 = {
+        .name      = "pll_p_out4",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa8,
+        .reg_shift = 16,
+        .max_rate  = 432000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 9600000, 564480000, 294, 5, 1, 4},
+        { 9600000, 552960000, 288, 5, 1, 4},
+        { 9600000, 24000000,  5,   2, 1, 1},
+
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_a = {
+        .name      = "pll_a",
+        .flags     = PLL_HAS_CPCON,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xb0,
+        .parent    = &tegra_pll_p_out1,
+        .max_rate  = 700000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1400000000,
+                .freq_table = tegra_pll_a_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_a_out0 = {
+        .name      = "pll_a_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_U71,
+        .parent    = &tegra_pll_a,
+        .reg       = 0xb4,
+        .reg_shift = 0,
+        .max_rate  = 100000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 16800000, 216000000, 180, 14, 1, 4},
+        { 19200000, 216000000, 180, 16, 1, 4},
+        { 26000000, 216000000, 216, 26, 1, 4},
+
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 16800000, 594000000, 495, 14, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_d = {
+        .name      = "pll_d",
+        .flags     = PLL_HAS_CPCON | PLLD,
+        .ops       = &tegra_plld_ops,
+        .reg       = 0xd0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1000000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 40000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 40000000,
+                .vco_max   = 1000000000,
+                .freq_table = tegra_pll_d_freq_table,
+                .lock_delay = 1000,
+        },
+};
+
+static struct clk tegra_pll_d_out0 = {
+        .name      = "pll_d_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_2 | PLLD,
+        .parent    = &tegra_pll_d,
+        .max_rate  = 500000000,
+};
+
+static struct clk tegra_pll_d2 = {
+        .name      = "pll_d2",
+        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
+        .ops       = &tegra_plld_ops,
+        .reg       = 0x4b8,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1000000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 40000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 40000000,
+                .vco_max   = 1000000000,
+                .freq_table = tegra_pll_d_freq_table,
+                .lock_delay = 1000,
+        },
+};
+
+static struct clk tegra_pll_d2_out0 = {
+        .name      = "pll_d2_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_2 | PLLD,
+        .parent    = &tegra_pll_d2,
+        .max_rate  = 500000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 12},
+        { 13000000, 480000000, 960, 13, 2, 12},
+        { 16800000, 480000000, 400, 7,  2, 5},
+        { 19200000, 480000000, 200, 4,  2, 3},
+        { 26000000, 480000000, 960, 26, 2, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_u = {
+        .name      = "pll_u",
+        .flags     = PLL_HAS_CPCON | PLLU,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xc0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 480000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 40000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 480000000,
+                .vco_max   = 960000000,
+                .freq_table = tegra_pll_u_freq_table,
+                .lock_delay = 1000,
+        },
+};
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1.7 GHz */
+        { 12000000, 1700000000, 850,  6,  1, 8},
+        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
+        { 26000000, 1700000000, 850,  13, 1, 8},
+
+        /* 1.6 GHz */
+        { 12000000, 1600000000, 800,  6,  1, 8},
+        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
+        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
+        { 19200000, 1600000000, 500,  6,  1, 8},
+        { 26000000, 1600000000, 800,  13, 1, 8},
+
+        /* 1.5 GHz */
+        { 12000000, 1500000000, 750,  6,  1, 8},
+        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
+        { 16800000, 1500000000, 625,  7,  1, 8},
+        { 19200000, 1500000000, 625,  8,  1, 8},
+        { 26000000, 1500000000, 750,  13, 1, 8},
+
+        /* 1.4 GHz */
+        { 12000000, 1400000000, 700,  6,  1, 8},
+        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
+        { 16800000, 1400000000, 1000, 12, 1, 8},
+        { 19200000, 1400000000, 875,  12, 1, 8},
+        { 26000000, 1400000000, 700,  13, 1, 8},
+
+        /* 1.3 GHz */
+        { 12000000, 1300000000, 975,  9,  1, 8},
+        { 13000000, 1300000000, 1000, 10, 1, 8},
+        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 26000000, 1300000000, 650,  13, 1, 8},
+
+        /* 1.2 GHz */
+        { 12000000, 1200000000, 1000, 10, 1, 8},
+        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
+        { 16800000, 1200000000, 1000, 14, 1, 8},
+        { 19200000, 1200000000, 1000, 16, 1, 8},
+        { 26000000, 1200000000, 600,  13, 1, 8},
+
+        /* 1.1 GHz */
+        { 12000000, 1100000000, 825,  9,  1, 8},
+        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
+        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
+        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
+        { 26000000, 1100000000, 550,  13, 1, 8},
+
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 8},
+        { 13000000, 1000000000, 1000, 13, 1, 8},
+        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 8},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_x = {
+        .name      = "pll_x",
+        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xe0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1700000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1700000000,
+                .freq_table = tegra_pll_x_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_x_out0 = {
+        .name      = "pll_x_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_2 | PLLX,
+        .parent    = &tegra_pll_x,
+        .max_rate  = 850000000,
+};
+
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        /* PLLE special case: use cpcon field to store cml divider value */
+        { 12000000,  100000000, 150, 1,  18, 11},
+        { 216000000, 100000000, 200, 18, 24, 13},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_e = {
+        .name      = "pll_e",
+        .flags     = PLL_ALT_MISC_REG,
+        .ops       = &tegra_plle_ops,
+        .reg       = 0xe8,
+        .max_rate  = 100000000,
+        .u.pll = {
+                .input_min = 12000000,
+                .input_max = 216000000,
+                .cf_min    = 12000000,
+                .cf_max    = 12000000,
+                .vco_min   = 1200000000,
+                .vco_max   = 2400000000U,
+                .freq_table = tegra_pll_e_freq_table,
+                .lock_delay = 300,
+                .fixed_rate = 100000000,
+        },
+};
+
+static struct clk tegra_cml0_clk = {
+        .name      = "cml0",
+        .parent    = &tegra_pll_e,
+        .ops       = &tegra_cml_clk_ops,
+        .reg       = PLLE_AUX,
+        .max_rate  = 100000000,
+        .u.periph  = {
+                .clk_num = 0,
+        },
+};
+
+static struct clk tegra_cml1_clk = {
+        .name      = "cml1",
+        .parent    = &tegra_pll_e,
+        .ops       = &tegra_cml_clk_ops,
+        .reg       = PLLE_AUX,
+        .max_rate  = 100000000,
+        .u.periph  = {
+                .clk_num   = 1,
+        },
+};
+
+static struct clk tegra_pciex_clk = {
+        .name      = "pciex",
+        .parent    = &tegra_pll_e,
+        .ops       = &tegra_pciex_clk_ops,
+        .max_rate  = 100000000,
+        .u.periph  = {
+                .clk_num   = 74,
+        },
+};
+
+/* Audio sync clocks */
+#define SYNC_SOURCE(_id)                                \
+        {                                               \
+                .name      = #_id "_sync",              \
+                .rate      = 24000000,                  \
+                .max_rate  = 24000000,                  \
+                .ops       = &tegra_sync_source_ops     \
+        }
+static struct clk tegra_sync_source_list[] = {
+        SYNC_SOURCE(spdif_in),
+        SYNC_SOURCE(i2s0),
+        SYNC_SOURCE(i2s1),
+        SYNC_SOURCE(i2s2),
+        SYNC_SOURCE(i2s3),
+        SYNC_SOURCE(i2s4),
+        SYNC_SOURCE(vimclk),
+};
+
+static struct clk_mux_sel mux_audio_sync_clk[] = {
+        { .input = &tegra_sync_source_list[0],  .value = 0},
+        { .input = &tegra_sync_source_list[1],  .value = 1},
+        { .input = &tegra_sync_source_list[2],  .value = 2},
+        { .input = &tegra_sync_source_list[3],  .value = 3},
+        { .input = &tegra_sync_source_list[4],  .value = 4},
+        { .input = &tegra_sync_source_list[5],  .value = 5},
+        { .input = &tegra_pll_a_out0,           .value = 6},
+        { .input = &tegra_sync_source_list[6],  .value = 7},
+        { 0, 0 }
+};
+
+#define AUDIO_SYNC_CLK(_id, _index)                     \
+        {                                               \
+                .name      = #_id,                      \
+                .inputs    = mux_audio_sync_clk,        \
+                .reg       = 0x4A0 + (_index) * 4,      \
+                .max_rate  = 24000000,                  \
+                .ops       = &tegra_audio_sync_clk_ops  \
+        }
+static struct clk tegra_clk_audio_list[] = {
+        AUDIO_SYNC_CLK(audio0, 0),
+        AUDIO_SYNC_CLK(audio1, 1),
+        AUDIO_SYNC_CLK(audio2, 2),
+        AUDIO_SYNC_CLK(audio3, 3),
+        AUDIO_SYNC_CLK(audio4, 4),
+        AUDIO_SYNC_CLK(audio, 5),       /* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_id, _index)                          \
+        {                                                       \
+                .name      = #_id "_2x",                        \
+                .flags     = PERIPH_NO_RESET,                   \
+                .max_rate  = 48000000,                          \
+                .ops       = &tegra_clk_double_ops,             \
+                .reg       = 0x49C,                             \
+                .reg_shift = 24 + (_index),                     \
+                .parent    = &tegra_clk_audio_list[(_index)],   \
+                .u.periph = {                                   \
+                        .clk_num = 113 + (_index),              \
+                },                                              \
+        }
+static struct clk tegra_clk_audio_2x_list[] = {
+        AUDIO_SYNC_2X_CLK(audio0, 0),
+        AUDIO_SYNC_2X_CLK(audio1, 1),
+        AUDIO_SYNC_2X_CLK(audio2, 2),
+        AUDIO_SYNC_2X_CLK(audio3, 3),
+        AUDIO_SYNC_2X_CLK(audio4, 4),
+        AUDIO_SYNC_2X_CLK(audio, 5),    /* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id, _index)                                      \
+static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {       \
+        {.input = &tegra_pll_a_out0, .value = 0},                       \
+        {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},      \
+        {.input = &tegra_pll_p, .value = 2},                            \
+        {.input = &tegra_clk_m, .value = 3},                            \
+        { 0, 0},                                                        \
+}
+MUX_I2S_SPDIF(audio0, 0);
+MUX_I2S_SPDIF(audio1, 1);
+MUX_I2S_SPDIF(audio2, 2);
+MUX_I2S_SPDIF(audio3, 3);
+MUX_I2S_SPDIF(audio4, 4);
+MUX_I2S_SPDIF(audio, 5);                /* SPDIF */
+
+/* External clock outputs (through PMC) */
+#define MUX_EXTERN_OUT(_id)                                             \
+static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {        \
+        {.input = &tegra_clk_m,         .value = 0},                    \
+        {.input = &tegra_clk_m_div2,    .value = 1},                    \
+        {.input = &tegra_clk_m_div4,    .value = 2},                    \
+        {.input = NULL,                 .value = 3}, /* placeholder */  \
+        { 0, 0},                                                        \
+}
+MUX_EXTERN_OUT(1);
+MUX_EXTERN_OUT(2);
+MUX_EXTERN_OUT(3);
+
+static struct clk_mux_sel *mux_extern_out_list[] = {
+        mux_clkm_clkm2_clkm4_extern1,
+        mux_clkm_clkm2_clkm4_extern2,
+        mux_clkm_clkm2_clkm4_extern3,
+};
+
+#define CLK_OUT_CLK(_id)                                        \
+        {                                                       \
+                .name      = "clk_out_" #_id,                   \
+                .lookup    = {                                  \
+                        .dev_id    = "clk_out_" #_id,           \
+                        .con_id    = "extern" #_id,             \
+                },                                              \
+                .ops       = &tegra_clk_out_ops,                \
+                .reg       = 0x1a8,                             \
+                .inputs    = mux_clkm_clkm2_clkm4_extern##_id,  \
+                .flags     = MUX_CLK_OUT,                       \
+                .max_rate  = 216000000,                         \
+                .u.periph = {                                   \
+                        .clk_num   = (_id - 1) * 8 + 2,         \
+                },                                              \
+        }
+static struct clk tegra_clk_out_list[] = {
+        CLK_OUT_CLK(1),
+        CLK_OUT_CLK(2),
+        CLK_OUT_CLK(3),
+};
+
+/* called after peripheral external clocks are initialized */
+static void init_clk_out_mux(void)
+{
+        int i;
+        struct clk *c;
+
+        /* output clock con_id is the name of peripheral
+           external clock connected to input 3 of the output mux */
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
+                c = tegra_get_clock_by_name(
+                        tegra_clk_out_list[i].lookup.con_id);
+                if (!c)
+                        pr_err("%s: could not find clk %s\n", __func__,
+                               tegra_clk_out_list[i].lookup.con_id);
+                mux_extern_out_list[i][3].input = c;
+        }
+}
+
+/* Peripheral muxes */
+static struct clk_mux_sel mux_sclk[] = {
+        { .input = &tegra_clk_m,        .value = 0},
+        { .input = &tegra_pll_c_out1,   .value = 1},
+        { .input = &tegra_pll_p_out4,   .value = 2},
+        { .input = &tegra_pll_p_out3,   .value = 3},
+        { .input = &tegra_pll_p_out2,   .value = 4},
+        /* { .input = &tegra_clk_d,     .value = 5}, - no use on tegra30 */
+        { .input = &tegra_clk_32k,      .value = 6},
+        { .input = &tegra_pll_m_out1,   .value = 7},
+        { 0, 0},
+};
+
+static struct clk tegra_clk_sclk = {
+        .name   = "sclk",
+        .inputs = mux_sclk,
+        .reg    = 0x28,
+        .ops    = &tegra_super_ops,
+        .max_rate = 334000000,
+        .min_rate = 40000000,
+};
+
+static struct clk tegra_clk_blink = {
+        .name           = "blink",
+        .parent         = &tegra_clk_32k,
+        .reg            = 0x40,
+        .ops            = &tegra_blink_clk_ops,
+        .max_rate       = 32768,
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
+        { .input = &tegra_pll_m, .value = 0},
+        { .input = &tegra_pll_c, .value = 1},
+        { .input = &tegra_pll_p, .value = 2},
+        { .input = &tegra_pll_a_out0, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
+        { .input = &tegra_pll_p, .value = 0},
+        { .input = &tegra_pll_c, .value = 1},
+        { .input = &tegra_pll_m, .value = 2},
+        { .input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_clkm[] = {
+        { .input = &tegra_pll_p, .value = 0},
+        { .input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
+        {.input = &tegra_pll_p, .value = 0},
+        {.input = &tegra_pll_d_out0, .value = 1},
+        {.input = &tegra_pll_c, .value = 2},
+        {.input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+        {.input = &tegra_pll_p, .value = 0},
+        {.input = &tegra_pll_m, .value = 1},
+        {.input = &tegra_pll_d_out0, .value = 2},
+        {.input = &tegra_pll_a_out0, .value = 3},
+        {.input = &tegra_pll_c, .value = 4},
+        {.input = &tegra_pll_d2_out0, .value = 5},
+        {.input = &tegra_clk_m, .value = 6},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
+        { .input = &tegra_pll_a_out0, .value = 0},
+        /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
+        { .input = &tegra_pll_p, .value = 2},
+        { .input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
+        {.input = &tegra_pll_p,     .value = 0},
+        {.input = &tegra_pll_c,     .value = 1},
+        {.input = &tegra_clk_32k,   .value = 2},
+        {.input = &tegra_clk_m,     .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
+        {.input = &tegra_pll_p,     .value = 0},
+        {.input = &tegra_pll_c,     .value = 1},
+        {.input = &tegra_clk_m,     .value = 2},
+        {.input = &tegra_clk_32k,   .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
+        {.input = &tegra_pll_p,     .value = 0},
+        {.input = &tegra_pll_c,     .value = 1},
+        {.input = &tegra_pll_m,     .value = 2},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_m[] = {
+        { .input = &tegra_clk_m, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_out3[] = {
+        { .input = &tegra_pll_p_out3, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plld_out0[] = {
+        { .input = &tegra_pll_d_out0, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
+        { .input = &tegra_pll_d_out0,  .value = 0},
+        { .input = &tegra_pll_d2_out0, .value = 1},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_32k[] = {
+        { .input = &tegra_clk_32k, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
+        { .input = &tegra_pll_a_out0, .value = 0},
+        { .input = &tegra_clk_32k,    .value = 1},
+        { .input = &tegra_pll_p,      .value = 2},
+        { .input = &tegra_clk_m,      .value = 3},
+        { .input = &tegra_pll_e,      .value = 4},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_cclk_g[] = {
+        { .input = &tegra_clk_m,        .value = 0},
+        { .input = &tegra_pll_c,        .value = 1},
+        { .input = &tegra_clk_32k,      .value = 2},
+        { .input = &tegra_pll_m,        .value = 3},
+        { .input = &tegra_pll_p,        .value = 4},
+        { .input = &tegra_pll_p_out4,   .value = 5},
+        { .input = &tegra_pll_p_out3,   .value = 6},
+        { .input = &tegra_pll_x,        .value = 8},
+        { 0, 0},
+};
+
+static struct clk tegra_clk_cclk_g = {
+        .name   = "cclk_g",
+        .flags  = DIV_U71 | DIV_U71_INT,
+        .inputs = mux_cclk_g,
+        .reg    = 0x368,
+        .ops    = &tegra_super_ops,
+        .max_rate = 1700000000,
+};
+
+static struct clk tegra30_clk_twd = {
+        .parent   = &tegra_clk_cclk_g,
+        .name     = "twd",
+        .ops      = &tegra30_twd_ops,
+        .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
+        .mul      = 1,
+        .div      = 2,
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
+        {                                               \
+                .name      = _name,                     \
+                .lookup    = {                          \
+                        .dev_id    = _dev,              \
+                        .con_id    = _con,              \
+                },                                      \
+                .ops       = &tegra_periph_clk_ops,     \
+                .reg       = _reg,                      \
+                .inputs    = _inputs,                   \
+                .flags     = _flags,                    \
+                .max_rate  = _max,                      \
+                .u.periph = {                           \
+                        .clk_num   = _clk_num,          \
+                },                                      \
+        }
+
+#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
+                        _flags, _ops)                                   \
+        {                                               \
+                .name      = _name,                     \
+                .lookup    = {                          \
+                        .dev_id    = _dev,              \
+                        .con_id    = _con,              \
+                },                                      \
+                .ops       = _ops,                      \
+                .reg       = _reg,                      \
+                .inputs    = _inputs,                   \
+                .flags     = _flags,                    \
+                .max_rate  = _max,                      \
+                .u.periph = {                           \
+                        .clk_num   = _clk_num,          \
+                },                                      \
+        }
+
+#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
+        {                                               \
+                .name      = _name,                     \
+                .lookup    = {                          \
+                        .dev_id    = _dev,              \
+                        .con_id    = _con,              \
+                },                                      \
+                .ops       = &tegra_clk_shared_bus_ops, \
+                .parent = _parent,                      \
+                .u.shared_bus_user = {                  \
+                        .client_id = _id,               \
+                        .client_div = _div,             \
+                        .mode = _mode,                  \
+                },                                      \
+        }
+struct clk tegra_list_clks[] = {
+        PERIPH_CLK("apbdma",    "tegra-dma",            NULL,   34,     0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
+        PERIPH_CLK("kbc",       "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
+        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("kfuse",     "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("fuse",      "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB),
+        PERIPH_CLK("fuse_burn", "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB),
+        PERIPH_CLK("apbif",     "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("i2s0",      "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s1",      "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s2",      "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s3",      "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s4",      "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("spdif_out", "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio_2x_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("spdif_in",  "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("pwm",       "pwm",                  NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("d_audio",   "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("dam0",      "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("dam1",      "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("dam2",      "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("hda",       "tegra30-hda",          "hda",   125,   0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",   111,     0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0),
+        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc5",      "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc6",      "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0),
+        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71,  &tegra_nand_clk_ops),
+        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
+        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
+        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c4",      "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c5",      "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("uarta",     "tegra_uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartb",     "tegra_uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartc",     "tegra_uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartd",     "tegra_uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarte",     "tegra_uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarta_dbg", "serial8250.0",         "uarta", 6,     0x178,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartb_dbg", "serial8250.0",         "uartb", 7,     0x17c,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartc_dbg", "serial8250.0",         "uartc", 55,    0x1a0,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartd_dbg", "serial8250.0",         "uartd", 65,    0x1c0,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarte_dbg", "serial8250.0",         "uarte", 66,    0x1c4,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
+        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+        PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
+        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK_EX("dtv",    "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0,              &tegra_dtv_clk_ops),
+        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
+        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
+        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("dsia",      "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0),
+        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0xd0,   500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsib_clk_ops),
+        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
+        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
+        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
+
+        PERIPH_CLK("tsensor",   "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71),
+        PERIPH_CLK("actmon",    "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71),
+        PERIPH_CLK("extern1",   "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("extern2",   "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("extern3",   "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("i2cslow",   "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("pcie",      "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)                \
+        {                                               \
+                .name   = _name,                        \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id         = _con,         \
+                },                                      \
+        }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
+        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
+        CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
+        CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
+        CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
+        CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
+        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
+        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
+        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
+        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
+        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
+        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
+        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
+        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
+        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
+        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
+        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
+        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
+        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
+        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
+        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
+        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+        CLK_DUPLICATE("twd", "smp_twd", NULL),
+        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
+};
+
+struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_clk_m,
+        &tegra_clk_m_div2,
+        &tegra_clk_m_div4,
+        &tegra_pll_ref,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_d2,
+        &tegra_pll_d2_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_x_out0,
+        &tegra_pll_e,
+        &tegra_clk_cclk_g,
+        &tegra_cml0_clk,
+        &tegra_cml1_clk,
+        &tegra_pciex_clk,
+        &tegra_clk_sclk,
+        &tegra_clk_blink,
+        &tegra30_clk_twd,
+};
+
+
+static void tegra30_init_one_clock(struct clk *c)
+{
+        clk_init(c);
+        INIT_LIST_HEAD(&c->shared_bus_list);
+        if (!c->lookup.dev_id && !c->lookup.con_id)
+                c->lookup.con_id = c->name;
+        c->lookup.clk = c;
+        clkdev_add(&c->lookup);
+}
+
+void __init tegra30_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra30_init_one_clock(tegra_ptr_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra30_init_one_clock(&tegra_list_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+
+        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+                tegra30_init_one_clock(&tegra_sync_source_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+                tegra30_init_one_clock(&tegra_clk_audio_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+                tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+
+        init_clk_out_mux();
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+                tegra30_init_one_clock(&tegra_clk_out_list[i]);
+
+}
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 1d1acda4f3e..1eed8d4a80e 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/time.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 
 #include <mach/iomap.h>
@@ -162,6 +162,21 @@ static struct irqaction tegra_timer_irq = {
         .irq            = INT_TMR3,
 };
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              TEGRA_ARM_PERIF_BASE + 0x600,
+                              IRQ_LOCALTIMER);
+
+static void __init tegra_twd_init(void)
+{
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+}
+#else
+#define tegra_twd_init()        do {} while(0)
+#endif
+
 static void __init tegra_init_timer(void)
 {
         struct clk *clk;
@@ -188,10 +203,6 @@ static void __init tegra_init_timer(void)
         else
                 clk_enable(clk);
 
-#ifdef CONFIG_HAVE_ARM_TWD
-        twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
-#endif
-
         switch (rate) {
         case 12000000:
                 timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -231,6 +242,7 @@ static void __init tegra_init_timer(void)
         tegra_clockevent.cpumask = cpu_all_mask;
         tegra_clockevent.irq = tegra_timer_irq.irq;
         clockevents_register_device(&tegra_clockevent);
+        tegra_twd_init();
 }
 
 struct sys_timer tegra_timer = {
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index ad321f9e2bb..c5b2ac04e2a 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -730,6 +731,7 @@ err0:
         kfree(phy);
         return ERR_PTR(err);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 {
@@ -738,6 +740,7 @@ int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
         else
                 return utmi_phy_power_on(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
 
 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 {
@@ -746,18 +749,21 @@ void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
         else
                 utmi_phy_power_off(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
 
 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_preresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 
 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_postresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 
 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
                                  enum tegra_usb_phy_port_speed port_speed)
@@ -765,24 +771,28 @@ void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
         if (!phy_is_ulpi(phy))
                 utmi_phy_restore_start(phy, port_speed);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 
 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_restore_end(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 
 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_clk_disable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
 
 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_clk_enable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
 
 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 {
@@ -794,3 +804,4 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
         clk_put(phy->pll_u);
         kfree(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 285538124e5..fd3a5c382f4 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -8,7 +8,6 @@ obj-n		:=
 obj-            :=
 
 obj-$(CONFIG_ARCH_U300)           += u300.o
-obj-$(CONFIG_MMC)                 += mmc.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a7b3f36e226..8b90c44d237 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -18,6 +18,7 @@
 #include <linux/termios.h>
 #include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/mmci.h>
 #include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
@@ -44,9 +45,9 @@
 #include <mach/gpio-u300.h>
 
 #include "clock.h"
-#include "mmc.h"
 #include "spi.h"
 #include "i2c.h"
+#include "u300-gpio.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -95,19 +96,9 @@ static struct amba_pl011_data uart0_plat_data = {
 #endif
 };
 
-static struct amba_device uart0_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "uart0", /* Slow device at 0x3000 offset */
-                .platform_data = &uart0_plat_data,
-        },
-        .res = {
-                .start = U300_UART0_BASE,
-                .end   = U300_UART0_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = { IRQ_U300_UART0, NO_IRQ },
-};
+/* Slow device at 0x3000 offset */
+static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
+        { IRQ_U300_UART0 }, &uart0_plat_data);
 
 /* The U335 have an additional UART1 on the APP CPU */
 #ifdef CONFIG_MACH_U300_BS335
@@ -119,72 +110,42 @@ static struct amba_pl011_data uart1_plat_data = {
 #endif
 };
 
-static struct amba_device uart1_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "uart1", /* Fast device at 0x7000 offset */
-                .platform_data = &uart1_plat_data,
-        },
-        .res = {
-                .start = U300_UART1_BASE,
-                .end   = U300_UART1_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = { IRQ_U300_UART1, NO_IRQ },
-};
+/* Fast device at 0x7000 offset */
+static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
+        { IRQ_U300_UART1 }, &uart1_plat_data);
 #endif
 
-static struct amba_device pl172_device = {
-        .dev = {
-                .init_name = "pl172", /* AHB device at 0x4000 offset */
-                .platform_data = NULL,
-        },
-        .res = {
-                .start = U300_EMIF_CFG_BASE,
-                .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
+/* AHB device at 0x4000 offset */
+static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 
+/* Fast device at 0x6000 offset */
+static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
+        { IRQ_U300_SPI }, NULL);
 
-/*
- * Everything within this next ifdef deals with external devices connected to
- * the APP SPI bus.
- */
-static struct amba_device pl022_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "pl022", /* Fast device at 0x6000 offset */
-        },
-        .res = {
-                .start = U300_SPI_BASE,
-                .end   = U300_SPI_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_U300_SPI, NO_IRQ },
-        /*
-         * This device has a DMA channel but the Linux driver does not use
-         * it currently.
-         */
-};
+/* Fast device at 0x1000 offset */
+#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 
-static struct amba_device mmcsd_device = {
-        .dev = {
-                .init_name = "mmci", /* Fast device at 0x1000 offset */
-                .platform_data = NULL, /* Added later */
-        },
-        .res = {
-                .start = U300_MMCSD_BASE,
-                .end   = U300_MMCSD_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
+static struct mmci_platform_data mmcsd_platform_data = {
         /*
-         * This device has a DMA channel but the Linux driver does not use
-         * it currently.
+         * Do not set ocr_mask or voltage translation function,
+         * we have a regulator we can control instead.
          */
+        .f_max = 24000000,
+        .gpio_wp = -1,
+        .gpio_cd = U300_GPIO_PIN_MMC_CD,
+        .cd_invert = true,
+        .capabilities = MMC_CAP_MMC_HIGHSPEED |
+        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
+        /* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
 
+static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
+        U300_MMCSD_IRQS, &mmcsd_platform_data);
+
 /*
  * The order of device declaration may be important, since some devices
  * have dependencies on other devices being initialized first.
@@ -1883,16 +1844,6 @@ void __init u300_init_devices(void)
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
 }
 
-static int core_module_init(void)
-{
-        /*
-         * This needs to be initialized later: it needs the input framework
-         * to be initialized first.
-         */
-        return mmc_init(&mmcsd_device);
-}
-module_init(core_module_init);
-
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
deleted file mode 100644
index 7181d6ac665..00000000000
--- a/arch/arm/mach-u300/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *
- * arch-arm/mach-u300/include/mach/entry-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Low-level IRQ helper macros for ST-Ericsson U300
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
deleted file mode 100644
index 574d46e3829..00000000000
--- a/arch/arm/mach-u300/include/mach/system.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/system.h
- *
- *
- * Copyright (C) 2007-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * System shutdown and reset functions.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
deleted file mode 100644
index 05abd6ad9fa..00000000000
--- a/arch/arm/mach-u300/mmc.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/mmc.c
- *
- *
- * Copyright (C) 2009 ST-Ericsson SA
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- * Author: Johan Lundin
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/mmc/host.h>
-#include <linux/dmaengine.h>
-#include <linux/amba/mmci.h>
-#include <linux/slab.h>
-#include <mach/coh901318.h>
-#include <mach/dma_channels.h>
-
-#include "u300-gpio.h"
-#include "mmc.h"
-
-static struct mmci_platform_data mmc0_plat_data = {
-        /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
-         */
-        /* Nominally 2.85V on our platform */
-        .f_max = 24000000,
-        .gpio_wp = -1,
-        .gpio_cd = U300_GPIO_PIN_MMC_CD,
-        .cd_invert = true,
-        .capabilities = MMC_CAP_MMC_HIGHSPEED |
-        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-        /* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
-};
-
-int __devinit mmc_init(struct amba_device *adev)
-{
-        struct device *mmcsd_device = &adev->dev;
-        int ret = 0;
-
-        mmcsd_device->platform_data = &mmc0_plat_data;
-
-        return ret;
-}
diff --git a/arch/arm/mach-u300/mmc.h b/arch/arm/mach-u300/mmc.h
deleted file mode 100644
index 92b85125abb..00000000000
--- a/arch/arm/mach-u300/mmc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/mmc.h
- *
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#ifndef MMC_H
-#define MMC_H
-
-#include <linux/amba/bus.h>
-
-int __devinit mmc_init(struct amba_device *adev);
-
-#endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c59e8b892d6..880d02ec89d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -8,47 +8,62 @@ config UX500_SOC_COMMON
         select PL310_ERRATA_753970
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369
-
-menu "Ux500 SoC"
+        select CACHE_L2X0
 
 config UX500_SOC_DB5500
-        bool "DB5500"
+        bool
         select MFD_DB5500_PRCMU
 
 config UX500_SOC_DB8500
-        bool "DB8500"
+        bool
         select MFD_DB8500_PRCMU
         select REGULATOR_DB8500_PRCMU
-
-endmenu
+        select CPU_FREQ_TABLE if CPU_FREQ
 
 menu "Ux500 target platform (boards)"
 
-config MACH_U8500
-        bool "U8500 Development platform"
-        depends on UX500_SOC_DB8500
-        select TPS6105X
+config MACH_MOP500
+        bool "U8500 Development platform, MOP500 versions"
+        select UX500_SOC_DB8500
+        select I2C
+        select I2C_NOMADIK
+        select SOC_BUS
         help
-          Include support for the mop500 development platform.
+          Include support for the MOP500 development platform.
 
 config MACH_HREFV60
-       bool "U85000 Development platform, HREFv60 version"
-       depends on UX500_SOC_DB8500
-       help
-         Include support for the HREFv60 new development platform.
+        bool "U8500 Development platform, HREFv60 version"
+        select MACH_MOP500
+        help
+          Include support for the HREFv60 new development platform.
+          Includes HREFv70, v71 etc.
 
 config MACH_SNOWBALL
         bool "U8500 Snowball platform"
-        depends on UX500_SOC_DB8500
-        select MACH_U8500
+        select MACH_MOP500
         help
           Include support for the snowball development platform.
 
 config MACH_U5500
         bool "U5500 Development platform"
-        depends on UX500_SOC_DB5500
+        select UX500_SOC_DB5500
         help
           Include support for the U5500 development platform.
+
+config UX500_AUTO_PLATFORM
+        def_bool y
+        depends on !MACH_U5500
+        select MACH_MOP500
+        help
+          At least one platform needs to be selected in order to build
+          a working kernel. If everything else is disabled, this
+          automatically enables MACH_MOP500.
+
+config MACH_UX500_DT
+        bool "Generic U8500 support using device tree"
+        depends on MACH_MOP500
+        select USE_OF
+
 endmenu
 
 config UX500_DEBUG_UART
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 6bd2f451c18..465b9ec9510 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -7,7 +7,7 @@ obj-y				:= clock.o cpu.o devices.o devices-common.o \
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
-obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
+obj-$(CONFIG_MACH_MOP500)       += board-mop500.o board-mop500-sdi.o \
                                 board-mop500-regulators.o \
                                 board-mop500-uib.o board-mop500-stuib.o \
                                 board-mop500-u8500uib.o \
@@ -15,7 +15,6 @@ obj-$(CONFIG_MACH_U8500)	+= board-mop500.o board-mop500-sdi.o \
 obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
 obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
 
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
index ff0a4b5b0a8..dd5cd00e255 100644
--- a/arch/arm/mach-ux500/Makefile.boot
+++ b/arch/arm/mach-ux500/Makefile.boot
@@ -2,3 +2,4 @@
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
 
+dtb-$(CONFIG_MACH_SNOWBALL) += snowball.dtb
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 74bfcff2bdf..f5413dca532 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -6,6 +6,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <asm/mach-types.h>
 #include <plat/pincfg.h>
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 2735d03996c..52426a42578 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -74,6 +74,26 @@ static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
         REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
 };
 
+static struct regulator_consumer_supply ab8500_vaud_consumers[] = {
+        /* AB8500 audio-codec main supply */
+        REGULATOR_SUPPLY("vaud", "ab8500-codec.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vamic1_consumers[] = {
+        /* AB8500 audio-codec Mic1 supply */
+        REGULATOR_SUPPLY("vamic1", "ab8500-codec.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vamic2_consumers[] = {
+        /* AB8500 audio-codec Mic2 supply */
+        REGULATOR_SUPPLY("vamic2", "ab8500-codec.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vdmic_consumers[] = {
+        /* AB8500 audio-codec DMic supply */
+        REGULATOR_SUPPLY("vdmic", "ab8500-codec.0"),
+};
+
 static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
         /* SoC core supply, no device */
         REGULATOR_SUPPLY("v-intcore", NULL),
@@ -323,6 +343,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-AUD",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers),
+                .consumer_supplies = ab8500_vaud_consumers,
         },
         /* supply for v-anamic1 VAMic1-LDO */
         [AB8500_LDO_ANAMIC1] = {
@@ -330,6 +352,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-AMIC1",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers),
+                .consumer_supplies = ab8500_vamic1_consumers,
         },
         /* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
         [AB8500_LDO_ANAMIC2] = {
@@ -337,6 +361,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-AMIC2",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers),
+                .consumer_supplies = ab8500_vamic2_consumers,
         },
         /* supply for v-dmic, VDMIC LDO */
         [AB8500_LDO_DMIC] = {
@@ -344,6 +370,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-DMIC",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vdmic_consumers),
+                .consumer_supplies = ab8500_vdmic_consumers,
         },
         /* supply for v-intcore12, VINTCORE12 LDO */
         [AB8500_LDO_INTCORE] = {
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 5dde4d4ebe8..920251cf834 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -31,21 +31,13 @@
  * SDI 0 (MicroSD slot)
  */
 
-/* MMCIPOWER bits */
-#define MCI_DATA2DIREN          (1 << 2)
-#define MCI_CMDDIREN            (1 << 3)
-#define MCI_DATA0DIREN          (1 << 4)
-#define MCI_DATA31DIREN         (1 << 5)
-#define MCI_FBCLKEN             (1 << 7)
-
 /* GPIO pins used by the sdi0 level shifter */
 static int sdi0_en = -1;
 static int sdi0_vsel = -1;
 
-static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
-                                   unsigned char power_mode)
+static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
 {
-        switch (power_mode) {
+        switch (ios->power_mode) {
         case MMC_POWER_UP:
         case MMC_POWER_ON:
                 /*
@@ -65,8 +57,7 @@ static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
                 break;
         }
 
-        return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
-               MCI_DATA2DIREN | MCI_DATA31DIREN;
+        return 0;
 }
 
 #ifdef CONFIG_STE_DMA40
@@ -90,13 +81,17 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 #endif
 
 static struct mmci_platform_data mop500_sdi0_data = {
-        .vdd_handler    = mop500_sdi0_vdd_handler,
+        .ios_handler    = mop500_sdi0_ios_handler,
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_SD_HIGHSPEED |
                                 MMC_CAP_MMC_HIGHSPEED,
         .gpio_wp        = -1,
+        .sigdir         = MCI_ST_FBCLKEN |
+                                MCI_ST_CMDDIREN |
+                                MCI_ST_DATA0DIREN |
+                                MCI_ST_DATA2DIREN,
 #ifdef CONFIG_STE_DMA40
         .dma_filter     = stedma40_filter,
         .dma_rx_param   = &mop500_sdi0_dma_cfg_rx,
@@ -104,7 +99,7 @@ static struct mmci_platform_data mop500_sdi0_data = {
 #endif
 };
 
-static void sdi0_configure(void)
+static void sdi0_configure(struct device *parent)
 {
         int ret;
 
@@ -123,15 +118,15 @@ static void sdi0_configure(void)
         gpio_direction_output(sdi0_en, 1);
 
         /* Add the device, force v2 to subrevision 1 */
-        db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
+        db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
 }
 
-void mop500_sdi_tc35892_init(void)
+void mop500_sdi_tc35892_init(struct device *parent)
 {
         mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
         sdi0_en = GPIO_SDMMC_EN;
         sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
-        sdi0_configure();
+        sdi0_configure(parent);
 }
 
 /*
@@ -246,12 +241,13 @@ static struct mmci_platform_data mop500_sdi4_data = {
 #endif
 };
 
-void __init mop500_sdi_init(void)
+void __init mop500_sdi_init(struct device *parent)
 {
         /* PoP:ed eMMC */
-        db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
+        db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
         /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
+        db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
+
         /*
          * On boards with the TC35892 GPIO expander, sdi0 will finally
          * be added when the TC35892 initializes and calls
@@ -259,31 +255,31 @@ void __init mop500_sdi_init(void)
          */
 }
 
-void __init snowball_sdi_init(void)
+void __init snowball_sdi_init(struct device *parent)
 {
         /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
         mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
         /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
+        db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
         /* External Micro SD slot */
         mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
         mop500_sdi0_data.cd_invert = true;
         sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
         sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
-        sdi0_configure();
+        sdi0_configure(parent);
 }
 
-void __init hrefv60_sdi_init(void)
+void __init hrefv60_sdi_init(struct device *parent)
 {
         /* PoP:ed eMMC */
-        db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
+        db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
         /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
+        db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
         /* External Micro SD slot */
         mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
         sdi0_en = HREFV60_SDMMC_EN_GPIO;
         sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
-        sdi0_configure();
+        sdi0_configure(parent);
         /* WLAN SDIO channel */
-        db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
+        db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
 }
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
index feb5744d98b..ead91c968ff 100644
--- a/arch/arm/mach-ux500/board-mop500-u8500uib.c
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -8,7 +8,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/i2c.h>
-#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/input/matrix_keypad.h>
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 5c00712907d..77d03c1fbd0 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -30,6 +30,9 @@
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
 
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -72,7 +75,7 @@ static struct platform_device snowball_led_dev = {
 };
 
 static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
-        .gpio_base              = MOP500_AB8500_GPIO(0),
+        .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
         .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
         /* config_reg is the initial configuration of ab8500 pins.
          * The pins can be configured as GPIO or alt functions based
@@ -226,7 +229,12 @@ static struct tps6105x_platform_data mop500_tps61052_data = {
 
 static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
 {
-        mop500_sdi_tc35892_init();
+        struct device *parent = NULL;
+#if 0
+        /* FIXME: Is the sdi actually part of tc3589x? */
+        parent = tc3589x->dev;
+#endif
+        mop500_sdi_tc35892_init(parent);
 }
 
 static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
@@ -353,12 +361,12 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
 U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
 U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
 
-static void __init mop500_i2c_init(void)
+static void __init mop500_i2c_init(struct device *parent)
 {
-        db8500_add_i2c0(&u8500_i2c0_data);
-        db8500_add_i2c1(&u8500_i2c1_data);
-        db8500_add_i2c2(&u8500_i2c2_data);
-        db8500_add_i2c3(&u8500_i2c3_data);
+        db8500_add_i2c0(parent, &u8500_i2c0_data);
+        db8500_add_i2c1(parent, &u8500_i2c1_data);
+        db8500_add_i2c2(parent, &u8500_i2c2_data);
+        db8500_add_i2c3(parent, &u8500_i2c3_data);
 }
 
 static struct gpio_keys_button mop500_gpio_keys[] = {
@@ -435,7 +443,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
 };
 #endif
 
-static struct pl022_ssp_controller ssp0_platform_data = {
+static struct pl022_ssp_controller ssp0_plat = {
         .bus_id = 0,
 #ifdef CONFIG_STE_DMA40
         .enable_dma = 1,
@@ -451,9 +459,9 @@ static struct pl022_ssp_controller ssp0_platform_data = {
         .num_chipselect = 5,
 };
 
-static void __init mop500_spi_init(void)
+static void __init mop500_spi_init(struct device *parent)
 {
-        db8500_add_ssp0(&ssp0_platform_data);
+        db8500_add_ssp0(parent, &ssp0_plat);
 }
 
 #ifdef CONFIG_STE_DMA40
@@ -587,11 +595,11 @@ static struct amba_pl011_data uart2_plat = {
 #endif
 };
 
-static void __init mop500_uart_init(void)
+static void __init mop500_uart_init(struct device *parent)
 {
-        db8500_add_uart0(&uart0_plat);
-        db8500_add_uart1(&uart1_plat);
-        db8500_add_uart2(&uart2_plat);
+        db8500_add_uart0(parent, &uart0_plat);
+        db8500_add_uart1(parent, &uart1_plat);
+        db8500_add_uart2(parent, &uart2_plat);
 }
 
 static struct platform_device *snowball_platform_devs[] __initdata = {
@@ -603,21 +611,27 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
 
 static void __init mop500_init_machine(void)
 {
+        struct device *parent = NULL;
         int i2c0_devs;
+        int i;
 
         mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
 
-        u8500_init_devices();
+        parent = u8500_init_devices();
 
         mop500_pins_init();
 
+        /* FIXME: parent of ab8500 should be prcmu */
+        for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
+                mop500_platform_devs[i]->dev.parent = parent;
+
         platform_add_devices(mop500_platform_devs,
                         ARRAY_SIZE(mop500_platform_devs));
 
-        mop500_i2c_init();
-        mop500_sdi_init();
-        mop500_spi_init();
-        mop500_uart_init();
+        mop500_i2c_init(parent);
+        mop500_sdi_init(parent);
+        mop500_spi_init(parent);
+        mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 
@@ -631,19 +645,24 @@ static void __init mop500_init_machine(void)
 
 static void __init snowball_init_machine(void)
 {
+        struct device *parent = NULL;
         int i2c0_devs;
+        int i;
 
-        u8500_init_devices();
+        parent = u8500_init_devices();
 
         snowball_pins_init();
 
+        for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
+                snowball_platform_devs[i]->dev.parent = parent;
+
         platform_add_devices(snowball_platform_devs,
                         ARRAY_SIZE(snowball_platform_devs));
 
-        mop500_i2c_init();
-        snowball_sdi_init();
-        mop500_spi_init();
-        mop500_uart_init();
+        mop500_i2c_init(parent);
+        snowball_sdi_init(parent);
+        mop500_spi_init(parent);
+        mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
         i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
@@ -656,7 +675,9 @@ static void __init snowball_init_machine(void)
 
 static void __init hrefv60_init_machine(void)
 {
+        struct device *parent = NULL;
         int i2c0_devs;
+        int i;
 
         /*
          * The HREFv60 board removed a GPIO expander and routed
@@ -665,17 +686,20 @@ static void __init hrefv60_init_machine(void)
          */
         mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
 
-        u8500_init_devices();
+        parent = u8500_init_devices();
 
         hrefv60_pins_init();
 
+        for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
+                mop500_platform_devs[i]->dev.parent = parent;
+
         platform_add_devices(mop500_platform_devs,
                         ARRAY_SIZE(mop500_platform_devs));
 
-        mop500_i2c_init();
-        hrefv60_sdi_init();
-        mop500_spi_init();
-        mop500_uart_init();
+        mop500_i2c_init(parent);
+        hrefv60_sdi_init(parent);
+        mop500_spi_init(parent);
+        mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 
@@ -718,3 +742,94 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
         .handle_irq     = gic_handle_irq,
         .init_machine   = snowball_init_machine,
 MACHINE_END
+
+#ifdef CONFIG_MACH_UX500_DT
+
+struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+        OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+        {},
+};
+
+static const struct of_device_id u8500_soc_node[] = {
+        /* only create devices below soc node */
+        { .compatible = "stericsson,db8500", },
+        { },
+};
+
+static void __init u8500_init_machine(void)
+{
+        struct device *parent = NULL;
+        int i2c0_devs;
+        int i;
+
+        parent = u8500_init_devices();
+        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+
+        for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
+                mop500_platform_devs[i]->dev.parent = parent;
+        for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
+                snowball_platform_devs[i]->dev.parent = parent;
+
+        /* automatically probe child nodes of db8500 device */
+        of_platform_populate(NULL, u8500_soc_node, u8500_auxdata_lookup, parent);
+
+        if (of_machine_is_compatible("st-ericsson,mop500")) {
+                mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+                mop500_pins_init();
+
+                platform_add_devices(mop500_platform_devs,
+                                ARRAY_SIZE(mop500_platform_devs));
+
+                mop500_sdi_init(parent);
+        } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
+                snowball_pins_init();
+                platform_add_devices(snowball_platform_devs,
+                                ARRAY_SIZE(snowball_platform_devs));
+
+                snowball_sdi_init(parent);
+        } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
+                /*
+                 * The HREFv60 board removed a GPIO expander and routed
+                 * all these GPIO pins to the internal GPIO controller
+                 * instead.
+                 */
+                mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+                hrefv60_pins_init();
+                platform_add_devices(mop500_platform_devs,
+                                ARRAY_SIZE(mop500_platform_devs));
+
+                hrefv60_sdi_init(parent);
+        }
+        mop500_i2c_init(parent);
+
+        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+        i2c_register_board_info(2, mop500_i2c2_devices,
+                                ARRAY_SIZE(mop500_i2c2_devices));
+
+        /* This board has full regulator constraints */
+        regulator_has_full_constraints();
+}
+
+static const char * u8500_dt_board_compat[] = {
+        "calaosystems,snowball-a9500",
+        "st-ericsson,hrefv60+",
+        "st-ericsson,u8500",
+        "st-ericsson,mop500",
+        NULL,
+};
+
+
+DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
+        .map_io         = u8500_map_io,
+        .init_irq       = ux500_init_irq,
+        /* we re-use nomadik timer here */
+        .timer          = &ux500_timer,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = u8500_init_machine,
+        .dt_compat      = u8500_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index f926d3db620..fdcfa8721bb 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -63,7 +63,7 @@
  * because the AB8500 GPIO pins are enumbered starting from 1, so the value in
  * parens matches the GPIO pin number in the data sheet.
  */
-#define MOP500_AB8500_GPIO(x)           (MOP500_EGPIO_END + (x) - 1)
+#define MOP500_AB8500_PIN_GPIO(x)       (MOP500_EGPIO_END + (x) - 1)
 /*Snowball AB8500 GPIO */
 #define SNOWBALL_VSMPS2_1V8_GPIO        MOP500_AB8500_PIN_GPIO(1)       /* SYSCLKREQ2/GPIO1 */
 #define SNOWBALL_PM_GPIO1_GPIO          MOP500_AB8500_PIN_GPIO(2)       /* SYSCLKREQ3/GPIO2 */
@@ -75,10 +75,10 @@
 
 struct i2c_board_info;
 
-extern void mop500_sdi_init(void);
-extern void snowball_sdi_init(void);
-extern void hrefv60_sdi_init(void);
-extern void mop500_sdi_tc35892_init(void);
+extern void mop500_sdi_init(struct device *parent);
+extern void snowball_sdi_init(struct device *parent);
+extern void hrefv60_sdi_init(struct device *parent);
+extern void mop500_sdi_tc35892_init(struct device *parent);
 void __init mop500_u8500uib_init(void);
 void __init mop500_stuib_init(void);
 void __init mop500_pins_init(void);
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
index 63c3f8058ff..836112eedde 100644
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -66,9 +66,9 @@ static struct mmci_platform_data u5500_sdi0_data = {
 #endif
 };
 
-void __init u5500_sdi_init(void)
+void __init u5500_sdi_init(struct device *parent)
 {
         nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
 
-        db5500_add_sdi0(&u5500_sdi0_data);
+        db5500_add_sdi0(parent, &u5500_sdi0_data);
 }
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 9de9e9c4dbb..0ff4be72a80 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -97,9 +97,9 @@ static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
         },
 };
 
-static void __init u5500_i2c_init(void)
+static void __init u5500_i2c_init(struct device *parent)
 {
-        db5500_add_i2c2(&u5500_i2c2_data);
+        db5500_add_i2c2(parent, &u5500_i2c2_data);
         i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
 }
 
@@ -126,20 +126,27 @@ static struct platform_device *u5500_platform_devices[] __initdata = {
         &ab5500_device,
 };
 
-static void __init u5500_uart_init(void)
+static void __init u5500_uart_init(struct device *parent)
 {
-        db5500_add_uart0(NULL);
-        db5500_add_uart1(NULL);
-        db5500_add_uart2(NULL);
+        db5500_add_uart0(parent, NULL);
+        db5500_add_uart1(parent, NULL);
+        db5500_add_uart2(parent, NULL);
 }
 
 static void __init u5500_init_machine(void)
 {
-        u5500_init_devices();
+        struct device *parent = NULL;
+        int i;
+
+        parent = u5500_init_devices();
         nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
-        u5500_i2c_init();
-        u5500_sdi_init();
-        u5500_uart_init();
+
+        u5500_i2c_init(parent);
+        u5500_sdi_init(parent);
+        u5500_uart_init(parent);
+
+        for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++)
+                u5500_platform_devices[i]->dev.parent = parent;
 
         platform_add_devices(u5500_platform_devices,
                 ARRAY_SIZE(u5500_platform_devices));
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index da5569d83d5..77a75ed0df6 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -5,6 +5,8 @@
  */
 
 #include <linux/io.h>
+#include <linux/of.h>
+
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <mach/hardware.h>
@@ -45,7 +47,10 @@ static int __init ux500_l2x0_init(void)
         ux500_l2x0_unlock();
 
         /* 64KB way size, 8 way associativity, force WA */
-        l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
+        if (of_have_populated_dt())
+                l2x0_of_init(0x3e060000, 0xc0000fff);
+        else
+                l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 
         /*
          * We can't disable l2 as we are in non secure mode, currently
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 73790753700..ec35f0aa566 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -223,6 +223,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL(clk_set_rate);
 
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        /*TODO*/
+        return -ENOSYS;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
 static void clk_prcmu_enable(struct clk *clk)
 {
         void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index 07449070522..d776ada08db 100644
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -21,6 +21,7 @@ struct clkops {
         void (*enable) (struct clk *);
         void (*disable) (struct clk *);
         unsigned long (*get_rate) (struct clk *);
+        int (*set_parent)(struct clk *, struct clk *);
 };
 
 /**
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 18aa5c05c69..bca47f32082 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -147,13 +147,13 @@ static resource_size_t __initdata db5500_gpio_base[] = {
         U5500_GPIOBANK7_BASE,
 };
 
-static void __init db5500_add_gpios(void)
+static void __init db5500_add_gpios(struct device *parent)
 {
         struct nmk_gpio_platform_data pdata = {
                 /* No custom data yet */
         };
 
-        dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base),
+        dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base),
                          IRQ_DB5500_GPIO0, &pdata);
 }
 
@@ -212,14 +212,36 @@ static int usb_db5500_tx_dma_cfg[] = {
         DB5500_DMA_DEV38_USB_OTG_OEP_8
 };
 
-void __init u5500_init_devices(void)
+static const char *db5500_read_soc_id(void)
 {
-        db5500_add_gpios();
+        return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n");
+}
+
+static struct device * __init db5500_soc_device_init(void)
+{
+        const char *soc_id = db5500_read_soc_id();
+
+        return ux500_soc_device_init(soc_id);
+}
+
+struct device * __init u5500_init_devices(void)
+{
+        struct device *parent;
+        int i;
+
+        parent = db5500_soc_device_init();
+
+        db5500_add_gpios(parent);
         db5500_pmu_init();
-        db5500_dma_init();
-        db5500_add_rtc();
-        db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
+        db5500_dma_init(parent);
+        db5500_add_rtc(parent);
+        db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
+
+        for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++)
+                db5500_platform_devs[i]->dev.parent = parent;
 
         platform_add_devices(db5500_platform_devs,
                              ARRAY_SIZE(db5500_platform_devs));
+
+        return parent;
 }
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7176ee7491a..9bd8163896c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -24,6 +24,7 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/usb.h>
+#include <mach/db8500-regs.h>
 
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
@@ -132,13 +133,13 @@ static resource_size_t __initdata db8500_gpio_base[] = {
         U8500_GPIOBANK8_BASE,
 };
 
-static void __init db8500_add_gpios(void)
+static void __init db8500_add_gpios(struct device *parent)
 {
         struct nmk_gpio_platform_data pdata = {
                 .supports_sleepmode = true,
         };
 
-        dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
+        dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
                          IRQ_DB8500_GPIO0, &pdata);
 }
 
@@ -164,17 +165,44 @@ static int usb_db8500_tx_dma_cfg[] = {
         DB8500_DMA_DEV39_USB_OTG_OEP_8
 };
 
+static const char *db8500_read_soc_id(void)
+{
+        void __iomem *uid = __io_address(U8500_BB_UID_BASE);
+
+        return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
+                         readl((u32 *)uid+1),
+                         readl((u32 *)uid+1), readl((u32 *)uid+2),
+                         readl((u32 *)uid+3), readl((u32 *)uid+4));
+}
+
+static struct device * __init db8500_soc_device_init(void)
+{
+        const char *soc_id = db8500_read_soc_id();
+
+        return ux500_soc_device_init(soc_id);
+}
+
 /*
  * This function is called from the board init
  */
-void __init u8500_init_devices(void)
+struct device * __init u8500_init_devices(void)
 {
-        db8500_add_rtc();
-        db8500_add_gpios();
-        db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
+        struct device *parent;
+        int i;
+
+        parent = db8500_soc_device_init();
+
+        db8500_add_rtc(parent);
+        db8500_add_gpios(parent);
+        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
+
+        platform_device_register_data(parent,
+                "cpufreq-u8500", -1, NULL, 0);
+
+        for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
+                platform_devs[i]->dev.parent = parent;
 
-        platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
-        return ;
+        return parent;
 }
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index f4185749437..d11f3892a27 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -2,6 +2,7 @@
  * Copyright (C) ST-Ericsson SA 2010
  *
  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson
  * License terms: GNU General Public License (GPL) version 2
  */
 
@@ -11,10 +12,15 @@
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/mfd/db5500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
+#include <linux/sys_soc.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
-#include <asm/localtimer.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -24,6 +30,11 @@
 
 void __iomem *_PRCMU_BASE;
 
+static const struct of_device_id ux500_dt_irq_match[] = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {},
+};
+
 void __init ux500_init_irq(void)
 {
         void __iomem *dist_base;
@@ -38,7 +49,12 @@ void __init ux500_init_irq(void)
         } else
                 ux500_unknown_soc();
 
-        gic_init(0, 29, dist_base, cpu_base);
+#ifdef CONFIG_OF
+        if (of_have_populated_dt())
+                of_irq_init(ux500_dt_irq_match);
+        else
+#endif
+                gic_init(0, 29, dist_base, cpu_base);
 
         /*
          * Init clocks here so that they are available for system timer
@@ -50,3 +66,73 @@ void __init ux500_init_irq(void)
                 db8500_prcmu_early_init();
         clk_init();
 }
+
+static const char * __init ux500_get_machine(void)
+{
+        return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber());
+}
+
+static const char * __init ux500_get_family(void)
+{
+        return kasprintf(GFP_KERNEL, "ux500");
+}
+
+static const char * __init ux500_get_revision(void)
+{
+        unsigned int rev = dbx500_revision();
+
+        if (rev == 0x01)
+                return kasprintf(GFP_KERNEL, "%s", "ED");
+        else if (rev >= 0xA0)
+                return kasprintf(GFP_KERNEL, "%d.%d",
+                                 (rev >> 4) - 0xA + 1, rev & 0xf);
+
+        return kasprintf(GFP_KERNEL, "%s", "Unknown");
+}
+
+static ssize_t ux500_get_process(struct device *dev,
+                                        struct device_attribute *attr,
+                                        char *buf)
+{
+        if (dbx500_id.process == 0x00)
+                return sprintf(buf, "Standard\n");
+
+        return sprintf(buf, "%02xnm\n", dbx500_id.process);
+}
+
+static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr,
+                                     const char *soc_id)
+{
+        soc_dev_attr->soc_id   = soc_id;
+        soc_dev_attr->machine  = ux500_get_machine();
+        soc_dev_attr->family   = ux500_get_family();
+        soc_dev_attr->revision = ux500_get_revision();
+}
+
+struct device_attribute ux500_soc_attr =
+        __ATTR(process,  S_IRUGO, ux500_get_process,  NULL);
+
+struct device * __init ux500_soc_device_init(const char *soc_id)
+{
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return ERR_PTR(-ENOMEM);
+
+        soc_info_populate(soc_dev_attr, soc_id);
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR_OR_NULL(soc_dev)) {
+                kfree(soc_dev_attr);
+                return NULL;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+        if (!IS_ERR_OR_NULL(parent))
+                device_create_file(parent, &ux500_soc_attr);
+
+        return parent;
+}
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index c563e5418d8..c5312a4b49f 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -20,35 +20,31 @@
 #include "devices-common.h"
 
 struct amba_device *
-dbx500_add_amba_device(const char *name, resource_size_t base,
-                       int irq, void *pdata, unsigned int periphid)
+dbx500_add_amba_device(struct device *parent, const char *name,
+                       resource_size_t base, int irq, void *pdata,
+                       unsigned int periphid)
 {
         struct amba_device *dev;
         int ret;
 
-        dev = kzalloc(sizeof *dev, GFP_KERNEL);
+        dev = amba_device_alloc(name, base, SZ_4K);
         if (!dev)
                 return ERR_PTR(-ENOMEM);
 
-        dev->dev.init_name = name;
-
-        dev->res.start = base;
-        dev->res.end = base + SZ_4K - 1;
-        dev->res.flags = IORESOURCE_MEM;
-
         dev->dma_mask = DMA_BIT_MASK(32);
         dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
         dev->irq[0] = irq;
-        dev->irq[1] = NO_IRQ;
 
         dev->periphid = periphid;
 
         dev->dev.platform_data = pdata;
 
-        ret = amba_device_register(dev, &iomem_resource);
+        dev->dev.parent = parent;
+
+        ret = amba_device_add(dev, &iomem_resource);
         if (ret) {
-                kfree(dev);
+                amba_device_put(dev);
                 return ERR_PTR(ret);
         }
 
@@ -56,60 +52,7 @@ dbx500_add_amba_device(const char *name, resource_size_t base,
 }
 
 static struct platform_device *
-dbx500_add_platform_device(const char *name, int id, void *pdata,
-                           struct resource *res, int resnum)
-{
-        struct platform_device *dev;
-        int ret;
-
-        dev = platform_device_alloc(name, id);
-        if (!dev)
-                return ERR_PTR(-ENOMEM);
-
-        dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-        dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
-
-        ret = platform_device_add_resources(dev, res, resnum);
-        if (ret)
-                goto out_free;
-
-        dev->dev.platform_data = pdata;
-
-        ret = platform_device_add(dev);
-        if (ret)
-                goto out_free;
-
-        return dev;
-
-out_free:
-        platform_device_put(dev);
-        return ERR_PTR(ret);
-}
-
-struct platform_device *
-dbx500_add_platform_device_4k1irq(const char *name, int id,
-                                  resource_size_t base,
-                                  int irq, void *pdata)
-{
-        struct resource resources[] = {
-                [0] = {
-                        .start  = base,
-                        .end    = base + SZ_4K - 1,
-                        .flags  = IORESOURCE_MEM,
-                },
-                [1] = {
-                        .start  = irq,
-                        .end    = irq,
-                        .flags  = IORESOURCE_IRQ,
-                }
-        };
-
-        return dbx500_add_platform_device(name, id, pdata, resources,
-                                          ARRAY_SIZE(resources));
-}
-
-static struct platform_device *
-dbx500_add_gpio(int id, resource_size_t addr, int irq,
+dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq,
                 struct nmk_gpio_platform_data *pdata)
 {
         struct resource resources[] = {
@@ -125,13 +68,18 @@ dbx500_add_gpio(int id, resource_size_t addr, int irq,
                 }
         };
 
-        return platform_device_register_resndata(NULL, "gpio", id,
-                                resources, ARRAY_SIZE(resources),
-                                pdata, sizeof(*pdata));
+        return platform_device_register_resndata(
+                parent,
+                "gpio",
+                id,
+                resources,
+                ARRAY_SIZE(resources),
+                pdata,
+                sizeof(*pdata));
 }
 
-void dbx500_add_gpios(resource_size_t *base, int num, int irq,
-                      struct nmk_gpio_platform_data *pdata)
+void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
+                      int irq, struct nmk_gpio_platform_data *pdata)
 {
         int first = 0;
         int i;
@@ -141,6 +89,6 @@ void dbx500_add_gpios(resource_size_t *base, int num, int irq,
                 pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
                 pdata->num_gpio = 32;
 
-                dbx500_add_gpio(i, base[i], irq, pdata);
+                dbx500_add_gpio(parent, i, base[i], irq, pdata);
         }
 }
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 7825705033b..39c74ec82ad 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -8,80 +8,89 @@
 #ifndef __DEVICES_COMMON_H
 #define __DEVICES_COMMON_H
 
-extern struct amba_device *
-dbx500_add_amba_device(const char *name, resource_size_t base,
-                       int irq, void *pdata, unsigned int periphid);
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/sys_soc.h>
+#include <plat/i2c.h>
 
-extern struct platform_device *
-dbx500_add_platform_device_4k1irq(const char *name, int id,
-                                  resource_size_t base,
-                                  int irq, void *pdata);
+extern struct amba_device *
+dbx500_add_amba_device(struct device *parent, const char *name,
+                       resource_size_t base, int irq, void *pdata,
+                       unsigned int periphid);
 
 struct spi_master_cntlr;
 
 static inline struct amba_device *
-dbx500_add_msp_spi(const char *name, resource_size_t base, int irq,
+dbx500_add_msp_spi(struct device *parent, const char *name,
+                   resource_size_t base, int irq,
                    struct spi_master_cntlr *pdata)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+        return dbx500_add_amba_device(parent, name, base, irq,
+                                      pdata, 0);
 }
 
 static inline struct amba_device *
-dbx500_add_spi(const char *name, resource_size_t base, int irq,
-               struct spi_master_cntlr *pdata,
+dbx500_add_spi(struct device *parent, const char *name, resource_size_t base,
+               int irq, struct spi_master_cntlr *pdata,
                u32 periphid)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, periphid);
+        return dbx500_add_amba_device(parent, name, base, irq,
+                                      pdata, periphid);
 }
 
 struct mmci_platform_data;
 
 static inline struct amba_device *
-dbx500_add_sdi(const char *name, resource_size_t base, int irq,
-               struct mmci_platform_data *pdata,
-               u32 periphid)
+dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base,
+               int irq, struct mmci_platform_data *pdata, u32 periphid)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, periphid);
+        return dbx500_add_amba_device(parent, name, base, irq,
+                                      pdata, periphid);
 }
 
 struct amba_pl011_data;
 
 static inline struct amba_device *
-dbx500_add_uart(const char *name, resource_size_t base, int irq,
-                struct amba_pl011_data *pdata)
+dbx500_add_uart(struct device *parent, const char *name, resource_size_t base,
+                int irq, struct amba_pl011_data *pdata)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+        return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
 }
 
 struct nmk_i2c_controller;
 
 static inline struct platform_device *
-dbx500_add_i2c(int id, resource_size_t base, int irq,
-               struct nmk_i2c_controller *pdata)
-{
-        return dbx500_add_platform_device_4k1irq("nmk-i2c", id, base, irq,
-                                                 pdata);
-}
-
-struct msp_i2s_platform_data;
-
-static inline struct platform_device *
-dbx500_add_msp_i2s(int id, resource_size_t base, int irq,
-                   struct msp_i2s_platform_data *pdata)
+dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq,
+               struct nmk_i2c_controller *data)
 {
-        return dbx500_add_platform_device_4k1irq("MSP_I2S", id, base, irq,
-                                                 pdata);
+        struct resource res[] = {
+                DEFINE_RES_MEM(base, SZ_4K),
+                DEFINE_RES_IRQ(irq),
+        };
+
+        struct platform_device_info pdevinfo = {
+                .parent = parent,
+                .name = "nmk-i2c",
+                .id = id,
+                .res = res,
+                .num_res = ARRAY_SIZE(res),
+                .data = data,
+                .size_data = sizeof(*data),
+                .dma_mask = DMA_BIT_MASK(32),
+        };
+
+        return platform_device_register_full(&pdevinfo);
 }
 
 static inline struct amba_device *
-dbx500_add_rtc(resource_size_t base, int irq)
+dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
 {
-        return dbx500_add_amba_device("rtc-pl031", base, irq, NULL, 0);
+        return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0);
 }
 
 struct nmk_gpio_platform_data;
 
-void dbx500_add_gpios(resource_size_t *base, int num, int irq,
-                      struct nmk_gpio_platform_data *pdata);
+void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
+                      int irq, struct nmk_gpio_platform_data *pdata);
 
 #endif
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index 0c4bccd02b9..e70955502c3 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -10,70 +10,90 @@
 
 #include "devices-common.h"
 
-#define db5500_add_i2c1(pdata) \
-        dbx500_add_i2c(1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
-#define db5500_add_i2c2(pdata) \
-        dbx500_add_i2c(2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
-#define db5500_add_i2c3(pdata) \
-        dbx500_add_i2c(3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
+#define db5500_add_i2c1(parent, pdata) \
+        dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
+#define db5500_add_i2c2(parent, pdata) \
+        dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
+#define db5500_add_i2c3(parent, pdata) \
+        dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
 
-#define db5500_add_msp0_i2s(pdata) \
-        dbx500_add_msp_i2s(0, U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
-#define db5500_add_msp1_i2s(pdata) \
-        dbx500_add_msp_i2s(1, U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
-#define db5500_add_msp2_i2s(pdata) \
-        dbx500_add_msp_i2s(2, U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
+#define db5500_add_msp0_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
+                           IRQ_DB5500_MSP0, pdata)
+#define db5500_add_msp1_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
+                           IRQ_DB5500_MSP1, pdata)
+#define db5500_add_msp2_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
+                           IRQ_DB5500_MSP2, pdata)
 
-#define db5500_add_msp0_spi(pdata) \
-        dbx500_add_msp_spi("msp0", U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
-#define db5500_add_msp1_spi(pdata) \
-        dbx500_add_msp_spi("msp1", U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
-#define db5500_add_msp2_spi(pdata) \
-        dbx500_add_msp_spi("msp2", U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
+#define db5500_add_msp0_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
+                          IRQ_DB5500_MSP0, pdata)
+#define db5500_add_msp1_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
+                          IRQ_DB5500_MSP1, pdata)
+#define db5500_add_msp2_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
+                          IRQ_DB5500_MSP2, pdata)
 
-#define db5500_add_rtc() \
-        dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC);
+#define db5500_add_rtc(parent) \
+        dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC);
 
-#define db5500_add_usb(rx_cfg, tx_cfg) \
-        ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
+#define db5500_add_usb(parent, rx_cfg, tx_cfg) \
+        ux500_add_usb(parent, U5500_USBOTG_BASE, \
+                      IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
 
-#define db5500_add_sdi0(pdata) \
-        dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata, \
+#define db5500_add_sdi0(parent, pdata) \
+        dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \
+                       IRQ_DB5500_SDMMC0, pdata,        \
                        0x10480180)
-#define db5500_add_sdi1(pdata) \
-        dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata, \
+#define db5500_add_sdi1(parent, pdata) \
+        dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \
+                       IRQ_DB5500_SDMMC1, pdata,        \
                        0x10480180)
-#define db5500_add_sdi2(pdata) \
-        dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata \
+#define db5500_add_sdi2(parent, pdata) \
+        dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \
+                       IRQ_DB5500_SDMMC2, pdata         \
                        0x10480180)
-#define db5500_add_sdi3(pdata) \
-        dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata \
+#define db5500_add_sdi3(parent, pdata) \
+        dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \
+                       IRQ_DB5500_SDMMC3, pdata         \
                        0x10480180)
-#define db5500_add_sdi4(pdata) \
-        dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata \
+#define db5500_add_sdi4(parent, pdata) \
+        dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \
+                       IRQ_DB5500_SDMMC4, pdata         \
                        0x10480180)
 
 /* This one has a bad peripheral ID in the U5500 silicon */
-#define db5500_add_spi0(pdata) \
-        dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata, \
+#define db5500_add_spi0(parent, pdata) \
+        dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \
+                       IRQ_DB5500_SPI0, pdata,          \
                        0x10080023)
-#define db5500_add_spi1(pdata) \
-        dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata, \
+#define db5500_add_spi1(parent, pdata) \
+        dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \
+                       IRQ_DB5500_SPI1, pdata,          \
                        0x10080023)
-#define db5500_add_spi2(pdata) \
-        dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata \
+#define db5500_add_spi2(parent, pdata) \
+        dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \
+                       IRQ_DB5500_SPI2, pdata           \
                        0x10080023)
-#define db5500_add_spi3(pdata) \
-        dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata \
+#define db5500_add_spi3(parent, pdata) \
+        dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \
+                       IRQ_DB5500_SPI3, pdata           \
                        0x10080023)
 
-#define db5500_add_uart0(plat) \
-        dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat)
-#define db5500_add_uart1(plat) \
-        dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1, plat)
-#define db5500_add_uart2(plat) \
-        dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2, plat)
-#define db5500_add_uart3(plat) \
-        dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3, plat)
+#define db5500_add_uart0(parent, plat) \
+        dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \
+                        IRQ_DB5500_UART0, plat)
+#define db5500_add_uart1(parent, plat) \
+        dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \
+                        IRQ_DB5500_UART1, plat)
+#define db5500_add_uart2(parent, plat) \
+        dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \
+                        IRQ_DB5500_UART2, plat)
+#define db5500_add_uart3(parent, plat) \
+        dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \
+                        IRQ_DB5500_UART3, plat)
 
 #endif
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index a7c6cdc9b11..6e66d3777ed 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -101,6 +101,9 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
         [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
         [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
         [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
+        [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
 };
 
 /* Mapping between source event lines and physical device address */
@@ -133,6 +136,9 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
         [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
         [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
         [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
+        [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
 };
 
 /* Reserved event lines for memcpy only */
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index cbd4a9ae810..9fd93e9da52 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -14,88 +14,114 @@ struct ske_keypad_platform_data;
 struct pl022_ssp_controller;
 
 static inline struct platform_device *
-db8500_add_ske_keypad(struct ske_keypad_platform_data *pdata)
+db8500_add_ske_keypad(struct device *parent,
+                      struct ske_keypad_platform_data *pdata,
+                      size_t size)
 {
-        return dbx500_add_platform_device_4k1irq("nmk-ske-keypad", -1,
-                                                 U8500_SKE_BASE,
-                                                 IRQ_DB8500_KB, pdata);
+        struct resource resources[] = {
+                DEFINE_RES_MEM(U8500_SKE_BASE, SZ_4K),
+                DEFINE_RES_IRQ(IRQ_DB8500_KB),
+        };
+
+        return platform_device_register_resndata(parent, "nmk-ske-keypad", -1,
+                                                 resources, 2, pdata, size);
 }
 
 static inline struct amba_device *
-db8500_add_ssp(const char *name, resource_size_t base, int irq,
-               struct pl022_ssp_controller *pdata)
+db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
+               int irq, struct pl022_ssp_controller *pdata)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+        return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
 }
 
 
-#define db8500_add_i2c0(pdata) \
-        dbx500_add_i2c(0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
-#define db8500_add_i2c1(pdata) \
-        dbx500_add_i2c(1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata)
-#define db8500_add_i2c2(pdata) \
-        dbx500_add_i2c(2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata)
-#define db8500_add_i2c3(pdata) \
-        dbx500_add_i2c(3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata)
-#define db8500_add_i2c4(pdata) \
-        dbx500_add_i2c(4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
-
-#define db8500_add_msp0_i2s(pdata) \
-        dbx500_add_msp_i2s(0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
-#define db8500_add_msp1_i2s(pdata) \
-        dbx500_add_msp_i2s(1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
-#define db8500_add_msp2_i2s(pdata) \
-        dbx500_add_msp_i2s(2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
-#define db8500_add_msp3_i2s(pdata) \
-        dbx500_add_msp_i2s(3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
-
-#define db8500_add_msp0_spi(pdata) \
-        dbx500_add_msp_spi("msp0", U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
-#define db8500_add_msp1_spi(pdata) \
-        dbx500_add_msp_spi("msp1", U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
-#define db8500_add_msp2_spi(pdata) \
-        dbx500_add_msp_spi("msp2", U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
-#define db8500_add_msp3_spi(pdata) \
-        dbx500_add_msp_spi("msp3", U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
-
-#define db8500_add_rtc() \
-        dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC);
-
-#define db8500_add_usb(rx_cfg, tx_cfg) \
-        ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
-
-#define db8500_add_sdi0(pdata, pid) \
-        dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata, pid)
-#define db8500_add_sdi1(pdata, pid) \
-        dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata, pid)
-#define db8500_add_sdi2(pdata, pid) \
-        dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata, pid)
-#define db8500_add_sdi3(pdata, pid) \
-        dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata, pid)
-#define db8500_add_sdi4(pdata, pid) \
-        dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata, pid)
-#define db8500_add_sdi5(pdata, pid) \
-        dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata, pid)
-
-#define db8500_add_ssp0(pdata) \
-        db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata)
-#define db8500_add_ssp1(pdata) \
-        db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata)
-
-#define db8500_add_spi0(pdata) \
-        dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata, 0)
-#define db8500_add_spi1(pdata) \
-        dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata, 0)
-#define db8500_add_spi2(pdata) \
-        dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata, 0)
-#define db8500_add_spi3(pdata) \
-        dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata, 0)
-
-#define db8500_add_uart0(pdata) \
-        dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata)
-#define db8500_add_uart1(pdata) \
-        dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1, pdata)
-#define db8500_add_uart2(pdata) \
-        dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2, pdata)
+#define db8500_add_i2c0(parent, pdata) \
+        dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
+#define db8500_add_i2c1(parent, pdata) \
+        dbx500_add_i2c(parent, 1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata)
+#define db8500_add_i2c2(parent, pdata) \
+        dbx500_add_i2c(parent, 2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata)
+#define db8500_add_i2c3(parent, pdata) \
+        dbx500_add_i2c(parent, 3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata)
+#define db8500_add_i2c4(parent, pdata) \
+        dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
+
+#define db8500_add_msp0_i2s(parent, pdata) \
+        dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
+#define db8500_add_msp1_i2s(parent, pdata) \
+        dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
+#define db8500_add_msp2_i2s(parent, pdata) \
+        dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
+#define db8500_add_msp3_i2s(parent, pdata) \
+        dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
+
+#define db8500_add_msp0_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
+                           IRQ_DB8500_MSP0, pdata)
+#define db8500_add_msp1_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp1", U8500_MSP1_BASE, \
+                           IRQ_DB8500_MSP1, pdata)
+#define db8500_add_msp2_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp2", U8500_MSP2_BASE, \
+                           IRQ_DB8500_MSP2, pdata)
+#define db8500_add_msp3_spi(parent, pdata) \
+        dbx500_add_msp_spi(parent, "msp3", U8500_MSP3_BASE, \
+                           IRQ_DB8500_MSP1, pdata)
+
+#define db8500_add_rtc(parent) \
+        dbx500_add_rtc(parent, U8500_RTC_BASE, IRQ_DB8500_RTC);
+
+#define db8500_add_usb(parent, rx_cfg, tx_cfg) \
+        ux500_add_usb(parent, U8500_USBOTG_BASE, \
+                      IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
+
+#define db8500_add_sdi0(parent, pdata, pid) \
+        dbx500_add_sdi(parent, "sdi0", U8500_SDI0_BASE, \
+                       IRQ_DB8500_SDMMC0, pdata, pid)
+#define db8500_add_sdi1(parent, pdata, pid) \
+        dbx500_add_sdi(parent, "sdi1", U8500_SDI1_BASE, \
+                       IRQ_DB8500_SDMMC1, pdata, pid)
+#define db8500_add_sdi2(parent, pdata, pid) \
+        dbx500_add_sdi(parent, "sdi2", U8500_SDI2_BASE, \
+                       IRQ_DB8500_SDMMC2, pdata, pid)
+#define db8500_add_sdi3(parent, pdata, pid) \
+        dbx500_add_sdi(parent, "sdi3", U8500_SDI3_BASE, \
+                       IRQ_DB8500_SDMMC3, pdata, pid)
+#define db8500_add_sdi4(parent, pdata, pid) \
+        dbx500_add_sdi(parent, "sdi4", U8500_SDI4_BASE, \
+                       IRQ_DB8500_SDMMC4, pdata, pid)
+#define db8500_add_sdi5(parent, pdata, pid) \
+        dbx500_add_sdi(parent, "sdi5", U8500_SDI5_BASE, \
+                       IRQ_DB8500_SDMMC5, pdata, pid)
+
+#define db8500_add_ssp0(parent, pdata) \
+        db8500_add_ssp(parent, "ssp0", U8500_SSP0_BASE, \
+                       IRQ_DB8500_SSP0, pdata)
+#define db8500_add_ssp1(parent, pdata) \
+        db8500_add_ssp(parent, "ssp1", U8500_SSP1_BASE, \
+                       IRQ_DB8500_SSP1, pdata)
+
+#define db8500_add_spi0(parent, pdata) \
+        dbx500_add_spi(parent, "spi0", U8500_SPI0_BASE, \
+                       IRQ_DB8500_SPI0, pdata, 0)
+#define db8500_add_spi1(parent, pdata) \
+        dbx500_add_spi(parent, "spi1", U8500_SPI1_BASE, \
+                       IRQ_DB8500_SPI1, pdata, 0)
+#define db8500_add_spi2(parent, pdata) \
+        dbx500_add_spi(parent, "spi2", U8500_SPI2_BASE, \
+                       IRQ_DB8500_SPI2, pdata, 0)
+#define db8500_add_spi3(parent, pdata) \
+        dbx500_add_spi(parent, "spi3", U8500_SPI3_BASE, \
+                       IRQ_DB8500_SPI3, pdata, 0)
+
+#define db8500_add_uart0(parent, pdata) \
+        dbx500_add_uart(parent, "uart0", U8500_UART0_BASE, \
+                        IRQ_DB8500_UART0, pdata)
+#define db8500_add_uart1(parent, pdata) \
+        dbx500_add_uart(parent, "uart1", U8500_UART1_BASE, \
+                        IRQ_DB8500_UART1, pdata)
+#define db8500_add_uart2(parent, pdata) \
+        dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \
+                        IRQ_DB8500_UART2, pdata)
 
 #endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
index 1cfab68ae41..41e9470fa0e 100644
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -125,10 +125,11 @@ static struct platform_device dma40_device = {
         .resource       = dma40_resources
 };
 
-void __init db5500_dma_init(void)
+void __init db5500_dma_init(struct device *parent)
 {
         int ret;
 
+        dma40_device.dev.parent = parent;
         ret = platform_device_register(&dma40_device);
         if (ret)
                 dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 80e10f50282..9ec20b96d8f 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -161,4 +161,7 @@
 #define U8500_MODEM_BASE        0xe000000
 #define U8500_APE_BASE          0x6000000
 
+/* SoC identification number information */
+#define U8500_BB_UID_BASE      (U8500_BACKUPRAM1_BASE + 0xFC0)
+
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
deleted file mode 100644
index e16299e1020..00000000000
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Low-level IRQ helper macros for U8500 platforms
- *
- * Copyright (C) 2009 ST-Ericsson.
- *
- * This file is a copy of ARM Realview platform.
- *      -just satisfied checkpatch script.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index b6ba26a1367..d93d6dbef25 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -30,6 +30,8 @@
 #include <mach/db8500-regs.h>
 #include <mach/db5500-regs.h>
 
+#define MSP_TX_RX_REG_OFFSET    0
+
 #ifndef __ASSEMBLY__
 
 #include <mach/id.h>
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index d2d4131435a..7d34c52798b 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -13,7 +13,7 @@
 
 #define MOP500_AB8500_IRQ_BASE          IRQ_BOARD_START
 #define MOP500_AB8500_IRQ_END           (MOP500_AB8500_IRQ_BASE \
-                                         + AB8500_NR_IRQS)
+                                         + AB8500_MAX_NR_IRQS)
 
 /* TC35892 */
 #define TC35892_NR_INTERNAL_IRQS        8
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 9db68d264c5..c23a6b5f0c4 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -43,7 +43,7 @@
 /* This will be overridden by board-specific irq headers */
 #define IRQ_BOARD_END           IRQ_BOARD_START
 
-#ifdef CONFIG_MACH_U8500
+#ifdef CONFIG_MACH_MOP500
 #include <mach/irqs-board-mop500.h>
 #endif
 
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index a7d363fdb4c..3dc00ffa7bf 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -18,17 +18,16 @@ void __init ux500_map_io(void);
 extern void __init u5500_map_io(void);
 extern void __init u8500_map_io(void);
 
-extern void __init u5500_init_devices(void);
-extern void __init u8500_init_devices(void);
+extern struct device * __init u5500_init_devices(void);
+extern struct device * __init u8500_init_devices(void);
 
 extern void __init ux500_init_irq(void);
 
-extern void __init u5500_sdi_init(void);
+extern void __init u5500_sdi_init(struct device *parent);
 
-extern void __init db5500_dma_init(void);
+extern void __init db5500_dma_init(struct device *parent);
 
-/* We re-use nomadik_timer for this platform */
-extern void nmdk_timer_init(void);
+extern struct device *ux500_soc_device_init(const char *soc_id);
 
 struct amba_device;
 extern void __init amba_add_devices(struct amba_device *devs[], int num);
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
deleted file mode 100644
index 258e5c919c2..00000000000
--- a/arch/arm/mach-ux500/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h
index d3739d41881..4c1cc50a595 100644
--- a/arch/arm/mach-ux500/include/mach/usb.h
+++ b/arch/arm/mach-ux500/include/mach/usb.h
@@ -20,6 +20,6 @@ struct ux500_musb_board_data {
         bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
 };
 
-void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
-        int *dma_tx_cfg);
+void ux500_add_usb(struct device *parent, resource_size_t base,
+                   int irq, int *dma_rx_cfg, int *dma_tx_cfg);
 #endif
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
deleted file mode 100644
index 5ba113309a0..00000000000
--- a/arch/arm/mach-ux500/localtimer.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2008-2009 ST-Ericsson
- * Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
- *
- * This file is heavily based on relaview platform, almost a copy.
- *
- * Copyright (C) 2002 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index aea467d04ff..d37df98b5c3 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -7,29 +7,52 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
+#include <linux/of.h>
 
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 
 #include <plat/mtu.h>
 
 #include <mach/setup.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
+                              U5500_TWD_BASE, IRQ_LOCALTIMER);
+static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
+                              U8500_TWD_BASE, IRQ_LOCALTIMER);
+
+static void __init ux500_twd_init(void)
+{
+        struct twd_local_timer *twd_local_timer;
+        int err;
+
+        twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
+                                           &u8500_twd_local_timer;
+
+        if (of_have_populated_dt())
+                twd_local_timer_of_register();
+        else {
+                err = twd_local_timer_register(twd_local_timer);
+                if (err)
+                        pr_err("twd_local_timer_register failed %d\n", err);
+        }
+}
+#else
+#define ux500_twd_init()        do { } while(0)
+#endif
 
 static void __init ux500_timer_init(void)
 {
+        void __iomem *mtu_timer_base;
         void __iomem *prcmu_timer_base;
 
         if (cpu_is_u5500()) {
-#ifdef CONFIG_LOCAL_TIMERS
-                twd_base = __io_address(U5500_TWD_BASE);
-#endif
-                mtu_base = __io_address(U5500_MTU0_BASE);
+                mtu_timer_base = __io_address(U5500_MTU0_BASE);
                 prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
         } else if (cpu_is_u8500()) {
-#ifdef CONFIG_LOCAL_TIMERS
-                twd_base = __io_address(U8500_TWD_BASE);
-#endif
-                mtu_base = __io_address(U8500_MTU0_BASE);
+                mtu_timer_base = __io_address(U8500_MTU0_BASE);
                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
         } else {
                 ux500_unknown_soc();
@@ -52,8 +75,9 @@ static void __init ux500_timer_init(void)
          *
          */
 
-        nmdk_timer_init();
+        nmdk_timer_init(mtu_timer_base);
         clksrc_dbx500_prcmu_init(prcmu_timer_base);
+        ux500_twd_init();
 }
 
 static void ux500_timer_reset(void)
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 9f9e1c20306..a74af389bc6 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -7,6 +7,7 @@
 #include <linux/platform_device.h>
 #include <linux/usb/musb.h>
 #include <linux/dma-mapping.h>
+
 #include <plat/ste_dma40.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -140,8 +141,8 @@ static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
                 musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
 }
 
-void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
-        int *dma_tx_cfg)
+void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
+                   int *dma_rx_cfg, int *dma_tx_cfg)
 {
         ux500_musb_device.resource[0].start = base;
         ux500_musb_device.resource[0].end = base + SZ_64K - 1;
@@ -151,5 +152,7 @@ void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
         ux500_usb_dma_update_rx_ch_config(dma_rx_cfg);
         ux500_usb_dma_update_tx_ch_config(dma_tx_cfg);
 
+        ux500_musb_device.dev.parent = parent;
+
         platform_device_register(&ux500_musb_device);
 }
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 4cf706165af..6bbd74e950a 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -584,58 +584,58 @@ static struct pl022_ssp_controller ssp0_plat_data = {
         .num_chipselect = 1,
 };
 
-#define AACI_IRQ        { IRQ_AACI, NO_IRQ }
+#define AACI_IRQ        { IRQ_AACI }
 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
-#define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
-#define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
+#define KMI0_IRQ        { IRQ_SIC_KMI0 }
+#define KMI1_IRQ        { IRQ_SIC_KMI1 }
 
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
-#define SMC_IRQ         { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
-#define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
+#define SMC_IRQ         { }
+#define MPMC_IRQ        { }
+#define CLCD_IRQ        { IRQ_CLCDINT }
+#define DMAC_IRQ        { IRQ_DMAINT }
 
 /*
  * These devices are connected via the core APB bridge
  */
-#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
-#define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
-#define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
-#define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
+#define SCTL_IRQ        { }
+#define WATCHDOG_IRQ    { IRQ_WDOGINT }
+#define GPIO0_IRQ       { IRQ_GPIOINT0 }
+#define GPIO1_IRQ       { IRQ_GPIOINT1 }
+#define RTC_IRQ         { IRQ_RTCINT }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
-#define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
-#define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
-#define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
-#define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
-#define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
+#define SCI_IRQ         { IRQ_SCIINT }
+#define UART0_IRQ       { IRQ_UARTINT0 }
+#define UART1_IRQ       { IRQ_UARTINT1 }
+#define UART2_IRQ       { IRQ_UARTINT2 }
+#define SSP_IRQ         { IRQ_SSPINT }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
-AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
-AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
-AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
+APB_DEVICE(aaci,  "fpga:04", AACI,     NULL);
+APB_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
+APB_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
+APB_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
-AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
-AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
-AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
-AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
-AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
-AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
-AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
-AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
-AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
-AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
-AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
-AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
+AHB_DEVICE(smc,   "dev:00",  SMC,      NULL);
+AHB_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
+AHB_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
+AHB_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
+APB_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
+APB_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
+APB_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
+APB_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
+APB_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
+APB_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
+APB_DEVICE(uart0, "dev:f1",  UART0,    NULL);
+APB_DEVICE(uart1, "dev:f2",  UART1,    NULL);
+APB_DEVICE(uart2, "dev:f3",  UART2,    NULL);
+APB_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 2ef2f555f31..683e60776a8 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -36,20 +36,10 @@ extern unsigned int mmc_status(struct device *dev);
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
 #endif
 
-#define AMBA_DEVICE(name,busid,base,plat)                       \
-static struct amba_device name##_device = {                     \
-        .dev            = {                                     \
-                .coherent_dma_mask = ~0,                        \
-                .init_name = busid,                             \
-                .platform_data = plat,                          \
-        },                                                      \
-        .res            = {                                     \
-                .start  = VERSATILE_##base##_BASE,              \
-                .end    = (VERSATILE_##base##_BASE) + SZ_4K - 1,\
-                .flags  = IORESOURCE_MEM,                       \
-        },                                                      \
-        .dma_mask       = ~0,                                   \
-        .irq            = base##_IRQ,                           \
-}
+#define APB_DEVICE(name, busid, base, plat)     \
+static AMBA_APB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
+
+#define AHB_DEVICE(name, busid, base, plat)     \
+static AMBA_AHB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
 
 #endif
diff --git a/arch/arm/mach-versatile/include/mach/entry-macro.S b/arch/arm/mach-versatile/include/mach/entry-macro.S
deleted file mode 100644
index b6f0dbf122e..00000000000
--- a/arch/arm/mach-versatile/include/mach/entry-macro.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-versatile/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Versatile platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h
deleted file mode 100644
index f3fa347895f..00000000000
--- a/arch/arm/mach-versatile/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-versatile/include/mach/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 787cf5f26da..a6e23f46452 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -218,9 +218,9 @@ static int __init pci_versatile_setup_resources(struct list_head *resources)
          * the mem resource for this bus
          * the prefetch mem resource for this bus
          */
-        pci_add_resource(resources, &io_mem);
-        pci_add_resource(resources, &non_mem);
-        pci_add_resource(resources, &pre_mem);
+        pci_add_resource_offset(resources, &io_mem, sys->io_offset);
+        pci_add_resource_offset(resources, &non_mem, sys->mem_offset);
+        pci_add_resource_offset(resources, &pre_mem, sys->mem_offset);
 
         goto out;
 
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 9581c197500..19738331bd3 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -58,28 +58,28 @@ static struct pl061_platform_data gpio3_plat_data = {
         .irq_base       = IRQ_GPIO3_START,
 };
 
-#define UART3_IRQ       { IRQ_SIC_UART3, NO_IRQ }
-#define SCI1_IRQ        { IRQ_SIC_SCI3, NO_IRQ }
+#define UART3_IRQ       { IRQ_SIC_UART3 }
+#define SCI1_IRQ        { IRQ_SIC_SCI3 }
 #define MMCI1_IRQ       { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
 
 /*
  * These devices are connected via the core APB bridge
  */
-#define GPIO2_IRQ       { IRQ_GPIOINT2, NO_IRQ }
-#define GPIO3_IRQ       { IRQ_GPIOINT3, NO_IRQ }
+#define GPIO2_IRQ       { IRQ_GPIOINT2 }
+#define GPIO3_IRQ       { IRQ_GPIOINT3 }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
 
 /* FPGA Primecells */
-AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
-AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
-AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
+APB_DEVICE(uart3, "fpga:09", UART3,    NULL);
+APB_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
+APB_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 
 /* DevChip Primecells */
-AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
-AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
+APB_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
+APB_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart3_device,
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 88c3ba151e8..cf8730d35e7 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,14 +1,55 @@
 menu "Versatile Express platform type"
         depends on ARCH_VEXPRESS
 
+config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+        bool
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_751472
+        select PL310_ERRATA_753970 if CACHE_PL310
+        help
+          Provides common dependencies for Versatile Express platforms
+          based on Cortex-A5 and Cortex-A9 processors. In order to
+          build a working kernel, you must also enable relevant core
+          tile support or Flattened Device Tree based support options.
+
 config ARCH_VEXPRESS_CA9X4
         bool "Versatile Express Cortex-A9x4 tile"
+        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+        select ARM_GIC
         select CPU_V7
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+
+config ARCH_VEXPRESS_DT
+        bool "Device Tree support for Versatile Express platforms"
+        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         select ARM_GIC
-        select ARM_ERRATA_720789
-        select ARM_ERRATA_751472
-        select PL310_ERRATA_753970
+        select ARM_PATCH_PHYS_VIRT
+        select AUTO_ZRELADDR
+        select CPU_V7
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select USE_OF
+        help
+          New Versatile Express platforms require Flattened Device Tree to
+          be passed to the kernel.
+
+          This option enables support for systems using Cortex processor based
+          ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
+          for example:
+
+          - CoreTile Express A5x2 (V2P-CA5s)
+          - CoreTile Express A9x4 (V2P-CA9)
+          - CoreTile Express A15x2 (V2P-CA15)
+          - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
+            (Soft Macrocell Models)
+          - Versatile Express RTSMs (Models)
+
+          You must boot using a Flattened Device Tree in order to use these
+          platforms. The traditional (ATAGs) boot method is not usable on
+          these boards with this option.
+
+          If your bootloader supports Flattened Device Tree based booting,
+          say Y here.
 
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 8630b3d10a4..909f85ebf5f 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -1,3 +1,9 @@
+# Those numbers are used only by the non-DT V2P-CA9 platform
+# The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y
    zreladdr-y   += 0x60008000
 params_phys-y   := 0x60000100
 initrd_phys-y   := 0x60800000
+
+dtb-$(CONFIG_ARCH_VEXPRESS_DT)  += vexpress-v2p-ca5s.dtb \
+                                   vexpress-v2p-ca9.dtb \
+                                   vexpress-v2p-ca15-tc1.dtb
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f4397159c17..a3a4980770b 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,19 +1,7 @@
-#define __MMIO_P2V(x)   (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
-#define MMIO_P2V(x)     ((void __iomem *)__MMIO_P2V(x))
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH 0xf8000000
 
-#define AMBA_DEVICE(name,busid,base,plat)       \
-struct amba_device name##_device = {            \
-        .dev            = {                     \
-                .coherent_dma_mask = ~0UL,      \
-                .init_name = busid,             \
-                .platform_data = plat,          \
-        },                                      \
-        .res            = {                     \
-                .start  = base,                 \
-                .end    = base + SZ_4K - 1,     \
-                .flags  = IORESOURCE_MEM,       \
-        },                                      \
-        .dma_mask       = ~0UL,                 \
-        .irq            = IRQ_##base,           \
-        /* .dma         = DMA_##base,*/         \
-}
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH 0xf8200000
+
+void vexpress_dt_smp_map_io(void);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index b1e87c184e5..c65cc3b462a 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,40 @@
 
 #include <plat/clcd.h>
 
-#define V2M_PA_CS7      0x10000000
-
 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
         {
-                .virtual        = __MMIO_P2V(CT_CA9X4_MPIC),
-                .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
-                .pfn            = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = __MMIO_P2V(CT_CA9X4_L2CC),
-                .pfn            = __phys_to_pfn(CT_CA9X4_L2CC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
+                .virtual        = V2T_PERIPH,
+                .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
         },
 };
 
 static void __init ct_ca9x4_map_io(void)
 {
-#ifdef CONFIG_LOCAL_TIMERS
-        twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
-static void __init ct_ca9x4_init_irq(void)
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
+
+static void __init ca9x4_twd_init(void)
 {
-        gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-                 MMIO_P2V(A9_MPCORE_GIC_CPU));
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
 }
+#else
+#define ca9x4_twd_init()        do {} while(0)
+#endif
 
-#if 0
-static void __init ct_ca9x4_timer_init(void)
+static void __init ct_ca9x4_init_irq(void)
 {
-        writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
-        writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
-        sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
-        sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
-                "ct-timer0");
+        gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
+                 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
+        ca9x4_twd_init();
 }
 
-static struct sys_timer ct_ca9x4_timer = {
-        .init   = ct_ca9x4_timer_init,
-};
-#endif
-
 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 {
         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -109,10 +92,10 @@ static struct clcd_board ct_ca9x4_clcd_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
-static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
-static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
-static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
+static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
+static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
+static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
+static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
 
 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
         &clcd_device,
@@ -201,7 +184,7 @@ static void __init ct_ca9x4_init(void)
         int i;
 
 #ifdef CONFIG_CACHE_L2X0
-        void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
 
         /* set RAM latencies to 1 cycle for this core tile. */
         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -217,9 +200,17 @@ static void __init ct_ca9x4_init(void)
 }
 
 #ifdef CONFIG_SMP
+static void *ct_ca9x4_scu_base __initdata;
+
 static void __init ct_ca9x4_init_cpu_map(void)
 {
-        int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+        int i, ncores;
+
+        ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
+        if (WARN_ON(!ct_ca9x4_scu_base))
+                return;
+
+        ncores = scu_get_core_count(ct_ca9x4_scu_base);
 
         if (ncores > nr_cpu_ids) {
                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -235,7 +226,7 @@ static void __init ct_ca9x4_init_cpu_map(void)
 
 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
 {
-        scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+        scu_enable(ct_ca9x4_scu_base);
 }
 #endif
 
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index a34d3d4faae..84acf8439d4 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -22,9 +22,6 @@
 #define CT_CA9X4_SYSWDT         (0x1e007000)
 #define CT_CA9X4_L2CC           (0x1e00a000)
 
-#define CT_CA9X4_TIMER0         (CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1         (CT_CA9X4_SP804_TIMER + 0x020)
-
 #define A9_MPCORE_SCU           (CT_CA9X4_MPIC + 0x0000)
 #define A9_MPCORE_GIC_CPU       (CT_CA9X4_MPIC + 0x0100)
 #define A9_MPCORE_GIT           (CT_CA9X4_MPIC + 0x0200)
@@ -35,7 +32,7 @@
  * Interrupts.  Those in {} are for AMBA devices
  */
 #define IRQ_CT_CA9X4_CLCDC      { 76 }
-#define IRQ_CT_CA9X4_DMC        { -1 }
+#define IRQ_CT_CA9X4_DMC        { 0 }
 #define IRQ_CT_CA9X4_SMC        { 77, 78 }
 #define IRQ_CT_CA9X4_TIMER0     80
 #define IRQ_CT_CA9X4_TIMER1     81
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7ea49..fa8224794e0 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,34 @@
  * published by the Free Software Foundation.
  */
 
-#define DEBUG_LL_UART_OFFSET    0x00009000
+#define DEBUG_LL_PHYS_BASE              0x10000000
+#define DEBUG_LL_UART_OFFSET            0x00009000
+
+#define DEBUG_LL_PHYS_BASE_RS1          0x1c000000
+#define DEBUG_LL_UART_OFFSET_RS1        0x00090000
+
+#define DEBUG_LL_VIRT_BASE              0xf8000000
 
                 .macro  addruart,rp,rv,tmp
-                mov     \rp, #DEBUG_LL_UART_OFFSET
-                orr     \rv, \rp, #0xf8000000   @ virtual base
-                orr     \rp, \rp, #0x10000000   @ physical base
+
+                @ Make an educated guess regarding the memory map:
+                @ - the original A9 core tile, which has MPCore peripherals
+                @   located at 0x1e000000, should use UART at 0x10009000
+                @ - all other (RS1 complaint) tiles use UART mapped
+                @   at 0x1c090000
+                mrc     p15, 4, \tmp, c15, c0, 0
+                cmp     \tmp, #0x1e000000
+
+                @ Original memory map
+                moveq   \rp, #DEBUG_LL_UART_OFFSET
+                orreq   \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orreq   \rp, \rp, #DEBUG_LL_PHYS_BASE
+
+                @ RS1 memory map
+                movne   \rp, #DEBUG_LL_UART_OFFSET_RS1
+                orrne   \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orrne   \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
deleted file mode 100644
index a14f9e62ca9..00000000000
--- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ /dev/null
@@ -1,5 +0,0 @@
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
index 7054cbfc9de..4b10ee7657a 100644
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -1,4 +1,4 @@
 #define IRQ_LOCALTIMER          29
 #define IRQ_LOCALWDOG           30
 
-#define NR_IRQS 128
+#define NR_IRQS 256
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 0a3a3751840..31a92890893 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -39,33 +39,30 @@
 #define V2M_CF                  (V2M_PA_CS7 + 0x0001a000)
 #define V2M_CLCD                (V2M_PA_CS7 + 0x0001f000)
 
-#define V2M_SYS_ID              (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW              (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED             (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ           (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS           (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET        (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR        (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS         (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET      (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR      (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI             (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH           (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW           (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ           (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC            (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA             (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0         (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1         (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA         (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL         (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT         (V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0              (V2M_TIMER01 + 0x000)
-#define V2M_TIMER1              (V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2              (V2M_TIMER23 + 0x000)
-#define V2M_TIMER3              (V2M_TIMER23 + 0x020)
+/*
+ * Offsets from SYSREGS base
+ */
+#define V2M_SYS_ID              0x000
+#define V2M_SYS_SW              0x004
+#define V2M_SYS_LED             0x008
+#define V2M_SYS_100HZ           0x024
+#define V2M_SYS_FLAGS           0x030
+#define V2M_SYS_FLAGSSET        0x030
+#define V2M_SYS_FLAGSCLR        0x034
+#define V2M_SYS_NVFLAGS         0x038
+#define V2M_SYS_NVFLAGSSET      0x038
+#define V2M_SYS_NVFLAGSCLR      0x03c
+#define V2M_SYS_MCI             0x048
+#define V2M_SYS_FLASH           0x03c
+#define V2M_SYS_CFGSW           0x058
+#define V2M_SYS_24MHZ           0x05c
+#define V2M_SYS_MISC            0x060
+#define V2M_SYS_DMA             0x064
+#define V2M_SYS_PROCID0         0x084
+#define V2M_SYS_PROCID1         0x088
+#define V2M_SYS_CFGDATA         0x0a0
+#define V2M_SYS_CFGCTRL         0x0a4
+#define V2M_SYS_CFGSTAT         0x0a8
 
 
 /*
@@ -117,6 +114,13 @@
 
 int v2m_cfg_write(u32 devfn, u32 data);
 int v2m_cfg_read(u32 devfn, u32 *data);
+void v2m_flags_set(u32 data);
+
+/*
+ * Miscellaneous
+ */
+#define SYS_MISC_MASTERSITE     (1 << 14)
+#define SYS_PROCIDx_HBI_MASK    0xfff
 
 /*
  * Core tile IDs
diff --git a/arch/arm/mach-vexpress/include/mach/system.h b/arch/arm/mach-vexpress/include/mach/system.h
deleted file mode 100644
index f653a8e265b..00000000000
--- a/arch/arm/mach-vexpress/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c5748d0..7dab5596b86 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,27 @@
 #define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
 #define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
 
-#define get_uart_base() (0x10000000 + 0x00009000)
+#define UART_BASE       0x10009000
+#define UART_BASE_RS1   0x1c090000
+
+static unsigned long get_uart_base(void)
+{
+        unsigned long mpcore_periph;
+
+        /*
+         * Make an educated guess regarding the memory map:
+         * - the original A9 core tile, which has MPCore peripherals
+         *   located at 0x1e000000, should use UART at 0x10009000
+         * - all other (RS1 complaint) tiles use UART mapped
+         *   at 0x1c090000
+         */
+        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
+
+        if (mpcore_periph == 0x1e000000)
+                return UART_BASE;
+        else
+                return UART_BASE_RS1;
+}
 
 /*
  * This does not append a newline
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 124ffb16909..14ba1128ae8 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,21 +12,168 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/of_fdt.h>
+
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
 
 #include <mach/motherboard.h>
-#define V2M_PA_CS7 0x10000000
 
 #include "core.h"
 
 extern void versatile_secondary_startup(void);
 
+#if defined(CONFIG_OF)
+
+static enum {
+        GENERIC_SCU,
+        CORTEX_A9_SCU,
+} vexpress_dt_scu __initdata = GENERIC_SCU;
+
+static struct map_desc vexpress_dt_cortex_a9_scu_map __initdata = {
+        .virtual        = V2T_PERIPH,
+        /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
+        .length         = SZ_128,
+        .type           = MT_DEVICE,
+};
+
+static void *vexpress_dt_cortex_a9_scu_base __initdata;
+
+const static char *vexpress_dt_cortex_a9_match[] __initconst = {
+        "arm,cortex-a5-scu",
+        "arm,cortex-a9-scu",
+        NULL
+};
+
+static int __init vexpress_dt_find_scu(unsigned long node,
+                const char *uname, int depth, void *data)
+{
+        if (of_flat_dt_match(node, vexpress_dt_cortex_a9_match)) {
+                phys_addr_t phys_addr;
+                __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL);
+
+                if (WARN_ON(!reg))
+                        return -EINVAL;
+
+                phys_addr = be32_to_cpup(reg);
+                vexpress_dt_scu = CORTEX_A9_SCU;
+
+                vexpress_dt_cortex_a9_scu_map.pfn = __phys_to_pfn(phys_addr);
+                iotable_init(&vexpress_dt_cortex_a9_scu_map, 1);
+                vexpress_dt_cortex_a9_scu_base = ioremap(phys_addr, SZ_256);
+                if (WARN_ON(!vexpress_dt_cortex_a9_scu_base))
+                        return -EFAULT;
+        }
+
+        return 0;
+}
+
+void __init vexpress_dt_smp_map_io(void)
+{
+        if (initial_boot_params)
+                WARN_ON(of_scan_flat_dt(vexpress_dt_find_scu, NULL));
+}
+
+static int __init vexpress_dt_cpus_num(unsigned long node, const char *uname,
+                int depth, void *data)
+{
+        static int prev_depth = -1;
+        static int nr_cpus = -1;
+
+        if (prev_depth > depth && nr_cpus > 0)
+                return nr_cpus;
+
+        if (nr_cpus < 0 && strcmp(uname, "cpus") == 0)
+                nr_cpus = 0;
+
+        if (nr_cpus >= 0) {
+                const char *device_type = of_get_flat_dt_prop(node,
+                                "device_type", NULL);
+
+                if (device_type && strcmp(device_type, "cpu") == 0)
+                        nr_cpus++;
+        }
+
+        prev_depth = depth;
+
+        return 0;
+}
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+        int ncores = 0, i;
+
+        switch (vexpress_dt_scu) {
+        case GENERIC_SCU:
+                ncores = of_scan_flat_dt(vexpress_dt_cpus_num, NULL);
+                break;
+        case CORTEX_A9_SCU:
+                ncores = scu_get_core_count(vexpress_dt_cortex_a9_scu_base);
+                break;
+        default:
+                WARN_ON(1);
+                break;
+        }
+
+        if (ncores < 2)
+                return;
+
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                                ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
+        }
+
+        for (i = 0; i < ncores; ++i)
+                set_cpu_possible(i, true);
+
+        set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
+
+        switch (vexpress_dt_scu) {
+        case GENERIC_SCU:
+                for (i = 0; i < max_cpus; i++)
+                        set_cpu_present(i, true);
+                break;
+        case CORTEX_A9_SCU:
+                scu_enable(vexpress_dt_cortex_a9_scu_base);
+                break;
+        default:
+                WARN_ON(1);
+                break;
+        }
+}
+
+#else
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+        WARN_ON(1);
+}
+
+void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+        WARN_ON(1);
+}
+
+#endif
+
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
-        ct_desc->init_cpu_map();
+        if (ct_desc)
+                ct_desc->init_cpu_map();
+        else
+                vexpress_dt_smp_init_cpus();
+
 }
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
@@ -35,7 +182,10 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * Initialise the present map, which describes the set of CPUs
          * actually populated at the present time.
          */
-        ct_desc->smp_enable(max_cpus);
+        if (ct_desc)
+                ct_desc->smp_enable(max_cpus);
+        else
+                vexpress_dt_smp_prepare_cpus(max_cpus);
 
         /*
          * Write the address of secondary startup into the
@@ -43,7 +193,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
-        writel(virt_to_phys(versatile_secondary_startup),
-                MMIO_P2V(V2M_SYS_FLAGSSET));
+        v2m_flags_set(virt_to_phys(versatile_secondary_startup));
 }
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index b4a28ca0e50..47cdcca5a7e 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -6,6 +6,10 @@
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/smsc911x.h>
@@ -21,6 +25,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/arm_timer.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/sp810.h>
 #include <asm/hardware/gic.h>
@@ -40,29 +46,45 @@
 
 static struct map_desc v2m_io_desc[] __initdata = {
         {
-                .virtual        = __MMIO_P2V(V2M_PA_CS7),
+                .virtual        = V2M_PERIPH,
                 .pfn            = __phys_to_pfn(V2M_PA_CS7),
                 .length         = SZ_128K,
                 .type           = MT_DEVICE,
         },
 };
 
-static void __init v2m_timer_init(void)
+static void __iomem *v2m_sysreg_base;
+
+static void __init v2m_sysctl_init(void __iomem *base)
 {
         u32 scctrl;
 
+        if (WARN_ON(!base))
+                return;
+
         /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
-        scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
+        scctrl = readl(base + SCCTRL);
         scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
         scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
-        writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
+        writel(scctrl, base + SCCTRL);
+}
+
+static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
+{
+        if (WARN_ON(!base || irq == NO_IRQ))
+                return;
+
+        writel(0, base + TIMER_1_BASE + TIMER_CTRL);
+        writel(0, base + TIMER_2_BASE + TIMER_CTRL);
 
-        writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
-        writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
+        sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
+        sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
+}
 
-        sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
-        sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
-                "v2m-timer0");
+static void __init v2m_timer_init(void)
+{
+        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
 }
 
 static struct sys_timer v2m_timer = {
@@ -82,14 +104,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
         devfn |= SYS_CFG_START | SYS_CFG_WRITE;
 
         spin_lock(&v2m_cfg_lock);
-        val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
-        writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+        val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
+        writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
 
-        writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
-        writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+        writel(data, v2m_sysreg_base +  V2M_SYS_CFGDATA);
+        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
 
         do {
-                val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
         } while (val == 0);
         spin_unlock(&v2m_cfg_lock);
 
@@ -103,22 +125,28 @@ int v2m_cfg_read(u32 devfn, u32 *data)
         devfn |= SYS_CFG_START;
 
         spin_lock(&v2m_cfg_lock);
-        writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
-        writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+        writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
+        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
 
         mb();
 
         do {
                 cpu_relax();
-                val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
         } while (val == 0);
 
-        *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+        *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
         spin_unlock(&v2m_cfg_lock);
 
         return !!(val & SYS_CFG_ERR);
 }
 
+void __init v2m_flags_set(u32 data)
+{
+        writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
+        writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
+}
+
 
 static struct resource v2m_pcie_i2c_resource = {
         .start  = V2M_SERIAL_BUS_PCI,
@@ -204,7 +232,7 @@ static struct platform_device v2m_usb_device = {
 
 static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
 {
-        writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+        writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
 }
 
 static struct physmap_flash_data v2m_flash_data = {
@@ -258,7 +286,7 @@ static struct platform_device v2m_cf_device = {
 
 static unsigned int v2m_mmci_status(struct device *dev)
 {
-        return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+        return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
 }
 
 static struct mmci_platform_data v2m_mmci_data = {
@@ -266,16 +294,16 @@ static struct mmci_platform_data v2m_mmci_data = {
         .status         = v2m_mmci_status,
 };
 
-static AMBA_DEVICE(aaci,  "mb:aaci",  V2M_AACI, NULL);
-static AMBA_DEVICE(mmci,  "mb:mmci",  V2M_MMCI, &v2m_mmci_data);
-static AMBA_DEVICE(kmi0,  "mb:kmi0",  V2M_KMI0, NULL);
-static AMBA_DEVICE(kmi1,  "mb:kmi1",  V2M_KMI1, NULL);
-static AMBA_DEVICE(uart0, "mb:uart0", V2M_UART0, NULL);
-static AMBA_DEVICE(uart1, "mb:uart1", V2M_UART1, NULL);
-static AMBA_DEVICE(uart2, "mb:uart2", V2M_UART2, NULL);
-static AMBA_DEVICE(uart3, "mb:uart3", V2M_UART3, NULL);
-static AMBA_DEVICE(wdt,   "mb:wdt",   V2M_WDT, NULL);
-static AMBA_DEVICE(rtc,   "mb:rtc",   V2M_RTC, NULL);
+static AMBA_APB_DEVICE(aaci,  "mb:aaci",  0, V2M_AACI, IRQ_V2M_AACI, NULL);
+static AMBA_APB_DEVICE(mmci,  "mb:mmci",  0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
+static AMBA_APB_DEVICE(kmi0,  "mb:kmi0",  0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
+static AMBA_APB_DEVICE(kmi1,  "mb:kmi1",  0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
+static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
+static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
+static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
+static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
+static AMBA_APB_DEVICE(wdt,   "mb:wdt",   0, V2M_WDT, IRQ_V2M_WDT, NULL);
+static AMBA_APB_DEVICE(rtc,   "mb:rtc",   0, V2M_RTC, IRQ_V2M_RTC, NULL);
 
 static struct amba_device *v2m_amba_devs[] __initdata = {
         &aaci_device,
@@ -371,7 +399,7 @@ static void __init v2m_init_early(void)
 {
         ct_desc->init_early();
         clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
-        versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+        versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
 static void v2m_power_off(void)
@@ -400,20 +428,23 @@ static void __init v2m_populate_ct_desc(void)
         u32 current_tile_id;
 
         ct_desc = NULL;
-        current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+        current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+                                & V2M_CT_ID_MASK;
 
         for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
                 if (ct_descs[i]->id == current_tile_id)
                         ct_desc = ct_descs[i];
 
         if (!ct_desc)
-                panic("vexpress: failed to populate core tile description "
-                      "for tile ID 0x%8x\n", current_tile_id);
+                panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
+                      "You may need a device tree blob or a different kernel to boot on this board.\n",
+                      current_tile_id);
 }
 
 static void __init v2m_map_io(void)
 {
         iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+        v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
         v2m_populate_ct_desc();
         ct_desc->map_io();
 }
@@ -452,3 +483,205 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
         .init_machine   = v2m_init,
         .restart        = v2m_restart,
 MACHINE_END
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+static struct map_desc v2m_rs1_io_desc __initdata = {
+        .virtual        = V2M_PERIPH,
+        .pfn            = __phys_to_pfn(0x1c000000),
+        .length         = SZ_2M,
+        .type           = MT_DEVICE,
+};
+
+static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
+                int depth, void *data)
+{
+        const char **map = data;
+
+        if (strcmp(uname, "motherboard") != 0)
+                return 0;
+
+        *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
+
+        return 1;
+}
+
+void __init v2m_dt_map_io(void)
+{
+        const char *map = NULL;
+
+        of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
+
+        if (map && strcmp(map, "rs1") == 0)
+                iotable_init(&v2m_rs1_io_desc, 1);
+        else
+                iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+
+#if defined(CONFIG_SMP)
+        vexpress_dt_smp_map_io();
+#endif
+}
+
+static struct clk_lookup v2m_dt_lookups[] = {
+        {       /* AMBA bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* SP804 timers */
+                .dev_id         = "sp804",
+                .con_id         = "v2m-timer0",
+                .clk            = &v2m_sp804_clk,
+        }, {    /* SP804 timers */
+                .dev_id         = "sp804",
+                .con_id         = "v2m-timer1",
+                .clk            = &v2m_sp804_clk,
+        }, {    /* PL180 MMCI */
+                .dev_id         = "mb:mmci", /* 10005000.mmci */
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI0 */
+                .dev_id         = "10006000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI1 */
+                .dev_id         = "10007000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART0 */
+                .dev_id         = "10009000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART1 */
+                .dev_id         = "1000a000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART2 */
+                .dev_id         = "1000b000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART3 */
+                .dev_id         = "1000c000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* SP805 WDT */
+                .dev_id         = "1000f000.wdt",
+                .clk            = &v2m_ref_clk,
+        }, {    /* PL111 CLCD */
+                .dev_id         = "1001f000.clcd",
+                .clk            = &osc1_clk,
+        },
+        /* RS1 memory map */
+        {       /* PL180 MMCI */
+                .dev_id         = "mb:mmci", /* 1c050000.mmci */
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI0 */
+                .dev_id         = "1c060000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI1 */
+                .dev_id         = "1c070000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART0 */
+                .dev_id         = "1c090000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART1 */
+                .dev_id         = "1c0a0000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART2 */
+                .dev_id         = "1c0b0000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART3 */
+                .dev_id         = "1c0c0000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* SP805 WDT */
+                .dev_id         = "1c0f0000.wdt",
+                .clk            = &v2m_ref_clk,
+        }, {    /* PL111 CLCD */
+                .dev_id         = "1c1f0000.clcd",
+                .clk            = &osc1_clk,
+        },
+};
+
+void __init v2m_dt_init_early(void)
+{
+        struct device_node *node;
+        u32 dt_hbi;
+
+        node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
+        v2m_sysreg_base = of_iomap(node, 0);
+        if (WARN_ON(!v2m_sysreg_base))
+                return;
+
+        /* Confirm board type against DT property, if available */
+        if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
+                u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+                u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+                                V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
+                u32 hbi = id & SYS_PROCIDx_HBI_MASK;
+
+                if (WARN_ON(dt_hbi != hbi))
+                        pr_warning("vexpress: DT HBI (%x) is not matching "
+                                        "hardware (%x)!\n", dt_hbi, hbi);
+        }
+
+        clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
+        versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+}
+
+static  struct of_device_id vexpress_irq_match[] __initdata = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {}
+};
+
+static void __init v2m_dt_init_irq(void)
+{
+        of_irq_init(vexpress_irq_match);
+}
+
+static void __init v2m_dt_timer_init(void)
+{
+        struct device_node *node;
+        const char *path;
+        int err;
+
+        node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+        v2m_sysctl_init(of_iomap(node, 0));
+
+        err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
+}
+
+static struct sys_timer v2m_dt_timer = {
+        .init = v2m_dt_timer_init,
+};
+
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+                        &v2m_flash_data),
+        OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+        /* RS1 memory map */
+        OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
+                        &v2m_flash_data),
+        OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
+        {}
+};
+
+static void __init v2m_dt_init(void)
+{
+        l2x0_of_init(0x00400000, 0xfe0fffff);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        v2m_dt_auxdata_lookup, NULL);
+        pm_power_off = v2m_power_off;
+}
+
+const static char *v2m_dt_match[] __initconst = {
+        "arm,vexpress",
+        NULL,
+};
+
+DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
+        .dt_compat      = v2m_dt_match,
+        .map_io         = v2m_dt_map_io,
+        .init_early     = v2m_dt_init_early,
+        .init_irq       = v2m_dt_init_irq,
+        .timer          = &v2m_dt_timer,
+        .init_machine   = v2m_dt_init,
+        .handle_irq     = gic_handle_irq,
+        .restart        = v2m_restart,
+MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-vt8500/include/mach/entry-macro.S b/arch/arm/mach-vt8500/include/mach/entry-macro.S
index 92684c7eaed..367d1b55fb9 100644
--- a/arch/arm/mach-vt8500/include/mach/entry-macro.S
+++ b/arch/arm/mach-vt8500/include/mach/entry-macro.S
@@ -8,18 +8,12 @@
  * warranty of any kind, whether express or implied.
  */
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         @ physical 0xd8140000 is virtual 0xf8140000
         mov     \base, #0xf8000000
         orr     \base, \base, #0x00140000
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqnr, [\base]
         cmp     \irqnr, #63 @ may be false positive, check interrupt status
diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h
index d6c757eaf26..58fa8010ee6 100644
--- a/arch/arm/mach-vt8500/include/mach/system.h
+++ b/arch/arm/mach-vt8500/include/mach/system.h
@@ -7,11 +7,6 @@
 /* PM Software Reset request register */
 #define VT8500_PMSR_VIRT        0xf8130060
 
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
 static inline void arch_reset(char mode, const char *cmd)
 {
         writel(1, VT8500_PMSR_VIRT);
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 78110befb7a..db82568a998 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -530,6 +530,7 @@ static struct platform_device *nuc900_public_dev[] __initdata = {
 
 void __init nuc900_board_init(struct platform_device **device, int size)
 {
+        disable_hlt();
         platform_add_devices(device, size);
         platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev));
         spi_register_board_info(nuc900_spi_board_info,
diff --git a/arch/arm/mach-w90x900/include/mach/entry-macro.S b/arch/arm/mach-w90x900/include/mach/entry-macro.S
index d39aca5be9e..e286daca682 100644
--- a/arch/arm/mach-w90x900/include/mach/entry-macro.S
+++ b/arch/arm/mach-w90x900/include/mach/entry-macro.S
@@ -15,9 +15,6 @@
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \base, #AIC_BA
@@ -27,8 +24,3 @@
                 cmp     \irqnr, #0
 
         .endm
-
-        /* currently don't need an disable_fiq macro */
-
-        .macro  disable_fiq
-        .endm
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
deleted file mode 100644
index 2aaeb931161..00000000000
--- a/arch/arm/mach-w90x900/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-w90x900/include/mach/system.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/system.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-static void arch_idle(void)
-{
-}
diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S
deleted file mode 100644
index d621fb73256..00000000000
--- a/arch/arm/mach-zynq/include/mach/entry-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-zynq/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros
- *
- *  Copyright (C) 2011 Xilinx
- *
- * based on arch/plat-mxc/include/mach/entry-macro.S
- *
- *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-zynq/include/mach/system.h b/arch/arm/mach-zynq/include/mach/system.h
deleted file mode 100644
index 8e88e0b8d2b..00000000000
--- a/arch/arm/mach-zynq/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/system.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_SYSTEM_H__
-#define __MACH_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
index e62956e1203..4614208369f 100644
--- a/arch/arm/mm/iomap.c
+++ b/arch/arm/mm/iomap.c
@@ -32,9 +32,6 @@ EXPORT_SYMBOL(pcibios_min_io);
 unsigned long pcibios_min_mem = 0x01000000;
 EXPORT_SYMBOL(pcibios_min_mem);
 
-unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC;
-EXPORT_SYMBOL(pci_flags);
-
 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 {
         if ((unsigned long)addr >= VMALLOC_START &&
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index bb269819666..0da42058a20 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -214,8 +214,8 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
         sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
         sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
 
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55f15699a38..689f81f9593 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -60,7 +60,7 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
         unsigned int mask = 0x0F << irq % 8 * 4;
 
         if (irq >= AVIC_NUM_IRQS)
-                return -EINVAL;;
+                return -EINVAL;
 
         temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
         temp &= ~mask;
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index f5b7e0fa237..220dd6f9312 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -1,5 +1,6 @@
 
 #include <linux/module.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 
 unsigned int __mxc_cpu_type;
@@ -18,3 +19,26 @@ void imx_print_silicon_rev(const char *cpu, int srev)
                 pr_info("CPU identified as %s, silicon rev %d.%d\n",
                                 cpu, (srev >> 4) & 0xf, srev & 0xf);
 }
+
+void __init imx_set_aips(void __iomem *base)
+{
+        unsigned int reg;
+/*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+        __raw_writel(0x77777777, base + 0x0);
+        __raw_writel(0x77777777, base + 0x4);
+
+/*
+ * Set all OPACRx to be non-bufferable, to not require
+ * supervisor privilege level for access, allow for
+ * write access and untrusted master access.
+ */
+        __raw_writel(0x0, base + 0x40);
+        __raw_writel(0x0, base + 0x44);
+        __raw_writel(0x0, base + 0x48);
+        __raw_writel(0x0, base + 0x4C);
+        reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+        __raw_writel(reg, base + 0x50);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
index d8a56aee521..ade4a1c4e2a 100644
--- a/arch/arm/plat-mxc/devices/platform-ahci-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
@@ -60,9 +60,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
                 dev_err(dev, "no sata clock.\n");
                 return PTR_ERR(sata_clk);
         }
-        ret = clk_enable(sata_clk);
+        ret = clk_prepare_enable(sata_clk);
         if (ret) {
-                dev_err(dev, "can't enable sata clock.\n");
+                dev_err(dev, "can't prepare/enable sata clock.\n");
                 goto put_sata_clk;
         }
 
@@ -73,9 +73,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
                 ret = PTR_ERR(sata_ref_clk);
                 goto release_sata_clk;
         }
-        ret = clk_enable(sata_ref_clk);
+        ret = clk_prepare_enable(sata_ref_clk);
         if (ret) {
-                dev_err(dev, "can't enable sata ref clock.\n");
+                dev_err(dev, "can't prepare/enable sata ref clock.\n");
                 goto put_sata_ref_clk;
         }
 
@@ -104,11 +104,11 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
         return 0;
 
 release_sata_ref_clk:
-        clk_disable(sata_ref_clk);
+        clk_disable_unprepare(sata_ref_clk);
 put_sata_ref_clk:
         clk_put(sata_ref_clk);
 release_sata_clk:
-        clk_disable(sata_clk);
+        clk_disable_unprepare(sata_clk);
 put_sata_clk:
         clk_put(sata_clk);
 
@@ -117,10 +117,10 @@ put_sata_clk:
 
 static void imx_sata_exit(struct device *dev)
 {
-        clk_disable(sata_ref_clk);
+        clk_disable_unprepare(sata_ref_clk);
         clk_put(sata_ref_clk);
 
-        clk_disable(sata_clk);
+        clk_disable_unprepare(sata_clk);
         clk_put(sata_clk);
 
 }
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
index b3f4828dc44..11eace953a0 100644
--- a/arch/arm/plat-mxc/devices/platform-mx2-camera.c
+++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
@@ -62,3 +62,21 @@ struct platform_device *__init imx_add_mx2_camera(
                         res, data->iobaseemmaprp ? 4 : 2,
                         pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 }
+
+struct platform_device *__init imx_add_mx2_emmaprp(
+                const struct imx_mx2_camera_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobaseemmaprp,
+                        .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irqemmaprp,
+                        .end = data->irqemmaprp,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
+                        res, 2, NULL, 0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index d3467f818c3..9129c9e7d53 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -203,7 +203,7 @@ static int __init epit_clockevent_init(struct clk *timer_clk)
 
 void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
 
         timer_base = base;
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 94b60dd4713..00000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-
-#include <mach/hardware.h>
-
-/*
- * These symbols are used by drivers/net/cs89x0.c.
- * This is ugly as hell, but we have to provide them until
- * someone fixed the driver.
- */
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
-/* Offsets for the PBC Controller register */
-
-/* Ethernet Controller IO base address */
-#define PBC_CS8900A_IOBASE      0x020000
-
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 1bf0df81bdc..0319c4a0caf 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -65,6 +65,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
+extern int mx27_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
@@ -75,6 +76,7 @@ extern void mxc_restart(char, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
+extern void imx_set_aips(void __iomem *);
 
 enum mxc_cpu_pwr_mode {
         WAIT_CLOCKED,           /* wfi only */
@@ -84,6 +86,14 @@ enum mxc_cpu_pwr_mode {
         STOP_POWER_OFF,         /* STOP + SRPG */
 };
 
+enum mx3_cpu_pwr_mode {
+        MX3_RUN,
+        MX3_WAIT,
+        MX3_DOZE,
+        MX3_SLEEP,
+};
+
+extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
 extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 6e192c4a391..8ddda365f1a 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -24,7 +24,7 @@
 #define UART_PADDR      MX51_UART1_BASE_ADDR
 #elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
 #define UART_PADDR      MX53_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX6Q_UART)
+#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
 #define UART_PADDR      MX6Q_UART4_BASE_ADDR
 #endif
 
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index def9ba53e23..1b2258daa05 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -223,6 +223,8 @@ struct imx_mx2_camera_data {
 struct platform_device *__init imx_add_mx2_camera(
                 const struct imx_mx2_camera_data *data,
                 const struct mx2_camera_platform_data *pdata);
+struct platform_device *__init imx_add_mx2_emmaprp(
+                const struct imx_mx2_camera_data *data);
 
 #include <mach/mxc_ehci.h>
 struct imx_mxc_ehci_data {
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index 233d0a5e2d6..1b9080385b4 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -60,8 +60,7 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan)
 
 static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
 {
-        return !strcmp(dev_name(chan->device->dev), "imx31-sdma") ||
-                !strcmp(dev_name(chan->device->dev), "imx35-sdma") ||
+        return strstr(dev_name(chan->device->dev), "sdma") ||
                 !strcmp(dev_name(chan->device->dev), "imx-dma");
 }
 
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
deleted file mode 100644
index def5d30cb67..00000000000
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
- *  Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f0726d48df2..c61ec0fc10d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -139,15 +139,15 @@
 #define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
@@ -192,54 +192,54 @@
 #define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
@@ -468,11 +468,11 @@
 #define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16           IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_E__LD16           IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17           IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__LD17           IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
deleted file mode 100644
index 13ad0df2e86..00000000000
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_MXC_SYSTEM_H__
-#define __ASM_ARCH_MXC_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index e032717f7d0..c0cab2270dd 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -132,7 +132,7 @@ int pwm_enable(struct pwm_device *pwm)
         int rc = 0;
 
         if (!pwm->clk_enabled) {
-                rc = clk_enable(pwm->clk);
+                rc = clk_prepare_enable(pwm->clk);
                 if (!rc)
                         pwm->clk_enabled = 1;
         }
@@ -145,7 +145,7 @@ void pwm_disable(struct pwm_device *pwm)
         writel(0, pwm->mmio_base + MX3_PWMCR);
 
         if (pwm->clk_enabled) {
-                clk_disable(pwm->clk);
+                clk_disable_unprepare(pwm->clk);
                 pwm->clk_enabled = 0;
         }
 }
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index c195d6d04d1..1996c3e3b8f 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -48,7 +48,7 @@ void mxc_restart(char mode, const char *cmd)
 
                 clk = clk_get_sys("imx2-wdt.0", NULL);
                 if (!IS_ERR(clk))
-                        clk_enable(clk);
+                        clk_prepare_enable(clk);
                 wcr_enable = (1 << 2);
         }
 
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 1c96cdb4c35..7daf7c9a413 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -283,7 +283,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
         uint32_t tctl_val;
 
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
 
         timer_base = base;
 
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 6508e7694a4..582641f3dc0 100644
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,9 +1,7 @@
 #ifndef __PLAT_MTU_H
 #define __PLAT_MTU_H
 
-/* should be set by the platform code */
-extern void __iomem *mtu_base;
-
+void nmdk_timer_init(void __iomem *base);
 void nmdk_clkevt_reset(void);
 void nmdk_clksrc_reset(void);
 
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ad1b45b605a..9222e5522a4 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -21,12 +21,6 @@
 #include <asm/sched_clock.h>
 
 /*
- * Guaranteed runtime conversion range in seconds for
- * the clocksource and clockevent.
- */
-#define MTU_MIN_RANGE 4
-
-/*
  * The MTU device hosts four different counters, with 4 set of
  * registers. These are register names.
  */
@@ -66,12 +60,11 @@
 #define MTU_PCELL2      0xff8
 #define MTU_PCELL3      0xffC
 
+static void __iomem *mtu_base;
 static bool clkevt_periodic;
 static u32 clk_prescale;
 static u32 nmdk_cycle;          /* write-once */
 
-void __iomem *mtu_base; /* Assigned by machine code */
-
 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
 /*
  * Override the global weak sched_clock symbol with this
@@ -103,7 +96,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
 void nmdk_clkevt_reset(void)
 {
         if (clkevt_periodic) {
-
                 /* Timer: configure load and background-load, and fire it up */
                 writel(nmdk_cycle, mtu_base + MTU_LR(1));
                 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
@@ -121,7 +113,6 @@ void nmdk_clkevt_reset(void)
 static void nmdk_clkevt_mode(enum clock_event_mode mode,
                              struct clock_event_device *dev)
 {
-
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 clkevt_periodic = true;
@@ -183,15 +174,16 @@ void nmdk_clksrc_reset(void)
                mtu_base + MTU_CR(0));
 }
 
-void __init nmdk_timer_init(void)
+void __init nmdk_timer_init(void __iomem *base)
 {
         unsigned long rate;
         struct clk *clk0;
 
+        mtu_base = base;
         clk0 = clk_get_sys("mtu0", NULL);
         BUG_ON(IS_ERR(clk0));
-
-        clk_enable(clk0);
+        BUG_ON(clk_prepare(clk0) < 0);
+        BUG_ON(clk_enable(clk0) < 0);
 
         /*
          * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
@@ -224,17 +216,8 @@ void __init nmdk_timer_init(void)
         setup_sched_clock(nomadik_read_sched_clock, 32, rate);
 #endif
 
-        /* Timer 1 is used for events */
-
-        clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
-
-        nmdk_clkevt.max_delta_ns =
-                clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
-        nmdk_clkevt.min_delta_ns =
-                clockevent_delta2ns(0x00000002, &nmdk_clkevt);
-        nmdk_clkevt.cpumask     = cpumask_of(0);
-
-        /* Register irq and clockevents */
+        /* Timer 1 is used for events, register irq and clockevents */
         setup_irq(IRQ_MTU0, &nmdk_timer_irq);
-        clockevents_register_device(&nmdk_clkevt);
+        nmdk_clkevt.cpumask = cpumask_of(0);
+        clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
 }
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 8f81503a4df..ce1e9b96ba1 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -14,6 +14,7 @@ config ARCH_OMAP1
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
         select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
         select HAVE_IDE
         select NEED_MACH_MEMORY_H
         help
@@ -24,6 +25,8 @@ config ARCH_OMAP2PLUS
         select CLKDEV_LOOKUP
         select GENERIC_IRQ_CHIP
         select OMAP_DM_TIMER
+        select USE_OF
+        select PROC_DEVICETREE if PROC_FS
         help
           "Systems based on OMAP2, OMAP3 or OMAP4"
 
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 567e4b54f24..56b6f8b7053 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -20,7 +20,6 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 #include <linux/cpufreq.h>
-#include <linux/debugfs.h>
 #include <linux/io.h>
 
 #include <plat/clock.h>
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5f0f2292b7f..5068fe5a691 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -21,6 +21,7 @@
 
 #include <asm/sched_clock.h>
 
+#include <plat/hardware.h>
 #include <plat/common.h>
 #include <plat/board.h>
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index dbb10497d2a..ecdb3da0dea 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -163,6 +163,8 @@ static inline void set_gdma_dev(int req, int dev)
 }
 #else
 #define set_gdma_dev(req, dev)  do {} while (0)
+#define omap_readl(reg)         0
+#define omap_writel(val, reg)   do {} while (0)
 #endif
 
 void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -2124,7 +2126,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
 
 static struct platform_driver omap_system_dma_driver = {
         .probe          = omap_system_dma_probe,
-        .remove         = omap_system_dma_remove,
+        .remove         = __devexit_p(omap_system_dma_remove),
         .driver         = {
                 .name   = "omap_dma_system"
         },
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index af3b92be845..652139c0339 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,8 @@
 
 #include <plat/dmtimer.h>
 
+#include <mach/hardware.h>
+
 static LIST_HEAD(omap_timer_list);
 static DEFINE_SPINLOCK(dm_timer_lock);
 
@@ -80,9 +82,9 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
 
 static void omap_timer_restore_context(struct omap_dm_timer *timer)
 {
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
-                                timer->context.tiocp_cfg);
-        if (timer->revision > 1)
+        __raw_writel(timer->context.tiocp_cfg,
+                        timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
+        if (timer->revision == 1)
                 __raw_writel(timer->context.tistat, timer->sys_stat);
 
         __raw_writel(timer->context.tisr, timer->irq_stat);
@@ -357,6 +359,19 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
 
         __omap_dm_timer_stop(timer, timer->posted, rate);
 
+        if (timer->loses_context && timer->get_context_loss_count)
+                timer->ctx_loss_count =
+                        timer->get_context_loss_count(&timer->pdev->dev);
+
+        /*
+         * Since the register values are computed and written within
+         * __omap_dm_timer_stop, we need to use read to retrieve the
+         * context.
+         */
+        timer->context.tclr =
+                        omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+        timer->context.tisr = __raw_readl(timer->irq_stat);
+        omap_dm_timer_disable(timer);
         return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906..ad6f865d1f1 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
@@ -28,33 +28,8 @@
 
 #if defined (CONFIG_MACH_AMS_DELTA)
 
-#define AMS_DELTA_LATCH1_PHYS           0x01000000
-#define AMS_DELTA_LATCH1_VIRT           0xEA000000
-#define AMS_DELTA_MODEM_PHYS            0x04000000
-#define AMS_DELTA_MODEM_VIRT            0xEB000000
-#define AMS_DELTA_LATCH2_PHYS           0x08000000
-#define AMS_DELTA_LATCH2_VIRT           0xEC000000
-
-#define AMS_DELTA_LATCH1_LED_CAMERA     0x01
-#define AMS_DELTA_LATCH1_LED_ADVERT     0x02
-#define AMS_DELTA_LATCH1_LED_EMAIL      0x04
-#define AMS_DELTA_LATCH1_LED_HANDSFREE  0x08
-#define AMS_DELTA_LATCH1_LED_VOICEMAIL  0x10
-#define AMS_DELTA_LATCH1_LED_VOICE      0x20
-
-#define AMS_DELTA_LATCH2_LCD_VBLEN      0x0001
-#define AMS_DELTA_LATCH2_LCD_NDISP      0x0002
-#define AMS_DELTA_LATCH2_NAND_NCE       0x0004
-#define AMS_DELTA_LATCH2_NAND_NRE       0x0008
-#define AMS_DELTA_LATCH2_NAND_NWP       0x0010
-#define AMS_DELTA_LATCH2_NAND_NWE       0x0020
-#define AMS_DELTA_LATCH2_NAND_ALE       0x0040
-#define AMS_DELTA_LATCH2_NAND_CLE       0x0080
-#define AMD_DELTA_LATCH2_KEYBRD_PWR     0x0100
-#define AMD_DELTA_LATCH2_KEYBRD_DATA    0x0200
 #define AMD_DELTA_LATCH2_SCARD_RSTIN    0x0400
 #define AMD_DELTA_LATCH2_SCARD_CMDVCC   0x0800
-#define AMS_DELTA_LATCH2_MODEM_NRESET   0x1000
 #define AMS_DELTA_LATCH2_MODEM_CODEC    0x2000
 
 #define AMS_DELTA_GPIO_PIN_KEYBRD_DATA  0
@@ -66,9 +41,29 @@
 #define AMS_DELTA_GPIO_PIN_CONFIG       11
 #define AMS_DELTA_GPIO_PIN_NAND_RB      12
 
+#define AMS_DELTA_GPIO_PIN_LCD_VBLEN            240
+#define AMS_DELTA_GPIO_PIN_LCD_NDISP            241
+#define AMS_DELTA_GPIO_PIN_NAND_NCE             242
+#define AMS_DELTA_GPIO_PIN_NAND_NRE             243
+#define AMS_DELTA_GPIO_PIN_NAND_NWP             244
+#define AMS_DELTA_GPIO_PIN_NAND_NWE             245
+#define AMS_DELTA_GPIO_PIN_NAND_ALE             246
+#define AMS_DELTA_GPIO_PIN_NAND_CLE             247
+#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR           248
+#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT       249
+#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN          250
+#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC         251
+#define AMS_DELTA_GPIO_PIN_MODEM_NRESET         252
+#define AMS_DELTA_GPIO_PIN_MODEM_CODEC          253
+
+#define AMS_DELTA_LATCH2_GPIO_BASE      AMS_DELTA_GPIO_PIN_LCD_VBLEN
+#define AMS_DELTA_LATCH2_NGPIO          16
+
 #ifndef __ASSEMBLY__
-void ams_delta_latch1_write(u8 mask, u8 value);
-void ams_delta_latch2_write(u16 mask, u16 value);
+void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value);
+#define ams_delta_latch2_write(mask, value) \
+        ams_delta_latch_write(AMS_DELTA_LATCH2_GPIO_BASE, \
+                        AMS_DELTA_LATCH2_NGPIO, (mask), (value))
 #endif
 
 #endif /* CONFIG_MACH_AMS_DELTA */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 6b51086fce1..dc6a86bf217 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -250,7 +250,6 @@ IS_AM_SUBCLASS(335x, 0x335)
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
- * cpu_is_omap4430():   True for OMAP4430
  * cpu_is_omap3505():   True for OMAP3505
  * cpu_is_omap3517():   True for OMAP3517
  */
@@ -299,7 +298,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap3505()               0
 #define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
-#define cpu_is_omap4430()               0
 #define cpu_is_omap3630()               0
 
 /*
@@ -451,7 +449,12 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP447X_CLASS          0x44700044
 #define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
 
-void omap2_check_revision(void);
+void omap2xxx_check_revision(void);
+void omap3xxx_check_revision(void);
+void omap4xxx_check_revision(void);
+void omap3xxx_check_features(void);
+void ti81xx_check_features(void);
+void omap4xxx_check_features(void);
 
 /*
  * Runtime detection of OMAP3 features
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0aed0..b8a96c6a1a3 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -162,13 +162,6 @@
                                  IH_MPUIO_BASE + ((nr) & 0x0f) : \
                                  IH_GPIO_BASE + (nr))
 
-#define METHOD_MPUIO            0
-#define METHOD_GPIO_1510        1
-#define METHOD_GPIO_1610        2
-#define METHOD_GPIO_7XX         3
-#define METHOD_GPIO_24XX        5
-#define METHOD_GPIO_44XX        6
-
 struct omap_gpio_dev_attr {
         int bank_width;         /* GPIO bank width */
         bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs {
         u16 irqstatus;
         u16 irqstatus2;
         u16 irqenable;
+        u16 irqenable2;
         u16 set_irqenable;
         u16 clr_irqenable;
         u16 debounce;
         u16 debounce_en;
+        u16 ctrl;
+        u16 wkup_en;
+        u16 leveldetect0;
+        u16 leveldetect1;
+        u16 risingdetect;
+        u16 fallingdetect;
+        u16 irqctrl;
+        u16 edgectrl1;
+        u16 edgectrl2;
+        u16 pinctrl;
 
         bool irqenable_inv;
 };
@@ -198,45 +202,30 @@ struct omap_gpio_platform_data {
         int bank_width;         /* GPIO bank width */
         int bank_stride;        /* Only needed for omap1 MPUIO */
         bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
+        bool loses_context;     /* whether the bank would ever lose context */
+        bool is_mpuio;          /* whether the bank is of type MPUIO */
+        u32 non_wakeup_gpios;
 
         struct omap_gpio_reg_offs *regs;
-};
 
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-extern int gpio_bank_count;
+        /* Return context loss count due to PM states changing */
+        int (*get_context_loss_count)(struct device *dev);
+};
 
 extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-extern void omap_gpio_save_context(void);
-extern void omap_gpio_restore_context(void);
 /*-------------------------------------------------------------------------*/
 
-/* Wrappers for "new style" GPIO calls, using the new infrastructure
+/*
+ * Wrappers for "new style" GPIO calls, using the new infrastructure
  * which lets us plug in FPGA, I2C, and other implementations.
- * *
+ *
  * The original OMAP-specific calls should eventually be removed.
  */
 
 #include <linux/errno.h>
 #include <asm-generic/gpio.h>
 
-static inline int irq_to_gpio(unsigned irq)
-{
-        int tmp;
-
-        /* omap1 SOC mpuio */
-        if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
-                return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
-
-        /* SOC gpio */
-        tmp = irq - IH_GPIO_BASE;
-        if (tmp < OMAP_MAX_GPIO_LINES)
-                return tmp;
-
-        /* we don't supply reverse mappings for non-SOC gpios */
-        return -EIO;
-}
-
 #endif
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c..537b05ae1f5 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -43,6 +43,12 @@
 #endif
 #include <plat/serial.h>
 
+#ifdef __ASSEMBLER__
+#define IOMEM(x)                (x)
+#else
+#define IOMEM(x)                ((void __force __iomem *)(x))
+#endif
+
 /*
  * ---------------------------------------------------------------------------
  * Common definitions for all OMAP processors
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 793ce9d5329..a6b21eddb21 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -12,6 +12,8 @@
 
 #ifndef CONFIG_ARCH_OMAP1
 #warning Please update the board to use matrix-keypad driver
+#define omap_readw(reg)         0
+#define omap_writew(val, reg)   do {} while (0)
 #endif
 #include <linux/input/matrix_keypad.h>
 
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 3d51b18131c..a357eb26bd2 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -18,9 +18,6 @@ struct omap2_mcspi_dev_attr {
 
 struct omap2_mcspi_device_config {
         unsigned turbo_mode:1;
-
-        /* Do we want one channel enabled at the same time? */
-        unsigned single_channel:1;
 };
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 51423d2727a..4327b2c90c3 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,7 +36,7 @@
 
 #include <plat/omap_hwmod.h>
 
-extern struct device omap_device_parent;
+extern struct dev_pm_domain omap_device_pm_domain;
 
 /* omap_device._state values */
 #define OMAP_DEVICE_STATE_UNKNOWN       0
@@ -100,6 +100,13 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_device_pm_latency *pm_lats,
                                          int pm_lats_cnt, int is_early_device);
 
+struct omap_device *omap_device_alloc(struct platform_device *pdev,
+                                      struct omap_hwmod **ohs, int oh_cnt,
+                                      struct omap_device_pm_latency *pm_lats,
+                                      int pm_lats_cnt);
+void omap_device_delete(struct omap_device *od);
+int omap_device_register(struct platform_device *pdev);
+
 void __iomem *omap_device_get_rt_va(struct omap_device *od);
 struct device *omap_device_get_by_hwmod_name(const char *oh_name);
 
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 647010109af..9e8e63d52aa 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -484,7 +484,6 @@ struct omap_hwmod_class {
  * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
  * @opt_clks: other device clocks that drivers can request (0..*)
- * @vdd_name: voltage domain name
  * @voltdm: pointer to voltage domain (filled in at runtime)
  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
@@ -528,7 +527,6 @@ struct omap_hwmod {
         struct omap_hwmod_opt_clk       *opt_clks;
         char                            *clkdm_name;
         struct clockdomain              *clkdm;
-        char                            *vdd_name;
         struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
         struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
         void                            *dev_attr;
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
new file mode 100644
index 00000000000..b10eac89e2e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/remoteproc.h
@@ -0,0 +1,57 @@
+/*
+ * Remote Processor - omap-specific bits
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _PLAT_REMOTEPROC_H
+#define _PLAT_REMOTEPROC_H
+
+struct rproc_ops;
+struct platform_device;
+
+/*
+ * struct omap_rproc_pdata - omap remoteproc's platform data
+ * @name: the remoteproc's name
+ * @oh_name: omap hwmod device
+ * @oh_name_opt: optional, secondary omap hwmod device
+ * @firmware: name of firmware file to load
+ * @mbox_name: name of omap mailbox device to use with this rproc
+ * @ops: start/stop rproc handlers
+ * @device_enable: omap-specific handler for enabling a device
+ * @device_shutdown: omap-specific handler for shutting down a device
+ */
+struct omap_rproc_pdata {
+        const char *name;
+        const char *oh_name;
+        const char *oh_name_opt;
+        const char *firmware;
+        const char *mbox_name;
+        const struct rproc_ops *ops;
+        int (*device_enable) (struct platform_device *pdev);
+        int (*device_shutdown) (struct platform_device *pdev);
+};
+
+#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
+
+void __init omap_rproc_reserve_cma(void);
+
+#else
+
+void __init omap_rproc_reserve_cma(void)
+{
+}
+
+#endif
+
+#endif /* _PLAT_REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 198d1e6a4a6..b073e5f2b19 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -110,7 +110,6 @@ struct omap_board_data;
 struct omap_uart_port_info;
 
 extern void omap_serial_init(void);
-extern int omap_uart_can_sleep(void);
 extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
 extern void omap_serial_init_port(struct omap_board_data *bdata,
                 struct omap_uart_port_info *platform_data);
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 75aa1b2bef5..227ae265755 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -101,4 +101,5 @@ static inline void omap_push_sram_idle(void) {}
 #else
 #define OMAP4_SRAM_PA           0x40300000
 #endif
+#define AM33XX_SRAM_PA          0x40300000
 #endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
deleted file mode 100644
index 8e5ebd74b12..00000000000
--- a/arch/arm/plat-omap/include/plat/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copied from arch/arm/mach-sa1100/include/mach/system.h
- * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9..1b4b2da8620 100644
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
@@ -84,23 +84,6 @@
 #define EMIFS_CCS(n)            (EMIFS_CS0_CONFIG + (4 * (n)))
 #define EMIFS_ACS(n)            (EMIFS_ACS0 + (4 * (n)))
 
-/* Almost all documentation for chip and board memory maps assumes
- * BM is clear.  Most devel boards have a switch to control booting
- * from NOR flash (using external chipselect 3) rather than mask ROM,
- * which uses BM to interchange the physical CS0 and CS3 addresses.
- */
-static inline u32 omap_cs0_phys(void)
-{
-        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
-                        ?  OMAP_CS3_PHYS : 0;
-}
-
-static inline u32 omap_cs3_phys(void)
-{
-        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
-                        ? 0 : OMAP_CS3_PHYS;
-}
-
 #endif  /* __ASSEMBLER__ */
 
 #endif  /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 6ee90495ca4..cc3f11ba7a9 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -160,6 +160,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_OMAP3(3, igep0020);
                 DEBUG_LL_OMAP3(3, igep0030);
                 DEBUG_LL_OMAP3(3, nokia_rm680);
+                DEBUG_LL_OMAP3(3, nokia_rm696);
                 DEBUG_LL_OMAP3(3, nokia_rx51);
                 DEBUG_LL_OMAP3(3, omap3517evm);
                 DEBUG_LL_OMAP3(3, omap3_beagle);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index dc864b580da..d0fc9f4dc15 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,6 +3,7 @@
 #ifndef __ASM_ARCH_OMAP_USB_H
 #define __ASM_ARCH_OMAP_USB_H
 
+#include <linux/io.h>
 #include <linux/usb/musb.h>
 #include <plat/board.h>
 
@@ -105,6 +106,46 @@ extern int omap4430_phy_set_clk(struct device *dev, int on);
 extern int omap4430_phy_init(struct device *dev);
 extern int omap4430_phy_exit(struct device *dev);
 extern int omap4430_phy_suspend(struct device *dev, int suspend);
+
+/*
+ * NOTE: Please update omap USB drivers to use ioremap + read/write
+ */
+
+#define OMAP2_L4_IO_OFFSET      0xb2000000
+#define IOMEM(x)                ((void __force __iomem *)(x))
+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
+
+static inline u8 omap_readb(u32 pa)
+{
+        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline u16 omap_readw(u32 pa)
+{
+        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline u32 omap_readl(u32 pa)
+{
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline void omap_writeb(u8 v, u32 pa)
+{
+        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
+
+static inline void omap_writew(u16 v, u32 pa)
+{
+        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline void omap_writel(u32 v, u32 pa)
+{
+        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
 #endif
 
 extern void am35x_musb_reset(void);
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ad80112c227..ad32621aa52 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -307,7 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
         if (!--mbox->use_count) {
                 free_irq(mbox->irq, mbox);
                 tasklet_kill(&mbox->txq->tasklet);
-        flush_work_sync(&mbox->rxq->work);
+                flush_work_sync(&mbox->rxq->work);
                 mbox_queue_free(mbox->txq);
                 mbox_queue_free(mbox->rxq);
         }
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 976fc801029..cff8712122b 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -27,6 +27,10 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+
+#include <asm/system.h>
+
+#include <plat/cpu.h>
 #include <plat/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 3dc3801aace..5a97b4d98d4 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -319,7 +319,7 @@ int omap_pm_get_dev_context_loss_count(struct device *dev)
         if (WARN_ON(!dev))
                 return -ENODEV;
 
-        if (dev->parent == &omap_device_parent) {
+        if (dev->pm_domain == &omap_device_pm_domain) {
                 count = omap_device_get_context_loss_count(pdev);
         } else {
                 WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index e8d98693d2d..d50cbc6385b 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,3 +1,4 @@
+
 /*
  * omap_device implementation
  *
@@ -97,14 +98,7 @@
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
 
-static int omap_device_register(struct platform_device *pdev);
 static int omap_early_device_register(struct platform_device *pdev);
-static struct omap_device *omap_device_alloc(struct platform_device *pdev,
-                                      struct omap_hwmod **ohs, int oh_cnt,
-                                      struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt);
-static void omap_device_delete(struct omap_device *od);
-
 
 static struct omap_device_pm_latency omap_default_latency[] = {
         {
@@ -320,8 +314,6 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
 }
 
 
-static struct dev_pm_domain omap_device_pm_domain;
-
 /**
  * omap_device_build_from_dt - build an omap_device with multiple hwmods
  * @pdev_name: name of the platform_device driver to use
@@ -348,7 +340,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
 
         oh_cnt = of_property_count_strings(node, "ti,hwmods");
         if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
-                dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
+                dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n");
                 return -ENODEV;
         }
 
@@ -509,7 +501,7 @@ static int omap_device_fill_resources(struct omap_device *od,
  *
  * Returns an struct omap_device pointer or ERR_PTR() on error;
  */
-static struct omap_device *omap_device_alloc(struct platform_device *pdev,
+struct omap_device *omap_device_alloc(struct platform_device *pdev,
                                         struct omap_hwmod **ohs, int oh_cnt,
                                         struct omap_device_pm_latency *pm_lats,
                                         int pm_lats_cnt)
@@ -591,7 +583,7 @@ oda_exit1:
         return ERR_PTR(ret);
 }
 
-static void omap_device_delete(struct omap_device *od)
+void omap_device_delete(struct omap_device *od)
 {
         if (!od)
                 return;
@@ -619,7 +611,7 @@ static void omap_device_delete(struct omap_device *od)
  * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
  * passes along the return value of omap_device_build_ss().
  */
-struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
+struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
@@ -652,7 +644,7 @@ struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
  * platform_device record.  Returns an ERR_PTR() on error, or passes
  * along the return value of omap_device_register().
  */
-struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **ohs, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
@@ -717,7 +709,7 @@ odbs_exit:
  * platform_early_add_device() on the underlying platform_device.
  * Returns 0 by default.
  */
-static int omap_early_device_register(struct platform_device *pdev)
+static int __init omap_early_device_register(struct platform_device *pdev)
 {
         struct platform_device *devices[1];
 
@@ -762,14 +754,12 @@ static int _od_suspend_noirq(struct device *dev)
         struct omap_device *od = to_omap_device(pdev);
         int ret;
 
-        if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
-                return pm_generic_suspend_noirq(dev);
-
         ret = pm_generic_suspend_noirq(dev);
 
         if (!ret && !pm_runtime_status_suspended(dev)) {
                 if (pm_generic_runtime_suspend(dev) == 0) {
-                        omap_device_idle(pdev);
+                        if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+                                omap_device_idle(pdev);
                         od->flags |= OMAP_DEVICE_SUSPENDED;
                 }
         }
@@ -782,13 +772,11 @@ static int _od_resume_noirq(struct device *dev)
         struct platform_device *pdev = to_platform_device(dev);
         struct omap_device *od = to_omap_device(pdev);
 
-        if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
-                return pm_generic_resume_noirq(dev);
-
         if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
             !pm_runtime_status_suspended(dev)) {
                 od->flags &= ~OMAP_DEVICE_SUSPENDED;
-                omap_device_enable(pdev);
+                if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+                        omap_device_enable(pdev);
                 pm_generic_runtime_resume(dev);
         }
 
@@ -799,7 +787,7 @@ static int _od_resume_noirq(struct device *dev)
 #define _od_resume_noirq NULL
 #endif
 
-static struct dev_pm_domain omap_device_pm_domain = {
+struct dev_pm_domain omap_device_pm_domain = {
         .ops = {
                 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
                                    _od_runtime_idle)
@@ -817,11 +805,10 @@ static struct dev_pm_domain omap_device_pm_domain = {
  * platform_device_register() on the underlying platform_device.
  * Returns the return value of platform_device_register().
  */
-static int omap_device_register(struct platform_device *pdev)
+int omap_device_register(struct platform_device *pdev)
 {
         pr_debug("omap_device: %s: registering\n", pdev->name);
 
-        pdev->dev.parent = &omap_device_parent;
         pdev->dev.pm_domain = &omap_device_pm_domain;
         return platform_device_add(pdev);
 }
@@ -1130,11 +1117,6 @@ int omap_device_enable_clocks(struct omap_device *od)
         return 0;
 }
 
-struct device omap_device_parent = {
-        .init_name      = "omap",
-        .parent         = &platform_bus,
-};
-
 static struct notifier_block platform_nb = {
         .notifier_call = _omap_device_notifier_call,
 };
@@ -1142,6 +1124,6 @@ static struct notifier_block platform_nb = {
 static int __init omap_device_init(void)
 {
         bus_register_notifier(&platform_bus_type, &platform_nb);
-        return device_register(&omap_device_parent);
+        return 0;
 }
 core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4243bdcc87b..eec98afa0f8 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -31,11 +31,10 @@
 
 #include "sram.h"
 
-/* XXX These "sideways" includes are a sign that something is wrong */
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-# include "../mach-omap2/prm2xxx_3xxx.h"
-# include "../mach-omap2/sdrc.h"
-#endif
+/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
+#include "../mach-omap2/iomap.h"
+#include "../mach-omap2/prm2xxx_3xxx.h"
+#include "../mach-omap2/sdrc.h"
 
 #define OMAP1_SRAM_PA           0x20000000
 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
@@ -86,7 +85,7 @@ static int is_sram_locked(void)
                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
                 }
-                if (cpu_is_omap34xx()) {
+                if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
@@ -124,7 +123,10 @@ static void __init omap_detect_sram(void)
                                 omap_sram_size = 0x800; /* 2K */
                         }
                 } else {
-                        if (cpu_is_omap34xx()) {
+                        if (cpu_is_am33xx()) {
+                                omap_sram_start = AM33XX_SRAM_PA;
+                                omap_sram_size = 0x10000; /* 64K */
+                        } else if (cpu_is_omap34xx()) {
                                 omap_sram_start = OMAP3_SRAM_PA;
                                 omap_sram_size = 0x10000; /* 64K */
                         } else if (cpu_is_omap44xx()) {
@@ -368,6 +370,11 @@ static inline int omap34xx_sram_init(void)
         return 0;
 }
 
+static inline int am33xx_sram_init(void)
+{
+        return 0;
+}
+
 int __init omap_sram_init(void)
 {
         omap_detect_sram();
@@ -379,6 +386,8 @@ int __init omap_sram_init(void)
                 omap242x_sram_init();
         else if (cpu_is_omap2430())
                 omap243x_sram_init();
+        else if (cpu_is_am33xx())
+                am33xx_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
 
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index f3570884883..d2bbfd1cb0b 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -29,6 +29,10 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 
+#include <mach/hardware.h>
+
+#include "../mach-omap2/common.h"
+
 #ifdef  CONFIG_ARCH_OMAP_OTG
 
 void __init
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 089899a7db7..74daf5ed143 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -21,6 +21,7 @@
 #include <plat/orion_wdt.h>
 #include <plat/mv_xor.h>
 #include <plat/ehci-orion.h>
+#include <mach/bridge-regs.h>
 
 /* Fill in the resources structure and link it into the platform
    device structure. There is always a memory region, and nearly
@@ -568,13 +569,17 @@ void __init orion_spi_1_init(unsigned long mapbase,
  ****************************************************************************/
 static struct orion_wdt_platform_data orion_wdt_data;
 
+static struct resource orion_wdt_resource =
+                DEFINE_RES_MEM(TIMER_VIRT_BASE, 0x28);
+
 static struct platform_device orion_wdt_device = {
         .name           = "orion_wdt",
         .id             = -1,
         .dev            = {
                 .platform_data  = &orion_wdt_data,
         },
-        .num_resources  = 0,
+        .resource       = &orion_wdt_resource,
+        .num_resources  = 1,
 };
 
 void __init orion_wdt_init(unsigned long tclk)
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
index 885f8abd927..d6a55bd2e57 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/arch/arm/plat-orion/include/plat/audio.h
@@ -2,7 +2,6 @@
 #define __PLAT_AUDIO_H
 
 struct kirkwood_asoc_platform_data {
-        u32 tclk;
         int burst;
 };
 #endif
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index d8973ac46bc..21bf6adb919 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -4,7 +4,7 @@
 
 config PLAT_S3C24XX
         bool
-        depends on ARCH_S3C2410
+        depends on ARCH_S3C24XX
         default y
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
@@ -44,12 +44,6 @@ config S3C2410_CLOCK
           Clock code for the S3C2410, and similar processors which
           is currently includes the S3C2410, S3C2440, S3C2442.
 
-config S3C2443_CLOCK
-        bool
-        help
-          Clock code for the S3C2443 and similar processors, which includes
-          the S3C2416 and S3C2450.
-
 config S3C24XX_DCLK
         bool
         help
@@ -76,15 +70,9 @@ config S3C24XX_GPIO_EXTRA128
           Add an extra 128 gpio numbers to the available GPIO pool. This is
           available for boards that need extra gpios for external devices.
 
-config PM_SIMTEC
-        bool
-        help
-          Common power management code for systems that are
-          compatible with the Simtec style of power management
-
-config S3C2410_DMA
+config S3C24XX_DMA
         bool "S3C2410 DMA support"
-        depends on ARCH_S3C2410
+        depends on ARCH_S3C24XX
         select S3C_DMA
         help
           S3C2410 DMA support. This is needed for drivers like sound which
@@ -93,31 +81,11 @@ config S3C2410_DMA
 
 config S3C2410_DMA_DEBUG
         bool "S3C2410 DMA support debug"
-        depends on ARCH_S3C2410 && S3C2410_DMA
+        depends on ARCH_S3C24XX && S3C2410_DMA
         help
           Enable debugging output for the DMA code. This option sends info
           to the kernel log, at priority KERN_DEBUG.
 
-# SPI default pin configuration code
-
-config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
-        bool
-        help
-          SPI GPIO configuration code for BUS0 when connected to
-          GPE11, GPE12 and GPE13.
-
-config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
-        bool
-        help
-          SPI GPIO configuration code for BUS 1 when connected to
-          GPG5, GPG6 and GPG7.
-
-config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10
-        bool
-        help
-          SPI GPIO configuration code for BUS 1 when connected to
-          GPD8, GPD9 and GPD10.
-
 # common code for s3c24xx based machines, such as the SMDKs.
 
 # cpu frequency items common between s3c2410 and s3c2440/s3c2442
@@ -145,21 +113,4 @@ config S3C2412_IOTIMING
           Intel node to select io timing code that is common to the s3c2412
           and the s3c2443.
 
-config MACH_SMDK
-        bool
-        help
-          Common machine code for SMDK2410 and SMDK2440
-
-config S3C24XX_SIMTEC_AUDIO
-        bool
-        depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
-        default y
-        help
-          Add audio devices for common Simtec S3C24XX boards
-
-config S3C2410_SETUP_TS
-        bool
-        help
-          Compile in platform device definition for Samsung TouchScreen.
-
 endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index b2b01125de6..2467b800cc7 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -23,28 +23,11 @@ obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
 
 # Architecture dependent builds
 
-obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
-obj-$(CONFIG_S3C2443_CLOCK)     += s3c2443-clock.o
-obj-$(CONFIG_S3C2410_DMA)       += dma.o
+obj-$(CONFIG_S3C24XX_DMA)       += dma.o
 obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
 obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
-
-# device specific setup and/or initialisation
-obj-$(CONFIG_ARCH_S3C2410)      += setup-i2c.o
-obj-$(CONFIG_S3C2410_SETUP_TS)  += setup-ts.o
-
-# SPI gpio central GPIO functions
-
-obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
-obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7)    += spi-bus1-gpg5_6_7.o
-obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10)   += spi-bus1-gpd8_9_10.o
-
-# machine common support
-
-obj-$(CONFIG_MACH_SMDK)         += common-smdk.o
-obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)      += simtec-audio.o
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index ded64318fcc..0db73ae646b 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -32,6 +32,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <mach/regs-clock.h>
 #include <asm/irq.h>
 #include <asm/cacheflush.h>
 #include <asm/system_info.h>
@@ -191,8 +192,34 @@ static unsigned long s3c24xx_read_idcode_v4(void)
         return __raw_readl(S3C2410_GSTATUS1);
 }
 
+static void s3c24xx_default_idle(void)
+{
+        unsigned long tmp;
+        int i;
+
+        /* idle the system by using the idle mode which will wait for an
+         * interrupt to happen before restarting the system.
+         */
+
+        /* Warning: going into idle state upsets jtag scanning */
+
+        __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
+                     S3C2410_CLKCON);
+
+        /* the samsung port seems to do a loop and then unset idle.. */
+        for (i = 0; i < 50; i++)
+                tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
+
+        /* this bit is not cleared on re-start... */
+
+        __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
+                     S3C2410_CLKCON);
+}
+
 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 {
+        arm_pm_idle = s3c24xx_default_idle;
+
         /* initialise the io descriptors we need for initialisation */
         iotable_init(mach_desc, size);
         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
deleted file mode 100644
index 704175b0573..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-
-#include <mach/spi.h>
-#include <mach/regs-gpio.h>
-
-void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
-                                          int enable)
-{
-        if (enable) {
-                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
-                s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
-                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
-                s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
-                s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
-        } else {
-                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
-                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
-                s3c_gpio_setpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE);
-        }
-}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
deleted file mode 100644
index 72457afd625..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-
-#include <mach/spi.h>
-#include <mach/regs-gpio.h>
-
-void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
-                                        int enable)
-{
-
-        printk(KERN_INFO "%s(%d)\n", __func__, enable);
-        if (enable) {
-                s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
-                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
-                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
-                s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
-                s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
-        } else {
-                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
-                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
-                s3c_gpio_setpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
-        }
-}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
deleted file mode 100644
index c3972b645d1..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-
-#include <mach/spi.h>
-#include <mach/regs-gpio.h>
-
-void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
-                                       int enable)
-{
-        if (enable) {
-                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
-                s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
-                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
-                s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
-                s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
-        } else {
-                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
-                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
-                s3c_gpio_setpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE);
-        }
-}
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8167ce66188..96bea320230 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -9,8 +9,8 @@ config PLAT_S5P
         bool
         depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
         default y
-        select ARM_VIC if !ARCH_EXYNOS4
-        select ARM_GIC if ARCH_EXYNOS4
+        select ARM_VIC if !ARCH_EXYNOS
+        select ARM_GIC if ARCH_EXYNOS
         select GIC_NON_BANKED if ARCH_EXYNOS4
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
@@ -40,6 +40,10 @@ config S5P_HRT
         help
           Use the High Resolution timer support
 
+config S5P_DEV_UART
+        def_bool y
+        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+
 config S5P_PM
         bool
         help
@@ -80,6 +84,16 @@ config S5P_DEV_FIMC3
         help
           Compile in platform device definitions for FIMC controller 3
 
+config S5P_DEV_JPEG
+        bool
+        help
+          Compile in platform device definitions for JPEG codec
+
+config S5P_DEV_G2D
+        bool
+        help
+          Compile in platform device definitions for G2D device
+
 config S5P_DEV_FIMD0
         bool
         help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 30d8c3016e6..4bd82413665 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -12,7 +12,6 @@ obj-				:=
 
 # Core files
 
-obj-y                           += dev-uart.o
 obj-y                           += clock.o
 obj-y                           += irq.o
 obj-$(CONFIG_S5P_EXT_INT)       += irq-eint.o
@@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP)		+= sleep.o
 obj-$(CONFIG_S5P_HRT)           += s5p-time.o
 
 # devices
+
+obj-$(CONFIG_S5P_DEV_UART)      += dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)       += dev-mfc.o
 obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 963edea7f7e..f68a9bb1194 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
         .id             = -1,
 };
 
+/* BPLL clock output */
+
+struct clk clk_fout_bpll = {
+        .name           = "fout_bpll",
+        .id             = -1,
+};
+
+/* CPLL clock output */
+
+struct clk clk_fout_cpll = {
+        .name           = "fout_cpll",
+        .id             = -1,
+};
+
 /* MPLL clock output
  * No need .ctrlbit, this is always on
 */
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
         .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
 };
 
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+        [0] = &clk_fin_bpll,
+        [1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll = {
+        .sources        = clk_src_bpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_bpll_list),
+};
+
+/* Possible clock sources for CPLL Mux */
+static struct clk *clk_src_cpll_list[] = {
+        [0] = &clk_fin_cpll,
+        [1] = &clk_fout_cpll,
+};
+
+struct clksrc_sources clk_src_cpll = {
+        .sources        = clk_src_cpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_cpll_list),
+};
+
 /* Possible clock sources for MPLL Mux */
 static struct clk *clk_src_mpll_list[] = {
         [0] = &clk_fin_mpll,
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index c496b359c37..139c050918c 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -200,7 +200,7 @@ static struct irq_chip s5p_irq_vic_eint = {
 #endif
 };
 
-int __init s5p_init_irq_eint(void)
+static int __init s5p_init_irq_eint(void)
 {
         int irq;
 
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 1fdfaa4599c..82c7311017a 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -41,7 +41,7 @@ struct s5p_gpioint_bank {
         void                    (*handler)(unsigned int, struct irq_desc *);
 };
 
-LIST_HEAD(banks);
+static LIST_HEAD(banks);
 
 static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
 {
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
index 327acb3a446..d1bfecae6c9 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow	= 0xffffffffL;
 int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
         unsigned long irqbit;
+        unsigned int irq_rtc_tic, irq_rtc_alarm;
+
+#ifdef CONFIG_ARCH_EXYNOS
+        if (soc_is_exynos5250()) {
+                irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
+                irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
+        } else {
+                irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
+                irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
+        }
+#else
+        irq_rtc_tic = IRQ_RTC_TIC;
+        irq_rtc_alarm = IRQ_RTC_ALARM;
+#endif
+
+        if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
+                irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
 
-        switch (data->irq) {
-        case IRQ_RTC_TIC:
-        case IRQ_RTC_ALARM:
-                irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
                 if (!state)
                         s3c_irqwake_intmask |= irqbit;
                 else
                         s3c_irqwake_intmask &= ~irqbit;
-                break;
-        default:
+        } else {
                 return -ENOENT;
         }
+
         return 0;
 }
 
diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S
index 0fd591bfc9f..006bd01eda0 100644
--- a/arch/arm/plat-s5p/sleep.S
+++ b/arch/arm/plat-s5p/sleep.S
@@ -23,9 +23,18 @@
 */
 
 #include <linux/linkage.h>
-#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
 
-        .text
+/*
+ *       The following code is located into the .data section. This is to
+ *       allow l2x0_regs_phys to be accessed with a relative load while we
+ *       can't rely on any MMU translation. We could have put l2x0_regs_phys
+ *       in the .text section as well, but some setups might insist on it to
+ *       be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
+ */
+        .data
+        .align
 
         /*
          * sleep magic, to allow the bootloader to check for an valid
@@ -39,11 +48,34 @@
          * s3c_cpu_resume
          *
          * resume code entry for bootloader to call
-         *
-         * we must put this code here in the data segment as we have no
-         * other way of restoring the stack pointer after sleep, and we
-         * must not write to the code segment (code is read-only)
          */
 
 ENTRY(s3c_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        adr     r0, l2x0_regs_phys
+        ldr     r0, [r0]
+        ldr     r1, [r0, #L2X0_R_PHY_BASE]
+        ldr     r2, [r1, #L2X0_CTRL]
+        tst     r2, #0x1
+        bne     resume_l2on
+        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
+        str     r2, [r1, #L2X0_AUX_CTRL]
+        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
+        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
+        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
+        str     r2, [r1, #L2X0_PREFETCH_CTRL]
+        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
+        str     r2, [r1, #L2X0_POWER_CTRL]
+        mov     r2, #1
+        str     r2, [r1, #L2X0_CTRL]
+resume_l2on:
+#endif
         b       cpu_resume
+ENDPROC(s3c_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        .globl l2x0_regs_phys
+l2x0_regs_phys:
+        .long   0
+#endif
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 6a2abe67c8b..71553f41001 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -205,7 +205,7 @@ config S3C_DEV_USB_HSOTG
 
 config S3C_DEV_WDT
         bool
-        default y if ARCH_S3C2410
+        default y if ARCH_S3C24XX
         help
           Complie in platform device definition for Watchdog Timer
 
@@ -264,7 +264,7 @@ config SAMSUNG_DEV_KEYPAD
 
 config SAMSUNG_DEV_PWM
         bool
-        default y if ARCH_S3C2410
+        default y if ARCH_S3C24XX
         help
           Compile in platform device definition for PWM Timer
 
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 10f71179071..65c5eca475e 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -84,31 +84,35 @@ static int clk_null_enable(struct clk *clk, int enable)
 
 int clk_enable(struct clk *clk)
 {
+        unsigned long flags;
+
         if (IS_ERR(clk) || clk == NULL)
                 return -EINVAL;
 
         clk_enable(clk->parent);
 
-        spin_lock(&clocks_lock);
+        spin_lock_irqsave(&clocks_lock, flags);
 
         if ((clk->usage++) == 0)
                 (clk->enable)(clk, 1);
 
-        spin_unlock(&clocks_lock);
+        spin_unlock_irqrestore(&clocks_lock, flags);
         return 0;
 }
 
 void clk_disable(struct clk *clk)
 {
+        unsigned long flags;
+
         if (IS_ERR(clk) || clk == NULL)
                 return;
 
-        spin_lock(&clocks_lock);
+        spin_lock_irqsave(&clocks_lock, flags);
 
         if ((--clk->usage) == 0)
                 (clk->enable)(clk, 0);
 
-        spin_unlock(&clocks_lock);
+        spin_unlock_irqrestore(&clocks_lock, flags);
         clk_disable(clk->parent);
 }
 
diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c
index a976c023b28..5f197dcaf10 100644
--- a/arch/arm/plat-samsung/dev-backlight.c
+++ b/arch/arm/plat-samsung/dev-backlight.c
@@ -77,7 +77,7 @@ static struct platform_device samsung_dfl_bl_device __initdata = {
  * @gpio_info:  structure containing GPIO info for PWM timer
  * @bl_data:    structure containing Backlight control data
  */
-void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
+void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
         struct platform_pwm_backlight_data *bl_data)
 {
         int ret = 0;
@@ -115,6 +115,8 @@ void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
                 samsung_bl_data->init = bl_data->init;
         if (bl_data->notify)
                 samsung_bl_data->notify = bl_data->notify;
+        if (bl_data->notify_after)
+                samsung_bl_data->notify_after = bl_data->notify_after;
         if (bl_data->exit)
                 samsung_bl_data->exit = bl_data->exit;
         if (bl_data->check_fb)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index d21d744e4d9..8b928f9bc1c 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -57,6 +57,7 @@
 #include <plat/sdhci.h>
 #include <plat/ts.h>
 #include <plat/udc.h>
+#include <plat/udc-hs.h>
 #include <plat/usb-control.h>
 #include <plat/usb-phy.h>
 #include <plat/regs-iic.h>
@@ -267,6 +268,52 @@ struct platform_device s5p_device_fimc3 = {
 };
 #endif /* CONFIG_S5P_DEV_FIMC3 */
 
+/* G2D */
+
+#ifdef CONFIG_S5P_DEV_G2D
+static struct resource s5p_g2d_resource[] = {
+        [0] = {
+                .start  = S5P_PA_G2D,
+                .end    = S5P_PA_G2D + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_2D,
+                .end    = IRQ_2D,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5p_device_g2d = {
+        .name           = "s5p-g2d",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_g2d_resource),
+        .resource       = s5p_g2d_resource,
+        .dev            = {
+                .dma_mask               = &samsung_device_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+#endif /* CONFIG_S5P_DEV_G2D */
+
+#ifdef CONFIG_S5P_DEV_JPEG
+static struct resource s5p_jpeg_resource[] = {
+        [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
+        [1] = DEFINE_RES_IRQ(IRQ_JPEG),
+};
+
+struct platform_device s5p_device_jpeg = {
+        .name           = "s5p-jpeg",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_jpeg_resource),
+        .resource       = s5p_jpeg_resource,
+        .dev            = {
+                .dma_mask               = &samsung_device_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+#endif /*  CONFIG_S5P_DEV_JPEG */
+
 /* FIMD0 */
 
 #ifdef CONFIG_S5P_DEV_FIMD0
@@ -744,17 +791,6 @@ struct platform_device s3c_device_iis = {
 };
 #endif /* CONFIG_PLAT_S3C24XX */
 
-#ifdef CONFIG_CPU_S3C2440
-struct platform_device s3c2412_device_iis = {
-        .name           = "s3c2412-iis",
-        .id             = -1,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
-#endif /* CONFIG_CPU_S3C2440 */
-
 /* IDE CFCON */
 
 #ifdef CONFIG_SAMSUNG_DEV_IDE
@@ -769,7 +805,7 @@ struct platform_device s3c_device_cfcon = {
         .resource       = s3c_cfcon_resource,
 };
 
-void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
+void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
 {
         s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
                          &s3c_device_cfcon);
@@ -887,7 +923,7 @@ struct platform_device s5p_device_mfc_r = {
 
 #ifdef CONFIG_S5P_DEV_CSIS0
 static struct resource s5p_mipi_csis0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_4K),
+        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
         [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
 };
 
@@ -901,7 +937,7 @@ struct platform_device s5p_device_mipi_csis0 = {
 
 #ifdef CONFIG_S5P_DEV_CSIS1
 static struct resource s5p_mipi_csis1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_4K),
+        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
         [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
 };
 
@@ -1049,7 +1085,7 @@ struct platform_device s3c64xx_device_onenand1 = {
         .resource       = s3c64xx_onenand1_resources,
 };
 
-void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
+void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
 {
         s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
                          &s3c64xx_device_onenand1);
@@ -1078,7 +1114,7 @@ static struct resource s5p_pmu_resource[] = {
         DEFINE_RES_IRQ(IRQ_PMU)
 };
 
-struct platform_device s5p_device_pmu = {
+static struct platform_device s5p_device_pmu = {
         .name           = "arm-pmu",
         .id             = ARM_PMU_DEVICE_CPU,
         .num_resources  = ARRAY_SIZE(s5p_pmu_resource),
@@ -1423,6 +1459,19 @@ struct platform_device s3c_device_usb_hsotg = {
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
 };
+
+void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
+{
+        struct s3c_hsotg_plat *npd;
+
+        npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
+                        &s3c_device_usb_hsotg);
+
+        if (!npd->phy_init)
+                npd->phy_init = s5p_usb_phy_init;
+        if (!npd->phy_exit)
+                npd->phy_exit = s5p_usb_phy_exit;
+}
 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
 
 /* USB High Spped 2.0 Device (Gadget) */
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 0747c77a2fd..301d9c319d0 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -116,7 +116,7 @@ static inline int samsung_dmadev_flush(unsigned ch)
         return dmaengine_terminate_all((struct dma_chan *)ch);
 }
 
-struct samsung_dma_ops dmadev_ops = {
+static struct samsung_dma_ops dmadev_ops = {
         .request        = samsung_dmadev_request,
         .release        = samsung_dmadev_release,
         .prepare        = samsung_dmadev_prepare,
diff --git a/arch/arm/plat-samsung/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
index 5345364e742..376af5286a3 100644
--- a/arch/arm/plat-samsung/include/plat/audio-simtec.h
+++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h
@@ -32,6 +32,3 @@ struct s3c24xx_audio_simtec_pdata {
 
         void    (*startup)(void);
 };
-
-extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
-                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 73c66d4d10f..a62753dc15b 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -79,6 +79,10 @@ extern struct clk clk_epll;
 extern struct clk clk_xtal;
 extern struct clk clk_ext;
 
+/* S3C2443/S3C2416 specific clocks */
+extern struct clksrc_clk clk_epllref;
+extern struct clksrc_clk clk_esysclk;
+
 /* S3C64XX specific clocks */
 extern struct clk clk_h2;
 extern struct clk clk_27m;
@@ -114,7 +118,23 @@ extern void s3c24xx_setup_clocks(unsigned long fclk,
 extern void s3c2410_setup_clocks(void);
 extern void s3c2412_setup_clocks(void);
 extern void s3c244x_setup_clocks(void);
-extern void s3c2443_setup_clocks(void);
+
+/* S3C2410 specific clock functions */
+
+extern int s3c2410_baseclk_add(void);
+
+/* S3C2443/S3C2416 specific clock functions */
+
+typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
+
+extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
+extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
+                                       unsigned int *divs, int nr_divs,
+                                       int divmask);
+
+extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
 
 /* S3C64XX specific functions and clocks */
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 73cb3cfd068..787ceaca0be 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4412_CPU_ID       0xE4412200
 #define EXYNOS4_CPU_MASK        0xFFFE0000
 
+#define EXYNOS5250_SOC_ID       0x43520000
+#define EXYNOS5_SOC_MASK        0xFFFFF000
+
 #define IS_SAMSUNG_CPU(name, id, mask)          \
 static inline int is_samsung_##name(void)       \
 {                                               \
@@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
     defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 #define EXYNOS4210_REV_1_0      (0x10)
 #define EXYNOS4210_REV_1_1      (0x11)
 
+#if defined(CONFIG_SOC_EXYNOS5250)
+# define soc_is_exynos5250()    is_samsung_exynos5250()
+#else
+# define soc_is_exynos5250()    0
+#endif
+
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef MHZ
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4214ea0ff8f..2155d4af62a 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -26,6 +26,8 @@ struct s3c24xx_uart_resources {
 extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
 extern struct s3c24xx_uart_resources s5p_uart_resources[];
+extern struct s3c24xx_uart_resources exynos4_uart_resources[];
+extern struct s3c24xx_uart_resources exynos5_uart_resources[];
 
 extern struct platform_device *s3c24xx_uart_devs[];
 extern struct platform_device *s3c24xx_uart_src[];
@@ -79,6 +81,8 @@ extern struct platform_device s5p_device_fimc1;
 extern struct platform_device s5p_device_fimc2;
 extern struct platform_device s5p_device_fimc3;
 extern struct platform_device s5p_device_fimc_md;
+extern struct platform_device s5p_device_jpeg;
+extern struct platform_device s5p_device_g2d;
 extern struct platform_device s5p_device_fimd0;
 extern struct platform_device s5p_device_hdmi;
 extern struct platform_device s5p_device_i2c_hdmiphy;
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index c5eaad529de..0670f37aaae 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -82,6 +82,22 @@ enum dma_ch {
         DMACH_SLIMBUS4_TX,
         DMACH_SLIMBUS5_RX,
         DMACH_SLIMBUS5_TX,
+        DMACH_MIPI_HSI0,
+        DMACH_MIPI_HSI1,
+        DMACH_MIPI_HSI2,
+        DMACH_MIPI_HSI3,
+        DMACH_MIPI_HSI4,
+        DMACH_MIPI_HSI5,
+        DMACH_MIPI_HSI6,
+        DMACH_MIPI_HSI7,
+        DMACH_MTOM_0,
+        DMACH_MTOM_1,
+        DMACH_MTOM_2,
+        DMACH_MTOM_3,
+        DMACH_MTOM_4,
+        DMACH_MTOM_5,
+        DMACH_MTOM_6,
+        DMACH_MTOM_7,
         /* END Marker, also used to denote a reserved channel */
         DMACH_MAX,
 };
diff --git a/arch/arm/plat-samsung/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
index 178bccbe480..a7d622ef16a 100644
--- a/arch/arm/plat-samsung/include/plat/regs-dma.h
+++ b/arch/arm/plat-samsung/include/plat/regs-dma.h
@@ -119,7 +119,7 @@
 #define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
 #endif /* CONFIG_CPU_S3C2412 */
 
-#ifdef CONFIG_CPU_S3C2443
+#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
 
 #define S3C2443_DMAREQSEL_SRC(x)        ((x) << 1)
 
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
index 30b7cc14cef..0f8263e93ee 100644
--- a/arch/arm/plat-samsung/include/plat/regs-rtc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h
@@ -18,51 +18,54 @@
 #define S3C2410_INTP_ALM        (1 << 1)
 #define S3C2410_INTP_TIC        (1 << 0)
 
-#define S3C2410_RTCCON        S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN  (1<<0)
-#define S3C2410_RTCCON_CLKSEL (1<<1)
-#define S3C2410_RTCCON_CNTSEL (1<<2)
-#define S3C2410_RTCCON_CLKRST (1<<3)
-#define S3C64XX_RTCCON_TICEN  (1<<8)
+#define S3C2410_RTCCON          S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN    (1 << 0)
+#define S3C2410_RTCCON_CNTSEL   (1 << 2)
+#define S3C2410_RTCCON_CLKRST   (1 << 3)
+#define S3C2443_RTCCON_TICSEL   (1 << 4)
+#define S3C64XX_RTCCON_TICEN    (1 << 8)
 
-#define S3C64XX_RTCCON_TICMSK (0xF<<7)
-#define S3C64XX_RTCCON_TICSHT (7)
+#define S3C2410_TICNT           S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE    (1 << 7)
 
-#define S3C2410_TICNT         S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE  (1<<7)
+/* S3C2443: tick count is 15 bit wide
+ * TICNT[6:0] contains upper 7 bits
+ * TICNT1[7:0] contains lower 8 bits
+ */
+#define S3C2443_TICNT_PART(x)   ((x & 0x7f00) >> 8)
+#define S3C2443_TICNT1          S3C2410_RTCREG(0x4C)
+#define S3C2443_TICNT1_PART(x)  (x & 0xff)
 
-#define S3C2410_RTCALM        S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN  (1<<6)
-#define S3C2410_RTCALM_YEAREN (1<<5)
-#define S3C2410_RTCALM_MONEN  (1<<4)
-#define S3C2410_RTCALM_DAYEN  (1<<3)
-#define S3C2410_RTCALM_HOUREN (1<<2)
-#define S3C2410_RTCALM_MINEN  (1<<1)
-#define S3C2410_RTCALM_SECEN  (1<<0)
+/* S3C2416: tick count is 32 bit wide
+ * TICNT[6:0] contains bits [14:8]
+ * TICNT1[7:0] contains lower 8 bits
+ * TICNT2[16:0] contains upper 17 bits
+ */
+#define S3C2416_TICNT2          S3C2410_RTCREG(0x48)
+#define S3C2416_TICNT2_PART(x)  ((x & 0xffff8000) >> 15)
 
-#define S3C2410_RTCALM_ALL \
-  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
-  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
-  S3C2410_RTCALM_SECEN
+#define S3C2410_RTCALM          S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN    (1 << 6)
+#define S3C2410_RTCALM_YEAREN   (1 << 5)
+#define S3C2410_RTCALM_MONEN    (1 << 4)
+#define S3C2410_RTCALM_DAYEN    (1 << 3)
+#define S3C2410_RTCALM_HOUREN   (1 << 2)
+#define S3C2410_RTCALM_MINEN    (1 << 1)
+#define S3C2410_RTCALM_SECEN    (1 << 0)
 
+#define S3C2410_ALMSEC          S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN          S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR         S3C2410_RTCREG(0x5c)
 
-#define S3C2410_ALMSEC        S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN        S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR       S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE       S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON        S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR       S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCRST        S3C2410_RTCREG(0x6c)
-
-#define S3C2410_RTCSEC        S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN        S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR       S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE       S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCDAY        S3C2410_RTCREG(0x80)
-#define S3C2410_RTCMON        S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR       S3C2410_RTCREG(0x88)
+#define S3C2410_ALMDATE         S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON          S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR         S3C2410_RTCREG(0x68)
 
+#define S3C2410_RTCSEC          S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN          S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR         S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE         S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCMON          S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR         S3C2410_RTCREG(0x88)
 
 #endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
index a111ad87183..fcf27966206 100644
--- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
@@ -25,8 +25,9 @@
 #define S3C_HSOTG_PHYREG(x)     ((x) + S3C_VA_USB_HSPHY)
 
 #define S3C_PHYPWR                              S3C_HSOTG_PHYREG(0x00)
-#define SRC_PHYPWR_OTG_DISABLE                  (1 << 4)
-#define SRC_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
+#define S3C_PHYPWR_NORMAL_MASK                  (0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE                  (1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
 #define SRC_PHYPWR_FORCE_SUSPEND                (1 << 1)
 
 #define S3C_PHYCLK                              S3C_HSOTG_PHYREG(0x04)
@@ -42,7 +43,7 @@
 
 #define S3C_RSTCON                              S3C_HSOTG_PHYREG(0x08)
 #define S3C_RSTCON_PHYCLK                       (1 << 2)
-#define S3C_RSTCON_HCLK                         (1 << 2)
+#define S3C_RSTCON_HCLK                         (1 << 1)
 #define S3C_RSTCON_PHY                          (1 << 0)
 
 #define S3C_PHYTUNE                             S3C_HSOTG_PHYREG(0x20)
diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h
new file mode 100644
index 00000000000..21d8594d37c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/rtc-core.h
@@ -0,0 +1,27 @@
+/* linux/arch/arm/plat-samsung/include/plat/rtc-core.h
+ *
+ * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de>
+ *
+ * Samsung RTC Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_RTC_CORE_H
+#define __ASM_PLAT_RTC_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_rtc_setname(char *name)
+{
+#if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
+        s3c_device_rtc.name = name;
+#endif
+}
+
+#endif /* __ASM_PLAT_RTC_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
index 3986497dd3f..55b0e5f51e9 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2410.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2410.h
@@ -29,5 +29,3 @@ extern void s3c2410_init_clocks(int xtal);
 #define s3c2410_init NULL
 #define s3c2410a_init NULL
 #endif
-
-extern int s3c2410_baseclk_add(void);
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
index dce05b43d51..a5b794ff838 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -32,23 +32,3 @@ extern void s3c2443_restart(char mode, const char *cmd);
 #define s3c2443_init NULL
 #define s3c2443_restart NULL
 #endif
-
-/* common code used by s3c2443 and others.
- * note, not to be used outside of arch/arm/mach-s3c* */
-
-struct clk;     /* some files don't need clk.h otherwise */
-
-typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
-
-extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
-extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-                                       unsigned int *divs, int nr_divs,
-                                       int divmask);
-
-extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
-extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
-extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
-
-extern struct clksrc_clk clk_epllref;
-extern struct clksrc_clk clk_esysclk;
-extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 984bf9e7bc8..1de4b32f98e 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -18,6 +18,8 @@
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 
 #define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_bpll clk_ext_xtal_mux
+#define clk_fin_cpll clk_ext_xtal_mux
 #define clk_fin_mpll clk_ext_xtal_mux
 #define clk_fin_epll clk_ext_xtal_mux
 #define clk_fin_dpll clk_ext_xtal_mux
@@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
 extern struct clk clk_48m;
 extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
+extern struct clk clk_fout_bpll;
+extern struct clk clk_fout_cpll;
 extern struct clk clk_fout_mpll;
 extern struct clk clk_fout_epll;
 extern struct clk clk_fout_dpll;
@@ -37,6 +41,8 @@ extern struct clk clk_arm;
 extern struct clk clk_vpll;
 
 extern struct clksrc_sources clk_src_apll;
+extern struct clksrc_sources clk_src_bpll;
+extern struct clksrc_sources clk_src_cpll;
 extern struct clksrc_sources clk_src_mpll;
 extern struct clksrc_sources clk_src_epll;
 extern struct clksrc_sources clk_src_dpll;
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index f82f888b91a..317e246ffc5 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -40,6 +40,7 @@ enum clk_types {
  * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
  * @max_width: The maximum number of data bits supported.
  * @host_caps: Standard MMC host capabilities bit field.
+ * @host_caps2: The second standard MMC host capabilities bit field.
  * @cd_type: Type of Card Detection method (see cd_types enum above)
  * @clk_type: Type of clock divider method (see clk_types enum above)
  * @ext_cd_init: Initialize external card detect subsystem. Called on
@@ -63,6 +64,7 @@ enum clk_types {
 struct s3c_sdhci_platdata {
         unsigned int    max_width;
         unsigned int    host_caps;
+        unsigned int    host_caps2;
         unsigned int    pm_caps;
         enum cd_types   cd_type;
         enum clk_types  clk_type;
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
index a22a4f2eea9..c9e3667cb2b 100644
--- a/arch/arm/plat-samsung/include/plat/udc-hs.h
+++ b/arch/arm/plat-samsung/include/plat/udc-hs.h
@@ -26,4 +26,9 @@ enum s3c_hsotg_dmamode {
 struct s3c_hsotg_plat {
         enum s3c_hsotg_dmamode  dma;
         unsigned int            is_osc : 1;
+
+        int (*phy_init)(struct platform_device *pdev, int type);
+        int (*phy_exit)(struct platform_device *pdev, int type);
 };
+
+extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index ee48e12a1e7..7e068d182c3 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -37,7 +37,9 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX         (14)
 
+#ifdef S3C_PA_UART
 #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
+#endif
 
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 51583cd3016..f980cf3d2ba 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 
 #include <mach/map.h>
+#include <plat/cpu.h>
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
 
@@ -57,6 +58,21 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
         struct irq_chip_type *ct;
         unsigned int i;
 
+#ifdef CONFIG_ARCH_EXYNOS
+        if (soc_is_exynos5250()) {
+                pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
+                pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
+                pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
+                pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
+                pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
+        } else {
+                pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
+                pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
+                pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
+                pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
+                pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
+        }
+#endif
         s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
                                          S3C64XX_TINT_CSTAT, handle_level_irq);
 
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 0f707184eae..fa78aa710ed 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -53,6 +53,8 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
                 set->cfg_gpio = pd->cfg_gpio;
         if (pd->host_caps)
                 set->host_caps |= pd->host_caps;
+        if (pd->host_caps2)
+                set->host_caps2 |= pd->host_caps2;
         if (pd->pm_caps)
                 set->pm_caps |= pd->pm_caps;
         if (pd->clk_type)
diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
deleted file mode 100644
index 86c6f83b44c..00000000000
--- a/arch/arm/plat-spear/include/plat/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/system.h
- *
- * SPEAr platform specific architecture functions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_SYSTEM_H
-#define __PLAT_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif /* __PLAT_SYSTEM_H */
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 69714db47c3..a5cb1945bdc 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,5 +1,4 @@
 obj-y   := clock.o
-obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
 obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
diff --git a/arch/arm/plat-versatile/localtimer.c b/arch/arm/plat-versatile/localtimer.c
deleted file mode 100644
index 0fb3961999b..00000000000
--- a/arch/arm/plat-versatile/localtimer.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  linux/arch/arm/plat-versatile/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-#include <mach/irqs.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index 7c756fb189f..afeae8978a8 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -97,6 +97,7 @@ static struct atmel_nand_data atngw100mkii_nand_data __initdata = {
         .rdy_pin        = GPIO_PIN_PB(28),
         .enable_pin     = GPIO_PIN_PE(23),
         .bus_width_16   = true,
+        .ecc_mode       = NAND_ECC_SOFT,
         .parts          = nand_partitions,
         .num_parts      = ARRAY_SIZE(nand_partitions),
 };
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index c56ddac85d6..dc526332148 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -95,6 +95,7 @@ static struct atmel_nand_data atstk1006_nand_data __initdata = {
         .ale            = 22,
         .rdy_pin        = GPIO_PIN_PB(30),
         .enable_pin     = GPIO_PIN_PB(29),
+        .ecc_mode       = NAND_ECC_SOFT,
         .parts          = nand_partitions,
         .num_parts      = ARRAY_SIZE(num_partitions),
 };
diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h
index 22c97ef9220..cf60d0a9f17 100644
--- a/arch/avr32/include/asm/io.h
+++ b/arch/avr32/include/asm/io.h
@@ -1,6 +1,7 @@
 #ifndef __ASM_AVR32_IO_H
 #define __ASM_AVR32_IO_H
 
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/types.h>
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 402a7bb7266..889c544688c 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1055,8 +1055,6 @@ struct platform_device *__init at32_add_device_usart(unsigned int id)
         return at32_usarts[id];
 }
 
-struct platform_device *atmel_default_console_device;
-
 void __init at32_setup_serial_console(unsigned int usart_id)
 {
         atmel_default_console_device = at32_usarts[usart_id];
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index 67b111ce332..71733866cb4 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -7,6 +7,7 @@
 #include <linux/types.h>
 #include <linux/serial.h>
 #include <linux/platform_data/macb.h>
+#include <linux/platform_data/atmel_nand.h>
 
 #define GPIO_PIN_NONE   (-1)
 
@@ -116,18 +117,6 @@ struct platform_device *
 at32_add_device_cf(unsigned int id, unsigned int extint,
                 struct cf_platform_data *data);
 
-/* NAND / SmartMedia */
-struct atmel_nand_data {
-        int     enable_pin;     /* chip enable */
-        int     det_pin;        /* card detect */
-        int     rdy_pin;        /* ready/busy */
-        u8      rdy_pin_active_low;     /* rdy_pin value is inverted */
-        u8      ale;            /* address line number connected to ALE */
-        u8      cle;            /* address line number connected to CLE */
-        u8      bus_width_16;   /* buswidth is 16 bit */
-        struct mtd_partition *parts;
-        unsigned int    num_parts;
-};
 struct platform_device *
 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
 
diff --git a/arch/avr32/mach-at32ap/include/mach/cpu.h b/arch/avr32/mach-at32ap/include/mach/cpu.h
index 8181293115e..16a24b14146 100644
--- a/arch/avr32/mach-at32ap/include/mach/cpu.h
+++ b/arch/avr32/mach-at32ap/include/mach/cpu.h
@@ -30,9 +30,6 @@
 #define cpu_is_at91sam9261()    (0)
 #define cpu_is_at91sam9263()    (0)
 #define cpu_is_at91sam9rl()     (0)
-#define cpu_is_at91cap9()       (0)
-#define cpu_is_at91cap9_revB()  (0)
-#define cpu_is_at91cap9_revC()  (0)
 #define cpu_is_at91sam9g10()    (0)
 #define cpu_is_at91sam9g20()    (0)
 #define cpu_is_at91sam9g45()    (0)
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index abe5a9e8514..c1269a1085e 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -36,6 +36,7 @@ config BLACKFIN
         select GENERIC_ATOMIC64
         select GENERIC_IRQ_PROBE
         select IRQ_PER_CPU if SMP
+        select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
 
 config GENERIC_CSUM
         def_bool y
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 12f4060a31b..89de539ed01 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -38,8 +38,4 @@
 
 #include <asm-generic/irq.h>
 
-#ifdef CONFIG_NMI_WATCHDOG
-# define ARCH_HAS_NMI_WATCHDOG
-#endif
-
 #endif                          /* _BFIN_IRQ_H_ */
diff --git a/arch/c6x/include/asm/pgtable.h b/arch/c6x/include/asm/pgtable.h
index 68c8af4f1f9..38a4312eb2c 100644
--- a/arch/c6x/include/asm/pgtable.h
+++ b/arch/c6x/include/asm/pgtable.h
@@ -73,9 +73,6 @@ extern unsigned long empty_zero_page;
 #define pgtable_cache_init()   do { } while (0)
 #define io_remap_pfn_range      remap_pfn_range
 
-#define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
-                remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
-
 #include <asm-generic/pgtable.h>
 
 #endif /* _ASM_C6X_PGTABLE_H */
diff --git a/arch/hexagon/kernel/signal.c b/arch/hexagon/kernel/signal.c
index b45be318119..ecbab345760 100644
--- a/arch/hexagon/kernel/signal.c
+++ b/arch/hexagon/kernel/signal.c
@@ -192,12 +192,7 @@ static int handle_signal(int sig, siginfo_t *info, struct k_sigaction *ka,
         if (rc)
                 return rc;
 
-        spin_lock_irq(&current->sighand->siglock);
-        sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked, sig);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        block_sigmask(ka, sig);
 
         return 0;
 }
@@ -305,10 +300,7 @@ asmlinkage int sys_rt_sigreturn(void)
                 goto badframe;
 
         sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
 
         if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
                 goto badframe;
diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c
index 16277c33308..f212a453b52 100644
--- a/arch/hexagon/kernel/vdso.c
+++ b/arch/hexagon/kernel/vdso.c
@@ -78,8 +78,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
         /* MAYWRITE to allow gdb to COW and set breakpoints. */
         ret = install_special_mapping(mm, vdso_base, PAGE_SIZE,
                                       VM_READ|VM_EXEC|
-                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                       &vdso_page);
 
         if (ret)
diff --git a/arch/ia64/include/asm/kvm.h b/arch/ia64/include/asm/kvm.h
index bc90c75adf6..b9f82c84f09 100644
--- a/arch/ia64/include/asm/kvm.h
+++ b/arch/ia64/include/asm/kvm.h
@@ -261,4 +261,8 @@ struct kvm_debug_exit_arch {
 struct kvm_guest_debug_arch {
 };
 
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
 #endif
diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h
index 2689ee54a1c..e35b3a84a40 100644
--- a/arch/ia64/include/asm/kvm_host.h
+++ b/arch/ia64/include/asm/kvm_host.h
@@ -459,6 +459,9 @@ struct kvm_sal_data {
         unsigned long boot_gp;
 };
 
+struct kvm_arch_memory_slot {
+};
+
 struct kvm_arch {
         spinlock_t dirty_log_lock;
 
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index c5e6da95522..5e04b591e42 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -116,12 +116,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
         return (pci_domain_nr(bus) != 0);
 }
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                struct resource *res, struct pci_bus_region *region);
-
 static inline struct resource *
 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 {
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 93c648887f8..d1cc81e63ba 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -348,11 +348,11 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
 
         iosapic_override_isa_irq(p->source_irq, p->global_irq,
                                  ((p->inti_flags & ACPI_MADT_POLARITY_MASK) ==
-                                  ACPI_MADT_POLARITY_ACTIVE_HIGH) ?
-                                 IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW,
+                                  ACPI_MADT_POLARITY_ACTIVE_LOW) ?
+                                 IOSAPIC_POL_LOW : IOSAPIC_POL_HIGH,
                                  ((p->inti_flags & ACPI_MADT_TRIGGER_MASK) ==
-                                 ACPI_MADT_TRIGGER_EDGE) ?
-                                 IOSAPIC_EDGE : IOSAPIC_LEVEL);
+                                 ACPI_MADT_TRIGGER_LEVEL) ?
+                                 IOSAPIC_LEVEL : IOSAPIC_EDGE);
         return 0;
 }
 
diff --git a/arch/ia64/kernel/machine_kexec.c b/arch/ia64/kernel/machine_kexec.c
index 4eed3581499..070e8effa17 100644
--- a/arch/ia64/kernel/machine_kexec.c
+++ b/arch/ia64/kernel/machine_kexec.c
@@ -157,7 +157,7 @@ void arch_crash_save_vmcoreinfo(void)
 #endif
 #ifdef CONFIG_PGTABLE_3
         VMCOREINFO_CONFIG(PGTABLE_3);
-#elif  CONFIG_PGTABLE_4
+#elif defined(CONFIG_PGTABLE_4)
         VMCOREINFO_CONFIG(PGTABLE_4);
 #endif
 }
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 9198a799140..a39fe098a73 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -1446,6 +1446,8 @@ out:
         /* Get the CMC error record and log it */
         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
 
+        local_irq_disable();
+
         return IRQ_HANDLED;
 }
 
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 40505200249..f5104b7c52c 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -809,10 +809,13 @@ static void kvm_build_io_pmt(struct kvm *kvm)
 #define GUEST_PHYSICAL_RR4      0x2739
 #define VMM_INIT_RR             0x1660
 
-int kvm_arch_init_vm(struct kvm *kvm)
+int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 {
         BUG_ON(!kvm);
 
+        if (type)
+                return -EINVAL;
+
         kvm->arch.is_sn2 = ia64_platform_is("sn2");
 
         kvm->arch.metaphysical_rr0 = GUEST_PHYSICAL_RR0;
@@ -1169,6 +1172,11 @@ out:
 
 #define PALE_RESET_ENTRY    0x80000000ffffffb0UL
 
+bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
+{
+        return irqchip_in_kernel(vcpu->kcm) == (vcpu->arch.apic != NULL);
+}
+
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
 {
         struct kvm_vcpu *v;
@@ -1563,6 +1571,21 @@ out:
         return r;
 }
 
+int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
+{
+        return VM_FAULT_SIGBUS;
+}
+
+void kvm_arch_free_memslot(struct kvm_memory_slot *free,
+                           struct kvm_memory_slot *dont)
+{
+}
+
+int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
+{
+        return 0;
+}
+
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                 struct kvm_memory_slot *memslot,
                 struct kvm_memory_slot old,
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 94627926552..524df4295c9 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -319,7 +319,8 @@ static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
          * Ignore these tiny memory ranges */
         if (!((window->resource.flags & IORESOURCE_MEM) &&
               (window->resource.end - window->resource.start < 16)))
-                pci_add_resource(&info->resources, &window->resource);
+                pci_add_resource_offset(&info->resources, &window->resource,
+                                        window->offset);
 
         return AE_OK;
 }
@@ -394,54 +395,6 @@ out1:
         return NULL;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev,
-                struct pci_bus_region *region, struct resource *res)
-{
-        struct pci_controller *controller = PCI_CONTROLLER(dev);
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < controller->windows; i++) {
-                struct pci_window *window = &controller->window[i];
-                if (!(window->resource.flags & res->flags))
-                        continue;
-                if (window->resource.start > res->start)
-                        continue;
-                if (window->resource.end < res->end)
-                        continue;
-                offset = window->offset;
-                break;
-        }
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *dev,
-                struct resource *res, struct pci_bus_region *region)
-{
-        struct pci_controller *controller = PCI_CONTROLLER(dev);
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < controller->windows; i++) {
-                struct pci_window *window = &controller->window[i];
-                if (!(window->resource.flags & res->flags))
-                        continue;
-                if (window->resource.start - window->offset > region->start)
-                        continue;
-                if (window->resource.end - window->offset < region->end)
-                        continue;
-                offset = window->offset;
-                break;
-        }
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 {
         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
@@ -463,15 +416,11 @@ static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 static void __devinit
 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
 {
-        struct pci_bus_region region;
         int i;
 
         for (i = start; i < limit; i++) {
                 if (!dev->resource[i].flags)
                         continue;
-                region.start = dev->resource[i].start;
-                region.end = dev->resource[i].end;
-                pcibios_bus_to_resource(dev, &dev->resource[i], &region);
                 if ((is_valid_resource(dev, i)))
                         pci_claim_resource(dev, i);
         }
diff --git a/arch/ia64/sn/kernel/huberror.c b/arch/ia64/sn/kernel/huberror.c
index 08b0d9bb62e..f925dec2da9 100644
--- a/arch/ia64/sn/kernel/huberror.c
+++ b/arch/ia64/sn/kernel/huberror.c
@@ -192,6 +192,7 @@ void hub_error_init(struct hubdev_info *hubdev_info)
                     hubdev_info);
                 return;
         }
+        irq_set_handler(SGI_II_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_II_ERROR);
 }
 
@@ -213,6 +214,7 @@ void ice_error_init(struct hubdev_info *hubdev_info)
                        hubdev_info);
                 return;
         }
+        irq_set_handler(SGI_TIO_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_TIO_ERROR);
 }
 
diff --git a/arch/ia64/sn/kernel/io_common.c b/arch/ia64/sn/kernel/io_common.c
index 4433dd019d3..fbb5f2f87ee 100644
--- a/arch/ia64/sn/kernel/io_common.c
+++ b/arch/ia64/sn/kernel/io_common.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/bootmem.h>
+#include <linux/export.h>
 #include <linux/slab.h>
 #include <asm/sn/types.h>
 #include <asm/sn/addrs.h>
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 0a36f082eaf..238e2c511d9 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -297,7 +297,8 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
         s64 status = 0;
         struct pci_controller *controller;
         struct pcibus_bussoft *prom_bussoft_ptr;
-
+        LIST_HEAD(resources);
+        int i;
 
         status = sal_get_pcibus_info((u64) segment, (u64) busnum,
                                      (u64) ia64_tpa(&prom_bussoft_ptr));
@@ -315,7 +316,15 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
          */
         controller->platform_data = prom_bussoft_ptr;
 
-        bus = pci_scan_bus(busnum, &pci_root_ops, controller);
+        sn_legacy_pci_window_fixup(controller,
+                                   prom_bussoft_ptr->bs_legacy_io,
+                                   prom_bussoft_ptr->bs_legacy_mem);
+        for (i = 0; i < controller->windows; i++)
+                pci_add_resource_offset(&resources,
+                                        &controller->window[i].resource,
+                                        controller->window[i].offset);
+        bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, controller,
+                                &resources);
         if (bus == NULL)
                 goto error_return; /* error, or bus already scanned */
 
@@ -348,9 +357,6 @@ sn_bus_fixup(struct pci_bus *bus)
                         return;
                 }
                 sn_common_bus_fixup(bus, prom_bussoft_ptr);
-                sn_legacy_pci_window_fixup(PCI_CONTROLLER(bus),
-                                           prom_bussoft_ptr->bs_legacy_io,
-                                           prom_bussoft_ptr->bs_legacy_mem);
         }
         list_for_each_entry(pci_dev, &bus->devices, bus_list) {
                 sn_io_slot_fixup(pci_dev);
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index dfac09ab027..62cf4dde6a0 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -352,6 +352,8 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
         spin_lock(&sn_irq_info_lock);
         list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
         reserve_irq_vector(sn_irq_info->irq_irq);
+        if (sn_irq_info->irq_int_bit != -1)
+                irq_set_handler(sn_irq_info->irq_irq, handle_level_irq);
         spin_unlock(&sn_irq_info_lock);
 
         register_intr_pda(sn_irq_info);
diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
index 2de41d44266..4554f68b786 100644
--- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c
+++ b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
@@ -25,6 +25,7 @@
 
 #include <linux/fs.h>
 #include <linux/slab.h>
+#include <linux/export.h>
 #include <linux/vmalloc.h>
 #include <linux/seq_file.h>
 #include <linux/miscdevice.h>
diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c
index 26aeccb04f8..14c1711238c 100644
--- a/arch/ia64/sn/kernel/tiocx.c
+++ b/arch/ia64/sn/kernel/tiocx.c
@@ -190,6 +190,7 @@ cx_device_register(nasid_t nasid, int part_num, int mfg_num,
                    struct hubdev_info *hubdev, int bt)
 {
         struct cx_dev *cx_dev;
+        int r;
 
         cx_dev = kzalloc(sizeof(struct cx_dev), GFP_KERNEL);
         DBG("cx_dev= 0x%p\n", cx_dev);
@@ -206,7 +207,11 @@ cx_device_register(nasid_t nasid, int part_num, int mfg_num,
         cx_dev->dev.bus = &tiocx_bus_type;
         cx_dev->dev.release = tiocx_bus_release;
         dev_set_name(&cx_dev->dev, "%d", cx_dev->cx_id.nasid);
-        device_register(&cx_dev->dev);
+        r = device_register(&cx_dev->dev);
+        if (r) {
+                kfree(cx_dev);
+                return r;
+        }
         get_device(&cx_dev->dev);
 
         device_create_file(&cx_dev->dev, &dev_attr_cxdev_control);
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
index 8886a0bc4a1..8dbbef4a4f4 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
@@ -146,6 +146,7 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
                 printk(KERN_WARNING
                        "pcibr cannot allocate interrupt for error handler\n");
         }
+        irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
 
         /* 
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index e77c477245f..a70b11fd57d 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -649,6 +649,7 @@ tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
                        __func__, SGI_TIOCA_ERROR,
                        (int)tioca_common->ca_common.bs_persist_busnum);
 
+        irq_set_handler(SGI_TIOCA_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_TIOCA_ERROR);
 
         /* Setup locality information */
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
index 27faba035f3..46d3df4b03a 100644
--- a/arch/ia64/sn/pci/tioce_provider.c
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -1037,6 +1037,7 @@ tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
                        tioce_common->ce_pcibus.bs_persist_segment,
                        tioce_common->ce_pcibus.bs_persist_busnum);
 
+        irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
         return tioce_common;
 }
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 11060fa87da..ac22dc7f4ca 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -1,6 +1,7 @@
 config MICROBLAZE
         def_bool y
         select HAVE_MEMBLOCK
+        select HAVE_MEMBLOCK_NODE_MAP
         select HAVE_FUNCTION_TRACER
         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
         select HAVE_FUNCTION_GRAPH_TRACER
@@ -28,6 +29,12 @@ config SWAP
 config RWSEM_GENERIC_SPINLOCK
         def_bool y
 
+config ZONE_DMA
+        def_bool y
+
+config ARCH_POPULATES_NODE_MAP
+        def_bool y
+
 config RWSEM_XCHGADD_ALGORITHM
         bool
 
@@ -153,20 +160,18 @@ config XILINX_UNCACHED_SHADOW
           The feature requires the design to define the RAM memory controller
           window to be twice as large as the actual physical memory.
 
-config HIGHMEM_START_BOOL
-        bool "Set high memory pool address"
-        depends on ADVANCED_OPTIONS && HIGHMEM
+config HIGHMEM
+        bool "High memory support"
+        depends on MMU
         help
-          This option allows you to set the base address of the kernel virtual
-          area used to map high memory pages.  This can be useful in
-          optimizing the layout of kernel virtual memory.
+          The address space of Microblaze processors is only 4 Gigabytes large
+          and it has to accommodate user address space, kernel address
+          space as well as some memory mapped IO. That means that, if you
+          have a large amount of physical memory and/or IO, not all of the
+          memory can be "permanently mapped" by the kernel. The physical
+          memory that is not permanently mapped is called "high memory".
 
-          Say N here unless you know what you are doing.
-
-config HIGHMEM_START
-        hex "Virtual start address of high memory pool" if HIGHMEM_START_BOOL
-        depends on MMU
-        default "0xfe000000"
+          If unsure, say n.
 
 config LOWMEM_SIZE_BOOL
         bool "Set maximum low memory"
@@ -255,6 +260,10 @@ config MICROBLAZE_32K_PAGES
 
 endchoice
 
+config KERNEL_PAD
+        hex "Kernel PAD for unpacking" if ADVANCED_OPTIONS
+        default "0x80000" if MMU
+
 endmenu
 
 source "mm/Kconfig"
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index 0c796cf8158..34940c828de 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -8,7 +8,7 @@ obj-y += linked_dtb.o
 
 targets := linux.bin linux.bin.gz simpleImage.%
 
-OBJCOPYFLAGS := -O binary
+OBJCOPYFLAGS := -R .note -R .comment -R .note.gnu.build-id -O binary
 
 # Ensure system.dtb exists
 $(obj)/linked_dtb.o: $(obj)/system.dtb
diff --git a/arch/microblaze/include/asm/fixmap.h b/arch/microblaze/include/asm/fixmap.h
new file mode 100644
index 00000000000..f2b312e10b1
--- /dev/null
+++ b/arch/microblaze/include/asm/fixmap.h
@@ -0,0 +1,109 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Copyright 2008 Freescale Semiconductor Inc.
+ *   Port to powerpc added by Kumar Gala
+ *
+ * Copyright 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright 2011 PetaLogix Qld Pty Ltd
+ *   Port to Microblaze
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#ifndef __ASSEMBLY__
+#include <linux/kernel.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+#define FIXADDR_TOP     ((unsigned long)(-PAGE_SIZE))
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special addresses
+ * from the end of virtual memory (0xfffff000) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+enum fixed_addresses {
+        FIX_HOLE,
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
+        FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * num_possible_cpus()) - 1,
+#endif
+        __end_of_fixed_addresses
+};
+
+extern void __set_fixmap(enum fixed_addresses idx,
+                                        phys_addr_t phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL_CI)
+
+#define clear_fixmap(idx) \
+                __set_fixmap(idx, 0, __pgprot(0))
+
+#define __FIXADDR_SIZE  (__end_of_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START           (FIXADDR_TOP - __FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static __always_inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+#endif /* !__ASSEMBLY__ */
+#endif
diff --git a/arch/microblaze/include/asm/highmem.h b/arch/microblaze/include/asm/highmem.h
new file mode 100644
index 00000000000..2446a73140a
--- /dev/null
+++ b/arch/microblaze/include/asm/highmem.h
@@ -0,0 +1,96 @@
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <asm/fixmap.h>
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+/*
+ * We use one full pte table with 4K pages. And with 16K/64K/256K pages pte
+ * table covers enough memory (32MB/512MB/2GB resp.), so that both FIXMAP
+ * and PKMAP can be placed in a single pte table. We use 512 pages for PKMAP
+ * in case of 16K/64K/256K page sizes.
+ */
+
+#define PKMAP_ORDER     PTE_SHIFT
+#define LAST_PKMAP      (1 << PKMAP_ORDER)
+
+#define PKMAP_BASE      ((FIXADDR_START - PAGE_SIZE * (LAST_PKMAP + 1)) \
+                                                                & PMD_MASK)
+
+#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
+#define PKMAP_NR(virt)  ((virt - PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+extern void *kmap_atomic_prot(struct page *page, pgprot_t prot);
+extern void __kunmap_atomic(void *kvaddr);
+
+static inline void *kmap(struct page *page)
+{
+        might_sleep();
+        if (!PageHighMem(page))
+                return page_address(page);
+        return kmap_high(page);
+}
+
+static inline void kunmap(struct page *page)
+{
+        BUG_ON(in_interrupt());
+        if (!PageHighMem(page))
+                return;
+        kunmap_high(page);
+}
+
+static inline void *__kmap_atomic(struct page *page)
+{
+        return kmap_atomic_prot(page, kmap_prot);
+}
+
+static inline struct page *kmap_atomic_to_page(void *ptr)
+{
+        unsigned long idx, vaddr = (unsigned long) ptr;
+        pte_t *pte;
+
+        if (vaddr < FIXADDR_START)
+                return virt_to_page(ptr);
+
+        idx = virt_to_fix(vaddr);
+        pte = kmap_pte - (idx - FIX_KMAP_BEGIN);
+        return pte_page(*pte);
+}
+
+#define flush_cache_kmaps()     { flush_icache(); flush_dcache(); }
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/microblaze/include/asm/mmu.h b/arch/microblaze/include/asm/mmu.h
index 8d6a654ceff..1f9edddf7f4 100644
--- a/arch/microblaze/include/asm/mmu.h
+++ b/arch/microblaze/include/asm/mmu.h
@@ -56,6 +56,12 @@ typedef struct _SEGREG {
 
 extern void _tlbie(unsigned long va);   /* invalidate a TLB entry */
 extern void _tlbia(void);               /* invalidate all TLB entries */
+
+/*
+ * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
+ * mapping has to increase tlb_skip size.
+ */
+extern u32 tlb_skip;
 #   endif /* __ASSEMBLY__ */
 
 /*
@@ -69,6 +75,12 @@ extern void _tlbia(void);		/* invalidate all TLB entries */
 
 #  define MICROBLAZE_TLB_SIZE 64
 
+/* For cases when you want to skip some TLB entries */
+#  define MICROBLAZE_TLB_SKIP 0
+
+/* Use the last TLB for temporary access to LMB */
+#  define MICROBLAZE_LMB_TLB_ID 63
+
 /*
  * TLB entries are defined by a "high" tag portion and a "low" data
  * portion. The data portion is 32-bits.
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index a25e6b5e2ad..287c5485d28 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -135,8 +135,10 @@ extern unsigned long min_low_pfn;
 extern unsigned long max_pfn;
 
 extern unsigned long memory_start;
-extern unsigned long memory_end;
 extern unsigned long memory_size;
+extern unsigned long lowmem_size;
+
+extern unsigned long kernel_tlb;
 
 extern int page_is_ram(unsigned long pfn);
 
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index e9834b2991d..cb5d3979480 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -10,7 +10,6 @@
 #include <linux/pci.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
-#include <asm-generic/pci-bridge.h>
 
 struct device_node;
 
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index 033137628e8..a0da88bf70c 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -94,14 +94,6 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
  */
 #define PCI_DMA_BUS_IS_PHYS     (1)
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                        struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                        struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
                         struct resource *res)
 {
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index b2af42311a1..3ef7b9cafec 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -94,8 +94,7 @@ static inline pte_t pte_mkspecial(pte_t pte)	{ return pte; }
 /* Start and end of the vmalloc area. */
 /* Make sure to map the vmalloc area above the pinned kernel memory area
    of 32Mb.  */
-#define VMALLOC_START   (CONFIG_KERNEL_START + \
-                                max(32 * 1024 * 1024UL, memory_size))
+#define VMALLOC_START   (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
 #define VMALLOC_END     ioremap_bot
 
 #endif /* __ASSEMBLY__ */
@@ -543,8 +542,6 @@ extern unsigned long iopa(unsigned long addr);
 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_page_range remap_page_range
-
 /*
  * No page table caches to initialise
  */
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index aa22511819d..0061aa13a34 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -41,7 +41,8 @@ extern void of_platform_reset_gpio_probe(void);
 void time_init(void);
 void init_IRQ(void);
 void machine_early_init(const char *cmdline, unsigned int ram,
-                        unsigned int fdt, unsigned int msr);
+                unsigned int fdt, unsigned int msr, unsigned int tlb0,
+                unsigned int tlb1);
 
 void machine_restart(char *cmd);
 void machine_shutdown(void);
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 072b0077abf..ef25f7538d4 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -80,7 +80,7 @@ extern unsigned long search_exception_table(unsigned long);
 static inline int ___range_ok(unsigned long addr, unsigned long size)
 {
         return ((addr < memory_start) ||
-                ((addr + size) > memory_end));
+                ((addr + size - 1) > (memory_start + memory_size - 1)));
 }
 
 #define __range_ok(addr, size) \
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
index 54194b28574..eab6abf5652 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -35,6 +35,8 @@ const struct cpu_ver_key cpu_ver_lookup[] = {
         {"8.00.b", 0x13},
         {"8.10.a", 0x14},
         {"8.20.a", 0x15},
+        {"8.20.b", 0x16},
+        {"8.30.a", 0x17},
         {NULL, 0},
 };
 
diff --git a/arch/microblaze/kernel/early_printk.c b/arch/microblaze/kernel/early_printk.c
index 8356e47631c..ec485876d0d 100644
--- a/arch/microblaze/kernel/early_printk.c
+++ b/arch/microblaze/kernel/early_printk.c
@@ -171,10 +171,24 @@ void __init remap_early_printk(void)
 {
         if (!early_console_initialized || !early_console)
                 return;
-        printk(KERN_INFO "early_printk_console remaping from 0x%x to ",
+        printk(KERN_INFO "early_printk_console remapping from 0x%x to ",
                                                                 base_addr);
         base_addr = (u32) ioremap(base_addr, PAGE_SIZE);
         printk(KERN_CONT "0x%x\n", base_addr);
+
+        /*
+         * Early console is on the top of skipped TLB entries
+         * decrease tlb_skip size ensure that hardcoded TLB entry will be
+         * used by generic algorithm
+         * FIXME check if early console mapping is on the top by rereading
+         * TLB entry and compare baseaddr
+         *  mts  rtlbx, (tlb_skip - 1)
+         *  nop
+         *  mfs  rX, rtlblo
+         *  nop
+         *  cmp rX, orig_base_addr
+         */
+        tlb_skip -= 1;
 }
 
 void __init disable_early_printk(void)
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 77320b8fc16..98b17f9f904 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -63,9 +63,7 @@ ENTRY(_start)
 real_start:
 #endif
 
-        mfs     r1, rmsr
-        andi    r1, r1, ~2
-        mts     rmsr, r1
+        mts     rmsr, r0
 /*
  * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
  * if the msrclr instruction is not enabled. We use this to detect
@@ -73,6 +71,7 @@ real_start:
  * r8 == 0 - msr instructions are implemented
  * r8 != 0 - msr instructions are not implemented
  */
+        mfs     r1, rmsr
         msrclr  r8, 0 /* clear nothing - just read msr for test */
         cmpu    r8, r8, r1 /* r1 must contain msr reg content */
 
@@ -96,7 +95,7 @@ big_endian:
 _prepare_copy_fdt:
         or      r11, r0, r0 /* incremment */
         ori     r4, r0, TOPHYS(_fdt_start)
-        ori     r3, r0, (0x4000 - 4)
+        ori     r3, r0, (0x8000 - 4)
 _copy_fdt:
         lw      r12, r7, r11 /* r12 = r7 + r11 */
         sw      r12, r4, r11 /* addr[r4 + r11] = r12 */
@@ -150,6 +149,7 @@ _copy_bram:
 _invalidate:
         mts     rtlbx, r3
         mts     rtlbhi, r0                      /* flush: ensure V is clear   */
+        mts     rtlblo, r0
         bgtid   r3, _invalidate         /* loop for all entries       */
         addik   r3, r3, -1
         /* sync */
@@ -169,6 +169,53 @@ _invalidate:
         addik   r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
         tophys(r4,r3)                   /* Load the kernel physical address */
 
+        /* start to do TLB calculation */
+        addik   r12, r0, _end
+        rsub    r12, r3, r12
+        addik   r12, r12, CONFIG_KERNEL_PAD /* that's the pad */
+
+        or r9, r0, r0 /* TLB0 = 0 */
+        or r10, r0, r0 /* TLB1 = 0 */
+
+        addik   r11, r12, -0x1000000
+        bgei    r11, GT16 /* size is greater than 16MB */
+        addik   r11, r12, -0x0800000
+        bgei    r11, GT8 /* size is greater than 8MB */
+        addik   r11, r12, -0x0400000
+        bgei    r11, GT4 /* size is greater than 4MB */
+        /* size is less than 4MB */
+        addik   r11, r12, -0x0200000
+        bgei    r11, GT2 /* size is greater than 2MB */
+        addik   r9, r0, 0x0100000 /* TLB0 must be 1MB */
+        addik   r11, r12, -0x0100000
+        bgei    r11, GT1 /* size is greater than 1MB */
+        /* TLB1 is 0 which is setup above */
+        bri tlb_end
+GT4: /* r11 contains the rest - will be either 1 or 4 */
+        ori r9, r0, 0x400000 /* TLB0 is 4MB */
+        bri TLB1
+GT16: /* TLB0 is 16MB */
+        addik   r9, r0, 0x1000000 /* means TLB0 is 16MB */
+TLB1:
+        /* must be used r2 because of substract if failed */
+        addik   r2, r11, -0x0400000
+        bgei    r2, GT20 /* size is greater than 16MB */
+        /* size is >16MB and <20MB */
+        addik   r11, r11, -0x0100000
+        bgei    r11, GT17 /* size is greater than 17MB */
+        /* kernel is >16MB and < 17MB */
+GT1:
+        addik   r10, r0, 0x0100000 /* means TLB1 is 1MB */
+        bri tlb_end
+GT2: /* TLB0 is 0 and TLB1 will be 4MB */
+GT17: /* TLB1 is 4MB - kernel size <20MB */
+        addik   r10, r0, 0x0400000 /* means TLB1 is 4MB */
+        bri tlb_end
+GT8: /* TLB0 is still zero that's why I can use only TLB1 */
+GT20: /* TLB1 is 16MB - kernel size >20MB */
+        addik   r10, r0, 0x1000000 /* means TLB1 is 16MB */
+tlb_end:
+
         /*
          * Configure and load two entries into TLB slots 0 and 1.
          * In case we are pinning TLBs, these are reserved in by the
@@ -178,28 +225,81 @@ _invalidate:
         andi    r4,r4,0xfffffc00        /* Mask off the real page number */
         ori     r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
 
+        /*
+         * TLB0 is always used - check if is not zero (r9 stores TLB0 value)
+         * if is use TLB1 value and clear it (r10 stores TLB1 value)
+         */
+        bnei    r9, tlb0_not_zero
+        add     r9, r10, r0
+        add     r10, r0, r0
+tlb0_not_zero:
+
+        /* look at the code below */
+        ori     r30, r0, 0x200
+        andi    r29, r9, 0x100000
+        bneid   r29, 1f
+        addik   r30, r30, 0x80
+        andi    r29, r9, 0x400000
+        bneid   r29, 1f
+        addik   r30, r30, 0x80
+        andi    r29, r9, 0x1000000
+        bneid   r29, 1f
+        addik   r30, r30, 0x80
+1:
         andi    r3,r3,0xfffffc00        /* Mask off the effective page number */
-        ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
+        ori     r3,r3,(TLB_VALID)
+        or      r3, r3, r30
 
-        mts     rtlbx,r0                /* TLB slow 0 */
+        /* Load tlb_skip size value which is index to first unused TLB entry */
+        lwi     r11, r0, TOPHYS(tlb_skip)
+        mts     rtlbx,r11               /* TLB slow 0 */
 
         mts     rtlblo,r4               /* Load the data portion of the entry */
         mts     rtlbhi,r3               /* Load the tag portion of the entry */
 
-        addik   r4, r4, 0x01000000      /* Map next 16 M entries */
-        addik   r3, r3, 0x01000000
+        /* Increase tlb_skip size */
+        addik   r11, r11, 1
+        swi     r11, r0, TOPHYS(tlb_skip)
+
+        /* TLB1 can be zeroes that's why we not setup it */
+        beqi    r10, jump_over2
+
+        /* look at the code below */
+        ori     r30, r0, 0x200
+        andi    r29, r10, 0x100000
+        bneid   r29, 1f
+        addik   r30, r30, 0x80
+        andi    r29, r10, 0x400000
+        bneid   r29, 1f
+        addik   r30, r30, 0x80
+        andi    r29, r10, 0x1000000
+        bneid   r29, 1f
+        addik   r30, r30, 0x80
+1:
+        addk    r4, r4, r9      /* previous addr + TLB0 size */
+        addk    r3, r3, r9
 
-        ori     r6,r0,1                 /* TLB slot 1 */
-        mts     rtlbx,r6
+        andi    r3,r3,0xfffffc00        /* Mask off the effective page number */
+        ori     r3,r3,(TLB_VALID)
+        or      r3, r3, r30
+
+        lwi     r11, r0, TOPHYS(tlb_skip)
+        mts     rtlbx, r11              /* r11 is used from TLB0 */
 
         mts     rtlblo,r4               /* Load the data portion of the entry */
         mts     rtlbhi,r3               /* Load the tag portion of the entry */
 
+        /* Increase tlb_skip size */
+        addik   r11, r11, 1
+        swi     r11, r0, TOPHYS(tlb_skip)
+
+jump_over2:
         /*
          * Load a TLB entry for LMB, since we need access to
          * the exception vectors, using a 4k real==virtual mapping.
          */
-        ori     r6,r0,3                 /* TLB slot 3 */
+        /* Use temporary TLB_ID for LMB - clear this temporary mapping later */
+        ori     r6, r0, MICROBLAZE_LMB_TLB_ID
         mts     rtlbx,r6
 
         ori     r4,r0,(TLB_WR | TLB_EX)
@@ -238,8 +338,8 @@ start_here:
          * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
          * the function.
          */
-        addik   r9, r0, machine_early_init
-        brald   r15, r9
+        addik   r11, r0, machine_early_init
+        brald   r15, r11
         nop
 
 #ifndef CONFIG_MMU
@@ -268,8 +368,7 @@ start_here:
 
         /* Load up the kernel context */
 kernel_load_context:
-        # Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away.
-        ori     r5,r0,3
+        ori     r5, r0, MICROBLAZE_LMB_TLB_ID
         mts     rtlbx,r5
         nop
         mts     rtlbhi,r0
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index e62be837960..aa510f450ac 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -820,19 +820,26 @@ ex_handler_done:
  *      Upon exit, we reload everything and RFI.
  * A common place to load the TLB.
  */
+.section .data
+.align 4
+.global tlb_skip
+        tlb_skip:
+                .long   MICROBLAZE_TLB_SKIP
         tlb_index:
-                .long   1 /* MS: storing last used tlb index */
+                /* MS: storing last used tlb index */
+                .long   MICROBLAZE_TLB_SIZE/2
+.previous
         finish_tlb_load:
                 /* MS: load the last used TLB index. */
                 lwi     r5, r0, TOPHYS(tlb_index)
                 addik   r5, r5, 1 /* MS: inc tlb_index -> use next one */
 
 /* MS: FIXME this is potential fault, because this is mask not count */
-                andi    r5, r5, (MICROBLAZE_TLB_SIZE-1)
+                andi    r5, r5, MICROBLAZE_TLB_SIZE - 1
                 ori     r6, r0, 1
                 cmp     r31, r5, r6
                 blti    r31, ex12
-                addik   r5, r6, 1
+                lwi     r5, r0, TOPHYS(tlb_skip)
         ex12:
                 /* MS: save back current TLB index */
                 swi     r5, r0, TOPHYS(tlb_index)
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index ad120672cee..6c54d4dcdec 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -151,8 +151,8 @@ void __init init_IRQ(void)
 #ifdef CONFIG_SELFMOD_INTC
         selfmod_function((int *) arr_func, intc_baseaddr);
 #endif
-        printk(KERN_INFO "XPS intc #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
-                intc_baseaddr, nr_irq, intr_mask);
+        printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
+                intc->name, intc_baseaddr, nr_irq, intr_mask);
 
         /*
          * Disable all external interrupts until they are
diff --git a/arch/microblaze/kernel/misc.S b/arch/microblaze/kernel/misc.S
index 206da3da361..1dafddeb8a0 100644
--- a/arch/microblaze/kernel/misc.S
+++ b/arch/microblaze/kernel/misc.S
@@ -29,16 +29,16 @@
 .type  _tlbia, @function
 .align 4;
 _tlbia:
-        addik   r12, r0, MICROBLAZE_TLB_SIZE - 1 /* flush all entries (63 - 3) */
+        lwi     r12, r0, tlb_skip;
         /* isync */
 _tlbia_1:
         mts     rtlbx, r12
         nop
         mts     rtlbhi, r0 /* flush: ensure V is clear */
         nop
-        addik   r11, r12, -2
+        rsubi   r11, r12, MICROBLAZE_TLB_SIZE - 1
         bneid   r11, _tlbia_1 /* loop for all entries */
-        addik   r12, r12, -1
+        addik   r12, r12, 1
         /* sync */
         rtsd    r15, 8
         nop
@@ -75,7 +75,7 @@ early_console_reg_tlb_alloc:
          * Load a TLB entry for the UART, so that microblaze_progress() can use
          * the UARTs nice and early.  We use a 4k real==virtual mapping.
          */
-        ori     r4, r0, MICROBLAZE_TLB_SIZE - 1
+        lwi     r4, r0, tlb_skip
         mts     rtlbx, r4 /* TLB slot 63 */
 
         or      r4,r5,r0
@@ -89,6 +89,11 @@ early_console_reg_tlb_alloc:
         nop
         mts     rtlbhi,r5 /* Load the tag portion of the entry */
         nop
+
+        lwi     r5, r0, tlb_skip
+        addik   r5, r5, 1
+        swi     r5, r0, tlb_skip
+
         rtsd    r15, 8
         nop
 
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 7a9f39efbf3..71af974aa24 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -94,8 +94,11 @@ inline unsigned get_romfs_len(unsigned *addr)
 }
 #endif  /* CONFIG_MTD_UCLINUX_EBSS */
 
+unsigned long kernel_tlb;
+
 void __init machine_early_init(const char *cmdline, unsigned int ram,
-                unsigned int fdt, unsigned int msr)
+                unsigned int fdt, unsigned int msr, unsigned int tlb0,
+                unsigned int tlb1)
 {
         unsigned long *src, *dst;
         unsigned int offset = 0;
@@ -142,6 +145,12 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         setup_early_printk(NULL);
 #endif
 
+        /* setup kernel_tlb after BSS cleaning
+         * Maybe worth to move to asm code */
+        kernel_tlb = tlb0 + tlb1;
+        /* printk("TLB1 0x%08x, TLB0 0x%08x, tlb 0x%x\n", tlb0,
+                                                        tlb1, kernel_tlb); */
+
         printk("Ramdisk addr 0x%08x, ", ram);
         if (fdt)
                 printk("FDT at 0x%08x\n", fdt);
@@ -196,6 +205,19 @@ static int microblaze_debugfs_init(void)
         return of_debugfs_root == NULL;
 }
 arch_initcall(microblaze_debugfs_init);
+
+static int __init debugfs_tlb(void)
+{
+        struct dentry *d;
+
+        if (!of_debugfs_root)
+                return -ENODEV;
+
+        d = debugfs_create_u32("tlb_skip", S_IRUGO, of_debugfs_root, &tlb_skip);
+        if (!d)
+                return -ENOMEM;
+}
+device_initcall(debugfs_tlb);
 #endif
 
 static int dflt_bus_notify(struct notifier_block *nb,
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index d3a38eca12d..522defa7d41 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -78,7 +78,7 @@ static inline void microblaze_timer0_start_periodic(unsigned long load_val)
          * !PWMA - disable pwm
          * TINT - clear interrupt status
          * ENT- enable timer itself
-         * EINT - enable interrupt
+         * ENIT - enable interrupt
          * !LOAD - clear the bit to let go
          * ARHT - auto reload
          * !CAPT - no external trigger
@@ -273,8 +273,8 @@ void __init time_init(void)
 #ifdef CONFIG_SELFMOD_TIMER
         selfmod_function((int *) arr_func, timer_baseaddr);
 #endif
-        printk(KERN_INFO "XPS timer #0 at 0x%08x, irq=%d\n",
-                timer_baseaddr, irq);
+        printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
+                timer->name, timer_baseaddr, irq);
 
         /* If there is clock-frequency property than use it */
         prop = of_get_property(timer, "clock-frequency", NULL);
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index ac0e1a5d478..109e9d86ade 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -44,7 +44,7 @@ SECTIONS {
         __fdt_blob : AT(ADDR(__fdt_blob) - LOAD_OFFSET) {
                 _fdt_start = . ;                /* place for fdt blob */
                 *(__fdt_blob) ;                 /* Any link-placed DTB */
-                . = _fdt_start + 0x4000;        /* Pad up to 16kbyte */
+                . = _fdt_start + 0x8000;        /* Pad up to 32kbyte */
                 _fdt_end = . ;
         }
 
diff --git a/arch/microblaze/mm/Makefile b/arch/microblaze/mm/Makefile
index 09c49ed8723..7313bd8acbb 100644
--- a/arch/microblaze/mm/Makefile
+++ b/arch/microblaze/mm/Makefile
@@ -5,3 +5,4 @@
 obj-y := consistent.o init.o
 
 obj-$(CONFIG_MMU) += pgtable.o mmu_context.o fault.o
+obj-$(CONFIG_HIGHMEM) += highmem.o
diff --git a/arch/microblaze/mm/highmem.c b/arch/microblaze/mm/highmem.c
new file mode 100644
index 00000000000..7d78838e8bf
--- /dev/null
+++ b/arch/microblaze/mm/highmem.c
@@ -0,0 +1,88 @@
+/*
+ * highmem.c: virtual kernel memory mappings for high memory
+ *
+ * PowerPC version, stolen from the i386 version.
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terrabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ *
+ * Reworked for PowerPC by various contributors. Moved from
+ * highmem.h by Benjamin Herrenschmidt (c) 2009 IBM Corp.
+ */
+
+#include <linux/highmem.h>
+#include <linux/module.h>
+
+/*
+ * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
+ * gives a more generic (and caching) interface. But kmap_atomic can
+ * be used in IRQ contexts, so in some (very limited) cases we need
+ * it.
+ */
+#include <asm/tlbflush.h>
+
+void *kmap_atomic_prot(struct page *page, pgprot_t prot)
+{
+
+        unsigned long vaddr;
+        int idx, type;
+
+        /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
+        pagefault_disable();
+        if (!PageHighMem(page))
+                return page_address(page);
+
+
+        type = kmap_atomic_idx_push();
+        idx = type + KM_TYPE_NR*smp_processor_id();
+        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+#ifdef CONFIG_DEBUG_HIGHMEM
+        BUG_ON(!pte_none(*(kmap_pte-idx)));
+#endif
+        set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
+        local_flush_tlb_page(NULL, vaddr);
+
+        return (void *) vaddr;
+}
+EXPORT_SYMBOL(kmap_atomic_prot);
+
+void __kunmap_atomic(void *kvaddr)
+{
+        unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
+        int type;
+
+        if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
+                pagefault_enable();
+                return;
+        }
+
+        type = kmap_atomic_idx();
+#ifdef CONFIG_DEBUG_HIGHMEM
+        {
+                unsigned int idx;
+
+                idx = type + KM_TYPE_NR * smp_processor_id();
+                BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
+
+                /*
+                 * force other mappings to Oops if they'll try to access
+                 * this pte without first remap it
+                 */
+                pte_clear(&init_mm, vaddr, kmap_pte-idx);
+                local_flush_tlb_page(NULL, vaddr);
+        }
+#endif
+        kmap_atomic_idx_pop();
+        pagefault_enable();
+}
+EXPORT_SYMBOL(__kunmap_atomic);
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 565d193c7eb..ce80823051b 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -24,6 +24,7 @@
 #include <asm/pgalloc.h>
 #include <asm/sections.h>
 #include <asm/tlb.h>
+#include <asm/fixmap.h>
 
 /* Use for MMU and noMMU because of PCI generic code */
 int mem_init_done;
@@ -44,9 +45,56 @@ char *klimit = _end;
  */
 unsigned long memory_start;
 EXPORT_SYMBOL(memory_start);
-unsigned long memory_end; /* due to mm/nommu.c */
 unsigned long memory_size;
 EXPORT_SYMBOL(memory_size);
+unsigned long lowmem_size;
+
+#ifdef CONFIG_HIGHMEM
+pte_t *kmap_pte;
+EXPORT_SYMBOL(kmap_pte);
+pgprot_t kmap_prot;
+EXPORT_SYMBOL(kmap_prot);
+
+static inline pte_t *virt_to_kpte(unsigned long vaddr)
+{
+        return pte_offset_kernel(pmd_offset(pgd_offset_k(vaddr),
+                        vaddr), vaddr);
+}
+
+static void __init highmem_init(void)
+{
+        pr_debug("%x\n", (u32)PKMAP_BASE);
+        map_page(PKMAP_BASE, 0, 0);     /* XXX gross */
+        pkmap_page_table = virt_to_kpte(PKMAP_BASE);
+
+        kmap_pte = virt_to_kpte(__fix_to_virt(FIX_KMAP_BEGIN));
+        kmap_prot = PAGE_KERNEL;
+}
+
+static unsigned long highmem_setup(void)
+{
+        unsigned long pfn;
+        unsigned long reservedpages = 0;
+
+        for (pfn = max_low_pfn; pfn < max_pfn; ++pfn) {
+                struct page *page = pfn_to_page(pfn);
+
+                /* FIXME not sure about */
+                if (memblock_is_reserved(pfn << PAGE_SHIFT))
+                        continue;
+                ClearPageReserved(page);
+                init_page_count(page);
+                __free_page(page);
+                totalhigh_pages++;
+                reservedpages++;
+        }
+        totalram_pages += totalhigh_pages;
+        printk(KERN_INFO "High memory: %luk\n",
+                                        totalhigh_pages << (PAGE_SHIFT-10));
+
+        return reservedpages;
+}
+#endif /* CONFIG_HIGHMEM */
 
 /*
  * paging_init() sets up the page tables - in fact we've already done this.
@@ -54,17 +102,28 @@ EXPORT_SYMBOL(memory_size);
 static void __init paging_init(void)
 {
         unsigned long zones_size[MAX_NR_ZONES];
+#ifdef CONFIG_MMU
+        int idx;
+
+        /* Setup fixmaps */
+        for (idx = 0; idx < __end_of_fixed_addresses; idx++)
+                clear_fixmap(idx);
+#endif
 
         /* Clean every zones */
         memset(zones_size, 0, sizeof(zones_size));
 
-        /*
-         * old: we can DMA to/from any address.put all page into ZONE_DMA
-         * We use only ZONE_NORMAL
-         */
-        zones_size[ZONE_NORMAL] = max_mapnr;
+#ifdef CONFIG_HIGHMEM
+        highmem_init();
 
-        free_area_init(zones_size);
+        zones_size[ZONE_DMA] = max_low_pfn;
+        zones_size[ZONE_HIGHMEM] = max_pfn;
+#else
+        zones_size[ZONE_DMA] = max_pfn;
+#endif
+
+        /* We don't have holes in memory map */
+        free_area_init_nodes(zones_size);
 }
 
 void __init setup_memory(void)
@@ -78,32 +137,31 @@ void __init setup_memory(void)
         /* Find main memory where is the kernel */
         for_each_memblock(memory, reg) {
                 memory_start = (u32)reg->base;
-                memory_end = (u32) reg->base + reg->size;
+                lowmem_size = reg->size;
                 if ((memory_start <= (u32)_text) &&
-                                        ((u32)_text <= memory_end)) {
-                        memory_size = memory_end - memory_start;
+                        ((u32)_text <= (memory_start + lowmem_size - 1))) {
+                        memory_size = lowmem_size;
                         PAGE_OFFSET = memory_start;
-                        printk(KERN_INFO "%s: Main mem: 0x%x-0x%x, "
+                        printk(KERN_INFO "%s: Main mem: 0x%x, "
                                 "size 0x%08x\n", __func__, (u32) memory_start,
-                                        (u32) memory_end, (u32) memory_size);
+                                        (u32) memory_size);
                         break;
                 }
         }
 
-        if (!memory_start || !memory_end) {
-                panic("%s: Missing memory setting 0x%08x-0x%08x\n",
-                        __func__, (u32) memory_start, (u32) memory_end);
+        if (!memory_start || !memory_size) {
+                panic("%s: Missing memory setting 0x%08x, size=0x%08x\n",
+                        __func__, (u32) memory_start, (u32) memory_size);
         }
 
         /* reservation of region where is the kernel */
         kernel_align_start = PAGE_DOWN((u32)_text);
         /* ALIGN can be remove because _end in vmlinux.lds.S is align */
         kernel_align_size = PAGE_UP((u32)klimit) - kernel_align_start;
-        memblock_reserve(kernel_align_start, kernel_align_size);
-        printk(KERN_INFO "%s: kernel addr=0x%08x-0x%08x size=0x%08x\n",
+        printk(KERN_INFO "%s: kernel addr:0x%08x-0x%08x size=0x%08x\n",
                 __func__, kernel_align_start, kernel_align_start
                         + kernel_align_size, kernel_align_size);
-
+        memblock_reserve(kernel_align_start, kernel_align_size);
 #endif
         /*
          * Kernel:
@@ -120,11 +178,13 @@ void __init setup_memory(void)
         min_low_pfn = memory_start >> PAGE_SHIFT; /* minimum for allocation */
         /* RAM is assumed contiguous */
         num_physpages = max_mapnr = memory_size >> PAGE_SHIFT;
-        max_pfn = max_low_pfn = memory_end >> PAGE_SHIFT;
+        max_low_pfn = ((u64)memory_start + (u64)lowmem_size) >> PAGE_SHIFT;
+        max_pfn = ((u64)memory_start + (u64)memory_size) >> PAGE_SHIFT;
 
         printk(KERN_INFO "%s: max_mapnr: %#lx\n", __func__, max_mapnr);
         printk(KERN_INFO "%s: min_low_pfn: %#lx\n", __func__, min_low_pfn);
         printk(KERN_INFO "%s: max_low_pfn: %#lx\n", __func__, max_low_pfn);
+        printk(KERN_INFO "%s: max_pfn: %#lx\n", __func__, max_pfn);
 
         /*
          * Find an area to use for the bootmem bitmap.
@@ -137,15 +197,39 @@ void __init setup_memory(void)
                 PFN_UP(TOPHYS((u32)klimit)), min_low_pfn, max_low_pfn);
         memblock_reserve(PFN_UP(TOPHYS((u32)klimit)) << PAGE_SHIFT, map_size);
 
+        /* Add active regions with valid PFNs */
+        for_each_memblock(memory, reg) {
+                unsigned long start_pfn, end_pfn;
+
+                start_pfn = memblock_region_memory_base_pfn(reg);
+                end_pfn = memblock_region_memory_end_pfn(reg);
+                memblock_set_node(start_pfn << PAGE_SHIFT,
+                                        (end_pfn - start_pfn) << PAGE_SHIFT, 0);
+        }
+
         /* free bootmem is whole main memory */
-        free_bootmem(memory_start, memory_size);
+        free_bootmem_with_active_regions(0, max_low_pfn);
 
         /* reserve allocate blocks */
         for_each_memblock(reserved, reg) {
-                pr_debug("reserved - 0x%08x-0x%08x\n",
-                         (u32) reg->base, (u32) reg->size);
-                reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
+                unsigned long top = reg->base + reg->size - 1;
+
+                pr_debug("reserved - 0x%08x-0x%08x, %lx, %lx\n",
+                         (u32) reg->base, (u32) reg->size, top,
+                                                memory_start + lowmem_size - 1);
+
+                if (top <= (memory_start + lowmem_size - 1)) {
+                        reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
+                } else if (reg->base < (memory_start + lowmem_size - 1)) {
+                        unsigned long trunc_size = memory_start + lowmem_size -
+                                                                reg->base;
+                        reserve_bootmem(reg->base, trunc_size, BOOTMEM_DEFAULT);
+                }
         }
+
+        /* XXX need to clip this if using highmem? */
+        sparse_memory_present_with_active_regions(0);
+
 #ifdef CONFIG_MMU
         init_bootmem_done = 1;
 #endif
@@ -190,13 +274,58 @@ void free_initmem(void)
 
 void __init mem_init(void)
 {
-        high_memory = (void *)__va(memory_end);
+        pg_data_t *pgdat;
+        unsigned long reservedpages = 0, codesize, initsize, datasize, bsssize;
+
+        high_memory = (void *)__va(memory_start + lowmem_size - 1);
+
         /* this will put all memory onto the freelists */
         totalram_pages += free_all_bootmem();
 
-        printk(KERN_INFO "Memory: %luk/%luk available\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               num_physpages << (PAGE_SHIFT-10));
+        for_each_online_pgdat(pgdat) {
+                unsigned long i;
+                struct page *page;
+
+                for (i = 0; i < pgdat->node_spanned_pages; i++) {
+                        if (!pfn_valid(pgdat->node_start_pfn + i))
+                                continue;
+                        page = pgdat_page_nr(pgdat, i);
+                        if (PageReserved(page))
+                                reservedpages++;
+                }
+        }
+
+#ifdef CONFIG_HIGHMEM
+        reservedpages -= highmem_setup();
+#endif
+
+        codesize = (unsigned long)&_sdata - (unsigned long)&_stext;
+        datasize = (unsigned long)&_edata - (unsigned long)&_sdata;
+        initsize = (unsigned long)&__init_end - (unsigned long)&__init_begin;
+        bsssize = (unsigned long)&__bss_stop - (unsigned long)&__bss_start;
+
+        pr_info("Memory: %luk/%luk available (%luk kernel code, "
+                "%luk reserved, %luk data, %luk bss, %luk init)\n",
+                nr_free_pages() << (PAGE_SHIFT-10),
+                num_physpages << (PAGE_SHIFT-10),
+                codesize >> 10,
+                reservedpages << (PAGE_SHIFT-10),
+                datasize >> 10,
+                bsssize >> 10,
+                initsize >> 10);
+
+#ifdef CONFIG_MMU
+        pr_info("Kernel virtual memory layout:\n");
+        pr_info("  * 0x%08lx..0x%08lx  : fixmap\n", FIXADDR_START, FIXADDR_TOP);
+#ifdef CONFIG_HIGHMEM
+        pr_info("  * 0x%08lx..0x%08lx  : highmem PTEs\n",
+                PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP));
+#endif /* CONFIG_HIGHMEM */
+        pr_info("  * 0x%08lx..0x%08lx  : early ioremap\n",
+                ioremap_bot, ioremap_base);
+        pr_info("  * 0x%08lx..0x%08lx  : vmalloc & ioremap\n",
+                (unsigned long)VMALLOC_START, VMALLOC_END);
+#endif
         mem_init_done = 1;
 }
 
@@ -226,7 +355,6 @@ static void mm_cmdline_setup(void)
                 maxmem = memparse(p, &p);
                 if (maxmem && memory_size > maxmem) {
                         memory_size = maxmem;
-                        memory_end = memory_start + memory_size;
                         memblock.memory.regions[0].size = memory_size;
                 }
         }
@@ -270,15 +398,26 @@ asmlinkage void __init mmu_init(void)
                 machine_restart(NULL);
         }
 
-        if ((u32) memblock.memory.regions[0].size < 0x1000000) {
-                printk(KERN_EMERG "Memory must be greater than 16MB\n");
+        if ((u32) memblock.memory.regions[0].size < 0x400000) {
+                printk(KERN_EMERG "Memory must be greater than 4MB\n");
+                machine_restart(NULL);
+        }
+
+        if ((u32) memblock.memory.regions[0].size < kernel_tlb) {
+                printk(KERN_EMERG "Kernel size is greater than memory node\n");
                 machine_restart(NULL);
         }
+
         /* Find main memory where the kernel is */
         memory_start = (u32) memblock.memory.regions[0].base;
-        memory_end = (u32) memblock.memory.regions[0].base +
-                                (u32) memblock.memory.regions[0].size;
-        memory_size = memory_end - memory_start;
+        lowmem_size = memory_size = (u32) memblock.memory.regions[0].size;
+
+        if (lowmem_size > CONFIG_LOWMEM_SIZE) {
+                lowmem_size = CONFIG_LOWMEM_SIZE;
+#ifndef CONFIG_HIGHMEM
+                memory_size = lowmem_size;
+#endif
+        }
 
         mm_cmdline_setup(); /* FIXME parse args from command line - not used */
 
@@ -305,15 +444,20 @@ asmlinkage void __init mmu_init(void)
         /* Map in all of RAM starting at CONFIG_KERNEL_START */
         mapin_ram();
 
-#ifdef CONFIG_HIGHMEM_START_BOOL
-        ioremap_base = CONFIG_HIGHMEM_START;
+        /* Extend vmalloc and ioremap area as big as possible */
+#ifdef CONFIG_HIGHMEM
+        ioremap_base = ioremap_bot = PKMAP_BASE;
 #else
-        ioremap_base = 0xfe000000UL;    /* for now, could be 0xfffff000 */
-#endif /* CONFIG_HIGHMEM_START_BOOL */
-        ioremap_bot = ioremap_base;
+        ioremap_base = ioremap_bot = FIXADDR_START;
+#endif
 
         /* Initialize the context management stuff */
         mmu_context_init();
+
+        /* Shortly after that, the entire linear mapping will be available */
+        /* This will also cause that unflatten device tree will be allocated
+         * inside 768MB limit */
+        memblock_set_current_limit(memory_start + lowmem_size - 1);
 }
 
 /* This is only called until mem_init is done. */
@@ -324,11 +468,11 @@ void __init *early_get_page(void)
                 p = alloc_bootmem_pages(PAGE_SIZE);
         } else {
                 /*
-                 * Mem start + 32MB -> here is limit
+                 * Mem start + kernel_tlb -> here is limit
                  * because of mem mapping from head.S
                  */
                 p = __va(memblock_alloc_base(PAGE_SIZE, PAGE_SIZE,
-                                        memory_start + 0x2000000));
+                                        memory_start + kernel_tlb));
         }
         return p;
 }
diff --git a/arch/microblaze/mm/pgtable.c b/arch/microblaze/mm/pgtable.c
index 59bf2335a4c..d1c06d07fed 100644
--- a/arch/microblaze/mm/pgtable.c
+++ b/arch/microblaze/mm/pgtable.c
@@ -37,6 +37,7 @@
 #include <linux/io.h>
 #include <asm/mmu.h>
 #include <asm/sections.h>
+#include <asm/fixmap.h>
 
 #define flush_HPTE(X, va, pg)   _tlbie(va)
 
@@ -44,11 +45,6 @@ unsigned long ioremap_base;
 unsigned long ioremap_bot;
 EXPORT_SYMBOL(ioremap_bot);
 
-/* The maximum lowmem defaults to 768Mb, but this can be configured to
- * another value.
- */
-#define MAX_LOW_MEM     CONFIG_LOWMEM_SIZE
-
 #ifndef CONFIG_SMP
 struct pgtable_cache_struct quicklists;
 #endif
@@ -80,7 +76,7 @@ static void __iomem *__ioremap(phys_addr_t addr, unsigned long size,
                 !(p >= virt_to_phys((unsigned long)&__bss_stop) &&
                 p < virt_to_phys((unsigned long)__bss_stop))) {
                 printk(KERN_WARNING "__ioremap(): phys addr "PTE_FMT
-                        " is RAM lr %p\n", (unsigned long)p,
+                        " is RAM lr %pf\n", (unsigned long)p,
                         __builtin_return_address(0));
                 return NULL;
         }
@@ -171,7 +167,7 @@ void __init mapin_ram(void)
 
         v = CONFIG_KERNEL_START;
         p = memory_start;
-        for (s = 0; s < memory_size; s += PAGE_SIZE) {
+        for (s = 0; s < lowmem_size; s += PAGE_SIZE) {
                 f = _PAGE_PRESENT | _PAGE_ACCESSED |
                                 _PAGE_SHARED | _PAGE_HWEXEC;
                 if ((char *) v < _stext || (char *) v >= _etext)
@@ -254,3 +250,13 @@ __init_refok pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
         }
         return pte;
 }
+
+void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t flags)
+{
+        unsigned long address = __fix_to_virt(idx);
+
+        if (idx >= __end_of_fixed_addresses)
+                BUG();
+
+        map_page(address, phys, pgprot_val(flags));
+}
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 85f2ac1230a..d10403dadd2 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -46,9 +46,6 @@ static int global_phb_number;		/* Global phb counter */
 /* ISA Memory physical address */
 resource_size_t isa_mem_base;
 
-/* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
-unsigned int pci_flags;
-
 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 
 unsigned long isa_io_base;
@@ -833,64 +830,7 @@ int pci_proc_domain(struct pci_bus *bus)
 {
         struct pci_controller *hose = pci_bus_to_host(bus);
 
-        if (!(pci_flags & PCI_ENABLE_PROC_DOMAINS))
-                return 0;
-        if (pci_flags & PCI_COMPAT_DOMAIN_0)
-                return hose->global_number != 0;
-        return 1;
-}
-
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        region->start = (res->start - offset) & mask;
-        region->end = (res->end - offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-        res->start = (region->start + offset) & mask;
-        res->end = (region->end + offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/* Fixup a bus resource into a linux resource */
-static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
-{
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        res->start = (res->start + offset) & mask;
-        res->end = (res->end + offset) & mask;
+        return 0;
 }
 
 /* This header fixup will do the resource fixup for all devices as they are
@@ -910,13 +850,7 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
                 struct resource *res = dev->resource + i;
                 if (!res->flags)
                         continue;
-                /* On platforms that have PCI_PROBE_ONLY set, we don't
-                 * consider 0 as an unassigned BAR value. It's technically
-                 * a valid value, but linux doesn't like it... so when we can
-                 * re-assign things, we do so, but if we can't, we keep it
-                 * around and hope for the best...
-                 */
-                if (res->start == 0 && !(pci_flags & PCI_PROBE_ONLY)) {
+                if (res->start == 0) {
                         pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
                                                         "is unassigned\n",
                                  pci_name(dev), i,
@@ -929,18 +863,11 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
                         continue;
                 }
 
-                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
+                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
                          pci_name(dev), i,
                          (unsigned long long)res->start,\
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
-
-                fixup_resource(res, dev);
-
-                pr_debug("PCI:%s            %016llx-%016llx\n",
-                         pci_name(dev),
-                         (unsigned long long)res->start,
-                         (unsigned long long)res->end);
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
@@ -959,10 +886,6 @@ static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
         u16 command;
         int i;
 
-        /* We don't do anything if PCI_PROBE_ONLY is set */
-        if (pci_flags & PCI_PROBE_ONLY)
-                return 0;
-
         /* Job is a bit different between memory and IO */
         if (res->flags & IORESOURCE_MEM) {
                 /* If the BAR is non-0 (res != pci_mem_offset) then it's
@@ -1037,9 +960,6 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
 
-                /* Perform fixup */
-                fixup_resource(res, dev);
-
                 /* Try to detect uninitialized P2P bridge resources,
                  * and clear them out so they get re-assigned later
                  */
@@ -1107,9 +1027,6 @@ EXPORT_SYMBOL(pcibios_fixup_bus);
 
 static int skip_isa_ioresource_align(struct pci_dev *dev)
 {
-        if ((pci_flags & PCI_CAN_SKIP_ISA_ALIGN) &&
-            !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
-                return 1;
         return 0;
 }
 
@@ -1236,8 +1153,6 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
                          * and as such ensure proper re-allocation
                          * later.
                          */
-                        if (pci_flags & PCI_REASSIGN_ALL_RSRC)
-                                goto clear_resource;
                         pr = pci_find_parent_resource(bus->self, res);
                         if (pr == res) {
                                 /* this happens when the generic PCI
@@ -1422,27 +1337,19 @@ void __init pcibios_resource_survey(void)
         list_for_each_entry(b, &pci_root_buses, node)
                 pcibios_allocate_bus_resources(b);
 
-        if (!(pci_flags & PCI_REASSIGN_ALL_RSRC)) {
-                pcibios_allocate_resources(0);
-                pcibios_allocate_resources(1);
-        }
+        pcibios_allocate_resources(0);
+        pcibios_allocate_resources(1);
 
         /* Before we start assigning unassigned resource, we try to reserve
          * the low IO area and the VGA memory area if they intersect the
          * bus available resources to avoid allocating things on top of them
          */
-        if (!(pci_flags & PCI_PROBE_ONLY)) {
-                list_for_each_entry(b, &pci_root_buses, node)
-                        pcibios_reserve_legacy_regions(b);
-        }
+        list_for_each_entry(b, &pci_root_buses, node)
+                pcibios_reserve_legacy_regions(b);
 
-        /* Now, if the platform didn't decide to blindly trust the firmware,
-         * we proceed to assigning things that were left unassigned
-         */
-        if (!(pci_flags & PCI_PROBE_ONLY)) {
-                pr_debug("PCI: Assigning unassigned resources...\n");
-                pci_assign_unassigned_resources();
-        }
+        /* Now proceed to assigning things that were left unassigned */
+        pr_debug("PCI: Assigning unassigned resources...\n");
+        pci_assign_unassigned_resources();
 }
 
 #ifdef CONFIG_HOTPLUG
@@ -1535,7 +1442,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                 res->end = res->start + IO_SPACE_LIMIT;
                 res->flags = IORESOURCE_IO;
         }
-        pci_add_resource(resources, res);
+        pci_add_resource_offset(resources, res, hose->io_base_virt - _IO_BASE);
 
         pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
                  (unsigned long long)res->start,
@@ -1558,7 +1465,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                         res->flags = IORESOURCE_MEM;
 
                 }
-                pci_add_resource(resources, res);
+                pci_add_resource_offset(resources, res, hose->pci_mem_offset);
 
                 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
                         i, (unsigned long long)res->start,
diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index 9fdf07e50f1..c0122a1dc58 100644
--- a/arch/mips/fw/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
@@ -7,6 +7,7 @@
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  */
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c
index 788060a53dc..54a33c756f6 100644
--- a/arch/mips/fw/arc/identify.c
+++ b/arch/mips/fw/arc/identify.c
@@ -11,6 +11,7 @@
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  */
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
diff --git a/arch/mips/include/asm/mman.h b/arch/mips/include/asm/mman.h
index 785b4ea4ec3..46d3da0d4b9 100644
--- a/arch/mips/include/asm/mman.h
+++ b/arch/mips/include/asm/mman.h
@@ -80,6 +80,10 @@
 #define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   16              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     17              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 576397c6992..fcd4060f642 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -92,6 +92,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 #include <asm/scatterlist.h>
 #include <linux/string.h>
 #include <asm/io.h>
+#include <asm-generic/pci-bridge.h>
 
 struct pci_dev;
 
@@ -112,12 +113,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-        struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
@@ -145,8 +140,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 #define arch_setup_msi_irqs arch_setup_msi_irqs
 #endif
 
-extern int pci_probe_only;
-
 extern char * (*pcibios_plat_setup)(char *str);
 
 #endif /* _ASM_PCI_H */
diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c
index e5cdfd603f8..0f1af58b036 100644
--- a/arch/mips/kernel/vdso.c
+++ b/arch/mips/kernel/vdso.c
@@ -88,8 +88,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         ret = install_special_mapping(mm, addr, PAGE_SIZE,
                                       VM_READ|VM_EXEC|
-                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                       &vdso_page);
 
         if (ret)
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index acacd1407c6..9553b14002d 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -51,67 +51,6 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
-static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
-                                                       struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = hose->io_offset;
-        struct resource orig = *res;
-
-        if (!(res->flags & IORESOURCE_IO) ||
-            !(res->flags & IORESOURCE_PCI_FIXED))
-                return;
-
-        res->start -= offset;
-        res->end -= offset;
-        dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
-                   &orig, res);
-}
-
-static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
-{
-        u32 class;
-        u8 progif;
-
-        /*
-         * If the IDE controller is in legacy mode, pci_setup_device() fills in
-         * the resources with the legacy addresses that normally appear on the
-         * PCI bus, just as if we had read them from a BAR.
-         *
-         * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
-         * will never appear on the PCI bus because it converts memory accesses
-         * in the PCI I/O region (which is never at address zero) into I/O port
-         * accesses with no address translation.
-         *
-         * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
-         * to physical address 0x100001f0 will become a PCI access to I/O port
-         * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
-         * but the VT82C586 IDE controller does respond at 0x100001f0 because
-         * it only decodes the low 24 bits of the address.
-         *
-         * When this quirk runs, the pci_dev resources should contain bus
-         * addresses, not Linux I/O port numbers, so convert legacy addresses
-         * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
-         * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
-         */
-        class = dev->class >> 8;
-        if (class != PCI_CLASS_STORAGE_IDE)
-                return;
-
-        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
-        if ((progif & 1) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
-        }
-        if ((progif & 4) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
-        }
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
-          cobalt_legacy_ide_fixup);
-
 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index af8c3199696..37b52dc3d27 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -204,7 +204,7 @@ static int __init bcm1480_pcibios_init(void)
         uint64_t reg;
 
         /* CFE will assign PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         /* Avoid ISA compat ranges.  */
         PCIBIOS_MIN_IO = 0x00008000UL;
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 193e9494f98..0fbe4c0c170 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -50,7 +50,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
         bridge_t *bridge;
         int slot;
 
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         printk("a bridge\n");
 
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index be1e1afe12c..030c77e7926 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -270,7 +270,8 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
 {
         struct ltq_pci_data *ltq_pci_data =
                 (struct ltq_pci_data *) pdev->dev.platform_data;
-        pci_probe_only = 0;
+
+        pci_clear_flags(PCI_PROBE_ONLY);
         ltq_pci_irq_map = ltq_pci_data->irq;
         ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
         ltq_pci_mapped_cfg =
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 1711e8e101b..dd97f3a83ba 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -213,7 +213,7 @@ static int __init sb1250_pcibios_init(void)
         uint64_t reg;
 
         /* CFE will assign PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         /* Avoid ISA compat ranges.  */
         PCIBIOS_MIN_IO = 0x00008000UL;
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 3d701a962ef..1644805a673 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -292,7 +292,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 static int __init pcibios_init(void)
 {
         /* PSB assigns PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
         pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
 
         /* Extend IO port for memory mapped io */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 15521505ebe..0514866fa92 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -20,16 +20,9 @@
 #include <asm/cpu-info.h>
 
 /*
- * Indicate whether we respect the PCI setup left by the firmware.
- *
- * Make this long-lived  so that we know when shutting down
- * whether we probed only or not.
+ * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
+ * assignments.
  */
-int pci_probe_only;
-
-#define PCI_ASSIGN_ALL_BUSSES   1
-
-unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
 
 /*
  * The PCI controller list.
@@ -92,11 +85,12 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
         if (!hose->iommu)
                 PCI_DMA_BUS_IS_PHYS = 1;
 
-        if (hose->get_busno && pci_probe_only)
+        if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
                 next_busno = (*hose->get_busno)();
 
-        pci_add_resource(&resources, hose->mem_resource);
-        pci_add_resource(&resources, hose->io_resource);
+        pci_add_resource_offset(&resources,
+                                hose->mem_resource, hose->mem_offset);
+        pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
                                 &resources);
         if (!bus)
@@ -115,7 +109,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
                         need_domain_info = 1;
                 }
 
-                if (!pci_probe_only) {
+                if (!pci_has_flag(PCI_PROBE_ONLY)) {
                         pci_bus_size_bridges(bus);
                         pci_bus_assign_resources(bus);
                         pci_enable_bridges(bus);
@@ -241,7 +235,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 
 unsigned int pcibios_assign_all_busses(void)
 {
-        return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
+        return 1;
 }
 
 int pcibios_enable_device(struct pci_dev *dev, int mask)
@@ -254,42 +248,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return pcibios_plat_dev_init(dev);
 }
 
-static void pcibios_fixup_device_resources(struct pci_dev *dev,
-        struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        offset = hose->io_offset;
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = hose->mem_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end += offset;
-        }
-}
-
 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
-        /* Propagate hose info into the subordinate devices.  */
-
         struct pci_dev *dev = bus->self;
 
-        if (pci_probe_only && dev &&
+        if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
                 pci_read_bridge_bases(bus);
-                pcibios_fixup_device_resources(dev, bus);
-        }
-
-        list_for_each_entry(dev, &bus->devices, bus_list) {
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
         }
 }
 
@@ -299,40 +264,7 @@ pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void __devinit
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
 #ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 #endif
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 8f1c40d5817..3aa3de01715 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -5,6 +5,7 @@ config MN10300
         select GENERIC_IRQ_SHOW
         select HAVE_ARCH_TRACEHOOK
         select HAVE_ARCH_KGDB
+        select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER
 
 config AM33_2
         def_bool n
diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h
index 6095a28561d..8137c25c4e1 100644
--- a/arch/mn10300/include/asm/pci.h
+++ b/arch/mn10300/include/asm/pci.h
@@ -85,22 +85,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 /* implement the pci_ DMA API in terms of the generic device dma_ one */
 #include <asm-generic/pci-dma-compat.h>
 
-/**
- * pcibios_resource_to_bus - convert resource to PCI bus address
- * @dev: device which owns this resource
- * @region: converted bus-centric region (start,end)
- * @res: resource to convert
- *
- * Convert a resource to a PCI device bus address or bus window.
- */
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                                    struct pci_bus_region *region,
-                                    struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                                    struct resource *res,
-                                    struct pci_bus_region *region);
-
 static inline struct resource *
 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 {
diff --git a/arch/mn10300/include/asm/reset-regs.h b/arch/mn10300/include/asm/reset-regs.h
index 10c7502a113..8ca2a42d365 100644
--- a/arch/mn10300/include/asm/reset-regs.h
+++ b/arch/mn10300/include/asm/reset-regs.h
@@ -17,10 +17,6 @@
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_MN10300_WD_TIMER
-#define ARCH_HAS_NMI_WATCHDOG           /* See include/linux/nmi.h */
-#endif
-
 /*
  * watchdog timer registers
  */
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
index a7c5f08ca9f..6dce9fc2cf3 100644
--- a/arch/mn10300/unit-asb2305/pci.c
+++ b/arch/mn10300/unit-asb2305/pci.c
@@ -32,8 +32,7 @@ struct pci_ops *pci_root_ops;
  * insert specific PCI bus resources instead of using the platform-level bus
  * resources directly for the PCI root bus.
  *
- * These are configured and inserted by pcibios_init() and are attached to the
- * root bus by pcibios_fixup_bus().
+ * These are configured and inserted by pcibios_init().
  */
 static struct resource pci_ioport_resource = {
         .name   = "PCI IO",
@@ -78,52 +77,6 @@ static inline int __query(const struct pci_bus *bus, unsigned int devfn)
 }
 
 /*
- * translate Linuxcentric addresses to PCI bus addresses
- */
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        if (res->flags & IORESOURCE_IO) {
-                region->start = (res->start & 0x00ffffff);
-                region->end   = (res->end   & 0x00ffffff);
-        }
-
-        if (res->flags & IORESOURCE_MEM) {
-                region->start = (res->start & 0x03ffffff) | MEM_PAGING_REG;
-                region->end   = (res->end   & 0x03ffffff) | MEM_PAGING_REG;
-        }
-
-#if 0
-        printk(KERN_DEBUG "RES->BUS: %lx-%lx => %lx-%lx\n",
-               res->start, res->end, region->start, region->end);
-#endif
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-/*
- * translate PCI bus addresses to Linuxcentric addresses
- */
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        if (res->flags & IORESOURCE_IO) {
-                res->start = (region->start & 0x00ffffff) | 0xbe000000;
-                res->end   = (region->end   & 0x00ffffff) | 0xbe000000;
-        }
-
-        if (res->flags & IORESOURCE_MEM) {
-                res->start = (region->start & 0x03ffffff) | 0xb8000000;
-                res->end   = (region->end   & 0x03ffffff) | 0xb8000000;
-        }
-
-#if 0
-        printk(KERN_INFO "BUS->RES: %lx-%lx => %lx-%lx\n",
-               region->start, region->end, res->start, res->end);
-#endif
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/*
  *
  */
 static int pci_ampci_read_config_byte(struct pci_bus *bus, unsigned int devfn,
@@ -364,9 +317,6 @@ static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
                 if (!dev->resource[i].flags)
                         continue;
 
-                region.start = dev->resource[i].start;
-                region.end = dev->resource[i].end;
-                pcibios_bus_to_resource(dev, &dev->resource[i], &region);
                 if (is_valid_resource(dev, i))
                         pci_claim_resource(dev, i);
         }
@@ -397,6 +347,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
  */
 static int __init pcibios_init(void)
 {
+        resource_size_t io_offset, mem_offset;
         LIST_HEAD(resources);
 
         ioport_resource.start   = 0xA0000000;
@@ -420,8 +371,13 @@ static int __init pcibios_init(void)
         printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
                MEM_PAGING_REG);
 
-        pci_add_resource(&resources, &pci_ioport_resource);
-        pci_add_resource(&resources, &pci_iomem_resource);
+        io_offset = pci_ioport_resource.start -
+            (pci_ioport_resource.start & 0x00ffffff);
+        mem_offset = pci_iomem_resource.start -
+            ((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG);
+
+        pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset);
+        pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset);
         pci_root_bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL,
                                          &resources);
 
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index bc428b5f126..a4787197d8f 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -16,6 +16,7 @@ config OPENRISC
         select GENERIC_IRQ_SHOW
         select GENERIC_IOMAP
         select GENERIC_CPU_DEVICES
+        select GENERIC_ATOMIC64
 
 config MMU
         def_bool y
diff --git a/arch/openrisc/include/asm/page.h b/arch/openrisc/include/asm/page.h
index b041b344b22..108906f991d 100644
--- a/arch/openrisc/include/asm/page.h
+++ b/arch/openrisc/include/asm/page.h
@@ -71,9 +71,6 @@ typedef struct page *pgtable_t;
 #define __pgd(x)        ((pgd_t) { (x) })
 #define __pgprot(x)     ((pgprot_t) { (x) })
 
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
 #endif /* !__ASSEMBLY__ */
 
 
@@ -94,8 +91,7 @@ extern unsigned long memory_end;
 
 #define pfn_valid(pfn)          ((pfn) < max_mapnr)
 
-#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
-                                ((void *)(kaddr) < (void *)memory_end))
+#define virt_addr_valid(kaddr)  (pfn_valid(virt_to_pfn(kaddr)))
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
index 043505d7f68..14c900cfd30 100644
--- a/arch/openrisc/include/asm/pgtable.h
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -455,7 +455,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
  * No page table caches to initialise
  */
 #define pgtable_cache_init()            do { } while (0)
-#define io_remap_page_range             remap_page_range
 
 typedef pte_t *pte_addr_t;
 
diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h
index bb54c97b978..f7516fa78b5 100644
--- a/arch/openrisc/include/asm/processor.h
+++ b/arch/openrisc/include/asm/processor.h
@@ -81,8 +81,8 @@ extern inline void prepare_to_copy(struct task_struct *tsk)
 #define INIT_THREAD  { }
 
 
-#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->pc);
-#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->sp);
+#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->pc)
+#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->sp)
 
 
 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
index e612ce4512c..4651a737591 100644
--- a/arch/openrisc/include/asm/ptrace.h
+++ b/arch/openrisc/include/asm/ptrace.h
@@ -73,9 +73,13 @@ struct pt_regs {
                 };
         };
         long  pc;
+        /* For restarting system calls:
+         * Set to syscall number for syscall exceptions,
+         * -1 for all other exceptions.
+         */
         long  orig_gpr11;       /* For restarting system calls */
-        long  syscallno;        /* Syscall number (used by strace) */
         long dummy;             /* Cheap alignment fix */
+        long dummy2;            /* Cheap alignment fix */
 };
 
 /* TODO: Rename this to REDZONE because that's what it is */
diff --git a/arch/openrisc/include/asm/syscall.h b/arch/openrisc/include/asm/syscall.h
index 9f0337055d2..b752bb67891 100644
--- a/arch/openrisc/include/asm/syscall.h
+++ b/arch/openrisc/include/asm/syscall.h
@@ -25,7 +25,7 @@
 static inline int
 syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
 {
-        return regs->syscallno ? regs->syscallno : -1;
+        return regs->orig_gpr11;
 }
 
 static inline void
@@ -50,10 +50,7 @@ static inline void
 syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
                          int error, long val)
 {
-        if (error)
-                regs->gpr[11] = -error;
-        else
-                regs->gpr[11] = val;
+        regs->gpr[11] = (long) error ?: val;
 }
 
 static inline void
diff --git a/arch/openrisc/include/asm/uaccess.h b/arch/openrisc/include/asm/uaccess.h
index c310e45b538..f5abaa0ffc3 100644
--- a/arch/openrisc/include/asm/uaccess.h
+++ b/arch/openrisc/include/asm/uaccess.h
@@ -26,7 +26,6 @@
 #include <linux/thread_info.h>
 #include <linux/prefetch.h>
 #include <linux/string.h>
-#include <linux/thread_info.h>
 #include <asm/page.h>
 
 #define VERIFY_READ     0
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index d5f9c35a583..6e61af8682b 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -95,7 +95,6 @@ handler:							;\
         /* r1, EPCR, ESR a already saved */                     ;\
         l.sw    PT_GPR2(r1),r2                                  ;\
         l.sw    PT_GPR3(r1),r3                                  ;\
-        l.sw    PT_ORIG_GPR11(r1),r11                           ;\
         /* r4 already save */                                   ;\
         l.sw    PT_GPR5(r1),r5                                  ;\
         l.sw    PT_GPR6(r1),r6                                  ;\
@@ -125,7 +124,9 @@ handler:							;\
         /* r30 already save */                                  ;\
 /*        l.sw    PT_GPR30(r1),r30*/                                    ;\
         l.sw    PT_GPR31(r1),r31                                        ;\
-        l.sw    PT_SYSCALLNO(r1),r0
+        /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
+        l.addi  r30,r0,-1                                       ;\
+        l.sw    PT_ORIG_GPR11(r1),r30
 
 #define UNHANDLED_EXCEPTION(handler,vector)                     \
         .global handler                                         ;\
@@ -133,7 +134,6 @@ handler:							;\
         /* r1, EPCR, ESR already saved */                       ;\
         l.sw    PT_GPR2(r1),r2                                  ;\
         l.sw    PT_GPR3(r1),r3                                  ;\
-        l.sw    PT_ORIG_GPR11(r1),r11                           ;\
         l.sw    PT_GPR5(r1),r5                                  ;\
         l.sw    PT_GPR6(r1),r6                                  ;\
         l.sw    PT_GPR7(r1),r7                                  ;\
@@ -162,7 +162,9 @@ handler:							;\
         /* r31 already saved */                                 ;\
         l.sw    PT_GPR30(r1),r30                                        ;\
 /*        l.sw    PT_GPR31(r1),r31      */                              ;\
-        l.sw    PT_SYSCALLNO(r1),r0                             ;\
+        /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
+        l.addi  r30,r0,-1                                       ;\
+        l.sw    PT_ORIG_GPR11(r1),r30                           ;\
         l.addi  r3,r1,0                                         ;\
         /* r4 is exception EA */                                ;\
         l.addi  r5,r0,vector                                    ;\
@@ -554,6 +556,7 @@ ENTRY(_sys_call_handler)
         l.sw    PT_GPR9(r1),r9
         /* r10 already saved */
         l.sw    PT_GPR11(r1),r11
+        /* orig_gpr11 must be set for syscalls */
         l.sw    PT_ORIG_GPR11(r1),r11
         /* r12,r13 already saved */
 
@@ -567,9 +570,6 @@ ENTRY(_sys_call_handler)
         /* r30 is the only register we clobber in the fast path */
         /* r30 already saved */
 /*      l.sw    PT_GPR30(r1),r30 */
-        /* This is used by do_signal to determine whether to check for
-         * syscall restart or not */
-        l.sw    PT_SYSCALLNO(r1),r11
 
 _syscall_check_trace_enter:
         /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
@@ -731,7 +731,7 @@ _syscall_trace_enter:
          * so that we can do the syscall for real and return to the syscall
          * hot path.
          */
-        l.lwz   r11,PT_SYSCALLNO(r1)
+        l.lwz   r11,PT_GPR11(r1)
         l.lwz   r3,PT_GPR3(r1)
         l.lwz   r4,PT_GPR4(r1)
         l.lwz   r5,PT_GPR5(r1)
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index c75018d2264..1088b5fca3b 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -26,6 +26,7 @@
 #include <asm/cache.h>
 #include <asm/spr_defs.h>
 #include <asm/asm-offsets.h>
+#include <linux/of_fdt.h>
 
 #define tophys(rd,rs)                           \
         l.movhi rd,hi(-KERNELBASE)              ;\
@@ -440,6 +441,9 @@ _dispatch_do_ipage_fault:
         __HEAD
         .global _start
 _start:
+        /* save kernel parameters */
+        l.or    r25,r0,r3       /* pointer to fdt */
+
         /*
          * ensure a deterministic start
          */
@@ -471,7 +475,6 @@ _start:
         CLEAR_GPR(r22)
         CLEAR_GPR(r23)
         CLEAR_GPR(r24)
-        CLEAR_GPR(r25)
         CLEAR_GPR(r26)
         CLEAR_GPR(r27)
         CLEAR_GPR(r28)
@@ -565,6 +568,18 @@ enable_mmu:
         // reset the simulation counters
         l.nop 5
 
+        /* check fdt header magic word */
+        l.lwz   r3,0(r25)       /* load magic from fdt into r3 */
+        l.movhi r4,hi(OF_DT_HEADER)
+        l.ori   r4,r4,lo(OF_DT_HEADER)
+        l.sfeq  r3,r4
+        l.bf    _fdt_found
+         l.nop
+        /* magic number mismatch, set fdt pointer to null */
+        l.or    r25,r0,r0
+_fdt_found:
+        /* pass fdt pointer to or32_early_setup in r3 */
+        l.or    r3,r0,r25
         LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
         l.jalr r24
          l.nop
diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c
index 967d499da68..e71781d24b0 100644
--- a/arch/openrisc/kernel/ptrace.c
+++ b/arch/openrisc/kernel/ptrace.c
@@ -187,11 +187,11 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
                  */
                 ret = -1L;
 
-        audit_syscall_entry(audit_arch(), regs->syscallno,
+        audit_syscall_entry(audit_arch(), regs->gpr[11],
                             regs->gpr[3], regs->gpr[4],
                             regs->gpr[5], regs->gpr[6]);
 
-        return ret ? : regs->syscallno;
+        return ret ? : regs->gpr[11];
 }
 
 asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index ad2c290f239..f4d5bedc3b4 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -206,18 +206,18 @@ void __init setup_cpuinfo(void)
  * Handles the pointer to the device tree that this kernel is to use
  * for establishing the available platform devices.
  *
- * For now, this is limited to using the built-in device tree.  In the future,
- * it is intended that this function will take a pointer to the device tree
- * that is potentially built-in, but potentially also passed in by the
- * bootloader, or discovered by some equally clever means...
+ * Falls back on built-in device tree in case null pointer is passed.
  */
 
-void __init or32_early_setup(void)
+void __init or32_early_setup(unsigned int fdt)
 {
-
-        early_init_devtree(__dtb_start);
-
-        printk(KERN_INFO "Compiled-in FDT at 0x%p\n", __dtb_start);
+        if (fdt) {
+                early_init_devtree((void*) fdt);
+                printk(KERN_INFO "FDT at 0x%08x\n", fdt);
+        } else {
+                early_init_devtree(__dtb_start);
+                printk(KERN_INFO "Compiled-in FDT at %p\n", __dtb_start);
+        }
 }
 
 static int __init openrisc_device_probe(void)
diff --git a/arch/openrisc/kernel/signal.c b/arch/openrisc/kernel/signal.c
index 95207ab0c99..e970743251a 100644
--- a/arch/openrisc/kernel/signal.c
+++ b/arch/openrisc/kernel/signal.c
@@ -102,10 +102,7 @@ asmlinkage long _sys_rt_sigreturn(struct pt_regs *regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
                 goto badframe;
@@ -189,8 +186,8 @@ static inline void __user *get_sigframe(struct k_sigaction *ka,
  * trampoline which performs the syscall sigreturn, or a provided
  * user-mode trampoline.
  */
-static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-                           sigset_t *set, struct pt_regs *regs)
+static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+                          sigset_t *set, struct pt_regs *regs)
 {
         struct rt_sigframe *frame;
         unsigned long return_ip;
@@ -247,31 +244,27 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         /* actually move the usp to reflect the stacked frame */
         regs->sp = (unsigned long)frame;
 
-        return;
+        return 0;
 
 give_sigsegv:
-        if (sig == SIGSEGV)
-                ka->sa.sa_handler = SIG_DFL;
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
+        return -EFAULT;
 }
 
-static inline void
+static inline int
 handle_signal(unsigned long sig,
               siginfo_t *info, struct k_sigaction *ka,
               sigset_t *oldset, struct pt_regs *regs)
 {
-        setup_rt_frame(sig, ka, info, oldset, regs);
+        int ret;
 
-        if (ka->sa.sa_flags & SA_ONESHOT)
-                ka->sa.sa_handler = SIG_DFL;
+        ret = setup_rt_frame(sig, ka, info, oldset, regs);
+        if (ret)
+                return ret;
 
-        spin_lock_irq(&current->sighand->siglock);
-        sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked, sig);
-        recalc_sigpending();
+        block_sigmask(ka, sig);
 
-        spin_unlock_irq(&current->sighand->siglock);
+        return 0;
 }
 
 /*
@@ -312,7 +305,7 @@ void do_signal(struct pt_regs *regs)
          * below mean that the syscall executed to completion and no
          * restart is necessary.
          */
-        if (regs->syscallno) {
+        if (regs->orig_gpr11) {
                 int restart = 0;
 
                 switch (regs->gpr[11]) {
@@ -360,13 +353,13 @@ void do_signal(struct pt_regs *regs)
                         oldset = &current->blocked;
 
                 /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &info, &ka, oldset, regs);
-                /* a signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TIF_RESTORE_SIGMASK flag */
-                if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                if (!handle_signal(signr, &info, &ka, oldset, regs)) {
+                        /* a signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag */
                         clear_thread_flag(TIF_RESTORE_SIGMASK);
+                }
 
                 tracehook_signal_handler(signr, &info, &ka, regs,
                                          test_thread_flag(TIF_SINGLESTEP));
diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c
index bd946ef1623..7c52e9494a8 100644
--- a/arch/openrisc/kernel/time.c
+++ b/arch/openrisc/kernel/time.c
@@ -125,16 +125,13 @@ irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
 
 static __init void openrisc_clockevent_init(void)
 {
-        clockevents_calc_mult_shift(&clockevent_openrisc_timer,
-                                    cpuinfo.clock_frequency, 4);
+        clockevent_openrisc_timer.cpumask = cpumask_of(0);
 
         /* We only have 28 bits */
-        clockevent_openrisc_timer.max_delta_ns =
-            clockevent_delta2ns((u32) 0x0fffffff, &clockevent_openrisc_timer);
-        clockevent_openrisc_timer.min_delta_ns =
-            clockevent_delta2ns(1, &clockevent_openrisc_timer);
-        clockevent_openrisc_timer.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_openrisc_timer);
+        clockevents_config_and_register(&clockevent_openrisc_timer,
+                                        cpuinfo.clock_frequency,
+                                        100, 0x0fffffff);
+
 }
 
 /**
diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c
index 52ca32b5b65..5cce396016d 100644
--- a/arch/openrisc/kernel/traps.c
+++ b/arch/openrisc/kernel/traps.c
@@ -114,6 +114,7 @@ void dump_stack(void)
 
         show_stack(current, &stack);
 }
+EXPORT_SYMBOL(dump_stack);
 
 void show_registers(struct pt_regs *regs)
 {
@@ -144,8 +145,8 @@ void show_registers(struct pt_regs *regs)
                regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]);
         printk("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n",
                regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]);
-        printk("  RES: %08lx oGPR11: %08lx syscallno: %08lx\n",
-               regs->gpr[11], regs->orig_gpr11, regs->syscallno);
+        printk("  RES: %08lx oGPR11: %08lx\n",
+               regs->gpr[11], regs->orig_gpr11);
 
         printk("Process %s (pid: %d, stackpage=%08lx)\n",
                current->comm, current->pid, (unsigned long)current);
@@ -206,8 +207,8 @@ void nommu_dump_state(struct pt_regs *regs,
                regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]);
         printk("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n",
                regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]);
-        printk("  RES: %08lx oGPR11: %08lx syscallno: %08lx\n",
-               regs->gpr[11], regs->orig_gpr11, regs->syscallno);
+        printk("  RES: %08lx oGPR11: %08lx\n",
+               regs->gpr[11], regs->orig_gpr11);
 
         printk("Process %s (pid: %d, stackpage=%08lx)\n",
                ((struct task_struct *)(__pa(current)))->comm,
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index 1cf3a8a3154..79dea9740a3 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -221,8 +221,7 @@ void __init mem_init(void)
 {
         int codesize, reservedpages, datasize, initsize;
 
-        if (!mem_map)
-                BUG();
+        BUG_ON(!mem_map);
 
         set_max_mapnr_init();
 
diff --git a/arch/parisc/include/asm/mman.h b/arch/parisc/include/asm/mman.h
index f5b7bf5fba6..12219ebce86 100644
--- a/arch/parisc/include/asm/mman.h
+++ b/arch/parisc/include/asm/mman.h
@@ -62,6 +62,10 @@
 #define MADV_HUGEPAGE   67              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 68              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   69              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     70              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 #define MAP_VARIABLE    0
diff --git a/arch/parisc/include/asm/pci.h b/arch/parisc/include/asm/pci.h
index 2242a5c636c..3234f492d57 100644
--- a/arch/parisc/include/asm/pci.h
+++ b/arch/parisc/include/asm/pci.h
@@ -82,38 +82,8 @@ struct pci_hba_data {
 
 #ifdef CONFIG_64BIT
 #define PCI_F_EXTEND            0xffffffff00000000UL
-#define PCI_IS_LMMIO(hba,a)     pci_is_lmmio(hba,a)
-
-/* We need to know if an address is LMMMIO or GMMIO.
- * LMMIO requires mangling and GMMIO we must use as-is.
- */
-static __inline__  int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
-{
-        return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
-}
-
-/*
-** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
-** See pci.c for more conversions used by Generic PCI code.
-**
-** Platform characteristics/firmware guarantee that
-**      (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
-**      (2) PA_VIEW == IO_VIEW for GMMIO
-*/
-#define PCI_BUS_ADDR(hba,a)     (PCI_IS_LMMIO(hba,a)    \
-                ?  ((a) - hba->lmmio_space_offset)      /* mangle LMMIO */ \
-                : (a))                                  /* GMMIO */
-#define PCI_HOST_ADDR(hba,a)    (((a) & PCI_F_EXTEND) == 0 \
-                ? (a) + hba->lmmio_space_offset \
-                : (a))
-
 #else   /* !CONFIG_64BIT */
-
-#define PCI_BUS_ADDR(hba,a)     (a)
-#define PCI_HOST_ADDR(hba,a)    (a)
 #define PCI_F_EXTEND            0UL
-#define PCI_IS_LMMIO(hba,a)     (1)     /* 32-bit doesn't support GMMIO */
-
 #endif /* !CONFIG_64BIT */
 
 /*
@@ -245,14 +215,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't need to penalize isa irq's */
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index 4f0cf0c9b0a..24644aca10c 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -194,58 +194,6 @@ void __init pcibios_init_bus(struct pci_bus *bus)
         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
 }
 
-/* called by drivers/pci/setup-bus.c:pci_setup_bridge().  */
-void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
-                struct pci_bus_region *region, struct resource *res)
-{
-#ifdef CONFIG_64BIT
-        struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
-#endif
-
-        if (res->flags & IORESOURCE_IO) {
-                /*
-                ** I/O space may see busnumbers here. Something
-                ** in the form of 0xbbxxxx where bb is the bus num
-                ** and xxxx is the I/O port space address.
-                ** Remaining address translation are done in the
-                ** PCI Host adapter specific code - ie dino_out8.
-                */
-                region->start = PCI_PORT_ADDR(res->start);
-                region->end   = PCI_PORT_ADDR(res->end);
-        } else if (res->flags & IORESOURCE_MEM) {
-                /* Convert MMIO addr to PCI addr (undo global virtualization) */
-                region->start = PCI_BUS_ADDR(hba, res->start);
-                region->end   = PCI_BUS_ADDR(hba, res->end);
-        }
-
-        DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
-                dev->bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
-                region->start, region->end);
-}
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                              struct pci_bus_region *region)
-{
-#ifdef CONFIG_64BIT
-        struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
-#endif
-
-        if (res->flags & IORESOURCE_MEM) {
-                res->start = PCI_HOST_ADDR(hba, region->start);
-                res->end = PCI_HOST_ADDR(hba, region->end);
-        }
-
-        if (res->flags & IORESOURCE_IO) {
-                res->start = region->start;
-                res->end = region->end;
-        }
-}
-
-#ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-#endif
-
 /*
  * pcibios align resources() is called every time generic PCI code
  * wants to generate a new address. The process of looking for
diff --git a/arch/parisc/math-emu/fpudispatch.c b/arch/parisc/math-emu/fpudispatch.c
index 6e28f9f4c62..673b73e8420 100644
--- a/arch/parisc/math-emu/fpudispatch.c
+++ b/arch/parisc/math-emu/fpudispatch.c
@@ -50,6 +50,7 @@
 #define FPUDEBUG 0
 
 #include "float.h"
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <asm/processor.h>
 /* #include <sys/debug.h> */
diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore
index 12da77ec022..1c1aadc8c48 100644
--- a/arch/powerpc/boot/.gitignore
+++ b/arch/powerpc/boot/.gitignore
@@ -27,7 +27,6 @@ zImage.bin.*
 zImage.chrp
 zImage.coff
 zImage.holly
-zImage.iseries
 zImage.*lds
 zImage.miboot
 zImage.pmac
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index edfc9803ec9..957a83f4364 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -112,7 +112,6 @@ extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
                              struct dma_attrs *attrs);
 
 extern void iommu_init_early_pSeries(void);
-extern void iommu_init_early_iSeries(void);
 extern void iommu_init_early_dart(void);
 extern void iommu_init_early_pasemi(void);
 
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index fe0b09dceb7..cf417e51073 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -27,12 +27,6 @@ extern atomic_t ppc_n_lost_interrupts;
 /* This number is used when no interrupt has been assigned */
 #define NO_IRQ                  (0)
 
-/* This is a special irq number to return from get_irq() to tell that
- * no interrupt happened _and_ ignore it (don't count it as bad). Some
- * platforms like iSeries rely on that.
- */
-#define NO_IRQ_IGNORE           ((unsigned int)-1)
-
 /* Total number of virq in the platform */
 #define NR_IRQS         CONFIG_NR_IRQS
 
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
index f7727d91ac6..b921c3f4892 100644
--- a/arch/powerpc/include/asm/kvm.h
+++ b/arch/powerpc/include/asm/kvm.h
@@ -265,12 +265,9 @@ struct kvm_debug_exit_arch {
 struct kvm_guest_debug_arch {
 };
 
-#define KVM_REG_MASK            0x001f
-#define KVM_REG_EXT_MASK        0xffe0
-#define KVM_REG_GPR             0x0000
-#define KVM_REG_FPR             0x0020
-#define KVM_REG_QPR             0x0040
-#define KVM_REG_FQPR            0x0060
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
 
 #define KVM_INTERRUPT_SET       -1U
 #define KVM_INTERRUPT_UNSET     -2U
@@ -292,4 +289,41 @@ struct kvm_allocate_rma {
         __u64 rma_size;
 };
 
+struct kvm_book3e_206_tlb_entry {
+        __u32 mas8;
+        __u32 mas1;
+        __u64 mas2;
+        __u64 mas7_3;
+};
+
+struct kvm_book3e_206_tlb_params {
+        /*
+         * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
+         *
+         * - The number of ways of TLB0 must be a power of two between 2 and
+         *   16.
+         * - TLB1 must be fully associative.
+         * - The size of TLB0 must be a multiple of the number of ways, and
+         *   the number of sets must be a power of two.
+         * - The size of TLB1 may not exceed 64 entries.
+         * - TLB0 supports 4 KiB pages.
+         * - The page sizes supported by TLB1 are as indicated by
+         *   TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
+         *   as returned by KVM_GET_SREGS.
+         * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
+         *   and tlb_ways[] must be zero.
+         *
+         * tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
+         *
+         * KVM will adjust TLBnCFG based on the sizes configured here,
+         * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
+         * set to zero.
+         */
+        __u32 tlb_sizes[4];
+        __u32 tlb_ways[4];
+        __u32 reserved[8];
+};
+
+#define KVM_REG_PPC_HIOR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
+
 #endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 69c7377d207..aa795ccef29 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -90,6 +90,8 @@ struct kvmppc_vcpu_book3s {
 #endif
         int context_id[SID_CONTEXTS];
 
+        bool hior_explicit;             /* HIOR is set by ioctl, not PVR */
+
         struct hlist_head hpte_hash_pte[HPTEG_HASH_NUM_PTE];
         struct hlist_head hpte_hash_pte_long[HPTEG_HASH_NUM_PTE_LONG];
         struct hlist_head hpte_hash_vpte[HPTEG_HASH_NUM_VPTE];
@@ -119,6 +121,11 @@ extern void kvmppc_mmu_book3s_hv_init(struct kvm_vcpu *vcpu);
 extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte);
 extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr);
 extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu);
+extern int kvmppc_book3s_hv_page_fault(struct kvm_run *run,
+                        struct kvm_vcpu *vcpu, unsigned long addr,
+                        unsigned long status);
+extern long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr,
+                        unsigned long slb_v, unsigned long valid);
 
 extern void kvmppc_mmu_hpte_cache_map(struct kvm_vcpu *vcpu, struct hpte_cache *pte);
 extern struct hpte_cache *kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu);
@@ -138,6 +145,21 @@ extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
 extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
 extern int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu);
 extern pfn_t kvmppc_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn);
+extern void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
+                        unsigned long *rmap, long pte_index, int realmode);
+extern void kvmppc_invalidate_hpte(struct kvm *kvm, unsigned long *hptep,
+                        unsigned long pte_index);
+void kvmppc_clear_ref_hpte(struct kvm *kvm, unsigned long *hptep,
+                        unsigned long pte_index);
+extern void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long addr,
+                        unsigned long *nb_ret);
+extern void kvmppc_unpin_guest_page(struct kvm *kvm, void *addr);
+extern long kvmppc_virtmode_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
+                        long pte_index, unsigned long pteh, unsigned long ptel);
+extern long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
+                        long pte_index, unsigned long pteh, unsigned long ptel);
+extern long kvmppc_hv_get_dirty_log(struct kvm *kvm,
+                        struct kvm_memory_slot *memslot);
 
 extern void kvmppc_entry_trampoline(void);
 extern void kvmppc_hv_entry_trampoline(void);
@@ -183,7 +205,9 @@ static inline void kvmppc_update_int_pending(struct kvm_vcpu *vcpu,
 static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
 {
         if ( num < 14 ) {
-                to_svcpu(vcpu)->gpr[num] = val;
+                struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+                svcpu->gpr[num] = val;
+                svcpu_put(svcpu);
                 to_book3s(vcpu)->shadow_vcpu->gpr[num] = val;
         } else
                 vcpu->arch.gpr[num] = val;
@@ -191,80 +215,120 @@ static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
 
 static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
 {
-        if ( num < 14 )
-                return to_svcpu(vcpu)->gpr[num];
-        else
+        if ( num < 14 ) {
+                struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+                ulong r = svcpu->gpr[num];
+                svcpu_put(svcpu);
+                return r;
+        } else
                 return vcpu->arch.gpr[num];
 }
 
 static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
 {
-        to_svcpu(vcpu)->cr = val;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        svcpu->cr = val;
+        svcpu_put(svcpu);
         to_book3s(vcpu)->shadow_vcpu->cr = val;
 }
 
 static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu)
 {
-        return to_svcpu(vcpu)->cr;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        u32 r;
+        r = svcpu->cr;
+        svcpu_put(svcpu);
+        return r;
 }
 
 static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val)
 {
-        to_svcpu(vcpu)->xer = val;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        svcpu->xer = val;
         to_book3s(vcpu)->shadow_vcpu->xer = val;
+        svcpu_put(svcpu);
 }
 
 static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu)
 {
-        return to_svcpu(vcpu)->xer;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        u32 r;
+        r = svcpu->xer;
+        svcpu_put(svcpu);
+        return r;
 }
 
 static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val)
 {
-        to_svcpu(vcpu)->ctr = val;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        svcpu->ctr = val;
+        svcpu_put(svcpu);
 }
 
 static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu)
 {
-        return to_svcpu(vcpu)->ctr;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        ulong r;
+        r = svcpu->ctr;
+        svcpu_put(svcpu);
+        return r;
 }
 
 static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val)
 {
-        to_svcpu(vcpu)->lr = val;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        svcpu->lr = val;
+        svcpu_put(svcpu);
 }
 
 static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu)
 {
-        return to_svcpu(vcpu)->lr;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        ulong r;
+        r = svcpu->lr;
+        svcpu_put(svcpu);
+        return r;
 }
 
 static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val)
 {
-        to_svcpu(vcpu)->pc = val;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        svcpu->pc = val;
+        svcpu_put(svcpu);
 }
 
 static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
 {
-        return to_svcpu(vcpu)->pc;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        ulong r;
+        r = svcpu->pc;
+        svcpu_put(svcpu);
+        return r;
 }
 
 static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
 {
         ulong pc = kvmppc_get_pc(vcpu);
-        struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu);
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        u32 r;
 
         /* Load the instruction manually if it failed to do so in the
          * exit path */
         if (svcpu->last_inst == KVM_INST_FETCH_FAILED)
                 kvmppc_ld(vcpu, &pc, sizeof(u32), &svcpu->last_inst, false);
 
-        return svcpu->last_inst;
+        r = svcpu->last_inst;
+        svcpu_put(svcpu);
+        return r;
 }
 
 static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
 {
-        return to_svcpu(vcpu)->fault_dar;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        ulong r;
+        r = svcpu->fault_dar;
+        svcpu_put(svcpu);
+        return r;
 }
 
 static inline bool kvmppc_critical_section(struct kvm_vcpu *vcpu)
diff --git a/arch/powerpc/include/asm/kvm_book3s_32.h b/arch/powerpc/include/asm/kvm_book3s_32.h
index de604db135f..38040ff8206 100644
--- a/arch/powerpc/include/asm/kvm_book3s_32.h
+++ b/arch/powerpc/include/asm/kvm_book3s_32.h
@@ -20,11 +20,15 @@
 #ifndef __ASM_KVM_BOOK3S_32_H__
 #define __ASM_KVM_BOOK3S_32_H__
 
-static inline struct kvmppc_book3s_shadow_vcpu *to_svcpu(struct kvm_vcpu *vcpu)
+static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
 {
         return to_book3s(vcpu)->shadow_vcpu;
 }
 
+static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
+{
+}
+
 #define PTE_SIZE        12
 #define VSID_ALL        0
 #define SR_INVALID      0x00000001      /* VSID 1 should always be unused */
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index d0ac94f98f9..b0c08b14277 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -21,14 +21,56 @@
 #define __ASM_KVM_BOOK3S_64_H__
 
 #ifdef CONFIG_KVM_BOOK3S_PR
-static inline struct kvmppc_book3s_shadow_vcpu *to_svcpu(struct kvm_vcpu *vcpu)
+static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
 {
+        preempt_disable();
         return &get_paca()->shadow_vcpu;
 }
+
+static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
+{
+        preempt_enable();
+}
 #endif
 
 #define SPAPR_TCE_SHIFT         12
 
+#ifdef CONFIG_KVM_BOOK3S_64_HV
+/* For now use fixed-size 16MB page table */
+#define HPT_ORDER       24
+#define HPT_NPTEG       (1ul << (HPT_ORDER - 7))        /* 128B per pteg */
+#define HPT_NPTE        (HPT_NPTEG << 3)                /* 8 PTEs per PTEG */
+#define HPT_HASH_MASK   (HPT_NPTEG - 1)
+#endif
+
+#define VRMA_VSID       0x1ffffffUL     /* 1TB VSID reserved for VRMA */
+
+/*
+ * We use a lock bit in HPTE dword 0 to synchronize updates and
+ * accesses to each HPTE, and another bit to indicate non-present
+ * HPTEs.
+ */
+#define HPTE_V_HVLOCK   0x40UL
+#define HPTE_V_ABSENT   0x20UL
+
+static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
+{
+        unsigned long tmp, old;
+
+        asm volatile("  ldarx   %0,0,%2\n"
+                     "  and.    %1,%0,%3\n"
+                     "  bne     2f\n"
+                     "  ori     %0,%0,%4\n"
+                     "  stdcx.  %0,0,%2\n"
+                     "  beq+    2f\n"
+                     "  li      %1,%3\n"
+                     "2:        isync"
+                     : "=&r" (tmp), "=&r" (old)
+                     : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
+                     : "cc", "memory");
+        return old == 0;
+}
+
 static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
                                              unsigned long pte_index)
 {
@@ -62,4 +104,140 @@ static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
         return rb;
 }
 
+static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
+{
+        /* only handle 4k, 64k and 16M pages for now */
+        if (!(h & HPTE_V_LARGE))
+                return 1ul << 12;               /* 4k page */
+        if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
+                return 1ul << 16;               /* 64k page */
+        if ((l & 0xff000) == 0)
+                return 1ul << 24;               /* 16M page */
+        return 0;                               /* error */
+}
+
+static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
+{
+        return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
+}
+
+static inline int hpte_is_writable(unsigned long ptel)
+{
+        unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
+
+        return pp != PP_RXRX && pp != PP_RXXX;
+}
+
+static inline unsigned long hpte_make_readonly(unsigned long ptel)
+{
+        if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
+                ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
+        else
+                ptel |= PP_RXRX;
+        return ptel;
+}
+
+static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
+{
+        unsigned int wimg = ptel & HPTE_R_WIMG;
+
+        /* Handle SAO */
+        if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
+            cpu_has_feature(CPU_FTR_ARCH_206))
+                wimg = HPTE_R_M;
+
+        if (!io_type)
+                return wimg == HPTE_R_M;
+
+        return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
+}
+
+/*
+ * Lock and read a linux PTE.  If it's present and writable, atomically
+ * set dirty and referenced bits and return the PTE, otherwise return 0.
+ */
+static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
+{
+        pte_t pte, tmp;
+
+        /* wait until _PAGE_BUSY is clear then set it atomically */
+        __asm__ __volatile__ (
+                "1:     ldarx   %0,0,%3\n"
+                "       andi.   %1,%0,%4\n"
+                "       bne-    1b\n"
+                "       ori     %1,%0,%4\n"
+                "       stdcx.  %1,0,%3\n"
+                "       bne-    1b"
+                : "=&r" (pte), "=&r" (tmp), "=m" (*p)
+                : "r" (p), "i" (_PAGE_BUSY)
+                : "cc");
+
+        if (pte_present(pte)) {
+                pte = pte_mkyoung(pte);
+                if (writing && pte_write(pte))
+                        pte = pte_mkdirty(pte);
+        }
+
+        *p = pte;       /* clears _PAGE_BUSY */
+
+        return pte;
+}
+
+/* Return HPTE cache control bits corresponding to Linux pte bits */
+static inline unsigned long hpte_cache_bits(unsigned long pte_val)
+{
+#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
+        return pte_val & (HPTE_R_W | HPTE_R_I);
+#else
+        return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
+                ((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
+#endif
+}
+
+static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
+{
+        if (key)
+                return PP_RWRX <= pp && pp <= PP_RXRX;
+        return 1;
+}
+
+static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
+{
+        if (key)
+                return pp == PP_RWRW;
+        return pp <= PP_RWRW;
+}
+
+static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
+{
+        unsigned long skey;
+
+        skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
+                ((hpte_r & HPTE_R_KEY_LO) >> 9);
+        return (amr >> (62 - 2 * skey)) & 3;
+}
+
+static inline void lock_rmap(unsigned long *rmap)
+{
+        do {
+                while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
+                        cpu_relax();
+        } while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
+}
+
+static inline void unlock_rmap(unsigned long *rmap)
+{
+        __clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
+}
+
+static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
+                                   unsigned long pagesize)
+{
+        unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
+
+        if (pagesize <= PAGE_SIZE)
+                return 1;
+        return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
+}
+
 #endif /* __ASM_KVM_BOOK3S_64_H__ */
diff --git a/arch/powerpc/include/asm/kvm_e500.h b/arch/powerpc/include/asm/kvm_e500.h
index adbfca9dd10..8cd50a51427 100644
--- a/arch/powerpc/include/asm/kvm_e500.h
+++ b/arch/powerpc/include/asm/kvm_e500.h
@@ -22,46 +22,55 @@
 #define E500_PID_NUM   3
 #define E500_TLB_NUM   2
 
-struct tlbe{
-        u32 mas1;
-        u32 mas2;
-        u32 mas3;
-        u32 mas7;
-};
-
 #define E500_TLB_VALID 1
 #define E500_TLB_DIRTY 2
 
-struct tlbe_priv {
+struct tlbe_ref {
         pfn_t pfn;
         unsigned int flags; /* E500_TLB_* */
 };
 
+struct tlbe_priv {
+        struct tlbe_ref ref; /* TLB0 only -- TLB1 uses tlb_refs */
+};
+
 struct vcpu_id_table;
 
+struct kvmppc_e500_tlb_params {
+        int entries, ways, sets;
+};
+
 struct kvmppc_vcpu_e500 {
-        /* Unmodified copy of the guest's TLB. */
-        struct tlbe *gtlb_arch[E500_TLB_NUM];
+        /* Unmodified copy of the guest's TLB -- shared with host userspace. */
+        struct kvm_book3e_206_tlb_entry *gtlb_arch;
+
+        /* Starting entry number in gtlb_arch[] */
+        int gtlb_offset[E500_TLB_NUM];
 
         /* KVM internal information associated with each guest TLB entry */
         struct tlbe_priv *gtlb_priv[E500_TLB_NUM];
 
-        unsigned int gtlb_size[E500_TLB_NUM];
+        struct kvmppc_e500_tlb_params gtlb_params[E500_TLB_NUM];
+
         unsigned int gtlb_nv[E500_TLB_NUM];
 
+        /*
+         * information associated with each host TLB entry --
+         * TLB1 only for now.  If/when guest TLB1 entries can be
+         * mapped with host TLB0, this will be used for that too.
+         *
+         * We don't want to use this for guest TLB0 because then we'd
+         * have the overhead of doing the translation again even if
+         * the entry is still in the guest TLB (e.g. we swapped out
+         * and back, and our host TLB entries got evicted).
+         */
+        struct tlbe_ref *tlb_refs[E500_TLB_NUM];
+        unsigned int host_tlb1_nv;
+
         u32 host_pid[E500_PID_NUM];
         u32 pid[E500_PID_NUM];
         u32 svr;
 
-        u32 mas0;
-        u32 mas1;
-        u32 mas2;
-        u32 mas3;
-        u32 mas4;
-        u32 mas5;
-        u32 mas6;
-        u32 mas7;
-
         /* vcpu id table */
         struct vcpu_id_table *idt;
 
@@ -73,6 +82,9 @@ struct kvmppc_vcpu_e500 {
         u32 tlb1cfg;
         u64 mcar;
 
+        struct page **shared_tlb_pages;
+        int num_shared_tlb_pages;
+
         struct kvm_vcpu vcpu;
 };
 
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index bf8af5d5d5d..52eb9c1f4fe 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -32,17 +32,32 @@
 #include <linux/atomic.h>
 #include <asm/kvm_asm.h>
 #include <asm/processor.h>
+#include <asm/page.h>
 
 #define KVM_MAX_VCPUS           NR_CPUS
 #define KVM_MAX_VCORES          NR_CPUS
 #define KVM_MEMORY_SLOTS 32
 /* memory slots that does not exposed to userspace */
 #define KVM_PRIVATE_MEM_SLOTS 4
+#define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS)
 
 #ifdef CONFIG_KVM_MMIO
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
 #endif
 
+#ifdef CONFIG_KVM_BOOK3S_64_HV
+#include <linux/mmu_notifier.h>
+
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+
+struct kvm;
+extern int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
+extern int kvm_age_hva(struct kvm *kvm, unsigned long hva);
+extern int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
+extern void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+
+#endif
+
 /* We don't currently support large pages. */
 #define KVM_HPAGE_GFN_SHIFT(x)  0
 #define KVM_NR_PAGE_SIZES       1
@@ -158,34 +173,72 @@ struct kvmppc_spapr_tce_table {
         struct page *pages[0];
 };
 
-struct kvmppc_rma_info {
+struct kvmppc_linear_info {
         void            *base_virt;
         unsigned long    base_pfn;
         unsigned long    npages;
         struct list_head list;
-        atomic_t         use_count;
+        atomic_t         use_count;
+        int              type;
+};
+
+/*
+ * The reverse mapping array has one entry for each HPTE,
+ * which stores the guest's view of the second word of the HPTE
+ * (including the guest physical address of the mapping),
+ * plus forward and backward pointers in a doubly-linked ring
+ * of HPTEs that map the same host page.  The pointers in this
+ * ring are 32-bit HPTE indexes, to save space.
+ */
+struct revmap_entry {
+        unsigned long guest_rpte;
+        unsigned int forw, back;
+};
+
+/*
+ * We use the top bit of each memslot->rmap entry as a lock bit,
+ * and bit 32 as a present flag.  The bottom 32 bits are the
+ * index in the guest HPT of a HPTE that points to the page.
+ */
+#define KVMPPC_RMAP_LOCK_BIT    63
+#define KVMPPC_RMAP_RC_SHIFT    32
+#define KVMPPC_RMAP_REFERENCED  (HPTE_R_R << KVMPPC_RMAP_RC_SHIFT)
+#define KVMPPC_RMAP_CHANGED     (HPTE_R_C << KVMPPC_RMAP_RC_SHIFT)
+#define KVMPPC_RMAP_PRESENT     0x100000000ul
+#define KVMPPC_RMAP_INDEX       0xfffffffful
+
+/* Low-order bits in kvm->arch.slot_phys[][] */
+#define KVMPPC_PAGE_ORDER_MASK  0x1f
+#define KVMPPC_PAGE_NO_CACHE    HPTE_R_I        /* 0x20 */
+#define KVMPPC_PAGE_WRITETHRU   HPTE_R_W        /* 0x40 */
+#define KVMPPC_GOT_PAGE         0x80
+
+struct kvm_arch_memory_slot {
 };
 
 struct kvm_arch {
 #ifdef CONFIG_KVM_BOOK3S_64_HV
         unsigned long hpt_virt;
-        unsigned long ram_npages;
-        unsigned long ram_psize;
-        unsigned long ram_porder;
-        struct kvmppc_pginfo *ram_pginfo;
+        struct revmap_entry *revmap;
         unsigned int lpid;
         unsigned int host_lpid;
         unsigned long host_lpcr;
         unsigned long sdr1;
         unsigned long host_sdr1;
         int tlbie_lock;
-        int n_rma_pages;
         unsigned long lpcr;
         unsigned long rmor;
-        struct kvmppc_rma_info *rma;
+        struct kvmppc_linear_info *rma;
+        unsigned long vrma_slb_v;
+        int rma_setup_done;
+        int using_mmu_notifiers;
         struct list_head spapr_tce_tables;
+        spinlock_t slot_phys_lock;
+        unsigned long *slot_phys[KVM_MEM_SLOTS_NUM];
+        int slot_npages[KVM_MEM_SLOTS_NUM];
         unsigned short last_vcpu[NR_CPUS];
         struct kvmppc_vcore *vcores[KVM_MAX_VCORES];
+        struct kvmppc_linear_info *hpt_li;
 #endif /* CONFIG_KVM_BOOK3S_64_HV */
 };
 
@@ -318,10 +371,6 @@ struct kvm_vcpu_arch {
         u32 vrsave; /* also USPRG0 */
         u32 mmucr;
         ulong shadow_msr;
-        ulong sprg4;
-        ulong sprg5;
-        ulong sprg6;
-        ulong sprg7;
         ulong csrr0;
         ulong csrr1;
         ulong dsrr0;
@@ -329,16 +378,14 @@ struct kvm_vcpu_arch {
         ulong mcsrr0;
         ulong mcsrr1;
         ulong mcsr;
-        ulong esr;
         u32 dec;
         u32 decar;
         u32 tbl;
         u32 tbu;
         u32 tcr;
-        u32 tsr;
+        ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
         u32 ivor[64];
         ulong ivpr;
-        u32 pir;
         u32 pvr;
 
         u32 shadow_pid;
@@ -427,9 +474,14 @@ struct kvm_vcpu_arch {
 #ifdef CONFIG_KVM_BOOK3S_64_HV
         struct kvm_vcpu_arch_shared shregs;
 
+        unsigned long pgfault_addr;
+        long pgfault_index;
+        unsigned long pgfault_hpte[2];
+
         struct list_head run_list;
         struct task_struct *run_task;
         struct kvm_run *kvm_run;
+        pgd_t *pgdir;
 #endif
 };
 
@@ -438,4 +490,12 @@ struct kvm_vcpu_arch {
 #define KVMPPC_VCPU_BUSY_IN_HOST        1
 #define KVMPPC_VCPU_RUNNABLE            2
 
+/* Values for vcpu->arch.io_gpr */
+#define KVM_MMIO_REG_MASK       0x001f
+#define KVM_MMIO_REG_EXT_MASK   0xffe0
+#define KVM_MMIO_REG_GPR        0x0000
+#define KVM_MMIO_REG_FPR        0x0020
+#define KVM_MMIO_REG_QPR        0x0040
+#define KVM_MMIO_REG_FQPR       0x0060
+
 #endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_para.h b/arch/powerpc/include/asm/kvm_para.h
index 50533f9adf4..7b754e74300 100644
--- a/arch/powerpc/include/asm/kvm_para.h
+++ b/arch/powerpc/include/asm/kvm_para.h
@@ -22,6 +22,16 @@
 
 #include <linux/types.h>
 
+/*
+ * Additions to this struct must only occur at the end, and should be
+ * accompanied by a KVM_MAGIC_FEAT flag to advertise that they are present
+ * (albeit not necessarily relevant to the current target hardware platform).
+ *
+ * Struct fields are always 32 or 64 bit aligned, depending on them being 32
+ * or 64 bit wide respectively.
+ *
+ * See Documentation/virtual/kvm/ppc-pv.txt
+ */
 struct kvm_vcpu_arch_shared {
         __u64 scratch1;
         __u64 scratch2;
@@ -33,11 +43,35 @@ struct kvm_vcpu_arch_shared {
         __u64 sprg3;
         __u64 srr0;
         __u64 srr1;
-        __u64 dar;
+        __u64 dar;              /* dear on BookE */
         __u64 msr;
         __u32 dsisr;
         __u32 int_pending;      /* Tells the guest if we have an interrupt */
         __u32 sr[16];
+        __u32 mas0;
+        __u32 mas1;
+        __u64 mas7_3;
+        __u64 mas2;
+        __u32 mas4;
+        __u32 mas6;
+        __u32 esr;
+        __u32 pir;
+
+        /*
+         * SPRG4-7 are user-readable, so we can only keep these consistent
+         * between the shared area and the real registers when there's an
+         * intervening exit to KVM.  This also applies to SPRG3 on some
+         * chips.
+         *
+         * This suffices for access by guest userspace, since in PR-mode
+         * KVM, an exit must occur when changing the guest's MSR[PR].
+         * If the guest kernel writes to SPRG3-7 via the shared area, it
+         * must also use the shared area for reading while in kernel space.
+         */
+        __u64 sprg4;
+        __u64 sprg5;
+        __u64 sprg6;
+        __u64 sprg7;
 };
 
 #define KVM_SC_MAGIC_R0         0x4b564d21 /* "KVM!" */
@@ -47,7 +81,10 @@ struct kvm_vcpu_arch_shared {
 
 #define KVM_FEATURE_MAGIC_PAGE  1
 
-#define KVM_MAGIC_FEAT_SR       (1 << 0)
+#define KVM_MAGIC_FEAT_SR               (1 << 0)
+
+/* MASn, ESR, PIR, and high SPRGs */
+#define KVM_MAGIC_FEAT_MAS0_TO_SPRG7    (1 << 1)
 
 #ifdef __KERNEL__
 
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index 46efd1a265c..9d6dee0f7d4 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -66,6 +66,7 @@ extern int kvmppc_emulate_instruction(struct kvm_run *run,
 extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
 extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
 extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
+extern void kvmppc_decrementer_func(unsigned long data);
 extern int kvmppc_sanity_check(struct kvm_vcpu *vcpu);
 
 /* Core-specific hooks */
@@ -94,7 +95,7 @@ extern int kvmppc_core_vcpu_translate(struct kvm_vcpu *vcpu,
 extern void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 extern void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu);
 
-extern void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu);
+extern void kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu);
 extern int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu);
 extern void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags);
 extern void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu);
@@ -120,15 +121,17 @@ extern long kvmppc_alloc_hpt(struct kvm *kvm);
 extern void kvmppc_free_hpt(struct kvm *kvm);
 extern long kvmppc_prepare_vrma(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem);
-extern void kvmppc_map_vrma(struct kvm *kvm,
-                            struct kvm_userspace_memory_region *mem);
+extern void kvmppc_map_vrma(struct kvm_vcpu *vcpu,
+                        struct kvm_memory_slot *memslot, unsigned long porder);
 extern int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu);
 extern long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
                                 struct kvm_create_spapr_tce *args);
 extern long kvm_vm_ioctl_allocate_rma(struct kvm *kvm,
                                 struct kvm_allocate_rma *rma);
-extern struct kvmppc_rma_info *kvm_alloc_rma(void);
-extern void kvm_release_rma(struct kvmppc_rma_info *ri);
+extern struct kvmppc_linear_info *kvm_alloc_rma(void);
+extern void kvm_release_rma(struct kvmppc_linear_info *ri);
+extern struct kvmppc_linear_info *kvm_alloc_hpt(void);
+extern void kvm_release_hpt(struct kvmppc_linear_info *li);
 extern int kvmppc_core_init_vm(struct kvm *kvm);
 extern void kvmppc_core_destroy_vm(struct kvm *kvm);
 extern int kvmppc_core_prepare_memory_region(struct kvm *kvm,
@@ -175,6 +178,9 @@ int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
 void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
 int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
 
+int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg);
+int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg);
+
 void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid);
 
 #ifdef CONFIG_KVM_BOOK3S_64_HV
@@ -183,14 +189,19 @@ static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr)
         paca[cpu].kvm_hstate.xics_phys = addr;
 }
 
-extern void kvm_rma_init(void);
+extern void kvm_linear_init(void);
 
 #else
 static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr)
 {}
 
-static inline void kvm_rma_init(void)
+static inline void kvm_linear_init(void)
 {}
 #endif
 
+int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
+                              struct kvm_config_tlb *cfg);
+int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu *vcpu,
+                             struct kvm_dirty_tlb *cfg);
+
 #endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index bf37931d1ad..42ce570812c 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -99,9 +99,7 @@ struct machdep_calls {
 
         void            (*init_IRQ)(void);
 
-        /* Return an irq, or NO_IRQ to indicate there are none pending.
-         * If for some reason there is no irq, but the interrupt
-         * shouldn't be counted as spurious, return NO_IRQ_IGNORE. */
+        /* Return an irq, or NO_IRQ to indicate there are none pending. */
         unsigned int    (*get_irq)(void);
 
         /* PCI stuff */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index f5f89cafebd..cdb5421877e 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -41,9 +41,10 @@
 /* MAS registers bit definitions */
 
 #define MAS0_TLBSEL(x)          (((x) << 28) & 0x30000000)
-#define MAS0_ESEL(x)            (((x) << 16) & 0x0FFF0000)
-#define MAS0_NV(x)              ((x) & 0x00000FFF)
 #define MAS0_ESEL_MASK          0x0FFF0000
+#define MAS0_ESEL_SHIFT         16
+#define MAS0_ESEL(x)            (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK)
+#define MAS0_NV(x)              ((x) & 0x00000FFF)
 #define MAS0_HES                0x00004000
 #define MAS0_WQ_ALLWAYS         0x00000000
 #define MAS0_WQ_COND            0x00001000
@@ -167,6 +168,7 @@
 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 #define TLBnCFG_MAXSIZE_SHIFT   16
 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
+#define TLBnCFG_ASSOC_SHIFT     24
 
 /* TLBnPS encoding */
 #define TLBnPS_4K               0x00000004
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 412ba493cb9..1c65a59881e 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -108,11 +108,11 @@ extern char initial_stab[];
 #define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
 
 /* Values for PP (assumes Ks=0, Kp=1) */
-/* pp0 will always be 0 for linux     */
 #define PP_RWXX 0       /* Supervisor read/write, User none */
 #define PP_RWRX 1       /* Supervisor read/write, User read */
 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
 #define PP_RXRX 3       /* Supervisor read,       User read */
+#define PP_RXXX (HPTE_R_PP0 | 2)        /* Supervisor read, user none */
 
 #ifndef __ASSEMBLY__
 
@@ -267,7 +267,6 @@ extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
 
 extern void hpte_init_native(void);
 extern void hpte_init_lpar(void);
-extern void hpte_init_iSeries(void);
 extern void hpte_init_beat(void);
 extern void hpte_init_beat_v3(void);
 
@@ -325,9 +324,6 @@ extern void slb_set_size(u16 size);
  * WARNING - If you change these you must make sure the asm
  * implementations in slb_allocate (slb_low.S), do_stab_bolted
  * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
- *
- * You'll also need to change the precomputed VSID values in head.S
- * which are used by the iSeries firmware.
  */
 
 #define VSID_MULTIPLIER_256M    ASM_CONST(200730139)    /* 28-bit prime */
@@ -484,14 +480,6 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
                              | (ea >> SID_SHIFT_1T), 1T);
 }
 
-/*
- * This is only used on legacy iSeries in lparmap.c,
- * hence the 256MB segment assumption.
- */
-#define VSID_SCRAMBLE(pvsid)    (((pvsid) * VSID_MULTIPLIER_256M) %     \
-                                 VSID_MODULUS_256M)
-#define KERNEL_VSID(ea)         VSID_SCRAMBLE(GET_ESID(ea))
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 5d487657322..ac39e6a3b25 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -155,14 +155,7 @@ struct pci_dn {
 
         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 #ifdef CONFIG_EEH
-        int     class_code;             /* pci device class */
-        int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
-        int     eeh_config_addr;
-        int     eeh_pe_config_addr; /* new-style partition endpoint address */
-        int     eeh_check_count;        /* # times driver ignored error */
-        int     eeh_freeze_count;       /* # times this device froze up. */
-        int     eeh_false_positives;    /* # times this device reported #ff's */
-        u32     config_space[16];       /* saved PCI config space */
+        struct eeh_dev *edev;           /* eeh device */
 #endif
 #define IODA_INVALID_PE         (-1)
 #ifdef CONFIG_PPC_POWERNV
@@ -185,6 +178,13 @@ static inline int pci_device_from_OF_node(struct device_node *np,
         return 0;
 }
 
+#if defined(CONFIG_EEH)
+static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn)
+{
+        return PCI_DN(dn)->edev;
+}
+#endif
+
 /** Find the bus corresponding to the indicated device node */
 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index f54b3d26ce9..6653f2743c4 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -154,14 +154,6 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 
 #endif /* CONFIG_PPC64 */
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                        struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                        struct resource *res,
-                        struct pci_bus_region *region);
-
 extern void pcibios_claim_one_bus(struct pci_bus *b);
 
 extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
@@ -190,6 +182,7 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
                                  const struct resource *rsrc,
                                  resource_size_t *start, resource_size_t *end);
 
+extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
 extern void pcibios_setup_bus_devices(struct pci_bus *bus);
 extern void pcibios_setup_bus_self(struct pci_bus *bus);
 extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 1a8093fa8f7..078019b5b35 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -47,6 +47,8 @@ struct power_pmu {
  */
 #define PPMU_LIMITED_PMC5_6     1       /* PMC5/6 have limited function */
 #define PPMU_ALT_SIPR           2       /* uses alternate posn for SIPR/HV */
+#define PPMU_NO_SIPR            4       /* no SIPR/HV in MMCRA at all */
+#define PPMU_NO_CONT_SAMPLING   8       /* no continuous sampling */
 
 /*
  * Values for flags to get_alternatives()
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index e980faae422..d81f99430fe 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -45,6 +45,7 @@
 #define PPC_INST_MFSPR_DSCR_MASK        0xfc1fffff
 #define PPC_INST_MTSPR_DSCR             0x7c1103a6
 #define PPC_INST_MTSPR_DSCR_MASK        0xfc1fffff
+#define PPC_INST_SLBFEE                 0x7c0007a7
 
 #define PPC_INST_STRING                 0x7c00042a
 #define PPC_INST_STRING_MASK            0xfc0007fe
@@ -183,7 +184,8 @@
                                         __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
                                         __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
-
+#define PPC_SLBFEE_DOT(t, b)    stringify_in_c(.long PPC_INST_SLBFEE | \
+                                        __PPC_RT(t) | __PPC_RB(b))
 
 /*
  * Define what the VSX XX1 form instructions will look like, then add
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index e660b37aa7d..80fa704d410 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -45,8 +45,6 @@ extern void init_pci_config_tokens (void);
 extern unsigned long get_phb_buid (struct device_node *);
 extern int rtas_setup_phb(struct pci_controller *phb);
 
-extern unsigned long pci_probe_only;
-
 #ifdef CONFIG_EEH
 
 void pci_addr_cache_build(void);
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index b1a215eabef..9d7f0fb6902 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -216,6 +216,7 @@
 #define   DSISR_ISSTORE         0x02000000      /* access was a store */
 #define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
 #define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
+#define   DSISR_KEYFAULT        0x00200000      /* Key fault */
 #define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
@@ -237,6 +238,7 @@
 #define   LPCR_ISL      (1ul << (63-2))
 #define   LPCR_VC_SH    (63-2)
 #define   LPCR_DPFD_SH  (63-11)
+#define   LPCR_VRMASD   (0x1ful << (63-16))
 #define   LPCR_VRMA_L   (1ul << (63-12))
 #define   LPCR_VRMA_LP0 (1ul << (63-15))
 #define   LPCR_VRMA_LP1 (1ul << (63-16))
@@ -493,6 +495,9 @@
 #define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
+#define   SRR1_ISI_NOPT         0x40000000 /* ISI: Not found in hash */
+#define   SRR1_ISI_N_OR_G       0x10000000 /* ISI: Access is no-exec or G */
+#define   SRR1_ISI_PROT         0x08000000 /* ISI: Other protection fault */
 #define   SRR1_WAKEMASK         0x00380000 /* reason for wakeup */
 #define   SRR1_WAKESYSERR       0x00300000 /* System error */
 #define   SRR1_WAKEEE           0x00200000 /* External interrupt */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 9d6c37a11ee..557cff845de 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -74,7 +74,6 @@ struct rtas_suspend_me_data {
 /* RTAS event classes */
 #define RTAS_INTERNAL_ERROR             0x80000000 /* set bit 0 */
 #define RTAS_EPOW_WARNING               0x40000000 /* set bit 1 */
-#define RTAS_POWERMGM_EVENTS            0x20000000 /* set bit 2 */
 #define RTAS_HOTPLUG_EVENTS             0x10000000 /* set bit 3 */
 #define RTAS_IO_EVENTS                  0x08000000 /* set bit 4 */
 #define RTAS_EVENT_SCAN_ALL_EVENTS      0xffffffff
@@ -204,6 +203,39 @@ struct rtas_ext_event_log_v6 {
                                         /* Variable length.             */
 };
 
+/* pSeries event log format */
+
+/* Two bytes ASCII section IDs */
+#define PSERIES_ELOG_SECT_ID_PRIV_HDR           (('P' << 8) | 'H')
+#define PSERIES_ELOG_SECT_ID_USER_HDR           (('U' << 8) | 'H')
+#define PSERIES_ELOG_SECT_ID_PRIMARY_SRC        (('P' << 8) | 'S')
+#define PSERIES_ELOG_SECT_ID_EXTENDED_UH        (('E' << 8) | 'H')
+#define PSERIES_ELOG_SECT_ID_FAILING_MTMS       (('M' << 8) | 'T')
+#define PSERIES_ELOG_SECT_ID_SECONDARY_SRC      (('S' << 8) | 'S')
+#define PSERIES_ELOG_SECT_ID_DUMP_LOCATOR       (('D' << 8) | 'H')
+#define PSERIES_ELOG_SECT_ID_FW_ERROR           (('S' << 8) | 'W')
+#define PSERIES_ELOG_SECT_ID_IMPACT_PART_ID     (('L' << 8) | 'P')
+#define PSERIES_ELOG_SECT_ID_LOGIC_RESOURCE_ID  (('L' << 8) | 'R')
+#define PSERIES_ELOG_SECT_ID_HMC_ID             (('H' << 8) | 'M')
+#define PSERIES_ELOG_SECT_ID_EPOW               (('E' << 8) | 'P')
+#define PSERIES_ELOG_SECT_ID_IO_EVENT           (('I' << 8) | 'E')
+#define PSERIES_ELOG_SECT_ID_MANUFACT_INFO      (('M' << 8) | 'I')
+#define PSERIES_ELOG_SECT_ID_CALL_HOME          (('C' << 8) | 'H')
+#define PSERIES_ELOG_SECT_ID_USER_DEF           (('U' << 8) | 'D')
+
+/* Vendor specific Platform Event Log Format, Version 6, section header */
+struct pseries_errorlog {
+        uint16_t id;                    /* 0x00 2-byte ASCII section ID */
+        uint16_t length;                /* 0x02 Section length in bytes */
+        uint8_t version;                /* 0x04 Section version         */
+        uint8_t subtype;                /* 0x05 Section subtype         */
+        uint16_t creator_component;     /* 0x06 Creator component ID    */
+        uint8_t data[];                 /* 0x08 Start of section data   */
+};
+
+struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
+                                              uint16_t section_id);
+
 /*
  * This can be set by the rtas_flash module so that it can get called
  * as the absolutely last thing before the kernel terminates.
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index adba970ce91..ebc24dc5b1a 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -122,7 +122,6 @@ extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
 extern void smp_muxed_ipi_message_pass(int cpu, int msg);
 extern irqreturn_t smp_ipi_demux(void);
 
-void smp_init_iSeries(void);
 void smp_init_pSeries(void);
 void smp_init_cell(void);
 void smp_init_celleb(void);
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 8338aef5a4d..b3038817b8d 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -44,7 +44,6 @@ extern void __init udbg_init_debug_lpar_hvsi(void);
 extern void __init udbg_init_pmac_realmode(void);
 extern void __init udbg_init_maple_realmode(void);
 extern void __init udbg_init_pas_realmode(void);
-extern void __init udbg_init_iseries(void);
 extern void __init udbg_init_rtas_panel(void);
 extern void __init udbg_init_rtas_console(void);
 extern void __init udbg_init_debug_beat(void);
diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h
index 0a290a19594..6bfd5ffe1d4 100644
--- a/arch/powerpc/include/asm/vio.h
+++ b/arch/powerpc/include/asm/vio.h
@@ -69,6 +69,7 @@ struct vio_dev {
 };
 
 struct vio_driver {
+        const char *name;
         const struct vio_device_id *id_table;
         int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
         int (*remove)(struct vio_dev *dev);
@@ -76,10 +77,17 @@ struct vio_driver {
          * be loaded in a CMO environment if it uses DMA.
          */
         unsigned long (*get_desired_dma)(struct vio_dev *dev);
+        const struct dev_pm_ops *pm;
         struct device_driver driver;
 };
 
-extern int vio_register_driver(struct vio_driver *drv);
+extern int __vio_register_driver(struct vio_driver *drv, struct module *owner,
+                                 const char *mod_name);
+/*
+ * vio_register_driver must be a macro so that KBUILD_MODNAME can be expanded
+ */
+#define vio_register_driver(driver)             \
+        __vio_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
 extern void vio_unregister_driver(struct vio_driver *drv);
 
 extern int vio_cmo_entitlement_update(size_t);
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index cc492e48ddf..34b8afe94a5 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -412,16 +412,23 @@ int main(void)
         DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2));
         DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3));
 #endif
-        DEFINE(VCPU_SPRG4, offsetof(struct kvm_vcpu, arch.sprg4));
-        DEFINE(VCPU_SPRG5, offsetof(struct kvm_vcpu, arch.sprg5));
-        DEFINE(VCPU_SPRG6, offsetof(struct kvm_vcpu, arch.sprg6));
-        DEFINE(VCPU_SPRG7, offsetof(struct kvm_vcpu, arch.sprg7));
+        DEFINE(VCPU_SHARED_SPRG4, offsetof(struct kvm_vcpu_arch_shared, sprg4));
+        DEFINE(VCPU_SHARED_SPRG5, offsetof(struct kvm_vcpu_arch_shared, sprg5));
+        DEFINE(VCPU_SHARED_SPRG6, offsetof(struct kvm_vcpu_arch_shared, sprg6));
+        DEFINE(VCPU_SHARED_SPRG7, offsetof(struct kvm_vcpu_arch_shared, sprg7));
         DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid));
         DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1));
         DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared));
         DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
         DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr));
 
+        DEFINE(VCPU_SHARED_MAS0, offsetof(struct kvm_vcpu_arch_shared, mas0));
+        DEFINE(VCPU_SHARED_MAS1, offsetof(struct kvm_vcpu_arch_shared, mas1));
+        DEFINE(VCPU_SHARED_MAS2, offsetof(struct kvm_vcpu_arch_shared, mas2));
+        DEFINE(VCPU_SHARED_MAS7_3, offsetof(struct kvm_vcpu_arch_shared, mas7_3));
+        DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, mas4));
+        DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, mas6));
+
         /* book3s */
 #ifdef CONFIG_KVM_BOOK3S_64_HV
         DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
@@ -434,6 +441,7 @@ int main(void)
         DEFINE(KVM_LAST_VCPU, offsetof(struct kvm, arch.last_vcpu));
         DEFINE(KVM_LPCR, offsetof(struct kvm, arch.lpcr));
         DEFINE(KVM_RMOR, offsetof(struct kvm, arch.rmor));
+        DEFINE(KVM_VRMA_SLB_V, offsetof(struct kvm, arch.vrma_slb_v));
         DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr));
         DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
 #endif
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 2d0868a4e2f..cb705fdbb45 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -101,14 +101,14 @@ data_access_not_stab:
 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
 #endif
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD,
-                                 KVMTEST_PR, 0x300)
+                                 KVMTEST, 0x300)
 
         . = 0x380
         .globl data_access_slb_pSeries
 data_access_slb_pSeries:
         HMT_MEDIUM
         SET_SCRATCH0(r13)
-        EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
+        EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST, 0x380)
         std     r3,PACA_EXSLB+EX_R3(r13)
         mfspr   r3,SPRN_DAR
 #ifdef __DISABLED__
@@ -330,8 +330,8 @@ do_stab_bolted_pSeries:
         EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
 #endif /* CONFIG_POWER4_ONLY */
 
-        KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x300)
-        KVM_HANDLER_PR_SKIP(PACA_EXSLB, EXC_STD, 0x380)
+        KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x300)
+        KVM_HANDLER_SKIP(PACA_EXSLB, EXC_STD, 0x380)
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x400)
         KVM_HANDLER_PR(PACA_EXSLB, EXC_STD, 0x480)
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 2c5635dce05..243dbabfe74 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -208,8 +208,8 @@ notrace void arch_local_irq_restore(unsigned long en)
          * we are checking the "new" CPU instead of the old one. This
          * is only a problem if an event happened on the "old" CPU.
          *
-         * External interrupt events on non-iseries will have caused
-         * interrupts to be hard-disabled, so there is no problem, we
+         * External interrupt events will have caused interrupts to
+         * be hard-disabled, so there is no problem, we
          * cannot have preempted.
          */
         irq_happened = get_irq_happened();
@@ -445,9 +445,9 @@ void do_IRQ(struct pt_regs *regs)
         may_hard_irq_enable();
 
         /* And finally process it */
-        if (irq != NO_IRQ && irq != NO_IRQ_IGNORE)
+        if (irq != NO_IRQ)
                 handle_one_irq(irq);
-        else if (irq != NO_IRQ_IGNORE)
+        else
                 __get_cpu_var(irq_stat).spurious_irqs++;
 
         irq_exit();
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 2985338d0e1..62bdf238966 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2010 SUSE Linux Products GmbH. All rights reserved.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * Authors:
  *     Alexander Graf <agraf@suse.de>
@@ -29,6 +30,7 @@
 #include <asm/sections.h>
 #include <asm/cacheflush.h>
 #include <asm/disassemble.h>
+#include <asm/ppc-opcode.h>
 
 #define KVM_MAGIC_PAGE          (-4096L)
 #define magic_var(x) KVM_MAGIC_PAGE + offsetof(struct kvm_vcpu_arch_shared, x)
@@ -41,34 +43,30 @@
 #define KVM_INST_B              0x48000000
 #define KVM_INST_B_MASK         0x03ffffff
 #define KVM_INST_B_MAX          0x01ffffff
+#define KVM_INST_LI             0x38000000
 
 #define KVM_MASK_RT             0x03e00000
 #define KVM_RT_30               0x03c00000
 #define KVM_MASK_RB             0x0000f800
 #define KVM_INST_MFMSR          0x7c0000a6
-#define KVM_INST_MFSPR_SPRG0    0x7c1042a6
-#define KVM_INST_MFSPR_SPRG1    0x7c1142a6
-#define KVM_INST_MFSPR_SPRG2    0x7c1242a6
-#define KVM_INST_MFSPR_SPRG3    0x7c1342a6
-#define KVM_INST_MFSPR_SRR0     0x7c1a02a6
-#define KVM_INST_MFSPR_SRR1     0x7c1b02a6
-#define KVM_INST_MFSPR_DAR      0x7c1302a6
-#define KVM_INST_MFSPR_DSISR    0x7c1202a6
-
-#define KVM_INST_MTSPR_SPRG0    0x7c1043a6
-#define KVM_INST_MTSPR_SPRG1    0x7c1143a6
-#define KVM_INST_MTSPR_SPRG2    0x7c1243a6
-#define KVM_INST_MTSPR_SPRG3    0x7c1343a6
-#define KVM_INST_MTSPR_SRR0     0x7c1a03a6
-#define KVM_INST_MTSPR_SRR1     0x7c1b03a6
-#define KVM_INST_MTSPR_DAR      0x7c1303a6
-#define KVM_INST_MTSPR_DSISR    0x7c1203a6
+
+#define SPR_FROM                0
+#define SPR_TO                  0x100
+
+#define KVM_INST_SPR(sprn, moveto) (0x7c0002a6 | \
+                                    (((sprn) & 0x1f) << 16) | \
+                                    (((sprn) & 0x3e0) << 6) | \
+                                    (moveto))
+
+#define KVM_INST_MFSPR(sprn)    KVM_INST_SPR(sprn, SPR_FROM)
+#define KVM_INST_MTSPR(sprn)    KVM_INST_SPR(sprn, SPR_TO)
 
 #define KVM_INST_TLBSYNC        0x7c00046c
 #define KVM_INST_MTMSRD_L0      0x7c000164
 #define KVM_INST_MTMSRD_L1      0x7c010164
 #define KVM_INST_MTMSR          0x7c000124
 
+#define KVM_INST_WRTEE          0x7c000106
 #define KVM_INST_WRTEEI_0       0x7c000146
 #define KVM_INST_WRTEEI_1       0x7c008146
 
@@ -270,26 +268,27 @@ static void kvm_patch_ins_mtmsr(u32 *inst, u32 rt)
 
 #ifdef CONFIG_BOOKE
 
-extern u32 kvm_emulate_wrteei_branch_offs;
-extern u32 kvm_emulate_wrteei_ee_offs;
-extern u32 kvm_emulate_wrteei_len;
-extern u32 kvm_emulate_wrteei[];
+extern u32 kvm_emulate_wrtee_branch_offs;
+extern u32 kvm_emulate_wrtee_reg_offs;
+extern u32 kvm_emulate_wrtee_orig_ins_offs;
+extern u32 kvm_emulate_wrtee_len;
+extern u32 kvm_emulate_wrtee[];
 
-static void kvm_patch_ins_wrteei(u32 *inst)
+static void kvm_patch_ins_wrtee(u32 *inst, u32 rt, int imm_one)
 {
         u32 *p;
         int distance_start;
         int distance_end;
         ulong next_inst;
 
-        p = kvm_alloc(kvm_emulate_wrteei_len * 4);
+        p = kvm_alloc(kvm_emulate_wrtee_len * 4);
         if (!p)
                 return;
 
         /* Find out where we are and put everything there */
         distance_start = (ulong)p - (ulong)inst;
         next_inst = ((ulong)inst + 4);
-        distance_end = next_inst - (ulong)&p[kvm_emulate_wrteei_branch_offs];
+        distance_end = next_inst - (ulong)&p[kvm_emulate_wrtee_branch_offs];
 
         /* Make sure we only write valid b instructions */
         if (distance_start > KVM_INST_B_MAX) {
@@ -298,10 +297,65 @@ static void kvm_patch_ins_wrteei(u32 *inst)
         }
 
         /* Modify the chunk to fit the invocation */
-        memcpy(p, kvm_emulate_wrteei, kvm_emulate_wrteei_len * 4);
-        p[kvm_emulate_wrteei_branch_offs] |= distance_end & KVM_INST_B_MASK;
-        p[kvm_emulate_wrteei_ee_offs] |= (*inst & MSR_EE);
-        flush_icache_range((ulong)p, (ulong)p + kvm_emulate_wrteei_len * 4);
+        memcpy(p, kvm_emulate_wrtee, kvm_emulate_wrtee_len * 4);
+        p[kvm_emulate_wrtee_branch_offs] |= distance_end & KVM_INST_B_MASK;
+
+        if (imm_one) {
+                p[kvm_emulate_wrtee_reg_offs] =
+                        KVM_INST_LI | __PPC_RT(30) | MSR_EE;
+        } else {
+                /* Make clobbered registers work too */
+                switch (get_rt(rt)) {
+                case 30:
+                        kvm_patch_ins_ll(&p[kvm_emulate_wrtee_reg_offs],
+                                         magic_var(scratch2), KVM_RT_30);
+                        break;
+                case 31:
+                        kvm_patch_ins_ll(&p[kvm_emulate_wrtee_reg_offs],
+                                         magic_var(scratch1), KVM_RT_30);
+                        break;
+                default:
+                        p[kvm_emulate_wrtee_reg_offs] |= rt;
+                        break;
+                }
+        }
+
+        p[kvm_emulate_wrtee_orig_ins_offs] = *inst;
+        flush_icache_range((ulong)p, (ulong)p + kvm_emulate_wrtee_len * 4);
+
+        /* Patch the invocation */
+        kvm_patch_ins_b(inst, distance_start);
+}
+
+extern u32 kvm_emulate_wrteei_0_branch_offs;
+extern u32 kvm_emulate_wrteei_0_len;
+extern u32 kvm_emulate_wrteei_0[];
+
+static void kvm_patch_ins_wrteei_0(u32 *inst)
+{
+        u32 *p;
+        int distance_start;
+        int distance_end;
+        ulong next_inst;
+
+        p = kvm_alloc(kvm_emulate_wrteei_0_len * 4);
+        if (!p)
+                return;
+
+        /* Find out where we are and put everything there */
+        distance_start = (ulong)p - (ulong)inst;
+        next_inst = ((ulong)inst + 4);
+        distance_end = next_inst - (ulong)&p[kvm_emulate_wrteei_0_branch_offs];
+
+        /* Make sure we only write valid b instructions */
+        if (distance_start > KVM_INST_B_MAX) {
+                kvm_patching_worked = false;
+                return;
+        }
+
+        memcpy(p, kvm_emulate_wrteei_0, kvm_emulate_wrteei_0_len * 4);
+        p[kvm_emulate_wrteei_0_branch_offs] |= distance_end & KVM_INST_B_MASK;
+        flush_icache_range((ulong)p, (ulong)p + kvm_emulate_wrteei_0_len * 4);
 
         /* Patch the invocation */
         kvm_patch_ins_b(inst, distance_start);
@@ -380,56 +434,191 @@ static void kvm_check_ins(u32 *inst, u32 features)
         case KVM_INST_MFMSR:
                 kvm_patch_ins_ld(inst, magic_var(msr), inst_rt);
                 break;
-        case KVM_INST_MFSPR_SPRG0:
+        case KVM_INST_MFSPR(SPRN_SPRG0):
                 kvm_patch_ins_ld(inst, magic_var(sprg0), inst_rt);
                 break;
-        case KVM_INST_MFSPR_SPRG1:
+        case KVM_INST_MFSPR(SPRN_SPRG1):
                 kvm_patch_ins_ld(inst, magic_var(sprg1), inst_rt);
                 break;
-        case KVM_INST_MFSPR_SPRG2:
+        case KVM_INST_MFSPR(SPRN_SPRG2):
                 kvm_patch_ins_ld(inst, magic_var(sprg2), inst_rt);
                 break;
-        case KVM_INST_MFSPR_SPRG3:
+        case KVM_INST_MFSPR(SPRN_SPRG3):
                 kvm_patch_ins_ld(inst, magic_var(sprg3), inst_rt);
                 break;
-        case KVM_INST_MFSPR_SRR0:
+        case KVM_INST_MFSPR(SPRN_SRR0):
                 kvm_patch_ins_ld(inst, magic_var(srr0), inst_rt);
                 break;
-        case KVM_INST_MFSPR_SRR1:
+        case KVM_INST_MFSPR(SPRN_SRR1):
                 kvm_patch_ins_ld(inst, magic_var(srr1), inst_rt);
                 break;
-        case KVM_INST_MFSPR_DAR:
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MFSPR(SPRN_DEAR):
+#else
+        case KVM_INST_MFSPR(SPRN_DAR):
+#endif
                 kvm_patch_ins_ld(inst, magic_var(dar), inst_rt);
                 break;
-        case KVM_INST_MFSPR_DSISR:
+        case KVM_INST_MFSPR(SPRN_DSISR):
                 kvm_patch_ins_lwz(inst, magic_var(dsisr), inst_rt);
                 break;
 
+#ifdef CONFIG_PPC_BOOK3E_MMU
+        case KVM_INST_MFSPR(SPRN_MAS0):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(mas0), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_MAS1):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(mas1), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_MAS2):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_ld(inst, magic_var(mas2), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_MAS3):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(mas7_3) + 4, inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_MAS4):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(mas4), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_MAS6):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(mas6), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_MAS7):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(mas7_3), inst_rt);
+                break;
+#endif /* CONFIG_PPC_BOOK3E_MMU */
+
+        case KVM_INST_MFSPR(SPRN_SPRG4):
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MFSPR(SPRN_SPRG4R):
+#endif
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_ld(inst, magic_var(sprg4), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_SPRG5):
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MFSPR(SPRN_SPRG5R):
+#endif
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_ld(inst, magic_var(sprg5), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_SPRG6):
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MFSPR(SPRN_SPRG6R):
+#endif
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_ld(inst, magic_var(sprg6), inst_rt);
+                break;
+        case KVM_INST_MFSPR(SPRN_SPRG7):
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MFSPR(SPRN_SPRG7R):
+#endif
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_ld(inst, magic_var(sprg7), inst_rt);
+                break;
+
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MFSPR(SPRN_ESR):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(esr), inst_rt);
+                break;
+#endif
+
+        case KVM_INST_MFSPR(SPRN_PIR):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_lwz(inst, magic_var(pir), inst_rt);
+                break;
+
+
         /* Stores */
-        case KVM_INST_MTSPR_SPRG0:
+        case KVM_INST_MTSPR(SPRN_SPRG0):
                 kvm_patch_ins_std(inst, magic_var(sprg0), inst_rt);
                 break;
-        case KVM_INST_MTSPR_SPRG1:
+        case KVM_INST_MTSPR(SPRN_SPRG1):
                 kvm_patch_ins_std(inst, magic_var(sprg1), inst_rt);
                 break;
-        case KVM_INST_MTSPR_SPRG2:
+        case KVM_INST_MTSPR(SPRN_SPRG2):
                 kvm_patch_ins_std(inst, magic_var(sprg2), inst_rt);
                 break;
-        case KVM_INST_MTSPR_SPRG3:
+        case KVM_INST_MTSPR(SPRN_SPRG3):
                 kvm_patch_ins_std(inst, magic_var(sprg3), inst_rt);
                 break;
-        case KVM_INST_MTSPR_SRR0:
+        case KVM_INST_MTSPR(SPRN_SRR0):
                 kvm_patch_ins_std(inst, magic_var(srr0), inst_rt);
                 break;
-        case KVM_INST_MTSPR_SRR1:
+        case KVM_INST_MTSPR(SPRN_SRR1):
                 kvm_patch_ins_std(inst, magic_var(srr1), inst_rt);
                 break;
-        case KVM_INST_MTSPR_DAR:
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MTSPR(SPRN_DEAR):
+#else
+        case KVM_INST_MTSPR(SPRN_DAR):
+#endif
                 kvm_patch_ins_std(inst, magic_var(dar), inst_rt);
                 break;
-        case KVM_INST_MTSPR_DSISR:
+        case KVM_INST_MTSPR(SPRN_DSISR):
                 kvm_patch_ins_stw(inst, magic_var(dsisr), inst_rt);
                 break;
+#ifdef CONFIG_PPC_BOOK3E_MMU
+        case KVM_INST_MTSPR(SPRN_MAS0):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_stw(inst, magic_var(mas0), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_MAS1):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_stw(inst, magic_var(mas1), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_MAS2):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_std(inst, magic_var(mas2), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_MAS3):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_stw(inst, magic_var(mas7_3) + 4, inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_MAS4):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_stw(inst, magic_var(mas4), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_MAS6):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_stw(inst, magic_var(mas6), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_MAS7):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_stw(inst, magic_var(mas7_3), inst_rt);
+                break;
+#endif /* CONFIG_PPC_BOOK3E_MMU */
+
+        case KVM_INST_MTSPR(SPRN_SPRG4):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_std(inst, magic_var(sprg4), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_SPRG5):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_std(inst, magic_var(sprg5), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_SPRG6):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_std(inst, magic_var(sprg6), inst_rt);
+                break;
+        case KVM_INST_MTSPR(SPRN_SPRG7):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_std(inst, magic_var(sprg7), inst_rt);
+                break;
+
+#ifdef CONFIG_BOOKE
+        case KVM_INST_MTSPR(SPRN_ESR):
+                if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
+                        kvm_patch_ins_stw(inst, magic_var(esr), inst_rt);
+                break;
+#endif
 
         /* Nops */
         case KVM_INST_TLBSYNC:
@@ -444,6 +633,11 @@ static void kvm_check_ins(u32 *inst, u32 features)
         case KVM_INST_MTMSRD_L0:
                 kvm_patch_ins_mtmsr(inst, inst_rt);
                 break;
+#ifdef CONFIG_BOOKE
+        case KVM_INST_WRTEE:
+                kvm_patch_ins_wrtee(inst, inst_rt, 0);
+                break;
+#endif
         }
 
         switch (inst_no_rt & ~KVM_MASK_RB) {
@@ -461,13 +655,19 @@ static void kvm_check_ins(u32 *inst, u32 features)
         switch (_inst) {
 #ifdef CONFIG_BOOKE
         case KVM_INST_WRTEEI_0:
+                kvm_patch_ins_wrteei_0(inst);
+                break;
+
         case KVM_INST_WRTEEI_1:
-                kvm_patch_ins_wrteei(inst);
+                kvm_patch_ins_wrtee(inst, 0, 1);
                 break;
 #endif
         }
 }
 
+extern u32 kvm_template_start[];
+extern u32 kvm_template_end[];
+
 static void kvm_use_magic_page(void)
 {
         u32 *p;
@@ -488,8 +688,23 @@ static void kvm_use_magic_page(void)
         start = (void*)_stext;
         end = (void*)_etext;
 
-        for (p = start; p < end; p++)
+        /*
+         * Being interrupted in the middle of patching would
+         * be bad for SPRG4-7, which KVM can't keep in sync
+         * with emulated accesses because reads don't trap.
+         */
+        local_irq_disable();
+
+        for (p = start; p < end; p++) {
+                /* Avoid patching the template code */
+                if (p >= kvm_template_start && p < kvm_template_end) {
+                        p = kvm_template_end - 1;
+                        continue;
+                }
                 kvm_check_ins(p, features);
+        }
+
+        local_irq_enable();
 
         printk(KERN_INFO "KVM: Live patching for a fast VM %s\n",
                          kvm_patching_worked ? "worked" : "failed");
diff --git a/arch/powerpc/kernel/kvm_emul.S b/arch/powerpc/kernel/kvm_emul.S
index f2b1b2523e6..e291cf3cf95 100644
--- a/arch/powerpc/kernel/kvm_emul.S
+++ b/arch/powerpc/kernel/kvm_emul.S
@@ -13,6 +13,7 @@
  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
  * Copyright SUSE Linux Products GmbH 2010
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * Authors: Alexander Graf <agraf@suse.de>
  */
@@ -65,6 +66,9 @@ kvm_hypercall_start:
            shared->critical == r1 and r2 is always != r1 */             \
         STL64(r2, KVM_MAGIC_PAGE + KVM_MAGIC_CRITICAL, 0);
 
+.global kvm_template_start
+kvm_template_start:
+
 .global kvm_emulate_mtmsrd
 kvm_emulate_mtmsrd:
 
@@ -167,6 +171,9 @@ maybe_stay_in_guest:
 kvm_emulate_mtmsr_reg2:
         ori     r30, r0, 0
 
+        /* Put MSR into magic page because we don't call mtmsr */
+        STL64(r30, KVM_MAGIC_PAGE + KVM_MAGIC_MSR, 0)
+
         /* Check if we have to fetch an interrupt */
         lwz     r31, (KVM_MAGIC_PAGE + KVM_MAGIC_INT)(0)
         cmpwi   r31, 0
@@ -174,15 +181,10 @@ kvm_emulate_mtmsr_reg2:
 
         /* Check if we may trigger an interrupt */
         andi.   r31, r30, MSR_EE
-        beq     no_mtmsr
-
-        b       do_mtmsr
+        bne     do_mtmsr
 
 no_mtmsr:
 
-        /* Put MSR into magic page because we don't call mtmsr */
-        STL64(r30, KVM_MAGIC_PAGE + KVM_MAGIC_MSR, 0)
-
         SCRATCH_RESTORE
 
         /* Go back to caller */
@@ -210,24 +212,80 @@ kvm_emulate_mtmsr_orig_ins_offs:
 kvm_emulate_mtmsr_len:
         .long (kvm_emulate_mtmsr_end - kvm_emulate_mtmsr) / 4
 
+/* also used for wrteei 1 */
+.global kvm_emulate_wrtee
+kvm_emulate_wrtee:
+
+        SCRATCH_SAVE
+
+        /* Fetch old MSR in r31 */
+        LL64(r31, KVM_MAGIC_PAGE + KVM_MAGIC_MSR, 0)
+
+        /* Insert new MSR[EE] */
+kvm_emulate_wrtee_reg:
+        ori     r30, r0, 0
+        rlwimi  r31, r30, 0, MSR_EE
+
+        /*
+         * If MSR[EE] is now set, check for a pending interrupt.
+         * We could skip this if MSR[EE] was already on, but that
+         * should be rare, so don't bother.
+         */
+        andi.   r30, r30, MSR_EE
+
+        /* Put MSR into magic page because we don't call wrtee */
+        STL64(r31, KVM_MAGIC_PAGE + KVM_MAGIC_MSR, 0)
+
+        beq     no_wrtee
+
+        /* Check if we have to fetch an interrupt */
+        lwz     r30, (KVM_MAGIC_PAGE + KVM_MAGIC_INT)(0)
+        cmpwi   r30, 0
+        bne     do_wrtee
+
+no_wrtee:
+        SCRATCH_RESTORE
+
+        /* Go back to caller */
+kvm_emulate_wrtee_branch:
+        b       .
+
+do_wrtee:
+        SCRATCH_RESTORE
 
+        /* Just fire off the wrtee if it's critical */
+kvm_emulate_wrtee_orig_ins:
+        wrtee   r0
 
-.global kvm_emulate_wrteei
-kvm_emulate_wrteei:
+        b       kvm_emulate_wrtee_branch
 
+kvm_emulate_wrtee_end:
+
+.global kvm_emulate_wrtee_branch_offs
+kvm_emulate_wrtee_branch_offs:
+        .long (kvm_emulate_wrtee_branch - kvm_emulate_wrtee) / 4
+
+.global kvm_emulate_wrtee_reg_offs
+kvm_emulate_wrtee_reg_offs:
+        .long (kvm_emulate_wrtee_reg - kvm_emulate_wrtee) / 4
+
+.global kvm_emulate_wrtee_orig_ins_offs
+kvm_emulate_wrtee_orig_ins_offs:
+        .long (kvm_emulate_wrtee_orig_ins - kvm_emulate_wrtee) / 4
+
+.global kvm_emulate_wrtee_len
+kvm_emulate_wrtee_len:
+        .long (kvm_emulate_wrtee_end - kvm_emulate_wrtee) / 4
+
+.global kvm_emulate_wrteei_0
+kvm_emulate_wrteei_0:
         SCRATCH_SAVE
 
         /* Fetch old MSR in r31 */
         LL64(r31, KVM_MAGIC_PAGE + KVM_MAGIC_MSR, 0)
 
         /* Remove MSR_EE from old MSR */
-        li      r30, 0
-        ori     r30, r30, MSR_EE
-        andc    r31, r31, r30
-
-        /* OR new MSR_EE onto the old MSR */
-kvm_emulate_wrteei_ee:
-        ori     r31, r31, 0
+        rlwinm  r31, r31, 0, ~MSR_EE
 
         /* Write new MSR value back */
         STL64(r31, KVM_MAGIC_PAGE + KVM_MAGIC_MSR, 0)
@@ -235,22 +293,17 @@ kvm_emulate_wrteei_ee:
         SCRATCH_RESTORE
 
         /* Go back to caller */
-kvm_emulate_wrteei_branch:
+kvm_emulate_wrteei_0_branch:
         b       .
-kvm_emulate_wrteei_end:
-
-.global kvm_emulate_wrteei_branch_offs
-kvm_emulate_wrteei_branch_offs:
-        .long (kvm_emulate_wrteei_branch - kvm_emulate_wrteei) / 4
+kvm_emulate_wrteei_0_end:
 
-.global kvm_emulate_wrteei_ee_offs
-kvm_emulate_wrteei_ee_offs:
-        .long (kvm_emulate_wrteei_ee - kvm_emulate_wrteei) / 4
-
-.global kvm_emulate_wrteei_len
-kvm_emulate_wrteei_len:
-        .long (kvm_emulate_wrteei_end - kvm_emulate_wrteei) / 4
+.global kvm_emulate_wrteei_0_branch_offs
+kvm_emulate_wrteei_0_branch_offs:
+        .long (kvm_emulate_wrteei_0_branch - kvm_emulate_wrteei_0) / 4
 
+.global kvm_emulate_wrteei_0_len
+kvm_emulate_wrteei_0_len:
+        .long (kvm_emulate_wrteei_0_end - kvm_emulate_wrteei_0) / 4
 
 .global kvm_emulate_mtsrin
 kvm_emulate_mtsrin:
@@ -300,3 +353,6 @@ kvm_emulate_mtsrin_orig_ins_offs:
 .global kvm_emulate_mtsrin_len
 kvm_emulate_mtsrin_len:
         .long (kvm_emulate_mtsrin_end - kvm_emulate_mtsrin) / 4
+
+.global kvm_template_end
+kvm_template_end:
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index d0373bcb7c9..8e78e93c818 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -49,9 +49,6 @@ static int global_phb_number;		/* Global phb counter */
 /* ISA Memory physical address */
 resource_size_t isa_mem_base;
 
-/* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
-unsigned int pci_flags = 0;
-
 
 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 
@@ -834,60 +831,6 @@ int pci_proc_domain(struct pci_bus *bus)
         return 1;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        region->start = (res->start - offset) & mask;
-        region->end = (res->end - offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-        res->start = (region->start + offset) & mask;
-        res->end = (region->end + offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/* Fixup a bus resource into a linux resource */
-static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
-{
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        res->start = (res->start + offset) & mask;
-        res->end = (res->end + offset) & mask;
-}
-
-
 /* This header fixup will do the resource fixup for all devices as they are
  * probed, but not for bridge ranges
  */
@@ -927,18 +870,11 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
                         continue;
                 }
 
-                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
+                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
                          pci_name(dev), i,
                          (unsigned long long)res->start,\
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
-
-                fixup_resource(res, dev);
-
-                pr_debug("PCI:%s            %016llx-%016llx\n",
-                         pci_name(dev),
-                         (unsigned long long)res->start,
-                         (unsigned long long)res->end);
         }
 
         /* Call machine specific resource fixup */
@@ -1040,27 +976,18 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
                         continue;
                 }
 
-                pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
+                pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
                          pci_name(dev), i,
                          (unsigned long long)res->start,\
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
 
-                /* Perform fixup */
-                fixup_resource(res, dev);
-
                 /* Try to detect uninitialized P2P bridge resources,
                  * and clear them out so they get re-assigned later
                  */
                 if (pcibios_uninitialized_bridge_resource(bus, res)) {
                         res->flags = 0;
                         pr_debug("PCI:%s            (unassigned)\n", pci_name(dev));
-                } else {
-
-                        pr_debug("PCI:%s            %016llx-%016llx\n",
-                                 pci_name(dev),
-                                 (unsigned long long)res->start,
-                                 (unsigned long long)res->end);
                 }
         }
 }
@@ -1550,6 +1477,11 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return pci_enable_resources(dev, mask);
 }
 
+resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
+{
+        return (unsigned long) hose->io_base_virt - _IO_BASE;
+}
+
 static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
 {
         struct resource *res;
@@ -1574,7 +1506,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                  (unsigned long long)res->start,
                  (unsigned long long)res->end,
                  (unsigned long)res->flags);
-        pci_add_resource(resources, res);
+        pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose));
 
         /* Hookup PHB Memory resources */
         for (i = 0; i < 3; ++i) {
@@ -1597,7 +1529,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                          (unsigned long long)res->start,
                          (unsigned long long)res->end,
                          (unsigned long)res->flags);
-                pci_add_resource(resources, res);
+                pci_add_resource_offset(resources, res, hose->pci_mem_offset);
         }
 
         pr_debug("PCI: PHB MEM offset     = %016llx\n",
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index fdd1a3d951d..4b06ec5a502 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -219,9 +219,9 @@ void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
         struct resource *res = &hose->io_resource;
 
         /* Fixup IO space offset */
-        io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
-        res->start = (res->start + io_offset) & 0xffffffffu;
-        res->end = (res->end + io_offset) & 0xffffffffu;
+        io_offset = pcibios_io_space_offset(hose);
+        res->start += io_offset;
+        res->end += io_offset;
 }
 
 static int __init pcibios_init(void)
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 3318d39b7d4..94a54f61d34 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -33,8 +33,6 @@
 #include <asm/machdep.h>
 #include <asm/ppc-pci.h>
 
-unsigned long pci_probe_only = 1;
-
 /* pci_io_base -- the base address from which io bars are offsets.
  * This is the lowest I/O base address (so bar values are always positive),
  * and it *must* be the start of ISA space if an ISA bus exists because
@@ -55,9 +53,6 @@ static int __init pcibios_init(void)
          */
         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 
-        if (pci_probe_only)
-                pci_add_flags(PCI_PROBE_ONLY);
-
         /* On ppc64, we always enable PCI domains and we keep domain 0
          * backward compatible in /proc for video cards
          */
@@ -173,7 +168,7 @@ static int __devinit pcibios_map_phb_io_space(struct pci_controller *hose)
                 return -ENOMEM;
 
         /* Fixup hose IO resource */
-        io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
+        io_virt_offset = pcibios_io_space_offset(hose);
         hose->io_resource.start += io_virt_offset;
         hose->io_resource.end += io_virt_offset;
 
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index b37d0b5a796..89dde171a6f 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -75,6 +75,7 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
 {
         u64 base, size;
         unsigned int flags;
+        struct pci_bus_region region;
         struct resource *res;
         const u32 *addrs;
         u32 i;
@@ -106,10 +107,11 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
                         continue;
                 }
-                res->start = base;
-                res->end = base + size - 1;
                 res->flags = flags;
                 res->name = pci_name(dev);
+                region.start = base;
+                region.end = base + size - 1;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 }
 
@@ -209,6 +211,7 @@ void __devinit of_scan_pci_bridge(struct pci_dev *dev)
         struct pci_bus *bus;
         const u32 *busrange, *ranges;
         int len, i, mode;
+        struct pci_bus_region region;
         struct resource *res;
         unsigned int flags;
         u64 size;
@@ -270,9 +273,10 @@ void __devinit of_scan_pci_bridge(struct pci_dev *dev)
                         res = bus->resource[i];
                         ++i;
                 }
-                res->start = of_read_number(&ranges[1], 2);
-                res->end = res->start + size - 1;
                 res->flags = flags;
+                region.start = of_read_number(&ranges[1], 2);
+                region.end = region.start + size - 1;
+                pcibios_bus_to_resource(dev, res, &region);
         }
         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
                 bus->number);
diff --git a/arch/powerpc/kernel/pmc.c b/arch/powerpc/kernel/pmc.c
index a841a9d136a..58eaa3ddf7b 100644
--- a/arch/powerpc/kernel/pmc.c
+++ b/arch/powerpc/kernel/pmc.c
@@ -13,6 +13,7 @@
  */
 
 #include <linux/errno.h>
+#include <linux/bug.h>
 #include <linux/spinlock.h>
 #include <linux/export.h>
 
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index b2aae219b4b..99860273211 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -446,7 +446,7 @@ static void __init __attribute__((noreturn)) prom_panic(const char *reason)
         if (RELOC(of_platform) == PLATFORM_POWERMAC)
                 asm("trap\n");
 
-        /* ToDo: should put up an SRC here on p/iSeries */
+        /* ToDo: should put up an SRC here on pSeries */
         call_prom("exit", 0, 0);
 
         for (;;)                        /* should never get here */
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 3dc679930d0..fcec38241f7 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -867,6 +867,40 @@ int rtas_ibm_suspend_me(struct rtas_args *args)
 }
 #endif
 
+/**
+ * Find a specific pseries error log in an RTAS extended event log.
+ * @log: RTAS error/event log
+ * @section_id: two character section identifier
+ *
+ * Returns a pointer to the specified errorlog or NULL if not found.
+ */
+struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
+                                              uint16_t section_id)
+{
+        struct rtas_ext_event_log_v6 *ext_log =
+                (struct rtas_ext_event_log_v6 *)log->buffer;
+        struct pseries_errorlog *sect;
+        unsigned char *p, *log_end;
+
+        /* Check that we understand the format */
+        if (log->extended_log_length < sizeof(struct rtas_ext_event_log_v6) ||
+            ext_log->log_format != RTAS_V6EXT_LOG_FORMAT_EVENT_LOG ||
+            ext_log->company_id != RTAS_V6EXT_COMPANY_ID_IBM)
+                return NULL;
+
+        log_end = log->buffer + log->extended_log_length;
+        p = ext_log->vendor_log;
+
+        while (p < log_end) {
+                sect = (struct pseries_errorlog *)p;
+                if (sect->id == section_id)
+                        return sect;
+                p += sect->length;
+        }
+
+        return NULL;
+}
+
 asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
 {
         struct rtas_args args;
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 517bd86bc3f..179af906dcd 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -279,7 +279,7 @@ void __init find_and_init_phbs(void)
         eeh_dev_phb_init();
 
         /*
-         * pci_probe_only and pci_assign_all_buses can be set via properties
+         * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
          * in chosen.
          */
         if (of_chosen) {
@@ -287,8 +287,12 @@ void __init find_and_init_phbs(void)
 
                 prop = of_get_property(of_chosen,
                                 "linux,pci-probe-only", NULL);
-                if (prop)
-                        pci_probe_only = *prop;
+                if (prop) {
+                        if (*prop)
+                                pci_add_flags(PCI_PROBE_ONLY);
+                        else
+                                pci_clear_flags(PCI_PROBE_ONLY);
+                }
 
 #ifdef CONFIG_PPC32 /* Will be made generic soon */
                 prop = of_get_property(of_chosen,
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 6d639b2d24c..389bd4f0cdb 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -597,7 +597,7 @@ void __init setup_arch(char **cmdline_p)
         /* Initialize the MMU context management stuff */
         mmu_context_init();
 
-        kvm_rma_init();
+        kvm_linear_init();
 
         ppc64_boot_msg(0x15, "Setup Done");
 }
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index 57fa2c0a531..c39c1ca77f4 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -46,9 +46,6 @@ void __init udbg_early_init(void)
 #elif defined(CONFIG_PPC_EARLY_DEBUG_MAPLE)
         /* Maple real mode debug */
         udbg_init_maple_realmode();
-#elif defined(CONFIG_PPC_EARLY_DEBUG_ISERIES)
-        /* For iSeries - hit Ctrl-x Ctrl-x to see the output */
-        udbg_init_iseries();
 #elif defined(CONFIG_PPC_EARLY_DEBUG_BEAT)
         udbg_init_debug_beat();
 #elif defined(CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE)
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 1ce1ec410a1..9eb5b9b536a 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -262,17 +262,11 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
          * the "data" page of the vDSO or you'll stop getting kernel updates
          * and your nice userland gettimeofday will be totally dead.
          * It's fine to use that for setting breakpoints in the vDSO code
-         * pages though
-         *
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
+         * pages though.
          */
         rc = install_special_mapping(mm, vdso_base, vdso_pages << PAGE_SHIFT,
                                      VM_READ|VM_EXEC|
-                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                     VM_ALWAYSDUMP,
+                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                      vdso_pagelist);
         if (rc) {
                 current->mm->context.vdso_base = 0;
@@ -726,10 +720,10 @@ static int __init vdso_init(void)
         vdso_data->version.minor = SYSTEMCFG_MINOR;
         vdso_data->processor = mfspr(SPRN_PVR);
         /*
-         * Fake the old platform number for pSeries and iSeries and add
+         * Fake the old platform number for pSeries and add
          * in LPAR bit if necessary
          */
-        vdso_data->platform = machine_is(iseries) ? 0x200 : 0x100;
+        vdso_data->platform = 0x100;
         if (firmware_has_feature(FW_FEATURE_LPAR))
                 vdso_data->platform |= 1;
         vdso_data->physicalMemorySize = memblock_phys_mem_size();
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index bca3fc427b4..b2f7c8480bf 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -1159,17 +1159,21 @@ static int vio_bus_remove(struct device *dev)
  * vio_register_driver: - Register a new vio driver
  * @drv:        The vio_driver structure to be registered.
  */
-int vio_register_driver(struct vio_driver *viodrv)
+int __vio_register_driver(struct vio_driver *viodrv, struct module *owner,
+                          const char *mod_name)
 {
-        printk(KERN_DEBUG "%s: driver %s registering\n", __func__,
-                viodrv->driver.name);
+        pr_debug("%s: driver %s registering\n", __func__, viodrv->name);
 
         /* fill in 'struct driver' fields */
+        viodrv->driver.name = viodrv->name;
+        viodrv->driver.pm = viodrv->pm;
         viodrv->driver.bus = &vio_bus_type;
+        viodrv->driver.owner = owner;
+        viodrv->driver.mod_name = mod_name;
 
         return driver_register(&viodrv->driver);
 }
-EXPORT_SYMBOL(vio_register_driver);
+EXPORT_SYMBOL(__vio_register_driver);
 
 /**
  * vio_unregister_driver - Remove registration of vio driver.
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index 78133deb4b6..8f64709ae33 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -69,6 +69,7 @@ config KVM_BOOK3S_64
 config KVM_BOOK3S_64_HV
         bool "KVM support for POWER7 and PPC970 using hypervisor mode in host"
         depends on KVM_BOOK3S_64
+        select MMU_NOTIFIER
         ---help---
           Support running unmodified book3s_64 guest kernels in
           virtual machines on POWER7 and PPC970 processors that have
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index e41ac6f7dcf..7d54f4ed6d9 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -258,7 +258,7 @@ static bool clear_irqprio(struct kvm_vcpu *vcpu, unsigned int priority)
         return true;
 }
 
-void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu)
+void kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
 {
         unsigned long *pending = &vcpu->arch.pending_exceptions;
         unsigned long old_pending = vcpu->arch.pending_exceptions;
@@ -423,10 +423,10 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         regs->sprg1 = vcpu->arch.shared->sprg1;
         regs->sprg2 = vcpu->arch.shared->sprg2;
         regs->sprg3 = vcpu->arch.shared->sprg3;
-        regs->sprg4 = vcpu->arch.sprg4;
-        regs->sprg5 = vcpu->arch.sprg5;
-        regs->sprg6 = vcpu->arch.sprg6;
-        regs->sprg7 = vcpu->arch.sprg7;
+        regs->sprg4 = vcpu->arch.shared->sprg4;
+        regs->sprg5 = vcpu->arch.shared->sprg5;
+        regs->sprg6 = vcpu->arch.shared->sprg6;
+        regs->sprg7 = vcpu->arch.shared->sprg7;
 
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
@@ -450,10 +450,10 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         vcpu->arch.shared->sprg1 = regs->sprg1;
         vcpu->arch.shared->sprg2 = regs->sprg2;
         vcpu->arch.shared->sprg3 = regs->sprg3;
-        vcpu->arch.sprg4 = regs->sprg4;
-        vcpu->arch.sprg5 = regs->sprg5;
-        vcpu->arch.sprg6 = regs->sprg6;
-        vcpu->arch.sprg7 = regs->sprg7;
+        vcpu->arch.shared->sprg4 = regs->sprg4;
+        vcpu->arch.shared->sprg5 = regs->sprg5;
+        vcpu->arch.shared->sprg6 = regs->sprg6;
+        vcpu->arch.shared->sprg7 = regs->sprg7;
 
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
@@ -477,41 +477,10 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
         return 0;
 }
 
-/*
- * Get (and clear) the dirty memory log for a memory slot.
- */
-int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
-                                      struct kvm_dirty_log *log)
+void kvmppc_decrementer_func(unsigned long data)
 {
-        struct kvm_memory_slot *memslot;
-        struct kvm_vcpu *vcpu;
-        ulong ga, ga_end;
-        int is_dirty = 0;
-        int r;
-        unsigned long n;
-
-        mutex_lock(&kvm->slots_lock);
-
-        r = kvm_get_dirty_log(kvm, log, &is_dirty);
-        if (r)
-                goto out;
-
-        /* If nothing is dirty, don't bother messing with page tables. */
-        if (is_dirty) {
-                memslot = id_to_memslot(kvm->memslots, log->slot);
+        struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
 
-                ga = memslot->base_gfn << PAGE_SHIFT;
-                ga_end = ga + (memslot->npages << PAGE_SHIFT);
-
-                kvm_for_each_vcpu(n, vcpu, kvm)
-                        kvmppc_mmu_pte_pflush(vcpu, ga, ga_end);
-
-                n = kvm_dirty_bitmap_bytes(memslot);
-                memset(memslot->dirty_bitmap, 0, n);
-        }
-
-        r = 0;
-out:
-        mutex_unlock(&kvm->slots_lock);
-        return r;
+        kvmppc_core_queue_dec(vcpu);
+        kvm_vcpu_kick(vcpu);
 }
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c
index 9fecbfbce77..f922c29bb23 100644
--- a/arch/powerpc/kvm/book3s_32_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_32_mmu_host.c
@@ -151,13 +151,15 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
         bool primary = false;
         bool evict = false;
         struct hpte_cache *pte;
+        int r = 0;
 
         /* Get host physical address for gpa */
         hpaddr = kvmppc_gfn_to_pfn(vcpu, orig_pte->raddr >> PAGE_SHIFT);
         if (is_error_pfn(hpaddr)) {
                 printk(KERN_INFO "Couldn't get guest page for gfn %lx!\n",
                                  orig_pte->eaddr);
-                return -EINVAL;
+                r = -EINVAL;
+                goto out;
         }
         hpaddr <<= PAGE_SHIFT;
 
@@ -249,7 +251,8 @@ next_pteg:
 
         kvmppc_mmu_hpte_cache_map(vcpu, pte);
 
-        return 0;
+out:
+        return r;
 }
 
 static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid)
@@ -297,12 +300,14 @@ int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr)
         u64 gvsid;
         u32 sr;
         struct kvmppc_sid_map *map;
-        struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu);
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        int r = 0;
 
         if (vcpu->arch.mmu.esid_to_vsid(vcpu, esid, &gvsid)) {
                 /* Invalidate an entry */
                 svcpu->sr[esid] = SR_INVALID;
-                return -ENOENT;
+                r = -ENOENT;
+                goto out;
         }
 
         map = find_sid_vsid(vcpu, gvsid);
@@ -315,17 +320,21 @@ int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr)
 
         dprintk_sr("MMU: mtsr %d, 0x%x\n", esid, sr);
 
-        return 0;
+out:
+        svcpu_put(svcpu);
+        return r;
 }
 
 void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu)
 {
         int i;
-        struct kvmppc_book3s_shadow_vcpu *svcpu = to_svcpu(vcpu);
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
 
         dprintk_sr("MMU: flushing all segments (%d)\n", ARRAY_SIZE(svcpu->sr));
         for (i = 0; i < ARRAY_SIZE(svcpu->sr); i++)
                 svcpu->sr[i] = SR_INVALID;
+
+        svcpu_put(svcpu);
 }
 
 void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index fa2f08434ba..6f87f39a1ac 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -88,12 +88,14 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
         int vflags = 0;
         int attempt = 0;
         struct kvmppc_sid_map *map;
+        int r = 0;
 
         /* Get host physical address for gpa */
         hpaddr = kvmppc_gfn_to_pfn(vcpu, orig_pte->raddr >> PAGE_SHIFT);
         if (is_error_pfn(hpaddr)) {
                 printk(KERN_INFO "Couldn't get guest page for gfn %lx!\n", orig_pte->eaddr);
-                return -EINVAL;
+                r = -EINVAL;
+                goto out;
         }
         hpaddr <<= PAGE_SHIFT;
         hpaddr |= orig_pte->raddr & (~0xfffULL & ~PAGE_MASK);
@@ -110,7 +112,8 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
                 printk(KERN_ERR "KVM: Segment map for 0x%llx (0x%lx) failed\n",
                                 vsid, orig_pte->eaddr);
                 WARN_ON(true);
-                return -EINVAL;
+                r = -EINVAL;
+                goto out;
         }
 
         vsid = map->host_vsid;
@@ -131,8 +134,10 @@ map_again:
 
         /* In case we tried normal mapping already, let's nuke old entries */
         if (attempt > 1)
-                if (ppc_md.hpte_remove(hpteg) < 0)
-                        return -1;
+                if (ppc_md.hpte_remove(hpteg) < 0) {
+                        r = -1;
+                        goto out;
+                }
 
         ret = ppc_md.hpte_insert(hpteg, va, hpaddr, rflags, vflags, MMU_PAGE_4K, MMU_SEGSIZE_256M);
 
@@ -162,7 +167,8 @@ map_again:
                 kvmppc_mmu_hpte_cache_map(vcpu, pte);
         }
 
-        return 0;
+out:
+        return r;
 }
 
 static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid)
@@ -207,25 +213,30 @@ static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid)
 
 static int kvmppc_mmu_next_segment(struct kvm_vcpu *vcpu, ulong esid)
 {
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
         int i;
         int max_slb_size = 64;
         int found_inval = -1;
         int r;
 
-        if (!to_svcpu(vcpu)->slb_max)
-                to_svcpu(vcpu)->slb_max = 1;
+        if (!svcpu->slb_max)
+                svcpu->slb_max = 1;
 
         /* Are we overwriting? */
-        for (i = 1; i < to_svcpu(vcpu)->slb_max; i++) {
-                if (!(to_svcpu(vcpu)->slb[i].esid & SLB_ESID_V))
+        for (i = 1; i < svcpu->slb_max; i++) {
+                if (!(svcpu->slb[i].esid & SLB_ESID_V))
                         found_inval = i;
-                else if ((to_svcpu(vcpu)->slb[i].esid & ESID_MASK) == esid)
-                        return i;
+                else if ((svcpu->slb[i].esid & ESID_MASK) == esid) {
+                        r = i;
+                        goto out;
+                }
         }
 
         /* Found a spare entry that was invalidated before */
-        if (found_inval > 0)
-                return found_inval;
+        if (found_inval > 0) {
+                r = found_inval;
+                goto out;
+        }
 
         /* No spare invalid entry, so create one */
 
@@ -233,30 +244,35 @@ static int kvmppc_mmu_next_segment(struct kvm_vcpu *vcpu, ulong esid)
                 max_slb_size = mmu_slb_size;
 
         /* Overflowing -> purge */
-        if ((to_svcpu(vcpu)->slb_max) == max_slb_size)
+        if ((svcpu->slb_max) == max_slb_size)
                 kvmppc_mmu_flush_segments(vcpu);
 
-        r = to_svcpu(vcpu)->slb_max;
-        to_svcpu(vcpu)->slb_max++;
+        r = svcpu->slb_max;
+        svcpu->slb_max++;
 
+out:
+        svcpu_put(svcpu);
         return r;
 }
 
 int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr)
 {
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
         u64 esid = eaddr >> SID_SHIFT;
         u64 slb_esid = (eaddr & ESID_MASK) | SLB_ESID_V;
         u64 slb_vsid = SLB_VSID_USER;
         u64 gvsid;
         int slb_index;
         struct kvmppc_sid_map *map;
+        int r = 0;
 
         slb_index = kvmppc_mmu_next_segment(vcpu, eaddr & ESID_MASK);
 
         if (vcpu->arch.mmu.esid_to_vsid(vcpu, esid, &gvsid)) {
                 /* Invalidate an entry */
-                to_svcpu(vcpu)->slb[slb_index].esid = 0;
-                return -ENOENT;
+                svcpu->slb[slb_index].esid = 0;
+                r = -ENOENT;
+                goto out;
         }
 
         map = find_sid_vsid(vcpu, gvsid);
@@ -269,18 +285,22 @@ int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr)
         slb_vsid &= ~SLB_VSID_KP;
         slb_esid |= slb_index;
 
-        to_svcpu(vcpu)->slb[slb_index].esid = slb_esid;
-        to_svcpu(vcpu)->slb[slb_index].vsid = slb_vsid;
+        svcpu->slb[slb_index].esid = slb_esid;
+        svcpu->slb[slb_index].vsid = slb_vsid;
 
         trace_kvm_book3s_slbmte(slb_vsid, slb_esid);
 
-        return 0;
+out:
+        svcpu_put(svcpu);
+        return r;
 }
 
 void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu)
 {
-        to_svcpu(vcpu)->slb_max = 1;
-        to_svcpu(vcpu)->slb[0].esid = 0;
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        svcpu->slb_max = 1;
+        svcpu->slb[0].esid = 0;
+        svcpu_put(svcpu);
 }
 
 void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index bc3a2ea9421..ddc485a529f 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -23,6 +23,7 @@
 #include <linux/gfp.h>
 #include <linux/slab.h>
 #include <linux/hugetlb.h>
+#include <linux/vmalloc.h>
 
 #include <asm/tlbflush.h>
 #include <asm/kvm_ppc.h>
@@ -33,15 +34,6 @@
 #include <asm/ppc-opcode.h>
 #include <asm/cputable.h>
 
-/* For now use fixed-size 16MB page table */
-#define HPT_ORDER       24
-#define HPT_NPTEG       (1ul << (HPT_ORDER - 7))        /* 128B per pteg */
-#define HPT_HASH_MASK   (HPT_NPTEG - 1)
-
-/* Pages in the VRMA are 16MB pages */
-#define VRMA_PAGE_ORDER 24
-#define VRMA_VSID       0x1ffffffUL     /* 1TB VSID reserved for VRMA */
-
 /* POWER7 has 10-bit LPIDs, PPC970 has 6-bit LPIDs */
 #define MAX_LPID_970    63
 #define NR_LPIDS        (LPID_RSVD + 1)
@@ -51,21 +43,41 @@ long kvmppc_alloc_hpt(struct kvm *kvm)
 {
         unsigned long hpt;
         unsigned long lpid;
+        struct revmap_entry *rev;
+        struct kvmppc_linear_info *li;
+
+        /* Allocate guest's hashed page table */
+        li = kvm_alloc_hpt();
+        if (li) {
+                /* using preallocated memory */
+                hpt = (ulong)li->base_virt;
+                kvm->arch.hpt_li = li;
+        } else {
+                /* using dynamic memory */
+                hpt = __get_free_pages(GFP_KERNEL|__GFP_ZERO|__GFP_REPEAT|
+                                       __GFP_NOWARN, HPT_ORDER - PAGE_SHIFT);
+        }
 
-        hpt = __get_free_pages(GFP_KERNEL|__GFP_ZERO|__GFP_REPEAT|__GFP_NOWARN,
-                               HPT_ORDER - PAGE_SHIFT);
         if (!hpt) {
                 pr_err("kvm_alloc_hpt: Couldn't alloc HPT\n");
                 return -ENOMEM;
         }
         kvm->arch.hpt_virt = hpt;
 
+        /* Allocate reverse map array */
+        rev = vmalloc(sizeof(struct revmap_entry) * HPT_NPTE);
+        if (!rev) {
+                pr_err("kvmppc_alloc_hpt: Couldn't alloc reverse map array\n");
+                goto out_freehpt;
+        }
+        kvm->arch.revmap = rev;
+
+        /* Allocate the guest's logical partition ID */
         do {
                 lpid = find_first_zero_bit(lpid_inuse, NR_LPIDS);
                 if (lpid >= NR_LPIDS) {
                         pr_err("kvm_alloc_hpt: No LPIDs free\n");
-                        free_pages(hpt, HPT_ORDER - PAGE_SHIFT);
-                        return -ENOMEM;
+                        goto out_freeboth;
                 }
         } while (test_and_set_bit(lpid, lpid_inuse));
 
@@ -74,37 +86,64 @@ long kvmppc_alloc_hpt(struct kvm *kvm)
 
         pr_info("KVM guest htab at %lx, LPID %lx\n", hpt, lpid);
         return 0;
+
+ out_freeboth:
+        vfree(rev);
+ out_freehpt:
+        free_pages(hpt, HPT_ORDER - PAGE_SHIFT);
+        return -ENOMEM;
 }
 
 void kvmppc_free_hpt(struct kvm *kvm)
 {
         clear_bit(kvm->arch.lpid, lpid_inuse);
-        free_pages(kvm->arch.hpt_virt, HPT_ORDER - PAGE_SHIFT);
+        vfree(kvm->arch.revmap);
+        if (kvm->arch.hpt_li)
+                kvm_release_hpt(kvm->arch.hpt_li);
+        else
+                free_pages(kvm->arch.hpt_virt, HPT_ORDER - PAGE_SHIFT);
+}
+
+/* Bits in first HPTE dword for pagesize 4k, 64k or 16M */
+static inline unsigned long hpte0_pgsize_encoding(unsigned long pgsize)
+{
+        return (pgsize > 0x1000) ? HPTE_V_LARGE : 0;
+}
+
+/* Bits in second HPTE dword for pagesize 4k, 64k or 16M */
+static inline unsigned long hpte1_pgsize_encoding(unsigned long pgsize)
+{
+        return (pgsize == 0x10000) ? 0x1000 : 0;
 }
 
-void kvmppc_map_vrma(struct kvm *kvm, struct kvm_userspace_memory_region *mem)
+void kvmppc_map_vrma(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot,
+                     unsigned long porder)
 {
         unsigned long i;
-        unsigned long npages = kvm->arch.ram_npages;
-        unsigned long pfn;
-        unsigned long *hpte;
-        unsigned long hash;
-        struct kvmppc_pginfo *pginfo = kvm->arch.ram_pginfo;
+        unsigned long npages;
+        unsigned long hp_v, hp_r;
+        unsigned long addr, hash;
+        unsigned long psize;
+        unsigned long hp0, hp1;
+        long ret;
 
-        if (!pginfo)
-                return;
+        psize = 1ul << porder;
+        npages = memslot->npages >> (porder - PAGE_SHIFT);
 
         /* VRMA can't be > 1TB */
-        if (npages > 1ul << (40 - kvm->arch.ram_porder))
-                npages = 1ul << (40 - kvm->arch.ram_porder);
+        if (npages > 1ul << (40 - porder))
+                npages = 1ul << (40 - porder);
         /* Can't use more than 1 HPTE per HPTEG */
         if (npages > HPT_NPTEG)
                 npages = HPT_NPTEG;
 
+        hp0 = HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)) |
+                HPTE_V_BOLTED | hpte0_pgsize_encoding(psize);
+        hp1 = hpte1_pgsize_encoding(psize) |
+                HPTE_R_R | HPTE_R_C | HPTE_R_M | PP_RWXX;
+
         for (i = 0; i < npages; ++i) {
-                pfn = pginfo[i].pfn;
-                if (!pfn)
-                        break;
+                addr = i << porder;
                 /* can't use hpt_hash since va > 64 bits */
                 hash = (i ^ (VRMA_VSID ^ (VRMA_VSID << 25))) & HPT_HASH_MASK;
                 /*
@@ -113,15 +152,15 @@ void kvmppc_map_vrma(struct kvm *kvm, struct kvm_userspace_memory_region *mem)
                  * at most one HPTE per HPTEG, we just assume entry 7
                  * is available and use it.
                  */
-                hpte = (unsigned long *) (kvm->arch.hpt_virt + (hash << 7));
-                hpte += 7 * 2;
-                /* HPTE low word - RPN, protection, etc. */
-                hpte[1] = (pfn << PAGE_SHIFT) | HPTE_R_R | HPTE_R_C |
-                        HPTE_R_M | PP_RWXX;
-                wmb();
-                hpte[0] = HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)) |
-                        (i << (VRMA_PAGE_ORDER - 16)) | HPTE_V_BOLTED |
-                        HPTE_V_LARGE | HPTE_V_VALID;
+                hash = (hash << 3) + 7;
+                hp_v = hp0 | ((addr >> 16) & ~0x7fUL);
+                hp_r = hp1 | addr;
+                ret = kvmppc_virtmode_h_enter(vcpu, H_EXACT, hash, hp_v, hp_r);
+                if (ret != H_SUCCESS) {
+                        pr_err("KVM: map_vrma at %lx failed, ret=%ld\n",
+                               addr, ret);
+                        break;
+                }
         }
 }
 
@@ -158,10 +197,814 @@ static void kvmppc_mmu_book3s_64_hv_reset_msr(struct kvm_vcpu *vcpu)
         kvmppc_set_msr(vcpu, MSR_SF | MSR_ME);
 }
 
+/*
+ * This is called to get a reference to a guest page if there isn't
+ * one already in the kvm->arch.slot_phys[][] arrays.
+ */
+static long kvmppc_get_guest_page(struct kvm *kvm, unsigned long gfn,
+                                  struct kvm_memory_slot *memslot,
+                                  unsigned long psize)
+{
+        unsigned long start;
+        long np, err;
+        struct page *page, *hpage, *pages[1];
+        unsigned long s, pgsize;
+        unsigned long *physp;
+        unsigned int is_io, got, pgorder;
+        struct vm_area_struct *vma;
+        unsigned long pfn, i, npages;
+
+        physp = kvm->arch.slot_phys[memslot->id];
+        if (!physp)
+                return -EINVAL;
+        if (physp[gfn - memslot->base_gfn])
+                return 0;
+
+        is_io = 0;
+        got = 0;
+        page = NULL;
+        pgsize = psize;
+        err = -EINVAL;
+        start = gfn_to_hva_memslot(memslot, gfn);
+
+        /* Instantiate and get the page we want access to */
+        np = get_user_pages_fast(start, 1, 1, pages);
+        if (np != 1) {
+                /* Look up the vma for the page */
+                down_read(&current->mm->mmap_sem);
+                vma = find_vma(current->mm, start);
+                if (!vma || vma->vm_start > start ||
+                    start + psize > vma->vm_end ||
+                    !(vma->vm_flags & VM_PFNMAP))
+                        goto up_err;
+                is_io = hpte_cache_bits(pgprot_val(vma->vm_page_prot));
+                pfn = vma->vm_pgoff + ((start - vma->vm_start) >> PAGE_SHIFT);
+                /* check alignment of pfn vs. requested page size */
+                if (psize > PAGE_SIZE && (pfn & ((psize >> PAGE_SHIFT) - 1)))
+                        goto up_err;
+                up_read(&current->mm->mmap_sem);
+
+        } else {
+                page = pages[0];
+                got = KVMPPC_GOT_PAGE;
+
+                /* See if this is a large page */
+                s = PAGE_SIZE;
+                if (PageHuge(page)) {
+                        hpage = compound_head(page);
+                        s <<= compound_order(hpage);
+                        /* Get the whole large page if slot alignment is ok */
+                        if (s > psize && slot_is_aligned(memslot, s) &&
+                            !(memslot->userspace_addr & (s - 1))) {
+                                start &= ~(s - 1);
+                                pgsize = s;
+                                page = hpage;
+                        }
+                }
+                if (s < psize)
+                        goto out;
+                pfn = page_to_pfn(page);
+        }
+
+        npages = pgsize >> PAGE_SHIFT;
+        pgorder = __ilog2(npages);
+        physp += (gfn - memslot->base_gfn) & ~(npages - 1);
+        spin_lock(&kvm->arch.slot_phys_lock);
+        for (i = 0; i < npages; ++i) {
+                if (!physp[i]) {
+                        physp[i] = ((pfn + i) << PAGE_SHIFT) +
+                                got + is_io + pgorder;
+                        got = 0;
+                }
+        }
+        spin_unlock(&kvm->arch.slot_phys_lock);
+        err = 0;
+
+ out:
+        if (got) {
+                if (PageHuge(page))
+                        page = compound_head(page);
+                put_page(page);
+        }
+        return err;
+
+ up_err:
+        up_read(&current->mm->mmap_sem);
+        return err;
+}
+
+/*
+ * We come here on a H_ENTER call from the guest when we are not
+ * using mmu notifiers and we don't have the requested page pinned
+ * already.
+ */
+long kvmppc_virtmode_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
+                        long pte_index, unsigned long pteh, unsigned long ptel)
+{
+        struct kvm *kvm = vcpu->kvm;
+        unsigned long psize, gpa, gfn;
+        struct kvm_memory_slot *memslot;
+        long ret;
+
+        if (kvm->arch.using_mmu_notifiers)
+                goto do_insert;
+
+        psize = hpte_page_size(pteh, ptel);
+        if (!psize)
+                return H_PARAMETER;
+
+        pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
+
+        /* Find the memslot (if any) for this address */
+        gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
+        gfn = gpa >> PAGE_SHIFT;
+        memslot = gfn_to_memslot(kvm, gfn);
+        if (memslot && !(memslot->flags & KVM_MEMSLOT_INVALID)) {
+                if (!slot_is_aligned(memslot, psize))
+                        return H_PARAMETER;
+                if (kvmppc_get_guest_page(kvm, gfn, memslot, psize) < 0)
+                        return H_PARAMETER;
+        }
+
+ do_insert:
+        /* Protect linux PTE lookup from page table destruction */
+        rcu_read_lock_sched();  /* this disables preemption too */
+        vcpu->arch.pgdir = current->mm->pgd;
+        ret = kvmppc_h_enter(vcpu, flags, pte_index, pteh, ptel);
+        rcu_read_unlock_sched();
+        if (ret == H_TOO_HARD) {
+                /* this can't happen */
+                pr_err("KVM: Oops, kvmppc_h_enter returned too hard!\n");
+                ret = H_RESOURCE;       /* or something */
+        }
+        return ret;
+
+}
+
+static struct kvmppc_slb *kvmppc_mmu_book3s_hv_find_slbe(struct kvm_vcpu *vcpu,
+                                                         gva_t eaddr)
+{
+        u64 mask;
+        int i;
+
+        for (i = 0; i < vcpu->arch.slb_nr; i++) {
+                if (!(vcpu->arch.slb[i].orige & SLB_ESID_V))
+                        continue;
+
+                if (vcpu->arch.slb[i].origv & SLB_VSID_B_1T)
+                        mask = ESID_MASK_1T;
+                else
+                        mask = ESID_MASK;
+
+                if (((vcpu->arch.slb[i].orige ^ eaddr) & mask) == 0)
+                        return &vcpu->arch.slb[i];
+        }
+        return NULL;
+}
+
+static unsigned long kvmppc_mmu_get_real_addr(unsigned long v, unsigned long r,
+                        unsigned long ea)
+{
+        unsigned long ra_mask;
+
+        ra_mask = hpte_page_size(v, r) - 1;
+        return (r & HPTE_R_RPN & ~ra_mask) | (ea & ra_mask);
+}
+
 static int kvmppc_mmu_book3s_64_hv_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
-                                struct kvmppc_pte *gpte, bool data)
+                        struct kvmppc_pte *gpte, bool data)
+{
+        struct kvm *kvm = vcpu->kvm;
+        struct kvmppc_slb *slbe;
+        unsigned long slb_v;
+        unsigned long pp, key;
+        unsigned long v, gr;
+        unsigned long *hptep;
+        int index;
+        int virtmode = vcpu->arch.shregs.msr & (data ? MSR_DR : MSR_IR);
+
+        /* Get SLB entry */
+        if (virtmode) {
+                slbe = kvmppc_mmu_book3s_hv_find_slbe(vcpu, eaddr);
+                if (!slbe)
+                        return -EINVAL;
+                slb_v = slbe->origv;
+        } else {
+                /* real mode access */
+                slb_v = vcpu->kvm->arch.vrma_slb_v;
+        }
+
+        /* Find the HPTE in the hash table */
+        index = kvmppc_hv_find_lock_hpte(kvm, eaddr, slb_v,
+                                         HPTE_V_VALID | HPTE_V_ABSENT);
+        if (index < 0)
+                return -ENOENT;
+        hptep = (unsigned long *)(kvm->arch.hpt_virt + (index << 4));
+        v = hptep[0] & ~HPTE_V_HVLOCK;
+        gr = kvm->arch.revmap[index].guest_rpte;
+
+        /* Unlock the HPTE */
+        asm volatile("lwsync" : : : "memory");
+        hptep[0] = v;
+
+        gpte->eaddr = eaddr;
+        gpte->vpage = ((v & HPTE_V_AVPN) << 4) | ((eaddr >> 12) & 0xfff);
+
+        /* Get PP bits and key for permission check */
+        pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
+        key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
+        key &= slb_v;
+
+        /* Calculate permissions */
+        gpte->may_read = hpte_read_permission(pp, key);
+        gpte->may_write = hpte_write_permission(pp, key);
+        gpte->may_execute = gpte->may_read && !(gr & (HPTE_R_N | HPTE_R_G));
+
+        /* Storage key permission check for POWER7 */
+        if (data && virtmode && cpu_has_feature(CPU_FTR_ARCH_206)) {
+                int amrfield = hpte_get_skey_perm(gr, vcpu->arch.amr);
+                if (amrfield & 1)
+                        gpte->may_read = 0;
+                if (amrfield & 2)
+                        gpte->may_write = 0;
+        }
+
+        /* Get the guest physical address */
+        gpte->raddr = kvmppc_mmu_get_real_addr(v, gr, eaddr);
+        return 0;
+}
+
+/*
+ * Quick test for whether an instruction is a load or a store.
+ * If the instruction is a load or a store, then this will indicate
+ * which it is, at least on server processors.  (Embedded processors
+ * have some external PID instructions that don't follow the rule
+ * embodied here.)  If the instruction isn't a load or store, then
+ * this doesn't return anything useful.
+ */
+static int instruction_is_store(unsigned int instr)
+{
+        unsigned int mask;
+
+        mask = 0x10000000;
+        if ((instr & 0xfc000000) == 0x7c000000)
+                mask = 0x100;           /* major opcode 31 */
+        return (instr & mask) != 0;
+}
+
+static int kvmppc_hv_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu,
+                                  unsigned long gpa, int is_store)
+{
+        int ret;
+        u32 last_inst;
+        unsigned long srr0 = kvmppc_get_pc(vcpu);
+
+        /* We try to load the last instruction.  We don't let
+         * emulate_instruction do it as it doesn't check what
+         * kvmppc_ld returns.
+         * If we fail, we just return to the guest and try executing it again.
+         */
+        if (vcpu->arch.last_inst == KVM_INST_FETCH_FAILED) {
+                ret = kvmppc_ld(vcpu, &srr0, sizeof(u32), &last_inst, false);
+                if (ret != EMULATE_DONE || last_inst == KVM_INST_FETCH_FAILED)
+                        return RESUME_GUEST;
+                vcpu->arch.last_inst = last_inst;
+        }
+
+        /*
+         * WARNING: We do not know for sure whether the instruction we just
+         * read from memory is the same that caused the fault in the first
+         * place.  If the instruction we read is neither an load or a store,
+         * then it can't access memory, so we don't need to worry about
+         * enforcing access permissions.  So, assuming it is a load or
+         * store, we just check that its direction (load or store) is
+         * consistent with the original fault, since that's what we
+         * checked the access permissions against.  If there is a mismatch
+         * we just return and retry the instruction.
+         */
+
+        if (instruction_is_store(vcpu->arch.last_inst) != !!is_store)
+                return RESUME_GUEST;
+
+        /*
+         * Emulated accesses are emulated by looking at the hash for
+         * translation once, then performing the access later. The
+         * translation could be invalidated in the meantime in which
+         * point performing the subsequent memory access on the old
+         * physical address could possibly be a security hole for the
+         * guest (but not the host).
+         *
+         * This is less of an issue for MMIO stores since they aren't
+         * globally visible. It could be an issue for MMIO loads to
+         * a certain extent but we'll ignore it for now.
+         */
+
+        vcpu->arch.paddr_accessed = gpa;
+        return kvmppc_emulate_mmio(run, vcpu);
+}
+
+int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
+                                unsigned long ea, unsigned long dsisr)
+{
+        struct kvm *kvm = vcpu->kvm;
+        unsigned long *hptep, hpte[3], r;
+        unsigned long mmu_seq, psize, pte_size;
+        unsigned long gfn, hva, pfn;
+        struct kvm_memory_slot *memslot;
+        unsigned long *rmap;
+        struct revmap_entry *rev;
+        struct page *page, *pages[1];
+        long index, ret, npages;
+        unsigned long is_io;
+        unsigned int writing, write_ok;
+        struct vm_area_struct *vma;
+        unsigned long rcbits;
+
+        /*
+         * Real-mode code has already searched the HPT and found the
+         * entry we're interested in.  Lock the entry and check that
+         * it hasn't changed.  If it has, just return and re-execute the
+         * instruction.
+         */
+        if (ea != vcpu->arch.pgfault_addr)
+                return RESUME_GUEST;
+        index = vcpu->arch.pgfault_index;
+        hptep = (unsigned long *)(kvm->arch.hpt_virt + (index << 4));
+        rev = &kvm->arch.revmap[index];
+        preempt_disable();
+        while (!try_lock_hpte(hptep, HPTE_V_HVLOCK))
+                cpu_relax();
+        hpte[0] = hptep[0] & ~HPTE_V_HVLOCK;
+        hpte[1] = hptep[1];
+        hpte[2] = r = rev->guest_rpte;
+        asm volatile("lwsync" : : : "memory");
+        hptep[0] = hpte[0];
+        preempt_enable();
+
+        if (hpte[0] != vcpu->arch.pgfault_hpte[0] ||
+            hpte[1] != vcpu->arch.pgfault_hpte[1])
+                return RESUME_GUEST;
+
+        /* Translate the logical address and get the page */
+        psize = hpte_page_size(hpte[0], r);
+        gfn = hpte_rpn(r, psize);
+        memslot = gfn_to_memslot(kvm, gfn);
+
+        /* No memslot means it's an emulated MMIO region */
+        if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID)) {
+                unsigned long gpa = (gfn << PAGE_SHIFT) | (ea & (psize - 1));
+                return kvmppc_hv_emulate_mmio(run, vcpu, gpa,
+                                              dsisr & DSISR_ISSTORE);
+        }
+
+        if (!kvm->arch.using_mmu_notifiers)
+                return -EFAULT;         /* should never get here */
+
+        /* used to check for invalidations in progress */
+        mmu_seq = kvm->mmu_notifier_seq;
+        smp_rmb();
+
+        is_io = 0;
+        pfn = 0;
+        page = NULL;
+        pte_size = PAGE_SIZE;
+        writing = (dsisr & DSISR_ISSTORE) != 0;
+        /* If writing != 0, then the HPTE must allow writing, if we get here */
+        write_ok = writing;
+        hva = gfn_to_hva_memslot(memslot, gfn);
+        npages = get_user_pages_fast(hva, 1, writing, pages);
+        if (npages < 1) {
+                /* Check if it's an I/O mapping */
+                down_read(&current->mm->mmap_sem);
+                vma = find_vma(current->mm, hva);
+                if (vma && vma->vm_start <= hva && hva + psize <= vma->vm_end &&
+                    (vma->vm_flags & VM_PFNMAP)) {
+                        pfn = vma->vm_pgoff +
+                                ((hva - vma->vm_start) >> PAGE_SHIFT);
+                        pte_size = psize;
+                        is_io = hpte_cache_bits(pgprot_val(vma->vm_page_prot));
+                        write_ok = vma->vm_flags & VM_WRITE;
+                }
+                up_read(&current->mm->mmap_sem);
+                if (!pfn)
+                        return -EFAULT;
+        } else {
+                page = pages[0];
+                if (PageHuge(page)) {
+                        page = compound_head(page);
+                        pte_size <<= compound_order(page);
+                }
+                /* if the guest wants write access, see if that is OK */
+                if (!writing && hpte_is_writable(r)) {
+                        pte_t *ptep, pte;
+
+                        /*
+                         * We need to protect against page table destruction
+                         * while looking up and updating the pte.
+                         */
+                        rcu_read_lock_sched();
+                        ptep = find_linux_pte_or_hugepte(current->mm->pgd,
+                                                         hva, NULL);
+                        if (ptep && pte_present(*ptep)) {
+                                pte = kvmppc_read_update_linux_pte(ptep, 1);
+                                if (pte_write(pte))
+                                        write_ok = 1;
+                        }
+                        rcu_read_unlock_sched();
+                }
+                pfn = page_to_pfn(page);
+        }
+
+        ret = -EFAULT;
+        if (psize > pte_size)
+                goto out_put;
+
+        /* Check WIMG vs. the actual page we're accessing */
+        if (!hpte_cache_flags_ok(r, is_io)) {
+                if (is_io)
+                        return -EFAULT;
+                /*
+                 * Allow guest to map emulated device memory as
+                 * uncacheable, but actually make it cacheable.
+                 */
+                r = (r & ~(HPTE_R_W|HPTE_R_I|HPTE_R_G)) | HPTE_R_M;
+        }
+
+        /* Set the HPTE to point to pfn */
+        r = (r & ~(HPTE_R_PP0 - pte_size)) | (pfn << PAGE_SHIFT);
+        if (hpte_is_writable(r) && !write_ok)
+                r = hpte_make_readonly(r);
+        ret = RESUME_GUEST;
+        preempt_disable();
+        while (!try_lock_hpte(hptep, HPTE_V_HVLOCK))
+                cpu_relax();
+        if ((hptep[0] & ~HPTE_V_HVLOCK) != hpte[0] || hptep[1] != hpte[1] ||
+            rev->guest_rpte != hpte[2])
+                /* HPTE has been changed under us; let the guest retry */
+                goto out_unlock;
+        hpte[0] = (hpte[0] & ~HPTE_V_ABSENT) | HPTE_V_VALID;
+
+        rmap = &memslot->rmap[gfn - memslot->base_gfn];
+        lock_rmap(rmap);
+
+        /* Check if we might have been invalidated; let the guest retry if so */
+        ret = RESUME_GUEST;
+        if (mmu_notifier_retry(vcpu, mmu_seq)) {
+                unlock_rmap(rmap);
+                goto out_unlock;
+        }
+
+        /* Only set R/C in real HPTE if set in both *rmap and guest_rpte */
+        rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
+        r &= rcbits | ~(HPTE_R_R | HPTE_R_C);
+
+        if (hptep[0] & HPTE_V_VALID) {
+                /* HPTE was previously valid, so we need to invalidate it */
+                unlock_rmap(rmap);
+                hptep[0] |= HPTE_V_ABSENT;
+                kvmppc_invalidate_hpte(kvm, hptep, index);
+                /* don't lose previous R and C bits */
+                r |= hptep[1] & (HPTE_R_R | HPTE_R_C);
+        } else {
+                kvmppc_add_revmap_chain(kvm, rev, rmap, index, 0);
+        }
+
+        hptep[1] = r;
+        eieio();
+        hptep[0] = hpte[0];
+        asm volatile("ptesync" : : : "memory");
+        preempt_enable();
+        if (page && hpte_is_writable(r))
+                SetPageDirty(page);
+
+ out_put:
+        if (page)
+                put_page(page);
+        return ret;
+
+ out_unlock:
+        hptep[0] &= ~HPTE_V_HVLOCK;
+        preempt_enable();
+        goto out_put;
+}
+
+static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
+                          int (*handler)(struct kvm *kvm, unsigned long *rmapp,
+                                         unsigned long gfn))
+{
+        int ret;
+        int retval = 0;
+        struct kvm_memslots *slots;
+        struct kvm_memory_slot *memslot;
+
+        slots = kvm_memslots(kvm);
+        kvm_for_each_memslot(memslot, slots) {
+                unsigned long start = memslot->userspace_addr;
+                unsigned long end;
+
+                end = start + (memslot->npages << PAGE_SHIFT);
+                if (hva >= start && hva < end) {
+                        gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
+
+                        ret = handler(kvm, &memslot->rmap[gfn_offset],
+                                      memslot->base_gfn + gfn_offset);
+                        retval |= ret;
+                }
+        }
+
+        return retval;
+}
+
+static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
+                           unsigned long gfn)
+{
+        struct revmap_entry *rev = kvm->arch.revmap;
+        unsigned long h, i, j;
+        unsigned long *hptep;
+        unsigned long ptel, psize, rcbits;
+
+        for (;;) {
+                lock_rmap(rmapp);
+                if (!(*rmapp & KVMPPC_RMAP_PRESENT)) {
+                        unlock_rmap(rmapp);
+                        break;
+                }
+
+                /*
+                 * To avoid an ABBA deadlock with the HPTE lock bit,
+                 * we can't spin on the HPTE lock while holding the
+                 * rmap chain lock.
+                 */
+                i = *rmapp & KVMPPC_RMAP_INDEX;
+                hptep = (unsigned long *) (kvm->arch.hpt_virt + (i << 4));
+                if (!try_lock_hpte(hptep, HPTE_V_HVLOCK)) {
+                        /* unlock rmap before spinning on the HPTE lock */
+                        unlock_rmap(rmapp);
+                        while (hptep[0] & HPTE_V_HVLOCK)
+                                cpu_relax();
+                        continue;
+                }
+                j = rev[i].forw;
+                if (j == i) {
+                        /* chain is now empty */
+                        *rmapp &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
+                } else {
+                        /* remove i from chain */
+                        h = rev[i].back;
+                        rev[h].forw = j;
+                        rev[j].back = h;
+                        rev[i].forw = rev[i].back = i;
+                        *rmapp = (*rmapp & ~KVMPPC_RMAP_INDEX) | j;
+                }
+
+                /* Now check and modify the HPTE */
+                ptel = rev[i].guest_rpte;
+                psize = hpte_page_size(hptep[0], ptel);
+                if ((hptep[0] & HPTE_V_VALID) &&
+                    hpte_rpn(ptel, psize) == gfn) {
+                        hptep[0] |= HPTE_V_ABSENT;
+                        kvmppc_invalidate_hpte(kvm, hptep, i);
+                        /* Harvest R and C */
+                        rcbits = hptep[1] & (HPTE_R_R | HPTE_R_C);
+                        *rmapp |= rcbits << KVMPPC_RMAP_RC_SHIFT;
+                        rev[i].guest_rpte = ptel | rcbits;
+                }
+                unlock_rmap(rmapp);
+                hptep[0] &= ~HPTE_V_HVLOCK;
+        }
+        return 0;
+}
+
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
+{
+        if (kvm->arch.using_mmu_notifiers)
+                kvm_handle_hva(kvm, hva, kvm_unmap_rmapp);
+        return 0;
+}
+
+static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
+                         unsigned long gfn)
+{
+        struct revmap_entry *rev = kvm->arch.revmap;
+        unsigned long head, i, j;
+        unsigned long *hptep;
+        int ret = 0;
+
+ retry:
+        lock_rmap(rmapp);
+        if (*rmapp & KVMPPC_RMAP_REFERENCED) {
+                *rmapp &= ~KVMPPC_RMAP_REFERENCED;
+                ret = 1;
+        }
+        if (!(*rmapp & KVMPPC_RMAP_PRESENT)) {
+                unlock_rmap(rmapp);
+                return ret;
+        }
+
+        i = head = *rmapp & KVMPPC_RMAP_INDEX;
+        do {
+                hptep = (unsigned long *) (kvm->arch.hpt_virt + (i << 4));
+                j = rev[i].forw;
+
+                /* If this HPTE isn't referenced, ignore it */
+                if (!(hptep[1] & HPTE_R_R))
+                        continue;
+
+                if (!try_lock_hpte(hptep, HPTE_V_HVLOCK)) {
+                        /* unlock rmap before spinning on the HPTE lock */
+                        unlock_rmap(rmapp);
+                        while (hptep[0] & HPTE_V_HVLOCK)
+                                cpu_relax();
+                        goto retry;
+                }
+
+                /* Now check and modify the HPTE */
+                if ((hptep[0] & HPTE_V_VALID) && (hptep[1] & HPTE_R_R)) {
+                        kvmppc_clear_ref_hpte(kvm, hptep, i);
+                        rev[i].guest_rpte |= HPTE_R_R;
+                        ret = 1;
+                }
+                hptep[0] &= ~HPTE_V_HVLOCK;
+        } while ((i = j) != head);
+
+        unlock_rmap(rmapp);
+        return ret;
+}
+
+int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        if (!kvm->arch.using_mmu_notifiers)
+                return 0;
+        return kvm_handle_hva(kvm, hva, kvm_age_rmapp);
+}
+
+static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
+                              unsigned long gfn)
+{
+        struct revmap_entry *rev = kvm->arch.revmap;
+        unsigned long head, i, j;
+        unsigned long *hp;
+        int ret = 1;
+
+        if (*rmapp & KVMPPC_RMAP_REFERENCED)
+                return 1;
+
+        lock_rmap(rmapp);
+        if (*rmapp & KVMPPC_RMAP_REFERENCED)
+                goto out;
+
+        if (*rmapp & KVMPPC_RMAP_PRESENT) {
+                i = head = *rmapp & KVMPPC_RMAP_INDEX;
+                do {
+                        hp = (unsigned long *)(kvm->arch.hpt_virt + (i << 4));
+                        j = rev[i].forw;
+                        if (hp[1] & HPTE_R_R)
+                                goto out;
+                } while ((i = j) != head);
+        }
+        ret = 0;
+
+ out:
+        unlock_rmap(rmapp);
+        return ret;
+}
+
+int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        if (!kvm->arch.using_mmu_notifiers)
+                return 0;
+        return kvm_handle_hva(kvm, hva, kvm_test_age_rmapp);
+}
+
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
 {
-        return -ENOENT;
+        if (!kvm->arch.using_mmu_notifiers)
+                return;
+        kvm_handle_hva(kvm, hva, kvm_unmap_rmapp);
+}
+
+static int kvm_test_clear_dirty(struct kvm *kvm, unsigned long *rmapp)
+{
+        struct revmap_entry *rev = kvm->arch.revmap;
+        unsigned long head, i, j;
+        unsigned long *hptep;
+        int ret = 0;
+
+ retry:
+        lock_rmap(rmapp);
+        if (*rmapp & KVMPPC_RMAP_CHANGED) {
+                *rmapp &= ~KVMPPC_RMAP_CHANGED;
+                ret = 1;
+        }
+        if (!(*rmapp & KVMPPC_RMAP_PRESENT)) {
+                unlock_rmap(rmapp);
+                return ret;
+        }
+
+        i = head = *rmapp & KVMPPC_RMAP_INDEX;
+        do {
+                hptep = (unsigned long *) (kvm->arch.hpt_virt + (i << 4));
+                j = rev[i].forw;
+
+                if (!(hptep[1] & HPTE_R_C))
+                        continue;
+
+                if (!try_lock_hpte(hptep, HPTE_V_HVLOCK)) {
+                        /* unlock rmap before spinning on the HPTE lock */
+                        unlock_rmap(rmapp);
+                        while (hptep[0] & HPTE_V_HVLOCK)
+                                cpu_relax();
+                        goto retry;
+                }
+
+                /* Now check and modify the HPTE */
+                if ((hptep[0] & HPTE_V_VALID) && (hptep[1] & HPTE_R_C)) {
+                        /* need to make it temporarily absent to clear C */
+                        hptep[0] |= HPTE_V_ABSENT;
+                        kvmppc_invalidate_hpte(kvm, hptep, i);
+                        hptep[1] &= ~HPTE_R_C;
+                        eieio();
+                        hptep[0] = (hptep[0] & ~HPTE_V_ABSENT) | HPTE_V_VALID;
+                        rev[i].guest_rpte |= HPTE_R_C;
+                        ret = 1;
+                }
+                hptep[0] &= ~HPTE_V_HVLOCK;
+        } while ((i = j) != head);
+
+        unlock_rmap(rmapp);
+        return ret;
+}
+
+long kvmppc_hv_get_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
+{
+        unsigned long i;
+        unsigned long *rmapp, *map;
+
+        preempt_disable();
+        rmapp = memslot->rmap;
+        map = memslot->dirty_bitmap;
+        for (i = 0; i < memslot->npages; ++i) {
+                if (kvm_test_clear_dirty(kvm, rmapp))
+                        __set_bit_le(i, map);
+                ++rmapp;
+        }
+        preempt_enable();
+        return 0;
+}
+
+void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
+                            unsigned long *nb_ret)
+{
+        struct kvm_memory_slot *memslot;
+        unsigned long gfn = gpa >> PAGE_SHIFT;
+        struct page *page, *pages[1];
+        int npages;
+        unsigned long hva, psize, offset;
+        unsigned long pa;
+        unsigned long *physp;
+
+        memslot = gfn_to_memslot(kvm, gfn);
+        if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID))
+                return NULL;
+        if (!kvm->arch.using_mmu_notifiers) {
+                physp = kvm->arch.slot_phys[memslot->id];
+                if (!physp)
+                        return NULL;
+                physp += gfn - memslot->base_gfn;
+                pa = *physp;
+                if (!pa) {
+                        if (kvmppc_get_guest_page(kvm, gfn, memslot,
+                                                  PAGE_SIZE) < 0)
+                                return NULL;
+                        pa = *physp;
+                }
+                page = pfn_to_page(pa >> PAGE_SHIFT);
+        } else {
+                hva = gfn_to_hva_memslot(memslot, gfn);
+                npages = get_user_pages_fast(hva, 1, 1, pages);
+                if (npages < 1)
+                        return NULL;
+                page = pages[0];
+        }
+        psize = PAGE_SIZE;
+        if (PageHuge(page)) {
+                page = compound_head(page);
+                psize <<= compound_order(page);
+        }
+        if (!kvm->arch.using_mmu_notifiers)
+                get_page(page);
+        offset = gpa & (psize - 1);
+        if (nb_ret)
+                *nb_ret = psize - offset;
+        return page_address(page) + offset;
+}
+
+void kvmppc_unpin_guest_page(struct kvm *kvm, void *va)
+{
+        struct page *page = virt_to_page(va);
+
+        page = compound_head(page);
+        put_page(page);
 }
 
 void kvmppc_mmu_book3s_hv_init(struct kvm_vcpu *vcpu)
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 0c9dc62532d..f1950d13182 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -230,9 +230,12 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
                         r = kvmppc_st(vcpu, &addr, 32, zeros, true);
                         if ((r == -ENOENT) || (r == -EPERM)) {
+                                struct kvmppc_book3s_shadow_vcpu *svcpu;
+
+                                svcpu = svcpu_get(vcpu);
                                 *advance = 0;
                                 vcpu->arch.shared->dar = vaddr;
-                                to_svcpu(vcpu)->fault_dar = vaddr;
+                                svcpu->fault_dar = vaddr;
 
                                 dsisr = DSISR_ISSTORE;
                                 if (r == -ENOENT)
@@ -241,7 +244,8 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                         dsisr |= DSISR_PROTFAULT;
 
                                 vcpu->arch.shared->dsisr = dsisr;
-                                to_svcpu(vcpu)->fault_dsisr = dsisr;
+                                svcpu->fault_dsisr = dsisr;
+                                svcpu_put(svcpu);
 
                                 kvmppc_book3s_queue_irqprio(vcpu,
                                         BOOK3S_INTERRUPT_DATA_STORAGE);
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index ab4267760b7..01294a5099d 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -49,22 +49,14 @@
 #include <linux/gfp.h>
 #include <linux/vmalloc.h>
 #include <linux/highmem.h>
-
-/*
- * For now, limit memory to 64GB and require it to be large pages.
- * This value is chosen because it makes the ram_pginfo array be
- * 64kB in size, which is about as large as we want to be trying
- * to allocate with kmalloc.
- */
-#define MAX_MEM_ORDER           36
-
-#define LARGE_PAGE_ORDER        24      /* 16MB pages */
+#include <linux/hugetlb.h>
 
 /* #define EXIT_DEBUG */
 /* #define EXIT_DEBUG_SIMPLE */
 /* #define EXIT_DEBUG_INT */
 
 static void kvmppc_end_cede(struct kvm_vcpu *vcpu);
+static int kvmppc_hv_setup_rma(struct kvm_vcpu *vcpu);
 
 void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
@@ -147,10 +139,10 @@ static unsigned long do_h_register_vpa(struct kvm_vcpu *vcpu,
                                        unsigned long vcpuid, unsigned long vpa)
 {
         struct kvm *kvm = vcpu->kvm;
-        unsigned long pg_index, ra, len;
-        unsigned long pg_offset;
+        unsigned long len, nb;
         void *va;
         struct kvm_vcpu *tvcpu;
+        int err = H_PARAMETER;
 
         tvcpu = kvmppc_find_vcpu(kvm, vcpuid);
         if (!tvcpu)
@@ -163,45 +155,41 @@ static unsigned long do_h_register_vpa(struct kvm_vcpu *vcpu,
         if (flags < 4) {
                 if (vpa & 0x7f)
                         return H_PARAMETER;
+                if (flags >= 2 && !tvcpu->arch.vpa)
+                        return H_RESOURCE;
                 /* registering new area; convert logical addr to real */
-                pg_index = vpa >> kvm->arch.ram_porder;
-                pg_offset = vpa & (kvm->arch.ram_psize - 1);
-                if (pg_index >= kvm->arch.ram_npages)
+                va = kvmppc_pin_guest_page(kvm, vpa, &nb);
+                if (va == NULL)
                         return H_PARAMETER;
-                if (kvm->arch.ram_pginfo[pg_index].pfn == 0)
-                        return H_PARAMETER;
-                ra = kvm->arch.ram_pginfo[pg_index].pfn << PAGE_SHIFT;
-                ra |= pg_offset;
-                va = __va(ra);
                 if (flags <= 1)
                         len = *(unsigned short *)(va + 4);
                 else
                         len = *(unsigned int *)(va + 4);
-                if (pg_offset + len > kvm->arch.ram_psize)
-                        return H_PARAMETER;
+                if (len > nb)
+                        goto out_unpin;
                 switch (flags) {
                 case 1:         /* register VPA */
                         if (len < 640)
-                                return H_PARAMETER;
+                                goto out_unpin;
+                        if (tvcpu->arch.vpa)
+                                kvmppc_unpin_guest_page(kvm, vcpu->arch.vpa);
                         tvcpu->arch.vpa = va;
                         init_vpa(vcpu, va);
                         break;
                 case 2:         /* register DTL */
                         if (len < 48)
-                                return H_PARAMETER;
-                        if (!tvcpu->arch.vpa)
-                                return H_RESOURCE;
+                                goto out_unpin;
                         len -= len % 48;
+                        if (tvcpu->arch.dtl)
+                                kvmppc_unpin_guest_page(kvm, vcpu->arch.dtl);
                         tvcpu->arch.dtl = va;
                         tvcpu->arch.dtl_end = va + len;
                         break;
                 case 3:         /* register SLB shadow buffer */
-                        if (len < 8)
-                                return H_PARAMETER;
-                        if (!tvcpu->arch.vpa)
-                                return H_RESOURCE;
-                        tvcpu->arch.slb_shadow = va;
-                        len = (len - 16) / 16;
+                        if (len < 16)
+                                goto out_unpin;
+                        if (tvcpu->arch.slb_shadow)
+                                kvmppc_unpin_guest_page(kvm, vcpu->arch.slb_shadow);
                         tvcpu->arch.slb_shadow = va;
                         break;
                 }
@@ -210,17 +198,30 @@ static unsigned long do_h_register_vpa(struct kvm_vcpu *vcpu,
                 case 5:         /* unregister VPA */
                         if (tvcpu->arch.slb_shadow || tvcpu->arch.dtl)
                                 return H_RESOURCE;
+                        if (!tvcpu->arch.vpa)
+                                break;
+                        kvmppc_unpin_guest_page(kvm, tvcpu->arch.vpa);
                         tvcpu->arch.vpa = NULL;
                         break;
                 case 6:         /* unregister DTL */
+                        if (!tvcpu->arch.dtl)
+                                break;
+                        kvmppc_unpin_guest_page(kvm, tvcpu->arch.dtl);
                         tvcpu->arch.dtl = NULL;
                         break;
                 case 7:         /* unregister SLB shadow buffer */
+                        if (!tvcpu->arch.slb_shadow)
+                                break;
+                        kvmppc_unpin_guest_page(kvm, tvcpu->arch.slb_shadow);
                         tvcpu->arch.slb_shadow = NULL;
                         break;
                 }
         }
         return H_SUCCESS;
+
+ out_unpin:
+        kvmppc_unpin_guest_page(kvm, va);
+        return err;
 }
 
 int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
@@ -230,6 +231,12 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
         struct kvm_vcpu *tvcpu;
 
         switch (req) {
+        case H_ENTER:
+                ret = kvmppc_virtmode_h_enter(vcpu, kvmppc_get_gpr(vcpu, 4),
+                                              kvmppc_get_gpr(vcpu, 5),
+                                              kvmppc_get_gpr(vcpu, 6),
+                                              kvmppc_get_gpr(vcpu, 7));
+                break;
         case H_CEDE:
                 break;
         case H_PROD:
@@ -319,20 +326,19 @@ static int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 break;
         }
         /*
-         * We get these next two if the guest does a bad real-mode access,
-         * as we have enabled VRMA (virtualized real mode area) mode in the
-         * LPCR.  We just generate an appropriate DSI/ISI to the guest.
+         * We get these next two if the guest accesses a page which it thinks
+         * it has mapped but which is not actually present, either because
+         * it is for an emulated I/O device or because the corresonding
+         * host page has been paged out.  Any other HDSI/HISI interrupts
+         * have been handled already.
          */
         case BOOK3S_INTERRUPT_H_DATA_STORAGE:
-                vcpu->arch.shregs.dsisr = vcpu->arch.fault_dsisr;
-                vcpu->arch.shregs.dar = vcpu->arch.fault_dar;
-                kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE, 0);
-                r = RESUME_GUEST;
+                r = kvmppc_book3s_hv_page_fault(run, vcpu,
+                                vcpu->arch.fault_dar, vcpu->arch.fault_dsisr);
                 break;
         case BOOK3S_INTERRUPT_H_INST_STORAGE:
-                kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_INST_STORAGE,
-                                        0x08000000);
-                r = RESUME_GUEST;
+                r = kvmppc_book3s_hv_page_fault(run, vcpu,
+                                kvmppc_get_pc(vcpu), 0);
                 break;
         /*
          * This occurs if the guest executes an illegal instruction.
@@ -392,6 +398,42 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         return 0;
 }
 
+int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        int r = -EINVAL;
+
+        switch (reg->id) {
+        case KVM_REG_PPC_HIOR:
+                r = put_user(0, (u64 __user *)reg->addr);
+                break;
+        default:
+                break;
+        }
+
+        return r;
+}
+
+int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        int r = -EINVAL;
+
+        switch (reg->id) {
+        case KVM_REG_PPC_HIOR:
+        {
+                u64 hior;
+                /* Only allow this to be set to zero */
+                r = get_user(hior, (u64 __user *)reg->addr);
+                if (!r && (hior != 0))
+                        r = -EINVAL;
+                break;
+        }
+        default:
+                break;
+        }
+
+        return r;
+}
+
 int kvmppc_core_check_processor_compat(void)
 {
         if (cpu_has_feature(CPU_FTR_HVMODE))
@@ -411,7 +453,7 @@ struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
                 goto out;
 
         err = -ENOMEM;
-        vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
+        vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
         if (!vcpu)
                 goto out;
 
@@ -463,15 +505,21 @@ struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
         return vcpu;
 
 free_vcpu:
-        kfree(vcpu);
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
 out:
         return ERR_PTR(err);
 }
 
 void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
 {
+        if (vcpu->arch.dtl)
+                kvmppc_unpin_guest_page(vcpu->kvm, vcpu->arch.dtl);
+        if (vcpu->arch.slb_shadow)
+                kvmppc_unpin_guest_page(vcpu->kvm, vcpu->arch.slb_shadow);
+        if (vcpu->arch.vpa)
+                kvmppc_unpin_guest_page(vcpu->kvm, vcpu->arch.vpa);
         kvm_vcpu_uninit(vcpu);
-        kfree(vcpu);
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
 }
 
 static void kvmppc_set_timer(struct kvm_vcpu *vcpu)
@@ -482,7 +530,7 @@ static void kvmppc_set_timer(struct kvm_vcpu *vcpu)
         if (now > vcpu->arch.dec_expires) {
                 /* decrementer has already gone negative */
                 kvmppc_core_queue_dec(vcpu);
-                kvmppc_core_deliver_interrupts(vcpu);
+                kvmppc_core_prepare_to_enter(vcpu);
                 return;
         }
         dec_nsec = (vcpu->arch.dec_expires - now) * NSEC_PER_SEC
@@ -797,7 +845,7 @@ static int kvmppc_run_vcpu(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 
                 list_for_each_entry_safe(v, vn, &vc->runnable_threads,
                                          arch.run_list) {
-                        kvmppc_core_deliver_interrupts(v);
+                        kvmppc_core_prepare_to_enter(v);
                         if (signal_pending(v->arch.run_task)) {
                                 kvmppc_remove_runnable(vc, v);
                                 v->stat.signal_exits++;
@@ -836,20 +884,26 @@ int kvmppc_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 return -EINVAL;
         }
 
+        kvmppc_core_prepare_to_enter(vcpu);
+
         /* No need to go into the guest when all we'll do is come back out */
         if (signal_pending(current)) {
                 run->exit_reason = KVM_EXIT_INTR;
                 return -EINTR;
         }
 
-        /* On PPC970, check that we have an RMA region */
-        if (!vcpu->kvm->arch.rma && cpu_has_feature(CPU_FTR_ARCH_201))
-                return -EPERM;
+        /* On the first time here, set up VRMA or RMA */
+        if (!vcpu->kvm->arch.rma_setup_done) {
+                r = kvmppc_hv_setup_rma(vcpu);
+                if (r)
+                        return r;
+        }
 
         flush_fp_to_thread(current);
         flush_altivec_to_thread(current);
         flush_vsx_to_thread(current);
         vcpu->arch.wqp = &vcpu->arch.vcore->wq;
+        vcpu->arch.pgdir = current->mm->pgd;
 
         do {
                 r = kvmppc_run_vcpu(run, vcpu);
@@ -857,7 +911,7 @@ int kvmppc_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 if (run->exit_reason == KVM_EXIT_PAPR_HCALL &&
                     !(vcpu->arch.shregs.msr & MSR_PR)) {
                         r = kvmppc_pseries_do_hcall(vcpu);
-                        kvmppc_core_deliver_interrupts(vcpu);
+                        kvmppc_core_prepare_to_enter(vcpu);
                 }
         } while (r == RESUME_GUEST);
         return r;
@@ -1001,7 +1055,7 @@ static inline int lpcr_rmls(unsigned long rma_size)
 
 static int kvm_rma_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 {
-        struct kvmppc_rma_info *ri = vma->vm_file->private_data;
+        struct kvmppc_linear_info *ri = vma->vm_file->private_data;
         struct page *page;
 
         if (vmf->pgoff >= ri->npages)
@@ -1026,7 +1080,7 @@ static int kvm_rma_mmap(struct file *file, struct vm_area_struct *vma)
 
 static int kvm_rma_release(struct inode *inode, struct file *filp)
 {
-        struct kvmppc_rma_info *ri = filp->private_data;
+        struct kvmppc_linear_info *ri = filp->private_data;
 
         kvm_release_rma(ri);
         return 0;
@@ -1039,7 +1093,7 @@ static struct file_operations kvm_rma_fops = {
 
 long kvm_vm_ioctl_allocate_rma(struct kvm *kvm, struct kvm_allocate_rma *ret)
 {
-        struct kvmppc_rma_info *ri;
+        struct kvmppc_linear_info *ri;
         long fd;
 
         ri = kvm_alloc_rma();
@@ -1054,89 +1108,189 @@ long kvm_vm_ioctl_allocate_rma(struct kvm *kvm, struct kvm_allocate_rma *ret)
         return fd;
 }
 
-static struct page *hva_to_page(unsigned long addr)
+/*
+ * Get (and clear) the dirty memory log for a memory slot.
+ */
+int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 {
-        struct page *page[1];
-        int npages;
+        struct kvm_memory_slot *memslot;
+        int r;
+        unsigned long n;
 
-        might_sleep();
+        mutex_lock(&kvm->slots_lock);
 
-        npages = get_user_pages_fast(addr, 1, 1, page);
+        r = -EINVAL;
+        if (log->slot >= KVM_MEMORY_SLOTS)
+                goto out;
 
-        if (unlikely(npages != 1))
-                return 0;
+        memslot = id_to_memslot(kvm->memslots, log->slot);
+        r = -ENOENT;
+        if (!memslot->dirty_bitmap)
+                goto out;
+
+        n = kvm_dirty_bitmap_bytes(memslot);
+        memset(memslot->dirty_bitmap, 0, n);
+
+        r = kvmppc_hv_get_dirty_log(kvm, memslot);
+        if (r)
+                goto out;
 
-        return page[0];
+        r = -EFAULT;
+        if (copy_to_user(log->dirty_bitmap, memslot->dirty_bitmap, n))
+                goto out;
+
+        r = 0;
+out:
+        mutex_unlock(&kvm->slots_lock);
+        return r;
+}
+
+static unsigned long slb_pgsize_encoding(unsigned long psize)
+{
+        unsigned long senc = 0;
+
+        if (psize > 0x1000) {
+                senc = SLB_VSID_L;
+                if (psize == 0x10000)
+                        senc |= SLB_VSID_LP_01;
+        }
+        return senc;
 }
 
 int kvmppc_core_prepare_memory_region(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem)
 {
-        unsigned long psize, porder;
-        unsigned long i, npages, totalpages;
-        unsigned long pg_ix;
-        struct kvmppc_pginfo *pginfo;
-        unsigned long hva;
-        struct kvmppc_rma_info *ri = NULL;
+        unsigned long npages;
+        unsigned long *phys;
+
+        /* Allocate a slot_phys array */
+        phys = kvm->arch.slot_phys[mem->slot];
+        if (!kvm->arch.using_mmu_notifiers && !phys) {
+                npages = mem->memory_size >> PAGE_SHIFT;
+                phys = vzalloc(npages * sizeof(unsigned long));
+                if (!phys)
+                        return -ENOMEM;
+                kvm->arch.slot_phys[mem->slot] = phys;
+                kvm->arch.slot_npages[mem->slot] = npages;
+        }
+
+        return 0;
+}
+
+static void unpin_slot(struct kvm *kvm, int slot_id)
+{
+        unsigned long *physp;
+        unsigned long j, npages, pfn;
         struct page *page;
 
-        /* For now, only allow 16MB pages */
-        porder = LARGE_PAGE_ORDER;
-        psize = 1ul << porder;
-        if ((mem->memory_size & (psize - 1)) ||
-            (mem->guest_phys_addr & (psize - 1))) {
-                pr_err("bad memory_size=%llx @ %llx\n",
-                       mem->memory_size, mem->guest_phys_addr);
-                return -EINVAL;
+        physp = kvm->arch.slot_phys[slot_id];
+        npages = kvm->arch.slot_npages[slot_id];
+        if (physp) {
+                spin_lock(&kvm->arch.slot_phys_lock);
+                for (j = 0; j < npages; j++) {
+                        if (!(physp[j] & KVMPPC_GOT_PAGE))
+                                continue;
+                        pfn = physp[j] >> PAGE_SHIFT;
+                        page = pfn_to_page(pfn);
+                        if (PageHuge(page))
+                                page = compound_head(page);
+                        SetPageDirty(page);
+                        put_page(page);
+                }
+                kvm->arch.slot_phys[slot_id] = NULL;
+                spin_unlock(&kvm->arch.slot_phys_lock);
+                vfree(physp);
         }
+}
 
-        npages = mem->memory_size >> porder;
-        totalpages = (mem->guest_phys_addr + mem->memory_size) >> porder;
+void kvmppc_core_commit_memory_region(struct kvm *kvm,
+                                struct kvm_userspace_memory_region *mem)
+{
+}
 
-        /* More memory than we have space to track? */
-        if (totalpages > (1ul << (MAX_MEM_ORDER - LARGE_PAGE_ORDER)))
-                return -EINVAL;
+static int kvmppc_hv_setup_rma(struct kvm_vcpu *vcpu)
+{
+        int err = 0;
+        struct kvm *kvm = vcpu->kvm;
+        struct kvmppc_linear_info *ri = NULL;
+        unsigned long hva;
+        struct kvm_memory_slot *memslot;
+        struct vm_area_struct *vma;
+        unsigned long lpcr, senc;
+        unsigned long psize, porder;
+        unsigned long rma_size;
+        unsigned long rmls;
+        unsigned long *physp;
+        unsigned long i, npages;
 
-        /* Do we already have an RMA registered? */
-        if (mem->guest_phys_addr == 0 && kvm->arch.rma)
-                return -EINVAL;
+        mutex_lock(&kvm->lock);
+        if (kvm->arch.rma_setup_done)
+                goto out;       /* another vcpu beat us to it */
 
-        if (totalpages > kvm->arch.ram_npages)
-                kvm->arch.ram_npages = totalpages;
+        /* Look up the memslot for guest physical address 0 */
+        memslot = gfn_to_memslot(kvm, 0);
+
+        /* We must have some memory at 0 by now */
+        err = -EINVAL;
+        if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID))
+                goto out;
+
+        /* Look up the VMA for the start of this memory slot */
+        hva = memslot->userspace_addr;
+        down_read(&current->mm->mmap_sem);
+        vma = find_vma(current->mm, hva);
+        if (!vma || vma->vm_start > hva || (vma->vm_flags & VM_IO))
+                goto up_out;
+
+        psize = vma_kernel_pagesize(vma);
+        porder = __ilog2(psize);
 
         /* Is this one of our preallocated RMAs? */
-        if (mem->guest_phys_addr == 0) {
-                struct vm_area_struct *vma;
-
-                down_read(&current->mm->mmap_sem);
-                vma = find_vma(current->mm, mem->userspace_addr);
-                if (vma && vma->vm_file &&
-                    vma->vm_file->f_op == &kvm_rma_fops &&
-                    mem->userspace_addr == vma->vm_start)
-                        ri = vma->vm_file->private_data;
-                up_read(&current->mm->mmap_sem);
-                if (!ri && cpu_has_feature(CPU_FTR_ARCH_201)) {
-                        pr_err("CPU requires an RMO\n");
-                        return -EINVAL;
+        if (vma->vm_file && vma->vm_file->f_op == &kvm_rma_fops &&
+            hva == vma->vm_start)
+                ri = vma->vm_file->private_data;
+
+        up_read(&current->mm->mmap_sem);
+
+        if (!ri) {
+                /* On POWER7, use VRMA; on PPC970, give up */
+                err = -EPERM;
+                if (cpu_has_feature(CPU_FTR_ARCH_201)) {
+                        pr_err("KVM: CPU requires an RMO\n");
+                        goto out;
                 }
-        }
 
-        if (ri) {
-                unsigned long rma_size;
-                unsigned long lpcr;
-                long rmls;
+                /* We can handle 4k, 64k or 16M pages in the VRMA */
+                err = -EINVAL;
+                if (!(psize == 0x1000 || psize == 0x10000 ||
+                      psize == 0x1000000))
+                        goto out;
+
+                /* Update VRMASD field in the LPCR */
+                senc = slb_pgsize_encoding(psize);
+                kvm->arch.vrma_slb_v = senc | SLB_VSID_B_1T |
+                        (VRMA_VSID << SLB_VSID_SHIFT_1T);
+                lpcr = kvm->arch.lpcr & ~LPCR_VRMASD;
+                lpcr |= senc << (LPCR_VRMASD_SH - 4);
+                kvm->arch.lpcr = lpcr;
 
-                rma_size = ri->npages << PAGE_SHIFT;
-                if (rma_size > mem->memory_size)
-                        rma_size = mem->memory_size;
+                /* Create HPTEs in the hash page table for the VRMA */
+                kvmppc_map_vrma(vcpu, memslot, porder);
+
+        } else {
+                /* Set up to use an RMO region */
+                rma_size = ri->npages;
+                if (rma_size > memslot->npages)
+                        rma_size = memslot->npages;
+                rma_size <<= PAGE_SHIFT;
                 rmls = lpcr_rmls(rma_size);
+                err = -EINVAL;
                 if (rmls < 0) {
-                        pr_err("Can't use RMA of 0x%lx bytes\n", rma_size);
-                        return -EINVAL;
+                        pr_err("KVM: Can't use RMA of 0x%lx bytes\n", rma_size);
+                        goto out;
                 }
                 atomic_inc(&ri->use_count);
                 kvm->arch.rma = ri;
-                kvm->arch.n_rma_pages = rma_size >> porder;
 
                 /* Update LPCR and RMOR */
                 lpcr = kvm->arch.lpcr;
@@ -1156,53 +1310,35 @@ int kvmppc_core_prepare_memory_region(struct kvm *kvm,
                         kvm->arch.rmor = kvm->arch.rma->base_pfn << PAGE_SHIFT;
                 }
                 kvm->arch.lpcr = lpcr;
-                pr_info("Using RMO at %lx size %lx (LPCR = %lx)\n",
+                pr_info("KVM: Using RMO at %lx size %lx (LPCR = %lx)\n",
                         ri->base_pfn << PAGE_SHIFT, rma_size, lpcr);
-        }
 
-        pg_ix = mem->guest_phys_addr >> porder;
-        pginfo = kvm->arch.ram_pginfo + pg_ix;
-        for (i = 0; i < npages; ++i, ++pg_ix) {
-                if (ri && pg_ix < kvm->arch.n_rma_pages) {
-                        pginfo[i].pfn = ri->base_pfn +
-                                (pg_ix << (porder - PAGE_SHIFT));
-                        continue;
-                }
-                hva = mem->userspace_addr + (i << porder);
-                page = hva_to_page(hva);
-                if (!page) {
-                        pr_err("oops, no pfn for hva %lx\n", hva);
-                        goto err;
-                }
-                /* Check it's a 16MB page */
-                if (!PageHead(page) ||
-                    compound_order(page) != (LARGE_PAGE_ORDER - PAGE_SHIFT)) {
-                        pr_err("page at %lx isn't 16MB (o=%d)\n",
-                               hva, compound_order(page));
-                        goto err;
-                }
-                pginfo[i].pfn = page_to_pfn(page);
+                /* Initialize phys addrs of pages in RMO */
+                npages = ri->npages;
+                porder = __ilog2(npages);
+                physp = kvm->arch.slot_phys[memslot->id];
+                spin_lock(&kvm->arch.slot_phys_lock);
+                for (i = 0; i < npages; ++i)
+                        physp[i] = ((ri->base_pfn + i) << PAGE_SHIFT) + porder;
+                spin_unlock(&kvm->arch.slot_phys_lock);
         }
 
-        return 0;
-
- err:
-        return -EINVAL;
-}
+        /* Order updates to kvm->arch.lpcr etc. vs. rma_setup_done */
+        smp_wmb();
+        kvm->arch.rma_setup_done = 1;
+        err = 0;
+ out:
+        mutex_unlock(&kvm->lock);
+        return err;
 
-void kvmppc_core_commit_memory_region(struct kvm *kvm,
-                                struct kvm_userspace_memory_region *mem)
-{
-        if (mem->guest_phys_addr == 0 && mem->memory_size != 0 &&
-            !kvm->arch.rma)
-                kvmppc_map_vrma(kvm, mem);
+ up_out:
+        up_read(&current->mm->mmap_sem);
+        goto out;
 }
 
 int kvmppc_core_init_vm(struct kvm *kvm)
 {
         long r;
-        unsigned long npages = 1ul << (MAX_MEM_ORDER - LARGE_PAGE_ORDER);
-        long err = -ENOMEM;
         unsigned long lpcr;
 
         /* Allocate hashed page table */
@@ -1212,19 +1348,7 @@ int kvmppc_core_init_vm(struct kvm *kvm)
 
         INIT_LIST_HEAD(&kvm->arch.spapr_tce_tables);
 
-        kvm->arch.ram_pginfo = kzalloc(npages * sizeof(struct kvmppc_pginfo),
-                                       GFP_KERNEL);
-        if (!kvm->arch.ram_pginfo) {
-                pr_err("kvmppc_core_init_vm: couldn't alloc %lu bytes\n",
-                       npages * sizeof(struct kvmppc_pginfo));
-                goto out_free;
-        }
-
-        kvm->arch.ram_npages = 0;
-        kvm->arch.ram_psize = 1ul << LARGE_PAGE_ORDER;
-        kvm->arch.ram_porder = LARGE_PAGE_ORDER;
         kvm->arch.rma = NULL;
-        kvm->arch.n_rma_pages = 0;
 
         kvm->arch.host_sdr1 = mfspr(SPRN_SDR1);
 
@@ -1242,30 +1366,25 @@ int kvmppc_core_init_vm(struct kvm *kvm)
                 kvm->arch.host_lpcr = lpcr = mfspr(SPRN_LPCR);
                 lpcr &= LPCR_PECE | LPCR_LPES;
                 lpcr |= (4UL << LPCR_DPFD_SH) | LPCR_HDICE |
-                        LPCR_VPM0 | LPCR_VRMA_L;
+                        LPCR_VPM0 | LPCR_VPM1;
+                kvm->arch.vrma_slb_v = SLB_VSID_B_1T |
+                        (VRMA_VSID << SLB_VSID_SHIFT_1T);
         }
         kvm->arch.lpcr = lpcr;
 
+        kvm->arch.using_mmu_notifiers = !!cpu_has_feature(CPU_FTR_ARCH_206);
+        spin_lock_init(&kvm->arch.slot_phys_lock);
         return 0;
-
- out_free:
-        kvmppc_free_hpt(kvm);
-        return err;
 }
 
 void kvmppc_core_destroy_vm(struct kvm *kvm)
 {
-        struct kvmppc_pginfo *pginfo;
         unsigned long i;
 
-        if (kvm->arch.ram_pginfo) {
-                pginfo = kvm->arch.ram_pginfo;
-                kvm->arch.ram_pginfo = NULL;
-                for (i = kvm->arch.n_rma_pages; i < kvm->arch.ram_npages; ++i)
-                        if (pginfo[i].pfn)
-                                put_page(pfn_to_page(pginfo[i].pfn));
-                kfree(pginfo);
-        }
+        if (!kvm->arch.using_mmu_notifiers)
+                for (i = 0; i < KVM_MEM_SLOTS_NUM; i++)
+                        unpin_slot(kvm, i);
+
         if (kvm->arch.rma) {
                 kvm_release_rma(kvm->arch.rma);
                 kvm->arch.rma = NULL;
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index a795a13f4a7..bed1279aa6a 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -18,6 +18,15 @@
 #include <asm/kvm_ppc.h>
 #include <asm/kvm_book3s.h>
 
+#define KVM_LINEAR_RMA          0
+#define KVM_LINEAR_HPT          1
+
+static void __init kvm_linear_init_one(ulong size, int count, int type);
+static struct kvmppc_linear_info *kvm_alloc_linear(int type);
+static void kvm_release_linear(struct kvmppc_linear_info *ri);
+
+/*************** RMA *************/
+
 /*
  * This maintains a list of RMAs (real mode areas) for KVM guests to use.
  * Each RMA has to be physically contiguous and of a size that the
@@ -29,32 +38,6 @@
 static unsigned long kvm_rma_size = 64 << 20;   /* 64MB */
 static unsigned long kvm_rma_count;
 
-static int __init early_parse_rma_size(char *p)
-{
-        if (!p)
-                return 1;
-
-        kvm_rma_size = memparse(p, &p);
-
-        return 0;
-}
-early_param("kvm_rma_size", early_parse_rma_size);
-
-static int __init early_parse_rma_count(char *p)
-{
-        if (!p)
-                return 1;
-
-        kvm_rma_count = simple_strtoul(p, NULL, 0);
-
-        return 0;
-}
-early_param("kvm_rma_count", early_parse_rma_count);
-
-static struct kvmppc_rma_info *rma_info;
-static LIST_HEAD(free_rmas);
-static DEFINE_SPINLOCK(rma_lock);
-
 /* Work out RMLS (real mode limit selector) field value for a given RMA size.
    Assumes POWER7 or PPC970. */
 static inline int lpcr_rmls(unsigned long rma_size)
@@ -81,45 +64,106 @@ static inline int lpcr_rmls(unsigned long rma_size)
         }
 }
 
+static int __init early_parse_rma_size(char *p)
+{
+        if (!p)
+                return 1;
+
+        kvm_rma_size = memparse(p, &p);
+
+        return 0;
+}
+early_param("kvm_rma_size", early_parse_rma_size);
+
+static int __init early_parse_rma_count(char *p)
+{
+        if (!p)
+                return 1;
+
+        kvm_rma_count = simple_strtoul(p, NULL, 0);
+
+        return 0;
+}
+early_param("kvm_rma_count", early_parse_rma_count);
+
+struct kvmppc_linear_info *kvm_alloc_rma(void)
+{
+        return kvm_alloc_linear(KVM_LINEAR_RMA);
+}
+EXPORT_SYMBOL_GPL(kvm_alloc_rma);
+
+void kvm_release_rma(struct kvmppc_linear_info *ri)
+{
+        kvm_release_linear(ri);
+}
+EXPORT_SYMBOL_GPL(kvm_release_rma);
+
+/*************** HPT *************/
+
 /*
- * Called at boot time while the bootmem allocator is active,
- * to allocate contiguous physical memory for the real memory
- * areas for guests.
+ * This maintains a list of big linear HPT tables that contain the GVA->HPA
+ * memory mappings. If we don't reserve those early on, we might not be able
+ * to get a big (usually 16MB) linear memory region from the kernel anymore.
  */
-void __init kvm_rma_init(void)
+
+static unsigned long kvm_hpt_count;
+
+static int __init early_parse_hpt_count(char *p)
+{
+        if (!p)
+                return 1;
+
+        kvm_hpt_count = simple_strtoul(p, NULL, 0);
+
+        return 0;
+}
+early_param("kvm_hpt_count", early_parse_hpt_count);
+
+struct kvmppc_linear_info *kvm_alloc_hpt(void)
+{
+        return kvm_alloc_linear(KVM_LINEAR_HPT);
+}
+EXPORT_SYMBOL_GPL(kvm_alloc_hpt);
+
+void kvm_release_hpt(struct kvmppc_linear_info *li)
+{
+        kvm_release_linear(li);
+}
+EXPORT_SYMBOL_GPL(kvm_release_hpt);
+
+/*************** generic *************/
+
+static LIST_HEAD(free_linears);
+static DEFINE_SPINLOCK(linear_lock);
+
+static void __init kvm_linear_init_one(ulong size, int count, int type)
 {
         unsigned long i;
         unsigned long j, npages;
-        void *rma;
+        void *linear;
         struct page *pg;
+        const char *typestr;
+        struct kvmppc_linear_info *linear_info;
 
-        /* Only do this on PPC970 in HV mode */
-        if (!cpu_has_feature(CPU_FTR_HVMODE) ||
-            !cpu_has_feature(CPU_FTR_ARCH_201))
-                return;
-
-        if (!kvm_rma_size || !kvm_rma_count)
+        if (!count)
                 return;
 
-        /* Check that the requested size is one supported in hardware */
-        if (lpcr_rmls(kvm_rma_size) < 0) {
-                pr_err("RMA size of 0x%lx not supported\n", kvm_rma_size);
-                return;
-        }
-
-        npages = kvm_rma_size >> PAGE_SHIFT;
-        rma_info = alloc_bootmem(kvm_rma_count * sizeof(struct kvmppc_rma_info));
-        for (i = 0; i < kvm_rma_count; ++i) {
-                rma = alloc_bootmem_align(kvm_rma_size, kvm_rma_size);
-                pr_info("Allocated KVM RMA at %p (%ld MB)\n", rma,
-                        kvm_rma_size >> 20);
-                rma_info[i].base_virt = rma;
-                rma_info[i].base_pfn = __pa(rma) >> PAGE_SHIFT;
-                rma_info[i].npages = npages;
-                list_add_tail(&rma_info[i].list, &free_rmas);
-                atomic_set(&rma_info[i].use_count, 0);
-
-                pg = pfn_to_page(rma_info[i].base_pfn);
+        typestr = (type == KVM_LINEAR_RMA) ? "RMA" : "HPT";
+
+        npages = size >> PAGE_SHIFT;
+        linear_info = alloc_bootmem(count * sizeof(struct kvmppc_linear_info));
+        for (i = 0; i < count; ++i) {
+                linear = alloc_bootmem_align(size, size);
+                pr_info("Allocated KVM %s at %p (%ld MB)\n", typestr, linear,
+                        size >> 20);
+                linear_info[i].base_virt = linear;
+                linear_info[i].base_pfn = __pa(linear) >> PAGE_SHIFT;
+                linear_info[i].npages = npages;
+                linear_info[i].type = type;
+                list_add_tail(&linear_info[i].list, &free_linears);
+                atomic_set(&linear_info[i].use_count, 0);
+
+                pg = pfn_to_page(linear_info[i].base_pfn);
                 for (j = 0; j < npages; ++j) {
                         atomic_inc(&pg->_count);
                         ++pg;
@@ -127,30 +171,59 @@ void __init kvm_rma_init(void)
         }
 }
 
-struct kvmppc_rma_info *kvm_alloc_rma(void)
+static struct kvmppc_linear_info *kvm_alloc_linear(int type)
 {
-        struct kvmppc_rma_info *ri;
+        struct kvmppc_linear_info *ri;
 
         ri = NULL;
-        spin_lock(&rma_lock);
-        if (!list_empty(&free_rmas)) {
-                ri = list_first_entry(&free_rmas, struct kvmppc_rma_info, list);
+        spin_lock(&linear_lock);
+        list_for_each_entry(ri, &free_linears, list) {
+                if (ri->type != type)
+                        continue;
+
                 list_del(&ri->list);
                 atomic_inc(&ri->use_count);
+                break;
         }
-        spin_unlock(&rma_lock);
+        spin_unlock(&linear_lock);
+        memset(ri->base_virt, 0, ri->npages << PAGE_SHIFT);
         return ri;
 }
-EXPORT_SYMBOL_GPL(kvm_alloc_rma);
 
-void kvm_release_rma(struct kvmppc_rma_info *ri)
+static void kvm_release_linear(struct kvmppc_linear_info *ri)
 {
         if (atomic_dec_and_test(&ri->use_count)) {
-                spin_lock(&rma_lock);
-                list_add_tail(&ri->list, &free_rmas);
-                spin_unlock(&rma_lock);
+                spin_lock(&linear_lock);
+                list_add_tail(&ri->list, &free_linears);
+                spin_unlock(&linear_lock);
 
         }
 }
-EXPORT_SYMBOL_GPL(kvm_release_rma);
 
+/*
+ * Called at boot time while the bootmem allocator is active,
+ * to allocate contiguous physical memory for the hash page
+ * tables for guests.
+ */
+void __init kvm_linear_init(void)
+{
+        /* HPT */
+        kvm_linear_init_one(1 << HPT_ORDER, kvm_hpt_count, KVM_LINEAR_HPT);
+
+        /* RMA */
+        /* Only do this on PPC970 in HV mode */
+        if (!cpu_has_feature(CPU_FTR_HVMODE) ||
+            !cpu_has_feature(CPU_FTR_ARCH_201))
+                return;
+
+        if (!kvm_rma_size || !kvm_rma_count)
+                return;
+
+        /* Check that the requested size is one supported in hardware */
+        if (lpcr_rmls(kvm_rma_size) < 0) {
+                pr_err("RMA size of 0x%lx not supported\n", kvm_rma_size);
+                return;
+        }
+
+        kvm_linear_init_one(kvm_rma_size, kvm_rma_count, KVM_LINEAR_RMA);
+}
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index bacb0cfa360..def880aea63 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -11,6 +11,7 @@
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
 #include <linux/hugetlb.h>
+#include <linux/module.h>
 
 #include <asm/tlbflush.h>
 #include <asm/kvm_ppc.h>
@@ -20,95 +21,307 @@
 #include <asm/synch.h>
 #include <asm/ppc-opcode.h>
 
-/* For now use fixed-size 16MB page table */
-#define HPT_ORDER       24
-#define HPT_NPTEG       (1ul << (HPT_ORDER - 7))        /* 128B per pteg */
-#define HPT_HASH_MASK   (HPT_NPTEG - 1)
+/* Translate address of a vmalloc'd thing to a linear map address */
+static void *real_vmalloc_addr(void *x)
+{
+        unsigned long addr = (unsigned long) x;
+        pte_t *p;
 
-#define HPTE_V_HVLOCK   0x40UL
+        p = find_linux_pte(swapper_pg_dir, addr);
+        if (!p || !pte_present(*p))
+                return NULL;
+        /* assume we don't have huge pages in vmalloc space... */
+        addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
+        return __va(addr);
+}
 
-static inline long lock_hpte(unsigned long *hpte, unsigned long bits)
+/*
+ * Add this HPTE into the chain for the real page.
+ * Must be called with the chain locked; it unlocks the chain.
+ */
+void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
+                             unsigned long *rmap, long pte_index, int realmode)
 {
-        unsigned long tmp, old;
+        struct revmap_entry *head, *tail;
+        unsigned long i;
 
-        asm volatile("  ldarx   %0,0,%2\n"
-                     "  and.    %1,%0,%3\n"
-                     "  bne     2f\n"
-                     "  ori     %0,%0,%4\n"
-                     "  stdcx.  %0,0,%2\n"
-                     "  beq+    2f\n"
-                     "  li      %1,%3\n"
-                     "2:        isync"
-                     : "=&r" (tmp), "=&r" (old)
-                     : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
-                     : "cc", "memory");
-        return old == 0;
+        if (*rmap & KVMPPC_RMAP_PRESENT) {
+                i = *rmap & KVMPPC_RMAP_INDEX;
+                head = &kvm->arch.revmap[i];
+                if (realmode)
+                        head = real_vmalloc_addr(head);
+                tail = &kvm->arch.revmap[head->back];
+                if (realmode)
+                        tail = real_vmalloc_addr(tail);
+                rev->forw = i;
+                rev->back = head->back;
+                tail->forw = pte_index;
+                head->back = pte_index;
+        } else {
+                rev->forw = rev->back = pte_index;
+                i = pte_index;
+        }
+        smp_wmb();
+        *rmap = i | KVMPPC_RMAP_REFERENCED | KVMPPC_RMAP_PRESENT; /* unlock */
+}
+EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
+
+/* Remove this HPTE from the chain for a real page */
+static void remove_revmap_chain(struct kvm *kvm, long pte_index,
+                                struct revmap_entry *rev,
+                                unsigned long hpte_v, unsigned long hpte_r)
+{
+        struct revmap_entry *next, *prev;
+        unsigned long gfn, ptel, head;
+        struct kvm_memory_slot *memslot;
+        unsigned long *rmap;
+        unsigned long rcbits;
+
+        rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
+        ptel = rev->guest_rpte |= rcbits;
+        gfn = hpte_rpn(ptel, hpte_page_size(hpte_v, ptel));
+        memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
+        if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID))
+                return;
+
+        rmap = real_vmalloc_addr(&memslot->rmap[gfn - memslot->base_gfn]);
+        lock_rmap(rmap);
+
+        head = *rmap & KVMPPC_RMAP_INDEX;
+        next = real_vmalloc_addr(&kvm->arch.revmap[rev->forw]);
+        prev = real_vmalloc_addr(&kvm->arch.revmap[rev->back]);
+        next->back = rev->back;
+        prev->forw = rev->forw;
+        if (head == pte_index) {
+                head = rev->forw;
+                if (head == pte_index)
+                        *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
+                else
+                        *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
+        }
+        *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
+        unlock_rmap(rmap);
+}
+
+static pte_t lookup_linux_pte(struct kvm_vcpu *vcpu, unsigned long hva,
+                              int writing, unsigned long *pte_sizep)
+{
+        pte_t *ptep;
+        unsigned long ps = *pte_sizep;
+        unsigned int shift;
+
+        ptep = find_linux_pte_or_hugepte(vcpu->arch.pgdir, hva, &shift);
+        if (!ptep)
+                return __pte(0);
+        if (shift)
+                *pte_sizep = 1ul << shift;
+        else
+                *pte_sizep = PAGE_SIZE;
+        if (ps > *pte_sizep)
+                return __pte(0);
+        if (!pte_present(*ptep))
+                return __pte(0);
+        return kvmppc_read_update_linux_pte(ptep, writing);
+}
+
+static inline void unlock_hpte(unsigned long *hpte, unsigned long hpte_v)
+{
+        asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
+        hpte[0] = hpte_v;
 }
 
 long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
                     long pte_index, unsigned long pteh, unsigned long ptel)
 {
-        unsigned long porder;
         struct kvm *kvm = vcpu->kvm;
-        unsigned long i, lpn, pa;
+        unsigned long i, pa, gpa, gfn, psize;
+        unsigned long slot_fn, hva;
         unsigned long *hpte;
+        struct revmap_entry *rev;
+        unsigned long g_ptel = ptel;
+        struct kvm_memory_slot *memslot;
+        unsigned long *physp, pte_size;
+        unsigned long is_io;
+        unsigned long *rmap;
+        pte_t pte;
+        unsigned int writing;
+        unsigned long mmu_seq;
+        unsigned long rcbits;
+        bool realmode = vcpu->arch.vcore->vcore_state == VCORE_RUNNING;
 
-        /* only handle 4k, 64k and 16M pages for now */
-        porder = 12;
-        if (pteh & HPTE_V_LARGE) {
-                if (cpu_has_feature(CPU_FTR_ARCH_206) &&
-                    (ptel & 0xf000) == 0x1000) {
-                        /* 64k page */
-                        porder = 16;
-                } else if ((ptel & 0xff000) == 0) {
-                        /* 16M page */
-                        porder = 24;
-                        /* lowest AVA bit must be 0 for 16M pages */
-                        if (pteh & 0x80)
-                                return H_PARAMETER;
-                } else
+        psize = hpte_page_size(pteh, ptel);
+        if (!psize)
+                return H_PARAMETER;
+        writing = hpte_is_writable(ptel);
+        pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
+
+        /* used later to detect if we might have been invalidated */
+        mmu_seq = kvm->mmu_notifier_seq;
+        smp_rmb();
+
+        /* Find the memslot (if any) for this address */
+        gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
+        gfn = gpa >> PAGE_SHIFT;
+        memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
+        pa = 0;
+        is_io = ~0ul;
+        rmap = NULL;
+        if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
+                /* PPC970 can't do emulated MMIO */
+                if (!cpu_has_feature(CPU_FTR_ARCH_206))
                         return H_PARAMETER;
+                /* Emulated MMIO - mark this with key=31 */
+                pteh |= HPTE_V_ABSENT;
+                ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
+                goto do_insert;
         }
-        lpn = (ptel & HPTE_R_RPN) >> kvm->arch.ram_porder;
-        if (lpn >= kvm->arch.ram_npages || porder > kvm->arch.ram_porder)
-                return H_PARAMETER;
-        pa = kvm->arch.ram_pginfo[lpn].pfn << PAGE_SHIFT;
-        if (!pa)
+
+        /* Check if the requested page fits entirely in the memslot. */
+        if (!slot_is_aligned(memslot, psize))
                 return H_PARAMETER;
-        /* Check WIMG */
-        if ((ptel & HPTE_R_WIMG) != HPTE_R_M &&
-            (ptel & HPTE_R_WIMG) != (HPTE_R_W | HPTE_R_I | HPTE_R_M))
+        slot_fn = gfn - memslot->base_gfn;
+        rmap = &memslot->rmap[slot_fn];
+
+        if (!kvm->arch.using_mmu_notifiers) {
+                physp = kvm->arch.slot_phys[memslot->id];
+                if (!physp)
+                        return H_PARAMETER;
+                physp += slot_fn;
+                if (realmode)
+                        physp = real_vmalloc_addr(physp);
+                pa = *physp;
+                if (!pa)
+                        return H_TOO_HARD;
+                is_io = pa & (HPTE_R_I | HPTE_R_W);
+                pte_size = PAGE_SIZE << (pa & KVMPPC_PAGE_ORDER_MASK);
+                pa &= PAGE_MASK;
+        } else {
+                /* Translate to host virtual address */
+                hva = gfn_to_hva_memslot(memslot, gfn);
+
+                /* Look up the Linux PTE for the backing page */
+                pte_size = psize;
+                pte = lookup_linux_pte(vcpu, hva, writing, &pte_size);
+                if (pte_present(pte)) {
+                        if (writing && !pte_write(pte))
+                                /* make the actual HPTE be read-only */
+                                ptel = hpte_make_readonly(ptel);
+                        is_io = hpte_cache_bits(pte_val(pte));
+                        pa = pte_pfn(pte) << PAGE_SHIFT;
+                }
+        }
+        if (pte_size < psize)
                 return H_PARAMETER;
-        pteh &= ~0x60UL;
-        ptel &= ~(HPTE_R_PP0 - kvm->arch.ram_psize);
+        if (pa && pte_size > psize)
+                pa |= gpa & (pte_size - 1);
+
+        ptel &= ~(HPTE_R_PP0 - psize);
         ptel |= pa;
-        if (pte_index >= (HPT_NPTEG << 3))
+
+        if (pa)
+                pteh |= HPTE_V_VALID;
+        else
+                pteh |= HPTE_V_ABSENT;
+
+        /* Check WIMG */
+        if (is_io != ~0ul && !hpte_cache_flags_ok(ptel, is_io)) {
+                if (is_io)
+                        return H_PARAMETER;
+                /*
+                 * Allow guest to map emulated device memory as
+                 * uncacheable, but actually make it cacheable.
+                 */
+                ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
+                ptel |= HPTE_R_M;
+        }
+
+        /* Find and lock the HPTEG slot to use */
+ do_insert:
+        if (pte_index >= HPT_NPTE)
                 return H_PARAMETER;
         if (likely((flags & H_EXACT) == 0)) {
                 pte_index &= ~7UL;
                 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
-                for (i = 0; ; ++i) {
-                        if (i == 8)
-                                return H_PTEG_FULL;
+                for (i = 0; i < 8; ++i) {
                         if ((*hpte & HPTE_V_VALID) == 0 &&
-                            lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID))
+                            try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
+                                          HPTE_V_ABSENT))
                                 break;
                         hpte += 2;
                 }
+                if (i == 8) {
+                        /*
+                         * Since try_lock_hpte doesn't retry (not even stdcx.
+                         * failures), it could be that there is a free slot
+                         * but we transiently failed to lock it.  Try again,
+                         * actually locking each slot and checking it.
+                         */
+                        hpte -= 16;
+                        for (i = 0; i < 8; ++i) {
+                                while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
+                                        cpu_relax();
+                                if (!(*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)))
+                                        break;
+                                *hpte &= ~HPTE_V_HVLOCK;
+                                hpte += 2;
+                        }
+                        if (i == 8)
+                                return H_PTEG_FULL;
+                }
+                pte_index += i;
         } else {
-                i = 0;
                 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
-                if (!lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID))
-                        return H_PTEG_FULL;
+                if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
+                                   HPTE_V_ABSENT)) {
+                        /* Lock the slot and check again */
+                        while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
+                                cpu_relax();
+                        if (*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
+                                *hpte &= ~HPTE_V_HVLOCK;
+                                return H_PTEG_FULL;
+                        }
+                }
         }
+
+        /* Save away the guest's idea of the second HPTE dword */
+        rev = &kvm->arch.revmap[pte_index];
+        if (realmode)
+                rev = real_vmalloc_addr(rev);
+        if (rev)
+                rev->guest_rpte = g_ptel;
+
+        /* Link HPTE into reverse-map chain */
+        if (pteh & HPTE_V_VALID) {
+                if (realmode)
+                        rmap = real_vmalloc_addr(rmap);
+                lock_rmap(rmap);
+                /* Check for pending invalidations under the rmap chain lock */
+                if (kvm->arch.using_mmu_notifiers &&
+                    mmu_notifier_retry(vcpu, mmu_seq)) {
+                        /* inval in progress, write a non-present HPTE */
+                        pteh |= HPTE_V_ABSENT;
+                        pteh &= ~HPTE_V_VALID;
+                        unlock_rmap(rmap);
+                } else {
+                        kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
+                                                realmode);
+                        /* Only set R/C in real HPTE if already set in *rmap */
+                        rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
+                        ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
+                }
+        }
+
         hpte[1] = ptel;
+
+        /* Write the first HPTE dword, unlocking the HPTE and making it valid */
         eieio();
         hpte[0] = pteh;
         asm volatile("ptesync" : : : "memory");
-        atomic_inc(&kvm->arch.ram_pginfo[lpn].refcnt);
-        vcpu->arch.gpr[4] = pte_index + i;
+
+        vcpu->arch.gpr[4] = pte_index;
         return H_SUCCESS;
 }
+EXPORT_SYMBOL_GPL(kvmppc_h_enter);
 
 #define LOCK_TOKEN      (*(u32 *)(&get_paca()->lock_token))
 
@@ -137,37 +350,46 @@ long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
         struct kvm *kvm = vcpu->kvm;
         unsigned long *hpte;
         unsigned long v, r, rb;
+        struct revmap_entry *rev;
 
-        if (pte_index >= (HPT_NPTEG << 3))
+        if (pte_index >= HPT_NPTE)
                 return H_PARAMETER;
         hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
-        while (!lock_hpte(hpte, HPTE_V_HVLOCK))
+        while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
                 cpu_relax();
-        if ((hpte[0] & HPTE_V_VALID) == 0 ||
+        if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
             ((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn) ||
             ((flags & H_ANDCOND) && (hpte[0] & avpn) != 0)) {
                 hpte[0] &= ~HPTE_V_HVLOCK;
                 return H_NOT_FOUND;
         }
-        if (atomic_read(&kvm->online_vcpus) == 1)
-                flags |= H_LOCAL;
-        vcpu->arch.gpr[4] = v = hpte[0] & ~HPTE_V_HVLOCK;
-        vcpu->arch.gpr[5] = r = hpte[1];
-        rb = compute_tlbie_rb(v, r, pte_index);
-        hpte[0] = 0;
-        if (!(flags & H_LOCAL)) {
-                while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
-                        cpu_relax();
-                asm volatile("ptesync" : : : "memory");
-                asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
-                             : : "r" (rb), "r" (kvm->arch.lpid));
-                asm volatile("ptesync" : : : "memory");
-                kvm->arch.tlbie_lock = 0;
-        } else {
-                asm volatile("ptesync" : : : "memory");
-                asm volatile("tlbiel %0" : : "r" (rb));
-                asm volatile("ptesync" : : : "memory");
+
+        rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
+        v = hpte[0] & ~HPTE_V_HVLOCK;
+        if (v & HPTE_V_VALID) {
+                hpte[0] &= ~HPTE_V_VALID;
+                rb = compute_tlbie_rb(v, hpte[1], pte_index);
+                if (!(flags & H_LOCAL) && atomic_read(&kvm->online_vcpus) > 1) {
+                        while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
+                                cpu_relax();
+                        asm volatile("ptesync" : : : "memory");
+                        asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
+                                     : : "r" (rb), "r" (kvm->arch.lpid));
+                        asm volatile("ptesync" : : : "memory");
+                        kvm->arch.tlbie_lock = 0;
+                } else {
+                        asm volatile("ptesync" : : : "memory");
+                        asm volatile("tlbiel %0" : : "r" (rb));
+                        asm volatile("ptesync" : : : "memory");
+                }
+                /* Read PTE low word after tlbie to get final R/C values */
+                remove_revmap_chain(kvm, pte_index, rev, v, hpte[1]);
         }
+        r = rev->guest_rpte;
+        unlock_hpte(hpte, 0);
+
+        vcpu->arch.gpr[4] = v;
+        vcpu->arch.gpr[5] = r;
         return H_SUCCESS;
 }
 
@@ -175,78 +397,117 @@ long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
 {
         struct kvm *kvm = vcpu->kvm;
         unsigned long *args = &vcpu->arch.gpr[4];
-        unsigned long *hp, tlbrb[4];
-        long int i, found;
-        long int n_inval = 0;
-        unsigned long flags, req, pte_index;
+        unsigned long *hp, *hptes[4], tlbrb[4];
+        long int i, j, k, n, found, indexes[4];
+        unsigned long flags, req, pte_index, rcbits;
         long int local = 0;
         long int ret = H_SUCCESS;
+        struct revmap_entry *rev, *revs[4];
 
         if (atomic_read(&kvm->online_vcpus) == 1)
                 local = 1;
-        for (i = 0; i < 4; ++i) {
-                pte_index = args[i * 2];
-                flags = pte_index >> 56;
-                pte_index &= ((1ul << 56) - 1);
-                req = flags >> 6;
-                flags &= 3;
-                if (req == 3)
-                        break;
-                if (req != 1 || flags == 3 ||
-                    pte_index >= (HPT_NPTEG << 3)) {
-                        /* parameter error */
-                        args[i * 2] = ((0xa0 | flags) << 56) + pte_index;
-                        ret = H_PARAMETER;
-                        break;
-                }
-                hp = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
-                while (!lock_hpte(hp, HPTE_V_HVLOCK))
-                        cpu_relax();
-                found = 0;
-                if (hp[0] & HPTE_V_VALID) {
-                        switch (flags & 3) {
-                        case 0:         /* absolute */
-                                found = 1;
+        for (i = 0; i < 4 && ret == H_SUCCESS; ) {
+                n = 0;
+                for (; i < 4; ++i) {
+                        j = i * 2;
+                        pte_index = args[j];
+                        flags = pte_index >> 56;
+                        pte_index &= ((1ul << 56) - 1);
+                        req = flags >> 6;
+                        flags &= 3;
+                        if (req == 3) {         /* no more requests */
+                                i = 4;
                                 break;
-                        case 1:         /* andcond */
-                                if (!(hp[0] & args[i * 2 + 1]))
-                                        found = 1;
+                        }
+                        if (req != 1 || flags == 3 || pte_index >= HPT_NPTE) {
+                                /* parameter error */
+                                args[j] = ((0xa0 | flags) << 56) + pte_index;
+                                ret = H_PARAMETER;
                                 break;
-                        case 2:         /* AVPN */
-                                if ((hp[0] & ~0x7fUL) == args[i * 2 + 1])
+                        }
+                        hp = (unsigned long *)
+                                (kvm->arch.hpt_virt + (pte_index << 4));
+                        /* to avoid deadlock, don't spin except for first */
+                        if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
+                                if (n)
+                                        break;
+                                while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
+                                        cpu_relax();
+                        }
+                        found = 0;
+                        if (hp[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) {
+                                switch (flags & 3) {
+                                case 0:         /* absolute */
                                         found = 1;
-                                break;
+                                        break;
+                                case 1:         /* andcond */
+                                        if (!(hp[0] & args[j + 1]))
+                                                found = 1;
+                                        break;
+                                case 2:         /* AVPN */
+                                        if ((hp[0] & ~0x7fUL) == args[j + 1])
+                                                found = 1;
+                                        break;
+                                }
+                        }
+                        if (!found) {
+                                hp[0] &= ~HPTE_V_HVLOCK;
+                                args[j] = ((0x90 | flags) << 56) + pte_index;
+                                continue;
                         }
+
+                        args[j] = ((0x80 | flags) << 56) + pte_index;
+                        rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
+
+                        if (!(hp[0] & HPTE_V_VALID)) {
+                                /* insert R and C bits from PTE */
+                                rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
+                                args[j] |= rcbits << (56 - 5);
+                                continue;
+                        }
+
+                        hp[0] &= ~HPTE_V_VALID;         /* leave it locked */
+                        tlbrb[n] = compute_tlbie_rb(hp[0], hp[1], pte_index);
+                        indexes[n] = j;
+                        hptes[n] = hp;
+                        revs[n] = rev;
+                        ++n;
+                }
+
+                if (!n)
+                        break;
+
+                /* Now that we've collected a batch, do the tlbies */
+                if (!local) {
+                        while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
+                                cpu_relax();
+                        asm volatile("ptesync" : : : "memory");
+                        for (k = 0; k < n; ++k)
+                                asm volatile(PPC_TLBIE(%1,%0) : :
+                                             "r" (tlbrb[k]),
+                                             "r" (kvm->arch.lpid));
+                        asm volatile("eieio; tlbsync; ptesync" : : : "memory");
+                        kvm->arch.tlbie_lock = 0;
+                } else {
+                        asm volatile("ptesync" : : : "memory");
+                        for (k = 0; k < n; ++k)
+                                asm volatile("tlbiel %0" : : "r" (tlbrb[k]));
+                        asm volatile("ptesync" : : : "memory");
                 }
-                if (!found) {
-                        hp[0] &= ~HPTE_V_HVLOCK;
-                        args[i * 2] = ((0x90 | flags) << 56) + pte_index;
-                        continue;
+
+                /* Read PTE low words after tlbie to get final R/C values */
+                for (k = 0; k < n; ++k) {
+                        j = indexes[k];
+                        pte_index = args[j] & ((1ul << 56) - 1);
+                        hp = hptes[k];
+                        rev = revs[k];
+                        remove_revmap_chain(kvm, pte_index, rev, hp[0], hp[1]);
+                        rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
+                        args[j] |= rcbits << (56 - 5);
+                        hp[0] = 0;
                 }
-                /* insert R and C bits from PTE */
-                flags |= (hp[1] >> 5) & 0x0c;
-                args[i * 2] = ((0x80 | flags) << 56) + pte_index;
-                tlbrb[n_inval++] = compute_tlbie_rb(hp[0], hp[1], pte_index);
-                hp[0] = 0;
-        }
-        if (n_inval == 0)
-                return ret;
-
-        if (!local) {
-                while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
-                        cpu_relax();
-                asm volatile("ptesync" : : : "memory");
-                for (i = 0; i < n_inval; ++i)
-                        asm volatile(PPC_TLBIE(%1,%0)
-                                     : : "r" (tlbrb[i]), "r" (kvm->arch.lpid));
-                asm volatile("eieio; tlbsync; ptesync" : : : "memory");
-                kvm->arch.tlbie_lock = 0;
-        } else {
-                asm volatile("ptesync" : : : "memory");
-                for (i = 0; i < n_inval; ++i)
-                        asm volatile("tlbiel %0" : : "r" (tlbrb[i]));
-                asm volatile("ptesync" : : : "memory");
         }
+
         return ret;
 }
 
@@ -256,40 +517,55 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
 {
         struct kvm *kvm = vcpu->kvm;
         unsigned long *hpte;
-        unsigned long v, r, rb;
+        struct revmap_entry *rev;
+        unsigned long v, r, rb, mask, bits;
 
-        if (pte_index >= (HPT_NPTEG << 3))
+        if (pte_index >= HPT_NPTE)
                 return H_PARAMETER;
+
         hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
-        while (!lock_hpte(hpte, HPTE_V_HVLOCK))
+        while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
                 cpu_relax();
-        if ((hpte[0] & HPTE_V_VALID) == 0 ||
+        if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
             ((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn)) {
                 hpte[0] &= ~HPTE_V_HVLOCK;
                 return H_NOT_FOUND;
         }
+
         if (atomic_read(&kvm->online_vcpus) == 1)
                 flags |= H_LOCAL;
         v = hpte[0];
-        r = hpte[1] & ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
-                        HPTE_R_KEY_HI | HPTE_R_KEY_LO);
-        r |= (flags << 55) & HPTE_R_PP0;
-        r |= (flags << 48) & HPTE_R_KEY_HI;
-        r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
-        rb = compute_tlbie_rb(v, r, pte_index);
-        hpte[0] = v & ~HPTE_V_VALID;
-        if (!(flags & H_LOCAL)) {
-                while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
-                        cpu_relax();
-                asm volatile("ptesync" : : : "memory");
-                asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
-                             : : "r" (rb), "r" (kvm->arch.lpid));
-                asm volatile("ptesync" : : : "memory");
-                kvm->arch.tlbie_lock = 0;
-        } else {
-                asm volatile("ptesync" : : : "memory");
-                asm volatile("tlbiel %0" : : "r" (rb));
-                asm volatile("ptesync" : : : "memory");
+        bits = (flags << 55) & HPTE_R_PP0;
+        bits |= (flags << 48) & HPTE_R_KEY_HI;
+        bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
+
+        /* Update guest view of 2nd HPTE dword */
+        mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
+                HPTE_R_KEY_HI | HPTE_R_KEY_LO;
+        rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
+        if (rev) {
+                r = (rev->guest_rpte & ~mask) | bits;
+                rev->guest_rpte = r;
+        }
+        r = (hpte[1] & ~mask) | bits;
+
+        /* Update HPTE */
+        if (v & HPTE_V_VALID) {
+                rb = compute_tlbie_rb(v, r, pte_index);
+                hpte[0] = v & ~HPTE_V_VALID;
+                if (!(flags & H_LOCAL)) {
+                        while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
+                                cpu_relax();
+                        asm volatile("ptesync" : : : "memory");
+                        asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
+                                     : : "r" (rb), "r" (kvm->arch.lpid));
+                        asm volatile("ptesync" : : : "memory");
+                        kvm->arch.tlbie_lock = 0;
+                } else {
+                        asm volatile("ptesync" : : : "memory");
+                        asm volatile("tlbiel %0" : : "r" (rb));
+                        asm volatile("ptesync" : : : "memory");
+                }
         }
         hpte[1] = r;
         eieio();
@@ -298,40 +574,243 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
         return H_SUCCESS;
 }
 
-static unsigned long reverse_xlate(struct kvm *kvm, unsigned long realaddr)
-{
-        long int i;
-        unsigned long offset, rpn;
-
-        offset = realaddr & (kvm->arch.ram_psize - 1);
-        rpn = (realaddr - offset) >> PAGE_SHIFT;
-        for (i = 0; i < kvm->arch.ram_npages; ++i)
-                if (rpn == kvm->arch.ram_pginfo[i].pfn)
-                        return (i << PAGE_SHIFT) + offset;
-        return HPTE_R_RPN;      /* all 1s in the RPN field */
-}
-
 long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
                    unsigned long pte_index)
 {
         struct kvm *kvm = vcpu->kvm;
-        unsigned long *hpte, r;
+        unsigned long *hpte, v, r;
         int i, n = 1;
+        struct revmap_entry *rev = NULL;
 
-        if (pte_index >= (HPT_NPTEG << 3))
+        if (pte_index >= HPT_NPTE)
                 return H_PARAMETER;
         if (flags & H_READ_4) {
                 pte_index &= ~3;
                 n = 4;
         }
+        rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
         for (i = 0; i < n; ++i, ++pte_index) {
                 hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
+                v = hpte[0] & ~HPTE_V_HVLOCK;
                 r = hpte[1];
-                if ((flags & H_R_XLATE) && (hpte[0] & HPTE_V_VALID))
-                        r = reverse_xlate(kvm, r & HPTE_R_RPN) |
-                                (r & ~HPTE_R_RPN);
-                vcpu->arch.gpr[4 + i * 2] = hpte[0];
+                if (v & HPTE_V_ABSENT) {
+                        v &= ~HPTE_V_ABSENT;
+                        v |= HPTE_V_VALID;
+                }
+                if (v & HPTE_V_VALID)
+                        r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
+                vcpu->arch.gpr[4 + i * 2] = v;
                 vcpu->arch.gpr[5 + i * 2] = r;
         }
         return H_SUCCESS;
 }
+
+void kvmppc_invalidate_hpte(struct kvm *kvm, unsigned long *hptep,
+                        unsigned long pte_index)
+{
+        unsigned long rb;
+
+        hptep[0] &= ~HPTE_V_VALID;
+        rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
+        while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
+                cpu_relax();
+        asm volatile("ptesync" : : : "memory");
+        asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
+                     : : "r" (rb), "r" (kvm->arch.lpid));
+        asm volatile("ptesync" : : : "memory");
+        kvm->arch.tlbie_lock = 0;
+}
+EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
+
+void kvmppc_clear_ref_hpte(struct kvm *kvm, unsigned long *hptep,
+                           unsigned long pte_index)
+{
+        unsigned long rb;
+        unsigned char rbyte;
+
+        rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
+        rbyte = (hptep[1] & ~HPTE_R_R) >> 8;
+        /* modify only the second-last byte, which contains the ref bit */
+        *((char *)hptep + 14) = rbyte;
+        while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
+                cpu_relax();
+        asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
+                     : : "r" (rb), "r" (kvm->arch.lpid));
+        asm volatile("ptesync" : : : "memory");
+        kvm->arch.tlbie_lock = 0;
+}
+EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
+
+static int slb_base_page_shift[4] = {
+        24,     /* 16M */
+        16,     /* 64k */
+        34,     /* 16G */
+        20,     /* 1M, unsupported */
+};
+
+long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
+                              unsigned long valid)
+{
+        unsigned int i;
+        unsigned int pshift;
+        unsigned long somask;
+        unsigned long vsid, hash;
+        unsigned long avpn;
+        unsigned long *hpte;
+        unsigned long mask, val;
+        unsigned long v, r;
+
+        /* Get page shift, work out hash and AVPN etc. */
+        mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
+        val = 0;
+        pshift = 12;
+        if (slb_v & SLB_VSID_L) {
+                mask |= HPTE_V_LARGE;
+                val |= HPTE_V_LARGE;
+                pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
+        }
+        if (slb_v & SLB_VSID_B_1T) {
+                somask = (1UL << 40) - 1;
+                vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
+                vsid ^= vsid << 25;
+        } else {
+                somask = (1UL << 28) - 1;
+                vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
+        }
+        hash = (vsid ^ ((eaddr & somask) >> pshift)) & HPT_HASH_MASK;
+        avpn = slb_v & ~(somask >> 16); /* also includes B */
+        avpn |= (eaddr & somask) >> 16;
+
+        if (pshift >= 24)
+                avpn &= ~((1UL << (pshift - 16)) - 1);
+        else
+                avpn &= ~0x7fUL;
+        val |= avpn;
+
+        for (;;) {
+                hpte = (unsigned long *)(kvm->arch.hpt_virt + (hash << 7));
+
+                for (i = 0; i < 16; i += 2) {
+                        /* Read the PTE racily */
+                        v = hpte[i] & ~HPTE_V_HVLOCK;
+
+                        /* Check valid/absent, hash, segment size and AVPN */
+                        if (!(v & valid) || (v & mask) != val)
+                                continue;
+
+                        /* Lock the PTE and read it under the lock */
+                        while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
+                                cpu_relax();
+                        v = hpte[i] & ~HPTE_V_HVLOCK;
+                        r = hpte[i+1];
+
+                        /*
+                         * Check the HPTE again, including large page size
+                         * Since we don't currently allow any MPSS (mixed
+                         * page-size segment) page sizes, it is sufficient
+                         * to check against the actual page size.
+                         */
+                        if ((v & valid) && (v & mask) == val &&
+                            hpte_page_size(v, r) == (1ul << pshift))
+                                /* Return with the HPTE still locked */
+                                return (hash << 3) + (i >> 1);
+
+                        /* Unlock and move on */
+                        hpte[i] = v;
+                }
+
+                if (val & HPTE_V_SECONDARY)
+                        break;
+                val |= HPTE_V_SECONDARY;
+                hash = hash ^ HPT_HASH_MASK;
+        }
+        return -1;
+}
+EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
+
+/*
+ * Called in real mode to check whether an HPTE not found fault
+ * is due to accessing a paged-out page or an emulated MMIO page,
+ * or if a protection fault is due to accessing a page that the
+ * guest wanted read/write access to but which we made read-only.
+ * Returns a possibly modified status (DSISR) value if not
+ * (i.e. pass the interrupt to the guest),
+ * -1 to pass the fault up to host kernel mode code, -2 to do that
+ * and also load the instruction word (for MMIO emulation),
+ * or 0 if we should make the guest retry the access.
+ */
+long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
+                          unsigned long slb_v, unsigned int status, bool data)
+{
+        struct kvm *kvm = vcpu->kvm;
+        long int index;
+        unsigned long v, r, gr;
+        unsigned long *hpte;
+        unsigned long valid;
+        struct revmap_entry *rev;
+        unsigned long pp, key;
+
+        /* For protection fault, expect to find a valid HPTE */
+        valid = HPTE_V_VALID;
+        if (status & DSISR_NOHPTE)
+                valid |= HPTE_V_ABSENT;
+
+        index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
+        if (index < 0) {
+                if (status & DSISR_NOHPTE)
+                        return status;  /* there really was no HPTE */
+                return 0;               /* for prot fault, HPTE disappeared */
+        }
+        hpte = (unsigned long *)(kvm->arch.hpt_virt + (index << 4));
+        v = hpte[0] & ~HPTE_V_HVLOCK;
+        r = hpte[1];
+        rev = real_vmalloc_addr(&kvm->arch.revmap[index]);
+        gr = rev->guest_rpte;
+
+        unlock_hpte(hpte, v);
+
+        /* For not found, if the HPTE is valid by now, retry the instruction */
+        if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
+                return 0;
+
+        /* Check access permissions to the page */
+        pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
+        key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
+        status &= ~DSISR_NOHPTE;        /* DSISR_NOHPTE == SRR1_ISI_NOPT */
+        if (!data) {
+                if (gr & (HPTE_R_N | HPTE_R_G))
+                        return status | SRR1_ISI_N_OR_G;
+                if (!hpte_read_permission(pp, slb_v & key))
+                        return status | SRR1_ISI_PROT;
+        } else if (status & DSISR_ISSTORE) {
+                /* check write permission */
+                if (!hpte_write_permission(pp, slb_v & key))
+                        return status | DSISR_PROTFAULT;
+        } else {
+                if (!hpte_read_permission(pp, slb_v & key))
+                        return status | DSISR_PROTFAULT;
+        }
+
+        /* Check storage key, if applicable */
+        if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
+                unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
+                if (status & DSISR_ISSTORE)
+                        perm >>= 1;
+                if (perm & 1)
+                        return status | DSISR_KEYFAULT;
+        }
+
+        /* Save HPTE info for virtual-mode handler */
+        vcpu->arch.pgfault_addr = addr;
+        vcpu->arch.pgfault_index = index;
+        vcpu->arch.pgfault_hpte[0] = v;
+        vcpu->arch.pgfault_hpte[1] = r;
+
+        /* Check the storage key to see if it is possibly emulated MMIO */
+        if (data && (vcpu->arch.shregs.msr & MSR_IR) &&
+            (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
+            (HPTE_R_KEY_HI | HPTE_R_KEY_LO))
+                return -2;      /* MMIO emulation - load instr word */
+
+        return -1;              /* send fault up to host kernel mode */
+}
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 5c8b26183f5..b70bf22a3ff 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -601,6 +601,30 @@ kvmppc_interrupt:
 
         stw     r12,VCPU_TRAP(r9)
 
+        /* Save HEIR (HV emulation assist reg) in last_inst
+           if this is an HEI (HV emulation interrupt, e40) */
+        li      r3,KVM_INST_FETCH_FAILED
+BEGIN_FTR_SECTION
+        cmpwi   r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
+        bne     11f
+        mfspr   r3,SPRN_HEIR
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+11:     stw     r3,VCPU_LAST_INST(r9)
+
+        /* these are volatile across C function calls */
+        mfctr   r3
+        mfxer   r4
+        std     r3, VCPU_CTR(r9)
+        stw     r4, VCPU_XER(r9)
+
+BEGIN_FTR_SECTION
+        /* If this is a page table miss then see if it's theirs or ours */
+        cmpwi   r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
+        beq     kvmppc_hdsi
+        cmpwi   r12, BOOK3S_INTERRUPT_H_INST_STORAGE
+        beq     kvmppc_hisi
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+
         /* See if this is a leftover HDEC interrupt */
         cmpwi   r12,BOOK3S_INTERRUPT_HV_DECREMENTER
         bne     2f
@@ -608,7 +632,7 @@ kvmppc_interrupt:
         cmpwi   r3,0
         bge     ignore_hdec
 2:
-        /* See if this is something we can handle in real mode */
+        /* See if this is an hcall we can handle in real mode */
         cmpwi   r12,BOOK3S_INTERRUPT_SYSCALL
         beq     hcall_try_real_mode
 
@@ -624,6 +648,7 @@ BEGIN_FTR_SECTION
 1:
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 
+nohpte_cont:
 hcall_real_cont:                /* r9 = vcpu, r12 = trap, r13 = paca */
         /* Save DEC */
         mfspr   r5,SPRN_DEC
@@ -632,36 +657,21 @@ hcall_real_cont:		/* r9 = vcpu, r12 = trap, r13 = paca */
         add     r5,r5,r6
         std     r5,VCPU_DEC_EXPIRES(r9)
 
-        /* Save HEIR (HV emulation assist reg) in last_inst
-           if this is an HEI (HV emulation interrupt, e40) */
-        li      r3,-1
-BEGIN_FTR_SECTION
-        cmpwi   r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
-        bne     11f
-        mfspr   r3,SPRN_HEIR
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
-11:     stw     r3,VCPU_LAST_INST(r9)
-
         /* Save more register state  */
-        mfxer   r5
         mfdar   r6
         mfdsisr r7
-        mfctr   r8
-
-        stw     r5, VCPU_XER(r9)
         std     r6, VCPU_DAR(r9)
         stw     r7, VCPU_DSISR(r9)
-        std     r8, VCPU_CTR(r9)
-        /* grab HDAR & HDSISR if HV data storage interrupt (HDSI) */
 BEGIN_FTR_SECTION
+        /* don't overwrite fault_dar/fault_dsisr if HDSI */
         cmpwi   r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
         beq     6f
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
-7:      std     r6, VCPU_FAULT_DAR(r9)
+        std     r6, VCPU_FAULT_DAR(r9)
         stw     r7, VCPU_FAULT_DSISR(r9)
 
         /* Save guest CTRL register, set runlatch to 1 */
-        mfspr   r6,SPRN_CTRLF
+6:      mfspr   r6,SPRN_CTRLF
         stw     r6,VCPU_CTRL(r9)
         andi.   r0,r6,1
         bne     4f
@@ -1094,9 +1104,131 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         mtspr   SPRN_HSRR1, r7
         ba      0x500
 
-6:      mfspr   r6,SPRN_HDAR
-        mfspr   r7,SPRN_HDSISR
-        b       7b
+/*
+ * Check whether an HDSI is an HPTE not found fault or something else.
+ * If it is an HPTE not found fault that is due to the guest accessing
+ * a page that they have mapped but which we have paged out, then
+ * we continue on with the guest exit path.  In all other cases,
+ * reflect the HDSI to the guest as a DSI.
+ */
+kvmppc_hdsi:
+        mfspr   r4, SPRN_HDAR
+        mfspr   r6, SPRN_HDSISR
+        /* HPTE not found fault or protection fault? */
+        andis.  r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
+        beq     1f                      /* if not, send it to the guest */
+        andi.   r0, r11, MSR_DR         /* data relocation enabled? */
+        beq     3f
+        clrrdi  r0, r4, 28
+        PPC_SLBFEE_DOT(r5, r0)          /* if so, look up SLB */
+        bne     1f                      /* if no SLB entry found */
+4:      std     r4, VCPU_FAULT_DAR(r9)
+        stw     r6, VCPU_FAULT_DSISR(r9)
+
+        /* Search the hash table. */
+        mr      r3, r9                  /* vcpu pointer */
+        li      r7, 1                   /* data fault */
+        bl      .kvmppc_hpte_hv_fault
+        ld      r9, HSTATE_KVM_VCPU(r13)
+        ld      r10, VCPU_PC(r9)
+        ld      r11, VCPU_MSR(r9)
+        li      r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
+        cmpdi   r3, 0                   /* retry the instruction */
+        beq     6f
+        cmpdi   r3, -1                  /* handle in kernel mode */
+        beq     nohpte_cont
+        cmpdi   r3, -2                  /* MMIO emulation; need instr word */
+        beq     2f
+
+        /* Synthesize a DSI for the guest */
+        ld      r4, VCPU_FAULT_DAR(r9)
+        mr      r6, r3
+1:      mtspr   SPRN_DAR, r4
+        mtspr   SPRN_DSISR, r6
+        mtspr   SPRN_SRR0, r10
+        mtspr   SPRN_SRR1, r11
+        li      r10, BOOK3S_INTERRUPT_DATA_STORAGE
+        li      r11, (MSR_ME << 1) | 1  /* synthesize MSR_SF | MSR_ME */
+        rotldi  r11, r11, 63
+6:      ld      r7, VCPU_CTR(r9)
+        lwz     r8, VCPU_XER(r9)
+        mtctr   r7
+        mtxer   r8
+        mr      r4, r9
+        b       fast_guest_return
+
+3:      ld      r5, VCPU_KVM(r9)        /* not relocated, use VRMA */
+        ld      r5, KVM_VRMA_SLB_V(r5)
+        b       4b
+
+        /* If this is for emulated MMIO, load the instruction word */
+2:      li      r8, KVM_INST_FETCH_FAILED       /* In case lwz faults */
+
+        /* Set guest mode to 'jump over instruction' so if lwz faults
+         * we'll just continue at the next IP. */
+        li      r0, KVM_GUEST_MODE_SKIP
+        stb     r0, HSTATE_IN_GUEST(r13)
+
+        /* Do the access with MSR:DR enabled */
+        mfmsr   r3
+        ori     r4, r3, MSR_DR          /* Enable paging for data */
+        mtmsrd  r4
+        lwz     r8, 0(r10)
+        mtmsrd  r3
+
+        /* Store the result */
+        stw     r8, VCPU_LAST_INST(r9)
+
+        /* Unset guest mode. */
+        li      r0, KVM_GUEST_MODE_NONE
+        stb     r0, HSTATE_IN_GUEST(r13)
+        b       nohpte_cont
+
+/*
+ * Similarly for an HISI, reflect it to the guest as an ISI unless
+ * it is an HPTE not found fault for a page that we have paged out.
+ */
+kvmppc_hisi:
+        andis.  r0, r11, SRR1_ISI_NOPT@h
+        beq     1f
+        andi.   r0, r11, MSR_IR         /* instruction relocation enabled? */
+        beq     3f
+        clrrdi  r0, r10, 28
+        PPC_SLBFEE_DOT(r5, r0)          /* if so, look up SLB */
+        bne     1f                      /* if no SLB entry found */
+4:
+        /* Search the hash table. */
+        mr      r3, r9                  /* vcpu pointer */
+        mr      r4, r10
+        mr      r6, r11
+        li      r7, 0                   /* instruction fault */
+        bl      .kvmppc_hpte_hv_fault
+        ld      r9, HSTATE_KVM_VCPU(r13)
+        ld      r10, VCPU_PC(r9)
+        ld      r11, VCPU_MSR(r9)
+        li      r12, BOOK3S_INTERRUPT_H_INST_STORAGE
+        cmpdi   r3, 0                   /* retry the instruction */
+        beq     6f
+        cmpdi   r3, -1                  /* handle in kernel mode */
+        beq     nohpte_cont
+
+        /* Synthesize an ISI for the guest */
+        mr      r11, r3
+1:      mtspr   SPRN_SRR0, r10
+        mtspr   SPRN_SRR1, r11
+        li      r10, BOOK3S_INTERRUPT_INST_STORAGE
+        li      r11, (MSR_ME << 1) | 1  /* synthesize MSR_SF | MSR_ME */
+        rotldi  r11, r11, 63
+6:      ld      r7, VCPU_CTR(r9)
+        lwz     r8, VCPU_XER(r9)
+        mtctr   r7
+        mtxer   r8
+        mr      r4, r9
+        b       fast_guest_return
+
+3:      ld      r6, VCPU_KVM(r9)        /* not relocated, use VRMA */
+        ld      r5, KVM_VRMA_SLB_V(r6)
+        b       4b
 
 /*
  * Try to handle an hcall in real mode.
diff --git a/arch/powerpc/kvm/book3s_paired_singles.c b/arch/powerpc/kvm/book3s_paired_singles.c
index 7b0ee96c1be..e70ef2d8643 100644
--- a/arch/powerpc/kvm/book3s_paired_singles.c
+++ b/arch/powerpc/kvm/book3s_paired_singles.c
@@ -196,7 +196,8 @@ static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 kvmppc_inject_pf(vcpu, addr, false);
                 goto done_load;
         } else if (r == EMULATE_DO_MMIO) {
-                emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FPR | rs, len, 1);
+                emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FPR | rs,
+                                              len, 1);
                 goto done_load;
         }
 
@@ -286,11 +287,13 @@ static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 kvmppc_inject_pf(vcpu, addr, false);
                 goto done_load;
         } else if ((r == EMULATE_DO_MMIO) && w) {
-                emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FPR | rs, 4, 1);
+                emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FPR | rs,
+                                              4, 1);
                 vcpu->arch.qpr[rs] = tmp[1];
                 goto done_load;
         } else if (r == EMULATE_DO_MMIO) {
-                emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FQPR | rs, 8, 1);
+                emulated = kvmppc_handle_load(run, vcpu, KVM_MMIO_REG_FQPR | rs,
+                                              8, 1);
                 goto done_load;
         }
 
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 220fcdf2697..7340e1090b7 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -51,15 +51,19 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
 #define MSR_USER32 MSR_USER
 #define MSR_USER64 MSR_USER
 #define HW_PAGE_SIZE PAGE_SIZE
+#define __hard_irq_disable local_irq_disable
+#define __hard_irq_enable local_irq_enable
 #endif
 
 void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
 #ifdef CONFIG_PPC_BOOK3S_64
-        memcpy(to_svcpu(vcpu)->slb, to_book3s(vcpu)->slb_shadow, sizeof(to_svcpu(vcpu)->slb));
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb));
         memcpy(&get_paca()->shadow_vcpu, to_book3s(vcpu)->shadow_vcpu,
                sizeof(get_paca()->shadow_vcpu));
-        to_svcpu(vcpu)->slb_max = to_book3s(vcpu)->slb_shadow_max;
+        svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max;
+        svcpu_put(svcpu);
 #endif
 
 #ifdef CONFIG_PPC_BOOK3S_32
@@ -70,10 +74,12 @@ void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
 {
 #ifdef CONFIG_PPC_BOOK3S_64
-        memcpy(to_book3s(vcpu)->slb_shadow, to_svcpu(vcpu)->slb, sizeof(to_svcpu(vcpu)->slb));
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb));
         memcpy(to_book3s(vcpu)->shadow_vcpu, &get_paca()->shadow_vcpu,
                sizeof(get_paca()->shadow_vcpu));
-        to_book3s(vcpu)->slb_shadow_max = to_svcpu(vcpu)->slb_max;
+        to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max;
+        svcpu_put(svcpu);
 #endif
 
         kvmppc_giveup_ext(vcpu, MSR_FP);
@@ -151,14 +157,16 @@ void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr)
 #ifdef CONFIG_PPC_BOOK3S_64
         if ((pvr >= 0x330000) && (pvr < 0x70330000)) {
                 kvmppc_mmu_book3s_64_init(vcpu);
-                to_book3s(vcpu)->hior = 0xfff00000;
+                if (!to_book3s(vcpu)->hior_explicit)
+                        to_book3s(vcpu)->hior = 0xfff00000;
                 to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL;
                 vcpu->arch.cpu_type = KVM_CPU_3S_64;
         } else
 #endif
         {
                 kvmppc_mmu_book3s_32_init(vcpu);
-                to_book3s(vcpu)->hior = 0;
+                if (!to_book3s(vcpu)->hior_explicit)
+                        to_book3s(vcpu)->hior = 0;
                 to_book3s(vcpu)->msr_mask = 0xffffffffULL;
                 vcpu->arch.cpu_type = KVM_CPU_3S_32;
         }
@@ -308,19 +316,22 @@ int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
         if (page_found == -ENOENT) {
                 /* Page not found in guest PTE entries */
+                struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
                 vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu);
-                vcpu->arch.shared->dsisr = to_svcpu(vcpu)->fault_dsisr;
+                vcpu->arch.shared->dsisr = svcpu->fault_dsisr;
                 vcpu->arch.shared->msr |=
-                        (to_svcpu(vcpu)->shadow_srr1 & 0x00000000f8000000ULL);
+                        (svcpu->shadow_srr1 & 0x00000000f8000000ULL);
+                svcpu_put(svcpu);
                 kvmppc_book3s_queue_irqprio(vcpu, vec);
         } else if (page_found == -EPERM) {
                 /* Storage protection */
+                struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
                 vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu);
-                vcpu->arch.shared->dsisr =
-                        to_svcpu(vcpu)->fault_dsisr & ~DSISR_NOHPTE;
+                vcpu->arch.shared->dsisr = svcpu->fault_dsisr & ~DSISR_NOHPTE;
                 vcpu->arch.shared->dsisr |= DSISR_PROTFAULT;
                 vcpu->arch.shared->msr |=
-                        (to_svcpu(vcpu)->shadow_srr1 & 0x00000000f8000000ULL);
+                        svcpu->shadow_srr1 & 0x00000000f8000000ULL;
+                svcpu_put(svcpu);
                 kvmppc_book3s_queue_irqprio(vcpu, vec);
         } else if (page_found == -EINVAL) {
                 /* Page not found in guest SLB */
@@ -517,24 +528,29 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
         run->ready_for_interrupt_injection = 1;
 
         trace_kvm_book3s_exit(exit_nr, vcpu);
+        preempt_enable();
         kvm_resched(vcpu);
         switch (exit_nr) {
         case BOOK3S_INTERRUPT_INST_STORAGE:
+        {
+                struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+                ulong shadow_srr1 = svcpu->shadow_srr1;
                 vcpu->stat.pf_instruc++;
 
 #ifdef CONFIG_PPC_BOOK3S_32
                 /* We set segments as unused segments when invalidating them. So
                  * treat the respective fault as segment fault. */
-                if (to_svcpu(vcpu)->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT]
-                    == SR_INVALID) {
+                if (svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT] == SR_INVALID) {
                         kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
                         r = RESUME_GUEST;
+                        svcpu_put(svcpu);
                         break;
                 }
 #endif
+                svcpu_put(svcpu);
 
                 /* only care about PTEG not found errors, but leave NX alone */
-                if (to_svcpu(vcpu)->shadow_srr1 & 0x40000000) {
+                if (shadow_srr1 & 0x40000000) {
                         r = kvmppc_handle_pagefault(run, vcpu, kvmppc_get_pc(vcpu), exit_nr);
                         vcpu->stat.sp_instruc++;
                 } else if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
@@ -547,33 +563,37 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL);
                         r = RESUME_GUEST;
                 } else {
-                        vcpu->arch.shared->msr |=
-                                to_svcpu(vcpu)->shadow_srr1 & 0x58000000;
+                        vcpu->arch.shared->msr |= shadow_srr1 & 0x58000000;
                         kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
                         r = RESUME_GUEST;
                 }
                 break;
+        }
         case BOOK3S_INTERRUPT_DATA_STORAGE:
         {
                 ulong dar = kvmppc_get_fault_dar(vcpu);
+                struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+                u32 fault_dsisr = svcpu->fault_dsisr;
                 vcpu->stat.pf_storage++;
 
 #ifdef CONFIG_PPC_BOOK3S_32
                 /* We set segments as unused segments when invalidating them. So
                  * treat the respective fault as segment fault. */
-                if ((to_svcpu(vcpu)->sr[dar >> SID_SHIFT]) == SR_INVALID) {
+                if ((svcpu->sr[dar >> SID_SHIFT]) == SR_INVALID) {
                         kvmppc_mmu_map_segment(vcpu, dar);
                         r = RESUME_GUEST;
+                        svcpu_put(svcpu);
                         break;
                 }
 #endif
+                svcpu_put(svcpu);
 
                 /* The only case we need to handle is missing shadow PTEs */
-                if (to_svcpu(vcpu)->fault_dsisr & DSISR_NOHPTE) {
+                if (fault_dsisr & DSISR_NOHPTE) {
                         r = kvmppc_handle_pagefault(run, vcpu, dar, exit_nr);
                 } else {
                         vcpu->arch.shared->dar = dar;
-                        vcpu->arch.shared->dsisr = to_svcpu(vcpu)->fault_dsisr;
+                        vcpu->arch.shared->dsisr = fault_dsisr;
                         kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
                         r = RESUME_GUEST;
                 }
@@ -609,10 +629,13 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
         case BOOK3S_INTERRUPT_PROGRAM:
         {
                 enum emulation_result er;
+                struct kvmppc_book3s_shadow_vcpu *svcpu;
                 ulong flags;
 
 program_interrupt:
-                flags = to_svcpu(vcpu)->shadow_srr1 & 0x1f0000ull;
+                svcpu = svcpu_get(vcpu);
+                flags = svcpu->shadow_srr1 & 0x1f0000ull;
+                svcpu_put(svcpu);
 
                 if (vcpu->arch.shared->msr & MSR_PR) {
 #ifdef EXIT_DEBUG
@@ -740,20 +763,33 @@ program_interrupt:
                 r = RESUME_GUEST;
                 break;
         default:
+        {
+                struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+                ulong shadow_srr1 = svcpu->shadow_srr1;
+                svcpu_put(svcpu);
                 /* Ugh - bork here! What did we get? */
                 printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n",
-                        exit_nr, kvmppc_get_pc(vcpu), to_svcpu(vcpu)->shadow_srr1);
+                        exit_nr, kvmppc_get_pc(vcpu), shadow_srr1);
                 r = RESUME_HOST;
                 BUG();
                 break;
         }
-
+        }
 
         if (!(r & RESUME_HOST)) {
                 /* To avoid clobbering exit_reason, only check for signals if
                  * we aren't already exiting to userspace for some other
                  * reason. */
+
+                /*
+                 * Interrupts could be timers for the guest which we have to
+                 * inject again, so let's postpone them until we're in the guest
+                 * and if we really did time things so badly, then we just exit
+                 * again due to a host external interrupt.
+                 */
+                __hard_irq_disable();
                 if (signal_pending(current)) {
+                        __hard_irq_enable();
 #ifdef EXIT_DEBUG
                         printk(KERN_EMERG "KVM: Going back to host\n");
 #endif
@@ -761,10 +797,12 @@ program_interrupt:
                         run->exit_reason = KVM_EXIT_INTR;
                         r = -EINTR;
                 } else {
+                        preempt_disable();
+
                         /* In case an interrupt came in that was triggered
                          * from userspace (like DEC), we need to check what
                          * to inject now! */
-                        kvmppc_core_deliver_interrupts(vcpu);
+                        kvmppc_core_prepare_to_enter(vcpu);
                 }
         }
 
@@ -836,6 +874,38 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         return 0;
 }
 
+int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        int r = -EINVAL;
+
+        switch (reg->id) {
+        case KVM_REG_PPC_HIOR:
+                r = put_user(to_book3s(vcpu)->hior, (u64 __user *)reg->addr);
+                break;
+        default:
+                break;
+        }
+
+        return r;
+}
+
+int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        int r = -EINVAL;
+
+        switch (reg->id) {
+        case KVM_REG_PPC_HIOR:
+                r = get_user(to_book3s(vcpu)->hior, (u64 __user *)reg->addr);
+                if (!r)
+                        to_book3s(vcpu)->hior_explicit = true;
+                break;
+        default:
+                break;
+        }
+
+        return r;
+}
+
 int kvmppc_core_check_processor_compat(void)
 {
         return 0;
@@ -923,16 +993,31 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 #endif
         ulong ext_msr;
 
+        preempt_disable();
+
         /* Check if we can run the vcpu at all */
         if (!vcpu->arch.sane) {
                 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
-                return -EINVAL;
+                ret = -EINVAL;
+                goto out;
         }
 
+        kvmppc_core_prepare_to_enter(vcpu);
+
+        /*
+         * Interrupts could be timers for the guest which we have to inject
+         * again, so let's postpone them until we're in the guest and if we
+         * really did time things so badly, then we just exit again due to
+         * a host external interrupt.
+         */
+        __hard_irq_disable();
+
         /* No need to go into the guest when all we do is going out */
         if (signal_pending(current)) {
+                __hard_irq_enable();
                 kvm_run->exit_reason = KVM_EXIT_INTR;
-                return -EINTR;
+                ret = -EINTR;
+                goto out;
         }
 
         /* Save FPU state in stack */
@@ -974,8 +1059,6 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 
         kvm_guest_exit();
 
-        local_irq_disable();
-
         current->thread.regs->msr = ext_msr;
 
         /* Make sure we save the guest FPU/Altivec/VSX state */
@@ -1002,9 +1085,50 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         current->thread.used_vsr = used_vsr;
 #endif
 
+out:
+        preempt_enable();
         return ret;
 }
 
+/*
+ * Get (and clear) the dirty memory log for a memory slot.
+ */
+int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
+                                      struct kvm_dirty_log *log)
+{
+        struct kvm_memory_slot *memslot;
+        struct kvm_vcpu *vcpu;
+        ulong ga, ga_end;
+        int is_dirty = 0;
+        int r;
+        unsigned long n;
+
+        mutex_lock(&kvm->slots_lock);
+
+        r = kvm_get_dirty_log(kvm, log, &is_dirty);
+        if (r)
+                goto out;
+
+        /* If nothing is dirty, don't bother messing with page tables. */
+        if (is_dirty) {
+                memslot = id_to_memslot(kvm->memslots, log->slot);
+
+                ga = memslot->base_gfn << PAGE_SHIFT;
+                ga_end = ga + (memslot->npages << PAGE_SHIFT);
+
+                kvm_for_each_vcpu(n, vcpu, kvm)
+                        kvmppc_mmu_pte_pflush(vcpu, ga, ga_end);
+
+                n = kvm_dirty_bitmap_bytes(memslot);
+                memset(memslot->dirty_bitmap, 0, n);
+        }
+
+        r = 0;
+out:
+        mutex_unlock(&kvm->slots_lock);
+        return r;
+}
+
 int kvmppc_core_prepare_memory_region(struct kvm *kvm,
                                       struct kvm_userspace_memory_region *mem)
 {
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index bb6c988f010..ee9e1ee9c85 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -124,12 +124,6 @@ void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
         vcpu->arch.shared->msr = new_msr;
 
         kvmppc_mmu_msr_notify(vcpu, old_msr);
-
-        if (vcpu->arch.shared->msr & MSR_WE) {
-                kvm_vcpu_block(vcpu);
-                kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
-        };
-
         kvmppc_vcpu_sync_spe(vcpu);
 }
 
@@ -258,9 +252,11 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
                 allowed = vcpu->arch.shared->msr & MSR_ME;
                 msr_mask = 0;
                 break;
-        case BOOKE_IRQPRIO_EXTERNAL:
         case BOOKE_IRQPRIO_DECREMENTER:
         case BOOKE_IRQPRIO_FIT:
+                keep_irq = true;
+                /* fall through */
+        case BOOKE_IRQPRIO_EXTERNAL:
                 allowed = vcpu->arch.shared->msr & MSR_EE;
                 allowed = allowed && !crit;
                 msr_mask = MSR_CE|MSR_ME|MSR_DE;
@@ -276,7 +272,7 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
                 vcpu->arch.shared->srr1 = vcpu->arch.shared->msr;
                 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
                 if (update_esr == true)
-                        vcpu->arch.esr = vcpu->arch.queued_esr;
+                        vcpu->arch.shared->esr = vcpu->arch.queued_esr;
                 if (update_dear == true)
                         vcpu->arch.shared->dar = vcpu->arch.queued_dear;
                 kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask);
@@ -288,13 +284,26 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
         return allowed;
 }
 
-/* Check pending exceptions and deliver one, if possible. */
-void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu)
+static void update_timer_ints(struct kvm_vcpu *vcpu)
+{
+        if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
+                kvmppc_core_queue_dec(vcpu);
+        else
+                kvmppc_core_dequeue_dec(vcpu);
+}
+
+static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
 {
         unsigned long *pending = &vcpu->arch.pending_exceptions;
-        unsigned long old_pending = vcpu->arch.pending_exceptions;
         unsigned int priority;
 
+        if (vcpu->requests) {
+                if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu)) {
+                        smp_mb();
+                        update_timer_ints(vcpu);
+                }
+        }
+
         priority = __ffs(*pending);
         while (priority <= BOOKE_IRQPRIO_MAX) {
                 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
@@ -306,10 +315,24 @@ void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu)
         }
 
         /* Tell the guest about our interrupt status */
-        if (*pending)
-                vcpu->arch.shared->int_pending = 1;
-        else if (old_pending)
-                vcpu->arch.shared->int_pending = 0;
+        vcpu->arch.shared->int_pending = !!*pending;
+}
+
+/* Check pending exceptions and deliver one, if possible. */
+void kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
+{
+        WARN_ON_ONCE(!irqs_disabled());
+
+        kvmppc_core_check_exceptions(vcpu);
+
+        if (vcpu->arch.shared->msr & MSR_WE) {
+                local_irq_enable();
+                kvm_vcpu_block(vcpu);
+                local_irq_disable();
+
+                kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
+                kvmppc_core_check_exceptions(vcpu);
+        };
 }
 
 int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
@@ -322,11 +345,21 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         }
 
         local_irq_disable();
+
+        kvmppc_core_prepare_to_enter(vcpu);
+
+        if (signal_pending(current)) {
+                kvm_run->exit_reason = KVM_EXIT_INTR;
+                ret = -EINTR;
+                goto out;
+        }
+
         kvm_guest_enter();
         ret = __kvmppc_vcpu_run(kvm_run, vcpu);
         kvm_guest_exit();
-        local_irq_enable();
 
+out:
+        local_irq_enable();
         return ret;
 }
 
@@ -603,7 +636,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
         local_irq_disable();
 
-        kvmppc_core_deliver_interrupts(vcpu);
+        kvmppc_core_prepare_to_enter(vcpu);
 
         if (!(r & RESUME_HOST)) {
                 /* To avoid clobbering exit_reason, only check for signals if
@@ -628,6 +661,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
         vcpu->arch.pc = 0;
         vcpu->arch.shared->msr = 0;
         vcpu->arch.shadow_msr = MSR_USER | MSR_DE | MSR_IS | MSR_DS;
+        vcpu->arch.shared->pir = vcpu->vcpu_id;
         kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
 
         vcpu->arch.shadow_pid = 1;
@@ -662,10 +696,10 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         regs->sprg1 = vcpu->arch.shared->sprg1;
         regs->sprg2 = vcpu->arch.shared->sprg2;
         regs->sprg3 = vcpu->arch.shared->sprg3;
-        regs->sprg4 = vcpu->arch.sprg4;
-        regs->sprg5 = vcpu->arch.sprg5;
-        regs->sprg6 = vcpu->arch.sprg6;
-        regs->sprg7 = vcpu->arch.sprg7;
+        regs->sprg4 = vcpu->arch.shared->sprg4;
+        regs->sprg5 = vcpu->arch.shared->sprg5;
+        regs->sprg6 = vcpu->arch.shared->sprg6;
+        regs->sprg7 = vcpu->arch.shared->sprg7;
 
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
@@ -690,10 +724,10 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         vcpu->arch.shared->sprg1 = regs->sprg1;
         vcpu->arch.shared->sprg2 = regs->sprg2;
         vcpu->arch.shared->sprg3 = regs->sprg3;
-        vcpu->arch.sprg4 = regs->sprg4;
-        vcpu->arch.sprg5 = regs->sprg5;
-        vcpu->arch.sprg6 = regs->sprg6;
-        vcpu->arch.sprg7 = regs->sprg7;
+        vcpu->arch.shared->sprg4 = regs->sprg4;
+        vcpu->arch.shared->sprg5 = regs->sprg5;
+        vcpu->arch.shared->sprg6 = regs->sprg6;
+        vcpu->arch.shared->sprg7 = regs->sprg7;
 
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
@@ -711,7 +745,7 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
         sregs->u.e.csrr0 = vcpu->arch.csrr0;
         sregs->u.e.csrr1 = vcpu->arch.csrr1;
         sregs->u.e.mcsr = vcpu->arch.mcsr;
-        sregs->u.e.esr = vcpu->arch.esr;
+        sregs->u.e.esr = vcpu->arch.shared->esr;
         sregs->u.e.dear = vcpu->arch.shared->dar;
         sregs->u.e.tsr = vcpu->arch.tsr;
         sregs->u.e.tcr = vcpu->arch.tcr;
@@ -729,28 +763,19 @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
         vcpu->arch.csrr0 = sregs->u.e.csrr0;
         vcpu->arch.csrr1 = sregs->u.e.csrr1;
         vcpu->arch.mcsr = sregs->u.e.mcsr;
-        vcpu->arch.esr = sregs->u.e.esr;
+        vcpu->arch.shared->esr = sregs->u.e.esr;
         vcpu->arch.shared->dar = sregs->u.e.dear;
         vcpu->arch.vrsave = sregs->u.e.vrsave;
-        vcpu->arch.tcr = sregs->u.e.tcr;
+        kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
 
-        if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC)
+        if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
                 vcpu->arch.dec = sregs->u.e.dec;
-
-        kvmppc_emulate_dec(vcpu);
+                kvmppc_emulate_dec(vcpu);
+        }
 
         if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) {
-                /*
-                 * FIXME: existing KVM timer handling is incomplete.
-                 * TSR cannot be read by the guest, and its value in
-                 * vcpu->arch is always zero.  For now, just handle
-                 * the case where the caller is trying to inject a
-                 * decrementer interrupt.
-                 */
-
-                if ((sregs->u.e.tsr & TSR_DIS) &&
-                    (vcpu->arch.tcr & TCR_DIE))
-                        kvmppc_core_queue_dec(vcpu);
+                vcpu->arch.tsr = sregs->u.e.tsr;
+                update_timer_ints(vcpu);
         }
 
         return 0;
@@ -761,7 +786,7 @@ static void get_sregs_arch206(struct kvm_vcpu *vcpu,
 {
         sregs->u.e.features |= KVM_SREGS_E_ARCH206;
 
-        sregs->u.e.pir = 0;
+        sregs->u.e.pir = vcpu->vcpu_id;
         sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
         sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
         sregs->u.e.decar = vcpu->arch.decar;
@@ -774,7 +799,7 @@ static int set_sregs_arch206(struct kvm_vcpu *vcpu,
         if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
                 return 0;
 
-        if (sregs->u.e.pir != 0)
+        if (sregs->u.e.pir != vcpu->vcpu_id)
                 return -EINVAL;
 
         vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
@@ -862,6 +887,16 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         return kvmppc_core_set_sregs(vcpu, sregs);
 }
 
+int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        return -EINVAL;
+}
+
+int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
+{
+        return -EINVAL;
+}
+
 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
         return -ENOTSUPP;
@@ -906,6 +941,33 @@ void kvmppc_core_destroy_vm(struct kvm *kvm)
 {
 }
 
+void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
+{
+        vcpu->arch.tcr = new_tcr;
+        update_timer_ints(vcpu);
+}
+
+void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
+{
+        set_bits(tsr_bits, &vcpu->arch.tsr);
+        smp_wmb();
+        kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
+        kvm_vcpu_kick(vcpu);
+}
+
+void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
+{
+        clear_bits(tsr_bits, &vcpu->arch.tsr);
+        update_timer_ints(vcpu);
+}
+
+void kvmppc_decrementer_func(unsigned long data)
+{
+        struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
+
+        kvmppc_set_tsr_bits(vcpu, TSR_DIS);
+}
+
 int __init kvmppc_booke_init(void)
 {
         unsigned long ivor[16];
diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
index 8e1fe33d64e..2fe202705a3 100644
--- a/arch/powerpc/kvm/booke.h
+++ b/arch/powerpc/kvm/booke.h
@@ -55,6 +55,10 @@ extern unsigned long kvmppc_booke_handlers;
 void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr);
 void kvmppc_mmu_msr_notify(struct kvm_vcpu *vcpu, u32 old_msr);
 
+void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr);
+void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits);
+void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits);
+
 int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                             unsigned int inst, int *advance);
 int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt);
diff --git a/arch/powerpc/kvm/booke_emulate.c b/arch/powerpc/kvm/booke_emulate.c
index 1260f5f24c0..3e652da3653 100644
--- a/arch/powerpc/kvm/booke_emulate.c
+++ b/arch/powerpc/kvm/booke_emulate.c
@@ -13,6 +13,7 @@
  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
  * Copyright IBM Corp. 2008
+ * Copyright 2011 Freescale Semiconductor, Inc.
  *
  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  */
@@ -107,7 +108,7 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
         case SPRN_DEAR:
                 vcpu->arch.shared->dar = spr_val; break;
         case SPRN_ESR:
-                vcpu->arch.esr = spr_val; break;
+                vcpu->arch.shared->esr = spr_val; break;
         case SPRN_DBCR0:
                 vcpu->arch.dbcr0 = spr_val; break;
         case SPRN_DBCR1:
@@ -115,23 +116,23 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
         case SPRN_DBSR:
                 vcpu->arch.dbsr &= ~spr_val; break;
         case SPRN_TSR:
-                vcpu->arch.tsr &= ~spr_val; break;
+                kvmppc_clr_tsr_bits(vcpu, spr_val);
+                break;
         case SPRN_TCR:
-                vcpu->arch.tcr = spr_val;
-                kvmppc_emulate_dec(vcpu);
+                kvmppc_set_tcr(vcpu, spr_val);
                 break;
 
         /* Note: SPRG4-7 are user-readable. These values are
          * loaded into the real SPRGs when resuming the
          * guest. */
         case SPRN_SPRG4:
-                vcpu->arch.sprg4 = spr_val; break;
+                vcpu->arch.shared->sprg4 = spr_val; break;
         case SPRN_SPRG5:
-                vcpu->arch.sprg5 = spr_val; break;
+                vcpu->arch.shared->sprg5 = spr_val; break;
         case SPRN_SPRG6:
-                vcpu->arch.sprg6 = spr_val; break;
+                vcpu->arch.shared->sprg6 = spr_val; break;
         case SPRN_SPRG7:
-                vcpu->arch.sprg7 = spr_val; break;
+                vcpu->arch.shared->sprg7 = spr_val; break;
 
         case SPRN_IVPR:
                 vcpu->arch.ivpr = spr_val;
@@ -202,13 +203,17 @@ int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
         case SPRN_DEAR:
                 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->dar); break;
         case SPRN_ESR:
-                kvmppc_set_gpr(vcpu, rt, vcpu->arch.esr); break;
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->esr); break;
         case SPRN_DBCR0:
                 kvmppc_set_gpr(vcpu, rt, vcpu->arch.dbcr0); break;
         case SPRN_DBCR1:
                 kvmppc_set_gpr(vcpu, rt, vcpu->arch.dbcr1); break;
         case SPRN_DBSR:
                 kvmppc_set_gpr(vcpu, rt, vcpu->arch.dbsr); break;
+        case SPRN_TSR:
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.tsr); break;
+        case SPRN_TCR:
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.tcr); break;
 
         case SPRN_IVOR0:
                 kvmppc_set_gpr(vcpu, rt, vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]);
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S
index 42f2fb1f66e..10d8ef602e5 100644
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@ -402,19 +402,25 @@ lightweight_exit:
         /* Save vcpu pointer for the exception handlers. */
         mtspr   SPRN_SPRG_WVCPU, r4
 
+        lwz     r5, VCPU_SHARED(r4)
+
         /* Can't switch the stack pointer until after IVPR is switched,
          * because host interrupt handlers would get confused. */
         lwz     r1, VCPU_GPR(r1)(r4)
 
-        /* Host interrupt handlers may have clobbered these guest-readable
-         * SPRGs, so we need to reload them here with the guest's values. */
-        lwz     r3, VCPU_SPRG4(r4)
+        /*
+         * Host interrupt handlers may have clobbered these
+         * guest-readable SPRGs, or the guest kernel may have
+         * written directly to the shared area, so we
+         * need to reload them here with the guest's values.
+         */
+        lwz     r3, VCPU_SHARED_SPRG4(r5)
         mtspr   SPRN_SPRG4W, r3
-        lwz     r3, VCPU_SPRG5(r4)
+        lwz     r3, VCPU_SHARED_SPRG5(r5)
         mtspr   SPRN_SPRG5W, r3
-        lwz     r3, VCPU_SPRG6(r4)
+        lwz     r3, VCPU_SHARED_SPRG6(r5)
         mtspr   SPRN_SPRG6W, r3
-        lwz     r3, VCPU_SPRG7(r4)
+        lwz     r3, VCPU_SHARED_SPRG7(r5)
         mtspr   SPRN_SPRG7W, r3
 
 #ifdef CONFIG_KVM_EXIT_TIMING
diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index 8c0d45a6faf..ddcd896fa2f 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -71,9 +71,6 @@ int kvmppc_core_vcpu_setup(struct kvm_vcpu *vcpu)
         vcpu->arch.pvr = mfspr(SPRN_PVR);
         vcpu_e500->svr = mfspr(SPRN_SVR);
 
-        /* Since booke kvm only support one core, update all vcpus' PIR to 0 */
-        vcpu->vcpu_id = 0;
-
         vcpu->arch.cpu_type = KVM_CPU_E500V2;
 
         return 0;
@@ -118,12 +115,12 @@ void kvmppc_core_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
         sregs->u.e.impl.fsl.hid0 = vcpu_e500->hid0;
         sregs->u.e.impl.fsl.mcar = vcpu_e500->mcar;
 
-        sregs->u.e.mas0 = vcpu_e500->mas0;
-        sregs->u.e.mas1 = vcpu_e500->mas1;
-        sregs->u.e.mas2 = vcpu_e500->mas2;
-        sregs->u.e.mas7_3 = ((u64)vcpu_e500->mas7 << 32) | vcpu_e500->mas3;
-        sregs->u.e.mas4 = vcpu_e500->mas4;
-        sregs->u.e.mas6 = vcpu_e500->mas6;
+        sregs->u.e.mas0 = vcpu->arch.shared->mas0;
+        sregs->u.e.mas1 = vcpu->arch.shared->mas1;
+        sregs->u.e.mas2 = vcpu->arch.shared->mas2;
+        sregs->u.e.mas7_3 = vcpu->arch.shared->mas7_3;
+        sregs->u.e.mas4 = vcpu->arch.shared->mas4;
+        sregs->u.e.mas6 = vcpu->arch.shared->mas6;
 
         sregs->u.e.mmucfg = mfspr(SPRN_MMUCFG);
         sregs->u.e.tlbcfg[0] = vcpu_e500->tlb0cfg;
@@ -151,13 +148,12 @@ int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
         }
 
         if (sregs->u.e.features & KVM_SREGS_E_ARCH206_MMU) {
-                vcpu_e500->mas0 = sregs->u.e.mas0;
-                vcpu_e500->mas1 = sregs->u.e.mas1;
-                vcpu_e500->mas2 = sregs->u.e.mas2;
-                vcpu_e500->mas7 = sregs->u.e.mas7_3 >> 32;
-                vcpu_e500->mas3 = (u32)sregs->u.e.mas7_3;
-                vcpu_e500->mas4 = sregs->u.e.mas4;
-                vcpu_e500->mas6 = sregs->u.e.mas6;
+                vcpu->arch.shared->mas0 = sregs->u.e.mas0;
+                vcpu->arch.shared->mas1 = sregs->u.e.mas1;
+                vcpu->arch.shared->mas2 = sregs->u.e.mas2;
+                vcpu->arch.shared->mas7_3 = sregs->u.e.mas7_3;
+                vcpu->arch.shared->mas4 = sregs->u.e.mas4;
+                vcpu->arch.shared->mas6 = sregs->u.e.mas6;
         }
 
         if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
@@ -233,6 +229,10 @@ static int __init kvmppc_e500_init(void)
         unsigned long ivor[3];
         unsigned long max_ivor = 0;
 
+        r = kvmppc_core_check_processor_compat();
+        if (r)
+                return r;
+
         r = kvmppc_booke_init();
         if (r)
                 return r;
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index d48ae396f41..6d0b2bd54fb 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -89,19 +89,23 @@ int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
                         return EMULATE_FAIL;
                 vcpu_e500->pid[2] = spr_val; break;
         case SPRN_MAS0:
-                vcpu_e500->mas0 = spr_val; break;
+                vcpu->arch.shared->mas0 = spr_val; break;
         case SPRN_MAS1:
-                vcpu_e500->mas1 = spr_val; break;
+                vcpu->arch.shared->mas1 = spr_val; break;
         case SPRN_MAS2:
-                vcpu_e500->mas2 = spr_val; break;
+                vcpu->arch.shared->mas2 = spr_val; break;
         case SPRN_MAS3:
-                vcpu_e500->mas3 = spr_val; break;
+                vcpu->arch.shared->mas7_3 &= ~(u64)0xffffffff;
+                vcpu->arch.shared->mas7_3 |= spr_val;
+                break;
         case SPRN_MAS4:
-                vcpu_e500->mas4 = spr_val; break;
+                vcpu->arch.shared->mas4 = spr_val; break;
         case SPRN_MAS6:
-                vcpu_e500->mas6 = spr_val; break;
+                vcpu->arch.shared->mas6 = spr_val; break;
         case SPRN_MAS7:
-                vcpu_e500->mas7 = spr_val; break;
+                vcpu->arch.shared->mas7_3 &= (u64)0xffffffff;
+                vcpu->arch.shared->mas7_3 |= (u64)spr_val << 32;
+                break;
         case SPRN_L1CSR0:
                 vcpu_e500->l1csr0 = spr_val;
                 vcpu_e500->l1csr0 &= ~(L1CSR0_DCFI | L1CSR0_CLFC);
@@ -143,6 +147,7 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
         int emulated = EMULATE_DONE;
+        unsigned long val;
 
         switch (sprn) {
         case SPRN_PID:
@@ -152,20 +157,23 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
         case SPRN_PID2:
                 kvmppc_set_gpr(vcpu, rt, vcpu_e500->pid[2]); break;
         case SPRN_MAS0:
-                kvmppc_set_gpr(vcpu, rt, vcpu_e500->mas0); break;
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas0); break;
         case SPRN_MAS1:
-                kvmppc_set_gpr(vcpu, rt, vcpu_e500->mas1); break;
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas1); break;
         case SPRN_MAS2:
-                kvmppc_set_gpr(vcpu, rt, vcpu_e500->mas2); break;
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas2); break;
         case SPRN_MAS3:
-                kvmppc_set_gpr(vcpu, rt, vcpu_e500->mas3); break;
+                val = (u32)vcpu->arch.shared->mas7_3;
+                kvmppc_set_gpr(vcpu, rt, val);
+                break;
         case SPRN_MAS4:
-                kvmppc_set_gpr(vcpu, rt, vcpu_e500->mas4); break;
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas4); break;
         case SPRN_MAS6:
-                kvmppc_set_gpr(vcpu, rt, vcpu_e500->mas6); break;
+                kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas6); break;
         case SPRN_MAS7:
-                kvmppc_set_gpr(vcpu, rt, vcpu_e500->mas7); break;
-
+                val = vcpu->arch.shared->mas7_3 >> 32;
+                kvmppc_set_gpr(vcpu, rt, val);
+                break;
         case SPRN_TLB0CFG:
                 kvmppc_set_gpr(vcpu, rt, vcpu_e500->tlb0cfg); break;
         case SPRN_TLB1CFG:
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index 13c432ea2fa..6e53e4164de 100644
--- a/arch/powerpc/kvm/e500_tlb.c
+++ b/arch/powerpc/kvm/e500_tlb.c
@@ -12,12 +12,19 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
 #include <linux/highmem.h>
+#include <linux/log2.h>
+#include <linux/uaccess.h>
+#include <linux/sched.h>
+#include <linux/rwsem.h>
+#include <linux/vmalloc.h>
+#include <linux/hugetlb.h>
 #include <asm/kvm_ppc.h>
 #include <asm/kvm_e500.h>
 
@@ -26,7 +33,7 @@
 #include "trace.h"
 #include "timing.h"
 
-#define to_htlb1_esel(esel) (tlb1_entry_num - (esel) - 1)
+#define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1)
 
 struct id {
         unsigned long val;
@@ -63,7 +70,14 @@ static DEFINE_PER_CPU(struct pcpu_id_table, pcpu_sids);
  * The valid range of shadow ID is [1..255] */
 static DEFINE_PER_CPU(unsigned long, pcpu_last_used_sid);
 
-static unsigned int tlb1_entry_num;
+static struct kvmppc_e500_tlb_params host_tlb_params[E500_TLB_NUM];
+
+static struct kvm_book3e_206_tlb_entry *get_entry(
+        struct kvmppc_vcpu_e500 *vcpu_e500, int tlbsel, int entry)
+{
+        int offset = vcpu_e500->gtlb_offset[tlbsel];
+        return &vcpu_e500->gtlb_arch[offset + entry];
+}
 
 /*
  * Allocate a free shadow id and setup a valid sid mapping in given entry.
@@ -116,13 +130,11 @@ static inline int local_sid_lookup(struct id *entry)
         return -1;
 }
 
-/* Invalidate all id mappings on local core */
+/* Invalidate all id mappings on local core -- call with preempt disabled */
 static inline void local_sid_destroy_all(void)
 {
-        preempt_disable();
         __get_cpu_var(pcpu_last_used_sid) = 0;
         memset(&__get_cpu_var(pcpu_sids), 0, sizeof(__get_cpu_var(pcpu_sids)));
-        preempt_enable();
 }
 
 static void *kvmppc_e500_id_table_alloc(struct kvmppc_vcpu_e500 *vcpu_e500)
@@ -218,34 +230,13 @@ void kvmppc_e500_recalc_shadow_pid(struct kvmppc_vcpu_e500 *vcpu_e500)
         preempt_enable();
 }
 
-void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
-{
-        struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
-        struct tlbe *tlbe;
-        int i, tlbsel;
-
-        printk("| %8s | %8s | %8s | %8s | %8s |\n",
-                        "nr", "mas1", "mas2", "mas3", "mas7");
-
-        for (tlbsel = 0; tlbsel < 2; tlbsel++) {
-                printk("Guest TLB%d:\n", tlbsel);
-                for (i = 0; i < vcpu_e500->gtlb_size[tlbsel]; i++) {
-                        tlbe = &vcpu_e500->gtlb_arch[tlbsel][i];
-                        if (tlbe->mas1 & MAS1_VALID)
-                                printk(" G[%d][%3d] |  %08X | %08X | %08X | %08X |\n",
-                                        tlbsel, i, tlbe->mas1, tlbe->mas2,
-                                        tlbe->mas3, tlbe->mas7);
-                }
-        }
-}
-
-static inline unsigned int tlb0_get_next_victim(
+static inline unsigned int gtlb0_get_next_victim(
                 struct kvmppc_vcpu_e500 *vcpu_e500)
 {
         unsigned int victim;
 
         victim = vcpu_e500->gtlb_nv[0]++;
-        if (unlikely(vcpu_e500->gtlb_nv[0] >= KVM_E500_TLB0_WAY_NUM))
+        if (unlikely(vcpu_e500->gtlb_nv[0] >= vcpu_e500->gtlb_params[0].ways))
                 vcpu_e500->gtlb_nv[0] = 0;
 
         return victim;
@@ -254,12 +245,12 @@ static inline unsigned int tlb0_get_next_victim(
 static inline unsigned int tlb1_max_shadow_size(void)
 {
         /* reserve one entry for magic page */
-        return tlb1_entry_num - tlbcam_index - 1;
+        return host_tlb_params[1].entries - tlbcam_index - 1;
 }
 
-static inline int tlbe_is_writable(struct tlbe *tlbe)
+static inline int tlbe_is_writable(struct kvm_book3e_206_tlb_entry *tlbe)
 {
-        return tlbe->mas3 & (MAS3_SW|MAS3_UW);
+        return tlbe->mas7_3 & (MAS3_SW|MAS3_UW);
 }
 
 static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode)
@@ -290,40 +281,66 @@ static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode)
 /*
  * writing shadow tlb entry to host TLB
  */
-static inline void __write_host_tlbe(struct tlbe *stlbe, uint32_t mas0)
+static inline void __write_host_tlbe(struct kvm_book3e_206_tlb_entry *stlbe,
+                                     uint32_t mas0)
 {
         unsigned long flags;
 
         local_irq_save(flags);
         mtspr(SPRN_MAS0, mas0);
         mtspr(SPRN_MAS1, stlbe->mas1);
-        mtspr(SPRN_MAS2, stlbe->mas2);
-        mtspr(SPRN_MAS3, stlbe->mas3);
-        mtspr(SPRN_MAS7, stlbe->mas7);
+        mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2);
+        mtspr(SPRN_MAS3, (u32)stlbe->mas7_3);
+        mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32));
         asm volatile("isync; tlbwe" : : : "memory");
         local_irq_restore(flags);
+
+        trace_kvm_booke206_stlb_write(mas0, stlbe->mas8, stlbe->mas1,
+                                      stlbe->mas2, stlbe->mas7_3);
+}
+
+/*
+ * Acquire a mas0 with victim hint, as if we just took a TLB miss.
+ *
+ * We don't care about the address we're searching for, other than that it's
+ * in the right set and is not present in the TLB.  Using a zero PID and a
+ * userspace address means we don't have to set and then restore MAS5, or
+ * calculate a proper MAS6 value.
+ */
+static u32 get_host_mas0(unsigned long eaddr)
+{
+        unsigned long flags;
+        u32 mas0;
+
+        local_irq_save(flags);
+        mtspr(SPRN_MAS6, 0);
+        asm volatile("tlbsx 0, %0" : : "b" (eaddr & ~CONFIG_PAGE_OFFSET));
+        mas0 = mfspr(SPRN_MAS0);
+        local_irq_restore(flags);
+
+        return mas0;
 }
 
+/* sesel is for tlb1 only */
 static inline void write_host_tlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
-                int tlbsel, int esel, struct tlbe *stlbe)
+                int tlbsel, int sesel, struct kvm_book3e_206_tlb_entry *stlbe)
 {
+        u32 mas0;
+
         if (tlbsel == 0) {
-                __write_host_tlbe(stlbe,
-                                  MAS0_TLBSEL(0) |
-                                  MAS0_ESEL(esel & (KVM_E500_TLB0_WAY_NUM - 1)));
+                mas0 = get_host_mas0(stlbe->mas2);
+                __write_host_tlbe(stlbe, mas0);
         } else {
                 __write_host_tlbe(stlbe,
                                   MAS0_TLBSEL(1) |
-                                  MAS0_ESEL(to_htlb1_esel(esel)));
+                                  MAS0_ESEL(to_htlb1_esel(sesel)));
         }
-        trace_kvm_stlb_write(index_of(tlbsel, esel), stlbe->mas1, stlbe->mas2,
-                             stlbe->mas3, stlbe->mas7);
 }
 
 void kvmppc_map_magic(struct kvm_vcpu *vcpu)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
-        struct tlbe magic;
+        struct kvm_book3e_206_tlb_entry magic;
         ulong shared_page = ((ulong)vcpu->arch.shared) & PAGE_MASK;
         unsigned int stid;
         pfn_t pfn;
@@ -337,9 +354,9 @@ void kvmppc_map_magic(struct kvm_vcpu *vcpu)
         magic.mas1 = MAS1_VALID | MAS1_TS | MAS1_TID(stid) |
                      MAS1_TSIZE(BOOK3E_PAGESZ_4K);
         magic.mas2 = vcpu->arch.magic_page_ea | MAS2_M;
-        magic.mas3 = (pfn << PAGE_SHIFT) |
-                     MAS3_SW | MAS3_SR | MAS3_UW | MAS3_UR;
-        magic.mas7 = pfn >> (32 - PAGE_SHIFT);
+        magic.mas7_3 = ((u64)pfn << PAGE_SHIFT) |
+                       MAS3_SW | MAS3_SR | MAS3_UW | MAS3_UR;
+        magic.mas8 = 0;
 
         __write_host_tlbe(&magic, MAS0_TLBSEL(1) | MAS0_ESEL(tlbcam_index));
         preempt_enable();
@@ -357,10 +374,11 @@ void kvmppc_e500_tlb_put(struct kvm_vcpu *vcpu)
 {
 }
 
-static void kvmppc_e500_stlbe_invalidate(struct kvmppc_vcpu_e500 *vcpu_e500,
-                                         int tlbsel, int esel)
+static void inval_gtlbe_on_host(struct kvmppc_vcpu_e500 *vcpu_e500,
+                                int tlbsel, int esel)
 {
-        struct tlbe *gtlbe = &vcpu_e500->gtlb_arch[tlbsel][esel];
+        struct kvm_book3e_206_tlb_entry *gtlbe =
+                get_entry(vcpu_e500, tlbsel, esel);
         struct vcpu_id_table *idt = vcpu_e500->idt;
         unsigned int pr, tid, ts, pid;
         u32 val, eaddr;
@@ -414,25 +432,57 @@ static void kvmppc_e500_stlbe_invalidate(struct kvmppc_vcpu_e500 *vcpu_e500,
         preempt_enable();
 }
 
+static int tlb0_set_base(gva_t addr, int sets, int ways)
+{
+        int set_base;
+
+        set_base = (addr >> PAGE_SHIFT) & (sets - 1);
+        set_base *= ways;
+
+        return set_base;
+}
+
+static int gtlb0_set_base(struct kvmppc_vcpu_e500 *vcpu_e500, gva_t addr)
+{
+        return tlb0_set_base(addr, vcpu_e500->gtlb_params[0].sets,
+                             vcpu_e500->gtlb_params[0].ways);
+}
+
+static unsigned int get_tlb_esel(struct kvm_vcpu *vcpu, int tlbsel)
+{
+        struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
+        int esel = get_tlb_esel_bit(vcpu);
+
+        if (tlbsel == 0) {
+                esel &= vcpu_e500->gtlb_params[0].ways - 1;
+                esel += gtlb0_set_base(vcpu_e500, vcpu->arch.shared->mas2);
+        } else {
+                esel &= vcpu_e500->gtlb_params[tlbsel].entries - 1;
+        }
+
+        return esel;
+}
+
 /* Search the guest TLB for a matching entry. */
 static int kvmppc_e500_tlb_index(struct kvmppc_vcpu_e500 *vcpu_e500,
                 gva_t eaddr, int tlbsel, unsigned int pid, int as)
 {
-        int size = vcpu_e500->gtlb_size[tlbsel];
-        int set_base;
+        int size = vcpu_e500->gtlb_params[tlbsel].entries;
+        unsigned int set_base, offset;
         int i;
 
         if (tlbsel == 0) {
-                int mask = size / KVM_E500_TLB0_WAY_NUM - 1;
-                set_base = (eaddr >> PAGE_SHIFT) & mask;
-                set_base *= KVM_E500_TLB0_WAY_NUM;
-                size = KVM_E500_TLB0_WAY_NUM;
+                set_base = gtlb0_set_base(vcpu_e500, eaddr);
+                size = vcpu_e500->gtlb_params[0].ways;
         } else {
                 set_base = 0;
         }
 
+        offset = vcpu_e500->gtlb_offset[tlbsel];
+
         for (i = 0; i < size; i++) {
-                struct tlbe *tlbe = &vcpu_e500->gtlb_arch[tlbsel][set_base + i];
+                struct kvm_book3e_206_tlb_entry *tlbe =
+                        &vcpu_e500->gtlb_arch[offset + set_base + i];
                 unsigned int tid;
 
                 if (eaddr < get_tlb_eaddr(tlbe))
@@ -457,27 +507,55 @@ static int kvmppc_e500_tlb_index(struct kvmppc_vcpu_e500 *vcpu_e500,
         return -1;
 }
 
-static inline void kvmppc_e500_priv_setup(struct tlbe_priv *priv,
-                                          struct tlbe *gtlbe,
-                                          pfn_t pfn)
+static inline void kvmppc_e500_ref_setup(struct tlbe_ref *ref,
+                                         struct kvm_book3e_206_tlb_entry *gtlbe,
+                                         pfn_t pfn)
 {
-        priv->pfn = pfn;
-        priv->flags = E500_TLB_VALID;
+        ref->pfn = pfn;
+        ref->flags = E500_TLB_VALID;
 
         if (tlbe_is_writable(gtlbe))
-                priv->flags |= E500_TLB_DIRTY;
+                ref->flags |= E500_TLB_DIRTY;
 }
 
-static inline void kvmppc_e500_priv_release(struct tlbe_priv *priv)
+static inline void kvmppc_e500_ref_release(struct tlbe_ref *ref)
 {
-        if (priv->flags & E500_TLB_VALID) {
-                if (priv->flags & E500_TLB_DIRTY)
-                        kvm_release_pfn_dirty(priv->pfn);
+        if (ref->flags & E500_TLB_VALID) {
+                if (ref->flags & E500_TLB_DIRTY)
+                        kvm_release_pfn_dirty(ref->pfn);
                 else
-                        kvm_release_pfn_clean(priv->pfn);
+                        kvm_release_pfn_clean(ref->pfn);
+
+                ref->flags = 0;
+        }
+}
+
+static void clear_tlb_privs(struct kvmppc_vcpu_e500 *vcpu_e500)
+{
+        int tlbsel = 0;
+        int i;
+
+        for (i = 0; i < vcpu_e500->gtlb_params[tlbsel].entries; i++) {
+                struct tlbe_ref *ref =
+                        &vcpu_e500->gtlb_priv[tlbsel][i].ref;
+                kvmppc_e500_ref_release(ref);
+        }
+}
+
+static void clear_tlb_refs(struct kvmppc_vcpu_e500 *vcpu_e500)
+{
+        int stlbsel = 1;
+        int i;
+
+        kvmppc_e500_id_table_reset_all(vcpu_e500);
 
-                priv->flags = 0;
+        for (i = 0; i < host_tlb_params[stlbsel].entries; i++) {
+                struct tlbe_ref *ref =
+                        &vcpu_e500->tlb_refs[stlbsel][i];
+                kvmppc_e500_ref_release(ref);
         }
+
+        clear_tlb_privs(vcpu_e500);
 }
 
 static inline void kvmppc_e500_deliver_tlb_miss(struct kvm_vcpu *vcpu,
@@ -488,59 +566,54 @@ static inline void kvmppc_e500_deliver_tlb_miss(struct kvm_vcpu *vcpu,
         int tlbsel;
 
         /* since we only have two TLBs, only lower bit is used. */
-        tlbsel = (vcpu_e500->mas4 >> 28) & 0x1;
-        victim = (tlbsel == 0) ? tlb0_get_next_victim(vcpu_e500) : 0;
-        pidsel = (vcpu_e500->mas4 >> 16) & 0xf;
-        tsized = (vcpu_e500->mas4 >> 7) & 0x1f;
+        tlbsel = (vcpu->arch.shared->mas4 >> 28) & 0x1;
+        victim = (tlbsel == 0) ? gtlb0_get_next_victim(vcpu_e500) : 0;
+        pidsel = (vcpu->arch.shared->mas4 >> 16) & 0xf;
+        tsized = (vcpu->arch.shared->mas4 >> 7) & 0x1f;
 
-        vcpu_e500->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(victim)
+        vcpu->arch.shared->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(victim)
                 | MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
-        vcpu_e500->mas1 = MAS1_VALID | (as ? MAS1_TS : 0)
+        vcpu->arch.shared->mas1 = MAS1_VALID | (as ? MAS1_TS : 0)
                 | MAS1_TID(vcpu_e500->pid[pidsel])
                 | MAS1_TSIZE(tsized);
-        vcpu_e500->mas2 = (eaddr & MAS2_EPN)
-                | (vcpu_e500->mas4 & MAS2_ATTRIB_MASK);
-        vcpu_e500->mas3 &= MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3;
-        vcpu_e500->mas6 = (vcpu_e500->mas6 & MAS6_SPID1)
+        vcpu->arch.shared->mas2 = (eaddr & MAS2_EPN)
+                | (vcpu->arch.shared->mas4 & MAS2_ATTRIB_MASK);
+        vcpu->arch.shared->mas7_3 &= MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3;
+        vcpu->arch.shared->mas6 = (vcpu->arch.shared->mas6 & MAS6_SPID1)
                 | (get_cur_pid(vcpu) << 16)
                 | (as ? MAS6_SAS : 0);
-        vcpu_e500->mas7 = 0;
 }
 
-static inline void kvmppc_e500_setup_stlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
-                                           struct tlbe *gtlbe, int tsize,
-                                           struct tlbe_priv *priv,
-                                           u64 gvaddr, struct tlbe *stlbe)
+/* TID must be supplied by the caller */
+static inline void kvmppc_e500_setup_stlbe(
+        struct kvmppc_vcpu_e500 *vcpu_e500,
+        struct kvm_book3e_206_tlb_entry *gtlbe,
+        int tsize, struct tlbe_ref *ref, u64 gvaddr,
+        struct kvm_book3e_206_tlb_entry *stlbe)
 {
-        pfn_t pfn = priv->pfn;
-        unsigned int stid;
+        pfn_t pfn = ref->pfn;
 
-        stid = kvmppc_e500_get_sid(vcpu_e500, get_tlb_ts(gtlbe),
-                                   get_tlb_tid(gtlbe),
-                                   get_cur_pr(&vcpu_e500->vcpu), 0);
+        BUG_ON(!(ref->flags & E500_TLB_VALID));
 
         /* Force TS=1 IPROT=0 for all guest mappings. */
-        stlbe->mas1 = MAS1_TSIZE(tsize)
-                | MAS1_TID(stid) | MAS1_TS | MAS1_VALID;
+        stlbe->mas1 = MAS1_TSIZE(tsize) | MAS1_TS | MAS1_VALID;
         stlbe->mas2 = (gvaddr & MAS2_EPN)
                 | e500_shadow_mas2_attrib(gtlbe->mas2,
                                 vcpu_e500->vcpu.arch.shared->msr & MSR_PR);
-        stlbe->mas3 = ((pfn << PAGE_SHIFT) & MAS3_RPN)
-                | e500_shadow_mas3_attrib(gtlbe->mas3,
+        stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT)
+                | e500_shadow_mas3_attrib(gtlbe->mas7_3,
                                 vcpu_e500->vcpu.arch.shared->msr & MSR_PR);
-        stlbe->mas7 = (pfn >> (32 - PAGE_SHIFT)) & MAS7_RPN;
 }
 
-
 static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
-        u64 gvaddr, gfn_t gfn, struct tlbe *gtlbe, int tlbsel, int esel,
-        struct tlbe *stlbe)
+        u64 gvaddr, gfn_t gfn, struct kvm_book3e_206_tlb_entry *gtlbe,
+        int tlbsel, struct kvm_book3e_206_tlb_entry *stlbe,
+        struct tlbe_ref *ref)
 {
         struct kvm_memory_slot *slot;
         unsigned long pfn, hva;
         int pfnmap = 0;
         int tsize = BOOK3E_PAGESZ_4K;
-        struct tlbe_priv *priv;
 
         /*
          * Translate guest physical to true physical, acquiring
@@ -621,12 +694,31 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
                                 pfn &= ~(tsize_pages - 1);
                                 break;
                         }
+                } else if (vma && hva >= vma->vm_start &&
+                           (vma->vm_flags & VM_HUGETLB)) {
+                        unsigned long psize = vma_kernel_pagesize(vma);
+
+                        tsize = (gtlbe->mas1 & MAS1_TSIZE_MASK) >>
+                                MAS1_TSIZE_SHIFT;
+
+                        /*
+                         * Take the largest page size that satisfies both host
+                         * and guest mapping
+                         */
+                        tsize = min(__ilog2(psize) - 10, tsize);
+
+                        /*
+                         * e500 doesn't implement the lowest tsize bit,
+                         * or 1K pages.
+                         */
+                        tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
                 }
 
                 up_read(&current->mm->mmap_sem);
         }
 
         if (likely(!pfnmap)) {
+                unsigned long tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT);
                 pfn = gfn_to_pfn_memslot(vcpu_e500->vcpu.kvm, slot, gfn);
                 if (is_error_pfn(pfn)) {
                         printk(KERN_ERR "Couldn't get real page for gfn %lx!\n",
@@ -634,45 +726,52 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
                         kvm_release_pfn_clean(pfn);
                         return;
                 }
+
+                /* Align guest and physical address to page map boundaries */
+                pfn &= ~(tsize_pages - 1);
+                gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1);
         }
 
-        /* Drop old priv and setup new one. */
-        priv = &vcpu_e500->gtlb_priv[tlbsel][esel];
-        kvmppc_e500_priv_release(priv);
-        kvmppc_e500_priv_setup(priv, gtlbe, pfn);
+        /* Drop old ref and setup new one. */
+        kvmppc_e500_ref_release(ref);
+        kvmppc_e500_ref_setup(ref, gtlbe, pfn);
 
-        kvmppc_e500_setup_stlbe(vcpu_e500, gtlbe, tsize, priv, gvaddr, stlbe);
+        kvmppc_e500_setup_stlbe(vcpu_e500, gtlbe, tsize, ref, gvaddr, stlbe);
 }
 
 /* XXX only map the one-one case, for now use TLB0 */
-static int kvmppc_e500_tlb0_map(struct kvmppc_vcpu_e500 *vcpu_e500,
-                                int esel, struct tlbe *stlbe)
+static void kvmppc_e500_tlb0_map(struct kvmppc_vcpu_e500 *vcpu_e500,
+                                 int esel,
+                                 struct kvm_book3e_206_tlb_entry *stlbe)
 {
-        struct tlbe *gtlbe;
+        struct kvm_book3e_206_tlb_entry *gtlbe;
+        struct tlbe_ref *ref;
 
-        gtlbe = &vcpu_e500->gtlb_arch[0][esel];
+        gtlbe = get_entry(vcpu_e500, 0, esel);
+        ref = &vcpu_e500->gtlb_priv[0][esel].ref;
 
         kvmppc_e500_shadow_map(vcpu_e500, get_tlb_eaddr(gtlbe),
                         get_tlb_raddr(gtlbe) >> PAGE_SHIFT,
-                        gtlbe, 0, esel, stlbe);
-
-        return esel;
+                        gtlbe, 0, stlbe, ref);
 }
 
 /* Caller must ensure that the specified guest TLB entry is safe to insert into
  * the shadow TLB. */
 /* XXX for both one-one and one-to-many , for now use TLB1 */
 static int kvmppc_e500_tlb1_map(struct kvmppc_vcpu_e500 *vcpu_e500,
-                u64 gvaddr, gfn_t gfn, struct tlbe *gtlbe, struct tlbe *stlbe)
+                u64 gvaddr, gfn_t gfn, struct kvm_book3e_206_tlb_entry *gtlbe,
+                struct kvm_book3e_206_tlb_entry *stlbe)
 {
+        struct tlbe_ref *ref;
         unsigned int victim;
 
-        victim = vcpu_e500->gtlb_nv[1]++;
+        victim = vcpu_e500->host_tlb1_nv++;
 
-        if (unlikely(vcpu_e500->gtlb_nv[1] >= tlb1_max_shadow_size()))
-                vcpu_e500->gtlb_nv[1] = 0;
+        if (unlikely(vcpu_e500->host_tlb1_nv >= tlb1_max_shadow_size()))
+                vcpu_e500->host_tlb1_nv = 0;
 
-        kvmppc_e500_shadow_map(vcpu_e500, gvaddr, gfn, gtlbe, 1, victim, stlbe);
+        ref = &vcpu_e500->tlb_refs[1][victim];
+        kvmppc_e500_shadow_map(vcpu_e500, gvaddr, gfn, gtlbe, 1, stlbe, ref);
 
         return victim;
 }
@@ -689,7 +788,8 @@ static inline int kvmppc_e500_gtlbe_invalidate(
                                 struct kvmppc_vcpu_e500 *vcpu_e500,
                                 int tlbsel, int esel)
 {
-        struct tlbe *gtlbe = &vcpu_e500->gtlb_arch[tlbsel][esel];
+        struct kvm_book3e_206_tlb_entry *gtlbe =
+                get_entry(vcpu_e500, tlbsel, esel);
 
         if (unlikely(get_tlb_iprot(gtlbe)))
                 return -1;
@@ -704,10 +804,10 @@ int kvmppc_e500_emul_mt_mmucsr0(struct kvmppc_vcpu_e500 *vcpu_e500, ulong value)
         int esel;
 
         if (value & MMUCSR0_TLB0FI)
-                for (esel = 0; esel < vcpu_e500->gtlb_size[0]; esel++)
+                for (esel = 0; esel < vcpu_e500->gtlb_params[0].entries; esel++)
                         kvmppc_e500_gtlbe_invalidate(vcpu_e500, 0, esel);
         if (value & MMUCSR0_TLB1FI)
-                for (esel = 0; esel < vcpu_e500->gtlb_size[1]; esel++)
+                for (esel = 0; esel < vcpu_e500->gtlb_params[1].entries; esel++)
                         kvmppc_e500_gtlbe_invalidate(vcpu_e500, 1, esel);
 
         /* Invalidate all vcpu id mappings */
@@ -732,7 +832,8 @@ int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb)
 
         if (ia) {
                 /* invalidate all entries */
-                for (esel = 0; esel < vcpu_e500->gtlb_size[tlbsel]; esel++)
+                for (esel = 0; esel < vcpu_e500->gtlb_params[tlbsel].entries;
+                     esel++)
                         kvmppc_e500_gtlbe_invalidate(vcpu_e500, tlbsel, esel);
         } else {
                 ea &= 0xfffff000;
@@ -752,18 +853,17 @@ int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
         int tlbsel, esel;
-        struct tlbe *gtlbe;
+        struct kvm_book3e_206_tlb_entry *gtlbe;
 
-        tlbsel = get_tlb_tlbsel(vcpu_e500);
-        esel = get_tlb_esel(vcpu_e500, tlbsel);
+        tlbsel = get_tlb_tlbsel(vcpu);
+        esel = get_tlb_esel(vcpu, tlbsel);
 
-        gtlbe = &vcpu_e500->gtlb_arch[tlbsel][esel];
-        vcpu_e500->mas0 &= ~MAS0_NV(~0);
-        vcpu_e500->mas0 |= MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
-        vcpu_e500->mas1 = gtlbe->mas1;
-        vcpu_e500->mas2 = gtlbe->mas2;
-        vcpu_e500->mas3 = gtlbe->mas3;
-        vcpu_e500->mas7 = gtlbe->mas7;
+        gtlbe = get_entry(vcpu_e500, tlbsel, esel);
+        vcpu->arch.shared->mas0 &= ~MAS0_NV(~0);
+        vcpu->arch.shared->mas0 |= MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
+        vcpu->arch.shared->mas1 = gtlbe->mas1;
+        vcpu->arch.shared->mas2 = gtlbe->mas2;
+        vcpu->arch.shared->mas7_3 = gtlbe->mas7_3;
 
         return EMULATE_DONE;
 }
@@ -771,10 +871,10 @@ int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu)
 int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
-        int as = !!get_cur_sas(vcpu_e500);
-        unsigned int pid = get_cur_spid(vcpu_e500);
+        int as = !!get_cur_sas(vcpu);
+        unsigned int pid = get_cur_spid(vcpu);
         int esel, tlbsel;
-        struct tlbe *gtlbe = NULL;
+        struct kvm_book3e_206_tlb_entry *gtlbe = NULL;
         gva_t ea;
 
         ea = kvmppc_get_gpr(vcpu, rb);
@@ -782,70 +882,90 @@ int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb)
         for (tlbsel = 0; tlbsel < 2; tlbsel++) {
                 esel = kvmppc_e500_tlb_index(vcpu_e500, ea, tlbsel, pid, as);
                 if (esel >= 0) {
-                        gtlbe = &vcpu_e500->gtlb_arch[tlbsel][esel];
+                        gtlbe = get_entry(vcpu_e500, tlbsel, esel);
                         break;
                 }
         }
 
         if (gtlbe) {
-                vcpu_e500->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel)
+                esel &= vcpu_e500->gtlb_params[tlbsel].ways - 1;
+
+                vcpu->arch.shared->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel)
                         | MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
-                vcpu_e500->mas1 = gtlbe->mas1;
-                vcpu_e500->mas2 = gtlbe->mas2;
-                vcpu_e500->mas3 = gtlbe->mas3;
-                vcpu_e500->mas7 = gtlbe->mas7;
+                vcpu->arch.shared->mas1 = gtlbe->mas1;
+                vcpu->arch.shared->mas2 = gtlbe->mas2;
+                vcpu->arch.shared->mas7_3 = gtlbe->mas7_3;
         } else {
                 int victim;
 
                 /* since we only have two TLBs, only lower bit is used. */
-                tlbsel = vcpu_e500->mas4 >> 28 & 0x1;
-                victim = (tlbsel == 0) ? tlb0_get_next_victim(vcpu_e500) : 0;
+                tlbsel = vcpu->arch.shared->mas4 >> 28 & 0x1;
+                victim = (tlbsel == 0) ? gtlb0_get_next_victim(vcpu_e500) : 0;
 
-                vcpu_e500->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(victim)
+                vcpu->arch.shared->mas0 = MAS0_TLBSEL(tlbsel)
+                        | MAS0_ESEL(victim)
                         | MAS0_NV(vcpu_e500->gtlb_nv[tlbsel]);
-                vcpu_e500->mas1 = (vcpu_e500->mas6 & MAS6_SPID0)
-                        | (vcpu_e500->mas6 & (MAS6_SAS ? MAS1_TS : 0))
-                        | (vcpu_e500->mas4 & MAS4_TSIZED(~0));
-                vcpu_e500->mas2 &= MAS2_EPN;
-                vcpu_e500->mas2 |= vcpu_e500->mas4 & MAS2_ATTRIB_MASK;
-                vcpu_e500->mas3 &= MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3;
-                vcpu_e500->mas7 = 0;
+                vcpu->arch.shared->mas1 =
+                          (vcpu->arch.shared->mas6 & MAS6_SPID0)
+                        | (vcpu->arch.shared->mas6 & (MAS6_SAS ? MAS1_TS : 0))
+                        | (vcpu->arch.shared->mas4 & MAS4_TSIZED(~0));
+                vcpu->arch.shared->mas2 &= MAS2_EPN;
+                vcpu->arch.shared->mas2 |= vcpu->arch.shared->mas4 &
+                                           MAS2_ATTRIB_MASK;
+                vcpu->arch.shared->mas7_3 &= MAS3_U0 | MAS3_U1 |
+                                             MAS3_U2 | MAS3_U3;
         }
 
         kvmppc_set_exit_type(vcpu, EMULATED_TLBSX_EXITS);
         return EMULATE_DONE;
 }
 
+/* sesel is for tlb1 only */
+static void write_stlbe(struct kvmppc_vcpu_e500 *vcpu_e500,
+                        struct kvm_book3e_206_tlb_entry *gtlbe,
+                        struct kvm_book3e_206_tlb_entry *stlbe,
+                        int stlbsel, int sesel)
+{
+        int stid;
+
+        preempt_disable();
+        stid = kvmppc_e500_get_sid(vcpu_e500, get_tlb_ts(gtlbe),
+                                   get_tlb_tid(gtlbe),
+                                   get_cur_pr(&vcpu_e500->vcpu), 0);
+
+        stlbe->mas1 |= MAS1_TID(stid);
+        write_host_tlbe(vcpu_e500, stlbsel, sesel, stlbe);
+        preempt_enable();
+}
+
 int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
-        struct tlbe *gtlbe;
+        struct kvm_book3e_206_tlb_entry *gtlbe;
         int tlbsel, esel;
 
-        tlbsel = get_tlb_tlbsel(vcpu_e500);
-        esel = get_tlb_esel(vcpu_e500, tlbsel);
+        tlbsel = get_tlb_tlbsel(vcpu);
+        esel = get_tlb_esel(vcpu, tlbsel);
 
-        gtlbe = &vcpu_e500->gtlb_arch[tlbsel][esel];
+        gtlbe = get_entry(vcpu_e500, tlbsel, esel);
 
         if (get_tlb_v(gtlbe))
-                kvmppc_e500_stlbe_invalidate(vcpu_e500, tlbsel, esel);
+                inval_gtlbe_on_host(vcpu_e500, tlbsel, esel);
 
-        gtlbe->mas1 = vcpu_e500->mas1;
-        gtlbe->mas2 = vcpu_e500->mas2;
-        gtlbe->mas3 = vcpu_e500->mas3;
-        gtlbe->mas7 = vcpu_e500->mas7;
+        gtlbe->mas1 = vcpu->arch.shared->mas1;
+        gtlbe->mas2 = vcpu->arch.shared->mas2;
+        gtlbe->mas7_3 = vcpu->arch.shared->mas7_3;
 
-        trace_kvm_gtlb_write(vcpu_e500->mas0, gtlbe->mas1, gtlbe->mas2,
-                             gtlbe->mas3, gtlbe->mas7);
+        trace_kvm_booke206_gtlb_write(vcpu->arch.shared->mas0, gtlbe->mas1,
+                                      gtlbe->mas2, gtlbe->mas7_3);
 
         /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
         if (tlbe_is_host_safe(vcpu, gtlbe)) {
-                struct tlbe stlbe;
+                struct kvm_book3e_206_tlb_entry stlbe;
                 int stlbsel, sesel;
                 u64 eaddr;
                 u64 raddr;
 
-                preempt_disable();
                 switch (tlbsel) {
                 case 0:
                         /* TLB0 */
@@ -853,7 +973,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                         gtlbe->mas1 |= MAS1_TSIZE(BOOK3E_PAGESZ_4K);
 
                         stlbsel = 0;
-                        sesel = kvmppc_e500_tlb0_map(vcpu_e500, esel, &stlbe);
+                        kvmppc_e500_tlb0_map(vcpu_e500, esel, &stlbe);
+                        sesel = 0; /* unused */
 
                         break;
 
@@ -874,8 +995,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                 default:
                         BUG();
                 }
-                write_host_tlbe(vcpu_e500, stlbsel, sesel, &stlbe);
-                preempt_enable();
+
+                write_stlbe(vcpu_e500, gtlbe, &stlbe, stlbsel, sesel);
         }
 
         kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
@@ -914,9 +1035,11 @@ gpa_t kvmppc_mmu_xlate(struct kvm_vcpu *vcpu, unsigned int index,
                         gva_t eaddr)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
-        struct tlbe *gtlbe =
-                &vcpu_e500->gtlb_arch[tlbsel_of(index)][esel_of(index)];
-        u64 pgmask = get_tlb_bytes(gtlbe) - 1;
+        struct kvm_book3e_206_tlb_entry *gtlbe;
+        u64 pgmask;
+
+        gtlbe = get_entry(vcpu_e500, tlbsel_of(index), esel_of(index));
+        pgmask = get_tlb_bytes(gtlbe) - 1;
 
         return get_tlb_raddr(gtlbe) | (eaddr & pgmask);
 }
@@ -930,22 +1053,21 @@ void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 eaddr, gpa_t gpaddr,
 {
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
         struct tlbe_priv *priv;
-        struct tlbe *gtlbe, stlbe;
+        struct kvm_book3e_206_tlb_entry *gtlbe, stlbe;
         int tlbsel = tlbsel_of(index);
         int esel = esel_of(index);
         int stlbsel, sesel;
 
-        gtlbe = &vcpu_e500->gtlb_arch[tlbsel][esel];
+        gtlbe = get_entry(vcpu_e500, tlbsel, esel);
 
-        preempt_disable();
         switch (tlbsel) {
         case 0:
                 stlbsel = 0;
-                sesel = esel;
-                priv = &vcpu_e500->gtlb_priv[stlbsel][sesel];
+                sesel = 0; /* unused */
+                priv = &vcpu_e500->gtlb_priv[tlbsel][esel];
 
                 kvmppc_e500_setup_stlbe(vcpu_e500, gtlbe, BOOK3E_PAGESZ_4K,
-                                        priv, eaddr, &stlbe);
+                                        &priv->ref, eaddr, &stlbe);
                 break;
 
         case 1: {
@@ -962,8 +1084,7 @@ void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 eaddr, gpa_t gpaddr,
                 break;
         }
 
-        write_host_tlbe(vcpu_e500, stlbsel, sesel, &stlbe);
-        preempt_enable();
+        write_stlbe(vcpu_e500, gtlbe, &stlbe, stlbsel, sesel);
 }
 
 int kvmppc_e500_tlb_search(struct kvm_vcpu *vcpu,
@@ -993,85 +1114,279 @@ void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid)
 
 void kvmppc_e500_tlb_setup(struct kvmppc_vcpu_e500 *vcpu_e500)
 {
-        struct tlbe *tlbe;
+        struct kvm_book3e_206_tlb_entry *tlbe;
 
         /* Insert large initial mapping for guest. */
-        tlbe = &vcpu_e500->gtlb_arch[1][0];
+        tlbe = get_entry(vcpu_e500, 1, 0);
         tlbe->mas1 = MAS1_VALID | MAS1_TSIZE(BOOK3E_PAGESZ_256M);
         tlbe->mas2 = 0;
-        tlbe->mas3 = E500_TLB_SUPER_PERM_MASK;
-        tlbe->mas7 = 0;
+        tlbe->mas7_3 = E500_TLB_SUPER_PERM_MASK;
 
         /* 4K map for serial output. Used by kernel wrapper. */
-        tlbe = &vcpu_e500->gtlb_arch[1][1];
+        tlbe = get_entry(vcpu_e500, 1, 1);
         tlbe->mas1 = MAS1_VALID | MAS1_TSIZE(BOOK3E_PAGESZ_4K);
         tlbe->mas2 = (0xe0004500 & 0xFFFFF000) | MAS2_I | MAS2_G;
-        tlbe->mas3 = (0xe0004500 & 0xFFFFF000) | E500_TLB_SUPER_PERM_MASK;
-        tlbe->mas7 = 0;
+        tlbe->mas7_3 = (0xe0004500 & 0xFFFFF000) | E500_TLB_SUPER_PERM_MASK;
+}
+
+static void free_gtlb(struct kvmppc_vcpu_e500 *vcpu_e500)
+{
+        int i;
+
+        clear_tlb_refs(vcpu_e500);
+        kfree(vcpu_e500->gtlb_priv[0]);
+        kfree(vcpu_e500->gtlb_priv[1]);
+
+        if (vcpu_e500->shared_tlb_pages) {
+                vfree((void *)(round_down((uintptr_t)vcpu_e500->gtlb_arch,
+                                          PAGE_SIZE)));
+
+                for (i = 0; i < vcpu_e500->num_shared_tlb_pages; i++) {
+                        set_page_dirty_lock(vcpu_e500->shared_tlb_pages[i]);
+                        put_page(vcpu_e500->shared_tlb_pages[i]);
+                }
+
+                vcpu_e500->num_shared_tlb_pages = 0;
+                vcpu_e500->shared_tlb_pages = NULL;
+        } else {
+                kfree(vcpu_e500->gtlb_arch);
+        }
+
+        vcpu_e500->gtlb_arch = NULL;
+}
+
+int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
+                              struct kvm_config_tlb *cfg)
+{
+        struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
+        struct kvm_book3e_206_tlb_params params;
+        char *virt;
+        struct page **pages;
+        struct tlbe_priv *privs[2] = {};
+        size_t array_len;
+        u32 sets;
+        int num_pages, ret, i;
+
+        if (cfg->mmu_type != KVM_MMU_FSL_BOOKE_NOHV)
+                return -EINVAL;
+
+        if (copy_from_user(&params, (void __user *)(uintptr_t)cfg->params,
+                           sizeof(params)))
+                return -EFAULT;
+
+        if (params.tlb_sizes[1] > 64)
+                return -EINVAL;
+        if (params.tlb_ways[1] != params.tlb_sizes[1])
+                return -EINVAL;
+        if (params.tlb_sizes[2] != 0 || params.tlb_sizes[3] != 0)
+                return -EINVAL;
+        if (params.tlb_ways[2] != 0 || params.tlb_ways[3] != 0)
+                return -EINVAL;
+
+        if (!is_power_of_2(params.tlb_ways[0]))
+                return -EINVAL;
+
+        sets = params.tlb_sizes[0] >> ilog2(params.tlb_ways[0]);
+        if (!is_power_of_2(sets))
+                return -EINVAL;
+
+        array_len = params.tlb_sizes[0] + params.tlb_sizes[1];
+        array_len *= sizeof(struct kvm_book3e_206_tlb_entry);
+
+        if (cfg->array_len < array_len)
+                return -EINVAL;
+
+        num_pages = DIV_ROUND_UP(cfg->array + array_len - 1, PAGE_SIZE) -
+                    cfg->array / PAGE_SIZE;
+        pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL);
+        if (!pages)
+                return -ENOMEM;
+
+        ret = get_user_pages_fast(cfg->array, num_pages, 1, pages);
+        if (ret < 0)
+                goto err_pages;
+
+        if (ret != num_pages) {
+                num_pages = ret;
+                ret = -EFAULT;
+                goto err_put_page;
+        }
+
+        virt = vmap(pages, num_pages, VM_MAP, PAGE_KERNEL);
+        if (!virt)
+                goto err_put_page;
+
+        privs[0] = kzalloc(sizeof(struct tlbe_priv) * params.tlb_sizes[0],
+                           GFP_KERNEL);
+        privs[1] = kzalloc(sizeof(struct tlbe_priv) * params.tlb_sizes[1],
+                           GFP_KERNEL);
+
+        if (!privs[0] || !privs[1])
+                goto err_put_page;
+
+        free_gtlb(vcpu_e500);
+
+        vcpu_e500->gtlb_priv[0] = privs[0];
+        vcpu_e500->gtlb_priv[1] = privs[1];
+
+        vcpu_e500->gtlb_arch = (struct kvm_book3e_206_tlb_entry *)
+                (virt + (cfg->array & (PAGE_SIZE - 1)));
+
+        vcpu_e500->gtlb_params[0].entries = params.tlb_sizes[0];
+        vcpu_e500->gtlb_params[1].entries = params.tlb_sizes[1];
+
+        vcpu_e500->gtlb_offset[0] = 0;
+        vcpu_e500->gtlb_offset[1] = params.tlb_sizes[0];
+
+        vcpu_e500->tlb0cfg &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        if (params.tlb_sizes[0] <= 2048)
+                vcpu_e500->tlb0cfg |= params.tlb_sizes[0];
+        vcpu_e500->tlb0cfg |= params.tlb_ways[0] << TLBnCFG_ASSOC_SHIFT;
+
+        vcpu_e500->tlb1cfg &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        vcpu_e500->tlb1cfg |= params.tlb_sizes[1];
+        vcpu_e500->tlb1cfg |= params.tlb_ways[1] << TLBnCFG_ASSOC_SHIFT;
+
+        vcpu_e500->shared_tlb_pages = pages;
+        vcpu_e500->num_shared_tlb_pages = num_pages;
+
+        vcpu_e500->gtlb_params[0].ways = params.tlb_ways[0];
+        vcpu_e500->gtlb_params[0].sets = sets;
+
+        vcpu_e500->gtlb_params[1].ways = params.tlb_sizes[1];
+        vcpu_e500->gtlb_params[1].sets = 1;
+
+        return 0;
+
+err_put_page:
+        kfree(privs[0]);
+        kfree(privs[1]);
+
+        for (i = 0; i < num_pages; i++)
+                put_page(pages[i]);
+
+err_pages:
+        kfree(pages);
+        return ret;
+}
+
+int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu *vcpu,
+                             struct kvm_dirty_tlb *dirty)
+{
+        struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
+
+        clear_tlb_refs(vcpu_e500);
+        return 0;
 }
 
 int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500)
 {
-        tlb1_entry_num = mfspr(SPRN_TLB1CFG) & 0xFFF;
-
-        vcpu_e500->gtlb_size[0] = KVM_E500_TLB0_SIZE;
-        vcpu_e500->gtlb_arch[0] =
-                kzalloc(sizeof(struct tlbe) * KVM_E500_TLB0_SIZE, GFP_KERNEL);
-        if (vcpu_e500->gtlb_arch[0] == NULL)
-                goto err_out;
-
-        vcpu_e500->gtlb_size[1] = KVM_E500_TLB1_SIZE;
-        vcpu_e500->gtlb_arch[1] =
-                kzalloc(sizeof(struct tlbe) * KVM_E500_TLB1_SIZE, GFP_KERNEL);
-        if (vcpu_e500->gtlb_arch[1] == NULL)
-                goto err_out_guest0;
-
-        vcpu_e500->gtlb_priv[0] = (struct tlbe_priv *)
-                kzalloc(sizeof(struct tlbe_priv) * KVM_E500_TLB0_SIZE, GFP_KERNEL);
-        if (vcpu_e500->gtlb_priv[0] == NULL)
-                goto err_out_guest1;
-        vcpu_e500->gtlb_priv[1] = (struct tlbe_priv *)
-                kzalloc(sizeof(struct tlbe_priv) * KVM_E500_TLB1_SIZE, GFP_KERNEL);
-
-        if (vcpu_e500->gtlb_priv[1] == NULL)
-                goto err_out_priv0;
+        int entry_size = sizeof(struct kvm_book3e_206_tlb_entry);
+        int entries = KVM_E500_TLB0_SIZE + KVM_E500_TLB1_SIZE;
+
+        host_tlb_params[0].entries = mfspr(SPRN_TLB0CFG) & TLBnCFG_N_ENTRY;
+        host_tlb_params[1].entries = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
+
+        /*
+         * This should never happen on real e500 hardware, but is
+         * architecturally possible -- e.g. in some weird nested
+         * virtualization case.
+         */
+        if (host_tlb_params[0].entries == 0 ||
+            host_tlb_params[1].entries == 0) {
+                pr_err("%s: need to know host tlb size\n", __func__);
+                return -ENODEV;
+        }
+
+        host_tlb_params[0].ways = (mfspr(SPRN_TLB0CFG) & TLBnCFG_ASSOC) >>
+                                  TLBnCFG_ASSOC_SHIFT;
+        host_tlb_params[1].ways = host_tlb_params[1].entries;
+
+        if (!is_power_of_2(host_tlb_params[0].entries) ||
+            !is_power_of_2(host_tlb_params[0].ways) ||
+            host_tlb_params[0].entries < host_tlb_params[0].ways ||
+            host_tlb_params[0].ways == 0) {
+                pr_err("%s: bad tlb0 host config: %u entries %u ways\n",
+                       __func__, host_tlb_params[0].entries,
+                       host_tlb_params[0].ways);
+                return -ENODEV;
+        }
+
+        host_tlb_params[0].sets =
+                host_tlb_params[0].entries / host_tlb_params[0].ways;
+        host_tlb_params[1].sets = 1;
+
+        vcpu_e500->gtlb_params[0].entries = KVM_E500_TLB0_SIZE;
+        vcpu_e500->gtlb_params[1].entries = KVM_E500_TLB1_SIZE;
+
+        vcpu_e500->gtlb_params[0].ways = KVM_E500_TLB0_WAY_NUM;
+        vcpu_e500->gtlb_params[0].sets =
+                KVM_E500_TLB0_SIZE / KVM_E500_TLB0_WAY_NUM;
+
+        vcpu_e500->gtlb_params[1].ways = KVM_E500_TLB1_SIZE;
+        vcpu_e500->gtlb_params[1].sets = 1;
+
+        vcpu_e500->gtlb_arch = kmalloc(entries * entry_size, GFP_KERNEL);
+        if (!vcpu_e500->gtlb_arch)
+                return -ENOMEM;
+
+        vcpu_e500->gtlb_offset[0] = 0;
+        vcpu_e500->gtlb_offset[1] = KVM_E500_TLB0_SIZE;
+
+        vcpu_e500->tlb_refs[0] =
+                kzalloc(sizeof(struct tlbe_ref) * host_tlb_params[0].entries,
+                        GFP_KERNEL);
+        if (!vcpu_e500->tlb_refs[0])
+                goto err;
+
+        vcpu_e500->tlb_refs[1] =
+                kzalloc(sizeof(struct tlbe_ref) * host_tlb_params[1].entries,
+                        GFP_KERNEL);
+        if (!vcpu_e500->tlb_refs[1])
+                goto err;
+
+        vcpu_e500->gtlb_priv[0] = kzalloc(sizeof(struct tlbe_ref) *
+                                          vcpu_e500->gtlb_params[0].entries,
+                                          GFP_KERNEL);
+        if (!vcpu_e500->gtlb_priv[0])
+                goto err;
+
+        vcpu_e500->gtlb_priv[1] = kzalloc(sizeof(struct tlbe_ref) *
+                                          vcpu_e500->gtlb_params[1].entries,
+                                          GFP_KERNEL);
+        if (!vcpu_e500->gtlb_priv[1])
+                goto err;
 
         if (kvmppc_e500_id_table_alloc(vcpu_e500) == NULL)
-                goto err_out_priv1;
+                goto err;
 
         /* Init TLB configuration register */
-        vcpu_e500->tlb0cfg = mfspr(SPRN_TLB0CFG) & ~0xfffUL;
-        vcpu_e500->tlb0cfg |= vcpu_e500->gtlb_size[0];
-        vcpu_e500->tlb1cfg = mfspr(SPRN_TLB1CFG) & ~0xfffUL;
-        vcpu_e500->tlb1cfg |= vcpu_e500->gtlb_size[1];
+        vcpu_e500->tlb0cfg = mfspr(SPRN_TLB0CFG) &
+                             ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        vcpu_e500->tlb0cfg |= vcpu_e500->gtlb_params[0].entries;
+        vcpu_e500->tlb0cfg |=
+                vcpu_e500->gtlb_params[0].ways << TLBnCFG_ASSOC_SHIFT;
+
+        vcpu_e500->tlb1cfg = mfspr(SPRN_TLB1CFG) &
+                             ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        vcpu_e500->tlb0cfg |= vcpu_e500->gtlb_params[1].entries;
+        vcpu_e500->tlb0cfg |=
+                vcpu_e500->gtlb_params[1].ways << TLBnCFG_ASSOC_SHIFT;
 
         return 0;
 
-err_out_priv1:
-        kfree(vcpu_e500->gtlb_priv[1]);
-err_out_priv0:
-        kfree(vcpu_e500->gtlb_priv[0]);
-err_out_guest1:
-        kfree(vcpu_e500->gtlb_arch[1]);
-err_out_guest0:
-        kfree(vcpu_e500->gtlb_arch[0]);
-err_out:
+err:
+        free_gtlb(vcpu_e500);
+        kfree(vcpu_e500->tlb_refs[0]);
+        kfree(vcpu_e500->tlb_refs[1]);
         return -1;
 }
 
 void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *vcpu_e500)
 {
-        int stlbsel, i;
-
-        /* release all privs */
-        for (stlbsel = 0; stlbsel < 2; stlbsel++)
-                for (i = 0; i < vcpu_e500->gtlb_size[stlbsel]; i++) {
-                        struct tlbe_priv *priv =
-                                &vcpu_e500->gtlb_priv[stlbsel][i];
-                        kvmppc_e500_priv_release(priv);
-                }
-
+        free_gtlb(vcpu_e500);
         kvmppc_e500_id_table_free(vcpu_e500);
-        kfree(vcpu_e500->gtlb_arch[1]);
-        kfree(vcpu_e500->gtlb_arch[0]);
+
+        kfree(vcpu_e500->tlb_refs[0]);
+        kfree(vcpu_e500->tlb_refs[1]);
 }
diff --git a/arch/powerpc/kvm/e500_tlb.h b/arch/powerpc/kvm/e500_tlb.h
index 59b88e99a23..5c6d2d7bf05 100644
--- a/arch/powerpc/kvm/e500_tlb.h
+++ b/arch/powerpc/kvm/e500_tlb.h
@@ -20,13 +20,9 @@
 #include <asm/tlb.h>
 #include <asm/kvm_e500.h>
 
-#define KVM_E500_TLB0_WAY_SIZE_BIT      7       /* Fixed */
-#define KVM_E500_TLB0_WAY_SIZE          (1UL << KVM_E500_TLB0_WAY_SIZE_BIT)
-#define KVM_E500_TLB0_WAY_SIZE_MASK     (KVM_E500_TLB0_WAY_SIZE - 1)
-
-#define KVM_E500_TLB0_WAY_NUM_BIT       1       /* No greater than 7 */
-#define KVM_E500_TLB0_WAY_NUM           (1UL << KVM_E500_TLB0_WAY_NUM_BIT)
-#define KVM_E500_TLB0_WAY_NUM_MASK      (KVM_E500_TLB0_WAY_NUM - 1)
+/* This geometry is the legacy default -- can be overridden by userspace */
+#define KVM_E500_TLB0_WAY_SIZE          128
+#define KVM_E500_TLB0_WAY_NUM           2
 
 #define KVM_E500_TLB0_SIZE  (KVM_E500_TLB0_WAY_SIZE * KVM_E500_TLB0_WAY_NUM)
 #define KVM_E500_TLB1_SIZE  16
@@ -58,50 +54,54 @@ extern void kvmppc_e500_tlb_setup(struct kvmppc_vcpu_e500 *);
 extern void kvmppc_e500_recalc_shadow_pid(struct kvmppc_vcpu_e500 *);
 
 /* TLB helper functions */
-static inline unsigned int get_tlb_size(const struct tlbe *tlbe)
+static inline unsigned int
+get_tlb_size(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         return (tlbe->mas1 >> 7) & 0x1f;
 }
 
-static inline gva_t get_tlb_eaddr(const struct tlbe *tlbe)
+static inline gva_t get_tlb_eaddr(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         return tlbe->mas2 & 0xfffff000;
 }
 
-static inline u64 get_tlb_bytes(const struct tlbe *tlbe)
+static inline u64 get_tlb_bytes(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         unsigned int pgsize = get_tlb_size(tlbe);
         return 1ULL << 10 << pgsize;
 }
 
-static inline gva_t get_tlb_end(const struct tlbe *tlbe)
+static inline gva_t get_tlb_end(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         u64 bytes = get_tlb_bytes(tlbe);
         return get_tlb_eaddr(tlbe) + bytes - 1;
 }
 
-static inline u64 get_tlb_raddr(const struct tlbe *tlbe)
+static inline u64 get_tlb_raddr(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
-        u64 rpn = tlbe->mas7;
-        return (rpn << 32) | (tlbe->mas3 & 0xfffff000);
+        return tlbe->mas7_3 & ~0xfffULL;
 }
 
-static inline unsigned int get_tlb_tid(const struct tlbe *tlbe)
+static inline unsigned int
+get_tlb_tid(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         return (tlbe->mas1 >> 16) & 0xff;
 }
 
-static inline unsigned int get_tlb_ts(const struct tlbe *tlbe)
+static inline unsigned int
+get_tlb_ts(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         return (tlbe->mas1 >> 12) & 0x1;
 }
 
-static inline unsigned int get_tlb_v(const struct tlbe *tlbe)
+static inline unsigned int
+get_tlb_v(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         return (tlbe->mas1 >> 31) & 0x1;
 }
 
-static inline unsigned int get_tlb_iprot(const struct tlbe *tlbe)
+static inline unsigned int
+get_tlb_iprot(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         return (tlbe->mas1 >> 30) & 0x1;
 }
@@ -121,59 +121,37 @@ static inline unsigned int get_cur_pr(struct kvm_vcpu *vcpu)
         return !!(vcpu->arch.shared->msr & MSR_PR);
 }
 
-static inline unsigned int get_cur_spid(
-                const struct kvmppc_vcpu_e500 *vcpu_e500)
+static inline unsigned int get_cur_spid(const struct kvm_vcpu *vcpu)
 {
-        return (vcpu_e500->mas6 >> 16) & 0xff;
+        return (vcpu->arch.shared->mas6 >> 16) & 0xff;
 }
 
-static inline unsigned int get_cur_sas(
-                const struct kvmppc_vcpu_e500 *vcpu_e500)
+static inline unsigned int get_cur_sas(const struct kvm_vcpu *vcpu)
 {
-        return vcpu_e500->mas6 & 0x1;
+        return vcpu->arch.shared->mas6 & 0x1;
 }
 
-static inline unsigned int get_tlb_tlbsel(
-                const struct kvmppc_vcpu_e500 *vcpu_e500)
+static inline unsigned int get_tlb_tlbsel(const struct kvm_vcpu *vcpu)
 {
         /*
          * Manual says that tlbsel has 2 bits wide.
          * Since we only have two TLBs, only lower bit is used.
          */
-        return (vcpu_e500->mas0 >> 28) & 0x1;
-}
-
-static inline unsigned int get_tlb_nv_bit(
-                const struct kvmppc_vcpu_e500 *vcpu_e500)
-{
-        return vcpu_e500->mas0 & 0xfff;
+        return (vcpu->arch.shared->mas0 >> 28) & 0x1;
 }
 
-static inline unsigned int get_tlb_esel_bit(
-                const struct kvmppc_vcpu_e500 *vcpu_e500)
+static inline unsigned int get_tlb_nv_bit(const struct kvm_vcpu *vcpu)
 {
-        return (vcpu_e500->mas0 >> 16) & 0xfff;
+        return vcpu->arch.shared->mas0 & 0xfff;
 }
 
-static inline unsigned int get_tlb_esel(
-                const struct kvmppc_vcpu_e500 *vcpu_e500,
-                int tlbsel)
+static inline unsigned int get_tlb_esel_bit(const struct kvm_vcpu *vcpu)
 {
-        unsigned int esel = get_tlb_esel_bit(vcpu_e500);
-
-        if (tlbsel == 0) {
-                esel &= KVM_E500_TLB0_WAY_NUM_MASK;
-                esel |= ((vcpu_e500->mas2 >> 12) & KVM_E500_TLB0_WAY_SIZE_MASK)
-                                << KVM_E500_TLB0_WAY_NUM_BIT;
-        } else {
-                esel &= KVM_E500_TLB1_SIZE - 1;
-        }
-
-        return esel;
+        return (vcpu->arch.shared->mas0 >> 16) & 0xfff;
 }
 
 static inline int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
-                        const struct tlbe *tlbe)
+                        const struct kvm_book3e_206_tlb_entry *tlbe)
 {
         gpa_t gpa;
 
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 141dce3c681..968f4010188 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -13,6 +13,7 @@
  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
  * Copyright IBM Corp. 2007
+ * Copyright 2011 Freescale Semiconductor, Inc.
  *
  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  */
@@ -69,54 +70,55 @@
 #define OP_STH  44
 #define OP_STHU 45
 
-#ifdef CONFIG_PPC_BOOK3S
-static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
-{
-        return 1;
-}
-#else
-static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
-{
-        return vcpu->arch.tcr & TCR_DIE;
-}
-#endif
-
 void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
 {
         unsigned long dec_nsec;
+        unsigned long long dec_time;
 
         pr_debug("mtDEC: %x\n", vcpu->arch.dec);
+        hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
+
 #ifdef CONFIG_PPC_BOOK3S
         /* mtdec lowers the interrupt line when positive. */
         kvmppc_core_dequeue_dec(vcpu);
 
         /* POWER4+ triggers a dec interrupt if the value is < 0 */
         if (vcpu->arch.dec & 0x80000000) {
-                hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
                 kvmppc_core_queue_dec(vcpu);
                 return;
         }
 #endif
-        if (kvmppc_dec_enabled(vcpu)) {
-                /* The decrementer ticks at the same rate as the timebase, so
-                 * that's how we convert the guest DEC value to the number of
-                 * host ticks. */
-
-                hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
-                dec_nsec = vcpu->arch.dec;
-                dec_nsec *= 1000;
-                dec_nsec /= tb_ticks_per_usec;
-                hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
-                              HRTIMER_MODE_REL);
-                vcpu->arch.dec_jiffies = get_tb();
-        } else {
-                hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
-        }
+
+#ifdef CONFIG_BOOKE
+        /* On BOOKE, DEC = 0 is as good as decrementer not enabled */
+        if (vcpu->arch.dec == 0)
+                return;
+#endif
+
+        /*
+         * The decrementer ticks at the same rate as the timebase, so
+         * that's how we convert the guest DEC value to the number of
+         * host ticks.
+         */
+
+        dec_time = vcpu->arch.dec;
+        dec_time *= 1000;
+        do_div(dec_time, tb_ticks_per_usec);
+        dec_nsec = do_div(dec_time, NSEC_PER_SEC);
+        hrtimer_start(&vcpu->arch.dec_timer,
+                ktime_set(dec_time, dec_nsec), HRTIMER_MODE_REL);
+        vcpu->arch.dec_jiffies = get_tb();
 }
 
 u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb)
 {
         u64 jd = tb - vcpu->arch.dec_jiffies;
+
+#ifdef CONFIG_BOOKE
+        if (vcpu->arch.dec < jd)
+                return 0;
+#endif
+
         return vcpu->arch.dec - jd;
 }
 
@@ -159,7 +161,8 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
         case OP_TRAP_64:
                 kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
 #else
-                kvmppc_core_queue_program(vcpu, vcpu->arch.esr | ESR_PTR);
+                kvmppc_core_queue_program(vcpu,
+                                          vcpu->arch.shared->esr | ESR_PTR);
 #endif
                 advance = 0;
                 break;
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 607fbdf24b8..00d7e345b3f 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -39,7 +39,8 @@
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
 {
         return !(v->arch.shared->msr & MSR_WE) ||
-               !!(v->arch.pending_exceptions);
+               !!(v->arch.pending_exceptions) ||
+               v->requests;
 }
 
 int kvmppc_kvm_pv(struct kvm_vcpu *vcpu)
@@ -66,7 +67,7 @@ int kvmppc_kvm_pv(struct kvm_vcpu *vcpu)
                 vcpu->arch.magic_page_pa = param1;
                 vcpu->arch.magic_page_ea = param2;
 
-                r2 = KVM_MAGIC_FEAT_SR;
+                r2 = KVM_MAGIC_FEAT_SR | KVM_MAGIC_FEAT_MAS0_TO_SPRG7;
 
                 r = HC_EV_SUCCESS;
                 break;
@@ -171,8 +172,11 @@ void kvm_arch_check_processor_compat(void *rtn)
         *(int *)rtn = kvmppc_core_check_processor_compat();
 }
 
-int kvm_arch_init_vm(struct kvm *kvm)
+int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 {
+        if (type)
+                return -EINVAL;
+
         return kvmppc_core_init_vm(kvm);
 }
 
@@ -208,17 +212,22 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_PPC_BOOKE_SREGS:
 #else
         case KVM_CAP_PPC_SEGSTATE:
+        case KVM_CAP_PPC_HIOR:
         case KVM_CAP_PPC_PAPR:
 #endif
         case KVM_CAP_PPC_UNSET_IRQ:
         case KVM_CAP_PPC_IRQ_LEVEL:
         case KVM_CAP_ENABLE_CAP:
+        case KVM_CAP_ONE_REG:
                 r = 1;
                 break;
 #ifndef CONFIG_KVM_BOOK3S_64_HV
         case KVM_CAP_PPC_PAIRED_SINGLES:
         case KVM_CAP_PPC_OSI:
         case KVM_CAP_PPC_GET_PVINFO:
+#ifdef CONFIG_KVM_E500
+        case KVM_CAP_SW_TLB:
+#endif
                 r = 1;
                 break;
         case KVM_CAP_COALESCED_MMIO:
@@ -238,7 +247,26 @@ int kvm_dev_ioctl_check_extension(long ext)
                 if (cpu_has_feature(CPU_FTR_ARCH_201))
                         r = 2;
                 break;
+        case KVM_CAP_SYNC_MMU:
+                r = cpu_has_feature(CPU_FTR_ARCH_206) ? 1 : 0;
+                break;
 #endif
+        case KVM_CAP_NR_VCPUS:
+                /*
+                 * Recommending a number of CPUs is somewhat arbitrary; we
+                 * return the number of present CPUs for -HV (since a host
+                 * will have secondary threads "offline"), and for other KVM
+                 * implementations just count online CPUs.
+                 */
+#ifdef CONFIG_KVM_BOOK3S_64_HV
+                r = num_present_cpus();
+#else
+                r = num_online_cpus();
+#endif
+                break;
+        case KVM_CAP_MAX_VCPUS:
+                r = KVM_MAX_VCPUS;
+                break;
         default:
                 r = 0;
                 break;
@@ -253,6 +281,16 @@ long kvm_arch_dev_ioctl(struct file *filp,
         return -EINVAL;
 }
 
+void kvm_arch_free_memslot(struct kvm_memory_slot *free,
+                           struct kvm_memory_slot *dont)
+{
+}
+
+int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
+{
+        return 0;
+}
+
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                    struct kvm_memory_slot *memslot,
                                    struct kvm_memory_slot old,
@@ -279,9 +317,10 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 {
         struct kvm_vcpu *vcpu;
         vcpu = kvmppc_core_vcpu_create(kvm, id);
-        vcpu->arch.wqp = &vcpu->wq;
-        if (!IS_ERR(vcpu))
+        if (!IS_ERR(vcpu)) {
+                vcpu->arch.wqp = &vcpu->wq;
                 kvmppc_create_vcpu_debugfs(vcpu, id);
+        }
         return vcpu;
 }
 
@@ -305,18 +344,6 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
         return kvmppc_core_pending_dec(vcpu);
 }
 
-static void kvmppc_decrementer_func(unsigned long data)
-{
-        struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
-
-        kvmppc_core_queue_dec(vcpu);
-
-        if (waitqueue_active(vcpu->arch.wqp)) {
-                wake_up_interruptible(vcpu->arch.wqp);
-                vcpu->stat.halt_wakeup++;
-        }
-}
-
 /*
  * low level hrtimer wake routine. Because this runs in hardirq context
  * we schedule a tasklet to do the real work.
@@ -431,20 +458,20 @@ static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu,
 
         kvmppc_set_gpr(vcpu, vcpu->arch.io_gpr, gpr);
 
-        switch (vcpu->arch.io_gpr & KVM_REG_EXT_MASK) {
-        case KVM_REG_GPR:
+        switch (vcpu->arch.io_gpr & KVM_MMIO_REG_EXT_MASK) {
+        case KVM_MMIO_REG_GPR:
                 kvmppc_set_gpr(vcpu, vcpu->arch.io_gpr, gpr);
                 break;
-        case KVM_REG_FPR:
-                vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr;
+        case KVM_MMIO_REG_FPR:
+                vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
                 break;
 #ifdef CONFIG_PPC_BOOK3S
-        case KVM_REG_QPR:
-                vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr;
+        case KVM_MMIO_REG_QPR:
+                vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
                 break;
-        case KVM_REG_FQPR:
-                vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr;
-                vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_REG_MASK] = gpr;
+        case KVM_MMIO_REG_FQPR:
+                vcpu->arch.fpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
+                vcpu->arch.qpr[vcpu->arch.io_gpr & KVM_MMIO_REG_MASK] = gpr;
                 break;
 #endif
         default:
@@ -553,8 +580,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
                 vcpu->arch.hcall_needed = 0;
         }
 
-        kvmppc_core_deliver_interrupts(vcpu);
-
         r = kvmppc_vcpu_run(run, vcpu);
 
         if (vcpu->sigset_active)
@@ -563,6 +588,21 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
         return r;
 }
 
+void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
+{
+        int me;
+        int cpu = vcpu->cpu;
+
+        me = get_cpu();
+        if (waitqueue_active(vcpu->arch.wqp)) {
+                wake_up_interruptible(vcpu->arch.wqp);
+                vcpu->stat.halt_wakeup++;
+        } else if (cpu != me && cpu != -1) {
+                smp_send_reschedule(vcpu->cpu);
+        }
+        put_cpu();
+}
+
 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq)
 {
         if (irq->irq == KVM_INTERRUPT_UNSET) {
@@ -571,13 +611,7 @@ int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq)
         }
 
         kvmppc_core_queue_external(vcpu, irq);
-
-        if (waitqueue_active(vcpu->arch.wqp)) {
-                wake_up_interruptible(vcpu->arch.wqp);
-                vcpu->stat.halt_wakeup++;
-        } else if (vcpu->cpu != -1) {
-                smp_send_reschedule(vcpu->cpu);
-        }
+        kvm_vcpu_kick(vcpu);
 
         return 0;
 }
@@ -599,6 +633,19 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
                 r = 0;
                 vcpu->arch.papr_enabled = true;
                 break;
+#ifdef CONFIG_KVM_E500
+        case KVM_CAP_SW_TLB: {
+                struct kvm_config_tlb cfg;
+                void __user *user_ptr = (void __user *)(uintptr_t)cap->args[0];
+
+                r = -EFAULT;
+                if (copy_from_user(&cfg, user_ptr, sizeof(cfg)))
+                        break;
+
+                r = kvm_vcpu_ioctl_config_tlb(vcpu, &cfg);
+                break;
+        }
+#endif
         default:
                 r = -EINVAL;
                 break;
@@ -648,6 +695,32 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
                 break;
         }
+
+        case KVM_SET_ONE_REG:
+        case KVM_GET_ONE_REG:
+        {
+                struct kvm_one_reg reg;
+                r = -EFAULT;
+                if (copy_from_user(&reg, argp, sizeof(reg)))
+                        goto out;
+                if (ioctl == KVM_SET_ONE_REG)
+                        r = kvm_vcpu_ioctl_set_one_reg(vcpu, &reg);
+                else
+                        r = kvm_vcpu_ioctl_get_one_reg(vcpu, &reg);
+                break;
+        }
+
+#ifdef CONFIG_KVM_E500
+        case KVM_DIRTY_TLB: {
+                struct kvm_dirty_tlb dirty;
+                r = -EFAULT;
+                if (copy_from_user(&dirty, argp, sizeof(dirty)))
+                        goto out;
+                r = kvm_vcpu_ioctl_dirty_tlb(vcpu, &dirty);
+                break;
+        }
+#endif
+
         default:
                 r = -EINVAL;
         }
@@ -656,6 +729,11 @@ out:
         return r;
 }
 
+int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
+{
+        return VM_FAULT_SIGBUS;
+}
+
 static int kvm_vm_ioctl_get_pvinfo(struct kvm_ppc_pvinfo *pvinfo)
 {
         u32 inst_lis = 0x3c000000;
diff --git a/arch/powerpc/kvm/trace.h b/arch/powerpc/kvm/trace.h
index b135d3d397d..877186b7b1c 100644
--- a/arch/powerpc/kvm/trace.h
+++ b/arch/powerpc/kvm/trace.h
@@ -118,11 +118,14 @@ TRACE_EVENT(kvm_book3s_exit,
         ),
 
         TP_fast_assign(
+                struct kvmppc_book3s_shadow_vcpu *svcpu;
                 __entry->exit_nr        = exit_nr;
                 __entry->pc             = kvmppc_get_pc(vcpu);
                 __entry->dar            = kvmppc_get_fault_dar(vcpu);
                 __entry->msr            = vcpu->arch.shared->msr;
-                __entry->srr1           = to_svcpu(vcpu)->shadow_srr1;
+                svcpu = svcpu_get(vcpu);
+                __entry->srr1           = svcpu->shadow_srr1;
+                svcpu_put(svcpu);
         ),
 
         TP_printk("exit=0x%x | pc=0x%lx | msr=0x%lx | dar=0x%lx | srr1=0x%lx",
@@ -337,6 +340,63 @@ TRACE_EVENT(kvm_book3s_slbmte,
 
 #endif /* CONFIG_PPC_BOOK3S */
 
+
+/*************************************************************************
+ *                         Book3E trace points                           *
+ *************************************************************************/
+
+#ifdef CONFIG_BOOKE
+
+TRACE_EVENT(kvm_booke206_stlb_write,
+        TP_PROTO(__u32 mas0, __u32 mas8, __u32 mas1, __u64 mas2, __u64 mas7_3),
+        TP_ARGS(mas0, mas8, mas1, mas2, mas7_3),
+
+        TP_STRUCT__entry(
+                __field(        __u32,  mas0            )
+                __field(        __u32,  mas8            )
+                __field(        __u32,  mas1            )
+                __field(        __u64,  mas2            )
+                __field(        __u64,  mas7_3          )
+        ),
+
+        TP_fast_assign(
+                __entry->mas0           = mas0;
+                __entry->mas8           = mas8;
+                __entry->mas1           = mas1;
+                __entry->mas2           = mas2;
+                __entry->mas7_3         = mas7_3;
+        ),
+
+        TP_printk("mas0=%x mas8=%x mas1=%x mas2=%llx mas7_3=%llx",
+                __entry->mas0, __entry->mas8, __entry->mas1,
+                __entry->mas2, __entry->mas7_3)
+);
+
+TRACE_EVENT(kvm_booke206_gtlb_write,
+        TP_PROTO(__u32 mas0, __u32 mas1, __u64 mas2, __u64 mas7_3),
+        TP_ARGS(mas0, mas1, mas2, mas7_3),
+
+        TP_STRUCT__entry(
+                __field(        __u32,  mas0            )
+                __field(        __u32,  mas1            )
+                __field(        __u64,  mas2            )
+                __field(        __u64,  mas7_3          )
+        ),
+
+        TP_fast_assign(
+                __entry->mas0           = mas0;
+                __entry->mas1           = mas1;
+                __entry->mas2           = mas2;
+                __entry->mas7_3         = mas7_3;
+        ),
+
+        TP_printk("mas0=%x mas1=%x mas2=%llx mas7_3=%llx",
+                __entry->mas0, __entry->mas1,
+                __entry->mas2, __entry->mas7_3)
+);
+
+#endif
+
 #endif /* _TRACE_KVM_H */
 
 /* This part must be outside protection */
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 57c7465e656..fb05b123218 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -12,6 +12,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/hugetlb.h>
+#include <linux/export.h>
 #include <linux/of_fdt.h>
 #include <linux/memblock.h>
 #include <linux/bootmem.h>
@@ -103,6 +104,7 @@ pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift
                 *shift = hugepd_shift(*hpdp);
         return hugepte_offset(hpdp, ea, pdshift);
 }
+EXPORT_SYMBOL_GPL(find_linux_pte_or_hugepte);
 
 pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
 {
@@ -310,7 +312,8 @@ void __init reserve_hugetlb_gpages(void)
         int i;
 
         strlcpy(cmdline, boot_command_line, COMMAND_LINE_SIZE);
-        parse_args("hugetlb gpages", cmdline, NULL, 0, &do_gpage_early_setup);
+        parse_args("hugetlb gpages", cmdline, NULL, 0, 0, 0,
+                        &do_gpage_early_setup);
 
         /*
          * Walk gpage list in reverse, allocating larger page sizes first.
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index c2e27ede07e..02aee03e713 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -116,14 +116,45 @@ static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
                 *addrp = mfspr(SPRN_SDAR);
 }
 
+static inline u32 perf_flags_from_msr(struct pt_regs *regs)
+{
+        if (regs->msr & MSR_PR)
+                return PERF_RECORD_MISC_USER;
+        if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
+                return PERF_RECORD_MISC_HYPERVISOR;
+        return PERF_RECORD_MISC_KERNEL;
+}
+
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
         unsigned long mmcra = regs->dsisr;
         unsigned long sihv = MMCRA_SIHV;
         unsigned long sipr = MMCRA_SIPR;
 
+        /* Not a PMU interrupt: Make up flags from regs->msr */
         if (TRAP(regs) != 0xf00)
-                return 0;       /* not a PMU interrupt */
+                return perf_flags_from_msr(regs);
+
+        /*
+         * If we don't support continuous sampling and this
+         * is not a marked event, same deal
+         */
+        if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) &&
+            !(mmcra & MMCRA_SAMPLE_ENABLE))
+                return perf_flags_from_msr(regs);
+
+        /*
+         * If we don't have flags in MMCRA, rather than using
+         * the MSR, we intuit the flags from the address in
+         * SIAR which should give slightly more reliable
+         * results
+         */
+        if (ppmu->flags & PPMU_NO_SIPR) {
+                unsigned long siar = mfspr(SPRN_SIAR);
+                if (siar >= PAGE_OFFSET)
+                        return PERF_RECORD_MISC_KERNEL;
+                return PERF_RECORD_MISC_USER;
+        }
 
         if (ppmu->flags & PPMU_ALT_SIPR) {
                 sihv = POWER6_MMCRA_SIHV;
@@ -1299,13 +1330,18 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
  */
 unsigned long perf_instruction_pointer(struct pt_regs *regs)
 {
-        unsigned long ip;
+        unsigned long mmcra = regs->dsisr;
 
+        /* Not a PMU interrupt */
         if (TRAP(regs) != 0xf00)
-                return regs->nip;       /* not a PMU interrupt */
+                return regs->nip;
+
+        /* Processor doesn't support sampling non marked events */
+        if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) &&
+            !(mmcra & MMCRA_SAMPLE_ENABLE))
+                return regs->nip;
 
-        ip = mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
-        return ip;
+        return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
 }
 
 static bool pmc_overflow(unsigned long val)
diff --git a/arch/powerpc/perf/power4-pmu.c b/arch/powerpc/perf/power4-pmu.c
index b4f1dda4d08..9103a1de864 100644
--- a/arch/powerpc/perf/power4-pmu.c
+++ b/arch/powerpc/perf/power4-pmu.c
@@ -607,6 +607,7 @@ static struct power_pmu power4_pmu = {
         .n_generic              = ARRAY_SIZE(p4_generic_events),
         .generic_events         = p4_generic_events,
         .cache_events           = &power4_cache_events,
+        .flags                  = PPMU_NO_SIPR | PPMU_NO_CONT_SAMPLING,
 };
 
 static int __init init_power4_pmu(void)
diff --git a/arch/powerpc/perf/ppc970-pmu.c b/arch/powerpc/perf/ppc970-pmu.c
index 111eb25bb0b..20139ceeacf 100644
--- a/arch/powerpc/perf/ppc970-pmu.c
+++ b/arch/powerpc/perf/ppc970-pmu.c
@@ -487,6 +487,7 @@ static struct power_pmu ppc970_pmu = {
         .n_generic              = ARRAY_SIZE(ppc970_generic_events),
         .generic_events         = ppc970_generic_events,
         .cache_events           = &ppc970_cache_events,
+        .flags                  = PPMU_NO_SIPR | PPMU_NO_CONT_SAMPLING,
 };
 
 static int __init init_ppc970_pmu(void)
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index 2516c1cf846..943c9d39aa1 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -95,7 +95,6 @@ static long beat_lpar_hpte_insert(unsigned long hpte_group,
         unsigned long lpar_rc;
         u64 hpte_v, hpte_r, slot;
 
-        /* same as iseries */
         if (vflags & HPTE_V_SECONDARY)
                 return -1;
 
@@ -319,7 +318,6 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
         unsigned long lpar_rc;
         u64 hpte_v, hpte_r, slot;
 
-        /* same as iseries */
         if (vflags & HPTE_V_SECONDARY)
                 return -1;
 
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index 401e3f3f74c..465ee8f5c08 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -620,7 +620,7 @@ void __init maple_pci_init(void)
         }
 
         /* Tell pci.c to not change any resource allocations.  */
-        pci_probe_only = 1;
+        pci_add_flags(PCI_PROBE_ONLY);
 }
 
 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/pasemi/pci.c
index b6a0ec45c69..aa862713258 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -229,9 +229,6 @@ void __init pas_pci_init(void)
 
         /* Setup the linkage between OF nodes and PHBs */
         pci_devs_phb_init();
-
-        /* Use the common resource allocation mechanism */
-        pci_probe_only = 1;
 }
 
 void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset)
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 31a7d3a7ce2..43bbe1bda93 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -1059,9 +1059,6 @@ void __init pmac_pci_init(void)
         }
         /* pmac_check_ht_link(); */
 
-        /* We can allocate missing resources if any */
-        pci_probe_only = 0;
-
 #else /* CONFIG_PPC64 */
         init_p2pbridge();
         init_second_ohare();
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 5e155dfc432..fbdd74dac3a 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1299,15 +1299,14 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         /* Setup MSI support */
         pnv_pci_init_ioda_msis(phb);
 
-        /* We set both probe_only and PCI_REASSIGN_ALL_RSRC. This is an
+        /* We set both PCI_PROBE_ONLY and PCI_REASSIGN_ALL_RSRC. This is an
          * odd combination which essentially means that we skip all resource
          * fixups and assignments in the generic code, and do it all
          * ourselves here
          */
-        pci_probe_only = 1;
         ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
-        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
+        pci_add_flags(PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC);
 
         /* Reset IODA tables to a clean state */
         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 214478d781a..be3cfc5ceab 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -562,10 +562,7 @@ void __init pnv_pci_init(void)
 {
         struct device_node *np;
 
-        pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
-
-        /* We do not want to just probe */
-        pci_probe_only = 0;
+        pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
 
         /* OPAL absent, try POPAL first then RTAS detection of PHBs */
         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 8011088392d..309d38ef732 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -984,7 +984,8 @@ int __exit eeh_ops_unregister(const char *name)
  */
 void __init eeh_init(void)
 {
-        struct device_node *phb, *np;
+        struct pci_controller *hose, *tmp;
+        struct device_node *phb;
         int ret;
 
         /* call platform initialization function */
@@ -1000,19 +1001,9 @@ void __init eeh_init(void)
 
         raw_spin_lock_init(&confirm_error_lock);
 
-        np = of_find_node_by_path("/rtas");
-        if (np == NULL)
-                return;
-
-        /* Enable EEH for all adapters.  Note that eeh requires buid's */
-        for (phb = of_find_node_by_name(NULL, "pci"); phb;
-             phb = of_find_node_by_name(phb, "pci")) {
-                unsigned long buid;
-
-                buid = get_phb_buid(phb);
-                if (buid == 0 || !of_node_to_eeh_dev(phb))
-                        continue;
-
+        /* Enable EEH for all adapters */
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+                phb = hose->dn;
                 traverse_pci_devices(phb, eeh_early_enable, NULL);
         }
 
diff --git a/arch/powerpc/platforms/pseries/eeh_dev.c b/arch/powerpc/platforms/pseries/eeh_dev.c
index f3aed7dcae9..c4507d09590 100644
--- a/arch/powerpc/platforms/pseries/eeh_dev.c
+++ b/arch/powerpc/platforms/pseries/eeh_dev.c
@@ -62,7 +62,7 @@ void * __devinit eeh_dev_init(struct device_node *dn, void *data)
         }
 
         /* Associate EEH device with OF node */
-        dn->edev  = edev;
+        PCI_DN(dn)->edev = edev;
         edev->dn  = dn;
         edev->phb = phb;
 
diff --git a/arch/powerpc/platforms/pseries/io_event_irq.c b/arch/powerpc/platforms/pseries/io_event_irq.c
index 1a709bc48ce..ef9d9d84c7d 100644
--- a/arch/powerpc/platforms/pseries/io_event_irq.c
+++ b/arch/powerpc/platforms/pseries/io_event_irq.c
@@ -63,73 +63,9 @@ EXPORT_SYMBOL_GPL(pseries_ioei_notifier_list);
 
 static int ioei_check_exception_token;
 
-/* pSeries event log format */
-
-/* Two bytes ASCII section IDs */
-#define PSERIES_ELOG_SECT_ID_PRIV_HDR           (('P' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_USER_HDR           (('U' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_PRIMARY_SRC        (('P' << 8) | 'S')
-#define PSERIES_ELOG_SECT_ID_EXTENDED_UH        (('E' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_FAILING_MTMS       (('M' << 8) | 'T')
-#define PSERIES_ELOG_SECT_ID_SECONDARY_SRC      (('S' << 8) | 'S')
-#define PSERIES_ELOG_SECT_ID_DUMP_LOCATOR       (('D' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_FW_ERROR           (('S' << 8) | 'W')
-#define PSERIES_ELOG_SECT_ID_IMPACT_PART_ID     (('L' << 8) | 'P')
-#define PSERIES_ELOG_SECT_ID_LOGIC_RESOURCE_ID  (('L' << 8) | 'R')
-#define PSERIES_ELOG_SECT_ID_HMC_ID             (('H' << 8) | 'M')
-#define PSERIES_ELOG_SECT_ID_EPOW               (('E' << 8) | 'P')
-#define PSERIES_ELOG_SECT_ID_IO_EVENT           (('I' << 8) | 'E')
-#define PSERIES_ELOG_SECT_ID_MANUFACT_INFO      (('M' << 8) | 'I')
-#define PSERIES_ELOG_SECT_ID_CALL_HOME          (('C' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_USER_DEF           (('U' << 8) | 'D')
-
-/* Vendor specific Platform Event Log Format, Version 6, section header */
-struct pseries_elog_section {
-        uint16_t id;                    /* 0x00 2-byte ASCII section ID */
-        uint16_t length;                /* 0x02 Section length in bytes */
-        uint8_t version;                /* 0x04 Section version         */
-        uint8_t subtype;                /* 0x05 Section subtype         */
-        uint16_t creator_component;     /* 0x06 Creator component ID    */
-        uint8_t data[];                 /* 0x08 Start of section data   */
-};
-
 static char ioei_rtas_buf[RTAS_DATA_BUF_SIZE] __cacheline_aligned;
 
 /**
- * Find data portion of a specific section in RTAS extended event log.
- * @elog: RTAS error/event log.
- * @sect_id: secsion ID.
- *
- * Return:
- *      pointer to the section data of the specified section
- *      NULL if not found
- */
-static struct pseries_elog_section *find_xelog_section(struct rtas_error_log *elog,
-                                                       uint16_t sect_id)
-{
-        struct rtas_ext_event_log_v6 *xelog =
-                (struct rtas_ext_event_log_v6 *) elog->buffer;
-        struct pseries_elog_section *sect;
-        unsigned char *p, *log_end;
-
-        /* Check that we understand the format */
-        if (elog->extended_log_length < sizeof(struct rtas_ext_event_log_v6) ||
-            xelog->log_format != RTAS_V6EXT_LOG_FORMAT_EVENT_LOG ||
-            xelog->company_id != RTAS_V6EXT_COMPANY_ID_IBM)
-                return NULL;
-
-        log_end = elog->buffer + elog->extended_log_length;
-        p = xelog->vendor_log;
-        while (p < log_end) {
-                sect = (struct pseries_elog_section *)p;
-                if (sect->id == sect_id)
-                        return sect;
-                p += sect->length;
-        }
-        return NULL;
-}
-
-/**
  * Find the data portion of an IO Event section from event log.
  * @elog: RTAS error/event log.
  *
@@ -138,7 +74,7 @@ static struct pseries_elog_section *find_xelog_section(struct rtas_error_log *el
  */
 static struct pseries_io_event * ioei_find_event(struct rtas_error_log *elog)
 {
-        struct pseries_elog_section *sect;
+        struct pseries_errorlog *sect;
 
         /* We should only ever get called for io-event interrupts, but if
          * we do get called for another type then something went wrong so
@@ -152,7 +88,7 @@ static struct pseries_io_event * ioei_find_event(struct rtas_error_log *elog)
                 return NULL;
         }
 
-        sect = find_xelog_section(elog, PSERIES_ELOG_SECT_ID_IO_EVENT);
+        sect = get_pseries_errorlog(elog, PSERIES_ELOG_SECT_ID_IO_EVENT);
         if (unlikely(!sect)) {
                 printk_once(KERN_WARNING "io_event_irq: RTAS extended event "
                             "log does not contain an IO Event section. "
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index c442f2b1980..0915b1ad66c 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -809,8 +809,7 @@ machine_arch_initcall(pseries, find_existing_ddw_windows);
 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
                         struct ddw_query_response *query)
 {
-        struct device_node *dn;
-        struct pci_dn *pcidn;
+        struct eeh_dev *edev;
         u32 cfg_addr;
         u64 buid;
         int ret;
@@ -821,12 +820,12 @@ static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
          * Retrieve them from the pci device, not the node with the
          * dma-window property
          */
-        dn = pci_device_to_OF_node(dev);
-        pcidn = PCI_DN(dn);
-        cfg_addr = pcidn->eeh_config_addr;
-        if (pcidn->eeh_pe_config_addr)
-                cfg_addr = pcidn->eeh_pe_config_addr;
-        buid = pcidn->phb->buid;
+        edev = pci_dev_to_eeh_dev(dev);
+        cfg_addr = edev->config_addr;
+        if (edev->pe_config_addr)
+                cfg_addr = edev->pe_config_addr;
+        buid = edev->phb->buid;
+
         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
@@ -839,8 +838,7 @@ static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
                         struct ddw_create_response *create, int page_shift,
                         int window_shift)
 {
-        struct device_node *dn;
-        struct pci_dn *pcidn;
+        struct eeh_dev *edev;
         u32 cfg_addr;
         u64 buid;
         int ret;
@@ -851,12 +849,11 @@ static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
          * Retrieve them from the pci device, not the node with the
          * dma-window property
          */
-        dn = pci_device_to_OF_node(dev);
-        pcidn = PCI_DN(dn);
-        cfg_addr = pcidn->eeh_config_addr;
-        if (pcidn->eeh_pe_config_addr)
-                cfg_addr = pcidn->eeh_pe_config_addr;
-        buid = pcidn->phb->buid;
+        edev = pci_dev_to_eeh_dev(dev);
+        cfg_addr = edev->config_addr;
+        if (edev->pe_config_addr)
+                cfg_addr = edev->pe_config_addr;
+        buid = edev->phb->buid;
 
         do {
                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index fbb21fc3080..8b7bafa489c 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -84,7 +84,7 @@ void pcibios_remove_pci_devices(struct pci_bus *bus)
         list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
                 pr_debug("     * Removing %s...\n", pci_name(dev));
                 eeh_remove_bus_device(dev);
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
         }
 }
 EXPORT_SYMBOL_GPL(pcibios_remove_pci_devices);
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 9e248ef6cc6..c4dfccd3a3d 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -16,36 +16,15 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
-/* Change Activity:
- * 2001/09/21 : engebret : Created with minimal EPOW and HW exception support.
- * End Change Activity
- */
-
-#include <linux/errno.h>
-#include <linux/threads.h>
-#include <linux/kernel_stat.h>
-#include <linux/signal.h>
 #include <linux/sched.h>
-#include <linux/ioport.h>
 #include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/init.h>
-#include <linux/delay.h>
 #include <linux/irq.h>
-#include <linux/random.h>
-#include <linux/sysrq.h>
-#include <linux/bitops.h>
-
-#include <asm/uaccess.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/irq.h>
-#include <asm/cache.h>
-#include <asm/prom.h>
-#include <asm/ptrace.h>
+#include <linux/of.h>
+#include <linux/fs.h>
+#include <linux/reboot.h>
+
 #include <asm/machdep.h>
 #include <asm/rtas.h>
-#include <asm/udbg.h>
 #include <asm/firmware.h>
 
 #include "pseries.h"
@@ -56,7 +35,6 @@ static DEFINE_SPINLOCK(ras_log_buf_lock);
 static char global_mce_data_buf[RTAS_ERROR_LOG_MAX];
 static DEFINE_PER_CPU(__u64, mce_data_buf);
 
-static int ras_get_sensor_state_token;
 static int ras_check_exception_token;
 
 #define EPOW_SENSOR_TOKEN       9
@@ -74,7 +52,6 @@ static int __init init_ras_IRQ(void)
 {
         struct device_node *np;
 
-        ras_get_sensor_state_token = rtas_token("get-sensor-state");
         ras_check_exception_token = rtas_token("check-exception");
 
         /* Internal Errors */
@@ -94,26 +71,126 @@ static int __init init_ras_IRQ(void)
 
         return 0;
 }
-__initcall(init_ras_IRQ);
+subsys_initcall(init_ras_IRQ);
 
-/*
- * Handle power subsystem events (EPOW).
- *
- * Presently we just log the event has occurred.  This should be fixed
- * to examine the type of power failure and take appropriate action where
- * the time horizon permits something useful to be done.
- */
+#define EPOW_SHUTDOWN_NORMAL                            1
+#define EPOW_SHUTDOWN_ON_UPS                            2
+#define EPOW_SHUTDOWN_LOSS_OF_CRITICAL_FUNCTIONS        3
+#define EPOW_SHUTDOWN_AMBIENT_TEMPERATURE_TOO_HIGH      4
+
+static void handle_system_shutdown(char event_modifier)
+{
+        switch (event_modifier) {
+        case EPOW_SHUTDOWN_NORMAL:
+                pr_emerg("Firmware initiated power off");
+                orderly_poweroff(1);
+                break;
+
+        case EPOW_SHUTDOWN_ON_UPS:
+                pr_emerg("Loss of power reported by firmware, system is "
+                        "running on UPS/battery");
+                break;
+
+        case EPOW_SHUTDOWN_LOSS_OF_CRITICAL_FUNCTIONS:
+                pr_emerg("Loss of system critical functions reported by "
+                        "firmware");
+                pr_emerg("Check RTAS error log for details");
+                orderly_poweroff(1);
+                break;
+
+        case EPOW_SHUTDOWN_AMBIENT_TEMPERATURE_TOO_HIGH:
+                pr_emerg("Ambient temperature too high reported by firmware");
+                pr_emerg("Check RTAS error log for details");
+                orderly_poweroff(1);
+                break;
+
+        default:
+                pr_err("Unknown power/cooling shutdown event (modifier %d)",
+                        event_modifier);
+        }
+}
+
+struct epow_errorlog {
+        unsigned char sensor_value;
+        unsigned char event_modifier;
+        unsigned char extended_modifier;
+        unsigned char reserved;
+        unsigned char platform_reason;
+};
+
+#define EPOW_RESET                      0
+#define EPOW_WARN_COOLING               1
+#define EPOW_WARN_POWER                 2
+#define EPOW_SYSTEM_SHUTDOWN            3
+#define EPOW_SYSTEM_HALT                4
+#define EPOW_MAIN_ENCLOSURE             5
+#define EPOW_POWER_OFF                  7
+
+void rtas_parse_epow_errlog(struct rtas_error_log *log)
+{
+        struct pseries_errorlog *pseries_log;
+        struct epow_errorlog *epow_log;
+        char action_code;
+        char modifier;
+
+        pseries_log = get_pseries_errorlog(log, PSERIES_ELOG_SECT_ID_EPOW);
+        if (pseries_log == NULL)
+                return;
+
+        epow_log = (struct epow_errorlog *)pseries_log->data;
+        action_code = epow_log->sensor_value & 0xF;     /* bottom 4 bits */
+        modifier = epow_log->event_modifier & 0xF;      /* bottom 4 bits */
+
+        switch (action_code) {
+        case EPOW_RESET:
+                pr_err("Non critical power or cooling issue cleared");
+                break;
+
+        case EPOW_WARN_COOLING:
+                pr_err("Non critical cooling issue reported by firmware");
+                pr_err("Check RTAS error log for details");
+                break;
+
+        case EPOW_WARN_POWER:
+                pr_err("Non critical power issue reported by firmware");
+                pr_err("Check RTAS error log for details");
+                break;
+
+        case EPOW_SYSTEM_SHUTDOWN:
+                handle_system_shutdown(epow_log->event_modifier);
+                break;
+
+        case EPOW_SYSTEM_HALT:
+                pr_emerg("Firmware initiated power off");
+                orderly_poweroff(1);
+                break;
+
+        case EPOW_MAIN_ENCLOSURE:
+        case EPOW_POWER_OFF:
+                pr_emerg("Critical power/cooling issue reported by firmware");
+                pr_emerg("Check RTAS error log for details");
+                pr_emerg("Immediate power off");
+                emergency_sync();
+                kernel_power_off();
+                break;
+
+        default:
+                pr_err("Unknown power/cooling event (action code %d)",
+                        action_code);
+        }
+}
+
+/* Handle environmental and power warning (EPOW) interrupts. */
 static irqreturn_t ras_epow_interrupt(int irq, void *dev_id)
 {
-        int status = 0xdeadbeef;
-        int state = 0;
+        int status;
+        int state;
         int critical;
 
-        status = rtas_call(ras_get_sensor_state_token, 2, 2, &state,
-                           EPOW_SENSOR_TOKEN, EPOW_SENSOR_INDEX);
+        status = rtas_get_sensor(EPOW_SENSOR_TOKEN, EPOW_SENSOR_INDEX, &state);
 
         if (state > 3)
-                critical = 1;  /* Time Critical */
+                critical = 1;           /* Time Critical */
         else
                 critical = 0;
 
@@ -122,18 +199,14 @@ static irqreturn_t ras_epow_interrupt(int irq, void *dev_id)
         status = rtas_call(ras_check_exception_token, 6, 1, NULL,
                            RTAS_VECTOR_EXTERNAL_INTERRUPT,
                            virq_to_hw(irq),
-                           RTAS_EPOW_WARNING | RTAS_POWERMGM_EVENTS,
+                           RTAS_EPOW_WARNING,
                            critical, __pa(&ras_log_buf),
                                 rtas_get_error_log_max());
 
-        udbg_printf("EPOW <0x%lx 0x%x 0x%x>\n",
-                    *((unsigned long *)&ras_log_buf), status, state);
-        printk(KERN_WARNING "EPOW <0x%lx 0x%x 0x%x>\n",
-               *((unsigned long *)&ras_log_buf), status, state);
-
-        /* format and print the extended information */
         log_error(ras_log_buf, ERR_TYPE_RTAS_LOG, 0);
 
+        rtas_parse_epow_errlog((struct rtas_error_log *)ras_log_buf);
+
         spin_unlock(&ras_log_buf_lock);
         return IRQ_HANDLED;
 }
@@ -149,7 +222,7 @@ static irqreturn_t ras_epow_interrupt(int irq, void *dev_id)
 static irqreturn_t ras_error_interrupt(int irq, void *dev_id)
 {
         struct rtas_error_log *rtas_elog;
-        int status = 0xdeadbeef;
+        int status;
         int fatal;
 
         spin_lock(&ras_log_buf_lock);
@@ -157,7 +230,7 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id)
         status = rtas_call(ras_check_exception_token, 6, 1, NULL,
                            RTAS_VECTOR_EXTERNAL_INTERRUPT,
                            virq_to_hw(irq),
-                           RTAS_INTERNAL_ERROR, 1 /*Time Critical */,
+                           RTAS_INTERNAL_ERROR, 1 /* Time Critical */,
                            __pa(&ras_log_buf),
                                 rtas_get_error_log_max());
 
@@ -172,24 +245,13 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id)
         log_error(ras_log_buf, ERR_TYPE_RTAS_LOG, fatal);
 
         if (fatal) {
-                udbg_printf("Fatal HW Error <0x%lx 0x%x>\n",
-                            *((unsigned long *)&ras_log_buf), status);
-                printk(KERN_EMERG "Error: Fatal hardware error <0x%lx 0x%x>\n",
-                       *((unsigned long *)&ras_log_buf), status);
-
-#ifndef DEBUG_RTAS_POWER_OFF
-                /* Don't actually power off when debugging so we can test
-                 * without actually failing while injecting errors.
-                 * Error data will not be logged to syslog.
-                 */
-                ppc_md.power_off();
-#endif
+                pr_emerg("Fatal hardware error reported by firmware");
+                pr_emerg("Check RTAS error log for details");
+                pr_emerg("Immediate power off");
+                emergency_sync();
+                kernel_power_off();
         } else {
-                udbg_printf("Recoverable HW Error <0x%lx 0x%x>\n",
-                            *((unsigned long *)&ras_log_buf), status);
-                printk(KERN_WARNING
-                       "Warning: Recoverable hardware error <0x%lx 0x%x>\n",
-                       *((unsigned long *)&ras_log_buf), status);
+                pr_err("Recoverable hardware error reported by firmware");
         }
 
         spin_unlock(&ras_log_buf_lock);
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 8f137af616a..51ecac920dd 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -383,6 +383,9 @@ static void __init pSeries_setup_arch(void)
 
         fwnmi_init();
 
+        /* By default, only probe PCI (can be overriden by rtas_pci) */
+        pci_add_flags(PCI_PROBE_ONLY);
+
         /* Find and initialize PCI host bridges */
         init_pci_config_tokens();
         eeh_pseries_init();
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.c b/arch/powerpc/platforms/wsp/wsp_pci.c
index 386879412e9..1526551f9fe 100644
--- a/arch/powerpc/platforms/wsp/wsp_pci.c
+++ b/arch/powerpc/platforms/wsp/wsp_pci.c
@@ -683,7 +683,6 @@ static int __init wsp_setup_one_phb(struct device_node *np)
         /* XXX Force re-assigning of everything for now */
         pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC |
                       PCI_ENABLE_PROC_DOMAINS);
-        pci_probe_only = 0;
 
         /* Calculate how the TCE space is divided */
         phb->dma32_base         = 0;
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index af3780e52e7..6845e91ba04 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -22,6 +22,7 @@
 
 #include <linux/stddef.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "nonstdio.h"
 #include "ppc.h"
 
diff --git a/arch/powerpc/xmon/spu-opc.c b/arch/powerpc/xmon/spu-opc.c
index 530df3d6d7b..7d37597c4bc 100644
--- a/arch/powerpc/xmon/spu-opc.c
+++ b/arch/powerpc/xmon/spu-opc.c
@@ -19,6 +19,7 @@
    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "spu.h"
 
 /* This file holds the Spu opcode table */
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 6d99a5fcc09..465d5be1f0f 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -64,6 +64,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 config S390
         def_bool y
         select USE_GENERIC_SMP_HELPERS if SMP
+        select GENERIC_CPU_DEVICES if !SMP
         select HAVE_SYSCALL_WRAPPERS
         select HAVE_FUNCTION_TRACER
         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
diff --git a/arch/s390/include/asm/cpu_mf.h b/arch/s390/include/asm/cpu_mf.h
new file mode 100644
index 00000000000..e49db5d5d06
--- /dev/null
+++ b/arch/s390/include/asm/cpu_mf.h
@@ -0,0 +1,95 @@
+/*
+ * CPU-measurement facilities
+ *
+ *  Copyright IBM Corp. 2012
+ *  Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
+ *             Jan Glauber <jang@linux.vnet.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ */
+#ifndef _ASM_S390_CPU_MF_H
+#define _ASM_S390_CPU_MF_H
+
+#define CPU_MF_INT_SF_IAE       (1 << 31)       /* invalid entry address */
+#define CPU_MF_INT_SF_ISE       (1 << 30)       /* incorrect SDBT entry */
+#define CPU_MF_INT_SF_PRA       (1 << 29)       /* program request alert */
+#define CPU_MF_INT_SF_SACA      (1 << 23)       /* sampler auth. change alert */
+#define CPU_MF_INT_SF_LSDA      (1 << 22)       /* loss of sample data alert */
+#define CPU_MF_INT_CF_CACA      (1 <<  7)       /* counter auth. change alert */
+#define CPU_MF_INT_CF_LCDA      (1 <<  6)       /* loss of counter data alert */
+
+#define CPU_MF_INT_CF_MASK      (CPU_MF_INT_CF_CACA|CPU_MF_INT_CF_LCDA)
+#define CPU_MF_INT_SF_MASK      (CPU_MF_INT_SF_IAE|CPU_MF_INT_SF_ISE|   \
+                                 CPU_MF_INT_SF_PRA|CPU_MF_INT_SF_SACA|  \
+                                 CPU_MF_INT_SF_LSDA)
+
+/* CPU measurement facility support */
+static inline int cpum_cf_avail(void)
+{
+        return MACHINE_HAS_SPP && test_facility(67);
+}
+
+static inline int cpum_sf_avail(void)
+{
+        return MACHINE_HAS_SPP && test_facility(68);
+}
+
+
+struct cpumf_ctr_info {
+        u16   cfvn;
+        u16   auth_ctl;
+        u16   enable_ctl;
+        u16   act_ctl;
+        u16   max_cpu;
+        u16   csvn;
+        u16   max_cg;
+        u16   reserved1;
+        u32   reserved2[12];
+} __packed;
+
+/* Query counter information */
+static inline int qctri(struct cpumf_ctr_info *info)
+{
+        int rc = -EINVAL;
+
+        asm volatile (
+                "0:     .insn   s,0xb28e0000,%1\n"
+                "1:     lhi     %0,0\n"
+                "2:\n"
+                EX_TABLE(1b, 2b)
+                : "+d" (rc), "=Q" (*info));
+        return rc;
+}
+
+/* Load CPU-counter-set controls */
+static inline int lcctl(u64 ctl)
+{
+        int cc;
+
+        asm volatile (
+                "       .insn   s,0xb2840000,%1\n"
+                "       ipm     %0\n"
+                "       srl     %0,28\n"
+                : "=d" (cc) : "m" (ctl) : "cc");
+        return cc;
+}
+
+/* Extract CPU counter */
+static inline int ecctr(u64 ctr, u64 *val)
+{
+        register u64 content asm("4") = 0;
+        int cc;
+
+        asm volatile (
+                "       .insn   rre,0xb2e40000,%0,%2\n"
+                "       ipm     %1\n"
+                "       srl     %1,28\n"
+                : "=d" (content), "=d" (cc) : "d" (ctr) : "cc");
+        if (!cc)
+                *val = content;
+        return cc;
+}
+
+#endif /* _ASM_S390_CPU_MF_H */
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
index acee1806f61..5289cacd486 100644
--- a/arch/s390/include/asm/irq.h
+++ b/arch/s390/include/asm/irq.h
@@ -45,5 +45,7 @@ int register_external_interrupt(u16 code, ext_int_handler_t handler);
 int unregister_external_interrupt(u16 code, ext_int_handler_t handler);
 void service_subclass_irq_register(void);
 void service_subclass_irq_unregister(void);
+void measurement_alert_subclass_register(void);
+void measurement_alert_subclass_unregister(void);
 
 #endif /* _ASM_IRQ_H */
diff --git a/arch/s390/include/asm/kvm.h b/arch/s390/include/asm/kvm.h
index 82b32a100c7..96076676e22 100644
--- a/arch/s390/include/asm/kvm.h
+++ b/arch/s390/include/asm/kvm.h
@@ -41,4 +41,15 @@ struct kvm_debug_exit_arch {
 struct kvm_guest_debug_arch {
 };
 
+#define KVM_SYNC_PREFIX (1UL << 0)
+#define KVM_SYNC_GPRS   (1UL << 1)
+#define KVM_SYNC_ACRS   (1UL << 2)
+#define KVM_SYNC_CRS    (1UL << 3)
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+        __u64 prefix;   /* prefix register */
+        __u64 gprs[16]; /* general purpose registers */
+        __u32 acrs[16]; /* access registers */
+        __u64 crs[16];  /* control registers */
+};
 #endif
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index b0c235cb6ad..7343872890a 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -220,18 +220,17 @@ struct kvm_s390_float_interrupt {
         struct list_head list;
         atomic_t active;
         int next_rr_cpu;
-        unsigned long idle_mask [(64 + sizeof(long) - 1) / sizeof(long)];
-        struct kvm_s390_local_interrupt *local_int[64];
+        unsigned long idle_mask[(KVM_MAX_VCPUS + sizeof(long) - 1)
+                                / sizeof(long)];
+        struct kvm_s390_local_interrupt *local_int[KVM_MAX_VCPUS];
 };
 
 
 struct kvm_vcpu_arch {
         struct kvm_s390_sie_block *sie_block;
-        unsigned long     guest_gprs[16];
         s390_fp_regs      host_fpregs;
         unsigned int      host_acrs[NUM_ACRS];
         s390_fp_regs      guest_fpregs;
-        unsigned int      guest_acrs[NUM_ACRS];
         struct kvm_s390_local_interrupt local_int;
         struct hrtimer    ckc_timer;
         struct tasklet_struct tasklet;
@@ -246,6 +245,9 @@ struct kvm_vm_stat {
         u32 remote_tlb_flush;
 };
 
+struct kvm_arch_memory_slot {
+};
+
 struct kvm_arch{
         struct sca_block *sca;
         debug_info_t *dbf;
@@ -253,5 +255,5 @@ struct kvm_arch{
         struct gmap *gmap;
 };
 
-extern int sie64a(struct kvm_s390_sie_block *, unsigned long *);
+extern int sie64a(struct kvm_s390_sie_block *, u64 *);
 #endif
diff --git a/arch/s390/include/asm/perf_event.h b/arch/s390/include/asm/perf_event.h
index 4eb444edbe4..7941968e12b 100644
--- a/arch/s390/include/asm/perf_event.h
+++ b/arch/s390/include/asm/perf_event.h
@@ -1,8 +1,16 @@
 /*
  * Performance event support - s390 specific definitions.
  *
- * Copyright 2009 Martin Schwidefsky, IBM Corporation.
+ * Copyright IBM Corp. 2009, 2012
+ * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
+ *            Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
  */
 
-/* Empty, just to avoid compiling error */
+#include <asm/cpu_mf.h>
 
+/* CPU-measurement counter facility */
+#define PERF_CPUM_CF_MAX_CTR            160
+
+/* Per-CPU flags for PMU states */
+#define PMU_F_RESERVED                  0x1000
+#define PMU_F_ENABLED                   0x2000
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 16b0b433f1f..884b18afc86 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
 obj-$(CONFIG_FTRACE_SYSCALLS)  += ftrace.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
+obj-$(CONFIG_PERF_EVENTS)       += perf_event.o perf_cpum_cf.o
 
 # Kexec part
 S390_KEXEC_OBJS := machine_kexec.o crash.o
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index 2429ecd6887..1c2cdd59ccd 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -255,3 +255,26 @@ void service_subclass_irq_unregister(void)
         spin_unlock(&sc_irq_lock);
 }
 EXPORT_SYMBOL(service_subclass_irq_unregister);
+
+static DEFINE_SPINLOCK(ma_subclass_lock);
+static int ma_subclass_refcount;
+
+void measurement_alert_subclass_register(void)
+{
+        spin_lock(&ma_subclass_lock);
+        if (!ma_subclass_refcount)
+                ctl_set_bit(0, 5);
+        ma_subclass_refcount++;
+        spin_unlock(&ma_subclass_lock);
+}
+EXPORT_SYMBOL(measurement_alert_subclass_register);
+
+void measurement_alert_subclass_unregister(void)
+{
+        spin_lock(&ma_subclass_lock);
+        ma_subclass_refcount--;
+        if (!ma_subclass_refcount)
+                ctl_clear_bit(0, 5);
+        spin_unlock(&ma_subclass_lock);
+}
+EXPORT_SYMBOL(measurement_alert_subclass_unregister);
diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c
new file mode 100644
index 00000000000..8481ecf2ad7
--- /dev/null
+++ b/arch/s390/kernel/perf_cpum_cf.c
@@ -0,0 +1,690 @@
+/*
+ * Performance event support for s390x - CPU-measurement Counter Facility
+ *
+ *  Copyright IBM Corp. 2012
+ *  Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ */
+#define KMSG_COMPONENT  "cpum_cf"
+#define pr_fmt(fmt)     KMSG_COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/kernel_stat.h>
+#include <linux/perf_event.h>
+#include <linux/percpu.h>
+#include <linux/notifier.h>
+#include <linux/init.h>
+#include <linux/export.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/cpu_mf.h>
+
+/* CPU-measurement counter facility supports these CPU counter sets:
+ * For CPU counter sets:
+ *    Basic counter set:             0-31
+ *    Problem-state counter set:    32-63
+ *    Crypto-activity counter set:  64-127
+ *    Extented counter set:        128-159
+ */
+enum cpumf_ctr_set {
+        /* CPU counter sets */
+        CPUMF_CTR_SET_BASIC   = 0,
+        CPUMF_CTR_SET_USER    = 1,
+        CPUMF_CTR_SET_CRYPTO  = 2,
+        CPUMF_CTR_SET_EXT     = 3,
+
+        /* Maximum number of counter sets */
+        CPUMF_CTR_SET_MAX,
+};
+
+#define CPUMF_LCCTL_ENABLE_SHIFT    16
+#define CPUMF_LCCTL_ACTCTL_SHIFT     0
+static const u64 cpumf_state_ctl[CPUMF_CTR_SET_MAX] = {
+        [CPUMF_CTR_SET_BASIC]   = 0x02,
+        [CPUMF_CTR_SET_USER]    = 0x04,
+        [CPUMF_CTR_SET_CRYPTO]  = 0x08,
+        [CPUMF_CTR_SET_EXT]     = 0x01,
+};
+
+static void ctr_set_enable(u64 *state, int ctr_set)
+{
+        *state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT;
+}
+static void ctr_set_disable(u64 *state, int ctr_set)
+{
+        *state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT);
+}
+static void ctr_set_start(u64 *state, int ctr_set)
+{
+        *state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT;
+}
+static void ctr_set_stop(u64 *state, int ctr_set)
+{
+        *state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT);
+}
+
+/* Local CPUMF event structure */
+struct cpu_hw_events {
+        struct cpumf_ctr_info   info;
+        atomic_t                ctr_set[CPUMF_CTR_SET_MAX];
+        u64                     state, tx_state;
+        unsigned int            flags;
+};
+static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
+        .ctr_set = {
+                [CPUMF_CTR_SET_BASIC]  = ATOMIC_INIT(0),
+                [CPUMF_CTR_SET_USER]   = ATOMIC_INIT(0),
+                [CPUMF_CTR_SET_CRYPTO] = ATOMIC_INIT(0),
+                [CPUMF_CTR_SET_EXT]    = ATOMIC_INIT(0),
+        },
+        .state = 0,
+        .flags = 0,
+};
+
+static int get_counter_set(u64 event)
+{
+        int set = -1;
+
+        if (event < 32)
+                set = CPUMF_CTR_SET_BASIC;
+        else if (event < 64)
+                set = CPUMF_CTR_SET_USER;
+        else if (event < 128)
+                set = CPUMF_CTR_SET_CRYPTO;
+        else if (event < 160)
+                set = CPUMF_CTR_SET_EXT;
+
+        return set;
+}
+
+static int validate_event(const struct hw_perf_event *hwc)
+{
+        switch (hwc->config_base) {
+        case CPUMF_CTR_SET_BASIC:
+        case CPUMF_CTR_SET_USER:
+        case CPUMF_CTR_SET_CRYPTO:
+        case CPUMF_CTR_SET_EXT:
+                /* check for reserved counters */
+                if ((hwc->config >=  6 && hwc->config <=  31) ||
+                    (hwc->config >= 38 && hwc->config <=  63) ||
+                    (hwc->config >= 80 && hwc->config <= 127))
+                        return -EOPNOTSUPP;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int validate_ctr_version(const struct hw_perf_event *hwc)
+{
+        struct cpu_hw_events *cpuhw;
+        int err = 0;
+
+        cpuhw = &get_cpu_var(cpu_hw_events);
+
+        /* check required version for counter sets */
+        switch (hwc->config_base) {
+        case CPUMF_CTR_SET_BASIC:
+        case CPUMF_CTR_SET_USER:
+                if (cpuhw->info.cfvn < 1)
+                        err = -EOPNOTSUPP;
+                break;
+        case CPUMF_CTR_SET_CRYPTO:
+        case CPUMF_CTR_SET_EXT:
+                if (cpuhw->info.csvn < 1)
+                        err = -EOPNOTSUPP;
+                break;
+        }
+
+        put_cpu_var(cpu_hw_events);
+        return err;
+}
+
+static int validate_ctr_auth(const struct hw_perf_event *hwc)
+{
+        struct cpu_hw_events *cpuhw;
+        u64 ctrs_state;
+        int err = 0;
+
+        cpuhw = &get_cpu_var(cpu_hw_events);
+
+        /* check authorization for cpu counter sets */
+        ctrs_state = cpumf_state_ctl[hwc->config_base];
+        if (!(ctrs_state & cpuhw->info.auth_ctl))
+                err = -EPERM;
+
+        put_cpu_var(cpu_hw_events);
+        return err;
+}
+
+/*
+ * Change the CPUMF state to active.
+ * Enable and activate the CPU-counter sets according
+ * to the per-cpu control state.
+ */
+static void cpumf_pmu_enable(struct pmu *pmu)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+        int err;
+
+        if (cpuhw->flags & PMU_F_ENABLED)
+                return;
+
+        err = lcctl(cpuhw->state);
+        if (err) {
+                pr_err("Enabling the performance measuring unit "
+                       "failed with rc=%lx\n", err);
+                return;
+        }
+
+        cpuhw->flags |= PMU_F_ENABLED;
+}
+
+/*
+ * Change the CPUMF state to inactive.
+ * Disable and enable (inactive) the CPU-counter sets according
+ * to the per-cpu control state.
+ */
+static void cpumf_pmu_disable(struct pmu *pmu)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+        int err;
+        u64 inactive;
+
+        if (!(cpuhw->flags & PMU_F_ENABLED))
+                return;
+
+        inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
+        err = lcctl(inactive);
+        if (err) {
+                pr_err("Disabling the performance measuring unit "
+                       "failed with rc=%lx\n", err);
+                return;
+        }
+
+        cpuhw->flags &= ~PMU_F_ENABLED;
+}
+
+
+/* Number of perf events counting hardware events */
+static atomic_t num_events = ATOMIC_INIT(0);
+/* Used to avoid races in calling reserve/release_cpumf_hardware */
+static DEFINE_MUTEX(pmc_reserve_mutex);
+
+/* CPU-measurement alerts for the counter facility */
+static void cpumf_measurement_alert(struct ext_code ext_code,
+                                    unsigned int alert, unsigned long unused)
+{
+        struct cpu_hw_events *cpuhw;
+
+        if (!(alert & CPU_MF_INT_CF_MASK))
+                return;
+
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_CPM]++;
+        cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        /* Measurement alerts are shared and might happen when the PMU
+         * is not reserved.  Ignore these alerts in this case. */
+        if (!(cpuhw->flags & PMU_F_RESERVED))
+                return;
+
+        /* counter authorization change alert */
+        if (alert & CPU_MF_INT_CF_CACA)
+                qctri(&cpuhw->info);
+
+        /* loss of counter data alert */
+        if (alert & CPU_MF_INT_CF_LCDA)
+                pr_err("CPU[%i] Counter data was lost\n", smp_processor_id());
+}
+
+#define PMC_INIT      0
+#define PMC_RELEASE   1
+static void setup_pmc_cpu(void *flags)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        switch (*((int *) flags)) {
+        case PMC_INIT:
+                memset(&cpuhw->info, 0, sizeof(cpuhw->info));
+                qctri(&cpuhw->info);
+                cpuhw->flags |= PMU_F_RESERVED;
+                break;
+
+        case PMC_RELEASE:
+                cpuhw->flags &= ~PMU_F_RESERVED;
+                break;
+        }
+
+        /* Disable CPU counter sets */
+        lcctl(0);
+}
+
+/* Initialize the CPU-measurement facility */
+static int reserve_pmc_hardware(void)
+{
+        int flags = PMC_INIT;
+
+        on_each_cpu(setup_pmc_cpu, &flags, 1);
+        measurement_alert_subclass_register();
+
+        return 0;
+}
+
+/* Release the CPU-measurement facility */
+static void release_pmc_hardware(void)
+{
+        int flags = PMC_RELEASE;
+
+        on_each_cpu(setup_pmc_cpu, &flags, 1);
+        measurement_alert_subclass_unregister();
+}
+
+/* Release the PMU if event is the last perf event */
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+        if (!atomic_add_unless(&num_events, -1, 1)) {
+                mutex_lock(&pmc_reserve_mutex);
+                if (atomic_dec_return(&num_events) == 0)
+                        release_pmc_hardware();
+                mutex_unlock(&pmc_reserve_mutex);
+        }
+}
+
+/* CPUMF <-> perf event mappings for kernel+userspace (basic set) */
+static const int cpumf_generic_events_basic[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = 0,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = 1,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = -1,
+        [PERF_COUNT_HW_CACHE_MISSES]        = -1,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = -1,
+        [PERF_COUNT_HW_BUS_CYCLES]          = -1,
+};
+/* CPUMF <-> perf event mappings for userspace (problem-state set) */
+static const int cpumf_generic_events_user[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = 32,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = 33,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = -1,
+        [PERF_COUNT_HW_CACHE_MISSES]        = -1,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = -1,
+        [PERF_COUNT_HW_BUS_CYCLES]          = -1,
+};
+
+static int __hw_perf_event_init(struct perf_event *event)
+{
+        struct perf_event_attr *attr = &event->attr;
+        struct hw_perf_event *hwc = &event->hw;
+        int err;
+        u64 ev;
+
+        switch (attr->type) {
+        case PERF_TYPE_RAW:
+                /* Raw events are used to access counters directly,
+                 * hence do not permit excludes */
+                if (attr->exclude_kernel || attr->exclude_user ||
+                    attr->exclude_hv)
+                        return -EOPNOTSUPP;
+                ev = attr->config;
+                break;
+
+        case PERF_TYPE_HARDWARE:
+                ev = attr->config;
+                /* Count user space (problem-state) only */
+                if (!attr->exclude_user && attr->exclude_kernel) {
+                        if (ev >= ARRAY_SIZE(cpumf_generic_events_user))
+                                return -EOPNOTSUPP;
+                        ev = cpumf_generic_events_user[ev];
+
+                /* No support for kernel space counters only */
+                } else if (!attr->exclude_kernel && attr->exclude_user) {
+                        return -EOPNOTSUPP;
+
+                /* Count user and kernel space */
+                } else {
+                        if (ev >= ARRAY_SIZE(cpumf_generic_events_basic))
+                                return -EOPNOTSUPP;
+                        ev = cpumf_generic_events_basic[ev];
+                }
+                break;
+
+        default:
+                return -ENOENT;
+        }
+
+        if (ev == -1)
+                return -ENOENT;
+
+        if (ev >= PERF_CPUM_CF_MAX_CTR)
+                return -EINVAL;
+
+        /* The CPU measurement counter facility does not have any interrupts
+         * to do sampling.  Sampling must be provided by external means,
+         * for example, by timers.
+         */
+        if (hwc->sample_period)
+                return -EINVAL;
+
+        /* Use the hardware perf event structure to store the counter number
+         * in 'config' member and the counter set to which the counter belongs
+         * in the 'config_base'.  The counter set (config_base) is then used
+         * to enable/disable the counters.
+         */
+        hwc->config = ev;
+        hwc->config_base = get_counter_set(ev);
+
+        /* Validate the counter that is assigned to this event.
+         * Because the counter facility can use numerous counters at the
+         * same time without constraints, it is not necessary to explicity
+         * validate event groups (event->group_leader != event).
+         */
+        err = validate_event(hwc);
+        if (err)
+                return err;
+
+        /* Initialize for using the CPU-measurement counter facility */
+        if (!atomic_inc_not_zero(&num_events)) {
+                mutex_lock(&pmc_reserve_mutex);
+                if (atomic_read(&num_events) == 0 && reserve_pmc_hardware())
+                        err = -EBUSY;
+                else
+                        atomic_inc(&num_events);
+                mutex_unlock(&pmc_reserve_mutex);
+        }
+        event->destroy = hw_perf_event_destroy;
+
+        /* Finally, validate version and authorization of the counter set */
+        err = validate_ctr_auth(hwc);
+        if (!err)
+                err = validate_ctr_version(hwc);
+
+        return err;
+}
+
+static int cpumf_pmu_event_init(struct perf_event *event)
+{
+        int err;
+
+        switch (event->attr.type) {
+        case PERF_TYPE_HARDWARE:
+        case PERF_TYPE_HW_CACHE:
+        case PERF_TYPE_RAW:
+                err = __hw_perf_event_init(event);
+                break;
+        default:
+                return -ENOENT;
+        }
+
+        if (unlikely(err) && event->destroy)
+                event->destroy(event);
+
+        return err;
+}
+
+static int hw_perf_event_reset(struct perf_event *event)
+{
+        u64 prev, new;
+        int err;
+
+        do {
+                prev = local64_read(&event->hw.prev_count);
+                err = ecctr(event->hw.config, &new);
+                if (err) {
+                        if (err != 3)
+                                break;
+                        /* The counter is not (yet) available. This
+                         * might happen if the counter set to which
+                         * this counter belongs is in the disabled
+                         * state.
+                         */
+                        new = 0;
+                }
+        } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
+
+        return err;
+}
+
+static int hw_perf_event_update(struct perf_event *event)
+{
+        u64 prev, new, delta;
+        int err;
+
+        do {
+                prev = local64_read(&event->hw.prev_count);
+                err = ecctr(event->hw.config, &new);
+                if (err)
+                        goto out;
+        } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
+
+        delta = (prev <= new) ? new - prev
+                              : (-1ULL - prev) + new + 1;        /* overflow */
+        local64_add(delta, &event->count);
+out:
+        return err;
+}
+
+static void cpumf_pmu_read(struct perf_event *event)
+{
+        if (event->hw.state & PERF_HES_STOPPED)
+                return;
+
+        hw_perf_event_update(event);
+}
+
+static void cpumf_pmu_start(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+                return;
+
+        if (WARN_ON_ONCE(hwc->config == -1))
+                return;
+
+        if (flags & PERF_EF_RELOAD)
+                WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+
+        hwc->state = 0;
+
+        /* (Re-)enable and activate the counter set */
+        ctr_set_enable(&cpuhw->state, hwc->config_base);
+        ctr_set_start(&cpuhw->state, hwc->config_base);
+
+        /* The counter set to which this counter belongs can be already active.
+         * Because all counters in a set are active, the event->hw.prev_count
+         * needs to be synchronized.  At this point, the counter set can be in
+         * the inactive or disabled state.
+         */
+        hw_perf_event_reset(event);
+
+        /* increment refcount for this counter set */
+        atomic_inc(&cpuhw->ctr_set[hwc->config_base]);
+}
+
+static void cpumf_pmu_stop(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (!(hwc->state & PERF_HES_STOPPED)) {
+                /* Decrement reference count for this counter set and if this
+                 * is the last used counter in the set, clear activation
+                 * control and set the counter set state to inactive.
+                 */
+                if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base]))
+                        ctr_set_stop(&cpuhw->state, hwc->config_base);
+                event->hw.state |= PERF_HES_STOPPED;
+        }
+
+        if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
+                hw_perf_event_update(event);
+                event->hw.state |= PERF_HES_UPTODATE;
+        }
+}
+
+static int cpumf_pmu_add(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        /* Check authorization for the counter set to which this
+         * counter belongs.
+         * For group events transaction, the authorization check is
+         * done in cpumf_pmu_commit_txn().
+         */
+        if (!(cpuhw->flags & PERF_EVENT_TXN))
+                if (validate_ctr_auth(&event->hw))
+                        return -EPERM;
+
+        ctr_set_enable(&cpuhw->state, event->hw.config_base);
+        event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+        if (flags & PERF_EF_START)
+                cpumf_pmu_start(event, PERF_EF_RELOAD);
+
+        perf_event_update_userpage(event);
+
+        return 0;
+}
+
+static void cpumf_pmu_del(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        cpumf_pmu_stop(event, PERF_EF_UPDATE);
+
+        /* Check if any counter in the counter set is still used.  If not used,
+         * change the counter set to the disabled state.  This also clears the
+         * content of all counters in the set.
+         *
+         * When a new perf event has been added but not yet started, this can
+         * clear enable control and resets all counters in a set.  Therefore,
+         * cpumf_pmu_start() always has to reenable a counter set.
+         */
+        if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base]))
+                ctr_set_disable(&cpuhw->state, event->hw.config_base);
+
+        perf_event_update_userpage(event);
+}
+
+/*
+ * Start group events scheduling transaction.
+ * Set flags to perform a single test at commit time.
+ */
+static void cpumf_pmu_start_txn(struct pmu *pmu)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        perf_pmu_disable(pmu);
+        cpuhw->flags |= PERF_EVENT_TXN;
+        cpuhw->tx_state = cpuhw->state;
+}
+
+/*
+ * Stop and cancel a group events scheduling tranctions.
+ * Assumes cpumf_pmu_del() is called for each successful added
+ * cpumf_pmu_add() during the transaction.
+ */
+static void cpumf_pmu_cancel_txn(struct pmu *pmu)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        WARN_ON(cpuhw->tx_state != cpuhw->state);
+
+        cpuhw->flags &= ~PERF_EVENT_TXN;
+        perf_pmu_enable(pmu);
+}
+
+/*
+ * Commit the group events scheduling transaction.  On success, the
+ * transaction is closed.   On error, the transaction is kept open
+ * until cpumf_pmu_cancel_txn() is called.
+ */
+static int cpumf_pmu_commit_txn(struct pmu *pmu)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+        u64 state;
+
+        /* check if the updated state can be scheduled */
+        state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
+        state >>= CPUMF_LCCTL_ENABLE_SHIFT;
+        if ((state & cpuhw->info.auth_ctl) != state)
+                return -EPERM;
+
+        cpuhw->flags &= ~PERF_EVENT_TXN;
+        perf_pmu_enable(pmu);
+        return 0;
+}
+
+/* Performance monitoring unit for s390x */
+static struct pmu cpumf_pmu = {
+        .pmu_enable   = cpumf_pmu_enable,
+        .pmu_disable  = cpumf_pmu_disable,
+        .event_init   = cpumf_pmu_event_init,
+        .add          = cpumf_pmu_add,
+        .del          = cpumf_pmu_del,
+        .start        = cpumf_pmu_start,
+        .stop         = cpumf_pmu_stop,
+        .read         = cpumf_pmu_read,
+        .start_txn    = cpumf_pmu_start_txn,
+        .commit_txn   = cpumf_pmu_commit_txn,
+        .cancel_txn   = cpumf_pmu_cancel_txn,
+};
+
+static int __cpuinit cpumf_pmu_notifier(struct notifier_block *self,
+                                        unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (long) hcpu;
+        int flags;
+
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_ONLINE:
+                flags = PMC_INIT;
+                smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
+                break;
+        case CPU_DOWN_PREPARE:
+                flags = PMC_RELEASE;
+                smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
+                break;
+        default:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static int __init cpumf_pmu_init(void)
+{
+        int rc;
+
+        if (!cpum_cf_avail())
+                return -ENODEV;
+
+        /* clear bit 15 of cr0 to unauthorize problem-state to
+         * extract measurement counters */
+        ctl_clear_bit(0, 48);
+
+        /* register handler for measurement-alert interruptions */
+        rc = register_external_interrupt(0x1407, cpumf_measurement_alert);
+        if (rc) {
+                pr_err("Registering for CPU-measurement alerts "
+                       "failed with rc=%i\n", rc);
+                goto out;
+        }
+
+        rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW);
+        if (rc) {
+                pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc);
+                unregister_external_interrupt(0x1407, cpumf_measurement_alert);
+                goto out;
+        }
+        perf_cpu_notifier(cpumf_pmu_notifier);
+out:
+        return rc;
+}
+early_initcall(cpumf_pmu_init);
diff --git a/arch/s390/kernel/perf_event.c b/arch/s390/kernel/perf_event.c
new file mode 100644
index 00000000000..609f985198c
--- /dev/null
+++ b/arch/s390/kernel/perf_event.c
@@ -0,0 +1,125 @@
+/*
+ * Performance event support for s390x
+ *
+ *  Copyright IBM Corp. 2012
+ *  Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ */
+#define KMSG_COMPONENT  "perf"
+#define pr_fmt(fmt)     KMSG_COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/percpu.h>
+#include <linux/export.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/cpu_mf.h>
+#include <asm/lowcore.h>
+#include <asm/processor.h>
+
+const char *perf_pmu_name(void)
+{
+        if (cpum_cf_avail() || cpum_sf_avail())
+                return "CPU-measurement facilities (CPUMF)";
+        return "pmu";
+}
+EXPORT_SYMBOL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+        int num = 0;
+
+        if (cpum_cf_avail())
+                num += PERF_CPUM_CF_MAX_CTR;
+
+        return num;
+}
+EXPORT_SYMBOL(perf_num_counters);
+
+void perf_event_print_debug(void)
+{
+        struct cpumf_ctr_info cf_info;
+        unsigned long flags;
+        int cpu;
+
+        if (!cpum_cf_avail())
+                return;
+
+        local_irq_save(flags);
+
+        cpu = smp_processor_id();
+        memset(&cf_info, 0, sizeof(cf_info));
+        if (!qctri(&cf_info)) {
+                pr_info("CPU[%i] CPUM_CF: ver=%u.%u A=%04x E=%04x C=%04x\n",
+                        cpu, cf_info.cfvn, cf_info.csvn,
+                        cf_info.auth_ctl, cf_info.enable_ctl, cf_info.act_ctl);
+                print_hex_dump_bytes("CPUMF Query: ", DUMP_PREFIX_OFFSET,
+                                     &cf_info, sizeof(cf_info));
+        }
+
+        local_irq_restore(flags);
+}
+
+/* See also arch/s390/kernel/traps.c */
+static unsigned long __store_trace(struct perf_callchain_entry *entry,
+                                   unsigned long sp,
+                                   unsigned long low, unsigned long high)
+{
+        struct stack_frame *sf;
+        struct pt_regs *regs;
+
+        while (1) {
+                sp = sp & PSW_ADDR_INSN;
+                if (sp < low || sp > high - sizeof(*sf))
+                        return sp;
+                sf = (struct stack_frame *) sp;
+                perf_callchain_store(entry, sf->gprs[8] & PSW_ADDR_INSN);
+                /* Follow the backchain. */
+                while (1) {
+                        low = sp;
+                        sp = sf->back_chain & PSW_ADDR_INSN;
+                        if (!sp)
+                                break;
+                        if (sp <= low || sp > high - sizeof(*sf))
+                                return sp;
+                        sf = (struct stack_frame *) sp;
+                        perf_callchain_store(entry,
+                                             sf->gprs[8] & PSW_ADDR_INSN);
+                }
+                /* Zero backchain detected, check for interrupt frame. */
+                sp = (unsigned long) (sf + 1);
+                if (sp <= low || sp > high - sizeof(*regs))
+                        return sp;
+                regs = (struct pt_regs *) sp;
+                perf_callchain_store(entry, sf->gprs[8] & PSW_ADDR_INSN);
+                low = sp;
+                sp = regs->gprs[15];
+        }
+}
+
+void perf_callchain_kernel(struct perf_callchain_entry *entry,
+                           struct pt_regs *regs)
+{
+        unsigned long head;
+        struct stack_frame *head_sf;
+
+        if (user_mode(regs))
+                return;
+
+        head = regs->gprs[15];
+        head_sf = (struct stack_frame *) head;
+
+        if (!head_sf || !head_sf->back_chain)
+                return;
+
+        head = head_sf->back_chain;
+        head = __store_trace(entry, head, S390_lowcore.async_stack - ASYNC_SIZE,
+                             S390_lowcore.async_stack);
+
+        __store_trace(entry, head, S390_lowcore.thread_info,
+                      S390_lowcore.thread_info + THREAD_SIZE);
+}
diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c
index d95427e32a5..ea5590fdca3 100644
--- a/arch/s390/kernel/vdso.c
+++ b/arch/s390/kernel/vdso.c
@@ -241,17 +241,11 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
          * on the "data" page of the vDSO or you'll stop getting kernel
          * updates and your nice userland gettimeofday will be totally dead.
          * It's fine to use that for setting breakpoints in the vDSO code
-         * pages though
-         *
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
+         * pages though.
          */
         rc = install_special_mapping(mm, vdso_base, vdso_pages << PAGE_SHIFT,
                                      VM_READ|VM_EXEC|
-                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                     VM_ALWAYSDUMP,
+                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                      vdso_pagelist);
         if (rc)
                 current->mm->context.vdso_base = 0;
diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig
index a21634173a6..78eb9847008 100644
--- a/arch/s390/kvm/Kconfig
+++ b/arch/s390/kvm/Kconfig
@@ -34,6 +34,15 @@ config KVM
 
           If unsure, say N.
 
+config KVM_S390_UCONTROL
+        bool "Userspace controlled virtual machines"
+        depends on KVM
+        ---help---
+          Allow CAP_SYS_ADMIN users to create KVM virtual machines that are
+          controlled by userspace.
+
+          If unsure, say N.
+
 # OK, it's a little counter-intuitive to do this, but it puts it neatly under
 # the virtualization menu.
 source drivers/vhost/Kconfig
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index 8943e82cd4d..a353f0ea45c 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -20,8 +20,8 @@ static int diag_release_pages(struct kvm_vcpu *vcpu)
         unsigned long start, end;
         unsigned long prefix  = vcpu->arch.sie_block->prefix;
 
-        start = vcpu->arch.guest_gprs[(vcpu->arch.sie_block->ipa & 0xf0) >> 4];
-        end = vcpu->arch.guest_gprs[vcpu->arch.sie_block->ipa & 0xf] + 4096;
+        start = vcpu->run->s.regs.gprs[(vcpu->arch.sie_block->ipa & 0xf0) >> 4];
+        end = vcpu->run->s.regs.gprs[vcpu->arch.sie_block->ipa & 0xf] + 4096;
 
         if (start & ~PAGE_MASK || end & ~PAGE_MASK || start > end
             || start < 2 * PAGE_SIZE)
@@ -56,7 +56,7 @@ static int __diag_time_slice_end(struct kvm_vcpu *vcpu)
 static int __diag_ipl_functions(struct kvm_vcpu *vcpu)
 {
         unsigned int reg = vcpu->arch.sie_block->ipa & 0xf;
-        unsigned long subcode = vcpu->arch.guest_gprs[reg] & 0xffff;
+        unsigned long subcode = vcpu->run->s.regs.gprs[reg] & 0xffff;
 
         VCPU_EVENT(vcpu, 5, "diag ipl functions, subcode %lx", subcode);
         switch (subcode) {
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 02434543eab..361456577c6 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -36,7 +36,7 @@ static int handle_lctlg(struct kvm_vcpu *vcpu)
 
         useraddr = disp2;
         if (base2)
-                useraddr += vcpu->arch.guest_gprs[base2];
+                useraddr += vcpu->run->s.regs.gprs[base2];
 
         if (useraddr & 7)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
@@ -75,7 +75,7 @@ static int handle_lctl(struct kvm_vcpu *vcpu)
 
         useraddr = disp2;
         if (base2)
-                useraddr += vcpu->arch.guest_gprs[base2];
+                useraddr += vcpu->run->s.regs.gprs[base2];
 
         if (useraddr & 3)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
@@ -133,13 +133,6 @@ static int handle_stop(struct kvm_vcpu *vcpu)
 
         vcpu->stat.exit_stop_request++;
         spin_lock_bh(&vcpu->arch.local_int.lock);
-        if (vcpu->arch.local_int.action_bits & ACTION_STORE_ON_STOP) {
-                vcpu->arch.local_int.action_bits &= ~ACTION_STORE_ON_STOP;
-                rc = kvm_s390_vcpu_store_status(vcpu,
-                                                  KVM_S390_STORE_STATUS_NOADDR);
-                if (rc >= 0)
-                        rc = -EOPNOTSUPP;
-        }
 
         if (vcpu->arch.local_int.action_bits & ACTION_RELOADVCPU_ON_STOP) {
                 vcpu->arch.local_int.action_bits &= ~ACTION_RELOADVCPU_ON_STOP;
@@ -155,7 +148,18 @@ static int handle_stop(struct kvm_vcpu *vcpu)
                 rc = -EOPNOTSUPP;
         }
 
-        spin_unlock_bh(&vcpu->arch.local_int.lock);
+        if (vcpu->arch.local_int.action_bits & ACTION_STORE_ON_STOP) {
+                vcpu->arch.local_int.action_bits &= ~ACTION_STORE_ON_STOP;
+                /* store status must be called unlocked. Since local_int.lock
+                 * only protects local_int.* and not guest memory we can give
+                 * up the lock here */
+                spin_unlock_bh(&vcpu->arch.local_int.lock);
+                rc = kvm_s390_vcpu_store_status(vcpu,
+                                                KVM_S390_STORE_STATUS_NOADDR);
+                if (rc >= 0)
+                        rc = -EOPNOTSUPP;
+        } else
+                spin_unlock_bh(&vcpu->arch.local_int.lock);
         return rc;
 }
 
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index f0647ce6da2..2d9f9a72bb8 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -236,8 +236,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 VCPU_EVENT(vcpu, 4, "interrupt: set prefix to %x",
                            inti->prefix.address);
                 vcpu->stat.deliver_prefix_signal++;
-                vcpu->arch.sie_block->prefix = inti->prefix.address;
-                vcpu->arch.sie_block->ihcpu = 0xffff;
+                kvm_s390_set_prefix(vcpu, inti->prefix.address);
                 break;
 
         case KVM_S390_RESTART:
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index d56de16a651..217ce44395a 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -129,6 +129,10 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_S390_PSW:
         case KVM_CAP_S390_GMAP:
         case KVM_CAP_SYNC_MMU:
+#ifdef CONFIG_KVM_S390_UCONTROL
+        case KVM_CAP_S390_UCONTROL:
+#endif
+        case KVM_CAP_SYNC_REGS:
                 r = 1;
                 break;
         default:
@@ -171,11 +175,22 @@ long kvm_arch_vm_ioctl(struct file *filp,
         return r;
 }
 
-int kvm_arch_init_vm(struct kvm *kvm)
+int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 {
         int rc;
         char debug_name[16];
 
+        rc = -EINVAL;
+#ifdef CONFIG_KVM_S390_UCONTROL
+        if (type & ~KVM_VM_S390_UCONTROL)
+                goto out_err;
+        if ((type & KVM_VM_S390_UCONTROL) && (!capable(CAP_SYS_ADMIN)))
+                goto out_err;
+#else
+        if (type)
+                goto out_err;
+#endif
+
         rc = s390_enable_sie();
         if (rc)
                 goto out_err;
@@ -198,10 +213,13 @@ int kvm_arch_init_vm(struct kvm *kvm)
         debug_register_view(kvm->arch.dbf, &debug_sprintf_view);
         VM_EVENT(kvm, 3, "%s", "vm created");
 
-        kvm->arch.gmap = gmap_alloc(current->mm);
-        if (!kvm->arch.gmap)
-                goto out_nogmap;
-
+        if (type & KVM_VM_S390_UCONTROL) {
+                kvm->arch.gmap = NULL;
+        } else {
+                kvm->arch.gmap = gmap_alloc(current->mm);
+                if (!kvm->arch.gmap)
+                        goto out_nogmap;
+        }
         return 0;
 out_nogmap:
         debug_unregister(kvm->arch.dbf);
@@ -214,11 +232,18 @@ out_err:
 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 {
         VCPU_EVENT(vcpu, 3, "%s", "free cpu");
-        clear_bit(63 - vcpu->vcpu_id, (unsigned long *) &vcpu->kvm->arch.sca->mcn);
-        if (vcpu->kvm->arch.sca->cpu[vcpu->vcpu_id].sda ==
-                (__u64) vcpu->arch.sie_block)
-                vcpu->kvm->arch.sca->cpu[vcpu->vcpu_id].sda = 0;
+        if (!kvm_is_ucontrol(vcpu->kvm)) {
+                clear_bit(63 - vcpu->vcpu_id,
+                          (unsigned long *) &vcpu->kvm->arch.sca->mcn);
+                if (vcpu->kvm->arch.sca->cpu[vcpu->vcpu_id].sda ==
+                    (__u64) vcpu->arch.sie_block)
+                        vcpu->kvm->arch.sca->cpu[vcpu->vcpu_id].sda = 0;
+        }
         smp_mb();
+
+        if (kvm_is_ucontrol(vcpu->kvm))
+                gmap_free(vcpu->arch.gmap);
+
         free_page((unsigned long)(vcpu->arch.sie_block));
         kvm_vcpu_uninit(vcpu);
         kfree(vcpu);
@@ -249,13 +274,25 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
         kvm_free_vcpus(kvm);
         free_page((unsigned long)(kvm->arch.sca));
         debug_unregister(kvm->arch.dbf);
-        gmap_free(kvm->arch.gmap);
+        if (!kvm_is_ucontrol(kvm))
+                gmap_free(kvm->arch.gmap);
 }
 
 /* Section: vcpu related */
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
 {
+        if (kvm_is_ucontrol(vcpu->kvm)) {
+                vcpu->arch.gmap = gmap_alloc(current->mm);
+                if (!vcpu->arch.gmap)
+                        return -ENOMEM;
+                return 0;
+        }
+
         vcpu->arch.gmap = vcpu->kvm->arch.gmap;
+        vcpu->run->kvm_valid_regs = KVM_SYNC_PREFIX |
+                                    KVM_SYNC_GPRS |
+                                    KVM_SYNC_ACRS |
+                                    KVM_SYNC_CRS;
         return 0;
 }
 
@@ -270,7 +307,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
         save_access_regs(vcpu->arch.host_acrs);
         vcpu->arch.guest_fpregs.fpc &= FPC_VALID_MASK;
         restore_fp_regs(&vcpu->arch.guest_fpregs);
-        restore_access_regs(vcpu->arch.guest_acrs);
+        restore_access_regs(vcpu->run->s.regs.acrs);
         gmap_enable(vcpu->arch.gmap);
         atomic_set_mask(CPUSTAT_RUNNING, &vcpu->arch.sie_block->cpuflags);
 }
@@ -280,7 +317,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
         atomic_clear_mask(CPUSTAT_RUNNING, &vcpu->arch.sie_block->cpuflags);
         gmap_disable(vcpu->arch.gmap);
         save_fp_regs(&vcpu->arch.guest_fpregs);
-        save_access_regs(vcpu->arch.guest_acrs);
+        save_access_regs(vcpu->run->s.regs.acrs);
         restore_fp_regs(&vcpu->arch.host_fpregs);
         restore_access_regs(vcpu->arch.host_acrs);
 }
@@ -290,8 +327,7 @@ static void kvm_s390_vcpu_initial_reset(struct kvm_vcpu *vcpu)
         /* this equals initial cpu reset in pop, but we don't switch to ESA */
         vcpu->arch.sie_block->gpsw.mask = 0UL;
         vcpu->arch.sie_block->gpsw.addr = 0UL;
-        vcpu->arch.sie_block->prefix    = 0UL;
-        vcpu->arch.sie_block->ihcpu     = 0xffff;
+        kvm_s390_set_prefix(vcpu, 0);
         vcpu->arch.sie_block->cputm     = 0UL;
         vcpu->arch.sie_block->ckc       = 0UL;
         vcpu->arch.sie_block->todpr     = 0;
@@ -342,12 +378,19 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
                 goto out_free_cpu;
 
         vcpu->arch.sie_block->icpua = id;
-        BUG_ON(!kvm->arch.sca);
-        if (!kvm->arch.sca->cpu[id].sda)
-                kvm->arch.sca->cpu[id].sda = (__u64) vcpu->arch.sie_block;
-        vcpu->arch.sie_block->scaoh = (__u32)(((__u64)kvm->arch.sca) >> 32);
-        vcpu->arch.sie_block->scaol = (__u32)(__u64)kvm->arch.sca;
-        set_bit(63 - id, (unsigned long *) &kvm->arch.sca->mcn);
+        if (!kvm_is_ucontrol(kvm)) {
+                if (!kvm->arch.sca) {
+                        WARN_ON_ONCE(1);
+                        goto out_free_cpu;
+                }
+                if (!kvm->arch.sca->cpu[id].sda)
+                        kvm->arch.sca->cpu[id].sda =
+                                (__u64) vcpu->arch.sie_block;
+                vcpu->arch.sie_block->scaoh =
+                        (__u32)(((__u64)kvm->arch.sca) >> 32);
+                vcpu->arch.sie_block->scaol = (__u32)(__u64)kvm->arch.sca;
+                set_bit(63 - id, (unsigned long *) &kvm->arch.sca->mcn);
+        }
 
         spin_lock_init(&vcpu->arch.local_int.lock);
         INIT_LIST_HEAD(&vcpu->arch.local_int.list);
@@ -388,29 +431,29 @@ static int kvm_arch_vcpu_ioctl_initial_reset(struct kvm_vcpu *vcpu)
 
 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
-        memcpy(&vcpu->arch.guest_gprs, &regs->gprs, sizeof(regs->gprs));
+        memcpy(&vcpu->run->s.regs.gprs, &regs->gprs, sizeof(regs->gprs));
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
-        memcpy(&regs->gprs, &vcpu->arch.guest_gprs, sizeof(regs->gprs));
+        memcpy(&regs->gprs, &vcpu->run->s.regs.gprs, sizeof(regs->gprs));
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
                                   struct kvm_sregs *sregs)
 {
-        memcpy(&vcpu->arch.guest_acrs, &sregs->acrs, sizeof(sregs->acrs));
+        memcpy(&vcpu->run->s.regs.acrs, &sregs->acrs, sizeof(sregs->acrs));
         memcpy(&vcpu->arch.sie_block->gcr, &sregs->crs, sizeof(sregs->crs));
-        restore_access_regs(vcpu->arch.guest_acrs);
+        restore_access_regs(vcpu->run->s.regs.acrs);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
                                   struct kvm_sregs *sregs)
 {
-        memcpy(&sregs->acrs, &vcpu->arch.guest_acrs, sizeof(sregs->acrs));
+        memcpy(&sregs->acrs, &vcpu->run->s.regs.acrs, sizeof(sregs->acrs));
         memcpy(&sregs->crs, &vcpu->arch.sie_block->gcr, sizeof(sregs->crs));
         return 0;
 }
@@ -418,7 +461,7 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
         memcpy(&vcpu->arch.guest_fpregs.fprs, &fpu->fprs, sizeof(fpu->fprs));
-        vcpu->arch.guest_fpregs.fpc = fpu->fpc;
+        vcpu->arch.guest_fpregs.fpc = fpu->fpc & FPC_VALID_MASK;
         restore_fp_regs(&vcpu->arch.guest_fpregs);
         return 0;
 }
@@ -467,9 +510,11 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
         return -EINVAL; /* not implemented yet */
 }
 
-static void __vcpu_run(struct kvm_vcpu *vcpu)
+static int __vcpu_run(struct kvm_vcpu *vcpu)
 {
-        memcpy(&vcpu->arch.sie_block->gg14, &vcpu->arch.guest_gprs[14], 16);
+        int rc;
+
+        memcpy(&vcpu->arch.sie_block->gg14, &vcpu->run->s.regs.gprs[14], 16);
 
         if (need_resched())
                 schedule();
@@ -477,7 +522,8 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
         if (test_thread_flag(TIF_MCCK_PENDING))
                 s390_handle_mcck();
 
-        kvm_s390_deliver_pending_interrupts(vcpu);
+        if (!kvm_is_ucontrol(vcpu->kvm))
+                kvm_s390_deliver_pending_interrupts(vcpu);
 
         vcpu->arch.sie_block->icptcode = 0;
         local_irq_disable();
@@ -485,9 +531,15 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
         local_irq_enable();
         VCPU_EVENT(vcpu, 6, "entering sie flags %x",
                    atomic_read(&vcpu->arch.sie_block->cpuflags));
-        if (sie64a(vcpu->arch.sie_block, vcpu->arch.guest_gprs)) {
-                VCPU_EVENT(vcpu, 3, "%s", "fault in sie instruction");
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+        rc = sie64a(vcpu->arch.sie_block, vcpu->run->s.regs.gprs);
+        if (rc) {
+                if (kvm_is_ucontrol(vcpu->kvm)) {
+                        rc = SIE_INTERCEPT_UCONTROL;
+                } else {
+                        VCPU_EVENT(vcpu, 3, "%s", "fault in sie instruction");
+                        kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+                        rc = 0;
+                }
         }
         VCPU_EVENT(vcpu, 6, "exit sie icptcode %d",
                    vcpu->arch.sie_block->icptcode);
@@ -495,7 +547,8 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
         kvm_guest_exit();
         local_irq_enable();
 
-        memcpy(&vcpu->arch.guest_gprs[14], &vcpu->arch.sie_block->gg14, 16);
+        memcpy(&vcpu->run->s.regs.gprs[14], &vcpu->arch.sie_block->gg14, 16);
+        return rc;
 }
 
 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
@@ -516,6 +569,7 @@ rerun_vcpu:
         case KVM_EXIT_UNKNOWN:
         case KVM_EXIT_INTR:
         case KVM_EXIT_S390_RESET:
+        case KVM_EXIT_S390_UCONTROL:
                 break;
         default:
                 BUG();
@@ -523,12 +577,26 @@ rerun_vcpu:
 
         vcpu->arch.sie_block->gpsw.mask = kvm_run->psw_mask;
         vcpu->arch.sie_block->gpsw.addr = kvm_run->psw_addr;
+        if (kvm_run->kvm_dirty_regs & KVM_SYNC_PREFIX) {
+                kvm_run->kvm_dirty_regs &= ~KVM_SYNC_PREFIX;
+                kvm_s390_set_prefix(vcpu, kvm_run->s.regs.prefix);
+        }
+        if (kvm_run->kvm_dirty_regs & KVM_SYNC_CRS) {
+                kvm_run->kvm_dirty_regs &= ~KVM_SYNC_CRS;
+                memcpy(&vcpu->arch.sie_block->gcr, &kvm_run->s.regs.crs, 128);
+                kvm_s390_set_prefix(vcpu, kvm_run->s.regs.prefix);
+        }
 
         might_fault();
 
         do {
-                __vcpu_run(vcpu);
-                rc = kvm_handle_sie_intercept(vcpu);
+                rc = __vcpu_run(vcpu);
+                if (rc)
+                        break;
+                if (kvm_is_ucontrol(vcpu->kvm))
+                        rc = -EOPNOTSUPP;
+                else
+                        rc = kvm_handle_sie_intercept(vcpu);
         } while (!signal_pending(current) && !rc);
 
         if (rc == SIE_INTERCEPT_RERUNVCPU)
@@ -539,6 +607,16 @@ rerun_vcpu:
                 rc = -EINTR;
         }
 
+#ifdef CONFIG_KVM_S390_UCONTROL
+        if (rc == SIE_INTERCEPT_UCONTROL) {
+                kvm_run->exit_reason = KVM_EXIT_S390_UCONTROL;
+                kvm_run->s390_ucontrol.trans_exc_code =
+                        current->thread.gmap_addr;
+                kvm_run->s390_ucontrol.pgm_code = 0x10;
+                rc = 0;
+        }
+#endif
+
         if (rc == -EOPNOTSUPP) {
                 /* intercept cannot be handled in-kernel, prepare kvm-run */
                 kvm_run->exit_reason         = KVM_EXIT_S390_SIEIC;
@@ -556,6 +634,8 @@ rerun_vcpu:
 
         kvm_run->psw_mask     = vcpu->arch.sie_block->gpsw.mask;
         kvm_run->psw_addr     = vcpu->arch.sie_block->gpsw.addr;
+        kvm_run->s.regs.prefix = vcpu->arch.sie_block->prefix;
+        memcpy(&kvm_run->s.regs.crs, &vcpu->arch.sie_block->gcr, 128);
 
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
@@ -602,7 +682,7 @@ int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
                 return -EFAULT;
 
         if (__guestcopy(vcpu, addr + offsetof(struct save_area, gp_regs),
-                        vcpu->arch.guest_gprs, 128, prefix))
+                        vcpu->run->s.regs.gprs, 128, prefix))
                 return -EFAULT;
 
         if (__guestcopy(vcpu, addr + offsetof(struct save_area, psw),
@@ -631,7 +711,7 @@ int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
                 return -EFAULT;
 
         if (__guestcopy(vcpu, addr + offsetof(struct save_area, acc_regs),
-                        &vcpu->arch.guest_acrs, 64, prefix))
+                        &vcpu->run->s.regs.acrs, 64, prefix))
                 return -EFAULT;
 
         if (__guestcopy(vcpu,
@@ -673,12 +753,77 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
         case KVM_S390_INITIAL_RESET:
                 r = kvm_arch_vcpu_ioctl_initial_reset(vcpu);
                 break;
+#ifdef CONFIG_KVM_S390_UCONTROL
+        case KVM_S390_UCAS_MAP: {
+                struct kvm_s390_ucas_mapping ucasmap;
+
+                if (copy_from_user(&ucasmap, argp, sizeof(ucasmap))) {
+                        r = -EFAULT;
+                        break;
+                }
+
+                if (!kvm_is_ucontrol(vcpu->kvm)) {
+                        r = -EINVAL;
+                        break;
+                }
+
+                r = gmap_map_segment(vcpu->arch.gmap, ucasmap.user_addr,
+                                     ucasmap.vcpu_addr, ucasmap.length);
+                break;
+        }
+        case KVM_S390_UCAS_UNMAP: {
+                struct kvm_s390_ucas_mapping ucasmap;
+
+                if (copy_from_user(&ucasmap, argp, sizeof(ucasmap))) {
+                        r = -EFAULT;
+                        break;
+                }
+
+                if (!kvm_is_ucontrol(vcpu->kvm)) {
+                        r = -EINVAL;
+                        break;
+                }
+
+                r = gmap_unmap_segment(vcpu->arch.gmap, ucasmap.vcpu_addr,
+                        ucasmap.length);
+                break;
+        }
+#endif
+        case KVM_S390_VCPU_FAULT: {
+                r = gmap_fault(arg, vcpu->arch.gmap);
+                if (!IS_ERR_VALUE(r))
+                        r = 0;
+                break;
+        }
         default:
-                r = -EINVAL;
+                r = -ENOTTY;
         }
         return r;
 }
 
+int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
+{
+#ifdef CONFIG_KVM_S390_UCONTROL
+        if ((vmf->pgoff == KVM_S390_SIE_PAGE_OFFSET)
+                 && (kvm_is_ucontrol(vcpu->kvm))) {
+                vmf->page = virt_to_page(vcpu->arch.sie_block);
+                get_page(vmf->page);
+                return 0;
+        }
+#endif
+        return VM_FAULT_SIGBUS;
+}
+
+void kvm_arch_free_memslot(struct kvm_memory_slot *free,
+                           struct kvm_memory_slot *dont)
+{
+}
+
+int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
+{
+        return 0;
+}
+
 /* Section: memory related */
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                    struct kvm_memory_slot *memslot,
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index 99b0b759711..ff28f9d1c9e 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -26,6 +26,7 @@ typedef int (*intercept_handler_t)(struct kvm_vcpu *vcpu);
 
 /* negativ values are error codes, positive values for internal conditions */
 #define SIE_INTERCEPT_RERUNVCPU         (1<<0)
+#define SIE_INTERCEPT_UCONTROL          (1<<1)
 int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu);
 
 #define VM_EVENT(d_kvm, d_loglevel, d_string, d_args...)\
@@ -47,6 +48,23 @@ static inline int __cpu_is_stopped(struct kvm_vcpu *vcpu)
         return atomic_read(&vcpu->arch.sie_block->cpuflags) & CPUSTAT_STOP_INT;
 }
 
+static inline int kvm_is_ucontrol(struct kvm *kvm)
+{
+#ifdef CONFIG_KVM_S390_UCONTROL
+        if (kvm->arch.gmap)
+                return 0;
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+static inline void kvm_s390_set_prefix(struct kvm_vcpu *vcpu, u32 prefix)
+{
+        vcpu->arch.sie_block->prefix = prefix & 0x7fffe000u;
+        vcpu->arch.sie_block->ihcpu  = 0xffff;
+}
+
 int kvm_s390_handle_wait(struct kvm_vcpu *vcpu);
 enum hrtimer_restart kvm_s390_idle_wakeup(struct hrtimer *timer);
 void kvm_s390_tasklet(unsigned long parm);
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index d0263895992..e5a45dbd26a 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -33,7 +33,7 @@ static int handle_set_prefix(struct kvm_vcpu *vcpu)
 
         operand2 = disp2;
         if (base2)
-                operand2 += vcpu->arch.guest_gprs[base2];
+                operand2 += vcpu->run->s.regs.gprs[base2];
 
         /* must be word boundary */
         if (operand2 & 3) {
@@ -56,8 +56,7 @@ static int handle_set_prefix(struct kvm_vcpu *vcpu)
                 goto out;
         }
 
-        vcpu->arch.sie_block->prefix = address;
-        vcpu->arch.sie_block->ihcpu = 0xffff;
+        kvm_s390_set_prefix(vcpu, address);
 
         VCPU_EVENT(vcpu, 5, "setting prefix to %x", address);
 out:
@@ -74,7 +73,7 @@ static int handle_store_prefix(struct kvm_vcpu *vcpu)
         vcpu->stat.instruction_stpx++;
         operand2 = disp2;
         if (base2)
-                operand2 += vcpu->arch.guest_gprs[base2];
+                operand2 += vcpu->run->s.regs.gprs[base2];
 
         /* must be word boundary */
         if (operand2 & 3) {
@@ -106,7 +105,7 @@ static int handle_store_cpu_address(struct kvm_vcpu *vcpu)
         vcpu->stat.instruction_stap++;
         useraddr = disp2;
         if (base2)
-                useraddr += vcpu->arch.guest_gprs[base2];
+                useraddr += vcpu->run->s.regs.gprs[base2];
 
         if (useraddr & 1) {
                 kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
@@ -181,7 +180,7 @@ static int handle_stidp(struct kvm_vcpu *vcpu)
         vcpu->stat.instruction_stidp++;
         operand2 = disp2;
         if (base2)
-                operand2 += vcpu->arch.guest_gprs[base2];
+                operand2 += vcpu->run->s.regs.gprs[base2];
 
         if (operand2 & 7) {
                 kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
@@ -232,9 +231,9 @@ static void handle_stsi_3_2_2(struct kvm_vcpu *vcpu, struct sysinfo_3_2_2 *mem)
 
 static int handle_stsi(struct kvm_vcpu *vcpu)
 {
-        int fc = (vcpu->arch.guest_gprs[0] & 0xf0000000) >> 28;
-        int sel1 = vcpu->arch.guest_gprs[0] & 0xff;
-        int sel2 = vcpu->arch.guest_gprs[1] & 0xffff;
+        int fc = (vcpu->run->s.regs.gprs[0] & 0xf0000000) >> 28;
+        int sel1 = vcpu->run->s.regs.gprs[0] & 0xff;
+        int sel2 = vcpu->run->s.regs.gprs[1] & 0xffff;
         int base2 = vcpu->arch.sie_block->ipb >> 28;
         int disp2 = ((vcpu->arch.sie_block->ipb & 0x0fff0000) >> 16);
         u64 operand2;
@@ -245,14 +244,14 @@ static int handle_stsi(struct kvm_vcpu *vcpu)
 
         operand2 = disp2;
         if (base2)
-                operand2 += vcpu->arch.guest_gprs[base2];
+                operand2 += vcpu->run->s.regs.gprs[base2];
 
         if (operand2 & 0xfff && fc > 0)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
         switch (fc) {
         case 0:
-                vcpu->arch.guest_gprs[0] = 3 << 28;
+                vcpu->run->s.regs.gprs[0] = 3 << 28;
                 vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);
                 return 0;
         case 1: /* same handling for 1 and 2 */
@@ -281,7 +280,7 @@ static int handle_stsi(struct kvm_vcpu *vcpu)
         }
         free_page(mem);
         vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);
-        vcpu->arch.guest_gprs[0] = 0;
+        vcpu->run->s.regs.gprs[0] = 0;
         return 0;
 out_mem:
         free_page(mem);
@@ -333,8 +332,8 @@ static int handle_tprot(struct kvm_vcpu *vcpu)
         int disp1 = (vcpu->arch.sie_block->ipb & 0x0fff0000) >> 16;
         int base2 = (vcpu->arch.sie_block->ipb & 0xf000) >> 12;
         int disp2 = vcpu->arch.sie_block->ipb & 0x0fff;
-        u64 address1 = disp1 + base1 ? vcpu->arch.guest_gprs[base1] : 0;
-        u64 address2 = disp2 + base2 ? vcpu->arch.guest_gprs[base2] : 0;
+        u64 address1 = disp1 + base1 ? vcpu->run->s.regs.gprs[base1] : 0;
+        u64 address2 = disp2 + base2 ? vcpu->run->s.regs.gprs[base2] : 0;
         struct vm_area_struct *vma;
         unsigned long user_address;
 
diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c
index 0a7941d74bc..0ad4cf23839 100644
--- a/arch/s390/kvm/sigp.c
+++ b/arch/s390/kvm/sigp.c
@@ -48,7 +48,7 @@
 
 
 static int __sigp_sense(struct kvm_vcpu *vcpu, u16 cpu_addr,
-                        unsigned long *reg)
+                        u64 *reg)
 {
         struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
         int rc;
@@ -160,12 +160,15 @@ static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
         inti->type = KVM_S390_SIGP_STOP;
 
         spin_lock_bh(&li->lock);
+        if ((atomic_read(li->cpuflags) & CPUSTAT_STOPPED))
+                goto out;
         list_add_tail(&inti->list, &li->list);
         atomic_set(&li->active, 1);
         atomic_set_mask(CPUSTAT_STOP_INT, li->cpuflags);
         li->action_bits |= action;
         if (waitqueue_active(&li->wq))
                 wake_up_interruptible(&li->wq);
+out:
         spin_unlock_bh(&li->lock);
 
         return 0; /* order accepted */
@@ -220,7 +223,7 @@ static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
 }
 
 static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
-                             unsigned long *reg)
+                             u64 *reg)
 {
         struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
         struct kvm_s390_local_interrupt *li = NULL;
@@ -278,7 +281,7 @@ out_fi:
 }
 
 static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
-                                unsigned long *reg)
+                                u64 *reg)
 {
         int rc;
         struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
@@ -309,6 +312,34 @@ static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
         return rc;
 }
 
+static int __sigp_restart(struct kvm_vcpu *vcpu, u16 cpu_addr)
+{
+        int rc = 0;
+        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
+        struct kvm_s390_local_interrupt *li;
+
+        if (cpu_addr >= KVM_MAX_VCPUS)
+                return 3; /* not operational */
+
+        spin_lock(&fi->lock);
+        li = fi->local_int[cpu_addr];
+        if (li == NULL) {
+                rc = 3; /* not operational */
+                goto out;
+        }
+
+        spin_lock_bh(&li->lock);
+        if (li->action_bits & ACTION_STOP_ON_STOP)
+                rc = 2; /* busy */
+        else
+                VCPU_EVENT(vcpu, 4, "sigp restart %x to handle userspace",
+                        cpu_addr);
+        spin_unlock_bh(&li->lock);
+out:
+        spin_unlock(&fi->lock);
+        return rc;
+}
+
 int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
 {
         int r1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4;
@@ -316,7 +347,7 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
         int base2 = vcpu->arch.sie_block->ipb >> 28;
         int disp2 = ((vcpu->arch.sie_block->ipb & 0x0fff0000) >> 16);
         u32 parameter;
-        u16 cpu_addr = vcpu->arch.guest_gprs[r3];
+        u16 cpu_addr = vcpu->run->s.regs.gprs[r3];
         u8 order_code;
         int rc;
 
@@ -327,18 +358,18 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
 
         order_code = disp2;
         if (base2)
-                order_code += vcpu->arch.guest_gprs[base2];
+                order_code += vcpu->run->s.regs.gprs[base2];
 
         if (r1 % 2)
-                parameter = vcpu->arch.guest_gprs[r1];
+                parameter = vcpu->run->s.regs.gprs[r1];
         else
-                parameter = vcpu->arch.guest_gprs[r1 + 1];
+                parameter = vcpu->run->s.regs.gprs[r1 + 1];
 
         switch (order_code) {
         case SIGP_SENSE:
                 vcpu->stat.instruction_sigp_sense++;
                 rc = __sigp_sense(vcpu, cpu_addr,
-                                  &vcpu->arch.guest_gprs[r1]);
+                                  &vcpu->run->s.regs.gprs[r1]);
                 break;
         case SIGP_EXTERNAL_CALL:
                 vcpu->stat.instruction_sigp_external_call++;
@@ -354,7 +385,8 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
                 break;
         case SIGP_STOP_STORE_STATUS:
                 vcpu->stat.instruction_sigp_stop++;
-                rc = __sigp_stop(vcpu, cpu_addr, ACTION_STORE_ON_STOP);
+                rc = __sigp_stop(vcpu, cpu_addr, ACTION_STORE_ON_STOP |
+                                                 ACTION_STOP_ON_STOP);
                 break;
         case SIGP_SET_ARCH:
                 vcpu->stat.instruction_sigp_arch++;
@@ -363,15 +395,18 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
         case SIGP_SET_PREFIX:
                 vcpu->stat.instruction_sigp_prefix++;
                 rc = __sigp_set_prefix(vcpu, cpu_addr, parameter,
-                                       &vcpu->arch.guest_gprs[r1]);
+                                       &vcpu->run->s.regs.gprs[r1]);
                 break;
         case SIGP_SENSE_RUNNING:
                 vcpu->stat.instruction_sigp_sense_running++;
                 rc = __sigp_sense_running(vcpu, cpu_addr,
-                                          &vcpu->arch.guest_gprs[r1]);
+                                          &vcpu->run->s.regs.gprs[r1]);
                 break;
         case SIGP_RESTART:
                 vcpu->stat.instruction_sigp_restart++;
+                rc = __sigp_restart(vcpu, cpu_addr);
+                if (rc == 2) /* busy */
+                        break;
                 /* user space must know about restart */
         default:
                 return -EOPNOTSUPP;
diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c
index a0155c02e32..2857c48486e 100644
--- a/arch/s390/mm/mmap.c
+++ b/arch/s390/mm/mmap.c
@@ -100,7 +100,6 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
                 mm->unmap_area = arch_unmap_area_topdown;
         }
 }
-EXPORT_SYMBOL_GPL(arch_pick_mmap_layout);
 
 #else
 
@@ -175,6 +174,5 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
                 mm->unmap_area = arch_unmap_area_topdown;
         }
 }
-EXPORT_SYMBOL_GPL(arch_pick_mmap_layout);
 
 #endif
diff --git a/arch/s390/oprofile/hwsampler.c b/arch/s390/oprofile/hwsampler.c
index 59c9278befc..c6646de07bf 100644
--- a/arch/s390/oprofile/hwsampler.c
+++ b/arch/s390/oprofile/hwsampler.c
@@ -19,7 +19,7 @@
 #include <linux/oprofile.h>
 
 #include <asm/facility.h>
-#include <asm/lowcore.h>
+#include <asm/cpu_mf.h>
 #include <asm/irq.h>
 
 #include "hwsampler.h"
@@ -31,12 +31,6 @@
 #define ALERT_REQ_MASK   0x4000000000000000ul
 #define BUFFER_FULL_MASK 0x8000000000000000ul
 
-#define EI_IEA      (1 << 31)   /* invalid entry address              */
-#define EI_ISE      (1 << 30)   /* incorrect SDBT entry               */
-#define EI_PRA      (1 << 29)   /* program request alert              */
-#define EI_SACA     (1 << 23)   /* sampler authorization change alert */
-#define EI_LSDA     (1 << 22)   /* loss of sample data alert          */
-
 DECLARE_PER_CPU(struct hws_cpu_buffer, sampler_cpu_buffer);
 
 struct hws_execute_parms {
@@ -233,9 +227,20 @@ static inline unsigned long *trailer_entry_ptr(unsigned long v)
         return (unsigned long *) ret;
 }
 
-/* prototypes for external interrupt handler and worker */
 static void hws_ext_handler(struct ext_code ext_code,
-                            unsigned int param32, unsigned long param64);
+                            unsigned int param32, unsigned long param64)
+{
+        struct hws_cpu_buffer *cb = &__get_cpu_var(sampler_cpu_buffer);
+
+        if (!(param32 & CPU_MF_INT_SF_MASK))
+                return;
+
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_CPM]++;
+        atomic_xchg(&cb->ext_params, atomic_read(&cb->ext_params) | param32);
+
+        if (hws_wq)
+                queue_work(hws_wq, &cb->worker);
+}
 
 static void worker(struct work_struct *work);
 
@@ -674,18 +679,6 @@ int hwsampler_activate(unsigned int cpu)
         return rc;
 }
 
-static void hws_ext_handler(struct ext_code ext_code,
-                            unsigned int param32, unsigned long param64)
-{
-        struct hws_cpu_buffer *cb;
-
-        kstat_cpu(smp_processor_id()).irqs[EXTINT_CPM]++;
-        cb = &__get_cpu_var(sampler_cpu_buffer);
-        atomic_xchg(&cb->ext_params, atomic_read(&cb->ext_params) | param32);
-        if (hws_wq)
-                queue_work(hws_wq, &cb->worker);
-}
-
 static int check_qsi_on_setup(void)
 {
         int rc;
@@ -761,23 +754,23 @@ static int worker_check_error(unsigned int cpu, int ext_params)
         if (!sdbt || !*sdbt)
                 return -EINVAL;
 
-        if (ext_params & EI_PRA)
+        if (ext_params & CPU_MF_INT_SF_PRA)
                 cb->req_alert++;
 
-        if (ext_params & EI_LSDA)
+        if (ext_params & CPU_MF_INT_SF_LSDA)
                 cb->loss_of_sample_data++;
 
-        if (ext_params & EI_IEA) {
+        if (ext_params & CPU_MF_INT_SF_IAE) {
                 cb->invalid_entry_address++;
                 rc = -EINVAL;
         }
 
-        if (ext_params & EI_ISE) {
+        if (ext_params & CPU_MF_INT_SF_ISE) {
                 cb->incorrect_sdbt_entry++;
                 rc = -EINVAL;
         }
 
-        if (ext_params & EI_SACA) {
+        if (ext_params & CPU_MF_INT_SF_SACA) {
                 cb->sample_auth_change_alert++;
                 rc = -EINVAL;
         }
@@ -1010,7 +1003,7 @@ int hwsampler_deallocate(void)
         if (hws_state != HWS_STOPPED)
                 goto deallocate_exit;
 
-        ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
+        measurement_alert_subclass_unregister();
         deallocate_sdbt();
 
         hws_state = HWS_DEALLOCATED;
@@ -1124,7 +1117,7 @@ int hwsampler_shutdown(void)
                 mutex_lock(&hws_sem);
 
                 if (hws_state == HWS_STOPPED) {
-                        ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
+                        measurement_alert_subclass_unregister();
                         deallocate_sdbt();
                 }
                 if (hws_wq) {
@@ -1199,7 +1192,7 @@ start_all_exit:
         hws_oom = 1;
         hws_flush_all = 0;
         /* now let them in, 1407 CPUMF external interrupts */
-        ctl_set_bit(0, 5); /* set CR0 bit 58 */
+        measurement_alert_subclass_register();
 
         return 0;
 }
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index 74b8db1b74a..4a52590fe3d 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -322,7 +322,7 @@ static void ivdr_clk_disable(struct clk *clk)
         __raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
 }
 
-static struct clk_ops ivdr_clk_ops = {
+static struct sh_clk_ops ivdr_clk_ops = {
         .enable         = ivdr_clk_enable,
         .disable        = ivdr_clk_disable,
 };
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 486d1ac3694..27a2314f50a 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -167,7 +167,7 @@ static void sdk7786_pcie_clk_disable(struct clk *clk)
         fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
 }
 
-static struct clk_ops sdk7786_pcie_clk_ops = {
+static struct sh_clk_ops sdk7786_pcie_clk_ops = {
         .enable         = sdk7786_pcie_clk_enable,
         .disable        = sdk7786_pcie_clk_disable,
 };
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 1e7b0e2e764..9d10a3cb879 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -37,11 +37,20 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
         static int next_busno;
         static int need_domain_info;
         LIST_HEAD(resources);
+        struct resource *res;
+        resource_size_t offset;
         int i;
         struct pci_bus *bus;
 
-        for (i = 0; i < hose->nr_resources; i++)
-                pci_add_resource(&resources, hose->resources + i);
+        for (i = 0; i < hose->nr_resources; i++) {
+                res = hose->resources + i;
+                offset = 0;
+                if (res->flags & IORESOURCE_IO)
+                        offset = hose->io_offset;
+                else if (res->flags & IORESOURCE_MEM)
+                        offset = hose->mem_offset;
+                pci_add_resource_offset(&resources, res, offset);
+        }
 
         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
                                 &resources);
@@ -143,42 +152,12 @@ static int __init pcibios_init(void)
 }
 subsys_initcall(pcibios_init);
 
-static void pcibios_fixup_device_resources(struct pci_dev *dev,
-        struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_channel *hose = bus->sysdata;
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        offset = hose->io_offset;
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = hose->mem_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end += offset;
-        }
-}
-
 /*
  *  Called after each bus is probed, but before its children
  *  are examined.
  */
 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
-        struct pci_dev *dev;
-        struct list_head *ln;
-
-        for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
-                dev = pci_dev_b(ln);
-
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
-        }
 }
 
 /*
@@ -208,36 +187,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
         return start;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        struct pci_channel *hose = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct pci_channel *hose = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
 int pcibios_enable_device(struct pci_dev *dev, int mask)
 {
         return pci_enable_resources(dev, mask);
@@ -381,8 +330,6 @@ EXPORT_SYMBOL(pci_iounmap);
 #endif /* CONFIG_GENERIC_IOMAP */
 
 #ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 #endif
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 803d4c7f09d..0390a07e7e3 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -4,7 +4,7 @@
 #include <linux/sh_clk.h>
 
 /* Should be defined by processor-specific code */
-void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
+void __deprecated arch_init_clk_ops(struct sh_clk_ops **, int type);
 int __init arch_clk_init(void);
 
 /* arch/sh/kernel/cpu/clock-cpg.c */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index cb21e2399dc..bff96c2e7d2 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -114,12 +114,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 /* Board-specific fixup routines. */
 int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-        struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
 #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 5b7f12e58a8..e80252ae5bc 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -28,7 +28,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
-static struct clk_ops sh7619_master_clk_ops = {
+static struct sh_clk_ops sh7619_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -38,7 +38,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7619_module_clk_ops = {
+static struct sh_clk_ops sh7619_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -47,22 +47,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
-static struct clk_ops sh7619_bus_clk_ops = {
+static struct sh_clk_ops sh7619_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static struct clk_ops sh7619_cpu_clk_ops = {
+static struct sh_clk_ops sh7619_cpu_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
-static struct clk_ops *sh7619_clk_ops[] = {
+static struct sh_clk_ops *sh7619_clk_ops[] = {
         &sh7619_master_clk_ops,
         &sh7619_module_clk_ops,
         &sh7619_bus_clk_ops,
         &sh7619_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
             test_mode_pin(MODE_PIN2 | MODE_PIN1))
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 1174e2d96c0..532a36c7232 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
                pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
-static struct clk_ops sh7201_master_clk_ops = {
+static struct sh_clk_ops sh7201_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -40,7 +40,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7201_module_clk_ops = {
+static struct sh_clk_ops sh7201_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -50,7 +50,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7201_bus_clk_ops = {
+static struct sh_clk_ops sh7201_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -60,18 +60,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7201_cpu_clk_ops = {
+static struct sh_clk_ops sh7201_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7201_clk_ops[] = {
+static struct sh_clk_ops *sh7201_clk_ops[] = {
         &sh7201_master_clk_ops,
         &sh7201_module_clk_ops,
         &sh7201_bus_clk_ops,
         &sh7201_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
                 pll2_mult = 1;
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 95a008e8b73..529f719b6e3 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -32,7 +32,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
 }
 
-static struct clk_ops sh7203_master_clk_ops = {
+static struct sh_clk_ops sh7203_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7203_module_clk_ops = {
+static struct sh_clk_ops sh7203_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -52,22 +52,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx-2];
 }
 
-static struct clk_ops sh7203_bus_clk_ops = {
+static struct sh_clk_ops sh7203_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static struct clk_ops sh7203_cpu_clk_ops = {
+static struct sh_clk_ops sh7203_cpu_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
-static struct clk_ops *sh7203_clk_ops[] = {
+static struct sh_clk_ops *sh7203_clk_ops[] = {
         &sh7203_master_clk_ops,
         &sh7203_module_clk_ops,
         &sh7203_bus_clk_ops,
         &sh7203_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN1))
                 pll2_mult = 4;
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index 3c314d7cd6e..17778983467 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
-static struct clk_ops sh7206_master_clk_ops = {
+static struct sh_clk_ops sh7206_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7206_module_clk_ops = {
+static struct sh_clk_ops sh7206_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
-static struct clk_ops sh7206_bus_clk_ops = {
+static struct sh_clk_ops sh7206_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7206_cpu_clk_ops = {
+static struct sh_clk_ops sh7206_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7206_clk_ops[] = {
+static struct sh_clk_ops *sh7206_clk_ops[] = {
         &sh7206_master_clk_ops,
         &sh7206_module_clk_ops,
         &sh7206_bus_clk_ops,
         &sh7206_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
                 pll2_mult = 1;
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index b78384afac0..90faa44ca94 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -34,7 +34,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[idx];
 }
 
-static struct clk_ops sh3_master_clk_ops = {
+static struct sh_clk_ops sh3_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -46,7 +46,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh3_module_clk_ops = {
+static struct sh_clk_ops sh3_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -58,7 +58,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / stc_multipliers[idx];
 }
 
-static struct clk_ops sh3_bus_clk_ops = {
+static struct sh_clk_ops sh3_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -70,18 +70,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh3_cpu_clk_ops = {
+static struct sh_clk_ops sh3_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh3_clk_ops[] = {
+static struct sh_clk_ops *sh3_clk_ops[] = {
         &sh3_master_clk_ops,
         &sh3_module_clk_ops,
         &sh3_bus_clk_ops,
         &sh3_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh3_clk_ops))
                 *ops = sh3_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index 0ecea1451c6..a8da4a9986b 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -35,7 +35,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
 }
 
-static struct clk_ops sh7705_master_clk_ops = {
+static struct sh_clk_ops sh7705_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -45,7 +45,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7705_module_clk_ops = {
+static struct sh_clk_ops sh7705_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -55,7 +55,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / stc_multipliers[idx];
 }
 
-static struct clk_ops sh7705_bus_clk_ops = {
+static struct sh_clk_ops sh7705_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -65,18 +65,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7705_cpu_clk_ops = {
+static struct sh_clk_ops sh7705_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7705_clk_ops[] = {
+static struct sh_clk_ops *sh7705_clk_ops[] = {
         &sh7705_master_clk_ops,
         &sh7705_module_clk_ops,
         &sh7705_bus_clk_ops,
         &sh7705_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7705_clk_ops))
                 *ops = sh7705_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 6f9ff8b57dd..a4088e5b220 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[idx];
 }
 
-static struct clk_ops sh7706_master_clk_ops = {
+static struct sh_clk_ops sh7706_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7706_module_clk_ops = {
+static struct sh_clk_ops sh7706_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -54,7 +54,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / stc_multipliers[idx];
 }
 
-static struct clk_ops sh7706_bus_clk_ops = {
+static struct sh_clk_ops sh7706_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -66,18 +66,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7706_cpu_clk_ops = {
+static struct sh_clk_ops sh7706_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7706_clk_ops[] = {
+static struct sh_clk_ops *sh7706_clk_ops[] = {
         &sh7706_master_clk_ops,
         &sh7706_module_clk_ops,
         &sh7706_bus_clk_ops,
         &sh7706_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7706_clk_ops))
                 *ops = sh7706_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index f302ba09e68..54a6d4bcc0d 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[idx];
 }
 
-static struct clk_ops sh7709_master_clk_ops = {
+static struct sh_clk_ops sh7709_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7709_module_clk_ops = {
+static struct sh_clk_ops sh7709_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -55,7 +55,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate * stc_multipliers[idx];
 }
 
-static struct clk_ops sh7709_bus_clk_ops = {
+static struct sh_clk_ops sh7709_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -67,18 +67,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7709_cpu_clk_ops = {
+static struct sh_clk_ops sh7709_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7709_clk_ops[] = {
+static struct sh_clk_ops *sh7709_clk_ops[] = {
         &sh7709_master_clk_ops,
         &sh7709_module_clk_ops,
         &sh7709_bus_clk_ops,
         &sh7709_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7709_clk_ops))
                 *ops = sh7709_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 29a87d8946a..ce601b2e397 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
 }
 
-static struct clk_ops sh7710_master_clk_ops = {
+static struct sh_clk_ops sh7710_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / md_table[idx];
 }
 
-static struct clk_ops sh7710_module_clk_ops = {
+static struct sh_clk_ops sh7710_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -49,7 +49,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / md_table[idx];
 }
 
-static struct clk_ops sh7710_bus_clk_ops = {
+static struct sh_clk_ops sh7710_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -59,18 +59,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / md_table[idx];
 }
 
-static struct clk_ops sh7710_cpu_clk_ops = {
+static struct sh_clk_ops sh7710_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7710_clk_ops[] = {
+static struct sh_clk_ops *sh7710_clk_ops[] = {
         &sh7710_master_clk_ops,
         &sh7710_module_clk_ops,
         &sh7710_bus_clk_ops,
         &sh7710_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7710_clk_ops))
                 *ops = sh7710_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index b0d0c520399..21438a9a1ae 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= multipliers[idx];
 }
 
-static struct clk_ops sh7712_master_clk_ops = {
+static struct sh_clk_ops sh7712_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -41,7 +41,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / divisors[idx];
 }
 
-static struct clk_ops sh7712_module_clk_ops = {
+static struct sh_clk_ops sh7712_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -53,17 +53,17 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / divisors[idx];
 }
 
-static struct clk_ops sh7712_cpu_clk_ops = {
+static struct sh_clk_ops sh7712_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7712_clk_ops[] = {
+static struct sh_clk_ops *sh7712_clk_ops[] = {
         &sh7712_master_clk_ops,
         &sh7712_module_clk_ops,
         &sh7712_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7712_clk_ops))
                 *ops = sh7712_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index f4e262adb39..4b5bab5f875 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -41,7 +41,7 @@ static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
         return 5;
 }
 
-static struct clk_ops sh4202_emi_clk_ops = {
+static struct sh_clk_ops sh4202_emi_clk_ops = {
         .recalc         = emi_clk_recalc,
 };
 
@@ -56,7 +56,7 @@ static unsigned long femi_clk_recalc(struct clk *clk)
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
-static struct clk_ops sh4202_femi_clk_ops = {
+static struct sh_clk_ops sh4202_femi_clk_ops = {
         .recalc         = femi_clk_recalc,
 };
 
@@ -130,7 +130,7 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops sh4202_shoc_clk_ops = {
+static struct sh_clk_ops sh4202_shoc_clk_ops = {
         .init           = shoc_clk_init,
         .recalc         = shoc_clk_recalc,
         .set_rate       = shoc_clk_set_rate,
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index 5add75c1f53..99e5ec8b483 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -31,7 +31,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];
 }
 
-static struct clk_ops sh4_master_clk_ops = {
+static struct sh_clk_ops sh4_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -41,7 +41,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh4_module_clk_ops = {
+static struct sh_clk_ops sh4_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -51,7 +51,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh4_bus_clk_ops = {
+static struct sh_clk_ops sh4_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -61,18 +61,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh4_cpu_clk_ops = {
+static struct sh_clk_ops sh4_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh4_clk_ops[] = {
+static struct sh_clk_ops *sh4_clk_ops[] = {
         &sh4_master_clk_ops,
         &sh4_module_clk_ops,
         &sh4_bus_clk_ops,
         &sh4_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh4_clk_ops))
                 *ops = sh4_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 70e45bdaadc..ea01a72f1b9 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -61,7 +61,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -81,7 +81,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 3c3165000c5..7ac07b4f75d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -61,7 +61,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -84,7 +84,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 212c72ef959..8e1f97010c0 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -64,7 +64,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -87,7 +87,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 2f8c9179da4..35f75cf0c7e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -65,7 +65,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -88,7 +88,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 70bd96646f4..2a87901673f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -70,7 +70,7 @@ static unsigned long fll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops fll_clk_ops = {
+static struct sh_clk_ops fll_clk_ops = {
         .recalc         = fll_recalc,
 };
 
@@ -90,7 +90,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
@@ -105,7 +105,7 @@ static unsigned long div3_recalc(struct clk *clk)
         return clk->parent->rate / 3;
 }
 
-static struct clk_ops div3_clk_ops = {
+static struct sh_clk_ops div3_clk_ops = {
         .recalc         = div3_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 0bd21c82151..5853989586e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -33,7 +33,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 2d4c7fd79c0..7707e35aea4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -27,7 +27,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
 }
 
-static struct clk_ops sh7763_master_clk_ops = {
+static struct sh_clk_ops sh7763_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -37,7 +37,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / p0fc_divisors[idx];
 }
 
-static struct clk_ops sh7763_module_clk_ops = {
+static struct sh_clk_ops sh7763_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -47,22 +47,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh7763_bus_clk_ops = {
+static struct sh_clk_ops sh7763_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static struct clk_ops sh7763_cpu_clk_ops = {
+static struct sh_clk_ops sh7763_cpu_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
-static struct clk_ops *sh7763_clk_ops[] = {
+static struct sh_clk_ops *sh7763_clk_ops[] = {
         &sh7763_master_clk_ops,
         &sh7763_module_clk_ops,
         &sh7763_bus_clk_ops,
         &sh7763_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7763_clk_ops))
                 *ops = sh7763_clk_ops[idx];
@@ -74,7 +74,7 @@ static unsigned long shyway_clk_recalc(struct clk *clk)
         return clk->parent->rate / cfc_divisors[idx];
 }
 
-static struct clk_ops sh7763_shyway_clk_ops = {
+static struct sh_clk_ops sh7763_shyway_clk_ops = {
         .recalc         = shyway_clk_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index 9e3354365d4..5d36f334bb0 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -24,7 +24,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
 }
 
-static struct clk_ops sh7770_master_clk_ops = {
+static struct sh_clk_ops sh7770_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -34,7 +34,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7770_module_clk_ops = {
+static struct sh_clk_ops sh7770_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -44,7 +44,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh7770_bus_clk_ops = {
+static struct sh_clk_ops sh7770_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -54,18 +54,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7770_cpu_clk_ops = {
+static struct sh_clk_ops sh7770_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7770_clk_ops[] = {
+static struct sh_clk_ops *sh7770_clk_ops[] = {
         &sh7770_master_clk_ops,
         &sh7770_module_clk_ops,
         &sh7770_bus_clk_ops,
         &sh7770_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7770_clk_ops))
                 *ops = sh7770_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 3b53348fe2f..793dae42a2f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -27,7 +27,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
 }
 
-static struct clk_ops sh7780_master_clk_ops = {
+static struct sh_clk_ops sh7780_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -37,7 +37,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7780_module_clk_ops = {
+static struct sh_clk_ops sh7780_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -47,7 +47,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh7780_bus_clk_ops = {
+static struct sh_clk_ops sh7780_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -57,18 +57,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7780_cpu_clk_ops = {
+static struct sh_clk_ops sh7780_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7780_clk_ops[] = {
+static struct sh_clk_ops *sh7780_clk_ops[] = {
         &sh7780_master_clk_ops,
         &sh7780_module_clk_ops,
         &sh7780_bus_clk_ops,
         &sh7780_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7780_clk_ops))
                 *ops = sh7780_clk_ops[idx];
@@ -80,7 +80,7 @@ static unsigned long shyway_clk_recalc(struct clk *clk)
         return clk->parent->rate / cfc_divisors[idx];
 }
 
-static struct clk_ops sh7780_shyway_clk_ops = {
+static struct sh_clk_ops sh7780_shyway_clk_ops = {
         .recalc         = shyway_clk_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 2b314439d35..ab1c58f2d10 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -36,7 +36,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index f6c0c3d5599..491709483e1 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -38,7 +38,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index bf2d00b8b90..0f11b392bf4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -32,7 +32,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * 72;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 9cfc19b8dbe..c48b93d4c08 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -28,7 +28,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= ifc_table[idx];
 }
 
-static struct clk_ops sh5_master_clk_ops = {
+static struct sh_clk_ops sh5_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -38,7 +38,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_table[idx];
 }
 
-static struct clk_ops sh5_module_clk_ops = {
+static struct sh_clk_ops sh5_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_table[idx];
 }
 
-static struct clk_ops sh5_bus_clk_ops = {
+static struct sh_clk_ops sh5_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_table[idx];
 }
 
-static struct clk_ops sh5_cpu_clk_ops = {
+static struct sh_clk_ops sh5_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh5_clk_ops[] = {
+static struct sh_clk_ops *sh5_clk_ops[] = {
         &sh5_master_clk_ops,
         &sh5_module_clk_ops,
         &sh5_bus_clk_ops,
         &sh5_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         cprc_base = (unsigned long)ioremap_nocache(CPRC_BASE, 1024);
         BUG_ON(!cprc_base);
diff --git a/arch/sh/kernel/vsyscall/vsyscall.c b/arch/sh/kernel/vsyscall/vsyscall.c
index 1d6d51a1ce7..5ca579720a0 100644
--- a/arch/sh/kernel/vsyscall/vsyscall.c
+++ b/arch/sh/kernel/vsyscall/vsyscall.c
@@ -73,8 +73,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         ret = install_special_mapping(mm, addr, PAGE_SIZE,
                                       VM_READ | VM_EXEC |
-                                      VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC |
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
                                       syscall_pages);
         if (unlikely(ret))
                 goto up_fail;
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index ca5580e4d81..1666de84d47 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -29,6 +29,7 @@ config SPARC
         select GENERIC_IRQ_SHOW
         select USE_GENERIC_SMP_HELPERS if SMP
         select GENERIC_PCI_IOMAP
+        select HAVE_NMI_WATCHDOG if SPARC64
 
 config SPARC32
         def_bool !64BIT
diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
index 16dcae6d56e..abf6afe82ca 100644
--- a/arch/sparc/include/asm/irq_64.h
+++ b/arch/sparc/include/asm/irq_64.h
@@ -95,7 +95,6 @@ void arch_trigger_all_cpu_backtrace(void);
 extern void *hardirq_stack[NR_CPUS];
 extern void *softirq_stack[NR_CPUS];
 #define __ARCH_HAS_DO_SOFTIRQ
-#define ARCH_HAS_NMI_WATCHDOG
 
 #define NO_IRQ          0xffffffff
 
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
index 6de7f7bf956..dc503297481 100644
--- a/arch/sparc/include/asm/pci_32.h
+++ b/arch/sparc/include/asm/pci_32.h
@@ -52,14 +52,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  * 64Kbytes by the Host controller.
  */
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
         return PCI_IRQ_NONE;
diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h
index 755a4bb6bcd..1633b718d3b 100644
--- a/arch/sparc/include/asm/pci_64.h
+++ b/arch/sparc/include/asm/pci_64.h
@@ -73,14 +73,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state,
                                int write_combine);
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
         return PCI_IRQ_NONE;
diff --git a/arch/sparc/include/asm/vga.h b/arch/sparc/include/asm/vga.h
index c69d5b2ba19..ec0e9967d93 100644
--- a/arch/sparc/include/asm/vga.h
+++ b/arch/sparc/include/asm/vga.h
@@ -7,6 +7,7 @@
 #ifndef _LINUX_ASM_VGA_H_
 #define _LINUX_ASM_VGA_H_
 
+#include <linux/bug.h>
 #include <asm/types.h>
 
 #define VT_BUF_HAVE_RW
diff --git a/arch/sparc/include/asm/vio.h b/arch/sparc/include/asm/vio.h
index 9d83d3bcb49..432afa83886 100644
--- a/arch/sparc/include/asm/vio.h
+++ b/arch/sparc/include/asm/vio.h
@@ -284,6 +284,7 @@ struct vio_dev {
 };
 
 struct vio_driver {
+        const char                      *name;
         struct list_head                node;
         const struct vio_device_id      *id_table;
         int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
@@ -371,7 +372,13 @@ do {	if (vio->debug & VIO_DEBUG_##TYPE) \
                        vio->vdev->channel_id, ## a); \
 } while (0)
 
-extern int vio_register_driver(struct vio_driver *drv);
+extern int __vio_register_driver(struct vio_driver *drv, struct module *owner,
+                                 const char *mod_name);
+/*
+ * vio_register_driver must be a macro so that KBUILD_MODNAME can be expanded
+ */
+#define vio_register_driver(driver)             \
+        __vio_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
 extern void vio_unregister_driver(struct vio_driver *drv);
 
 static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c
index 381edcd5bc2..fea13c7b1ae 100644
--- a/arch/sparc/kernel/ds.c
+++ b/arch/sparc/kernel/ds.c
@@ -1244,10 +1244,7 @@ static struct vio_driver ds_driver = {
         .id_table       = ds_match,
         .probe          = ds_probe,
         .remove         = ds_remove,
-        .driver         = {
-                .name   = "ds",
-                .owner  = THIS_MODULE,
-        }
+        .name           = "ds",
 };
 
 static int __init ds_init(void)
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index c7bec25fdb1..aba6b958b2a 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -15,14 +15,19 @@
 
 /* The LEON architecture does not rely on a BIOS or bootloader to setup
  * PCI for us. The Linux generic routines are used to setup resources,
- * reset values of confuration-space registers settings ae preseved.
+ * reset values of configuration-space register settings are preserved.
+ *
+ * PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
+ * accessed through a Window which is translated to low 64KB in PCI space, the
+ * first 4KB is not used so 60KB is available.
  */
 void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
 {
         LIST_HEAD(resources);
         struct pci_bus *root_bus;
 
-        pci_add_resource(&resources, &info->io_space);
+        pci_add_resource_offset(&resources, &info->io_space,
+                                info->io_space.start - 0x1000);
         pci_add_resource(&resources, &info->mem_space);
 
         root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info,
@@ -38,44 +43,6 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
         }
 }
 
-/* PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
- * accessed through a Window which is translated to low 64KB in PCI space, the
- * first 4KB is not used so 60KB is available.
- *
- * This function is used by generic code to translate resource addresses into
- * PCI addresses.
- */
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        struct leon_pci_info *info = dev->bus->sysdata;
-
-        region->start = res->start;
-        region->end = res->end;
-
-        if (res->flags & IORESOURCE_IO) {
-                region->start -= (info->io_space.start - 0x1000);
-                region->end -= (info->io_space.start - 0x1000);
-        }
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-/* see pcibios_resource_to_bus() comment */
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct leon_pci_info *info = dev->bus->sysdata;
-
-        res->start = region->start;
-        res->end = region->end;
-
-        if (res->flags & IORESOURCE_IO) {
-                res->start += (info->io_space.start - 0x1000);
-                res->end += (info->io_space.start - 0x1000);
-        }
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
 {
         struct leon_pci_info *info = pbus->sysdata;
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index bb8bc2e519a..fdaf2181167 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -375,13 +375,6 @@ static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
         *last_p = last;
 }
 
-static void pci_resource_adjust(struct resource *res,
-                                struct resource *root)
-{
-        res->start += root->start;
-        res->end += root->start;
-}
-
 /* For PCI bus devices which lack a 'ranges' property we interrogate
  * the config space values to set the resources, just like the generic
  * Linux PCI probing code does.
@@ -390,7 +383,8 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
                                           struct pci_bus *bus,
                                           struct pci_pbm_info *pbm)
 {
-        struct resource *res;
+        struct pci_bus_region region;
+        struct resource *res, res2;
         u8 io_base_lo, io_limit_lo;
         u16 mem_base_lo, mem_limit_lo;
         unsigned long base, limit;
@@ -412,11 +406,14 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
         res = bus->resource[0];
         if (base <= limit) {
                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
+                res2.flags = res->flags;
+                region.start = base;
+                region.end = limit + 0xfff;
+                pcibios_bus_to_resource(dev, &res2, &region);
                 if (!res->start)
-                        res->start = base;
+                        res->start = res2.start;
                 if (!res->end)
-                        res->end = limit + 0xfff;
-                pci_resource_adjust(res, &pbm->io_space);
+                        res->end = res2.end;
         }
 
         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
@@ -428,9 +425,9 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
         if (base <= limit) {
                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
                               IORESOURCE_MEM);
-                res->start = base;
-                res->end = limit + 0xfffff;
-                pci_resource_adjust(res, &pbm->mem_space);
+                region.start = base;
+                region.end = limit + 0xfffff;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 
         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
@@ -459,9 +456,9 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
         if (base <= limit) {
                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
                               IORESOURCE_MEM | IORESOURCE_PREFETCH);
-                res->start = base;
-                res->end = limit + 0xfffff;
-                pci_resource_adjust(res, &pbm->mem_space);
+                region.start = base;
+                region.end = limit + 0xfffff;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 }
 
@@ -472,6 +469,7 @@ static void __devinit apb_fake_ranges(struct pci_dev *dev,
                                       struct pci_bus *bus,
                                       struct pci_pbm_info *pbm)
 {
+        struct pci_bus_region region;
         struct resource *res;
         u32 first, last;
         u8 map;
@@ -479,18 +477,18 @@ static void __devinit apb_fake_ranges(struct pci_dev *dev,
         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
         apb_calc_first_last(map, &first, &last);
         res = bus->resource[0];
-        res->start = (first << 21);
-        res->end = (last << 21) + ((1 << 21) - 1);
         res->flags = IORESOURCE_IO;
-        pci_resource_adjust(res, &pbm->io_space);
+        region.start = (first << 21);
+        region.end = (last << 21) + ((1 << 21) - 1);
+        pcibios_bus_to_resource(dev, res, &region);
 
         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
         apb_calc_first_last(map, &first, &last);
         res = bus->resource[1];
-        res->start = (first << 21);
-        res->end = (last << 21) + ((1 << 21) - 1);
         res->flags = IORESOURCE_MEM;
-        pci_resource_adjust(res, &pbm->mem_space);
+        region.start = (first << 21);
+        region.end = (last << 21) + ((1 << 21) - 1);
+        pcibios_bus_to_resource(dev, res, &region);
 }
 
 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
@@ -506,6 +504,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
         struct pci_bus *bus;
         const u32 *busrange, *ranges;
         int len, i, simba;
+        struct pci_bus_region region;
         struct resource *res;
         unsigned int flags;
         u64 size;
@@ -556,8 +555,6 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
         }
         i = 1;
         for (; len >= 32; len -= 32, ranges += 8) {
-                struct resource *root;
-
                 flags = pci_parse_of_flags(ranges[0]);
                 size = GET_64BIT(ranges, 6);
                 if (flags == 0 || size == 0)
@@ -569,7 +566,6 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
                                        " for bridge %s\n", node->full_name);
                                 continue;
                         }
-                        root = &pbm->io_space;
                 } else {
                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
                                 printk(KERN_ERR "PCI: too many memory ranges"
@@ -578,18 +574,12 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
                         }
                         res = bus->resource[i];
                         ++i;
-                        root = &pbm->mem_space;
                 }
 
-                res->start = GET_64BIT(ranges, 1);
-                res->end = res->start + size - 1;
                 res->flags = flags;
-
-                /* Another way to implement this would be to add an of_device
-                 * layer routine that can calculate a resource for a given
-                 * range property value in a PCI device.
-                 */
-                pci_resource_adjust(res, root);
+                region.start = GET_64BIT(ranges, 1);
+                region.end = region.start + size - 1;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 after_ranges:
         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
@@ -691,8 +681,10 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
 
         printk("PCI: Scanning PBM %s\n", node->full_name);
 
-        pci_add_resource(&resources, &pbm->io_space);
-        pci_add_resource(&resources, &pbm->mem_space);
+        pci_add_resource_offset(&resources, &pbm->io_space,
+                                pbm->io_space.start);
+        pci_add_resource_offset(&resources, &pbm->mem_space,
+                                pbm->mem_space.start);
         bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
                                   pbm, &resources);
         if (!bus) {
@@ -755,46 +747,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return 0;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        struct pci_pbm_info *pbm = pdev->bus->sysdata;
-        struct resource zero_res, *root;
-
-        zero_res.start = 0;
-        zero_res.end = 0;
-        zero_res.flags = res->flags;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &pbm->io_space;
-        else
-                root = &pbm->mem_space;
-
-        pci_resource_adjust(&zero_res, root);
-
-        region->start = res->start - zero_res.start;
-        region->end = res->end - zero_res.start;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct pci_pbm_info *pbm = pdev->bus->sysdata;
-        struct resource *root;
-
-        res->start = region->start;
-        res->end = region->end;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &pbm->io_space;
-        else
-                root = &pbm->mem_space;
-
-        pci_resource_adjust(res, root);
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
 char * __devinit pcibios_setup(char *str)
 {
         return str;
diff --git a/arch/sparc/kernel/vio.c b/arch/sparc/kernel/vio.c
index f67e28ef598..5cffdc55f07 100644
--- a/arch/sparc/kernel/vio.c
+++ b/arch/sparc/kernel/vio.c
@@ -119,13 +119,17 @@ static struct bus_type vio_bus_type = {
         .remove         = vio_device_remove,
 };
 
-int vio_register_driver(struct vio_driver *viodrv)
+int __vio_register_driver(struct vio_driver *viodrv, struct module *owner,
+                        const char *mod_name)
 {
         viodrv->driver.bus = &vio_bus_type;
+        viodrv->driver.name = viodrv->name;
+        viodrv->driver.owner = owner;
+        viodrv->driver.mod_name = mod_name;
 
         return driver_register(&viodrv->driver);
 }
-EXPORT_SYMBOL(vio_register_driver);
+EXPORT_SYMBOL(__vio_register_driver);
 
 void vio_unregister_driver(struct vio_driver *viodrv)
 {
diff --git a/arch/tile/mm/elf.c b/arch/tile/mm/elf.c
index 33368d1aea9..758b6038c2b 100644
--- a/arch/tile/mm/elf.c
+++ b/arch/tile/mm/elf.c
@@ -118,17 +118,11 @@ int arch_setup_additional_pages(struct linux_binprm *bprm,
 
         /*
          * MAYWRITE to allow gdb to COW and set breakpoints
-         *
-         * Make sure the vDSO gets into every core dump.  Dumping its
-         * contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to
-         * see what PC values meant.
          */
         vdso_base = VDSO_BASE;
         retval = install_special_mapping(mm, vdso_base, PAGE_SIZE,
                                          VM_READ|VM_EXEC|
-                                         VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                         VM_ALWAYSDUMP,
+                                         VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                          vdso_pages);
 
 #ifndef __tilegx__
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index b37ae706af3..20a49ba93cb 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -9,6 +9,7 @@ config UML
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_SHOW
         select GENERIC_CPU_DEVICES
+        select GENERIC_IO
 
 config MMU
         bool
diff --git a/arch/um/Makefile b/arch/um/Makefile
index 28688e6d96d..55c0661e2b5 100644
--- a/arch/um/Makefile
+++ b/arch/um/Makefile
@@ -28,6 +28,7 @@ ifeq ($(SUBARCH),i386)
 endif
 ifeq ($(SUBARCH),x86_64)
         HEADER_ARCH := x86
+        KBUILD_CFLAGS += -mcmodel=large
 endif
 
 HOST_DIR := arch/$(HEADER_ARCH)
@@ -50,7 +51,7 @@ KBUILD_CPPFLAGS += -I$(srctree)/$(HOST_DIR)/um
 #
 # These apply to USER_CFLAGS to.
 
-KBUILD_CFLAGS += $(CFLAGS) $(CFLAGS-y) -D__arch_um__ -DSUBARCH=\"$(SUBARCH)\" \
+KBUILD_CFLAGS += $(CFLAGS) $(CFLAGS-y) -D__arch_um__ \
         $(ARCH_INCLUDE) $(MODE_INCLUDE) -Dvmap=kernel_vmap      \
         -Din6addr_loopback=kernel_in6addr_loopback \
         -Din6addr_any=kernel_in6addr_any -Dstrrchr=kernel_strrchr
@@ -99,7 +100,7 @@ KBUILD_KCONFIG := $(HOST_DIR)/um/Kconfig
 
 archheaders:
         $(Q)$(MAKE) -C '$(srctree)' KBUILD_SRC= \
-                ARCH=$(SUBARCH) O='$(objtree)' archheaders
+                ARCH=$(HEADER_ARCH) O='$(objtree)' archheaders
 
 archprepare: include/generated/user_constants.h
 
diff --git a/arch/um/defconfig b/arch/um/defconfig
index 761f5e1a657..fdc97e2c3d7 100644
--- a/arch/um/defconfig
+++ b/arch/um/defconfig
@@ -1,10 +1,8 @@
 #
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24
-# Thu Feb  7 11:48:55 2008
+# Automatically generated file; DO NOT EDIT.
+# User Mode Linux/i386 3.3.0 Kernel Configuration
 #
 CONFIG_DEFCONFIG_LIST="arch/$ARCH/defconfig"
-CONFIG_GENERIC_HARDIRQS=y
 CONFIG_UML=y
 CONFIG_MMU=y
 CONFIG_NO_IOMEM=y
@@ -20,12 +18,10 @@ CONFIG_HZ=100
 #
 # UML-specific options
 #
-# CONFIG_STATIC_LINK is not set
 
 #
 # Host processor type and features
 #
-# CONFIG_M386 is not set
 # CONFIG_M486 is not set
 # CONFIG_M586 is not set
 # CONFIG_M586TSC is not set
@@ -41,17 +37,17 @@ CONFIG_M686=y
 # CONFIG_MCRUSOE is not set
 # CONFIG_MEFFICEON is not set
 # CONFIG_MWINCHIPC6 is not set
-# CONFIG_MWINCHIP2 is not set
 # CONFIG_MWINCHIP3D is not set
+# CONFIG_MELAN is not set
 # CONFIG_MGEODEGX1 is not set
 # CONFIG_MGEODE_LX is not set
 # CONFIG_MCYRIXIII is not set
 # CONFIG_MVIAC3_2 is not set
 # CONFIG_MVIAC7 is not set
-# CONFIG_MPSC is not set
 # CONFIG_MCORE2 is not set
-# CONFIG_GENERIC_CPU is not set
+# CONFIG_MATOM is not set
 # CONFIG_X86_GENERIC is not set
+CONFIG_X86_INTERNODE_CACHE_SHIFT=5
 CONFIG_X86_CMPXCHG=y
 CONFIG_X86_L1_CACHE_SHIFT=5
 CONFIG_X86_XADD=y
@@ -60,47 +56,59 @@ CONFIG_X86_WP_WORKS_OK=y
 CONFIG_X86_INVLPG=y
 CONFIG_X86_BSWAP=y
 CONFIG_X86_POPAD_OK=y
-CONFIG_X86_GOOD_APIC=y
 CONFIG_X86_USE_PPRO_CHECKSUM=y
 CONFIG_X86_TSC=y
+CONFIG_X86_CMPXCHG64=y
 CONFIG_X86_CMOV=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=4
-CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=5
+CONFIG_CPU_SUP_INTEL=y
+CONFIG_CPU_SUP_CYRIX_32=y
+CONFIG_CPU_SUP_AMD=y
+CONFIG_CPU_SUP_CENTAUR=y
+CONFIG_CPU_SUP_TRANSMETA_32=y
+CONFIG_CPU_SUP_UMC_32=y
 CONFIG_UML_X86=y
-CONFIG_X86_32=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 # CONFIG_64BIT is not set
-CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_X86_32=y
+# CONFIG_X86_64 is not set
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_3_LEVEL_PGTABLES is not set
 CONFIG_ARCH_HAS_SC_SIGNALS=y
 CONFIG_ARCH_REUSE_HOST_VSYSCALL_AREA=y
 CONFIG_GENERIC_HWEIGHT=y
+# CONFIG_STATIC_LINK is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_LD_SCRIPT_DYN=y
 CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_HOSTFS=y
 # CONFIG_HPPFS is not set
 CONFIG_MCONSOLE=y
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_HIGHMEM is not set
 CONFIG_KERNEL_STACK_ORDER=0
+# CONFIG_MMAPPER is not set
+CONFIG_NO_DMA=y
 
 #
 # General setup
@@ -108,99 +116,169 @@ CONFIG_KERNEL_STACK_ORDER=0
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=128
+CONFIG_CROSS_COMPILE=""
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_FHANDLE is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_SHOW=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TINY_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_TREE_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+# CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED is not set
+# CONFIG_CGROUP_MEM_RES_CTLR_KMEM is not set
+CONFIG_CGROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_BLK_CGROUP=m
+# CONFIG_DEBUG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+CONFIG_MM_OWNER=y
 CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 # CONFIG_EXPERT is not set
 CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+# CONFIG_EMBEDDED is not set
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-# CONFIG_HAVE_OPROFILE is not set
-# CONFIG_HAVE_KPROBES is not set
-CONFIG_PROC_PAGE_MONITOR=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=m
+# CONFIG_CFQ_GROUP_IOSCHED is not set
+CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_BLK_DEV=y
-CONFIG_BLK_DEV_UBD=y
-# CONFIG_BLK_DEV_UBD_SYNC is not set
-CONFIG_BLK_DEV_COW_COMMON=y
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_ATA_OVER_ETH is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
-# Character Devices
+# UML Character Devices
 #
 CONFIG_STDERR_CONSOLE=y
 CONFIG_STDIO_CONSOLE=y
@@ -214,40 +292,191 @@ CONFIG_XTERM_CHAN=y
 CONFIG_CON_ZERO_CHAN="fd:0,fd:1"
 CONFIG_CON_CHAN="xterm"
 CONFIG_SSL_CHAN="pts"
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-# CONFIG_RAW_DRIVER is not set
-CONFIG_LEGACY_PTY_COUNT=32
-# CONFIG_WATCHDOG is not set
 CONFIG_UML_SOUND=m
 CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_HOSTAUDIO=m
-# CONFIG_HW_RANDOM is not set
-CONFIG_UML_RANDOM=y
-# CONFIG_MMAPPER is not set
+
+#
+# Device Drivers
+#
 
 #
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
+CONFIG_GENERIC_CPU_DEVICES=y
+# CONFIG_DMA_SHARED_BUFFER is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_UBD=y
+# CONFIG_BLK_DEV_UBD_SYNC is not set
+CONFIG_BLK_DEV_COW_COMMON=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+
+#
+# Altera FPGA firmware download module
+#
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+CONFIG_DUMMY=m
+# CONFIG_EQUALIZER is not set
+# CONFIG_MII is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_CHELSIO=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_PHYLIB is not set
+CONFIG_PPP=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_SLIP=m
+CONFIG_SLHC=m
+# CONFIG_SLIP_COMPRESSED is not set
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+CONFIG_WLAN=y
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+
+#
+# Character devices
+#
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_UML_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_NSC_GPIO is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_REGULATOR is not set
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_BALLOON is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_STAGING is not set
 
 #
-# Networking
+# Hardware Spinlock drivers
 #
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
 CONFIG_NET=y
 
 #
 # Networking options
 #
 CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
@@ -257,10 +486,9 @@ CONFIG_XFRM=y
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
 # CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_INET_AH is not set
@@ -274,20 +502,23 @@ CONFIG_INET_XFRM_MODE_BEET=y
 # CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_UDP_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+# CONFIG_L2TP is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -297,7 +528,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
 
 #
 # Network testing
@@ -308,16 +546,19 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
 
 #
-# Wireless
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
 
 #
 # UML Network Devices
@@ -331,76 +572,51 @@ CONFIG_UML_NET_DAEMON=y
 CONFIG_UML_NET_MCAST=y
 # CONFIG_UML_NET_PCAP is not set
 CONFIG_UML_NET_SLIRP=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-CONFIG_TUN=m
-# CONFIG_VETH is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-# CONFIG_PPP_ASYNC is not set
-# CONFIG_PPP_SYNC_TTY is not set
-# CONFIG_PPP_DEFLATE is not set
-# CONFIG_PPP_BSDCOMP is not set
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-CONFIG_SLIP=m
-# CONFIG_SLIP_COMPRESSED is not set
-CONFIG_SLHC=m
-# CONFIG_SLIP_SMART is not set
-# CONFIG_SLIP_MODE_SLIP6 is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_CONNECTOR is not set
 
 #
 # File systems
 #
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT23=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
 CONFIG_REISERFS_FS=y
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_REISERFS_FS_XATTR is not set
 # CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
 CONFIG_QUOTA=y
 # CONFIG_QUOTA_NETLINK_INTERFACE is not set
 CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QUOTA_DEBUG is not set
 # CONFIG_QFMT_V1 is not set
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 CONFIG_ISO9660_FS=m
@@ -421,15 +637,14 @@ CONFIG_JOLIET=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -437,26 +652,26 @@ CONFIG_TMPFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
-# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_437 is not set
@@ -497,119 +712,191 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-# CONFIG_DLM is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
 # CONFIG_SECURITY is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=m
 # CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_TWOFISH_586 is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
 # CONFIG_CRYPTO_AES_586 is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_SALSA20_586 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_TWOFISH_586 is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
-CONFIG_BITREVERSE=m
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_IO=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=m
+CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_MD is not set
-# CONFIG_INPUT is not set
+# CONFIG_CRC8 is not set
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
+# CONFIG_CORDIC is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_DETECT_HUNG_TASK is not set
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
 # CONFIG_SAMPLES is not set
+# CONFIG_TEST_KSTRTOX is not set
 # CONFIG_GPROF is not set
 # CONFIG_GCOV is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/um/drivers/chan.h b/arch/um/drivers/chan.h
index 8df0fd9024d..02b5a76e98d 100644
--- a/arch/um/drivers/chan.h
+++ b/arch/um/drivers/chan.h
@@ -27,24 +27,24 @@ struct chan {
         void *data;
 };
 
-extern void chan_interrupt(struct list_head *chans, struct delayed_work *task,
+extern void chan_interrupt(struct line *line,
                            struct tty_struct *tty, int irq);
 extern int parse_chan_pair(char *str, struct line *line, int device,
                            const struct chan_opts *opts, char **error_out);
-extern int write_chan(struct list_head *chans, const char *buf, int len,
+extern int write_chan(struct chan *chan, const char *buf, int len,
                              int write_irq);
-extern int console_write_chan(struct list_head *chans, const char *buf, 
+extern int console_write_chan(struct chan *chan, const char *buf, 
                               int len);
 extern int console_open_chan(struct line *line, struct console *co);
-extern void deactivate_chan(struct list_head *chans, int irq);
-extern void reactivate_chan(struct list_head *chans, int irq);
-extern void chan_enable_winch(struct list_head *chans, struct tty_struct *tty);
+extern void deactivate_chan(struct chan *chan, int irq);
+extern void reactivate_chan(struct chan *chan, int irq);
+extern void chan_enable_winch(struct chan *chan, struct tty_struct *tty);
 extern int enable_chan(struct line *line);
-extern void close_chan(struct list_head *chans, int delay_free_irq);
-extern int chan_window_size(struct list_head *chans, 
+extern void close_chan(struct line *line);
+extern int chan_window_size(struct line *line, 
                              unsigned short *rows_out, 
                              unsigned short *cols_out);
-extern int chan_config_string(struct list_head *chans, char *str, int size,
+extern int chan_config_string(struct line *line, char *str, int size,
                               char **error_out);
 
 #endif
diff --git a/arch/um/drivers/chan_kern.c b/arch/um/drivers/chan_kern.c
index 420e2c80079..ca4c7ebfd0a 100644
--- a/arch/um/drivers/chan_kern.c
+++ b/arch/um/drivers/chan_kern.c
@@ -140,18 +140,18 @@ static int open_chan(struct list_head *chans)
         return err;
 }
 
-void chan_enable_winch(struct list_head *chans, struct tty_struct *tty)
+void chan_enable_winch(struct chan *chan, struct tty_struct *tty)
 {
-        struct list_head *ele;
-        struct chan *chan;
+        if (chan && chan->primary && chan->ops->winch)
+                register_winch(chan->fd, tty);
+}
 
-        list_for_each(ele, chans) {
-                chan = list_entry(ele, struct chan, list);
-                if (chan->primary && chan->output && chan->ops->winch) {
-                        register_winch(chan->fd, tty);
-                        return;
-                }
-        }
+static void line_timer_cb(struct work_struct *work)
+{
+        struct line *line = container_of(work, struct line, task.work);
+
+        if (!line->throttled)
+                chan_interrupt(line, line->tty, line->driver->read_irq);
 }
 
 int enable_chan(struct line *line)
@@ -160,6 +160,8 @@ int enable_chan(struct line *line)
         struct chan *chan;
         int err;
 
+        INIT_DELAYED_WORK(&line->task, line_timer_cb);
+
         list_for_each(ele, &line->chan_list) {
                 chan = list_entry(ele, struct chan, list);
                 err = open_one_chan(chan);
@@ -183,7 +185,7 @@ int enable_chan(struct line *line)
         return 0;
 
  out_close:
-        close_chan(&line->chan_list, 0);
+        close_chan(line);
         return err;
 }
 
@@ -244,7 +246,7 @@ static void close_one_chan(struct chan *chan, int delay_free_irq)
         chan->fd = -1;
 }
 
-void close_chan(struct list_head *chans, int delay_free_irq)
+void close_chan(struct line *line)
 {
         struct chan *chan;
 
@@ -253,77 +255,50 @@ void close_chan(struct list_head *chans, int delay_free_irq)
          * state.  Then, the first one opened will have the original state,
          * so it must be the last closed.
          */
-        list_for_each_entry_reverse(chan, chans, list) {
-                close_one_chan(chan, delay_free_irq);
+        list_for_each_entry_reverse(chan, &line->chan_list, list) {
+                close_one_chan(chan, 0);
         }
 }
 
-void deactivate_chan(struct list_head *chans, int irq)
+void deactivate_chan(struct chan *chan, int irq)
 {
-        struct list_head *ele;
-
-        struct chan *chan;
-        list_for_each(ele, chans) {
-                chan = list_entry(ele, struct chan, list);
-
-                if (chan->enabled && chan->input)
-                        deactivate_fd(chan->fd, irq);
-        }
+        if (chan && chan->enabled)
+                deactivate_fd(chan->fd, irq);
 }
 
-void reactivate_chan(struct list_head *chans, int irq)
+void reactivate_chan(struct chan *chan, int irq)
 {
-        struct list_head *ele;
-        struct chan *chan;
-
-        list_for_each(ele, chans) {
-                chan = list_entry(ele, struct chan, list);
-
-                if (chan->enabled && chan->input)
-                        reactivate_fd(chan->fd, irq);
-        }
+        if (chan && chan->enabled)
+                reactivate_fd(chan->fd, irq);
 }
 
-int write_chan(struct list_head *chans, const char *buf, int len,
+int write_chan(struct chan *chan, const char *buf, int len,
                int write_irq)
 {
-        struct list_head *ele;
-        struct chan *chan = NULL;
         int n, ret = 0;
 
-        if (len == 0)
+        if (len == 0 || !chan || !chan->ops->write)
                 return 0;
 
-        list_for_each(ele, chans) {
-                chan = list_entry(ele, struct chan, list);
-                if (!chan->output || (chan->ops->write == NULL))
-                        continue;
-
-                n = chan->ops->write(chan->fd, buf, len, chan->data);
-                if (chan->primary) {
-                        ret = n;
-                        if ((ret == -EAGAIN) || ((ret >= 0) && (ret < len)))
-                                reactivate_fd(chan->fd, write_irq);
-                }
+        n = chan->ops->write(chan->fd, buf, len, chan->data);
+        if (chan->primary) {
+                ret = n;
+                if ((ret == -EAGAIN) || ((ret >= 0) && (ret < len)))
+                        reactivate_fd(chan->fd, write_irq);
         }
         return ret;
 }
 
-int console_write_chan(struct list_head *chans, const char *buf, int len)
+int console_write_chan(struct chan *chan, const char *buf, int len)
 {
-        struct list_head *ele;
-        struct chan *chan;
         int n, ret = 0;
 
-        list_for_each(ele, chans) {
-                chan = list_entry(ele, struct chan, list);
-                if (!chan->output || (chan->ops->console_write == NULL))
-                        continue;
+        if (!chan || !chan->ops->console_write)
+                return 0;
 
-                n = chan->ops->console_write(chan->fd, buf, len);
-                if (chan->primary)
-                        ret = n;
-        }
+        n = chan->ops->console_write(chan->fd, buf, len);
+        if (chan->primary)
+                ret = n;
         return ret;
 }
 
@@ -340,20 +315,24 @@ int console_open_chan(struct line *line, struct console *co)
         return 0;
 }
 
-int chan_window_size(struct list_head *chans, unsigned short *rows_out,
+int chan_window_size(struct line *line, unsigned short *rows_out,
                       unsigned short *cols_out)
 {
-        struct list_head *ele;
         struct chan *chan;
 
-        list_for_each(ele, chans) {
-                chan = list_entry(ele, struct chan, list);
-                if (chan->primary) {
-                        if (chan->ops->window_size == NULL)
-                                return 0;
-                        return chan->ops->window_size(chan->fd, chan->data,
-                                                      rows_out, cols_out);
-                }
+        chan = line->chan_in;
+        if (chan && chan->primary) {
+                if (chan->ops->window_size == NULL)
+                        return 0;
+                return chan->ops->window_size(chan->fd, chan->data,
+                                              rows_out, cols_out);
+        }
+        chan = line->chan_out;
+        if (chan && chan->primary) {
+                if (chan->ops->window_size == NULL)
+                        return 0;
+                return chan->ops->window_size(chan->fd, chan->data,
+                                              rows_out, cols_out);
         }
         return 0;
 }
@@ -429,21 +408,15 @@ static int chan_pair_config_string(struct chan *in, struct chan *out,
         return n;
 }
 
-int chan_config_string(struct list_head *chans, char *str, int size,
+int chan_config_string(struct line *line, char *str, int size,
                        char **error_out)
 {
-        struct list_head *ele;
-        struct chan *chan, *in = NULL, *out = NULL;
+        struct chan *in = line->chan_in, *out = line->chan_out;
 
-        list_for_each(ele, chans) {
-                chan = list_entry(ele, struct chan, list);
-                if (!chan->primary)
-                        continue;
-                if (chan->input)
-                        in = chan;
-                if (chan->output)
-                        out = chan;
-        }
+        if (in && !in->primary)
+                in = NULL;
+        if (out && !out->primary)
+                out = NULL;
 
         return chan_pair_config_string(in, out, str, size, error_out);
 }
@@ -547,10 +520,14 @@ int parse_chan_pair(char *str, struct line *line, int device,
         char *in, *out;
 
         if (!list_empty(chans)) {
+                line->chan_in = line->chan_out = NULL;
                 free_chan(chans);
                 INIT_LIST_HEAD(chans);
         }
 
+        if (!str)
+                return 0;
+
         out = strchr(str, ',');
         if (out != NULL) {
                 in = str;
@@ -562,6 +539,7 @@ int parse_chan_pair(char *str, struct line *line, int device,
 
                 new->input = 1;
                 list_add(&new->list, chans);
+                line->chan_in = new;
 
                 new = parse_chan(line, out, device, opts, error_out);
                 if (new == NULL)
@@ -569,6 +547,7 @@ int parse_chan_pair(char *str, struct line *line, int device,
 
                 list_add(&new->list, chans);
                 new->output = 1;
+                line->chan_out = new;
         }
         else {
                 new = parse_chan(line, str, device, opts, error_out);
@@ -578,43 +557,42 @@ int parse_chan_pair(char *str, struct line *line, int device,
                 list_add(&new->list, chans);
                 new->input = 1;
                 new->output = 1;
+                line->chan_in = line->chan_out = new;
         }
         return 0;
 }
 
-void chan_interrupt(struct list_head *chans, struct delayed_work *task,
-                    struct tty_struct *tty, int irq)
+void chan_interrupt(struct line *line, struct tty_struct *tty, int irq)
 {
-        struct list_head *ele, *next;
-        struct chan *chan;
+        struct chan *chan = line->chan_in;
         int err;
         char c;
 
-        list_for_each_safe(ele, next, chans) {
-                chan = list_entry(ele, struct chan, list);
-                if (!chan->input || (chan->ops->read == NULL))
-                        continue;
-                do {
-                        if (tty && !tty_buffer_request_room(tty, 1)) {
-                                schedule_delayed_work(task, 1);
-                                goto out;
-                        }
-                        err = chan->ops->read(chan->fd, &c, chan->data);
-                        if (err > 0)
-                                tty_receive_char(tty, c);
-                } while (err > 0);
-
-                if (err == 0)
-                        reactivate_fd(chan->fd, irq);
-                if (err == -EIO) {
-                        if (chan->primary) {
-                                if (tty != NULL)
-                                        tty_hangup(tty);
-                                close_chan(chans, 1);
-                                return;
-                        }
-                        else close_one_chan(chan, 1);
+        if (!chan || !chan->ops->read)
+                goto out;
+
+        do {
+                if (tty && !tty_buffer_request_room(tty, 1)) {
+                        schedule_delayed_work(&line->task, 1);
+                        goto out;
                 }
+                err = chan->ops->read(chan->fd, &c, chan->data);
+                if (err > 0)
+                        tty_receive_char(tty, c);
+        } while (err > 0);
+
+        if (err == 0)
+                reactivate_fd(chan->fd, irq);
+        if (err == -EIO) {
+                if (chan->primary) {
+                        if (tty != NULL)
+                                tty_hangup(tty);
+                        if (line->chan_out != chan)
+                                close_one_chan(line->chan_out, 1);
+                }
+                close_one_chan(chan, 1);
+                if (chan->primary)
+                        return;
         }
  out:
         if (tty)
diff --git a/arch/um/drivers/chan_user.h b/arch/um/drivers/chan_user.h
index 9b9ced85b70..6257b7a6e1a 100644
--- a/arch/um/drivers/chan_user.h
+++ b/arch/um/drivers/chan_user.h
@@ -14,8 +14,6 @@ struct chan_opts {
         const int raw;
 };
 
-enum chan_init_pri { INIT_STATIC, INIT_ALL, INIT_ONE };
-
 struct chan_ops {
         char *type;
         void *(*init)(char *, int, const struct chan_opts *);
diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c
index c1cf2206b84..4ab0d9c0911 100644
--- a/arch/um/drivers/line.c
+++ b/arch/um/drivers/line.c
@@ -21,19 +21,10 @@ static irqreturn_t line_interrupt(int irq, void *data)
         struct line *line = chan->line;
 
         if (line)
-                chan_interrupt(&line->chan_list, &line->task, line->tty, irq);
+                chan_interrupt(line, line->tty, irq);
         return IRQ_HANDLED;
 }
 
-static void line_timer_cb(struct work_struct *work)
-{
-        struct line *line = container_of(work, struct line, task.work);
-
-        if (!line->throttled)
-                chan_interrupt(&line->chan_list, &line->task, line->tty,
-                               line->driver->read_irq);
-}
-
 /*
  * Returns the free space inside the ring buffer of this line.
  *
@@ -145,7 +136,7 @@ static int flush_buffer(struct line *line)
                 /* line->buffer + LINE_BUFSIZE is the end of the buffer! */
                 count = line->buffer + LINE_BUFSIZE - line->head;
 
-                n = write_chan(&line->chan_list, line->head, count,
+                n = write_chan(line->chan_out, line->head, count,
                                line->driver->write_irq);
                 if (n < 0)
                         return n;
@@ -162,7 +153,7 @@ static int flush_buffer(struct line *line)
         }
 
         count = line->tail - line->head;
-        n = write_chan(&line->chan_list, line->head, count,
+        n = write_chan(line->chan_out, line->head, count,
                        line->driver->write_irq);
 
         if (n < 0)
@@ -206,7 +197,7 @@ int line_write(struct tty_struct *tty, const unsigned char *buf, int len)
         if (line->head != line->tail)
                 ret = buffer_data(line, buf, len);
         else {
-                n = write_chan(&line->chan_list, buf, len,
+                n = write_chan(line->chan_out, buf, len,
                                line->driver->write_irq);
                 if (n < 0) {
                         ret = n;
@@ -318,7 +309,7 @@ void line_throttle(struct tty_struct *tty)
 {
         struct line *line = tty->driver_data;
 
-        deactivate_chan(&line->chan_list, line->driver->read_irq);
+        deactivate_chan(line->chan_in, line->driver->read_irq);
         line->throttled = 1;
 }
 
@@ -327,8 +318,7 @@ void line_unthrottle(struct tty_struct *tty)
         struct line *line = tty->driver_data;
 
         line->throttled = 0;
-        chan_interrupt(&line->chan_list, &line->task, tty,
-                       line->driver->read_irq);
+        chan_interrupt(line, tty, line->driver->read_irq);
 
         /*
          * Maybe there is enough stuff pending that calling the interrupt
@@ -336,7 +326,7 @@ void line_unthrottle(struct tty_struct *tty)
          * again and we shouldn't turn the interrupt back on.
          */
         if (!line->throttled)
-                reactivate_chan(&line->chan_list, line->driver->read_irq);
+                reactivate_chan(line->chan_in, line->driver->read_irq);
 }
 
 static irqreturn_t line_write_interrupt(int irq, void *data)
@@ -347,13 +337,14 @@ static irqreturn_t line_write_interrupt(int irq, void *data)
         int err;
 
         /*
-         * Interrupts are disabled here because we registered the interrupt with
-         * IRQF_DISABLED (see line_setup_irq).
+         * Interrupts are disabled here because genirq keep irqs disabled when
+         * calling the action handler.
          */
 
         spin_lock(&line->lock);
         err = flush_buffer(line);
         if (err == 0) {
+                spin_unlock(&line->lock);
                 return IRQ_NONE;
         } else if (err < 0) {
                 line->head = line->buffer;
@@ -371,7 +362,7 @@ static irqreturn_t line_write_interrupt(int irq, void *data)
 int line_setup_irq(int fd, int input, int output, struct line *line, void *data)
 {
         const struct line_driver *driver = line->driver;
-        int err = 0, flags = IRQF_DISABLED | IRQF_SHARED | IRQF_SAMPLE_RANDOM;
+        int err = 0, flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
 
         if (input)
                 err = um_request_irq(driver->read_irq, fd, IRQ_READ,
@@ -383,7 +374,6 @@ int line_setup_irq(int fd, int input, int output, struct line *line, void *data)
                 err = um_request_irq(driver->write_irq, fd, IRQ_WRITE,
                                         line_write_interrupt, flags,
                                         driver->write_irq_name, data);
-        line->have_irq = 1;
         return err;
 }
 
@@ -409,7 +399,7 @@ int line_open(struct line *lines, struct tty_struct *tty)
         struct line *line = &lines[tty->index];
         int err = -ENODEV;
 
-        spin_lock(&line->count_lock);
+        mutex_lock(&line->count_lock);
         if (!line->valid)
                 goto out_unlock;
 
@@ -421,25 +411,19 @@ int line_open(struct line *lines, struct tty_struct *tty)
         tty->driver_data = line;
         line->tty = tty;
 
-        spin_unlock(&line->count_lock);
         err = enable_chan(line);
         if (err) /* line_close() will be called by our caller */
-                return err;
-
-        INIT_DELAYED_WORK(&line->task, line_timer_cb);
+                goto out_unlock;
 
         if (!line->sigio) {
-                chan_enable_winch(&line->chan_list, tty);
+                chan_enable_winch(line->chan_out, tty);
                 line->sigio = 1;
         }
 
-        chan_window_size(&line->chan_list, &tty->winsize.ws_row,
+        chan_window_size(line, &tty->winsize.ws_row,
                          &tty->winsize.ws_col);
-
-        return 0;
-
 out_unlock:
-        spin_unlock(&line->count_lock);
+        mutex_unlock(&line->count_lock);
         return err;
 }
 
@@ -459,7 +443,7 @@ void line_close(struct tty_struct *tty, struct file * filp)
         /* We ignore the error anyway! */
         flush_buffer(line);
 
-        spin_lock(&line->count_lock);
+        mutex_lock(&line->count_lock);
         BUG_ON(!line->valid);
 
         if (--line->count)
@@ -468,17 +452,13 @@ void line_close(struct tty_struct *tty, struct file * filp)
         line->tty = NULL;
         tty->driver_data = NULL;
 
-        spin_unlock(&line->count_lock);
-
         if (line->sigio) {
                 unregister_winch(tty);
                 line->sigio = 0;
         }
 
-        return;
-
 out_unlock:
-        spin_unlock(&line->count_lock);
+        mutex_unlock(&line->count_lock);
 }
 
 void close_lines(struct line *lines, int nlines)
@@ -486,34 +466,60 @@ void close_lines(struct line *lines, int nlines)
         int i;
 
         for(i = 0; i < nlines; i++)
-                close_chan(&lines[i].chan_list, 0);
+                close_chan(&lines[i]);
 }
 
-static int setup_one_line(struct line *lines, int n, char *init, int init_prio,
-                          char **error_out)
+int setup_one_line(struct line *lines, int n, char *init,
+                   const struct chan_opts *opts, char **error_out)
 {
         struct line *line = &lines[n];
+        struct tty_driver *driver = line->driver->driver;
         int err = -EINVAL;
 
-        spin_lock(&line->count_lock);
+        mutex_lock(&line->count_lock);
 
         if (line->count) {
                 *error_out = "Device is already open";
                 goto out;
         }
 
-        if (line->init_pri <= init_prio) {
-                line->init_pri = init_prio;
-                if (!strcmp(init, "none"))
+        if (!strcmp(init, "none")) {
+                if (line->valid) {
+                        line->valid = 0;
+                        kfree(line->init_str);
+                        tty_unregister_device(driver, n);
+                        parse_chan_pair(NULL, line, n, opts, error_out);
+                        err = 0;
+                }
+        } else {
+                char *new = kstrdup(init, GFP_KERNEL);
+                if (!new) {
+                        *error_out = "Failed to allocate memory";
+                        return -ENOMEM;
+                }
+                if (line->valid) {
+                        tty_unregister_device(driver, n);
+                        kfree(line->init_str);
+                }
+                line->init_str = new;
+                line->valid = 1;
+                err = parse_chan_pair(new, line, n, opts, error_out);
+                if (!err) {
+                        struct device *d = tty_register_device(driver, n, NULL);
+                        if (IS_ERR(d)) {
+                                *error_out = "Failed to register device";
+                                err = PTR_ERR(d);
+                                parse_chan_pair(NULL, line, n, opts, error_out);
+                        }
+                }
+                if (err) {
+                        line->init_str = NULL;
                         line->valid = 0;
-                else {
-                        line->init_str = init;
-                        line->valid = 1;
+                        kfree(new);
                 }
         }
-        err = 0;
 out:
-        spin_unlock(&line->count_lock);
+        mutex_unlock(&line->count_lock);
         return err;
 }
 
@@ -524,54 +530,43 @@ out:
  * @error_out is an error string in the case of failure;
  */
 
-int line_setup(struct line *lines, unsigned int num, char *init,
-               char **error_out)
+int line_setup(char **conf, unsigned int num, char **def,
+               char *init, char *name)
 {
-        int i, n, err;
-        char *end;
+        char *error;
 
         if (*init == '=') {
                 /*
                  * We said con=/ssl= instead of con#=, so we are configuring all
                  * consoles at once.
                  */
-                n = -1;
-        }
-        else {
-                n = simple_strtoul(init, &end, 0);
+                *def = init + 1;
+        } else {
+                char *end;
+                unsigned n = simple_strtoul(init, &end, 0);
+
                 if (*end != '=') {
-                        *error_out = "Couldn't parse device number";
-                        return -EINVAL;
+                        error = "Couldn't parse device number";
+                        goto out;
                 }
-                init = end;
-        }
-        init++;
-
-        if (n >= (signed int) num) {
-                *error_out = "Device number out of range";
-                return -EINVAL;
-        }
-        else if (n >= 0) {
-                err = setup_one_line(lines, n, init, INIT_ONE, error_out);
-                if (err)
-                        return err;
-        }
-        else {
-                for(i = 0; i < num; i++) {
-                        err = setup_one_line(lines, i, init, INIT_ALL,
-                                             error_out);
-                        if (err)
-                                return err;
+                if (n >= num) {
+                        error = "Device number out of range";
+                        goto out;
                 }
+                conf[n] = end + 1;
         }
-        return n == -1 ? num : n;
+        return 0;
+
+out:
+        printk(KERN_ERR "Failed to set up %s with "
+               "configuration string \"%s\" : %s\n", name, init, error);
+        return -EINVAL;
 }
 
 int line_config(struct line *lines, unsigned int num, char *str,
                 const struct chan_opts *opts, char **error_out)
 {
-        struct line *line;
-        char *new;
+        char *end;
         int n;
 
         if (*str == '=') {
@@ -579,17 +574,17 @@ int line_config(struct line *lines, unsigned int num, char *str,
                 return -EINVAL;
         }
 
-        new = kstrdup(str, GFP_KERNEL);
-        if (new == NULL) {
-                *error_out = "Failed to allocate memory";
-                return -ENOMEM;
+        n = simple_strtoul(str, &end, 0);
+        if (*end++ != '=') {
+                *error_out = "Couldn't parse device number";
+                return -EINVAL;
+        }
+        if (n >= num) {
+                *error_out = "Device number out of range";
+                return -EINVAL;
         }
-        n = line_setup(lines, num, new, error_out);
-        if (n < 0)
-                return n;
 
-        line = &lines[n];
-        return parse_chan_pair(line->init_str, line, n, opts, error_out);
+        return setup_one_line(lines, n, end, opts, error_out);
 }
 
 int line_get_config(char *name, struct line *lines, unsigned int num, char *str,
@@ -612,13 +607,13 @@ int line_get_config(char *name, struct line *lines, unsigned int num, char *str,
 
         line = &lines[dev];
 
-        spin_lock(&line->count_lock);
+        mutex_lock(&line->count_lock);
         if (!line->valid)
                 CONFIG_CHUNK(str, size, n, "none", 1);
         else if (line->tty == NULL)
                 CONFIG_CHUNK(str, size, n, line->init_str, 1);
-        else n = chan_config_string(&line->chan_list, str, size, error_out);
-        spin_unlock(&line->count_lock);
+        else n = chan_config_string(line, str, size, error_out);
+        mutex_unlock(&line->count_lock);
 
         return n;
 }
@@ -640,25 +635,23 @@ int line_id(char **str, int *start_out, int *end_out)
 
 int line_remove(struct line *lines, unsigned int num, int n, char **error_out)
 {
-        int err;
-        char config[sizeof("conxxxx=none\0")];
-
-        sprintf(config, "%d=none", n);
-        err = line_setup(lines, num, config, error_out);
-        if (err >= 0)
-                err = 0;
-        return err;
+        if (n >= num) {
+                *error_out = "Device number out of range";
+                return -EINVAL;
+        }
+        return setup_one_line(lines, n, "none", NULL, error_out);
 }
 
-struct tty_driver *register_lines(struct line_driver *line_driver,
-                                  const struct tty_operations *ops,
-                                  struct line *lines, int nlines)
+int register_lines(struct line_driver *line_driver,
+                   const struct tty_operations *ops,
+                   struct line *lines, int nlines)
 {
-        int i;
         struct tty_driver *driver = alloc_tty_driver(nlines);
+        int err;
+        int i;
 
         if (!driver)
-                return NULL;
+                return -ENOMEM;
 
         driver->driver_name = line_driver->name;
         driver->name = line_driver->device_name;
@@ -666,54 +659,33 @@ struct tty_driver *register_lines(struct line_driver *line_driver,
         driver->minor_start = line_driver->minor_start;
         driver->type = line_driver->type;
         driver->subtype = line_driver->subtype;
-        driver->flags = TTY_DRIVER_REAL_RAW;
+        driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
         driver->init_termios = tty_std_termios;
+        
+        for (i = 0; i < nlines; i++) {
+                spin_lock_init(&lines[i].lock);
+                mutex_init(&lines[i].count_lock);
+                lines[i].driver = line_driver;
+                INIT_LIST_HEAD(&lines[i].chan_list);
+        }
         tty_set_operations(driver, ops);
 
-        if (tty_register_driver(driver)) {
+        err = tty_register_driver(driver);
+        if (err) {
                 printk(KERN_ERR "register_lines : can't register %s driver\n",
                        line_driver->name);
                 put_tty_driver(driver);
-                return NULL;
-        }
-
-        for(i = 0; i < nlines; i++) {
-                if (!lines[i].valid)
-                        tty_unregister_device(driver, i);
+                return err;
         }
 
+        line_driver->driver = driver;
         mconsole_register_dev(&line_driver->mc);
-        return driver;
+        return 0;
 }
 
 static DEFINE_SPINLOCK(winch_handler_lock);
 static LIST_HEAD(winch_handlers);
 
-void lines_init(struct line *lines, int nlines, struct chan_opts *opts)
-{
-        struct line *line;
-        char *error;
-        int i;
-
-        for(i = 0; i < nlines; i++) {
-                line = &lines[i];
-                INIT_LIST_HEAD(&line->chan_list);
-
-                if (line->init_str == NULL)
-                        continue;
-
-                line->init_str = kstrdup(line->init_str, GFP_KERNEL);
-                if (line->init_str == NULL)
-                        printk(KERN_ERR "lines_init - kstrdup returned NULL\n");
-
-                if (parse_chan_pair(line->init_str, line, i, opts, &error)) {
-                        printk(KERN_ERR "parse_chan_pair failed for "
-                               "device %d : %s\n", i, error);
-                        line->valid = 0;
-                }
-        }
-}
-
 struct winch {
         struct list_head list;
         int fd;
@@ -777,7 +749,7 @@ static irqreturn_t winch_interrupt(int irq, void *data)
         if (tty != NULL) {
                 line = tty->driver_data;
                 if (line != NULL) {
-                        chan_window_size(&line->chan_list, &tty->winsize.ws_row,
+                        chan_window_size(line, &tty->winsize.ws_row,
                                          &tty->winsize.ws_col);
                         kill_pgrp(tty->pgrp, SIGWINCH, 1);
                 }
@@ -807,7 +779,7 @@ void register_winch_irq(int fd, int tty_fd, int pid, struct tty_struct *tty,
                                    .stack       = stack });
 
         if (um_request_irq(WINCH_IRQ, fd, IRQ_READ, winch_interrupt,
-                           IRQF_DISABLED | IRQF_SHARED | IRQF_SAMPLE_RANDOM,
+                           IRQF_SHARED | IRQF_SAMPLE_RANDOM,
                            "winch", winch) < 0) {
                 printk(KERN_ERR "register_winch_irq - failed to register "
                        "IRQ\n");
diff --git a/arch/um/drivers/line.h b/arch/um/drivers/line.h
index 63df3ca02ac..0a1834719db 100644
--- a/arch/um/drivers/line.h
+++ b/arch/um/drivers/line.h
@@ -15,7 +15,7 @@
 #include "chan_user.h"
 #include "mconsole_kern.h"
 
-/* There's only one modifiable field in this - .mc.list */
+/* There's only two modifiable fields in this - .mc.list and .driver */
 struct line_driver {
         const char *name;
         const char *device_name;
@@ -28,17 +28,18 @@ struct line_driver {
         const int write_irq;
         const char *write_irq_name;
         struct mc_device mc;
+        struct tty_driver *driver;
 };
 
 struct line {
         struct tty_struct *tty;
-        spinlock_t count_lock;
+        struct mutex count_lock;
         unsigned long count;
         int valid;
 
         char *init_str;
-        int init_pri;
         struct list_head chan_list;
+        struct chan *chan_in, *chan_out;
 
         /*This lock is actually, mostly, local to*/
         spinlock_t lock;
@@ -55,21 +56,12 @@ struct line {
         int sigio;
         struct delayed_work task;
         const struct line_driver *driver;
-        int have_irq;
 };
 
-#define LINE_INIT(str, d) \
-        { .count_lock = __SPIN_LOCK_UNLOCKED((str).count_lock), \
-          .init_str =   str,    \
-          .init_pri =   INIT_STATIC, \
-          .valid =      1, \
-          .lock =       __SPIN_LOCK_UNLOCKED((str).lock), \
-          .driver =     d }
-
 extern void line_close(struct tty_struct *tty, struct file * filp);
 extern int line_open(struct line *lines, struct tty_struct *tty);
-extern int line_setup(struct line *lines, unsigned int sizeof_lines,
-                      char *init, char **error_out);
+extern int line_setup(char **conf, unsigned nlines, char **def,
+                      char *init, char *name);
 extern int line_write(struct tty_struct *tty, const unsigned char *buf,
                       int len);
 extern int line_put_char(struct tty_struct *tty, unsigned char ch);
@@ -87,10 +79,11 @@ extern char *add_xterm_umid(char *base);
 extern int line_setup_irq(int fd, int input, int output, struct line *line,
                           void *data);
 extern void line_close_chan(struct line *line);
-extern struct tty_driver *register_lines(struct line_driver *line_driver,
-                                         const struct tty_operations *driver,
-                                         struct line *lines, int nlines);
-extern void lines_init(struct line *lines, int nlines, struct chan_opts *opts);
+extern int register_lines(struct line_driver *line_driver,
+                          const struct tty_operations *driver,
+                          struct line *lines, int nlines);
+extern int setup_one_line(struct line *lines, int n, char *init,
+                          const struct chan_opts *opts, char **error_out);
 extern void close_lines(struct line *lines, int nlines);
 
 extern int line_config(struct line *lines, unsigned int sizeof_lines,
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index c70e047eed7..e672bd6d43e 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -773,7 +773,7 @@ static int __init mconsole_init(void)
         register_reboot_notifier(&reboot_notifier);
 
         err = um_request_irq(MCONSOLE_IRQ, sock, IRQ_READ, mconsole_interrupt,
-                             IRQF_DISABLED | IRQF_SHARED | IRQF_SAMPLE_RANDOM,
+                             IRQF_SHARED | IRQF_SAMPLE_RANDOM,
                              "mconsole", (void *)sock);
         if (err) {
                 printk(KERN_ERR "Failed to get IRQ for management console\n");
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index d2996183e58..95f4416e6d9 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -161,7 +161,7 @@ static int uml_net_open(struct net_device *dev)
         }
 
         err = um_request_irq(dev->irq, lp->fd, IRQ_READ, uml_net_interrupt,
-                             IRQF_DISABLED | IRQF_SHARED, dev->name, dev);
+                             IRQF_SHARED, dev->name, dev);
         if (err != 0) {
                 printk(KERN_ERR "uml_net_open: failed to get irq(%d)\n", err);
                 err = -ENETUNREACH;
diff --git a/arch/um/drivers/port_kern.c b/arch/um/drivers/port_kern.c
index a11573be096..e31680e662a 100644
--- a/arch/um/drivers/port_kern.c
+++ b/arch/um/drivers/port_kern.c
@@ -100,7 +100,7 @@ static int port_accept(struct port_list *port)
                   .port         = port });
 
         if (um_request_irq(TELNETD_IRQ, socket[0], IRQ_READ, pipe_interrupt,
-                          IRQF_DISABLED | IRQF_SHARED | IRQF_SAMPLE_RANDOM,
+                          IRQF_SHARED | IRQF_SAMPLE_RANDOM,
                           "telnetd", conn)) {
                 printk(KERN_ERR "port_accept : failed to get IRQ for "
                        "telnetd\n");
@@ -184,7 +184,7 @@ void *port_data(int port_num)
         }
 
         if (um_request_irq(ACCEPT_IRQ, fd, IRQ_READ, port_interrupt,
-                          IRQF_DISABLED | IRQF_SHARED | IRQF_SAMPLE_RANDOM,
+                          IRQF_SHARED | IRQF_SAMPLE_RANDOM,
                           "port", port)) {
                 printk(KERN_ERR "Failed to get IRQ for port %d\n", port_num);
                 goto out_close;
diff --git a/arch/um/drivers/random.c b/arch/um/drivers/random.c
index 981085a93f3..b25296e6218 100644
--- a/arch/um/drivers/random.c
+++ b/arch/um/drivers/random.c
@@ -131,7 +131,7 @@ static int __init rng_init (void)
         random_fd = err;
 
         err = um_request_irq(RANDOM_IRQ, random_fd, IRQ_READ, random_interrupt,
-                             IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "random",
+                             IRQF_SAMPLE_RANDOM, "random",
                              NULL);
         if (err)
                 goto err_out_cleanup_hw;
diff --git a/arch/um/drivers/ssl.c b/arch/um/drivers/ssl.c
index 9d8c20af6f8..e09801a1327 100644
--- a/arch/um/drivers/ssl.c
+++ b/arch/um/drivers/ssl.c
@@ -20,12 +20,6 @@
 
 static const int ssl_version = 1;
 
-/* Referenced only by tty_driver below - presumably it's locked correctly
- * by the tty driver.
- */
-
-static struct tty_driver *ssl_driver;
-
 #define NR_PORTS 64
 
 static void ssl_announce(char *dev_name, int dev)
@@ -71,8 +65,9 @@ static struct line_driver driver = {
 /* The array is initialized by line_init, at initcall time.  The
  * elements are locked individually as needed.
  */
-static struct line serial_lines[NR_PORTS] =
-        { [0 ... NR_PORTS - 1] = LINE_INIT(CONFIG_SSL_CHAN, &driver) };
+static char *conf[NR_PORTS];
+static char *def_conf = CONFIG_SSL_CHAN;
+static struct line serial_lines[NR_PORTS];
 
 static int ssl_config(char *str, char **error_out)
 {
@@ -156,14 +151,14 @@ static void ssl_console_write(struct console *c, const char *string,
         unsigned long flags;
 
         spin_lock_irqsave(&line->lock, flags);
-        console_write_chan(&line->chan_list, string, len);
+        console_write_chan(line->chan_out, string, len);
         spin_unlock_irqrestore(&line->lock, flags);
 }
 
 static struct tty_driver *ssl_console_device(struct console *c, int *index)
 {
         *index = c->index;
-        return ssl_driver;
+        return driver.driver;
 }
 
 static int ssl_console_setup(struct console *co, char *options)
@@ -186,17 +181,30 @@ static struct console ssl_cons = {
 static int ssl_init(void)
 {
         char *new_title;
+        int err;
+        int i;
 
         printk(KERN_INFO "Initializing software serial port version %d\n",
                ssl_version);
-        ssl_driver = register_lines(&driver, &ssl_ops, serial_lines,
+
+        err = register_lines(&driver, &ssl_ops, serial_lines,
                                     ARRAY_SIZE(serial_lines));
+        if (err)
+                return err;
 
         new_title = add_xterm_umid(opts.xterm_title);
         if (new_title != NULL)
                 opts.xterm_title = new_title;
 
-        lines_init(serial_lines, ARRAY_SIZE(serial_lines), &opts);
+        for (i = 0; i < NR_PORTS; i++) {
+                char *error;
+                char *s = conf[i];
+                if (!s)
+                        s = def_conf;
+                if (setup_one_line(serial_lines, i, s, &opts, &error))
+                        printk(KERN_ERR "setup_one_line failed for "
+                               "device %d : %s\n", i, error);
+        }
 
         ssl_init_done = 1;
         register_console(&ssl_cons);
@@ -214,14 +222,7 @@ __uml_exitcall(ssl_exit);
 
 static int ssl_chan_setup(char *str)
 {
-        char *error;
-        int ret;
-
-        ret = line_setup(serial_lines, ARRAY_SIZE(serial_lines), str, &error);
-        if(ret < 0)
-                printk(KERN_ERR "Failed to set up serial line with "
-                       "configuration string \"%s\" : %s\n", str, error);
-
+        line_setup(conf, NR_PORTS, &def_conf, str, "serial line");
         return 1;
 }
 
diff --git a/arch/um/drivers/stdio_console.c b/arch/um/drivers/stdio_console.c
index 088776f0190..7663541c372 100644
--- a/arch/um/drivers/stdio_console.c
+++ b/arch/um/drivers/stdio_console.c
@@ -27,12 +27,6 @@
 
 #define MAX_TTYS (16)
 
-/* Referenced only by tty_driver below - presumably it's locked correctly
- * by the tty driver.
- */
-
-static struct tty_driver *console_driver;
-
 static void stdio_announce(char *dev_name, int dev)
 {
         printk(KERN_INFO "Virtual console %d assigned device '%s'\n", dev,
@@ -76,9 +70,9 @@ static struct line_driver driver = {
 /* The array is initialized by line_init, at initcall time.  The
  * elements are locked individually as needed.
  */
-static struct line vts[MAX_TTYS] = { LINE_INIT(CONFIG_CON_ZERO_CHAN, &driver),
-                                     [ 1 ... MAX_TTYS - 1 ] =
-                                     LINE_INIT(CONFIG_CON_CHAN, &driver) };
+static char *vt_conf[MAX_TTYS];
+static char *def_conf;
+static struct line vts[MAX_TTYS];
 
 static int con_config(char *str, char **error_out)
 {
@@ -130,14 +124,14 @@ static void uml_console_write(struct console *console, const char *string,
         unsigned long flags;
 
         spin_lock_irqsave(&line->lock, flags);
-        console_write_chan(&line->chan_list, string, len);
+        console_write_chan(line->chan_out, string, len);
         spin_unlock_irqrestore(&line->lock, flags);
 }
 
 static struct tty_driver *uml_console_device(struct console *c, int *index)
 {
         *index = c->index;
-        return console_driver;
+        return driver.driver;
 }
 
 static int uml_console_setup(struct console *co, char *options)
@@ -160,18 +154,31 @@ static struct console stdiocons = {
 static int stdio_init(void)
 {
         char *new_title;
+        int err;
+        int i;
 
-        console_driver = register_lines(&driver, &console_ops, vts,
+        err = register_lines(&driver, &console_ops, vts,
                                         ARRAY_SIZE(vts));
-        if (console_driver == NULL)
-                return -1;
+        if (err)
+                return err;
+
         printk(KERN_INFO "Initialized stdio console driver\n");
 
         new_title = add_xterm_umid(opts.xterm_title);
         if(new_title != NULL)
                 opts.xterm_title = new_title;
 
-        lines_init(vts, ARRAY_SIZE(vts), &opts);
+        for (i = 0; i < MAX_TTYS; i++) {
+                char *error;
+                char *s = vt_conf[i];
+                if (!s)
+                        s = def_conf;
+                if (!s)
+                        s = i ? CONFIG_CON_CHAN : CONFIG_CON_ZERO_CHAN;
+                if (setup_one_line(vts, i, s, &opts, &error))
+                        printk(KERN_ERR "setup_one_line failed for "
+                               "device %d : %s\n", i, error);
+        }
 
         con_init_done = 1;
         register_console(&stdiocons);
@@ -189,14 +196,7 @@ __uml_exitcall(console_exit);
 
 static int console_chan_setup(char *str)
 {
-        char *error;
-        int ret;
-
-        ret = line_setup(vts, ARRAY_SIZE(vts), str, &error);
-        if(ret < 0)
-                printk(KERN_ERR "Failed to set up console with "
-                       "configuration string \"%s\" : %s\n", str, error);
-
+        line_setup(vt_conf, MAX_TTYS, &def_conf, str, "console");
         return 1;
 }
 __setup("con", console_chan_setup);
diff --git a/arch/um/drivers/ubd_user.h b/arch/um/drivers/ubd.h
index 3845051f1b1..3845051f1b1 100644
--- a/arch/um/drivers/ubd_user.h
+++ b/arch/um/drivers/ubd.h
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index 944453a3ec9..20505cafa29 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -19,40 +19,26 @@
 
 #define UBD_SHIFT 4
 
-#include "linux/kernel.h"
-#include "linux/module.h"
-#include "linux/blkdev.h"
-#include "linux/ata.h"
-#include "linux/hdreg.h"
-#include "linux/init.h"
-#include "linux/cdrom.h"
-#include "linux/proc_fs.h"
-#include "linux/seq_file.h"
-#include "linux/ctype.h"
-#include "linux/capability.h"
-#include "linux/mm.h"
-#include "linux/slab.h"
-#include "linux/vmalloc.h"
-#include "linux/mutex.h"
-#include "linux/blkpg.h"
-#include "linux/genhd.h"
-#include "linux/spinlock.h"
-#include "linux/platform_device.h"
-#include "linux/scatterlist.h"
-#include "asm/segment.h"
-#include "asm/uaccess.h"
-#include "asm/irq.h"
-#include "asm/types.h"
-#include "asm/tlbflush.h"
-#include "mem_user.h"
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/ata.h>
+#include <linux/hdreg.h>
+#include <linux/cdrom.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/ctype.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/scatterlist.h>
+#include <asm/tlbflush.h>
 #include "kern_util.h"
 #include "mconsole_kern.h"
 #include "init.h"
-#include "irq_user.h"
 #include "irq_kern.h"
-#include "ubd_user.h"
+#include "ubd.h"
 #include "os.h"
-#include "mem.h"
 #include "cow.h"
 
 enum ubd_req { UBD_READ, UBD_WRITE };
@@ -1115,7 +1101,7 @@ static int __init ubd_driver_init(void){
                 return 0;
         }
         err = um_request_irq(UBD_IRQ, thread_fd, IRQ_READ, ubd_intr,
-                             IRQF_DISABLED, "ubd", ubd_devs);
+                             0, "ubd", ubd_devs);
         if(err != 0)
                 printk(KERN_ERR "um_request_irq failed - errno = %d\n", -err);
         return 0;
diff --git a/arch/um/drivers/ubd_user.c b/arch/um/drivers/ubd_user.c
index 007b94d9772..ffe02c431de 100644
--- a/arch/um/drivers/ubd_user.c
+++ b/arch/um/drivers/ubd_user.c
@@ -15,14 +15,12 @@
 #include <sys/socket.h>
 #include <sys/mman.h>
 #include <sys/param.h>
-#include "asm/types.h"
-#include "ubd_user.h"
-#include "os.h"
-#include "cow.h"
-
 #include <endian.h>
 #include <byteswap.h>
 
+#include "ubd.h"
+#include "os.h"
+
 void ignore_sigwinch_sig(void)
 {
         signal(SIGWINCH, SIG_IGN);
diff --git a/arch/um/drivers/xterm_kern.c b/arch/um/drivers/xterm_kern.c
index b646bccef37..8bd130f0bda 100644
--- a/arch/um/drivers/xterm_kern.c
+++ b/arch/um/drivers/xterm_kern.c
@@ -50,7 +50,7 @@ int xterm_fd(int socket, int *pid_out)
         init_completion(&data->ready);
 
         err = um_request_irq(XTERM_IRQ, socket, IRQ_READ, xterm_interrupt,
-                             IRQF_DISABLED | IRQF_SHARED | IRQF_SAMPLE_RANDOM,
+                             IRQF_SHARED | IRQF_SAMPLE_RANDOM,
                              "xterm", data);
         if (err) {
                 printk(KERN_ERR "xterm_fd : failed to get IRQ for xterm, "
diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild
index 451f4517b33..8419f5cf2ac 100644
--- a/arch/um/include/asm/Kbuild
+++ b/arch/um/include/asm/Kbuild
@@ -1,3 +1,3 @@
 generic-y += bug.h cputime.h device.h emergency-restart.h futex.h hardirq.h
 generic-y += hw_irq.h irq_regs.h kdebug.h percpu.h sections.h topology.h xor.h
-generic-y += ftrace.h
+generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h
diff --git a/arch/um/include/asm/asm-offsets.h b/arch/um/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a18..00000000000
--- a/arch/um/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/um/include/asm/auxvec.h b/arch/um/include/asm/auxvec.h
deleted file mode 100644
index 1e5e1c2fc9b..00000000000
--- a/arch/um/include/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __UM_AUXVEC_H
-#define __UM_AUXVEC_H
-
-#endif
diff --git a/arch/um/include/asm/current.h b/arch/um/include/asm/current.h
deleted file mode 100644
index c2191d9aa03..00000000000
--- a/arch/um/include/asm/current.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __UM_CURRENT_H
-#define __UM_CURRENT_H
-
-#include "linux/thread_info.h"
-
-#define current (current_thread_info()->task)
-
-#endif
diff --git a/arch/um/include/asm/delay.h b/arch/um/include/asm/delay.h
deleted file mode 100644
index 8a5576d8eda..00000000000
--- a/arch/um/include/asm/delay.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __UM_DELAY_H
-#define __UM_DELAY_H
-
-/* Undefined on purpose */
-extern void __bad_udelay(void);
-extern void __bad_ndelay(void);
-
-extern void __udelay(unsigned long usecs);
-extern void __ndelay(unsigned long usecs);
-extern void __delay(unsigned long loops);
-
-#define udelay(n) ((__builtin_constant_p(n) && (n) > 20000) ? \
-        __bad_udelay() : __udelay(n))
-
-#define ndelay(n) ((__builtin_constant_p(n) && (n) > 20000) ? \
-        __bad_ndelay() : __ndelay(n))
-
-#endif
diff --git a/arch/um/include/asm/io.h b/arch/um/include/asm/io.h
deleted file mode 100644
index 44e8b8c772a..00000000000
--- a/arch/um/include/asm/io.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef __UM_IO_H
-#define __UM_IO_H
-
-#include "asm/page.h"
-
-#define IO_SPACE_LIMIT 0xdeadbeef /* Sure hope nothing uses this */
-
-static inline int inb(unsigned long i) { return(0); }
-static inline void outb(char c, unsigned long i) { }
-
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are pretty trivial
- */
-static inline unsigned long virt_to_phys(volatile void * address)
-{
-        return __pa((void *) address);
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-        return __va(address);
-}
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-static inline void writeb(unsigned char b, volatile void __iomem *addr)
-{
-        *(volatile unsigned char __force *) addr = b;
-}
-static inline void writew(unsigned short b, volatile void __iomem *addr)
-{
-        *(volatile unsigned short __force *) addr = b;
-}
-static inline void writel(unsigned int b, volatile void __iomem *addr)
-{
-        *(volatile unsigned int __force *) addr = b;
-}
-static inline void writeq(unsigned int b, volatile void __iomem *addr)
-{
-        *(volatile unsigned long long __force *) addr = b;
-}
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define __raw_writeq writeq
-
-#endif
diff --git a/arch/um/include/asm/mutex.h b/arch/um/include/asm/mutex.h
deleted file mode 100644
index 458c1f7fbc1..00000000000
--- a/arch/um/include/asm/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/arch/um/include/asm/param.h b/arch/um/include/asm/param.h
deleted file mode 100644
index e44f4e60d16..00000000000
--- a/arch/um/include/asm/param.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _UM_PARAM_H
-#define _UM_PARAM_H
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#ifdef __KERNEL__
-#define HZ CONFIG_HZ
-#define USER_HZ 100        /* .. some user interfaces are in "ticks" */
-#define CLOCKS_PER_SEC (USER_HZ)  /* frequency at which times() counts */
-#else
-#define HZ 100
-#endif
-
-#endif
diff --git a/arch/um/include/asm/pci.h b/arch/um/include/asm/pci.h
deleted file mode 100644
index b44cf59ede1..00000000000
--- a/arch/um/include/asm/pci.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_PCI_H
-#define __UM_PCI_H
-
-#define PCI_DMA_BUS_IS_PHYS     (1)
-
-#endif
diff --git a/arch/um/include/asm/pgalloc.h b/arch/um/include/asm/pgalloc.h
index 32c8ce4e151..bf90b2aa200 100644
--- a/arch/um/include/asm/pgalloc.h
+++ b/arch/um/include/asm/pgalloc.h
@@ -8,8 +8,7 @@
 #ifndef __UM_PGALLOC_H
 #define __UM_PGALLOC_H
 
-#include "linux/mm.h"
-#include "asm/fixmap.h"
+#include <linux/mm.h>
 
 #define pmd_populate_kernel(mm, pmd, pte) \
         set_pmd(pmd, __pmd(_PAGE_TABLE + (unsigned long) __pa(pte)))
diff --git a/arch/um/include/asm/pgtable.h b/arch/um/include/asm/pgtable.h
index 41474fb5eee..6a3f9845743 100644
--- a/arch/um/include/asm/pgtable.h
+++ b/arch/um/include/asm/pgtable.h
@@ -69,6 +69,8 @@ extern unsigned long end_iomem;
 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
 #define PAGE_KERNEL_EXEC        __pgprot(__PAGE_KERNEL_EXEC)
 
+#define io_remap_pfn_range      remap_pfn_range
+
 /*
  * The i386 can't do page protection for execute, and considers that the same
  * are read.
diff --git a/arch/um/include/asm/ptrace-generic.h b/arch/um/include/asm/ptrace-generic.h
index f605d3c4844..e786a6a3ec5 100644
--- a/arch/um/include/asm/ptrace-generic.h
+++ b/arch/um/include/asm/ptrace-generic.h
@@ -9,7 +9,6 @@
 #ifndef __ASSEMBLY__
 
 #include <asm/ptrace-abi.h>
-#include <asm/user.h>
 #include "sysdep/ptrace.h"
 
 struct pt_regs {
diff --git a/arch/um/include/shared/common-offsets.h b/arch/um/include/shared/common-offsets.h
index d7fe563aa7e..40db8f71dea 100644
--- a/arch/um/include/shared/common-offsets.h
+++ b/arch/um/include/shared/common-offsets.h
@@ -2,8 +2,6 @@
 
 DEFINE(KERNEL_MADV_REMOVE, MADV_REMOVE);
 
-OFFSET(HOST_TASK_PID, task_struct, pid);
-
 DEFINE(UM_KERN_PAGE_SIZE, PAGE_SIZE);
 DEFINE(UM_KERN_PAGE_MASK, PAGE_MASK);
 DEFINE(UM_KERN_PAGE_SHIFT, PAGE_SHIFT);
diff --git a/arch/um/include/shared/kern_util.h b/arch/um/include/shared/kern_util.h
index 0f148385246..00965d06d2c 100644
--- a/arch/um/include/shared/kern_util.h
+++ b/arch/um/include/shared/kern_util.h
@@ -48,7 +48,7 @@ extern void do_uml_exitcalls(void);
  * GFP_ATOMIC.
  */
 extern int __cant_sleep(void);
-extern void *get_current(void);
+extern int get_current_pid(void);
 extern int copy_from_user_proc(void *to, void *from, int size);
 extern int cpu(void);
 extern char *uml_strdup(const char *string);
diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile
index bc494741b1f..492bc4c1b62 100644
--- a/arch/um/kernel/Makefile
+++ b/arch/um/kernel/Makefile
@@ -3,7 +3,7 @@
 # Licensed under the GPL
 #
 
-CPPFLAGS_vmlinux.lds := -U$(SUBARCH) -DSTART=$(LDS_START) \
+CPPFLAGS_vmlinux.lds := -DSTART=$(LDS_START) \
                         -DELF_ARCH=$(LDS_ELF_ARCH)        \
                         -DELF_FORMAT=$(LDS_ELF_FORMAT)
 extra-y := vmlinux.lds
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index 69f24905abd..f386d04a84a 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -126,9 +126,9 @@ void exit_thread(void)
 {
 }
 
-void *get_current(void)
+int get_current_pid(void)
 {
-        return current;
+        return task_pid_nr(current);
 }
 
 /*
diff --git a/arch/um/kernel/sigio.c b/arch/um/kernel/sigio.c
index 2b272b63b51..2a163925576 100644
--- a/arch/um/kernel/sigio.c
+++ b/arch/um/kernel/sigio.c
@@ -25,7 +25,7 @@ int write_sigio_irq(int fd)
         int err;
 
         err = um_request_irq(SIGIO_WRITE_IRQ, fd, IRQ_READ, sigio_interrupt,
-                             IRQF_DISABLED|IRQF_SAMPLE_RANDOM, "write sigio",
+                             IRQF_SAMPLE_RANDOM, "write sigio",
                              NULL);
         if (err) {
                 printk(KERN_ERR "write_sigio_irq : um_request_irq failed, "
diff --git a/arch/um/kernel/signal.c b/arch/um/kernel/signal.c
index e8b889d3bce..fb12f4c5e64 100644
--- a/arch/um/kernel/signal.c
+++ b/arch/um/kernel/signal.c
@@ -65,21 +65,10 @@ static int handle_signal(struct pt_regs *regs, unsigned long signr,
 #endif
                 err = setup_signal_stack_si(sp, signr, ka, regs, info, oldset);
 
-        if (err) {
-                spin_lock_irq(&current->sighand->siglock);
-                current->blocked = *oldset;
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
+        if (err)
                 force_sigsegv(signr, current);
-        } else {
-                spin_lock_irq(&current->sighand->siglock);
-                sigorsets(&current->blocked, &current->blocked,
-                          &ka->sa.sa_mask);
-                if (!(ka->sa.sa_flags & SA_NODEFER))
-                        sigaddset(&current->blocked, signr);
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
-        }
+        else
+                block_sigmask(ka, signr);
 
         return err;
 }
@@ -162,12 +151,11 @@ int do_signal(void)
  */
 long sys_sigsuspend(int history0, int history1, old_sigset_t mask)
 {
+        sigset_t blocked;
+
         mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        siginitset(&blocked, mask);
+        set_current_blocked(&blocked);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c
index 82a6e22f1f3..d1a23fb3190 100644
--- a/arch/um/kernel/time.c
+++ b/arch/um/kernel/time.c
@@ -82,7 +82,7 @@ static void __init setup_itimer(void)
 {
         int err;
 
-        err = request_irq(TIMER_IRQ, um_timer, IRQF_DISABLED, "timer", NULL);
+        err = request_irq(TIMER_IRQ, um_timer, 0, "timer", NULL);
         if (err != 0)
                 printk(KERN_ERR "register_timer : request_irq failed - "
                        "errno = %d\n", -err);
diff --git a/arch/um/os-Linux/Makefile b/arch/um/os-Linux/Makefile
index dd764101e48..08ff5094fcd 100644
--- a/arch/um/os-Linux/Makefile
+++ b/arch/um/os-Linux/Makefile
@@ -13,8 +13,6 @@ USER_OBJS := $(user-objs-y) aio.o elf_aux.o execvp.o file.o helper.o irq.o \
         main.o mem.o process.o registers.o sigio.o signal.o start_up.o time.o \
         tty.o umid.o util.o
 
-CFLAGS_user_syms.o += -DSUBARCH_$(SUBARCH)
-
 HAVE_AIO_ABI := $(shell [ -r /usr/include/linux/aio_abi.h ] && \
         echo -DHAVE_AIO_ABI )
 CFLAGS_aio.o += $(HAVE_AIO_ABI)
diff --git a/arch/um/os-Linux/user_syms.c b/arch/um/os-Linux/user_syms.c
index 45ffe46871e..73926fa3f96 100644
--- a/arch/um/os-Linux/user_syms.c
+++ b/arch/um/os-Linux/user_syms.c
@@ -45,7 +45,7 @@ EXPORT_SYMBOL(readdir64);
 extern void truncate64(void) __attribute__((weak));
 EXPORT_SYMBOL(truncate64);
 
-#ifdef SUBARCH_i386
+#ifdef CONFIG_ARCH_REUSE_HOST_VSYSCALL_AREA
 EXPORT_SYMBOL(vsyscall_ehdr);
 EXPORT_SYMBOL(vsyscall_end);
 #endif
diff --git a/arch/um/scripts/Makefile.rules b/arch/um/scripts/Makefile.rules
index 2eb2843b063..d50270d26b4 100644
--- a/arch/um/scripts/Makefile.rules
+++ b/arch/um/scripts/Makefile.rules
@@ -9,8 +9,6 @@ USER_OBJS := $(foreach file,$(USER_OBJS),$(obj)/$(file))
 
 $(USER_OBJS:.o=.%): \
         c_flags = -Wp,-MD,$(depfile) $(USER_CFLAGS) -include user.h $(CFLAGS_$(basetarget).o)
-$(USER_OBJS) : CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ \
-        -Dunix -D__unix__ -D__$(SUBARCH)__ $(CF)
 
 # These are like USER_OBJS but filter USER_CFLAGS through unprofile instead of
 # using it directly.
@@ -18,8 +16,9 @@ UNPROFILE_OBJS := $(foreach file,$(UNPROFILE_OBJS),$(obj)/$(file))
 
 $(UNPROFILE_OBJS:.o=.%): \
         c_flags = -Wp,-MD,$(depfile) $(call unprofile,$(USER_CFLAGS)) $(CFLAGS_$(basetarget).o)
-$(UNPROFILE_OBJS) : CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ \
-        -Dunix -D__unix__ -D__$(SUBARCH)__ $(CF)
+
+$(USER_OBJS) $(UNPROFILE_OBJS): \
+        CHECKFLAGS := $(patsubst $(NOSTDINC_FLAGS),,$(CHECKFLAGS))
 
 # The stubs can't try to call mcount or update basic block data
 define unprofile
diff --git a/arch/unicore32/include/asm/pci.h b/arch/unicore32/include/asm/pci.h
index dd3867727c3..f5e108f4a15 100644
--- a/arch/unicore32/include/asm/pci.h
+++ b/arch/unicore32/include/asm/pci.h
@@ -14,6 +14,7 @@
 
 #ifdef __KERNEL__
 #include <asm-generic/pci-dma-compat.h>
+#include <asm-generic/pci-bridge.h>
 #include <asm-generic/pci.h>
 #include <mach/hardware.h> /* for PCIBIOS_MIN_* */
 
diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c
index a8f07fe10ca..2fc2b1ba825 100644
--- a/arch/unicore32/kernel/pci.c
+++ b/arch/unicore32/kernel/pci.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 
 static int debug_pci;
-static int use_firmware;
 
 #define CONFIG_CMD(bus, devfn, where)   \
         (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
@@ -276,7 +275,7 @@ static int __init pci_common_init(void)
 
         pci_fixup_irqs(pci_common_swizzle, pci_puv3_map_irq);
 
-        if (!use_firmware) {
+        if (!pci_has_flag(PCI_PROBE_ONLY)) {
                 /*
                  * Size the bridge windows.
                  */
@@ -303,7 +302,7 @@ char * __devinit pcibios_setup(char *str)
                 debug_pci = 1;
                 return NULL;
         } else if (!strcmp(str, "firmware")) {
-                use_firmware = 1;
+                pci_add_flags(PCI_PROBE_ONLY);
                 return NULL;
         }
         return str;
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 1b3f152bb9c..b6f0458c314 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -380,7 +380,7 @@ int vectors_user_mapping(void)
         return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
                                        VM_READ | VM_EXEC |
                                        VM_MAYREAD | VM_MAYEXEC |
-                                       VM_ALWAYSDUMP | VM_RESERVED,
+                                       VM_RESERVED,
                                        NULL);
 }
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 90195235596..3ad653de710 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2125,6 +2125,13 @@ config NET5501
         ---help---
           This option enables system support for the Soekris Engineering net5501.
 
+config GEOS
+        bool "Traverse Technologies GEOS System Support (LEDS, GPIO, etc)"
+        select GPIOLIB
+        depends on DMI
+        ---help---
+          This option enables system support for the Traverse Technologies GEOS.
+
 endif # X86_32
 
 config AMD_NB
diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um
index 36ddec6a41c..4be406abeef 100644
--- a/arch/x86/Makefile.um
+++ b/arch/x86/Makefile.um
@@ -8,15 +8,11 @@ ELF_ARCH		:= i386
 ELF_FORMAT              := elf32-i386
 CHECKFLAGS      += -D__i386__
 
-ifeq ("$(origin SUBARCH)", "command line")
-ifneq ("$(shell uname -m | sed -e s/i.86/i386/)", "$(SUBARCH)")
 KBUILD_CFLAGS           += $(call cc-option,-m32)
 KBUILD_AFLAGS           += $(call cc-option,-m32)
 LINK-y                  += $(call cc-option,-m32)
 
 export LDFLAGS
-endif
-endif
 
 # First of all, tune CFLAGS for the specific CPU. This actually sets cflags-y.
 include $(srctree)/arch/x86/Makefile_32.cpu
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index 3e02148bb77..5a747dd884d 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -37,9 +37,9 @@ setup-y		+= video-bios.o
 targets         += $(setup-y)
 hostprogs-y     := mkcpustr tools/build
 
-HOSTCFLAGS_mkcpustr.o := -I$(srctree)/arch/$(SRCARCH)/include
-HOST_EXTRACFLAGS += -I$(objtree)/include -I$(srctree)/tools/include \
-                   -include $(srctree)/include/linux/kconfig.h
+HOST_EXTRACFLAGS += -I$(srctree)/tools/include $(LINUXINCLUDE) \
+                    -D__EXPORTED_HEADERS__
+
 $(obj)/cpu.o: $(obj)/cpustr.h
 
 quiet_cmd_cpustr = CPUSTR  $@
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index b903d5ea394..2d91580bf22 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -78,8 +78,75 @@
  */
 #ifdef __KERNEL__
 
+#include <linux/bug.h>
+
 DECLARE_PER_CPU(unsigned long, cpu_dr7);
 
+#ifndef CONFIG_PARAVIRT
+/*
+ * These special macros can be used to get or set a debugging register
+ */
+#define get_debugreg(var, register)                             \
+        (var) = native_get_debugreg(register)
+#define set_debugreg(value, register)                           \
+        native_set_debugreg(register, value)
+#endif
+
+static inline unsigned long native_get_debugreg(int regno)
+{
+        unsigned long val = 0;  /* Damn you, gcc! */
+
+        switch (regno) {
+        case 0:
+                asm("mov %%db0, %0" :"=r" (val));
+                break;
+        case 1:
+                asm("mov %%db1, %0" :"=r" (val));
+                break;
+        case 2:
+                asm("mov %%db2, %0" :"=r" (val));
+                break;
+        case 3:
+                asm("mov %%db3, %0" :"=r" (val));
+                break;
+        case 6:
+                asm("mov %%db6, %0" :"=r" (val));
+                break;
+        case 7:
+                asm("mov %%db7, %0" :"=r" (val));
+                break;
+        default:
+                BUG();
+        }
+        return val;
+}
+
+static inline void native_set_debugreg(int regno, unsigned long value)
+{
+        switch (regno) {
+        case 0:
+                asm("mov %0, %%db0"     ::"r" (value));
+                break;
+        case 1:
+                asm("mov %0, %%db1"     ::"r" (value));
+                break;
+        case 2:
+                asm("mov %0, %%db2"     ::"r" (value));
+                break;
+        case 3:
+                asm("mov %0, %%db3"     ::"r" (value));
+                break;
+        case 6:
+                asm("mov %0, %%db6"     ::"r" (value));
+                break;
+        case 7:
+                asm("mov %0, %%db7"     ::"r" (value));
+                break;
+        default:
+                BUG();
+        }
+}
+
 static inline void hw_breakpoint_disable(void)
 {
         /* Zero the control register for HW Breakpoint */
diff --git a/arch/x86/include/asm/kgdb.h b/arch/x86/include/asm/kgdb.h
index 77e95f54570..332f98c9111 100644
--- a/arch/x86/include/asm/kgdb.h
+++ b/arch/x86/include/asm/kgdb.h
@@ -64,11 +64,15 @@ enum regnames {
         GDB_PS,                 /* 17 */
         GDB_CS,                 /* 18 */
         GDB_SS,                 /* 19 */
+        GDB_DS,                 /* 20 */
+        GDB_ES,                 /* 21 */
+        GDB_FS,                 /* 22 */
+        GDB_GS,                 /* 23 */
 };
 #define GDB_ORIG_AX             57
-#define DBG_MAX_REG_NUM         20
-/* 17 64 bit regs and 3 32 bit regs */
-#define NUMREGBYTES             ((17 * 8) + (3 * 4))
+#define DBG_MAX_REG_NUM         24
+/* 17 64 bit regs and 5 32 bit regs */
+#define NUMREGBYTES             ((17 * 8) + (5 * 4))
 #endif /* ! CONFIG_X86_32 */
 
 static inline void arch_kgdb_breakpoint(void)
diff --git a/arch/x86/include/asm/kvm.h b/arch/x86/include/asm/kvm.h
index 4d8dcbdfc12..e7d1c194d27 100644
--- a/arch/x86/include/asm/kvm.h
+++ b/arch/x86/include/asm/kvm.h
@@ -321,4 +321,8 @@ struct kvm_xcrs {
         __u64 padding[16];
 };
 
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
 #endif /* _ASM_X86_KVM_H */
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index 7b9cfc4878a..c222e1a1b12 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -176,6 +176,7 @@ struct x86_emulate_ops {
         void (*set_idt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
         ulong (*get_cr)(struct x86_emulate_ctxt *ctxt, int cr);
         int (*set_cr)(struct x86_emulate_ctxt *ctxt, int cr, ulong val);
+        void (*set_rflags)(struct x86_emulate_ctxt *ctxt, ulong val);
         int (*cpl)(struct x86_emulate_ctxt *ctxt);
         int (*get_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong *dest);
         int (*set_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong value);
@@ -388,7 +389,7 @@ bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt);
 #define EMULATION_INTERCEPTED 2
 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt);
 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
-                         u16 tss_selector, int reason,
+                         u16 tss_selector, int idt_index, int reason,
                          bool has_error_code, u32 error_code);
 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq);
 #endif /* _ASM_X86_KVM_X86_EMULATE_H */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 52d6640a5ca..e216ba066e7 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -29,7 +29,7 @@
 #include <asm/msr-index.h>
 
 #define KVM_MAX_VCPUS 254
-#define KVM_SOFT_MAX_VCPUS 64
+#define KVM_SOFT_MAX_VCPUS 160
 #define KVM_MEMORY_SLOTS 32
 /* memory slots that does not exposed to userspace */
 #define KVM_PRIVATE_MEM_SLOTS 4
@@ -181,13 +181,6 @@ struct kvm_mmu_memory_cache {
         void *objects[KVM_NR_MEM_OBJS];
 };
 
-#define NR_PTE_CHAIN_ENTRIES 5
-
-struct kvm_pte_chain {
-        u64 *parent_ptes[NR_PTE_CHAIN_ENTRIES];
-        struct hlist_node link;
-};
-
 /*
  * kvm_mmu_page_role, below, is defined as:
  *
@@ -427,12 +420,16 @@ struct kvm_vcpu_arch {
 
         u64 last_guest_tsc;
         u64 last_kernel_ns;
-        u64 last_tsc_nsec;
-        u64 last_tsc_write;
-        u32 virtual_tsc_khz;
+        u64 last_host_tsc;
+        u64 tsc_offset_adjustment;
+        u64 this_tsc_nsec;
+        u64 this_tsc_write;
+        u8  this_tsc_generation;
         bool tsc_catchup;
-        u32  tsc_catchup_mult;
-        s8   tsc_catchup_shift;
+        bool tsc_always_catchup;
+        s8 virtual_tsc_shift;
+        u32 virtual_tsc_mult;
+        u32 virtual_tsc_khz;
 
         atomic_t nmi_queued;  /* unprocessed asynchronous NMIs */
         unsigned nmi_pending; /* NMI queued after currently running handler */
@@ -478,6 +475,21 @@ struct kvm_vcpu_arch {
                 u32 id;
                 bool send_user_only;
         } apf;
+
+        /* OSVW MSRs (AMD only) */
+        struct {
+                u64 length;
+                u64 status;
+        } osvw;
+};
+
+struct kvm_lpage_info {
+        unsigned long rmap_pde;
+        int write_count;
+};
+
+struct kvm_arch_memory_slot {
+        struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
 };
 
 struct kvm_arch {
@@ -511,8 +523,12 @@ struct kvm_arch {
         s64 kvmclock_offset;
         raw_spinlock_t tsc_write_lock;
         u64 last_tsc_nsec;
-        u64 last_tsc_offset;
         u64 last_tsc_write;
+        u32 last_tsc_khz;
+        u64 cur_tsc_nsec;
+        u64 cur_tsc_write;
+        u64 cur_tsc_offset;
+        u8  cur_tsc_generation;
 
         struct kvm_xen_hvm_config xen_hvm_config;
 
@@ -644,7 +660,7 @@ struct kvm_x86_ops {
         u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
         int (*get_lpage_level)(void);
         bool (*rdtscp_supported)(void);
-        void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment);
+        void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host);
 
         void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
 
@@ -652,7 +668,7 @@ struct kvm_x86_ops {
 
         bool (*has_wbinvd_exit)(void);
 
-        void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz);
+        void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale);
         void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
 
         u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc);
@@ -674,6 +690,17 @@ struct kvm_arch_async_pf {
 
 extern struct kvm_x86_ops *kvm_x86_ops;
 
+static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
+                                           s64 adjustment)
+{
+        kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false);
+}
+
+static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
+{
+        kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true);
+}
+
 int kvm_mmu_module_init(void);
 void kvm_mmu_module_exit(void);
 
@@ -741,8 +768,8 @@ int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
 
-int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
-                    bool has_error_code, u32 error_code);
+int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
+                    int reason, bool has_error_code, u32 error_code);
 
 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index c0180fd372d..aa0f9130836 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -10,6 +10,7 @@
 #include <asm/paravirt_types.h>
 
 #ifndef __ASSEMBLY__
+#include <linux/bug.h>
 #include <linux/types.h>
 #include <linux/cpumask.h>
 
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index e8fb2c7a5f4..2291895b183 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -23,6 +23,7 @@
 #define ARCH_PERFMON_EVENTSEL_USR                       (1ULL << 16)
 #define ARCH_PERFMON_EVENTSEL_OS                        (1ULL << 17)
 #define ARCH_PERFMON_EVENTSEL_EDGE                      (1ULL << 18)
+#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL               (1ULL << 19)
 #define ARCH_PERFMON_EVENTSEL_INT                       (1ULL << 20)
 #define ARCH_PERFMON_EVENTSEL_ANY                       (1ULL << 21)
 #define ARCH_PERFMON_EVENTSEL_ENABLE                    (1ULL << 22)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 78e30ea492b..a19542c1685 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -484,61 +484,6 @@ struct thread_struct {
         unsigned                io_bitmap_max;
 };
 
-static inline unsigned long native_get_debugreg(int regno)
-{
-        unsigned long val = 0;  /* Damn you, gcc! */
-
-        switch (regno) {
-        case 0:
-                asm("mov %%db0, %0" :"=r" (val));
-                break;
-        case 1:
-                asm("mov %%db1, %0" :"=r" (val));
-                break;
-        case 2:
-                asm("mov %%db2, %0" :"=r" (val));
-                break;
-        case 3:
-                asm("mov %%db3, %0" :"=r" (val));
-                break;
-        case 6:
-                asm("mov %%db6, %0" :"=r" (val));
-                break;
-        case 7:
-                asm("mov %%db7, %0" :"=r" (val));
-                break;
-        default:
-                BUG();
-        }
-        return val;
-}
-
-static inline void native_set_debugreg(int regno, unsigned long value)
-{
-        switch (regno) {
-        case 0:
-                asm("mov %0, %%db0"     ::"r" (value));
-                break;
-        case 1:
-                asm("mov %0, %%db1"     ::"r" (value));
-                break;
-        case 2:
-                asm("mov %0, %%db2"     ::"r" (value));
-                break;
-        case 3:
-                asm("mov %0, %%db3"     ::"r" (value));
-                break;
-        case 6:
-                asm("mov %0, %%db6"     ::"r" (value));
-                break;
-        case 7:
-                asm("mov %0, %%db7"     ::"r" (value));
-                break;
-        default:
-                BUG();
-        }
-}
-
 /*
  * Set IOPL bits in EFLAGS from given mask
  */
@@ -584,14 +529,6 @@ static inline void native_swapgs(void)
 #define __cpuid                 native_cpuid
 #define paravirt_enabled()      0
 
-/*
- * These special macros can be used to get or set a debugging register
- */
-#define get_debugreg(var, register)                             \
-        (var) = native_get_debugreg(register)
-#define set_debugreg(value, register)                           \
-        native_set_debugreg(register, value)
-
 static inline void load_sp0(struct tss_struct *tss,
                             struct thread_struct *thread)
 {
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 15d99153a96..c91e8b9d588 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -61,7 +61,7 @@ extern void check_tsc_sync_source(int cpu);
 extern void check_tsc_sync_target(void);
 
 extern int notsc_setup(char *);
-extern void save_sched_clock_state(void);
-extern void restore_sched_clock_state(void);
+extern void tsc_save_sched_clock_state(void);
+extern void tsc_restore_sched_clock_state(void);
 
 #endif /* _ASM_X86_TSC_H */
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 517d4767ffd..baaca8defec 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -145,9 +145,11 @@ struct x86_init_ops {
 /**
  * struct x86_cpuinit_ops - platform specific cpu hotplug setups
  * @setup_percpu_clockev:       set up the per cpu clock event device
+ * @early_percpu_clock_init:    early init of the per cpu clock event device
  */
 struct x86_cpuinit_ops {
         void (*setup_percpu_clockev)(void);
+        void (*early_percpu_clock_init)(void);
         void (*fixup_cpu_id)(struct cpuinfo_x86 *c, int node);
 };
 
@@ -160,6 +162,8 @@ struct x86_cpuinit_ops {
  * @is_untracked_pat_range      exclude from PAT logic
  * @nmi_init                    enable NMI on cpus
  * @i8042_detect                pre-detect if i8042 controller exists
+ * @save_sched_clock_state:     save state for sched_clock() on suspend
+ * @restore_sched_clock_state:  restore state for sched_clock() on resume
  */
 struct x86_platform_ops {
         unsigned long (*calibrate_tsc)(void);
@@ -171,6 +175,8 @@ struct x86_platform_ops {
         void (*nmi_init)(void);
         unsigned char (*get_nmi_reason)(void);
         int (*i8042_detect)(void);
+        void (*save_sched_clock_state)(void);
+        void (*restore_sched_clock_state)(void);
 };
 
 struct pci_dev;
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index ade9c794ed9..e49477444ff 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -18,6 +18,7 @@
 #include <asm/archrandom.h>
 #include <asm/hypervisor.h>
 #include <asm/processor.h>
+#include <asm/debugreg.h>
 #include <asm/sections.h>
 #include <linux/topology.h>
 #include <linux/cpumask.h>
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 0a18d16cb58..fa2900c0e39 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -643,14 +643,14 @@ static bool __perf_sched_find_counter(struct perf_sched *sched)
         /* Prefer fixed purpose counters */
         if (x86_pmu.num_counters_fixed) {
                 idx = X86_PMC_IDX_FIXED;
-                for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_MAX) {
+                for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
                         if (!__test_and_set_bit(idx, sched->state.used))
                                 goto done;
                 }
         }
         /* Grab the first unused counter starting with idx */
         idx = sched->state.counter;
-        for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
+        for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
                 if (!__test_and_set_bit(idx, sched->state.used))
                         goto done;
         }
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index 79d97e68f04..7b784f4ef1e 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -98,12 +98,6 @@
 #endif
 .endm
 
-#ifdef CONFIG_VM86
-#define resume_userspace_sig    check_userspace
-#else
-#define resume_userspace_sig    resume_userspace
-#endif
-
 /*
  * User gs save/restore
  *
@@ -327,10 +321,19 @@ ret_from_exception:
         preempt_stop(CLBR_ANY)
 ret_from_intr:
         GET_THREAD_INFO(%ebp)
-check_userspace:
+resume_userspace_sig:
+#ifdef CONFIG_VM86
         movl PT_EFLAGS(%esp), %eax      # mix EFLAGS and CS
         movb PT_CS(%esp), %al
         andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
+#else
+        /*
+         * We can be coming here from a syscall done in the kernel space,
+         * e.g. a failed kernel_execve().
+         */
+        movl PT_CS(%esp), %eax
+        andl $SEGMENT_RPL_MASK, %eax
+#endif
         cmpl $USER_RPL, %eax
         jb resume_kernel                # not returning to v8086 or userspace
 
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 99b85b423bb..6d5fc8cfd5d 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -305,10 +305,10 @@ void __init native_init_IRQ(void)
          * us. (some of these will be overridden and become
          * 'special' SMP interrupts)
          */
-        for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
+        i = FIRST_EXTERNAL_VECTOR;
+        for_each_clear_bit_from(i, used_vectors, NR_VECTORS) {
                 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */
-                if (!test_bit(i, used_vectors))
-                        set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
+                set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
         }
 
         if (!acpi_ioapic && !of_ioapic)
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 4425a12ece4..db6720edfdd 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -66,8 +66,6 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
         { "ss", 4, offsetof(struct pt_regs, ss) },
         { "ds", 4, offsetof(struct pt_regs, ds) },
         { "es", 4, offsetof(struct pt_regs, es) },
-        { "fs", 4, -1 },
-        { "gs", 4, -1 },
 #else
         { "ax", 8, offsetof(struct pt_regs, ax) },
         { "bx", 8, offsetof(struct pt_regs, bx) },
@@ -89,7 +87,11 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
         { "flags", 4, offsetof(struct pt_regs, flags) },
         { "cs", 4, offsetof(struct pt_regs, cs) },
         { "ss", 4, offsetof(struct pt_regs, ss) },
+        { "ds", 4, -1 },
+        { "es", 4, -1 },
 #endif
+        { "fs", 4, -1 },
+        { "gs", 4, -1 },
 };
 
 int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c
index 44842d756b2..f8492da65bf 100644
--- a/arch/x86/kernel/kvmclock.c
+++ b/arch/x86/kernel/kvmclock.c
@@ -136,6 +136,15 @@ int kvm_register_clock(char *txt)
         return ret;
 }
 
+static void kvm_save_sched_clock_state(void)
+{
+}
+
+static void kvm_restore_sched_clock_state(void)
+{
+        kvm_register_clock("primary cpu clock, resume");
+}
+
 #ifdef CONFIG_X86_LOCAL_APIC
 static void __cpuinit kvm_setup_secondary_clock(void)
 {
@@ -144,8 +153,6 @@ static void __cpuinit kvm_setup_secondary_clock(void)
          * we shouldn't fail.
          */
         WARN_ON(kvm_register_clock("secondary cpu clock"));
-        /* ok, done with our trickery, call native */
-        setup_secondary_APIC_clock();
 }
 #endif
 
@@ -194,9 +201,11 @@ void __init kvmclock_init(void)
         x86_platform.get_wallclock = kvm_get_wallclock;
         x86_platform.set_wallclock = kvm_set_wallclock;
 #ifdef CONFIG_X86_LOCAL_APIC
-        x86_cpuinit.setup_percpu_clockev =
+        x86_cpuinit.early_percpu_clock_init =
                 kvm_setup_secondary_clock;
 #endif
+        x86_platform.save_sched_clock_state = kvm_save_sched_clock_state;
+        x86_platform.restore_sched_clock_state = kvm_restore_sched_clock_state;
         machine_ops.shutdown  = kvm_shutdown;
 #ifdef CONFIG_KEXEC
         machine_ops.crash_shutdown  = kvm_crash_shutdown;
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 2b26485f0c1..ab137605e69 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -26,6 +26,7 @@
 
 #include <asm/bug.h>
 #include <asm/paravirt.h>
+#include <asm/debugreg.h>
 #include <asm/desc.h>
 #include <asm/setup.h>
 #include <asm/pgtable.h>
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 1c4d769e21e..28e5e06fcba 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -262,10 +262,11 @@ rootfs_initcall(pci_iommu_init);
 
 static __devinit void via_no_dac(struct pci_dev *dev)
 {
-        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
+        if (forbid_dac == 0) {
                 dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
                 forbid_dac = 1;
         }
 }
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
+                                PCI_CLASS_BRIDGE_PCI, 8, via_no_dac);
 #endif
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index e578a79a309..5104a2b685c 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -255,6 +255,7 @@ notrace static void __cpuinit start_secondary(void *unused)
          * most necessary things.
          */
         cpu_init();
+        x86_cpuinit.early_percpu_clock_init();
         preempt_disable();
         smp_callin();
 
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 183c5925a9f..899a03f2d18 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -630,7 +630,7 @@ static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
 
 static unsigned long long cyc2ns_suspend;
 
-void save_sched_clock_state(void)
+void tsc_save_sched_clock_state(void)
 {
         if (!sched_clock_stable)
                 return;
@@ -646,7 +646,7 @@ void save_sched_clock_state(void)
  * that sched_clock() continues from the point where it was left off during
  * suspend.
  */
-void restore_sched_clock_state(void)
+void tsc_restore_sched_clock_state(void)
 {
         unsigned long long offset;
         unsigned long flags;
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 947a06ccc67..e9f265fd79a 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -91,6 +91,7 @@ struct x86_init_ops x86_init __initdata = {
 };
 
 struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
+        .early_percpu_clock_init        = x86_init_noop,
         .setup_percpu_clockev           = setup_secondary_APIC_clock,
         .fixup_cpu_id                   = x86_default_fixup_cpu_id,
 };
@@ -107,7 +108,9 @@ struct x86_platform_ops x86_platform = {
         .is_untracked_pat_range         = is_ISA_range,
         .nmi_init                       = default_nmi_init,
         .get_nmi_reason                 = default_get_nmi_reason,
-        .i8042_detect                   = default_i8042_detect
+        .i8042_detect                   = default_i8042_detect,
+        .save_sched_clock_state         = tsc_save_sched_clock_state,
+        .restore_sched_clock_state      = tsc_restore_sched_clock_state,
 };
 
 EXPORT_SYMBOL_GPL(x86_platform);
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 89b02bfaaca..9fed5bedaad 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -236,7 +236,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
         const u32 kvm_supported_word6_x86_features =
                 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
                 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
-                F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
+                F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
                 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
 
         /* cpuid 0xC0000001.edx */
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index 5b97e1797a6..26d1fb437eb 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -43,4 +43,12 @@ static inline bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
         return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
 }
 
+static inline bool guest_cpuid_has_osvw(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
+        return best && (best->ecx & bit(X86_FEATURE_OSVW));
+}
+
 #endif
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 0982507b962..83756223f8a 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -57,6 +57,7 @@
 #define OpDS              23ull  /* DS */
 #define OpFS              24ull  /* FS */
 #define OpGS              25ull  /* GS */
+#define OpMem8            26ull  /* 8-bit zero extended memory operand */
 
 #define OpBits             5  /* Width of operand field */
 #define OpMask             ((1ull << OpBits) - 1)
@@ -101,6 +102,7 @@
 #define SrcAcc      (OpAcc << SrcShift)
 #define SrcImmU16   (OpImmU16 << SrcShift)
 #define SrcDX       (OpDX << SrcShift)
+#define SrcMem8     (OpMem8 << SrcShift)
 #define SrcMask     (OpMask << SrcShift)
 #define BitOp       (1<<11)
 #define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
@@ -858,8 +860,7 @@ static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
 }
 
 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
-                                    struct operand *op,
-                                    int inhibit_bytereg)
+                                    struct operand *op)
 {
         unsigned reg = ctxt->modrm_reg;
         int highbyte_regs = ctxt->rex_prefix == 0;
@@ -876,7 +877,7 @@ static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
         }
 
         op->type = OP_REG;
-        if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
+        if (ctxt->d & ByteOp) {
                 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
                 op->bytes = 1;
         } else {
@@ -1151,6 +1152,22 @@ static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
         return 1;
 }
 
+static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
+                                     u16 index, struct desc_struct *desc)
+{
+        struct desc_ptr dt;
+        ulong addr;
+
+        ctxt->ops->get_idt(ctxt, &dt);
+
+        if (dt.size < index * 8 + 7)
+                return emulate_gp(ctxt, index << 3 | 0x2);
+
+        addr = dt.address + index * 8;
+        return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
+                                   &ctxt->exception);
+}
+
 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
                                      u16 selector, struct desc_ptr *dt)
 {
@@ -1227,6 +1244,8 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
                 seg_desc.type = 3;
                 seg_desc.p = 1;
                 seg_desc.s = 1;
+                if (ctxt->mode == X86EMUL_MODE_VM86)
+                        seg_desc.dpl = 3;
                 goto load;
         }
 
@@ -1891,6 +1910,17 @@ setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
         ss->p = 1;
 }
 
+static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
+{
+        u32 eax, ebx, ecx, edx;
+
+        eax = ecx = 0;
+        return ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)
+                && ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
+                && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
+                && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
+}
+
 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
 {
         struct x86_emulate_ops *ops = ctxt->ops;
@@ -2007,6 +2037,14 @@ static int em_sysenter(struct x86_emulate_ctxt *ctxt)
         if (ctxt->mode == X86EMUL_MODE_REAL)
                 return emulate_gp(ctxt, 0);
 
+        /*
+         * Not recognized on AMD in compat mode (but is recognized in legacy
+         * mode).
+         */
+        if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
+            && !vendor_intel(ctxt))
+                return emulate_ud(ctxt);
+
         /* XXX sysenter/sysexit have not been tested in 64bit mode.
         * Therefore, we inject an #UD.
         */
@@ -2306,6 +2344,8 @@ static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
                 return emulate_gp(ctxt, 0);
         ctxt->_eip = tss->eip;
         ctxt->eflags = tss->eflags | 2;
+
+        /* General purpose registers */
         ctxt->regs[VCPU_REGS_RAX] = tss->eax;
         ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
         ctxt->regs[VCPU_REGS_RDX] = tss->edx;
@@ -2328,6 +2368,24 @@ static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
         set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
 
         /*
+         * If we're switching between Protected Mode and VM86, we need to make
+         * sure to update the mode before loading the segment descriptors so
+         * that the selectors are interpreted correctly.
+         *
+         * Need to get rflags to the vcpu struct immediately because it
+         * influences the CPL which is checked at least when loading the segment
+         * descriptors and when pushing an error code to the new kernel stack.
+         *
+         * TODO Introduce a separate ctxt->ops->set_cpl callback
+         */
+        if (ctxt->eflags & X86_EFLAGS_VM)
+                ctxt->mode = X86EMUL_MODE_VM86;
+        else
+                ctxt->mode = X86EMUL_MODE_PROT32;
+
+        ctxt->ops->set_rflags(ctxt, ctxt->eflags);
+
+        /*
          * Now load segment descriptors. If fault happenes at this stage
          * it is handled in a context of new task
          */
@@ -2401,7 +2459,7 @@ static int task_switch_32(struct x86_emulate_ctxt *ctxt,
 }
 
 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
-                                   u16 tss_selector, int reason,
+                                   u16 tss_selector, int idt_index, int reason,
                                    bool has_error_code, u32 error_code)
 {
         struct x86_emulate_ops *ops = ctxt->ops;
@@ -2423,12 +2481,35 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
 
         /* FIXME: check that next_tss_desc is tss */
 
-        if (reason != TASK_SWITCH_IRET) {
-                if ((tss_selector & 3) > next_tss_desc.dpl ||
-                    ops->cpl(ctxt) > next_tss_desc.dpl)
-                        return emulate_gp(ctxt, 0);
+        /*
+         * Check privileges. The three cases are task switch caused by...
+         *
+         * 1. jmp/call/int to task gate: Check against DPL of the task gate
+         * 2. Exception/IRQ/iret: No check is performed
+         * 3. jmp/call to TSS: Check agains DPL of the TSS
+         */
+        if (reason == TASK_SWITCH_GATE) {
+                if (idt_index != -1) {
+                        /* Software interrupts */
+                        struct desc_struct task_gate_desc;
+                        int dpl;
+
+                        ret = read_interrupt_descriptor(ctxt, idt_index,
+                                                        &task_gate_desc);
+                        if (ret != X86EMUL_CONTINUE)
+                                return ret;
+
+                        dpl = task_gate_desc.dpl;
+                        if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
+                                return emulate_gp(ctxt, (idt_index << 3) | 0x2);
+                }
+        } else if (reason != TASK_SWITCH_IRET) {
+                int dpl = next_tss_desc.dpl;
+                if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
+                        return emulate_gp(ctxt, tss_selector);
         }
 
+
         desc_limit = desc_limit_scaled(&next_tss_desc);
         if (!next_tss_desc.p ||
             ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
@@ -2481,7 +2562,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
 }
 
 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
-                         u16 tss_selector, int reason,
+                         u16 tss_selector, int idt_index, int reason,
                          bool has_error_code, u32 error_code)
 {
         int rc;
@@ -2489,7 +2570,7 @@ int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
         ctxt->_eip = ctxt->eip;
         ctxt->dst.type = OP_NONE;
 
-        rc = emulator_do_task_switch(ctxt, tss_selector, reason,
+        rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
                                      has_error_code, error_code);
 
         if (rc == X86EMUL_CONTINUE)
@@ -3514,13 +3595,13 @@ static struct opcode twobyte_table[256] = {
         I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
         I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
         I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
-        D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
+        D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
         /* 0xB8 - 0xBF */
         N, N,
         G(BitOp, group8),
         I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
         I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
-        D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
+        D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
         /* 0xC0 - 0xCF */
         D2bv(DstMem | SrcReg | ModRM | Lock),
         N, D(DstMem | SrcReg | ModRM | Mov),
@@ -3602,9 +3683,7 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
 
         switch (d) {
         case OpReg:
-                decode_register_operand(ctxt, op,
-                         op == &ctxt->dst &&
-                         ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
+                decode_register_operand(ctxt, op);
                 break;
         case OpImmUByte:
                 rc = decode_imm(ctxt, op, 1, false);
@@ -3656,6 +3735,9 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
         case OpImm:
                 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
                 break;
+        case OpMem8:
+                ctxt->memop.bytes = 1;
+                goto mem_common;
         case OpMem16:
                 ctxt->memop.bytes = 2;
                 goto mem_common;
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index b6a73537e1e..81cf4fa4a2b 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
                 if (val & 0x10) {
                         s->init4 = val & 1;
                         s->last_irr = 0;
+                        s->irr &= s->elcr;
                         s->imr = 0;
                         s->priority_add = 0;
                         s->special_mask = 0;
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 31bfc6927bc..858432287ab 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -433,7 +433,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                 break;
 
         case APIC_DM_INIT:
-                if (level) {
+                if (!trig_mode || level) {
                         result = 1;
                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
                         kvm_make_request(KVM_REQ_EVENT, vcpu);
@@ -731,7 +731,7 @@ static void start_apic_timer(struct kvm_lapic *apic)
                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
                 u64 ns = 0;
                 struct kvm_vcpu *vcpu = apic->vcpu;
-                unsigned long this_tsc_khz = vcpu_tsc_khz(vcpu);
+                unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
                 unsigned long flags;
 
                 if (unlikely(!tscdeadline || !this_tsc_khz))
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 224b02c3cda..4cb16426884 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -688,9 +688,8 @@ static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
 {
         unsigned long idx;
 
-        idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
-              (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
-        return &slot->lpage_info[level - 2][idx];
+        idx = gfn_to_index(gfn, slot->base_gfn, level);
+        return &slot->arch.lpage_info[level - 2][idx];
 }
 
 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
@@ -946,7 +945,7 @@ static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
         }
 }
 
-static unsigned long *__gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level,
+static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
                                     struct kvm_memory_slot *slot)
 {
         struct kvm_lpage_info *linfo;
@@ -966,7 +965,7 @@ static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
         struct kvm_memory_slot *slot;
 
         slot = gfn_to_memslot(kvm, gfn);
-        return __gfn_to_rmap(kvm, gfn, level, slot);
+        return __gfn_to_rmap(gfn, level, slot);
 }
 
 static bool rmap_can_add(struct kvm_vcpu *vcpu)
@@ -988,7 +987,7 @@ static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
         return pte_list_add(vcpu, spte, rmapp);
 }
 
-static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
+static u64 *rmap_next(unsigned long *rmapp, u64 *spte)
 {
         return pte_list_next(rmapp, spte);
 }
@@ -1018,8 +1017,8 @@ int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
         u64 *spte;
         int i, write_protected = 0;
 
-        rmapp = __gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL, slot);
-        spte = rmap_next(kvm, rmapp, NULL);
+        rmapp = __gfn_to_rmap(gfn, PT_PAGE_TABLE_LEVEL, slot);
+        spte = rmap_next(rmapp, NULL);
         while (spte) {
                 BUG_ON(!(*spte & PT_PRESENT_MASK));
                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
@@ -1027,14 +1026,14 @@ int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
                         mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
                         write_protected = 1;
                 }
-                spte = rmap_next(kvm, rmapp, spte);
+                spte = rmap_next(rmapp, spte);
         }
 
         /* check for huge page mappings */
         for (i = PT_DIRECTORY_LEVEL;
              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
-                rmapp = __gfn_to_rmap(kvm, gfn, i, slot);
-                spte = rmap_next(kvm, rmapp, NULL);
+                rmapp = __gfn_to_rmap(gfn, i, slot);
+                spte = rmap_next(rmapp, NULL);
                 while (spte) {
                         BUG_ON(!(*spte & PT_PRESENT_MASK));
                         BUG_ON(!is_large_pte(*spte));
@@ -1045,7 +1044,7 @@ int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
                                 spte = NULL;
                                 write_protected = 1;
                         }
-                        spte = rmap_next(kvm, rmapp, spte);
+                        spte = rmap_next(rmapp, spte);
                 }
         }
 
@@ -1066,7 +1065,7 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
         u64 *spte;
         int need_tlb_flush = 0;
 
-        while ((spte = rmap_next(kvm, rmapp, NULL))) {
+        while ((spte = rmap_next(rmapp, NULL))) {
                 BUG_ON(!(*spte & PT_PRESENT_MASK));
                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
                 drop_spte(kvm, spte);
@@ -1085,14 +1084,14 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
 
         WARN_ON(pte_huge(*ptep));
         new_pfn = pte_pfn(*ptep);
-        spte = rmap_next(kvm, rmapp, NULL);
+        spte = rmap_next(rmapp, NULL);
         while (spte) {
                 BUG_ON(!is_shadow_present_pte(*spte));
                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
                 need_flush = 1;
                 if (pte_write(*ptep)) {
                         drop_spte(kvm, spte);
-                        spte = rmap_next(kvm, rmapp, NULL);
+                        spte = rmap_next(rmapp, NULL);
                 } else {
                         new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
@@ -1102,7 +1101,7 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
                         new_spte &= ~shadow_accessed_mask;
                         mmu_spte_clear_track_bits(spte);
                         mmu_spte_set(spte, new_spte);
-                        spte = rmap_next(kvm, rmapp, spte);
+                        spte = rmap_next(rmapp, spte);
                 }
         }
         if (need_flush)
@@ -1176,7 +1175,7 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
         if (!shadow_accessed_mask)
                 return kvm_unmap_rmapp(kvm, rmapp, data);
 
-        spte = rmap_next(kvm, rmapp, NULL);
+        spte = rmap_next(rmapp, NULL);
         while (spte) {
                 int _young;
                 u64 _spte = *spte;
@@ -1186,7 +1185,7 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
                         young = 1;
                         clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
                 }
-                spte = rmap_next(kvm, rmapp, spte);
+                spte = rmap_next(rmapp, spte);
         }
         return young;
 }
@@ -1205,7 +1204,7 @@ static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
         if (!shadow_accessed_mask)
                 goto out;
 
-        spte = rmap_next(kvm, rmapp, NULL);
+        spte = rmap_next(rmapp, NULL);
         while (spte) {
                 u64 _spte = *spte;
                 BUG_ON(!(_spte & PT_PRESENT_MASK));
@@ -1214,7 +1213,7 @@ static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
                         young = 1;
                         break;
                 }
-                spte = rmap_next(kvm, rmapp, spte);
+                spte = rmap_next(rmapp, spte);
         }
 out:
         return young;
@@ -1391,11 +1390,6 @@ struct kvm_mmu_pages {
         unsigned int nr;
 };
 
-#define for_each_unsync_children(bitmap, idx)           \
-        for (idx = find_first_bit(bitmap, 512);         \
-             idx < 512;                                 \
-             idx = find_next_bit(bitmap, 512, idx+1))
-
 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
                          int idx)
 {
@@ -1417,7 +1411,7 @@ static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
 {
         int i, ret, nr_unsync_leaf = 0;
 
-        for_each_unsync_children(sp->unsync_child_bitmap, i) {
+        for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
                 struct kvm_mmu_page *child;
                 u64 ent = sp->spt[i];
 
@@ -1803,6 +1797,7 @@ static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
 {
         if (is_large_pte(*sptep)) {
                 drop_spte(vcpu->kvm, sptep);
+                --vcpu->kvm->stat.lpages;
                 kvm_flush_remote_tlbs(vcpu->kvm);
         }
 }
@@ -3190,15 +3185,14 @@ static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
 #undef PTTYPE
 
 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
-                                  struct kvm_mmu *context,
-                                  int level)
+                                  struct kvm_mmu *context)
 {
         int maxphyaddr = cpuid_maxphyaddr(vcpu);
         u64 exb_bit_rsvd = 0;
 
         if (!context->nx)
                 exb_bit_rsvd = rsvd_bits(63, 63);
-        switch (level) {
+        switch (context->root_level) {
         case PT32_ROOT_LEVEL:
                 /* no rsvd bits for 2 level 4K page table entries */
                 context->rsvd_bits_mask[0][1] = 0;
@@ -3256,8 +3250,9 @@ static int paging64_init_context_common(struct kvm_vcpu *vcpu,
                                         int level)
 {
         context->nx = is_nx(vcpu);
+        context->root_level = level;
 
-        reset_rsvds_bits_mask(vcpu, context, level);
+        reset_rsvds_bits_mask(vcpu, context);
 
         ASSERT(is_pae(vcpu));
         context->new_cr3 = paging_new_cr3;
@@ -3267,7 +3262,6 @@ static int paging64_init_context_common(struct kvm_vcpu *vcpu,
         context->invlpg = paging64_invlpg;
         context->update_pte = paging64_update_pte;
         context->free = paging_free;
-        context->root_level = level;
         context->shadow_root_level = level;
         context->root_hpa = INVALID_PAGE;
         context->direct_map = false;
@@ -3284,8 +3278,9 @@ static int paging32_init_context(struct kvm_vcpu *vcpu,
                                  struct kvm_mmu *context)
 {
         context->nx = false;
+        context->root_level = PT32_ROOT_LEVEL;
 
-        reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
+        reset_rsvds_bits_mask(vcpu, context);
 
         context->new_cr3 = paging_new_cr3;
         context->page_fault = paging32_page_fault;
@@ -3294,7 +3289,6 @@ static int paging32_init_context(struct kvm_vcpu *vcpu,
         context->sync_page = paging32_sync_page;
         context->invlpg = paging32_invlpg;
         context->update_pte = paging32_update_pte;
-        context->root_level = PT32_ROOT_LEVEL;
         context->shadow_root_level = PT32E_ROOT_LEVEL;
         context->root_hpa = INVALID_PAGE;
         context->direct_map = false;
@@ -3325,7 +3319,6 @@ static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
         context->get_cr3 = get_cr3;
         context->get_pdptr = kvm_pdptr_read;
         context->inject_page_fault = kvm_inject_page_fault;
-        context->nx = is_nx(vcpu);
 
         if (!is_paging(vcpu)) {
                 context->nx = false;
@@ -3333,19 +3326,19 @@ static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
                 context->root_level = 0;
         } else if (is_long_mode(vcpu)) {
                 context->nx = is_nx(vcpu);
-                reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
-                context->gva_to_gpa = paging64_gva_to_gpa;
                 context->root_level = PT64_ROOT_LEVEL;
+                reset_rsvds_bits_mask(vcpu, context);
+                context->gva_to_gpa = paging64_gva_to_gpa;
         } else if (is_pae(vcpu)) {
                 context->nx = is_nx(vcpu);
-                reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
-                context->gva_to_gpa = paging64_gva_to_gpa;
                 context->root_level = PT32E_ROOT_LEVEL;
+                reset_rsvds_bits_mask(vcpu, context);
+                context->gva_to_gpa = paging64_gva_to_gpa;
         } else {
                 context->nx = false;
-                reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
-                context->gva_to_gpa = paging32_gva_to_gpa;
                 context->root_level = PT32_ROOT_LEVEL;
+                reset_rsvds_bits_mask(vcpu, context);
+                context->gva_to_gpa = paging32_gva_to_gpa;
         }
 
         return 0;
@@ -3408,18 +3401,18 @@ static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
         } else if (is_long_mode(vcpu)) {
                 g_context->nx = is_nx(vcpu);
-                reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
                 g_context->root_level = PT64_ROOT_LEVEL;
+                reset_rsvds_bits_mask(vcpu, g_context);
                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
         } else if (is_pae(vcpu)) {
                 g_context->nx = is_nx(vcpu);
-                reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
                 g_context->root_level = PT32E_ROOT_LEVEL;
+                reset_rsvds_bits_mask(vcpu, g_context);
                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
         } else {
                 g_context->nx = false;
-                reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
                 g_context->root_level = PT32_ROOT_LEVEL;
+                reset_rsvds_bits_mask(vcpu, g_context);
                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
         }
 
@@ -3555,7 +3548,7 @@ static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
  * If we're seeing too many writes to a page, it may no longer be a page table,
  * or we may be forking, in which case it is better to unmap the page.
  */
-static bool detect_write_flooding(struct kvm_mmu_page *sp, u64 *spte)
+static bool detect_write_flooding(struct kvm_mmu_page *sp)
 {
         /*
          * Skip write-flooding detected for the sp whose level is 1, because
@@ -3664,10 +3657,8 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
 
         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
-                spte = get_written_sptes(sp, gpa, &npte);
-
                 if (detect_write_misaligned(sp, gpa, bytes) ||
-                      detect_write_flooding(sp, spte)) {
+                      detect_write_flooding(sp)) {
                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
                                                      &invalid_list);
                         ++vcpu->kvm->stat.mmu_flooded;
diff --git a/arch/x86/kvm/mmu_audit.c b/arch/x86/kvm/mmu_audit.c
index ea7b4fd3467..715da5a19a5 100644
--- a/arch/x86/kvm/mmu_audit.c
+++ b/arch/x86/kvm/mmu_audit.c
@@ -200,13 +200,13 @@ static void audit_write_protection(struct kvm *kvm, struct kvm_mmu_page *sp)
         slot = gfn_to_memslot(kvm, sp->gfn);
         rmapp = &slot->rmap[sp->gfn - slot->base_gfn];
 
-        spte = rmap_next(kvm, rmapp, NULL);
+        spte = rmap_next(rmapp, NULL);
         while (spte) {
                 if (is_writable_pte(*spte))
                         audit_printk(kvm, "shadow page has writable "
                                      "mappings: gfn %llx role %x\n",
                                      sp->gfn, sp->role.word);
-                spte = rmap_next(kvm, rmapp, spte);
+                spte = rmap_next(rmapp, spte);
         }
 }
 
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 7aad5446f39..a73f0c10481 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -33,10 +33,11 @@ static struct kvm_arch_event_perf_mapping {
         [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
         [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
         [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
+        [7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
 };
 
 /* mapping between fixed pmc index and arch_events array */
-int fixed_pmc_events[] = {1, 0, 2};
+int fixed_pmc_events[] = {1, 0, 7};
 
 static bool pmc_is_gp(struct kvm_pmc *pmc)
 {
@@ -210,6 +211,9 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
         unsigned config, type = PERF_TYPE_RAW;
         u8 event_select, unit_mask;
 
+        if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
+                printk_once("kvm pmu: pin control bit is ignored\n");
+
         pmc->eventsel = eventsel;
 
         stop_counter(pmc);
@@ -220,7 +224,7 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
         event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
         unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
 
-        if (!(event_select & (ARCH_PERFMON_EVENTSEL_EDGE |
+        if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
                                 ARCH_PERFMON_EVENTSEL_INV |
                                 ARCH_PERFMON_EVENTSEL_CMASK))) {
                 config = find_arch_event(&pmc->vcpu->arch.pmu, event_select,
@@ -413,7 +417,7 @@ int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data)
         struct kvm_pmc *counters;
         u64 ctr;
 
-        pmc &= (3u << 30) - 1;
+        pmc &= ~(3u << 30);
         if (!fixed && pmc >= pmu->nr_arch_gp_counters)
                 return 1;
         if (fixed && pmc >= pmu->nr_arch_fixed_counters)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index e385214711c..e334389e1c7 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -111,6 +111,12 @@ struct nested_state {
 #define MSRPM_OFFSETS   16
 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 
+/*
+ * Set osvw_len to higher value when updated Revision Guides
+ * are published and we know what the new status bits are
+ */
+static uint64_t osvw_len = 4, osvw_status;
+
 struct vcpu_svm {
         struct kvm_vcpu vcpu;
         struct vmcb *vmcb;
@@ -177,11 +183,13 @@ static bool npt_enabled = true;
 #else
 static bool npt_enabled;
 #endif
-static int npt = 1;
 
+/* allow nested paging (virtualized MMU) for all guests */
+static int npt = true;
 module_param(npt, int, S_IRUGO);
 
-static int nested = 1;
+/* allow nested virtualization in KVM/SVM */
+static int nested = true;
 module_param(nested, int, S_IRUGO);
 
 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
@@ -557,6 +565,27 @@ static void svm_init_erratum_383(void)
         erratum_383_found = true;
 }
 
+static void svm_init_osvw(struct kvm_vcpu *vcpu)
+{
+        /*
+         * Guests should see errata 400 and 415 as fixed (assuming that
+         * HLT and IO instructions are intercepted).
+         */
+        vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
+        vcpu->arch.osvw.status = osvw_status & ~(6ULL);
+
+        /*
+         * By increasing VCPU's osvw.length to 3 we are telling the guest that
+         * all osvw.status bits inside that length, including bit 0 (which is
+         * reserved for erratum 298), are valid. However, if host processor's
+         * osvw_len is 0 then osvw_status[0] carries no information. We need to
+         * be conservative here and therefore we tell the guest that erratum 298
+         * is present (because we really don't know).
+         */
+        if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
+                vcpu->arch.osvw.status |= 1;
+}
+
 static int has_svm(void)
 {
         const char *msg;
@@ -623,6 +652,36 @@ static int svm_hardware_enable(void *garbage)
                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
         }
 
+
+        /*
+         * Get OSVW bits.
+         *
+         * Note that it is possible to have a system with mixed processor
+         * revisions and therefore different OSVW bits. If bits are not the same
+         * on different processors then choose the worst case (i.e. if erratum
+         * is present on one processor and not on another then assume that the
+         * erratum is present everywhere).
+         */
+        if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
+                uint64_t len, status = 0;
+                int err;
+
+                len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
+                if (!err)
+                        status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
+                                                      &err);
+
+                if (err)
+                        osvw_status = osvw_len = 0;
+                else {
+                        if (len < osvw_len)
+                                osvw_len = len;
+                        osvw_status |= status;
+                        osvw_status &= (1ULL << osvw_len) - 1;
+                }
+        } else
+                osvw_status = osvw_len = 0;
+
         svm_init_erratum_383();
 
         amd_pmu_enable_virt();
@@ -910,20 +969,25 @@ static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
         return _tsc;
 }
 
-static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
+static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
         u64 ratio;
         u64 khz;
 
-        /* TSC scaling supported? */
-        if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
+        /* Guest TSC same frequency as host TSC? */
+        if (!scale) {
+                svm->tsc_ratio = TSC_RATIO_DEFAULT;
                 return;
+        }
 
-        /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
-        if (user_tsc_khz == 0) {
-                vcpu->arch.virtual_tsc_khz = 0;
-                svm->tsc_ratio = TSC_RATIO_DEFAULT;
+        /* TSC scaling supported? */
+        if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
+                if (user_tsc_khz > tsc_khz) {
+                        vcpu->arch.tsc_catchup = 1;
+                        vcpu->arch.tsc_always_catchup = 1;
+                } else
+                        WARN(1, "user requested TSC rate below hardware speed\n");
                 return;
         }
 
@@ -938,7 +1002,6 @@ static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
                                 user_tsc_khz);
                 return;
         }
-        vcpu->arch.virtual_tsc_khz = user_tsc_khz;
         svm->tsc_ratio             = ratio;
 }
 
@@ -958,10 +1021,14 @@ static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 }
 
-static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
+static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
 
+        WARN_ON(adjustment < 0);
+        if (host)
+                adjustment = svm_scale_tsc(vcpu, adjustment);
+
         svm->vmcb->control.tsc_offset += adjustment;
         if (is_guest_mode(vcpu))
                 svm->nested.hsave->control.tsc_offset += adjustment;
@@ -1191,6 +1258,8 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
         if (kvm_vcpu_is_bsp(&svm->vcpu))
                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 
+        svm_init_osvw(&svm->vcpu);
+
         return &svm->vcpu;
 
 free_page4:
@@ -1268,6 +1337,21 @@ static void svm_vcpu_put(struct kvm_vcpu *vcpu)
                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 }
 
+static void svm_update_cpl(struct kvm_vcpu *vcpu)
+{
+        struct vcpu_svm *svm = to_svm(vcpu);
+        int cpl;
+
+        if (!is_protmode(vcpu))
+                cpl = 0;
+        else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
+                cpl = 3;
+        else
+                cpl = svm->vmcb->save.cs.selector & 0x3;
+
+        svm->vmcb->save.cpl = cpl;
+}
+
 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 {
         return to_svm(vcpu)->vmcb->save.rflags;
@@ -1275,7 +1359,11 @@ static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 
 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 {
+        unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
+
         to_svm(vcpu)->vmcb->save.rflags = rflags;
+        if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
+                svm_update_cpl(vcpu);
 }
 
 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
@@ -1543,9 +1631,7 @@ static void svm_set_segment(struct kvm_vcpu *vcpu,
                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
         }
         if (seg == VCPU_SREG_CS)
-                svm->vmcb->save.cpl
-                        = (svm->vmcb->save.cs.attrib
-                           >> SVM_SELECTOR_DPL_SHIFT) & 3;
+                svm_update_cpl(vcpu);
 
         mark_dirty(svm->vmcb, VMCB_SEG);
 }
@@ -2735,7 +2821,10 @@ static int task_switch_interception(struct vcpu_svm *svm)
              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
                 skip_emulated_instruction(&svm->vcpu);
 
-        if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
+        if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
+                int_vec = -1;
+
+        if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
                                 has_error_code, error_code) == EMULATE_FAIL) {
                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 246490f643b..280751c8472 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -70,9 +70,6 @@ module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 static bool __read_mostly vmm_exclusive = 1;
 module_param(vmm_exclusive, bool, S_IRUGO);
 
-static bool __read_mostly yield_on_hlt = 1;
-module_param(yield_on_hlt, bool, S_IRUGO);
-
 static bool __read_mostly fasteoi = 1;
 module_param(fasteoi, bool, S_IRUGO);
 
@@ -1655,17 +1652,6 @@ static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
         vmx_set_interrupt_shadow(vcpu, 0);
 }
 
-static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
-{
-        /* Ensure that we clear the HLT state in the VMCS.  We don't need to
-         * explicitly skip the instruction because if the HLT state is set, then
-         * the instruction is already executing and RIP has already been
-         * advanced. */
-        if (!yield_on_hlt &&
-            vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
-                vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
-}
-
 /*
  * KVM wants to inject page-faults which it got to the guest. This function
  * checks whether in a nested guest, we need to inject them to L1 or L2.
@@ -1678,7 +1664,7 @@ static int nested_pf_handled(struct kvm_vcpu *vcpu)
         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 
         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
-        if (!(vmcs12->exception_bitmap & PF_VECTOR))
+        if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
                 return 0;
 
         nested_vmx_vmexit(vcpu);
@@ -1718,7 +1704,6 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 
         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
-        vmx_clear_hlt(vcpu);
 }
 
 static bool vmx_rdtscp_supported(void)
@@ -1817,13 +1802,19 @@ u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
 }
 
 /*
- * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
- * ioctl. In this case the call-back should update internal vmx state to make
- * the changes effective.
+ * Engage any workarounds for mis-matched TSC rates.  Currently limited to
+ * software catchup for faster rates on slower CPUs.
  */
-static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
+static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 {
-        /* Nothing to do here */
+        if (!scale)
+                return;
+
+        if (user_tsc_khz > tsc_khz) {
+                vcpu->arch.tsc_catchup = 1;
+                vcpu->arch.tsc_always_catchup = 1;
+        } else
+                WARN(1, "user requested TSC rate below hardware speed\n");
 }
 
 /*
@@ -1850,7 +1841,7 @@ static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
         }
 }
 
-static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
+static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
 {
         u64 offset = vmcs_read64(TSC_OFFSET);
         vmcs_write64(TSC_OFFSET, offset + adjustment);
@@ -2219,6 +2210,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
                 msr = find_msr_entry(vmx, msr_index);
                 if (msr) {
                         msr->data = data;
+                        if (msr - vmx->guest_msrs < vmx->save_nmsrs)
+                                kvm_set_shared_msr(msr->index, msr->data,
+                                                   msr->mask);
                         break;
                 }
                 ret = kvm_set_msr_common(vcpu, msr_index, data);
@@ -2399,7 +2393,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
                                 &_pin_based_exec_control) < 0)
                 return -EIO;
 
-        min =
+        min = CPU_BASED_HLT_EXITING |
 #ifdef CONFIG_X86_64
               CPU_BASED_CR8_LOAD_EXITING |
               CPU_BASED_CR8_STORE_EXITING |
@@ -2414,9 +2408,6 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
               CPU_BASED_INVLPG_EXITING |
               CPU_BASED_RDPMC_EXITING;
 
-        if (yield_on_hlt)
-                min |= CPU_BASED_HLT_EXITING;
-
         opt = CPU_BASED_TPR_SHADOW |
               CPU_BASED_USE_MSR_BITMAPS |
               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
@@ -4003,7 +3994,6 @@ static void vmx_inject_irq(struct kvm_vcpu *vcpu)
         } else
                 intr |= INTR_TYPE_EXT_INTR;
         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
-        vmx_clear_hlt(vcpu);
 }
 
 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
@@ -4035,7 +4025,6 @@ static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
         }
         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
-        vmx_clear_hlt(vcpu);
 }
 
 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
@@ -4672,9 +4661,10 @@ static int handle_task_switch(struct kvm_vcpu *vcpu)
         bool has_error_code = false;
         u32 error_code = 0;
         u16 tss_selector;
-        int reason, type, idt_v;
+        int reason, type, idt_v, idt_index;
 
         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
+        idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
 
         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
@@ -4712,8 +4702,9 @@ static int handle_task_switch(struct kvm_vcpu *vcpu)
                        type != INTR_TYPE_NMI_INTR))
                 skip_emulated_instruction(vcpu);
 
-        if (kvm_task_switch(vcpu, tss_selector, reason,
-                                has_error_code, error_code) == EMULATE_FAIL) {
+        if (kvm_task_switch(vcpu, tss_selector,
+                            type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
+                            has_error_code, error_code) == EMULATE_FAIL) {
                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
                 vcpu->run->internal.ndata = 0;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 54696b5f844..4044ce0bf7c 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -97,6 +97,10 @@ EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 u32  kvm_max_guest_tsc_khz;
 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 
+/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
+static u32 tsc_tolerance_ppm = 250;
+module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
+
 #define KVM_NR_SHARED_MSRS 16
 
 struct kvm_shared_msrs_global {
@@ -969,50 +973,51 @@ static inline u64 get_kernel_ns(void)
 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
 unsigned long max_tsc_khz;
 
-static inline int kvm_tsc_changes_freq(void)
+static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
 {
-        int cpu = get_cpu();
-        int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
-                  cpufreq_quick_get(cpu) != 0;
-        put_cpu();
-        return ret;
+        return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
+                                   vcpu->arch.virtual_tsc_shift);
 }
 
-u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
+static u32 adjust_tsc_khz(u32 khz, s32 ppm)
 {
-        if (vcpu->arch.virtual_tsc_khz)
-                return vcpu->arch.virtual_tsc_khz;
-        else
-                return __this_cpu_read(cpu_tsc_khz);
+        u64 v = (u64)khz * (1000000 + ppm);
+        do_div(v, 1000000);
+        return v;
 }
 
-static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
+static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
 {
-        u64 ret;
-
-        WARN_ON(preemptible());
-        if (kvm_tsc_changes_freq())
-                printk_once(KERN_WARNING
-                 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
-        ret = nsec * vcpu_tsc_khz(vcpu);
-        do_div(ret, USEC_PER_SEC);
-        return ret;
-}
+        u32 thresh_lo, thresh_hi;
+        int use_scaling = 0;
 
-static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
-{
         /* Compute a scale to convert nanoseconds in TSC cycles */
         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
-                           &vcpu->arch.tsc_catchup_shift,
-                           &vcpu->arch.tsc_catchup_mult);
+                           &vcpu->arch.virtual_tsc_shift,
+                           &vcpu->arch.virtual_tsc_mult);
+        vcpu->arch.virtual_tsc_khz = this_tsc_khz;
+
+        /*
+         * Compute the variation in TSC rate which is acceptable
+         * within the range of tolerance and decide if the
+         * rate being applied is within that bounds of the hardware
+         * rate.  If so, no scaling or compensation need be done.
+         */
+        thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
+        thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
+        if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
+                pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
+                use_scaling = 1;
+        }
+        kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
 }
 
 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
 {
-        u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
-                                      vcpu->arch.tsc_catchup_mult,
-                                      vcpu->arch.tsc_catchup_shift);
-        tsc += vcpu->arch.last_tsc_write;
+        u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
+                                      vcpu->arch.virtual_tsc_mult,
+                                      vcpu->arch.virtual_tsc_shift);
+        tsc += vcpu->arch.this_tsc_write;
         return tsc;
 }
 
@@ -1021,48 +1026,88 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
         struct kvm *kvm = vcpu->kvm;
         u64 offset, ns, elapsed;
         unsigned long flags;
-        s64 sdiff;
+        s64 usdiff;
 
         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
         ns = get_kernel_ns();
         elapsed = ns - kvm->arch.last_tsc_nsec;
-        sdiff = data - kvm->arch.last_tsc_write;
-        if (sdiff < 0)
-                sdiff = -sdiff;
+
+        /* n.b - signed multiplication and division required */
+        usdiff = data - kvm->arch.last_tsc_write;
+#ifdef CONFIG_X86_64
+        usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
+#else
+        /* do_div() only does unsigned */
+        asm("idivl %2; xor %%edx, %%edx"
+            : "=A"(usdiff)
+            : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
+#endif
+        do_div(elapsed, 1000);
+        usdiff -= elapsed;
+        if (usdiff < 0)
+                usdiff = -usdiff;
 
         /*
-         * Special case: close write to TSC within 5 seconds of
-         * another CPU is interpreted as an attempt to synchronize
-         * The 5 seconds is to accommodate host load / swapping as
-         * well as any reset of TSC during the boot process.
-         *
-         * In that case, for a reliable TSC, we can match TSC offsets,
-         * or make a best guest using elapsed value.
-         */
-        if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
-            elapsed < 5ULL * NSEC_PER_SEC) {
+         * Special case: TSC write with a small delta (1 second) of virtual
+         * cycle time against real time is interpreted as an attempt to
+         * synchronize the CPU.
+         *
+         * For a reliable TSC, we can match TSC offsets, and for an unstable
+         * TSC, we add elapsed time in this computation.  We could let the
+         * compensation code attempt to catch up if we fall behind, but
+         * it's better to try to match offsets from the beginning.
+         */
+        if (usdiff < USEC_PER_SEC &&
+            vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
                 if (!check_tsc_unstable()) {
-                        offset = kvm->arch.last_tsc_offset;
+                        offset = kvm->arch.cur_tsc_offset;
                         pr_debug("kvm: matched tsc offset for %llu\n", data);
                 } else {
                         u64 delta = nsec_to_cycles(vcpu, elapsed);
-                        offset += delta;
+                        data += delta;
+                        offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
                 }
-                ns = kvm->arch.last_tsc_nsec;
+        } else {
+                /*
+                 * We split periods of matched TSC writes into generations.
+                 * For each generation, we track the original measured
+                 * nanosecond time, offset, and write, so if TSCs are in
+                 * sync, we can match exact offset, and if not, we can match
+                 * exact software computaion in compute_guest_tsc()
+                 *
+                 * These values are tracked in kvm->arch.cur_xxx variables.
+                 */
+                kvm->arch.cur_tsc_generation++;
+                kvm->arch.cur_tsc_nsec = ns;
+                kvm->arch.cur_tsc_write = data;
+                kvm->arch.cur_tsc_offset = offset;
+                pr_debug("kvm: new tsc generation %u, clock %llu\n",
+                         kvm->arch.cur_tsc_generation, data);
         }
+
+        /*
+         * We also track th most recent recorded KHZ, write and time to
+         * allow the matching interval to be extended at each write.
+         */
         kvm->arch.last_tsc_nsec = ns;
         kvm->arch.last_tsc_write = data;
-        kvm->arch.last_tsc_offset = offset;
-        kvm_x86_ops->write_tsc_offset(vcpu, offset);
-        raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
+        kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
 
         /* Reset of TSC must disable overshoot protection below */
         vcpu->arch.hv_clock.tsc_timestamp = 0;
-        vcpu->arch.last_tsc_write = data;
-        vcpu->arch.last_tsc_nsec = ns;
+        vcpu->arch.last_guest_tsc = data;
+
+        /* Keep track of which generation this VCPU has synchronized to */
+        vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
+        vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
+        vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
+
+        kvm_x86_ops->write_tsc_offset(vcpu, offset);
+        raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
 }
+
 EXPORT_SYMBOL_GPL(kvm_write_tsc);
 
 static int kvm_guest_time_update(struct kvm_vcpu *v)
@@ -1078,7 +1123,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
         local_irq_save(flags);
         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
         kernel_ns = get_kernel_ns();
-        this_tsc_khz = vcpu_tsc_khz(v);
+        this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
         if (unlikely(this_tsc_khz == 0)) {
                 local_irq_restore(flags);
                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
@@ -1098,7 +1143,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
         if (vcpu->tsc_catchup) {
                 u64 tsc = compute_guest_tsc(v, kernel_ns);
                 if (tsc > tsc_timestamp) {
-                        kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
+                        adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
                         tsc_timestamp = tsc;
                 }
         }
@@ -1130,7 +1175,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
          * observed by the guest and ensure the new system time is greater.
          */
         max_kernel_ns = 0;
-        if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
+        if (vcpu->hv_clock.tsc_timestamp) {
                 max_kernel_ns = vcpu->last_guest_tsc -
                                 vcpu->hv_clock.tsc_timestamp;
                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
@@ -1504,6 +1549,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
         case MSR_K7_HWCR:
                 data &= ~(u64)0x40;     /* ignore flush filter disable */
                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
+                data &= ~(u64)0x8;      /* ignore TLB cache disable */
                 if (data != 0) {
                         pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
                                 data);
@@ -1676,6 +1722,16 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                  */
                 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
                 break;
+        case MSR_AMD64_OSVW_ID_LENGTH:
+                if (!guest_cpuid_has_osvw(vcpu))
+                        return 1;
+                vcpu->arch.osvw.length = data;
+                break;
+        case MSR_AMD64_OSVW_STATUS:
+                if (!guest_cpuid_has_osvw(vcpu))
+                        return 1;
+                vcpu->arch.osvw.status = data;
+                break;
         default:
                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
                         return xen_hvm_config(vcpu, data);
@@ -1960,6 +2016,16 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
                  */
                 data = 0xbe702111;
                 break;
+        case MSR_AMD64_OSVW_ID_LENGTH:
+                if (!guest_cpuid_has_osvw(vcpu))
+                        return 1;
+                data = vcpu->arch.osvw.length;
+                break;
+        case MSR_AMD64_OSVW_STATUS:
+                if (!guest_cpuid_has_osvw(vcpu))
+                        return 1;
+                data = vcpu->arch.osvw.status;
+                break;
         default:
                 if (kvm_pmu_msr(vcpu, msr))
                         return kvm_pmu_get_msr(vcpu, msr, pdata);
@@ -2080,6 +2146,7 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_XSAVE:
         case KVM_CAP_ASYNC_PF:
         case KVM_CAP_GET_TSC_KHZ:
+        case KVM_CAP_PCI_2_3:
                 r = 1;
                 break;
         case KVM_CAP_COALESCED_MMIO:
@@ -2214,19 +2281,23 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
         }
 
         kvm_x86_ops->vcpu_load(vcpu, cpu);
-        if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
-                /* Make sure TSC doesn't go backwards */
-                s64 tsc_delta;
-                u64 tsc;
 
-                tsc = kvm_x86_ops->read_l1_tsc(vcpu);
-                tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
-                             tsc - vcpu->arch.last_guest_tsc;
+        /* Apply any externally detected TSC adjustments (due to suspend) */
+        if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
+                adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
+                vcpu->arch.tsc_offset_adjustment = 0;
+                set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
+        }
 
+        if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
+                s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
+                                native_read_tsc() - vcpu->arch.last_host_tsc;
                 if (tsc_delta < 0)
                         mark_tsc_unstable("KVM discovered backwards TSC");
                 if (check_tsc_unstable()) {
-                        kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
+                        u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
+                                                vcpu->arch.last_guest_tsc);
+                        kvm_x86_ops->write_tsc_offset(vcpu, offset);
                         vcpu->arch.tsc_catchup = 1;
                 }
                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
@@ -2243,7 +2314,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
 {
         kvm_x86_ops->vcpu_put(vcpu);
         kvm_put_guest_fpu(vcpu);
-        vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
+        vcpu->arch.last_host_tsc = native_read_tsc();
 }
 
 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
@@ -2785,26 +2856,21 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 u32 user_tsc_khz;
 
                 r = -EINVAL;
-                if (!kvm_has_tsc_control)
-                        break;
-
                 user_tsc_khz = (u32)arg;
 
                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
                         goto out;
 
-                kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
+                if (user_tsc_khz == 0)
+                        user_tsc_khz = tsc_khz;
+
+                kvm_set_tsc_khz(vcpu, user_tsc_khz);
 
                 r = 0;
                 goto out;
         }
         case KVM_GET_TSC_KHZ: {
-                r = -EIO;
-                if (check_tsc_unstable())
-                        goto out;
-
-                r = vcpu_tsc_khz(vcpu);
-
+                r = vcpu->arch.virtual_tsc_khz;
                 goto out;
         }
         default:
@@ -2815,6 +2881,11 @@ out:
         return r;
 }
 
+int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
+{
+        return VM_FAULT_SIGBUS;
+}
+
 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
 {
         int ret;
@@ -2998,6 +3069,8 @@ static void write_protect_slot(struct kvm *kvm,
                                unsigned long *dirty_bitmap,
                                unsigned long nr_dirty_pages)
 {
+        spin_lock(&kvm->mmu_lock);
+
         /* Not many dirty pages compared to # of shadow pages. */
         if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
                 unsigned long gfn_offset;
@@ -3005,16 +3078,13 @@ static void write_protect_slot(struct kvm *kvm,
                 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
                         unsigned long gfn = memslot->base_gfn + gfn_offset;
 
-                        spin_lock(&kvm->mmu_lock);
                         kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
-                        spin_unlock(&kvm->mmu_lock);
                 }
                 kvm_flush_remote_tlbs(kvm);
-        } else {
-                spin_lock(&kvm->mmu_lock);
+        } else
                 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
-                spin_unlock(&kvm->mmu_lock);
-        }
+
+        spin_unlock(&kvm->mmu_lock);
 }
 
 /*
@@ -3133,6 +3203,9 @@ long kvm_arch_vm_ioctl(struct file *filp,
                 r = -EEXIST;
                 if (kvm->arch.vpic)
                         goto create_irqchip_unlock;
+                r = -EINVAL;
+                if (atomic_read(&kvm->online_vcpus))
+                        goto create_irqchip_unlock;
                 r = -ENOMEM;
                 vpic = kvm_create_pic(kvm);
                 if (vpic) {
@@ -4063,6 +4136,11 @@ static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
         return res;
 }
 
+static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
+{
+        kvm_set_rflags(emul_to_vcpu(ctxt), val);
+}
+
 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
 {
         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
@@ -4244,6 +4322,7 @@ static struct x86_emulate_ops emulate_ops = {
         .set_idt             = emulator_set_idt,
         .get_cr              = emulator_get_cr,
         .set_cr              = emulator_set_cr,
+        .set_rflags          = emulator_set_rflags,
         .cpl                 = emulator_get_cpl,
         .get_dr              = emulator_get_dr,
         .set_dr              = emulator_set_dr,
@@ -5288,6 +5367,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                 profile_hit(KVM_PROFILING, (void *)rip);
         }
 
+        if (unlikely(vcpu->arch.tsc_always_catchup))
+                kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
 
         kvm_lapic_sync_from_vapic(vcpu);
 
@@ -5587,15 +5668,15 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
         return 0;
 }
 
-int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
-                    bool has_error_code, u32 error_code)
+int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
+                    int reason, bool has_error_code, u32 error_code)
 {
         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
         int ret;
 
         init_emulate_ctxt(vcpu);
 
-        ret = emulator_task_switch(ctxt, tss_selector, reason,
+        ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
                                    has_error_code, error_code);
 
         if (ret)
@@ -5928,13 +6009,88 @@ int kvm_arch_hardware_enable(void *garbage)
         struct kvm *kvm;
         struct kvm_vcpu *vcpu;
         int i;
+        int ret;
+        u64 local_tsc;
+        u64 max_tsc = 0;
+        bool stable, backwards_tsc = false;
 
         kvm_shared_msr_cpu_online();
-        list_for_each_entry(kvm, &vm_list, vm_list)
-                kvm_for_each_vcpu(i, vcpu, kvm)
-                        if (vcpu->cpu == smp_processor_id())
-                                kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
-        return kvm_x86_ops->hardware_enable(garbage);
+        ret = kvm_x86_ops->hardware_enable(garbage);
+        if (ret != 0)
+                return ret;
+
+        local_tsc = native_read_tsc();
+        stable = !check_tsc_unstable();
+        list_for_each_entry(kvm, &vm_list, vm_list) {
+                kvm_for_each_vcpu(i, vcpu, kvm) {
+                        if (!stable && vcpu->cpu == smp_processor_id())
+                                set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
+                        if (stable && vcpu->arch.last_host_tsc > local_tsc) {
+                                backwards_tsc = true;
+                                if (vcpu->arch.last_host_tsc > max_tsc)
+                                        max_tsc = vcpu->arch.last_host_tsc;
+                        }
+                }
+        }
+
+        /*
+         * Sometimes, even reliable TSCs go backwards.  This happens on
+         * platforms that reset TSC during suspend or hibernate actions, but
+         * maintain synchronization.  We must compensate.  Fortunately, we can
+         * detect that condition here, which happens early in CPU bringup,
+         * before any KVM threads can be running.  Unfortunately, we can't
+         * bring the TSCs fully up to date with real time, as we aren't yet far
+         * enough into CPU bringup that we know how much real time has actually
+         * elapsed; our helper function, get_kernel_ns() will be using boot
+         * variables that haven't been updated yet.
+         *
+         * So we simply find the maximum observed TSC above, then record the
+         * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
+         * the adjustment will be applied.  Note that we accumulate
+         * adjustments, in case multiple suspend cycles happen before some VCPU
+         * gets a chance to run again.  In the event that no KVM threads get a
+         * chance to run, we will miss the entire elapsed period, as we'll have
+         * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
+         * loose cycle time.  This isn't too big a deal, since the loss will be
+         * uniform across all VCPUs (not to mention the scenario is extremely
+         * unlikely). It is possible that a second hibernate recovery happens
+         * much faster than a first, causing the observed TSC here to be
+         * smaller; this would require additional padding adjustment, which is
+         * why we set last_host_tsc to the local tsc observed here.
+         *
+         * N.B. - this code below runs only on platforms with reliable TSC,
+         * as that is the only way backwards_tsc is set above.  Also note
+         * that this runs for ALL vcpus, which is not a bug; all VCPUs should
+         * have the same delta_cyc adjustment applied if backwards_tsc
+         * is detected.  Note further, this adjustment is only done once,
+         * as we reset last_host_tsc on all VCPUs to stop this from being
+         * called multiple times (one for each physical CPU bringup).
+         *
+         * Platforms with unnreliable TSCs don't have to deal with this, they
+         * will be compensated by the logic in vcpu_load, which sets the TSC to
+         * catchup mode.  This will catchup all VCPUs to real time, but cannot
+         * guarantee that they stay in perfect synchronization.
+         */
+        if (backwards_tsc) {
+                u64 delta_cyc = max_tsc - local_tsc;
+                list_for_each_entry(kvm, &vm_list, vm_list) {
+                        kvm_for_each_vcpu(i, vcpu, kvm) {
+                                vcpu->arch.tsc_offset_adjustment += delta_cyc;
+                                vcpu->arch.last_host_tsc = local_tsc;
+                        }
+
+                        /*
+                         * We have to disable TSC offset matching.. if you were
+                         * booting a VM while issuing an S4 host suspend....
+                         * you may have some problem.  Solving this issue is
+                         * left as an exercise to the reader.
+                         */
+                        kvm->arch.last_tsc_nsec = 0;
+                        kvm->arch.last_tsc_write = 0;
+                }
+
+        }
+        return 0;
 }
 
 void kvm_arch_hardware_disable(void *garbage)
@@ -5958,6 +6114,11 @@ void kvm_arch_check_processor_compat(void *rtn)
         kvm_x86_ops->check_processor_compatibility(rtn);
 }
 
+bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
+{
+        return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
+}
+
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
 {
         struct page *page;
@@ -5980,7 +6141,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         }
         vcpu->arch.pio_data = page_address(page);
 
-        kvm_init_tsc_catchup(vcpu, max_tsc_khz);
+        kvm_set_tsc_khz(vcpu, max_tsc_khz);
 
         r = kvm_mmu_create(vcpu);
         if (r < 0)
@@ -6032,8 +6193,11 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
         free_page((unsigned long)vcpu->arch.pio_data);
 }
 
-int kvm_arch_init_vm(struct kvm *kvm)
+int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 {
+        if (type)
+                return -EINVAL;
+
         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
 
@@ -6093,6 +6257,65 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
                 put_page(kvm->arch.ept_identity_pagetable);
 }
 
+void kvm_arch_free_memslot(struct kvm_memory_slot *free,
+                           struct kvm_memory_slot *dont)
+{
+        int i;
+
+        for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
+                if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
+                        vfree(free->arch.lpage_info[i]);
+                        free->arch.lpage_info[i] = NULL;
+                }
+        }
+}
+
+int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
+{
+        int i;
+
+        for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
+                unsigned long ugfn;
+                int lpages;
+                int level = i + 2;
+
+                lpages = gfn_to_index(slot->base_gfn + npages - 1,
+                                      slot->base_gfn, level) + 1;
+
+                slot->arch.lpage_info[i] =
+                        vzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
+                if (!slot->arch.lpage_info[i])
+                        goto out_free;
+
+                if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
+                        slot->arch.lpage_info[i][0].write_count = 1;
+                if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
+                        slot->arch.lpage_info[i][lpages - 1].write_count = 1;
+                ugfn = slot->userspace_addr >> PAGE_SHIFT;
+                /*
+                 * If the gfn and userspace address are not aligned wrt each
+                 * other, or if explicitly asked to, disable large page
+                 * support for this slot
+                 */
+                if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
+                    !kvm_largepages_enabled()) {
+                        unsigned long j;
+
+                        for (j = 0; j < lpages; ++j)
+                                slot->arch.lpage_info[i][j].write_count = 1;
+                }
+        }
+
+        return 0;
+
+out_free:
+        for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
+                vfree(slot->arch.lpage_info[i]);
+                slot->arch.lpage_info[i] = NULL;
+        }
+        return -ENOMEM;
+}
+
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                 struct kvm_memory_slot *memslot,
                                 struct kvm_memory_slot old,
diff --git a/arch/x86/mm/kmemcheck/selftest.c b/arch/x86/mm/kmemcheck/selftest.c
index 036efbea8b2..aef7140c006 100644
--- a/arch/x86/mm/kmemcheck/selftest.c
+++ b/arch/x86/mm/kmemcheck/selftest.c
@@ -1,3 +1,4 @@
+#include <linux/bug.h>
 #include <linux/kernel.h>
 
 #include "opcode.h"
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 49a5cb55429..ed2835e148b 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -416,7 +416,12 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
                 kfree(sd);
         } else {
                 get_current_resources(device, busnum, domain, &resources);
-                if (list_empty(&resources))
+
+                /*
+                 * _CRS with no apertures is normal, so only fall back to
+                 * defaults or native bridge info if we're ignoring _CRS.
+                 */
+                if (!pci_use_crs)
                         x86_pci_root_bus_resources(busnum, &resources);
                 bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
                                           &resources);
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 6dd89555fbf..d0e6e403b4f 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -164,11 +164,11 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_
  */
 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
 {
-        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
-            (dev->device & 0xff00) == 0x2400)
+        if ((dev->device & 0xff00) == 0x2400)
                 dev->transparent = 1;
 }
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
+DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
+                         PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
 
 /*
  * Fixup for C1 Halt Disconnect problem on nForce2 systems.
@@ -322,9 +322,6 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
         struct pci_bus *bus;
         u16 config;
 
-        if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
-                return;
-
         /* Is VGA routed to us? */
         bus = pdev->bus;
         while (bus) {
@@ -353,7 +350,8 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
                 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
         }
 }
-DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+                                PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
 
 
 static const struct dmi_system_id __devinitconst msi_k8t_dmi_table[] = {
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 91821a1a0c3..831971e731f 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -39,6 +39,87 @@
 #include <asm/io_apic.h>
 
 
+/*
+ * This list of dynamic mappings is for temporarily maintaining
+ * original BIOS BAR addresses for possible reinstatement.
+ */
+struct pcibios_fwaddrmap {
+        struct list_head list;
+        struct pci_dev *dev;
+        resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
+};
+
+static LIST_HEAD(pcibios_fwaddrmappings);
+static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
+
+/* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
+static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
+{
+        struct pcibios_fwaddrmap *map;
+
+        WARN_ON(!spin_is_locked(&pcibios_fwaddrmap_lock));
+
+        list_for_each_entry(map, &pcibios_fwaddrmappings, list)
+                if (map->dev == dev)
+                        return map;
+
+        return NULL;
+}
+
+static void
+pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *map;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        map = pcibios_fwaddrmap_lookup(dev);
+        if (!map) {
+                spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+                map = kzalloc(sizeof(*map), GFP_KERNEL);
+                if (!map)
+                        return;
+
+                map->dev = pci_dev_get(dev);
+                map->fw_addr[idx] = fw_addr;
+                INIT_LIST_HEAD(&map->list);
+
+                spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+                list_add_tail(&map->list, &pcibios_fwaddrmappings);
+        } else
+                map->fw_addr[idx] = fw_addr;
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+}
+
+resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *map;
+        resource_size_t fw_addr = 0;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        map = pcibios_fwaddrmap_lookup(dev);
+        if (map)
+                fw_addr = map->fw_addr[idx];
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+
+        return fw_addr;
+}
+
+static void pcibios_fw_addr_list_del(void)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *entry, *next;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
+                list_del(&entry->list);
+                pci_dev_put(entry->dev);
+                kfree(entry);
+        }
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+}
+
 static int
 skip_isa_ioresource_align(struct pci_dev *dev) {
 
@@ -182,7 +263,8 @@ static void __init pcibios_allocate_resources(int pass)
                                         idx, r, disabled, pass);
                                 if (pci_claim_resource(dev, idx) < 0) {
                                         /* We'll assign a new address later */
-                                        dev->fw_addr[idx] = r->start;
+                                        pcibios_save_fw_addr(dev,
+                                                        idx, r->start);
                                         r->end -= r->start;
                                         r->start = 0;
                                 }
@@ -228,6 +310,7 @@ static int __init pcibios_assign_resources(void)
         }
 
         pci_assign_unassigned_resources();
+        pcibios_fw_addr_list_del();
 
         return 0;
 }
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index cb29191cee5..140942f66b3 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -43,6 +43,8 @@
 #define PCI_FIXED_BAR_4_SIZE    0x14
 #define PCI_FIXED_BAR_5_SIZE    0x1c
 
+static int pci_soc_mode = 0;
+
 /**
  * fixed_bar_cap - return the offset of the fixed BAR cap if found
  * @bus: PCI bus
@@ -148,7 +150,9 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
          */
         if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
                 return 0;
-        if (bus == 0 && (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(0, 0)))
+        if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
+                                || devfn == PCI_DEVFN(0, 0)
+                                || devfn == PCI_DEVFN(3, 0)))
                 return 1;
         return 0; /* langwell on others */
 }
@@ -231,14 +235,43 @@ struct pci_ops pci_mrst_ops = {
  */
 int __init pci_mrst_init(void)
 {
-        printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n");
+        printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n");
         pci_mmcfg_late_init();
         pcibios_enable_irq = mrst_pci_irq_enable;
         pci_root_ops = pci_mrst_ops;
+        pci_soc_mode = 1;
         /* Continue with standard init */
         return 1;
 }
 
+/* Langwell devices are not true pci devices, they are not subject to 10 ms
+ * d3 to d0 delay required by pci spec.
+ */
+static void __devinit pci_d3delay_fixup(struct pci_dev *dev)
+{
+        /* PCI fixups are effectively decided compile time. If we have a dual
+           SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */
+        if (!pci_soc_mode)
+            return;
+        /* true pci devices in lincroft should allow type 1 access, the rest
+         * are langwell fake pci devices.
+         */
+        if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
+                return;
+        dev->d3_delay = 0;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
+
+static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev)
+{
+        pci_set_power_state(dev, PCI_D3cold);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0812, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
+
 /*
  * Langwell devices reside at fixed offsets, don't try to move them.
  */
@@ -248,6 +281,9 @@ static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev)
         u32 size;
         int i;
 
+        if (!pci_soc_mode)
+                return;
+
         /* Must have extended configuration space */
         if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
                 return;
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts
index e70be38ce03..ce874f872cc 100644
--- a/arch/x86/platform/ce4100/falconfalls.dts
+++ b/arch/x86/platform/ce4100/falconfalls.dts
@@ -208,16 +208,19 @@
                                         interrupts = <14 1>;
                                 };
 
-                                gpio@b,1 {
+                                pcigpio: gpio@b,1 {
+                                        #gpio-cells = <2>;
+                                        #interrupt-cells = <2>;
                                         compatible = "pci8086,2e67.2",
                                                    "pci8086,2e67",
                                                    "pciclassff0000",
                                                    "pciclassff00";
 
-                                        #gpio-cells = <2>;
                                         reg = <0x15900 0x0 0x0 0x0 0x0>;
                                         interrupts = <15 1>;
+                                        interrupt-controller;
                                         gpio-controller;
+                                        intel,muxctl = <0>;
                                 };
 
                                 i2c-controller@b,2 {
diff --git a/arch/x86/platform/geode/Makefile b/arch/x86/platform/geode/Makefile
index 246b788847f..5b51194f4c8 100644
--- a/arch/x86/platform/geode/Makefile
+++ b/arch/x86/platform/geode/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_ALIX)              += alix.o
 obj-$(CONFIG_NET5501)           += net5501.o
+obj-$(CONFIG_GEOS)              += geos.o
diff --git a/arch/x86/platform/geode/geos.c b/arch/x86/platform/geode/geos.c
new file mode 100644
index 00000000000..c2e6d53558b
--- /dev/null
+++ b/arch/x86/platform/geode/geos.c
@@ -0,0 +1,128 @@
+/*
+ * System Specific setup for Traverse Technologies GEOS.
+ * At the moment this means setup of GPIO control of LEDs.
+ *
+ * Copyright (C) 2008 Constantin Baranov <const@mimas.ru>
+ * Copyright (C) 2011 Ed Wildgoose <kernel@wildgooses.com>
+ *                and Philip Prindeville <philipp@redfish-solutions.com>
+ *
+ * TODO: There are large similarities with leds-net5501.c
+ * by Alessandro Zummo <a.zummo@towertech.it>
+ * In the future leds-net5501.c should be migrated over to platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/dmi.h>
+
+#include <asm/geode.h>
+
+static struct gpio_keys_button geos_gpio_buttons[] = {
+        {
+                .code = KEY_RESTART,
+                .gpio = 3,
+                .active_low = 1,
+                .desc = "Reset button",
+                .type = EV_KEY,
+                .wakeup = 0,
+                .debounce_interval = 100,
+                .can_disable = 0,
+        }
+};
+static struct gpio_keys_platform_data geos_buttons_data = {
+        .buttons = geos_gpio_buttons,
+        .nbuttons = ARRAY_SIZE(geos_gpio_buttons),
+        .poll_interval = 20,
+};
+
+static struct platform_device geos_buttons_dev = {
+        .name = "gpio-keys-polled",
+        .id = 1,
+        .dev = {
+                .platform_data = &geos_buttons_data,
+        }
+};
+
+static struct gpio_led geos_leds[] = {
+        {
+                .name = "geos:1",
+                .gpio = 6,
+                .default_trigger = "default-on",
+                .active_low = 1,
+        },
+        {
+                .name = "geos:2",
+                .gpio = 25,
+                .default_trigger = "default-off",
+                .active_low = 1,
+        },
+        {
+                .name = "geos:3",
+                .gpio = 27,
+                .default_trigger = "default-off",
+                .active_low = 1,
+        },
+};
+
+static struct gpio_led_platform_data geos_leds_data = {
+        .num_leds = ARRAY_SIZE(geos_leds),
+        .leds = geos_leds,
+};
+
+static struct platform_device geos_leds_dev = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev.platform_data = &geos_leds_data,
+};
+
+static struct __initdata platform_device *geos_devs[] = {
+        &geos_buttons_dev,
+        &geos_leds_dev,
+};
+
+static void __init register_geos(void)
+{
+        /* Setup LED control through leds-gpio driver */
+        platform_add_devices(geos_devs, ARRAY_SIZE(geos_devs));
+}
+
+static int __init geos_init(void)
+{
+        const char *vendor, *product;
+
+        if (!is_geode())
+                return 0;
+
+        vendor = dmi_get_system_info(DMI_SYS_VENDOR);
+        if (!vendor || strcmp(vendor, "Traverse Technologies"))
+                return 0;
+
+        product = dmi_get_system_info(DMI_PRODUCT_NAME);
+        if (!product || strcmp(product, "Geos"))
+                return 0;
+
+        printk(KERN_INFO "%s: system is recognized as \"%s %s\"\n",
+               KBUILD_MODNAME, vendor, product);
+
+        register_geos();
+
+        return 0;
+}
+
+module_init(geos_init);
+
+MODULE_AUTHOR("Philip Prindeville <philipp@redfish-solutions.com>");
+MODULE_DESCRIPTION("Traverse Technologies Geos System Setup");
+MODULE_LICENSE("GPL");
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 4889655ba78..47936830968 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -115,7 +115,7 @@ static void __save_processor_state(struct saved_context *ctxt)
 void save_processor_state(void)
 {
         __save_processor_state(&saved_context);
-        save_sched_clock_state();
+        x86_platform.save_sched_clock_state();
 }
 #ifdef CONFIG_X86_32
 EXPORT_SYMBOL(save_processor_state);
@@ -231,8 +231,8 @@ static void __restore_processor_state(struct saved_context *ctxt)
 /* Needed by apm.c */
 void restore_processor_state(void)
 {
+        x86_platform.restore_sched_clock_state();
         __restore_processor_state(&saved_context);
-        restore_sched_clock_state();
 }
 #ifdef CONFIG_X86_32
 EXPORT_SYMBOL(restore_processor_state);
diff --git a/arch/x86/syscalls/syscall_32.tbl b/arch/x86/syscalls/syscall_32.tbl
index ce98e287c06..e7e67cc3c14 100644
--- a/arch/x86/syscalls/syscall_32.tbl
+++ b/arch/x86/syscalls/syscall_32.tbl
@@ -288,7 +288,7 @@
 279     i386    mq_timedsend            sys_mq_timedsend                compat_sys_mq_timedsend
 280     i386    mq_timedreceive         sys_mq_timedreceive             compat_sys_mq_timedreceive
 281     i386    mq_notify               sys_mq_notify                   compat_sys_mq_notify
-282     i386    mq_getsetaddr           sys_mq_getsetattr               compat_sys_mq_getsetattr
+282     i386    mq_getsetattr           sys_mq_getsetattr               compat_sys_mq_getsetattr
 283     i386    kexec_load              sys_kexec_load                  compat_sys_kexec_load
 284     i386    waitid                  sys_waitid                      compat_sys_waitid
 # 285 sys_setaltroot
diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig
index b2b54d2edf5..9926e11a772 100644
--- a/arch/x86/um/Kconfig
+++ b/arch/x86/um/Kconfig
@@ -15,8 +15,8 @@ config UML_X86
         select GENERIC_FIND_FIRST_BIT
 
 config 64BIT
-        bool
-        default SUBARCH = "x86_64"
+        bool "64-bit kernel" if SUBARCH = "x86"
+        default SUBARCH != "i386"
 
 config X86_32
         def_bool !64BIT
diff --git a/arch/x86/um/asm/processor.h b/arch/x86/um/asm/processor.h
index 2c32df6fe23..04f82e020f2 100644
--- a/arch/x86/um/asm/processor.h
+++ b/arch/x86/um/asm/processor.h
@@ -17,6 +17,16 @@
 #define ARCH_IS_STACKGROW(address) \
        (address + 65536 + 32 * sizeof(unsigned long) >= UPT_SP(&current->thread.regs.regs))
 
+#include <asm/user.h>
+
+/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
+static inline void rep_nop(void)
+{
+        __asm__ __volatile__("rep;nop": : :"memory");
+}
+
+#define cpu_relax()     rep_nop()
+
 #include <asm/processor-generic.h>
 
 #endif
diff --git a/arch/x86/um/asm/processor_32.h b/arch/x86/um/asm/processor_32.h
index 018f732704d..6c6689e574c 100644
--- a/arch/x86/um/asm/processor_32.h
+++ b/arch/x86/um/asm/processor_32.h
@@ -45,16 +45,6 @@ static inline void arch_copy_thread(struct arch_thread *from,
         memcpy(&to->tls_array, &from->tls_array, sizeof(from->tls_array));
 }
 
-#include <asm/user.h>
-
-/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
-static inline void rep_nop(void)
-{
-        __asm__ __volatile__("rep;nop": : :"memory");
-}
-
-#define cpu_relax()     rep_nop()
-
 /*
  * Default implementation of macro that returns current
  * instruction pointer ("program counter"). Stolen
diff --git a/arch/x86/um/asm/processor_64.h b/arch/x86/um/asm/processor_64.h
index 61de92d916c..4b02a8455bd 100644
--- a/arch/x86/um/asm/processor_64.h
+++ b/arch/x86/um/asm/processor_64.h
@@ -14,14 +14,6 @@ struct arch_thread {
         struct faultinfo faultinfo;
 };
 
-/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
-static inline void rep_nop(void)
-{
-        __asm__ __volatile__("rep;nop": : :"memory");
-}
-
-#define cpu_relax()   rep_nop()
-
 #define INIT_ARCH_THREAD { .debugregs           = { [ 0 ... 7 ] = 0 }, \
                            .debugregs_seq       = 0, \
                            .fs                  = 0, \
@@ -37,8 +29,6 @@ static inline void arch_copy_thread(struct arch_thread *from,
         to->fs = from->fs;
 }
 
-#include <asm/user.h>
-
 #define current_text_addr() \
         ({ void *pc; __asm__("movq $1f,%0\n1:":"=g" (pc)); pc; })
 
diff --git a/arch/x86/um/bugs_32.c b/arch/x86/um/bugs_32.c
index a1fba5fb9db..17d88cf2c6c 100644
--- a/arch/x86/um/bugs_32.c
+++ b/arch/x86/um/bugs_32.c
@@ -13,8 +13,6 @@
 static int host_has_cmov = 1;
 static jmp_buf cmov_test_return;
 
-#define TASK_PID(task) *((int *) &(((char *) (task))[HOST_TASK_PID]))
-
 static void cmov_sigill_test_handler(int sig)
 {
         host_has_cmov = 0;
@@ -51,7 +49,7 @@ void arch_examine_signal(int sig, struct uml_pt_regs *regs)
          * This is testing for a cmov (0x0f 0x4x) instruction causing a
          * SIGILL in init.
          */
-        if ((sig != SIGILL) || (TASK_PID(get_current()) != 1))
+        if ((sig != SIGILL) || (get_current_pid() != 1))
                 return;
 
         if (copy_from_user_proc(tmp, (void *) UPT_IP(regs), 2)) {
diff --git a/arch/x86/um/mem_32.c b/arch/x86/um/mem_32.c
index 639900a6fde..f40281e5d6a 100644
--- a/arch/x86/um/mem_32.c
+++ b/arch/x86/um/mem_32.c
@@ -23,14 +23,6 @@ static int __init gate_vma_init(void)
         gate_vma.vm_flags = VM_READ | VM_MAYREAD | VM_EXEC | VM_MAYEXEC;
         gate_vma.vm_page_prot = __P101;
 
-        /*
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
-         */
-        gate_vma.vm_flags |= VM_ALWAYSDUMP;
-
         return 0;
 }
 __initcall(gate_vma_init);
diff --git a/arch/x86/um/vdso/vma.c b/arch/x86/um/vdso/vma.c
index 91f4ec9a0a5..af91901babb 100644
--- a/arch/x86/um/vdso/vma.c
+++ b/arch/x86/um/vdso/vma.c
@@ -64,8 +64,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         err = install_special_mapping(mm, um_vdso_addr, PAGE_SIZE,
                 VM_READ|VM_EXEC|
-                VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                VM_ALWAYSDUMP,
+                VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                 vdsop);
 
         up_write(&mm->mmap_sem);
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index 468d591dde3..a944020fa85 100644
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -250,13 +250,7 @@ static int __init gate_vma_init(void)
         gate_vma.vm_end = FIXADDR_USER_END;
         gate_vma.vm_flags = VM_READ | VM_MAYREAD | VM_EXEC | VM_MAYEXEC;
         gate_vma.vm_page_prot = __P101;
-        /*
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
-         */
-        gate_vma.vm_flags |= VM_ALWAYSDUMP;
+
         return 0;
 }
 
@@ -343,17 +337,10 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
         if (compat_uses_vma || !compat) {
                 /*
                  * MAYWRITE to allow gdb to COW and set breakpoints
-                 *
-                 * Make sure the vDSO gets into every core dump.
-                 * Dumping its contents makes post-mortem fully
-                 * interpretable later without matching up the same
-                 * kernel and hardware config to see what PC values
-                 * meant.
                  */
                 ret = install_special_mapping(mm, addr, PAGE_SIZE,
                                               VM_READ|VM_EXEC|
-                                              VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                              VM_ALWAYSDUMP,
+                                              VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                               vdso32_pages);
 
                 if (ret)
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index 153407c35b7..17e18279649 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -124,8 +124,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         ret = install_special_mapping(mm, addr, vdso_size,
                                       VM_READ|VM_EXEC|
-                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                       vdso_pages);
         if (ret) {
                 current->mm->context.vdso = NULL;
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index 12366238d07..1ba8dff2675 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -10,6 +10,7 @@
 #include <linux/pm.h>
 #include <linux/memblock.h>
 #include <linux/cpuidle.h>
+#include <linux/cpufreq.h>
 
 #include <asm/elf.h>
 #include <asm/vdso.h>
@@ -420,6 +421,7 @@ void __init xen_arch_setup(void)
         boot_cpu_data.hlt_works_ok = 1;
 #endif
         disable_cpuidle();
+        disable_cpufreq();
         WARN_ON(set_pm_idle_to_default());
         fiddle_vdso();
 }
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 315d8fa0c8f..02900e8ce26 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -75,8 +75,14 @@ static void __cpuinit cpu_bringup(void)
 
         xen_setup_cpu_clockevents();
 
+        notify_cpu_starting(cpu);
+
+        ipi_call_lock();
         set_cpu_online(cpu, true);
+        ipi_call_unlock();
+
         this_cpu_write(cpu_state, CPU_ONLINE);
+
         wmb();
 
         /* We can take interrupts now: we're officially "up". */
diff --git a/arch/xtensa/include/asm/mman.h b/arch/xtensa/include/asm/mman.h
index 30789010733..25bc6c1309c 100644
--- a/arch/xtensa/include/asm/mman.h
+++ b/arch/xtensa/include/asm/mman.h
@@ -86,6 +86,10 @@
 #define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   16              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     17              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 
diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c
index 61045c192e8..eb30e356f5b 100644
--- a/arch/xtensa/kernel/pci.c
+++ b/arch/xtensa/kernel/pci.c
@@ -153,7 +153,7 @@ static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
         }
         res->start += io_offset;
         res->end += io_offset;
-        pci_add_resource(resources, res);
+        pci_add_resource_offset(resources, res, io_offset);
 
         for (i = 0; i < 3; i++) {
                 res = &pci_ctrl->mem_resources[i];
@@ -200,24 +200,9 @@ subsys_initcall(pcibios_init);
 
 void __init pcibios_fixup_bus(struct pci_bus *bus)
 {
-        struct pci_controller *pci_ctrl = bus->sysdata;
-        struct resource *res;
-        unsigned long io_offset;
-        int i;
-
-        io_offset = (unsigned long)pci_ctrl->io_space.base;
         if (bus->parent) {
                 /* This is a subordinate bridge */
                 pci_read_bridge_bases(bus);
-
-                for (i = 0; i < 4; i++) {
-                        if ((res = bus->resource[i]) == NULL || !res->flags)
-                                continue;
-                        if (io_offset && (res->flags & IORESOURCE_IO)) {
-                                res->start += io_offset;
-                                res->end += io_offset;
-                        }
-                }
         }
 }