1 files changed, 72 insertions, 28 deletions

diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c
index 9c70af45b42..947554ddabb 100644
--- a/arch/x86/kernel/tsc_64.c
+++ b/arch/x86/kernel/tsc_64.c
@@ -10,6 +10,7 @@
 
 #include <asm/hpet.h>
 #include <asm/timex.h>
+#include <asm/timer.h>
 
 static int notsc __initdata = 0;
 
@@ -18,19 +19,51 @@ EXPORT_SYMBOL(cpu_khz);
 unsigned int tsc_khz;
 EXPORT_SYMBOL(tsc_khz);
 
-static unsigned int cyc2ns_scale __read_mostly;
+/* Accelerators for sched_clock()
+ * convert from cycles(64bits) => nanoseconds (64bits)
+ *  basic equation:
+ *              ns = cycles / (freq / ns_per_sec)
+ *              ns = cycles * (ns_per_sec / freq)
+ *              ns = cycles * (10^9 / (cpu_khz * 10^3))
+ *              ns = cycles * (10^6 / cpu_khz)
+ *
+ *      Then we use scaling math (suggested by george@mvista.com) to get:
+ *              ns = cycles * (10^6 * SC / cpu_khz) / SC
+ *              ns = cycles * cyc2ns_scale / SC
+ *
+ *      And since SC is a constant power of two, we can convert the div
+ *  into a shift.
+ *
+ *  We can use khz divisor instead of mhz to keep a better precision, since
+ *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
+ *  (mathieu.desnoyers@polymtl.ca)
+ *
+ *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
+ */
+DEFINE_PER_CPU(unsigned long, cyc2ns);
 
-static inline void set_cyc2ns_scale(unsigned long khz)
+static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
 {
-        cyc2ns_scale = (NSEC_PER_MSEC << NS_SCALE) / khz;
-}
+        unsigned long flags, prev_scale, *scale;
+        unsigned long long tsc_now, ns_now;
 
-static unsigned long long cycles_2_ns(unsigned long long cyc)
-{
-        return (cyc * cyc2ns_scale) >> NS_SCALE;
+        local_irq_save(flags);
+        sched_clock_idle_sleep_event();
+
+        scale = &per_cpu(cyc2ns, cpu);
+
+        rdtscll(tsc_now);
+        ns_now = __cycles_2_ns(tsc_now);
+
+        prev_scale = *scale;
+        if (cpu_khz)
+                *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
+
+        sched_clock_idle_wakeup_event(0);
+        local_irq_restore(flags);
 }
 
-unsigned long long sched_clock(void)
+unsigned long long native_sched_clock(void)
 {
         unsigned long a = 0;
 
@@ -44,12 +77,27 @@ unsigned long long sched_clock(void)
         return cycles_2_ns(a);
 }
 
+/* We need to define a real function for sched_clock, to override the
+   weak default version */
+#ifdef CONFIG_PARAVIRT
+unsigned long long sched_clock(void)
+{
+        return paravirt_sched_clock();
+}
+#else
+unsigned long long
+sched_clock(void) __attribute__((alias("native_sched_clock")));
+#endif
+
+
 static int tsc_unstable;
 
-inline int check_tsc_unstable(void)
+int check_tsc_unstable(void)
 {
         return tsc_unstable;
 }
+EXPORT_SYMBOL_GPL(check_tsc_unstable);
+
 #ifdef CONFIG_CPU_FREQ
 
 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
@@ -100,7 +148,9 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
                         mark_tsc_unstable("cpufreq changes");
         }
 
-        set_cyc2ns_scale(tsc_khz_ref);
+        preempt_disable();
+        set_cyc2ns_scale(tsc_khz_ref, smp_processor_id());
+        preempt_enable();
 
         return 0;
 }
@@ -133,12 +183,12 @@ static unsigned long __init tsc_read_refs(unsigned long *pm,
         int i;
 
         for (i = 0; i < MAX_RETRIES; i++) {
-                t1 = get_cycles_sync();
+                t1 = get_cycles();
                 if (hpet)
                         *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
                 else
                         *pm = acpi_pm_read_early();
-                t2 = get_cycles_sync();
+                t2 = get_cycles();
                 if ((t2 - t1) < SMI_TRESHOLD)
                         return t2;
         }
@@ -151,7 +201,7 @@ static unsigned long __init tsc_read_refs(unsigned long *pm,
 void __init tsc_calibrate(void)
 {
         unsigned long flags, tsc1, tsc2, tr1, tr2, pm1, pm2, hpet1, hpet2;
-        int hpet = is_hpet_enabled();
+        int hpet = is_hpet_enabled(), cpu;
 
         local_irq_save(flags);
 
@@ -162,9 +212,9 @@ void __init tsc_calibrate(void)
         outb(0xb0, 0x43);
         outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
         outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
-        tr1 = get_cycles_sync();
+        tr1 = get_cycles();
         while ((inb(0x61) & 0x20) == 0);
-        tr2 = get_cycles_sync();
+        tr2 = get_cycles();
 
         tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
 
@@ -206,7 +256,9 @@ void __init tsc_calibrate(void)
         }
 
         tsc_khz = tsc2 / tsc1;
-        set_cyc2ns_scale(tsc_khz);
+
+        for_each_possible_cpu(cpu)
+                set_cyc2ns_scale(tsc_khz, cpu);
 }
 
 /*
@@ -222,17 +274,9 @@ __cpuinit int unsynchronized_tsc(void)
         if (apic_is_clustered_box())
                 return 1;
 #endif
-        /* Most intel systems have synchronized TSCs except for
-           multi node systems */
-        if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
-#ifdef CONFIG_ACPI
-                /* But TSC doesn't tick in C3 so don't use it there */
-                if (acpi_gbl_FADT.header.length > 0 &&
-                    acpi_gbl_FADT.C3latency < 1000)
-                        return 1;
-#endif
+
+        if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
                 return 0;
-        }
 
         /* Assume multi socket systems are not synchronized */
         return num_present_cpus() > 1;
@@ -250,13 +294,13 @@ __setup("notsc", notsc_setup);
 /* clock source code: */
 static cycle_t read_tsc(void)
 {
-        cycle_t ret = (cycle_t)get_cycles_sync();
+        cycle_t ret = (cycle_t)get_cycles();
         return ret;
 }
 
 static cycle_t __vsyscall_fn vread_tsc(void)
 {
-        cycle_t ret = (cycle_t)get_cycles_sync();
+        cycle_t ret = (cycle_t)vget_cycles();
         return ret;
 }