6 files changed, 163 insertions, 152 deletions

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b9338b8cf42..a2fd72e0ab3 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -27,6 +27,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/delay.h>
 #include <linux/timex.h>
+#include <linux/i8253.h>
 #include <linux/dmar.h>
 #include <linux/init.h>
 #include <linux/cpu.h>
@@ -37,9 +38,8 @@
 #include <asm/perf_event.h>
 #include <asm/x86_init.h>
 #include <asm/pgalloc.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/mpspec.h>
-#include <asm/i8253.h>
 #include <asm/i8259.h>
 #include <asm/proto.h>
 #include <asm/apic.h>
@@ -48,6 +48,7 @@
 #include <asm/hpet.h>
 #include <asm/idle.h>
 #include <asm/mtrr.h>
+#include <asm/time.h>
 #include <asm/smp.h>
 #include <asm/mce.h>
 #include <asm/tsc.h>
@@ -1429,34 +1430,28 @@ void enable_x2apic(void)
         rdmsr(MSR_IA32_APICBASE, msr, msr2);
         if (!(msr & X2APIC_ENABLE)) {
                 printk_once(KERN_INFO "Enabling x2apic\n");
-                wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+                wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
         }
 }
 #endif /* CONFIG_X86_X2APIC */
 
 int __init enable_IR(void)
 {
-#ifdef CONFIG_INTR_REMAP
+#ifdef CONFIG_IRQ_REMAP
         if (!intr_remapping_supported()) {
                 pr_debug("intr-remapping not supported\n");
-                return 0;
+                return -1;
         }
 
         if (!x2apic_preenabled && skip_ioapic_setup) {
                 pr_info("Skipped enabling intr-remap because of skipping "
                         "io-apic setup\n");
-                return 0;
+                return -1;
         }
 
-        if (enable_intr_remapping(x2apic_supported()))
-                return 0;
-
-        pr_info("Enabled Interrupt-remapping\n");
-
-        return 1;
-
+        return enable_intr_remapping();
 #endif
-        return 0;
+        return -1;
 }
 
 void __init enable_IR_x2apic(void)
@@ -1480,11 +1475,11 @@ void __init enable_IR_x2apic(void)
         mask_ioapic_entries();
 
         if (dmar_table_init_ret)
-                ret = 0;
+                ret = -1;
         else
                 ret = enable_IR();
 
-        if (!ret) {
+        if (ret < 0) {
                 /* IR is required if there is APIC ID > 255 even when running
                  * under KVM
                  */
@@ -1498,6 +1493,9 @@ void __init enable_IR_x2apic(void)
                 x2apic_force_phys();
         }
 
+        if (ret == IRQ_REMAP_XAPIC_MODE)
+                goto nox2apic;
+
         x2apic_enabled = 1;
 
         if (x2apic_supported() && !x2apic_mode) {
@@ -1507,19 +1505,21 @@ void __init enable_IR_x2apic(void)
         }
 
 nox2apic:
-        if (!ret) /* IR enabling failed */
+        if (ret < 0) /* IR enabling failed */
                 restore_ioapic_entries();
         legacy_pic->restore_mask();
         local_irq_restore(flags);
 
 out:
-        if (x2apic_enabled)
+        if (x2apic_enabled || !x2apic_supported())
                 return;
 
         if (x2apic_preenabled)
                 panic("x2apic: enabled by BIOS but kernel init failed.");
-        else if (cpu_has_x2apic)
-                pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
+        else if (ret == IRQ_REMAP_XAPIC_MODE)
+                pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
+        else if (ret < 0)
+                pr_info("x2apic not enabled, IRQ remapping init failed\n");
 }
 
 #ifdef CONFIG_X86_64
@@ -1943,10 +1943,28 @@ void disconnect_bsp_APIC(int virt_wire_setup)
 
 void __cpuinit generic_processor_info(int apicid, int version)
 {
-        int cpu;
+        int cpu, max = nr_cpu_ids;
+        bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
+                                phys_cpu_present_map);
+
+        /*
+         * If boot cpu has not been detected yet, then only allow upto
+         * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
+         */
+        if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
+            apicid != boot_cpu_physical_apicid) {
+                int thiscpu = max + disabled_cpus - 1;
+
+                pr_warning(
+                        "ACPI: NR_CPUS/possible_cpus limit of %i almost"
+                        " reached. Keeping one slot for boot cpu."
+                        "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
+
+                disabled_cpus++;
+                return;
+        }
 
         if (num_processors >= nr_cpu_ids) {
-                int max = nr_cpu_ids;
                 int thiscpu = max + disabled_cpus;
 
                 pr_warning(
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index efd737e827f..521bead0113 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -255,12 +255,24 @@ static struct apic apic_bigsmp = {
         .x86_32_early_logical_apicid    = bigsmp_early_logical_apicid,
 };
 
-struct apic * __init generic_bigsmp_probe(void)
+void __init generic_bigsmp_probe(void)
 {
-        if (probe_bigsmp())
-                return &apic_bigsmp;
+        unsigned int cpu;
 
-        return NULL;
+        if (!probe_bigsmp())
+                return;
+
+        apic = &apic_bigsmp;
+
+        for_each_possible_cpu(cpu) {
+                if (early_per_cpu(x86_cpu_to_logical_apicid,
+                                  cpu) == BAD_APICID)
+                        continue;
+                early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
+                        bigsmp_early_logical_apicid(cpu);
+        }
+
+        pr_info("Overriding APIC driver with %s\n", apic_bigsmp.name);
 }
 
 apic_driver(apic_bigsmp);
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index 9536b3fe43f..5d513bc47b6 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -48,7 +48,7 @@
 #include <linux/io.h>
 
 #include <asm/apicdef.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 #include <asm/fixmap.h>
 #include <asm/mpspec.h>
 #include <asm/setup.h>
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index e5293394b54..620da6fed6b 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1202,7 +1202,6 @@ void __setup_vector_irq(int cpu)
 }
 
 static struct irq_chip ioapic_chip;
-static struct irq_chip ir_ioapic_chip;
 
 #ifdef CONFIG_X86_32
 static inline int IO_APIC_irq_trigger(int irq)
@@ -1246,7 +1245,7 @@ static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
 
         if (irq_remapped(cfg)) {
                 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
-                chip = &ir_ioapic_chip;
+                irq_remap_modify_chip_defaults(chip);
                 fasteoi = trigger != 0;
         }
 
@@ -1295,6 +1294,16 @@ static int setup_ioapic_entry(int apic_id, int irq,
                  * irq handler will do the explicit EOI to the io-apic.
                  */
                 ir_entry->vector = pin;
+
+                apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
+                        "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
+                        "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
+                        "Avail:%X Vector:%02X Dest:%08X "
+                        "SID:%04X SQ:%X SVT:%X)\n",
+                        apic_id, irte.present, irte.fpd, irte.dst_mode,
+                        irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
+                        irte.avail, irte.vector, irte.dest_id,
+                        irte.sid, irte.sq, irte.svt);
         } else {
                 entry->delivery_mode = apic->irq_delivery_mode;
                 entry->dest_mode = apic->irq_dest_mode;
@@ -1337,9 +1346,9 @@ static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
 
         apic_printk(APIC_VERBOSE,KERN_DEBUG
                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
-                    "IRQ %d Mode:%i Active:%i)\n",
+                    "IRQ %d Mode:%i Active:%i Dest:%d)\n",
                     apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector,
-                    irq, trigger, polarity);
+                    irq, trigger, polarity, dest);
 
 
         if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry,
@@ -1522,10 +1531,12 @@ __apicdebuginit(void) print_IO_APIC(void)
         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
 
         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
-        printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
+        printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
+                reg_01.bits.entries);
 
         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
-        printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
+        printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
+                reg_01.bits.version);
 
         /*
          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
@@ -1550,31 +1561,60 @@ __apicdebuginit(void) print_IO_APIC(void)
 
         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 
-        printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
-                          " Stat Dmod Deli Vect:\n");
+        if (intr_remapping_enabled) {
+                printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
+                        " Pol Stat Indx2 Zero Vect:\n");
+        } else {
+                printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
+                        " Stat Dmod Deli Vect:\n");
+        }
 
         for (i = 0; i <= reg_01.bits.entries; i++) {
-                struct IO_APIC_route_entry entry;
-
-                entry = ioapic_read_entry(apic, i);
-
-                printk(KERN_DEBUG " %02x %03X ",
-                        i,
-                        entry.dest
-                );
+                if (intr_remapping_enabled) {
+                        struct IO_APIC_route_entry entry;
+                        struct IR_IO_APIC_route_entry *ir_entry;
+
+                        entry = ioapic_read_entry(apic, i);
+                        ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
+                        printk(KERN_DEBUG " %02x %04X ",
+                                i,
+                                ir_entry->index
+                        );
+                        printk("%1d   %1d    %1d    %1d   %1d   "
+                                "%1d    %1d     %X    %02X\n",
+                                ir_entry->format,
+                                ir_entry->mask,
+                                ir_entry->trigger,
+                                ir_entry->irr,
+                                ir_entry->polarity,
+                                ir_entry->delivery_status,
+                                ir_entry->index2,
+                                ir_entry->zero,
+                                ir_entry->vector
+                        );
+                } else {
+                        struct IO_APIC_route_entry entry;
 
-                printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
-                        entry.mask,
-                        entry.trigger,
-                        entry.irr,
-                        entry.polarity,
-                        entry.delivery_status,
-                        entry.dest_mode,
-                        entry.delivery_mode,
-                        entry.vector
-                );
+                        entry = ioapic_read_entry(apic, i);
+                        printk(KERN_DEBUG " %02x %02X  ",
+                                i,
+                                entry.dest
+                        );
+                        printk("%1d    %1d    %1d   %1d   %1d    "
+                                "%1d    %1d    %02X\n",
+                                entry.mask,
+                                entry.trigger,
+                                entry.irr,
+                                entry.polarity,
+                                entry.delivery_status,
+                                entry.dest_mode,
+                                entry.delivery_mode,
+                                entry.vector
+                        );
+                }
         }
         }
+
         printk(KERN_DEBUG "IRQ to pin mappings:\n");
         for_each_active_irq(irq) {
                 struct irq_pin_list *entry;
@@ -1792,7 +1832,7 @@ __apicdebuginit(int) print_ICs(void)
         return 0;
 }
 
-fs_initcall(print_ICs);
+late_initcall(print_ICs);
 
 
 /* Where if anywhere is the i8259 connect in external int mode */
@@ -2214,7 +2254,7 @@ ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
         return ret;
 }
 
-#ifdef CONFIG_INTR_REMAP
+#ifdef CONFIG_IRQ_REMAP
 
 /*
  * Migrate the IO-APIC irq in the presence of intr-remapping.
@@ -2226,6 +2266,9 @@ ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
  * updated vector information), by using a virtual vector (io-apic pin number).
  * Real vector that is used for interrupting cpu will be coming from
  * the interrupt-remapping table entry.
+ *
+ * As the migration is a simple atomic update of IRTE, the same mechanism
+ * is used to migrate MSI irq's in the presence of interrupt-remapping.
  */
 static int
 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
@@ -2250,10 +2293,16 @@ ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
         irte.dest_id = IRTE_DEST(dest);
 
         /*
-         * Modified the IRTE and flushes the Interrupt entry cache.
+         * Atomically updates the IRTE with the new destination, vector
+         * and flushes the interrupt entry cache.
          */
         modify_irte(irq, &irte);
 
+        /*
+         * After this point, all the interrupts will start arriving
+         * at the new destination. So, time to cleanup the previous
+         * vector allocation.
+         */
         if (cfg->move_in_progress)
                 send_cleanup_vector(cfg);
 
@@ -2511,7 +2560,7 @@ static void ack_apic_level(struct irq_data *data)
         }
 }
 
-#ifdef CONFIG_INTR_REMAP
+#ifdef CONFIG_IRQ_REMAP
 static void ir_ack_apic_edge(struct irq_data *data)
 {
         ack_APIC_irq();
@@ -2522,7 +2571,23 @@ static void ir_ack_apic_level(struct irq_data *data)
         ack_APIC_irq();
         eoi_ioapic_irq(data->irq, data->chip_data);
 }
-#endif /* CONFIG_INTR_REMAP */
+
+static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
+{
+        seq_printf(p, " IR-%s", data->chip->name);
+}
+
+static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
+{
+        chip->irq_print_chip = ir_print_prefix;
+        chip->irq_ack = ir_ack_apic_edge;
+        chip->irq_eoi = ir_ack_apic_level;
+
+#ifdef CONFIG_SMP
+        chip->irq_set_affinity = ir_ioapic_set_affinity;
+#endif
+}
+#endif /* CONFIG_IRQ_REMAP */
 
 static struct irq_chip ioapic_chip __read_mostly = {
         .name                   = "IO-APIC",
@@ -2537,21 +2602,6 @@ static struct irq_chip ioapic_chip __read_mostly = {
         .irq_retrigger          = ioapic_retrigger_irq,
 };
 
-static struct irq_chip ir_ioapic_chip __read_mostly = {
-        .name                   = "IR-IO-APIC",
-        .irq_startup            = startup_ioapic_irq,
-        .irq_mask               = mask_ioapic_irq,
-        .irq_unmask             = unmask_ioapic_irq,
-#ifdef CONFIG_INTR_REMAP
-        .irq_ack                = ir_ack_apic_edge,
-        .irq_eoi                = ir_ack_apic_level,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = ir_ioapic_set_affinity,
-#endif
-#endif
-        .irq_retrigger          = ioapic_retrigger_irq,
-};
-
 static inline void init_IO_APIC_traps(void)
 {
         struct irq_cfg *cfg;
@@ -3103,45 +3153,6 @@ msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
 
         return 0;
 }
-#ifdef CONFIG_INTR_REMAP
-/*
- * Migrate the MSI irq to another cpumask. This migration is
- * done in the process context using interrupt-remapping hardware.
- */
-static int
-ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
-                    bool force)
-{
-        struct irq_cfg *cfg = data->chip_data;
-        unsigned int dest, irq = data->irq;
-        struct irte irte;
-
-        if (get_irte(irq, &irte))
-                return -1;
-
-        if (__ioapic_set_affinity(data, mask, &dest))
-                return -1;
-
-        irte.vector = cfg->vector;
-        irte.dest_id = IRTE_DEST(dest);
-
-        /*
-         * atomically update the IRTE with the new destination and vector.
-         */
-        modify_irte(irq, &irte);
-
-        /*
-         * After this point, all the interrupts will start arriving
-         * at the new destination. So, time to cleanup the previous
-         * vector allocation.
-         */
-        if (cfg->move_in_progress)
-                send_cleanup_vector(cfg);
-
-        return 0;
-}
-
-#endif
 #endif /* CONFIG_SMP */
 
 /*
@@ -3159,19 +3170,6 @@ static struct irq_chip msi_chip = {
         .irq_retrigger          = ioapic_retrigger_irq,
 };
 
-static struct irq_chip msi_ir_chip = {
-        .name                   = "IR-PCI-MSI",
-        .irq_unmask             = unmask_msi_irq,
-        .irq_mask               = mask_msi_irq,
-#ifdef CONFIG_INTR_REMAP
-        .irq_ack                = ir_ack_apic_edge,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = ir_msi_set_affinity,
-#endif
-#endif
-        .irq_retrigger          = ioapic_retrigger_irq,
-};
-
 /*
  * Map the PCI dev to the corresponding remapping hardware unit
  * and allocate 'nvec' consecutive interrupt-remapping table entries
@@ -3214,7 +3212,7 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
 
         if (irq_remapped(irq_get_chip_data(irq))) {
                 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
-                chip = &msi_ir_chip;
+                irq_remap_modify_chip_defaults(chip);
         }
 
         irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
@@ -3287,7 +3285,7 @@ void native_teardown_msi_irq(unsigned int irq)
         destroy_irq(irq);
 }
 
-#if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
+#ifdef CONFIG_DMAR_TABLE
 #ifdef CONFIG_SMP
 static int
 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
@@ -3368,19 +3366,6 @@ static int hpet_msi_set_affinity(struct irq_data *data,
 
 #endif /* CONFIG_SMP */
 
-static struct irq_chip ir_hpet_msi_type = {
-        .name                   = "IR-HPET_MSI",
-        .irq_unmask             = hpet_msi_unmask,
-        .irq_mask               = hpet_msi_mask,
-#ifdef CONFIG_INTR_REMAP
-        .irq_ack                = ir_ack_apic_edge,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = ir_msi_set_affinity,
-#endif
-#endif
-        .irq_retrigger          = ioapic_retrigger_irq,
-};
-
 static struct irq_chip hpet_msi_type = {
         .name = "HPET_MSI",
         .irq_unmask = hpet_msi_unmask,
@@ -3417,7 +3402,7 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
         hpet_msi_write(irq_get_handler_data(irq), &msg);
         irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
         if (irq_remapped(irq_get_chip_data(irq)))
-                chip = &ir_hpet_msi_type;
+                irq_remap_modify_chip_defaults(chip);
 
         irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
         return 0;
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index b5254ad044a..0787bb3412f 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -200,14 +200,8 @@ void __init default_setup_apic_routing(void)
          * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
          */
 
-        if (!cmdline_apic && apic == &apic_default) {
-                struct apic *bigsmp = generic_bigsmp_probe();
-                if (bigsmp) {
-                        apic = bigsmp;
-                        printk(KERN_INFO "Overriding APIC driver with %s\n",
-                               apic->name);
-                }
-        }
+        if (!cmdline_apic && apic == &apic_default)
+                generic_bigsmp_probe();
 #endif
 
         if (apic->setup_apic_routing)
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index adc66c3a1fe..cfeb978f49f 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -207,7 +207,6 @@ static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_ri
             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
             APIC_DM_INIT;
         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
-        mdelay(10);
 
         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
@@ -833,6 +832,10 @@ void __init uv_system_init(void)
                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
                 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
 
+                uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
+                uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ?
+                                (m_val == 40 ? 40 : 39) : m_val;
+
                 pnode = uv_apicid_to_pnode(apicid);
                 blade = boot_pnode_to_blade(pnode);
                 lcpu = uv_blade_info[blade].nr_possible_cpus;
@@ -863,8 +866,7 @@ void __init uv_system_init(void)
                 if (uv_node_to_blade[nid] >= 0)
                         continue;
                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
-                paddr = uv_soc_phys_ram_to_gpa(paddr);
-                pnode = (paddr >> m_val) & pnode_mask;
+                pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
                 blade = boot_pnode_to_blade(pnode);
                 uv_node_to_blade[nid] = blade;
         }