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-rw-r--r--arch/x86/include/asm/processor.h940
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diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
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1#ifndef _ASM_X86_PROCESSOR_H
2#define _ASM_X86_PROCESSOR_H
3
4#include <asm/processor-flags.h>
5
6/* Forward declaration, a strange C thing */
7struct task_struct;
8struct mm_struct;
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/types.h>
14#include <asm/sigcontext.h>
15#include <asm/current.h>
16#include <asm/cpufeature.h>
17#include <asm/system.h>
18#include <asm/page.h>
19#include <asm/percpu.h>
20#include <asm/msr.h>
21#include <asm/desc_defs.h>
22#include <asm/nops.h>
23#include <asm/ds.h>
24
25#include <linux/personality.h>
26#include <linux/cpumask.h>
27#include <linux/cache.h>
28#include <linux/threads.h>
29#include <linux/init.h>
30
31/*
32 * Default implementation of macro that returns current
33 * instruction pointer ("program counter").
34 */
35static inline void *current_text_addr(void)
36{
37 void *pc;
38
39 asm volatile("mov $1f, %0; 1:":"=r" (pc));
40
41 return pc;
42}
43
44#ifdef CONFIG_X86_VSMP
45# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
46# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
47#else
48# define ARCH_MIN_TASKALIGN 16
49# define ARCH_MIN_MMSTRUCT_ALIGN 0
50#endif
51
52/*
53 * CPU type and hardware bug flags. Kept separately for each CPU.
54 * Members of this structure are referenced in head.S, so think twice
55 * before touching them. [mj]
56 */
57
58struct cpuinfo_x86 {
59 __u8 x86; /* CPU family */
60 __u8 x86_vendor; /* CPU vendor */
61 __u8 x86_model;
62 __u8 x86_mask;
63#ifdef CONFIG_X86_32
64 char wp_works_ok; /* It doesn't on 386's */
65
66 /* Problems on some 486Dx4's and old 386's: */
67 char hlt_works_ok;
68 char hard_math;
69 char rfu;
70 char fdiv_bug;
71 char f00f_bug;
72 char coma_bug;
73 char pad0;
74#else
75 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
76 int x86_tlbsize;
77 __u8 x86_virt_bits;
78 __u8 x86_phys_bits;
79#endif
80 /* CPUID returned core id bits: */
81 __u8 x86_coreid_bits;
82 /* Max extended CPUID function supported: */
83 __u32 extended_cpuid_level;
84 /* Maximum supported CPUID level, -1=no CPUID: */
85 int cpuid_level;
86 __u32 x86_capability[NCAPINTS];
87 char x86_vendor_id[16];
88 char x86_model_id[64];
89 /* in KB - valid for CPUS which support this call: */
90 int x86_cache_size;
91 int x86_cache_alignment; /* In bytes */
92 int x86_power;
93 unsigned long loops_per_jiffy;
94#ifdef CONFIG_SMP
95 /* cpus sharing the last level cache: */
96 cpumask_t llc_shared_map;
97#endif
98 /* cpuid returned max cores value: */
99 u16 x86_max_cores;
100 u16 apicid;
101 u16 initial_apicid;
102 u16 x86_clflush_size;
103#ifdef CONFIG_SMP
104 /* number of cores as seen by the OS: */
105 u16 booted_cores;
106 /* Physical processor id: */
107 u16 phys_proc_id;
108 /* Core id: */
109 u16 cpu_core_id;
110 /* Index into per_cpu list: */
111 u16 cpu_index;
112#endif
113 unsigned int x86_hyper_vendor;
114} __attribute__((__aligned__(SMP_CACHE_BYTES)));
115
116#define X86_VENDOR_INTEL 0
117#define X86_VENDOR_CYRIX 1
118#define X86_VENDOR_AMD 2
119#define X86_VENDOR_UMC 3
120#define X86_VENDOR_CENTAUR 5
121#define X86_VENDOR_TRANSMETA 7
122#define X86_VENDOR_NSC 8
123#define X86_VENDOR_NUM 9
124
125#define X86_VENDOR_UNKNOWN 0xff
126
127#define X86_HYPER_VENDOR_NONE 0
128#define X86_HYPER_VENDOR_VMWARE 1
129
130/*
131 * capabilities of CPUs
132 */
133extern struct cpuinfo_x86 boot_cpu_data;
134extern struct cpuinfo_x86 new_cpu_data;
135
136extern struct tss_struct doublefault_tss;
137extern __u32 cleared_cpu_caps[NCAPINTS];
138
139#ifdef CONFIG_SMP
140DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
141#define cpu_data(cpu) per_cpu(cpu_info, cpu)
142#define current_cpu_data __get_cpu_var(cpu_info)
143#else
144#define cpu_data(cpu) boot_cpu_data
145#define current_cpu_data boot_cpu_data
146#endif
147
148extern const struct seq_operations cpuinfo_op;
149
150static inline int hlt_works(int cpu)
151{
152#ifdef CONFIG_X86_32
153 return cpu_data(cpu).hlt_works_ok;
154#else
155 return 1;
156#endif
157}
158
159#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
160
161extern void cpu_detect(struct cpuinfo_x86 *c);
162
163extern struct pt_regs *idle_regs(struct pt_regs *);
164
165extern void early_cpu_init(void);
166extern void identify_boot_cpu(void);
167extern void identify_secondary_cpu(struct cpuinfo_x86 *);
168extern void print_cpu_info(struct cpuinfo_x86 *);
169extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
170extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
171extern unsigned short num_cache_leaves;
172
173extern void detect_extended_topology(struct cpuinfo_x86 *c);
174extern void detect_ht(struct cpuinfo_x86 *c);
175
176static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
177 unsigned int *ecx, unsigned int *edx)
178{
179 /* ecx is often an input as well as an output. */
180 asm("cpuid"
181 : "=a" (*eax),
182 "=b" (*ebx),
183 "=c" (*ecx),
184 "=d" (*edx)
185 : "0" (*eax), "2" (*ecx));
186}
187
188static inline void load_cr3(pgd_t *pgdir)
189{
190 write_cr3(__pa(pgdir));
191}
192
193#ifdef CONFIG_X86_32
194/* This is the TSS defined by the hardware. */
195struct x86_hw_tss {
196 unsigned short back_link, __blh;
197 unsigned long sp0;
198 unsigned short ss0, __ss0h;
199 unsigned long sp1;
200 /* ss1 caches MSR_IA32_SYSENTER_CS: */
201 unsigned short ss1, __ss1h;
202 unsigned long sp2;
203 unsigned short ss2, __ss2h;
204 unsigned long __cr3;
205 unsigned long ip;
206 unsigned long flags;
207 unsigned long ax;
208 unsigned long cx;
209 unsigned long dx;
210 unsigned long bx;
211 unsigned long sp;
212 unsigned long bp;
213 unsigned long si;
214 unsigned long di;
215 unsigned short es, __esh;
216 unsigned short cs, __csh;
217 unsigned short ss, __ssh;
218 unsigned short ds, __dsh;
219 unsigned short fs, __fsh;
220 unsigned short gs, __gsh;
221 unsigned short ldt, __ldth;
222 unsigned short trace;
223 unsigned short io_bitmap_base;
224
225} __attribute__((packed));
226#else
227struct x86_hw_tss {
228 u32 reserved1;
229 u64 sp0;
230 u64 sp1;
231 u64 sp2;
232 u64 reserved2;
233 u64 ist[7];
234 u32 reserved3;
235 u32 reserved4;
236 u16 reserved5;
237 u16 io_bitmap_base;
238
239} __attribute__((packed)) ____cacheline_aligned;
240#endif
241
242/*
243 * IO-bitmap sizes:
244 */
245#define IO_BITMAP_BITS 65536
246#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
247#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
248#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
249#define INVALID_IO_BITMAP_OFFSET 0x8000
250#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
251
252struct tss_struct {
253 /*
254 * The hardware state:
255 */
256 struct x86_hw_tss x86_tss;
257
258 /*
259 * The extra 1 is there because the CPU will access an
260 * additional byte beyond the end of the IO permission
261 * bitmap. The extra byte must be all 1 bits, and must
262 * be within the limit.
263 */
264 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
265 /*
266 * Cache the current maximum and the last task that used the bitmap:
267 */
268 unsigned long io_bitmap_max;
269 struct thread_struct *io_bitmap_owner;
270
271 /*
272 * .. and then another 0x100 bytes for the emergency kernel stack:
273 */
274 unsigned long stack[64];
275
276} ____cacheline_aligned;
277
278DECLARE_PER_CPU(struct tss_struct, init_tss);
279
280/*
281 * Save the original ist values for checking stack pointers during debugging
282 */
283struct orig_ist {
284 unsigned long ist[7];
285};
286
287#define MXCSR_DEFAULT 0x1f80
288
289struct i387_fsave_struct {
290 u32 cwd; /* FPU Control Word */
291 u32 swd; /* FPU Status Word */
292 u32 twd; /* FPU Tag Word */
293 u32 fip; /* FPU IP Offset */
294 u32 fcs; /* FPU IP Selector */
295 u32 foo; /* FPU Operand Pointer Offset */
296 u32 fos; /* FPU Operand Pointer Selector */
297
298 /* 8*10 bytes for each FP-reg = 80 bytes: */
299 u32 st_space[20];
300
301 /* Software status information [not touched by FSAVE ]: */
302 u32 status;
303};
304
305struct i387_fxsave_struct {
306 u16 cwd; /* Control Word */
307 u16 swd; /* Status Word */
308 u16 twd; /* Tag Word */
309 u16 fop; /* Last Instruction Opcode */
310 union {
311 struct {
312 u64 rip; /* Instruction Pointer */
313 u64 rdp; /* Data Pointer */
314 };
315 struct {
316 u32 fip; /* FPU IP Offset */
317 u32 fcs; /* FPU IP Selector */
318 u32 foo; /* FPU Operand Offset */
319 u32 fos; /* FPU Operand Selector */
320 };
321 };
322 u32 mxcsr; /* MXCSR Register State */
323 u32 mxcsr_mask; /* MXCSR Mask */
324
325 /* 8*16 bytes for each FP-reg = 128 bytes: */
326 u32 st_space[32];
327
328 /* 16*16 bytes for each XMM-reg = 256 bytes: */
329 u32 xmm_space[64];
330
331 u32 padding[12];
332
333 union {
334 u32 padding1[12];
335 u32 sw_reserved[12];
336 };
337
338} __attribute__((aligned(16)));
339
340struct i387_soft_struct {
341 u32 cwd;
342 u32 swd;
343 u32 twd;
344 u32 fip;
345 u32 fcs;
346 u32 foo;
347 u32 fos;
348 /* 8*10 bytes for each FP-reg = 80 bytes: */
349 u32 st_space[20];
350 u8 ftop;
351 u8 changed;
352 u8 lookahead;
353 u8 no_update;
354 u8 rm;
355 u8 alimit;
356 struct info *info;
357 u32 entry_eip;
358};
359
360struct xsave_hdr_struct {
361 u64 xstate_bv;
362 u64 reserved1[2];
363 u64 reserved2[5];
364} __attribute__((packed));
365
366struct xsave_struct {
367 struct i387_fxsave_struct i387;
368 struct xsave_hdr_struct xsave_hdr;
369 /* new processor state extensions will go here */
370} __attribute__ ((packed, aligned (64)));
371
372union thread_xstate {
373 struct i387_fsave_struct fsave;
374 struct i387_fxsave_struct fxsave;
375 struct i387_soft_struct soft;
376 struct xsave_struct xsave;
377};
378
379#ifdef CONFIG_X86_64
380DECLARE_PER_CPU(struct orig_ist, orig_ist);
381#endif
382
383extern void print_cpu_info(struct cpuinfo_x86 *);
384extern unsigned int xstate_size;
385extern void free_thread_xstate(struct task_struct *);
386extern struct kmem_cache *task_xstate_cachep;
387extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
388extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
389extern unsigned short num_cache_leaves;
390
391struct thread_struct {
392 /* Cached TLS descriptors: */
393 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
394 unsigned long sp0;
395 unsigned long sp;
396#ifdef CONFIG_X86_32
397 unsigned long sysenter_cs;
398#else
399 unsigned long usersp; /* Copy from PDA */
400 unsigned short es;
401 unsigned short ds;
402 unsigned short fsindex;
403 unsigned short gsindex;
404#endif
405 unsigned long ip;
406 unsigned long fs;
407 unsigned long gs;
408 /* Hardware debugging registers: */
409 unsigned long debugreg0;
410 unsigned long debugreg1;
411 unsigned long debugreg2;
412 unsigned long debugreg3;
413 unsigned long debugreg6;
414 unsigned long debugreg7;
415 /* Fault info: */
416 unsigned long cr2;
417 unsigned long trap_no;
418 unsigned long error_code;
419 /* floating point and extended processor state */
420 union thread_xstate *xstate;
421#ifdef CONFIG_X86_32
422 /* Virtual 86 mode info */
423 struct vm86_struct __user *vm86_info;
424 unsigned long screen_bitmap;
425 unsigned long v86flags;
426 unsigned long v86mask;
427 unsigned long saved_sp0;
428 unsigned int saved_fs;
429 unsigned int saved_gs;
430#endif
431 /* IO permissions: */
432 unsigned long *io_bitmap_ptr;
433 unsigned long iopl;
434 /* Max allowed port in the bitmap, in bytes: */
435 unsigned io_bitmap_max;
436/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
437 unsigned long debugctlmsr;
438#ifdef CONFIG_X86_DS
439/* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
440 struct ds_context *ds_ctx;
441#endif /* CONFIG_X86_DS */
442#ifdef CONFIG_X86_PTRACE_BTS
443/* the signal to send on a bts buffer overflow */
444 unsigned int bts_ovfl_signal;
445#endif /* CONFIG_X86_PTRACE_BTS */
446};
447
448static inline unsigned long native_get_debugreg(int regno)
449{
450 unsigned long val = 0; /* Damn you, gcc! */
451
452 switch (regno) {
453 case 0:
454 asm("mov %%db0, %0" :"=r" (val));
455 break;
456 case 1:
457 asm("mov %%db1, %0" :"=r" (val));
458 break;
459 case 2:
460 asm("mov %%db2, %0" :"=r" (val));
461 break;
462 case 3:
463 asm("mov %%db3, %0" :"=r" (val));
464 break;
465 case 6:
466 asm("mov %%db6, %0" :"=r" (val));
467 break;
468 case 7:
469 asm("mov %%db7, %0" :"=r" (val));
470 break;
471 default:
472 BUG();
473 }
474 return val;
475}
476
477static inline void native_set_debugreg(int regno, unsigned long value)
478{
479 switch (regno) {
480 case 0:
481 asm("mov %0, %%db0" ::"r" (value));
482 break;
483 case 1:
484 asm("mov %0, %%db1" ::"r" (value));
485 break;
486 case 2:
487 asm("mov %0, %%db2" ::"r" (value));
488 break;
489 case 3:
490 asm("mov %0, %%db3" ::"r" (value));
491 break;
492 case 6:
493 asm("mov %0, %%db6" ::"r" (value));
494 break;
495 case 7:
496 asm("mov %0, %%db7" ::"r" (value));
497 break;
498 default:
499 BUG();
500 }
501}
502
503/*
504 * Set IOPL bits in EFLAGS from given mask
505 */
506static inline void native_set_iopl_mask(unsigned mask)
507{
508#ifdef CONFIG_X86_32
509 unsigned int reg;
510
511 asm volatile ("pushfl;"
512 "popl %0;"
513 "andl %1, %0;"
514 "orl %2, %0;"
515 "pushl %0;"
516 "popfl"
517 : "=&r" (reg)
518 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
519#endif
520}
521
522static inline void
523native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
524{
525 tss->x86_tss.sp0 = thread->sp0;
526#ifdef CONFIG_X86_32
527 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
528 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
529 tss->x86_tss.ss1 = thread->sysenter_cs;
530 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
531 }
532#endif
533}
534
535static inline void native_swapgs(void)
536{
537#ifdef CONFIG_X86_64
538 asm volatile("swapgs" ::: "memory");
539#endif
540}
541
542#ifdef CONFIG_PARAVIRT
543#include <asm/paravirt.h>
544#else
545#define __cpuid native_cpuid
546#define paravirt_enabled() 0
547
548/*
549 * These special macros can be used to get or set a debugging register
550 */
551#define get_debugreg(var, register) \
552 (var) = native_get_debugreg(register)
553#define set_debugreg(value, register) \
554 native_set_debugreg(register, value)
555
556static inline void load_sp0(struct tss_struct *tss,
557 struct thread_struct *thread)
558{
559 native_load_sp0(tss, thread);
560}
561
562#define set_iopl_mask native_set_iopl_mask
563#endif /* CONFIG_PARAVIRT */
564
565/*
566 * Save the cr4 feature set we're using (ie
567 * Pentium 4MB enable and PPro Global page
568 * enable), so that any CPU's that boot up
569 * after us can get the correct flags.
570 */
571extern unsigned long mmu_cr4_features;
572
573static inline void set_in_cr4(unsigned long mask)
574{
575 unsigned cr4;
576
577 mmu_cr4_features |= mask;
578 cr4 = read_cr4();
579 cr4 |= mask;
580 write_cr4(cr4);
581}
582
583static inline void clear_in_cr4(unsigned long mask)
584{
585 unsigned cr4;
586
587 mmu_cr4_features &= ~mask;
588 cr4 = read_cr4();
589 cr4 &= ~mask;
590 write_cr4(cr4);
591}
592
593typedef struct {
594 unsigned long seg;
595} mm_segment_t;
596
597
598/*
599 * create a kernel thread without removing it from tasklists
600 */
601extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
602
603/* Free all resources held by a thread. */
604extern void release_thread(struct task_struct *);
605
606/* Prepare to copy thread state - unlazy all lazy state */
607extern void prepare_to_copy(struct task_struct *tsk);
608
609unsigned long get_wchan(struct task_struct *p);
610
611/*
612 * Generic CPUID function
613 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
614 * resulting in stale register contents being returned.
615 */
616static inline void cpuid(unsigned int op,
617 unsigned int *eax, unsigned int *ebx,
618 unsigned int *ecx, unsigned int *edx)
619{
620 *eax = op;
621 *ecx = 0;
622 __cpuid(eax, ebx, ecx, edx);
623}
624
625/* Some CPUID calls want 'count' to be placed in ecx */
626static inline void cpuid_count(unsigned int op, int count,
627 unsigned int *eax, unsigned int *ebx,
628 unsigned int *ecx, unsigned int *edx)
629{
630 *eax = op;
631 *ecx = count;
632 __cpuid(eax, ebx, ecx, edx);
633}
634
635/*
636 * CPUID functions returning a single datum
637 */
638static inline unsigned int cpuid_eax(unsigned int op)
639{
640 unsigned int eax, ebx, ecx, edx;
641
642 cpuid(op, &eax, &ebx, &ecx, &edx);
643
644 return eax;
645}
646
647static inline unsigned int cpuid_ebx(unsigned int op)
648{
649 unsigned int eax, ebx, ecx, edx;
650
651 cpuid(op, &eax, &ebx, &ecx, &edx);
652
653 return ebx;
654}
655
656static inline unsigned int cpuid_ecx(unsigned int op)
657{
658 unsigned int eax, ebx, ecx, edx;
659
660 cpuid(op, &eax, &ebx, &ecx, &edx);
661
662 return ecx;
663}
664
665static inline unsigned int cpuid_edx(unsigned int op)
666{
667 unsigned int eax, ebx, ecx, edx;
668
669 cpuid(op, &eax, &ebx, &ecx, &edx);
670
671 return edx;
672}
673
674/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
675static inline void rep_nop(void)
676{
677 asm volatile("rep; nop" ::: "memory");
678}
679
680static inline void cpu_relax(void)
681{
682 rep_nop();
683}
684
685/* Stop speculative execution: */
686static inline void sync_core(void)
687{
688 int tmp;
689
690 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
691 : "ebx", "ecx", "edx", "memory");
692}
693
694static inline void __monitor(const void *eax, unsigned long ecx,
695 unsigned long edx)
696{
697 /* "monitor %eax, %ecx, %edx;" */
698 asm volatile(".byte 0x0f, 0x01, 0xc8;"
699 :: "a" (eax), "c" (ecx), "d"(edx));
700}
701
702static inline void __mwait(unsigned long eax, unsigned long ecx)
703{
704 /* "mwait %eax, %ecx;" */
705 asm volatile(".byte 0x0f, 0x01, 0xc9;"
706 :: "a" (eax), "c" (ecx));
707}
708
709static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
710{
711 trace_hardirqs_on();
712 /* "mwait %eax, %ecx;" */
713 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
714 :: "a" (eax), "c" (ecx));
715}
716
717extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
718
719extern void select_idle_routine(const struct cpuinfo_x86 *c);
720
721extern unsigned long boot_option_idle_override;
722extern unsigned long idle_halt;
723extern unsigned long idle_nomwait;
724
725/*
726 * on systems with caches, caches must be flashed as the absolute
727 * last instruction before going into a suspended halt. Otherwise,
728 * dirty data can linger in the cache and become stale on resume,
729 * leading to strange errors.
730 *
731 * perform a variety of operations to guarantee that the compiler
732 * will not reorder instructions. wbinvd itself is serializing
733 * so the processor will not reorder.
734 *
735 * Systems without cache can just go into halt.
736 */
737static inline void wbinvd_halt(void)
738{
739 mb();
740 /* check for clflush to determine if wbinvd is legal */
741 if (cpu_has_clflush)
742 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
743 else
744 while (1)
745 halt();
746}
747
748extern void enable_sep_cpu(void);
749extern int sysenter_setup(void);
750
751/* Defined in head.S */
752extern struct desc_ptr early_gdt_descr;
753
754extern void cpu_set_gdt(int);
755extern void switch_to_new_gdt(void);
756extern void cpu_init(void);
757extern void init_gdt(int cpu);
758
759static inline void update_debugctlmsr(unsigned long debugctlmsr)
760{
761#ifndef CONFIG_X86_DEBUGCTLMSR
762 if (boot_cpu_data.x86 < 6)
763 return;
764#endif
765 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
766}
767
768/*
769 * from system description table in BIOS. Mostly for MCA use, but
770 * others may find it useful:
771 */
772extern unsigned int machine_id;
773extern unsigned int machine_submodel_id;
774extern unsigned int BIOS_revision;
775
776/* Boot loader type from the setup header: */
777extern int bootloader_type;
778
779extern char ignore_fpu_irq;
780
781#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
782#define ARCH_HAS_PREFETCHW
783#define ARCH_HAS_SPINLOCK_PREFETCH
784
785#ifdef CONFIG_X86_32
786# define BASE_PREFETCH ASM_NOP4
787# define ARCH_HAS_PREFETCH
788#else
789# define BASE_PREFETCH "prefetcht0 (%1)"
790#endif
791
792/*
793 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
794 *
795 * It's not worth to care about 3dnow prefetches for the K6
796 * because they are microcoded there and very slow.
797 */
798static inline void prefetch(const void *x)
799{
800 alternative_input(BASE_PREFETCH,
801 "prefetchnta (%1)",
802 X86_FEATURE_XMM,
803 "r" (x));
804}
805
806/*
807 * 3dnow prefetch to get an exclusive cache line.
808 * Useful for spinlocks to avoid one state transition in the
809 * cache coherency protocol:
810 */
811static inline void prefetchw(const void *x)
812{
813 alternative_input(BASE_PREFETCH,
814 "prefetchw (%1)",
815 X86_FEATURE_3DNOW,
816 "r" (x));
817}
818
819static inline void spin_lock_prefetch(const void *x)
820{
821 prefetchw(x);
822}
823
824#ifdef CONFIG_X86_32
825/*
826 * User space process size: 3GB (default).
827 */
828#define TASK_SIZE PAGE_OFFSET
829#define STACK_TOP TASK_SIZE
830#define STACK_TOP_MAX STACK_TOP
831
832#define INIT_THREAD { \
833 .sp0 = sizeof(init_stack) + (long)&init_stack, \
834 .vm86_info = NULL, \
835 .sysenter_cs = __KERNEL_CS, \
836 .io_bitmap_ptr = NULL, \
837 .fs = __KERNEL_PERCPU, \
838}
839
840/*
841 * Note that the .io_bitmap member must be extra-big. This is because
842 * the CPU will access an additional byte beyond the end of the IO
843 * permission bitmap. The extra byte must be all 1 bits, and must
844 * be within the limit.
845 */
846#define INIT_TSS { \
847 .x86_tss = { \
848 .sp0 = sizeof(init_stack) + (long)&init_stack, \
849 .ss0 = __KERNEL_DS, \
850 .ss1 = __KERNEL_CS, \
851 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
852 }, \
853 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
854}
855
856extern unsigned long thread_saved_pc(struct task_struct *tsk);
857
858#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
859#define KSTK_TOP(info) \
860({ \
861 unsigned long *__ptr = (unsigned long *)(info); \
862 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
863})
864
865/*
866 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
867 * This is necessary to guarantee that the entire "struct pt_regs"
868 * is accessable even if the CPU haven't stored the SS/ESP registers
869 * on the stack (interrupt gate does not save these registers
870 * when switching to the same priv ring).
871 * Therefore beware: accessing the ss/esp fields of the
872 * "struct pt_regs" is possible, but they may contain the
873 * completely wrong values.
874 */
875#define task_pt_regs(task) \
876({ \
877 struct pt_regs *__regs__; \
878 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
879 __regs__ - 1; \
880})
881
882#define KSTK_ESP(task) (task_pt_regs(task)->sp)
883
884#else
885/*
886 * User space process size. 47bits minus one guard page.
887 */
888#define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
889
890/* This decides where the kernel will search for a free chunk of vm
891 * space during mmap's.
892 */
893#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
894 0xc0000000 : 0xFFFFe000)
895
896#define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
897 IA32_PAGE_OFFSET : TASK_SIZE64)
898#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
899 IA32_PAGE_OFFSET : TASK_SIZE64)
900
901#define STACK_TOP TASK_SIZE
902#define STACK_TOP_MAX TASK_SIZE64
903
904#define INIT_THREAD { \
905 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
906}
907
908#define INIT_TSS { \
909 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
910}
911
912/*
913 * Return saved PC of a blocked thread.
914 * What is this good for? it will be always the scheduler or ret_from_fork.
915 */
916#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
917
918#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
919#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
920#endif /* CONFIG_X86_64 */
921
922extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
923 unsigned long new_sp);
924
925/*
926 * This decides where the kernel will search for a free chunk of vm
927 * space during mmap's.
928 */
929#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
930
931#define KSTK_EIP(task) (task_pt_regs(task)->ip)
932
933/* Get/set a process' ability to use the timestamp counter instruction */
934#define GET_TSC_CTL(adr) get_tsc_mode((adr))
935#define SET_TSC_CTL(val) set_tsc_mode((val))
936
937extern int get_tsc_mode(unsigned long adr);
938extern int set_tsc_mode(unsigned int val);
939
940#endif /* _ASM_X86_PROCESSOR_H */
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