7 files changed, 57 insertions, 48 deletions

diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
index 61ebe7411ce..cc0006dc5d4 100644
--- a/arch/sparc/include/asm/asi.h
+++ b/arch/sparc/include/asm/asi.h
@@ -141,7 +141,8 @@
 /* SpitFire and later extended ASIs.  The "(III)" marker designates
  * UltraSparc-III and later specific ASIs.  The "(CMT)" marker designates
  * Chip Multi Threading specific ASIs.  "(NG)" designates Niagara specific
- * ASIs, "(4V)" designates SUN4V specific ASIs.
+ * ASIs, "(4V)" designates SUN4V specific ASIs.  "(NG4)" designates SPARC-T4
+ * and later ASIs.
  */
 #define ASI_PHYS_USE_EC         0x14 /* PADDR, E-cachable               */
 #define ASI_PHYS_BYPASS_EC_E    0x15 /* PADDR, E-bit                    */
@@ -243,6 +244,7 @@
 #define ASI_UDBL_CONTROL_R      0x7f /* External UDB control regs rd low*/
 #define ASI_INTR_R              0x7f /* IRQ vector dispatch read        */
 #define ASI_INTR_DATAN_R        0x7f /* (III) In irq vector data reg N  */
+#define ASI_PIC                 0xb0 /* (NG4) PIC registers             */
 #define ASI_PST8_P              0xc0 /* Primary, 8 8-bit, partial       */
 #define ASI_PST8_S              0xc1 /* Secondary, 8 8-bit, partial     */
 #define ASI_PST16_P             0xc2 /* Primary, 4 16-bit, partial      */
diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
index 7df8b7f544d..370ca1e71ff 100644
--- a/arch/sparc/include/asm/elf_64.h
+++ b/arch/sparc/include/asm/elf_64.h
@@ -86,6 +86,15 @@
 #define AV_SPARC_IMA            0x00400000 /* integer multiply-add */
 #define AV_SPARC_ASI_CACHE_SPARING \
                                 0x00800000 /* cache sparing ASIs available */
+#define AV_SPARC_PAUSE          0x01000000 /* PAUSE available */
+#define AV_SPARC_CBCOND         0x02000000 /* CBCOND insns available */
+
+/* Solaris decided to enumerate every single crypto instruction type
+ * in the AT_HWCAP bits.  This is wasteful, since if crypto is present,
+ * you still need to look in the CFR register to see if the opcode is
+ * really available.  So we simply advertise only "crypto" support.
+ */
+#define HWCAP_SPARC_CRYPTO      0x04000000 /* CRYPTO insns available */
 
 #define CORE_DUMP_USE_REGSET
 
diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h
index 015a761eaa3..ca121f0fa3e 100644
--- a/arch/sparc/include/asm/hypervisor.h
+++ b/arch/sparc/include/asm/hypervisor.h
@@ -2934,6 +2934,16 @@ extern unsigned long sun4v_reboot_data_set(unsigned long ra,
                                            unsigned long len);
 #endif
 
+#define HV_FAST_VT_GET_PERFREG          0x184
+#define HV_FAST_VT_SET_PERFREG          0x185
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_vt_get_perfreg(unsigned long reg_num,
+                                          unsigned long *reg_val);
+extern unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
+                                          unsigned long reg_val);
+#endif
+
 /* Function numbers for HV_CORE_TRAP.  */
 #define HV_CORE_SET_VER                 0x00
 #define HV_CORE_PUTCHAR                 0x01
@@ -2964,6 +2974,7 @@ extern unsigned long sun4v_reboot_data_set(unsigned long ra,
 #define HV_GRP_NIU                      0x0204
 #define HV_GRP_VF_CPU                   0x0205
 #define HV_GRP_KT_CPU                   0x0209
+#define HV_GRP_VT_CPU                   0x020c
 #define HV_GRP_DIAG                     0x0300
 
 #ifndef __ASSEMBLY__
diff --git a/arch/sparc/include/asm/mdesc.h b/arch/sparc/include/asm/mdesc.h
index 9faa046713f..139097f3a67 100644
--- a/arch/sparc/include/asm/mdesc.h
+++ b/arch/sparc/include/asm/mdesc.h
@@ -73,6 +73,7 @@ extern void mdesc_register_notifier(struct mdesc_notifier_client *client);
 
 extern void mdesc_fill_in_cpu_data(cpumask_t *mask);
 extern void mdesc_populate_present_mask(cpumask_t *mask);
+extern void mdesc_get_page_sizes(cpumask_t *mask, unsigned long *pgsz_mask);
 
 extern void sun4v_mdesc_init(void);
 
diff --git a/arch/sparc/include/asm/pcr.h b/arch/sparc/include/asm/pcr.h
index 288d7beba05..942bb17f60c 100644
--- a/arch/sparc/include/asm/pcr.h
+++ b/arch/sparc/include/asm/pcr.h
@@ -2,8 +2,13 @@
 #define __PCR_H
 
 struct pcr_ops {
-        u64 (*read)(void);
-        void (*write)(u64);
+        u64 (*read_pcr)(unsigned long);
+        void (*write_pcr)(unsigned long, u64);
+        u64 (*read_pic)(unsigned long);
+        void (*write_pic)(unsigned long, u64);
+        u64 (*nmi_picl_value)(unsigned int nmi_hz);
+        u64 pcr_nmi_enable;
+        u64 pcr_nmi_disable;
 };
 extern const struct pcr_ops *pcr_ops;
 
@@ -27,21 +32,18 @@ extern void schedule_deferred_pcr_work(void);
 #define PCR_N2_SL1_SHIFT        27
 #define PCR_N2_OV1              0x80000000
 
-extern unsigned int picl_shift;
-
-/* In order to commonize as much of the implementation as
- * possible, we use PICH as our counter.  Mostly this is
- * to accommodate Niagara-1 which can only count insn cycles
- * in PICH.
- */
-static inline u64 picl_value(unsigned int nmi_hz)
-{
-        u32 delta = local_cpu_data().clock_tick / (nmi_hz << picl_shift);
-
-        return ((u64)((0 - delta) & 0xffffffff)) << 32;
-}
-
-extern u64 pcr_enable;
+#define PCR_N4_OV               0x00000001 /* PIC overflow             */
+#define PCR_N4_TOE              0x00000002 /* Trap On Event            */
+#define PCR_N4_UTRACE           0x00000004 /* Trace user events        */
+#define PCR_N4_STRACE           0x00000008 /* Trace supervisor events  */
+#define PCR_N4_HTRACE           0x00000010 /* Trace hypervisor events  */
+#define PCR_N4_MASK             0x000007e0 /* Event mask               */
+#define PCR_N4_MASK_SHIFT       5
+#define PCR_N4_SL               0x0000f800 /* Event Select             */
+#define PCR_N4_SL_SHIFT         11
+#define PCR_N4_PICNPT           0x00010000 /* PIC non-privileged trap  */
+#define PCR_N4_PICNHT           0x00020000 /* PIC non-hypervisor trap  */
+#define PCR_N4_NTC              0x00040000 /* Next-To-Commit wrap      */
 
 extern int pcr_arch_init(void);
 
diff --git a/arch/sparc/include/asm/perfctr.h b/arch/sparc/include/asm/perfctr.h
index 3332d2cba6c..214feefa577 100644
--- a/arch/sparc/include/asm/perfctr.h
+++ b/arch/sparc/include/asm/perfctr.h
@@ -54,11 +54,6 @@ enum perfctr_opcode {
         PERFCTR_GETPCR
 };
 
-/* I don't want the kernel's namespace to be polluted with this
- * stuff when this file is included.  --DaveM
- */
-#ifndef __KERNEL__
-
 #define  PRIV 0x00000001
 #define  SYS  0x00000002
 #define  USR  0x00000004
@@ -168,29 +163,4 @@ struct vcounter_struct {
   unsigned long long vcnt1;
 };
 
-#else /* !(__KERNEL__) */
-
-#ifndef CONFIG_SPARC32
-
-/* Performance counter register access. */
-#define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
-#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
-#define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
-
-/* Blackbird errata workaround.  See commentary in
- * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
- * for more information.
- */
-#define write_pic(__p)                                          \
-        __asm__ __volatile__("ba,pt     %%xcc, 99f\n\t"         \
-                             " nop\n\t"                         \
-                             ".align    64\n"                   \
-                          "99:wr        %0, 0x0, %%pic\n\t"     \
-                             "rd        %%pic, %%g0" : : "r" (__p))
-#define reset_pic()     write_pic(0)
-
-#endif /* !CONFIG_SPARC32 */
-
-#endif /* !(__KERNEL__) */
-
 #endif /* !(PERF_COUNTER_API) */
diff --git a/arch/sparc/include/asm/pstate.h b/arch/sparc/include/asm/pstate.h
index a26a53777bb..4b6b998afd9 100644
--- a/arch/sparc/include/asm/pstate.h
+++ b/arch/sparc/include/asm/pstate.h
@@ -88,4 +88,18 @@
 #define VERS_MAXTL      _AC(0x000000000000ff00,UL) /* Max Trap Level.   */
 #define VERS_MAXWIN     _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
 
+/* Compatability Feature Register (%asr26), SPARC-T4 and later  */
+#define CFR_AES         _AC(0x0000000000000001,UL) /* Supports AES opcodes     */
+#define CFR_DES         _AC(0x0000000000000002,UL) /* Supports DES opcodes     */
+#define CFR_KASUMI      _AC(0x0000000000000004,UL) /* Supports KASUMI opcodes  */
+#define CFR_CAMELLIA    _AC(0x0000000000000008,UL) /* Supports CAMELLIA opcodes*/
+#define CFR_MD5         _AC(0x0000000000000010,UL) /* Supports MD5 opcodes     */
+#define CFR_SHA1        _AC(0x0000000000000020,UL) /* Supports SHA1 opcodes    */
+#define CFR_SHA256      _AC(0x0000000000000040,UL) /* Supports SHA256 opcodes  */
+#define CFR_SHA512      _AC(0x0000000000000080,UL) /* Supports SHA512 opcodes  */
+#define CFR_MPMUL       _AC(0x0000000000000100,UL) /* Supports MPMUL opcodes   */
+#define CFR_MONTMUL     _AC(0x0000000000000200,UL) /* Supports MONTMUL opcodes */
+#define CFR_MONTSQR     _AC(0x0000000000000400,UL) /* Supports MONTSQR opcodes */
+#define CFR_CRC32C      _AC(0x0000000000000800,UL) /* Supports CRC32C opcodes  */
+
 #endif /* !(_SPARC64_PSTATE_H) */