25 files changed, 474 insertions, 260 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 33bab477d2e..b144e8af89d 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -41,7 +41,8 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7757)	:= pinmux-sh7757.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)     := pinmux-sh7785.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)     := pinmux-sh7786.o
 
-obj-y                           += $(clock-y)
-obj-$(CONFIG_SMP)               += $(smp-y)
-obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
-obj-$(CONFIG_PERF_EVENTS)       += perf_event.o
+obj-y                                   += $(clock-y)
+obj-$(CONFIG_SMP)                       += $(smp-y)
+obj-$(CONFIG_GENERIC_GPIO)              += $(pinmux-y)
+obj-$(CONFIG_PERF_EVENTS)               += perf_event.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += ubc.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 0ee3ee86125..2c16df37eda 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -107,13 +107,17 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index a95ebaba095..91588d280cd 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -110,13 +110,17 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index ea38b554dc0..15db6d521c5 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -110,19 +110,22 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
-enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
-       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
 
 #define DIV4(_str, _reg, _bit, _mask, _flags) \
   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
+
 struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
         [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
@@ -130,9 +133,19 @@ struct clk div4_clks[DIV4_NR] = {
         [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
         [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
         [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
+};
+
+enum { DIV4_IRDA, DIV4_ENABLE_NR };
+
+struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
+        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
+};
+
+enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
+
+struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
         [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
         [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
-        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
 };
 
 struct clk div6_clks[] = {
@@ -189,6 +202,14 @@ int __init arch_clk_init(void)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
+                ret = sh_clk_div4_enable_register(div4_enable_clks,
+                                        DIV4_ENABLE_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div4_reparent_register(div4_reparent_clks,
+                                        DIV4_REPARENT_NR, &div4_table);
+
+        if (!ret)
                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 
         if (!ret)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 20a31c2255a..50babe01fe4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -110,15 +110,18 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
-enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
-       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 
 #define DIV4(_str, _reg, _bit, _mask, _flags) \
   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
@@ -130,11 +133,20 @@ struct clk div4_clks[DIV4_NR] = {
         [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
         [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
         [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
-        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
-        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
+};
+
+enum { DIV4_IRDA, DIV4_ENABLE_NR };
+
+struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
         [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
 };
 
+enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
+
+struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
+        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
+        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
+};
 struct clk div6_clks[] = {
         SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
 };
@@ -216,6 +228,14 @@ int __init arch_clk_init(void)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
+                ret = sh_clk_div4_enable_register(div4_enable_clks,
+                                        DIV4_ENABLE_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div4_reparent_register(div4_reparent_clks,
+                                        DIV4_REPARENT_NR, &div4_table);
+
+        if (!ret)
                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 
         if (!ret)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 9db743802f0..6707061fbf5 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -127,13 +127,28 @@ struct clk *main_clks[] = {
         &div3_clk,
 };
 
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRA to update hardware setting */
+        value = __raw_readl(FRQCRA);
+        value |= (1 << 31);
+        __raw_writel(value, FRQCRA);
+}
+
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 
 #define DIV4(_str, _reg, _bit, _mask, _flags) \
@@ -144,7 +159,7 @@ struct clk div4_clks[DIV4_NR] = {
         [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
         [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
-        [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
+        [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 };
 
 struct clk div6_clks[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index ddc235ca966..86aae60677d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -35,7 +35,7 @@ static struct clk_ops sh7757_master_clk_ops = {
 
 static void module_clk_recalc(struct clk *clk)
 {
-        int idx = ctrl_inl(FRQCR) & 0x0000000f;
+        int idx = __raw_readl(FRQCR) & 0x0000000f;
         clk->rate = clk->parent->rate / p1fc_divisors[idx];
 }
 
@@ -45,7 +45,7 @@ static struct clk_ops sh7757_module_clk_ops = {
 
 static void bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
+        int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f;
         clk->rate = clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -55,7 +55,7 @@ static struct clk_ops sh7757_bus_clk_ops = {
 
 static void cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
+        int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
         clk->rate = clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -78,7 +78,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static void shyway_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
+        int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
         clk->rate = clk->parent->rate / sfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 370cd47642e..9f401163e71 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
+        clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
 }
 
 static struct clk_ops sh7763_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7763_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
         return clk->parent->rate / p0fc_divisors[idx];
 }
 
@@ -41,7 +41,7 @@ static struct clk_ops sh7763_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -68,7 +68,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index e0b89676920..9e3354365d4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -21,7 +21,7 @@ static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f];
+        clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
 }
 
 static struct clk_ops sh7770_master_clk_ops = {
@@ -30,7 +30,7 @@ static struct clk_ops sh7770_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
+        int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -40,7 +40,7 @@ static struct clk_ops sh7770_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) & 0x000f);
+        int idx = (__raw_readl(FRQCR) & 0x000f);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -50,7 +50,7 @@ static struct clk_ops sh7770_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
+        int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index a249d823578..150963a6001 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003];
+        clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
 }
 
 static struct clk_ops sh7780_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7780_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) & 0x0003);
+        int idx = (__raw_readl(FRQCR) & 0x0003);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -41,7 +41,7 @@ static struct clk_ops sh7780_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
+        int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -51,7 +51,7 @@ static struct clk_ops sh7780_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
+        int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -74,7 +74,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
+        int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 73abfbf2f16..d997f0a25b1 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -57,11 +57,15 @@ static struct clk *clks[] = {
 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
                                24, 32, 36, 48 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = div2,
         .nr_divisors = ARRAY_SIZE(div2),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
         DIV4_DU, DIV4_P, DIV4_NR };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index a0e8869071a..af69fd46870 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -3,11 +3,7 @@
  *
  * SH7786 support for the clock framework
  *
- * Copyright (C) 2008, 2009  Renesas Solutions Corp.
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * Based on SH7785
- *  Copyright (C) 2007  Paul Mundt
+ *  Copyright (C) 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -15,127 +11,127 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
-
-static int ifc_divisors[] = { 1, 2, 4, 1 };
-static int sfc_divisors[] = { 1, 1, 4, 1 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
-                             24, 32, 1, 1, 1, 1, 1, 1 };
-static int mfc_divisors[] = { 1, 1, 4, 1 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
-                              24, 32, 1, 48, 1, 1, 1, 1 };
 
-static void master_clk_init(struct clk *clk)
-{
-        clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
-}
-
-static struct clk_ops sh7786_master_clk_ops = {
-        .init           = master_clk_init,
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
 };
 
-static unsigned long module_clk_recalc(struct clk *clk)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQMR1) & 0x000f);
-        return clk->parent->rate / pfc_divisors[idx];
-}
+        int multiplier;
 
-static struct clk_ops sh7786_module_clk_ops = {
-        .recalc         = module_clk_recalc,
-};
+        /*
+         * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
+         * while modes 3, 4, and 5 use an x32.
+         */
+        multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
 
-static unsigned long bus_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
-        return clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops sh7786_bus_clk_ops = {
-        .recalc         = bus_clk_recalc,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static unsigned long cpu_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
-        return clk->parent->rate / ifc_divisors[idx];
-}
-
-static struct clk_ops sh7786_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
 };
 
-static struct clk_ops *sh7786_clk_ops[] = {
-        &sh7786_master_clk_ops,
-        &sh7786_module_clk_ops,
-        &sh7786_bus_clk_ops,
-        &sh7786_cpu_clk_ops,
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(sh7786_clk_ops))
-                *ops = sh7786_clk_ops[idx];
-}
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+                               24, 32, 36, 48 };
 
-static unsigned long shyway_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
-        return clk->parent->rate / sfc_divisors[idx];
-}
-
-static struct clk_ops sh7786_shyway_clk_ops = {
-        .recalc         = shyway_clk_recalc,
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
 };
 
-static struct clk sh7786_shyway_clk = {
-        .name           = "shyway_clk",
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &sh7786_shyway_clk_ops,
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
 };
 
-static unsigned long ddr_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
-        return clk->parent->rate / mfc_divisors[idx];
-}
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
 
-static struct clk_ops sh7786_ddr_clk_ops = {
-        .recalc         = ddr_clk_recalc,
-};
+#define DIV4(_str, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
 
-static struct clk sh7786_ddr_clk = {
-        .name           = "ddr_clk",
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &sh7786_ddr_clk_ops,
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
+        [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
+        [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
 };
 
-/*
- * Additional SH7786-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *sh7786_onchip_clocks[] = {
-        &sh7786_shyway_clk,
-        &sh7786_ddr_clk,
+#define MSTPCR0         0xffc40030
+#define MSTPCR1         0xffc40034
+
+static struct clk mstp_clks[] = {
+        /* MSTPCR0 */
+        SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
+        SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
+        SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
+        SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
+        SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
+        SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
+        SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
+        SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
+        SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
+        SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
+        SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
+
+        /* MSTPCR1 */
+        SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
+        SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
+        SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
+        SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
+        SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
+        SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
+        SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
+        SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
 };
 
 int __init arch_clk_init(void)
 {
-        struct clk *clk;
         int i, ret = 0;
 
-        cpg_clk_init();
-
-        clk = clk_get(NULL, "master_clk");
-        for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
-                struct clk *clkp = sh7786_onchip_clocks[i];
-
-                clkp->parent = clk;
-                ret |= clk_register(clkp);
-        }
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
 
-        clk_put(clk);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 23c27d32d98..e75c57bdfa5 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -33,7 +33,7 @@ static int cfc_divisors[] = { 1, 1, 4, 6 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK];
+        clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
 }
 
 static struct clk_ops shx3_master_clk_ops = {
@@ -42,7 +42,7 @@ static struct clk_ops shx3_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -52,7 +52,7 @@ static struct clk_ops shx3_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -62,7 +62,7 @@ static struct clk_ops shx3_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -85,7 +85,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index cb9d07bd59f..0688a7502f8 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -278,6 +278,7 @@ enum {
         HIZA8_LCDC, HIZA8_HIZ,
         HIZA7_LCDC, HIZA7_HIZ,
         HIZA6_LCDC, HIZA6_HIZ,
+        HIZB4_SIUA, HIZB4_HIZ,
         HIZB1_VIO, HIZB1_HIZ,
         HIZB0_VIO, HIZB0_HIZ,
         HIZC15_IRQ7, HIZC15_HIZ,
@@ -546,7 +547,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
                     HIZB0_VIO, FOE_VIO_VD2),
         PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
-                    HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2),
+                    HIZB1_VIO, FCE_VIO_HD2),
         PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
                     HIZB1_VIO, FRB_VIO_CLK2),
 
@@ -658,14 +659,14 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SDHICLK_MARK, SDHICLK),
 
         /* SIU - Port A */
-        PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC),
-        PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK),
-        PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD),
-        PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2),
-        PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1),
-        PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD),
-        PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0),
-        PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0),
+        PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, HIZB4_SIUA, SIUAOLR_SIOF1_SYNC),
+        PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, HIZB4_SIUA, SIUAOBT_SIOF1_SCK),
+        PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, HIZB4_SIUA, SIUAISLD_SIOF1_RXD),
+        PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, HIZB4_SIUA, SIUAILR_SIOF1_SS2),
+        PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, HIZB4_SIUA, SIUAIBT_SIOF1_SS1),
+        PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, HIZB4_SIUA, SIUAOSLD_SIOF1_TXD),
+        PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, HIZB4_SIUA, PSB1_SIUMCKA, PTK0),
+        PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, HIZB4_SIUA, PTK0),
 
         /* SIU - Port B */
         PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
@@ -1612,7 +1613,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 0, 0,
                 0, 0,
                 0, 0,
-                0, 0,
+                HIZB4_SIUA, HIZB4_HIZ,
                 0, 0,
                 0, 0,
                 HIZB1_VIO, HIZB1_HIZ,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index b5335b5e309..ef3f9782780 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -446,6 +446,8 @@ void __init plat_early_device_setup(void)
 
 enum {
         UNUSED=0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -461,7 +463,6 @@ enum {
         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
-        SDHI0, SDHI1, SDHI2, SDHI3,
         CMT, TSIF, SIU, TWODG,
         TMU0, TMU1, TMU2,
         IRDA, JPU, LCDC,
@@ -494,8 +495,8 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
-        INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
-        INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
+        INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
+        INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -513,7 +514,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
-        INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
@@ -535,7 +535,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
+          { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -573,9 +573,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7722",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 772b9265d0e..85c61f62470 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -592,14 +592,17 @@ void __init plat_early_device_setup(void)
 #define RAMCR_CACHE_L2FC        0x0002
 #define RAMCR_CACHE_L2E         0x0001
 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
-void __uses_jump_to_uncached l2_cache_init(void)
+
+void l2_cache_init(void)
 {
         /* Enable L2 cache */
-        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+        __raw_writel(L2_CACHE_ENABLE, RAMCR);
 }
 
 enum {
         UNUSED=0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -622,7 +625,6 @@ enum {
         SCIFA_SCIFA1,
         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
-        SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
         CMT_CMTI,
         TSIF_TSIFI,
         SIU_SIUI,
@@ -630,7 +632,6 @@ enum {
         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
         IRDA_IRDAI,
         ATAPI_ATAPII,
-        SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
         VEU2H1_VEU2HI,
         LCDC_LCDCI,
         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
@@ -701,9 +702,9 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(I2C_WAITI,0xE40),
         INTC_VECT(I2C_DTEI,0xE60),
 
-        INTC_VECT(SDHI0_SDHII0,0xE80),
-        INTC_VECT(SDHI0_SDHII1,0xEA0),
-        INTC_VECT(SDHI0_SDHII2,0xEC0),
+        INTC_VECT(SDHI0, 0xE80),
+        INTC_VECT(SDHI0, 0xEA0),
+        INTC_VECT(SDHI0, 0xEC0),
 
         INTC_VECT(CMT_CMTI,0xF00),
         INTC_VECT(TSIF_TSIFI,0xF20),
@@ -717,9 +718,9 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(IRDA_IRDAI,0x480),
         INTC_VECT(ATAPI_ATAPII,0x4A0),
 
-        INTC_VECT(SDHI1_SDHII0,0x4E0),
-        INTC_VECT(SDHI1_SDHII1,0x500),
-        INTC_VECT(SDHI1_SDHII2,0x520),
+        INTC_VECT(SDHI1, 0x4E0),
+        INTC_VECT(SDHI1, 0x500),
+        INTC_VECT(SDHI1, 0x520),
 
         INTC_VECT(VEU2H1_VEU2HI,0x560),
         INTC_VECT(LCDC_LCDCI,0x580),
@@ -738,15 +739,14 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
-        INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
-        INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
-          { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
+          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
+            0, DISABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
@@ -763,7 +763,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
+          { 0, DISABLED, ENABLED, ENABLED,
+            0, 0, SCIFA_SCIFA2, SIU_SIUI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -803,9 +804,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7723",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index d32f96c1cc1..31e3451f7e3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -714,14 +714,17 @@ void __init plat_early_device_setup(void)
 #define RAMCR_CACHE_L2FC        0x0002
 #define RAMCR_CACHE_L2E         0x0001
 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
-void __uses_jump_to_uncached l2_cache_init(void)
+
+void l2_cache_init(void)
 {
         /* Enable L2 cache */
-        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+        __raw_writel(L2_CACHE_ENABLE, RAMCR);
 }
 
 enum {
         UNUSED = 0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -750,14 +753,12 @@ enum {
         ETHI,
         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
-        SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
         CMT,
         TSIF,
         FSI,
         SCIFA5,
         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
         IRDA,
-        SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
         JPU,
         _2DDMAC,
         MMC_MMC2I, MMC_MMC3I,
@@ -839,10 +840,10 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(I2C0_WAITI, 0xE40),
         INTC_VECT(I2C0_DTEI, 0xE60),
 
-        INTC_VECT(SDHI0_SDHII0, 0xE80),
-        INTC_VECT(SDHI0_SDHII1, 0xEA0),
-        INTC_VECT(SDHI0_SDHII2, 0xEC0),
-        INTC_VECT(SDHI0_SDHII3, 0xEE0),
+        INTC_VECT(SDHI0, 0xE80),
+        INTC_VECT(SDHI0, 0xEA0),
+        INTC_VECT(SDHI0, 0xEC0),
+        INTC_VECT(SDHI0, 0xEE0),
 
         INTC_VECT(CMT,    0xF00),
         INTC_VECT(TSIF,   0xF20),
@@ -855,9 +856,9 @@ static struct intc_vect vectors[] __initdata = {
 
         INTC_VECT(IRDA,    0x480),
 
-        INTC_VECT(SDHI1_SDHII0, 0x4E0),
-        INTC_VECT(SDHI1_SDHII1, 0x500),
-        INTC_VECT(SDHI1_SDHII2, 0x520),
+        INTC_VECT(SDHI1, 0x4E0),
+        INTC_VECT(SDHI1, 0x500),
+        INTC_VECT(SDHI1, 0x520),
 
         INTC_VECT(JPU, 0x560),
         INTC_VECT(_2DDMAC, 0x4A0),
@@ -883,8 +884,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
-        INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
-        INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
         INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
         INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
 };
@@ -892,7 +891,7 @@ static struct intc_group groups[] __initdata = {
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
-            0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
+            0, DISABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
@@ -914,7 +913,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
+          { DISABLED, DISABLED, ENABLED, ENABLED,
             0, 0, SCIFA5, FSI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
@@ -961,9 +960,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7724",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 37e32efbbaa..e75edf58796 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -487,17 +487,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -507,32 +507,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 6aba26fec41..7f6b0a5f7f8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -538,11 +538,11 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         register_intc_controller(&intc_desc);
 }
@@ -552,27 +552,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index c1643bc9590..86d681ecf90 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -694,17 +694,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -714,27 +714,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index c310558490d..f8f21618d78 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -461,17 +461,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -481,27 +481,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index f685b9b2199..23448d8c671 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -541,17 +541,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -561,32 +561,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 71673487ace..7e585320710 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -867,14 +867,14 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -884,32 +884,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 5863e0c4d02..11bf4c1e25c 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -78,7 +78,10 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
 
 void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
 {
-        __raw_writel(entry_point, RESET_REG(cpu));
+        if (__in_29bit_mode())
+                __raw_writel(entry_point, RESET_REG(cpu));
+        else
+                __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
 
         if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
                 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
diff --git a/arch/sh/kernel/cpu/sh4a/ubc.c b/arch/sh/kernel/cpu/sh4a/ubc.c
new file mode 100644
index 00000000000..efb2745bcb3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/ubc.c
@@ -0,0 +1,133 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/ubc.c
+ *
+ * On-chip UBC support for SH-4A CPUs.
+ *
+ * Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <asm/hw_breakpoint.h>
+
+#define UBC_CBR(idx)    (0xff200000 + (0x20 * idx))
+#define UBC_CRR(idx)    (0xff200004 + (0x20 * idx))
+#define UBC_CAR(idx)    (0xff200008 + (0x20 * idx))
+#define UBC_CAMR(idx)   (0xff20000c + (0x20 * idx))
+
+#define UBC_CCMFR       0xff200600
+#define UBC_CBCR        0xff200620
+
+/* CRR */
+#define UBC_CRR_PCB     (1 << 1)
+#define UBC_CRR_BIE     (1 << 0)
+
+/* CBR */
+#define UBC_CBR_CE      (1 << 0)
+
+static struct sh_ubc sh4a_ubc;
+
+static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx)
+{
+        __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
+        __raw_writel(info->address, UBC_CAR(idx));
+}
+
+static void sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx)
+{
+        __raw_writel(0, UBC_CBR(idx));
+        __raw_writel(0, UBC_CAR(idx));
+}
+
+static void sh4a_ubc_enable_all(unsigned long mask)
+{
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                if (mask & (1 << i))
+                        __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
+                                     UBC_CBR(i));
+}
+
+static void sh4a_ubc_disable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
+                             UBC_CBR(i));
+}
+
+static unsigned long sh4a_ubc_active_mask(void)
+{
+        unsigned long active = 0;
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE)
+                        active |= (1 << i);
+
+        return active;
+}
+
+static unsigned long sh4a_ubc_triggered_mask(void)
+{
+        return __raw_readl(UBC_CCMFR);
+}
+
+static void sh4a_ubc_clear_triggered_mask(unsigned long mask)
+{
+        __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
+}
+
+static struct sh_ubc sh4a_ubc = {
+        .name                   = "SH-4A",
+        .num_events             = 2,
+        .trap_nr                = 0x1e0,
+        .enable                 = sh4a_ubc_enable,
+        .disable                = sh4a_ubc_disable,
+        .enable_all             = sh4a_ubc_enable_all,
+        .disable_all            = sh4a_ubc_disable_all,
+        .active_mask            = sh4a_ubc_active_mask,
+        .triggered_mask         = sh4a_ubc_triggered_mask,
+        .clear_triggered_mask   = sh4a_ubc_clear_triggered_mask,
+};
+
+static int __init sh4a_ubc_init(void)
+{
+        struct clk *ubc_iclk = clk_get(NULL, "ubc0");
+        int i;
+
+        /*
+         * The UBC MSTP bit is optional, as not all platforms will have
+         * it. Just ignore it if we can't find it.
+         */
+        if (IS_ERR(ubc_iclk))
+                ubc_iclk = NULL;
+
+        clk_enable(ubc_iclk);
+
+        __raw_writel(0, UBC_CBCR);
+
+        for (i = 0; i < sh4a_ubc.num_events; i++) {
+                __raw_writel(0, UBC_CAMR(i));
+                __raw_writel(0, UBC_CBR(i));
+
+                __raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i));
+
+                /* dummy read for write posting */
+                (void)__raw_readl(UBC_CRR(i));
+        }
+
+        clk_disable(ubc_iclk);
+
+        sh4a_ubc.clk = ubc_iclk;
+
+        return register_sh_ubc(&sh4a_ubc);
+}
+arch_initcall(sh4a_ubc_init);