diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7723.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 0eadefdbbba..072382280f9 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
@@ -24,6 +24,8 @@ | |||
24 | static struct plat_sci_port scif0_platform_data = { | 24 | static struct plat_sci_port scif0_platform_data = { |
25 | .mapbase = 0xffe00000, | 25 | .mapbase = 0xffe00000, |
26 | .flags = UPF_BOOT_AUTOCONF, | 26 | .flags = UPF_BOOT_AUTOCONF, |
27 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
28 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
27 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
28 | .irqs = { 80, 80, 80, 80 }, | 30 | .irqs = { 80, 80, 80, 80 }, |
29 | }; | 31 | }; |
@@ -39,6 +41,8 @@ static struct platform_device scif0_device = { | |||
39 | static struct plat_sci_port scif1_platform_data = { | 41 | static struct plat_sci_port scif1_platform_data = { |
40 | .mapbase = 0xffe10000, | 42 | .mapbase = 0xffe10000, |
41 | .flags = UPF_BOOT_AUTOCONF, | 43 | .flags = UPF_BOOT_AUTOCONF, |
44 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
45 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
42 | .type = PORT_SCIF, | 46 | .type = PORT_SCIF, |
43 | .irqs = { 81, 81, 81, 81 }, | 47 | .irqs = { 81, 81, 81, 81 }, |
44 | }; | 48 | }; |
@@ -54,6 +58,8 @@ static struct platform_device scif1_device = { | |||
54 | static struct plat_sci_port scif2_platform_data = { | 58 | static struct plat_sci_port scif2_platform_data = { |
55 | .mapbase = 0xffe20000, | 59 | .mapbase = 0xffe20000, |
56 | .flags = UPF_BOOT_AUTOCONF, | 60 | .flags = UPF_BOOT_AUTOCONF, |
61 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
62 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
57 | .type = PORT_SCIF, | 63 | .type = PORT_SCIF, |
58 | .irqs = { 82, 82, 82, 82 }, | 64 | .irqs = { 82, 82, 82, 82 }, |
59 | }; | 65 | }; |
@@ -69,6 +75,8 @@ static struct platform_device scif2_device = { | |||
69 | static struct plat_sci_port scif3_platform_data = { | 75 | static struct plat_sci_port scif3_platform_data = { |
70 | .mapbase = 0xa4e30000, | 76 | .mapbase = 0xa4e30000, |
71 | .flags = UPF_BOOT_AUTOCONF, | 77 | .flags = UPF_BOOT_AUTOCONF, |
78 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
79 | .scbrr_algo_id = SCBRR_ALGO_3, | ||
72 | .type = PORT_SCIFA, | 80 | .type = PORT_SCIFA, |
73 | .irqs = { 56, 56, 56, 56 }, | 81 | .irqs = { 56, 56, 56, 56 }, |
74 | }; | 82 | }; |
@@ -84,6 +92,8 @@ static struct platform_device scif3_device = { | |||
84 | static struct plat_sci_port scif4_platform_data = { | 92 | static struct plat_sci_port scif4_platform_data = { |
85 | .mapbase = 0xa4e40000, | 93 | .mapbase = 0xa4e40000, |
86 | .flags = UPF_BOOT_AUTOCONF, | 94 | .flags = UPF_BOOT_AUTOCONF, |
95 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
96 | .scbrr_algo_id = SCBRR_ALGO_3, | ||
87 | .type = PORT_SCIFA, | 97 | .type = PORT_SCIFA, |
88 | .irqs = { 88, 88, 88, 88 }, | 98 | .irqs = { 88, 88, 88, 88 }, |
89 | }; | 99 | }; |
@@ -99,6 +109,8 @@ static struct platform_device scif4_device = { | |||
99 | static struct plat_sci_port scif5_platform_data = { | 109 | static struct plat_sci_port scif5_platform_data = { |
100 | .mapbase = 0xa4e50000, | 110 | .mapbase = 0xa4e50000, |
101 | .flags = UPF_BOOT_AUTOCONF, | 111 | .flags = UPF_BOOT_AUTOCONF, |
112 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | ||
113 | .scbrr_algo_id = SCBRR_ALGO_3, | ||
102 | .type = PORT_SCIFA, | 114 | .type = PORT_SCIFA, |
103 | .irqs = { 109, 109, 109, 109 }, | 115 | .irqs = { 109, 109, 109, 109 }, |
104 | }; | 116 | }; |
@@ -719,7 +731,7 @@ static struct intc_group groups[] __initdata = { | |||
719 | static struct intc_mask_reg mask_registers[] __initdata = { | 731 | static struct intc_mask_reg mask_registers[] __initdata = { |
720 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ | 732 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ |
721 | { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, | 733 | { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, |
722 | 0, DISABLED, ENABLED, ENABLED } }, | 734 | 0, ENABLED, ENABLED, ENABLED } }, |
723 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ | 735 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
724 | { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, | 736 | { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, |
725 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ | 737 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ |
@@ -736,7 +748,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { | |||
736 | { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, | 748 | { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, |
737 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, | 749 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, |
738 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ | 750 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ |
739 | { 0, DISABLED, ENABLED, ENABLED, | 751 | { 0, ENABLED, ENABLED, ENABLED, |
740 | 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, | 752 | 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, |
741 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ | 753 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
742 | { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, | 754 | { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, |