diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7723.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 772b9265d0e..85c61f62470 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
@@ -592,14 +592,17 @@ void __init plat_early_device_setup(void) | |||
592 | #define RAMCR_CACHE_L2FC 0x0002 | 592 | #define RAMCR_CACHE_L2FC 0x0002 |
593 | #define RAMCR_CACHE_L2E 0x0001 | 593 | #define RAMCR_CACHE_L2E 0x0001 |
594 | #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) | 594 | #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) |
595 | void __uses_jump_to_uncached l2_cache_init(void) | 595 | |
596 | void l2_cache_init(void) | ||
596 | { | 597 | { |
597 | /* Enable L2 cache */ | 598 | /* Enable L2 cache */ |
598 | ctrl_outl(L2_CACHE_ENABLE, RAMCR); | 599 | __raw_writel(L2_CACHE_ENABLE, RAMCR); |
599 | } | 600 | } |
600 | 601 | ||
601 | enum { | 602 | enum { |
602 | UNUSED=0, | 603 | UNUSED=0, |
604 | ENABLED, | ||
605 | DISABLED, | ||
603 | 606 | ||
604 | /* interrupt sources */ | 607 | /* interrupt sources */ |
605 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | 608 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, |
@@ -622,7 +625,6 @@ enum { | |||
622 | SCIFA_SCIFA1, | 625 | SCIFA_SCIFA1, |
623 | FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, | 626 | FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, |
624 | I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, | 627 | I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, |
625 | SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2, | ||
626 | CMT_CMTI, | 628 | CMT_CMTI, |
627 | TSIF_TSIFI, | 629 | TSIF_TSIFI, |
628 | SIU_SIUI, | 630 | SIU_SIUI, |
@@ -630,7 +632,6 @@ enum { | |||
630 | TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, | 632 | TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, |
631 | IRDA_IRDAI, | 633 | IRDA_IRDAI, |
632 | ATAPI_ATAPII, | 634 | ATAPI_ATAPII, |
633 | SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2, | ||
634 | VEU2H1_VEU2HI, | 635 | VEU2H1_VEU2HI, |
635 | LCDC_LCDCI, | 636 | LCDC_LCDCI, |
636 | TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, | 637 | TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, |
@@ -701,9 +702,9 @@ static struct intc_vect vectors[] __initdata = { | |||
701 | INTC_VECT(I2C_WAITI,0xE40), | 702 | INTC_VECT(I2C_WAITI,0xE40), |
702 | INTC_VECT(I2C_DTEI,0xE60), | 703 | INTC_VECT(I2C_DTEI,0xE60), |
703 | 704 | ||
704 | INTC_VECT(SDHI0_SDHII0,0xE80), | 705 | INTC_VECT(SDHI0, 0xE80), |
705 | INTC_VECT(SDHI0_SDHII1,0xEA0), | 706 | INTC_VECT(SDHI0, 0xEA0), |
706 | INTC_VECT(SDHI0_SDHII2,0xEC0), | 707 | INTC_VECT(SDHI0, 0xEC0), |
707 | 708 | ||
708 | INTC_VECT(CMT_CMTI,0xF00), | 709 | INTC_VECT(CMT_CMTI,0xF00), |
709 | INTC_VECT(TSIF_TSIFI,0xF20), | 710 | INTC_VECT(TSIF_TSIFI,0xF20), |
@@ -717,9 +718,9 @@ static struct intc_vect vectors[] __initdata = { | |||
717 | INTC_VECT(IRDA_IRDAI,0x480), | 718 | INTC_VECT(IRDA_IRDAI,0x480), |
718 | INTC_VECT(ATAPI_ATAPII,0x4A0), | 719 | INTC_VECT(ATAPI_ATAPII,0x4A0), |
719 | 720 | ||
720 | INTC_VECT(SDHI1_SDHII0,0x4E0), | 721 | INTC_VECT(SDHI1, 0x4E0), |
721 | INTC_VECT(SDHI1_SDHII1,0x500), | 722 | INTC_VECT(SDHI1, 0x500), |
722 | INTC_VECT(SDHI1_SDHII2,0x520), | 723 | INTC_VECT(SDHI1, 0x520), |
723 | 724 | ||
724 | INTC_VECT(VEU2H1_VEU2HI,0x560), | 725 | INTC_VECT(VEU2H1_VEU2HI,0x560), |
725 | INTC_VECT(LCDC_LCDCI,0x580), | 726 | INTC_VECT(LCDC_LCDCI,0x580), |
@@ -738,15 +739,14 @@ static struct intc_group groups[] __initdata = { | |||
738 | INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), | 739 | INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), |
739 | INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), | 740 | INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), |
740 | INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), | 741 | INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), |
741 | INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2), | ||
742 | INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), | 742 | INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), |
743 | INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), | 743 | INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), |
744 | INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2), | ||
745 | }; | 744 | }; |
746 | 745 | ||
747 | static struct intc_mask_reg mask_registers[] __initdata = { | 746 | static struct intc_mask_reg mask_registers[] __initdata = { |
748 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ | 747 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ |
749 | { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} }, | 748 | { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, |
749 | 0, DISABLED, ENABLED, ENABLED } }, | ||
750 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ | 750 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
751 | { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, | 751 | { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, |
752 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ | 752 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ |
@@ -763,7 +763,8 @@ static struct intc_mask_reg mask_registers[] __initdata = { | |||
763 | { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, | 763 | { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, |
764 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, | 764 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, |
765 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ | 765 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ |
766 | { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } }, | 766 | { 0, DISABLED, ENABLED, ENABLED, |
767 | 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, | ||
767 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ | 768 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
768 | { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, | 769 | { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, |
769 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ | 770 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ |
@@ -803,9 +804,13 @@ static struct intc_mask_reg ack_registers[] __initdata = { | |||
803 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | 804 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
804 | }; | 805 | }; |
805 | 806 | ||
806 | static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups, | 807 | static struct intc_desc intc_desc __initdata = { |
807 | mask_registers, prio_registers, sense_registers, | 808 | .name = "sh7723", |
808 | ack_registers); | 809 | .force_enable = ENABLED, |
810 | .force_disable = DISABLED, | ||
811 | .hw = INTC_HW_DESC(vectors, groups, mask_registers, | ||
812 | prio_registers, sense_registers, ack_registers), | ||
813 | }; | ||
809 | 814 | ||
810 | void __init plat_irq_setup(void) | 815 | void __init plat_irq_setup(void) |
811 | { | 816 | { |