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Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7786.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c181
1 files changed, 125 insertions, 56 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index c4a84bb2f3d..105a6d41b56 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -23,8 +23,6 @@
23 * from the platform code. 23 * from the platform code.
24 */ 24 */
25static struct clk extal_clk = { 25static struct clk extal_clk = {
26 .name = "extal",
27 .id = -1,
28 .rate = 33333333, 26 .rate = 33333333,
29}; 27};
30 28
@@ -46,8 +44,6 @@ static struct clk_ops pll_clk_ops = {
46}; 44};
47 45
48static struct clk pll_clk = { 46static struct clk pll_clk = {
49 .name = "pll_clk",
50 .id = -1,
51 .ops = &pll_clk_ops, 47 .ops = &pll_clk_ops,
52 .parent = &extal_clk, 48 .parent = &extal_clk,
53 .flags = CLK_ENABLE_ON_INIT, 49 .flags = CLK_ENABLE_ON_INIT,
@@ -72,118 +68,191 @@ static struct clk_div4_table div4_table = {
72 68
73enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; 69enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
74 70
75#define DIV4(_str, _bit, _mask, _flags) \ 71#define DIV4(_bit, _mask, _flags) \
76 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 72 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
77 73
78struct clk div4_clks[DIV4_NR] = { 74struct clk div4_clks[DIV4_NR] = {
79 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0), 75 [DIV4_P] = DIV4(0, 0x0b40, 0),
80 [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0), 76 [DIV4_DU] = DIV4(4, 0x0010, 0),
81 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT), 77 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
82 [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT), 78 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
83 [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT), 79 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
84 [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
85}; 81};
86 82
87#define MSTPCR0 0xffc40030 83#define MSTPCR0 0xffc40030
88#define MSTPCR1 0xffc40034 84#define MSTPCR1 0xffc40034
89 85
90static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
89 MSTP005, MSTP004, MSTP002,
90 MSTP112, MSTP110, MSTP109, MSTP108,
91 MSTP105, MSTP104, MSTP103, MSTP102,
92 MSTP_NR };
93
94static struct clk mstp_clks[MSTP_NR] = {
91 /* MSTPCR0 */ 95 /* MSTPCR0 */
92 SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 96 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
93 SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 97 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
94 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 98 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
95 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 99 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
96 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 100 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
97 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 101 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
98 SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), 102 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
99 SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), 103 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
100 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 104 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
101 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 105 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
102 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 106 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
103 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 107 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
104 SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0), 108 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
105 SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0), 109 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
106 SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0), 110 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
107 SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0), 111 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
108 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 112 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
109 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 113 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
110 SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 114 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
111 SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0), 115 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
112 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 116 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
113 117
114 /* MSTPCR1 */ 118 /* MSTPCR1 */
115 SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0), 119 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
116 SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0), 120 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
117 SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0), 121 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
118 SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0), 122 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
119 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 123 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
120 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 124 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
121 SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0), 125 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
122 SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), 126 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
123}; 127};
124 128
129#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
130
125static struct clk_lookup lookups[] = { 131static struct clk_lookup lookups[] = {
132 /* main clocks */
133 CLKDEV_CON_ID("extal", &extal_clk),
134 CLKDEV_CON_ID("pll_clk", &pll_clk),
135
136 /* DIV4 clocks */
137 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
138 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
139 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
140 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
141 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
142 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
143
144 /* MSTP32 clocks */
145 {
146 /* SCIF5 */
147 .dev_id = "sh-sci.5",
148 .con_id = "sci_fck",
149 .clk = &mstp_clks[MSTP029],
150 }, {
151 /* SCIF4 */
152 .dev_id = "sh-sci.4",
153 .con_id = "sci_fck",
154 .clk = &mstp_clks[MSTP028],
155 }, {
156 /* SCIF3 */
157 .dev_id = "sh-sci.3",
158 .con_id = "sci_fck",
159 .clk = &mstp_clks[MSTP027],
160 }, {
161 /* SCIF2 */
162 .dev_id = "sh-sci.2",
163 .con_id = "sci_fck",
164 .clk = &mstp_clks[MSTP026],
165 }, {
166 /* SCIF1 */
167 .dev_id = "sh-sci.1",
168 .con_id = "sci_fck",
169 .clk = &mstp_clks[MSTP025],
170 }, {
171 /* SCIF0 */
172 .dev_id = "sh-sci.0",
173 .con_id = "sci_fck",
174 .clk = &mstp_clks[MSTP024],
175 },
176 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
177 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
178 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
179 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
180 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
181 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
182 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
183 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
126 { 184 {
127 /* TMU0 */ 185 /* TMU0 */
128 .dev_id = "sh_tmu.0", 186 .dev_id = "sh_tmu.0",
129 .con_id = "tmu_fck", 187 .con_id = "tmu_fck",
130 .clk = &mstp_clks[17], /* tmu012_fck */ 188 .clk = &mstp_clks[MSTP008],
131 }, { 189 }, {
132 /* TMU1 */ 190 /* TMU1 */
133 .dev_id = "sh_tmu.1", 191 .dev_id = "sh_tmu.1",
134 .con_id = "tmu_fck", 192 .con_id = "tmu_fck",
135 .clk = &mstp_clks[17], 193 .clk = &mstp_clks[MSTP008],
136 }, { 194 }, {
137 /* TMU2 */ 195 /* TMU2 */
138 .dev_id = "sh_tmu.2", 196 .dev_id = "sh_tmu.2",
139 .con_id = "tmu_fck", 197 .con_id = "tmu_fck",
140 .clk = &mstp_clks[17], 198 .clk = &mstp_clks[MSTP008],
141 }, { 199 }, {
142 /* TMU3 */ 200 /* TMU3 */
143 .dev_id = "sh_tmu.3", 201 .dev_id = "sh_tmu.3",
144 .con_id = "tmu_fck", 202 .con_id = "tmu_fck",
145 .clk = &mstp_clks[16], /* tmu345_fck */ 203 .clk = &mstp_clks[MSTP009],
146 }, { 204 }, {
147 /* TMU4 */ 205 /* TMU4 */
148 .dev_id = "sh_tmu.4", 206 .dev_id = "sh_tmu.4",
149 .con_id = "tmu_fck", 207 .con_id = "tmu_fck",
150 .clk = &mstp_clks[16], 208 .clk = &mstp_clks[MSTP009],
151 }, { 209 }, {
152 /* TMU5 */ 210 /* TMU5 */
153 .dev_id = "sh_tmu.5", 211 .dev_id = "sh_tmu.5",
154 .con_id = "tmu_fck", 212 .con_id = "tmu_fck",
155 .clk = &mstp_clks[16], 213 .clk = &mstp_clks[MSTP009],
156 }, { 214 }, {
157 /* TMU6 */ 215 /* TMU6 */
158 .dev_id = "sh_tmu.6", 216 .dev_id = "sh_tmu.6",
159 .con_id = "tmu_fck", 217 .con_id = "tmu_fck",
160 .clk = &mstp_clks[15], /* tmu678_fck */ 218 .clk = &mstp_clks[MSTP010],
161 }, { 219 }, {
162 /* TMU7 */ 220 /* TMU7 */
163 .dev_id = "sh_tmu.7", 221 .dev_id = "sh_tmu.7",
164 .con_id = "tmu_fck", 222 .con_id = "tmu_fck",
165 .clk = &mstp_clks[15], 223 .clk = &mstp_clks[MSTP010],
166 }, { 224 }, {
167 /* TMU8 */ 225 /* TMU8 */
168 .dev_id = "sh_tmu.8", 226 .dev_id = "sh_tmu.8",
169 .con_id = "tmu_fck", 227 .con_id = "tmu_fck",
170 .clk = &mstp_clks[15], 228 .clk = &mstp_clks[MSTP010],
171 }, { 229 }, {
172 /* TMU9 */ 230 /* TMU9 */
173 .dev_id = "sh_tmu.9", 231 .dev_id = "sh_tmu.9",
174 .con_id = "tmu_fck", 232 .con_id = "tmu_fck",
175 .clk = &mstp_clks[14], /* tmu9_11_fck */ 233 .clk = &mstp_clks[MSTP011],
176 }, { 234 }, {
177 /* TMU10 */ 235 /* TMU10 */
178 .dev_id = "sh_tmu.10", 236 .dev_id = "sh_tmu.10",
179 .con_id = "tmu_fck", 237 .con_id = "tmu_fck",
180 .clk = &mstp_clks[14], 238 .clk = &mstp_clks[MSTP011],
181 }, { 239 }, {
182 /* TMU11 */ 240 /* TMU11 */
183 .dev_id = "sh_tmu.11", 241 .dev_id = "sh_tmu.11",
184 .con_id = "tmu_fck", 242 .con_id = "tmu_fck",
185 .clk = &mstp_clks[14], 243 .clk = &mstp_clks[MSTP011],
186 } 244 },
245 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
246 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
247 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
248 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
249 CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
250 CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
251 CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
252 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
253 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
254 CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
255 CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
187}; 256};
188 257
189int __init arch_clk_init(void) 258int __init arch_clk_init(void)
@@ -199,7 +268,7 @@ int __init arch_clk_init(void)
199 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 268 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
200 &div4_table); 269 &div4_table);
201 if (!ret) 270 if (!ret)
202 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 271 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
203 272
204 return ret; 273 return ret;
205} 274}
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