1 files changed, 146 insertions, 67 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index a066c438b40..71291ae201b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -37,8 +37,6 @@
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-        .name           = "rclk",
-        .id             = -1,
         .rate           = 32768,
 };
 
@@ -47,8 +45,6 @@ static struct clk r_clk = {
  * from the platform code.
  */
 struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
         .rate           = 33333333,
 };
 
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
 };
 
 static struct clk dll_clk = {
-        .name           = "dll_clk",
-        .id             = -1,
         .ops            = &dll_clk_ops,
         .parent         = &r_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -92,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -122,18 +114,18 @@ static struct clk_div4_table div4_table = {
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
-        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
-        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
+        [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
+        [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
+        [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
 };
 
 enum { DIV6_V, DIV6_NR };
@@ -142,61 +134,148 @@ struct clk div6_clks[DIV6_NR] = {
         [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
 };
 
-#define MSTP(_str, _parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
-
-static struct clk mstp_clks[] = {
-        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
-        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
-        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
-        MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
-        MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
-        MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
-        MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
-        MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
-        MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
-        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
-        MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
-        MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
-        MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
-        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
-        MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
-        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
-        SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
-        SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
-        SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
-        SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
-        MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
-        MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
-        MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
-
-        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
-        MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
-
-        MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
-        MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
-        MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
-        MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
-        MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
-        MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
-        MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
-        MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
-        MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
-        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
-        MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
-        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
-        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
-        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
-        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
-        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
-        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
+       MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
+       MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
+       MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
+       MSTP109, MSTP108, MSTP100,
+       MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
+       MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
+       MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
+        [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
+        [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
+        [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
+        [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
+        [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
+        [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
+        [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
+        [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
+        [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
+        [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
+        [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
+
+        [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
+        [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
+
+        [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
+        [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
+        [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
+        [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
+        [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
+        [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
+        [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
+        [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
+        [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
+        [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
+        [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
+        [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
+        [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
+        [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
+        [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
+        [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
+        [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
 };
 
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 
 static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("dll_clk", &dll_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
+        CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
+
         /* DIV6 clocks */
         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+
+        /* MSTP32 clocks */
+        CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
+        CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
+        CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
+        CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
+        CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
+        CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
+        CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
+        CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
+        CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
+        CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
+        CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
+        CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
+        CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
+        CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
+        CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
+        CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
+        {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP007],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP006],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP005],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP004],
+        },
+        CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
+        CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
+        CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
+        CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
+        CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
+        CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
+        CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
+        CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
+        CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
+        CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
+        CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
+        CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
+        CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
+        CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
+        CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
+        CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
+        CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
+        CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
+        CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
+        CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
+        CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
 };
 
 int __init arch_clk_init(void)
@@ -221,7 +300,7 @@ int __init arch_clk_init(void)
                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
         return ret;
 }