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-rw-r--r--arch/sh/kernel/cpu/sh4/Makefile11
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c179
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4.c80
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh73180.c81
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh7770.c73
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh7780.c126
6 files changed, 549 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index ead1071eac7..3d5cafc71ae 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -5,6 +5,15 @@
5obj-y := ex.o probe.o 5obj-y := ex.o probe.o
6 6
7obj-$(CONFIG_SH_FPU) += fpu.o 7obj-$(CONFIG_SH_FPU) += fpu.o
8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += irq_intc2.o
9obj-$(CONFIG_SH_STORE_QUEUES) += sq.o 8obj-$(CONFIG_SH_STORE_QUEUES) += sq.o
10 9
10# Primary on-chip clocks (common)
11clock-$(CONFIG_CPU_SH4) := clock-sh4.o
12clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o
13clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
14clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
15
16# Additional clocks by subtype
17clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
18
19obj-y += $(clock-y)
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
new file mode 100644
index 00000000000..bfdf5fe8d94
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -0,0 +1,179 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh4-202.c
3 *
4 * Additional SH4-202 support for the clock framework
5 *
6 * Copyright (C) 2005 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <asm/clock.h>
16#include <asm/freq.h>
17#include <asm/io.h>
18
19#define CPG2_FRQCR3 0xfe0a0018
20
21static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
22static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
23
24static void emi_clk_recalc(struct clk *clk)
25{
26 int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
27 clk->rate = clk->parent->rate / frqcr3_divisors[idx];
28}
29
30static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
31{
32 int divisor = clk->parent->rate / rate;
33 int i;
34
35 for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++)
36 if (frqcr3_divisors[i] == divisor)
37 return frqcr3_values[i];
38
39 /* Safe fallback */
40 return 5;
41}
42
43static struct clk_ops sh4202_emi_clk_ops = {
44 .recalc = emi_clk_recalc,
45};
46
47static struct clk sh4202_emi_clk = {
48 .name = "emi_clk",
49 .flags = CLK_ALWAYS_ENABLED,
50 .ops = &sh4202_emi_clk_ops,
51};
52
53static void femi_clk_recalc(struct clk *clk)
54{
55 int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
56 clk->rate = clk->parent->rate / frqcr3_divisors[idx];
57}
58
59static struct clk_ops sh4202_femi_clk_ops = {
60 .recalc = femi_clk_recalc,
61};
62
63static struct clk sh4202_femi_clk = {
64 .name = "femi_clk",
65 .flags = CLK_ALWAYS_ENABLED,
66 .ops = &sh4202_femi_clk_ops,
67};
68
69static void shoc_clk_init(struct clk *clk)
70{
71 int i;
72
73 /*
74 * For some reason, the shoc_clk seems to be set to some really
75 * insane value at boot (values outside of the allowable frequency
76 * range for instance). We deal with this by scaling it back down
77 * to something sensible just in case.
78 *
79 * Start scaling from the high end down until we find something
80 * that passes rate verification..
81 */
82 for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
83 int divisor = frqcr3_divisors[i];
84
85 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
86 break;
87 }
88
89 WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */
90}
91
92static void shoc_clk_recalc(struct clk *clk)
93{
94 int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
95 clk->rate = clk->parent->rate / frqcr3_divisors[idx];
96}
97
98static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
99{
100 struct clk *bclk = clk_get("bus_clk");
101 unsigned long bclk_rate = clk_get_rate(bclk);
102
103 clk_put(bclk);
104
105 if (rate > bclk_rate)
106 return 1;
107 if (rate > 66000000)
108 return 1;
109
110 return 0;
111}
112
113static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
114{
115 unsigned long frqcr3;
116 unsigned int tmp;
117
118 /* Make sure we have something sensible to switch to */
119 if (shoc_clk_verify_rate(clk, rate) != 0)
120 return -EINVAL;
121
122 tmp = frqcr3_lookup(clk, rate);
123
124 frqcr3 = ctrl_inl(CPG2_FRQCR3);
125 frqcr3 &= ~(0x0007 << 6);
126 frqcr3 |= tmp << 6;
127 ctrl_outl(frqcr3, CPG2_FRQCR3);
128
129 clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
130
131 return 0;
132}
133
134static struct clk_ops sh4202_shoc_clk_ops = {
135 .init = shoc_clk_init,
136 .recalc = shoc_clk_recalc,
137 .set_rate = shoc_clk_set_rate,
138};
139
140static struct clk sh4202_shoc_clk = {
141 .name = "shoc_clk",
142 .flags = CLK_ALWAYS_ENABLED,
143 .ops = &sh4202_shoc_clk_ops,
144};
145
146static struct clk *sh4202_onchip_clocks[] = {
147 &sh4202_emi_clk,
148 &sh4202_femi_clk,
149 &sh4202_shoc_clk,
150};
151
152static int __init sh4202_clk_init(void)
153{
154 struct clk *clk = clk_get("master_clk");
155 int i;
156
157 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
158 struct clk *clkp = sh4202_onchip_clocks[i];
159
160 clkp->parent = clk;
161 clk_register(clkp);
162 clk_enable(clkp);
163 }
164
165 /*
166 * Now that we have the rest of the clocks registered, we need to
167 * force the parent clock to propagate so that these clocks will
168 * automatically figure out their rate. We cheat by handing the
169 * parent clock its current rate and forcing child propagation.
170 */
171 clk_set_rate(clk, clk_get_rate(clk));
172
173 clk_put(clk);
174
175 return 0;
176}
177
178arch_initcall(sh4202_clk_init);
179
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
new file mode 100644
index 00000000000..dca9f87a12d
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -0,0 +1,80 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh4.c
3 *
4 * Generic SH-4 support for the clock framework
5 *
6 * Copyright (C) 2005 Paul Mundt
7 *
8 * FRQCR parsing hacked out of arch/sh/kernel/time.c
9 *
10 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
11 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
12 * Copyright (C) 2002, 2003, 2004 Paul Mundt
13 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <asm/clock.h>
22#include <asm/freq.h>
23#include <asm/io.h>
24
25static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
26#define bfc_divisors ifc_divisors /* Same */
27static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
28
29static void master_clk_init(struct clk *clk)
30{
31 clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007];
32}
33
34static struct clk_ops sh4_master_clk_ops = {
35 .init = master_clk_init,
36};
37
38static void module_clk_recalc(struct clk *clk)
39{
40 int idx = (ctrl_inw(FRQCR) & 0x0007);
41 clk->rate = clk->parent->rate / pfc_divisors[idx];
42}
43
44static struct clk_ops sh4_module_clk_ops = {
45 .recalc = module_clk_recalc,
46};
47
48static void bus_clk_recalc(struct clk *clk)
49{
50 int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007;
51 clk->rate = clk->parent->rate / bfc_divisors[idx];
52}
53
54static struct clk_ops sh4_bus_clk_ops = {
55 .recalc = bus_clk_recalc,
56};
57
58static void cpu_clk_recalc(struct clk *clk)
59{
60 int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007;
61 clk->rate = clk->parent->rate / ifc_divisors[idx];
62}
63
64static struct clk_ops sh4_cpu_clk_ops = {
65 .recalc = cpu_clk_recalc,
66};
67
68static struct clk_ops *sh4_clk_ops[] = {
69 &sh4_master_clk_ops,
70 &sh4_module_clk_ops,
71 &sh4_bus_clk_ops,
72 &sh4_cpu_clk_ops,
73};
74
75void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
76{
77 if (idx < ARRAY_SIZE(sh4_clk_ops))
78 *ops = sh4_clk_ops[idx];
79}
80
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh73180.c b/arch/sh/kernel/cpu/sh4/clock-sh73180.c
new file mode 100644
index 00000000000..2fa5cb2ae68
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/clock-sh73180.c
@@ -0,0 +1,81 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh73180.c
3 *
4 * SH73180 support for the clock framework
5 *
6 * Copyright (C) 2005 Paul Mundt
7 *
8 * FRQCR parsing hacked out of arch/sh/kernel/time.c
9 *
10 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
11 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
12 * Copyright (C) 2002, 2003, 2004 Paul Mundt
13 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <asm/clock.h>
22#include <asm/freq.h>
23#include <asm/io.h>
24
25/*
26 * SH73180 uses a common set of divisors, so this is quite simple..
27 */
28static int divisors[] = { 1, 2, 3, 4, 6, 8, 12, 16 };
29
30static void master_clk_init(struct clk *clk)
31{
32 clk->rate *= divisors[ctrl_inl(FRQCR) & 0x0007];
33}
34
35static struct clk_ops sh73180_master_clk_ops = {
36 .init = master_clk_init,
37};
38
39static void module_clk_recalc(struct clk *clk)
40{
41 int idx = (ctrl_inl(FRQCR) & 0x0007);
42 clk->rate = clk->parent->rate / divisors[idx];
43}
44
45static struct clk_ops sh73180_module_clk_ops = {
46 .recalc = module_clk_recalc,
47};
48
49static void bus_clk_recalc(struct clk *clk)
50{
51 int idx = (ctrl_inl(FRQCR) >> 12) & 0x0007;
52 clk->rate = clk->parent->rate / divisors[idx];
53}
54
55static struct clk_ops sh73180_bus_clk_ops = {
56 .recalc = bus_clk_recalc,
57};
58
59static void cpu_clk_recalc(struct clk *clk)
60{
61 int idx = (ctrl_inl(FRQCR) >> 20) & 0x0007;
62 clk->rate = clk->parent->rate / divisors[idx];
63}
64
65static struct clk_ops sh73180_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc,
67};
68
69static struct clk_ops *sh73180_clk_ops[] = {
70 &sh73180_master_clk_ops,
71 &sh73180_module_clk_ops,
72 &sh73180_bus_clk_ops,
73 &sh73180_cpu_clk_ops,
74};
75
76void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
77{
78 if (idx < ARRAY_SIZE(sh73180_clk_ops))
79 *ops = sh73180_clk_ops[idx];
80}
81
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh7770.c b/arch/sh/kernel/cpu/sh4/clock-sh7770.c
new file mode 100644
index 00000000000..c8694bac647
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/clock-sh7770.c
@@ -0,0 +1,73 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh7770.c
3 *
4 * SH7770 support for the clock framework
5 *
6 * Copyright (C) 2005 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <asm/clock.h>
15#include <asm/freq.h>
16#include <asm/io.h>
17
18static int ifc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 1 };
19static int bfc_divisors[] = { 1, 1, 1, 1, 1, 8,12, 1 };
20static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
21
22static void master_clk_init(struct clk *clk)
23{
24 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f];
25}
26
27static struct clk_ops sh7770_master_clk_ops = {
28 .init = master_clk_init,
29};
30
31static void module_clk_recalc(struct clk *clk)
32{
33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
34 clk->rate = clk->parent->rate / pfc_divisors[idx];
35}
36
37static struct clk_ops sh7770_module_clk_ops = {
38 .recalc = module_clk_recalc,
39};
40
41static void bus_clk_recalc(struct clk *clk)
42{
43 int idx = (ctrl_inl(FRQCR) & 0x000f);
44 clk->rate = clk->parent->rate / bfc_divisors[idx];
45}
46
47static struct clk_ops sh7770_bus_clk_ops = {
48 .recalc = bus_clk_recalc,
49};
50
51static void cpu_clk_recalc(struct clk *clk)
52{
53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
54 clk->rate = clk->parent->rate / ifc_divisors[idx];
55}
56
57static struct clk_ops sh7770_cpu_clk_ops = {
58 .recalc = cpu_clk_recalc,
59};
60
61static struct clk_ops *sh7770_clk_ops[] = {
62 &sh7770_master_clk_ops,
63 &sh7770_module_clk_ops,
64 &sh7770_bus_clk_ops,
65 &sh7770_cpu_clk_ops,
66};
67
68void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
69{
70 if (idx < ARRAY_SIZE(sh7770_clk_ops))
71 *ops = sh7770_clk_ops[idx];
72}
73
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh7780.c b/arch/sh/kernel/cpu/sh4/clock-sh7780.c
new file mode 100644
index 00000000000..93ad367342c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/clock-sh7780.c
@@ -0,0 +1,126 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh7780.c
3 *
4 * SH7780 support for the clock framework
5 *
6 * Copyright (C) 2005 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <asm/clock.h>
15#include <asm/freq.h>
16#include <asm/io.h>
17
18static int ifc_divisors[] = { 2, 4 };
19static int bfc_divisors[] = { 1, 1, 1, 8, 12, 16, 24, 1 };
20static int pfc_divisors[] = { 1, 24, 24, 1 };
21static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
22
23static void master_clk_init(struct clk *clk)
24{
25 clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003];
26}
27
28static struct clk_ops sh7780_master_clk_ops = {
29 .init = master_clk_init,
30};
31
32static void module_clk_recalc(struct clk *clk)
33{
34 int idx = (ctrl_inl(FRQCR) & 0x0003);
35 clk->rate = clk->parent->rate / pfc_divisors[idx];
36}
37
38static struct clk_ops sh7780_module_clk_ops = {
39 .recalc = module_clk_recalc,
40};
41
42static void bus_clk_recalc(struct clk *clk)
43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
45 clk->rate = clk->parent->rate / bfc_divisors[idx];
46}
47
48static struct clk_ops sh7780_bus_clk_ops = {
49 .recalc = bus_clk_recalc,
50};
51
52static void cpu_clk_recalc(struct clk *clk)
53{
54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
55 clk->rate = clk->parent->rate / ifc_divisors[idx];
56}
57
58static struct clk_ops sh7780_cpu_clk_ops = {
59 .recalc = cpu_clk_recalc,
60};
61
62static struct clk_ops *sh7780_clk_ops[] = {
63 &sh7780_master_clk_ops,
64 &sh7780_module_clk_ops,
65 &sh7780_bus_clk_ops,
66 &sh7780_cpu_clk_ops,
67};
68
69void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
70{
71 if (idx < ARRAY_SIZE(sh7780_clk_ops))
72 *ops = sh7780_clk_ops[idx];
73}
74
75static void shyway_clk_recalc(struct clk *clk)
76{
77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
78 clk->rate = clk->parent->rate / cfc_divisors[idx];
79}
80
81static struct clk_ops sh7780_shyway_clk_ops = {
82 .recalc = shyway_clk_recalc,
83};
84
85static struct clk sh7780_shyway_clk = {
86 .name = "shyway_clk",
87 .flags = CLK_ALWAYS_ENABLED,
88 .ops = &sh7780_shyway_clk_ops,
89};
90
91/*
92 * Additional SH7780-specific on-chip clocks that aren't already part of the
93 * clock framework
94 */
95static struct clk *sh7780_onchip_clocks[] = {
96 &sh7780_shyway_clk,
97};
98
99static int __init sh7780_clk_init(void)
100{
101 struct clk *clk = clk_get("master_clk");
102 int i;
103
104 for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
105 struct clk *clkp = sh7780_onchip_clocks[i];
106
107 clkp->parent = clk;
108 clk_register(clkp);
109 clk_enable(clkp);
110 }
111
112 /*
113 * Now that we have the rest of the clocks registered, we need to
114 * force the parent clock to propagate so that these clocks will
115 * automatically figure out their rate. We cheat by handing the
116 * parent clock its current rate and forcing child propagation.
117 */
118 clk_set_rate(clk, clk_get_rate(clk));
119
120 clk_put(clk);
121
122 return 0;
123}
124
125arch_initcall(sh7780_clk_init);
126
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 22:20:34 -0400