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-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/axonram.c2
-rw-r--r--arch/powerpc/sysdev/cpm1.c2
-rw-r--r--arch/powerpc/sysdev/cpm_common.c2
-rw-r--r--arch/powerpc/sysdev/dart_iommu.c2
-rw-r--r--arch/powerpc/sysdev/ehv_pic.c302
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c2
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c99
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c7
-rw-r--r--arch/powerpc/sysdev/fsl_soc.c29
-rw-r--r--arch/powerpc/sysdev/fsl_soc.h3
-rw-r--r--arch/powerpc/sysdev/grackle.c2
-rw-r--r--arch/powerpc/sysdev/ipic.c2
-rw-r--r--arch/powerpc/sysdev/mmio_nvram.c2
-rw-r--r--arch/powerpc/sysdev/mpc8xx_pic.c2
-rw-r--r--arch/powerpc/sysdev/mpic.c38
-rw-r--r--arch/powerpc/sysdev/mv64x60_udbg.c4
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c166
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_ic.c2
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_io.c2
-rw-r--r--arch/powerpc/sysdev/tsi108_dev.c2
-rw-r--r--arch/powerpc/sysdev/xics/icp-native.c11
22 files changed, 485 insertions, 199 deletions
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 0efa990e334..cf736ca0cf0 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
4 4
5mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o 5mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
6obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) 6obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
7obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o
7fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o 8fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
8obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o 9obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
9 10
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c
index bd0d54060b9..265f0f09395 100644
--- a/arch/powerpc/sysdev/axonram.c
+++ b/arch/powerpc/sysdev/axonram.c
@@ -203,7 +203,7 @@ static int axon_ram_probe(struct platform_device *device)
203 goto failed; 203 goto failed;
204 } 204 }
205 205
206 bank->size = resource.end - resource.start + 1; 206 bank->size = resource_size(&resource);
207 207
208 if (bank->size == 0) { 208 if (bank->size == 0) {
209 dev_err(&device->dev, "No DDR2 memory found for %s%d\n", 209 dev_err(&device->dev, "No DDR2 memory found for %s%d\n",
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 350787c83e2..5d7d59a43c4 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -148,7 +148,7 @@ unsigned int cpm_pic_init(void)
148 if (ret) 148 if (ret)
149 goto end; 149 goto end;
150 150
151 cpic_reg = ioremap(res.start, res.end - res.start + 1); 151 cpic_reg = ioremap(res.start, resource_size(&res));
152 if (cpic_reg == NULL) 152 if (cpic_reg == NULL)
153 goto end; 153 goto end;
154 154
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 2b69aa0315b..d55d0ad0dea 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -115,7 +115,7 @@ int cpm_muram_init(void)
115 max = r.end; 115 max = r.end;
116 116
117 rh_attach_region(&cpm_muram_info, r.start - muram_pbase, 117 rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
118 r.end - r.start + 1); 118 resource_size(&r));
119 } 119 }
120 120
121 muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1); 121 muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index 8e9e06a7ca5..4f2680f431b 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -239,7 +239,7 @@ static int __init dart_init(struct device_node *dart_node)
239 DARTMAP_RPNMASK); 239 DARTMAP_RPNMASK);
240 240
241 /* Map in DART registers */ 241 /* Map in DART registers */
242 dart = ioremap(r.start, r.end - r.start + 1); 242 dart = ioremap(r.start, resource_size(&r));
243 if (dart == NULL) 243 if (dart == NULL)
244 panic("DART: Cannot map registers!"); 244 panic("DART: Cannot map registers!");
245 245
diff --git a/arch/powerpc/sysdev/ehv_pic.c b/arch/powerpc/sysdev/ehv_pic.c
new file mode 100644
index 00000000000..af1a5df46b3
--- /dev/null
+++ b/arch/powerpc/sysdev/ehv_pic.c
@@ -0,0 +1,302 @@
1/*
2 * Driver for ePAPR Embedded Hypervisor PIC
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/smp.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21#include <linux/of.h>
22
23#include <asm/io.h>
24#include <asm/irq.h>
25#include <asm/smp.h>
26#include <asm/machdep.h>
27#include <asm/ehv_pic.h>
28#include <asm/fsl_hcalls.h>
29
30#include "../../../kernel/irq/settings.h"
31
32static struct ehv_pic *global_ehv_pic;
33static DEFINE_SPINLOCK(ehv_pic_lock);
34
35static u32 hwirq_intspec[NR_EHV_PIC_INTS];
36static u32 __iomem *mpic_percpu_base_vaddr;
37
38#define IRQ_TYPE_MPIC_DIRECT 4
39#define MPIC_EOI 0x00B0
40
41/*
42 * Linux descriptor level callbacks
43 */
44
45void ehv_pic_unmask_irq(struct irq_data *d)
46{
47 unsigned int src = virq_to_hw(d->irq);
48
49 ev_int_set_mask(src, 0);
50}
51
52void ehv_pic_mask_irq(struct irq_data *d)
53{
54 unsigned int src = virq_to_hw(d->irq);
55
56 ev_int_set_mask(src, 1);
57}
58
59void ehv_pic_end_irq(struct irq_data *d)
60{
61 unsigned int src = virq_to_hw(d->irq);
62
63 ev_int_eoi(src);
64}
65
66void ehv_pic_direct_end_irq(struct irq_data *d)
67{
68 out_be32(mpic_percpu_base_vaddr + MPIC_EOI / 4, 0);
69}
70
71int ehv_pic_set_affinity(struct irq_data *d, const struct cpumask *dest,
72 bool force)
73{
74 unsigned int src = virq_to_hw(d->irq);
75 unsigned int config, prio, cpu_dest;
76 int cpuid = irq_choose_cpu(dest);
77 unsigned long flags;
78
79 spin_lock_irqsave(&ehv_pic_lock, flags);
80 ev_int_get_config(src, &config, &prio, &cpu_dest);
81 ev_int_set_config(src, config, prio, cpuid);
82 spin_unlock_irqrestore(&ehv_pic_lock, flags);
83
84 return 0;
85}
86
87static unsigned int ehv_pic_type_to_vecpri(unsigned int type)
88{
89 /* Now convert sense value */
90
91 switch (type & IRQ_TYPE_SENSE_MASK) {
92 case IRQ_TYPE_EDGE_RISING:
93 return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
94 EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
95
96 case IRQ_TYPE_EDGE_FALLING:
97 case IRQ_TYPE_EDGE_BOTH:
98 return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
99 EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
100
101 case IRQ_TYPE_LEVEL_HIGH:
102 return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
103 EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
104
105 case IRQ_TYPE_LEVEL_LOW:
106 default:
107 return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
108 EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
109 }
110}
111
112int ehv_pic_set_irq_type(struct irq_data *d, unsigned int flow_type)
113{
114 unsigned int src = virq_to_hw(d->irq);
115 struct irq_desc *desc = irq_to_desc(d->irq);
116 unsigned int vecpri, vold, vnew, prio, cpu_dest;
117 unsigned long flags;
118
119 if (flow_type == IRQ_TYPE_NONE)
120 flow_type = IRQ_TYPE_LEVEL_LOW;
121
122 irq_settings_clr_level(desc);
123 irq_settings_set_trigger_mask(desc, flow_type);
124 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
125 irq_settings_set_level(desc);
126
127 vecpri = ehv_pic_type_to_vecpri(flow_type);
128
129 spin_lock_irqsave(&ehv_pic_lock, flags);
130 ev_int_get_config(src, &vold, &prio, &cpu_dest);
131 vnew = vold & ~(EHV_PIC_INFO(VECPRI_POLARITY_MASK) |
132 EHV_PIC_INFO(VECPRI_SENSE_MASK));
133 vnew |= vecpri;
134
135 /*
136 * TODO : Add specific interface call for platform to set
137 * individual interrupt priorities.
138 * platform currently using static/default priority for all ints
139 */
140
141 prio = 8;
142
143 ev_int_set_config(src, vecpri, prio, cpu_dest);
144
145 spin_unlock_irqrestore(&ehv_pic_lock, flags);
146 return 0;
147}
148
149static struct irq_chip ehv_pic_irq_chip = {
150 .irq_mask = ehv_pic_mask_irq,
151 .irq_unmask = ehv_pic_unmask_irq,
152 .irq_eoi = ehv_pic_end_irq,
153 .irq_set_type = ehv_pic_set_irq_type,
154};
155
156static struct irq_chip ehv_pic_direct_eoi_irq_chip = {
157 .irq_mask = ehv_pic_mask_irq,
158 .irq_unmask = ehv_pic_unmask_irq,
159 .irq_eoi = ehv_pic_direct_end_irq,
160 .irq_set_type = ehv_pic_set_irq_type,
161};
162
163/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
164unsigned int ehv_pic_get_irq(void)
165{
166 int irq;
167
168 BUG_ON(global_ehv_pic == NULL);
169
170 if (global_ehv_pic->coreint_flag)
171 irq = mfspr(SPRN_EPR); /* if core int mode */
172 else
173 ev_int_iack(0, &irq); /* legacy mode */
174
175 if (irq == 0xFFFF) /* 0xFFFF --> no irq is pending */
176 return NO_IRQ;
177
178 /*
179 * this will also setup revmap[] in the slow path for the first
180 * time, next calls will always use fast path by indexing revmap
181 */
182 return irq_linear_revmap(global_ehv_pic->irqhost, irq);
183}
184
185static int ehv_pic_host_match(struct irq_host *h, struct device_node *node)
186{
187 /* Exact match, unless ehv_pic node is NULL */
188 return h->of_node == NULL || h->of_node == node;
189}
190
191static int ehv_pic_host_map(struct irq_host *h, unsigned int virq,
192 irq_hw_number_t hw)
193{
194 struct ehv_pic *ehv_pic = h->host_data;
195 struct irq_chip *chip;
196
197 /* Default chip */
198 chip = &ehv_pic->hc_irq;
199
200 if (mpic_percpu_base_vaddr)
201 if (hwirq_intspec[hw] & IRQ_TYPE_MPIC_DIRECT)
202 chip = &ehv_pic_direct_eoi_irq_chip;
203
204 irq_set_chip_data(virq, chip);
205 /*
206 * using handle_fasteoi_irq as our irq handler, this will
207 * only call the eoi callback and suitable for the MPIC
208 * controller which set ISR/IPR automatically and clear the
209 * highest priority active interrupt in ISR/IPR when we do
210 * a specific eoi
211 */
212 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
213
214 /* Set default irq type */
215 irq_set_irq_type(virq, IRQ_TYPE_NONE);
216
217 return 0;
218}
219
220static int ehv_pic_host_xlate(struct irq_host *h, struct device_node *ct,
221 const u32 *intspec, unsigned int intsize,
222 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
223
224{
225 /*
226 * interrupt sense values coming from the guest device tree
227 * interrupt specifiers can have four possible sense and
228 * level encoding information and they need to
229 * be translated between firmware type & linux type.
230 */
231
232 static unsigned char map_of_senses_to_linux_irqtype[4] = {
233 IRQ_TYPE_EDGE_FALLING,
234 IRQ_TYPE_EDGE_RISING,
235 IRQ_TYPE_LEVEL_LOW,
236 IRQ_TYPE_LEVEL_HIGH,
237 };
238
239 *out_hwirq = intspec[0];
240 if (intsize > 1) {
241 hwirq_intspec[intspec[0]] = intspec[1];
242 *out_flags = map_of_senses_to_linux_irqtype[intspec[1] &
243 ~IRQ_TYPE_MPIC_DIRECT];
244 } else {
245 *out_flags = IRQ_TYPE_NONE;
246 }
247
248 return 0;
249}
250
251static struct irq_host_ops ehv_pic_host_ops = {
252 .match = ehv_pic_host_match,
253 .map = ehv_pic_host_map,
254 .xlate = ehv_pic_host_xlate,
255};
256
257void __init ehv_pic_init(void)
258{
259 struct device_node *np, *np2;
260 struct ehv_pic *ehv_pic;
261 int coreint_flag = 1;
262
263 np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
264 if (!np) {
265 pr_err("ehv_pic_init: could not find epapr,hv-pic node\n");
266 return;
267 }
268
269 if (!of_find_property(np, "has-external-proxy", NULL))
270 coreint_flag = 0;
271
272 ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
273 if (!ehv_pic) {
274 of_node_put(np);
275 return;
276 }
277
278 ehv_pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
279 NR_EHV_PIC_INTS, &ehv_pic_host_ops, 0);
280
281 if (!ehv_pic->irqhost) {
282 of_node_put(np);
283 return;
284 }
285
286 np2 = of_find_compatible_node(NULL, NULL, "fsl,hv-mpic-per-cpu");
287 if (np2) {
288 mpic_percpu_base_vaddr = of_iomap(np2, 0);
289 if (!mpic_percpu_base_vaddr)
290 pr_err("ehv_pic_init: of_iomap failed\n");
291
292 of_node_put(np2);
293 }
294
295 ehv_pic->irqhost->host_data = ehv_pic;
296 ehv_pic->hc_irq = ehv_pic_irq_chip;
297 ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
298 ehv_pic->coreint_flag = coreint_flag;
299
300 global_ehv_pic = ehv_pic;
301 irq_set_default_host(global_ehv_pic->irqhost);
302}
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 92e78333c47..419a77239bd 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -349,7 +349,7 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
349 goto error_out; 349 goto error_out;
350 } 350 }
351 351
352 msi->msi_regs = ioremap(res.start, res.end - res.start + 1); 352 msi->msi_regs = ioremap(res.start, resource_size(&res));
353 if (!msi->msi_regs) { 353 if (!msi->msi_regs) {
354 dev_err(&dev->dev, "ioremap problem failed\n"); 354 dev_err(&dev->dev, "ioremap problem failed\n");
355 goto error_out; 355 goto error_out;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 68ca9290df9..4ce547e0047 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -38,10 +38,17 @@ static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38 38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{ 40{
41 u8 progif;
42
41 /* if we aren't a PCIe don't bother */ 43 /* if we aren't a PCIe don't bother */
42 if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) 44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
43 return; 45 return;
44 46
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
49 if (progif & 0x1)
50 return;
51
45 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
46 fsl_pcie_bus_fixup = 1; 53 fsl_pcie_bus_fixup = 1;
47 return; 54 return;
@@ -64,7 +71,7 @@ static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
64{ 71{
65 resource_size_t pci_addr = res->start - offset; 72 resource_size_t pci_addr = res->start - offset;
66 resource_size_t phys_addr = res->start; 73 resource_size_t phys_addr = res->start;
67 resource_size_t size = res->end - res->start + 1; 74 resource_size_t size = resource_size(res);
68 u32 flags = 0x80044000; /* enable & mem R/W */ 75 u32 flags = 0x80044000; /* enable & mem R/W */
69 unsigned int i; 76 unsigned int i;
70 77
@@ -108,7 +115,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
108 char *name = hose->dn->full_name; 115 char *name = hose->dn->full_name;
109 116
110 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 117 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
111 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); 118 (u64)rsrc->start, (u64)resource_size(rsrc));
112 119
113 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) { 120 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
114 win_idx = 2; 121 win_idx = 2;
@@ -116,7 +123,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
116 end_idx = 3; 123 end_idx = 3;
117 } 124 }
118 125
119 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 126 pci = ioremap(rsrc->start, resource_size(rsrc));
120 if (!pci) { 127 if (!pci) {
121 dev_err(hose->parent, "Unable to map ATMU registers\n"); 128 dev_err(hose->parent, "Unable to map ATMU registers\n");
122 return; 129 return;
@@ -153,9 +160,9 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
153 } else { 160 } else {
154 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 161 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
155 "phy base 0x%016llx.\n", 162 "phy base 0x%016llx.\n",
156 (u64)hose->io_resource.start, 163 (u64)hose->io_resource.start,
157 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, 164 (u64)resource_size(&hose->io_resource),
158 (u64)hose->io_base_phys); 165 (u64)hose->io_base_phys);
159 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 166 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
160 out_be32(&pci->pow[j].potear, 0); 167 out_be32(&pci->pow[j].potear, 0);
161 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 168 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
@@ -323,6 +330,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
323 struct pci_controller *hose; 330 struct pci_controller *hose;
324 struct resource rsrc; 331 struct resource rsrc;
325 const int *bus_range; 332 const int *bus_range;
333 u8 progif;
326 334
327 if (!of_device_is_available(dev)) { 335 if (!of_device_is_available(dev)) {
328 pr_warning("%s: disabled\n", dev->full_name); 336 pr_warning("%s: disabled\n", dev->full_name);
@@ -343,7 +351,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
343 printk(KERN_WARNING "Can't get bus-range for %s, assume" 351 printk(KERN_WARNING "Can't get bus-range for %s, assume"
344 " bus 0\n", dev->full_name); 352 " bus 0\n", dev->full_name);
345 353
346 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 354 pci_add_flags(PCI_REASSIGN_ALL_BUS);
347 hose = pcibios_alloc_controller(dev); 355 hose = pcibios_alloc_controller(dev);
348 if (!hose) 356 if (!hose)
349 return -ENOMEM; 357 return -ENOMEM;
@@ -353,6 +361,18 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
353 361
354 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 362 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
355 PPC_INDIRECT_TYPE_BIG_ENDIAN); 363 PPC_INDIRECT_TYPE_BIG_ENDIAN);
364
365 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
366 if ((progif & 1) == 1) {
367 /* unmap cfg_data & cfg_addr separately if not on same page */
368 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
369 ((unsigned long)hose->cfg_addr & PAGE_MASK))
370 iounmap(hose->cfg_data);
371 iounmap(hose->cfg_addr);
372 pcibios_free_controller(hose);
373 return 0;
374 }
375
356 setup_pci_cmd(hose); 376 setup_pci_cmd(hose);
357 377
358 /* check PCI express link status */ 378 /* check PCI express link status */
@@ -380,70 +400,11 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
380 400
381 return 0; 401 return 0;
382} 402}
383
384DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
385DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
386DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
387DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
388DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
389DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
390DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
391DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
392DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
393DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
394DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
395DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
396DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
397DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
398DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
399DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
400DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
401DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
402DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
403DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
404DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
405DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
406DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
407DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
408DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
409DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
410DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
411DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
412DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
413DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
414DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
415DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
416DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
417DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
418DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
419DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
420DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
421DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
422DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header);
423DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header);
424DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header);
425DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header);
426DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
427DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
428DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
429DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
430DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header);
431DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header);
432DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header);
433DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header);
434#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 403#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
435 404
436#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 405DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
437DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
438DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
439DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
440DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
441DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
442DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
443DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
444DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
445DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
446 406
407#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
447struct mpc83xx_pcie_priv { 408struct mpc83xx_pcie_priv {
448 void __iomem *cfg_type0; 409 void __iomem *cfg_type0;
449 void __iomem *cfg_type1; 410 void __iomem *cfg_type1;
@@ -679,7 +640,7 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
679 " bus 0\n", dev->full_name); 640 " bus 0\n", dev->full_name);
680 } 641 }
681 642
682 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 643 pci_add_flags(PCI_REASSIGN_ALL_BUS);
683 hose = pcibios_alloc_controller(dev); 644 hose = pcibios_alloc_controller(dev);
684 if (!hose) 645 if (!hose)
685 return -ENOMEM; 646 return -ENOMEM;
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index b3fd081d56f..c65f75aa7ff 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -54,6 +54,7 @@
54#define ODSR_CLEAR 0x1c00 54#define ODSR_CLEAR 0x1c00
55#define LTLEECSR_ENABLE_ALL 0xFFC000FC 55#define LTLEECSR_ENABLE_ALL 0xFFC000FC
56#define ESCSR_CLEAR 0x07120204 56#define ESCSR_CLEAR 0x07120204
57#define IECSR_CLEAR 0x80000000
57 58
58#define RIO_PORT1_EDCSR 0x0640 59#define RIO_PORT1_EDCSR 0x0640
59#define RIO_PORT2_EDCSR 0x0680 60#define RIO_PORT2_EDCSR 0x0680
@@ -1089,11 +1090,11 @@ static void port_error_handler(struct rio_mport *port, int offset)
1089 1090
1090 if (offset == 0) { 1091 if (offset == 0) {
1091 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0); 1092 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
1092 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), 0); 1093 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
1093 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR); 1094 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
1094 } else { 1095 } else {
1095 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0); 1096 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
1096 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), 0); 1097 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
1097 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); 1098 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
1098 } 1099 }
1099} 1100}
@@ -1524,7 +1525,7 @@ int fsl_rio_setup(struct platform_device *dev)
1524 port->priv = priv; 1525 port->priv = priv;
1525 port->phys_efptr = 0x100; 1526 port->phys_efptr = 0x100;
1526 1527
1527 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); 1528 priv->regs_win = ioremap(regs.start, resource_size(&regs));
1528 rio_regs_win = priv->regs_win; 1529 rio_regs_win = priv->regs_win;
1529 1530
1530 /* Probe the master port phy type */ 1531 /* Probe the master port phy type */
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 19e5015e039..2d66275e489 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -32,7 +32,7 @@
32#include <linux/fs_uart_pd.h> 32#include <linux/fs_uart_pd.h>
33 33
34#include <asm/system.h> 34#include <asm/system.h>
35#include <asm/atomic.h> 35#include <linux/atomic.h>
36#include <asm/io.h> 36#include <asm/io.h>
37#include <asm/irq.h> 37#include <asm/irq.h>
38#include <asm/time.h> 38#include <asm/time.h>
@@ -41,6 +41,7 @@
41#include <sysdev/fsl_soc.h> 41#include <sysdev/fsl_soc.h>
42#include <mm/mmu_decl.h> 42#include <mm/mmu_decl.h>
43#include <asm/cpm2.h> 43#include <asm/cpm2.h>
44#include <asm/fsl_hcalls.h> /* For the Freescale hypervisor */
44 45
45extern void init_fcc_ioports(struct fs_platform_info*); 46extern void init_fcc_ioports(struct fs_platform_info*);
46extern void init_fec_ioports(struct fs_platform_info*); 47extern void init_fec_ioports(struct fs_platform_info*);
@@ -252,3 +253,29 @@ void fsl_rstcr_restart(char *cmd)
252struct platform_diu_data_ops diu_ops; 253struct platform_diu_data_ops diu_ops;
253EXPORT_SYMBOL(diu_ops); 254EXPORT_SYMBOL(diu_ops);
254#endif 255#endif
256
257/*
258 * Restart the current partition
259 *
260 * This function should be assigned to the ppc_md.restart function pointer,
261 * to initiate a partition restart when we're running under the Freescale
262 * hypervisor.
263 */
264void fsl_hv_restart(char *cmd)
265{
266 pr_info("hv restart\n");
267 fh_partition_restart(-1);
268}
269
270/*
271 * Halt the current partition
272 *
273 * This function should be assigned to the ppc_md.power_off and ppc_md.halt
274 * function pointers, to shut down the partition when we're running under
275 * the Freescale hypervisor.
276 */
277void fsl_hv_halt(void)
278{
279 pr_info("hv exit\n");
280 fh_partition_stop(-1);
281}
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 53609489a62..2ece02beb8f 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -36,5 +36,8 @@ struct platform_diu_data_ops {
36extern struct platform_diu_data_ops diu_ops; 36extern struct platform_diu_data_ops diu_ops;
37#endif 37#endif
38 38
39void fsl_hv_restart(char *cmd);
40void fsl_hv_halt(void);
41
39#endif 42#endif
40#endif 43#endif
diff --git a/arch/powerpc/sysdev/grackle.c b/arch/powerpc/sysdev/grackle.c
index cf27df6e508..08abe91ae79 100644
--- a/arch/powerpc/sysdev/grackle.c
+++ b/arch/powerpc/sysdev/grackle.c
@@ -57,7 +57,7 @@ void __init setup_grackle(struct pci_controller *hose)
57{ 57{
58 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); 58 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
59 if (of_machine_is_compatible("PowerMac1,1")) 59 if (of_machine_is_compatible("PowerMac1,1"))
60 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 60 pci_add_flags(PCI_REASSIGN_ALL_BUS);
61 if (of_machine_is_compatible("AAPL,PowerBook1998")) 61 if (of_machine_is_compatible("AAPL,PowerBook1998"))
62 grackle_set_loop_snoop(hose, 1); 62 grackle_set_loop_snoop(hose, 1);
63#if 0 /* Disabled for now, HW problems ??? */ 63#if 0 /* Disabled for now, HW problems ??? */
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 7367d17364c..95da897f05a 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -736,7 +736,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
736 return NULL; 736 return NULL;
737 } 737 }
738 738
739 ipic->regs = ioremap(res.start, res.end - res.start + 1); 739 ipic->regs = ioremap(res.start, resource_size(&res));
740 740
741 ipic->irqhost->host_data = ipic; 741 ipic->irqhost->host_data = ipic;
742 742
diff --git a/arch/powerpc/sysdev/mmio_nvram.c b/arch/powerpc/sysdev/mmio_nvram.c
index ddc877a3a23..69f5814ae6d 100644
--- a/arch/powerpc/sysdev/mmio_nvram.c
+++ b/arch/powerpc/sysdev/mmio_nvram.c
@@ -129,7 +129,7 @@ int __init mmio_nvram_init(void)
129 goto out; 129 goto out;
130 } 130 }
131 nvram_addr = r.start; 131 nvram_addr = r.start;
132 mmio_nvram_len = r.end - r.start + 1; 132 mmio_nvram_len = resource_size(&r);
133 if ( (!mmio_nvram_len) || (!nvram_addr) ) { 133 if ( (!mmio_nvram_len) || (!nvram_addr) ) {
134 printk(KERN_WARNING "nvram: address or length is 0\n"); 134 printk(KERN_WARNING "nvram: address or length is 0\n");
135 ret = -EIO; 135 ret = -EIO;
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index 20924f2246f..22e48e2d71f 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -166,7 +166,7 @@ int mpc8xx_pic_init(void)
166 if (ret) 166 if (ret)
167 goto out; 167 goto out;
168 168
169 siu_reg = ioremap(res.start, res.end - res.start + 1); 169 siu_reg = ioremap(res.start, resource_size(&res));
170 if (siu_reg == NULL) { 170 if (siu_reg == NULL) {
171 ret = -EINVAL; 171 ret = -EINVAL;
172 goto out; 172 goto out;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 58d7a534f87..d5d3ff3d757 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -598,42 +598,6 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
598 598
599#endif /* CONFIG_MPIC_U3_HT_IRQS */ 599#endif /* CONFIG_MPIC_U3_HT_IRQS */
600 600
601#ifdef CONFIG_SMP
602static int irq_choose_cpu(const struct cpumask *mask)
603{
604 int cpuid;
605
606 if (cpumask_equal(mask, cpu_all_mask)) {
607 static int irq_rover = 0;
608 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
609 unsigned long flags;
610
611 /* Round-robin distribution... */
612 do_round_robin:
613 raw_spin_lock_irqsave(&irq_rover_lock, flags);
614
615 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
616 if (irq_rover >= nr_cpu_ids)
617 irq_rover = cpumask_first(cpu_online_mask);
618
619 cpuid = irq_rover;
620
621 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
622 } else {
623 cpuid = cpumask_first_and(mask, cpu_online_mask);
624 if (cpuid >= nr_cpu_ids)
625 goto do_round_robin;
626 }
627
628 return get_hard_smp_processor_id(cpuid);
629}
630#else
631static int irq_choose_cpu(const struct cpumask *mask)
632{
633 return hard_smp_processor_id();
634}
635#endif
636
637/* Find an mpic associated with a given linux interrupt */ 601/* Find an mpic associated with a given linux interrupt */
638static struct mpic *mpic_find(unsigned int irq) 602static struct mpic *mpic_find(unsigned int irq)
639{ 603{
@@ -849,7 +813,7 @@ static void mpic_unmask_tm(struct irq_data *d)
849 struct mpic *mpic = mpic_from_irq_data(d); 813 struct mpic *mpic = mpic_from_irq_data(d);
850 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; 814 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
851 815
852 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src); 816 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
853 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); 817 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
854 mpic_tm_read(src); 818 mpic_tm_read(src);
855} 819}
diff --git a/arch/powerpc/sysdev/mv64x60_udbg.c b/arch/powerpc/sysdev/mv64x60_udbg.c
index 2792dc8b038..50a81387e9b 100644
--- a/arch/powerpc/sysdev/mv64x60_udbg.c
+++ b/arch/powerpc/sysdev/mv64x60_udbg.c
@@ -125,11 +125,11 @@ static void mv64x60_udbg_init(void)
125 125
126 of_node_put(np); 126 of_node_put(np);
127 127
128 mpsc_base = ioremap(r[0].start, r[0].end - r[0].start + 1); 128 mpsc_base = ioremap(r[0].start, resource_size(&r[0]));
129 if (!mpsc_base) 129 if (!mpsc_base)
130 return; 130 return;
131 131
132 mpsc_intr_cause = ioremap(r[1].start, r[1].end - r[1].start + 1); 132 mpsc_intr_cause = ioremap(r[1].start, resource_size(&r[1]));
133 if (!mpsc_intr_cause) { 133 if (!mpsc_intr_cause) {
134 iounmap(mpsc_base); 134 iounmap(mpsc_base);
135 return; 135 return;
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 156aa7d3625..dbfe96bc878 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -265,7 +265,7 @@ static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
265 if (ppc4xx_setup_one_pci_PMM(hose, reg, 265 if (ppc4xx_setup_one_pci_PMM(hose, reg,
266 res->start, 266 res->start,
267 res->start - hose->pci_mem_offset, 267 res->start - hose->pci_mem_offset,
268 res->end + 1 - res->start, 268 resource_size(res),
269 res->flags, 269 res->flags,
270 j) == 0) { 270 j) == 0) {
271 j++; 271 j++;
@@ -290,7 +290,7 @@ static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
290 void __iomem *reg, 290 void __iomem *reg,
291 const struct resource *res) 291 const struct resource *res)
292{ 292{
293 resource_size_t size = res->end - res->start + 1; 293 resource_size_t size = resource_size(res);
294 u32 sa; 294 u32 sa;
295 295
296 /* Calculate window size */ 296 /* Calculate window size */
@@ -349,7 +349,7 @@ static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
349 bus_range = of_get_property(np, "bus-range", NULL); 349 bus_range = of_get_property(np, "bus-range", NULL);
350 350
351 /* Map registers */ 351 /* Map registers */
352 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); 352 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
353 if (reg == NULL) { 353 if (reg == NULL) {
354 printk(KERN_ERR "%s: Can't map registers !", np->full_name); 354 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
355 goto fail; 355 goto fail;
@@ -465,7 +465,7 @@ static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
465 if (ppc4xx_setup_one_pcix_POM(hose, reg, 465 if (ppc4xx_setup_one_pcix_POM(hose, reg,
466 res->start, 466 res->start,
467 res->start - hose->pci_mem_offset, 467 res->start - hose->pci_mem_offset,
468 res->end + 1 - res->start, 468 resource_size(res),
469 res->flags, 469 res->flags,
470 j) == 0) { 470 j) == 0) {
471 j++; 471 j++;
@@ -492,7 +492,7 @@ static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
492 int big_pim, 492 int big_pim,
493 int enable_msi_hole) 493 int enable_msi_hole)
494{ 494{
495 resource_size_t size = res->end - res->start + 1; 495 resource_size_t size = resource_size(res);
496 u32 sa; 496 u32 sa;
497 497
498 /* RAM is always at 0 */ 498 /* RAM is always at 0 */
@@ -555,7 +555,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
555 bus_range = of_get_property(np, "bus-range", NULL); 555 bus_range = of_get_property(np, "bus-range", NULL);
556 556
557 /* Map registers */ 557 /* Map registers */
558 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); 558 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
559 if (reg == NULL) { 559 if (reg == NULL) {
560 printk(KERN_ERR "%s: Can't map registers !", np->full_name); 560 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
561 goto fail; 561 goto fail;
@@ -650,10 +650,73 @@ struct ppc4xx_pciex_hwops
650 int (*core_init)(struct device_node *np); 650 int (*core_init)(struct device_node *np);
651 int (*port_init_hw)(struct ppc4xx_pciex_port *port); 651 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
652 int (*setup_utl)(struct ppc4xx_pciex_port *port); 652 int (*setup_utl)(struct ppc4xx_pciex_port *port);
653 void (*check_link)(struct ppc4xx_pciex_port *port);
653}; 654};
654 655
655static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops; 656static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
656 657
658static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
659 unsigned int sdr_offset,
660 unsigned int mask,
661 unsigned int value,
662 int timeout_ms)
663{
664 u32 val;
665
666 while(timeout_ms--) {
667 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
668 if ((val & mask) == value) {
669 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
670 port->index, sdr_offset, timeout_ms, val);
671 return 0;
672 }
673 msleep(1);
674 }
675 return -1;
676}
677
678static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
679{
680 /* Wait for reset to complete */
681 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
682 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
683 port->index);
684 return -1;
685 }
686 return 0;
687}
688
689
690static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
691{
692 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
693
694 /* Check for card presence detect if supported, if not, just wait for
695 * link unconditionally.
696 *
697 * note that we don't fail if there is no link, we just filter out
698 * config space accesses. That way, it will be easier to implement
699 * hotplug later on.
700 */
701 if (!port->has_ibpre ||
702 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
703 1 << 28, 1 << 28, 100)) {
704 printk(KERN_INFO
705 "PCIE%d: Device detected, waiting for link...\n",
706 port->index);
707 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
708 0x1000, 0x1000, 2000))
709 printk(KERN_WARNING
710 "PCIE%d: Link up failed\n", port->index);
711 else {
712 printk(KERN_INFO
713 "PCIE%d: link is up !\n", port->index);
714 port->link = 1;
715 }
716 } else
717 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
718}
719
657#ifdef CONFIG_44x 720#ifdef CONFIG_44x
658 721
659/* Check various reset bits of the 440SPe PCIe core */ 722/* Check various reset bits of the 440SPe PCIe core */
@@ -806,7 +869,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
806 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 869 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
807 (1 << 24) | (1 << 16), 1 << 12); 870 (1 << 24) | (1 << 16), 1 << 12);
808 871
809 return 0; 872 return ppc4xx_pciex_port_reset_sdr(port);
810} 873}
811 874
812static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 875static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
@@ -856,6 +919,7 @@ static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
856 .core_init = ppc440spe_pciex_core_init, 919 .core_init = ppc440spe_pciex_core_init,
857 .port_init_hw = ppc440speA_pciex_init_port_hw, 920 .port_init_hw = ppc440speA_pciex_init_port_hw,
858 .setup_utl = ppc440speA_pciex_init_utl, 921 .setup_utl = ppc440speA_pciex_init_utl,
922 .check_link = ppc4xx_pciex_check_link_sdr,
859}; 923};
860 924
861static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = 925static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
@@ -863,6 +927,7 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
863 .core_init = ppc440spe_pciex_core_init, 927 .core_init = ppc440spe_pciex_core_init,
864 .port_init_hw = ppc440speB_pciex_init_port_hw, 928 .port_init_hw = ppc440speB_pciex_init_port_hw,
865 .setup_utl = ppc440speB_pciex_init_utl, 929 .setup_utl = ppc440speB_pciex_init_utl,
930 .check_link = ppc4xx_pciex_check_link_sdr,
866}; 931};
867 932
868static int __init ppc460ex_pciex_core_init(struct device_node *np) 933static int __init ppc460ex_pciex_core_init(struct device_node *np)
@@ -944,7 +1009,7 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
944 1009
945 port->has_ibpre = 1; 1010 port->has_ibpre = 1;
946 1011
947 return 0; 1012 return ppc4xx_pciex_port_reset_sdr(port);
948} 1013}
949 1014
950static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 1015static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -972,6 +1037,7 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
972 .core_init = ppc460ex_pciex_core_init, 1037 .core_init = ppc460ex_pciex_core_init,
973 .port_init_hw = ppc460ex_pciex_init_port_hw, 1038 .port_init_hw = ppc460ex_pciex_init_port_hw,
974 .setup_utl = ppc460ex_pciex_init_utl, 1039 .setup_utl = ppc460ex_pciex_init_utl,
1040 .check_link = ppc4xx_pciex_check_link_sdr,
975}; 1041};
976 1042
977static int __init ppc460sx_pciex_core_init(struct device_node *np) 1043static int __init ppc460sx_pciex_core_init(struct device_node *np)
@@ -1075,7 +1141,7 @@ static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1075 1141
1076 port->has_ibpre = 1; 1142 port->has_ibpre = 1;
1077 1143
1078 return 0; 1144 return ppc4xx_pciex_port_reset_sdr(port);
1079} 1145}
1080 1146
1081static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) 1147static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -1089,6 +1155,7 @@ static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1089 .core_init = ppc460sx_pciex_core_init, 1155 .core_init = ppc460sx_pciex_core_init,
1090 .port_init_hw = ppc460sx_pciex_init_port_hw, 1156 .port_init_hw = ppc460sx_pciex_init_port_hw,
1091 .setup_utl = ppc460sx_pciex_init_utl, 1157 .setup_utl = ppc460sx_pciex_init_utl,
1158 .check_link = ppc4xx_pciex_check_link_sdr,
1092}; 1159};
1093 1160
1094#endif /* CONFIG_44x */ 1161#endif /* CONFIG_44x */
@@ -1154,7 +1221,7 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1154 1221
1155 port->has_ibpre = 1; 1222 port->has_ibpre = 1;
1156 1223
1157 return 0; 1224 return ppc4xx_pciex_port_reset_sdr(port);
1158} 1225}
1159 1226
1160static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 1227static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
@@ -1183,11 +1250,11 @@ static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1183 .core_init = ppc405ex_pciex_core_init, 1250 .core_init = ppc405ex_pciex_core_init,
1184 .port_init_hw = ppc405ex_pciex_init_port_hw, 1251 .port_init_hw = ppc405ex_pciex_init_port_hw,
1185 .setup_utl = ppc405ex_pciex_init_utl, 1252 .setup_utl = ppc405ex_pciex_init_utl,
1253 .check_link = ppc4xx_pciex_check_link_sdr,
1186}; 1254};
1187 1255
1188#endif /* CONFIG_40x */ 1256#endif /* CONFIG_40x */
1189 1257
1190
1191/* Check that the core has been initied and if not, do it */ 1258/* Check that the core has been initied and if not, do it */
1192static int __init ppc4xx_pciex_check_core_init(struct device_node *np) 1259static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1193{ 1260{
@@ -1261,26 +1328,6 @@ static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port
1261 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); 1328 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1262} 1329}
1263 1330
1264static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1265 unsigned int sdr_offset,
1266 unsigned int mask,
1267 unsigned int value,
1268 int timeout_ms)
1269{
1270 u32 val;
1271
1272 while(timeout_ms--) {
1273 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1274 if ((val & mask) == value) {
1275 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1276 port->index, sdr_offset, timeout_ms, val);
1277 return 0;
1278 }
1279 msleep(1);
1280 }
1281 return -1;
1282}
1283
1284static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) 1331static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1285{ 1332{
1286 int rc = 0; 1333 int rc = 0;
@@ -1291,40 +1338,8 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1291 if (rc != 0) 1338 if (rc != 0)
1292 return rc; 1339 return rc;
1293 1340
1294 printk(KERN_INFO "PCIE%d: Checking link...\n", 1341 if (ppc4xx_pciex_hwops->check_link)
1295 port->index); 1342 ppc4xx_pciex_hwops->check_link(port);
1296
1297 /* Wait for reset to complete */
1298 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1299 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1300 port->index);
1301 return -1;
1302 }
1303
1304 /* Check for card presence detect if supported, if not, just wait for
1305 * link unconditionally.
1306 *
1307 * note that we don't fail if there is no link, we just filter out
1308 * config space accesses. That way, it will be easier to implement
1309 * hotplug later on.
1310 */
1311 if (!port->has_ibpre ||
1312 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1313 1 << 28, 1 << 28, 100)) {
1314 printk(KERN_INFO
1315 "PCIE%d: Device detected, waiting for link...\n",
1316 port->index);
1317 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1318 0x1000, 0x1000, 2000))
1319 printk(KERN_WARNING
1320 "PCIE%d: Link up failed\n", port->index);
1321 else {
1322 printk(KERN_INFO
1323 "PCIE%d: link is up !\n", port->index);
1324 port->link = 1;
1325 }
1326 } else
1327 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1328 1343
1329 /* 1344 /*
1330 * Initialize mapping: disable all regions and configure 1345 * Initialize mapping: disable all regions and configure
@@ -1347,14 +1362,17 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1347 /* 1362 /*
1348 * Check for VC0 active and assert RDY. 1363 * Check for VC0 active and assert RDY.
1349 */ 1364 */
1350 if (port->link && 1365 if (port->sdr_base) {
1351 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1366 if (port->link &&
1352 1 << 16, 1 << 16, 5000)) { 1367 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1353 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index); 1368 1 << 16, 1 << 16, 5000)) {
1354 port->link = 0; 1369 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1370 port->link = 0;
1371 }
1372
1373 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1355 } 1374 }
1356 1375
1357 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1358 msleep(100); 1376 msleep(100);
1359 1377
1360 return 0; 1378 return 0;
@@ -1604,7 +1622,7 @@ static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1604 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, 1622 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1605 res->start, 1623 res->start,
1606 res->start - hose->pci_mem_offset, 1624 res->start - hose->pci_mem_offset,
1607 res->end + 1 - res->start, 1625 resource_size(res),
1608 res->flags, 1626 res->flags,
1609 j) == 0) { 1627 j) == 0) {
1610 j++; 1628 j++;
@@ -1639,7 +1657,7 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1639 void __iomem *mbase, 1657 void __iomem *mbase,
1640 struct resource *res) 1658 struct resource *res)
1641{ 1659{
1642 resource_size_t size = res->end - res->start + 1; 1660 resource_size_t size = resource_size(res);
1643 u64 sa; 1661 u64 sa;
1644 1662
1645 if (port->endpoint) { 1663 if (port->endpoint) {
@@ -1960,7 +1978,7 @@ static int __init ppc4xx_pci_find_bridges(void)
1960{ 1978{
1961 struct device_node *np; 1979 struct device_node *np;
1962 1980
1963 ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; 1981 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
1964 1982
1965#ifdef CONFIG_PPC4xx_PCI_EXPRESS 1983#ifdef CONFIG_PPC4xx_PCI_EXPRESS
1966 for_each_compatible_node(np, NULL, "ibm,plb-pciex") 1984 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index b2acda07220..18e75ca19fe 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -347,7 +347,7 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
347 return; 347 return;
348 } 348 }
349 349
350 qe_ic->regs = ioremap(res.start, res.end - res.start + 1); 350 qe_ic->regs = ioremap(res.start, resource_size(&res));
351 351
352 qe_ic->irqhost->host_data = qe_ic; 352 qe_ic->irqhost->host_data = qe_ic;
353 qe_ic->hc_irq = qe_ic_irq_chip; 353 qe_ic->hc_irq = qe_ic_irq_chip;
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index 77e4934b88c..fd1a6c3b172 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -41,7 +41,7 @@ int par_io_init(struct device_node *np)
41 ret = of_address_to_resource(np, 0, &res); 41 ret = of_address_to_resource(np, 0, &res);
42 if (ret) 42 if (ret)
43 return ret; 43 return ret;
44 par_io = ioremap(res.start, res.end - res.start + 1); 44 par_io = ioremap(res.start, resource_size(&res));
45 45
46 num_ports = of_get_property(np, "num-ports", NULL); 46 num_ports = of_get_property(np, "num-ports", NULL);
47 if (num_ports) 47 if (num_ports)
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c
index ee056807b52..9f51f97abb5 100644
--- a/arch/powerpc/sysdev/tsi108_dev.c
+++ b/arch/powerpc/sysdev/tsi108_dev.c
@@ -23,7 +23,7 @@
23#include <asm/tsi108.h> 23#include <asm/tsi108.h>
24 24
25#include <asm/system.h> 25#include <asm/system.h>
26#include <asm/atomic.h> 26#include <linux/atomic.h>
27#include <asm/io.h> 27#include <asm/io.h>
28#include <asm/irq.h> 28#include <asm/irq.h>
29#include <asm/prom.h> 29#include <asm/prom.h>
diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xics/icp-native.c
index 1f15ad43614..50e32afe392 100644
--- a/arch/powerpc/sysdev/xics/icp-native.c
+++ b/arch/powerpc/sysdev/xics/icp-native.c
@@ -17,6 +17,7 @@
17#include <linux/cpu.h> 17#include <linux/cpu.h>
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/spinlock.h> 19#include <linux/spinlock.h>
20#include <linux/module.h>
20 21
21#include <asm/prom.h> 22#include <asm/prom.h>
22#include <asm/io.h> 23#include <asm/io.h>
@@ -24,6 +25,7 @@
24#include <asm/irq.h> 25#include <asm/irq.h>
25#include <asm/errno.h> 26#include <asm/errno.h>
26#include <asm/xics.h> 27#include <asm/xics.h>
28#include <asm/kvm_ppc.h>
27 29
28struct icp_ipl { 30struct icp_ipl {
29 union { 31 union {
@@ -139,6 +141,12 @@ static void icp_native_cause_ipi(int cpu, unsigned long data)
139 icp_native_set_qirr(cpu, IPI_PRIORITY); 141 icp_native_set_qirr(cpu, IPI_PRIORITY);
140} 142}
141 143
144void xics_wake_cpu(int cpu)
145{
146 icp_native_set_qirr(cpu, IPI_PRIORITY);
147}
148EXPORT_SYMBOL_GPL(xics_wake_cpu);
149
142static irqreturn_t icp_native_ipi_action(int irq, void *dev_id) 150static irqreturn_t icp_native_ipi_action(int irq, void *dev_id)
143{ 151{
144 int cpu = smp_processor_id(); 152 int cpu = smp_processor_id();
@@ -185,6 +193,7 @@ static int __init icp_native_map_one_cpu(int hw_id, unsigned long addr,
185 } 193 }
186 194
187 icp_native_regs[cpu] = ioremap(addr, size); 195 icp_native_regs[cpu] = ioremap(addr, size);
196 kvmppc_set_xics_phys(cpu, addr);
188 if (!icp_native_regs[cpu]) { 197 if (!icp_native_regs[cpu]) {
189 pr_warning("icp_native: Failed ioremap for CPU %d, " 198 pr_warning("icp_native: Failed ioremap for CPU %d, "
190 "interrupt server #0x%x, addr %#lx\n", 199 "interrupt server #0x%x, addr %#lx\n",
@@ -247,7 +256,7 @@ static int __init icp_native_init_one_node(struct device_node *np,
247 return -1; 256 return -1;
248 } 257 }
249 258
250 if (icp_native_map_one_cpu(*indx, r.start, r.end - r.start)) 259 if (icp_native_map_one_cpu(*indx, r.start, resource_size(&r)))
251 return -1; 260 return -1;
252 261
253 (*indx)++; 262 (*indx)++;
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-31 06:26:04 -0400