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-rw-r--r--arch/powerpc/include/asm/Kbuild2
-rw-r--r--arch/powerpc/include/asm/cputable.h5
-rw-r--r--arch/powerpc/include/asm/cputime.h74
-rw-r--r--arch/powerpc/include/asm/fsl_ifc.h834
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h7
-rw-r--r--arch/powerpc/include/asm/hugetlb.h38
-rw-r--r--arch/powerpc/include/asm/kdump.h4
-rw-r--r--arch/powerpc/include/asm/kexec.h7
-rw-r--r--arch/powerpc/include/asm/lv1call.h10
-rw-r--r--arch/powerpc/include/asm/machdep.h3
-rw-r--r--arch/powerpc/include/asm/memblock.h8
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h11
-rw-r--r--arch/powerpc/include/asm/mmu-hash64.h7
-rw-r--r--arch/powerpc/include/asm/mpic.h14
-rw-r--r--arch/powerpc/include/asm/opal.h131
-rw-r--r--arch/powerpc/include/asm/paca.h1
-rw-r--r--arch/powerpc/include/asm/page.h90
-rw-r--r--arch/powerpc/include/asm/page_64.h2
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h6
-rw-r--r--arch/powerpc/include/asm/pci.h2
-rw-r--r--arch/powerpc/include/asm/pgtable.h3
-rw-r--r--arch/powerpc/include/asm/processor.h3
-rw-r--r--arch/powerpc/include/asm/reg.h1
-rw-r--r--arch/powerpc/include/asm/reg_booke.h4
-rw-r--r--arch/powerpc/include/asm/rtas.h18
-rw-r--r--arch/powerpc/include/asm/rwsem.h132
-rw-r--r--arch/powerpc/include/asm/socket.h3
-rw-r--r--arch/powerpc/include/asm/system.h11
-rw-r--r--arch/powerpc/include/asm/tce.h10
-rw-r--r--arch/powerpc/include/asm/time.h2
-rw-r--r--arch/powerpc/include/asm/types.h5
31 files changed, 1211 insertions, 237 deletions
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index d51df17c7e6..7e313f1ed18 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -34,3 +34,5 @@ header-y += termios.h
34header-y += types.h 34header-y += types.h
35header-y += ucontext.h 35header-y += ucontext.h
36header-y += unistd.h 36header-y += unistd.h
37
38generic-y += rwsem.h
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index e30442c539c..ad55a1ccb9f 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -201,6 +201,7 @@ extern const char *powerpc_base_platform;
201#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000) 201#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
202#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000) 202#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
203#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000) 203#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
204#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000)
204 205
205#ifndef __ASSEMBLY__ 206#ifndef __ASSEMBLY__
206 207
@@ -425,7 +426,7 @@ extern const char *powerpc_base_platform;
425 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 426 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
426 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 427 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
427 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 428 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
428 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE) 429 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
429#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 430#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 431 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
431 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 432 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -437,7 +438,7 @@ extern const char *powerpc_base_platform;
437#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 438#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
438 439
439#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ 440#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
440 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 441 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
441 442
442#ifdef __powerpc64__ 443#ifdef __powerpc64__
443#ifdef CONFIG_PPC_BOOK3E 444#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index 98b7c4b49c9..487d46ff68a 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -29,25 +29,8 @@ static inline void setup_cputime_one_jiffy(void) { }
29#include <asm/time.h> 29#include <asm/time.h>
30#include <asm/param.h> 30#include <asm/param.h>
31 31
32typedef u64 cputime_t; 32typedef u64 __nocast cputime_t;
33typedef u64 cputime64_t; 33typedef u64 __nocast cputime64_t;
34
35#define cputime_zero ((cputime_t)0)
36#define cputime_max ((~((cputime_t)0) >> 1) - 1)
37#define cputime_add(__a, __b) ((__a) + (__b))
38#define cputime_sub(__a, __b) ((__a) - (__b))
39#define cputime_div(__a, __n) ((__a) / (__n))
40#define cputime_halve(__a) ((__a) >> 1)
41#define cputime_eq(__a, __b) ((__a) == (__b))
42#define cputime_gt(__a, __b) ((__a) > (__b))
43#define cputime_ge(__a, __b) ((__a) >= (__b))
44#define cputime_lt(__a, __b) ((__a) < (__b))
45#define cputime_le(__a, __b) ((__a) <= (__b))
46
47#define cputime64_zero ((cputime64_t)0)
48#define cputime64_add(__a, __b) ((__a) + (__b))
49#define cputime64_sub(__a, __b) ((__a) - (__b))
50#define cputime_to_cputime64(__ct) (__ct)
51 34
52#ifdef __KERNEL__ 35#ifdef __KERNEL__
53 36
@@ -65,7 +48,7 @@ DECLARE_PER_CPU(unsigned long, cputime_scaled_last_delta);
65 48
66static inline unsigned long cputime_to_jiffies(const cputime_t ct) 49static inline unsigned long cputime_to_jiffies(const cputime_t ct)
67{ 50{
68 return mulhdu(ct, __cputime_jiffies_factor); 51 return mulhdu((__force u64) ct, __cputime_jiffies_factor);
69} 52}
70 53
71/* Estimate the scaled cputime by scaling the real cputime based on 54/* Estimate the scaled cputime by scaling the real cputime based on
@@ -74,14 +57,15 @@ static inline cputime_t cputime_to_scaled(const cputime_t ct)
74{ 57{
75 if (cpu_has_feature(CPU_FTR_SPURR) && 58 if (cpu_has_feature(CPU_FTR_SPURR) &&
76 __get_cpu_var(cputime_last_delta)) 59 __get_cpu_var(cputime_last_delta))
77 return ct * __get_cpu_var(cputime_scaled_last_delta) / 60 return (__force u64) ct *
78 __get_cpu_var(cputime_last_delta); 61 __get_cpu_var(cputime_scaled_last_delta) /
62 __get_cpu_var(cputime_last_delta);
79 return ct; 63 return ct;
80} 64}
81 65
82static inline cputime_t jiffies_to_cputime(const unsigned long jif) 66static inline cputime_t jiffies_to_cputime(const unsigned long jif)
83{ 67{
84 cputime_t ct; 68 u64 ct;
85 unsigned long sec; 69 unsigned long sec;
86 70
87 /* have to be a little careful about overflow */ 71 /* have to be a little careful about overflow */
@@ -93,7 +77,7 @@ static inline cputime_t jiffies_to_cputime(const unsigned long jif)
93 } 77 }
94 if (sec) 78 if (sec)
95 ct += (cputime_t) sec * tb_ticks_per_sec; 79 ct += (cputime_t) sec * tb_ticks_per_sec;
96 return ct; 80 return (__force cputime_t) ct;
97} 81}
98 82
99static inline void setup_cputime_one_jiffy(void) 83static inline void setup_cputime_one_jiffy(void)
@@ -103,7 +87,7 @@ static inline void setup_cputime_one_jiffy(void)
103 87
104static inline cputime64_t jiffies64_to_cputime64(const u64 jif) 88static inline cputime64_t jiffies64_to_cputime64(const u64 jif)
105{ 89{
106 cputime_t ct; 90 u64 ct;
107 u64 sec; 91 u64 sec;
108 92
109 /* have to be a little careful about overflow */ 93 /* have to be a little careful about overflow */
@@ -114,28 +98,28 @@ static inline cputime64_t jiffies64_to_cputime64(const u64 jif)
114 do_div(ct, HZ); 98 do_div(ct, HZ);
115 } 99 }
116 if (sec) 100 if (sec)
117 ct += (cputime_t) sec * tb_ticks_per_sec; 101 ct += (u64) sec * tb_ticks_per_sec;
118 return ct; 102 return (__force cputime64_t) ct;
119} 103}
120 104
121static inline u64 cputime64_to_jiffies64(const cputime_t ct) 105static inline u64 cputime64_to_jiffies64(const cputime_t ct)
122{ 106{
123 return mulhdu(ct, __cputime_jiffies_factor); 107 return mulhdu((__force u64) ct, __cputime_jiffies_factor);
124} 108}
125 109
126/* 110/*
127 * Convert cputime <-> microseconds 111 * Convert cputime <-> microseconds
128 */ 112 */
129extern u64 __cputime_msec_factor; 113extern u64 __cputime_usec_factor;
130 114
131static inline unsigned long cputime_to_usecs(const cputime_t ct) 115static inline unsigned long cputime_to_usecs(const cputime_t ct)
132{ 116{
133 return mulhdu(ct, __cputime_msec_factor) * USEC_PER_MSEC; 117 return mulhdu((__force u64) ct, __cputime_usec_factor);
134} 118}
135 119
136static inline cputime_t usecs_to_cputime(const unsigned long us) 120static inline cputime_t usecs_to_cputime(const unsigned long us)
137{ 121{
138 cputime_t ct; 122 u64 ct;
139 unsigned long sec; 123 unsigned long sec;
140 124
141 /* have to be a little careful about overflow */ 125 /* have to be a little careful about overflow */
@@ -143,11 +127,11 @@ static inline cputime_t usecs_to_cputime(const unsigned long us)
143 sec = us / 1000000; 127 sec = us / 1000000;
144 if (ct) { 128 if (ct) {
145 ct *= tb_ticks_per_sec; 129 ct *= tb_ticks_per_sec;
146 do_div(ct, 1000); 130 do_div(ct, 1000000);
147 } 131 }
148 if (sec) 132 if (sec)
149 ct += (cputime_t) sec * tb_ticks_per_sec; 133 ct += (cputime_t) sec * tb_ticks_per_sec;
150 return ct; 134 return (__force cputime_t) ct;
151} 135}
152 136
153#define usecs_to_cputime64(us) usecs_to_cputime(us) 137#define usecs_to_cputime64(us) usecs_to_cputime(us)
@@ -159,12 +143,12 @@ extern u64 __cputime_sec_factor;
159 143
160static inline unsigned long cputime_to_secs(const cputime_t ct) 144static inline unsigned long cputime_to_secs(const cputime_t ct)
161{ 145{
162 return mulhdu(ct, __cputime_sec_factor); 146 return mulhdu((__force u64) ct, __cputime_sec_factor);
163} 147}
164 148
165static inline cputime_t secs_to_cputime(const unsigned long sec) 149static inline cputime_t secs_to_cputime(const unsigned long sec)
166{ 150{
167 return (cputime_t) sec * tb_ticks_per_sec; 151 return (__force cputime_t)((u64) sec * tb_ticks_per_sec);
168} 152}
169 153
170/* 154/*
@@ -172,7 +156,7 @@ static inline cputime_t secs_to_cputime(const unsigned long sec)
172 */ 156 */
173static inline void cputime_to_timespec(const cputime_t ct, struct timespec *p) 157static inline void cputime_to_timespec(const cputime_t ct, struct timespec *p)
174{ 158{
175 u64 x = ct; 159 u64 x = (__force u64) ct;
176 unsigned int frac; 160 unsigned int frac;
177 161
178 frac = do_div(x, tb_ticks_per_sec); 162 frac = do_div(x, tb_ticks_per_sec);
@@ -184,11 +168,11 @@ static inline void cputime_to_timespec(const cputime_t ct, struct timespec *p)
184 168
185static inline cputime_t timespec_to_cputime(const struct timespec *p) 169static inline cputime_t timespec_to_cputime(const struct timespec *p)
186{ 170{
187 cputime_t ct; 171 u64 ct;
188 172
189 ct = (u64) p->tv_nsec * tb_ticks_per_sec; 173 ct = (u64) p->tv_nsec * tb_ticks_per_sec;
190 do_div(ct, 1000000000); 174 do_div(ct, 1000000000);
191 return ct + (u64) p->tv_sec * tb_ticks_per_sec; 175 return (__force cputime_t)(ct + (u64) p->tv_sec * tb_ticks_per_sec);
192} 176}
193 177
194/* 178/*
@@ -196,7 +180,7 @@ static inline cputime_t timespec_to_cputime(const struct timespec *p)
196 */ 180 */
197static inline void cputime_to_timeval(const cputime_t ct, struct timeval *p) 181static inline void cputime_to_timeval(const cputime_t ct, struct timeval *p)
198{ 182{
199 u64 x = ct; 183 u64 x = (__force u64) ct;
200 unsigned int frac; 184 unsigned int frac;
201 185
202 frac = do_div(x, tb_ticks_per_sec); 186 frac = do_div(x, tb_ticks_per_sec);
@@ -208,11 +192,11 @@ static inline void cputime_to_timeval(const cputime_t ct, struct timeval *p)
208 192
209static inline cputime_t timeval_to_cputime(const struct timeval *p) 193static inline cputime_t timeval_to_cputime(const struct timeval *p)
210{ 194{
211 cputime_t ct; 195 u64 ct;
212 196
213 ct = (u64) p->tv_usec * tb_ticks_per_sec; 197 ct = (u64) p->tv_usec * tb_ticks_per_sec;
214 do_div(ct, 1000000); 198 do_div(ct, 1000000);
215 return ct + (u64) p->tv_sec * tb_ticks_per_sec; 199 return (__force cputime_t)(ct + (u64) p->tv_sec * tb_ticks_per_sec);
216} 200}
217 201
218/* 202/*
@@ -222,12 +206,12 @@ extern u64 __cputime_clockt_factor;
222 206
223static inline unsigned long cputime_to_clock_t(const cputime_t ct) 207static inline unsigned long cputime_to_clock_t(const cputime_t ct)
224{ 208{
225 return mulhdu(ct, __cputime_clockt_factor); 209 return mulhdu((__force u64) ct, __cputime_clockt_factor);
226} 210}
227 211
228static inline cputime_t clock_t_to_cputime(const unsigned long clk) 212static inline cputime_t clock_t_to_cputime(const unsigned long clk)
229{ 213{
230 cputime_t ct; 214 u64 ct;
231 unsigned long sec; 215 unsigned long sec;
232 216
233 /* have to be a little careful about overflow */ 217 /* have to be a little careful about overflow */
@@ -238,8 +222,8 @@ static inline cputime_t clock_t_to_cputime(const unsigned long clk)
238 do_div(ct, USER_HZ); 222 do_div(ct, USER_HZ);
239 } 223 }
240 if (sec) 224 if (sec)
241 ct += (cputime_t) sec * tb_ticks_per_sec; 225 ct += (u64) sec * tb_ticks_per_sec;
242 return ct; 226 return (__force cputime_t) ct;
243} 227}
244 228
245#define cputime64_to_clock_t(ct) cputime_to_clock_t((cputime_t)(ct)) 229#define cputime64_to_clock_t(ct) cputime_to_clock_t((cputime_t)(ct))
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 00000000000..b955012939a
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
1/* Freescale Integrated Flash Controller
2 *
3 * Copyright 2011 Freescale Semiconductor, Inc
4 *
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ASM_FSL_IFC_H
23#define __ASM_FSL_IFC_H
24
25#include <linux/compiler.h>
26#include <linux/types.h>
27#include <linux/io.h>
28
29#include <linux/of_platform.h>
30#include <linux/interrupt.h>
31
32#define FSL_IFC_BANK_COUNT 4
33
34/*
35 * CSPR - Chip Select Property Register
36 */
37#define CSPR_BA 0xFFFF0000
38#define CSPR_BA_SHIFT 16
39#define CSPR_PORT_SIZE 0x00000180
40#define CSPR_PORT_SIZE_SHIFT 7
41/* Port Size 8 bit */
42#define CSPR_PORT_SIZE_8 0x00000080
43/* Port Size 16 bit */
44#define CSPR_PORT_SIZE_16 0x00000100
45/* Port Size 32 bit */
46#define CSPR_PORT_SIZE_32 0x00000180
47/* Write Protect */
48#define CSPR_WP 0x00000040
49#define CSPR_WP_SHIFT 6
50/* Machine Select */
51#define CSPR_MSEL 0x00000006
52#define CSPR_MSEL_SHIFT 1
53/* NOR */
54#define CSPR_MSEL_NOR 0x00000000
55/* NAND */
56#define CSPR_MSEL_NAND 0x00000002
57/* GPCM */
58#define CSPR_MSEL_GPCM 0x00000004
59/* Bank Valid */
60#define CSPR_V 0x00000001
61#define CSPR_V_SHIFT 0
62
63/*
64 * Address Mask Register
65 */
66#define IFC_AMASK_MASK 0xFFFF0000
67#define IFC_AMASK_SHIFT 16
68#define IFC_AMASK(n) (IFC_AMASK_MASK << \
69 (__ilog2(n) - IFC_AMASK_SHIFT))
70
71/*
72 * Chip Select Option Register IFC_NAND Machine
73 */
74/* Enable ECC Encoder */
75#define CSOR_NAND_ECC_ENC_EN 0x80000000
76#define CSOR_NAND_ECC_MODE_MASK 0x30000000
77/* 4 bit correction per 520 Byte sector */
78#define CSOR_NAND_ECC_MODE_4 0x00000000
79/* 8 bit correction per 528 Byte sector */
80#define CSOR_NAND_ECC_MODE_8 0x10000000
81/* Enable ECC Decoder */
82#define CSOR_NAND_ECC_DEC_EN 0x04000000
83/* Row Address Length */
84#define CSOR_NAND_RAL_MASK 0x01800000
85#define CSOR_NAND_RAL_SHIFT 20
86#define CSOR_NAND_RAL_1 0x00000000
87#define CSOR_NAND_RAL_2 0x00800000
88#define CSOR_NAND_RAL_3 0x01000000
89#define CSOR_NAND_RAL_4 0x01800000
90/* Page Size 512b, 2k, 4k */
91#define CSOR_NAND_PGS_MASK 0x00180000
92#define CSOR_NAND_PGS_SHIFT 16
93#define CSOR_NAND_PGS_512 0x00000000
94#define CSOR_NAND_PGS_2K 0x00080000
95#define CSOR_NAND_PGS_4K 0x00100000
96/* Spare region Size */
97#define CSOR_NAND_SPRZ_MASK 0x0000E000
98#define CSOR_NAND_SPRZ_SHIFT 13
99#define CSOR_NAND_SPRZ_16 0x00000000
100#define CSOR_NAND_SPRZ_64 0x00002000
101#define CSOR_NAND_SPRZ_128 0x00004000
102#define CSOR_NAND_SPRZ_210 0x00006000
103#define CSOR_NAND_SPRZ_218 0x00008000
104#define CSOR_NAND_SPRZ_224 0x0000A000
105/* Pages Per Block */
106#define CSOR_NAND_PB_MASK 0x00000700
107#define CSOR_NAND_PB_SHIFT 8
108#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
109/* Time for Read Enable High to Output High Impedance */
110#define CSOR_NAND_TRHZ_MASK 0x0000001C
111#define CSOR_NAND_TRHZ_SHIFT 2
112#define CSOR_NAND_TRHZ_20 0x00000000
113#define CSOR_NAND_TRHZ_40 0x00000004
114#define CSOR_NAND_TRHZ_60 0x00000008
115#define CSOR_NAND_TRHZ_80 0x0000000C
116#define CSOR_NAND_TRHZ_100 0x00000010
117/* Buffer control disable */
118#define CSOR_NAND_BCTLD 0x00000001
119
120/*
121 * Chip Select Option Register - NOR Flash Mode
122 */
123/* Enable Address shift Mode */
124#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
125/* Page Read Enable from NOR device */
126#define CSOR_NOR_PGRD_EN 0x10000000
127/* AVD Toggle Enable during Burst Program */
128#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
129/* Address Data Multiplexing Shift */
130#define CSOR_NOR_ADM_MASK 0x0003E000
131#define CSOR_NOR_ADM_SHIFT_SHIFT 13
132#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
133/* Type of the NOR device hooked */
134#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
135#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
136/* Time for Read Enable High to Output High Impedance */
137#define CSOR_NOR_TRHZ_MASK 0x0000001C
138#define CSOR_NOR_TRHZ_SHIFT 2
139#define CSOR_NOR_TRHZ_20 0x00000000
140#define CSOR_NOR_TRHZ_40 0x00000004
141#define CSOR_NOR_TRHZ_60 0x00000008
142#define CSOR_NOR_TRHZ_80 0x0000000C
143#define CSOR_NOR_TRHZ_100 0x00000010
144/* Buffer control disable */
145#define CSOR_NOR_BCTLD 0x00000001
146
147/*
148 * Chip Select Option Register - GPCM Mode
149 */
150/* GPCM Mode - Normal */
151#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
152/* GPCM Mode - GenericASIC */
153#define CSOR_GPCM_GPMODE_ASIC 0x80000000
154/* Parity Mode odd/even */
155#define CSOR_GPCM_PARITY_EVEN 0x40000000
156/* Parity Checking enable/disable */
157#define CSOR_GPCM_PAR_EN 0x20000000
158/* GPCM Timeout Count */
159#define CSOR_GPCM_GPTO_MASK 0x0F000000
160#define CSOR_GPCM_GPTO_SHIFT 24
161#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
162/* GPCM External Access Termination mode for read access */
163#define CSOR_GPCM_RGETA_EXT 0x00080000
164/* GPCM External Access Termination mode for write access */
165#define CSOR_GPCM_WGETA_EXT 0x00040000
166/* Address Data Multiplexing Shift */
167#define CSOR_GPCM_ADM_MASK 0x0003E000
168#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
169#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
170/* Generic ASIC Parity error indication delay */
171#define CSOR_GPCM_GAPERRD_MASK 0x00000180
172#define CSOR_GPCM_GAPERRD_SHIFT 7
173#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
174/* Time for Read Enable High to Output High Impedance */
175#define CSOR_GPCM_TRHZ_MASK 0x0000001C
176#define CSOR_GPCM_TRHZ_20 0x00000000
177#define CSOR_GPCM_TRHZ_40 0x00000004
178#define CSOR_GPCM_TRHZ_60 0x00000008
179#define CSOR_GPCM_TRHZ_80 0x0000000C
180#define CSOR_GPCM_TRHZ_100 0x00000010
181/* Buffer control disable */
182#define CSOR_GPCM_BCTLD 0x00000001
183
184/*
185 * Ready Busy Status Register (RB_STAT)
186 */
187/* CSn is READY */
188#define IFC_RB_STAT_READY_CS0 0x80000000
189#define IFC_RB_STAT_READY_CS1 0x40000000
190#define IFC_RB_STAT_READY_CS2 0x20000000
191#define IFC_RB_STAT_READY_CS3 0x10000000
192
193/*
194 * General Control Register (GCR)
195 */
196#define IFC_GCR_MASK 0x8000F800
197/* reset all IFC hardware */
198#define IFC_GCR_SOFT_RST_ALL 0x80000000
199/* Turnaroud Time of external buffer */
200#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
201#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
202
203/*
204 * Common Event and Error Status Register (CM_EVTER_STAT)
205 */
206/* Chip select error */
207#define IFC_CM_EVTER_STAT_CSER 0x80000000
208
209/*
210 * Common Event and Error Enable Register (CM_EVTER_EN)
211 */
212/* Chip select error checking enable */
213#define IFC_CM_EVTER_EN_CSEREN 0x80000000
214
215/*
216 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
217 */
218/* Chip select error interrupt enable */
219#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
220
221/*
222 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
223 */
224/* transaction type of error Read/Write */
225#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
226#define IFC_CM_ERATTR0_ERAID 0x0FF00000
227#define IFC_CM_ERATTR0_ERAID_SHIFT 20
228#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
229#define IFC_CM_ERATTR0_ESRCID_SHIFT 8
230
231/*
232 * Clock Control Register (CCR)
233 */
234#define IFC_CCR_MASK 0x0F0F8800
235/* Clock division ratio */
236#define IFC_CCR_CLK_DIV_MASK 0x0F000000
237#define IFC_CCR_CLK_DIV_SHIFT 24
238#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
239/* IFC Clock Delay */
240#define IFC_CCR_CLK_DLY_MASK 0x000F0000
241#define IFC_CCR_CLK_DLY_SHIFT 16
242#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
243/* Invert IFC clock before sending out */
244#define IFC_CCR_INV_CLK_EN 0x00008000
245/* Fedback IFC Clock */
246#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
247
248/*
249 * Clock Status Register (CSR)
250 */
251/* Clk is stable */
252#define IFC_CSR_CLK_STAT_STABLE 0x80000000
253
254/*
255 * IFC_NAND Machine Specific Registers
256 */
257/*
258 * NAND Configuration Register (NCFGR)
259 */
260/* Auto Boot Mode */
261#define IFC_NAND_NCFGR_BOOT 0x80000000
262/* Addressing Mode-ROW0+n/COL0 */
263#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
264/* Addressing Mode-ROW0+n/COL0+n */
265#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
266/* Number of loop iterations of FIR sequences for multi page operations */
267#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
268#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
269#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
270/* Number of wait cycles */
271#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
272#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
273
274/*
275 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
276 */
277/* General purpose FCM flash command bytes CMD0-CMD7 */
278#define IFC_NAND_FCR0_CMD0 0xFF000000
279#define IFC_NAND_FCR0_CMD0_SHIFT 24
280#define IFC_NAND_FCR0_CMD1 0x00FF0000
281#define IFC_NAND_FCR0_CMD1_SHIFT 16
282#define IFC_NAND_FCR0_CMD2 0x0000FF00
283#define IFC_NAND_FCR0_CMD2_SHIFT 8
284#define IFC_NAND_FCR0_CMD3 0x000000FF
285#define IFC_NAND_FCR0_CMD3_SHIFT 0
286#define IFC_NAND_FCR1_CMD4 0xFF000000
287#define IFC_NAND_FCR1_CMD4_SHIFT 24
288#define IFC_NAND_FCR1_CMD5 0x00FF0000
289#define IFC_NAND_FCR1_CMD5_SHIFT 16
290#define IFC_NAND_FCR1_CMD6 0x0000FF00
291#define IFC_NAND_FCR1_CMD6_SHIFT 8
292#define IFC_NAND_FCR1_CMD7 0x000000FF
293#define IFC_NAND_FCR1_CMD7_SHIFT 0
294
295/*
296 * Flash ROW and COL Address Register (ROWn, COLn)
297 */
298/* Main/spare region locator */
299#define IFC_NAND_COL_MS 0x80000000
300/* Column Address */
301#define IFC_NAND_COL_CA_MASK 0x00000FFF
302
303/*
304 * NAND Flash Byte Count Register (NAND_BC)
305 */
306/* Byte Count for read/Write */
307#define IFC_NAND_BC 0x000001FF
308
309/*
310 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
311 */
312/* NAND Machine specific opcodes OP0-OP14*/
313#define IFC_NAND_FIR0_OP0 0xFC000000
314#define IFC_NAND_FIR0_OP0_SHIFT 26
315#define IFC_NAND_FIR0_OP1 0x03F00000
316#define IFC_NAND_FIR0_OP1_SHIFT 20
317#define IFC_NAND_FIR0_OP2 0x000FC000
318#define IFC_NAND_FIR0_OP2_SHIFT 14
319#define IFC_NAND_FIR0_OP3 0x00003F00
320#define IFC_NAND_FIR0_OP3_SHIFT 8
321#define IFC_NAND_FIR0_OP4 0x000000FC
322#define IFC_NAND_FIR0_OP4_SHIFT 2
323#define IFC_NAND_FIR1_OP5 0xFC000000
324#define IFC_NAND_FIR1_OP5_SHIFT 26
325#define IFC_NAND_FIR1_OP6 0x03F00000
326#define IFC_NAND_FIR1_OP6_SHIFT 20
327#define IFC_NAND_FIR1_OP7 0x000FC000
328#define IFC_NAND_FIR1_OP7_SHIFT 14
329#define IFC_NAND_FIR1_OP8 0x00003F00
330#define IFC_NAND_FIR1_OP8_SHIFT 8
331#define IFC_NAND_FIR1_OP9 0x000000FC
332#define IFC_NAND_FIR1_OP9_SHIFT 2
333#define IFC_NAND_FIR2_OP10 0xFC000000
334#define IFC_NAND_FIR2_OP10_SHIFT 26
335#define IFC_NAND_FIR2_OP11 0x03F00000
336#define IFC_NAND_FIR2_OP11_SHIFT 20
337#define IFC_NAND_FIR2_OP12 0x000FC000
338#define IFC_NAND_FIR2_OP12_SHIFT 14
339#define IFC_NAND_FIR2_OP13 0x00003F00
340#define IFC_NAND_FIR2_OP13_SHIFT 8
341#define IFC_NAND_FIR2_OP14 0x000000FC
342#define IFC_NAND_FIR2_OP14_SHIFT 2
343
344/*
345 * Instruction opcodes to be programmed
346 * in FIR registers- 6bits
347 */
348enum ifc_nand_fir_opcodes {
349 IFC_FIR_OP_NOP,
350 IFC_FIR_OP_CA0,
351 IFC_FIR_OP_CA1,
352 IFC_FIR_OP_CA2,
353 IFC_FIR_OP_CA3,
354 IFC_FIR_OP_RA0,
355 IFC_FIR_OP_RA1,
356 IFC_FIR_OP_RA2,
357 IFC_FIR_OP_RA3,
358 IFC_FIR_OP_CMD0,
359 IFC_FIR_OP_CMD1,
360 IFC_FIR_OP_CMD2,
361 IFC_FIR_OP_CMD3,
362 IFC_FIR_OP_CMD4,
363 IFC_FIR_OP_CMD5,
364 IFC_FIR_OP_CMD6,
365 IFC_FIR_OP_CMD7,
366 IFC_FIR_OP_CW0,
367 IFC_FIR_OP_CW1,
368 IFC_FIR_OP_CW2,
369 IFC_FIR_OP_CW3,
370 IFC_FIR_OP_CW4,
371 IFC_FIR_OP_CW5,
372 IFC_FIR_OP_CW6,
373 IFC_FIR_OP_CW7,
374 IFC_FIR_OP_WBCD,
375 IFC_FIR_OP_RBCD,
376 IFC_FIR_OP_BTRD,
377 IFC_FIR_OP_RDSTAT,
378 IFC_FIR_OP_NWAIT,
379 IFC_FIR_OP_WFR,
380 IFC_FIR_OP_SBRD,
381 IFC_FIR_OP_UA,
382 IFC_FIR_OP_RB,
383};
384
385/*
386 * NAND Chip Select Register (NAND_CSEL)
387 */
388#define IFC_NAND_CSEL 0x0C000000
389#define IFC_NAND_CSEL_SHIFT 26
390#define IFC_NAND_CSEL_CS0 0x00000000
391#define IFC_NAND_CSEL_CS1 0x04000000
392#define IFC_NAND_CSEL_CS2 0x08000000
393#define IFC_NAND_CSEL_CS3 0x0C000000
394
395/*
396 * NAND Operation Sequence Start (NANDSEQ_STRT)
397 */
398/* NAND Flash Operation Start */
399#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
400/* Automatic Erase */
401#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
402/* Automatic Program */
403#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
404/* Automatic Copyback */
405#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
406/* Automatic Read Operation */
407#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
408/* Automatic Status Read */
409#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
410
411/*
412 * NAND Event and Error Status Register (NAND_EVTER_STAT)
413 */
414/* Operation Complete */
415#define IFC_NAND_EVTER_STAT_OPC 0x80000000
416/* Flash Timeout Error */
417#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
418/* Write Protect Error */
419#define IFC_NAND_EVTER_STAT_WPER 0x04000000
420/* ECC Error */
421#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
422/* RCW Load Done */
423#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
424/* Boot Loadr Done */
425#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
426/* Bad Block Indicator search select */
427#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
428
429/*
430 * NAND Flash Page Read Completion Event Status Register
431 * (PGRDCMPL_EVT_STAT)
432 */
433#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
434/* Small Page 0-15 Done */
435#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
436/* Large Page(2K) 0-3 Done */
437#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
438/* Large Page(4K) 0-1 Done */
439#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
440
441/*
442 * NAND Event and Error Enable Register (NAND_EVTER_EN)
443 */
444/* Operation complete event enable */
445#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
446/* Page read complete event enable */
447#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
448/* Flash Timeout error enable */
449#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
450/* Write Protect error enable */
451#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
452/* ECC error logging enable */
453#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
454
455/*
456 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
457 */
458/* Enable interrupt for operation complete */
459#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
460/* Enable interrupt for Page read complete */
461#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
462/* Enable interrupt for Flash timeout error */
463#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
464/* Enable interrupt for Write protect error */
465#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
466/* Enable interrupt for ECC error*/
467#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
468
469/*
470 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
471 */
472#define IFC_NAND_ERATTR0_MASK 0x0C080000
473/* Error on CS0-3 for NAND */
474#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
475#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
476#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
477#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
478/* Transaction type of error Read/Write */
479#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
480
481/*
482 * NAND Flash Status Register (NAND_FSR)
483 */
484/* First byte of data read from read status op */
485#define IFC_NAND_NFSR_RS0 0xFF000000
486/* Second byte of data read from read status op */
487#define IFC_NAND_NFSR_RS1 0x00FF0000
488
489/*
490 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
491 */
492/* Number of ECC errors on sector n (n = 0-15) */
493#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
494#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
495#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
496#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
497#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
498#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
499#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
500#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
501#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
502#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
503#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
504#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
505#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
506#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
507#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
508#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
509#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
510#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
511#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
512#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
513#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
514#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
515#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
516#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
517#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
518#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
519#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
520#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
521#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
522#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
523#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
524#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
525
526/*
527 * NAND Control Register (NANDCR)
528 */
529#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
530#define IFC_NAND_NCR_FTOCNT_SHIFT 25
531#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
532
533/*
534 * NAND_AUTOBOOT_TRGR
535 */
536/* Trigger RCW load */
537#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
538/* Trigget Auto Boot */
539#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
540
541/*
542 * NAND_MDR
543 */
544/* 1st read data byte when opcode SBRD */
545#define IFC_NAND_MDR_RDATA0 0xFF000000
546/* 2nd read data byte when opcode SBRD */
547#define IFC_NAND_MDR_RDATA1 0x00FF0000
548
549/*
550 * NOR Machine Specific Registers
551 */
552/*
553 * NOR Event and Error Status Register (NOR_EVTER_STAT)
554 */
555/* NOR Command Sequence Operation Complete */
556#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
557/* Write Protect Error */
558#define IFC_NOR_EVTER_STAT_WPER 0x04000000
559/* Command Sequence Timeout Error */
560#define IFC_NOR_EVTER_STAT_STOER 0x01000000
561
562/*
563 * NOR Event and Error Enable Register (NOR_EVTER_EN)
564 */
565/* NOR Command Seq complete event enable */
566#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
567/* Write Protect Error Checking Enable */
568#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
569/* Timeout Error Enable */
570#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
571
572/*
573 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
574 */
575/* Enable interrupt for OPC complete */
576#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
577/* Enable interrupt for write protect error */
578#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
579/* Enable interrupt for timeout error */
580#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
581
582/*
583 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
584 */
585/* Source ID for error transaction */
586#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
587/* AXI ID for error transation */
588#define IFC_NOR_ERATTR0_ERAID 0x000FF000
589/* Chip select corresponds to NOR error */
590#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
591#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
592#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
593#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
594/* Type of transaction read/write */
595#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
596
597/*
598 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
599 */
600#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
601#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
602
603/*
604 * NOR Control Register (NORCR)
605 */
606#define IFC_NORCR_MASK 0x0F0F0000
607/* No. of Address/Data Phase */
608#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
609#define IFC_NORCR_NUM_PHASE_SHIFT 24
610#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
611/* Sequence Timeout Count */
612#define IFC_NORCR_STOCNT_MASK 0x000F0000
613#define IFC_NORCR_STOCNT_SHIFT 16
614#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
615
616/*
617 * GPCM Machine specific registers
618 */
619/*
620 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
621 */
622/* Timeout error */
623#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
624/* Parity error */
625#define IFC_GPCM_EVTER_STAT_PER 0x01000000
626
627/*
628 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
629 */
630/* Timeout error enable */
631#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
632/* Parity error enable */
633#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
634
635/*
636 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
637 */
638/* Enable Interrupt for timeout error */
639#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
640/* Enable Interrupt for Parity error */
641#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
642
643/*
644 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
645 */
646/* Source ID for error transaction */
647#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
648/* AXI ID for error transaction */
649#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
650/* Chip select corresponds to GPCM error */
651#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
652#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
653#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
654#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
655/* Type of transaction read/Write */
656#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
657
658/*
659 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
660 */
661/* On which beat of address/data parity error is observed */
662#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
663/* Parity Error on byte */
664#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
665/* Parity Error reported in addr or data phase */
666#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
667
668/*
669 * GPCM Status Register (GPCM_STAT)
670 */
671#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
672
673/*
674 * IFC Controller NAND Machine registers
675 */
676struct fsl_ifc_nand {
677 __be32 ncfgr;
678 u32 res1[0x4];
679 __be32 nand_fcr0;
680 __be32 nand_fcr1;
681 u32 res2[0x8];
682 __be32 row0;
683 u32 res3;
684 __be32 col0;
685 u32 res4;
686 __be32 row1;
687 u32 res5;
688 __be32 col1;
689 u32 res6;
690 __be32 row2;
691 u32 res7;
692 __be32 col2;
693 u32 res8;
694 __be32 row3;
695 u32 res9;
696 __be32 col3;
697 u32 res10[0x24];
698 __be32 nand_fbcr;
699 u32 res11;
700 __be32 nand_fir0;
701 __be32 nand_fir1;
702 __be32 nand_fir2;
703 u32 res12[0x10];
704 __be32 nand_csel;
705 u32 res13;
706 __be32 nandseq_strt;
707 u32 res14;
708 __be32 nand_evter_stat;
709 u32 res15;
710 __be32 pgrdcmpl_evt_stat;
711 u32 res16[0x2];
712 __be32 nand_evter_en;
713 u32 res17[0x2];
714 __be32 nand_evter_intr_en;
715 u32 res18[0x2];
716 __be32 nand_erattr0;
717 __be32 nand_erattr1;
718 u32 res19[0x10];
719 __be32 nand_fsr;
720 u32 res20;
721 __be32 nand_eccstat[4];
722 u32 res21[0x20];
723 __be32 nanndcr;
724 u32 res22[0x2];
725 __be32 nand_autoboot_trgr;
726 u32 res23;
727 __be32 nand_mdr;
728 u32 res24[0x5C];
729};
730
731/*
732 * IFC controller NOR Machine registers
733 */
734struct fsl_ifc_nor {
735 __be32 nor_evter_stat;
736 u32 res1[0x2];
737 __be32 nor_evter_en;
738 u32 res2[0x2];
739 __be32 nor_evter_intr_en;
740 u32 res3[0x2];
741 __be32 nor_erattr0;
742 __be32 nor_erattr1;
743 __be32 nor_erattr2;
744 u32 res4[0x4];
745 __be32 norcr;
746 u32 res5[0xEF];
747};
748
749/*
750 * IFC controller GPCM Machine registers
751 */
752struct fsl_ifc_gpcm {
753 __be32 gpcm_evter_stat;
754 u32 res1[0x2];
755 __be32 gpcm_evter_en;
756 u32 res2[0x2];
757 __be32 gpcm_evter_intr_en;
758 u32 res3[0x2];
759 __be32 gpcm_erattr0;
760 __be32 gpcm_erattr1;
761 __be32 gpcm_erattr2;
762 __be32 gpcm_stat;
763 u32 res4[0x1F3];
764};
765
766/*
767 * IFC Controller Registers
768 */
769struct fsl_ifc_regs {
770 __be32 ifc_rev;
771 u32 res1[0x3];
772 struct {
773 __be32 cspr;
774 u32 res2[0x2];
775 } cspr_cs[FSL_IFC_BANK_COUNT];
776 u32 res3[0x18];
777 struct {
778 __be32 amask;
779 u32 res4[0x2];
780 } amask_cs[FSL_IFC_BANK_COUNT];
781 u32 res5[0x18];
782 struct {
783 __be32 csor;
784 u32 res6[0x2];
785 } csor_cs[FSL_IFC_BANK_COUNT];
786 u32 res7[0x18];
787 struct {
788 __be32 ftim[4];
789 u32 res8[0x8];
790 } ftim_cs[FSL_IFC_BANK_COUNT];
791 u32 res9[0x60];
792 __be32 rb_stat;
793 u32 res10[0x2];
794 __be32 ifc_gcr;
795 u32 res11[0x2];
796 __be32 cm_evter_stat;
797 u32 res12[0x2];
798 __be32 cm_evter_en;
799 u32 res13[0x2];
800 __be32 cm_evter_intr_en;
801 u32 res14[0x2];
802 __be32 cm_erattr0;
803 __be32 cm_erattr1;
804 u32 res15[0x2];
805 __be32 ifc_ccr;
806 __be32 ifc_csr;
807 u32 res16[0x2EB];
808 struct fsl_ifc_nand ifc_nand;
809 struct fsl_ifc_nor ifc_nor;
810 struct fsl_ifc_gpcm ifc_gpcm;
811};
812
813extern unsigned int convert_ifc_address(phys_addr_t addr_base);
814extern int fsl_ifc_find(phys_addr_t addr_base);
815
816/* overview of the fsl ifc controller */
817
818struct fsl_ifc_ctrl {
819 /* device info */
820 struct device *dev;
821 struct fsl_ifc_regs __iomem *regs;
822 int irq;
823 int nand_irq;
824 spinlock_t lock;
825 void *nand;
826
827 u32 nand_stat;
828 wait_queue_head_t nand_wait;
829};
830
831extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
832
833
834#endif /* __ASM_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 8a0b5ece8f7..420b45368fc 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -238,8 +238,6 @@ struct fsl_lbc_regs {
238#define FPAR_LP_CI_SHIFT 0 238#define FPAR_LP_CI_SHIFT 0
239 __be32 fbcr; /**< Flash Byte Count Register */ 239 __be32 fbcr; /**< Flash Byte Count Register */
240#define FBCR_BC 0x00000FFF 240#define FBCR_BC 0x00000FFF
241 u8 res11[0x8];
242 u8 res8[0xF00];
243}; 241};
244 242
245/* 243/*
@@ -294,6 +292,11 @@ struct fsl_lbc_ctrl {
294 292
295 /* status read from LTESR by irq handler */ 293 /* status read from LTESR by irq handler */
296 unsigned int irq_status; 294 unsigned int irq_status;
295
296#ifdef CONFIG_SUSPEND
297 /* save regs when system go to deep-sleep */
298 struct fsl_lbc_regs *saved_regs;
299#endif
297}; 300};
298 301
299extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, 302extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 86004930a78..dfdb95bc59a 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -5,7 +5,6 @@
5#include <asm/page.h> 5#include <asm/page.h>
6 6
7extern struct kmem_cache *hugepte_cache; 7extern struct kmem_cache *hugepte_cache;
8extern void __init reserve_hugetlb_gpages(void);
9 8
10static inline pte_t *hugepd_page(hugepd_t hpd) 9static inline pte_t *hugepd_page(hugepd_t hpd)
11{ 10{
@@ -22,14 +21,14 @@ static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
22 unsigned pdshift) 21 unsigned pdshift)
23{ 22{
24 /* 23 /*
25 * On 32-bit, we have multiple higher-level table entries that point to 24 * On FSL BookE, we have multiple higher-level table entries that
26 * the same hugepte. Just use the first one since they're all 25 * point to the same hugepte. Just use the first one since they're all
27 * identical. So for that case, idx=0. 26 * identical. So for that case, idx=0.
28 */ 27 */
29 unsigned long idx = 0; 28 unsigned long idx = 0;
30 29
31 pte_t *dir = hugepd_page(*hpdp); 30 pte_t *dir = hugepd_page(*hpdp);
32#ifdef CONFIG_PPC64 31#ifndef CONFIG_PPC_FSL_BOOK3E
33 idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp); 32 idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
34#endif 33#endif
35 34
@@ -53,7 +52,8 @@ static inline int is_hugepage_only_range(struct mm_struct *mm,
53} 52}
54#endif 53#endif
55 54
56void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte); 55void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
56 pte_t pte);
57void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr); 57void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
58 58
59void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, 59void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
@@ -124,7 +124,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
124 unsigned long addr, pte_t *ptep, 124 unsigned long addr, pte_t *ptep,
125 pte_t pte, int dirty) 125 pte_t pte, int dirty)
126{ 126{
127#ifdef HUGETLB_NEED_PRELOAD
128 /*
129 * The "return 1" forces a call of update_mmu_cache, which will write a
130 * TLB entry. Without this, platforms that don't do a write of the TLB
131 * entry in the TLB miss handler asm will fault ad infinitum.
132 */
133 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
134 return 1;
135#else
127 return ptep_set_access_flags(vma, addr, ptep, pte, dirty); 136 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
137#endif
128} 138}
129 139
130static inline pte_t huge_ptep_get(pte_t *ptep) 140static inline pte_t huge_ptep_get(pte_t *ptep)
@@ -142,14 +152,24 @@ static inline void arch_release_hugepage(struct page *page)
142} 152}
143 153
144#else /* ! CONFIG_HUGETLB_PAGE */ 154#else /* ! CONFIG_HUGETLB_PAGE */
145static inline void reserve_hugetlb_gpages(void)
146{
147 pr_err("Cannot reserve gpages without hugetlb enabled\n");
148}
149static inline void flush_hugetlb_page(struct vm_area_struct *vma, 155static inline void flush_hugetlb_page(struct vm_area_struct *vma,
150 unsigned long vmaddr) 156 unsigned long vmaddr)
151{ 157{
152} 158}
159#endif /* CONFIG_HUGETLB_PAGE */
160
161
162/*
163 * FSL Book3E platforms require special gpage handling - the gpages
164 * are reserved early in the boot process by memblock instead of via
165 * the .dts as on IBM platforms.
166 */
167#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
168extern void __init reserve_hugetlb_gpages(void);
169#else
170static inline void reserve_hugetlb_gpages(void)
171{
172}
153#endif 173#endif
154 174
155#endif /* _ASM_POWERPC_HUGETLB_H */ 175#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/kdump.h b/arch/powerpc/include/asm/kdump.h
index bffd062adf7..c9776202d7e 100644
--- a/arch/powerpc/include/asm/kdump.h
+++ b/arch/powerpc/include/asm/kdump.h
@@ -32,11 +32,11 @@
32 32
33#ifndef __ASSEMBLY__ 33#ifndef __ASSEMBLY__
34 34
35#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_RELOCATABLE) 35#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_NONSTATIC_KERNEL)
36extern void reserve_kdump_trampoline(void); 36extern void reserve_kdump_trampoline(void);
37extern void setup_kdump_trampoline(void); 37extern void setup_kdump_trampoline(void);
38#else 38#else
39/* !CRASH_DUMP || RELOCATABLE */ 39/* !CRASH_DUMP || !NONSTATIC_KERNEL */
40static inline void reserve_kdump_trampoline(void) { ; } 40static inline void reserve_kdump_trampoline(void) { ; }
41static inline void setup_kdump_trampoline(void) { ; } 41static inline void setup_kdump_trampoline(void) { ; }
42#endif 42#endif
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index f921eb121d3..16d7e33d35e 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -49,7 +49,6 @@
49#define KEXEC_STATE_REAL_MODE 2 49#define KEXEC_STATE_REAL_MODE 2
50 50
51#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
52#include <linux/cpumask.h>
53#include <asm/reg.h> 52#include <asm/reg.h>
54 53
55typedef void (*crash_shutdown_t)(void); 54typedef void (*crash_shutdown_t)(void);
@@ -73,11 +72,6 @@ extern void kexec_smp_wait(void); /* get and clear naca physid, wait for
73 master to copy new code to 0 */ 72 master to copy new code to 0 */
74extern int crashing_cpu; 73extern int crashing_cpu;
75extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)); 74extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
76extern cpumask_t cpus_in_sr;
77static inline int kexec_sr_activated(int cpu)
78{
79 return cpumask_test_cpu(cpu, &cpus_in_sr);
80}
81 75
82struct kimage; 76struct kimage;
83struct pt_regs; 77struct pt_regs;
@@ -94,7 +88,6 @@ extern void reserve_crashkernel(void);
94extern void machine_kexec_mask_interrupts(void); 88extern void machine_kexec_mask_interrupts(void);
95 89
96#else /* !CONFIG_KEXEC */ 90#else /* !CONFIG_KEXEC */
97static inline int kexec_sr_activated(int cpu) { return 0; }
98static inline void crash_kexec_secondary(struct pt_regs *regs) { } 91static inline void crash_kexec_secondary(struct pt_regs *regs) { }
99 92
100static inline int overlaps_crashkernel(unsigned long start, unsigned long size) 93static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
diff --git a/arch/powerpc/include/asm/lv1call.h b/arch/powerpc/include/asm/lv1call.h
index f77c708c67a..233f9ecae76 100644
--- a/arch/powerpc/include/asm/lv1call.h
+++ b/arch/powerpc/include/asm/lv1call.h
@@ -231,7 +231,7 @@ LV1_CALL(allocate_memory, 4, 2, 0 )
231LV1_CALL(write_htab_entry, 4, 0, 1 ) 231LV1_CALL(write_htab_entry, 4, 0, 1 )
232LV1_CALL(construct_virtual_address_space, 3, 2, 2 ) 232LV1_CALL(construct_virtual_address_space, 3, 2, 2 )
233LV1_CALL(invalidate_htab_entries, 5, 0, 3 ) 233LV1_CALL(invalidate_htab_entries, 5, 0, 3 )
234LV1_CALL(get_virtual_address_space_id_of_ppe, 1, 1, 4 ) 234LV1_CALL(get_virtual_address_space_id_of_ppe, 0, 1, 4 )
235LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 ) 235LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 )
236LV1_CALL(select_virtual_address_space, 1, 0, 7 ) 236LV1_CALL(select_virtual_address_space, 1, 0, 7 )
237LV1_CALL(pause, 1, 0, 9 ) 237LV1_CALL(pause, 1, 0, 9 )
@@ -264,7 +264,7 @@ LV1_CALL(configure_execution_time_variable, 1, 0, 77 )
264LV1_CALL(get_spe_irq_outlet, 2, 1, 78 ) 264LV1_CALL(get_spe_irq_outlet, 2, 1, 78 )
265LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 ) 265LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 )
266LV1_CALL(create_repository_node, 6, 0, 90 ) 266LV1_CALL(create_repository_node, 6, 0, 90 )
267LV1_CALL(get_repository_node_value, 5, 2, 91 ) 267LV1_CALL(read_repository_node, 5, 2, 91 )
268LV1_CALL(modify_repository_node_value, 6, 0, 92 ) 268LV1_CALL(modify_repository_node_value, 6, 0, 92 )
269LV1_CALL(remove_repository_node, 4, 0, 93 ) 269LV1_CALL(remove_repository_node, 4, 0, 93 )
270LV1_CALL(read_htab_entries, 2, 5, 95 ) 270LV1_CALL(read_htab_entries, 2, 5, 95 )
@@ -276,7 +276,7 @@ LV1_CALL(construct_io_irq_outlet, 1, 1, 120 )
276LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 ) 276LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 )
277LV1_CALL(map_htab, 1, 1, 122 ) 277LV1_CALL(map_htab, 1, 1, 122 )
278LV1_CALL(unmap_htab, 1, 0, 123 ) 278LV1_CALL(unmap_htab, 1, 0, 123 )
279LV1_CALL(get_version_info, 0, 1, 127 ) 279LV1_CALL(get_version_info, 0, 2, 127 )
280LV1_CALL(insert_htab_entry, 6, 3, 158 ) 280LV1_CALL(insert_htab_entry, 6, 3, 158 )
281LV1_CALL(read_virtual_uart, 3, 1, 162 ) 281LV1_CALL(read_virtual_uart, 3, 1, 162 )
282LV1_CALL(write_virtual_uart, 3, 1, 163 ) 282LV1_CALL(write_virtual_uart, 3, 1, 163 )
@@ -294,9 +294,9 @@ LV1_CALL(unmap_device_dma_region, 4, 0, 177 )
294LV1_CALL(net_add_multicast_address, 4, 0, 185 ) 294LV1_CALL(net_add_multicast_address, 4, 0, 185 )
295LV1_CALL(net_remove_multicast_address, 4, 0, 186 ) 295LV1_CALL(net_remove_multicast_address, 4, 0, 186 )
296LV1_CALL(net_start_tx_dma, 4, 0, 187 ) 296LV1_CALL(net_start_tx_dma, 4, 0, 187 )
297LV1_CALL(net_stop_tx_dma, 3, 0, 188 ) 297LV1_CALL(net_stop_tx_dma, 2, 0, 188 )
298LV1_CALL(net_start_rx_dma, 4, 0, 189 ) 298LV1_CALL(net_start_rx_dma, 4, 0, 189 )
299LV1_CALL(net_stop_rx_dma, 3, 0, 190 ) 299LV1_CALL(net_stop_rx_dma, 2, 0, 190 )
300LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 ) 300LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 )
301LV1_CALL(net_set_interrupt_mask, 4, 0, 193 ) 301LV1_CALL(net_set_interrupt_mask, 4, 0, 193 )
302LV1_CALL(net_control, 6, 2, 194 ) 302LV1_CALL(net_control, 6, 2, 194 )
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index b540d6fcedd..bf37931d1ad 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -213,6 +213,9 @@ struct machdep_calls {
213 * allow assignment/enabling of the device. */ 213 * allow assignment/enabling of the device. */
214 int (*pcibios_enable_device_hook)(struct pci_dev *); 214 int (*pcibios_enable_device_hook)(struct pci_dev *);
215 215
216 /* Called after scan and before resource survey */
217 void (*pcibios_fixup_phb)(struct pci_controller *hose);
218
216 /* Called to shutdown machine specific hardware not already controlled 219 /* Called to shutdown machine specific hardware not already controlled
217 * by other drivers. 220 * by other drivers.
218 */ 221 */
diff --git a/arch/powerpc/include/asm/memblock.h b/arch/powerpc/include/asm/memblock.h
deleted file mode 100644
index 43efc345065..00000000000
--- a/arch/powerpc/include/asm/memblock.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef _ASM_POWERPC_MEMBLOCK_H
2#define _ASM_POWERPC_MEMBLOCK_H
3
4#include <asm/udbg.h>
5
6#define MEMBLOCK_DBG(fmt...) udbg_printf(fmt)
7
8#endif /* _ASM_POWERPC_MEMBLOCK_H */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 0260ea5ec3c..f5f89cafebd 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -214,6 +214,10 @@ typedef struct {
214 unsigned int id; 214 unsigned int id;
215 unsigned int active; 215 unsigned int active;
216 unsigned long vdso_base; 216 unsigned long vdso_base;
217#ifdef CONFIG_PPC_ICSWX
218 struct spinlock *cop_lockp; /* guard cop related stuff */
219 unsigned long acop; /* mask of enabled coprocessor types */
220#endif /* CONFIG_PPC_ICSWX */
217#ifdef CONFIG_PPC_MM_SLICES 221#ifdef CONFIG_PPC_MM_SLICES
218 u64 low_slices_psize; /* SLB page size encodings */ 222 u64 low_slices_psize; /* SLB page size encodings */
219 u64 high_slices_psize; /* 4 bits per slice for now */ 223 u64 high_slices_psize; /* 4 bits per slice for now */
@@ -254,6 +258,13 @@ extern int mmu_vmemmap_psize;
254 258
255#ifdef CONFIG_PPC64 259#ifdef CONFIG_PPC64
256extern unsigned long linear_map_top; 260extern unsigned long linear_map_top;
261
262/*
263 * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
264 * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
265 * return 1, indicating that the tlb requires preloading.
266 */
267#define HUGETLB_NEED_PRELOAD
257#endif 268#endif
258 269
259#endif /* !__ASSEMBLY__ */ 270#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index db645ec842b..412ba493cb9 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -312,10 +312,9 @@ extern void slb_set_size(u16 size);
312 * (i.e. everything above 0xC000000000000000), except the very top 312 * (i.e. everything above 0xC000000000000000), except the very top
313 * segment, which simplifies several things. 313 * segment, which simplifies several things.
314 * 314 *
315 * - We allow for 15 significant bits of ESID and 20 bits of 315 * - We allow for 16 significant bits of ESID and 19 bits of
316 * context for user addresses. i.e. 8T (43 bits) of address space for 316 * context for user addresses. i.e. 16T (44 bits) of address space for
317 * up to 1M contexts (although the page table structure and context 317 * up to half a million contexts.
318 * allocation will need changes to take advantage of this).
319 * 318 *
320 * - The scramble function gives robust scattering in the hash 319 * - The scramble function gives robust scattering in the hash
321 * table (at least based on some initial results). The previous 320 * table (at least based on some initial results). The previous
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index e6fae49e0b7..67b4d983723 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -251,6 +251,9 @@ struct mpic_irq_save {
251/* The instance data of a given MPIC */ 251/* The instance data of a given MPIC */
252struct mpic 252struct mpic
253{ 253{
254 /* The OpenFirmware dt node for this MPIC */
255 struct device_node *node;
256
254 /* The remapper for this MPIC */ 257 /* The remapper for this MPIC */
255 struct irq_host *irqhost; 258 struct irq_host *irqhost;
256 259
@@ -293,6 +296,9 @@ struct mpic
293 /* Register access method */ 296 /* Register access method */
294 enum mpic_reg_type reg_type; 297 enum mpic_reg_type reg_type;
295 298
299 /* The physical base address of the MPIC */
300 phys_addr_t paddr;
301
296 /* The various ioremap'ed bases */ 302 /* The various ioremap'ed bases */
297 struct mpic_reg_bank gregs; 303 struct mpic_reg_bank gregs;
298 struct mpic_reg_bank tmregs; 304 struct mpic_reg_bank tmregs;
@@ -331,11 +337,11 @@ struct mpic
331 * Note setting any ID (leaving those bits to 0) means standard MPIC 337 * Note setting any ID (leaving those bits to 0) means standard MPIC
332 */ 338 */
333 339
334/* This is the primary controller, only that one has IPIs and 340/*
335 * has afinity control. A non-primary MPIC always uses CPU0 341 * This is a secondary ("chained") controller; it only uses the CPU0
336 * registers only 342 * registers. Primary controllers have IPIs and affinity control.
337 */ 343 */
338#define MPIC_PRIMARY 0x00000001 344#define MPIC_SECONDARY 0x00000001
339 345
340/* Set this for a big-endian MPIC */ 346/* Set this for a big-endian MPIC */
341#define MPIC_BIG_ENDIAN 0x00000002 347#define MPIC_BIG_ENDIAN 0x00000002
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 2893e8f5406..a4b28f165b6 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -109,6 +109,14 @@ extern int opal_enter_rtas(struct rtas_args *args,
109#define OPAL_PCI_MAP_PE_DMA_WINDOW 44 109#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 110#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111#define OPAL_PCI_RESET 49 111#define OPAL_PCI_RESET 49
112#define OPAL_PCI_GET_HUB_DIAG_DATA 50
113#define OPAL_PCI_GET_PHB_DIAG_DATA 51
114#define OPAL_PCI_FENCE_PHB 52
115#define OPAL_PCI_REINIT 53
116#define OPAL_PCI_MASK_PE_ERROR 54
117#define OPAL_SET_SLOT_LED_STATUS 55
118#define OPAL_GET_EPOW_STATUS 56
119#define OPAL_SET_SYSTEM_ATTENTION_LED 57
112 120
113#ifndef __ASSEMBLY__ 121#ifndef __ASSEMBLY__
114 122
@@ -169,7 +177,11 @@ enum OpalPendingState {
169 OPAL_EVENT_NVRAM = 0x2, 177 OPAL_EVENT_NVRAM = 0x2,
170 OPAL_EVENT_RTC = 0x4, 178 OPAL_EVENT_RTC = 0x4,
171 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 179 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
172 OPAL_EVENT_CONSOLE_INPUT = 0x10 180 OPAL_EVENT_CONSOLE_INPUT = 0x10,
181 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
182 OPAL_EVENT_ERROR_LOG = 0x40,
183 OPAL_EVENT_EPOW = 0x80,
184 OPAL_EVENT_LED_STATUS = 0x100
173}; 185};
174 186
175/* Machine check related definitions */ 187/* Machine check related definitions */
@@ -258,13 +270,49 @@ enum OpalPeAction {
258 OPAL_MAP_PE = 1 270 OPAL_MAP_PE = 1
259}; 271};
260 272
273enum OpalPeltvAction {
274 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
275 OPAL_ADD_PE_TO_DOMAIN = 1
276};
277
278enum OpalMveEnableAction {
279 OPAL_DISABLE_MVE = 0,
280 OPAL_ENABLE_MVE = 1
281};
282
261enum OpalPciResetAndReinitScope { 283enum OpalPciResetAndReinitScope {
262 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 284 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
263 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 285 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
264 OPAL_PCI_IODA_RESET = 6, 286 OPAL_PCI_IODA_TABLE_RESET = 6,
287};
288
289enum OpalPciResetState {
290 OPAL_DEASSERT_RESET = 0,
291 OPAL_ASSERT_RESET = 1
265}; 292};
266 293
267enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 }; 294enum OpalPciMaskAction {
295 OPAL_UNMASK_ERROR_TYPE = 0,
296 OPAL_MASK_ERROR_TYPE = 1
297};
298
299enum OpalSlotLedType {
300 OPAL_SLOT_LED_ID_TYPE = 0,
301 OPAL_SLOT_LED_FAULT_TYPE = 1
302};
303
304enum OpalLedAction {
305 OPAL_TURN_OFF_LED = 0,
306 OPAL_TURN_ON_LED = 1,
307 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
308};
309
310enum OpalEpowStatus {
311 OPAL_EPOW_NONE = 0,
312 OPAL_EPOW_UPS = 1,
313 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
314 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
315};
268 316
269struct opal_machine_check_event { 317struct opal_machine_check_event {
270 enum OpalMCE_Version version:8; /* 0x00 */ 318 enum OpalMCE_Version version:8; /* 0x00 */
@@ -314,8 +362,74 @@ struct opal_machine_check_event {
314 } u; 362 } u;
315}; 363};
316 364
365/**
366 * This structure defines the overlay which will be used to store PHB error
367 * data upon request.
368 */
369enum {
370 OPAL_P7IOC_NUM_PEST_REGS = 128,
371};
372
373struct OpalIoP7IOCPhbErrorData {
374 uint32_t brdgCtl;
375
376 // P7IOC utl regs
377 uint32_t portStatusReg;
378 uint32_t rootCmplxStatus;
379 uint32_t busAgentStatus;
380
381 // P7IOC cfg regs
382 uint32_t deviceStatus;
383 uint32_t slotStatus;
384 uint32_t linkStatus;
385 uint32_t devCmdStatus;
386 uint32_t devSecStatus;
387
388 // cfg AER regs
389 uint32_t rootErrorStatus;
390 uint32_t uncorrErrorStatus;
391 uint32_t corrErrorStatus;
392 uint32_t tlpHdr1;
393 uint32_t tlpHdr2;
394 uint32_t tlpHdr3;
395 uint32_t tlpHdr4;
396 uint32_t sourceId;
397
398 uint32_t rsv3;
399
400 // Record data about the call to allocate a buffer.
401 uint64_t errorClass;
402 uint64_t correlator;
403
404 //P7IOC MMIO Error Regs
405 uint64_t p7iocPlssr; // n120
406 uint64_t p7iocCsr; // n110
407 uint64_t lemFir; // nC00
408 uint64_t lemErrorMask; // nC18
409 uint64_t lemWOF; // nC40
410 uint64_t phbErrorStatus; // nC80
411 uint64_t phbFirstErrorStatus; // nC88
412 uint64_t phbErrorLog0; // nCC0
413 uint64_t phbErrorLog1; // nCC8
414 uint64_t mmioErrorStatus; // nD00
415 uint64_t mmioFirstErrorStatus; // nD08
416 uint64_t mmioErrorLog0; // nD40
417 uint64_t mmioErrorLog1; // nD48
418 uint64_t dma0ErrorStatus; // nD80
419 uint64_t dma0FirstErrorStatus; // nD88
420 uint64_t dma0ErrorLog0; // nDC0
421 uint64_t dma0ErrorLog1; // nDC8
422 uint64_t dma1ErrorStatus; // nE00
423 uint64_t dma1FirstErrorStatus; // nE08
424 uint64_t dma1ErrorLog0; // nE40
425 uint64_t dma1ErrorLog1; // nE48
426 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
427 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
428};
429
317typedef struct oppanel_line { 430typedef struct oppanel_line {
318 /* XXX */ 431 const char * line;
432 uint64_t line_len;
319} oppanel_line_t; 433} oppanel_line_t;
320 434
321/* API functions */ 435/* API functions */
@@ -413,6 +527,15 @@ int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
413 uint64_t pci_mem_size); 527 uint64_t pci_mem_size);
414int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); 528int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
415 529
530int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
531int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
532int64_t opal_pci_fence_phb(uint64_t phb_id);
533int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
534int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
535int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
536int64_t opal_get_epow_status(uint64_t *status);
537int64_t opal_set_system_attention_led(uint8_t led_action);
538
416/* Internal functions */ 539/* Internal functions */
417extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data); 540extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
418 541
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 17722c73ba2..269c05a36d9 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -135,6 +135,7 @@ struct paca_struct {
135 u8 hard_enabled; /* set if irqs are enabled in MSR */ 135 u8 hard_enabled; /* set if irqs are enabled in MSR */
136 u8 io_sync; /* writel() needs spin_unlock sync */ 136 u8 io_sync; /* writel() needs spin_unlock sync */
137 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ 137 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
138 u8 nap_state_lost; /* NV GPR values lost in power7_idle */
138 139
139#ifdef CONFIG_PPC_POWERNV 140#ifdef CONFIG_PPC_POWERNV
140 /* Pointer to OPAL machine check event structure set by the 141 /* Pointer to OPAL machine check event structure set by the
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index dd9c4fd038e..f072e974f8a 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -92,20 +92,34 @@ extern unsigned int HPAGE_SHIFT;
92#define PAGE_OFFSET ASM_CONST(CONFIG_PAGE_OFFSET) 92#define PAGE_OFFSET ASM_CONST(CONFIG_PAGE_OFFSET)
93#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START)) 93#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
94 94
95#if defined(CONFIG_RELOCATABLE) 95#if defined(CONFIG_NONSTATIC_KERNEL)
96#ifndef __ASSEMBLY__ 96#ifndef __ASSEMBLY__
97 97
98extern phys_addr_t memstart_addr; 98extern phys_addr_t memstart_addr;
99extern phys_addr_t kernstart_addr; 99extern phys_addr_t kernstart_addr;
100
101#ifdef CONFIG_RELOCATABLE_PPC32
102extern long long virt_phys_offset;
100#endif 103#endif
104
105#endif /* __ASSEMBLY__ */
101#define PHYSICAL_START kernstart_addr 106#define PHYSICAL_START kernstart_addr
102#else 107
108#else /* !CONFIG_NONSTATIC_KERNEL */
103#define PHYSICAL_START ASM_CONST(CONFIG_PHYSICAL_START) 109#define PHYSICAL_START ASM_CONST(CONFIG_PHYSICAL_START)
104#endif 110#endif
105 111
112/* See Description below for VIRT_PHYS_OFFSET */
113#ifdef CONFIG_RELOCATABLE_PPC32
114#define VIRT_PHYS_OFFSET virt_phys_offset
115#else
116#define VIRT_PHYS_OFFSET (KERNELBASE - PHYSICAL_START)
117#endif
118
119
106#ifdef CONFIG_PPC64 120#ifdef CONFIG_PPC64
107#define MEMORY_START 0UL 121#define MEMORY_START 0UL
108#elif defined(CONFIG_RELOCATABLE) 122#elif defined(CONFIG_NONSTATIC_KERNEL)
109#define MEMORY_START memstart_addr 123#define MEMORY_START memstart_addr
110#else 124#else
111#define MEMORY_START (PHYSICAL_START + PAGE_OFFSET - KERNELBASE) 125#define MEMORY_START (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
@@ -125,12 +139,77 @@ extern phys_addr_t kernstart_addr;
125 * determine MEMORY_START until then. However we can determine PHYSICAL_START 139 * determine MEMORY_START until then. However we can determine PHYSICAL_START
126 * from information at hand (program counter, TLB lookup). 140 * from information at hand (program counter, TLB lookup).
127 * 141 *
142 * On BookE with RELOCATABLE (RELOCATABLE_PPC32)
143 *
144 * With RELOCATABLE_PPC32, we support loading the kernel at any physical
145 * address without any restriction on the page alignment.
146 *
147 * We find the runtime address of _stext and relocate ourselves based on
148 * the following calculation:
149 *
150 * virtual_base = ALIGN_DOWN(KERNELBASE,256M) +
151 * MODULO(_stext.run,256M)
152 * and create the following mapping:
153 *
154 * ALIGN_DOWN(_stext.run,256M) => ALIGN_DOWN(KERNELBASE,256M)
155 *
156 * When we process relocations, we cannot depend on the
157 * existing equation for the __va()/__pa() translations:
158 *
159 * __va(x) = (x) - PHYSICAL_START + KERNELBASE
160 *
161 * Where:
162 * PHYSICAL_START = kernstart_addr = Physical address of _stext
163 * KERNELBASE = Compiled virtual address of _stext.
164 *
165 * This formula holds true iff, kernel load address is TLB page aligned.
166 *
167 * In our case, we need to also account for the shift in the kernel Virtual
168 * address.
169 *
170 * E.g.,
171 *
172 * Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
173 * In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
174 *
175 * Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
176 * = 0xbc100000 , which is wrong.
177 *
178 * Rather, it should be : 0xc0000000 + 0x100000 = 0xc0100000
179 * according to our mapping.
180 *
181 * Hence we use the following formula to get the translations right:
182 *
183 * __va(x) = (x) - [ PHYSICAL_START - Effective KERNELBASE ]
184 *
185 * Where :
186 * PHYSICAL_START = dynamic load address.(kernstart_addr variable)
187 * Effective KERNELBASE = virtual_base =
188 * = ALIGN_DOWN(KERNELBASE,256M) +
189 * MODULO(PHYSICAL_START,256M)
190 *
191 * To make the cost of __va() / __pa() more light weight, we introduce
192 * a new variable virt_phys_offset, which will hold :
193 *
194 * virt_phys_offset = Effective KERNELBASE - PHYSICAL_START
195 * = ALIGN_DOWN(KERNELBASE,256M) -
196 * ALIGN_DOWN(PHYSICALSTART,256M)
197 *
198 * Hence :
199 *
200 * __va(x) = x - PHYSICAL_START + Effective KERNELBASE
201 * = x + virt_phys_offset
202 *
203 * and
204 * __pa(x) = x + PHYSICAL_START - Effective KERNELBASE
205 * = x - virt_phys_offset
206 *
128 * On non-Book-E PPC64 PAGE_OFFSET and MEMORY_START are constants so use 207 * On non-Book-E PPC64 PAGE_OFFSET and MEMORY_START are constants so use
129 * the other definitions for __va & __pa. 208 * the other definitions for __va & __pa.
130 */ 209 */
131#ifdef CONFIG_BOOKE 210#ifdef CONFIG_BOOKE
132#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) - PHYSICAL_START + KERNELBASE)) 211#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + VIRT_PHYS_OFFSET))
133#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE) 212#define __pa(x) ((unsigned long)(x) - VIRT_PHYS_OFFSET)
134#else 213#else
135#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + PAGE_OFFSET - MEMORY_START)) 214#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + PAGE_OFFSET - MEMORY_START))
136#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START) 215#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START)
@@ -290,6 +369,7 @@ extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
290extern void copy_user_page(void *to, void *from, unsigned long vaddr, 369extern void copy_user_page(void *to, void *from, unsigned long vaddr,
291 struct page *p); 370 struct page *p);
292extern int page_is_ram(unsigned long pfn); 371extern int page_is_ram(unsigned long pfn);
372extern int devmem_is_allowed(unsigned long pfn);
293 373
294#ifdef CONFIG_PPC_SMLPAR 374#ifdef CONFIG_PPC_SMLPAR
295void arch_free_page(struct page *page, int order); 375void arch_free_page(struct page *page, int order);
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fb40ede6bc0..fed85e6290e 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -130,7 +130,9 @@ do { \
130 130
131#ifdef CONFIG_HUGETLB_PAGE 131#ifdef CONFIG_HUGETLB_PAGE
132 132
133#ifdef CONFIG_PPC_MM_SLICES
133#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA 134#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
135#endif
134 136
135#endif /* !CONFIG_HUGETLB_PAGE */ 137#endif /* !CONFIG_HUGETLB_PAGE */
136 138
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 56b879ab3a4..882b6aa6c85 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -153,8 +153,8 @@ struct pci_dn {
153 153
154 int pci_ext_config_space; /* for pci devices */ 154 int pci_ext_config_space; /* for pci devices */
155 155
156#ifdef CONFIG_EEH
157 struct pci_dev *pcidev; /* back-pointer to the pci device */ 156 struct pci_dev *pcidev; /* back-pointer to the pci device */
157#ifdef CONFIG_EEH
158 int class_code; /* pci device class */ 158 int class_code; /* pci device class */
159 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 159 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
160 int eeh_config_addr; 160 int eeh_config_addr;
@@ -164,6 +164,10 @@ struct pci_dn {
164 int eeh_false_positives; /* # times this device reported #ff's */ 164 int eeh_false_positives; /* # times this device reported #ff's */
165 u32 config_space[16]; /* saved PCI config space */ 165 u32 config_space[16]; /* saved PCI config space */
166#endif 166#endif
167#define IODA_INVALID_PE (-1)
168#ifdef CONFIG_PPC_POWERNV
169 int pe_number;
170#endif
167}; 171};
168 172
169/* Get the pointer to a device_node's pci_dn */ 173/* Get the pointer to a device_node's pci_dn */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 49c3de582be..1c92013466e 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -184,8 +184,6 @@ extern void of_scan_pci_bridge(struct pci_dev *dev);
184extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); 184extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
185extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); 185extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
186 186
187extern int pci_read_irq_line(struct pci_dev *dev);
188
189struct file; 187struct file;
190extern pgprot_t pci_phys_mem_access_prot(struct file *file, 188extern pgprot_t pci_phys_mem_access_prot(struct file *file,
191 unsigned long pfn, 189 unsigned long pfn,
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 88b0bd925a8..2e0e4110f7a 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -170,6 +170,9 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre
170#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 170#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
171 _PAGE_COHERENT | _PAGE_WRITETHRU)) 171 _PAGE_COHERENT | _PAGE_WRITETHRU))
172 172
173#define pgprot_cached_noncoherent(prot) \
174 (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
175
173#define pgprot_writecombine pgprot_noncached_wc 176#define pgprot_writecombine pgprot_noncached_wc
174 177
175struct file; 178struct file;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index eb11a446720..b585bff1a02 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -382,6 +382,9 @@ static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
382} 382}
383#endif 383#endif
384 384
385extern unsigned long cpuidle_disable;
386enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
387
385#endif /* __KERNEL__ */ 388#endif /* __KERNEL__ */
386#endif /* __ASSEMBLY__ */ 389#endif /* __ASSEMBLY__ */
387#endif /* _ASM_POWERPC_PROCESSOR_H */ 390#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 559da199edb..7fdc2c0b7fa 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -951,6 +951,7 @@
951#define PVR_403GCX 0x00201400 951#define PVR_403GCX 0x00201400
952#define PVR_405GP 0x40110000 952#define PVR_405GP 0x40110000
953#define PVR_476 0x11a52000 953#define PVR_476 0x11a52000
954#define PVR_476FPE 0x7ff50000
954#define PVR_STB03XXX 0x40310000 955#define PVR_STB03XXX 0x40310000
955#define PVR_NP405H 0x41410000 956#define PVR_NP405H 0x41410000
956#define PVR_NP405L 0x41610000 957#define PVR_NP405L 0x41610000
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 03c48e819c8..500fe1dc43e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
187#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ 187#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
188#endif 188#endif
189 189
190#ifdef CONFIG_PPC_ICSWX
191#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
192#endif
193
190/* Bit definitions for CCR1. */ 194/* Bit definitions for CCR1. */
191#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 195#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
192#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 196#define CCR1_TCS 0x00000080 /* Timer Clock Select */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 41f69ae79d4..01c143bb77a 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -245,6 +245,12 @@ extern int early_init_dt_scan_rtas(unsigned long node,
245 245
246extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal); 246extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
247 247
248#ifdef CONFIG_PPC_RTAS_DAEMON
249extern void rtas_cancel_event_scan(void);
250#else
251static inline void rtas_cancel_event_scan(void) { }
252#endif
253
248/* Error types logged. */ 254/* Error types logged. */
249#define ERR_FLAG_ALREADY_LOGGED 0x0 255#define ERR_FLAG_ALREADY_LOGGED 0x0
250#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */ 256#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
@@ -307,5 +313,17 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg)
307extern void __cpuinit rtas_give_timebase(void); 313extern void __cpuinit rtas_give_timebase(void);
308extern void __cpuinit rtas_take_timebase(void); 314extern void __cpuinit rtas_take_timebase(void);
309 315
316#ifdef CONFIG_PPC_RTAS
317static inline int page_is_rtas_user_buf(unsigned long pfn)
318{
319 unsigned long paddr = (pfn << PAGE_SHIFT);
320 if (paddr >= rtas_rmo_buf && paddr < (rtas_rmo_buf + RTAS_RMOBUF_MAX))
321 return 1;
322 return 0;
323}
324#else
325static inline int page_is_rtas_user_buf(unsigned long pfn) { return 0;}
326#endif
327
310#endif /* __KERNEL__ */ 328#endif /* __KERNEL__ */
311#endif /* _POWERPC_RTAS_H */ 329#endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h
deleted file mode 100644
index bb1e2cdeb9b..00000000000
--- a/arch/powerpc/include/asm/rwsem.h
+++ /dev/null
@@ -1,132 +0,0 @@
1#ifndef _ASM_POWERPC_RWSEM_H
2#define _ASM_POWERPC_RWSEM_H
3
4#ifndef _LINUX_RWSEM_H
5#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
6#endif
7
8#ifdef __KERNEL__
9
10/*
11 * R/W semaphores for PPC using the stuff in lib/rwsem.c.
12 * Adapted largely from include/asm-i386/rwsem.h
13 * by Paul Mackerras <paulus@samba.org>.
14 */
15
16/*
17 * the semaphore definition
18 */
19#ifdef CONFIG_PPC64
20# define RWSEM_ACTIVE_MASK 0xffffffffL
21#else
22# define RWSEM_ACTIVE_MASK 0x0000ffffL
23#endif
24
25#define RWSEM_UNLOCKED_VALUE 0x00000000L
26#define RWSEM_ACTIVE_BIAS 0x00000001L
27#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
28#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
29#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
30
31/*
32 * lock for reading
33 */
34static inline void __down_read(struct rw_semaphore *sem)
35{
36 if (unlikely(atomic_long_inc_return((atomic_long_t *)&sem->count) <= 0))
37 rwsem_down_read_failed(sem);
38}
39
40static inline int __down_read_trylock(struct rw_semaphore *sem)
41{
42 long tmp;
43
44 while ((tmp = sem->count) >= 0) {
45 if (tmp == cmpxchg(&sem->count, tmp,
46 tmp + RWSEM_ACTIVE_READ_BIAS)) {
47 return 1;
48 }
49 }
50 return 0;
51}
52
53/*
54 * lock for writing
55 */
56static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
57{
58 long tmp;
59
60 tmp = atomic_long_add_return(RWSEM_ACTIVE_WRITE_BIAS,
61 (atomic_long_t *)&sem->count);
62 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
63 rwsem_down_write_failed(sem);
64}
65
66static inline void __down_write(struct rw_semaphore *sem)
67{
68 __down_write_nested(sem, 0);
69}
70
71static inline int __down_write_trylock(struct rw_semaphore *sem)
72{
73 long tmp;
74
75 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
76 RWSEM_ACTIVE_WRITE_BIAS);
77 return tmp == RWSEM_UNLOCKED_VALUE;
78}
79
80/*
81 * unlock after reading
82 */
83static inline void __up_read(struct rw_semaphore *sem)
84{
85 long tmp;
86
87 tmp = atomic_long_dec_return((atomic_long_t *)&sem->count);
88 if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
89 rwsem_wake(sem);
90}
91
92/*
93 * unlock after writing
94 */
95static inline void __up_write(struct rw_semaphore *sem)
96{
97 if (unlikely(atomic_long_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
98 (atomic_long_t *)&sem->count) < 0))
99 rwsem_wake(sem);
100}
101
102/*
103 * implement atomic add functionality
104 */
105static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
106{
107 atomic_long_add(delta, (atomic_long_t *)&sem->count);
108}
109
110/*
111 * downgrade write lock to read lock
112 */
113static inline void __downgrade_write(struct rw_semaphore *sem)
114{
115 long tmp;
116
117 tmp = atomic_long_add_return(-RWSEM_WAITING_BIAS,
118 (atomic_long_t *)&sem->count);
119 if (tmp < 0)
120 rwsem_downgrade_wake(sem);
121}
122
123/*
124 * implement exchange and add functionality
125 */
126static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
127{
128 return atomic_long_add_return(delta, (atomic_long_t *)&sem->count);
129}
130
131#endif /* __KERNEL__ */
132#endif /* _ASM_POWERPC_RWSEM_H */
diff --git a/arch/powerpc/include/asm/socket.h b/arch/powerpc/include/asm/socket.h
index 866f7606da6..2fc2af8fbf5 100644
--- a/arch/powerpc/include/asm/socket.h
+++ b/arch/powerpc/include/asm/socket.h
@@ -69,4 +69,7 @@
69 69
70#define SO_RXQ_OVFL 40 70#define SO_RXQ_OVFL 40
71 71
72#define SO_WIFI_STATUS 41
73#define SCM_WIFI_STATUS SO_WIFI_STATUS
74
72#endif /* _ASM_POWERPC_SOCKET_H */ 75#endif /* _ASM_POWERPC_SOCKET_H */
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index e30a13d1ee7..c377457d1b8 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -193,8 +193,8 @@ extern void cacheable_memzero(void *p, unsigned int nb);
193extern void *cacheable_memcpy(void *, const void *, unsigned int); 193extern void *cacheable_memcpy(void *, const void *, unsigned int);
194extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); 194extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
195extern void bad_page_fault(struct pt_regs *, unsigned long, int); 195extern void bad_page_fault(struct pt_regs *, unsigned long, int);
196extern int die(const char *, struct pt_regs *, long);
197extern void _exception(int, struct pt_regs *, int, unsigned long); 196extern void _exception(int, struct pt_regs *, int, unsigned long);
197extern void die(const char *, struct pt_regs *, long);
198extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 198extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
199 199
200#ifdef CONFIG_BOOKE_WDT 200#ifdef CONFIG_BOOKE_WDT
@@ -221,6 +221,15 @@ extern unsigned long klimit;
221extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); 221extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
222 222
223extern int powersave_nap; /* set if nap mode can be used in idle loop */ 223extern int powersave_nap; /* set if nap mode can be used in idle loop */
224void cpu_idle_wait(void);
225
226#ifdef CONFIG_PSERIES_IDLE
227extern void update_smt_snooze_delay(int snooze);
228extern int pseries_notify_cpuidle_add_cpu(int cpu);
229#else
230static inline void update_smt_snooze_delay(int snooze) {}
231static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
232#endif
224 233
225/* 234/*
226 * Atomic exchange 235 * Atomic exchange
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
index f663634cccc..743f36b38e5 100644
--- a/arch/powerpc/include/asm/tce.h
+++ b/arch/powerpc/include/asm/tce.h
@@ -26,10 +26,14 @@
26 26
27/* 27/*
28 * Tces come in two formats, one for the virtual bus and a different 28 * Tces come in two formats, one for the virtual bus and a different
29 * format for PCI 29 * format for PCI. PCI TCEs can have hardware or software maintianed
30 * coherency.
30 */ 31 */
31#define TCE_VB 0 32#define TCE_VB 0
32#define TCE_PCI 1 33#define TCE_PCI 1
34#define TCE_PCI_SWINV_CREATE 2
35#define TCE_PCI_SWINV_FREE 4
36#define TCE_PCI_SWINV_PAIR 8
33 37
34/* TCE page size is 4096 bytes (1 << 12) */ 38/* TCE page size is 4096 bytes (1 << 12) */
35 39
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index fe6f7c2c9c6..7eb10fb96cd 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -219,5 +219,7 @@ DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
219extern void secondary_cpu_time_init(void); 219extern void secondary_cpu_time_init(void);
220extern void iSeries_time_init_early(void); 220extern void iSeries_time_init_early(void);
221 221
222DECLARE_PER_CPU(u64, decrementers_next_tb);
223
222#endif /* __KERNEL__ */ 224#endif /* __KERNEL__ */
223#endif /* __POWERPC_TIME_H */ 225#endif /* __POWERPC_TIME_H */
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index 8947b9827bc..d82e94e6c2b 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -5,8 +5,11 @@
5 * This is here because we used to use l64 for 64bit powerpc 5 * This is here because we used to use l64 for 64bit powerpc
6 * and we don't want to impact user mode with our change to ll64 6 * and we don't want to impact user mode with our change to ll64
7 * in the kernel. 7 * in the kernel.
8 *
9 * However, some user programs are fine with this. They can
10 * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
8 */ 11 */
9#if defined(__powerpc64__) && !defined(__KERNEL__) 12#if !defined(__SANE_USERSPACE_TYPES__) && defined(__powerpc64__) && !defined(__KERNEL__)
10# include <asm-generic/int-l64.h> 13# include <asm-generic/int-l64.h>
11#else 14#else
12# include <asm-generic/int-ll64.h> 15# include <asm-generic/int-ll64.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 01:29:04 -0400