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-rw-r--r--arch/powerpc/boot/.gitignore5
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts5
-rw-r--r--arch/powerpc/boot/dts/glacier.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts2
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dts280
-rw-r--r--arch/powerpc/boot/dts/p1010si.dtsi376
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts2
-rw-r--r--arch/powerpc/boot/dts/p1023rds.dts546
-rw-r--r--arch/powerpc/boot/dts/p2040rdb.dts166
-rw-r--r--arch/powerpc/boot/dts/p2040si.dtsi623
-rw-r--r--arch/powerpc/boot/dts/p3041ds.dts214
-rw-r--r--arch/powerpc/boot/dts/p3041si.dtsi660
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts533
-rw-r--r--arch/powerpc/boot/dts/p4080si.dtsi661
-rw-r--r--arch/powerpc/boot/dts/p5020ds.dts215
-rw-r--r--arch/powerpc/boot/dts/p5020si.dtsi652
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts12
-rw-r--r--arch/powerpc/boot/dts/socrates.dts2
-rw-r--r--arch/powerpc/boot/dts/taishan.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts42
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts2
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts2
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts2
-rw-r--r--arch/powerpc/boot/dts/xpedite5200.dts2
-rw-r--r--arch/powerpc/boot/dts/xpedite5200_xmon.dts2
-rw-r--r--arch/powerpc/boot/treeboot-iss4xx.c23
26 files changed, 4528 insertions, 513 deletions
diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore
index 12da77ec022..c32ae5ce9ff 100644
--- a/arch/powerpc/boot/.gitignore
+++ b/arch/powerpc/boot/.gitignore
@@ -1,10 +1,6 @@
1addnote 1addnote
2empty.c 2empty.c
3hack-coff 3hack-coff
4infblock.c
5infblock.h
6infcodes.c
7infcodes.h
8inffast.c 4inffast.c
9inffast.h 5inffast.h
10inffixed.h 6inffixed.h
@@ -27,7 +23,6 @@ zImage.bin.*
27zImage.chrp 23zImage.chrp
28zImage.coff 24zImage.coff
29zImage.holly 25zImage.holly
30zImage.iseries
31zImage.*lds 26zImage.*lds
32zImage.miboot 27zImage.miboot
33zImage.pmac 28zImage.pmac
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 22dd6ae84da..3dc75deafbb 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -143,6 +143,11 @@
143 interrupts = <0x1d 0x4>; 143 interrupts = <0x1d 0x4>;
144 }; 144 };
145 145
146 HWRNG: hwrng@110000 {
147 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
148 reg = <4 0x00110000 0x50>;
149 };
150
146 MAL0: mcmal { 151 MAL0: mcmal {
147 compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 152 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
148 dcr-reg = <0x180 0x062>; 153 dcr-reg = <0x180 0x062>;
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index e618fc4cbc9..2000060386d 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -130,12 +130,18 @@
130 }; 130 };
131 131
132 CRYPTO: crypto@180000 { 132 CRYPTO: crypto@180000 {
133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; 133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
134 "amcc,ppc4xx-crypto";
134 reg = <4 0x00180000 0x80400>; 135 reg = <4 0x00180000 0x80400>;
135 interrupt-parent = <&UIC0>; 136 interrupt-parent = <&UIC0>;
136 interrupts = <0x1d 0x4>; 137 interrupts = <0x1d 0x4>;
137 }; 138 };
138 139
140 HWRNG: hwrng@110000 {
141 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
142 reg = <4 0x00110000 0x50>;
143 };
144
139 MAL0: mcmal { 145 MAL0: mcmal {
140 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 146 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
141 dcr-reg = <0x180 0x062>; 147 dcr-reg = <0x180 0x062>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 30cf0e098bb..647daf8e729 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -60,6 +60,8 @@
60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", 60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
61 "simple-bus"; 61 "simple-bus";
62 reg = <0xe0005000 0x1000>; 62 reg = <0xe0005000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <19 2>;
63 65
64 ranges = <0x0 0x0 0xfe000000 0x02000000 66 ranges = <0x0 0x0 0xfe000000 0x02000000
65 0x1 0x0 0xf8000000 0x00008000 67 0x1 0x0 0xf8000000 0x00008000
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
new file mode 100644
index 00000000000..6b33b73a5ba
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -0,0 +1,280 @@
1/*
2 * P1010 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "p1010si.dtsi"
13
14/ {
15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB";
17
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 };
27
28 memory {
29 device_type = "memory";
30 };
31
32 ifc@ffe1e000 {
33 /* NOR, NAND Flashes and CPLD on board */
34 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
35 0x1 0x0 0x0 0xff800000 0x00010000
36 0x3 0x0 0x0 0xffb00000 0x00000020>;
37
38 nor@0,0 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "cfi-flash";
42 reg = <0x0 0x0 0x2000000>;
43 bank-width = <2>;
44 device-width = <1>;
45
46 partition@40000 {
47 /* 256KB for DTB Image */
48 reg = <0x00040000 0x00040000>;
49 label = "NOR DTB Image";
50 };
51
52 partition@80000 {
53 /* 7 MB for Linux Kernel Image */
54 reg = <0x00080000 0x00700000>;
55 label = "NOR Linux Kernel Image";
56 };
57
58 partition@800000 {
59 /* 20MB for JFFS2 based Root file System */
60 reg = <0x00800000 0x01400000>;
61 label = "NOR JFFS2 Root File System";
62 };
63
64 partition@1f00000 {
65 /* This location must not be altered */
66 /* 512KB for u-boot Bootloader Image */
67 /* 512KB for u-boot Environment Variables */
68 reg = <0x01f00000 0x00100000>;
69 label = "NOR U-Boot Image";
70 read-only;
71 };
72 };
73
74 nand@1,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,ifc-nand";
78 reg = <0x1 0x0 0x10000>;
79
80 partition@0 {
81 /* This location must not be altered */
82 /* 1MB for u-boot Bootloader Image */
83 reg = <0x0 0x00100000>;
84 label = "NAND U-Boot Image";
85 read-only;
86 };
87
88 partition@100000 {
89 /* 1MB for DTB Image */
90 reg = <0x00100000 0x00100000>;
91 label = "NAND DTB Image";
92 };
93
94 partition@200000 {
95 /* 4MB for Linux Kernel Image */
96 reg = <0x00200000 0x00400000>;
97 label = "NAND Linux Kernel Image";
98 };
99
100 partition@600000 {
101 /* 4MB for Compressed Root file System Image */
102 reg = <0x00600000 0x00400000>;
103 label = "NAND Compressed RFS Image";
104 };
105
106 partition@a00000 {
107 /* 15MB for JFFS2 based Root file System */
108 reg = <0x00a00000 0x00f00000>;
109 label = "NAND JFFS2 Root File System";
110 };
111
112 partition@1900000 {
113 /* 7MB for User Area */
114 reg = <0x01900000 0x00700000>;
115 label = "NAND User area";
116 };
117 };
118
119 cpld@3,0 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,p1010rdb-cpld";
123 reg = <0x3 0x0 0x0000020>;
124 bank-width = <1>;
125 device-width = <1>;
126 };
127 };
128
129 soc@ffe00000 {
130 spi@7000 {
131 flash@0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "spansion,s25sl12801";
135 reg = <0>;
136 spi-max-frequency = <50000000>;
137
138 partition@0 {
139 /* 1MB for u-boot Bootloader Image */
140 /* 1MB for Environment */
141 reg = <0x0 0x00100000>;
142 label = "SPI Flash U-Boot Image";
143 read-only;
144 };
145
146 partition@100000 {
147 /* 512KB for DTB Image */
148 reg = <0x00100000 0x00080000>;
149 label = "SPI Flash DTB Image";
150 };
151
152 partition@180000 {
153 /* 4MB for Linux Kernel Image */
154 reg = <0x00180000 0x00400000>;
155 label = "SPI Flash Linux Kernel Image";
156 };
157
158 partition@580000 {
159 /* 4MB for Compressed RFS Image */
160 reg = <0x00580000 0x00400000>;
161 label = "SPI Flash Compressed RFSImage";
162 };
163
164 partition@980000 {
165 /* 6.5MB for JFFS2 based RFS */
166 reg = <0x00980000 0x00680000>;
167 label = "SPI Flash JFFS2 RFS";
168 };
169 };
170 };
171
172 can0@1c000 {
173 fsl,flexcan-clock-source = "platform";
174 };
175
176 can1@1d000 {
177 fsl,flexcan-clock-source = "platform";
178 };
179
180 usb@22000 {
181 phy_type = "utmi";
182 };
183
184 mdio@24000 {
185 phy0: ethernet-phy@0 {
186 interrupt-parent = <&mpic>;
187 interrupts = <3 1>;
188 reg = <0x1>;
189 };
190
191 phy1: ethernet-phy@1 {
192 interrupt-parent = <&mpic>;
193 interrupts = <2 1>;
194 reg = <0x0>;
195 };
196
197 phy2: ethernet-phy@2 {
198 interrupt-parent = <&mpic>;
199 interrupts = <2 1>;
200 reg = <0x2>;
201 };
202 };
203
204 enet0: ethernet@b0000 {
205 phy-handle = <&phy0>;
206 phy-connection-type = "rgmii-id";
207 };
208
209 enet1: ethernet@b1000 {
210 phy-handle = <&phy1>;
211 tbi-handle = <&tbi0>;
212 phy-connection-type = "sgmii";
213 };
214
215 enet2: ethernet@b2000 {
216 phy-handle = <&phy2>;
217 tbi-handle = <&tbi1>;
218 phy-connection-type = "sgmii";
219 };
220 };
221
222 pci0: pcie@ffe09000 {
223 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
224 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
225 pcie@0 {
226 reg = <0x0 0x0 0x0 0x0 0x0>;
227 #interrupt-cells = <1>;
228 #size-cells = <2>;
229 #address-cells = <3>;
230 device_type = "pci";
231 interrupt-parent = <&mpic>;
232 interrupts = <16 2>;
233 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
234 interrupt-map = <
235 /* IDSEL 0x0 */
236 0000 0x0 0x0 0x1 &mpic 0x4 0x1
237 0000 0x0 0x0 0x2 &mpic 0x5 0x1
238 0000 0x0 0x0 0x3 &mpic 0x6 0x1
239 0000 0x0 0x0 0x4 &mpic 0x7 0x1
240 >;
241
242 ranges = <0x2000000 0x0 0xa0000000
243 0x2000000 0x0 0xa0000000
244 0x0 0x20000000
245
246 0x1000000 0x0 0x0
247 0x1000000 0x0 0x0
248 0x0 0x100000>;
249 };
250 };
251
252 pci1: pcie@ffe0a000 {
253 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
254 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
255 pcie@0 {
256 reg = <0x0 0x0 0x0 0x0 0x0>;
257 #interrupt-cells = <1>;
258 #size-cells = <2>;
259 #address-cells = <3>;
260 device_type = "pci";
261 interrupt-parent = <&mpic>;
262 interrupts = <16 2>;
263 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
264 interrupt-map = <
265 /* IDSEL 0x0 */
266 0000 0x0 0x0 0x1 &mpic 0x4 0x1
267 0000 0x0 0x0 0x2 &mpic 0x5 0x1
268 0000 0x0 0x0 0x3 &mpic 0x6 0x1
269 0000 0x0 0x0 0x4 &mpic 0x7 0x1
270 >;
271 ranges = <0x2000000 0x0 0x80000000
272 0x2000000 0x0 0x80000000
273 0x0 0x20000000
274
275 0x1000000 0x0 0x0
276 0x1000000 0x0 0x0
277 0x0 0x100000>;
278 };
279 };
280};
diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
new file mode 100644
index 00000000000..7f51104f2e3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010si.dtsi
@@ -0,0 +1,376 @@
1/*
2 * P1010si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1010";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1010@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27 };
28
29 ifc@ffe1e000 {
30 #address-cells = <2>;
31 #size-cells = <1>;
32 compatible = "fsl,ifc", "simple-bus";
33 reg = <0x0 0xffe1e000 0 0x2000>;
34 interrupts = <16 2 19 2>;
35 interrupt-parent = <&mpic>;
36 };
37
38 soc@ffe00000 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 device_type = "soc";
42 compatible = "fsl,p1010-immr", "simple-bus";
43 ranges = <0x0 0x0 0xffe00000 0x100000>;
44 bus-frequency = <0>; // Filled out by uboot.
45
46 ecm-law@0 {
47 compatible = "fsl,ecm-law";
48 reg = <0x0 0x1000>;
49 fsl,num-laws = <12>;
50 };
51
52 ecm@1000 {
53 compatible = "fsl,p1010-ecm", "fsl,ecm";
54 reg = <0x1000 0x1000>;
55 interrupts = <16 2>;
56 interrupt-parent = <&mpic>;
57 };
58
59 memory-controller@2000 {
60 compatible = "fsl,p1010-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <16 2>;
64 };
65
66 i2c@3000 {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 cell-index = <0>;
70 compatible = "fsl-i2c";
71 reg = <0x3000 0x100>;
72 interrupts = <43 2>;
73 interrupt-parent = <&mpic>;
74 dfsrr;
75 };
76
77 i2c@3100 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <1>;
81 compatible = "fsl-i2c";
82 reg = <0x3100 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
88 serial0: serial@4500 {
89 cell-index = <0>;
90 device_type = "serial";
91 compatible = "ns16550";
92 reg = <0x4500 0x100>;
93 clock-frequency = <0>;
94 interrupts = <42 2>;
95 interrupt-parent = <&mpic>;
96 };
97
98 serial1: serial@4600 {
99 cell-index = <1>;
100 device_type = "serial";
101 compatible = "ns16550";
102 reg = <0x4600 0x100>;
103 clock-frequency = <0>;
104 interrupts = <42 2>;
105 interrupt-parent = <&mpic>;
106 };
107
108 spi@7000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,mpc8536-espi";
112 reg = <0x7000 0x1000>;
113 interrupts = <59 0x2>;
114 interrupt-parent = <&mpic>;
115 fsl,espi-num-chipselects = <1>;
116 };
117
118 gpio: gpio-controller@f000 {
119 #gpio-cells = <2>;
120 compatible = "fsl,mpc8572-gpio";
121 reg = <0xf000 0x100>;
122 interrupts = <47 0x2>;
123 interrupt-parent = <&mpic>;
124 gpio-controller;
125 };
126
127 sata@18000 {
128 compatible = "fsl,pq-sata-v2";
129 reg = <0x18000 0x1000>;
130 cell-index = <1>;
131 interrupts = <74 0x2>;
132 interrupt-parent = <&mpic>;
133 };
134
135 sata@19000 {
136 compatible = "fsl,pq-sata-v2";
137 reg = <0x19000 0x1000>;
138 cell-index = <2>;
139 interrupts = <41 0x2>;
140 interrupt-parent = <&mpic>;
141 };
142
143 can0@1c000 {
144 compatible = "fsl,flexcan-v1.0";
145 reg = <0x1c000 0x1000>;
146 interrupts = <48 0x2>;
147 interrupt-parent = <&mpic>;
148 fsl,flexcan-clock-divider = <2>;
149 };
150
151 can1@1d000 {
152 compatible = "fsl,flexcan-v1.0";
153 reg = <0x1d000 0x1000>;
154 interrupts = <61 0x2>;
155 interrupt-parent = <&mpic>;
156 fsl,flexcan-clock-divider = <2>;
157 };
158
159 L2: l2-cache-controller@20000 {
160 compatible = "fsl,p1010-l2-cache-controller",
161 "fsl,p1014-l2-cache-controller";
162 reg = <0x20000 0x1000>;
163 cache-line-size = <32>; // 32 bytes
164 cache-size = <0x40000>; // L2,256K
165 interrupt-parent = <&mpic>;
166 interrupts = <16 2>;
167 };
168
169 dma@21300 {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
173 reg = <0x21300 0x4>;
174 ranges = <0x0 0x21100 0x200>;
175 cell-index = <0>;
176 dma-channel@0 {
177 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
178 reg = <0x0 0x80>;
179 cell-index = <0>;
180 interrupt-parent = <&mpic>;
181 interrupts = <20 2>;
182 };
183 dma-channel@80 {
184 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>;
186 cell-index = <1>;
187 interrupt-parent = <&mpic>;
188 interrupts = <21 2>;
189 };
190 dma-channel@100 {
191 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
192 reg = <0x100 0x80>;
193 cell-index = <2>;
194 interrupt-parent = <&mpic>;
195 interrupts = <22 2>;
196 };
197 dma-channel@180 {
198 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
199 reg = <0x180 0x80>;
200 cell-index = <3>;
201 interrupt-parent = <&mpic>;
202 interrupts = <23 2>;
203 };
204 };
205
206 usb@22000 {
207 compatible = "fsl-usb2-dr";
208 reg = <0x22000 0x1000>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 interrupt-parent = <&mpic>;
212 interrupts = <28 0x2>;
213 dr_mode = "host";
214 };
215
216 mdio@24000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,etsec2-mdio";
220 reg = <0x24000 0x1000 0xb0030 0x4>;
221 };
222
223 mdio@25000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,etsec2-tbi";
227 reg = <0x25000 0x1000 0xb1030 0x4>;
228 tbi0: tbi-phy@11 {
229 reg = <0x11>;
230 device_type = "tbi-phy";
231 };
232 };
233
234 mdio@26000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "fsl,etsec2-tbi";
238 reg = <0x26000 0x1000 0xb1030 0x4>;
239 tbi1: tbi-phy@11 {
240 reg = <0x11>;
241 device_type = "tbi-phy";
242 };
243 };
244
245 sdhci@2e000 {
246 compatible = "fsl,esdhc";
247 reg = <0x2e000 0x1000>;
248 interrupts = <72 0x8>;
249 interrupt-parent = <&mpic>;
250 /* Filled in by U-Boot */
251 clock-frequency = <0>;
252 fsl,sdhci-auto-cmd12;
253 };
254
255 enet0: ethernet@b0000 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 device_type = "network";
259 model = "eTSEC";
260 compatible = "fsl,etsec2";
261 fsl,num_rx_queues = <0x8>;
262 fsl,num_tx_queues = <0x8>;
263 local-mac-address = [ 00 00 00 00 00 00 ];
264 interrupt-parent = <&mpic>;
265
266 queue-group@0 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 reg = <0xb0000 0x1000>;
270 fsl,rx-bit-map = <0xff>;
271 fsl,tx-bit-map = <0xff>;
272 interrupts = <29 2 30 2 34 2>;
273 };
274
275 };
276
277 enet1: ethernet@b1000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "fsl,etsec2";
283 fsl,num_rx_queues = <0x8>;
284 fsl,num_tx_queues = <0x8>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupt-parent = <&mpic>;
287
288 queue-group@0 {
289 #address-cells = <1>;
290 #size-cells = <1>;
291 reg = <0xb1000 0x1000>;
292 fsl,rx-bit-map = <0xff>;
293 fsl,tx-bit-map = <0xff>;
294 interrupts = <35 2 36 2 40 2>;
295 };
296
297 };
298
299 enet2: ethernet@b2000 {
300 #address-cells = <1>;
301 #size-cells = <1>;
302 device_type = "network";
303 model = "eTSEC";
304 compatible = "fsl,etsec2";
305 fsl,num_rx_queues = <0x8>;
306 fsl,num_tx_queues = <0x8>;
307 local-mac-address = [ 00 00 00 00 00 00 ];
308 interrupt-parent = <&mpic>;
309
310 queue-group@0 {
311 #address-cells = <1>;
312 #size-cells = <1>;
313 reg = <0xb2000 0x1000>;
314 fsl,rx-bit-map = <0xff>;
315 fsl,tx-bit-map = <0xff>;
316 interrupts = <31 2 32 2 33 2>;
317 };
318
319 };
320
321 mpic: pic@40000 {
322 interrupt-controller;
323 #address-cells = <0>;
324 #interrupt-cells = <2>;
325 reg = <0x40000 0x40000>;
326 compatible = "chrp,open-pic";
327 device_type = "open-pic";
328 };
329
330 msi@41600 {
331 compatible = "fsl,p1010-msi", "fsl,mpic-msi";
332 reg = <0x41600 0x80>;
333 msi-available-ranges = <0 0x100>;
334 interrupts = <
335 0xe0 0
336 0xe1 0
337 0xe2 0
338 0xe3 0
339 0xe4 0
340 0xe5 0
341 0xe6 0
342 0xe7 0>;
343 interrupt-parent = <&mpic>;
344 };
345
346 global-utilities@e0000 { //global utilities block
347 compatible = "fsl,p1010-guts";
348 reg = <0xe0000 0x1000>;
349 fsl,has-rstcr;
350 };
351 };
352
353 pci0: pcie@ffe09000 {
354 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
355 device_type = "pci";
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0 0xffe09000 0 0x1000>;
359 bus-range = <0 255>;
360 clock-frequency = <33333333>;
361 interrupt-parent = <&mpic>;
362 interrupts = <16 2>;
363 };
364
365 pci1: pcie@ffe0a000 {
366 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
367 device_type = "pci";
368 #size-cells = <2>;
369 #address-cells = <3>;
370 reg = <0 0xffe0a000 0 0x1000>;
371 bus-range = <0 255>;
372 clock-frequency = <33333333>;
373 interrupt-parent = <&mpic>;
374 interrupts = <16 2>;
375 };
376};
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index 98d9426d4b8..1be9743ab5e 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -412,7 +412,6 @@
412 fsl,magic-packet; 412 fsl,magic-packet;
413 fsl,wake-on-filer; 413 fsl,wake-on-filer;
414 local-mac-address = [ 00 00 00 00 00 00 ]; 414 local-mac-address = [ 00 00 00 00 00 00 ];
415 fixed-link = <1 1 1000 0 0>;
416 phy-handle = <&phy0>; 415 phy-handle = <&phy0>;
417 phy-connection-type = "rgmii-id"; 416 phy-connection-type = "rgmii-id";
418 queue-group@0{ 417 queue-group@0{
@@ -439,7 +438,6 @@
439 fsl,num_rx_queues = <0x8>; 438 fsl,num_rx_queues = <0x8>;
440 fsl,num_tx_queues = <0x8>; 439 fsl,num_tx_queues = <0x8>;
441 local-mac-address = [ 00 00 00 00 00 00 ]; 440 local-mac-address = [ 00 00 00 00 00 00 ];
442 fixed-link = <1 1 1000 0 0>;
443 phy-handle = <&phy1>; 441 phy-handle = <&phy1>;
444 phy-connection-type = "rgmii-id"; 442 phy-connection-type = "rgmii-id";
445 queue-group@0{ 443 queue-group@0{
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
new file mode 100644
index 00000000000..d9b776740a6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -0,0 +1,546 @@
1/*
2 * P1023 RDS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Author: Roy Zang <tie-fei.zang@freescale.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of Freescale Semiconductor nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation, either version 2 of that License or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
26 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
29 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/dts-v1/;
38
39/ {
40 model = "fsl,P1023";
41 compatible = "fsl,P1023RDS";
42 #address-cells = <2>;
43 #size-cells = <2>;
44
45 aliases {
46 serial0 = &serial0;
47 serial1 = &serial1;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51
52 crypto = &crypto;
53 sec_jr0 = &sec_jr0;
54 sec_jr1 = &sec_jr1;
55 sec_jr2 = &sec_jr2;
56 sec_jr3 = &sec_jr3;
57 rtic_a = &rtic_a;
58 rtic_b = &rtic_b;
59 rtic_c = &rtic_c;
60 rtic_d = &rtic_d;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,P1023@0 {
68 device_type = "cpu";
69 reg = <0x0>;
70 next-level-cache = <&L2>;
71 };
72
73 cpu1: PowerPC,P1023@1 {
74 device_type = "cpu";
75 reg = <0x1>;
76 next-level-cache = <&L2>;
77 };
78 };
79
80 memory {
81 device_type = "memory";
82 };
83
84 soc@ff600000 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 device_type = "soc";
88 compatible = "fsl,p1023-immr", "simple-bus";
89 ranges = <0x0 0x0 0xff600000 0x200000>;
90 bus-frequency = <0>; // Filled out by uboot.
91
92 ecm-law@0 {
93 compatible = "fsl,ecm-law";
94 reg = <0x0 0x1000>;
95 fsl,num-laws = <12>;
96 };
97
98 ecm@1000 {
99 compatible = "fsl,p1023-ecm", "fsl,ecm";
100 reg = <0x1000 0x1000>;
101 interrupts = <16 2>;
102 interrupt-parent = <&mpic>;
103 };
104
105 memory-controller@2000 {
106 compatible = "fsl,p1023-memory-controller";
107 reg = <0x2000 0x1000>;
108 interrupt-parent = <&mpic>;
109 interrupts = <16 2>;
110 };
111
112 i2c@3000 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 cell-index = <0>;
116 compatible = "fsl-i2c";
117 reg = <0x3000 0x100>;
118 interrupts = <43 2>;
119 interrupt-parent = <&mpic>;
120 dfsrr;
121 rtc@68 {
122 compatible = "dallas,ds1374";
123 reg = <0x68>;
124 };
125 };
126
127 i2c@3100 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <1>;
131 compatible = "fsl-i2c";
132 reg = <0x3100 0x100>;
133 interrupts = <43 2>;
134 interrupt-parent = <&mpic>;
135 dfsrr;
136 };
137
138 serial0: serial@4500 {
139 cell-index = <0>;
140 device_type = "serial";
141 compatible = "ns16550";
142 reg = <0x4500 0x100>;
143 clock-frequency = <0>;
144 interrupts = <42 2>;
145 interrupt-parent = <&mpic>;
146 };
147
148 serial1: serial@4600 {
149 cell-index = <1>;
150 device_type = "serial";
151 compatible = "ns16550";
152 reg = <0x4600 0x100>;
153 clock-frequency = <0>;
154 interrupts = <42 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 spi@7000 {
159 cell-index = <0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
163 reg = <0x7000 0x1000>;
164 interrupts = <59 0x2>;
165 interrupt-parent = <&mpic>;
166 fsl,espi-num-chipselects = <4>;
167
168 fsl_dataflash@0 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 compatible = "atmel,at45db081d";
172 reg = <0>;
173 spi-max-frequency = <40000000>; /* input clock */
174 partition@u-boot {
175 /* 512KB for u-boot Bootloader Image */
176 label = "u-boot-spi";
177 reg = <0x00000000 0x00080000>;
178 read-only;
179 };
180 partition@dtb {
181 /* 512KB for DTB Image */
182 label = "dtb-spi";
183 reg = <0x00080000 0x00080000>;
184 read-only;
185 };
186 };
187 };
188
189 gpio: gpio-controller@f000 {
190 #gpio-cells = <2>;
191 compatible = "fsl,qoriq-gpio";
192 reg = <0xf000 0x100>;
193 interrupts = <47 0x2>;
194 interrupt-parent = <&mpic>;
195 gpio-controller;
196 };
197
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,p1023-l2-cache-controller";
200 reg = <0x20000 0x1000>;
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x40000>; // L2,256K
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
205 };
206
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,eloplus-dma-channel";
216 reg = <0x0 0x80>;
217 cell-index = <0>;
218 interrupt-parent = <&mpic>;
219 interrupts = <20 2>;
220 };
221 dma-channel@80 {
222 compatible = "fsl,eloplus-dma-channel";
223 reg = <0x80 0x80>;
224 cell-index = <1>;
225 interrupt-parent = <&mpic>;
226 interrupts = <21 2>;
227 };
228 dma-channel@100 {
229 compatible = "fsl,eloplus-dma-channel";
230 reg = <0x100 0x80>;
231 cell-index = <2>;
232 interrupt-parent = <&mpic>;
233 interrupts = <22 2>;
234 };
235 dma-channel@180 {
236 compatible = "fsl,eloplus-dma-channel";
237 reg = <0x180 0x80>;
238 cell-index = <3>;
239 interrupt-parent = <&mpic>;
240 interrupts = <23 2>;
241 };
242 };
243
244 usb@22000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "fsl-usb2-dr";
248 reg = <0x22000 0x1000>;
249 interrupt-parent = <&mpic>;
250 interrupts = <28 0x2>;
251 dr_mode = "host";
252 phy_type = "ulpi";
253 };
254
255 crypto: crypto@300000 {
256 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 reg = <0x30000 0x10000>;
260 ranges = <0 0x30000 0x10000>;
261 interrupt-parent = <&mpic>;
262 interrupts = <58 2>;
263
264 sec_jr0: jr@1000 {
265 compatible = "fsl,sec-v4.2-job-ring",
266 "fsl,sec-v4.0-job-ring";
267 reg = <0x1000 0x1000>;
268 interrupts = <45 2>;
269 };
270
271 sec_jr1: jr@2000 {
272 compatible = "fsl,sec-v4.2-job-ring",
273 "fsl,sec-v4.0-job-ring";
274 reg = <0x2000 0x1000>;
275 interrupts = <45 2>;
276 };
277
278 sec_jr2: jr@3000 {
279 compatible = "fsl,sec-v4.2-job-ring",
280 "fsl,sec-v4.0-job-ring";
281 reg = <0x3000 0x1000>;
282 interrupts = <57 2>;
283 };
284
285 sec_jr3: jr@4000 {
286 compatible = "fsl,sec-v4.2-job-ring",
287 "fsl,sec-v4.0-job-ring";
288 reg = <0x4000 0x1000>;
289 interrupts = <57 2>;
290 };
291
292 rtic@6000 {
293 compatible = "fsl,sec-v4.2-rtic",
294 "fsl,sec-v4.0-rtic";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 reg = <0x6000 0x100>;
298 ranges = <0x0 0x6100 0xe00>;
299
300 rtic_a: rtic-a@0 {
301 compatible = "fsl,sec-v4.2-rtic-memory",
302 "fsl,sec-v4.0-rtic-memory";
303 reg = <0x00 0x20 0x100 0x80>;
304 };
305
306 rtic_b: rtic-b@20 {
307 compatible = "fsl,sec-v4.2-rtic-memory",
308 "fsl,sec-v4.0-rtic-memory";
309 reg = <0x20 0x20 0x200 0x80>;
310 };
311
312 rtic_c: rtic-c@40 {
313 compatible = "fsl,sec-v4.2-rtic-memory",
314 "fsl,sec-v4.0-rtic-memory";
315 reg = <0x40 0x20 0x300 0x80>;
316 };
317
318 rtic_d: rtic-d@60 {
319 compatible = "fsl,sec-v4.2-rtic-memory",
320 "fsl,sec-v4.0-rtic-memory";
321 reg = <0x60 0x20 0x500 0x80>;
322 };
323 };
324 };
325
326 power@e0070{
327 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
328 "fsl,p1022-pmc";
329 reg = <0xe0070 0x20>;
330 etsec1_clk: soc-clk@B0{
331 fsl,pmcdr-mask = <0x00000080>;
332 };
333 etsec2_clk: soc-clk@B1{
334 fsl,pmcdr-mask = <0x00000040>;
335 };
336 etsec3_clk: soc-clk@B2{
337 fsl,pmcdr-mask = <0x00000020>;
338 };
339 };
340
341 mpic: pic@40000 {
342 interrupt-controller;
343 #address-cells = <0>;
344 #interrupt-cells = <2>;
345 reg = <0x40000 0x40000>;
346 compatible = "chrp,open-pic";
347 device_type = "open-pic";
348 };
349
350 msi@41600 {
351 compatible = "fsl,p1023-msi", "fsl,mpic-msi";
352 reg = <0x41600 0x80>;
353 msi-available-ranges = <0 0x100>;
354 interrupts = <
355 0xe0 0
356 0xe1 0
357 0xe2 0
358 0xe3 0
359 0xe4 0
360 0xe5 0
361 0xe6 0
362 0xe7 0>;
363 interrupt-parent = <&mpic>;
364 };
365
366 global-utilities@e0000 { //global utilities block
367 compatible = "fsl,p1023-guts";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 };
371 };
372
373 localbus@ff605000 {
374 #address-cells = <2>;
375 #size-cells = <1>;
376 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
377 reg = <0 0xff605000 0 0x1000>;
378 interrupts = <19 2>;
379 interrupt-parent = <&mpic>;
380
381 /* NOR Flash, BCSR */
382 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
383 0x1 0x0 0x0 0xe0000000 0x00008000>;
384
385 nor@0,0 {
386 #address-cells = <1>;
387 #size-cells = <1>;
388 compatible = "cfi-flash";
389 reg = <0x0 0x0 0x02000000>;
390 bank-width = <2>;
391 device-width = <1>;
392 partition@0 {
393 label = "ramdisk";
394 reg = <0x00000000 0x01c00000>;
395 };
396 partition@1c00000 {
397 label = "kernel";
398 reg = <0x01c00000 0x002e0000>;
399 };
400 partiton@1ee0000 {
401 label = "dtb";
402 reg = <0x01ee0000 0x00020000>;
403 };
404 partition@1f00000 {
405 label = "firmware";
406 reg = <0x01f00000 0x00080000>;
407 read-only;
408 };
409 partition@1f80000 {
410 label = "u-boot";
411 reg = <0x01f80000 0x00080000>;
412 read-only;
413 };
414 };
415
416 fpga@1,0 {
417 #address-cells = <1>;
418 #size-cells = <1>;
419 compatible = "fsl,p1023rds-fpga";
420 reg = <1 0 0x8000>;
421 ranges = <0 1 0 0x8000>;
422
423 bcsr@20 {
424 compatible = "fsl,p1023rds-bcsr";
425 reg = <0x20 0x20>;
426 };
427 };
428 };
429
430 pci0: pcie@ff60a000 {
431 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
432 cell-index = <1>;
433 device_type = "pci";
434 #size-cells = <2>;
435 #address-cells = <3>;
436 reg = <0 0xff60a000 0 0x1000>;
437 bus-range = <0 255>;
438 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
439 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
440 clock-frequency = <33333333>;
441 interrupt-parent = <&mpic>;
442 interrupts = <16 2>;
443 pcie@0 {
444 reg = <0x0 0x0 0x0 0x0 0x0>;
445 #interrupt-cells = <1>;
446 #size-cells = <2>;
447 #address-cells = <3>;
448 device_type = "pci";
449 interrupt-parent = <&mpic>;
450 interrupts = <16 2>;
451 interrupt-map-mask = <0xf800 0 0 7>;
452 interrupt-map = <
453 /* IDSEL 0x0 */
454 0000 0 0 1 &mpic 0 1
455 0000 0 0 2 &mpic 1 1
456 0000 0 0 3 &mpic 2 1
457 0000 0 0 4 &mpic 3 1
458 >;
459 ranges = <0x2000000 0x0 0xc0000000
460 0x2000000 0x0 0xc0000000
461 0x0 0x20000000
462
463 0x1000000 0x0 0x0
464 0x1000000 0x0 0x0
465 0x0 0x100000>;
466 };
467 };
468
469 pci1: pcie@ff609000 {
470 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
471 cell-index = <2>;
472 device_type = "pci";
473 #size-cells = <2>;
474 #address-cells = <3>;
475 reg = <0 0xff609000 0 0x1000>;
476 bus-range = <0 255>;
477 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
478 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
479 clock-frequency = <33333333>;
480 interrupt-parent = <&mpic>;
481 interrupts = <16 2>;
482 pcie@0 {
483 reg = <0x0 0x0 0x0 0x0 0x0>;
484 #interrupt-cells = <1>;
485 #size-cells = <2>;
486 #address-cells = <3>;
487 device_type = "pci";
488 interrupt-parent = <&mpic>;
489 interrupts = <16 2>;
490 interrupt-map-mask = <0xf800 0 0 7>;
491 interrupt-map = <
492 /* IDSEL 0x0 */
493 0000 0 0 1 &mpic 4 1
494 0000 0 0 2 &mpic 5 1
495 0000 0 0 3 &mpic 6 1
496 0000 0 0 4 &mpic 7 1
497 >;
498 ranges = <0x2000000 0x0 0xa0000000
499 0x2000000 0x0 0xa0000000
500 0x0 0x20000000
501
502 0x1000000 0x0 0x0
503 0x1000000 0x0 0x0
504 0x0 0x100000>;
505 };
506 };
507
508 pci2: pcie@ff60b000 {
509 cell-index = <3>;
510 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
511 device_type = "pci";
512 #size-cells = <2>;
513 #address-cells = <3>;
514 reg = <0 0xff60b000 0 0x1000>;
515 bus-range = <0 255>;
516 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
517 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
518 clock-frequency = <33333333>;
519 interrupt-parent = <&mpic>;
520 interrupts = <16 2>;
521 pcie@0 {
522 reg = <0x0 0x0 0x0 0x0 0x0>;
523 #interrupt-cells = <1>;
524 #size-cells = <2>;
525 #address-cells = <3>;
526 device_type = "pci";
527 interrupt-parent = <&mpic>;
528 interrupts = <16 2>;
529 interrupt-map-mask = <0xf800 0 0 7>;
530 interrupt-map = <
531 /* IDSEL 0x0 */
532 0000 0 0 1 &mpic 8 1
533 0000 0 0 2 &mpic 9 1
534 0000 0 0 3 &mpic 10 1
535 0000 0 0 4 &mpic 11 1
536 >;
537 ranges = <0x2000000 0x0 0x80000000
538 0x2000000 0x0 0x80000000
539 0x0 0x20000000
540
541 0x1000000 0x0 0x0
542 0x1000000 0x0 0x0
543 0x0 0x100000>;
544 };
545 };
546};
diff --git a/arch/powerpc/boot/dts/p2040rdb.dts b/arch/powerpc/boot/dts/p2040rdb.dts
new file mode 100644
index 00000000000..7d84e391c63
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2040rdb.dts
@@ -0,0 +1,166 @@
1/*
2 * P2040RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p2040si.dtsi"
36
37/ {
38 model = "fsl,P2040RDB";
39 compatible = "fsl,P2040RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118000 {
79 lm75b@48 {
80 compatible = "nxp,lm75a";
81 reg = <0x48>;
82 };
83 eeprom@50 {
84 compatible = "at24,24c256";
85 reg = <0x50>;
86 };
87 rtc@68 {
88 compatible = "pericom,pt7c4338";
89 reg = <0x68>;
90 };
91 };
92
93 i2c@118100 {
94 eeprom@50 {
95 compatible = "at24,24c256";
96 reg = <0x50>;
97 };
98 };
99
100 usb0: usb@210000 {
101 phy_type = "utmi";
102 };
103
104 usb1: usb@211000 {
105 dr_mode = "host";
106 phy_type = "utmi";
107 };
108 };
109
110 localbus@ffe124000 {
111 reg = <0xf 0xfe124000 0 0x1000>;
112 ranges = <0 0 0xf 0xe8000000 0x08000000>;
113
114 flash@0,0 {
115 compatible = "cfi-flash";
116 reg = <0 0 0x08000000>;
117 bank-width = <2>;
118 device-width = <2>;
119 };
120 };
121
122 pci0: pcie@ffe200000 {
123 reg = <0xf 0xfe200000 0 0x1000>;
124 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
125 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
126 pcie@0 {
127 ranges = <0x02000000 0 0xe0000000
128 0x02000000 0 0xe0000000
129 0 0x20000000
130
131 0x01000000 0 0x00000000
132 0x01000000 0 0x00000000
133 0 0x00010000>;
134 };
135 };
136
137 pci1: pcie@ffe201000 {
138 reg = <0xf 0xfe201000 0 0x1000>;
139 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
140 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
141 pcie@0 {
142 ranges = <0x02000000 0 0xe0000000
143 0x02000000 0 0xe0000000
144 0 0x20000000
145
146 0x01000000 0 0x00000000
147 0x01000000 0 0x00000000
148 0 0x00010000>;
149 };
150 };
151
152 pci2: pcie@ffe202000 {
153 reg = <0xf 0xfe202000 0 0x1000>;
154 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
155 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
156 pcie@0 {
157 ranges = <0x02000000 0 0xe0000000
158 0x02000000 0 0xe0000000
159 0 0x20000000
160
161 0x01000000 0 0x00000000
162 0x01000000 0 0x00000000
163 0 0x00010000>;
164 };
165 };
166};
diff --git a/arch/powerpc/boot/dts/p2040si.dtsi b/arch/powerpc/boot/dts/p2040si.dtsi
new file mode 100644
index 00000000000..5fdbb24c076
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2040si.dtsi
@@ -0,0 +1,623 @@
1/*
2 * P2040 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P2040";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: PowerPC,e500mc@0 {
79 device_type = "cpu";
80 reg = <0>;
81 next-level-cache = <&L2_0>;
82 L2_0: l2-cache {
83 next-level-cache = <&cpc>;
84 };
85 };
86 cpu1: PowerPC,e500mc@1 {
87 device_type = "cpu";
88 reg = <1>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu2: PowerPC,e500mc@2 {
95 device_type = "cpu";
96 reg = <2>;
97 next-level-cache = <&L2_2>;
98 L2_2: l2-cache {
99 next-level-cache = <&cpc>;
100 };
101 };
102 cpu3: PowerPC,e500mc@3 {
103 device_type = "cpu";
104 reg = <3>;
105 next-level-cache = <&L2_3>;
106 L2_3: l2-cache {
107 next-level-cache = <&cpc>;
108 };
109 };
110 };
111
112 soc: soc@ffe000000 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 device_type = "soc";
116 compatible = "simple-bus";
117 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
118 reg = <0xf 0xfe000000 0 0x00001000>;
119
120 soc-sram-error {
121 compatible = "fsl,soc-sram-error";
122 interrupts = <16 2 1 29>;
123 };
124
125 corenet-law@0 {
126 compatible = "fsl,corenet-law";
127 reg = <0x0 0x1000>;
128 fsl,num-laws = <32>;
129 };
130
131 memory-controller@8000 {
132 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
133 reg = <0x8000 0x1000>;
134 interrupts = <16 2 1 23>;
135 };
136
137 cpc: l3-cache-controller@10000 {
138 compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
139 reg = <0x10000 0x1000>;
140 interrupts = <16 2 1 27>;
141 };
142
143 corenet-cf@18000 {
144 compatible = "fsl,corenet-cf";
145 reg = <0x18000 0x1000>;
146 interrupts = <16 2 1 31>;
147 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>;
149 };
150
151 iommu@20000 {
152 compatible = "fsl,pamu-v1.0", "fsl,pamu";
153 reg = <0x20000 0x4000>;
154 interrupts = <
155 24 2 0 0
156 16 2 1 30>;
157 };
158
159 mpic: pic@40000 {
160 clock-frequency = <0>;
161 interrupt-controller;
162 #address-cells = <0>;
163 #interrupt-cells = <4>;
164 reg = <0x40000 0x40000>;
165 compatible = "fsl,mpic", "chrp,open-pic";
166 device_type = "open-pic";
167 };
168
169 msi0: msi@41600 {
170 compatible = "fsl,mpic-msi";
171 reg = <0x41600 0x200>;
172 msi-available-ranges = <0 0x100>;
173 interrupts = <
174 0xe0 0 0 0
175 0xe1 0 0 0
176 0xe2 0 0 0
177 0xe3 0 0 0
178 0xe4 0 0 0
179 0xe5 0 0 0
180 0xe6 0 0 0
181 0xe7 0 0 0>;
182 };
183
184 msi1: msi@41800 {
185 compatible = "fsl,mpic-msi";
186 reg = <0x41800 0x200>;
187 msi-available-ranges = <0 0x100>;
188 interrupts = <
189 0xe8 0 0 0
190 0xe9 0 0 0
191 0xea 0 0 0
192 0xeb 0 0 0
193 0xec 0 0 0
194 0xed 0 0 0
195 0xee 0 0 0
196 0xef 0 0 0>;
197 };
198
199 msi2: msi@41a00 {
200 compatible = "fsl,mpic-msi";
201 reg = <0x41a00 0x200>;
202 msi-available-ranges = <0 0x100>;
203 interrupts = <
204 0xf0 0 0 0
205 0xf1 0 0 0
206 0xf2 0 0 0
207 0xf3 0 0 0
208 0xf4 0 0 0
209 0xf5 0 0 0
210 0xf6 0 0 0
211 0xf7 0 0 0>;
212 };
213
214 guts: global-utilities@e0000 {
215 compatible = "fsl,qoriq-device-config-1.0";
216 reg = <0xe0000 0xe00>;
217 fsl,has-rstcr;
218 #sleep-cells = <1>;
219 fsl,liodn-bits = <12>;
220 };
221
222 pins: global-utilities@e0e00 {
223 compatible = "fsl,qoriq-pin-control-1.0";
224 reg = <0xe0e00 0x200>;
225 #sleep-cells = <2>;
226 };
227
228 clockgen: global-utilities@e1000 {
229 compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
230 reg = <0xe1000 0x1000>;
231 clock-frequency = <0>;
232 };
233
234 rcpm: global-utilities@e2000 {
235 compatible = "fsl,qoriq-rcpm-1.0";
236 reg = <0xe2000 0x1000>;
237 #sleep-cells = <1>;
238 };
239
240 sfp: sfp@e8000 {
241 compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
242 reg = <0xe8000 0x1000>;
243 };
244
245 serdes: serdes@ea000 {
246 compatible = "fsl,p2040-serdes";
247 reg = <0xea000 0x1000>;
248 };
249
250 dma0: dma@100300 {
251 #address-cells = <1>;
252 #size-cells = <1>;
253 compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
254 reg = <0x100300 0x4>;
255 ranges = <0x0 0x100100 0x200>;
256 cell-index = <0>;
257 dma-channel@0 {
258 compatible = "fsl,p2040-dma-channel",
259 "fsl,eloplus-dma-channel";
260 reg = <0x0 0x80>;
261 cell-index = <0>;
262 interrupts = <28 2 0 0>;
263 };
264 dma-channel@80 {
265 compatible = "fsl,p2040-dma-channel",
266 "fsl,eloplus-dma-channel";
267 reg = <0x80 0x80>;
268 cell-index = <1>;
269 interrupts = <29 2 0 0>;
270 };
271 dma-channel@100 {
272 compatible = "fsl,p2040-dma-channel",
273 "fsl,eloplus-dma-channel";
274 reg = <0x100 0x80>;
275 cell-index = <2>;
276 interrupts = <30 2 0 0>;
277 };
278 dma-channel@180 {
279 compatible = "fsl,p2040-dma-channel",
280 "fsl,eloplus-dma-channel";
281 reg = <0x180 0x80>;
282 cell-index = <3>;
283 interrupts = <31 2 0 0>;
284 };
285 };
286
287 dma1: dma@101300 {
288 #address-cells = <1>;
289 #size-cells = <1>;
290 compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
291 reg = <0x101300 0x4>;
292 ranges = <0x0 0x101100 0x200>;
293 cell-index = <1>;
294 dma-channel@0 {
295 compatible = "fsl,p2040-dma-channel",
296 "fsl,eloplus-dma-channel";
297 reg = <0x0 0x80>;
298 cell-index = <0>;
299 interrupts = <32 2 0 0>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,p2040-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupts = <33 2 0 0>;
307 };
308 dma-channel@100 {
309 compatible = "fsl,p2040-dma-channel",
310 "fsl,eloplus-dma-channel";
311 reg = <0x100 0x80>;
312 cell-index = <2>;
313 interrupts = <34 2 0 0>;
314 };
315 dma-channel@180 {
316 compatible = "fsl,p2040-dma-channel",
317 "fsl,eloplus-dma-channel";
318 reg = <0x180 0x80>;
319 cell-index = <3>;
320 interrupts = <35 2 0 0>;
321 };
322 };
323
324 spi@110000 {
325 #address-cells = <1>;
326 #size-cells = <0>;
327 compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
328 reg = <0x110000 0x1000>;
329 interrupts = <53 0x2 0 0>;
330 fsl,espi-num-chipselects = <4>;
331
332 };
333
334 sdhc: sdhc@114000 {
335 compatible = "fsl,p2040-esdhc", "fsl,esdhc";
336 reg = <0x114000 0x1000>;
337 interrupts = <48 2 0 0>;
338 sdhci,auto-cmd12;
339 clock-frequency = <0>;
340 };
341
342
343 i2c@118000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 cell-index = <0>;
347 compatible = "fsl-i2c";
348 reg = <0x118000 0x100>;
349 interrupts = <38 2 0 0>;
350 dfsrr;
351 };
352
353 i2c@118100 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 cell-index = <1>;
357 compatible = "fsl-i2c";
358 reg = <0x118100 0x100>;
359 interrupts = <38 2 0 0>;
360 dfsrr;
361 };
362
363 i2c@119000 {
364 #address-cells = <1>;
365 #size-cells = <0>;
366 cell-index = <2>;
367 compatible = "fsl-i2c";
368 reg = <0x119000 0x100>;
369 interrupts = <39 2 0 0>;
370 dfsrr;
371 };
372
373 i2c@119100 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 cell-index = <3>;
377 compatible = "fsl-i2c";
378 reg = <0x119100 0x100>;
379 interrupts = <39 2 0 0>;
380 dfsrr;
381 };
382
383 serial0: serial@11c500 {
384 cell-index = <0>;
385 device_type = "serial";
386 compatible = "ns16550";
387 reg = <0x11c500 0x100>;
388 clock-frequency = <0>;
389 interrupts = <36 2 0 0>;
390 };
391
392 serial1: serial@11c600 {
393 cell-index = <1>;
394 device_type = "serial";
395 compatible = "ns16550";
396 reg = <0x11c600 0x100>;
397 clock-frequency = <0>;
398 interrupts = <36 2 0 0>;
399 };
400
401 serial2: serial@11d500 {
402 cell-index = <2>;
403 device_type = "serial";
404 compatible = "ns16550";
405 reg = <0x11d500 0x100>;
406 clock-frequency = <0>;
407 interrupts = <37 2 0 0>;
408 };
409
410 serial3: serial@11d600 {
411 cell-index = <3>;
412 device_type = "serial";
413 compatible = "ns16550";
414 reg = <0x11d600 0x100>;
415 clock-frequency = <0>;
416 interrupts = <37 2 0 0>;
417 };
418
419 gpio0: gpio@130000 {
420 compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
421 reg = <0x130000 0x1000>;
422 interrupts = <55 2 0 0>;
423 #gpio-cells = <2>;
424 gpio-controller;
425 };
426
427 usb0: usb@210000 {
428 compatible = "fsl,p2040-usb2-mph",
429 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
430 reg = <0x210000 0x1000>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 interrupts = <44 0x2 0 0>;
434 port0;
435 };
436
437 usb1: usb@211000 {
438 compatible = "fsl,p2040-usb2-dr",
439 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
440 reg = <0x211000 0x1000>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 interrupts = <45 0x2 0 0>;
444 };
445
446 sata@220000 {
447 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
448 reg = <0x220000 0x1000>;
449 interrupts = <68 0x2 0 0>;
450 };
451
452 sata@221000 {
453 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
454 reg = <0x221000 0x1000>;
455 interrupts = <69 0x2 0 0>;
456 };
457
458 crypto: crypto@300000 {
459 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
460 #address-cells = <1>;
461 #size-cells = <1>;
462 reg = <0x300000 0x10000>;
463 ranges = <0 0x300000 0x10000>;
464 interrupts = <92 2 0 0>;
465
466 sec_jr0: jr@1000 {
467 compatible = "fsl,sec-v4.2-job-ring",
468 "fsl,sec-v4.0-job-ring";
469 reg = <0x1000 0x1000>;
470 interrupts = <88 2 0 0>;
471 };
472
473 sec_jr1: jr@2000 {
474 compatible = "fsl,sec-v4.2-job-ring",
475 "fsl,sec-v4.0-job-ring";
476 reg = <0x2000 0x1000>;
477 interrupts = <89 2 0 0>;
478 };
479
480 sec_jr2: jr@3000 {
481 compatible = "fsl,sec-v4.2-job-ring",
482 "fsl,sec-v4.0-job-ring";
483 reg = <0x3000 0x1000>;
484 interrupts = <90 2 0 0>;
485 };
486
487 sec_jr3: jr@4000 {
488 compatible = "fsl,sec-v4.2-job-ring",
489 "fsl,sec-v4.0-job-ring";
490 reg = <0x4000 0x1000>;
491 interrupts = <91 2 0 0>;
492 };
493
494 rtic@6000 {
495 compatible = "fsl,sec-v4.2-rtic",
496 "fsl,sec-v4.0-rtic";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 reg = <0x6000 0x100>;
500 ranges = <0x0 0x6100 0xe00>;
501
502 rtic_a: rtic-a@0 {
503 compatible = "fsl,sec-v4.2-rtic-memory",
504 "fsl,sec-v4.0-rtic-memory";
505 reg = <0x00 0x20 0x100 0x80>;
506 };
507
508 rtic_b: rtic-b@20 {
509 compatible = "fsl,sec-v4.2-rtic-memory",
510 "fsl,sec-v4.0-rtic-memory";
511 reg = <0x20 0x20 0x200 0x80>;
512 };
513
514 rtic_c: rtic-c@40 {
515 compatible = "fsl,sec-v4.2-rtic-memory",
516 "fsl,sec-v4.0-rtic-memory";
517 reg = <0x40 0x20 0x300 0x80>;
518 };
519
520 rtic_d: rtic-d@60 {
521 compatible = "fsl,sec-v4.2-rtic-memory",
522 "fsl,sec-v4.0-rtic-memory";
523 reg = <0x60 0x20 0x500 0x80>;
524 };
525 };
526 };
527
528 sec_mon: sec_mon@314000 {
529 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
530 reg = <0x314000 0x1000>;
531 interrupts = <93 2 0 0>;
532 };
533
534 };
535
536 localbus@ffe124000 {
537 compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
538 interrupts = <25 2 0 0>;
539 #address-cells = <2>;
540 #size-cells = <1>;
541 };
542
543 pci0: pcie@ffe200000 {
544 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
545 device_type = "pci";
546 #size-cells = <2>;
547 #address-cells = <3>;
548 bus-range = <0x0 0xff>;
549 clock-frequency = <0x1fca055>;
550 fsl,msi = <&msi0>;
551 interrupts = <16 2 1 15>;
552 pcie@0 {
553 reg = <0 0 0 0 0>;
554 #interrupt-cells = <1>;
555 #size-cells = <2>;
556 #address-cells = <3>;
557 device_type = "pci";
558 interrupts = <16 2 1 15>;
559 interrupt-map-mask = <0xf800 0 0 7>;
560 interrupt-map = <
561 /* IDSEL 0x0 */
562 0000 0 0 1 &mpic 40 1 0 0
563 0000 0 0 2 &mpic 1 1 0 0
564 0000 0 0 3 &mpic 2 1 0 0
565 0000 0 0 4 &mpic 3 1 0 0
566 >;
567 };
568 };
569
570 pci1: pcie@ffe201000 {
571 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
572 device_type = "pci";
573 #size-cells = <2>;
574 #address-cells = <3>;
575 bus-range = <0 0xff>;
576 clock-frequency = <0x1fca055>;
577 fsl,msi = <&msi1>;
578 interrupts = <16 2 1 14>;
579 pcie@0 {
580 reg = <0 0 0 0 0>;
581 #interrupt-cells = <1>;
582 #size-cells = <2>;
583 #address-cells = <3>;
584 device_type = "pci";
585 interrupts = <16 2 1 14>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 41 1 0 0
590 0000 0 0 2 &mpic 5 1 0 0
591 0000 0 0 3 &mpic 6 1 0 0
592 0000 0 0 4 &mpic 7 1 0 0
593 >;
594 };
595 };
596
597 pci2: pcie@ffe202000 {
598 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
599 device_type = "pci";
600 #size-cells = <2>;
601 #address-cells = <3>;
602 bus-range = <0x0 0xff>;
603 clock-frequency = <0x1fca055>;
604 fsl,msi = <&msi2>;
605 interrupts = <16 2 1 13>;
606 pcie@0 {
607 reg = <0 0 0 0 0>;
608 #interrupt-cells = <1>;
609 #size-cells = <2>;
610 #address-cells = <3>;
611 device_type = "pci";
612 interrupts = <16 2 1 13>;
613 interrupt-map-mask = <0xf800 0 0 7>;
614 interrupt-map = <
615 /* IDSEL 0x0 */
616 0000 0 0 1 &mpic 42 1 0 0
617 0000 0 0 2 &mpic 9 1 0 0
618 0000 0 0 3 &mpic 10 1 0 0
619 0000 0 0 4 &mpic 11 1 0 0
620 >;
621 };
622 };
623};
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
new file mode 100644
index 00000000000..69cae674f39
--- /dev/null
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -0,0 +1,214 @@
1/*
2 * P3041DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p3041si.dtsi"
36
37/ {
38 model = "fsl,P3041DS";
39 compatible = "fsl,P3041DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118100 {
79 eeprom@51 {
80 compatible = "at24,24c256";
81 reg = <0x51>;
82 };
83 eeprom@52 {
84 compatible = "at24,24c256";
85 reg = <0x52>;
86 };
87 };
88
89 i2c@119100 {
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 interrupts = <0x1 0x1 0 0>;
94 };
95 };
96 };
97
98 localbus@ffe124000 {
99 reg = <0xf 0xfe124000 0 0x1000>;
100 ranges = <0 0 0xf 0xe8000000 0x08000000
101 2 0 0xf 0xffa00000 0x00040000
102 3 0 0xf 0xffdf0000 0x00008000>;
103
104 flash@0,0 {
105 compatible = "cfi-flash";
106 reg = <0 0 0x08000000>;
107 bank-width = <2>;
108 device-width = <2>;
109 };
110
111 nand@2,0 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,elbc-fcm-nand";
115 reg = <0x2 0x0 0x40000>;
116
117 partition@0 {
118 label = "NAND U-Boot Image";
119 reg = <0x0 0x02000000>;
120 read-only;
121 };
122
123 partition@2000000 {
124 label = "NAND Root File System";
125 reg = <0x02000000 0x10000000>;
126 };
127
128 partition@12000000 {
129 label = "NAND Compressed RFS Image";
130 reg = <0x12000000 0x08000000>;
131 };
132
133 partition@1a000000 {
134 label = "NAND Linux Kernel Image";
135 reg = <0x1a000000 0x04000000>;
136 };
137
138 partition@1e000000 {
139 label = "NAND DTB Image";
140 reg = <0x1e000000 0x01000000>;
141 };
142
143 partition@1f000000 {
144 label = "NAND Writable User area";
145 reg = <0x1f000000 0x21000000>;
146 };
147 };
148
149 board-control@3,0 {
150 compatible = "fsl,p3041ds-pixis";
151 reg = <3 0 0x20>;
152 };
153 };
154
155 pci0: pcie@ffe200000 {
156 reg = <0xf 0xfe200000 0 0x1000>;
157 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
158 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
159 pcie@0 {
160 ranges = <0x02000000 0 0xe0000000
161 0x02000000 0 0xe0000000
162 0 0x20000000
163
164 0x01000000 0 0x00000000
165 0x01000000 0 0x00000000
166 0 0x00010000>;
167 };
168 };
169
170 pci1: pcie@ffe201000 {
171 reg = <0xf 0xfe201000 0 0x1000>;
172 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
173 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
174 pcie@0 {
175 ranges = <0x02000000 0 0xe0000000
176 0x02000000 0 0xe0000000
177 0 0x20000000
178
179 0x01000000 0 0x00000000
180 0x01000000 0 0x00000000
181 0 0x00010000>;
182 };
183 };
184
185 pci2: pcie@ffe202000 {
186 reg = <0xf 0xfe202000 0 0x1000>;
187 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
188 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
189 pcie@0 {
190 ranges = <0x02000000 0 0xe0000000
191 0x02000000 0 0xe0000000
192 0 0x20000000
193
194 0x01000000 0 0x00000000
195 0x01000000 0 0x00000000
196 0 0x00010000>;
197 };
198 };
199
200 pci3: pcie@ffe203000 {
201 reg = <0xf 0xfe203000 0 0x1000>;
202 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
203 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
204 pcie@0 {
205 ranges = <0x02000000 0 0xe0000000
206 0x02000000 0 0xe0000000
207 0 0x20000000
208
209 0x01000000 0 0x00000000
210 0x01000000 0 0x00000000
211 0 0x00010000>;
212 };
213 };
214};
diff --git a/arch/powerpc/boot/dts/p3041si.dtsi b/arch/powerpc/boot/dts/p3041si.dtsi
new file mode 100644
index 00000000000..8b695801f50
--- /dev/null
+++ b/arch/powerpc/boot/dts/p3041si.dtsi
@@ -0,0 +1,660 @@
1/*
2 * P3041 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P3041";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74/*
75 rio0 = &rapidio0;
76 */
77 };
78
79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 cpu0: PowerPC,e500mc@0 {
84 device_type = "cpu";
85 reg = <0>;
86 next-level-cache = <&L2_0>;
87 L2_0: l2-cache {
88 next-level-cache = <&cpc>;
89 };
90 };
91 cpu1: PowerPC,e500mc@1 {
92 device_type = "cpu";
93 reg = <1>;
94 next-level-cache = <&L2_1>;
95 L2_1: l2-cache {
96 next-level-cache = <&cpc>;
97 };
98 };
99 cpu2: PowerPC,e500mc@2 {
100 device_type = "cpu";
101 reg = <2>;
102 next-level-cache = <&L2_2>;
103 L2_2: l2-cache {
104 next-level-cache = <&cpc>;
105 };
106 };
107 cpu3: PowerPC,e500mc@3 {
108 device_type = "cpu";
109 reg = <3>;
110 next-level-cache = <&L2_3>;
111 L2_3: l2-cache {
112 next-level-cache = <&cpc>;
113 };
114 };
115 };
116
117 soc: soc@ffe000000 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 device_type = "soc";
121 compatible = "simple-bus";
122 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
123 reg = <0xf 0xfe000000 0 0x00001000>;
124
125 soc-sram-error {
126 compatible = "fsl,soc-sram-error";
127 interrupts = <16 2 1 29>;
128 };
129
130 corenet-law@0 {
131 compatible = "fsl,corenet-law";
132 reg = <0x0 0x1000>;
133 fsl,num-laws = <32>;
134 };
135
136 memory-controller@8000 {
137 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
138 reg = <0x8000 0x1000>;
139 interrupts = <16 2 1 23>;
140 };
141
142 cpc: l3-cache-controller@10000 {
143 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
144 reg = <0x10000 0x1000>;
145 interrupts = <16 2 1 27>;
146 };
147
148 corenet-cf@18000 {
149 compatible = "fsl,corenet-cf";
150 reg = <0x18000 0x1000>;
151 interrupts = <16 2 1 31>;
152 fsl,ccf-num-csdids = <32>;
153 fsl,ccf-num-snoopids = <32>;
154 };
155
156 iommu@20000 {
157 compatible = "fsl,pamu-v1.0", "fsl,pamu";
158 reg = <0x20000 0x4000>;
159 interrupts = <
160 24 2 0 0
161 16 2 1 30>;
162 };
163
164 mpic: pic@40000 {
165 clock-frequency = <0>;
166 interrupt-controller;
167 #address-cells = <0>;
168 #interrupt-cells = <4>;
169 reg = <0x40000 0x40000>;
170 compatible = "fsl,mpic", "chrp,open-pic";
171 device_type = "open-pic";
172 };
173
174 msi0: msi@41600 {
175 compatible = "fsl,mpic-msi";
176 reg = <0x41600 0x200>;
177 msi-available-ranges = <0 0x100>;
178 interrupts = <
179 0xe0 0 0 0
180 0xe1 0 0 0
181 0xe2 0 0 0
182 0xe3 0 0 0
183 0xe4 0 0 0
184 0xe5 0 0 0
185 0xe6 0 0 0
186 0xe7 0 0 0>;
187 };
188
189 msi1: msi@41800 {
190 compatible = "fsl,mpic-msi";
191 reg = <0x41800 0x200>;
192 msi-available-ranges = <0 0x100>;
193 interrupts = <
194 0xe8 0 0 0
195 0xe9 0 0 0
196 0xea 0 0 0
197 0xeb 0 0 0
198 0xec 0 0 0
199 0xed 0 0 0
200 0xee 0 0 0
201 0xef 0 0 0>;
202 };
203
204 msi2: msi@41a00 {
205 compatible = "fsl,mpic-msi";
206 reg = <0x41a00 0x200>;
207 msi-available-ranges = <0 0x100>;
208 interrupts = <
209 0xf0 0 0 0
210 0xf1 0 0 0
211 0xf2 0 0 0
212 0xf3 0 0 0
213 0xf4 0 0 0
214 0xf5 0 0 0
215 0xf6 0 0 0
216 0xf7 0 0 0>;
217 };
218
219 guts: global-utilities@e0000 {
220 compatible = "fsl,qoriq-device-config-1.0";
221 reg = <0xe0000 0xe00>;
222 fsl,has-rstcr;
223 #sleep-cells = <1>;
224 fsl,liodn-bits = <12>;
225 };
226
227 pins: global-utilities@e0e00 {
228 compatible = "fsl,qoriq-pin-control-1.0";
229 reg = <0xe0e00 0x200>;
230 #sleep-cells = <2>;
231 };
232
233 clockgen: global-utilities@e1000 {
234 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
235 reg = <0xe1000 0x1000>;
236 clock-frequency = <0>;
237 };
238
239 rcpm: global-utilities@e2000 {
240 compatible = "fsl,qoriq-rcpm-1.0";
241 reg = <0xe2000 0x1000>;
242 #sleep-cells = <1>;
243 };
244
245 sfp: sfp@e8000 {
246 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
247 reg = <0xe8000 0x1000>;
248 };
249
250 serdes: serdes@ea000 {
251 compatible = "fsl,p3041-serdes";
252 reg = <0xea000 0x1000>;
253 };
254
255 dma0: dma@100300 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
259 reg = <0x100300 0x4>;
260 ranges = <0x0 0x100100 0x200>;
261 cell-index = <0>;
262 dma-channel@0 {
263 compatible = "fsl,p3041-dma-channel",
264 "fsl,eloplus-dma-channel";
265 reg = <0x0 0x80>;
266 cell-index = <0>;
267 interrupts = <28 2 0 0>;
268 };
269 dma-channel@80 {
270 compatible = "fsl,p3041-dma-channel",
271 "fsl,eloplus-dma-channel";
272 reg = <0x80 0x80>;
273 cell-index = <1>;
274 interrupts = <29 2 0 0>;
275 };
276 dma-channel@100 {
277 compatible = "fsl,p3041-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x100 0x80>;
280 cell-index = <2>;
281 interrupts = <30 2 0 0>;
282 };
283 dma-channel@180 {
284 compatible = "fsl,p3041-dma-channel",
285 "fsl,eloplus-dma-channel";
286 reg = <0x180 0x80>;
287 cell-index = <3>;
288 interrupts = <31 2 0 0>;
289 };
290 };
291
292 dma1: dma@101300 {
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
296 reg = <0x101300 0x4>;
297 ranges = <0x0 0x101100 0x200>;
298 cell-index = <1>;
299 dma-channel@0 {
300 compatible = "fsl,p3041-dma-channel",
301 "fsl,eloplus-dma-channel";
302 reg = <0x0 0x80>;
303 cell-index = <0>;
304 interrupts = <32 2 0 0>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,p3041-dma-channel",
308 "fsl,eloplus-dma-channel";
309 reg = <0x80 0x80>;
310 cell-index = <1>;
311 interrupts = <33 2 0 0>;
312 };
313 dma-channel@100 {
314 compatible = "fsl,p3041-dma-channel",
315 "fsl,eloplus-dma-channel";
316 reg = <0x100 0x80>;
317 cell-index = <2>;
318 interrupts = <34 2 0 0>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,p3041-dma-channel",
322 "fsl,eloplus-dma-channel";
323 reg = <0x180 0x80>;
324 cell-index = <3>;
325 interrupts = <35 2 0 0>;
326 };
327 };
328
329 spi@110000 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
333 reg = <0x110000 0x1000>;
334 interrupts = <53 0x2 0 0>;
335 fsl,espi-num-chipselects = <4>;
336 };
337
338 sdhc: sdhc@114000 {
339 compatible = "fsl,p3041-esdhc", "fsl,esdhc";
340 reg = <0x114000 0x1000>;
341 interrupts = <48 2 0 0>;
342 sdhci,auto-cmd12;
343 clock-frequency = <0>;
344 };
345
346 i2c@118000 {
347 #address-cells = <1>;
348 #size-cells = <0>;
349 cell-index = <0>;
350 compatible = "fsl-i2c";
351 reg = <0x118000 0x100>;
352 interrupts = <38 2 0 0>;
353 dfsrr;
354 };
355
356 i2c@118100 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 cell-index = <1>;
360 compatible = "fsl-i2c";
361 reg = <0x118100 0x100>;
362 interrupts = <38 2 0 0>;
363 dfsrr;
364 };
365
366 i2c@119000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 cell-index = <2>;
370 compatible = "fsl-i2c";
371 reg = <0x119000 0x100>;
372 interrupts = <39 2 0 0>;
373 dfsrr;
374 };
375
376 i2c@119100 {
377 #address-cells = <1>;
378 #size-cells = <0>;
379 cell-index = <3>;
380 compatible = "fsl-i2c";
381 reg = <0x119100 0x100>;
382 interrupts = <39 2 0 0>;
383 dfsrr;
384 };
385
386 serial0: serial@11c500 {
387 cell-index = <0>;
388 device_type = "serial";
389 compatible = "ns16550";
390 reg = <0x11c500 0x100>;
391 clock-frequency = <0>;
392 interrupts = <36 2 0 0>;
393 };
394
395 serial1: serial@11c600 {
396 cell-index = <1>;
397 device_type = "serial";
398 compatible = "ns16550";
399 reg = <0x11c600 0x100>;
400 clock-frequency = <0>;
401 interrupts = <36 2 0 0>;
402 };
403
404 serial2: serial@11d500 {
405 cell-index = <2>;
406 device_type = "serial";
407 compatible = "ns16550";
408 reg = <0x11d500 0x100>;
409 clock-frequency = <0>;
410 interrupts = <37 2 0 0>;
411 };
412
413 serial3: serial@11d600 {
414 cell-index = <3>;
415 device_type = "serial";
416 compatible = "ns16550";
417 reg = <0x11d600 0x100>;
418 clock-frequency = <0>;
419 interrupts = <37 2 0 0>;
420 };
421
422 gpio0: gpio@130000 {
423 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
424 reg = <0x130000 0x1000>;
425 interrupts = <55 2 0 0>;
426 #gpio-cells = <2>;
427 gpio-controller;
428 };
429
430 usb0: usb@210000 {
431 compatible = "fsl,p3041-usb2-mph",
432 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
433 reg = <0x210000 0x1000>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 interrupts = <44 0x2 0 0>;
437 phy_type = "utmi";
438 port0;
439 };
440
441 usb1: usb@211000 {
442 compatible = "fsl,p3041-usb2-dr",
443 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
444 reg = <0x211000 0x1000>;
445 #address-cells = <1>;
446 #size-cells = <0>;
447 interrupts = <45 0x2 0 0>;
448 dr_mode = "host";
449 phy_type = "utmi";
450 };
451
452 sata@220000 {
453 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
454 reg = <0x220000 0x1000>;
455 interrupts = <68 0x2 0 0>;
456 };
457
458 sata@221000 {
459 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
460 reg = <0x221000 0x1000>;
461 interrupts = <69 0x2 0 0>;
462 };
463
464 crypto: crypto@300000 {
465 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
466 #address-cells = <1>;
467 #size-cells = <1>;
468 reg = <0x300000 0x10000>;
469 ranges = <0 0x300000 0x10000>;
470 interrupts = <92 2 0 0>;
471
472 sec_jr0: jr@1000 {
473 compatible = "fsl,sec-v4.2-job-ring",
474 "fsl,sec-v4.0-job-ring";
475 reg = <0x1000 0x1000>;
476 interrupts = <88 2 0 0>;
477 };
478
479 sec_jr1: jr@2000 {
480 compatible = "fsl,sec-v4.2-job-ring",
481 "fsl,sec-v4.0-job-ring";
482 reg = <0x2000 0x1000>;
483 interrupts = <89 2 0 0>;
484 };
485
486 sec_jr2: jr@3000 {
487 compatible = "fsl,sec-v4.2-job-ring",
488 "fsl,sec-v4.0-job-ring";
489 reg = <0x3000 0x1000>;
490 interrupts = <90 2 0 0>;
491 };
492
493 sec_jr3: jr@4000 {
494 compatible = "fsl,sec-v4.2-job-ring",
495 "fsl,sec-v4.0-job-ring";
496 reg = <0x4000 0x1000>;
497 interrupts = <91 2 0 0>;
498 };
499
500 rtic@6000 {
501 compatible = "fsl,sec-v4.2-rtic",
502 "fsl,sec-v4.0-rtic";
503 #address-cells = <1>;
504 #size-cells = <1>;
505 reg = <0x6000 0x100>;
506 ranges = <0x0 0x6100 0xe00>;
507
508 rtic_a: rtic-a@0 {
509 compatible = "fsl,sec-v4.2-rtic-memory",
510 "fsl,sec-v4.0-rtic-memory";
511 reg = <0x00 0x20 0x100 0x80>;
512 };
513
514 rtic_b: rtic-b@20 {
515 compatible = "fsl,sec-v4.2-rtic-memory",
516 "fsl,sec-v4.0-rtic-memory";
517 reg = <0x20 0x20 0x200 0x80>;
518 };
519
520 rtic_c: rtic-c@40 {
521 compatible = "fsl,sec-v4.2-rtic-memory",
522 "fsl,sec-v4.0-rtic-memory";
523 reg = <0x40 0x20 0x300 0x80>;
524 };
525
526 rtic_d: rtic-d@60 {
527 compatible = "fsl,sec-v4.2-rtic-memory",
528 "fsl,sec-v4.0-rtic-memory";
529 reg = <0x60 0x20 0x500 0x80>;
530 };
531 };
532 };
533
534 sec_mon: sec_mon@314000 {
535 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
536 reg = <0x314000 0x1000>;
537 interrupts = <93 2 0 0>;
538 };
539 };
540
541/*
542 rapidio0: rapidio@ffe0c0000
543*/
544
545 localbus@ffe124000 {
546 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
547 interrupts = <25 2 0 0>;
548 #address-cells = <2>;
549 #size-cells = <1>;
550 };
551
552 pci0: pcie@ffe200000 {
553 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
554 device_type = "pci";
555 #size-cells = <2>;
556 #address-cells = <3>;
557 bus-range = <0x0 0xff>;
558 clock-frequency = <0x1fca055>;
559 fsl,msi = <&msi0>;
560 interrupts = <16 2 1 15>;
561
562 pcie@0 {
563 reg = <0 0 0 0 0>;
564 #interrupt-cells = <1>;
565 #size-cells = <2>;
566 #address-cells = <3>;
567 device_type = "pci";
568 interrupts = <16 2 1 15>;
569 interrupt-map-mask = <0xf800 0 0 7>;
570 interrupt-map = <
571 /* IDSEL 0x0 */
572 0000 0 0 1 &mpic 40 1 0 0
573 0000 0 0 2 &mpic 1 1 0 0
574 0000 0 0 3 &mpic 2 1 0 0
575 0000 0 0 4 &mpic 3 1 0 0
576 >;
577 };
578 };
579
580 pci1: pcie@ffe201000 {
581 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
582 device_type = "pci";
583 #size-cells = <2>;
584 #address-cells = <3>;
585 bus-range = <0 0xff>;
586 clock-frequency = <0x1fca055>;
587 fsl,msi = <&msi1>;
588 interrupts = <16 2 1 14>;
589 pcie@0 {
590 reg = <0 0 0 0 0>;
591 #interrupt-cells = <1>;
592 #size-cells = <2>;
593 #address-cells = <3>;
594 device_type = "pci";
595 interrupts = <16 2 1 14>;
596 interrupt-map-mask = <0xf800 0 0 7>;
597 interrupt-map = <
598 /* IDSEL 0x0 */
599 0000 0 0 1 &mpic 41 1 0 0
600 0000 0 0 2 &mpic 5 1 0 0
601 0000 0 0 3 &mpic 6 1 0 0
602 0000 0 0 4 &mpic 7 1 0 0
603 >;
604 };
605 };
606
607 pci2: pcie@ffe202000 {
608 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
609 device_type = "pci";
610 #size-cells = <2>;
611 #address-cells = <3>;
612 bus-range = <0x0 0xff>;
613 clock-frequency = <0x1fca055>;
614 fsl,msi = <&msi2>;
615 interrupts = <16 2 1 13>;
616 pcie@0 {
617 reg = <0 0 0 0 0>;
618 #interrupt-cells = <1>;
619 #size-cells = <2>;
620 #address-cells = <3>;
621 device_type = "pci";
622 interrupts = <16 2 1 13>;
623 interrupt-map-mask = <0xf800 0 0 7>;
624 interrupt-map = <
625 /* IDSEL 0x0 */
626 0000 0 0 1 &mpic 42 1 0 0
627 0000 0 0 2 &mpic 9 1 0 0
628 0000 0 0 3 &mpic 10 1 0 0
629 0000 0 0 4 &mpic 11 1 0 0
630 >;
631 };
632 };
633
634 pci3: pcie@ffe203000 {
635 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
636 device_type = "pci";
637 #size-cells = <2>;
638 #address-cells = <3>;
639 bus-range = <0x0 0xff>;
640 clock-frequency = <0x1fca055>;
641 fsl,msi = <&msi2>;
642 interrupts = <16 2 1 12>;
643 pcie@0 {
644 reg = <0 0 0 0 0>;
645 #interrupt-cells = <1>;
646 #size-cells = <2>;
647 #address-cells = <3>;
648 device_type = "pci";
649 interrupts = <16 2 1 12>;
650 interrupt-map-mask = <0xf800 0 0 7>;
651 interrupt-map = <
652 /* IDSEL 0x0 */
653 0000 0 0 1 &mpic 43 1 0 0
654 0000 0 0 2 &mpic 0 1 0 0
655 0000 0 0 3 &mpic 4 1 0 0
656 0000 0 0 4 &mpic 8 1 0 0
657 >;
658 };
659 };
660};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 927f94d16e9..eb11098bb68 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -3,258 +3,50 @@
3 * 3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * Redistribution and use in source and binary forms, with or without
7 * under the terms of the GNU General Public License as published by the 7 * modification, are permitted provided that the following conditions are met:
8 * Free Software Foundation; either version 2 of the License, or (at your 8 * * Redistributions of source code must retain the above copyright
9 * option) any later version. 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10 */ 33 */
11 34
12/dts-v1/; 35/include/ "p4080si.dtsi"
13 36
14/ { 37/ {
15 model = "fsl,P4080DS"; 38 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS"; 39 compatible = "fsl,P4080DS";
17 #address-cells = <2>; 40 #address-cells = <2>;
18 #size-cells = <2>; 41 #size-cells = <2>;
19 42 interrupt-parent = <&mpic>;
20 aliases {
21 ccsr = &soc;
22
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 pci2 = &pci2;
30 usb0 = &usb0;
31 usb1 = &usb1;
32 dma0 = &dma0;
33 dma1 = &dma1;
34 sdhc = &sdhc;
35
36 crypto = &crypto;
37 sec_jr0 = &sec_jr0;
38 sec_jr1 = &sec_jr1;
39 sec_jr2 = &sec_jr2;
40 sec_jr3 = &sec_jr3;
41 rtic_a = &rtic_a;
42 rtic_b = &rtic_b;
43 rtic_c = &rtic_c;
44 rtic_d = &rtic_d;
45 sec_mon = &sec_mon;
46
47 rio0 = &rapidio0;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: PowerPC,4080@0 {
55 device_type = "cpu";
56 reg = <0>;
57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache {
59 };
60 };
61 cpu1: PowerPC,4080@1 {
62 device_type = "cpu";
63 reg = <1>;
64 next-level-cache = <&L2_1>;
65 L2_1: l2-cache {
66 };
67 };
68 cpu2: PowerPC,4080@2 {
69 device_type = "cpu";
70 reg = <2>;
71 next-level-cache = <&L2_2>;
72 L2_2: l2-cache {
73 };
74 };
75 cpu3: PowerPC,4080@3 {
76 device_type = "cpu";
77 reg = <3>;
78 next-level-cache = <&L2_3>;
79 L2_3: l2-cache {
80 };
81 };
82 cpu4: PowerPC,4080@4 {
83 device_type = "cpu";
84 reg = <4>;
85 next-level-cache = <&L2_4>;
86 L2_4: l2-cache {
87 };
88 };
89 cpu5: PowerPC,4080@5 {
90 device_type = "cpu";
91 reg = <5>;
92 next-level-cache = <&L2_5>;
93 L2_5: l2-cache {
94 };
95 };
96 cpu6: PowerPC,4080@6 {
97 device_type = "cpu";
98 reg = <6>;
99 next-level-cache = <&L2_6>;
100 L2_6: l2-cache {
101 };
102 };
103 cpu7: PowerPC,4080@7 {
104 device_type = "cpu";
105 reg = <7>;
106 next-level-cache = <&L2_7>;
107 L2_7: l2-cache {
108 };
109 };
110 };
111 43
112 memory { 44 memory {
113 device_type = "memory"; 45 device_type = "memory";
114 }; 46 };
115 47
116 soc: soc@ffe000000 { 48 soc: soc@ffe000000 {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 device_type = "soc";
120 compatible = "simple-bus";
121 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
122 reg = <0xf 0xfe000000 0 0x00001000>;
123
124 corenet-law@0 {
125 compatible = "fsl,corenet-law";
126 reg = <0x0 0x1000>;
127 fsl,num-laws = <32>;
128 };
129
130 memory-controller@8000 {
131 compatible = "fsl,p4080-memory-controller";
132 reg = <0x8000 0x1000>;
133 interrupt-parent = <&mpic>;
134 interrupts = <0x12 2>;
135 };
136
137 memory-controller@9000 {
138 compatible = "fsl,p4080-memory-controller";
139 reg = <0x9000 0x1000>;
140 interrupt-parent = <&mpic>;
141 interrupts = <0x12 2>;
142 };
143
144 corenet-cf@18000 {
145 compatible = "fsl,corenet-cf";
146 reg = <0x18000 0x1000>;
147 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>;
149 };
150
151 iommu@20000 {
152 compatible = "fsl,p4080-pamu";
153 reg = <0x20000 0x10000>;
154 interrupts = <24 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 mpic: pic@40000 {
159 interrupt-controller;
160 #address-cells = <0>;
161 #interrupt-cells = <2>;
162 reg = <0x40000 0x40000>;
163 compatible = "chrp,open-pic";
164 device_type = "open-pic";
165 };
166
167 dma0: dma@100300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
171 reg = <0x100300 0x4>;
172 ranges = <0x0 0x100100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,p4080-dma-channel",
176 "fsl,eloplus-dma-channel";
177 reg = <0x0 0x80>;
178 cell-index = <0>;
179 interrupt-parent = <&mpic>;
180 interrupts = <28 2>;
181 };
182 dma-channel@80 {
183 compatible = "fsl,p4080-dma-channel",
184 "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>;
186 cell-index = <1>;
187 interrupt-parent = <&mpic>;
188 interrupts = <29 2>;
189 };
190 dma-channel@100 {
191 compatible = "fsl,p4080-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x100 0x80>;
194 cell-index = <2>;
195 interrupt-parent = <&mpic>;
196 interrupts = <30 2>;
197 };
198 dma-channel@180 {
199 compatible = "fsl,p4080-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x180 0x80>;
202 cell-index = <3>;
203 interrupt-parent = <&mpic>;
204 interrupts = <31 2>;
205 };
206 };
207
208 dma1: dma@101300 {
209 #address-cells = <1>;
210 #size-cells = <1>;
211 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
212 reg = <0x101300 0x4>;
213 ranges = <0x0 0x101100 0x200>;
214 cell-index = <1>;
215 dma-channel@0 {
216 compatible = "fsl,p4080-dma-channel",
217 "fsl,eloplus-dma-channel";
218 reg = <0x0 0x80>;
219 cell-index = <0>;
220 interrupt-parent = <&mpic>;
221 interrupts = <32 2>;
222 };
223 dma-channel@80 {
224 compatible = "fsl,p4080-dma-channel",
225 "fsl,eloplus-dma-channel";
226 reg = <0x80 0x80>;
227 cell-index = <1>;
228 interrupt-parent = <&mpic>;
229 interrupts = <33 2>;
230 };
231 dma-channel@100 {
232 compatible = "fsl,p4080-dma-channel",
233 "fsl,eloplus-dma-channel";
234 reg = <0x100 0x80>;
235 cell-index = <2>;
236 interrupt-parent = <&mpic>;
237 interrupts = <34 2>;
238 };
239 dma-channel@180 {
240 compatible = "fsl,p4080-dma-channel",
241 "fsl,eloplus-dma-channel";
242 reg = <0x180 0x80>;
243 cell-index = <3>;
244 interrupt-parent = <&mpic>;
245 interrupts = <35 2>;
246 };
247 };
248
249 spi@110000 { 49 spi@110000 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
253 reg = <0x110000 0x1000>;
254 interrupts = <53 0x2>;
255 interrupt-parent = <&mpic>;
256 fsl,espi-num-chipselects = <4>;
257
258 flash@0 { 50 flash@0 {
259 #address-cells = <1>; 51 #address-cells = <1>;
260 #size-cells = <1>; 52 #size-cells = <1>;
@@ -283,35 +75,7 @@
283 }; 75 };
284 }; 76 };
285 77
286 sdhc: sdhc@114000 {
287 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
288 reg = <0x114000 0x1000>;
289 interrupts = <48 2>;
290 interrupt-parent = <&mpic>;
291 voltage-ranges = <3300 3300>;
292 sdhci,auto-cmd12;
293 };
294
295 i2c@118000 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 cell-index = <0>;
299 compatible = "fsl-i2c";
300 reg = <0x118000 0x100>;
301 interrupts = <38 2>;
302 interrupt-parent = <&mpic>;
303 dfsrr;
304 };
305
306 i2c@118100 { 78 i2c@118100 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 cell-index = <1>;
310 compatible = "fsl-i2c";
311 reg = <0x118100 0x100>;
312 interrupts = <38 2>;
313 interrupt-parent = <&mpic>;
314 dfsrr;
315 eeprom@51 { 79 eeprom@51 {
316 compatible = "at24,24c256"; 80 compatible = "at24,24c256";
317 reg = <0x51>; 81 reg = <0x51>;
@@ -323,198 +87,27 @@
323 rtc@68 { 87 rtc@68 {
324 compatible = "dallas,ds3232"; 88 compatible = "dallas,ds3232";
325 reg = <0x68>; 89 reg = <0x68>;
326 interrupts = <0 0x1>; 90 interrupts = <0x1 0x1 0 0>;
327 interrupt-parent = <&mpic>;
328 }; 91 };
329 }; 92 };
330 93
331 i2c@119000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 cell-index = <2>;
335 compatible = "fsl-i2c";
336 reg = <0x119000 0x100>;
337 interrupts = <39 2>;
338 interrupt-parent = <&mpic>;
339 dfsrr;
340 };
341
342 i2c@119100 {
343 #address-cells = <1>;
344 #size-cells = <0>;
345 cell-index = <3>;
346 compatible = "fsl-i2c";
347 reg = <0x119100 0x100>;
348 interrupts = <39 2>;
349 interrupt-parent = <&mpic>;
350 dfsrr;
351 };
352
353 serial0: serial@11c500 {
354 cell-index = <0>;
355 device_type = "serial";
356 compatible = "ns16550";
357 reg = <0x11c500 0x100>;
358 clock-frequency = <0>;
359 interrupts = <36 2>;
360 interrupt-parent = <&mpic>;
361 };
362
363 serial1: serial@11c600 {
364 cell-index = <1>;
365 device_type = "serial";
366 compatible = "ns16550";
367 reg = <0x11c600 0x100>;
368 clock-frequency = <0>;
369 interrupts = <36 2>;
370 interrupt-parent = <&mpic>;
371 };
372
373 serial2: serial@11d500 {
374 cell-index = <2>;
375 device_type = "serial";
376 compatible = "ns16550";
377 reg = <0x11d500 0x100>;
378 clock-frequency = <0>;
379 interrupts = <37 2>;
380 interrupt-parent = <&mpic>;
381 };
382
383 serial3: serial@11d600 {
384 cell-index = <3>;
385 device_type = "serial";
386 compatible = "ns16550";
387 reg = <0x11d600 0x100>;
388 clock-frequency = <0>;
389 interrupts = <37 2>;
390 interrupt-parent = <&mpic>;
391 };
392
393 gpio0: gpio@130000 {
394 compatible = "fsl,p4080-gpio";
395 reg = <0x130000 0x1000>;
396 interrupts = <55 2>;
397 interrupt-parent = <&mpic>;
398 #gpio-cells = <2>;
399 gpio-controller;
400 };
401
402 usb0: usb@210000 { 94 usb0: usb@210000 {
403 compatible = "fsl,p4080-usb2-mph",
404 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
405 reg = <0x210000 0x1000>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 interrupt-parent = <&mpic>;
409 interrupts = <44 0x2>;
410 phy_type = "ulpi"; 95 phy_type = "ulpi";
411 }; 96 };
412 97
413 usb1: usb@211000 { 98 usb1: usb@211000 {
414 compatible = "fsl,p4080-usb2-dr",
415 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
416 reg = <0x211000 0x1000>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 interrupt-parent = <&mpic>;
420 interrupts = <45 0x2>;
421 dr_mode = "host"; 99 dr_mode = "host";
422 phy_type = "ulpi"; 100 phy_type = "ulpi";
423 }; 101 };
424
425 crypto: crypto@300000 {
426 compatible = "fsl,sec-v4.0";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 reg = <0x300000 0x10000>;
430 ranges = <0 0x300000 0x10000>;
431 interrupt-parent = <&mpic>;
432 interrupts = <92 2>;
433
434 sec_jr0: jr@1000 {
435 compatible = "fsl,sec-v4.0-job-ring";
436 reg = <0x1000 0x1000>;
437 interrupt-parent = <&mpic>;
438 interrupts = <88 2>;
439 };
440
441 sec_jr1: jr@2000 {
442 compatible = "fsl,sec-v4.0-job-ring";
443 reg = <0x2000 0x1000>;
444 interrupt-parent = <&mpic>;
445 interrupts = <89 2>;
446 };
447
448 sec_jr2: jr@3000 {
449 compatible = "fsl,sec-v4.0-job-ring";
450 reg = <0x3000 0x1000>;
451 interrupt-parent = <&mpic>;
452 interrupts = <90 2>;
453 };
454
455 sec_jr3: jr@4000 {
456 compatible = "fsl,sec-v4.0-job-ring";
457 reg = <0x4000 0x1000>;
458 interrupt-parent = <&mpic>;
459 interrupts = <91 2>;
460 };
461
462 rtic@6000 {
463 compatible = "fsl,sec-v4.0-rtic";
464 #address-cells = <1>;
465 #size-cells = <1>;
466 reg = <0x6000 0x100>;
467 ranges = <0x0 0x6100 0xe00>;
468
469 rtic_a: rtic-a@0 {
470 compatible = "fsl,sec-v4.0-rtic-memory";
471 reg = <0x00 0x20 0x100 0x80>;
472 };
473
474 rtic_b: rtic-b@20 {
475 compatible = "fsl,sec-v4.0-rtic-memory";
476 reg = <0x20 0x20 0x200 0x80>;
477 };
478
479 rtic_c: rtic-c@40 {
480 compatible = "fsl,sec-v4.0-rtic-memory";
481 reg = <0x40 0x20 0x300 0x80>;
482 };
483
484 rtic_d: rtic-d@60 {
485 compatible = "fsl,sec-v4.0-rtic-memory";
486 reg = <0x60 0x20 0x500 0x80>;
487 };
488 };
489 };
490
491 sec_mon: sec_mon@314000 {
492 compatible = "fsl,sec-v4.0-mon";
493 reg = <0x314000 0x1000>;
494 interrupt-parent = <&mpic>;
495 interrupts = <93 2>;
496 };
497 }; 102 };
498 103
499 rapidio0: rapidio@ffe0c0000 { 104 rapidio0: rapidio@ffe0c0000 {
500 #address-cells = <2>;
501 #size-cells = <2>;
502 compatible = "fsl,rapidio-delta";
503 reg = <0xf 0xfe0c0000 0 0x20000>; 105 reg = <0xf 0xfe0c0000 0 0x20000>;
504 ranges = <0 0 0xf 0xf5000000 0 0x01000000>; 106 ranges = <0 0 0xc 0x20000000 0 0x01000000>;
505 interrupt-parent = <&mpic>;
506 /* err_irq bell_outb_irq bell_inb_irq
507 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
508 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
509 }; 107 };
510 108
511 localbus@ffe124000 { 109 localbus@ffe124000 {
512 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
513 reg = <0xf 0xfe124000 0 0x1000>; 110 reg = <0xf 0xfe124000 0 0x1000>;
514 interrupts = <25 2>;
515 #address-cells = <2>;
516 #size-cells = <1>;
517
518 ranges = <0 0 0xf 0xe8000000 0x08000000>; 111 ranges = <0 0 0xf 0xe8000000 0x08000000>;
519 112
520 flash@0,0 { 113 flash@0,0 {
@@ -526,32 +119,10 @@
526 }; 119 };
527 120
528 pci0: pcie@ffe200000 { 121 pci0: pcie@ffe200000 {
529 compatible = "fsl,p4080-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xfe200000 0 0x1000>; 122 reg = <0xf 0xfe200000 0 0x1000>;
535 bus-range = <0x0 0xff>;
536 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 123 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
537 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 124 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
538 clock-frequency = <0x1fca055>;
539 interrupt-parent = <&mpic>;
540 interrupts = <16 2>;
541
542 interrupt-map-mask = <0xf800 0 0 7>;
543 interrupt-map = <
544 /* IDSEL 0x0 */
545 0000 0 0 1 &mpic 40 1
546 0000 0 0 2 &mpic 1 1
547 0000 0 0 3 &mpic 2 1
548 0000 0 0 4 &mpic 3 1
549 >;
550 pcie@0 { 125 pcie@0 {
551 reg = <0 0 0 0 0>;
552 #size-cells = <2>;
553 #address-cells = <3>;
554 device_type = "pci";
555 ranges = <0x02000000 0 0xe0000000 126 ranges = <0x02000000 0 0xe0000000
556 0x02000000 0 0xe0000000 127 0x02000000 0 0xe0000000
557 0 0x20000000 128 0 0x20000000
@@ -563,31 +134,10 @@
563 }; 134 };
564 135
565 pci1: pcie@ffe201000 { 136 pci1: pcie@ffe201000 {
566 compatible = "fsl,p4080-pcie";
567 device_type = "pci";
568 #interrupt-cells = <1>;
569 #size-cells = <2>;
570 #address-cells = <3>;
571 reg = <0xf 0xfe201000 0 0x1000>; 137 reg = <0xf 0xfe201000 0 0x1000>;
572 bus-range = <0 0xff>;
573 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 138 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
574 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 139 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
575 clock-frequency = <0x1fca055>;
576 interrupt-parent = <&mpic>;
577 interrupts = <16 2>;
578 interrupt-map-mask = <0xf800 0 0 7>;
579 interrupt-map = <
580 /* IDSEL 0x0 */
581 0000 0 0 1 &mpic 41 1
582 0000 0 0 2 &mpic 5 1
583 0000 0 0 3 &mpic 6 1
584 0000 0 0 4 &mpic 7 1
585 >;
586 pcie@0 { 140 pcie@0 {
587 reg = <0 0 0 0 0>;
588 #size-cells = <2>;
589 #address-cells = <3>;
590 device_type = "pci";
591 ranges = <0x02000000 0 0xe0000000 141 ranges = <0x02000000 0 0xe0000000
592 0x02000000 0 0xe0000000 142 0x02000000 0 0xe0000000
593 0 0x20000000 143 0 0x20000000
@@ -599,31 +149,10 @@
599 }; 149 };
600 150
601 pci2: pcie@ffe202000 { 151 pci2: pcie@ffe202000 {
602 compatible = "fsl,p4080-pcie";
603 device_type = "pci";
604 #interrupt-cells = <1>;
605 #size-cells = <2>;
606 #address-cells = <3>;
607 reg = <0xf 0xfe202000 0 0x1000>; 152 reg = <0xf 0xfe202000 0 0x1000>;
608 bus-range = <0x0 0xff>;
609 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 153 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
610 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 154 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
611 clock-frequency = <0x1fca055>;
612 interrupt-parent = <&mpic>;
613 interrupts = <16 2>;
614 interrupt-map-mask = <0xf800 0 0 7>;
615 interrupt-map = <
616 /* IDSEL 0x0 */
617 0000 0 0 1 &mpic 42 1
618 0000 0 0 2 &mpic 9 1
619 0000 0 0 3 &mpic 10 1
620 0000 0 0 4 &mpic 11 1
621 >;
622 pcie@0 { 155 pcie@0 {
623 reg = <0 0 0 0 0>;
624 #size-cells = <2>;
625 #address-cells = <3>;
626 device_type = "pci";
627 ranges = <0x02000000 0 0xe0000000 156 ranges = <0x02000000 0 0xe0000000
628 0x02000000 0 0xe0000000 157 0x02000000 0 0xe0000000
629 0 0x20000000 158 0 0x20000000
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
new file mode 100644
index 00000000000..b71051f506c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p4080si.dtsi
@@ -0,0 +1,661 @@
1/*
2 * P4080 Silicon Device Tree Source
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P4080";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72
73 rio0 = &rapidio0;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: PowerPC,4080@0 {
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2_0>;
84 L2_0: l2-cache {
85 next-level-cache = <&cpc>;
86 };
87 };
88 cpu1: PowerPC,4080@1 {
89 device_type = "cpu";
90 reg = <1>;
91 next-level-cache = <&L2_1>;
92 L2_1: l2-cache {
93 next-level-cache = <&cpc>;
94 };
95 };
96 cpu2: PowerPC,4080@2 {
97 device_type = "cpu";
98 reg = <2>;
99 next-level-cache = <&L2_2>;
100 L2_2: l2-cache {
101 next-level-cache = <&cpc>;
102 };
103 };
104 cpu3: PowerPC,4080@3 {
105 device_type = "cpu";
106 reg = <3>;
107 next-level-cache = <&L2_3>;
108 L2_3: l2-cache {
109 next-level-cache = <&cpc>;
110 };
111 };
112 cpu4: PowerPC,4080@4 {
113 device_type = "cpu";
114 reg = <4>;
115 next-level-cache = <&L2_4>;
116 L2_4: l2-cache {
117 next-level-cache = <&cpc>;
118 };
119 };
120 cpu5: PowerPC,4080@5 {
121 device_type = "cpu";
122 reg = <5>;
123 next-level-cache = <&L2_5>;
124 L2_5: l2-cache {
125 next-level-cache = <&cpc>;
126 };
127 };
128 cpu6: PowerPC,4080@6 {
129 device_type = "cpu";
130 reg = <6>;
131 next-level-cache = <&L2_6>;
132 L2_6: l2-cache {
133 next-level-cache = <&cpc>;
134 };
135 };
136 cpu7: PowerPC,4080@7 {
137 device_type = "cpu";
138 reg = <7>;
139 next-level-cache = <&L2_7>;
140 L2_7: l2-cache {
141 next-level-cache = <&cpc>;
142 };
143 };
144 };
145
146 soc: soc@ffe000000 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 device_type = "soc";
150 compatible = "simple-bus";
151 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
152 reg = <0xf 0xfe000000 0 0x00001000>;
153
154 soc-sram-error {
155 compatible = "fsl,soc-sram-error";
156 interrupts = <16 2 1 29>;
157 };
158
159 corenet-law@0 {
160 compatible = "fsl,corenet-law";
161 reg = <0x0 0x1000>;
162 fsl,num-laws = <32>;
163 };
164
165 memory-controller@8000 {
166 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
167 reg = <0x8000 0x1000>;
168 interrupts = <16 2 1 23>;
169 };
170
171 memory-controller@9000 {
172 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
173 reg = <0x9000 0x1000>;
174 interrupts = <16 2 1 22>;
175 };
176
177 cpc: l3-cache-controller@10000 {
178 compatible = "fsl,p4080-l3-cache-controller", "cache";
179 reg = <0x10000 0x1000
180 0x11000 0x1000>;
181 interrupts = <16 2 1 27
182 16 2 1 26>;
183 };
184
185 corenet-cf@18000 {
186 compatible = "fsl,corenet-cf";
187 reg = <0x18000 0x1000>;
188 interrupts = <16 2 1 31>;
189 fsl,ccf-num-csdids = <32>;
190 fsl,ccf-num-snoopids = <32>;
191 };
192
193 iommu@20000 {
194 compatible = "fsl,pamu-v1.0", "fsl,pamu";
195 reg = <0x20000 0x5000>;
196 interrupts = <
197 24 2 0 0
198 16 2 1 30>;
199 };
200
201 mpic: pic@40000 {
202 clock-frequency = <0>;
203 interrupt-controller;
204 #address-cells = <0>;
205 #interrupt-cells = <4>;
206 reg = <0x40000 0x40000>;
207 compatible = "fsl,mpic", "chrp,open-pic";
208 device_type = "open-pic";
209 };
210
211 msi0: msi@41600 {
212 compatible = "fsl,mpic-msi";
213 reg = <0x41600 0x200>;
214 msi-available-ranges = <0 0x100>;
215 interrupts = <
216 0xe0 0 0 0
217 0xe1 0 0 0
218 0xe2 0 0 0
219 0xe3 0 0 0
220 0xe4 0 0 0
221 0xe5 0 0 0
222 0xe6 0 0 0
223 0xe7 0 0 0>;
224 };
225
226 msi1: msi@41800 {
227 compatible = "fsl,mpic-msi";
228 reg = <0x41800 0x200>;
229 msi-available-ranges = <0 0x100>;
230 interrupts = <
231 0xe8 0 0 0
232 0xe9 0 0 0
233 0xea 0 0 0
234 0xeb 0 0 0
235 0xec 0 0 0
236 0xed 0 0 0
237 0xee 0 0 0
238 0xef 0 0 0>;
239 };
240
241 msi2: msi@41a00 {
242 compatible = "fsl,mpic-msi";
243 reg = <0x41a00 0x200>;
244 msi-available-ranges = <0 0x100>;
245 interrupts = <
246 0xf0 0 0 0
247 0xf1 0 0 0
248 0xf2 0 0 0
249 0xf3 0 0 0
250 0xf4 0 0 0
251 0xf5 0 0 0
252 0xf6 0 0 0
253 0xf7 0 0 0>;
254 };
255
256 guts: global-utilities@e0000 {
257 compatible = "fsl,qoriq-device-config-1.0";
258 reg = <0xe0000 0xe00>;
259 fsl,has-rstcr;
260 #sleep-cells = <1>;
261 fsl,liodn-bits = <12>;
262 };
263
264 pins: global-utilities@e0e00 {
265 compatible = "fsl,qoriq-pin-control-1.0";
266 reg = <0xe0e00 0x200>;
267 #sleep-cells = <2>;
268 };
269
270 clockgen: global-utilities@e1000 {
271 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
272 reg = <0xe1000 0x1000>;
273 clock-frequency = <0>;
274 };
275
276 rcpm: global-utilities@e2000 {
277 compatible = "fsl,qoriq-rcpm-1.0";
278 reg = <0xe2000 0x1000>;
279 #sleep-cells = <1>;
280 };
281
282 sfp: sfp@e8000 {
283 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
284 reg = <0xe8000 0x1000>;
285 };
286
287 serdes: serdes@ea000 {
288 compatible = "fsl,p4080-serdes";
289 reg = <0xea000 0x1000>;
290 };
291
292 dma0: dma@100300 {
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
296 reg = <0x100300 0x4>;
297 ranges = <0x0 0x100100 0x200>;
298 cell-index = <0>;
299 dma-channel@0 {
300 compatible = "fsl,p4080-dma-channel",
301 "fsl,eloplus-dma-channel";
302 reg = <0x0 0x80>;
303 cell-index = <0>;
304 interrupts = <28 2 0 0>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,p4080-dma-channel",
308 "fsl,eloplus-dma-channel";
309 reg = <0x80 0x80>;
310 cell-index = <1>;
311 interrupts = <29 2 0 0>;
312 };
313 dma-channel@100 {
314 compatible = "fsl,p4080-dma-channel",
315 "fsl,eloplus-dma-channel";
316 reg = <0x100 0x80>;
317 cell-index = <2>;
318 interrupts = <30 2 0 0>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,p4080-dma-channel",
322 "fsl,eloplus-dma-channel";
323 reg = <0x180 0x80>;
324 cell-index = <3>;
325 interrupts = <31 2 0 0>;
326 };
327 };
328
329 dma1: dma@101300 {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
333 reg = <0x101300 0x4>;
334 ranges = <0x0 0x101100 0x200>;
335 cell-index = <1>;
336 dma-channel@0 {
337 compatible = "fsl,p4080-dma-channel",
338 "fsl,eloplus-dma-channel";
339 reg = <0x0 0x80>;
340 cell-index = <0>;
341 interrupts = <32 2 0 0>;
342 };
343 dma-channel@80 {
344 compatible = "fsl,p4080-dma-channel",
345 "fsl,eloplus-dma-channel";
346 reg = <0x80 0x80>;
347 cell-index = <1>;
348 interrupts = <33 2 0 0>;
349 };
350 dma-channel@100 {
351 compatible = "fsl,p4080-dma-channel",
352 "fsl,eloplus-dma-channel";
353 reg = <0x100 0x80>;
354 cell-index = <2>;
355 interrupts = <34 2 0 0>;
356 };
357 dma-channel@180 {
358 compatible = "fsl,p4080-dma-channel",
359 "fsl,eloplus-dma-channel";
360 reg = <0x180 0x80>;
361 cell-index = <3>;
362 interrupts = <35 2 0 0>;
363 };
364 };
365
366 spi@110000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
370 reg = <0x110000 0x1000>;
371 interrupts = <53 0x2 0 0>;
372 fsl,espi-num-chipselects = <4>;
373 };
374
375 sdhc: sdhc@114000 {
376 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
377 reg = <0x114000 0x1000>;
378 interrupts = <48 2 0 0>;
379 voltage-ranges = <3300 3300>;
380 sdhci,auto-cmd12;
381 clock-frequency = <0>;
382 };
383
384 i2c@118000 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 cell-index = <0>;
388 compatible = "fsl-i2c";
389 reg = <0x118000 0x100>;
390 interrupts = <38 2 0 0>;
391 dfsrr;
392 };
393
394 i2c@118100 {
395 #address-cells = <1>;
396 #size-cells = <0>;
397 cell-index = <1>;
398 compatible = "fsl-i2c";
399 reg = <0x118100 0x100>;
400 interrupts = <38 2 0 0>;
401 dfsrr;
402 };
403
404 i2c@119000 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 cell-index = <2>;
408 compatible = "fsl-i2c";
409 reg = <0x119000 0x100>;
410 interrupts = <39 2 0 0>;
411 dfsrr;
412 };
413
414 i2c@119100 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 cell-index = <3>;
418 compatible = "fsl-i2c";
419 reg = <0x119100 0x100>;
420 interrupts = <39 2 0 0>;
421 dfsrr;
422 };
423
424 serial0: serial@11c500 {
425 cell-index = <0>;
426 device_type = "serial";
427 compatible = "ns16550";
428 reg = <0x11c500 0x100>;
429 clock-frequency = <0>;
430 interrupts = <36 2 0 0>;
431 };
432
433 serial1: serial@11c600 {
434 cell-index = <1>;
435 device_type = "serial";
436 compatible = "ns16550";
437 reg = <0x11c600 0x100>;
438 clock-frequency = <0>;
439 interrupts = <36 2 0 0>;
440 };
441
442 serial2: serial@11d500 {
443 cell-index = <2>;
444 device_type = "serial";
445 compatible = "ns16550";
446 reg = <0x11d500 0x100>;
447 clock-frequency = <0>;
448 interrupts = <37 2 0 0>;
449 };
450
451 serial3: serial@11d600 {
452 cell-index = <3>;
453 device_type = "serial";
454 compatible = "ns16550";
455 reg = <0x11d600 0x100>;
456 clock-frequency = <0>;
457 interrupts = <37 2 0 0>;
458 };
459
460 gpio0: gpio@130000 {
461 compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
462 reg = <0x130000 0x1000>;
463 interrupts = <55 2 0 0>;
464 #gpio-cells = <2>;
465 gpio-controller;
466 };
467
468 usb0: usb@210000 {
469 compatible = "fsl,p4080-usb2-mph",
470 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
471 reg = <0x210000 0x1000>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 interrupts = <44 0x2 0 0>;
475 };
476
477 usb1: usb@211000 {
478 compatible = "fsl,p4080-usb2-dr",
479 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
480 reg = <0x211000 0x1000>;
481 #address-cells = <1>;
482 #size-cells = <0>;
483 interrupts = <45 0x2 0 0>;
484 };
485
486 crypto: crypto@300000 {
487 compatible = "fsl,sec-v4.0";
488 #address-cells = <1>;
489 #size-cells = <1>;
490 reg = <0x300000 0x10000>;
491 ranges = <0 0x300000 0x10000>;
492 interrupt-parent = <&mpic>;
493 interrupts = <92 2 0 0>;
494
495 sec_jr0: jr@1000 {
496 compatible = "fsl,sec-v4.0-job-ring";
497 reg = <0x1000 0x1000>;
498 interrupt-parent = <&mpic>;
499 interrupts = <88 2 0 0>;
500 };
501
502 sec_jr1: jr@2000 {
503 compatible = "fsl,sec-v4.0-job-ring";
504 reg = <0x2000 0x1000>;
505 interrupt-parent = <&mpic>;
506 interrupts = <89 2 0 0>;
507 };
508
509 sec_jr2: jr@3000 {
510 compatible = "fsl,sec-v4.0-job-ring";
511 reg = <0x3000 0x1000>;
512 interrupt-parent = <&mpic>;
513 interrupts = <90 2 0 0>;
514 };
515
516 sec_jr3: jr@4000 {
517 compatible = "fsl,sec-v4.0-job-ring";
518 reg = <0x4000 0x1000>;
519 interrupt-parent = <&mpic>;
520 interrupts = <91 2 0 0>;
521 };
522
523 rtic@6000 {
524 compatible = "fsl,sec-v4.0-rtic";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 reg = <0x6000 0x100>;
528 ranges = <0x0 0x6100 0xe00>;
529
530 rtic_a: rtic-a@0 {
531 compatible = "fsl,sec-v4.0-rtic-memory";
532 reg = <0x00 0x20 0x100 0x80>;
533 };
534
535 rtic_b: rtic-b@20 {
536 compatible = "fsl,sec-v4.0-rtic-memory";
537 reg = <0x20 0x20 0x200 0x80>;
538 };
539
540 rtic_c: rtic-c@40 {
541 compatible = "fsl,sec-v4.0-rtic-memory";
542 reg = <0x40 0x20 0x300 0x80>;
543 };
544
545 rtic_d: rtic-d@60 {
546 compatible = "fsl,sec-v4.0-rtic-memory";
547 reg = <0x60 0x20 0x500 0x80>;
548 };
549 };
550 };
551
552 sec_mon: sec_mon@314000 {
553 compatible = "fsl,sec-v4.0-mon";
554 reg = <0x314000 0x1000>;
555 interrupt-parent = <&mpic>;
556 interrupts = <93 2 0 0>;
557 };
558 };
559
560 rapidio0: rapidio@ffe0c0000 {
561 #address-cells = <2>;
562 #size-cells = <2>;
563 compatible = "fsl,rapidio-delta";
564 interrupts = <
565 16 2 1 11 /* err_irq */
566 56 2 0 0 /* bell_outb_irq */
567 57 2 0 0 /* bell_inb_irq */
568 60 2 0 0 /* msg1_tx_irq */
569 61 2 0 0 /* msg1_rx_irq */
570 62 2 0 0 /* msg2_tx_irq */
571 63 2 0 0>; /* msg2_rx_irq */
572 };
573
574 localbus@ffe124000 {
575 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
576 interrupts = <25 2 0 0>;
577 #address-cells = <2>;
578 #size-cells = <1>;
579 };
580
581 pci0: pcie@ffe200000 {
582 compatible = "fsl,p4080-pcie";
583 device_type = "pci";
584 #size-cells = <2>;
585 #address-cells = <3>;
586 bus-range = <0x0 0xff>;
587 clock-frequency = <0x1fca055>;
588 fsl,msi = <&msi0>;
589 interrupts = <16 2 1 15>;
590 pcie@0 {
591 reg = <0 0 0 0 0>;
592 #interrupt-cells = <1>;
593 #size-cells = <2>;
594 #address-cells = <3>;
595 device_type = "pci";
596 interrupts = <16 2 1 15>;
597 interrupt-map-mask = <0xf800 0 0 7>;
598 interrupt-map = <
599 /* IDSEL 0x0 */
600 0000 0 0 1 &mpic 40 1 0 0
601 0000 0 0 2 &mpic 1 1 0 0
602 0000 0 0 3 &mpic 2 1 0 0
603 0000 0 0 4 &mpic 3 1 0 0
604 >;
605 };
606 };
607
608 pci1: pcie@ffe201000 {
609 compatible = "fsl,p4080-pcie";
610 device_type = "pci";
611 #size-cells = <2>;
612 #address-cells = <3>;
613 bus-range = <0 0xff>;
614 clock-frequency = <0x1fca055>;
615 fsl,msi = <&msi1>;
616 interrupts = <16 2 1 14>;
617 pcie@0 {
618 reg = <0 0 0 0 0>;
619 #interrupt-cells = <1>;
620 #size-cells = <2>;
621 #address-cells = <3>;
622 device_type = "pci";
623 interrupts = <16 2 1 14>;
624 interrupt-map-mask = <0xf800 0 0 7>;
625 interrupt-map = <
626 /* IDSEL 0x0 */
627 0000 0 0 1 &mpic 41 1 0 0
628 0000 0 0 2 &mpic 5 1 0 0
629 0000 0 0 3 &mpic 6 1 0 0
630 0000 0 0 4 &mpic 7 1 0 0
631 >;
632 };
633 };
634
635 pci2: pcie@ffe202000 {
636 compatible = "fsl,p4080-pcie";
637 device_type = "pci";
638 #size-cells = <2>;
639 #address-cells = <3>;
640 bus-range = <0x0 0xff>;
641 clock-frequency = <0x1fca055>;
642 fsl,msi = <&msi2>;
643 interrupts = <16 2 1 13>;
644 pcie@0 {
645 reg = <0 0 0 0 0>;
646 #interrupt-cells = <1>;
647 #size-cells = <2>;
648 #address-cells = <3>;
649 device_type = "pci";
650 interrupts = <16 2 1 13>;
651 interrupt-map-mask = <0xf800 0 0 7>;
652 interrupt-map = <
653 /* IDSEL 0x0 */
654 0000 0 0 1 &mpic 42 1 0 0
655 0000 0 0 2 &mpic 9 1 0 0
656 0000 0 0 3 &mpic 10 1 0 0
657 0000 0 0 4 &mpic 11 1 0 0
658 >;
659 };
660 };
661};
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
new file mode 100644
index 00000000000..8366e2fd2fb
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -0,0 +1,215 @@
1/*
2 * P5020DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p5020si.dtsi"
36
37/ {
38 model = "fsl,P5020DS";
39 compatible = "fsl,P5020DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 soc: soc@ffe000000 {
49 spi@110000 {
50 flash@0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "spansion,s25sl12801";
54 reg = <0>;
55 spi-max-frequency = <40000000>; /* input clock */
56 partition@u-boot {
57 label = "u-boot";
58 reg = <0x00000000 0x00100000>;
59 read-only;
60 };
61 partition@kernel {
62 label = "kernel";
63 reg = <0x00100000 0x00500000>;
64 read-only;
65 };
66 partition@dtb {
67 label = "dtb";
68 reg = <0x00600000 0x00100000>;
69 read-only;
70 };
71 partition@fs {
72 label = "file system";
73 reg = <0x00700000 0x00900000>;
74 };
75 };
76 };
77
78 i2c@118100 {
79 eeprom@51 {
80 compatible = "at24,24c256";
81 reg = <0x51>;
82 };
83 eeprom@52 {
84 compatible = "at24,24c256";
85 reg = <0x52>;
86 };
87 };
88
89 i2c@119100 {
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 interrupts = <0x1 0x1 0 0>;
94 };
95 };
96 };
97
98 localbus@ffe124000 {
99 reg = <0xf 0xfe124000 0 0x1000>;
100 ranges = <0 0 0xf 0xe8000000 0x08000000
101 2 0 0xf 0xffa00000 0x00040000
102 3 0 0xf 0xffdf0000 0x00008000>;
103
104 flash@0,0 {
105 compatible = "cfi-flash";
106 reg = <0 0 0x08000000>;
107 bank-width = <2>;
108 device-width = <2>;
109 };
110
111 nand@2,0 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,elbc-fcm-nand";
115 reg = <0x2 0x0 0x40000>;
116
117 partition@0 {
118 label = "NAND U-Boot Image";
119 reg = <0x0 0x02000000>;
120 read-only;
121 };
122
123 partition@2000000 {
124 label = "NAND Root File System";
125 reg = <0x02000000 0x10000000>;
126 };
127
128 partition@12000000 {
129 label = "NAND Compressed RFS Image";
130 reg = <0x12000000 0x08000000>;
131 };
132
133 partition@1a000000 {
134 label = "NAND Linux Kernel Image";
135 reg = <0x1a000000 0x04000000>;
136 };
137
138 partition@1e000000 {
139 label = "NAND DTB Image";
140 reg = <0x1e000000 0x01000000>;
141 };
142
143 partition@1f000000 {
144 label = "NAND Writable User area";
145 reg = <0x1f000000 0x21000000>;
146 };
147 };
148
149 board-control@3,0 {
150 compatible = "fsl,p5020ds-pixis";
151 reg = <3 0 0x20>;
152 };
153 };
154
155 pci0: pcie@ffe200000 {
156 reg = <0xf 0xfe200000 0 0x1000>;
157 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
158 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
159
160 pcie@0 {
161 ranges = <0x02000000 0 0xe0000000
162 0x02000000 0 0xe0000000
163 0 0x20000000
164
165 0x01000000 0 0x00000000
166 0x01000000 0 0x00000000
167 0 0x00010000>;
168 };
169 };
170
171 pci1: pcie@ffe201000 {
172 reg = <0xf 0xfe201000 0 0x1000>;
173 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
174 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
175 pcie@0 {
176 ranges = <0x02000000 0 0xe0000000
177 0x02000000 0 0xe0000000
178 0 0x20000000
179
180 0x01000000 0 0x00000000
181 0x01000000 0 0x00000000
182 0 0x00010000>;
183 };
184 };
185
186 pci2: pcie@ffe202000 {
187 reg = <0xf 0xfe202000 0 0x1000>;
188 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
189 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
190 pcie@0 {
191 ranges = <0x02000000 0 0xe0000000
192 0x02000000 0 0xe0000000
193 0 0x20000000
194
195 0x01000000 0 0x00000000
196 0x01000000 0 0x00000000
197 0 0x00010000>;
198 };
199 };
200
201 pci3: pcie@ffe203000 {
202 reg = <0xf 0xfe203000 0 0x1000>;
203 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
204 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
205 pcie@0 {
206 ranges = <0x02000000 0 0xe0000000
207 0x02000000 0 0xe0000000
208 0 0x20000000
209
210 0x01000000 0 0x00000000
211 0x01000000 0 0x00000000
212 0 0x00010000>;
213 };
214 };
215};
diff --git a/arch/powerpc/boot/dts/p5020si.dtsi b/arch/powerpc/boot/dts/p5020si.dtsi
new file mode 100644
index 00000000000..5e6048ec55b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5020si.dtsi
@@ -0,0 +1,652 @@
1/*
2 * P5020 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P5020";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74/*
75 rio0 = &rapidio0;
76 */
77 };
78
79 cpus {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 cpu0: PowerPC,e5500@0 {
84 device_type = "cpu";
85 reg = <0>;
86 next-level-cache = <&L2_0>;
87 L2_0: l2-cache {
88 next-level-cache = <&cpc>;
89 };
90 };
91 cpu1: PowerPC,e5500@1 {
92 device_type = "cpu";
93 reg = <1>;
94 next-level-cache = <&L2_1>;
95 L2_1: l2-cache {
96 next-level-cache = <&cpc>;
97 };
98 };
99 };
100
101 soc: soc@ffe000000 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 device_type = "soc";
105 compatible = "simple-bus";
106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
107 reg = <0xf 0xfe000000 0 0x00001000>;
108
109 soc-sram-error {
110 compatible = "fsl,soc-sram-error";
111 interrupts = <16 2 1 29>;
112 };
113
114 corenet-law@0 {
115 compatible = "fsl,corenet-law";
116 reg = <0x0 0x1000>;
117 fsl,num-laws = <32>;
118 };
119
120 memory-controller@8000 {
121 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
122 reg = <0x8000 0x1000>;
123 interrupts = <16 2 1 23>;
124 };
125
126 memory-controller@9000 {
127 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupts = <16 2 1 22>;
130 };
131
132 cpc: l3-cache-controller@10000 {
133 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
134 reg = <0x10000 0x1000
135 0x11000 0x1000>;
136 interrupts = <16 2 1 27
137 16 2 1 26>;
138 };
139
140 corenet-cf@18000 {
141 compatible = "fsl,corenet-cf";
142 reg = <0x18000 0x1000>;
143 interrupts = <16 2 1 31>;
144 fsl,ccf-num-csdids = <32>;
145 fsl,ccf-num-snoopids = <32>;
146 };
147
148 iommu@20000 {
149 compatible = "fsl,pamu-v1.0", "fsl,pamu";
150 reg = <0x20000 0x4000>;
151 interrupts = <
152 24 2 0 0
153 16 2 1 30>;
154 };
155
156 mpic: pic@40000 {
157 clock-frequency = <0>;
158 interrupt-controller;
159 #address-cells = <0>;
160 #interrupt-cells = <4>;
161 reg = <0x40000 0x40000>;
162 compatible = "fsl,mpic", "chrp,open-pic";
163 device_type = "open-pic";
164 };
165
166 msi0: msi@41600 {
167 compatible = "fsl,mpic-msi";
168 reg = <0x41600 0x200>;
169 msi-available-ranges = <0 0x100>;
170 interrupts = <
171 0xe0 0 0 0
172 0xe1 0 0 0
173 0xe2 0 0 0
174 0xe3 0 0 0
175 0xe4 0 0 0
176 0xe5 0 0 0
177 0xe6 0 0 0
178 0xe7 0 0 0>;
179 };
180
181 msi1: msi@41800 {
182 compatible = "fsl,mpic-msi";
183 reg = <0x41800 0x200>;
184 msi-available-ranges = <0 0x100>;
185 interrupts = <
186 0xe8 0 0 0
187 0xe9 0 0 0
188 0xea 0 0 0
189 0xeb 0 0 0
190 0xec 0 0 0
191 0xed 0 0 0
192 0xee 0 0 0
193 0xef 0 0 0>;
194 };
195
196 msi2: msi@41a00 {
197 compatible = "fsl,mpic-msi";
198 reg = <0x41a00 0x200>;
199 msi-available-ranges = <0 0x100>;
200 interrupts = <
201 0xf0 0 0 0
202 0xf1 0 0 0
203 0xf2 0 0 0
204 0xf3 0 0 0
205 0xf4 0 0 0
206 0xf5 0 0 0
207 0xf6 0 0 0
208 0xf7 0 0 0>;
209 };
210
211 guts: global-utilities@e0000 {
212 compatible = "fsl,qoriq-device-config-1.0";
213 reg = <0xe0000 0xe00>;
214 fsl,has-rstcr;
215 #sleep-cells = <1>;
216 fsl,liodn-bits = <12>;
217 };
218
219 pins: global-utilities@e0e00 {
220 compatible = "fsl,qoriq-pin-control-1.0";
221 reg = <0xe0e00 0x200>;
222 #sleep-cells = <2>;
223 };
224
225 clockgen: global-utilities@e1000 {
226 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
227 reg = <0xe1000 0x1000>;
228 clock-frequency = <0>;
229 };
230
231 rcpm: global-utilities@e2000 {
232 compatible = "fsl,qoriq-rcpm-1.0";
233 reg = <0xe2000 0x1000>;
234 #sleep-cells = <1>;
235 };
236
237 sfp: sfp@e8000 {
238 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
239 reg = <0xe8000 0x1000>;
240 };
241
242 serdes: serdes@ea000 {
243 compatible = "fsl,p5020-serdes";
244 reg = <0xea000 0x1000>;
245 };
246
247 dma0: dma@100300 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
251 reg = <0x100300 0x4>;
252 ranges = <0x0 0x100100 0x200>;
253 cell-index = <0>;
254 dma-channel@0 {
255 compatible = "fsl,p5020-dma-channel",
256 "fsl,eloplus-dma-channel";
257 reg = <0x0 0x80>;
258 cell-index = <0>;
259 interrupts = <28 2 0 0>;
260 };
261 dma-channel@80 {
262 compatible = "fsl,p5020-dma-channel",
263 "fsl,eloplus-dma-channel";
264 reg = <0x80 0x80>;
265 cell-index = <1>;
266 interrupts = <29 2 0 0>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,p5020-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupts = <30 2 0 0>;
274 };
275 dma-channel@180 {
276 compatible = "fsl,p5020-dma-channel",
277 "fsl,eloplus-dma-channel";
278 reg = <0x180 0x80>;
279 cell-index = <3>;
280 interrupts = <31 2 0 0>;
281 };
282 };
283
284 dma1: dma@101300 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
288 reg = <0x101300 0x4>;
289 ranges = <0x0 0x101100 0x200>;
290 cell-index = <1>;
291 dma-channel@0 {
292 compatible = "fsl,p5020-dma-channel",
293 "fsl,eloplus-dma-channel";
294 reg = <0x0 0x80>;
295 cell-index = <0>;
296 interrupts = <32 2 0 0>;
297 };
298 dma-channel@80 {
299 compatible = "fsl,p5020-dma-channel",
300 "fsl,eloplus-dma-channel";
301 reg = <0x80 0x80>;
302 cell-index = <1>;
303 interrupts = <33 2 0 0>;
304 };
305 dma-channel@100 {
306 compatible = "fsl,p5020-dma-channel",
307 "fsl,eloplus-dma-channel";
308 reg = <0x100 0x80>;
309 cell-index = <2>;
310 interrupts = <34 2 0 0>;
311 };
312 dma-channel@180 {
313 compatible = "fsl,p5020-dma-channel",
314 "fsl,eloplus-dma-channel";
315 reg = <0x180 0x80>;
316 cell-index = <3>;
317 interrupts = <35 2 0 0>;
318 };
319 };
320
321 spi@110000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
325 reg = <0x110000 0x1000>;
326 interrupts = <53 0x2 0 0>;
327 fsl,espi-num-chipselects = <4>;
328 };
329
330 sdhc: sdhc@114000 {
331 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
332 reg = <0x114000 0x1000>;
333 interrupts = <48 2 0 0>;
334 sdhci,auto-cmd12;
335 clock-frequency = <0>;
336 };
337
338 i2c@118000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 cell-index = <0>;
342 compatible = "fsl-i2c";
343 reg = <0x118000 0x100>;
344 interrupts = <38 2 0 0>;
345 dfsrr;
346 };
347
348 i2c@118100 {
349 #address-cells = <1>;
350 #size-cells = <0>;
351 cell-index = <1>;
352 compatible = "fsl-i2c";
353 reg = <0x118100 0x100>;
354 interrupts = <38 2 0 0>;
355 dfsrr;
356 };
357
358 i2c@119000 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 cell-index = <2>;
362 compatible = "fsl-i2c";
363 reg = <0x119000 0x100>;
364 interrupts = <39 2 0 0>;
365 dfsrr;
366 };
367
368 i2c@119100 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 cell-index = <3>;
372 compatible = "fsl-i2c";
373 reg = <0x119100 0x100>;
374 interrupts = <39 2 0 0>;
375 dfsrr;
376 };
377
378 serial0: serial@11c500 {
379 cell-index = <0>;
380 device_type = "serial";
381 compatible = "ns16550";
382 reg = <0x11c500 0x100>;
383 clock-frequency = <0>;
384 interrupts = <36 2 0 0>;
385 };
386
387 serial1: serial@11c600 {
388 cell-index = <1>;
389 device_type = "serial";
390 compatible = "ns16550";
391 reg = <0x11c600 0x100>;
392 clock-frequency = <0>;
393 interrupts = <36 2 0 0>;
394 };
395
396 serial2: serial@11d500 {
397 cell-index = <2>;
398 device_type = "serial";
399 compatible = "ns16550";
400 reg = <0x11d500 0x100>;
401 clock-frequency = <0>;
402 interrupts = <37 2 0 0>;
403 };
404
405 serial3: serial@11d600 {
406 cell-index = <3>;
407 device_type = "serial";
408 compatible = "ns16550";
409 reg = <0x11d600 0x100>;
410 clock-frequency = <0>;
411 interrupts = <37 2 0 0>;
412 };
413
414 gpio0: gpio@130000 {
415 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
416 reg = <0x130000 0x1000>;
417 interrupts = <55 2 0 0>;
418 #gpio-cells = <2>;
419 gpio-controller;
420 };
421
422 usb0: usb@210000 {
423 compatible = "fsl,p5020-usb2-mph",
424 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
425 reg = <0x210000 0x1000>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 interrupts = <44 0x2 0 0>;
429 phy_type = "utmi";
430 port0;
431 };
432
433 usb1: usb@211000 {
434 compatible = "fsl,p5020-usb2-dr",
435 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
436 reg = <0x211000 0x1000>;
437 #address-cells = <1>;
438 #size-cells = <0>;
439 interrupts = <45 0x2 0 0>;
440 dr_mode = "host";
441 phy_type = "utmi";
442 };
443
444 sata@220000 {
445 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
446 reg = <0x220000 0x1000>;
447 interrupts = <68 0x2 0 0>;
448 };
449
450 sata@221000 {
451 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
452 reg = <0x221000 0x1000>;
453 interrupts = <69 0x2 0 0>;
454 };
455
456 crypto: crypto@300000 {
457 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 reg = <0x300000 0x10000>;
461 ranges = <0 0x300000 0x10000>;
462 interrupts = <92 2 0 0>;
463
464 sec_jr0: jr@1000 {
465 compatible = "fsl,sec-v4.2-job-ring",
466 "fsl,sec-v4.0-job-ring";
467 reg = <0x1000 0x1000>;
468 interrupts = <88 2 0 0>;
469 };
470
471 sec_jr1: jr@2000 {
472 compatible = "fsl,sec-v4.2-job-ring",
473 "fsl,sec-v4.0-job-ring";
474 reg = <0x2000 0x1000>;
475 interrupts = <89 2 0 0>;
476 };
477
478 sec_jr2: jr@3000 {
479 compatible = "fsl,sec-v4.2-job-ring",
480 "fsl,sec-v4.0-job-ring";
481 reg = <0x3000 0x1000>;
482 interrupts = <90 2 0 0>;
483 };
484
485 sec_jr3: jr@4000 {
486 compatible = "fsl,sec-v4.2-job-ring",
487 "fsl,sec-v4.0-job-ring";
488 reg = <0x4000 0x1000>;
489 interrupts = <91 2 0 0>;
490 };
491
492 rtic@6000 {
493 compatible = "fsl,sec-v4.2-rtic",
494 "fsl,sec-v4.0-rtic";
495 #address-cells = <1>;
496 #size-cells = <1>;
497 reg = <0x6000 0x100>;
498 ranges = <0x0 0x6100 0xe00>;
499
500 rtic_a: rtic-a@0 {
501 compatible = "fsl,sec-v4.2-rtic-memory",
502 "fsl,sec-v4.0-rtic-memory";
503 reg = <0x00 0x20 0x100 0x80>;
504 };
505
506 rtic_b: rtic-b@20 {
507 compatible = "fsl,sec-v4.2-rtic-memory",
508 "fsl,sec-v4.0-rtic-memory";
509 reg = <0x20 0x20 0x200 0x80>;
510 };
511
512 rtic_c: rtic-c@40 {
513 compatible = "fsl,sec-v4.2-rtic-memory",
514 "fsl,sec-v4.0-rtic-memory";
515 reg = <0x40 0x20 0x300 0x80>;
516 };
517
518 rtic_d: rtic-d@60 {
519 compatible = "fsl,sec-v4.2-rtic-memory",
520 "fsl,sec-v4.0-rtic-memory";
521 reg = <0x60 0x20 0x500 0x80>;
522 };
523 };
524 };
525
526 sec_mon: sec_mon@314000 {
527 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
528 reg = <0x314000 0x1000>;
529 interrupts = <93 2 0 0>;
530 };
531 };
532
533/*
534 rapidio0: rapidio@ffe0c0000
535*/
536
537 localbus@ffe124000 {
538 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
539 interrupts = <25 2 0 0>;
540 #address-cells = <2>;
541 #size-cells = <1>;
542 };
543
544 pci0: pcie@ffe200000 {
545 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
546 device_type = "pci";
547 #size-cells = <2>;
548 #address-cells = <3>;
549 bus-range = <0x0 0xff>;
550 clock-frequency = <0x1fca055>;
551 fsl,msi = <&msi0>;
552 interrupts = <16 2 1 15>;
553
554 pcie@0 {
555 reg = <0 0 0 0 0>;
556 #interrupt-cells = <1>;
557 #size-cells = <2>;
558 #address-cells = <3>;
559 device_type = "pci";
560 interrupts = <16 2 1 15>;
561 interrupt-map-mask = <0xf800 0 0 7>;
562 interrupt-map = <
563 /* IDSEL 0x0 */
564 0000 0 0 1 &mpic 40 1 0 0
565 0000 0 0 2 &mpic 1 1 0 0
566 0000 0 0 3 &mpic 2 1 0 0
567 0000 0 0 4 &mpic 3 1 0 0
568 >;
569 };
570 };
571
572 pci1: pcie@ffe201000 {
573 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
574 device_type = "pci";
575 #size-cells = <2>;
576 #address-cells = <3>;
577 bus-range = <0 0xff>;
578 clock-frequency = <0x1fca055>;
579 fsl,msi = <&msi1>;
580 interrupts = <16 2 1 14>;
581 pcie@0 {
582 reg = <0 0 0 0 0>;
583 #interrupt-cells = <1>;
584 #size-cells = <2>;
585 #address-cells = <3>;
586 device_type = "pci";
587 interrupts = <16 2 1 14>;
588 interrupt-map-mask = <0xf800 0 0 7>;
589 interrupt-map = <
590 /* IDSEL 0x0 */
591 0000 0 0 1 &mpic 41 1 0 0
592 0000 0 0 2 &mpic 5 1 0 0
593 0000 0 0 3 &mpic 6 1 0 0
594 0000 0 0 4 &mpic 7 1 0 0
595 >;
596 };
597 };
598
599 pci2: pcie@ffe202000 {
600 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
601 device_type = "pci";
602 #size-cells = <2>;
603 #address-cells = <3>;
604 bus-range = <0x0 0xff>;
605 clock-frequency = <0x1fca055>;
606 fsl,msi = <&msi2>;
607 interrupts = <16 2 1 13>;
608 pcie@0 {
609 reg = <0 0 0 0 0>;
610 #interrupt-cells = <1>;
611 #size-cells = <2>;
612 #address-cells = <3>;
613 device_type = "pci";
614 interrupts = <16 2 1 13>;
615 interrupt-map-mask = <0xf800 0 0 7>;
616 interrupt-map = <
617 /* IDSEL 0x0 */
618 0000 0 0 1 &mpic 42 1 0 0
619 0000 0 0 2 &mpic 9 1 0 0
620 0000 0 0 3 &mpic 10 1 0 0
621 0000 0 0 4 &mpic 11 1 0 0
622 >;
623 };
624 };
625
626 pci3: pcie@ffe203000 {
627 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
628 device_type = "pci";
629 #size-cells = <2>;
630 #address-cells = <3>;
631 bus-range = <0x0 0xff>;
632 clock-frequency = <0x1fca055>;
633 fsl,msi = <&msi2>;
634 interrupts = <16 2 1 12>;
635 pcie@0 {
636 reg = <0 0 0 0 0>;
637 #interrupt-cells = <1>;
638 #size-cells = <2>;
639 #address-cells = <3>;
640 device_type = "pci";
641 interrupts = <16 2 1 12>;
642 interrupt-map-mask = <0xf800 0 0 7>;
643 interrupt-map = <
644 /* IDSEL 0x0 */
645 0000 0 0 1 &mpic 43 1 0 0
646 0000 0 0 2 &mpic 0 1 0 0
647 0000 0 0 3 &mpic 4 1 0 0
648 0000 0 0 4 &mpic 8 1 0 0
649 >;
650 };
651 };
652};
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 739dd0da241..b1d329246b0 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -110,6 +110,18 @@
110 dcr-reg = <0x010 0x002>; 110 dcr-reg = <0x010 0x002>;
111 }; 111 };
112 112
113 CRYPTO: crypto@e0100000 {
114 compatible = "amcc,ppc440epx-crypto","amcc,ppc4xx-crypto";
115 reg = <0 0xE0100000 0x80400>;
116 interrupt-parent = <&UIC0>;
117 interrupts = <0x17 0x4>;
118 };
119
120 rng@e0120000 {
121 compatible = "amcc,ppc440epx-rng","amcc,ppc4xx-rng";
122 reg = <0 0xE0120000 0x150>;
123 };
124
113 DMA0: dma { 125 DMA0: dma {
114 compatible = "ibm,dma-440epx", "ibm,dma-4xx"; 126 compatible = "ibm,dma-440epx", "ibm,dma-4xx";
115 dcr-reg = <0x100 0x027>; 127 dcr-reg = <0x100 0x027>;
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index feb4ef6bd14..38c35404bdc 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -240,6 +240,8 @@
240 #address-cells = <2>; 240 #address-cells = <2>;
241 #size-cells = <1>; 241 #size-cells = <1>;
242 reg = <0xe0005000 0x40>; 242 reg = <0xe0005000 0x40>;
243 interrupt-parent = <&mpic>;
244 interrupts = <19 2>;
243 245
244 ranges = <0 0 0xfc000000 0x04000000 246 ranges = <0 0 0xfc000000 0x04000000
245 2 0 0xc8000000 0x04000000 247 2 0 0xc8000000 0x04000000
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 058438f9629..1657ad0bf8a 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -337,7 +337,7 @@
337 rx-fifo-size = <4096>; 337 rx-fifo-size = <4096>;
338 tx-fifo-size = <2048>; 338 tx-fifo-size = <2048>;
339 phy-mode = "rgmii"; 339 phy-mode = "rgmii";
340 phy-map = <0x00000001>; 340 phy-address = <1>;
341 rgmii-device = <&RGMII0>; 341 rgmii-device = <&RGMII0>;
342 rgmii-channel = <0>; 342 rgmii-channel = <0>;
343 zmii-device = <&ZMII0>; 343 zmii-device = <&ZMII0>;
@@ -361,7 +361,7 @@
361 rx-fifo-size = <4096>; 361 rx-fifo-size = <4096>;
362 tx-fifo-size = <2048>; 362 tx-fifo-size = <2048>;
363 phy-mode = "rgmii"; 363 phy-mode = "rgmii";
364 phy-map = <0x00000003>; 364 phy-address = <3>;
365 rgmii-device = <&RGMII0>; 365 rgmii-device = <&RGMII0>;
366 rgmii-channel = <1>; 366 rgmii-channel = <1>;
367 zmii-device = <&ZMII0>; 367 zmii-device = <&ZMII0>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 15ca731bc24..0a4cedbdcb5 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -277,6 +277,48 @@
277 }; 277 };
278 }; 278 };
279 279
280 localbus@e0005000 {
281 #address-cells = <2>;
282 #size-cells = <1>;
283 compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
284 "simple-bus";
285 reg = <0xe0005000 0x1000>;
286 interrupt-parent = <&mpic>;
287 interrupts = <19 2>;
288
289 ranges = <0x0 0x0 0xfe000000 0x02000000>;
290
291 nor@0,0 {
292 #address-cells = <1>;
293 #size-cells = <1>;
294 compatible = "cfi-flash";
295 reg = <0x0 0x0 0x02000000>;
296 bank-width = <4>;
297 device-width = <2>;
298 partition@0 {
299 label = "kernel";
300 reg = <0x00000000 0x00180000>;
301 };
302 partition@180000 {
303 label = "root";
304 reg = <0x00180000 0x01dc0000>;
305 };
306 partition@1f40000 {
307 label = "env1";
308 reg = <0x01f40000 0x00040000>;
309 };
310 partition@1f80000 {
311 label = "env2";
312 reg = <0x01f80000 0x00040000>;
313 };
314 partition@1fc0000 {
315 label = "u-boot";
316 reg = <0x01fc0000 0x00040000>;
317 read-only;
318 };
319 };
320 };
321
280 pci0: pci@e0008000 { 322 pci0: pci@e0008000 {
281 #interrupt-cells = <1>; 323 #interrupt-cells = <1>;
282 #size-cells = <2>; 324 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 5dbb36edb03..9452c3c0511 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -346,6 +346,8 @@
346 #address-cells = <2>; 346 #address-cells = <2>;
347 #size-cells = <1>; 347 #size-cells = <1>;
348 reg = <0xa0005000 0x100>; // BRx, ORx, etc. 348 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
349 interrupt-parent = <&mpic>;
350 interrupts = <19 2>;
349 351
350 ranges = < 352 ranges = <
351 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index a050ae42710..619776f72c9 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -346,6 +346,8 @@
346 #address-cells = <2>; 346 #address-cells = <2>;
347 #size-cells = <1>; 347 #size-cells = <1>;
348 reg = <0xe0005000 0x100>; // BRx, ORx, etc. 348 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
349 interrupt-parent = <&mpic>;
350 interrupts = <19 2>;
349 351
350 ranges = < 352 ranges = <
351 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 22ec39b5bee..7665a16a8b9 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -312,6 +312,8 @@
312 #address-cells = <2>; 312 #address-cells = <2>;
313 #size-cells = <1>; 313 #size-cells = <1>;
314 reg = <0xe0005000 0x100>; // BRx, ORx, etc. 314 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
315 interrupt-parent = <&mpic>;
316 interrupts = <19 2>;
315 317
316 ranges = < 318 ranges = <
317 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 319 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
index a0cf53fbd55..c41a80c55e4 100644
--- a/arch/powerpc/boot/dts/xpedite5200.dts
+++ b/arch/powerpc/boot/dts/xpedite5200.dts
@@ -374,6 +374,8 @@
374 #address-cells = <2>; 374 #address-cells = <2>;
375 #size-cells = <1>; 375 #size-cells = <1>;
376 reg = <0xef005000 0x100>; // BRx, ORx, etc. 376 reg = <0xef005000 0x100>; // BRx, ORx, etc.
377 interrupt-parent = <&mpic>;
378 interrupts = <19 2>;
377 379
378 ranges = < 380 ranges = <
379 0 0x0 0xfc000000 0x04000000 // NOR boot flash 381 0 0x0 0xfc000000 0x04000000 // NOR boot flash
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
index c5b29752651..c0efcbb4513 100644
--- a/arch/powerpc/boot/dts/xpedite5200_xmon.dts
+++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
@@ -378,6 +378,8 @@
378 #address-cells = <2>; 378 #address-cells = <2>;
379 #size-cells = <1>; 379 #size-cells = <1>;
380 reg = <0xef005000 0x100>; // BRx, ORx, etc. 380 reg = <0xef005000 0x100>; // BRx, ORx, etc.
381 interrupt-parent = <&mpic>;
382 interrupts = <19 2>;
381 383
382 ranges = < 384 ranges = <
383 0 0x0 0xf8000000 0x08000000 // NOR boot flash 385 0 0x0 0xf8000000 0x08000000 // NOR boot flash
diff --git a/arch/powerpc/boot/treeboot-iss4xx.c b/arch/powerpc/boot/treeboot-iss4xx.c
index fcc44952874..329e710feda 100644
--- a/arch/powerpc/boot/treeboot-iss4xx.c
+++ b/arch/powerpc/boot/treeboot-iss4xx.c
@@ -34,9 +34,29 @@
34 34
35BSS_STACK(4096); 35BSS_STACK(4096);
36 36
37static u32 ibm4xx_memstart;
38
37static void iss_4xx_fixups(void) 39static void iss_4xx_fixups(void)
38{ 40{
39 ibm4xx_sdram_fixup_memsize(); 41 void *memory;
42 u32 reg[3];
43
44 memory = finddevice("/memory");
45 if (!memory)
46 fatal("Can't find memory node\n");
47 /* This assumes #address-cells = 2, #size-cells =1 and that */
48 getprop(memory, "reg", reg, sizeof(reg));
49 if (reg[2])
50 /* If the device tree specifies the memory range, use it */
51 ibm4xx_memstart = reg[1];
52 else
53 /* othersize, read it from the SDRAM controller */
54 ibm4xx_sdram_fixup_memsize();
55}
56
57static void *iss_4xx_vmlinux_alloc(unsigned long size)
58{
59 return (void *)ibm4xx_memstart;
40} 60}
41 61
42#define SPRN_PIR 0x11E /* Processor Indentification Register */ 62#define SPRN_PIR 0x11E /* Processor Indentification Register */
@@ -48,6 +68,7 @@ void platform_init(void)
48 68
49 simple_alloc_init(_end, avail_ram, 128, 64); 69 simple_alloc_init(_end, avail_ram, 128, 64);
50 platform_ops.fixups = iss_4xx_fixups; 70 platform_ops.fixups = iss_4xx_fixups;
71 platform_ops.vmlinux_alloc = iss_4xx_vmlinux_alloc;
51 platform_ops.exit = ibm44x_dbcr_reset; 72 platform_ops.exit = ibm44x_dbcr_reset;
52 pir_reg = mfspr(SPRN_PIR); 73 pir_reg = mfspr(SPRN_PIR);
53 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg); 74 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-31 06:03:22 -0400