aboutsummaryrefslogtreecommitdiffstats
path: root/arch/openrisc/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/openrisc/include')
-rw-r--r--arch/openrisc/include/asm/Kbuild64
-rw-r--r--arch/openrisc/include/asm/asm-offsets.h1
-rw-r--r--arch/openrisc/include/asm/bitops.h59
-rw-r--r--arch/openrisc/include/asm/bitops/__ffs.h33
-rw-r--r--arch/openrisc/include/asm/bitops/__fls.h33
-rw-r--r--arch/openrisc/include/asm/bitops/ffs.h32
-rw-r--r--arch/openrisc/include/asm/bitops/fls.h33
-rw-r--r--arch/openrisc/include/asm/byteorder.h1
-rw-r--r--arch/openrisc/include/asm/cache.h29
-rw-r--r--arch/openrisc/include/asm/cpuinfo.h34
-rw-r--r--arch/openrisc/include/asm/delay.h24
-rw-r--r--arch/openrisc/include/asm/dma-mapping.h189
-rw-r--r--arch/openrisc/include/asm/elf.h108
-rw-r--r--arch/openrisc/include/asm/fixmap.h87
-rw-r--r--arch/openrisc/include/asm/gpio.h65
-rw-r--r--arch/openrisc/include/asm/io.h51
-rw-r--r--arch/openrisc/include/asm/irq.h27
-rw-r--r--arch/openrisc/include/asm/irqflags.h29
-rw-r--r--arch/openrisc/include/asm/linkage.h25
-rw-r--r--arch/openrisc/include/asm/memblock.h24
-rw-r--r--arch/openrisc/include/asm/mmu.h26
-rw-r--r--arch/openrisc/include/asm/mmu_context.h43
-rw-r--r--arch/openrisc/include/asm/mutex.h27
-rw-r--r--arch/openrisc/include/asm/page.h110
-rw-r--r--arch/openrisc/include/asm/param.h26
-rw-r--r--arch/openrisc/include/asm/pgalloc.h102
-rw-r--r--arch/openrisc/include/asm/pgtable.h463
-rw-r--r--arch/openrisc/include/asm/processor.h113
-rw-r--r--arch/openrisc/include/asm/prom.h77
-rw-r--r--arch/openrisc/include/asm/ptrace.h131
-rw-r--r--arch/openrisc/include/asm/serial.h36
-rw-r--r--arch/openrisc/include/asm/sigcontext.h33
-rw-r--r--arch/openrisc/include/asm/spinlock.h24
-rw-r--r--arch/openrisc/include/asm/spr.h42
-rw-r--r--arch/openrisc/include/asm/spr_defs.h604
-rw-r--r--arch/openrisc/include/asm/syscall.h77
-rw-r--r--arch/openrisc/include/asm/syscalls.h27
-rw-r--r--arch/openrisc/include/asm/system.h35
-rw-r--r--arch/openrisc/include/asm/thread_info.h134
-rw-r--r--arch/openrisc/include/asm/timex.h36
-rw-r--r--arch/openrisc/include/asm/tlb.h34
-rw-r--r--arch/openrisc/include/asm/tlbflush.h55
-rw-r--r--arch/openrisc/include/asm/uaccess.h355
-rw-r--r--arch/openrisc/include/asm/unaligned.h51
-rw-r--r--arch/openrisc/include/asm/unistd.h31
45 files changed, 3640 insertions, 0 deletions
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
new file mode 100644
index 00000000000..11162e6c878
--- /dev/null
+++ b/arch/openrisc/include/asm/Kbuild
@@ -0,0 +1,64 @@
1include include/asm-generic/Kbuild.asm
2
3header-y += spr_defs.h
4
5generic-y += atomic.h
6generic-y += auxvec.h
7generic-y += bitsperlong.h
8generic-y += bug.h
9generic-y += bugs.h
10generic-y += cacheflush.h
11generic-y += checksum.h
12generic-y += cmpxchg.h
13generic-y += cmpxchg-local.h
14generic-y += cpumask.h
15generic-y += cputime.h
16generic-y += current.h
17generic-y += device.h
18generic-y += div64.h
19generic-y += dma.h
20generic-y += emergency-restart.h
21generic-y += errno.h
22generic-y += fb.h
23generic-y += fcntl.h
24generic-y += ftrace.h
25generic-y += futex.h
26generic-y += hardirq.h
27generic-y += hw_irq.h
28generic-y += ioctl.h
29generic-y += ioctls.h
30generic-y += ipcbuf.h
31generic-y += irq_regs.h
32generic-y += kdebug.h
33generic-y += kmap_types.h
34generic-y += local.h
35generic-y += mman.h
36generic-y += module.h
37generic-y += msgbuf.h
38generic-y += pci.h
39generic-y += percpu.h
40generic-y += poll.h
41generic-y += posix_types.h
42generic-y += resource.h
43generic-y += rmap.h
44generic-y += scatterlist.h
45generic-y += sections.h
46generic-y += segment.h
47generic-y += sembuf.h
48generic-y += setup.h
49generic-y += shmbuf.h
50generic-y += shmparam.h
51generic-y += siginfo.h
52generic-y += signal.h
53generic-y += socket.h
54generic-y += sockios.h
55generic-y += statfs.h
56generic-y += stat.h
57generic-y += string.h
58generic-y += swab.h
59generic-y += termbits.h
60generic-y += termios.h
61generic-y += topology.h
62generic-y += types.h
63generic-y += ucontext.h
64generic-y += user.h
diff --git a/arch/openrisc/include/asm/asm-offsets.h b/arch/openrisc/include/asm/asm-offsets.h
new file mode 100644
index 00000000000..d370ee36a18
--- /dev/null
+++ b/arch/openrisc/include/asm/asm-offsets.h
@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
new file mode 100644
index 00000000000..a9e11efae14
--- /dev/null
+++ b/arch/openrisc/include/asm/bitops.h
@@ -0,0 +1,59 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_BITOPS_H
20#define __ASM_OPENRISC_BITOPS_H
21
22/*
23 * Where we haven't written assembly versions yet, we fall back to the
24 * generic implementations. Otherwise, we pull in our (hopefully)
25 * optimized versions.
26 */
27
28#include <linux/irqflags.h>
29#include <linux/compiler.h>
30
31/*
32 * clear_bit may not imply a memory barrier
33 */
34#ifndef smp_mb__before_clear_bit
35#define smp_mb__before_clear_bit() smp_mb()
36#define smp_mb__after_clear_bit() smp_mb()
37#endif
38
39#include <asm/bitops/__ffs.h>
40#include <asm-generic/bitops/ffz.h>
41#include <asm/bitops/fls.h>
42#include <asm/bitops/__fls.h>
43#include <asm-generic/bitops/fls64.h>
44#include <asm-generic/bitops/find.h>
45
46#ifndef _LINUX_BITOPS_H
47#error only <linux/bitops.h> can be included directly
48#endif
49
50#include <asm-generic/bitops/sched.h>
51#include <asm/bitops/ffs.h>
52#include <asm-generic/bitops/hweight.h>
53#include <asm-generic/bitops/lock.h>
54
55#include <asm-generic/bitops/atomic.h>
56#include <asm-generic/bitops/non-atomic.h>
57#include <asm-generic/bitops/ext2-atomic.h>
58
59#endif /* __ASM_GENERIC_BITOPS_H */
diff --git a/arch/openrisc/include/asm/bitops/__ffs.h b/arch/openrisc/include/asm/bitops/__ffs.h
new file mode 100644
index 00000000000..6c8368a3405
--- /dev/null
+++ b/arch/openrisc/include/asm/bitops/__ffs.h
@@ -0,0 +1,33 @@
1/*
2 * OpenRISC Linux
3 *
4 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __ASM_OPENRISC___FFS_H
13#define __ASM_OPENRISC___FFS_H
14
15
16#ifdef CONFIG_OPENRISC_HAVE_INST_FF1
17
18static inline unsigned long __ffs(unsigned long x)
19{
20 int ret;
21
22 __asm__ ("l.ff1 %0,%1"
23 : "=r" (ret)
24 : "r" (x));
25
26 return ret-1;
27}
28
29#else
30#include <asm-generic/bitops/__ffs.h>
31#endif
32
33#endif /* __ASM_OPENRISC___FFS_H */
diff --git a/arch/openrisc/include/asm/bitops/__fls.h b/arch/openrisc/include/asm/bitops/__fls.h
new file mode 100644
index 00000000000..c4ecdb4c523
--- /dev/null
+++ b/arch/openrisc/include/asm/bitops/__fls.h
@@ -0,0 +1,33 @@
1/*
2 * OpenRISC Linux
3 *
4 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __ASM_OPENRISC___FLS_H
13#define __ASM_OPENRISC___FLS_H
14
15
16#ifdef CONFIG_OPENRISC_HAVE_INST_FL1
17
18static inline unsigned long __fls(unsigned long x)
19{
20 int ret;
21
22 __asm__ ("l.fl1 %0,%1"
23 : "=r" (ret)
24 : "r" (x));
25
26 return ret-1;
27}
28
29#else
30#include <asm-generic/bitops/__fls.h>
31#endif
32
33#endif /* __ASM_OPENRISC___FLS_H */
diff --git a/arch/openrisc/include/asm/bitops/ffs.h b/arch/openrisc/include/asm/bitops/ffs.h
new file mode 100644
index 00000000000..9de46246ebc
--- /dev/null
+++ b/arch/openrisc/include/asm/bitops/ffs.h
@@ -0,0 +1,32 @@
1/*
2 * OpenRISC Linux
3 *
4 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __ASM_OPENRISC_FFS_H
13#define __ASM_OPENRISC_FFS_H
14
15#ifdef CONFIG_OPENRISC_HAVE_INST_FF1
16
17static inline int ffs(int x)
18{
19 int ret;
20
21 __asm__ ("l.ff1 %0,%1"
22 : "=r" (ret)
23 : "r" (x));
24
25 return ret;
26}
27
28#else
29#include <asm-generic/bitops/ffs.h>
30#endif
31
32#endif /* __ASM_OPENRISC_FFS_H */
diff --git a/arch/openrisc/include/asm/bitops/fls.h b/arch/openrisc/include/asm/bitops/fls.h
new file mode 100644
index 00000000000..9efbf9ad86c
--- /dev/null
+++ b/arch/openrisc/include/asm/bitops/fls.h
@@ -0,0 +1,33 @@
1/*
2 * OpenRISC Linux
3 *
4 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __ASM_OPENRISC_FLS_H
13#define __ASM_OPENRISC_FLS_H
14
15
16#ifdef CONFIG_OPENRISC_HAVE_INST_FL1
17
18static inline int fls(int x)
19{
20 int ret;
21
22 __asm__ ("l.fl1 %0,%1"
23 : "=r" (ret)
24 : "r" (x));
25
26 return ret;
27}
28
29#else
30#include <asm-generic/bitops/fls.h>
31#endif
32
33#endif /* __ASM_OPENRISC_FLS_H */
diff --git a/arch/openrisc/include/asm/byteorder.h b/arch/openrisc/include/asm/byteorder.h
new file mode 100644
index 00000000000..60d14f7e14e
--- /dev/null
+++ b/arch/openrisc/include/asm/byteorder.h
@@ -0,0 +1 @@
#include <linux/byteorder/big_endian.h>
diff --git a/arch/openrisc/include/asm/cache.h b/arch/openrisc/include/asm/cache.h
new file mode 100644
index 00000000000..4ce7a01a252
--- /dev/null
+++ b/arch/openrisc/include/asm/cache.h
@@ -0,0 +1,29 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_CACHE_H
20#define __ASM_OPENRISC_CACHE_H
21
22/* FIXME: How can we replace these with values from the CPU...
23 * they shouldn't be hard-coded!
24 */
25
26#define L1_CACHE_BYTES 16
27#define L1_CACHE_SHIFT 4
28
29#endif /* __ASM_OPENRISC_CACHE_H */
diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
new file mode 100644
index 00000000000..917318b6a97
--- /dev/null
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -0,0 +1,34 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_CPUINFO_H
20#define __ASM_OPENRISC_CPUINFO_H
21
22struct cpuinfo {
23 u32 clock_frequency;
24
25 u32 icache_size;
26 u32 icache_block_size;
27
28 u32 dcache_size;
29 u32 dcache_block_size;
30};
31
32extern struct cpuinfo cpuinfo;
33
34#endif /* __ASM_OPENRISC_CPUINFO_H */
diff --git a/arch/openrisc/include/asm/delay.h b/arch/openrisc/include/asm/delay.h
new file mode 100644
index 00000000000..17f8bf5a5ac
--- /dev/null
+++ b/arch/openrisc/include/asm/delay.h
@@ -0,0 +1,24 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __ASM_OPENRISC_DELAY_H
18#define __ASM_OPENRISC_DELAY_H
19
20#include <asm-generic/delay.h>
21
22extern unsigned long loops_per_jiffy;
23
24#endif
diff --git a/arch/openrisc/include/asm/dma-mapping.h b/arch/openrisc/include/asm/dma-mapping.h
new file mode 100644
index 00000000000..60b47223390
--- /dev/null
+++ b/arch/openrisc/include/asm/dma-mapping.h
@@ -0,0 +1,189 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __ASM_OPENRISC_DMA_MAPPING_H
18#define __ASM_OPENRISC_DMA_MAPPING_H
19
20/*
21 * See Documentation/PCI/PCI-DMA-mapping.txt and
22 * Documentation/DMA-API.txt for documentation.
23 *
24 * This file is written with the intention of eventually moving over
25 * to largely using asm-generic/dma-mapping-common.h in its place.
26 */
27
28#include <linux/dma-debug.h>
29#include <asm-generic/dma-coherent.h>
30#include <linux/kmemcheck.h>
31
32#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
33
34
35#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
36#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
37
38void *or1k_dma_alloc_coherent(struct device *dev, size_t size,
39 dma_addr_t *dma_handle, gfp_t flag);
40void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
41 dma_addr_t dma_handle);
42dma_addr_t or1k_map_page(struct device *dev, struct page *page,
43 unsigned long offset, size_t size,
44 enum dma_data_direction dir,
45 struct dma_attrs *attrs);
46void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
47 size_t size, enum dma_data_direction dir,
48 struct dma_attrs *attrs);
49int or1k_map_sg(struct device *dev, struct scatterlist *sg,
50 int nents, enum dma_data_direction dir,
51 struct dma_attrs *attrs);
52void or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
53 int nents, enum dma_data_direction dir,
54 struct dma_attrs *attrs);
55void or1k_sync_single_for_cpu(struct device *dev,
56 dma_addr_t dma_handle, size_t size,
57 enum dma_data_direction dir);
58void or1k_sync_single_for_device(struct device *dev,
59 dma_addr_t dma_handle, size_t size,
60 enum dma_data_direction dir);
61
62static inline void *dma_alloc_coherent(struct device *dev, size_t size,
63 dma_addr_t *dma_handle, gfp_t flag)
64{
65 void *memory;
66
67 memory = or1k_dma_alloc_coherent(dev, size, dma_handle, flag);
68
69 debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
70 return memory;
71}
72
73static inline void dma_free_coherent(struct device *dev, size_t size,
74 void *cpu_addr, dma_addr_t dma_handle)
75{
76 debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
77 or1k_dma_free_coherent(dev, size, cpu_addr, dma_handle);
78}
79
80static inline dma_addr_t dma_map_single(struct device *dev, void *ptr,
81 size_t size,
82 enum dma_data_direction dir)
83{
84 dma_addr_t addr;
85
86 kmemcheck_mark_initialized(ptr, size);
87 BUG_ON(!valid_dma_direction(dir));
88 addr = or1k_map_page(dev, virt_to_page(ptr),
89 (unsigned long)ptr & ~PAGE_MASK, size,
90 dir, NULL);
91 debug_dma_map_page(dev, virt_to_page(ptr),
92 (unsigned long)ptr & ~PAGE_MASK, size,
93 dir, addr, true);
94 return addr;
95}
96
97static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
98 size_t size,
99 enum dma_data_direction dir)
100{
101 BUG_ON(!valid_dma_direction(dir));
102 or1k_unmap_page(dev, addr, size, dir, NULL);
103 debug_dma_unmap_page(dev, addr, size, dir, true);
104}
105
106static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
107 int nents, enum dma_data_direction dir)
108{
109 int i, ents;
110 struct scatterlist *s;
111
112 for_each_sg(sg, s, nents, i)
113 kmemcheck_mark_initialized(sg_virt(s), s->length);
114 BUG_ON(!valid_dma_direction(dir));
115 ents = or1k_map_sg(dev, sg, nents, dir, NULL);
116 debug_dma_map_sg(dev, sg, nents, ents, dir);
117
118 return ents;
119}
120
121static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
122 int nents, enum dma_data_direction dir)
123{
124 BUG_ON(!valid_dma_direction(dir));
125 debug_dma_unmap_sg(dev, sg, nents, dir);
126 or1k_unmap_sg(dev, sg, nents, dir, NULL);
127}
128
129static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
130 size_t offset, size_t size,
131 enum dma_data_direction dir)
132{
133 dma_addr_t addr;
134
135 kmemcheck_mark_initialized(page_address(page) + offset, size);
136 BUG_ON(!valid_dma_direction(dir));
137 addr = or1k_map_page(dev, page, offset, size, dir, NULL);
138 debug_dma_map_page(dev, page, offset, size, dir, addr, false);
139
140 return addr;
141}
142
143static inline void dma_unmap_page(struct device *dev, dma_addr_t addr,
144 size_t size, enum dma_data_direction dir)
145{
146 BUG_ON(!valid_dma_direction(dir));
147 or1k_unmap_page(dev, addr, size, dir, NULL);
148 debug_dma_unmap_page(dev, addr, size, dir, true);
149}
150
151static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
152 size_t size,
153 enum dma_data_direction dir)
154{
155 BUG_ON(!valid_dma_direction(dir));
156 or1k_sync_single_for_cpu(dev, addr, size, dir);
157 debug_dma_sync_single_for_cpu(dev, addr, size, dir);
158}
159
160static inline void dma_sync_single_for_device(struct device *dev,
161 dma_addr_t addr, size_t size,
162 enum dma_data_direction dir)
163{
164 BUG_ON(!valid_dma_direction(dir));
165 or1k_sync_single_for_device(dev, addr, size, dir);
166 debug_dma_sync_single_for_device(dev, addr, size, dir);
167}
168
169static inline int dma_supported(struct device *dev, u64 dma_mask)
170{
171 /* Support 32 bit DMA mask exclusively */
172 return dma_mask == DMA_BIT_MASK(32);
173}
174
175static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
176{
177 return 0;
178}
179
180static inline int dma_set_mask(struct device *dev, u64 dma_mask)
181{
182 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
183 return -EIO;
184
185 *dev->dma_mask = dma_mask;
186
187 return 0;
188}
189#endif /* __ASM_OPENRISC_DMA_MAPPING_H */
diff --git a/arch/openrisc/include/asm/elf.h b/arch/openrisc/include/asm/elf.h
new file mode 100644
index 00000000000..2ce603bbfdd
--- /dev/null
+++ b/arch/openrisc/include/asm/elf.h
@@ -0,0 +1,108 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_ELF_H
20#define __ASM_OPENRISC_ELF_H
21
22/*
23 * ELF register definitions..
24 */
25#include <linux/types.h>
26#include <linux/ptrace.h>
27
28
29/* The OR1K relocation types... not all relevant for module loader */
30#define R_OR32_NONE 0
31#define R_OR32_32 1
32#define R_OR32_16 2
33#define R_OR32_8 3
34#define R_OR32_CONST 4
35#define R_OR32_CONSTH 5
36#define R_OR32_JUMPTARG 6
37#define R_OR32_VTINHERIT 7
38#define R_OR32_VTENTRY 8
39
40typedef unsigned long elf_greg_t;
41
42/*
43 * Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is
44 * thus exposed to user-space.
45 */
46#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
47typedef elf_greg_t elf_gregset_t[ELF_NGREG];
48
49/* A placeholder; OR32 does not have fp support yes, so no fp regs for now. */
50typedef unsigned long elf_fpregset_t;
51
52/* This should be moved to include/linux/elf.h */
53#define EM_OR32 0x8472
54#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
55
56/*
57 * These are used to set parameters in the core dumps.
58 */
59#define ELF_ARCH EM_OR32
60#define ELF_CLASS ELFCLASS32
61#define ELF_DATA ELFDATA2MSB
62
63#ifdef __KERNEL__
64
65/*
66 * This is used to ensure we don't load something for the wrong architecture.
67 */
68
69#define elf_check_arch(x) \
70 (((x)->e_machine == EM_OR32) || ((x)->e_machine == EM_OPENRISC))
71
72/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
73 use of this is to invoke "./ld.so someprog" to test out a new version of
74 the loader. We need to make sure that it is out of the way of the program
75 that it will "exec", and that there is sufficient room for the brk. */
76
77#define ELF_ET_DYN_BASE (0x08000000)
78
79/*
80 * Enable dump using regset.
81 * This covers all of general/DSP/FPU regs.
82 */
83#define CORE_DUMP_USE_REGSET
84
85#define ELF_EXEC_PAGESIZE 8192
86
87extern void dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt);
88#define ELF_CORE_COPY_REGS(dest, regs) dump_elf_thread(dest, regs);
89
90/* This yields a mask that user programs can use to figure out what
91 instruction set this cpu supports. This could be done in userspace,
92 but it's not easy, and we've already done it here. */
93
94#define ELF_HWCAP (0)
95
96/* This yields a string that ld.so will use to load implementation
97 specific libraries for optimization. This is more specific in
98 intent than poking at uname or /proc/cpuinfo.
99
100 For the moment, we have only optimizations for the Intel generations,
101 but that could change... */
102
103#define ELF_PLATFORM (NULL)
104
105#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
106
107#endif /* __KERNEL__ */
108#endif
diff --git a/arch/openrisc/include/asm/fixmap.h b/arch/openrisc/include/asm/fixmap.h
new file mode 100644
index 00000000000..52733416c1f
--- /dev/null
+++ b/arch/openrisc/include/asm/fixmap.h
@@ -0,0 +1,87 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_FIXMAP_H
20#define __ASM_OPENRISC_FIXMAP_H
21
22/* Why exactly do we need 2 empty pages between the top of the fixed
23 * addresses and the top of virtual memory? Something is using that
24 * memory space but not sure what right now... If you find it, leave
25 * a comment here.
26 */
27#define FIXADDR_TOP ((unsigned long) (-2*PAGE_SIZE))
28
29#include <linux/kernel.h>
30#include <asm/page.h>
31
32/*
33 * On OpenRISC we use these special fixed_addresses for doing ioremap
34 * early in the boot process before memory initialization is complete.
35 * This is used, in particular, by the early serial console code.
36 *
37 * It's not really 'fixmap', per se, but fits loosely into the same
38 * paradigm.
39 */
40enum fixed_addresses {
41 /*
42 * FIX_IOREMAP entries are useful for mapping physical address
43 * space before ioremap() is useable, e.g. really early in boot
44 * before kmalloc() is working.
45 */
46#define FIX_N_IOREMAPS 32
47 FIX_IOREMAP_BEGIN,
48 FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS - 1,
49 __end_of_fixed_addresses
50};
51
52#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
53/* FIXADDR_BOTTOM might be a better name here... */
54#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
55
56#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
57#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
58
59/*
60 * 'index to address' translation. If anyone tries to use the idx
61 * directly without tranlation, we catch the bug with a NULL-deference
62 * kernel oops. Illegal ranges of incoming indices are caught too.
63 */
64static __always_inline unsigned long fix_to_virt(const unsigned int idx)
65{
66 /*
67 * this branch gets completely eliminated after inlining,
68 * except when someone tries to use fixaddr indices in an
69 * illegal way. (such as mixing up address types or using
70 * out-of-range indices).
71 *
72 * If it doesn't get removed, the linker will complain
73 * loudly with a reasonably clear error message..
74 */
75 if (idx >= __end_of_fixed_addresses)
76 BUG();
77
78 return __fix_to_virt(idx);
79}
80
81static inline unsigned long virt_to_fix(const unsigned long vaddr)
82{
83 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
84 return __virt_to_fix(vaddr);
85}
86
87#endif
diff --git a/arch/openrisc/include/asm/gpio.h b/arch/openrisc/include/asm/gpio.h
new file mode 100644
index 00000000000..0b0d174f47c
--- /dev/null
+++ b/arch/openrisc/include/asm/gpio.h
@@ -0,0 +1,65 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_GPIO_H
20#define __ASM_OPENRISC_GPIO_H
21
22#include <linux/errno.h>
23#include <asm-generic/gpio.h>
24
25#ifdef CONFIG_GPIOLIB
26
27/*
28 * OpenRISC (or1k) does not have on-chip GPIO's so there is not really
29 * any standardized implementation that makes sense here. If passing
30 * through gpiolib becomes a bottleneck then it may make sense, on a
31 * case-by-case basis, to implement these inlined/rapid versions.
32 *
33 * Just call gpiolib.
34 */
35static inline int gpio_get_value(unsigned int gpio)
36{
37 return __gpio_get_value(gpio);
38}
39
40static inline void gpio_set_value(unsigned int gpio, int value)
41{
42 __gpio_set_value(gpio, value);
43}
44
45static inline int gpio_cansleep(unsigned int gpio)
46{
47 return __gpio_cansleep(gpio);
48}
49
50/*
51 * Not implemented, yet.
52 */
53static inline int gpio_to_irq(unsigned int gpio)
54{
55 return -ENOSYS;
56}
57
58static inline int irq_to_gpio(unsigned int irq)
59{
60 return -EINVAL;
61}
62
63#endif /* CONFIG_GPIOLIB */
64
65#endif /* __ASM_OPENRISC_GPIO_H */
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
new file mode 100644
index 00000000000..07f5299d6c2
--- /dev/null
+++ b/arch/openrisc/include/asm/io.h
@@ -0,0 +1,51 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 * et al.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18#ifndef __ASM_OPENRISC_IO_H
19#define __ASM_OPENRISC_IO_H
20
21/*
22 * PCI: can we really do 0 here if we have no port IO?
23 */
24#define IO_SPACE_LIMIT 0
25
26/* OpenRISC has no port IO */
27#define HAVE_ARCH_PIO_SIZE 1
28#define PIO_RESERVED 0X0UL
29#define PIO_OFFSET 0
30#define PIO_MASK 0
31
32#include <asm-generic/io.h>
33
34extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size,
35 pgprot_t prot);
36
37static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
38{
39 return __ioremap(offset, size, PAGE_KERNEL);
40}
41
42/* #define _PAGE_CI 0x002 */
43static inline void __iomem *ioremap_nocache(phys_addr_t offset,
44 unsigned long size)
45{
46 return __ioremap(offset, size,
47 __pgprot(pgprot_val(PAGE_KERNEL) | _PAGE_CI));
48}
49
50extern void iounmap(void *addr);
51#endif
diff --git a/arch/openrisc/include/asm/irq.h b/arch/openrisc/include/asm/irq.h
new file mode 100644
index 00000000000..eb612b1865d
--- /dev/null
+++ b/arch/openrisc/include/asm/irq.h
@@ -0,0 +1,27 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_IRQ_H__
20#define __ASM_OPENRISC_IRQ_H__
21
22#define NR_IRQS 32
23#include <asm-generic/irq.h>
24
25#define NO_IRQ (-1)
26
27#endif /* __ASM_OPENRISC_IRQ_H__ */
diff --git a/arch/openrisc/include/asm/irqflags.h b/arch/openrisc/include/asm/irqflags.h
new file mode 100644
index 00000000000..dc86c653d70
--- /dev/null
+++ b/arch/openrisc/include/asm/irqflags.h
@@ -0,0 +1,29 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef ___ASM_OPENRISC_IRQFLAGS_H
20#define ___ASM_OPENRISC_IRQFLAGS_H
21
22#include <asm/spr_defs.h>
23
24#define ARCH_IRQ_DISABLED 0x00
25#define ARCH_IRQ_ENABLED (SPR_SR_IEE|SPR_SR_TEE)
26
27#include <asm-generic/irqflags.h>
28
29#endif /* ___ASM_OPENRISC_IRQFLAGS_H */
diff --git a/arch/openrisc/include/asm/linkage.h b/arch/openrisc/include/asm/linkage.h
new file mode 100644
index 00000000000..e2638752091
--- /dev/null
+++ b/arch/openrisc/include/asm/linkage.h
@@ -0,0 +1,25 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_LINKAGE_H
20#define __ASM_OPENRISC_LINKAGE_H
21
22#define __ALIGN .align 0
23#define __ALIGN_STR ".align 0"
24
25#endif /* __ASM_OPENRISC_LINKAGE_H */
diff --git a/arch/openrisc/include/asm/memblock.h b/arch/openrisc/include/asm/memblock.h
new file mode 100644
index 00000000000..bbe5a1c788c
--- /dev/null
+++ b/arch/openrisc/include/asm/memblock.h
@@ -0,0 +1,24 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_MEMBLOCK_H
20#define __ASM_OPENRISC_MEMBLOCK_H
21
22/* empty */
23
24#endif /* __ASM_OPENRISC_MEMBLOCK_H */
diff --git a/arch/openrisc/include/asm/mmu.h b/arch/openrisc/include/asm/mmu.h
new file mode 100644
index 00000000000..d069bc2ddfa
--- /dev/null
+++ b/arch/openrisc/include/asm/mmu.h
@@ -0,0 +1,26 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_MMU_H
20#define __ASM_OPENRISC_MMU_H
21
22#ifndef __ASSEMBLY__
23typedef unsigned long mm_context_t;
24#endif
25
26#endif
diff --git a/arch/openrisc/include/asm/mmu_context.h b/arch/openrisc/include/asm/mmu_context.h
new file mode 100644
index 00000000000..e94b814d2e3
--- /dev/null
+++ b/arch/openrisc/include/asm/mmu_context.h
@@ -0,0 +1,43 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_MMU_CONTEXT_H
20#define __ASM_OPENRISC_MMU_CONTEXT_H
21
22#include <asm-generic/mm_hooks.h>
23
24extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
25extern void destroy_context(struct mm_struct *mm);
26extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
27 struct task_struct *tsk);
28
29#define deactivate_mm(tsk, mm) do { } while (0)
30
31#define activate_mm(prev, next) switch_mm((prev), (next), NULL)
32
33/* current active pgd - this is similar to other processors pgd
34 * registers like cr3 on the i386
35 */
36
37extern volatile pgd_t *current_pgd; /* defined in arch/openrisc/mm/fault.c */
38
39static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
40{
41}
42
43#endif
diff --git a/arch/openrisc/include/asm/mutex.h b/arch/openrisc/include/asm/mutex.h
new file mode 100644
index 00000000000..b85a0cfa9fc
--- /dev/null
+++ b/arch/openrisc/include/asm/mutex.h
@@ -0,0 +1,27 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19/*
20 * Pull in the generic implementation for the mutex fastpath.
21 *
22 * TODO: implement optimized primitives instead, or leave the generic
23 * implementation in place, or pick the atomic_xchg() based generic
24 * implementation. (see asm-generic/mutex-xchg.h for details)
25 */
26
27#include <asm-generic/mutex-dec.h>
diff --git a/arch/openrisc/include/asm/page.h b/arch/openrisc/include/asm/page.h
new file mode 100644
index 00000000000..b041b344b22
--- /dev/null
+++ b/arch/openrisc/include/asm/page.h
@@ -0,0 +1,110 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_PAGE_H
20#define __ASM_OPENRISC_PAGE_H
21
22
23/* PAGE_SHIFT determines the page size */
24
25#define PAGE_SHIFT 13
26#ifdef __ASSEMBLY__
27#define PAGE_SIZE (1 << PAGE_SHIFT)
28#else
29#define PAGE_SIZE (1UL << PAGE_SHIFT)
30#endif
31#define PAGE_MASK (~(PAGE_SIZE-1))
32
33#define PAGE_OFFSET 0xc0000000
34#define KERNELBASE PAGE_OFFSET
35
36/* This is not necessarily the right place for this, but it's needed by
37 * drivers/of/fdt.c
38 */
39#include <asm/setup.h>
40
41#ifndef __ASSEMBLY__
42
43#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
44#define free_user_page(page, addr) free_page(addr)
45
46#define clear_page(page) memset((page), 0, PAGE_SIZE)
47#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE)
48
49#define clear_user_page(page, vaddr, pg) clear_page(page)
50#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
51
52/*
53 * These are used to make use of C type-checking..
54 */
55typedef struct {
56 unsigned long pte;
57} pte_t;
58typedef struct {
59 unsigned long pgd;
60} pgd_t;
61typedef struct {
62 unsigned long pgprot;
63} pgprot_t;
64typedef struct page *pgtable_t;
65
66#define pte_val(x) ((x).pte)
67#define pgd_val(x) ((x).pgd)
68#define pgprot_val(x) ((x).pgprot)
69
70#define __pte(x) ((pte_t) { (x) })
71#define __pgd(x) ((pgd_t) { (x) })
72#define __pgprot(x) ((pgprot_t) { (x) })
73
74extern unsigned long memory_start;
75extern unsigned long memory_end;
76
77#endif /* !__ASSEMBLY__ */
78
79
80#ifndef __ASSEMBLY__
81
82#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
83#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
84
85#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
86#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
87
88#define virt_to_page(addr) \
89 (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
90#define page_to_virt(page) \
91 ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
92
93#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
94
95#define pfn_valid(pfn) ((pfn) < max_mapnr)
96
97#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
98 ((void *)(kaddr) < (void *)memory_end))
99
100#endif /* __ASSEMBLY__ */
101
102
103#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
104 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
105
106
107#include <asm-generic/memory_model.h>
108#include <asm-generic/getorder.h>
109
110#endif /* __ASM_OPENRISC_PAGE_H */
diff --git a/arch/openrisc/include/asm/param.h b/arch/openrisc/include/asm/param.h
new file mode 100644
index 00000000000..c39a336610e
--- /dev/null
+++ b/arch/openrisc/include/asm/param.h
@@ -0,0 +1,26 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_PARAM_H
20#define __ASM_OPENRISC_PARAM_H
21
22#define EXEC_PAGESIZE 8192
23
24#include <asm-generic/param.h>
25
26#endif /* __ASM_OPENRISC_PARAM_H */
diff --git a/arch/openrisc/include/asm/pgalloc.h b/arch/openrisc/include/asm/pgalloc.h
new file mode 100644
index 00000000000..05c39ecd2ef
--- /dev/null
+++ b/arch/openrisc/include/asm/pgalloc.h
@@ -0,0 +1,102 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_PGALLOC_H
20#define __ASM_OPENRISC_PGALLOC_H
21
22#include <asm/page.h>
23#include <linux/threads.h>
24#include <linux/mm.h>
25#include <linux/memblock.h>
26#include <linux/bootmem.h>
27
28extern int mem_init_done;
29
30#define pmd_populate_kernel(mm, pmd, pte) \
31 set_pmd(pmd, __pmd(_KERNPG_TABLE + __pa(pte)))
32
33static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
34 struct page *pte)
35{
36 set_pmd(pmd, __pmd(_KERNPG_TABLE +
37 ((unsigned long)page_to_pfn(pte) <<
38 (unsigned long) PAGE_SHIFT)));
39}
40
41/*
42 * Allocate and free page tables.
43 */
44static inline pgd_t *pgd_alloc(struct mm_struct *mm)
45{
46 pgd_t *ret = (pgd_t *)__get_free_page(GFP_KERNEL);
47
48 if (ret) {
49 memset(ret, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
50 memcpy(ret + USER_PTRS_PER_PGD,
51 swapper_pg_dir + USER_PTRS_PER_PGD,
52 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
53
54 }
55 return ret;
56}
57
58#if 0
59/* FIXME: This seems to be the preferred style, but we are using
60 * current_pgd (from mm->pgd) to load kernel pages so we need it
61 * initialized. This needs to be looked into.
62 */
63extern inline pgd_t *pgd_alloc(struct mm_struct *mm)
64{
65 return (pgd_t *)get_zeroed_page(GFP_KERNEL);
66}
67#endif
68
69static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
70{
71 free_page((unsigned long)pgd);
72}
73
74extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address);
75
76static inline struct page *pte_alloc_one(struct mm_struct *mm,
77 unsigned long address)
78{
79 struct page *pte;
80 pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0);
81 if (pte)
82 clear_page(page_address(pte));
83 return pte;
84}
85
86static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
87{
88 free_page((unsigned long)pte);
89}
90
91static inline void pte_free(struct mm_struct *mm, struct page *pte)
92{
93 __free_page(pte);
94}
95
96
97#define __pte_free_tlb(tlb, pte, addr) tlb_remove_page((tlb), (pte))
98#define pmd_pgtable(pmd) pmd_page(pmd)
99
100#define check_pgt_cache() do { } while (0)
101
102#endif
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
new file mode 100644
index 00000000000..043505d7f68
--- /dev/null
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -0,0 +1,463 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19/* or32 pgtable.h - macros and functions to manipulate page tables
20 *
21 * Based on:
22 * include/asm-cris/pgtable.h
23 */
24
25#ifndef __ASM_OPENRISC_PGTABLE_H
26#define __ASM_OPENRISC_PGTABLE_H
27
28#include <asm-generic/pgtable-nopmd.h>
29
30#ifndef __ASSEMBLY__
31#include <asm/mmu.h>
32#include <asm/fixmap.h>
33
34/*
35 * The Linux memory management assumes a three-level page table setup. On
36 * or32, we use that, but "fold" the mid level into the top-level page
37 * table. Since the MMU TLB is software loaded through an interrupt, it
38 * supports any page table structure, so we could have used a three-level
39 * setup, but for the amounts of memory we normally use, a two-level is
40 * probably more efficient.
41 *
42 * This file contains the functions and defines necessary to modify and use
43 * the or32 page table tree.
44 */
45
46extern void paging_init(void);
47
48/* Certain architectures need to do special things when pte's
49 * within a page table are directly modified. Thus, the following
50 * hook is made available.
51 */
52#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
53#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
54/*
55 * (pmds are folded into pgds so this doesn't get actually called,
56 * but the define is needed for a generic inline function.)
57 */
58#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
59
60#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
61#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
62#define PGDIR_MASK (~(PGDIR_SIZE-1))
63
64/*
65 * entries per page directory level: we use a two-level, so
66 * we don't really have any PMD directory physically.
67 * pointers are 4 bytes so we can use the page size and
68 * divide it by 4 (shift by 2).
69 */
70#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
71
72#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
73
74/* calculate how many PGD entries a user-level program can use
75 * the first mappable virtual address is 0
76 * (TASK_SIZE is the maximum virtual address space)
77 */
78
79#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
80#define FIRST_USER_ADDRESS 0
81
82/*
83 * Kernels own virtual memory area.
84 */
85
86/*
87 * The size and location of the vmalloc area are chosen so that modules
88 * placed in this area aren't more than a 28-bit signed offset from any
89 * kernel functions that they may need. This greatly simplifies handling
90 * of the relocations for l.j and l.jal instructions as we don't need to
91 * introduce any trampolines for reaching "distant" code.
92 *
93 * 64 MB of vmalloc area is comparable to what's available on other arches.
94 */
95
96#define VMALLOC_START (PAGE_OFFSET-0x04000000)
97#define VMALLOC_END (PAGE_OFFSET)
98#define VMALLOC_VMADDR(x) ((unsigned long)(x))
99
100/* Define some higher level generic page attributes.
101 *
102 * If you change _PAGE_CI definition be sure to change it in
103 * io.h for ioremap_nocache() too.
104 */
105
106/*
107 * An OR32 PTE looks like this:
108 *
109 * | 31 ... 10 | 9 | 8 ... 6 | 5 | 4 | 3 | 2 | 1 | 0 |
110 * Phys pg.num L PP Index D A WOM WBC CI CC
111 *
112 * L : link
113 * PPI: Page protection index
114 * D : Dirty
115 * A : Accessed
116 * WOM: Weakly ordered memory
117 * WBC: Write-back cache
118 * CI : Cache inhibit
119 * CC : Cache coherent
120 *
121 * The protection bits below should correspond to the layout of the actual
122 * PTE as per above
123 */
124
125#define _PAGE_CC 0x001 /* software: pte contains a translation */
126#define _PAGE_CI 0x002 /* cache inhibit */
127#define _PAGE_WBC 0x004 /* write back cache */
128#define _PAGE_FILE 0x004 /* set: pagecache, unset: swap (when !PRESENT) */
129#define _PAGE_WOM 0x008 /* weakly ordered memory */
130
131#define _PAGE_A 0x010 /* accessed */
132#define _PAGE_D 0x020 /* dirty */
133#define _PAGE_URE 0x040 /* user read enable */
134#define _PAGE_UWE 0x080 /* user write enable */
135
136#define _PAGE_SRE 0x100 /* superuser read enable */
137#define _PAGE_SWE 0x200 /* superuser write enable */
138#define _PAGE_EXEC 0x400 /* software: page is executable */
139#define _PAGE_U_SHARED 0x800 /* software: page is shared in user space */
140
141/* 0x001 is cache coherency bit, which should always be set to
142 * 1 - for SMP (when we support it)
143 * 0 - otherwise
144 *
145 * we just reuse this bit in software for _PAGE_PRESENT and
146 * force it to 0 when loading it into TLB.
147 */
148#define _PAGE_PRESENT _PAGE_CC
149#define _PAGE_USER _PAGE_URE
150#define _PAGE_WRITE (_PAGE_UWE | _PAGE_SWE)
151#define _PAGE_DIRTY _PAGE_D
152#define _PAGE_ACCESSED _PAGE_A
153#define _PAGE_NO_CACHE _PAGE_CI
154#define _PAGE_SHARED _PAGE_U_SHARED
155#define _PAGE_READ (_PAGE_URE | _PAGE_SRE)
156
157#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
158#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
159#define _PAGE_ALL (_PAGE_PRESENT | _PAGE_ACCESSED)
160#define _KERNPG_TABLE \
161 (_PAGE_BASE | _PAGE_SRE | _PAGE_SWE | _PAGE_ACCESSED | _PAGE_DIRTY)
162
163#define PAGE_NONE __pgprot(_PAGE_ALL)
164#define PAGE_READONLY __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
165#define PAGE_READONLY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
166#define PAGE_SHARED \
167 __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
168 | _PAGE_SHARED)
169#define PAGE_SHARED_X \
170 __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
171 | _PAGE_SHARED | _PAGE_EXEC)
172#define PAGE_COPY __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
173#define PAGE_COPY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
174
175#define PAGE_KERNEL \
176 __pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
177 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
178#define PAGE_KERNEL_RO \
179 __pgprot(_PAGE_ALL | _PAGE_SRE \
180 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
181#define PAGE_KERNEL_NOCACHE \
182 __pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
183 | _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC | _PAGE_CI)
184
185#define __P000 PAGE_NONE
186#define __P001 PAGE_READONLY_X
187#define __P010 PAGE_COPY
188#define __P011 PAGE_COPY_X
189#define __P100 PAGE_READONLY
190#define __P101 PAGE_READONLY_X
191#define __P110 PAGE_COPY
192#define __P111 PAGE_COPY_X
193
194#define __S000 PAGE_NONE
195#define __S001 PAGE_READONLY_X
196#define __S010 PAGE_SHARED
197#define __S011 PAGE_SHARED_X
198#define __S100 PAGE_READONLY
199#define __S101 PAGE_READONLY_X
200#define __S110 PAGE_SHARED
201#define __S111 PAGE_SHARED_X
202
203/* zero page used for uninitialized stuff */
204extern unsigned long empty_zero_page[2048];
205#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
206
207/* number of bits that fit into a memory pointer */
208#define BITS_PER_PTR (8*sizeof(unsigned long))
209
210/* to align the pointer to a pointer address */
211#define PTR_MASK (~(sizeof(void *)-1))
212
213/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
214/* 64-bit machines, beware! SRB. */
215#define SIZEOF_PTR_LOG2 2
216
217/* to find an entry in a page-table */
218#define PAGE_PTR(address) \
219((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
220
221/* to set the page-dir */
222#define SET_PAGE_DIR(tsk, pgdir)
223
224#define pte_none(x) (!pte_val(x))
225#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
226#define pte_clear(mm, addr, xp) do { pte_val(*(xp)) = 0; } while (0)
227
228#define pmd_none(x) (!pmd_val(x))
229#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK)) != _KERNPG_TABLE)
230#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
231#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
232
233/*
234 * The following only work if pte_present() is true.
235 * Undefined behaviour if not..
236 */
237
238static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
239static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
240static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
241static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
242static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
243static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
244static inline int pte_special(pte_t pte) { return 0; }
245static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
246
247static inline pte_t pte_wrprotect(pte_t pte)
248{
249 pte_val(pte) &= ~(_PAGE_WRITE);
250 return pte;
251}
252
253static inline pte_t pte_rdprotect(pte_t pte)
254{
255 pte_val(pte) &= ~(_PAGE_READ);
256 return pte;
257}
258
259static inline pte_t pte_exprotect(pte_t pte)
260{
261 pte_val(pte) &= ~(_PAGE_EXEC);
262 return pte;
263}
264
265static inline pte_t pte_mkclean(pte_t pte)
266{
267 pte_val(pte) &= ~(_PAGE_DIRTY);
268 return pte;
269}
270
271static inline pte_t pte_mkold(pte_t pte)
272{
273 pte_val(pte) &= ~(_PAGE_ACCESSED);
274 return pte;
275}
276
277static inline pte_t pte_mkwrite(pte_t pte)
278{
279 pte_val(pte) |= _PAGE_WRITE;
280 return pte;
281}
282
283static inline pte_t pte_mkread(pte_t pte)
284{
285 pte_val(pte) |= _PAGE_READ;
286 return pte;
287}
288
289static inline pte_t pte_mkexec(pte_t pte)
290{
291 pte_val(pte) |= _PAGE_EXEC;
292 return pte;
293}
294
295static inline pte_t pte_mkdirty(pte_t pte)
296{
297 pte_val(pte) |= _PAGE_DIRTY;
298 return pte;
299}
300
301static inline pte_t pte_mkyoung(pte_t pte)
302{
303 pte_val(pte) |= _PAGE_ACCESSED;
304 return pte;
305}
306
307/*
308 * Conversion functions: convert a page and protection to a page entry,
309 * and a page entry and page directory to the page they refer to.
310 */
311
312/* What actually goes as arguments to the various functions is less than
313 * obvious, but a rule of thumb is that struct page's goes as struct page *,
314 * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
315 * addresses (the 0xc0xxxxxx's) goes as void *'s.
316 */
317
318static inline pte_t __mk_pte(void *page, pgprot_t pgprot)
319{
320 pte_t pte;
321 /* the PTE needs a physical address */
322 pte_val(pte) = __pa(page) | pgprot_val(pgprot);
323 return pte;
324}
325
326#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
327
328#define mk_pte_phys(physpage, pgprot) \
329({ \
330 pte_t __pte; \
331 \
332 pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
333 __pte; \
334})
335
336static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
337{
338 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
339 return pte;
340}
341
342
343/*
344 * pte_val refers to a page in the 0x0xxxxxxx physical DRAM interval
345 * __pte_page(pte_val) refers to the "virtual" DRAM interval
346 * pte_pagenr refers to the page-number counted starting from the virtual
347 * DRAM start
348 */
349
350static inline unsigned long __pte_page(pte_t pte)
351{
352 /* the PTE contains a physical address */
353 return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
354}
355
356#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
357
358/* permanent address of a page */
359
360#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
361#define pte_page(pte) (mem_map+pte_pagenr(pte))
362
363/*
364 * only the pte's themselves need to point to physical DRAM (see above)
365 * the pagetable links are purely handled within the kernel SW and thus
366 * don't need the __pa and __va transformations.
367 */
368static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
369{
370 pmd_val(*pmdp) = _KERNPG_TABLE | (unsigned long) ptep;
371}
372
373#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
374#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
375
376/* to find an entry in a page-table-directory. */
377#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
378
379#define __pgd_offset(address) pgd_index(address)
380
381#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
382
383/* to find an entry in a kernel page-table-directory */
384#define pgd_offset_k(address) pgd_offset(&init_mm, address)
385
386#define __pmd_offset(address) \
387 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
388
389/*
390 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
391 *
392 * this macro returns the index of the entry in the pte page which would
393 * control the given virtual address
394 */
395#define __pte_offset(address) \
396 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
397#define pte_offset_kernel(dir, address) \
398 ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address))
399#define pte_offset_map(dir, address) \
400 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
401#define pte_offset_map_nested(dir, address) \
402 pte_offset_map(dir, address)
403
404#define pte_unmap(pte) do { } while (0)
405#define pte_unmap_nested(pte) do { } while (0)
406#define pte_pfn(x) ((unsigned long)(((x).pte)) >> PAGE_SHIFT)
407#define pfn_pte(pfn, prot) __pte((((pfn) << PAGE_SHIFT)) | pgprot_val(prot))
408
409#define pte_ERROR(e) \
410 printk(KERN_ERR "%s:%d: bad pte %p(%08lx).\n", \
411 __FILE__, __LINE__, &(e), pte_val(e))
412#define pgd_ERROR(e) \
413 printk(KERN_ERR "%s:%d: bad pgd %p(%08lx).\n", \
414 __FILE__, __LINE__, &(e), pgd_val(e))
415
416extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
417
418/*
419 * or32 doesn't have any external MMU info: the kernel page
420 * tables contain all the necessary information.
421 *
422 * Actually I am not sure on what this could be used for.
423 */
424static inline void update_mmu_cache(struct vm_area_struct *vma,
425 unsigned long address, pte_t *pte)
426{
427}
428
429/* __PHX__ FIXME, SWAP, this probably doesn't work */
430
431/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
432/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
433
434#define __swp_type(x) (((x).val >> 5) & 0x7f)
435#define __swp_offset(x) ((x).val >> 12)
436#define __swp_entry(type, offset) \
437 ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
438#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
439#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
440
441/* Encode and decode a nonlinear file mapping entry */
442
443#define PTE_FILE_MAX_BITS 26
444#define pte_to_pgoff(x) (pte_val(x) >> 6)
445#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE)
446
447#define kern_addr_valid(addr) (1)
448
449#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
450 remap_pfn_range(vma, vaddr, pfn, size, prot)
451
452#include <asm-generic/pgtable.h>
453
454/*
455 * No page table caches to initialise
456 */
457#define pgtable_cache_init() do { } while (0)
458#define io_remap_page_range remap_page_range
459
460typedef pte_t *pte_addr_t;
461
462#endif /* __ASSEMBLY__ */
463#endif /* __ASM_OPENRISC_PGTABLE_H */
diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h
new file mode 100644
index 00000000000..bb54c97b978
--- /dev/null
+++ b/arch/openrisc/include/asm/processor.h
@@ -0,0 +1,113 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_PROCESSOR_H
20#define __ASM_OPENRISC_PROCESSOR_H
21
22#include <asm/spr_defs.h>
23#include <asm/page.h>
24#include <asm/ptrace.h>
25
26#define STACK_TOP TASK_SIZE
27#define STACK_TOP_MAX STACK_TOP
28/* Kernel and user SR register setting */
29#define KERNEL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_ICE \
30 | SPR_SR_DCE | SPR_SR_SM)
31#define USER_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_ICE \
32 | SPR_SR_DCE | SPR_SR_IEE | SPR_SR_TEE)
33/*
34 * Default implementation of macro that returns current
35 * instruction pointer ("program counter").
36 */
37#define current_text_addr() ({ __label__ _l; _l: &&_l; })
38
39/*
40 * User space process size. This is hardcoded into a few places,
41 * so don't change it unless you know what you are doing.
42 */
43
44#define TASK_SIZE (0x80000000UL)
45
46/* This decides where the kernel will search for a free chunk of vm
47 * space during mmap's.
48 */
49#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
50
51#ifndef __ASSEMBLY__
52
53struct task_struct;
54
55struct thread_struct {
56};
57
58/*
59 * At user->kernel entry, the pt_regs struct is stacked on the top of the
60 * kernel-stack. This macro allows us to find those regs for a task.
61 * Notice that subsequent pt_regs stackings, like recursive interrupts
62 * occurring while we're in the kernel, won't affect this - only the first
63 * user->kernel transition registers are reached by this (i.e. not regs
64 * for running signal handler)
65 */
66#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE - STACK_FRAME_OVERHEAD)) - 1)
67
68/*
69 * Dito but for the currently running task
70 */
71
72#define task_pt_regs(task) user_regs(task_thread_info(task))
73#define current_regs() user_regs(current_thread_info())
74
75extern inline void prepare_to_copy(struct task_struct *tsk)
76{
77}
78
79#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
80
81#define INIT_THREAD { }
82
83
84#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc);
85#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp);
86
87
88extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
89
90void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
91void release_thread(struct task_struct *);
92unsigned long get_wchan(struct task_struct *p);
93
94/*
95 * Free current thread data structures etc..
96 */
97
98extern inline void exit_thread(void)
99{
100 /* Nothing needs to be done. */
101}
102
103/*
104 * Return saved PC of a blocked thread. For now, this is the "user" PC
105 */
106extern unsigned long thread_saved_pc(struct task_struct *t);
107
108#define init_stack (init_thread_union.stack)
109
110#define cpu_relax() do { } while (0)
111
112#endif /* __ASSEMBLY__ */
113#endif /* __ASM_OPENRISC_PROCESSOR_H */
diff --git a/arch/openrisc/include/asm/prom.h b/arch/openrisc/include/asm/prom.h
new file mode 100644
index 00000000000..e1f3fe26606
--- /dev/null
+++ b/arch/openrisc/include/asm/prom.h
@@ -0,0 +1,77 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 * et al.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18#include <linux/of.h> /* linux/of.h gets to determine #include ordering */
19
20#ifndef _ASM_OPENRISC_PROM_H
21#define _ASM_OPENRISC_PROM_H
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24
25#include <linux/types.h>
26#include <asm/irq.h>
27#include <linux/atomic.h>
28#include <linux/of_irq.h>
29#include <linux/of_fdt.h>
30#include <linux/of_address.h>
31#include <linux/proc_fs.h>
32#include <linux/platform_device.h>
33#define HAVE_ARCH_DEVTREE_FIXUPS
34
35/* Other Prototypes */
36extern int early_uartlite_console(void);
37
38/* Parse the ibm,dma-window property of an OF node into the busno, phys and
39 * size parameters.
40 */
41void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
42 unsigned long *busno, unsigned long *phys, unsigned long *size);
43
44extern void kdump_move_device_tree(void);
45
46/* CPU OF node matching */
47struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
48
49/* Get the MAC address */
50extern const void *of_get_mac_address(struct device_node *np);
51
52/**
53 * of_irq_map_pci - Resolve the interrupt for a PCI device
54 * @pdev: the device whose interrupt is to be resolved
55 * @out_irq: structure of_irq filled by this function
56 *
57 * This function resolves the PCI interrupt for a given PCI device. If a
58 * device-node exists for a given pci_dev, it will use normal OF tree
59 * walking. If not, it will implement standard swizzling and walk up the
60 * PCI tree until an device-node is found, at which point it will finish
61 * resolving using the OF tree walking.
62 */
63struct pci_dev;
64extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
65
66/* This routine is here to provide compatibility with how powerpc
67 * handles IRQ mapping for OF device nodes. We precompute and permanently
68 * register them in the platform_device objects, whereas powerpc computes them
69 * on request.
70 */
71static inline void irq_dispose_mapping(unsigned int virq)
72{
73}
74
75#endif /* __ASSEMBLY__ */
76#endif /* __KERNEL__ */
77#endif /* _ASM_OPENRISC_PROM_H */
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
new file mode 100644
index 00000000000..054537c5f9c
--- /dev/null
+++ b/arch/openrisc/include/asm/ptrace.h
@@ -0,0 +1,131 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_PTRACE_H
20#define __ASM_OPENRISC_PTRACE_H
21
22#include <asm/spr_defs.h>
23
24#ifndef __ASSEMBLY__
25/*
26 * This is the layout of the regset returned by the GETREGSET ptrace call
27 */
28struct user_regs_struct {
29 /* GPR R0-R31... */
30 unsigned long gpr[32];
31 unsigned long pc;
32 unsigned long sr;
33 unsigned long pad1;
34 unsigned long pad2;
35};
36#endif
37
38#ifdef __KERNEL__
39
40/*
41 * Make kernel PTrace/register structures opaque to userspace... userspace can
42 * access thread state via the regset mechanism. This allows us a bit of
43 * flexibility in how we order the registers on the stack, permitting some
44 * optimizations like packing call-clobbered registers together so that
45 * they share a cacheline (not done yet, though... future optimization).
46 */
47
48#ifndef __ASSEMBLY__
49/*
50 * This struct describes how the registers are laid out on the kernel stack
51 * during a syscall or other kernel entry.
52 *
53 * This structure should always be cacheline aligned on the stack.
54 * FIXME: I don't think that's the case right now. The alignment is
55 * taken care of elsewhere... head.S, process.c, etc.
56 */
57
58struct pt_regs {
59 union {
60 struct {
61 /* Named registers */
62 long sr; /* Stored in place of r0 */
63 long sp; /* r1 */
64 };
65 struct {
66 /* Old style */
67 long offset[2];
68 long gprs[30];
69 };
70 struct {
71 /* New style */
72 long gpr[32];
73 };
74 };
75 long pc;
76 long orig_gpr11; /* For restarting system calls */
77 long syscallno; /* Syscall number (used by strace) */
78 long dummy; /* Cheap alignment fix */
79};
80#endif /* __ASSEMBLY__ */
81
82/* TODO: Rename this to REDZONE because that's what it is */
83#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */
84
85#define instruction_pointer(regs) ((regs)->pc)
86#define user_mode(regs) (((regs)->sr & SPR_SR_SM) == 0)
87#define user_stack_pointer(regs) ((unsigned long)(regs)->sp)
88#define profile_pc(regs) instruction_pointer(regs)
89
90/*
91 * Offsets used by 'ptrace' system call interface.
92 */
93#define PT_SR 0
94#define PT_SP 4
95#define PT_GPR2 8
96#define PT_GPR3 12
97#define PT_GPR4 16
98#define PT_GPR5 20
99#define PT_GPR6 24
100#define PT_GPR7 28
101#define PT_GPR8 32
102#define PT_GPR9 36
103#define PT_GPR10 40
104#define PT_GPR11 44
105#define PT_GPR12 48
106#define PT_GPR13 52
107#define PT_GPR14 56
108#define PT_GPR15 60
109#define PT_GPR16 64
110#define PT_GPR17 68
111#define PT_GPR18 72
112#define PT_GPR19 76
113#define PT_GPR20 80
114#define PT_GPR21 84
115#define PT_GPR22 88
116#define PT_GPR23 92
117#define PT_GPR24 96
118#define PT_GPR25 100
119#define PT_GPR26 104
120#define PT_GPR27 108
121#define PT_GPR28 112
122#define PT_GPR29 116
123#define PT_GPR30 120
124#define PT_GPR31 124
125#define PT_PC 128
126#define PT_ORIG_GPR11 132
127#define PT_SYSCALLNO 136
128
129#endif /* __KERNEL__ */
130
131#endif /* __ASM_OPENRISC_PTRACE_H */
diff --git a/arch/openrisc/include/asm/serial.h b/arch/openrisc/include/asm/serial.h
new file mode 100644
index 00000000000..270a4524163
--- /dev/null
+++ b/arch/openrisc/include/asm/serial.h
@@ -0,0 +1,36 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_SERIAL_H
20#define __ASM_OPENRISC_SERIAL_H
21
22#ifdef __KERNEL__
23
24#include <asm/cpuinfo.h>
25
26/* There's a generic version of this file, but it assumes a 1.8MHz UART clk...
27 * this, on the other hand, assumes the UART clock is tied to the system
28 * clock... 8250_early.c (early 8250 serial console) actually uses this, so
29 * it needs to be correct to get the early console working.
30 */
31
32#define BASE_BAUD (cpuinfo.clock_frequency/16)
33
34#endif /* __KERNEL__ */
35
36#endif /* __ASM_OPENRISC_SERIAL_H */
diff --git a/arch/openrisc/include/asm/sigcontext.h b/arch/openrisc/include/asm/sigcontext.h
new file mode 100644
index 00000000000..b79c2b19afb
--- /dev/null
+++ b/arch/openrisc/include/asm/sigcontext.h
@@ -0,0 +1,33 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_SIGCONTEXT_H
20#define __ASM_OPENRISC_SIGCONTEXT_H
21
22#include <asm/ptrace.h>
23
24/* This struct is saved by setup_frame in signal.c, to keep the current
25 context while a signal handler is executed. It's restored by sys_sigreturn.
26*/
27
28struct sigcontext {
29 struct user_regs_struct regs; /* needs to be first */
30 unsigned long oldmask;
31};
32
33#endif /* __ASM_OPENRISC_SIGCONTEXT_H */
diff --git a/arch/openrisc/include/asm/spinlock.h b/arch/openrisc/include/asm/spinlock.h
new file mode 100644
index 00000000000..fd00a3a2412
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -0,0 +1,24 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_SPINLOCK_H
20#define __ASM_OPENRISC_SPINLOCK_H
21
22#error "or32 doesn't do SMP yet"
23
24#endif
diff --git a/arch/openrisc/include/asm/spr.h b/arch/openrisc/include/asm/spr.h
new file mode 100644
index 00000000000..1cccb42dd47
--- /dev/null
+++ b/arch/openrisc/include/asm/spr.h
@@ -0,0 +1,42 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __ASM_OPENRISC_SPR_H
18#define __ASM_OPENRISC_SPR_H
19
20#define mtspr(_spr, _val) __asm__ __volatile__ ( \
21 "l.mtspr r0,%1,%0" \
22 : : "K" (_spr), "r" (_val))
23#define mtspr_off(_spr, _off, _val) __asm__ __volatile__ ( \
24 "l.mtspr %0,%1,%2" \
25 : : "r" (_off), "r" (_val), "K" (_spr))
26
27static inline unsigned long mfspr(unsigned long add)
28{
29 unsigned long ret;
30 __asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add));
31 return ret;
32}
33
34static inline unsigned long mfspr_off(unsigned long add, unsigned long offset)
35{
36 unsigned long ret;
37 __asm__ __volatile__ ("l.mfspr %0,%1,%2" : "=r" (ret)
38 : "r" (offset), "K" (add));
39 return ret;
40}
41
42#endif
diff --git a/arch/openrisc/include/asm/spr_defs.h b/arch/openrisc/include/asm/spr_defs.h
new file mode 100644
index 00000000000..5dbc668865c
--- /dev/null
+++ b/arch/openrisc/include/asm/spr_defs.h
@@ -0,0 +1,604 @@
1/*
2 * OpenRISC Linux
3 *
4 * SPR Definitions
5 *
6 * Copyright (C) 2000 Damjan Lampret
7 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
8 * Copyright (C) 2008, 2010 Embecosm Limited
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 * et al.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This file is part of OpenRISC 1000 Architectural Simulator.
18 */
19
20#ifndef SPR_DEFS__H
21#define SPR_DEFS__H
22
23/* Definition of special-purpose registers (SPRs). */
24
25#define MAX_GRPS (32)
26#define MAX_SPRS_PER_GRP_BITS (11)
27#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
28#define MAX_SPRS (0x10000)
29
30/* Base addresses for the groups */
31#define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
32#define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS)
33#define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
34#define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS)
35#define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)
36#define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS)
37#define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS)
38#define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS)
39#define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
40#define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS)
41#define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS)
42#define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS)
43
44/* System control and status group */
45#define SPR_VR (SPRGROUP_SYS + 0)
46#define SPR_UPR (SPRGROUP_SYS + 1)
47#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
48#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
49#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
50#define SPR_DCCFGR (SPRGROUP_SYS + 5)
51#define SPR_ICCFGR (SPRGROUP_SYS + 6)
52#define SPR_DCFGR (SPRGROUP_SYS + 7)
53#define SPR_PCCFGR (SPRGROUP_SYS + 8)
54#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
55#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
56#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
57#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */
58#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
59#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
60#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
61#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
62#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
63#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
64#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
65
66/* Data MMU group */
67#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
68#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
69#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
70#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
71#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
72#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
73
74/* Instruction MMU group */
75#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
76#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)
77#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
78#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
79#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
80#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
81
82/* Data cache group */
83#define SPR_DCCR (SPRGROUP_DC + 0)
84#define SPR_DCBPR (SPRGROUP_DC + 1)
85#define SPR_DCBFR (SPRGROUP_DC + 2)
86#define SPR_DCBIR (SPRGROUP_DC + 3)
87#define SPR_DCBWR (SPRGROUP_DC + 4)
88#define SPR_DCBLR (SPRGROUP_DC + 5)
89#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
90#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
91
92/* Instruction cache group */
93#define SPR_ICCR (SPRGROUP_IC + 0)
94#define SPR_ICBPR (SPRGROUP_IC + 1)
95#define SPR_ICBIR (SPRGROUP_IC + 2)
96#define SPR_ICBLR (SPRGROUP_IC + 3)
97#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
98#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
99
100/* MAC group */
101#define SPR_MACLO (SPRGROUP_MAC + 1)
102#define SPR_MACHI (SPRGROUP_MAC + 2)
103
104/* Debug group */
105#define SPR_DVR(N) (SPRGROUP_D + (N))
106#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
107#define SPR_DMR1 (SPRGROUP_D + 16)
108#define SPR_DMR2 (SPRGROUP_D + 17)
109#define SPR_DWCR0 (SPRGROUP_D + 18)
110#define SPR_DWCR1 (SPRGROUP_D + 19)
111#define SPR_DSR (SPRGROUP_D + 20)
112#define SPR_DRR (SPRGROUP_D + 21)
113
114/* Performance counters group */
115#define SPR_PCCR(N) (SPRGROUP_PC + (N))
116#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
117
118/* Power management group */
119#define SPR_PMR (SPRGROUP_PM + 0)
120
121/* PIC group */
122#define SPR_PICMR (SPRGROUP_PIC + 0)
123#define SPR_PICPR (SPRGROUP_PIC + 1)
124#define SPR_PICSR (SPRGROUP_PIC + 2)
125
126/* Tick Timer group */
127#define SPR_TTMR (SPRGROUP_TT + 0)
128#define SPR_TTCR (SPRGROUP_TT + 1)
129
130/*
131 * Bit definitions for the Version Register
132 *
133 */
134#define SPR_VR_VER 0xff000000 /* Processor version */
135#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
136#define SPR_VR_RES 0x0000ffc0 /* Reserved */
137#define SPR_VR_REV 0x0000003f /* Processor revision */
138
139#define SPR_VR_VER_OFF 24
140#define SPR_VR_CFG_OFF 16
141#define SPR_VR_REV_OFF 0
142
143/*
144 * Bit definitions for the Unit Present Register
145 *
146 */
147#define SPR_UPR_UP 0x00000001 /* UPR present */
148#define SPR_UPR_DCP 0x00000002 /* Data cache present */
149#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
150#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
151#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
152#define SPR_UPR_MP 0x00000020 /* MAC present */
153#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
154#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
155#define SPR_UPR_PMP 0x00000100 /* Power management present */
156#define SPR_UPR_PICP 0x00000200 /* PIC present */
157#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
158#define SPR_UPR_RES 0x00fe0000 /* Reserved */
159#define SPR_UPR_CUP 0xff000000 /* Context units present */
160
161/*
162 * JPB: Bit definitions for the CPU configuration register
163 *
164 */
165#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
166#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
167#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
168#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
169#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
170#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
171#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
172#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
173
174/*
175 * JPB: Bit definitions for the Debug configuration register and other
176 * constants.
177 *
178 */
179
180#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
181#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
182#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
183#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
184#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
185#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
186#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
187#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
188#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
189#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
190
191#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
192 2 == n ? SPR_DCFGR_NDP2 : \
193 3 == n ? SPR_DCFGR_NDP3 : \
194 4 == n ? SPR_DCFGR_NDP4 : \
195 5 == n ? SPR_DCFGR_NDP5 : \
196 6 == n ? SPR_DCFGR_NDP6 : \
197 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
198#define MAX_MATCHPOINTS 8
199#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
200
201/*
202 * Bit definitions for the Supervision Register
203 *
204 */
205#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
206#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
207#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
208#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
209#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
210#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
211#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
212#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
213#define SPR_SR_CE 0x00000100 /* CID Enable */
214#define SPR_SR_F 0x00000200 /* Condition Flag */
215#define SPR_SR_CY 0x00000400 /* Carry flag */
216#define SPR_SR_OV 0x00000800 /* Overflow flag */
217#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
218#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
219#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
220#define SPR_SR_FO 0x00008000 /* Fixed one */
221#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
222#define SPR_SR_RES 0x0ffe0000 /* Reserved */
223#define SPR_SR_CID 0xf0000000 /* Context ID */
224
225/*
226 * Bit definitions for the Data MMU Control Register
227 *
228 */
229#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
230#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
231#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
232#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
233
234/*
235 * Bit definitions for the Instruction MMU Control Register
236 *
237 */
238#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
239#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
240#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
241#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
242
243/*
244 * Bit definitions for the Data TLB Match Register
245 *
246 */
247#define SPR_DTLBMR_V 0x00000001 /* Valid */
248#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
249#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
250#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
251#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
252
253/*
254 * Bit definitions for the Data TLB Translate Register
255 *
256 */
257#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
258#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
259#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
260#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
261#define SPR_DTLBTR_A 0x00000010 /* Accessed */
262#define SPR_DTLBTR_D 0x00000020 /* Dirty */
263#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
264#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
265#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
266#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
267#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
268
269/*
270 * Bit definitions for the Instruction TLB Match Register
271 *
272 */
273#define SPR_ITLBMR_V 0x00000001 /* Valid */
274#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
275#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
276#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
277#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
278
279/*
280 * Bit definitions for the Instruction TLB Translate Register
281 *
282 */
283#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
284#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
285#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
286#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
287#define SPR_ITLBTR_A 0x00000010 /* Accessed */
288#define SPR_ITLBTR_D 0x00000020 /* Dirty */
289#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
290#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
291#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
292
293/*
294 * Bit definitions for Data Cache Control register
295 *
296 */
297#define SPR_DCCR_EW 0x000000ff /* Enable ways */
298
299/*
300 * Bit definitions for Insn Cache Control register
301 *
302 */
303#define SPR_ICCR_EW 0x000000ff /* Enable ways */
304
305/*
306 * Bit definitions for Data Cache Configuration Register
307 *
308 */
309
310#define SPR_DCCFGR_NCW 0x00000007
311#define SPR_DCCFGR_NCS 0x00000078
312#define SPR_DCCFGR_CBS 0x00000080
313#define SPR_DCCFGR_CWS 0x00000100
314#define SPR_DCCFGR_CCRI 0x00000200
315#define SPR_DCCFGR_CBIRI 0x00000400
316#define SPR_DCCFGR_CBPRI 0x00000800
317#define SPR_DCCFGR_CBLRI 0x00001000
318#define SPR_DCCFGR_CBFRI 0x00002000
319#define SPR_DCCFGR_CBWBRI 0x00004000
320
321#define SPR_DCCFGR_NCW_OFF 0
322#define SPR_DCCFGR_NCS_OFF 3
323#define SPR_DCCFGR_CBS_OFF 7
324
325/*
326 * Bit definitions for Instruction Cache Configuration Register
327 *
328 */
329#define SPR_ICCFGR_NCW 0x00000007
330#define SPR_ICCFGR_NCS 0x00000078
331#define SPR_ICCFGR_CBS 0x00000080
332#define SPR_ICCFGR_CCRI 0x00000200
333#define SPR_ICCFGR_CBIRI 0x00000400
334#define SPR_ICCFGR_CBPRI 0x00000800
335#define SPR_ICCFGR_CBLRI 0x00001000
336
337#define SPR_ICCFGR_NCW_OFF 0
338#define SPR_ICCFGR_NCS_OFF 3
339#define SPR_ICCFGR_CBS_OFF 7
340
341/*
342 * Bit definitions for Data MMU Configuration Register
343 *
344 */
345
346#define SPR_DMMUCFGR_NTW 0x00000003
347#define SPR_DMMUCFGR_NTS 0x0000001C
348#define SPR_DMMUCFGR_NAE 0x000000E0
349#define SPR_DMMUCFGR_CRI 0x00000100
350#define SPR_DMMUCFGR_PRI 0x00000200
351#define SPR_DMMUCFGR_TEIRI 0x00000400
352#define SPR_DMMUCFGR_HTR 0x00000800
353
354#define SPR_DMMUCFGR_NTW_OFF 0
355#define SPR_DMMUCFGR_NTS_OFF 2
356
357/*
358 * Bit definitions for Instruction MMU Configuration Register
359 *
360 */
361
362#define SPR_IMMUCFGR_NTW 0x00000003
363#define SPR_IMMUCFGR_NTS 0x0000001C
364#define SPR_IMMUCFGR_NAE 0x000000E0
365#define SPR_IMMUCFGR_CRI 0x00000100
366#define SPR_IMMUCFGR_PRI 0x00000200
367#define SPR_IMMUCFGR_TEIRI 0x00000400
368#define SPR_IMMUCFGR_HTR 0x00000800
369
370#define SPR_IMMUCFGR_NTW_OFF 0
371#define SPR_IMMUCFGR_NTS_OFF 2
372
373/*
374 * Bit definitions for Debug Control registers
375 *
376 */
377#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
378#define SPR_DCR_CC 0x0000000e /* Compare condition */
379#define SPR_DCR_SC 0x00000010 /* Signed compare */
380#define SPR_DCR_CT 0x000000e0 /* Compare to */
381
382/* Bit results with SPR_DCR_CC mask */
383#define SPR_DCR_CC_MASKED 0x00000000
384#define SPR_DCR_CC_EQUAL 0x00000002
385#define SPR_DCR_CC_LESS 0x00000004
386#define SPR_DCR_CC_LESSE 0x00000006
387#define SPR_DCR_CC_GREAT 0x00000008
388#define SPR_DCR_CC_GREATE 0x0000000a
389#define SPR_DCR_CC_NEQUAL 0x0000000c
390
391/* Bit results with SPR_DCR_CT mask */
392#define SPR_DCR_CT_DISABLED 0x00000000
393#define SPR_DCR_CT_IFEA 0x00000020
394#define SPR_DCR_CT_LEA 0x00000040
395#define SPR_DCR_CT_SEA 0x00000060
396#define SPR_DCR_CT_LD 0x00000080
397#define SPR_DCR_CT_SD 0x000000a0
398#define SPR_DCR_CT_LSEA 0x000000c0
399#define SPR_DCR_CT_LSD 0x000000e0
400/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
401
402/*
403 * Bit definitions for Debug Mode 1 register
404 *
405 */
406#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
407#define SPR_DMR1_CW0_AND 0x00000001
408#define SPR_DMR1_CW0_OR 0x00000002
409#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
410#define SPR_DMR1_CW1_AND 0x00000004
411#define SPR_DMR1_CW1_OR 0x00000008
412#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
413#define SPR_DMR1_CW2_AND 0x00000010
414#define SPR_DMR1_CW2_OR 0x00000020
415#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
416#define SPR_DMR1_CW3_AND 0x00000040
417#define SPR_DMR1_CW3_OR 0x00000080
418#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
419#define SPR_DMR1_CW4_AND 0x00000100
420#define SPR_DMR1_CW4_OR 0x00000200
421#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
422#define SPR_DMR1_CW5_AND 0x00000400
423#define SPR_DMR1_CW5_OR 0x00000800
424#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
425#define SPR_DMR1_CW6_AND 0x00001000
426#define SPR_DMR1_CW6_OR 0x00002000
427#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
428#define SPR_DMR1_CW7_AND 0x00004000
429#define SPR_DMR1_CW7_OR 0x00008000
430#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
431#define SPR_DMR1_CW8_AND 0x00010000
432#define SPR_DMR1_CW8_OR 0x00020000
433#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
434#define SPR_DMR1_CW9_AND 0x00040000
435#define SPR_DMR1_CW9_OR 0x00080000
436#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
437#define SPR_DMR1_RES1 0x00300000 /* Reserved */
438#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
439#define SPR_DMR1_BT 0x00800000 /* Branch trace */
440#define SPR_DMR1_RES2 0xff000000 /* Reserved */
441
442/*
443 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
444 *
445 */
446#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
447#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
448#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
449#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
450#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
451#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
452#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */
453#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
454
455/*
456 * Bit definitions for Debug watchpoint counter registers
457 *
458 */
459#define SPR_DWCR_COUNT 0x0000ffff /* Count */
460#define SPR_DWCR_MATCH 0xffff0000 /* Match */
461#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
462
463/*
464 * Bit definitions for Debug stop register
465 *
466 */
467#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
468#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
469#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
470#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
471#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */
472#define SPR_DSR_AE 0x00000020 /* Alignment exception */
473#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
474#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
475#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
476#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
477#define SPR_DSR_RE 0x00000400 /* Range exception */
478#define SPR_DSR_SCE 0x00000800 /* System call exception */
479#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
480#define SPR_DSR_TE 0x00002000 /* Trap exception */
481
482/*
483 * Bit definitions for Debug reason register
484 *
485 */
486#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
487#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
488#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
489#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
490#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
491#define SPR_DRR_AE 0x00000020 /* Alignment exception */
492#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
493#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
494#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
495#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
496#define SPR_DRR_RE 0x00000400 /* Range exception */
497#define SPR_DRR_SCE 0x00000800 /* System call exception */
498#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
499#define SPR_DRR_TE 0x00002000 /* Trap exception */
500
501/*
502 * Bit definitions for Performance counters mode registers
503 *
504 */
505#define SPR_PCMR_CP 0x00000001 /* Counter present */
506#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
507#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
508#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
509#define SPR_PCMR_LA 0x00000010 /* Load access event */
510#define SPR_PCMR_SA 0x00000020 /* Store access event */
511#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
512#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
513#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
514#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
515#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
516#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
517#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
518#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
519#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
520#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
521
522/*
523 * Bit definitions for the Power management register
524 *
525 */
526#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
527#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
528#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
529#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
530#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
531
532/*
533 * Bit definitions for PICMR
534 *
535 */
536#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
537
538/*
539 * Bit definitions for PICPR
540 *
541 */
542#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
543
544/*
545 * Bit definitions for PICSR
546 *
547 */
548#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
549
550/*
551 * Bit definitions for Tick Timer Control Register
552 *
553 */
554
555#define SPR_TTCR_CNT 0xffffffff /* Count, time period */
556#define SPR_TTMR_TP 0x0fffffff /* Time period */
557#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
558#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
559#define SPR_TTMR_DI 0x00000000 /* Disabled */
560#define SPR_TTMR_RT 0x40000000 /* Restart tick */
561#define SPR_TTMR_SR 0x80000000 /* Single run */
562#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
563#define SPR_TTMR_M 0xc0000000 /* Tick mode */
564
565/*
566 * Bit definitions for the FP Control Status Register
567 *
568 */
569#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
570#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
571#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
572#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
573#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
574#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
575#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
576#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
577#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
578#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
579#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
580#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
581 SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
582 SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
583
584#define FPCSR_RM_RN (0<<1)
585#define FPCSR_RM_RZ (1<<1)
586#define FPCSR_RM_RIP (2<<1)
587#define FPCSR_RM_RIN (3<<1)
588
589/*
590 * l.nop constants
591 *
592 */
593#define NOP_NOP 0x0000 /* Normal nop instruction */
594#define NOP_EXIT 0x0001 /* End of simulation */
595#define NOP_REPORT 0x0002 /* Simple report */
596/*#define NOP_PRINTF 0x0003 Simprintf instruction (obsolete)*/
597#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */
598#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
599#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */
600#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */
601#define NOP_REPORT_FIRST 0x0400 /* Report with number */
602#define NOP_REPORT_LAST 0x03ff /* Report with number */
603
604#endif /* SPR_DEFS__H */
diff --git a/arch/openrisc/include/asm/syscall.h b/arch/openrisc/include/asm/syscall.h
new file mode 100644
index 00000000000..9f0337055d2
--- /dev/null
+++ b/arch/openrisc/include/asm/syscall.h
@@ -0,0 +1,77 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_SYSCALL_H__
20#define __ASM_OPENRISC_SYSCALL_H__
21
22#include <linux/err.h>
23#include <linux/sched.h>
24
25static inline int
26syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
27{
28 return regs->syscallno ? regs->syscallno : -1;
29}
30
31static inline void
32syscall_rollback(struct task_struct *task, struct pt_regs *regs)
33{
34 regs->gpr[11] = regs->orig_gpr11;
35}
36
37static inline long
38syscall_get_error(struct task_struct *task, struct pt_regs *regs)
39{
40 return IS_ERR_VALUE(regs->gpr[11]) ? regs->gpr[11] : 0;
41}
42
43static inline long
44syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
45{
46 return regs->gpr[11];
47}
48
49static inline void
50syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
51 int error, long val)
52{
53 if (error)
54 regs->gpr[11] = -error;
55 else
56 regs->gpr[11] = val;
57}
58
59static inline void
60syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
61 unsigned int i, unsigned int n, unsigned long *args)
62{
63 BUG_ON(i + n > 6);
64
65 memcpy(args, &regs->gpr[3 + i], n * sizeof(args[0]));
66}
67
68static inline void
69syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
70 unsigned int i, unsigned int n, const unsigned long *args)
71{
72 BUG_ON(i + n > 6);
73
74 memcpy(&regs->gpr[3 + i], args, n * sizeof(args[0]));
75}
76
77#endif
diff --git a/arch/openrisc/include/asm/syscalls.h b/arch/openrisc/include/asm/syscalls.h
new file mode 100644
index 00000000000..84a978af44d
--- /dev/null
+++ b/arch/openrisc/include/asm/syscalls.h
@@ -0,0 +1,27 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_SYSCALLS_H
20#define __ASM_OPENRISC_SYSCALLS_H
21
22asmlinkage long sys_or1k_atomic(unsigned long type, unsigned long *v1,
23 unsigned long *v2);
24
25#include <asm-generic/syscalls.h>
26
27#endif /* __ASM_OPENRISC_SYSCALLS_H */
diff --git a/arch/openrisc/include/asm/system.h b/arch/openrisc/include/asm/system.h
new file mode 100644
index 00000000000..cf658882186
--- /dev/null
+++ b/arch/openrisc/include/asm/system.h
@@ -0,0 +1,35 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_SYSTEM_H
20#define __ASM_OPENRISC_SYSTEM_H
21
22#ifdef __KERNEL__
23#ifndef __ASSEMBLY__
24
25#include <asm/spr.h>
26#include <asm-generic/system.h>
27
28/* We probably need this definition, but the generic system.h provides it
29 * and it's not used on our arch anyway...
30 */
31/*#define nop() __asm__ __volatile__ ("l.nop"::)*/
32
33#endif /* __ASSEMBLY__ */
34#endif /* __KERNEL__ */
35#endif /* __ASM_OPENRISC_SYSTEM_H */
diff --git a/arch/openrisc/include/asm/thread_info.h b/arch/openrisc/include/asm/thread_info.h
new file mode 100644
index 00000000000..07a8bc080ef
--- /dev/null
+++ b/arch/openrisc/include/asm/thread_info.h
@@ -0,0 +1,134 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef _ASM_THREAD_INFO_H
20#define _ASM_THREAD_INFO_H
21
22#ifdef __KERNEL__
23
24#ifndef __ASSEMBLY__
25#include <asm/types.h>
26#include <asm/processor.h>
27#endif
28
29
30/* THREAD_SIZE is the size of the task_struct/kernel_stack combo.
31 * normally, the stack is found by doing something like p + THREAD_SIZE
32 * in or32, a page is 8192 bytes, which seems like a sane size
33 */
34
35#define THREAD_SIZE_ORDER 0
36#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
37
38/*
39 * low level task data that entry.S needs immediate access to
40 * - this struct should fit entirely inside of one cache line
41 * - this struct shares the supervisor stack pages
42 * - if the contents of this structure are changed, the assembly constants
43 * must also be changed
44 */
45#ifndef __ASSEMBLY__
46
47typedef unsigned long mm_segment_t;
48
49struct thread_info {
50 struct task_struct *task; /* main task structure */
51 struct exec_domain *exec_domain; /* execution domain */
52 unsigned long flags; /* low level flags */
53 __u32 cpu; /* current CPU */
54 __s32 preempt_count; /* 0 => preemptable, <0 => BUG */
55
56 mm_segment_t addr_limit; /* thread address space:
57 0-0x7FFFFFFF for user-thead
58 0-0xFFFFFFFF for kernel-thread
59 */
60 struct restart_block restart_block;
61 __u8 supervisor_stack[0];
62
63 /* saved context data */
64 unsigned long ksp;
65};
66#endif
67
68/*
69 * macros/functions for gaining access to the thread information structure
70 *
71 * preempt_count needs to be 1 initially, until the scheduler is functional.
72 */
73#ifndef __ASSEMBLY__
74#define INIT_THREAD_INFO(tsk) \
75{ \
76 .task = &tsk, \
77 .exec_domain = &default_exec_domain, \
78 .flags = 0, \
79 .cpu = 0, \
80 .preempt_count = 1, \
81 .addr_limit = KERNEL_DS, \
82 .restart_block = { \
83 .fn = do_no_restart_syscall, \
84 }, \
85 .ksp = 0, \
86}
87
88#define init_thread_info (init_thread_union.thread_info)
89
90/* how to get the thread information struct from C */
91register struct thread_info *current_thread_info_reg asm("r10");
92#define current_thread_info() (current_thread_info_reg)
93
94#define get_thread_info(ti) get_task_struct((ti)->task)
95#define put_thread_info(ti) put_task_struct((ti)->task)
96
97#endif /* !__ASSEMBLY__ */
98
99/*
100 * thread information flags
101 * these are process state flags that various assembly files may need to
102 * access
103 * - pending work-to-be-done flags are in LSW
104 * - other flags in MSW
105 */
106#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
107#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
108#define TIF_SIGPENDING 2 /* signal pending */
109#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
110#define TIF_SINGLESTEP 4 /* restore singlestep on return to user
111 * mode
112 */
113#define TIF_SYSCALL_TRACEPOINT 8 /* for ftrace syscall instrumentation */
114#define TIF_RESTORE_SIGMASK 9
115#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling * TIF_NEED_RESCHED
116 */
117#define TIF_MEMDIE 17
118
119#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
120#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
121#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
122#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
123#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
124#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
125#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
126
127
128/* Work to do when returning from interrupt/exception */
129/* For OpenRISC, this is anything in the LSW other than syscall trace */
130#define _TIF_WORK_MASK (0xff & ~(_TIF_SYSCALL_TRACE|_TIF_SINGLESTEP))
131
132#endif /* __KERNEL__ */
133
134#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/openrisc/include/asm/timex.h b/arch/openrisc/include/asm/timex.h
new file mode 100644
index 00000000000..9935cad1b9b
--- /dev/null
+++ b/arch/openrisc/include/asm/timex.h
@@ -0,0 +1,36 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __ASM_OPENRISC_TIMEX_H
18#define __ASM_OPENRISC_TIMEX_H
19
20#define get_cycles get_cycles
21
22#include <asm-generic/timex.h>
23#include <asm/spr.h>
24#include <asm/spr_defs.h>
25
26static inline cycles_t get_cycles(void)
27{
28 return mfspr(SPR_TTCR);
29}
30
31/* This isn't really used any more */
32#define CLOCK_TICK_RATE 1000
33
34#define ARCH_HAS_READ_CURRENT_TIMER
35
36#endif
diff --git a/arch/openrisc/include/asm/tlb.h b/arch/openrisc/include/asm/tlb.h
new file mode 100644
index 00000000000..fa4376a4515
--- /dev/null
+++ b/arch/openrisc/include/asm/tlb.h
@@ -0,0 +1,34 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_TLB_H__
20#define __ASM_OPENRISC_TLB_H__
21
22/*
23 * or32 doesn't need any special per-pte or
24 * per-vma handling..
25 */
26#define tlb_start_vma(tlb, vma) do { } while (0)
27#define tlb_end_vma(tlb, vma) do { } while (0)
28#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
29
30#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
31#include <linux/pagemap.h>
32#include <asm-generic/tlb.h>
33
34#endif /* __ASM_OPENRISC_TLB_H__ */
diff --git a/arch/openrisc/include/asm/tlbflush.h b/arch/openrisc/include/asm/tlbflush.h
new file mode 100644
index 00000000000..6a2accd6cb6
--- /dev/null
+++ b/arch/openrisc/include/asm/tlbflush.h
@@ -0,0 +1,55 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_TLBFLUSH_H
20#define __ASM_OPENRISC_TLBFLUSH_H
21
22#include <linux/mm.h>
23#include <asm/processor.h>
24#include <asm/pgtable.h>
25#include <asm/pgalloc.h>
26#include <asm/current.h>
27#include <linux/sched.h>
28
29/*
30 * - flush_tlb() flushes the current mm struct TLBs
31 * - flush_tlb_all() flushes all processes TLBs
32 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
33 * - flush_tlb_page(vma, vmaddr) flushes one page
34 * - flush_tlb_range(mm, start, end) flushes a range of pages
35 */
36
37void flush_tlb_all(void);
38void flush_tlb_mm(struct mm_struct *mm);
39void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
40void flush_tlb_range(struct vm_area_struct *vma,
41 unsigned long start,
42 unsigned long end);
43
44static inline void flush_tlb(void)
45{
46 flush_tlb_mm(current->mm);
47}
48
49static inline void flush_tlb_kernel_range(unsigned long start,
50 unsigned long end)
51{
52 flush_tlb_range(NULL, start, end);
53}
54
55#endif /* __ASM_OPENRISC_TLBFLUSH_H */
diff --git a/arch/openrisc/include/asm/uaccess.h b/arch/openrisc/include/asm/uaccess.h
new file mode 100644
index 00000000000..c310e45b538
--- /dev/null
+++ b/arch/openrisc/include/asm/uaccess.h
@@ -0,0 +1,355 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_UACCESS_H
20#define __ASM_OPENRISC_UACCESS_H
21
22/*
23 * User space memory access functions
24 */
25#include <linux/errno.h>
26#include <linux/thread_info.h>
27#include <linux/prefetch.h>
28#include <linux/string.h>
29#include <linux/thread_info.h>
30#include <asm/page.h>
31
32#define VERIFY_READ 0
33#define VERIFY_WRITE 1
34
35/*
36 * The fs value determines whether argument validity checking should be
37 * performed or not. If get_fs() == USER_DS, checking is performed, with
38 * get_fs() == KERNEL_DS, checking is bypassed.
39 *
40 * For historical reasons, these macros are grossly misnamed.
41 */
42
43/* addr_limit is the maximum accessible address for the task. we misuse
44 * the KERNEL_DS and USER_DS values to both assign and compare the
45 * addr_limit values through the equally misnamed get/set_fs macros.
46 * (see above)
47 */
48
49#define KERNEL_DS (~0UL)
50#define get_ds() (KERNEL_DS)
51
52#define USER_DS (TASK_SIZE)
53#define get_fs() (current_thread_info()->addr_limit)
54#define set_fs(x) (current_thread_info()->addr_limit = (x))
55
56#define segment_eq(a, b) ((a) == (b))
57
58/* Ensure that the range from addr to addr+size is all within the process'
59 * address space
60 */
61#define __range_ok(addr, size) (size <= get_fs() && addr <= (get_fs()-size))
62
63/* Ensure that addr is below task's addr_limit */
64#define __addr_ok(addr) ((unsigned long) addr < get_fs())
65
66#define access_ok(type, addr, size) \
67 __range_ok((unsigned long)addr, (unsigned long)size)
68
69/*
70 * The exception table consists of pairs of addresses: the first is the
71 * address of an instruction that is allowed to fault, and the second is
72 * the address at which the program should continue. No registers are
73 * modified, so it is entirely up to the continuation code to figure out
74 * what to do.
75 *
76 * All the routines below use bits of fixup code that are out of line
77 * with the main instruction path. This means when everything is well,
78 * we don't even have to jump over them. Further, they do not intrude
79 * on our cache or tlb entries.
80 */
81
82struct exception_table_entry {
83 unsigned long insn, fixup;
84};
85
86/* Returns 0 if exception not found and fixup otherwise. */
87extern unsigned long search_exception_table(unsigned long);
88extern void sort_exception_table(void);
89
90/*
91 * These are the main single-value transfer routines. They automatically
92 * use the right size if we just have the right pointer type.
93 *
94 * This gets kind of ugly. We want to return _two_ values in "get_user()"
95 * and yet we don't want to do any pointers, because that is too much
96 * of a performance impact. Thus we have a few rather ugly macros here,
97 * and hide all the uglyness from the user.
98 *
99 * The "__xxx" versions of the user access functions are versions that
100 * do not verify the address space, that must have been done previously
101 * with a separate "access_ok()" call (this is used when we do multiple
102 * accesses to the same area of user memory).
103 *
104 * As we use the same address space for kernel and user data on the
105 * PowerPC, we can just do these as direct assignments. (Of course, the
106 * exception handling means that it's no longer "just"...)
107 */
108#define get_user(x, ptr) \
109 __get_user_check((x), (ptr), sizeof(*(ptr)))
110#define put_user(x, ptr) \
111 __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
112
113#define __get_user(x, ptr) \
114 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
115#define __put_user(x, ptr) \
116 __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
117
118extern long __put_user_bad(void);
119
120#define __put_user_nocheck(x, ptr, size) \
121({ \
122 long __pu_err; \
123 __put_user_size((x), (ptr), (size), __pu_err); \
124 __pu_err; \
125})
126
127#define __put_user_check(x, ptr, size) \
128({ \
129 long __pu_err = -EFAULT; \
130 __typeof__(*(ptr)) *__pu_addr = (ptr); \
131 if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
132 __put_user_size((x), __pu_addr, (size), __pu_err); \
133 __pu_err; \
134})
135
136#define __put_user_size(x, ptr, size, retval) \
137do { \
138 retval = 0; \
139 switch (size) { \
140 case 1: __put_user_asm(x, ptr, retval, "l.sb"); break; \
141 case 2: __put_user_asm(x, ptr, retval, "l.sh"); break; \
142 case 4: __put_user_asm(x, ptr, retval, "l.sw"); break; \
143 case 8: __put_user_asm2(x, ptr, retval); break; \
144 default: __put_user_bad(); \
145 } \
146} while (0)
147
148struct __large_struct {
149 unsigned long buf[100];
150};
151#define __m(x) (*(struct __large_struct *)(x))
152
153/*
154 * We don't tell gcc that we are accessing memory, but this is OK
155 * because we do not write to any memory gcc knows about, so there
156 * are no aliasing issues.
157 */
158#define __put_user_asm(x, addr, err, op) \
159 __asm__ __volatile__( \
160 "1: "op" 0(%2),%1\n" \
161 "2:\n" \
162 ".section .fixup,\"ax\"\n" \
163 "3: l.addi %0,r0,%3\n" \
164 " l.j 2b\n" \
165 " l.nop\n" \
166 ".previous\n" \
167 ".section __ex_table,\"a\"\n" \
168 " .align 2\n" \
169 " .long 1b,3b\n" \
170 ".previous" \
171 : "=r"(err) \
172 : "r"(x), "r"(addr), "i"(-EFAULT), "0"(err))
173
174#define __put_user_asm2(x, addr, err) \
175 __asm__ __volatile__( \
176 "1: l.sw 0(%2),%1\n" \
177 "2: l.sw 4(%2),%H1\n" \
178 "3:\n" \
179 ".section .fixup,\"ax\"\n" \
180 "4: l.addi %0,r0,%3\n" \
181 " l.j 3b\n" \
182 " l.nop\n" \
183 ".previous\n" \
184 ".section __ex_table,\"a\"\n" \
185 " .align 2\n" \
186 " .long 1b,4b\n" \
187 " .long 2b,4b\n" \
188 ".previous" \
189 : "=r"(err) \
190 : "r"(x), "r"(addr), "i"(-EFAULT), "0"(err))
191
192#define __get_user_nocheck(x, ptr, size) \
193({ \
194 long __gu_err, __gu_val; \
195 __get_user_size(__gu_val, (ptr), (size), __gu_err); \
196 (x) = (__typeof__(*(ptr)))__gu_val; \
197 __gu_err; \
198})
199
200#define __get_user_check(x, ptr, size) \
201({ \
202 long __gu_err = -EFAULT, __gu_val = 0; \
203 const __typeof__(*(ptr)) * __gu_addr = (ptr); \
204 if (access_ok(VERIFY_READ, __gu_addr, size)) \
205 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
206 (x) = (__typeof__(*(ptr)))__gu_val; \
207 __gu_err; \
208})
209
210extern long __get_user_bad(void);
211
212#define __get_user_size(x, ptr, size, retval) \
213do { \
214 retval = 0; \
215 switch (size) { \
216 case 1: __get_user_asm(x, ptr, retval, "l.lbz"); break; \
217 case 2: __get_user_asm(x, ptr, retval, "l.lhz"); break; \
218 case 4: __get_user_asm(x, ptr, retval, "l.lwz"); break; \
219 case 8: __get_user_asm2(x, ptr, retval); \
220 default: (x) = __get_user_bad(); \
221 } \
222} while (0)
223
224#define __get_user_asm(x, addr, err, op) \
225 __asm__ __volatile__( \
226 "1: "op" %1,0(%2)\n" \
227 "2:\n" \
228 ".section .fixup,\"ax\"\n" \
229 "3: l.addi %0,r0,%3\n" \
230 " l.addi %1,r0,0\n" \
231 " l.j 2b\n" \
232 " l.nop\n" \
233 ".previous\n" \
234 ".section __ex_table,\"a\"\n" \
235 " .align 2\n" \
236 " .long 1b,3b\n" \
237 ".previous" \
238 : "=r"(err), "=r"(x) \
239 : "r"(addr), "i"(-EFAULT), "0"(err))
240
241#define __get_user_asm2(x, addr, err) \
242 __asm__ __volatile__( \
243 "1: l.lwz %1,0(%2)\n" \
244 "2: l.lwz %H1,4(%2)\n" \
245 "3:\n" \
246 ".section .fixup,\"ax\"\n" \
247 "4: l.addi %0,r0,%3\n" \
248 " l.addi %1,r0,0\n" \
249 " l.addi %H1,r0,0\n" \
250 " l.j 3b\n" \
251 " l.nop\n" \
252 ".previous\n" \
253 ".section __ex_table,\"a\"\n" \
254 " .align 2\n" \
255 " .long 1b,4b\n" \
256 " .long 2b,4b\n" \
257 ".previous" \
258 : "=r"(err), "=&r"(x) \
259 : "r"(addr), "i"(-EFAULT), "0"(err))
260
261/* more complex routines */
262
263extern unsigned long __must_check
264__copy_tofrom_user(void *to, const void *from, unsigned long size);
265
266#define __copy_from_user(to, from, size) \
267 __copy_tofrom_user(to, from, size)
268#define __copy_to_user(to, from, size) \
269 __copy_tofrom_user(to, from, size)
270
271#define __copy_to_user_inatomic __copy_to_user
272#define __copy_from_user_inatomic __copy_from_user
273
274static inline unsigned long
275copy_from_user(void *to, const void *from, unsigned long n)
276{
277 unsigned long over;
278
279 if (access_ok(VERIFY_READ, from, n))
280 return __copy_tofrom_user(to, from, n);
281 if ((unsigned long)from < TASK_SIZE) {
282 over = (unsigned long)from + n - TASK_SIZE;
283 return __copy_tofrom_user(to, from, n - over) + over;
284 }
285 return n;
286}
287
288static inline unsigned long
289copy_to_user(void *to, const void *from, unsigned long n)
290{
291 unsigned long over;
292
293 if (access_ok(VERIFY_WRITE, to, n))
294 return __copy_tofrom_user(to, from, n);
295 if ((unsigned long)to < TASK_SIZE) {
296 over = (unsigned long)to + n - TASK_SIZE;
297 return __copy_tofrom_user(to, from, n - over) + over;
298 }
299 return n;
300}
301
302extern unsigned long __clear_user(void *addr, unsigned long size);
303
304static inline __must_check unsigned long
305clear_user(void *addr, unsigned long size)
306{
307
308 if (access_ok(VERIFY_WRITE, addr, size))
309 return __clear_user(addr, size);
310 if ((unsigned long)addr < TASK_SIZE) {
311 unsigned long over = (unsigned long)addr + size - TASK_SIZE;
312 return __clear_user(addr, size - over) + over;
313 }
314 return size;
315}
316
317extern int __strncpy_from_user(char *dst, const char *src, long count);
318
319static inline long strncpy_from_user(char *dst, const char *src, long count)
320{
321 if (access_ok(VERIFY_READ, src, 1))
322 return __strncpy_from_user(dst, src, count);
323 return -EFAULT;
324}
325
326/*
327 * Return the size of a string (including the ending 0)
328 *
329 * Return 0 for error
330 */
331
332extern int __strnlen_user(const char *str, long len, unsigned long top);
333
334/*
335 * Returns the length of the string at str (including the null byte),
336 * or 0 if we hit a page we can't access,
337 * or something > len if we didn't find a null byte.
338 *
339 * The `top' parameter to __strnlen_user is to make sure that
340 * we can never overflow from the user area into kernel space.
341 */
342static inline long strnlen_user(const char __user *str, long len)
343{
344 unsigned long top = (unsigned long)get_fs();
345 unsigned long res = 0;
346
347 if (__addr_ok(str))
348 res = __strnlen_user(str, len, top);
349
350 return res;
351}
352
353#define strlen_user(str) strnlen_user(str, TASK_SIZE-1)
354
355#endif /* __ASM_OPENRISC_UACCESS_H */
diff --git a/arch/openrisc/include/asm/unaligned.h b/arch/openrisc/include/asm/unaligned.h
new file mode 100644
index 00000000000..1141cbd6fd7
--- /dev/null
+++ b/arch/openrisc/include/asm/unaligned.h
@@ -0,0 +1,51 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#ifndef __ASM_OPENRISC_UNALIGNED_H
20#define __ASM_OPENRISC_UNALIGNED_H
21
22/*
23 * This is copied from the generic implementation and the C-struct
24 * variant replaced with the memmove variant. The GCC compiler
25 * for the OR32 arch optimizes too aggressively for the C-struct
26 * variant to work, so use the memmove variant instead.
27 *
28 * It may be worth considering implementing the unaligned access
29 * exception handler and allowing unaligned accesses (access_ok.h)...
30 * not sure if it would be much of a performance win without further
31 * investigation.
32 */
33#include <asm/byteorder.h>
34
35#if defined(__LITTLE_ENDIAN)
36# include <linux/unaligned/le_memmove.h>
37# include <linux/unaligned/be_byteshift.h>
38# include <linux/unaligned/generic.h>
39# define get_unaligned __get_unaligned_le
40# define put_unaligned __put_unaligned_le
41#elif defined(__BIG_ENDIAN)
42# include <linux/unaligned/be_memmove.h>
43# include <linux/unaligned/le_byteshift.h>
44# include <linux/unaligned/generic.h>
45# define get_unaligned __get_unaligned_be
46# define put_unaligned __put_unaligned_be
47#else
48# error need to define endianess
49#endif
50
51#endif /* __ASM_OPENRISC_UNALIGNED_H */
diff --git a/arch/openrisc/include/asm/unistd.h b/arch/openrisc/include/asm/unistd.h
new file mode 100644
index 00000000000..89af3ab5c2e
--- /dev/null
+++ b/arch/openrisc/include/asm/unistd.h
@@ -0,0 +1,31 @@
1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * OpenRISC implementation:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 * et al.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#if !defined(__ASM_OPENRISC_UNISTD_H) || defined(__SYSCALL)
20#define __ASM_OPENRISC_UNISTD_H
21
22#define __ARCH_HAVE_MMU
23
24#define sys_mmap2 sys_mmap_pgoff
25
26#include <asm-generic/unistd.h>
27
28#define __NR_or1k_atomic __NR_arch_specific_syscall
29__SYSCALL(__NR_or1k_atomic, sys_or1k_atomic)
30
31#endif /* __ASM_OPENRISC_UNISTD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-02 13:13:57 -0400