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-rw-r--r--arch/mips/netlogic/common/earlycons.c2
-rw-r--r--arch/mips/netlogic/common/smpboot.S157
-rw-r--r--arch/mips/netlogic/xlp/Makefile2
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c52
-rw-r--r--arch/mips/netlogic/xlp/of.c34
-rw-r--r--arch/mips/netlogic/xlp/platform.c2
-rw-r--r--arch/mips/netlogic/xlp/setup.c16
-rw-r--r--arch/mips/netlogic/xlp/usb-init.c124
-rw-r--r--arch/mips/netlogic/xlr/Makefile2
-rw-r--r--arch/mips/netlogic/xlr/platform-flash.c220
-rw-r--r--arch/mips/netlogic/xlr/platform.c140
-rw-r--r--arch/mips/netlogic/xlr/setup.c2
12 files changed, 694 insertions, 59 deletions
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
index f193f7b3bd8..1902fa22d27 100644
--- a/arch/mips/netlogic/common/earlycons.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -54,7 +54,7 @@ void prom_putchar(char c)
54#elif defined(CONFIG_CPU_XLR) 54#elif defined(CONFIG_CPU_XLR)
55 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); 55 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
56#endif 56#endif
57 while (nlm_read_reg(uartbase, UART_LSR) == 0) 57 while ((nlm_read_reg(uartbase, UART_LSR) & UART_LSR_THRE) == 0)
58 ; 58 ;
59 nlm_write_reg(uartbase, UART_TX, c); 59 nlm_write_reg(uartbase, UART_TX, c);
60} 60}
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index c138b1a6dec..a13355cc97e 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -54,28 +54,68 @@
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4 55 SYS_CPU_NONCOHERENT_MODE * 4
56 56
57.macro __config_lsu 57#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
58 li t0, LSU_DEFEATURE
59 mfcr t1, t0
60 58
61 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ 59/* Enable XLP features and workarounds in the LSU */
62 or t1, t1, t2 60.macro xlp_config_lsu
63 li t2, ~0xe /* S1RCM */ 61 li t0, LSU_DEFEATURE
62 mfcr t1, t0
63
64 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
65 or t1, t1, t2
66#ifdef XLP_AX_WORKAROUND
67 li t2, ~0xe /* S1RCM */
64 and t1, t1, t2 68 and t1, t1, t2
65 mtcr t1, t0 69#endif
70 mtcr t1, t0
66 71
67 li t0, SCHED_DEFEATURE 72#ifdef XLP_AX_WORKAROUND
68 lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */ 73 li t0, SCHED_DEFEATURE
69 mtcr t1, t0 74 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
75 mtcr t1, t0
76#endif
77.endm
78
79/*
80 * This is the code that will be copied to the reset entry point for
81 * XLR and XLP. The XLP cores start here when they are woken up. This
82 * is also the NMI entry point.
83 */
84.macro xlp_flush_l1_dcache
85 li t0, LSU_DEBUG_DATA0
86 li t1, LSU_DEBUG_ADDR
87 li t2, 0 /* index */
88 li t3, 0x1000 /* loop count */
891:
90 sll v0, t2, 5
91 mtcr zero, t0
92 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
93 mtcr v1, t1
942:
95 mfcr v1, t1
96 andi v1, 0x1 /* wait for write_active == 0 */
97 bnez v1, 2b
98 nop
99 mtcr zero, t0
100 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
101 mtcr v1, t1
1023:
103 mfcr v1, t1
104 andi v1, 0x1 /* wait for write_active == 0 */
105 bnez v1, 3b
106 nop
107 addi t2, 1
108 bne t3, t2, 1b
109 nop
70.endm 110.endm
71 111
72/* 112/*
73 * The cores can come start when they are woken up. This is also the NMI 113 * The cores can come start when they are woken up. This is also the NMI
74 * entry, so check that first. 114 * entry, so check that first.
75 * 115 *
76 * The data corresponding to reset is stored at RESET_DATA_PHYS location, 116 * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
77 * this will have the thread mask (used when core is woken up) and the 117 * location, this will have the thread mask (used when core is woken up)
78 * current NMI handler in case we reached here for an NMI. 118 * and the current NMI handler in case we reached here for an NMI.
79 * 119 *
80 * When a core or thread is newly woken up, it loops in a 'wait'. When 120 * When a core or thread is newly woken up, it loops in a 'wait'. When
81 * the CPU really needs waking up, we send an NMI to it, with the NMI 121 * the CPU really needs waking up, we send an NMI to it, with the NMI
@@ -89,12 +129,12 @@
89FEXPORT(nlm_reset_entry) 129FEXPORT(nlm_reset_entry)
90 dmtc0 k0, $22, 6 130 dmtc0 k0, $22, 6
91 dmtc0 k1, $22, 7 131 dmtc0 k1, $22, 7
92 mfc0 k0, CP0_STATUS 132 mfc0 k0, CP0_STATUS
93 li k1, 0x80000 133 li k1, 0x80000
94 and k1, k0, k1 134 and k1, k0, k1
95 beqz k1, 1f /* go to real reset entry */ 135 beqz k1, 1f /* go to real reset entry */
96 nop 136 nop
97 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 137 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
98 ld k0, BOOT_NMI_HANDLER(k1) 138 ld k0, BOOT_NMI_HANDLER(k1)
99 jr k0 139 jr k0
100 nop 140 nop
@@ -114,21 +154,25 @@ FEXPORT(nlm_reset_entry)
114 li t2, SYS_CPU_COHERENT_BASE(0) 154 li t2, SYS_CPU_COHERENT_BASE(0)
115 add t2, t2, t3 /* t2 <- SYS offset for node */ 155 add t2, t2, t3 /* t2 <- SYS offset for node */
116 lw t1, 0(t2) 156 lw t1, 0(t2)
117 and t1, t1, t0 157 and t1, t1, t0
118 sw t1, 0(t2) 158 sw t1, 0(t2)
119 159
120 /* read back to ensure complete */ 160 /* read back to ensure complete */
121 lw t1, 0(t2) 161 lw t1, 0(t2)
122 sync 162 sync
123 163
124 /* Configure LSU on Non-0 Cores. */ 164 /* Configure LSU on Non-0 Cores. */
125 __config_lsu 165 xlp_config_lsu
166 /* FALL THROUGH */
126 167
127/* 168/*
128 * Wake up sibling threads from the initial thread in 169 * Wake up sibling threads from the initial thread in
129 * a core. 170 * a core.
130 */ 171 */
131EXPORT(nlm_boot_siblings) 172EXPORT(nlm_boot_siblings)
173 /* core L1D flush before enable threads */
174 xlp_flush_l1_dcache
175 /* Enable hw threads by writing to MAP_THREADMODE of the core */
132 li t0, CKSEG1ADDR(RESET_DATA_PHYS) 176 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
133 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ 177 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
134 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) 178 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
@@ -139,31 +183,28 @@ EXPORT(nlm_boot_siblings)
139 /* 183 /*
140 * The new hardware thread starts at the next instruction 184 * The new hardware thread starts at the next instruction
141 * For all the cases other than core 0 thread 0, we will 185 * For all the cases other than core 0 thread 0, we will
142 * jump to the secondary wait function. 186 * jump to the secondary wait function.
143 */ 187 */
144 mfc0 v0, CP0_EBASE, 1 188 mfc0 v0, CP0_EBASE, 1
145 andi v0, 0x7f /* v0 <- node/core */ 189 andi v0, 0x7f /* v0 <- node/core */
146 190
147#if 1 191 /* Init MMU in the first thread after changing THREAD_MODE
148 /* A0 errata - Write MMU_SETUP after changing thread mode register. */ 192 * register (Ax Errata?)
193 */
149 andi v1, v0, 0x3 /* v1 <- thread id */ 194 andi v1, v0, 0x3 /* v1 <- thread id */
150 bnez v1, 2f 195 bnez v1, 2f
151 nop 196 nop
152 197
153 li t0, MMU_SETUP 198 li t0, MMU_SETUP
154 li t1, 0 199 li t1, 0
155 mtcr t1, t0 200 mtcr t1, t0
156 ehb 201 _ehb
157#endif
158 202
1592: beqz v0, 4f 2032: beqz v0, 4f /* boot cpu (cpuid == 0)? */
160 nop 204 nop
161 205
162 /* setup status reg */ 206 /* setup status reg */
163 mfc0 t1, CP0_STATUS 207 move t1, zero
164 li t0, ST0_BEV
165 or t1, t0
166 xor t1, t0
167#ifdef CONFIG_64BIT 208#ifdef CONFIG_64BIT
168 ori t1, ST0_KX 209 ori t1, ST0_KX
169#endif 210#endif
@@ -183,9 +224,9 @@ EXPORT(nlm_boot_siblings)
183 * For the boot CPU, we have to restore registers and 224 * For the boot CPU, we have to restore registers and
184 * return 225 * return
185 */ 226 */
1864: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ 2274: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
187 li t1, 0xfadebeef 228 li t1, 0xfadebeef
188 dmtc0 t1, $4, 2 /* restore SP from UserLocal */ 229 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
189 PTR_SUBU sp, t0, PT_SIZE 230 PTR_SUBU sp, t0, PT_SIZE
190 RESTORE_ALL 231 RESTORE_ALL
191 jr ra 232 jr ra
@@ -193,7 +234,7 @@ EXPORT(nlm_boot_siblings)
193EXPORT(nlm_reset_entry_end) 234EXPORT(nlm_reset_entry_end)
194 235
195FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ 236FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
196 __config_lsu 237 xlp_config_lsu
197 dmtc0 sp, $4, 2 /* SP saved in UserLocal */ 238 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
198 SAVE_ALL 239 SAVE_ALL
199 sync 240 sync
@@ -210,6 +251,12 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
210 251
211 __CPUINIT 252 __CPUINIT
212NESTED(nlm_boot_secondary_cpus, 16, sp) 253NESTED(nlm_boot_secondary_cpus, 16, sp)
254 /* Initialize CP0 Status */
255 move t1, zero
256#ifdef CONFIG_64BIT
257 ori t1, ST0_KX
258#endif
259 mtc0 t1, CP0_STATUS
213 PTR_LA t1, nlm_next_sp 260 PTR_LA t1, nlm_next_sp
214 PTR_L sp, 0(t1) 261 PTR_L sp, 0(t1)
215 PTR_LA t1, nlm_next_gp 262 PTR_LA t1, nlm_next_gp
@@ -234,36 +281,36 @@ END(nlm_boot_secondary_cpus)
234 */ 281 */
235 __CPUINIT 282 __CPUINIT
236NESTED(nlm_rmiboot_preboot, 16, sp) 283NESTED(nlm_rmiboot_preboot, 16, sp)
237 mfc0 t0, $15, 1 # read ebase 284 mfc0 t0, $15, 1 /* read ebase */
238 andi t0, 0x1f # t0 has the processor_id() 285 andi t0, 0x1f /* t0 has the processor_id() */
239 andi t2, t0, 0x3 # thread no 286 andi t2, t0, 0x3 /* thread num */
240 sll t0, 2 # offset in cpu array 287 sll t0, 2 /* offset in cpu array */
241 288
242 PTR_LA t1, nlm_cpu_ready # mark CPU ready 289 PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
243 PTR_ADDU t1, t0 290 PTR_ADDU t1, t0
244 li t3, 1 291 li t3, 1
245 sw t3, 0(t1) 292 sw t3, 0(t1)
246 293
247 bnez t2, 1f # skip thread programming 294 bnez t2, 1f /* skip thread programming */
248 nop # for non zero hw threads 295 nop /* for thread id != 0 */
249 296
250 /* 297 /*
251 * MMU setup only for first thread in core 298 * XLR MMU setup only for first thread in core
252 */ 299 */
253 li t0, 0x400 300 li t0, 0x400
254 mfcr t1, t0 301 mfcr t1, t0
255 li t2, 6 # XLR thread mode mask 302 li t2, 6 /* XLR thread mode mask */
256 nor t3, t2, zero 303 nor t3, t2, zero
257 and t2, t1, t2 # t2 - current thread mode 304 and t2, t1, t2 /* t2 - current thread mode */
258 li v0, CKSEG1ADDR(RESET_DATA_PHYS) 305 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
259 lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode 306 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
260 sll v1, 1 307 sll v1, 1
261 beq v1, t2, 1f # same as request value 308 beq v1, t2, 1f /* same as request value */
262 nop # nothing to do */ 309 nop /* nothing to do */
263 310
264 and t2, t1, t3 # mask out old thread mode 311 and t2, t1, t3 /* mask out old thread mode */
265 or t1, t2, v1 # put in new value 312 or t1, t2, v1 /* put in new value */
266 mtcr t1, t0 # update core control 313 mtcr t1, t0 /* update core control */
267 314
2681: wait 3151: wait
269 j 1b 316 j 1b
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
index b93ed83474e..6b4b972218f 100644
--- a/arch/mips/netlogic/xlp/Makefile
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -1,2 +1,4 @@
1obj-y += setup.o platform.o nlm_hal.o 1obj-y += setup.o platform.o nlm_hal.o
2obj-$(CONFIG_OF) += of.o
2obj-$(CONFIG_SMP) += wakeup.o 3obj-$(CONFIG_SMP) += wakeup.o
4obj-$(CONFIG_USB) += usb-init.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 9428e7125fe..6c65ac70191 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -69,6 +69,32 @@ int nlm_irq_to_irt(int irq)
69 return PIC_IRT_UART_0_INDEX; 69 return PIC_IRT_UART_0_INDEX;
70 case PIC_UART_1_IRQ: 70 case PIC_UART_1_IRQ:
71 return PIC_IRT_UART_1_INDEX; 71 return PIC_IRT_UART_1_INDEX;
72 case PIC_PCIE_LINK_0_IRQ:
73 return PIC_IRT_PCIE_LINK_0_INDEX;
74 case PIC_PCIE_LINK_1_IRQ:
75 return PIC_IRT_PCIE_LINK_1_INDEX;
76 case PIC_PCIE_LINK_2_IRQ:
77 return PIC_IRT_PCIE_LINK_2_INDEX;
78 case PIC_PCIE_LINK_3_IRQ:
79 return PIC_IRT_PCIE_LINK_3_INDEX;
80 case PIC_EHCI_0_IRQ:
81 return PIC_IRT_EHCI_0_INDEX;
82 case PIC_EHCI_1_IRQ:
83 return PIC_IRT_EHCI_1_INDEX;
84 case PIC_OHCI_0_IRQ:
85 return PIC_IRT_OHCI_0_INDEX;
86 case PIC_OHCI_1_IRQ:
87 return PIC_IRT_OHCI_1_INDEX;
88 case PIC_OHCI_2_IRQ:
89 return PIC_IRT_OHCI_2_INDEX;
90 case PIC_OHCI_3_IRQ:
91 return PIC_IRT_OHCI_3_INDEX;
92 case PIC_MMC_IRQ:
93 return PIC_IRT_MMC_INDEX;
94 case PIC_I2C_0_IRQ:
95 return PIC_IRT_I2C_0_INDEX;
96 case PIC_I2C_1_IRQ:
97 return PIC_IRT_I2C_1_INDEX;
72 default: 98 default:
73 return -1; 99 return -1;
74 } 100 }
@@ -81,6 +107,32 @@ int nlm_irt_to_irq(int irt)
81 return PIC_UART_0_IRQ; 107 return PIC_UART_0_IRQ;
82 case PIC_IRT_UART_1_INDEX: 108 case PIC_IRT_UART_1_INDEX:
83 return PIC_UART_1_IRQ; 109 return PIC_UART_1_IRQ;
110 case PIC_IRT_PCIE_LINK_0_INDEX:
111 return PIC_PCIE_LINK_0_IRQ;
112 case PIC_IRT_PCIE_LINK_1_INDEX:
113 return PIC_PCIE_LINK_1_IRQ;
114 case PIC_IRT_PCIE_LINK_2_INDEX:
115 return PIC_PCIE_LINK_2_IRQ;
116 case PIC_IRT_PCIE_LINK_3_INDEX:
117 return PIC_PCIE_LINK_3_IRQ;
118 case PIC_IRT_EHCI_0_INDEX:
119 return PIC_EHCI_0_IRQ;
120 case PIC_IRT_EHCI_1_INDEX:
121 return PIC_EHCI_1_IRQ;
122 case PIC_IRT_OHCI_0_INDEX:
123 return PIC_OHCI_0_IRQ;
124 case PIC_IRT_OHCI_1_INDEX:
125 return PIC_OHCI_1_IRQ;
126 case PIC_IRT_OHCI_2_INDEX:
127 return PIC_OHCI_2_IRQ;
128 case PIC_IRT_OHCI_3_INDEX:
129 return PIC_OHCI_3_IRQ;
130 case PIC_IRT_MMC_INDEX:
131 return PIC_MMC_IRQ;
132 case PIC_IRT_I2C_0_INDEX:
133 return PIC_I2C_0_IRQ;
134 case PIC_IRT_I2C_1_INDEX:
135 return PIC_I2C_1_IRQ;
84 default: 136 default:
85 return -1; 137 return -1;
86 } 138 }
diff --git a/arch/mips/netlogic/xlp/of.c b/arch/mips/netlogic/xlp/of.c
new file mode 100644
index 00000000000..8e3921c0c20
--- /dev/null
+++ b/arch/mips/netlogic/xlp/of.c
@@ -0,0 +1,34 @@
1#include <linux/bootmem.h>
2#include <linux/init.h>
3#include <linux/io.h>
4#include <linux/of_fdt.h>
5#include <asm/byteorder.h>
6
7static int __init reserve_mem_mach(unsigned long addr, unsigned long size)
8{
9 return reserve_bootmem(addr, size, BOOTMEM_DEFAULT);
10}
11
12void __init free_mem_mach(unsigned long addr, unsigned long size)
13{
14 return free_bootmem(addr, size);
15}
16
17void __init device_tree_init(void)
18{
19 unsigned long base, size;
20
21 if (!initial_boot_params)
22 return;
23
24 base = virt_to_phys((void *)initial_boot_params);
25 size = be32_to_cpu(initial_boot_params->totalsize);
26
27 /* Before we do anything, lets reserve the dt blob */
28 reserve_mem_mach(base, size);
29
30 unflatten_device_tree();
31
32 /* free the space reserved for the dt blob */
33 free_mem_mach(base, size);
34}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
index 1f5e4cba891..2c510d58544 100644
--- a/arch/mips/netlogic/xlp/platform.c
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -53,7 +53,7 @@
53 53
54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset) 54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
55{ 55{
56 return nlm_read_reg(p->iobase, offset); 56 return nlm_read_reg(p->iobase, offset);
57} 57}
58 58
59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value) 59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index b3df7c2aad1..3dec9f28b65 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -41,6 +41,8 @@
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42 42
43#include <linux/of_fdt.h> 43#include <linux/of_fdt.h>
44#include <linux/of_platform.h>
45#include <linux/of_device.h>
44 46
45#include <asm/netlogic/haldefs.h> 47#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h> 48#include <asm/netlogic/common.h>
@@ -109,3 +111,17 @@ void __init prom_init(void)
109 register_smp_ops(&nlm_smp_ops); 111 register_smp_ops(&nlm_smp_ops);
110#endif 112#endif
111} 113}
114
115static struct of_device_id __initdata xlp_ids[] = {
116 { .compatible = "simple-bus", },
117 {},
118};
119
120int __init xlp8xx_ds_publish_devices(void)
121{
122 if (!of_have_populated_dt())
123 return 0;
124 return of_platform_bus_probe(NULL, xlp_ids, NULL);
125}
126
127device_initcall(xlp8xx_ds_publish_devices);
diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c
new file mode 100644
index 00000000000..dbe083a9353
--- /dev/null
+++ b/arch/mips/netlogic/xlp/usb-init.c
@@ -0,0 +1,124 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/dma-mapping.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/init.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41
42#include <asm/netlogic/haldefs.h>
43#include <asm/netlogic/xlp-hal/iomap.h>
44#include <asm/netlogic/xlp-hal/xlp.h>
45#include <asm/netlogic/xlp-hal/usb.h>
46
47static void nlm_usb_intr_en(int node, int port)
48{
49 uint32_t val;
50 uint64_t port_addr;
51
52 port_addr = nlm_get_usb_regbase(node, port);
53 val = nlm_read_usb_reg(port_addr, USB_INT_EN);
54 val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
55 USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN |
56 USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
57 nlm_write_usb_reg(port_addr, USB_INT_EN, val);
58}
59
60static void nlm_usb_hw_reset(int node, int port)
61{
62 uint64_t port_addr;
63 uint32_t val;
64
65 /* reset USB phy */
66 port_addr = nlm_get_usb_regbase(node, port);
67 val = nlm_read_usb_reg(port_addr, USB_PHY_0);
68 val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
69 nlm_write_usb_reg(port_addr, USB_PHY_0, val);
70
71 mdelay(100);
72 val = nlm_read_usb_reg(port_addr, USB_CTL_0);
73 val &= ~(USB_CONTROLLER_RESET);
74 val |= 0x4;
75 nlm_write_usb_reg(port_addr, USB_CTL_0, val);
76}
77
78static int __init nlm_platform_usb_init(void)
79{
80 pr_info("Initializing USB Interface\n");
81 nlm_usb_hw_reset(0, 0);
82 nlm_usb_hw_reset(0, 3);
83
84 /* Enable PHY interrupts */
85 nlm_usb_intr_en(0, 0);
86 nlm_usb_intr_en(0, 3);
87
88 return 0;
89}
90
91arch_initcall(nlm_platform_usb_init);
92
93static u64 xlp_usb_dmamask = ~(u32)0;
94
95/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
96static void nlm_usb_fixup_final(struct pci_dev *dev)
97{
98 dev->dev.dma_mask = &xlp_usb_dmamask;
99 dev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
100 switch (dev->devfn) {
101 case 0x10:
102 dev->irq = PIC_EHCI_0_IRQ;
103 break;
104 case 0x11:
105 dev->irq = PIC_OHCI_0_IRQ;
106 break;
107 case 0x12:
108 dev->irq = PIC_OHCI_1_IRQ;
109 break;
110 case 0x13:
111 dev->irq = PIC_EHCI_1_IRQ;
112 break;
113 case 0x14:
114 dev->irq = PIC_OHCI_2_IRQ;
115 break;
116 case 0x15:
117 dev->irq = PIC_OHCI_3_IRQ;
118 break;
119 }
120}
121DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
122 nlm_usb_fixup_final);
123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
124 nlm_usb_fixup_final);
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index f01e4d7a060..c287dea8757 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,2 +1,2 @@
1obj-y += setup.o platform.o 1obj-y += setup.o platform.o platform-flash.o
2obj-$(CONFIG_SMP) += wakeup.o 2obj-$(CONFIG_SMP) += wakeup.o
diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c
new file mode 100644
index 00000000000..340ab1601c4
--- /dev/null
+++ b/arch/mips/netlogic/xlr/platform-flash.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright 2011, Netlogic Microsystems.
3 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/ioport.h>
17#include <linux/resource.h>
18#include <linux/spi/flash.h>
19
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/physmap.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/netlogic/haldefs.h>
26#include <asm/netlogic/xlr/iomap.h>
27#include <asm/netlogic/xlr/flash.h>
28#include <asm/netlogic/xlr/bridge.h>
29#include <asm/netlogic/xlr/gpio.h>
30#include <asm/netlogic/xlr/xlr.h>
31
32/*
33 * Default NOR partition layout
34 */
35static struct mtd_partition xlr_nor_parts[] = {
36 {
37 .name = "User FS",
38 .offset = 0x800000,
39 .size = MTDPART_SIZ_FULL,
40 }
41};
42
43/*
44 * Default NAND partition layout
45 */
46static struct mtd_partition xlr_nand_parts[] = {
47 {
48 .name = "Root Filesystem",
49 .offset = 64 * 64 * 2048,
50 .size = 432 * 64 * 2048,
51 },
52 {
53 .name = "Home Filesystem",
54 .offset = MTDPART_OFS_APPEND,
55 .size = MTDPART_SIZ_FULL,
56 },
57};
58
59/* Use PHYSMAP flash for NOR */
60struct physmap_flash_data xlr_nor_data = {
61 .width = 2,
62 .parts = xlr_nor_parts,
63 .nr_parts = ARRAY_SIZE(xlr_nor_parts),
64};
65
66static struct resource xlr_nor_res[] = {
67 {
68 .flags = IORESOURCE_MEM,
69 },
70};
71
72static struct platform_device xlr_nor_dev = {
73 .name = "physmap-flash",
74 .dev = {
75 .platform_data = &xlr_nor_data,
76 },
77 .num_resources = ARRAY_SIZE(xlr_nor_res),
78 .resource = xlr_nor_res,
79};
80
81const char *xlr_part_probes[] = { "cmdlinepart", NULL };
82
83/*
84 * Use "gen_nand" driver for NAND flash
85 *
86 * There seems to be no way to store a private pointer containing
87 * platform specific info in gen_nand drivier. We will use a global
88 * struct for now, since we currently have only one NAND chip per board.
89 */
90struct xlr_nand_flash_priv {
91 int cs;
92 uint64_t flash_mmio;
93};
94
95static struct xlr_nand_flash_priv nand_priv;
96
97static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
98 unsigned int ctrl)
99{
100 if (ctrl & NAND_CLE)
101 nlm_write_reg(nand_priv.flash_mmio,
102 FLASH_NAND_CLE(nand_priv.cs), cmd);
103 else if (ctrl & NAND_ALE)
104 nlm_write_reg(nand_priv.flash_mmio,
105 FLASH_NAND_ALE(nand_priv.cs), cmd);
106}
107
108struct platform_nand_data xlr_nand_data = {
109 .chip = {
110 .nr_chips = 1,
111 .nr_partitions = ARRAY_SIZE(xlr_nand_parts),
112 .chip_delay = 50,
113 .partitions = xlr_nand_parts,
114 .part_probe_types = xlr_part_probes,
115 },
116 .ctrl = {
117 .cmd_ctrl = xlr_nand_ctrl,
118 },
119};
120
121static struct resource xlr_nand_res[] = {
122 {
123 .flags = IORESOURCE_MEM,
124 },
125};
126
127static struct platform_device xlr_nand_dev = {
128 .name = "gen_nand",
129 .id = -1,
130 .num_resources = ARRAY_SIZE(xlr_nand_res),
131 .resource = xlr_nand_res,
132 .dev = {
133 .platform_data = &xlr_nand_data,
134 }
135};
136
137/*
138 * XLR/XLS supports upto 8 devices on its FLASH interface. The value in
139 * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
140 * flash devices.
141 * Under this, each flash device has an offset and size given by the
142 * CSBASE_ADDR and CSBASE_MASK registers for the device.
143 *
144 * The CSBASE_ registers are expected to be setup by the bootloader.
145 */
146static void setup_flash_resource(uint64_t flash_mmio,
147 uint64_t flash_map_base, int cs, struct resource *res)
148{
149 u32 base, mask;
150
151 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
152 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
153
154 res->start = flash_map_base + ((unsigned long)base << 16);
155 res->end = res->start + (mask + 1) * 64 * 1024;
156}
157
158static int __init xlr_flash_init(void)
159{
160 uint64_t gpio_mmio, flash_mmio, flash_map_base;
161 u32 gpio_resetcfg, flash_bar;
162 int cs, boot_nand, boot_nor;
163
164 /* Flash address bits 39:24 is in bridge flash BAR */
165 flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
166 flash_map_base = (flash_bar & 0xffff0000) << 8;
167
168 gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
169 flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
170
171 /* Get the chip reset config */
172 gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
173
174 /* Check for boot flash type */
175 boot_nor = boot_nand = 0;
176 if (nlm_chip_is_xls()) {
177 /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
178 if (gpio_resetcfg & (1 << 16))
179 boot_nand = 1;
180
181 /* check boot from PCMCIA, (GPIO reset reg bit 15 */
182 if ((gpio_resetcfg & (1 << 15)) == 0)
183 boot_nor = 1; /* not set, booted from NOR */
184 } else { /* XLR */
185 /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
186 if ((gpio_resetcfg & (1 << 16)) == 0)
187 boot_nor = 1; /* not set, booted from NOR */
188 }
189
190 /* boot flash at chip select 0 */
191 cs = 0;
192
193 if (boot_nand) {
194 nand_priv.cs = cs;
195 nand_priv.flash_mmio = flash_mmio;
196 setup_flash_resource(flash_mmio, flash_map_base, cs,
197 xlr_nand_res);
198
199 /* Initialize NAND flash at CS 0 */
200 nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
201 FLASH_NAND_CSDEV_PARAM);
202 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
203 FLASH_NAND_CSTIME_PARAMA);
204 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
205 FLASH_NAND_CSTIME_PARAMB);
206
207 pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
208 return platform_device_register(&xlr_nand_dev);
209 }
210
211 if (boot_nor) {
212 setup_flash_resource(flash_mmio, flash_map_base, cs,
213 xlr_nor_res);
214 pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
215 return platform_device_register(&xlr_nor_dev);
216 }
217 return 0;
218}
219
220arch_initcall(xlr_flash_init);
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index eab64b45dff..71b44d82621 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -14,6 +14,7 @@
14#include <linux/resource.h> 14#include <linux/resource.h>
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17#include <linux/i2c.h>
17 18
18#include <asm/netlogic/haldefs.h> 19#include <asm/netlogic/haldefs.h>
19#include <asm/netlogic/xlr/iomap.h> 20#include <asm/netlogic/xlr/iomap.h>
@@ -97,3 +98,142 @@ static int __init nlm_uart_init(void)
97} 98}
98 99
99arch_initcall(nlm_uart_init); 100arch_initcall(nlm_uart_init);
101
102#ifdef CONFIG_USB
103/* Platform USB devices, only on XLS chips */
104static u64 xls_usb_dmamask = ~(u32)0;
105#define USB_PLATFORM_DEV(n, i, irq) \
106 { \
107 .name = n, \
108 .id = i, \
109 .num_resources = 2, \
110 .dev = { \
111 .dma_mask = &xls_usb_dmamask, \
112 .coherent_dma_mask = 0xffffffff, \
113 }, \
114 .resource = (struct resource[]) { \
115 { \
116 .flags = IORESOURCE_MEM, \
117 }, \
118 { \
119 .start = irq, \
120 .end = irq, \
121 .flags = IORESOURCE_IRQ, \
122 }, \
123 }, \
124 }
125
126static struct platform_device xls_usb_ehci_device =
127 USB_PLATFORM_DEV("ehci-xls", 0, PIC_USB_IRQ);
128static struct platform_device xls_usb_ohci_device_0 =
129 USB_PLATFORM_DEV("ohci-xls-0", 1, PIC_USB_IRQ);
130static struct platform_device xls_usb_ohci_device_1 =
131 USB_PLATFORM_DEV("ohci-xls-1", 2, PIC_USB_IRQ);
132
133static struct platform_device *xls_platform_devices[] = {
134 &xls_usb_ehci_device,
135 &xls_usb_ohci_device_0,
136 &xls_usb_ohci_device_1,
137};
138
139int xls_platform_usb_init(void)
140{
141 uint64_t usb_mmio, gpio_mmio;
142 unsigned long memres;
143 uint32_t val;
144
145 if (!nlm_chip_is_xls())
146 return 0;
147
148 gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
149 usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_1_OFFSET);
150
151 /* Clear Rogue Phy INTs */
152 nlm_write_reg(usb_mmio, 49, 0x10000000);
153 /* Enable all interrupts */
154 nlm_write_reg(usb_mmio, 50, 0x1f000000);
155
156 /* Enable ports */
157 nlm_write_reg(usb_mmio, 1, 0x07000500);
158
159 val = nlm_read_reg(gpio_mmio, 21);
160 if (((val >> 22) & 0x01) == 0) {
161 pr_info("Detected USB Device mode - Not supported!\n");
162 nlm_write_reg(usb_mmio, 0, 0x01000000);
163 return 0;
164 }
165
166 pr_info("Detected USB Host mode - Adding XLS USB devices.\n");
167 /* Clear reset, host mode */
168 nlm_write_reg(usb_mmio, 0, 0x02000000);
169
170 /* Memory resource for various XLS usb ports */
171 usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET);
172 memres = CPHYSADDR((unsigned long)usb_mmio);
173 xls_usb_ehci_device.resource[0].start = memres;
174 xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1;
175
176 memres += 0x400;
177 xls_usb_ohci_device_0.resource[0].start = memres;
178 xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1;
179
180 memres += 0x400;
181 xls_usb_ohci_device_1.resource[0].start = memres;
182 xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1;
183
184 return platform_add_devices(xls_platform_devices,
185 ARRAY_SIZE(xls_platform_devices));
186}
187
188arch_initcall(xls_platform_usb_init);
189#endif
190
191#ifdef CONFIG_I2C
192static struct i2c_board_info nlm_i2c_board_info1[] __initdata = {
193 /* All XLR boards have this RTC and Max6657 Temp Chip */
194 [0] = {
195 .type = "ds1374",
196 .addr = 0x68
197 },
198 [1] = {
199 .type = "lm90",
200 .addr = 0x4c
201 },
202};
203
204static struct resource i2c_resources[] = {
205 [0] = {
206 .start = 0, /* filled at init */
207 .end = 0,
208 .flags = IORESOURCE_MEM,
209 },
210};
211
212static struct platform_device nlm_xlr_i2c_1 = {
213 .name = "xlr-i2cbus",
214 .id = 1,
215 .num_resources = 1,
216 .resource = i2c_resources,
217};
218
219static int __init nlm_i2c_init(void)
220{
221 int err = 0;
222 unsigned int offset;
223
224 /* I2C bus 0 does not have any useful devices, configure only bus 1 */
225 offset = NETLOGIC_IO_I2C_1_OFFSET;
226 nlm_xlr_i2c_1.resource[0].start = CPHYSADDR(nlm_mmio_base(offset));
227 nlm_xlr_i2c_1.resource[0].end = nlm_xlr_i2c_1.resource[0].start + 0xfff;
228
229 platform_device_register(&nlm_xlr_i2c_1);
230
231 err = i2c_register_board_info(1, nlm_i2c_board_info1,
232 ARRAY_SIZE(nlm_i2c_board_info1));
233 if (err < 0)
234 pr_err("nlm-i2c: cannot register board I2C devices\n");
235 return err;
236}
237
238arch_initcall(nlm_i2c_init);
239#endif
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index c9d066dedc4..81b1d311834 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -85,7 +85,7 @@ static void nlm_linux_exit(void)
85 85
86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); 86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
88 nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1); 88 nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1);
89 for ( ; ; ) 89 for ( ; ; )
90 cpu_wait(); 90 cpu_wait();
91} 91}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 18:40:42 -0400