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-rw-r--r--arch/mips/include/asm/clock.h11
-rw-r--r--arch/mips/include/asm/cpu.h3
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h150
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h89
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h8
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h286
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h1
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h45
-rw-r--r--arch/mips/include/asm/mach-jz4740/jz4740_nand.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h4
-rw-r--r--arch/mips/include/asm/mach-loongson1/irq.h73
-rw-r--r--arch/mips/include/asm/mach-loongson1/loongson1.h44
-rw-r--r--arch/mips/include/asm/mach-loongson1/platform.h23
-rw-r--r--arch/mips/include/asm/mach-loongson1/prom.h24
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-clk.h33
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-wdt.h22
-rw-r--r--arch/mips/include/asm/mach-loongson1/war.h25
-rw-r--r--arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-tx49xx/mangle-port.h2
-rw-r--r--arch/mips/include/asm/mipsmtregs.h13
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h5
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pcibus.h76
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/usb.h64
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h17
-rw-r--r--arch/mips/include/asm/netlogic/xlr/bridge.h104
-rw-r--r--arch/mips/include/asm/netlogic/xlr/flash.h55
-rw-r--r--arch/mips/include/asm/netlogic/xlr/gpio.h59
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-fpa.h64
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper.h2
-rw-r--r--arch/mips/include/asm/octeon/octeon.h5
-rw-r--r--arch/mips/include/asm/prom.h3
-rw-r--r--arch/mips/include/asm/smtc.h6
-rw-r--r--arch/mips/include/asm/uaccess.h6
-rw-r--r--arch/mips/include/asm/uasm.h100
-rw-r--r--arch/mips/include/asm/unistd.h1
40 files changed, 1208 insertions, 244 deletions
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
index 83894aa7932..c9456e7a728 100644
--- a/arch/mips/include/asm/clock.h
+++ b/arch/mips/include/asm/clock.h
@@ -50,15 +50,4 @@ void clk_recalc_rate(struct clk *);
50int clk_register(struct clk *); 50int clk_register(struct clk *);
51void clk_unregister(struct clk *); 51void clk_unregister(struct clk *);
52 52
53/* the exported API, in addition to clk_set_rate */
54/**
55 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
56 * @clk: clock source
57 * @rate: desired clock rate in Hz
58 * @algo_id: algorithm id to be passed down to ops->set_rate
59 *
60 * Returns success (0) or negative errno.
61 */
62int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
63
64#endif /* __ASM_MIPS_CLOCK_H */ 53#endif /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 95e40c1e8ed..f21b7c04e95 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -197,6 +197,7 @@
197#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 197#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
198#define PRID_REV_VR4130 0x0080 198#define PRID_REV_VR4130 0x0080
199#define PRID_REV_34K_V1_0_2 0x0022 199#define PRID_REV_34K_V1_0_2 0x0022
200#define PRID_REV_LOONGSON1B 0x0020
200#define PRID_REV_LOONGSON2E 0x0002 201#define PRID_REV_LOONGSON2E 0x0002
201#define PRID_REV_LOONGSON2F 0x0003 202#define PRID_REV_LOONGSON2F 0x0003
202 203
@@ -261,7 +262,7 @@ enum cpu_type_enum {
261 */ 262 */
262 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 263 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
263 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 264 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
264 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC, 265 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
265 266
266 /* 267 /*
267 * MIPS64 class processors 268 * MIPS64 class processors
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 5b8d15bb5fe..e104ddb694a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
9 * compile time if only one CPU support is enabled (idea stolen from 9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types) 10 * arm mach-types)
11 */ 11 */
12#define BCM6328_CPU_ID 0x6328
12#define BCM6338_CPU_ID 0x6338 13#define BCM6338_CPU_ID 0x6338
13#define BCM6345_CPU_ID 0x6345 14#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 15#define BCM6348_CPU_ID 0x6348
@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
20u16 bcm63xx_get_cpu_rev(void); 21u16 bcm63xx_get_cpu_rev(void);
21unsigned int bcm63xx_get_cpu_freq(void); 22unsigned int bcm63xx_get_cpu_freq(void);
22 23
24#ifdef CONFIG_BCM63XX_CPU_6328
25# ifdef bcm63xx_get_cpu_id
26# undef bcm63xx_get_cpu_id
27# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28# define BCMCPU_RUNTIME_DETECT
29# else
30# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
31# endif
32# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
33#else
34# define BCMCPU_IS_6328() (0)
35#endif
36
23#ifdef CONFIG_BCM63XX_CPU_6338 37#ifdef CONFIG_BCM63XX_CPU_6338
24# ifdef bcm63xx_get_cpu_id 38# ifdef bcm63xx_get_cpu_id
25# undef bcm63xx_get_cpu_id 39# undef bcm63xx_get_cpu_id
@@ -102,13 +116,13 @@ enum bcm63xx_regs_set {
102 RSET_UART1, 116 RSET_UART1,
103 RSET_GPIO, 117 RSET_GPIO,
104 RSET_SPI, 118 RSET_SPI,
105 RSET_SPI2,
106 RSET_UDC0, 119 RSET_UDC0,
107 RSET_OHCI0, 120 RSET_OHCI0,
108 RSET_OHCI_PRIV, 121 RSET_OHCI_PRIV,
109 RSET_USBH_PRIV, 122 RSET_USBH_PRIV,
110 RSET_MPI, 123 RSET_MPI,
111 RSET_PCMCIA, 124 RSET_PCMCIA,
125 RSET_PCIE,
112 RSET_DSL, 126 RSET_DSL,
113 RSET_ENET0, 127 RSET_ENET0,
114 RSET_ENET1, 128 RSET_ENET1,
@@ -130,11 +144,17 @@ enum bcm63xx_regs_set {
130 RSET_PCMDMA, 144 RSET_PCMDMA,
131 RSET_PCMDMAC, 145 RSET_PCMDMAC,
132 RSET_PCMDMAS, 146 RSET_PCMDMAS,
147 RSET_RNG,
148 RSET_MISC
133}; 149};
134 150
135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 151#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
136#define RSET_DSL_SIZE 4096 152#define RSET_DSL_SIZE 4096
137#define RSET_WDT_SIZE 12 153#define RSET_WDT_SIZE 12
154#define BCM_6338_RSET_SPI_SIZE 64
155#define BCM_6348_RSET_SPI_SIZE 64
156#define BCM_6358_RSET_SPI_SIZE 1804
157#define BCM_6368_RSET_SPI_SIZE 1804
138#define RSET_ENET_SIZE 2048 158#define RSET_ENET_SIZE 2048
139#define RSET_ENETDMA_SIZE 2048 159#define RSET_ENETDMA_SIZE 2048
140#define RSET_ENETSW_SIZE 65536 160#define RSET_ENETSW_SIZE 65536
@@ -149,8 +169,53 @@ enum bcm63xx_regs_set {
149#define RSET_XTMDMA_SIZE 256 169#define RSET_XTMDMA_SIZE 256
150#define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) 170#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
151#define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) 171#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
172#define RSET_RNG_SIZE 20
152 173
153/* 174/*
175 * 6328 register sets base address
176 */
177#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
178#define BCM_6328_PERF_BASE (0xb0000000)
179#define BCM_6328_TIMER_BASE (0xb0000040)
180#define BCM_6328_WDT_BASE (0xb000005c)
181#define BCM_6328_UART0_BASE (0xb0000100)
182#define BCM_6328_UART1_BASE (0xb0000120)
183#define BCM_6328_GPIO_BASE (0xb0000080)
184#define BCM_6328_SPI_BASE (0xdeadbeef)
185#define BCM_6328_UDC0_BASE (0xdeadbeef)
186#define BCM_6328_USBDMA_BASE (0xdeadbeef)
187#define BCM_6328_OHCI0_BASE (0xdeadbeef)
188#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
189#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
190#define BCM_6328_MPI_BASE (0xdeadbeef)
191#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
192#define BCM_6328_PCIE_BASE (0xb0e40000)
193#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
194#define BCM_6328_DSL_BASE (0xb0001900)
195#define BCM_6328_UBUS_BASE (0xdeadbeef)
196#define BCM_6328_ENET0_BASE (0xdeadbeef)
197#define BCM_6328_ENET1_BASE (0xdeadbeef)
198#define BCM_6328_ENETDMA_BASE (0xb000d800)
199#define BCM_6328_ENETDMAC_BASE (0xb000da00)
200#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
201#define BCM_6328_ENETSW_BASE (0xb0e00000)
202#define BCM_6328_EHCI0_BASE (0x10002500)
203#define BCM_6328_SDRAM_BASE (0xdeadbeef)
204#define BCM_6328_MEMC_BASE (0xdeadbeef)
205#define BCM_6328_DDR_BASE (0xb0003000)
206#define BCM_6328_M2M_BASE (0xdeadbeef)
207#define BCM_6328_ATM_BASE (0xdeadbeef)
208#define BCM_6328_XTM_BASE (0xdeadbeef)
209#define BCM_6328_XTMDMA_BASE (0xb000b800)
210#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
211#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
212#define BCM_6328_PCM_BASE (0xb000a800)
213#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
214#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
215#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
216#define BCM_6328_RNG_BASE (0xdeadbeef)
217#define BCM_6328_MISC_BASE (0xb0001800)
218/*
154 * 6338 register sets base address 219 * 6338 register sets base address
155 */ 220 */
156#define BCM_6338_DSL_LMEM_BASE (0xfff00000) 221#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
@@ -162,7 +227,6 @@ enum bcm63xx_regs_set {
162#define BCM_6338_UART1_BASE (0xdeadbeef) 227#define BCM_6338_UART1_BASE (0xdeadbeef)
163#define BCM_6338_GPIO_BASE (0xfffe0400) 228#define BCM_6338_GPIO_BASE (0xfffe0400)
164#define BCM_6338_SPI_BASE (0xfffe0c00) 229#define BCM_6338_SPI_BASE (0xfffe0c00)
165#define BCM_6338_SPI2_BASE (0xdeadbeef)
166#define BCM_6338_UDC0_BASE (0xdeadbeef) 230#define BCM_6338_UDC0_BASE (0xdeadbeef)
167#define BCM_6338_USBDMA_BASE (0xfffe2400) 231#define BCM_6338_USBDMA_BASE (0xfffe2400)
168#define BCM_6338_OHCI0_BASE (0xdeadbeef) 232#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -170,6 +234,7 @@ enum bcm63xx_regs_set {
170#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 234#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
171#define BCM_6338_MPI_BASE (0xfffe3160) 235#define BCM_6338_MPI_BASE (0xfffe3160)
172#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 236#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
237#define BCM_6338_PCIE_BASE (0xdeadbeef)
173#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 238#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
174#define BCM_6338_DSL_BASE (0xfffe1000) 239#define BCM_6338_DSL_BASE (0xfffe1000)
175#define BCM_6338_UBUS_BASE (0xdeadbeef) 240#define BCM_6338_UBUS_BASE (0xdeadbeef)
@@ -193,6 +258,8 @@ enum bcm63xx_regs_set {
193#define BCM_6338_PCMDMA_BASE (0xdeadbeef) 258#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
194#define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 259#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
195#define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 260#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
261#define BCM_6338_RNG_BASE (0xdeadbeef)
262#define BCM_6338_MISC_BASE (0xdeadbeef)
196 263
197/* 264/*
198 * 6345 register sets base address 265 * 6345 register sets base address
@@ -206,7 +273,6 @@ enum bcm63xx_regs_set {
206#define BCM_6345_UART1_BASE (0xdeadbeef) 273#define BCM_6345_UART1_BASE (0xdeadbeef)
207#define BCM_6345_GPIO_BASE (0xfffe0400) 274#define BCM_6345_GPIO_BASE (0xfffe0400)
208#define BCM_6345_SPI_BASE (0xdeadbeef) 275#define BCM_6345_SPI_BASE (0xdeadbeef)
209#define BCM_6345_SPI2_BASE (0xdeadbeef)
210#define BCM_6345_UDC0_BASE (0xdeadbeef) 276#define BCM_6345_UDC0_BASE (0xdeadbeef)
211#define BCM_6345_USBDMA_BASE (0xfffe2800) 277#define BCM_6345_USBDMA_BASE (0xfffe2800)
212#define BCM_6345_ENET0_BASE (0xfffe1800) 278#define BCM_6345_ENET0_BASE (0xfffe1800)
@@ -216,6 +282,7 @@ enum bcm63xx_regs_set {
216#define BCM_6345_ENETSW_BASE (0xdeadbeef) 282#define BCM_6345_ENETSW_BASE (0xdeadbeef)
217#define BCM_6345_PCMCIA_BASE (0xfffe2028) 283#define BCM_6345_PCMCIA_BASE (0xfffe2028)
218#define BCM_6345_MPI_BASE (0xfffe2000) 284#define BCM_6345_MPI_BASE (0xfffe2000)
285#define BCM_6345_PCIE_BASE (0xdeadbeef)
219#define BCM_6345_OHCI0_BASE (0xfffe2100) 286#define BCM_6345_OHCI0_BASE (0xfffe2100)
220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 287#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 288#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
@@ -237,6 +304,8 @@ enum bcm63xx_regs_set {
237#define BCM_6345_PCMDMA_BASE (0xdeadbeef) 304#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
238#define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 305#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
239#define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 306#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
307#define BCM_6345_RNG_BASE (0xdeadbeef)
308#define BCM_6345_MISC_BASE (0xdeadbeef)
240 309
241/* 310/*
242 * 6348 register sets base address 311 * 6348 register sets base address
@@ -249,13 +318,13 @@ enum bcm63xx_regs_set {
249#define BCM_6348_UART1_BASE (0xdeadbeef) 318#define BCM_6348_UART1_BASE (0xdeadbeef)
250#define BCM_6348_GPIO_BASE (0xfffe0400) 319#define BCM_6348_GPIO_BASE (0xfffe0400)
251#define BCM_6348_SPI_BASE (0xfffe0c00) 320#define BCM_6348_SPI_BASE (0xfffe0c00)
252#define BCM_6348_SPI2_BASE (0xdeadbeef)
253#define BCM_6348_UDC0_BASE (0xfffe1000) 321#define BCM_6348_UDC0_BASE (0xfffe1000)
254#define BCM_6348_OHCI0_BASE (0xfffe1b00) 322#define BCM_6348_OHCI0_BASE (0xfffe1b00)
255#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 323#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
256#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 324#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
257#define BCM_6348_MPI_BASE (0xfffe2000) 325#define BCM_6348_MPI_BASE (0xfffe2000)
258#define BCM_6348_PCMCIA_BASE (0xfffe2054) 326#define BCM_6348_PCMCIA_BASE (0xfffe2054)
327#define BCM_6348_PCIE_BASE (0xdeadbeef)
259#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 328#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
260#define BCM_6348_M2M_BASE (0xfffe2800) 329#define BCM_6348_M2M_BASE (0xfffe2800)
261#define BCM_6348_DSL_BASE (0xfffe3000) 330#define BCM_6348_DSL_BASE (0xfffe3000)
@@ -278,6 +347,8 @@ enum bcm63xx_regs_set {
278#define BCM_6348_PCMDMA_BASE (0xdeadbeef) 347#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
279#define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 348#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
280#define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 349#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
350#define BCM_6348_RNG_BASE (0xdeadbeef)
351#define BCM_6348_MISC_BASE (0xdeadbeef)
281 352
282/* 353/*
283 * 6358 register sets base address 354 * 6358 register sets base address
@@ -289,14 +360,14 @@ enum bcm63xx_regs_set {
289#define BCM_6358_UART0_BASE (0xfffe0100) 360#define BCM_6358_UART0_BASE (0xfffe0100)
290#define BCM_6358_UART1_BASE (0xfffe0120) 361#define BCM_6358_UART1_BASE (0xfffe0120)
291#define BCM_6358_GPIO_BASE (0xfffe0080) 362#define BCM_6358_GPIO_BASE (0xfffe0080)
292#define BCM_6358_SPI_BASE (0xdeadbeef) 363#define BCM_6358_SPI_BASE (0xfffe0800)
293#define BCM_6358_SPI2_BASE (0xfffe0800)
294#define BCM_6358_UDC0_BASE (0xfffe0800) 364#define BCM_6358_UDC0_BASE (0xfffe0800)
295#define BCM_6358_OHCI0_BASE (0xfffe1400) 365#define BCM_6358_OHCI0_BASE (0xfffe1400)
296#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 366#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
297#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 367#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
298#define BCM_6358_MPI_BASE (0xfffe1000) 368#define BCM_6358_MPI_BASE (0xfffe1000)
299#define BCM_6358_PCMCIA_BASE (0xfffe1054) 369#define BCM_6358_PCMCIA_BASE (0xfffe1054)
370#define BCM_6358_PCIE_BASE (0xdeadbeef)
300#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 371#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
301#define BCM_6358_M2M_BASE (0xdeadbeef) 372#define BCM_6358_M2M_BASE (0xdeadbeef)
302#define BCM_6358_DSL_BASE (0xfffe3000) 373#define BCM_6358_DSL_BASE (0xfffe3000)
@@ -319,6 +390,8 @@ enum bcm63xx_regs_set {
319#define BCM_6358_PCMDMA_BASE (0xfffe1800) 390#define BCM_6358_PCMDMA_BASE (0xfffe1800)
320#define BCM_6358_PCMDMAC_BASE (0xfffe1900) 391#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 392#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
393#define BCM_6358_RNG_BASE (0xdeadbeef)
394#define BCM_6358_MISC_BASE (0xdeadbeef)
322 395
323 396
324/* 397/*
@@ -331,14 +404,14 @@ enum bcm63xx_regs_set {
331#define BCM_6368_UART0_BASE (0xb0000100) 404#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120) 405#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080) 406#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef) 407#define BCM_6368_SPI_BASE (0xb0000800)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef) 408#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600) 409#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) 410#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700) 411#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000) 412#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054) 413#define BCM_6368_PCMCIA_BASE (0xb0001054)
414#define BCM_6368_PCIE_BASE (0xdeadbeef)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) 415#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef) 416#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef) 417#define BCM_6368_DSL_BASE (0xdeadbeef)
@@ -361,6 +434,8 @@ enum bcm63xx_regs_set {
361#define BCM_6368_PCMDMA_BASE (0xb0005800) 434#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00) 435#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00) 436#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
437#define BCM_6368_RNG_BASE (0xb0004180)
438#define BCM_6368_MISC_BASE (0xdeadbeef)
364 439
365 440
366extern const unsigned long *bcm63xx_regs_base; 441extern const unsigned long *bcm63xx_regs_base;
@@ -379,13 +454,13 @@ extern const unsigned long *bcm63xx_regs_base;
379 __GEN_RSET_BASE(__cpu, UART1) \ 454 __GEN_RSET_BASE(__cpu, UART1) \
380 __GEN_RSET_BASE(__cpu, GPIO) \ 455 __GEN_RSET_BASE(__cpu, GPIO) \
381 __GEN_RSET_BASE(__cpu, SPI) \ 456 __GEN_RSET_BASE(__cpu, SPI) \
382 __GEN_RSET_BASE(__cpu, SPI2) \
383 __GEN_RSET_BASE(__cpu, UDC0) \ 457 __GEN_RSET_BASE(__cpu, UDC0) \
384 __GEN_RSET_BASE(__cpu, OHCI0) \ 458 __GEN_RSET_BASE(__cpu, OHCI0) \
385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ 459 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \ 460 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
387 __GEN_RSET_BASE(__cpu, MPI) \ 461 __GEN_RSET_BASE(__cpu, MPI) \
388 __GEN_RSET_BASE(__cpu, PCMCIA) \ 462 __GEN_RSET_BASE(__cpu, PCMCIA) \
463 __GEN_RSET_BASE(__cpu, PCIE) \
389 __GEN_RSET_BASE(__cpu, DSL) \ 464 __GEN_RSET_BASE(__cpu, DSL) \
390 __GEN_RSET_BASE(__cpu, ENET0) \ 465 __GEN_RSET_BASE(__cpu, ENET0) \
391 __GEN_RSET_BASE(__cpu, ENET1) \ 466 __GEN_RSET_BASE(__cpu, ENET1) \
@@ -407,6 +482,8 @@ extern const unsigned long *bcm63xx_regs_base;
407 __GEN_RSET_BASE(__cpu, PCMDMA) \ 482 __GEN_RSET_BASE(__cpu, PCMDMA) \
408 __GEN_RSET_BASE(__cpu, PCMDMAC) \ 483 __GEN_RSET_BASE(__cpu, PCMDMAC) \
409 __GEN_RSET_BASE(__cpu, PCMDMAS) \ 484 __GEN_RSET_BASE(__cpu, PCMDMAS) \
485 __GEN_RSET_BASE(__cpu, RNG) \
486 __GEN_RSET_BASE(__cpu, MISC) \
410 } 487 }
411 488
412#define __GEN_CPU_REGS_TABLE(__cpu) \ 489#define __GEN_CPU_REGS_TABLE(__cpu) \
@@ -418,13 +495,13 @@ extern const unsigned long *bcm63xx_regs_base;
418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 495 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 496 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 497 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 498 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 499 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 500 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ 501 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ 502 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ 503 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
504 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ 505 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ 506 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ 507 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
@@ -446,6 +523,8 @@ extern const unsigned long *bcm63xx_regs_base;
446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ 523 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 524 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 525 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
526 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
527 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
449 528
450 529
451static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 530static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
@@ -453,6 +532,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
453#ifdef BCMCPU_RUNTIME_DETECT 532#ifdef BCMCPU_RUNTIME_DETECT
454 return bcm63xx_regs_base[set]; 533 return bcm63xx_regs_base[set];
455#else 534#else
535#ifdef CONFIG_BCM63XX_CPU_6328
536 __GEN_RSET(6328)
537#endif
456#ifdef CONFIG_BCM63XX_CPU_6338 538#ifdef CONFIG_BCM63XX_CPU_6338
457 __GEN_RSET(6338) 539 __GEN_RSET(6338)
458#endif 540#endif
@@ -478,6 +560,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
478 */ 560 */
479enum bcm63xx_irq { 561enum bcm63xx_irq {
480 IRQ_TIMER = 0, 562 IRQ_TIMER = 0,
563 IRQ_SPI,
481 IRQ_UART0, 564 IRQ_UART0,
482 IRQ_UART1, 565 IRQ_UART1,
483 IRQ_DSL, 566 IRQ_DSL,
@@ -506,9 +589,51 @@ enum bcm63xx_irq {
506}; 589};
507 590
508/* 591/*
592 * 6328 irqs
593 */
594#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
595
596#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
597#define BCM_6328_SPI_IRQ 0
598#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
599#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
600#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
601#define BCM_6328_UDC0_IRQ 0
602#define BCM_6328_ENET0_IRQ 0
603#define BCM_6328_ENET1_IRQ 0
604#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
605#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
606#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
607#define BCM_6328_PCMCIA_IRQ 0
608#define BCM_6328_ENET0_RXDMA_IRQ 0
609#define BCM_6328_ENET0_TXDMA_IRQ 0
610#define BCM_6328_ENET1_RXDMA_IRQ 0
611#define BCM_6328_ENET1_TXDMA_IRQ 0
612#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
613#define BCM_6328_ATM_IRQ 0
614#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
615#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
616#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
617#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
618#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
619#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
620#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
621#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
622#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
623#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
624
625#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
626#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
627#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
628#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
629#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
630#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
631
632/*
509 * 6338 irqs 633 * 6338 irqs
510 */ 634 */
511#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 635#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
636#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
512#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 637#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
513#define BCM_6338_UART1_IRQ 0 638#define BCM_6338_UART1_IRQ 0
514#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 639#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
@@ -539,6 +664,7 @@ enum bcm63xx_irq {
539 * 6345 irqs 664 * 6345 irqs
540 */ 665 */
541#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 666#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
667#define BCM_6345_SPI_IRQ 0
542#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 668#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
543#define BCM_6345_UART1_IRQ 0 669#define BCM_6345_UART1_IRQ 0
544#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 670#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
@@ -569,6 +695,7 @@ enum bcm63xx_irq {
569 * 6348 irqs 695 * 6348 irqs
570 */ 696 */
571#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 697#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
698#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
572#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 699#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
573#define BCM_6348_UART1_IRQ 0 700#define BCM_6348_UART1_IRQ 0
574#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 701#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -599,6 +726,7 @@ enum bcm63xx_irq {
599 * 6358 irqs 726 * 6358 irqs
600 */ 727 */
601#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 728#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
729#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
602#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 730#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
603#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 731#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
604#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 732#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
@@ -638,6 +766,7 @@ enum bcm63xx_irq {
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 766#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639 767
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 768#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
769#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 770#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 771#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 772#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -677,6 +806,7 @@ extern const int *bcm63xx_irqs;
677 806
678#define __GEN_CPU_IRQ_TABLE(__cpu) \ 807#define __GEN_CPU_IRQ_TABLE(__cpu) \
679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ 808 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
809 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ 810 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ 811 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ 812 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
new file mode 100644
index 00000000000..354b8481ec4
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
@@ -0,0 +1,12 @@
1#ifndef __BCM63XX_FLASH_H
2#define __BCM63XX_FLASH_H
3
4enum {
5 BCM63XX_FLASH_TYPE_PARALLEL,
6 BCM63XX_FLASH_TYPE_SERIAL,
7 BCM63XX_FLASH_TYPE_NAND,
8};
9
10int __init bcm63xx_flash_register(void);
11
12#endif /* __BCM63XX_FLASH_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
new file mode 100644
index 00000000000..7d98dbe5d4b
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -0,0 +1,89 @@
1#ifndef BCM63XX_DEV_SPI_H
2#define BCM63XX_DEV_SPI_H
3
4#include <linux/types.h>
5#include <bcm63xx_io.h>
6#include <bcm63xx_regs.h>
7
8int __init bcm63xx_spi_register(void);
9
10struct bcm63xx_spi_pdata {
11 unsigned int fifo_size;
12 int bus_num;
13 int num_chipselect;
14 u32 speed_hz;
15};
16
17enum bcm63xx_regs_spi {
18 SPI_CMD,
19 SPI_INT_STATUS,
20 SPI_INT_MASK_ST,
21 SPI_INT_MASK,
22 SPI_ST,
23 SPI_CLK_CFG,
24 SPI_FILL_BYTE,
25 SPI_MSG_TAIL,
26 SPI_RX_TAIL,
27 SPI_MSG_CTL,
28 SPI_MSG_DATA,
29 SPI_RX_DATA,
30};
31
32#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
33 case SPI_## __rset: \
34 return SPI_## __cpu ##_## __rset;
35
36#define __GEN_SPI_RSET(__cpu) \
37 switch (reg) { \
38 __GEN_SPI_RSET_BASE(__cpu, CMD) \
39 __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
40 __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
41 __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
42 __GEN_SPI_RSET_BASE(__cpu, ST) \
43 __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
44 __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
45 __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
46 __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
47 __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
48 __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
49 __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
50 }
51
52#define __GEN_SPI_REGS_TABLE(__cpu) \
53 [SPI_CMD] = SPI_## __cpu ##_CMD, \
54 [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
55 [SPI_INT_MASK_ST] = SPI_## __cpu ##_INT_MASK_ST, \
56 [SPI_INT_MASK] = SPI_## __cpu ##_INT_MASK, \
57 [SPI_ST] = SPI_## __cpu ##_ST, \
58 [SPI_CLK_CFG] = SPI_## __cpu ##_CLK_CFG, \
59 [SPI_FILL_BYTE] = SPI_## __cpu ##_FILL_BYTE, \
60 [SPI_MSG_TAIL] = SPI_## __cpu ##_MSG_TAIL, \
61 [SPI_RX_TAIL] = SPI_## __cpu ##_RX_TAIL, \
62 [SPI_MSG_CTL] = SPI_## __cpu ##_MSG_CTL, \
63 [SPI_MSG_DATA] = SPI_## __cpu ##_MSG_DATA, \
64 [SPI_RX_DATA] = SPI_## __cpu ##_RX_DATA,
65
66static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
67{
68#ifdef BCMCPU_RUNTIME_DETECT
69 extern const unsigned long *bcm63xx_regs_spi;
70
71 return bcm63xx_regs_spi[reg];
72#else
73#ifdef CONFIG_BCM63XX_CPU_6338
74 __GEN_SPI_RSET(6338)
75#endif
76#ifdef CONFIG_BCM63XX_CPU_6348
77 __GEN_SPI_RSET(6348)
78#endif
79#ifdef CONFIG_BCM63XX_CPU_6358
80 __GEN_SPI_RSET(6358)
81#endif
82#ifdef CONFIG_BCM63XX_CPU_6368
83 __GEN_SPI_RSET(6368)
84#endif
85#endif
86 return 0;
87}
88
89#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 1d7dd96aa46..0a9891f7580 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
9static inline unsigned long bcm63xx_gpio_count(void) 9static inline unsigned long bcm63xx_gpio_count(void)
10{ 10{
11 switch (bcm63xx_get_cpu_id()) { 11 switch (bcm63xx_get_cpu_id()) {
12 case BCM6328_CPU_ID:
13 return 32;
12 case BCM6358_CPU_ID: 14 case BCM6358_CPU_ID:
13 return 40; 15 return 40;
14 case BCM6338_CPU_ID: 16 case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 72477a6441d..9203d90e610 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -40,6 +40,10 @@
40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ 40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
41 BCM_CB_MEM_SIZE - 1) 41 BCM_CB_MEM_SIZE - 1)
42 42
43#define BCM_PCIE_MEM_BASE_PA 0x10f00000
44#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
45#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
46 BCM_PCIE_MEM_SIZE - 1)
43 47
44/* 48/*
45 * Internal registers are accessed through KSEG3 49 * Internal registers are accessed through KSEG3
@@ -85,11 +89,15 @@
85#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o)) 89#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
86#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) 90#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
87#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) 91#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
92#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
93#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
88#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) 94#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
89#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o)) 95#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
90#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o)) 96#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
91#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o)) 97#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
92#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) 98#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
93#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o)) 99#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
100#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
101#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
94 102
95#endif /* ! BCM63XX_IO_H_ */ 103#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index fdcd78ca1b0..4ccc2a748af 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,30 @@
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
17 17
18#define CKCTL_6328_PHYMIPS_EN (1 << 0)
19#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
21#define CKCTL_6328_ADSL_EN (1 << 3)
22#define CKCTL_6328_MIPS_EN (1 << 4)
23#define CKCTL_6328_SAR_EN (1 << 5)
24#define CKCTL_6328_PCM_EN (1 << 6)
25#define CKCTL_6328_USBD_EN (1 << 7)
26#define CKCTL_6328_USBH_EN (1 << 8)
27#define CKCTL_6328_HSSPI_EN (1 << 9)
28#define CKCTL_6328_PCIE_EN (1 << 10)
29#define CKCTL_6328_ROBOSW_EN (1 << 11)
30
31#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
32 CKCTL_6328_ADSL_QPROC_EN | \
33 CKCTL_6328_ADSL_AFE_EN | \
34 CKCTL_6328_ADSL_EN | \
35 CKCTL_6328_SAR_EN | \
36 CKCTL_6328_PCM_EN | \
37 CKCTL_6328_USBD_EN | \
38 CKCTL_6328_USBH_EN | \
39 CKCTL_6328_ROBOSW_EN | \
40 CKCTL_6328_PCIE_EN)
41
18#define CKCTL_6338_ADSLPHY_EN (1 << 0) 42#define CKCTL_6338_ADSLPHY_EN (1 << 0)
19#define CKCTL_6338_MPI_EN (1 << 1) 43#define CKCTL_6338_MPI_EN (1 << 1)
20#define CKCTL_6338_DRAM_EN (1 << 2) 44#define CKCTL_6338_DRAM_EN (1 << 2)
@@ -90,35 +114,36 @@
90#define CKCTL_6368_PHYMIPS_EN (1 << 6) 114#define CKCTL_6368_PHYMIPS_EN (1 << 6)
91#define CKCTL_6368_SWPKT_USB_EN (1 << 7) 115#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
92#define CKCTL_6368_SWPKT_SAR_EN (1 << 8) 116#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
93#define CKCTL_6368_SPI_CLK_EN (1 << 9) 117#define CKCTL_6368_SPI_EN (1 << 9)
94#define CKCTL_6368_USBD_CLK_EN (1 << 10) 118#define CKCTL_6368_USBD_EN (1 << 10)
95#define CKCTL_6368_SAR_CLK_EN (1 << 11) 119#define CKCTL_6368_SAR_EN (1 << 11)
96#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12) 120#define CKCTL_6368_ROBOSW_EN (1 << 12)
97#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13) 121#define CKCTL_6368_UTOPIA_EN (1 << 13)
98#define CKCTL_6368_PCM_CLK_EN (1 << 14) 122#define CKCTL_6368_PCM_EN (1 << 14)
99#define CKCTL_6368_USBH_CLK_EN (1 << 15) 123#define CKCTL_6368_USBH_EN (1 << 15)
100#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) 124#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
101#define CKCTL_6368_NAND_CLK_EN (1 << 17) 125#define CKCTL_6368_NAND_EN (1 << 17)
102#define CKCTL_6368_IPSEC_CLK_EN (1 << 18) 126#define CKCTL_6368_IPSEC_EN (1 << 18)
103 127
104#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ 128#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
105 CKCTL_6368_SWPKT_SAR_EN | \ 129 CKCTL_6368_SWPKT_SAR_EN | \
106 CKCTL_6368_SPI_CLK_EN | \ 130 CKCTL_6368_SPI_EN | \
107 CKCTL_6368_USBD_CLK_EN | \ 131 CKCTL_6368_USBD_EN | \
108 CKCTL_6368_SAR_CLK_EN | \ 132 CKCTL_6368_SAR_EN | \
109 CKCTL_6368_ROBOSW_CLK_EN | \ 133 CKCTL_6368_ROBOSW_EN | \
110 CKCTL_6368_UTOPIA_CLK_EN | \ 134 CKCTL_6368_UTOPIA_EN | \
111 CKCTL_6368_PCM_CLK_EN | \ 135 CKCTL_6368_PCM_EN | \
112 CKCTL_6368_USBH_CLK_EN | \ 136 CKCTL_6368_USBH_EN | \
113 CKCTL_6368_DISABLE_GLESS_EN | \ 137 CKCTL_6368_DISABLE_GLESS_EN | \
114 CKCTL_6368_NAND_CLK_EN | \ 138 CKCTL_6368_NAND_EN | \
115 CKCTL_6368_IPSEC_CLK_EN) 139 CKCTL_6368_IPSEC_EN)
116 140
117/* System PLL Control register */ 141/* System PLL Control register */
118#define PERF_SYS_PLL_CTL_REG 0x8 142#define PERF_SYS_PLL_CTL_REG 0x8
119#define SYS_PLL_SOFT_RESET 0x1 143#define SYS_PLL_SOFT_RESET 0x1
120 144
121/* Interrupt Mask register */ 145/* Interrupt Mask register */
146#define PERF_IRQMASK_6328_REG 0x20
122#define PERF_IRQMASK_6338_REG 0xc 147#define PERF_IRQMASK_6338_REG 0xc
123#define PERF_IRQMASK_6345_REG 0xc 148#define PERF_IRQMASK_6345_REG 0xc
124#define PERF_IRQMASK_6348_REG 0xc 149#define PERF_IRQMASK_6348_REG 0xc
@@ -126,6 +151,7 @@
126#define PERF_IRQMASK_6368_REG 0x20 151#define PERF_IRQMASK_6368_REG 0x20
127 152
128/* Interrupt Status register */ 153/* Interrupt Status register */
154#define PERF_IRQSTAT_6328_REG 0x28
129#define PERF_IRQSTAT_6338_REG 0x10 155#define PERF_IRQSTAT_6338_REG 0x10
130#define PERF_IRQSTAT_6345_REG 0x10 156#define PERF_IRQSTAT_6345_REG 0x10
131#define PERF_IRQSTAT_6348_REG 0x10 157#define PERF_IRQSTAT_6348_REG 0x10
@@ -133,6 +159,7 @@
133#define PERF_IRQSTAT_6368_REG 0x28 159#define PERF_IRQSTAT_6368_REG 0x28
134 160
135/* External Interrupt Configuration register */ 161/* External Interrupt Configuration register */
162#define PERF_EXTIRQ_CFG_REG_6328 0x18
136#define PERF_EXTIRQ_CFG_REG_6338 0x14 163#define PERF_EXTIRQ_CFG_REG_6338 0x14
137#define PERF_EXTIRQ_CFG_REG_6348 0x14 164#define PERF_EXTIRQ_CFG_REG_6348 0x14
138#define PERF_EXTIRQ_CFG_REG_6358 0x14 165#define PERF_EXTIRQ_CFG_REG_6358 0x14
@@ -162,8 +189,21 @@
162 189
163/* Soft Reset register */ 190/* Soft Reset register */
164#define PERF_SOFTRESET_REG 0x28 191#define PERF_SOFTRESET_REG 0x28
192#define PERF_SOFTRESET_6328_REG 0x10
165#define PERF_SOFTRESET_6368_REG 0x10 193#define PERF_SOFTRESET_6368_REG 0x10
166 194
195#define SOFTRESET_6328_SPI_MASK (1 << 0)
196#define SOFTRESET_6328_EPHY_MASK (1 << 1)
197#define SOFTRESET_6328_SAR_MASK (1 << 2)
198#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
199#define SOFTRESET_6328_USBS_MASK (1 << 4)
200#define SOFTRESET_6328_USBH_MASK (1 << 5)
201#define SOFTRESET_6328_PCM_MASK (1 << 6)
202#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
203#define SOFTRESET_6328_PCIE_MASK (1 << 8)
204#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
205#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
206
167#define SOFTRESET_6338_SPI_MASK (1 << 0) 207#define SOFTRESET_6338_SPI_MASK (1 << 0)
168#define SOFTRESET_6338_ENET_MASK (1 << 2) 208#define SOFTRESET_6338_ENET_MASK (1 << 2)
169#define SOFTRESET_6338_USBH_MASK (1 << 3) 209#define SOFTRESET_6338_USBH_MASK (1 << 3)
@@ -307,6 +347,8 @@
307/* Watchdog reset length register */ 347/* Watchdog reset length register */
308#define WDT_RSTLEN_REG 0x8 348#define WDT_RSTLEN_REG 0x8
309 349
350/* Watchdog soft reset register (BCM6328 only) */
351#define WDT_SOFTRESET_REG 0xc
310 352
311/************************************************************************* 353/*************************************************************************
312 * _REG relative to RSET_UARTx 354 * _REG relative to RSET_UARTx
@@ -507,6 +549,15 @@
507#define GPIO_BASEMODE_6368_MASK 0x7 549#define GPIO_BASEMODE_6368_MASK 0x7
508/* those bits must be kept as read in gpio basemode register*/ 550/* those bits must be kept as read in gpio basemode register*/
509 551
552#define GPIO_STRAPBUS_REG 0x40
553#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
554#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
555#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
556#define STRAPBUS_6368_BOOT_SEL_NAND 0
557#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
558#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
559
560
510/************************************************************************* 561/*************************************************************************
511 * _REG relative to RSET_ENET 562 * _REG relative to RSET_ENET
512 *************************************************************************/ 563 *************************************************************************/
@@ -924,6 +975,8 @@
924 * _REG relative to RSET_DDR 975 * _REG relative to RSET_DDR
925 *************************************************************************/ 976 *************************************************************************/
926 977
978#define DDR_CSEND_REG 0x8
979
927#define DDR_DMIPSPLLCFG_REG 0x18 980#define DDR_DMIPSPLLCFG_REG 0x18
928#define DMIPSPLLCFG_M1_SHIFT 0 981#define DMIPSPLLCFG_M1_SHIFT 0
929#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 982#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
@@ -973,4 +1026,201 @@
973#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) 1026#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
974#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) 1027#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
975 1028
1029/*************************************************************************
1030 * _REG relative to RSET_RNG
1031 *************************************************************************/
1032
1033#define RNG_CTRL 0x00
1034#define RNG_EN (1 << 0)
1035
1036#define RNG_STAT 0x04
1037#define RNG_AVAIL_MASK (0xff000000)
1038
1039#define RNG_DATA 0x08
1040#define RNG_THRES 0x0c
1041#define RNG_MASK 0x10
1042
1043/*************************************************************************
1044 * _REG relative to RSET_SPI
1045 *************************************************************************/
1046
1047/* BCM 6338 SPI core */
1048#define SPI_6338_CMD 0x00 /* 16-bits register */
1049#define SPI_6338_INT_STATUS 0x02
1050#define SPI_6338_INT_MASK_ST 0x03
1051#define SPI_6338_INT_MASK 0x04
1052#define SPI_6338_ST 0x05
1053#define SPI_6338_CLK_CFG 0x06
1054#define SPI_6338_FILL_BYTE 0x07
1055#define SPI_6338_MSG_TAIL 0x09
1056#define SPI_6338_RX_TAIL 0x0b
1057#define SPI_6338_MSG_CTL 0x40
1058#define SPI_6338_MSG_DATA 0x41
1059#define SPI_6338_MSG_DATA_SIZE 0x3f
1060#define SPI_6338_RX_DATA 0x80
1061#define SPI_6338_RX_DATA_SIZE 0x3f
1062
1063/* BCM 6348 SPI core */
1064#define SPI_6348_CMD 0x00 /* 16-bits register */
1065#define SPI_6348_INT_STATUS 0x02
1066#define SPI_6348_INT_MASK_ST 0x03
1067#define SPI_6348_INT_MASK 0x04
1068#define SPI_6348_ST 0x05
1069#define SPI_6348_CLK_CFG 0x06
1070#define SPI_6348_FILL_BYTE 0x07
1071#define SPI_6348_MSG_TAIL 0x09
1072#define SPI_6348_RX_TAIL 0x0b
1073#define SPI_6348_MSG_CTL 0x40
1074#define SPI_6348_MSG_DATA 0x41
1075#define SPI_6348_MSG_DATA_SIZE 0x3f
1076#define SPI_6348_RX_DATA 0x80
1077#define SPI_6348_RX_DATA_SIZE 0x3f
1078
1079/* BCM 6358 SPI core */
1080#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1081#define SPI_6358_MSG_DATA 0x02
1082#define SPI_6358_MSG_DATA_SIZE 0x21e
1083#define SPI_6358_RX_DATA 0x400
1084#define SPI_6358_RX_DATA_SIZE 0x220
1085#define SPI_6358_CMD 0x700 /* 16-bits register */
1086#define SPI_6358_INT_STATUS 0x702
1087#define SPI_6358_INT_MASK_ST 0x703
1088#define SPI_6358_INT_MASK 0x704
1089#define SPI_6358_ST 0x705
1090#define SPI_6358_CLK_CFG 0x706
1091#define SPI_6358_FILL_BYTE 0x707
1092#define SPI_6358_MSG_TAIL 0x709
1093#define SPI_6358_RX_TAIL 0x70B
1094
1095/* BCM 6358 SPI core */
1096#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1097#define SPI_6368_MSG_DATA 0x02
1098#define SPI_6368_MSG_DATA_SIZE 0x21e
1099#define SPI_6368_RX_DATA 0x400
1100#define SPI_6368_RX_DATA_SIZE 0x220
1101#define SPI_6368_CMD 0x700 /* 16-bits register */
1102#define SPI_6368_INT_STATUS 0x702
1103#define SPI_6368_INT_MASK_ST 0x703
1104#define SPI_6368_INT_MASK 0x704
1105#define SPI_6368_ST 0x705
1106#define SPI_6368_CLK_CFG 0x706
1107#define SPI_6368_FILL_BYTE 0x707
1108#define SPI_6368_MSG_TAIL 0x709
1109#define SPI_6368_RX_TAIL 0x70B
1110
1111/* Shared SPI definitions */
1112
1113/* Message configuration */
1114#define SPI_FD_RW 0x00
1115#define SPI_HD_W 0x01
1116#define SPI_HD_R 0x02
1117#define SPI_BYTE_CNT_SHIFT 0
1118#define SPI_MSG_TYPE_SHIFT 14
1119
1120/* Command */
1121#define SPI_CMD_NOOP 0x00
1122#define SPI_CMD_SOFT_RESET 0x01
1123#define SPI_CMD_HARD_RESET 0x02
1124#define SPI_CMD_START_IMMEDIATE 0x03
1125#define SPI_CMD_COMMAND_SHIFT 0
1126#define SPI_CMD_COMMAND_MASK 0x000f
1127#define SPI_CMD_DEVICE_ID_SHIFT 4
1128#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1129#define SPI_CMD_ONE_BYTE_SHIFT 11
1130#define SPI_CMD_ONE_WIRE_SHIFT 12
1131#define SPI_DEV_ID_0 0
1132#define SPI_DEV_ID_1 1
1133#define SPI_DEV_ID_2 2
1134#define SPI_DEV_ID_3 3
1135
1136/* Interrupt mask */
1137#define SPI_INTR_CMD_DONE 0x01
1138#define SPI_INTR_RX_OVERFLOW 0x02
1139#define SPI_INTR_TX_UNDERFLOW 0x04
1140#define SPI_INTR_TX_OVERFLOW 0x08
1141#define SPI_INTR_RX_UNDERFLOW 0x10
1142#define SPI_INTR_CLEAR_ALL 0x1f
1143
1144/* Status */
1145#define SPI_RX_EMPTY 0x02
1146#define SPI_CMD_BUSY 0x04
1147#define SPI_SERIAL_BUSY 0x08
1148
1149/* Clock configuration */
1150#define SPI_CLK_20MHZ 0x00
1151#define SPI_CLK_0_391MHZ 0x01
1152#define SPI_CLK_0_781MHZ 0x02 /* default */
1153#define SPI_CLK_1_563MHZ 0x03
1154#define SPI_CLK_3_125MHZ 0x04
1155#define SPI_CLK_6_250MHZ 0x05
1156#define SPI_CLK_12_50MHZ 0x06
1157#define SPI_CLK_MASK 0x07
1158#define SPI_SSOFFTIME_MASK 0x38
1159#define SPI_SSOFFTIME_SHIFT 3
1160#define SPI_BYTE_SWAP 0x80
1161
1162/*************************************************************************
1163 * _REG relative to RSET_MISC
1164 *************************************************************************/
1165#define MISC_SERDES_CTRL_REG 0x0
1166#define SERDES_PCIE_EN (1 << 0)
1167#define SERDES_PCIE_EXD_EN (1 << 15)
1168
1169#define MISC_STRAPBUS_6328_REG 0x240
1170#define STRAPBUS_6328_FCVO_SHIFT 7
1171#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1172#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1173#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1174
1175/*************************************************************************
1176 * _REG relative to RSET_PCIE
1177 *************************************************************************/
1178
1179#define PCIE_CONFIG2_REG 0x408
1180#define CONFIG2_BAR1_SIZE_EN 1
1181#define CONFIG2_BAR1_SIZE_MASK 0xf
1182
1183#define PCIE_IDVAL3_REG 0x43c
1184#define IDVAL3_CLASS_CODE_MASK 0xffffff
1185#define IDVAL3_SUBCLASS_SHIFT 8
1186#define IDVAL3_CLASS_SHIFT 16
1187
1188#define PCIE_DLSTATUS_REG 0x1048
1189#define DLSTATUS_PHYLINKUP (1 << 13)
1190
1191#define PCIE_BRIDGE_OPT1_REG 0x2820
1192#define OPT1_RD_BE_OPT_EN (1 << 7)
1193#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
1194#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
1195#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
1196
1197#define PCIE_BRIDGE_OPT2_REG 0x2824
1198#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
1199#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
1200#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
1201#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
1202#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1203
1204#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1205#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1206#define BASEMASK_REMAP_EN (1 << 0)
1207#define BASEMASK_SWAP_EN (1 << 1)
1208#define BASEMASK_MASK_SHIFT 4
1209#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1210#define BASEMASK_BASE_SHIFT 20
1211#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1212
1213#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1214#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1215#define REBASE_ADDR_BASE_SHIFT 20
1216#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1217
1218#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1219#define PCIE_RC_INT_A (1 << 0)
1220#define PCIE_RC_INT_B (1 << 1)
1221#define PCIE_RC_INT_C (1 << 2)
1222#define PCIE_RC_INT_D (1 << 3)
1223
1224#define PCIE_DEVICE_OFFSET 0x8000
1225
976#endif /* BCM63XX_REGS_H_ */ 1226#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index ef94ba73646..30931c42379 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
18 if (offset >= 0xfff00000) 18 if (offset >= 0xfff00000)
19 return 1; 19 return 1;
20 break; 20 break;
21 case BCM6328_CPU_ID:
21 case BCM6368_CPU_ID: 22 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000) 23 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1; 24 return 1;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 5b05f186e39..418992042f6 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -41,61 +41,26 @@ enum octeon_irq {
41 OCTEON_IRQ_TWSI, 41 OCTEON_IRQ_TWSI,
42 OCTEON_IRQ_TWSI2, 42 OCTEON_IRQ_TWSI2,
43 OCTEON_IRQ_RML, 43 OCTEON_IRQ_RML,
44 OCTEON_IRQ_TRACE0,
45 OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
46 OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
47 OCTEON_IRQ_KEY_ZERO,
48 OCTEON_IRQ_TIMER0, 44 OCTEON_IRQ_TIMER0,
49 OCTEON_IRQ_TIMER1, 45 OCTEON_IRQ_TIMER1,
50 OCTEON_IRQ_TIMER2, 46 OCTEON_IRQ_TIMER2,
51 OCTEON_IRQ_TIMER3, 47 OCTEON_IRQ_TIMER3,
52 OCTEON_IRQ_USB0, 48 OCTEON_IRQ_USB0,
53 OCTEON_IRQ_USB1, 49 OCTEON_IRQ_USB1,
54 OCTEON_IRQ_PCM,
55 OCTEON_IRQ_MPI,
56 OCTEON_IRQ_POWIQ,
57 OCTEON_IRQ_IPDPPTHR,
58 OCTEON_IRQ_MII0, 50 OCTEON_IRQ_MII0,
59 OCTEON_IRQ_MII1, 51 OCTEON_IRQ_MII1,
60 OCTEON_IRQ_BOOTDMA, 52 OCTEON_IRQ_BOOTDMA,
61 53#ifndef CONFIG_PCI_MSI
62 OCTEON_IRQ_NAND, 54 OCTEON_IRQ_LAST = 127
63 OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ 55#endif
64 OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
65 OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
66 OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
67 OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
68 OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
69 OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
70 OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
71 OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
72 OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
73 OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
74 OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
75 OCTEON_IRQ_DFA, /* Summary of DFA */
76 OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
77 OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
78 OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
79 OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
80 OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
81 OCTEON_IRQ_PTP,
82 OCTEON_IRQ_PEM0,
83 OCTEON_IRQ_PEM1,
84 OCTEON_IRQ_SRIO0,
85 OCTEON_IRQ_SRIO1,
86 OCTEON_IRQ_LMC0,
87 OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
88 OCTEON_IRQ_RST,
89}; 56};
90 57
91#ifdef CONFIG_PCI_MSI 58#ifdef CONFIG_PCI_MSI
92/* 152 - 407 represent the MSI interrupts 0-255 */ 59/* 256 - 511 represent the MSI interrupts 0-255 */
93#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) 60#define OCTEON_IRQ_MSI_BIT0 (256)
94 61
95#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) 62#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
96#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) 63#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
97#else
98#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
99#endif 64#endif
100 65
101#endif 66#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
index bb5b9a4e29c..986982db7c3 100644
--- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -19,6 +19,8 @@
19#include <linux/mtd/nand.h> 19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h> 20#include <linux/mtd/partitions.h>
21 21
22#define JZ_NAND_NUM_BANKS 4
23
22struct jz_nand_platform_data { 24struct jz_nand_platform_data {
23 int num_partitions; 25 int num_partitions;
24 struct mtd_partition *partitions; 26 struct mtd_partition *partitions;
@@ -27,6 +29,8 @@ struct jz_nand_platform_data {
27 29
28 unsigned int busy_gpio; 30 unsigned int busy_gpio;
29 31
32 unsigned char banks[JZ_NAND_NUM_BANKS];
33
30 void (*ident_callback)(struct platform_device *, struct nand_chip *, 34 void (*ident_callback)(struct platform_device *, struct nand_chip *,
31 struct mtd_partition **, int *num_partitions); 35 struct mtd_partition **, int *num_partitions);
32}; 36};
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 1e29b9dd1d7..5222a007bc2 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/kconfig.h>
17 18
18/* loongson internal northbridge initialization */ 19/* loongson internal northbridge initialization */
19extern void bonito_irq_init(void); 20extern void bonito_irq_init(void);
@@ -66,7 +67,7 @@ extern int mach_i8259_irq(void);
66#include <linux/interrupt.h> 67#include <linux/interrupt.h>
67static inline void do_perfcnt_IRQ(void) 68static inline void do_perfcnt_IRQ(void)
68{ 69{
69#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE) 70#if IS_ENABLED(CONFIG_OPROFILE)
70 do_IRQ(LOONGSON2_PERFCNT_IRQ); 71 do_IRQ(LOONGSON2_PERFCNT_IRQ);
71#endif 72#endif
72} 73}
@@ -244,7 +245,6 @@ static inline void do_perfcnt_IRQ(void)
244 245
245#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ 246#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
246#include <linux/cpufreq.h> 247#include <linux/cpufreq.h>
247extern void loongson2_cpu_wait(void);
248extern struct cpufreq_frequency_table loongson2_clockmod_table[]; 248extern struct cpufreq_frequency_table loongson2_clockmod_table[];
249 249
250/* Chip Config */ 250/* Chip Config */
diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 00000000000..da96ed42f73
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * IRQ mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_IRQ_H
14#define __ASM_MACH_LOONGSON1_IRQ_H
15
16/*
17 * CPU core Interrupt Numbers
18 */
19#define MIPS_CPU_IRQ_BASE 0
20#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
21
22#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
23#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
24#define INT0_IRQ MIPS_CPU_IRQ(2)
25#define INT1_IRQ MIPS_CPU_IRQ(3)
26#define INT2_IRQ MIPS_CPU_IRQ(4)
27#define INT3_IRQ MIPS_CPU_IRQ(5)
28#define INT4_IRQ MIPS_CPU_IRQ(6)
29#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
30
31#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
32
33/*
34 * INT0~3 Interrupt Numbers
35 */
36#define LS1X_IRQ_BASE MIPS_CPU_IRQS
37#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
38
39#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
40#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
41#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
42#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
43#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
44#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
45#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
46#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
47#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
48#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
49#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
50#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
51#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
52#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
53#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
54#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
55#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
56#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
57#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
58#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
59#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
60#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
61#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
62#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
63
64#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
65#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
66#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
67#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
68
69#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
70
71#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
72
73#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
new file mode 100644
index 00000000000..4e18e88cebb
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Register mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
14#define __ASM_MACH_LOONGSON1_LOONGSON1_H
15
16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
17
18/* Loongson 1 Register Bases */
19#define LS1X_INTC_BASE 0x1fd01040
20#define LS1X_EHCI_BASE 0x1fe00000
21#define LS1X_OHCI_BASE 0x1fe08000
22#define LS1X_GMAC0_BASE 0x1fe10000
23#define LS1X_GMAC1_BASE 0x1fe20000
24
25#define LS1X_UART0_BASE 0x1fe40000
26#define LS1X_UART1_BASE 0x1fe44000
27#define LS1X_UART2_BASE 0x1fe48000
28#define LS1X_UART3_BASE 0x1fe4c000
29#define LS1X_CAN0_BASE 0x1fe50000
30#define LS1X_CAN1_BASE 0x1fe54000
31#define LS1X_I2C0_BASE 0x1fe58000
32#define LS1X_I2C1_BASE 0x1fe68000
33#define LS1X_I2C2_BASE 0x1fe70000
34#define LS1X_PWM_BASE 0x1fe5c000
35#define LS1X_WDT_BASE 0x1fe5c060
36#define LS1X_RTC_BASE 0x1fe64000
37#define LS1X_AC97_BASE 0x1fe74000
38#define LS1X_NAND_BASE 0x1fe78000
39#define LS1X_CLK_BASE 0x1fe78030
40
41#include <regs-clk.h>
42#include <regs-wdt.h>
43
44#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
new file mode 100644
index 00000000000..2f171617bad
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10
11#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
12#define __ASM_MACH_LOONGSON1_PLATFORM_H
13
14#include <linux/platform_device.h>
15
16extern struct platform_device ls1x_uart_device;
17extern struct platform_device ls1x_eth0_device;
18extern struct platform_device ls1x_ehci_device;
19extern struct platform_device ls1x_rtc_device;
20
21void ls1x_serial_setup(void);
22
23#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
new file mode 100644
index 00000000000..b871dc41b8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __ASM_MACH_LOONGSON1_PROM_H
11#define __ASM_MACH_LOONGSON1_PROM_H
12
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16
17/* environment arguments from bootloader */
18extern unsigned long memsize, highmemsize;
19
20/* loongson-specific command line, env and memory initialization */
21extern char *prom_getenv(char *name);
22extern void __init prom_init_cmdline(void);
23
24#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 00000000000..8efa7fb9f73
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 Clock Register Definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
13#define __ASM_MACH_LOONGSON1_REGS_CLK_H
14
15#define LS1X_CLK_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
17
18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
20
21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31)
23#define DIV_DC (0x1f << 26)
24#define DIV_CPU_EN (0x1 << 25)
25#define DIV_CPU (0x1f << 20)
26#define DIV_DDR_EN (0x1 << 19)
27#define DIV_DDR (0x1f << 14)
28
29#define DIV_DC_SHIFT 26
30#define DIV_CPU_SHIFT 20
31#define DIV_DDR_SHIFT 14
32
33#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
new file mode 100644
index 00000000000..f897de68c52
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 watchdog register definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
13#define __ASM_MACH_LOONGSON1_REGS_WDT_H
14
15#define LS1X_WDT_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x)))
17
18#define LS1X_WDT_EN LS1X_WDT_REG(0x0)
19#define LS1X_WDT_SET LS1X_WDT_REG(0x4)
20#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8)
21
22#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
new file mode 100644
index 00000000000..e3680a8fb34
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_LOONGSON1_WAR_H
9#define __ASM_MACH_LOONGSON1_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index d193fb68cf2..966db4be377 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -48,7 +48,6 @@
48#define cpu_has_userlocal 1 48#define cpu_has_userlocal 1
49#define cpu_has_mips32r2 1 49#define cpu_has_mips32r2 1
50#define cpu_has_mips64r2 1 50#define cpu_has_mips64r2 1
51#define cpu_has_dc_aliases 1
52#else 51#else
53#error "Unknown Netlogic CPU" 52#error "Unknown Netlogic CPU"
54#endif 53#endif
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
index 5e6912fdd0e..490867b03c8 100644
--- a/arch/mips/include/asm/mach-tx49xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -9,7 +9,7 @@
9#define ioswabb(a, x) (x) 9#define ioswabb(a, x) (x)
10#define __mem_ioswabb(a, x) (x) 10#define __mem_ioswabb(a, x) (x)
11#if defined(CONFIG_TOSHIBA_RBTX4939) && \ 11#if defined(CONFIG_TOSHIBA_RBTX4939) && \
12 (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \ 12 IS_ENABLED(CONFIG_SMC91X) && \
13 defined(__BIG_ENDIAN) 13 defined(__BIG_ENDIAN)
14#define NEEDS_TXX9_IOSWABW 14#define NEEDS_TXX9_IOSWABW
15extern u16 (*ioswabw)(volatile u16 *a, u16 x); 15extern u16 (*ioswabw)(volatile u16 *a, u16 x);
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index e71ff4c317f..5b3cb8553e9 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -28,6 +28,9 @@
28#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) 28#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
29#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) 29#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
30 30
31#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
32#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
33
31#define read_c0_tcstatus() __read_32bit_c0_register($2, 1) 34#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
32#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) 35#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
33 36
@@ -124,6 +127,14 @@
124#define VPECONF0_XTC_SHIFT 21 127#define VPECONF0_XTC_SHIFT 21
125#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) 128#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
126 129
130/* VPEConf1 fields (per VPE) */
131#define VPECONF1_NCP1_SHIFT 0
132#define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
133#define VPECONF1_NCP2_SHIFT 10
134#define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
135#define VPECONF1_NCX_SHIFT 20
136#define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
137
127/* TCStatus fields (per TC) */ 138/* TCStatus fields (per TC) */
128#define TCSTATUS_TASID (_ULCAST_(0xff)) 139#define TCSTATUS_TASID (_ULCAST_(0xff))
129#define TCSTATUS_IXMT_SHIFT 10 140#define TCSTATUS_IXMT_SHIFT 10
@@ -350,6 +361,8 @@ do { \
350#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) 361#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
351#define read_vpe_c0_vpeconf0() mftc0(1, 2) 362#define read_vpe_c0_vpeconf0() mftc0(1, 2)
352#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) 363#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
364#define read_vpe_c0_vpeconf1() mftc0(1, 3)
365#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
353#define read_vpe_c0_count() mftc0(9, 0) 366#define read_vpe_c0_count() mftc0(9, 0)
354#define write_vpe_c0_count(val) mttc0(9, 0, val) 367#define write_vpe_c0_count(val) mttc0(9, 0, val)
355#define read_vpe_c0_status() mftc0(12, 0) 368#define read_vpe_c0_status() mftc0(12, 0)
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 530008048c6..7531ecd654d 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -117,6 +117,8 @@ search_module_dbetables(unsigned long addr)
117#define MODULE_PROC_FAMILY "RM9000 " 117#define MODULE_PROC_FAMILY "RM9000 "
118#elif defined CONFIG_CPU_SB1 118#elif defined CONFIG_CPU_SB1
119#define MODULE_PROC_FAMILY "SB1 " 119#define MODULE_PROC_FAMILY "SB1 "
120#elif defined CONFIG_CPU_LOONGSON1
121#define MODULE_PROC_FAMILY "LOONGSON1 "
120#elif defined CONFIG_CPU_LOONGSON2 122#elif defined CONFIG_CPU_LOONGSON2
121#define MODULE_PROC_FAMILY "LOONGSON2 " 123#define MODULE_PROC_FAMILY "LOONGSON2 "
122#elif defined CONFIG_CPU_CAVIUM_OCTEON 124#elif defined CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index bf7d41deb9b..7b63a6b722a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -47,7 +47,9 @@
47#define CPU_BLOCKID_MAP 10 47#define CPU_BLOCKID_MAP 10
48 48
49#define LSU_DEFEATURE 0x304 49#define LSU_DEFEATURE 0x304
50#define LSU_CERRLOG_REGID 0x09 50#define LSU_DEBUG_ADDR 0x305
51#define LSU_DEBUG_DATA0 0x306
52#define LSU_CERRLOG_REGID 0x309
51#define SCHED_DEFEATURE 0x700 53#define SCHED_DEFEATURE 0x700
52 54
53/* Offsets of interest from the 'MAP' Block */ 55/* Offsets of interest from the 'MAP' Block */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 86cc3391e50..2c63f975464 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -36,6 +36,9 @@
36#define __NLM_HAL_IOMAP_H__ 36#define __NLM_HAL_IOMAP_H__
37 37
38#define XLP_DEFAULT_IO_BASE 0x18000000 38#define XLP_DEFAULT_IO_BASE 0x18000000
39#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
40#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000
41
39#define NMI_BASE 0xbfc00000 42#define NMI_BASE 0xbfc00000
40#define XLP_IO_CLK 133333333 43#define XLP_IO_CLK 133333333
41 44
@@ -129,7 +132,7 @@
129#define PCI_DEVICE_ID_NLM_PIC 0x1003 132#define PCI_DEVICE_ID_NLM_PIC 0x1003
130#define PCI_DEVICE_ID_NLM_PCIE 0x1004 133#define PCI_DEVICE_ID_NLM_PCIE 0x1004
131#define PCI_DEVICE_ID_NLM_EHCI 0x1007 134#define PCI_DEVICE_ID_NLM_EHCI 0x1007
132#define PCI_DEVICE_ID_NLM_ILK 0x1008 135#define PCI_DEVICE_ID_NLM_OHCI 0x1008
133#define PCI_DEVICE_ID_NLM_NAE 0x1009 136#define PCI_DEVICE_ID_NLM_NAE 0x1009
134#define PCI_DEVICE_ID_NLM_POE 0x100A 137#define PCI_DEVICE_ID_NLM_POE 0x100A
135#define PCI_DEVICE_ID_NLM_FMN 0x100B 138#define PCI_DEVICE_ID_NLM_FMN 0x100B
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
new file mode 100644
index 00000000000..66c323d1bd7
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_PCIBUS_H__
36#define __NLM_HAL_PCIBUS_H__
37
38/* PCIE Memory and IO regions */
39#define PCIE_MEM_BASE 0xd0000000ULL
40#define PCIE_MEM_LIMIT 0xdfffffffULL
41#define PCIE_IO_BASE 0x14000000ULL
42#define PCIE_IO_LIMIT 0x15ffffffULL
43
44#define PCIE_BRIDGE_CMD 0x1
45#define PCIE_BRIDGE_MSI_CAP 0x14
46#define PCIE_BRIDGE_MSI_ADDRL 0x15
47#define PCIE_BRIDGE_MSI_ADDRH 0x16
48#define PCIE_BRIDGE_MSI_DATA 0x17
49
50/* XLP Global PCIE configuration space registers */
51#define PCIE_BYTE_SWAP_MEM_BASE 0x247
52#define PCIE_BYTE_SWAP_MEM_LIM 0x248
53#define PCIE_BYTE_SWAP_IO_BASE 0x249
54#define PCIE_BYTE_SWAP_IO_LIM 0x24A
55#define PCIE_MSI_STATUS 0x25A
56#define PCIE_MSI_EN 0x25B
57#define PCIE_INT_EN0 0x261
58
59/* PCIE_MSI_EN */
60#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
61
62/* PCIE_INT_EN0 */
63#define PCIE_MSI_INT_EN (1 << 9)
64
65#ifndef __ASSEMBLY__
66
67#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
68#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
69#define nlm_get_pcie_base(node, inst) \
70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
71#define nlm_get_pcie_regbase(node, inst) \
72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
73
74int xlp_pcie_link_irt(int link);
75#endif
76#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index b6628f7ccf7..ad8b80233a6 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -201,7 +201,11 @@
201#define PIC_NUM_USB_IRTS 6 201#define PIC_NUM_USB_IRTS 6
202#define PIC_IRT_USB_0_INDEX 115 202#define PIC_IRT_USB_0_INDEX 115
203#define PIC_IRT_EHCI_0_INDEX 115 203#define PIC_IRT_EHCI_0_INDEX 115
204#define PIC_IRT_OHCI_0_INDEX 116
205#define PIC_IRT_OHCI_1_INDEX 117
204#define PIC_IRT_EHCI_1_INDEX 118 206#define PIC_IRT_EHCI_1_INDEX 118
207#define PIC_IRT_OHCI_2_INDEX 119
208#define PIC_IRT_OHCI_3_INDEX 120
205#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) 209#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
206/* 115 to 120 */ 210/* 115 to 120 */
207#define PIC_IRT_GDX_INDEX 121 211#define PIC_IRT_GDX_INDEX 121
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
new file mode 100644
index 00000000000..a9cd350dfb6
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_USB_H__
36#define __NLM_HAL_USB_H__
37
38#define USB_CTL_0 0x01
39#define USB_PHY_0 0x0A
40#define USB_PHY_RESET 0x01
41#define USB_PHY_PORT_RESET_0 0x10
42#define USB_PHY_PORT_RESET_1 0x20
43#define USB_CONTROLLER_RESET 0x01
44#define USB_INT_STATUS 0x0E
45#define USB_INT_EN 0x0F
46#define USB_PHY_INTERRUPT_EN 0x01
47#define USB_OHCI_INTERRUPT_EN 0x02
48#define USB_OHCI_INTERRUPT1_EN 0x04
49#define USB_OHCI_INTERRUPT2_EN 0x08
50#define USB_CTRL_INTERRUPT_EN 0x10
51
52#ifndef __ASSEMBLY__
53
54#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
55#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
56#define nlm_get_usb_pcibase(node, inst) \
57 nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
58#define nlm_get_usb_hcd_base(node, inst) \
59 nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
60#define nlm_get_usb_regbase(node, inst) \
61 (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
62
63#endif
64#endif /* __NLM_HAL_USB_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 1540588e396..7e47209327a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -35,8 +35,21 @@
35#ifndef _NLM_HAL_XLP_H 35#ifndef _NLM_HAL_XLP_H
36#define _NLM_HAL_XLP_H 36#define _NLM_HAL_XLP_H
37 37
38#define PIC_UART_0_IRQ 17 38#define PIC_UART_0_IRQ 17
39#define PIC_UART_1_IRQ 18 39#define PIC_UART_1_IRQ 18
40#define PIC_PCIE_LINK_0_IRQ 19
41#define PIC_PCIE_LINK_1_IRQ 20
42#define PIC_PCIE_LINK_2_IRQ 21
43#define PIC_PCIE_LINK_3_IRQ 22
44#define PIC_EHCI_0_IRQ 23
45#define PIC_EHCI_1_IRQ 24
46#define PIC_OHCI_0_IRQ 25
47#define PIC_OHCI_1_IRQ 26
48#define PIC_OHCI_2_IRQ 27
49#define PIC_OHCI_3_IRQ 28
50#define PIC_MMC_IRQ 29
51#define PIC_I2C_0_IRQ 30
52#define PIC_I2C_1_IRQ 31
40 53
41#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
42 55
diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h
new file mode 100644
index 00000000000..2d02428c4f1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/bridge.h
@@ -0,0 +1,104 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#ifndef _ASM_NLM_BRIDGE_H_
35#define _ASM_NLM_BRIDGE_H_
36
37#define BRIDGE_DRAM_0_BAR 0
38#define BRIDGE_DRAM_1_BAR 1
39#define BRIDGE_DRAM_2_BAR 2
40#define BRIDGE_DRAM_3_BAR 3
41#define BRIDGE_DRAM_4_BAR 4
42#define BRIDGE_DRAM_5_BAR 5
43#define BRIDGE_DRAM_6_BAR 6
44#define BRIDGE_DRAM_7_BAR 7
45#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8
46#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9
47#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10
48#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11
49#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12
50#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13
51#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14
52#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15
53#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16
54#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17
55#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18
56#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19
57#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20
58#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21
59#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22
60#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23
61#define BRIDGE_CFG_BAR 24
62#define BRIDGE_PHNX_IO_BAR 25
63#define BRIDGE_FLASH_BAR 26
64#define BRIDGE_SRAM_BAR 27
65#define BRIDGE_HTMEM_BAR 28
66#define BRIDGE_HTINT_BAR 29
67#define BRIDGE_HTPIC_BAR 30
68#define BRIDGE_HTSM_BAR 31
69#define BRIDGE_HTIO_BAR 32
70#define BRIDGE_HTCFG_BAR 33
71#define BRIDGE_PCIXCFG_BAR 34
72#define BRIDGE_PCIXMEM_BAR 35
73#define BRIDGE_PCIXIO_BAR 36
74#define BRIDGE_DEVICE_MASK 37
75#define BRIDGE_AERR_INTR_LOG1 38
76#define BRIDGE_AERR_INTR_LOG2 39
77#define BRIDGE_AERR_INTR_LOG3 40
78#define BRIDGE_AERR_DEV_STAT 41
79#define BRIDGE_AERR1_LOG1 42
80#define BRIDGE_AERR1_LOG2 43
81#define BRIDGE_AERR1_LOG3 44
82#define BRIDGE_AERR1_DEV_STAT 45
83#define BRIDGE_AERR_INTR_EN 46
84#define BRIDGE_AERR_UPG 47
85#define BRIDGE_AERR_CLEAR 48
86#define BRIDGE_AERR1_CLEAR 49
87#define BRIDGE_SBE_COUNTS 50
88#define BRIDGE_DBE_COUNTS 51
89#define BRIDGE_BITERR_INT_EN 52
90
91#define BRIDGE_SYS2IO_CREDITS 53
92#define BRIDGE_EVNT_CNT_CTRL1 54
93#define BRIDGE_EVNT_COUNTER1 55
94#define BRIDGE_EVNT_CNT_CTRL2 56
95#define BRIDGE_EVNT_COUNTER2 57
96#define BRIDGE_RESERVED1 58
97
98#define BRIDGE_DEFEATURE 59
99#define BRIDGE_SCRATCH0 60
100#define BRIDGE_SCRATCH1 61
101#define BRIDGE_SCRATCH2 62
102#define BRIDGE_SCRATCH3 63
103
104#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h
new file mode 100644
index 00000000000..f8aca5472b6
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/flash.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#ifndef _ASM_NLM_FLASH_H_
35#define _ASM_NLM_FLASH_H_
36
37#define FLASH_CSBASE_ADDR(cs) (cs)
38#define FLASH_CSADDR_MASK(cs) (0x10 + (cs))
39#define FLASH_CSDEV_PARM(cs) (0x20 + (cs))
40#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs))
41#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs))
42
43#define FLASH_INT_MASK 0x50
44#define FLASH_INT_STATUS 0x60
45#define FLASH_ERROR_STATUS 0x70
46#define FLASH_ERROR_ADDR 0x80
47
48#define FLASH_NAND_CLE(cs) (0x90 + (cs))
49#define FLASH_NAND_ALE(cs) (0xa0 + (cs))
50
51#define FLASH_NAND_CSDEV_PARAM 0x000041e6
52#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22
53#define FLASH_NAND_CSTIME_PARAMB 0x000083cf
54
55#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
index 51f6ad4aeb1..8492e835b11 100644
--- a/arch/mips/include/asm/netlogic/xlr/gpio.h
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -35,39 +35,40 @@
35#ifndef _ASM_NLM_GPIO_H 35#ifndef _ASM_NLM_GPIO_H
36#define _ASM_NLM_GPIO_H 36#define _ASM_NLM_GPIO_H
37 37
38#define NETLOGIC_GPIO_INT_EN_REG 0 38#define GPIO_INT_EN_REG 0
39#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 39#define GPIO_INPUT_INVERSION_REG 1
40#define NETLOGIC_GPIO_IO_DIR_REG 2 40#define GPIO_IO_DIR_REG 2
41#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 41#define GPIO_IO_DATA_WR_REG 3
42#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 42#define GPIO_IO_DATA_RD_REG 4
43 43
44#define NETLOGIC_GPIO_SWRESET_REG 8 44#define GPIO_SWRESET_REG 8
45#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 45#define GPIO_DRAM1_CNTRL_REG 9
46#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 46#define GPIO_DRAM1_RATIO_REG 10
47#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 47#define GPIO_DRAM1_RESET_REG 11
48#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 48#define GPIO_DRAM1_STATUS_REG 12
49#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 49#define GPIO_DRAM2_CNTRL_REG 13
50#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 50#define GPIO_DRAM2_RATIO_REG 14
51#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 51#define GPIO_DRAM2_RESET_REG 15
52#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 52#define GPIO_DRAM2_STATUS_REG 16
53 53
54#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 54#define GPIO_PWRON_RESET_CFG_REG 21
55#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 55#define GPIO_BIST_ALL_GO_STATUS_REG 24
56#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 56#define GPIO_BIST_CPU_GO_STATUS_REG 25
57#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 57#define GPIO_BIST_DEV_GO_STATUS_REG 26
58 58
59#define NETLOGIC_GPIO_FUSE_BANK_REG 35 59#define GPIO_FUSE_BANK_REG 35
60#define NETLOGIC_GPIO_CPU_RESET_REG 40 60#define GPIO_CPU_RESET_REG 40
61#define NETLOGIC_GPIO_RNG_REG 43 61#define GPIO_RNG_REG 43
62 62
63#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 63#define PWRON_RESET_PCMCIA_BOOT 17
64#define NETLOGIC_GPIO_LED_BITMAP 0x1700000
65#define NETLOGIC_GPIO_LED_0_SHIFT 20
66#define NETLOGIC_GPIO_LED_1_SHIFT 24
67 64
68#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 65#define GPIO_LED_BITMAP 0x1700000
69#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 66#define GPIO_LED_0_SHIFT 20
70#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 67#define GPIO_LED_1_SHIFT 24
71#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 68
69#define GPIO_LED_OUTPUT_CODE_RESET 0x01
70#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
71#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
72#define GPIO_LED_OUTPUT_CODE_MAIN 0x04
72 73
73#endif 74#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
deleted file mode 100644
index 5ff8c93198d..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper functions for FPA setup.
32 *
33 */
34#ifndef __CVMX_HELPER_H_FPA__
35#define __CVMX_HELPER_H_FPA__
36
37/**
38 * Allocate memory and initialize the FPA pools using memory
39 * from cvmx-bootmem. Sizes of each element in the pools is
40 * controlled by the cvmx-config.h header file. Specifying
41 * zero for any parameter will cause that FPA pool to not be
42 * setup. This is useful if you aren't using some of the
43 * hardware and want to save memory.
44 *
45 * @packet_buffers:
46 * Number of packet buffers to allocate
47 * @work_queue_entries:
48 * Number of work queue entries
49 * @pko_buffers:
50 * PKO Command buffers. You should at minimum have two per
51 * each PKO queue.
52 * @tim_buffers:
53 * TIM ring buffer command queues. At least two per timer bucket
54 * is recommened.
55 * @dfa_buffers:
56 * DFA command buffer. A relatively small (32 for example)
57 * number should work.
58 * Returns Zero on success, non-zero if out of memory
59 */
60extern int cvmx_helper_initialize_fpa(int packet_buffers,
61 int work_queue_entries, int pko_buffers,
62 int tim_buffers, int dfa_buffers);
63
64#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
index 3169cd79f2a..0ac6b9f412b 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -61,8 +61,6 @@ typedef union {
61 } s; 61 } s;
62} cvmx_helper_link_info_t; 62} cvmx_helper_link_info_t;
63 63
64#include "cvmx-helper-fpa.h"
65
66#include <asm/octeon/cvmx-helper-errata.h> 64#include <asm/octeon/cvmx-helper-errata.h>
67#include "cvmx-helper-loop.h" 65#include "cvmx-helper-loop.h"
68#include "cvmx-helper-npi.h" 66#include "cvmx-helper-npi.h"
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index f72f768cd3a..1e2486e2357 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -215,11 +215,6 @@ struct octeon_cf_data {
215 int dma_engine; /* -1 for no DMA */ 215 int dma_engine; /* -1 for no DMA */
216}; 216};
217 217
218struct octeon_i2c_data {
219 unsigned int sys_freq;
220 unsigned int i2c_freq;
221};
222
223extern void octeon_write_lcd(const char *s); 218extern void octeon_write_lcd(const char *s);
224extern void octeon_check_cpu_bist(void); 219extern void octeon_check_cpu_bist(void);
225extern int octeon_get_boot_debug_flag(void); 220extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 7206d445bab..8808bf548b9 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -20,9 +20,6 @@
20extern int early_init_dt_scan_memory_arch(unsigned long node, 20extern int early_init_dt_scan_memory_arch(unsigned long node,
21 const char *uname, int depth, void *data); 21 const char *uname, int depth, void *data);
22 22
23extern int reserve_mem_mach(unsigned long addr, unsigned long size);
24extern void free_mem_mach(unsigned long addr, unsigned long size);
25
26extern void device_tree_init(void); 23extern void device_tree_init(void);
27 24
28static inline unsigned long pci_address_to_pio(phys_addr_t address) 25static inline unsigned long pci_address_to_pio(phys_addr_t address)
diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h
index c9736fc0632..8935426a56a 100644
--- a/arch/mips/include/asm/smtc.h
+++ b/arch/mips/include/asm/smtc.h
@@ -33,6 +33,12 @@ typedef long asiduse;
33#endif 33#endif
34#endif 34#endif
35 35
36/*
37 * VPE Management information
38 */
39
40#define MAX_SMTC_VPES MAX_SMTC_TLBS /* FIXME: May not always be true. */
41
36extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 42extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
37 43
38struct mm_struct; 44struct mm_struct;
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 653a412c036..3b92efef56d 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -687,7 +687,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
687 __MODULE_JAL(__copy_user) \ 687 __MODULE_JAL(__copy_user) \
688 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 688 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
689 : \ 689 : \
690 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 690 : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \
691 DADDI_SCRATCH, "memory"); \ 691 DADDI_SCRATCH, "memory"); \
692 __cu_len_r; \ 692 __cu_len_r; \
693}) 693})
@@ -797,7 +797,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
797 ".set\treorder" \ 797 ".set\treorder" \
798 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 798 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
799 : \ 799 : \
800 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 800 : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \
801 DADDI_SCRATCH, "memory"); \ 801 DADDI_SCRATCH, "memory"); \
802 __cu_len_r; \ 802 __cu_len_r; \
803}) 803})
@@ -820,7 +820,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
820 ".set\treorder" \ 820 ".set\treorder" \
821 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 821 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
822 : \ 822 : \
823 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 823 : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \
824 DADDI_SCRATCH, "memory"); \ 824 DADDI_SCRATCH, "memory"); \
825 __cu_len_r; \ 825 __cu_len_r; \
826}) 826})
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 440a21dab57..3d9f75f7ffc 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -6,6 +6,7 @@
6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
7 * Copyright (C) 2005 Maciej W. Rozycki 7 * Copyright (C) 2005 Maciej W. Rozycki
8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2012 MIPS Technologies, Inc.
9 */ 10 */
10 11
11#include <linux/types.h> 12#include <linux/types.h>
@@ -62,8 +63,10 @@ void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
62 63
63Ip_u2u1s3(_addiu); 64Ip_u2u1s3(_addiu);
64Ip_u3u1u2(_addu); 65Ip_u3u1u2(_addu);
65Ip_u2u1u3(_andi);
66Ip_u3u1u2(_and); 66Ip_u3u1u2(_and);
67Ip_u2u1u3(_andi);
68Ip_u1u2s3(_bbit0);
69Ip_u1u2s3(_bbit1);
67Ip_u1u2s3(_beq); 70Ip_u1u2s3(_beq);
68Ip_u1u2s3(_beql); 71Ip_u1u2s3(_beql);
69Ip_u1s2(_bgez); 72Ip_u1s2(_bgez);
@@ -72,55 +75,54 @@ Ip_u1s2(_bltz);
72Ip_u1s2(_bltzl); 75Ip_u1s2(_bltzl);
73Ip_u1u2s3(_bne); 76Ip_u1u2s3(_bne);
74Ip_u2s3u1(_cache); 77Ip_u2s3u1(_cache);
75Ip_u1u2u3(_dmfc0);
76Ip_u1u2u3(_dmtc0);
77Ip_u2u1s3(_daddiu); 78Ip_u2u1s3(_daddiu);
78Ip_u3u1u2(_daddu); 79Ip_u3u1u2(_daddu);
80Ip_u2u1msbu3(_dins);
81Ip_u2u1msbu3(_dinsm);
82Ip_u1u2u3(_dmfc0);
83Ip_u1u2u3(_dmtc0);
84Ip_u2u1u3(_drotr);
85Ip_u2u1u3(_drotr32);
79Ip_u2u1u3(_dsll); 86Ip_u2u1u3(_dsll);
80Ip_u2u1u3(_dsll32); 87Ip_u2u1u3(_dsll32);
81Ip_u2u1u3(_dsra); 88Ip_u2u1u3(_dsra);
82Ip_u2u1u3(_dsrl); 89Ip_u2u1u3(_dsrl);
83Ip_u2u1u3(_dsrl32); 90Ip_u2u1u3(_dsrl32);
84Ip_u2u1u3(_drotr);
85Ip_u2u1u3(_drotr32);
86Ip_u3u1u2(_dsubu); 91Ip_u3u1u2(_dsubu);
87Ip_0(_eret); 92Ip_0(_eret);
88Ip_u1(_j); 93Ip_u1(_j);
89Ip_u1(_jal); 94Ip_u1(_jal);
90Ip_u1(_jr); 95Ip_u1(_jr);
91Ip_u2s3u1(_ld); 96Ip_u2s3u1(_ld);
97Ip_u3u1u2(_ldx);
92Ip_u2s3u1(_ll); 98Ip_u2s3u1(_ll);
93Ip_u2s3u1(_lld); 99Ip_u2s3u1(_lld);
94Ip_u1s2(_lui); 100Ip_u1s2(_lui);
95Ip_u2s3u1(_lw); 101Ip_u2s3u1(_lw);
102Ip_u3u1u2(_lwx);
96Ip_u1u2u3(_mfc0); 103Ip_u1u2u3(_mfc0);
97Ip_u1u2u3(_mtc0); 104Ip_u1u2u3(_mtc0);
98Ip_u2u1u3(_ori);
99Ip_u3u1u2(_or); 105Ip_u3u1u2(_or);
106Ip_u2u1u3(_ori);
100Ip_u2s3u1(_pref); 107Ip_u2s3u1(_pref);
101Ip_0(_rfe); 108Ip_0(_rfe);
109Ip_u2u1u3(_rotr);
102Ip_u2s3u1(_sc); 110Ip_u2s3u1(_sc);
103Ip_u2s3u1(_scd); 111Ip_u2s3u1(_scd);
104Ip_u2s3u1(_sd); 112Ip_u2s3u1(_sd);
105Ip_u2u1u3(_sll); 113Ip_u2u1u3(_sll);
106Ip_u2u1u3(_sra); 114Ip_u2u1u3(_sra);
107Ip_u2u1u3(_srl); 115Ip_u2u1u3(_srl);
108Ip_u2u1u3(_rotr);
109Ip_u3u1u2(_subu); 116Ip_u3u1u2(_subu);
110Ip_u2s3u1(_sw); 117Ip_u2s3u1(_sw);
118Ip_u1(_syscall);
111Ip_0(_tlbp); 119Ip_0(_tlbp);
112Ip_0(_tlbr); 120Ip_0(_tlbr);
113Ip_0(_tlbwi); 121Ip_0(_tlbwi);
114Ip_0(_tlbwr); 122Ip_0(_tlbwr);
115Ip_u3u1u2(_xor); 123Ip_u3u1u2(_xor);
116Ip_u2u1u3(_xori); 124Ip_u2u1u3(_xori);
117Ip_u2u1msbu3(_dins); 125
118Ip_u2u1msbu3(_dinsm);
119Ip_u1(_syscall);
120Ip_u1u2s3(_bbit0);
121Ip_u1u2s3(_bbit1);
122Ip_u3u1u2(_lwx);
123Ip_u3u1u2(_ldx);
124 126
125/* Handle labels. */ 127/* Handle labels. */
126struct uasm_label { 128struct uasm_label {
@@ -145,37 +147,37 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
145 147
146/* convenience macros for instructions */ 148/* convenience macros for instructions */
147#ifdef CONFIG_64BIT 149#ifdef CONFIG_64BIT
150# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
151# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
152# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
148# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off) 153# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
149# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off) 154# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
155# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
156# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
157# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
158# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
150# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) 159# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
151# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh) 160# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
152# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh) 161# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
153# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh) 162# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh)
154# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
155# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
156# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
157# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
158# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
159# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd) 163# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
160# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off) 164# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
161# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
162# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
163#else 165#else
166# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
167# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
168# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
164# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off) 169# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
165# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off) 170# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
171# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
172# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
173# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
174# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
166# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) 175# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
167# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh) 176# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
168# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) 177# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
169# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) 178# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
170# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
171# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
172# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
173# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
174# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
175# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd) 179# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
176# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off) 180# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
177# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
178# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
179#endif 181#endif
180 182
181#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off) 183#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
@@ -183,19 +185,10 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
183#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off) 185#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
184#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off) 186#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
185#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off) 187#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
188#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
186#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b) 189#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
187#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0) 190#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
188#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1) 191#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
189#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
190
191static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
192 unsigned int a2, unsigned int a3)
193{
194 if (a3 < 32)
195 uasm_i_dsrl(p, a1, a2, a3);
196 else
197 uasm_i_dsrl32(p, a1, a2, a3 - 32);
198}
199 192
200static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1, 193static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
201 unsigned int a2, unsigned int a3) 194 unsigned int a2, unsigned int a3)
@@ -215,6 +208,15 @@ static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
215 uasm_i_dsll32(p, a1, a2, a3 - 32); 208 uasm_i_dsll32(p, a1, a2, a3 - 32);
216} 209}
217 210
211static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
212 unsigned int a2, unsigned int a3)
213{
214 if (a3 < 32)
215 uasm_i_dsrl(p, a1, a2, a3);
216 else
217 uasm_i_dsrl32(p, a1, a2, a3 - 32);
218}
219
218/* Handle relocations. */ 220/* Handle relocations. */
219struct uasm_reloc { 221struct uasm_reloc {
220 u32 *addr; 222 u32 *addr;
@@ -234,16 +236,16 @@ void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
234int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr); 236int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
235 237
236/* Convenience functions for labeled branches. */ 238/* Convenience functions for labeled branches. */
237void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
238void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid); 239void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
240void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
241 unsigned int bit, int lid);
242void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
243 unsigned int bit, int lid);
239void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 244void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
240void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 245void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
246void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
247void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
248void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
241void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 249void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
242 unsigned int reg2, int lid); 250 unsigned int reg2, int lid);
243void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 251void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
244void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
245void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
246void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
247 unsigned int bit, int lid);
248void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
249 unsigned int bit, int lid);
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index d8dad5340ea..bebbde01be9 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -1034,7 +1034,6 @@
1034#ifndef __ASSEMBLY__ 1034#ifndef __ASSEMBLY__
1035 1035
1036#define __ARCH_OMIT_COMPAT_SYS_GETDENTS64 1036#define __ARCH_OMIT_COMPAT_SYS_GETDENTS64
1037#define __ARCH_WANT_IPC_PARSE_VERSION
1038#define __ARCH_WANT_OLD_READDIR 1037#define __ARCH_WANT_OLD_READDIR
1039#define __ARCH_WANT_SYS_ALARM 1038#define __ARCH_WANT_SYS_ALARM
1040#define __ARCH_WANT_SYS_GETHOSTNAME 1039#define __ARCH_WANT_SYS_GETHOSTNAME
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 18:28:13 -0400