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-rw-r--r--arch/mips/include/asm/bmips.h110
-rw-r--r--arch/mips/include/asm/bootinfo.h1
-rw-r--r--arch/mips/include/asm/branch.h5
-rw-r--r--arch/mips/include/asm/cpu.h6
-rw-r--r--arch/mips/include/asm/gio_device.h56
-rw-r--r--arch/mips/include/asm/hazards.h7
-rw-r--r--arch/mips/include/asm/hugetlb.h2
-rw-r--r--arch/mips/include/asm/kprobes.h5
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h81
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart.h67
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h18
-rw-r--r--arch/mips/include/asm/mach-ath79/ath79.h11
-rw-r--r--arch/mips/include/asm/mach-ath79/irq.h8
-rw-r--r--arch/mips/include/asm/mach-ath79/pci-ath724x.h21
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h273
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1200fb.h14
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1550nd.h16
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h31
-rw-r--r--arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1300.h241
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h3
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h597
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h231
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h42
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/irq.h7
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h36
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h11
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1300.h40
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h79
-rw-r--r--arch/mips/include/asm/mach-db1x00/irq.h23
-rw-r--r--arch/mips/include/asm/mach-generic/floppy.h2
-rw-r--r--arch/mips/include/asm/mach-jazz/floppy.h2
-rw-r--r--arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h23
-rw-r--r--arch/mips/include/asm/mach-pb1x00/mc146818rtc.h34
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h87
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h139
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h73
-rw-r--r--arch/mips/include/asm/mipsregs.h9
-rw-r--r--arch/mips/include/asm/module.h6
-rw-r--r--arch/mips/include/asm/netlogic/common.h76
-rw-r--r--arch/mips/include/asm/netlogic/haldefs.h163
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h187
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h83
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h153
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h411
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h129
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h191
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h51
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h22
-rw-r--r--arch/mips/include/asm/netlogic/xlr/msidef.h84
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h69
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h13
-rw-r--r--arch/mips/include/asm/octeon/cvmx-address.h274
-rw-r--r--arch/mips/include/asm/octeon/cvmx-asxx-defs.h475
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h82
-rw-r--r--arch/mips/include/asm/octeon/cvmx-cmd-queue.h617
-rw-r--r--arch/mips/include/asm/octeon/cvmx-config.h168
-rw-r--r--arch/mips/include/asm/octeon/cvmx-dbg-defs.h72
-rw-r--r--arch/mips/include/asm/octeon/cvmx-dpi-defs.h643
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fau.h597
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fpa-defs.h403
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fpa.h299
-rw-r--r--arch/mips/include/asm/octeon/cvmx-gmxx-defs.h2529
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-board.h157
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-fpa.h64
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-loop.h60
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-npi.h61
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-rgmii.h111
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-sgmii.h105
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-spi.h85
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-util.h215
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-xaui.h104
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper.h228
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ipd.h338
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mdio.h506
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mio-defs.h1033
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h4
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pciercx-defs.h609
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pcsx-defs.h370
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h316
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pemx-defs.h509
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pexp-defs.h19
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pip-defs.h1267
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pip.h524
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pko-defs.h1133
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pko.h610
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow.h1982
-rw-r--r--arch/mips/include/asm/octeon/cvmx-scratch.h139
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sli-defs.h2172
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spi.h269
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spxx-defs.h347
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sriox-defs.h1036
-rw-r--r--arch/mips/include/asm/octeon/cvmx-srxx-defs.h126
-rw-r--r--arch/mips/include/asm/octeon/cvmx-stxx-defs.h292
-rw-r--r--arch/mips/include/asm/octeon/cvmx-wqe.h397
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h42
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h114
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h215
-rw-r--r--arch/mips/include/asm/octeon/pci-octeon.h3
-rw-r--r--arch/mips/include/asm/page.h8
-rw-r--r--arch/mips/include/asm/pgtable-32.h18
-rw-r--r--arch/mips/include/asm/tlbmisc.h10
-rw-r--r--arch/mips/include/asm/traps.h13
107 files changed, 24772 insertions, 1068 deletions
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
new file mode 100644
index 00000000000..552a65a0cf2
--- /dev/null
+++ b/arch/mips/include/asm/bmips.h
@@ -0,0 +1,110 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Definitions for BMIPS processors
9 */
10#ifndef _ASM_BMIPS_H
11#define _ASM_BMIPS_H
12
13#include <linux/compiler.h>
14#include <linux/linkage.h>
15#include <asm/addrspace.h>
16#include <asm/mipsregs.h>
17#include <asm/hazards.h>
18
19/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
20#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \
21 (unsigned long) \
22 ((read_c0_brcm_cbr() >> 18) << 18)))
23
24#define BMIPS_RAC_CONFIG 0x00000000
25#define BMIPS_RAC_ADDRESS_RANGE 0x00000004
26#define BMIPS_RAC_CONFIG_1 0x00000008
27#define BMIPS_L2_CONFIG 0x0000000c
28#define BMIPS_LMB_CONTROL 0x0000001c
29#define BMIPS_SYSTEM_BASE 0x00000020
30#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000
31#define BMIPS_PERF_CONTROL_0 0x00020004
32#define BMIPS_PERF_CONTROL_1 0x00020008
33#define BMIPS_PERF_COUNTER_0 0x00020010
34#define BMIPS_PERF_COUNTER_1 0x00020014
35#define BMIPS_PERF_COUNTER_2 0x00020018
36#define BMIPS_PERF_COUNTER_3 0x0002001c
37#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
38#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
39
40#define BMIPS_NMI_RESET_VEC 0x80000000
41#define BMIPS_WARM_RESTART_VEC 0x80000380
42
43#define ZSCM_REG_BASE 0x97000000
44
45#if !defined(__ASSEMBLY__)
46
47#include <linux/cpumask.h>
48#include <asm/r4kcache.h>
49
50extern struct plat_smp_ops bmips_smp_ops;
51extern char bmips_reset_nmi_vec;
52extern char bmips_reset_nmi_vec_end;
53extern char bmips_smp_movevec;
54extern char bmips_smp_int_vec;
55extern char bmips_smp_int_vec_end;
56
57extern int bmips_smp_enabled;
58extern int bmips_cpu_offset;
59extern cpumask_t bmips_booted_mask;
60
61extern void bmips_ebase_setup(void);
62extern asmlinkage void plat_wired_tlb_setup(void);
63
64static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
65{
66 unsigned long ret;
67
68 __asm__ __volatile__(
69 ".set push\n"
70 ".set noreorder\n"
71 "cache %1, 0(%2)\n"
72 "sync\n"
73 "_ssnop\n"
74 "_ssnop\n"
75 "_ssnop\n"
76 "_ssnop\n"
77 "_ssnop\n"
78 "_ssnop\n"
79 "_ssnop\n"
80 "mfc0 %0, $28, 3\n"
81 "_ssnop\n"
82 ".set pop\n"
83 : "=&r" (ret)
84 : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
85 : "memory");
86 return ret;
87}
88
89static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
90{
91 __asm__ __volatile__(
92 ".set push\n"
93 ".set noreorder\n"
94 "mtc0 %0, $28, 3\n"
95 "_ssnop\n"
96 "_ssnop\n"
97 "_ssnop\n"
98 "cache %1, 0(%2)\n"
99 "_ssnop\n"
100 "_ssnop\n"
101 "_ssnop\n"
102 : /* no outputs */
103 : "r" (data),
104 "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
105 : "memory");
106}
107
108#endif /* !defined(__ASSEMBLY__) */
109
110#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 35cd1bab69c..7a51d879e6c 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -86,6 +86,7 @@ extern unsigned long mips_machtype;
86#define BOOT_MEM_RAM 1 86#define BOOT_MEM_RAM 1
87#define BOOT_MEM_ROM_DATA 2 87#define BOOT_MEM_ROM_DATA 2
88#define BOOT_MEM_RESERVED 3 88#define BOOT_MEM_RESERVED 3
89#define BOOT_MEM_INIT_RAM 4
89 90
90/* 91/*
91 * A memory map that's built upon what was determined 92 * A memory map that's built upon what was determined
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 37c6857c8d4..888766ae1f8 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -9,6 +9,7 @@
9#define _ASM_BRANCH_H 9#define _ASM_BRANCH_H
10 10
11#include <asm/ptrace.h> 11#include <asm/ptrace.h>
12#include <asm/inst.h>
12 13
13static inline int delay_slot(struct pt_regs *regs) 14static inline int delay_slot(struct pt_regs *regs)
14{ 15{
@@ -23,7 +24,11 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
23 return regs->cp0_epc + 4; 24 return regs->cp0_epc + 4;
24} 25}
25 26
27#define BRANCH_LIKELY_TAKEN 0x0001
28
26extern int __compute_return_epc(struct pt_regs *regs); 29extern int __compute_return_epc(struct pt_regs *regs);
30extern int __compute_return_epc_for_insn(struct pt_regs *regs,
31 union mips_instruction insn);
27 32
28static inline int compute_return_epc(struct pt_regs *regs) 33static inline int compute_return_epc(struct pt_regs *regs)
29{ 34{
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2f7f41873f2..f9fa2a479dd 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -169,6 +169,10 @@
169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
172#define PRID_IMP_NETLOGIC_AU13XX 0x8000
173
174#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
175#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
172 176
173/* 177/*
174 * Definitions for 7:0 on legacy processors 178 * Definitions for 7:0 on legacy processors
@@ -263,7 +267,7 @@ enum cpu_type_enum {
263 */ 267 */
264 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 268 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
265 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 269 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
266 CPU_XLR, 270 CPU_XLR, CPU_XLP,
267 271
268 CPU_LAST 272 CPU_LAST
269}; 273};
diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
new file mode 100644
index 00000000000..5437c84664b
--- /dev/null
+++ b/arch/mips/include/asm/gio_device.h
@@ -0,0 +1,56 @@
1#include <linux/device.h>
2#include <linux/mod_devicetable.h>
3
4struct gio_device_id {
5 __u8 id;
6};
7
8struct gio_device {
9 struct device dev;
10 struct resource resource;
11 unsigned int irq;
12 unsigned int slotno;
13
14 const char *name;
15 struct gio_device_id id;
16 unsigned id32:1;
17 unsigned gio64:1;
18};
19#define to_gio_device(d) container_of(d, struct gio_device, dev)
20
21struct gio_driver {
22 const char *name;
23 struct module *owner;
24 const struct gio_device_id *id_table;
25
26 int (*probe)(struct gio_device *, const struct gio_device_id *);
27 void (*remove)(struct gio_device *);
28 int (*suspend)(struct gio_device *, pm_message_t);
29 int (*resume)(struct gio_device *);
30 void (*shutdown)(struct gio_device *);
31
32 struct device_driver driver;
33};
34#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver)
35
36extern const struct gio_device_id *gio_match_device(const struct gio_device_id *,
37 const struct gio_device *);
38extern struct gio_device *gio_dev_get(struct gio_device *);
39extern void gio_dev_put(struct gio_device *);
40
41extern int gio_device_register(struct gio_device *);
42extern void gio_device_unregister(struct gio_device *);
43extern void gio_release_dev(struct device *);
44
45static inline void gio_device_free(struct gio_device *dev)
46{
47 gio_release_dev(&dev->dev);
48}
49
50extern int gio_register_driver(struct gio_driver *);
51extern void gio_unregister_driver(struct gio_driver *);
52
53#define gio_get_drvdata(_dev) drv_get_drvdata(&(_dev)->dev)
54#define gio_set_drvdata(_dev, data) drv_set_drvdata(&(_dev)->dev, (data))
55
56extern void gio_set_master(struct gio_device *);
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4e332165d7b..b4c20e4f87c 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,8 @@ do { \
87 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
88} while (0) 88} while (0)
89 89
90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY) 90#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
91 defined(CONFIG_CPU_BMIPS)
91 92
92/* 93/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to 94 * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,8 +140,8 @@ do { \
139} while (0) 140} while (0)
140 141
141#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
143 defined(CONFIG_CPU_R5500) 144 defined(CONFIG_CPU_R5500)
144 145
145/* 146/*
146 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index c565b7c3f0b..58d36889f09 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -70,7 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, 70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
71 unsigned long addr, pte_t *ptep) 71 unsigned long addr, pte_t *ptep)
72{ 72{
73 flush_tlb_mm(vma->vm_mm); 73 flush_tlb_page(vma, addr & huge_page_mask(hstate_vma(vma)));
74} 74}
75 75
76static inline int huge_pte_none(pte_t pte) 76static inline int huge_pte_none(pte_t pte)
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index e6ea4d4d720..1fbbca01e68 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -74,6 +74,8 @@ struct prev_kprobe {
74 : MAX_JPROBES_STACK_SIZE) 74 : MAX_JPROBES_STACK_SIZE)
75 75
76 76
77#define SKIP_DELAYSLOT 0x0001
78
77/* per-cpu kprobe control block */ 79/* per-cpu kprobe control block */
78struct kprobe_ctlblk { 80struct kprobe_ctlblk {
79 unsigned long kprobe_status; 81 unsigned long kprobe_status;
@@ -82,6 +84,9 @@ struct kprobe_ctlblk {
82 unsigned long kprobe_saved_epc; 84 unsigned long kprobe_saved_epc;
83 unsigned long jprobe_saved_sp; 85 unsigned long jprobe_saved_sp;
84 struct pt_regs jprobe_saved_regs; 86 struct pt_regs jprobe_saved_regs;
87 /* Per-thread fields, used while emulating branches */
88 unsigned long flags;
89 unsigned long target_epc;
85 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE]; 90 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
86 struct prev_kprobe prev_kprobe; 91 struct prev_kprobe prev_kprobe;
87}; 92};
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index cda1c8070b2..2f0becb4ec8 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21 21
22#define AR71XX_APB_BASE 0x18000000 22#define AR71XX_APB_BASE 0x18000000
23#define AR71XX_EHCI_BASE 0x1b000000
24#define AR71XX_EHCI_SIZE 0x1000
25#define AR71XX_OHCI_BASE 0x1c000000
26#define AR71XX_OHCI_SIZE 0x1000
23#define AR71XX_SPI_BASE 0x1f000000 27#define AR71XX_SPI_BASE 0x1f000000
24#define AR71XX_SPI_SIZE 0x01000000 28#define AR71XX_SPI_SIZE 0x01000000
25 29
@@ -27,6 +31,8 @@
27#define AR71XX_DDR_CTRL_SIZE 0x100 31#define AR71XX_DDR_CTRL_SIZE 0x100
28#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 32#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
29#define AR71XX_UART_SIZE 0x100 33#define AR71XX_UART_SIZE 0x100
34#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
35#define AR71XX_USB_CTRL_SIZE 0x100
30#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 36#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
31#define AR71XX_GPIO_SIZE 0x100 37#define AR71XX_GPIO_SIZE 0x100
32#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 38#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
@@ -34,9 +40,26 @@
34#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 40#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
35#define AR71XX_RESET_SIZE 0x100 41#define AR71XX_RESET_SIZE 0x100
36 42
43#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44#define AR7240_USB_CTRL_SIZE 0x100
45#define AR7240_OHCI_BASE 0x1b000000
46#define AR7240_OHCI_SIZE 0x1000
47
48#define AR724X_EHCI_BASE 0x1b000000
49#define AR724X_EHCI_SIZE 0x1000
50
51#define AR913X_EHCI_BASE 0x1b000000
52#define AR913X_EHCI_SIZE 0x1000
37#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 53#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
38#define AR913X_WMAC_SIZE 0x30000 54#define AR913X_WMAC_SIZE 0x30000
39 55
56#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
57#define AR933X_UART_SIZE 0x14
58#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
59#define AR933X_WMAC_SIZE 0x20000
60#define AR933X_EHCI_BASE 0x1b000000
61#define AR933X_EHCI_SIZE 0x1000
62
40/* 63/*
41 * DDR_CTRL block 64 * DDR_CTRL block
42 */ 65 */
@@ -63,6 +86,11 @@
63#define AR913X_DDR_REG_FLUSH_USB 0x84 86#define AR913X_DDR_REG_FLUSH_USB 0x84
64#define AR913X_DDR_REG_FLUSH_WMAC 0x88 87#define AR913X_DDR_REG_FLUSH_WMAC 0x88
65 88
89#define AR933X_DDR_REG_FLUSH_GE0 0x7c
90#define AR933X_DDR_REG_FLUSH_GE1 0x80
91#define AR933X_DDR_REG_FLUSH_USB 0x84
92#define AR933X_DDR_REG_FLUSH_WMAC 0x88
93
66/* 94/*
67 * PLL block 95 * PLL block
68 */ 96 */
@@ -104,6 +132,30 @@
104#define AR913X_AHB_DIV_SHIFT 19 132#define AR913X_AHB_DIV_SHIFT 19
105#define AR913X_AHB_DIV_MASK 0x1 133#define AR913X_AHB_DIV_MASK 0x1
106 134
135#define AR933X_PLL_CPU_CONFIG_REG 0x00
136#define AR933X_PLL_CLOCK_CTRL_REG 0x08
137
138#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
139#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
140#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
141#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
142#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
143#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
144
145#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
146#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
147#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
148#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
149#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
150#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
151#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
152
153/*
154 * USB_CONFIG block
155 */
156#define AR71XX_USB_CTRL_REG_FLADJ 0x00
157#define AR71XX_USB_CTRL_REG_CONFIG 0x04
158
107/* 159/*
108 * RESET block 160 * RESET block
109 */ 161 */
@@ -130,6 +182,13 @@
130 182
131#define AR724X_RESET_REG_RESET_MODULE 0x1c 183#define AR724X_RESET_REG_RESET_MODULE 0x1c
132 184
185#define AR933X_RESET_REG_RESET_MODULE 0x1c
186#define AR933X_RESET_REG_BOOTSTRAP 0xac
187
188#define MISC_INT_ETHSW BIT(12)
189#define MISC_INT_TIMER4 BIT(10)
190#define MISC_INT_TIMER3 BIT(9)
191#define MISC_INT_TIMER2 BIT(8)
133#define MISC_INT_DMA BIT(7) 192#define MISC_INT_DMA BIT(7)
134#define MISC_INT_OHCI BIT(6) 193#define MISC_INT_OHCI BIT(6)
135#define MISC_INT_PERFC BIT(5) 194#define MISC_INT_PERFC BIT(5)
@@ -158,14 +217,29 @@
158#define AR71XX_RESET_PCI_BUS BIT(1) 217#define AR71XX_RESET_PCI_BUS BIT(1)
159#define AR71XX_RESET_PCI_CORE BIT(0) 218#define AR71XX_RESET_PCI_CORE BIT(0)
160 219
220#define AR7240_RESET_USB_HOST BIT(5)
221#define AR7240_RESET_OHCI_DLL BIT(3)
222
161#define AR724X_RESET_GE1_MDIO BIT(23) 223#define AR724X_RESET_GE1_MDIO BIT(23)
162#define AR724X_RESET_GE0_MDIO BIT(22) 224#define AR724X_RESET_GE0_MDIO BIT(22)
163#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 225#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
164#define AR724X_RESET_PCIE_PHY BIT(7) 226#define AR724X_RESET_PCIE_PHY BIT(7)
165#define AR724X_RESET_PCIE BIT(6) 227#define AR724X_RESET_PCIE BIT(6)
166#define AR724X_RESET_OHCI_DLL BIT(3) 228#define AR724X_RESET_USB_HOST BIT(5)
229#define AR724X_RESET_USB_PHY BIT(4)
230#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
167 231
168#define AR913X_RESET_AMBA2WMAC BIT(22) 232#define AR913X_RESET_AMBA2WMAC BIT(22)
233#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
234#define AR913X_RESET_USB_HOST BIT(5)
235#define AR913X_RESET_USB_PHY BIT(4)
236
237#define AR933X_RESET_WMAC BIT(11)
238#define AR933X_RESET_USB_HOST BIT(5)
239#define AR933X_RESET_USB_PHY BIT(4)
240#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
241
242#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
169 243
170#define REV_ID_MAJOR_MASK 0xfff0 244#define REV_ID_MAJOR_MASK 0xfff0
171#define REV_ID_MAJOR_AR71XX 0x00a0 245#define REV_ID_MAJOR_AR71XX 0x00a0
@@ -173,6 +247,8 @@
173#define REV_ID_MAJOR_AR7240 0x00c0 247#define REV_ID_MAJOR_AR7240 0x00c0
174#define REV_ID_MAJOR_AR7241 0x0100 248#define REV_ID_MAJOR_AR7241 0x0100
175#define REV_ID_MAJOR_AR7242 0x1100 249#define REV_ID_MAJOR_AR7242 0x1100
250#define REV_ID_MAJOR_AR9330 0x0110
251#define REV_ID_MAJOR_AR9331 0x1110
176 252
177#define AR71XX_REV_ID_MINOR_MASK 0x3 253#define AR71XX_REV_ID_MINOR_MASK 0x3
178#define AR71XX_REV_ID_MINOR_AR7130 0x0 254#define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -187,6 +263,8 @@
187#define AR913X_REV_ID_REVISION_MASK 0x3 263#define AR913X_REV_ID_REVISION_MASK 0x3
188#define AR913X_REV_ID_REVISION_SHIFT 2 264#define AR913X_REV_ID_REVISION_SHIFT 2
189 265
266#define AR933X_REV_ID_REVISION_MASK 0x3
267
190#define AR724X_REV_ID_REVISION_MASK 0x3 268#define AR724X_REV_ID_REVISION_MASK 0x3
191 269
192/* 270/*
@@ -229,5 +307,6 @@
229#define AR71XX_GPIO_COUNT 16 307#define AR71XX_GPIO_COUNT 16
230#define AR724X_GPIO_COUNT 18 308#define AR724X_GPIO_COUNT 18
231#define AR913X_GPIO_COUNT 22 309#define AR913X_GPIO_COUNT 22
310#define AR933X_GPIO_COUNT 30
232 311
233#endif /* __ASM_MACH_AR71XX_REGS_H */ 312#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 00000000000..52730555937
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,67 @@
1/*
2 * Atheros AR933X UART defines
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __AR933X_UART_H
12#define __AR933X_UART_H
13
14#define AR933X_UART_REGS_SIZE 20
15#define AR933X_UART_FIFO_SIZE 16
16
17#define AR933X_UART_DATA_REG 0x00
18#define AR933X_UART_CS_REG 0x04
19#define AR933X_UART_CLOCK_REG 0x08
20#define AR933X_UART_INT_REG 0x0c
21#define AR933X_UART_INT_EN_REG 0x10
22
23#define AR933X_UART_DATA_TX_RX_MASK 0xff
24#define AR933X_UART_DATA_RX_CSR BIT(8)
25#define AR933X_UART_DATA_TX_CSR BIT(9)
26
27#define AR933X_UART_CS_PARITY_S 0
28#define AR933X_UART_CS_PARITY_M 0x3
29#define AR933X_UART_CS_PARITY_NONE 0
30#define AR933X_UART_CS_PARITY_ODD 1
31#define AR933X_UART_CS_PARITY_EVEN 2
32#define AR933X_UART_CS_IF_MODE_S 2
33#define AR933X_UART_CS_IF_MODE_M 0x3
34#define AR933X_UART_CS_IF_MODE_NONE 0
35#define AR933X_UART_CS_IF_MODE_DTE 1
36#define AR933X_UART_CS_IF_MODE_DCE 2
37#define AR933X_UART_CS_FLOW_CTRL_S 4
38#define AR933X_UART_CS_FLOW_CTRL_M 0x3
39#define AR933X_UART_CS_DMA_EN BIT(6)
40#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
41#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
42#define AR933X_UART_CS_TX_READY BIT(9)
43#define AR933X_UART_CS_RX_BREAK BIT(10)
44#define AR933X_UART_CS_TX_BREAK BIT(11)
45#define AR933X_UART_CS_HOST_INT BIT(12)
46#define AR933X_UART_CS_HOST_INT_EN BIT(13)
47#define AR933X_UART_CS_TX_BUSY BIT(14)
48#define AR933X_UART_CS_RX_BUSY BIT(15)
49
50#define AR933X_UART_CLOCK_STEP_M 0xffff
51#define AR933X_UART_CLOCK_SCALE_M 0xfff
52#define AR933X_UART_CLOCK_SCALE_S 16
53#define AR933X_UART_CLOCK_STEP_M 0xffff
54
55#define AR933X_UART_INT_RX_VALID BIT(0)
56#define AR933X_UART_INT_TX_READY BIT(1)
57#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
58#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
59#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
60#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
61#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
62#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
63#define AR933X_UART_INT_RX_FULL BIT(8)
64#define AR933X_UART_INT_TX_EMPTY BIT(9)
65#define AR933X_UART_INT_ALLINTS 0x3ff
66
67#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
new file mode 100644
index 00000000000..6cb30f2b719
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
@@ -0,0 +1,18 @@
1/*
2 * Platform data definition for Atheros AR933X UART
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef _AR933X_UART_PLATFORM_H
12#define _AR933X_UART_PLATFORM_H
13
14struct ar933x_uart_platform_data {
15 unsigned uartclk;
16};
17
18#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 6a9f168506f..6d0c6c9d562 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,10 +26,13 @@ enum ath79_soc_type {
26 ATH79_SOC_AR7241, 26 ATH79_SOC_AR7241,
27 ATH79_SOC_AR7242, 27 ATH79_SOC_AR7242,
28 ATH79_SOC_AR9130, 28 ATH79_SOC_AR9130,
29 ATH79_SOC_AR9132 29 ATH79_SOC_AR9132,
30 ATH79_SOC_AR9330,
31 ATH79_SOC_AR9331,
30}; 32};
31 33
32extern enum ath79_soc_type ath79_soc; 34extern enum ath79_soc_type ath79_soc;
35extern unsigned int ath79_soc_rev;
33 36
34static inline int soc_is_ar71xx(void) 37static inline int soc_is_ar71xx(void)
35{ 38{
@@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
66 ath79_soc == ATH79_SOC_AR9132); 69 ath79_soc == ATH79_SOC_AR9132);
67} 70}
68 71
72static inline int soc_is_ar933x(void)
73{
74 return (ath79_soc == ATH79_SOC_AR9330 ||
75 ath79_soc == ATH79_SOC_AR9331);
76}
77
69extern void __iomem *ath79_ddr_base; 78extern void __iomem *ath79_ddr_base;
70extern void __iomem *ath79_pll_base; 79extern void __iomem *ath79_pll_base;
71extern void __iomem *ath79_reset_base; 80extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 189bc6eb9c1..519958fe4e3 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,10 @@
10#define __ASM_MACH_ATH79_IRQ_H 10#define __ASM_MACH_ATH79_IRQ_H
11 11
12#define MIPS_CPU_IRQ_BASE 0 12#define MIPS_CPU_IRQ_BASE 0
13#define NR_IRQS 16 13#define NR_IRQS 40
14 14
15#define ATH79_MISC_IRQ_BASE 8 15#define ATH79_MISC_IRQ_BASE 8
16#define ATH79_MISC_IRQ_COUNT 8 16#define ATH79_MISC_IRQ_COUNT 32
17 17
18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) 18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) 19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
@@ -30,6 +30,10 @@
30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) 30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) 31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) 32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
33#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
34#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
35#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
36#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
33 37
34#include_next <irq.h> 38#include_next <irq.h>
35 39
diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 00000000000..454885fa30c
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
1/*
2 * Atheros 724x PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
12#define __ASM_MACH_ATH79_PCI_ATH724X_H
13
14struct ath724x_pci_data {
15 int irq;
16 void *pdata;
17};
18
19void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
20
21#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index de24ec57dd2..569828d3cca 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
136#define ALCHEMY_CPU_AU1100 2 136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3 137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4 138#define ALCHEMY_CPU_AU1200 4
139#define ALCHEMY_CPU_AU1300 5
139 140
140static inline int alchemy_get_cputype(void) 141static inline int alchemy_get_cputype(void)
141{ 142{
@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
156 case 0x05030000: 157 case 0x05030000:
157 return ALCHEMY_CPU_AU1200; 158 return ALCHEMY_CPU_AU1200;
158 break; 159 break;
160 case 0x800c0000:
161 return ALCHEMY_CPU_AU1300;
162 break;
159 } 163 }
160 164
161 return ALCHEMY_CPU_UNKNOWN; 165 return ALCHEMY_CPU_UNKNOWN;
@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
166{ 170{
167 switch (type) { 171 switch (type) {
168 case ALCHEMY_CPU_AU1000: 172 case ALCHEMY_CPU_AU1000:
173 case ALCHEMY_CPU_AU1300:
169 return 4; 174 return 4;
170 case ALCHEMY_CPU_AU1500: 175 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200: 176 case ALCHEMY_CPU_AU1200:
@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
243/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 248/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
244void alchemy_sleep_au1000(void); 249void alchemy_sleep_au1000(void);
245void alchemy_sleep_au1550(void); 250void alchemy_sleep_au1550(void);
251void alchemy_sleep_au1300(void);
246void au_sleep(void); 252void au_sleep(void);
247 253
248/* USB: drivers/usb/host/alchemy-common.c */ 254/* USB: drivers/usb/host/alchemy-common.c */
@@ -251,6 +257,7 @@ enum alchemy_usb_block {
251 ALCHEMY_USB_UDC0, 257 ALCHEMY_USB_UDC0,
252 ALCHEMY_USB_EHCI0, 258 ALCHEMY_USB_EHCI0,
253 ALCHEMY_USB_OTG0, 259 ALCHEMY_USB_OTG0,
260 ALCHEMY_USB_OHCI1,
254}; 261};
255int alchemy_usb_control(int block, int enable); 262int alchemy_usb_control(int block, int enable);
256 263
@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
263 unsigned long pci_cfg_clr; 270 unsigned long pci_cfg_clr;
264}; 271};
265 272
266/* SOC Interrupt numbers */ 273/* Multifunction pins: Each of these pins can either be assigned to the
274 * GPIO controller or a on-chip peripheral.
275 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
276 * assign one of these to either the GPIO controller or the device.
277 */
278enum au1300_multifunc_pins {
279 /* wake-from-str pins 0-3 */
280 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
281 AU1300_PIN_WAKE3,
282 /* external clock sources for PSCs: 4-5 */
283 AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
284 /* 8bit MMC interface on SD0: 6-9 */
285 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
286 AU1300_PIN_SD0DAT7,
287 /* aux clk input for freqgen 3: 10 */
288 AU1300_PIN_FG3AUX,
289 /* UART1 pins: 11-18 */
290 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
291 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
292 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
293 /* UART0 pins: 19-24 */
294 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
295 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
296 /* UART2: 25-26 */
297 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
298 /* UART3: 27-28 */
299 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
300 /* LCD controller PWMs, ext pixclock: 29-31 */
301 AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
302 /* SD1 interface: 32-37 */
303 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
304 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
305 /* SD2 interface: 38-43 */
306 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
307 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
308 /* PSC0/1 clocks: 44-45 */
309 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
310 /* PSCs: 46-49/50-53/54-57/58-61 */
311 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
312 AU1300_PIN_PSC0D1,
313 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
314 AU1300_PIN_PSC1D1,
315 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
316 AU1300_PIN_PSC2D1,
317 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
318 AU1300_PIN_PSC3D1,
319 /* PCMCIA interface: 62-70 */
320 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
321 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
322 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
323 /* camera interface H/V sync inputs: 71-72 */
324 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
325 /* PSC2/3 clocks: 73-74 */
326 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
327};
328
329/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
330extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
331extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
332extern void au1300_set_irq_priority(unsigned int irq, int p);
333extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
334
335/* Au1300 allows to disconnect certain blocks from internal power supply */
336enum au1300_vss_block {
337 AU1300_VSS_MPE = 0,
338 AU1300_VSS_BSA,
339 AU1300_VSS_GPE,
340 AU1300_VSS_MGP,
341};
267 342
343extern void au1300_vss_block_control(int block, int enable);
344
345
346/* SOC Interrupt numbers */
347/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
268#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 348#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
269#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 349#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
270#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) 350#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
271#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 351#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
272#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 352#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
273 353
354/* Au1300-style (GPIC): 1 controller with up to 128 sources */
355#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
356#define ALCHEMY_GPIC_INT_NUM 128
357#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
358
274enum soc_au1000_ints { 359enum soc_au1000_ints {
275 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, 360 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
276 AU1000_UART0_INT = AU1000_FIRST_INT, 361 AU1000_UART0_INT = AU1000_FIRST_INT,
@@ -591,24 +676,77 @@ enum soc_au1200_ints {
591 676
592#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 677#endif /* !defined (_LANGUAGE_ASSEMBLY) */
593 678
679/* Au1300 peripheral interrupt numbers */
680#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
681#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
682#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
683#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
684#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
685#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
686#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
687#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
688#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
689#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
690#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
691#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
692#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
693#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
694#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
695#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
696#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
697#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
698#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
699#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
700#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
701#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
702#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
703#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
704#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
705#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
706#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
707#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
708#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
709#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
710#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
711#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
712#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
713
714/**********************************************************************/
715
594/* 716/*
595 * Physical base addresses for integrated peripherals 717 * Physical base addresses for integrated peripherals
596 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 718 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
597 */ 719 */
598 720
599#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 721#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
722#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
723#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
724#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
725#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
726#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
727#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
728#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
600#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ 729#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
601#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ 730#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
731#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
602#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ 732#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
603#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ 733#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
604#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 734#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
735#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
605#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ 736#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
606#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ 737#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
607#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ 738#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
608#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ 739#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
740#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
741#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
609#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ 742#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
743#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
610#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ 744#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
611#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ 745#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
746#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
747#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
748#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
749#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
612#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ 750#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
613#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ 751#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
614#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ 752#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
@@ -622,37 +760,96 @@ enum soc_au1200_ints {
622#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ 760#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
623#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ 761#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
624#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 762#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
625#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ 763#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
626#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ 764#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
627#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ 765#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
628#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ 766#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
629#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ 767#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
768#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
630#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ 769#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
631#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 770#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
632#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 771#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
633#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ 772#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
634#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ 773#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
635#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ 774#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
636#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ 775#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
637#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ 776#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
638#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ 777#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
639#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ 778#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
779#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
780#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
640#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ 781#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
641#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ 782#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
642#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ 783#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
643#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ 784#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
644#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ 785#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
645#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ 786#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
787#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
788#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
789#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
790#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
791#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
792#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
646#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ 793#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
647#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ 794#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
648#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ 795#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
649#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ 796#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
650#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ 797#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
651#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ 798#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
652#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ 799#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
653#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ 800#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
654#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ 801#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
655 802
803/**********************************************************************/
804
805
806/*
807 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
808 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
809 */
810#define AU1300_GPIC_PINVAL 0x0000
811#define AU1300_GPIC_PINVALCLR 0x0010
812#define AU1300_GPIC_IPEND 0x0020
813#define AU1300_GPIC_PRIENC 0x0030
814#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
815#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
816#define AU1300_GPIC_DMASEL 0x0060
817#define AU1300_GPIC_DEVSEL 0x0080
818#define AU1300_GPIC_DEVCLR 0x0090
819#define AU1300_GPIC_RSTVAL 0x00a0
820/* pin configuration space. one 32bit register for up to 128 IRQs */
821#define AU1300_GPIC_PINCFG 0x1000
822
823#define GPIC_GPIO_TO_BIT(gpio) \
824 (1 << ((gpio) & 0x1f))
825
826#define GPIC_GPIO_BANKOFF(gpio) \
827 (((gpio) >> 5) * 4)
828
829/* Pin Control bits: who owns the pin, what does it do */
830#define GPIC_CFG_PC_GPIN 0
831#define GPIC_CFG_PC_DEV 1
832#define GPIC_CFG_PC_GPOLOW 2
833#define GPIC_CFG_PC_GPOHIGH 3
834#define GPIC_CFG_PC_MASK 3
835
836/* assign pin to MIPS IRQ line */
837#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
838#define GPIC_CFG_IL_MASK (3 << 2)
839
840/* pin interrupt type setup */
841#define GPIC_CFG_IC_OFF (0 << 4)
842#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
843#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
844#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
845#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
846#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
847#define GPIC_CFG_IC_MASK (7 << 4)
848
849/* allow interrupt to wake cpu from 'wait' */
850#define GPIC_CFG_IDLEWAKE (1 << 7)
851
852/***********************************************************************/
656 853
657/* Au1000 SDRAM memory controller register offsets */ 854/* Au1000 SDRAM memory controller register offsets */
658#define AU1000_MEM_SDMODE0 0x0000 855#define AU1000_MEM_SDMODE0 0x0000
@@ -1068,44 +1265,20 @@ enum soc_au1200_ints {
1068#define SSI_ENABLE_CD (1 << 1) 1265#define SSI_ENABLE_CD (1 << 1)
1069#define SSI_ENABLE_E (1 << 0) 1266#define SSI_ENABLE_E (1 << 0)
1070 1267
1071/* IrDA Controller */ 1268
1072#define IRDA_BASE 0xB0300000 1269/*
1073#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 1270 * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
1074#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 1271 * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a
1075#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 1272 * CPLD has to be told about the mode.
1076#define IR_RING_SIZE (IRDA_BASE + 0x0C) 1273 */
1077#define IR_RING_PROMPT (IRDA_BASE + 0x10) 1274#define AU1000_IRDA_PHY_MODE_OFF 0
1078#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 1275#define AU1000_IRDA_PHY_MODE_SIR 1
1079#define IR_INT_CLEAR (IRDA_BASE + 0x18) 1276#define AU1000_IRDA_PHY_MODE_FIR 2
1080#define IR_CONFIG_1 (IRDA_BASE + 0x20) 1277
1081# define IR_RX_INVERT_LED (1 << 0) 1278struct au1k_irda_platform_data {
1082# define IR_TX_INVERT_LED (1 << 1) 1279 void(*set_phy_mode)(int mode);
1083# define IR_ST (1 << 2) 1280};
1084# define IR_SF (1 << 3) 1281
1085# define IR_SIR (1 << 4)
1086# define IR_MIR (1 << 5)
1087# define IR_FIR (1 << 6)
1088# define IR_16CRC (1 << 7)
1089# define IR_TD (1 << 8)
1090# define IR_RX_ALL (1 << 9)
1091# define IR_DMA_ENABLE (1 << 10)
1092# define IR_RX_ENABLE (1 << 11)
1093# define IR_TX_ENABLE (1 << 12)
1094# define IR_LOOPBACK (1 << 14)
1095# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1096 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1097#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1098#define IR_ENABLE (IRDA_BASE + 0x28)
1099# define IR_RX_STATUS (1 << 9)
1100# define IR_TX_STATUS (1 << 10)
1101#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1102#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1103#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1104#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1105#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1106# define IR_MODE_INV (1 << 0)
1107# define IR_ONE_PIN (1 << 1)
1108#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1109 1282
1110/* GPIO */ 1283/* GPIO */
1111#define SYS_PINFUNC 0xB190002C 1284#define SYS_PINFUNC 0xB190002C
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index 94000a3b6f0..e221659f1bc 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
130#define SD_CONFIG2_DF (0x00000008) 130#define SD_CONFIG2_DF (0x00000008)
131#define SD_CONFIG2_DC (0x00000010) 131#define SD_CONFIG2_DC (0x00000010)
132#define SD_CONFIG2_xx2 (0x000000e0) 132#define SD_CONFIG2_xx2 (0x000000e0)
133#define SD_CONFIG2_BB (0x00000080)
133#define SD_CONFIG2_WB (0x00000100) 134#define SD_CONFIG2_WB (0x00000100)
134#define SD_CONFIG2_RW (0x00000200) 135#define SD_CONFIG2_RW (0x00000200)
136#define SD_CONFIG2_DP (0x00000400)
135 137
136 138
137/* 139/*
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
new file mode 100644
index 00000000000..b3c87cc64bb
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h
@@ -0,0 +1,14 @@
1/*
2 * platform data for au1200fb driver.
3 */
4
5#ifndef _AU1200FB_PLAT_H_
6#define _AU1200FB_PLAT_H_
7
8struct au1200fb_platdata {
9 int (*panel_index)(void);
10 int (*panel_init)(void);
11 int (*panel_shutdown)(void);
12};
13
14#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
new file mode 100644
index 00000000000..ad4c0a03afe
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h
@@ -0,0 +1,16 @@
1/*
2 * platform data for the Au1550 NAND driver
3 */
4
5#ifndef _AU1550ND_H_
6#define _AU1550ND_H_
7
8#include <linux/mtd/partitions.h>
9
10struct au1550nd_platdata {
11 struct mtd_partition *parts;
12 int num_parts;
13 int devwidth; /* 0 = 8bit device, 1 = 16bit device */
14};
15
16#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 323ce2d145f..217810e1836 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
183#define AU1200_DSCR_CMD0_PSC1_SYNC 25 183#define AU1200_DSCR_CMD0_PSC1_SYNC 25
184#define AU1200_DSCR_CMD0_CIM_SYNC 26 184#define AU1200_DSCR_CMD0_CIM_SYNC 26
185 185
186#define AU1300_DSCR_CMD0_UART0_TX 0
187#define AU1300_DSCR_CMD0_UART0_RX 1
188#define AU1300_DSCR_CMD0_UART1_TX 2
189#define AU1300_DSCR_CMD0_UART1_RX 3
190#define AU1300_DSCR_CMD0_UART2_TX 4
191#define AU1300_DSCR_CMD0_UART2_RX 5
192#define AU1300_DSCR_CMD0_UART3_TX 6
193#define AU1300_DSCR_CMD0_UART3_RX 7
194#define AU1300_DSCR_CMD0_SDMS_TX0 8
195#define AU1300_DSCR_CMD0_SDMS_RX0 9
196#define AU1300_DSCR_CMD0_SDMS_TX1 10
197#define AU1300_DSCR_CMD0_SDMS_RX1 11
198#define AU1300_DSCR_CMD0_AES_TX 12
199#define AU1300_DSCR_CMD0_AES_RX 13
200#define AU1300_DSCR_CMD0_PSC0_TX 14
201#define AU1300_DSCR_CMD0_PSC0_RX 15
202#define AU1300_DSCR_CMD0_PSC1_TX 16
203#define AU1300_DSCR_CMD0_PSC1_RX 17
204#define AU1300_DSCR_CMD0_PSC2_TX 18
205#define AU1300_DSCR_CMD0_PSC2_RX 19
206#define AU1300_DSCR_CMD0_PSC3_TX 20
207#define AU1300_DSCR_CMD0_PSC3_RX 21
208#define AU1300_DSCR_CMD0_LCD 22
209#define AU1300_DSCR_CMD0_NAND_FLASH 23
210#define AU1300_DSCR_CMD0_SDMS_TX2 24
211#define AU1300_DSCR_CMD0_SDMS_RX2 25
212#define AU1300_DSCR_CMD0_CIM_SYNC 26
213#define AU1300_DSCR_CMD0_UDMA 27
214#define AU1300_DSCR_CMD0_DMA_REQ0 28
215#define AU1300_DSCR_CMD0_DMA_REQ1 29
216
186#define DSCR_CMD0_THROTTLE 30 217#define DSCR_CMD0_THROTTLE 30
187#define DSCR_CMD0_ALWAYS 31 218#define DSCR_CMD0_ALWAYS 31
188#define DSCR_NDEV_IDS 32 219#define DSCR_NDEV_IDS 32
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index d5df0cab9b8..3f741af37d4 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,12 +13,14 @@
13#define cpu_has_4k_cache 1 13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0 14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0 15#define cpu_has_fpu 0
16#define cpu_has_32fpr 0
16#define cpu_has_counter 1 17#define cpu_has_counter 1
17#define cpu_has_watch 1 18#define cpu_has_watch 1
18#define cpu_has_divec 1 19#define cpu_has_divec 1
19#define cpu_has_vce 0 20#define cpu_has_vce 0
20#define cpu_has_cache_cdex_p 0 21#define cpu_has_cache_cdex_p 0
21#define cpu_has_cache_cdex_s 0 22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
22#define cpu_has_mcheck 1 24#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1 25#define cpu_has_ejtag 1
24#define cpu_has_llsc 1 26#define cpu_has_llsc 1
@@ -29,6 +31,7 @@
29#define cpu_has_vtag_icache 0 31#define cpu_has_vtag_icache 0
30#define cpu_has_dc_aliases 0 32#define cpu_has_dc_aliases 0
31#define cpu_has_ic_fills_f_dc 1 33#define cpu_has_ic_fills_f_dc 1
34#define cpu_has_pindexed_dcache 0
32#define cpu_has_mips32r1 1 35#define cpu_has_mips32r1 1
33#define cpu_has_mips32r2 0 36#define cpu_has_mips32r2 0
34#define cpu_has_mips64r1 0 37#define cpu_has_mips64r1 0
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 00000000000..556e1be20bf
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,241 @@
1/*
2 * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
3 *
4 * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#ifndef _GPIO_AU1300_H_
8#define _GPIO_AU1300_H_
9
10#include <asm/addrspace.h>
11#include <asm/io.h>
12#include <asm/mach-au1x00/au1000.h>
13
14/* with the current GPIC design, up to 128 GPIOs are possible.
15 * The only implementation so far is in the Au1300, which has 75 externally
16 * available GPIOs.
17 */
18#define AU1300_GPIO_BASE 0
19#define AU1300_GPIO_NUM 75
20#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
21
22#define AU1300_GPIC_ADDR \
23 (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
24
25static inline int au1300_gpio_get_value(unsigned int gpio)
26{
27 void __iomem *roff = AU1300_GPIC_ADDR;
28 int bit;
29
30 gpio -= AU1300_GPIO_BASE;
31 roff += GPIC_GPIO_BANKOFF(gpio);
32 bit = GPIC_GPIO_TO_BIT(gpio);
33 return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
34}
35
36static inline int au1300_gpio_direction_input(unsigned int gpio)
37{
38 void __iomem *roff = AU1300_GPIC_ADDR;
39 unsigned long bit;
40
41 gpio -= AU1300_GPIO_BASE;
42
43 roff += GPIC_GPIO_BANKOFF(gpio);
44 bit = GPIC_GPIO_TO_BIT(gpio);
45 __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
46 wmb();
47
48 return 0;
49}
50
51static inline int au1300_gpio_set_value(unsigned int gpio, int v)
52{
53 void __iomem *roff = AU1300_GPIC_ADDR;
54 unsigned long bit;
55
56 gpio -= AU1300_GPIO_BASE;
57
58 roff += GPIC_GPIO_BANKOFF(gpio);
59 bit = GPIC_GPIO_TO_BIT(gpio);
60 __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
61 : AU1300_GPIC_PINVALCLR));
62 wmb();
63
64 return 0;
65}
66
67static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
68{
69 /* hw switches to output automatically */
70 return au1300_gpio_set_value(gpio, v);
71}
72
73static inline int au1300_gpio_to_irq(unsigned int gpio)
74{
75 return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
76}
77
78static inline int au1300_irq_to_gpio(unsigned int irq)
79{
80 return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
81}
82
83static inline int au1300_gpio_is_valid(unsigned int gpio)
84{
85 int ret;
86
87 switch (alchemy_get_cputype()) {
88 case ALCHEMY_CPU_AU1300:
89 ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
90 break;
91 default:
92 ret = 0;
93 }
94 return ret;
95}
96
97static inline int au1300_gpio_cansleep(unsigned int gpio)
98{
99 return 0;
100}
101
102/* hardware remembers gpio 0-63 levels on powerup */
103static inline int au1300_gpio_getinitlvl(unsigned int gpio)
104{
105 void __iomem *roff = AU1300_GPIC_ADDR;
106 unsigned long v;
107
108 if (unlikely(gpio > 63))
109 return 0;
110 else if (gpio > 31) {
111 gpio -= 32;
112 roff += 4;
113 }
114
115 v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
116 return (v >> gpio) & 1;
117}
118
119/**********************************************************************/
120
121/* Linux gpio framework integration.
122*
123* 4 use cases of Alchemy GPIOS:
124*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
125* Board must register gpiochips.
126*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
127* A gpiochip for the 75 GPIOs is registered.
128*
129*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
130* the boards' gpio.h must provide the linux gpio wrapper functions,
131*
132*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
133* inlinable gpio functions are provided which enable access to the
134* Au1300 gpios only by using the numbers straight out of the data-
135* sheets.
136
137* Cases 1 and 3 are intended for boards which want to provide their own
138* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
139* which are in part provided by spare Au1300 GPIO pins and in part by
140* an external FPGA but you still want them to be accssible in linux
141* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
142* as required).
143*/
144
145#ifndef CONFIG_GPIOLIB
146
147#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
148
149#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
150
151static inline int gpio_direction_input(unsigned int gpio)
152{
153 return au1300_gpio_direction_input(gpio);
154}
155
156static inline int gpio_direction_output(unsigned int gpio, int v)
157{
158 return au1300_gpio_direction_output(gpio, v);
159}
160
161static inline int gpio_get_value(unsigned int gpio)
162{
163 return au1300_gpio_get_value(gpio);
164}
165
166static inline void gpio_set_value(unsigned int gpio, int v)
167{
168 au1300_gpio_set_value(gpio, v);
169}
170
171static inline int gpio_get_value_cansleep(unsigned gpio)
172{
173 return gpio_get_value(gpio);
174}
175
176static inline void gpio_set_value_cansleep(unsigned gpio, int value)
177{
178 gpio_set_value(gpio, value);
179}
180
181static inline int gpio_is_valid(unsigned int gpio)
182{
183 return au1300_gpio_is_valid(gpio);
184}
185
186static inline int gpio_cansleep(unsigned int gpio)
187{
188 return au1300_gpio_cansleep(gpio);
189}
190
191static inline int gpio_to_irq(unsigned int gpio)
192{
193 return au1300_gpio_to_irq(gpio);
194}
195
196static inline int irq_to_gpio(unsigned int irq)
197{
198 return au1300_irq_to_gpio(irq);
199}
200
201static inline int gpio_request(unsigned int gpio, const char *label)
202{
203 return 0;
204}
205
206static inline void gpio_free(unsigned int gpio)
207{
208}
209
210static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
211{
212 return -ENOSYS;
213}
214
215static inline void gpio_unexport(unsigned gpio)
216{
217}
218
219static inline int gpio_export(unsigned gpio, bool direction_may_change)
220{
221 return -ENOSYS;
222}
223
224static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
225{
226 return -ENOSYS;
227}
228
229static inline int gpio_export_link(struct device *dev, const char *name,
230 unsigned gpio)
231{
232 return -ENOSYS;
233}
234
235#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
236
237#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
238
239#endif /* CONFIG GPIOLIB */
240
241#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index fcdc8c4809d..22e7ff17fc4 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/mach-au1x00/au1000.h> 13#include <asm/mach-au1x00/au1000.h>
14#include <asm/mach-au1x00/gpio-au1000.h> 14#include <asm/mach-au1x00/gpio-au1000.h>
15#include <asm/mach-au1x00/gpio-au1300.h>
15 16
16/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before 17/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
17 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this 18 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
58 switch (alchemy_get_cputype()) { 59 switch (alchemy_get_cputype()) {
59 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: 60 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
60 return alchemy_irq_to_gpio(irq); 61 return alchemy_irq_to_gpio(irq);
62 case ALCHEMY_CPU_AU1300:
63 return au1300_irq_to_gpio(irq);
61 } 64 }
62 return -EINVAL; 65 return -EINVAL;
63} 66}
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85..5b8d15bb5fe 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
13#define BCM6345_CPU_ID 0x6345 13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358 15#define BCM6358_CPU_ID 0x6358
16#define BCM6368_CPU_ID 0x6368
16 17
17void __init bcm63xx_cpu_init(void); 18void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void); 19u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
71# define BCMCPU_IS_6358() (0) 72# define BCMCPU_IS_6358() (0)
72#endif 73#endif
73 74
75#ifdef CONFIG_BCM63XX_CPU_6368
76# ifdef bcm63xx_get_cpu_id
77# undef bcm63xx_get_cpu_id
78# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
79# define BCMCPU_RUNTIME_DETECT
80# else
81# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
82# endif
83# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
84#else
85# define BCMCPU_IS_6368() (0)
86#endif
87
74#ifndef bcm63xx_get_cpu_id 88#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured" 89#error "No CPU support configured"
76#endif 90#endif
@@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
88 RSET_UART1, 102 RSET_UART1,
89 RSET_GPIO, 103 RSET_GPIO,
90 RSET_SPI, 104 RSET_SPI,
105 RSET_SPI2,
91 RSET_UDC0, 106 RSET_UDC0,
92 RSET_OHCI0, 107 RSET_OHCI0,
93 RSET_OHCI_PRIV, 108 RSET_OHCI_PRIV,
@@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
98 RSET_ENET0, 113 RSET_ENET0,
99 RSET_ENET1, 114 RSET_ENET1,
100 RSET_ENETDMA, 115 RSET_ENETDMA,
116 RSET_ENETDMAC,
117 RSET_ENETDMAS,
118 RSET_ENETSW,
101 RSET_EHCI0, 119 RSET_EHCI0,
102 RSET_SDRAM, 120 RSET_SDRAM,
103 RSET_MEMC, 121 RSET_MEMC,
104 RSET_DDR, 122 RSET_DDR,
123 RSET_M2M,
124 RSET_ATM,
125 RSET_XTM,
126 RSET_XTMDMA,
127 RSET_XTMDMAC,
128 RSET_XTMDMAS,
129 RSET_PCM,
130 RSET_PCMDMA,
131 RSET_PCMDMAC,
132 RSET_PCMDMAS,
105}; 133};
106 134
107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
109#define RSET_WDT_SIZE 12 137#define RSET_WDT_SIZE 12
110#define RSET_ENET_SIZE 2048 138#define RSET_ENET_SIZE 2048
111#define RSET_ENETDMA_SIZE 2048 139#define RSET_ENETDMA_SIZE 2048
140#define RSET_ENETSW_SIZE 65536
112#define RSET_UART_SIZE 24 141#define RSET_UART_SIZE 24
113#define RSET_UDC_SIZE 256 142#define RSET_UDC_SIZE 256
114#define RSET_OHCI_SIZE 256 143#define RSET_OHCI_SIZE 256
115#define RSET_EHCI_SIZE 256 144#define RSET_EHCI_SIZE 256
116#define RSET_PCMCIA_SIZE 12 145#define RSET_PCMCIA_SIZE 12
146#define RSET_M2M_SIZE 256
147#define RSET_ATM_SIZE 4096
148#define RSET_XTM_SIZE 10240
149#define RSET_XTMDMA_SIZE 256
150#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
151#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
117 152
118/* 153/*
119 * 6338 register sets base address 154 * 6338 register sets base address
@@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
127#define BCM_6338_UART1_BASE (0xdeadbeef) 162#define BCM_6338_UART1_BASE (0xdeadbeef)
128#define BCM_6338_GPIO_BASE (0xfffe0400) 163#define BCM_6338_GPIO_BASE (0xfffe0400)
129#define BCM_6338_SPI_BASE (0xfffe0c00) 164#define BCM_6338_SPI_BASE (0xfffe0c00)
165#define BCM_6338_SPI2_BASE (0xdeadbeef)
130#define BCM_6338_UDC0_BASE (0xdeadbeef) 166#define BCM_6338_UDC0_BASE (0xdeadbeef)
131#define BCM_6338_USBDMA_BASE (0xfffe2400) 167#define BCM_6338_USBDMA_BASE (0xfffe2400)
132#define BCM_6338_OHCI0_BASE (0xdeadbeef) 168#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
136#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 172#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 173#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
138#define BCM_6338_DSL_BASE (0xfffe1000) 174#define BCM_6338_DSL_BASE (0xfffe1000)
139#define BCM_6338_SAR_BASE (0xfffe2000)
140#define BCM_6338_UBUS_BASE (0xdeadbeef) 175#define BCM_6338_UBUS_BASE (0xdeadbeef)
141#define BCM_6338_ENET0_BASE (0xfffe2800) 176#define BCM_6338_ENET0_BASE (0xfffe2800)
142#define BCM_6338_ENET1_BASE (0xdeadbeef) 177#define BCM_6338_ENET1_BASE (0xdeadbeef)
143#define BCM_6338_ENETDMA_BASE (0xfffe2400) 178#define BCM_6338_ENETDMA_BASE (0xfffe2400)
179#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
180#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
181#define BCM_6338_ENETSW_BASE (0xdeadbeef)
144#define BCM_6338_EHCI0_BASE (0xdeadbeef) 182#define BCM_6338_EHCI0_BASE (0xdeadbeef)
145#define BCM_6338_SDRAM_BASE (0xfffe3100) 183#define BCM_6338_SDRAM_BASE (0xfffe3100)
146#define BCM_6338_MEMC_BASE (0xdeadbeef) 184#define BCM_6338_MEMC_BASE (0xdeadbeef)
147#define BCM_6338_DDR_BASE (0xdeadbeef) 185#define BCM_6338_DDR_BASE (0xdeadbeef)
186#define BCM_6338_M2M_BASE (0xdeadbeef)
187#define BCM_6338_ATM_BASE (0xfffe2000)
188#define BCM_6338_XTM_BASE (0xdeadbeef)
189#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
190#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
191#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
192#define BCM_6338_PCM_BASE (0xdeadbeef)
193#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
194#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
195#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
148 196
149/* 197/*
150 * 6345 register sets base address 198 * 6345 register sets base address
@@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
158#define BCM_6345_UART1_BASE (0xdeadbeef) 206#define BCM_6345_UART1_BASE (0xdeadbeef)
159#define BCM_6345_GPIO_BASE (0xfffe0400) 207#define BCM_6345_GPIO_BASE (0xfffe0400)
160#define BCM_6345_SPI_BASE (0xdeadbeef) 208#define BCM_6345_SPI_BASE (0xdeadbeef)
209#define BCM_6345_SPI2_BASE (0xdeadbeef)
161#define BCM_6345_UDC0_BASE (0xdeadbeef) 210#define BCM_6345_UDC0_BASE (0xdeadbeef)
162#define BCM_6345_USBDMA_BASE (0xfffe2800) 211#define BCM_6345_USBDMA_BASE (0xfffe2800)
163#define BCM_6345_ENET0_BASE (0xfffe1800) 212#define BCM_6345_ENET0_BASE (0xfffe1800)
164#define BCM_6345_ENETDMA_BASE (0xfffe2800) 213#define BCM_6345_ENETDMA_BASE (0xfffe2800)
214#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
215#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
216#define BCM_6345_ENETSW_BASE (0xdeadbeef)
165#define BCM_6345_PCMCIA_BASE (0xfffe2028) 217#define BCM_6345_PCMCIA_BASE (0xfffe2028)
166#define BCM_6345_MPI_BASE (0xdeadbeef) 218#define BCM_6345_MPI_BASE (0xfffe2000)
167#define BCM_6345_OHCI0_BASE (0xfffe2100) 219#define BCM_6345_OHCI0_BASE (0xfffe2100)
168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 222#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
171#define BCM_6345_DSL_BASE (0xdeadbeef) 223#define BCM_6345_DSL_BASE (0xdeadbeef)
172#define BCM_6345_SAR_BASE (0xdeadbeef)
173#define BCM_6345_UBUS_BASE (0xdeadbeef) 224#define BCM_6345_UBUS_BASE (0xdeadbeef)
174#define BCM_6345_ENET1_BASE (0xdeadbeef) 225#define BCM_6345_ENET1_BASE (0xdeadbeef)
175#define BCM_6345_EHCI0_BASE (0xdeadbeef) 226#define BCM_6345_EHCI0_BASE (0xdeadbeef)
176#define BCM_6345_SDRAM_BASE (0xfffe2300) 227#define BCM_6345_SDRAM_BASE (0xfffe2300)
177#define BCM_6345_MEMC_BASE (0xdeadbeef) 228#define BCM_6345_MEMC_BASE (0xdeadbeef)
178#define BCM_6345_DDR_BASE (0xdeadbeef) 229#define BCM_6345_DDR_BASE (0xdeadbeef)
230#define BCM_6345_M2M_BASE (0xdeadbeef)
231#define BCM_6345_ATM_BASE (0xfffe4000)
232#define BCM_6345_XTM_BASE (0xdeadbeef)
233#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
234#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
235#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
236#define BCM_6345_PCM_BASE (0xdeadbeef)
237#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
238#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
239#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
179 240
180/* 241/*
181 * 6348 register sets base address 242 * 6348 register sets base address
@@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
188#define BCM_6348_UART1_BASE (0xdeadbeef) 249#define BCM_6348_UART1_BASE (0xdeadbeef)
189#define BCM_6348_GPIO_BASE (0xfffe0400) 250#define BCM_6348_GPIO_BASE (0xfffe0400)
190#define BCM_6348_SPI_BASE (0xfffe0c00) 251#define BCM_6348_SPI_BASE (0xfffe0c00)
252#define BCM_6348_SPI2_BASE (0xdeadbeef)
191#define BCM_6348_UDC0_BASE (0xfffe1000) 253#define BCM_6348_UDC0_BASE (0xfffe1000)
192#define BCM_6348_OHCI0_BASE (0xfffe1b00) 254#define BCM_6348_OHCI0_BASE (0xfffe1b00)
193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 255#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
@@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
195#define BCM_6348_MPI_BASE (0xfffe2000) 257#define BCM_6348_MPI_BASE (0xfffe2000)
196#define BCM_6348_PCMCIA_BASE (0xfffe2054) 258#define BCM_6348_PCMCIA_BASE (0xfffe2054)
197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 259#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
260#define BCM_6348_M2M_BASE (0xfffe2800)
198#define BCM_6348_DSL_BASE (0xfffe3000) 261#define BCM_6348_DSL_BASE (0xfffe3000)
199#define BCM_6348_ENET0_BASE (0xfffe6000) 262#define BCM_6348_ENET0_BASE (0xfffe6000)
200#define BCM_6348_ENET1_BASE (0xfffe6800) 263#define BCM_6348_ENET1_BASE (0xfffe6800)
201#define BCM_6348_ENETDMA_BASE (0xfffe7000) 264#define BCM_6348_ENETDMA_BASE (0xfffe7000)
265#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
266#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
267#define BCM_6348_ENETSW_BASE (0xdeadbeef)
202#define BCM_6348_EHCI0_BASE (0xdeadbeef) 268#define BCM_6348_EHCI0_BASE (0xdeadbeef)
203#define BCM_6348_SDRAM_BASE (0xfffe2300) 269#define BCM_6348_SDRAM_BASE (0xfffe2300)
204#define BCM_6348_MEMC_BASE (0xdeadbeef) 270#define BCM_6348_MEMC_BASE (0xdeadbeef)
205#define BCM_6348_DDR_BASE (0xdeadbeef) 271#define BCM_6348_DDR_BASE (0xdeadbeef)
272#define BCM_6348_ATM_BASE (0xfffe4000)
273#define BCM_6348_XTM_BASE (0xdeadbeef)
274#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
275#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
276#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
277#define BCM_6348_PCM_BASE (0xdeadbeef)
278#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
279#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
280#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
206 281
207/* 282/*
208 * 6358 register sets base address 283 * 6358 register sets base address
@@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
215#define BCM_6358_UART1_BASE (0xfffe0120) 290#define BCM_6358_UART1_BASE (0xfffe0120)
216#define BCM_6358_GPIO_BASE (0xfffe0080) 291#define BCM_6358_GPIO_BASE (0xfffe0080)
217#define BCM_6358_SPI_BASE (0xdeadbeef) 292#define BCM_6358_SPI_BASE (0xdeadbeef)
293#define BCM_6358_SPI2_BASE (0xfffe0800)
218#define BCM_6358_UDC0_BASE (0xfffe0800) 294#define BCM_6358_UDC0_BASE (0xfffe0800)
219#define BCM_6358_OHCI0_BASE (0xfffe1400) 295#define BCM_6358_OHCI0_BASE (0xfffe1400)
220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 296#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
222#define BCM_6358_MPI_BASE (0xfffe1000) 298#define BCM_6358_MPI_BASE (0xfffe1000)
223#define BCM_6358_PCMCIA_BASE (0xfffe1054) 299#define BCM_6358_PCMCIA_BASE (0xfffe1054)
224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 300#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
301#define BCM_6358_M2M_BASE (0xdeadbeef)
225#define BCM_6358_DSL_BASE (0xfffe3000) 302#define BCM_6358_DSL_BASE (0xfffe3000)
226#define BCM_6358_ENET0_BASE (0xfffe4000) 303#define BCM_6358_ENET0_BASE (0xfffe4000)
227#define BCM_6358_ENET1_BASE (0xfffe4800) 304#define BCM_6358_ENET1_BASE (0xfffe4800)
228#define BCM_6358_ENETDMA_BASE (0xfffe5000) 305#define BCM_6358_ENETDMA_BASE (0xfffe5000)
306#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
307#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
308#define BCM_6358_ENETSW_BASE (0xdeadbeef)
229#define BCM_6358_EHCI0_BASE (0xfffe1300) 309#define BCM_6358_EHCI0_BASE (0xfffe1300)
230#define BCM_6358_SDRAM_BASE (0xdeadbeef) 310#define BCM_6358_SDRAM_BASE (0xdeadbeef)
231#define BCM_6358_MEMC_BASE (0xfffe1200) 311#define BCM_6358_MEMC_BASE (0xfffe1200)
232#define BCM_6358_DDR_BASE (0xfffe12a0) 312#define BCM_6358_DDR_BASE (0xfffe12a0)
313#define BCM_6358_ATM_BASE (0xfffe2000)
314#define BCM_6358_XTM_BASE (0xdeadbeef)
315#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
316#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
317#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
318#define BCM_6358_PCM_BASE (0xfffe1600)
319#define BCM_6358_PCMDMA_BASE (0xfffe1800)
320#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
322
323
324/*
325 * 6368 register sets base address
326 */
327#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
328#define BCM_6368_PERF_BASE (0xb0000000)
329#define BCM_6368_TIMER_BASE (0xb0000040)
330#define BCM_6368_WDT_BASE (0xb000005c)
331#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef)
345#define BCM_6368_ENET0_BASE (0xdeadbeef)
346#define BCM_6368_ENET1_BASE (0xdeadbeef)
347#define BCM_6368_ENETDMA_BASE (0xb0006800)
348#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
349#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
350#define BCM_6368_ENETSW_BASE (0xb0f00000)
351#define BCM_6368_EHCI0_BASE (0xb0001500)
352#define BCM_6368_SDRAM_BASE (0xdeadbeef)
353#define BCM_6368_MEMC_BASE (0xb0001200)
354#define BCM_6368_DDR_BASE (0xb0001280)
355#define BCM_6368_ATM_BASE (0xdeadbeef)
356#define BCM_6368_XTM_BASE (0xb0001800)
357#define BCM_6368_XTMDMA_BASE (0xb0005000)
358#define BCM_6368_XTMDMAC_BASE (0xb0005200)
359#define BCM_6368_XTMDMAS_BASE (0xb0005400)
360#define BCM_6368_PCM_BASE (0xb0004000)
361#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
233 364
234 365
235extern const unsigned long *bcm63xx_regs_base; 366extern const unsigned long *bcm63xx_regs_base;
236 367
368#define __GEN_RSET_BASE(__cpu, __rset) \
369 case RSET_## __rset : \
370 return BCM_## __cpu ##_## __rset ##_BASE;
371
372#define __GEN_RSET(__cpu) \
373 switch (set) { \
374 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
375 __GEN_RSET_BASE(__cpu, PERF) \
376 __GEN_RSET_BASE(__cpu, TIMER) \
377 __GEN_RSET_BASE(__cpu, WDT) \
378 __GEN_RSET_BASE(__cpu, UART0) \
379 __GEN_RSET_BASE(__cpu, UART1) \
380 __GEN_RSET_BASE(__cpu, GPIO) \
381 __GEN_RSET_BASE(__cpu, SPI) \
382 __GEN_RSET_BASE(__cpu, SPI2) \
383 __GEN_RSET_BASE(__cpu, UDC0) \
384 __GEN_RSET_BASE(__cpu, OHCI0) \
385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
387 __GEN_RSET_BASE(__cpu, MPI) \
388 __GEN_RSET_BASE(__cpu, PCMCIA) \
389 __GEN_RSET_BASE(__cpu, DSL) \
390 __GEN_RSET_BASE(__cpu, ENET0) \
391 __GEN_RSET_BASE(__cpu, ENET1) \
392 __GEN_RSET_BASE(__cpu, ENETDMA) \
393 __GEN_RSET_BASE(__cpu, ENETDMAC) \
394 __GEN_RSET_BASE(__cpu, ENETDMAS) \
395 __GEN_RSET_BASE(__cpu, ENETSW) \
396 __GEN_RSET_BASE(__cpu, EHCI0) \
397 __GEN_RSET_BASE(__cpu, SDRAM) \
398 __GEN_RSET_BASE(__cpu, MEMC) \
399 __GEN_RSET_BASE(__cpu, DDR) \
400 __GEN_RSET_BASE(__cpu, M2M) \
401 __GEN_RSET_BASE(__cpu, ATM) \
402 __GEN_RSET_BASE(__cpu, XTM) \
403 __GEN_RSET_BASE(__cpu, XTMDMA) \
404 __GEN_RSET_BASE(__cpu, XTMDMAC) \
405 __GEN_RSET_BASE(__cpu, XTMDMAS) \
406 __GEN_RSET_BASE(__cpu, PCM) \
407 __GEN_RSET_BASE(__cpu, PCMDMA) \
408 __GEN_RSET_BASE(__cpu, PCMDMAC) \
409 __GEN_RSET_BASE(__cpu, PCMDMAS) \
410 }
411
412#define __GEN_CPU_REGS_TABLE(__cpu) \
413 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
414 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
415 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
416 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
417 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
431 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
432 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
433 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
434 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
435 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
436 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
437 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
438 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
439 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
440 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
441 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
442 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
443 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
444 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
445 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
449
450
237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 451static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
238{ 452{
239#ifdef BCMCPU_RUNTIME_DETECT 453#ifdef BCMCPU_RUNTIME_DETECT
240 return bcm63xx_regs_base[set]; 454 return bcm63xx_regs_base[set];
241#else 455#else
242#ifdef CONFIG_BCM63XX_CPU_6338 456#ifdef CONFIG_BCM63XX_CPU_6338
243 switch (set) { 457 __GEN_RSET(6338)
244 case RSET_DSL_LMEM:
245 return BCM_6338_DSL_LMEM_BASE;
246 case RSET_PERF:
247 return BCM_6338_PERF_BASE;
248 case RSET_TIMER:
249 return BCM_6338_TIMER_BASE;
250 case RSET_WDT:
251 return BCM_6338_WDT_BASE;
252 case RSET_UART0:
253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
256 case RSET_GPIO:
257 return BCM_6338_GPIO_BASE;
258 case RSET_SPI:
259 return BCM_6338_SPI_BASE;
260 case RSET_UDC0:
261 return BCM_6338_UDC0_BASE;
262 case RSET_OHCI0:
263 return BCM_6338_OHCI0_BASE;
264 case RSET_OHCI_PRIV:
265 return BCM_6338_OHCI_PRIV_BASE;
266 case RSET_USBH_PRIV:
267 return BCM_6338_USBH_PRIV_BASE;
268 case RSET_MPI:
269 return BCM_6338_MPI_BASE;
270 case RSET_PCMCIA:
271 return BCM_6338_PCMCIA_BASE;
272 case RSET_DSL:
273 return BCM_6338_DSL_BASE;
274 case RSET_ENET0:
275 return BCM_6338_ENET0_BASE;
276 case RSET_ENET1:
277 return BCM_6338_ENET1_BASE;
278 case RSET_ENETDMA:
279 return BCM_6338_ENETDMA_BASE;
280 case RSET_EHCI0:
281 return BCM_6338_EHCI0_BASE;
282 case RSET_SDRAM:
283 return BCM_6338_SDRAM_BASE;
284 case RSET_MEMC:
285 return BCM_6338_MEMC_BASE;
286 case RSET_DDR:
287 return BCM_6338_DDR_BASE;
288 }
289#endif 458#endif
290#ifdef CONFIG_BCM63XX_CPU_6345 459#ifdef CONFIG_BCM63XX_CPU_6345
291 switch (set) { 460 __GEN_RSET(6345)
292 case RSET_DSL_LMEM:
293 return BCM_6345_DSL_LMEM_BASE;
294 case RSET_PERF:
295 return BCM_6345_PERF_BASE;
296 case RSET_TIMER:
297 return BCM_6345_TIMER_BASE;
298 case RSET_WDT:
299 return BCM_6345_WDT_BASE;
300 case RSET_UART0:
301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
304 case RSET_GPIO:
305 return BCM_6345_GPIO_BASE;
306 case RSET_SPI:
307 return BCM_6345_SPI_BASE;
308 case RSET_UDC0:
309 return BCM_6345_UDC0_BASE;
310 case RSET_OHCI0:
311 return BCM_6345_OHCI0_BASE;
312 case RSET_OHCI_PRIV:
313 return BCM_6345_OHCI_PRIV_BASE;
314 case RSET_USBH_PRIV:
315 return BCM_6345_USBH_PRIV_BASE;
316 case RSET_MPI:
317 return BCM_6345_MPI_BASE;
318 case RSET_PCMCIA:
319 return BCM_6345_PCMCIA_BASE;
320 case RSET_DSL:
321 return BCM_6345_DSL_BASE;
322 case RSET_ENET0:
323 return BCM_6345_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6345_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6345_ENETDMA_BASE;
328 case RSET_EHCI0:
329 return BCM_6345_EHCI0_BASE;
330 case RSET_SDRAM:
331 return BCM_6345_SDRAM_BASE;
332 case RSET_MEMC:
333 return BCM_6345_MEMC_BASE;
334 case RSET_DDR:
335 return BCM_6345_DDR_BASE;
336 }
337#endif 461#endif
338#ifdef CONFIG_BCM63XX_CPU_6348 462#ifdef CONFIG_BCM63XX_CPU_6348
339 switch (set) { 463 __GEN_RSET(6348)
340 case RSET_DSL_LMEM:
341 return BCM_6348_DSL_LMEM_BASE;
342 case RSET_PERF:
343 return BCM_6348_PERF_BASE;
344 case RSET_TIMER:
345 return BCM_6348_TIMER_BASE;
346 case RSET_WDT:
347 return BCM_6348_WDT_BASE;
348 case RSET_UART0:
349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
352 case RSET_GPIO:
353 return BCM_6348_GPIO_BASE;
354 case RSET_SPI:
355 return BCM_6348_SPI_BASE;
356 case RSET_UDC0:
357 return BCM_6348_UDC0_BASE;
358 case RSET_OHCI0:
359 return BCM_6348_OHCI0_BASE;
360 case RSET_OHCI_PRIV:
361 return BCM_6348_OHCI_PRIV_BASE;
362 case RSET_USBH_PRIV:
363 return BCM_6348_USBH_PRIV_BASE;
364 case RSET_MPI:
365 return BCM_6348_MPI_BASE;
366 case RSET_PCMCIA:
367 return BCM_6348_PCMCIA_BASE;
368 case RSET_DSL:
369 return BCM_6348_DSL_BASE;
370 case RSET_ENET0:
371 return BCM_6348_ENET0_BASE;
372 case RSET_ENET1:
373 return BCM_6348_ENET1_BASE;
374 case RSET_ENETDMA:
375 return BCM_6348_ENETDMA_BASE;
376 case RSET_EHCI0:
377 return BCM_6348_EHCI0_BASE;
378 case RSET_SDRAM:
379 return BCM_6348_SDRAM_BASE;
380 case RSET_MEMC:
381 return BCM_6348_MEMC_BASE;
382 case RSET_DDR:
383 return BCM_6348_DDR_BASE;
384 }
385#endif 464#endif
386#ifdef CONFIG_BCM63XX_CPU_6358 465#ifdef CONFIG_BCM63XX_CPU_6358
387 switch (set) { 466 __GEN_RSET(6358)
388 case RSET_DSL_LMEM: 467#endif
389 return BCM_6358_DSL_LMEM_BASE; 468#ifdef CONFIG_BCM63XX_CPU_6368
390 case RSET_PERF: 469 __GEN_RSET(6368)
391 return BCM_6358_PERF_BASE;
392 case RSET_TIMER:
393 return BCM_6358_TIMER_BASE;
394 case RSET_WDT:
395 return BCM_6358_WDT_BASE;
396 case RSET_UART0:
397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
400 case RSET_GPIO:
401 return BCM_6358_GPIO_BASE;
402 case RSET_SPI:
403 return BCM_6358_SPI_BASE;
404 case RSET_UDC0:
405 return BCM_6358_UDC0_BASE;
406 case RSET_OHCI0:
407 return BCM_6358_OHCI0_BASE;
408 case RSET_OHCI_PRIV:
409 return BCM_6358_OHCI_PRIV_BASE;
410 case RSET_USBH_PRIV:
411 return BCM_6358_USBH_PRIV_BASE;
412 case RSET_MPI:
413 return BCM_6358_MPI_BASE;
414 case RSET_PCMCIA:
415 return BCM_6358_PCMCIA_BASE;
416 case RSET_ENET0:
417 return BCM_6358_ENET0_BASE;
418 case RSET_ENET1:
419 return BCM_6358_ENET1_BASE;
420 case RSET_ENETDMA:
421 return BCM_6358_ENETDMA_BASE;
422 case RSET_DSL:
423 return BCM_6358_DSL_BASE;
424 case RSET_EHCI0:
425 return BCM_6358_EHCI0_BASE;
426 case RSET_SDRAM:
427 return BCM_6358_SDRAM_BASE;
428 case RSET_MEMC:
429 return BCM_6358_MEMC_BASE;
430 case RSET_DDR:
431 return BCM_6358_DDR_BASE;
432 }
433#endif 470#endif
434#endif 471#endif
435 /* unreached */ 472 /* unreached */
@@ -449,75 +486,114 @@ enum bcm63xx_irq {
449 IRQ_ENET_PHY, 486 IRQ_ENET_PHY,
450 IRQ_OHCI0, 487 IRQ_OHCI0,
451 IRQ_EHCI0, 488 IRQ_EHCI0,
452 IRQ_PCMCIA0,
453 IRQ_ENET0_RXDMA, 489 IRQ_ENET0_RXDMA,
454 IRQ_ENET0_TXDMA, 490 IRQ_ENET0_TXDMA,
455 IRQ_ENET1_RXDMA, 491 IRQ_ENET1_RXDMA,
456 IRQ_ENET1_TXDMA, 492 IRQ_ENET1_TXDMA,
457 IRQ_PCI, 493 IRQ_PCI,
458 IRQ_PCMCIA, 494 IRQ_PCMCIA,
495 IRQ_ATM,
496 IRQ_ENETSW_RXDMA0,
497 IRQ_ENETSW_RXDMA1,
498 IRQ_ENETSW_RXDMA2,
499 IRQ_ENETSW_RXDMA3,
500 IRQ_ENETSW_TXDMA0,
501 IRQ_ENETSW_TXDMA1,
502 IRQ_ENETSW_TXDMA2,
503 IRQ_ENETSW_TXDMA3,
504 IRQ_XTM,
505 IRQ_XTM_DMA0,
459}; 506};
460 507
461/* 508/*
462 * 6338 irqs 509 * 6338 irqs
463 */ 510 */
464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 511#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 512#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 513#define BCM_6338_UART1_IRQ 0
468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 514#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 515#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6338_ENET1_IRQ 0
472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 517#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 518#define BCM_6338_OHCI0_IRQ 0
474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 519#define BCM_6338_EHCI0_IRQ 0
475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 520#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 521#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 522#define BCM_6338_ENET1_RXDMA_IRQ 0
523#define BCM_6338_ENET1_TXDMA_IRQ 0
524#define BCM_6338_PCI_IRQ 0
525#define BCM_6338_PCMCIA_IRQ 0
526#define BCM_6338_ATM_IRQ 0
527#define BCM_6338_ENETSW_RXDMA0_IRQ 0
528#define BCM_6338_ENETSW_RXDMA1_IRQ 0
529#define BCM_6338_ENETSW_RXDMA2_IRQ 0
530#define BCM_6338_ENETSW_RXDMA3_IRQ 0
531#define BCM_6338_ENETSW_TXDMA0_IRQ 0
532#define BCM_6338_ENETSW_TXDMA1_IRQ 0
533#define BCM_6338_ENETSW_TXDMA2_IRQ 0
534#define BCM_6338_ENETSW_TXDMA3_IRQ 0
535#define BCM_6338_XTM_IRQ 0
536#define BCM_6338_XTM_DMA0_IRQ 0
481 537
482/* 538/*
483 * 6345 irqs 539 * 6345 irqs
484 */ 540 */
485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 541#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 542#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
543#define BCM_6345_UART1_IRQ 0
487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 544#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 545#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
546#define BCM_6345_ENET1_IRQ 0
491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 547#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
548#define BCM_6345_OHCI0_IRQ 0
549#define BCM_6345_EHCI0_IRQ 0
492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 550#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 551#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 552#define BCM_6345_ENET1_RXDMA_IRQ 0
495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 553#define BCM_6345_ENET1_TXDMA_IRQ 0
496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 554#define BCM_6345_PCI_IRQ 0
497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 555#define BCM_6345_PCMCIA_IRQ 0
498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) 556#define BCM_6345_ATM_IRQ 0
499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) 557#define BCM_6345_ENETSW_RXDMA0_IRQ 0
500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) 558#define BCM_6345_ENETSW_RXDMA1_IRQ 0
501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) 559#define BCM_6345_ENETSW_RXDMA2_IRQ 0
502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) 560#define BCM_6345_ENETSW_RXDMA3_IRQ 0
503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) 561#define BCM_6345_ENETSW_TXDMA0_IRQ 0
562#define BCM_6345_ENETSW_TXDMA1_IRQ 0
563#define BCM_6345_ENETSW_TXDMA2_IRQ 0
564#define BCM_6345_ENETSW_TXDMA3_IRQ 0
565#define BCM_6345_XTM_IRQ 0
566#define BCM_6345_XTM_DMA0_IRQ 0
504 567
505/* 568/*
506 * 6348 irqs 569 * 6348 irqs
507 */ 570 */
508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 571#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 572#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
573#define BCM_6348_UART1_IRQ 0
510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 574#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 575#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
576#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 577#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 578#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
579#define BCM_6348_EHCI0_IRQ 0
515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 580#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 581#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 582#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 583#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 584#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
585#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
586#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
587#define BCM_6348_ENETSW_RXDMA0_IRQ 0
588#define BCM_6348_ENETSW_RXDMA1_IRQ 0
589#define BCM_6348_ENETSW_RXDMA2_IRQ 0
590#define BCM_6348_ENETSW_RXDMA3_IRQ 0
591#define BCM_6348_ENETSW_TXDMA0_IRQ 0
592#define BCM_6348_ENETSW_TXDMA1_IRQ 0
593#define BCM_6348_ENETSW_TXDMA2_IRQ 0
594#define BCM_6348_ENETSW_TXDMA3_IRQ 0
595#define BCM_6348_XTM_IRQ 0
596#define BCM_6348_XTM_DMA0_IRQ 0
521 597
522/* 598/*
523 * 6358 irqs 599 * 6358 irqs
@@ -525,21 +601,108 @@ enum bcm63xx_irq {
525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 601#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 602#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 603#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 604#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 605#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
606#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 607#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
608#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 609#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 610#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 611#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 612#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 613#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 614#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 615#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
616#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
617#define BCM_6358_ENETSW_RXDMA0_IRQ 0
618#define BCM_6358_ENETSW_RXDMA1_IRQ 0
619#define BCM_6358_ENETSW_RXDMA2_IRQ 0
620#define BCM_6358_ENETSW_RXDMA3_IRQ 0
621#define BCM_6358_ENETSW_TXDMA0_IRQ 0
622#define BCM_6358_ENETSW_TXDMA1_IRQ 0
623#define BCM_6358_ENETSW_TXDMA2_IRQ 0
624#define BCM_6358_ENETSW_TXDMA3_IRQ 0
625#define BCM_6358_XTM_IRQ 0
626#define BCM_6358_XTM_DMA0_IRQ 0
627
628#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
629#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
630#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
631#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
632#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
633#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
634
635/*
636 * 6368 irqs
637 */
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
644#define BCM_6368_ENET0_IRQ 0
645#define BCM_6368_ENET1_IRQ 0
646#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
647#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
648#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
649#define BCM_6368_PCMCIA_IRQ 0
650#define BCM_6368_ENET0_RXDMA_IRQ 0
651#define BCM_6368_ENET0_TXDMA_IRQ 0
652#define BCM_6368_ENET1_RXDMA_IRQ 0
653#define BCM_6368_ENET1_TXDMA_IRQ 0
654#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
655#define BCM_6368_ATM_IRQ 0
656#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
657#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
658#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
659#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
660#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
661#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
662#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
663#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
664#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
665#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
666
667#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
668#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
669#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
670#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
671#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
672#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
673#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
674#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
540 675
541extern const int *bcm63xx_irqs; 676extern const int *bcm63xx_irqs;
542 677
678#define __GEN_CPU_IRQ_TABLE(__cpu) \
679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
683 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
684 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
685 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
686 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
687 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
688 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
689 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
690 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
691 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
692 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
693 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
694 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
695 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
696 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
697 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
698 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
699 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
700 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
701 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
702 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
703 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
704 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
705
543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 706static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
544{ 707{
545 return bcm63xx_irqs[irq]; 708 return bcm63xx_irqs[irq];
@@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
550 */ 713 */
551unsigned int bcm63xx_get_memory_size(void); 714unsigned int bcm63xx_get_memory_size(void);
552 715
716void bcm63xx_machine_halt(void);
717
718void bcm63xx_machine_reboot(void);
719
553#endif /* !BCM63XX_CPU_H_ */ 720#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f..3d5de96d403 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
14 return 8; 14 return 8;
15 case BCM6345_CPU_ID: 15 case BCM6345_CPU_ID:
16 return 16; 16 return 16;
17 case BCM6368_CPU_ID:
18 return 38;
17 case BCM6348_CPU_ID: 19 case BCM6348_CPU_ID:
18 default: 20 default:
19 return 37; 21 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 91180fac6ed..72477a6441d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,9 +49,11 @@
49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) 49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) 50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) 51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
52#define bcm_readq(a) (*(volatile u64 *) BCM_REGS_VA(a))
52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) 53#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) 54#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) 55#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
56#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
55 57
56/* 58/*
57 * IO helpers to access register set for current CPU 59 * IO helpers to access register set for current CPU
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 5f95577c821..0c3074b871b 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,13 +3,11 @@
3 3
4#include <bcm63xx_cpu.h> 4#include <bcm63xx_cpu.h>
5 5
6#define IRQ_MIPS_BASE 0
7#define IRQ_INTERNAL_BASE 8 6#define IRQ_INTERNAL_BASE 8
8 7#define IRQ_EXTERNAL_BASE 100
9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3) 8#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0)
10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0) 9#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1)
11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1) 10#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2)
12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2) 11#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
14 12
15#endif /* ! BCM63XX_IRQ_H_ */ 13#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0ed5230243c..94d4faad29a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,30 +83,86 @@
83 CKCTL_6358_USBSU_EN | \ 83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN) 84 CKCTL_6358_EPHY_EN)
85 85
86#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
87#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
88#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
89#define CKCTL_6368_VDSL_EN (1 << 5)
90#define CKCTL_6368_PHYMIPS_EN (1 << 6)
91#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
92#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
93#define CKCTL_6368_SPI_CLK_EN (1 << 9)
94#define CKCTL_6368_USBD_CLK_EN (1 << 10)
95#define CKCTL_6368_SAR_CLK_EN (1 << 11)
96#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
97#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
98#define CKCTL_6368_PCM_CLK_EN (1 << 14)
99#define CKCTL_6368_USBH_CLK_EN (1 << 15)
100#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
101#define CKCTL_6368_NAND_CLK_EN (1 << 17)
102#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
103
104#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
105 CKCTL_6368_SWPKT_SAR_EN | \
106 CKCTL_6368_SPI_CLK_EN | \
107 CKCTL_6368_USBD_CLK_EN | \
108 CKCTL_6368_SAR_CLK_EN | \
109 CKCTL_6368_ROBOSW_CLK_EN | \
110 CKCTL_6368_UTOPIA_CLK_EN | \
111 CKCTL_6368_PCM_CLK_EN | \
112 CKCTL_6368_USBH_CLK_EN | \
113 CKCTL_6368_DISABLE_GLESS_EN | \
114 CKCTL_6368_NAND_CLK_EN | \
115 CKCTL_6368_IPSEC_CLK_EN)
116
86/* System PLL Control register */ 117/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8 118#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1 119#define SYS_PLL_SOFT_RESET 0x1
89 120
90/* Interrupt Mask register */ 121/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc 122#define PERF_IRQMASK_6338_REG 0xc
123#define PERF_IRQMASK_6345_REG 0xc
124#define PERF_IRQMASK_6348_REG 0xc
125#define PERF_IRQMASK_6358_REG 0xc
126#define PERF_IRQMASK_6368_REG 0x20
92 127
93/* Interrupt Status register */ 128/* Interrupt Status register */
94#define PERF_IRQSTAT_REG 0x10 129#define PERF_IRQSTAT_6338_REG 0x10
130#define PERF_IRQSTAT_6345_REG 0x10
131#define PERF_IRQSTAT_6348_REG 0x10
132#define PERF_IRQSTAT_6358_REG 0x10
133#define PERF_IRQSTAT_6368_REG 0x28
95 134
96/* External Interrupt Configuration register */ 135/* External Interrupt Configuration register */
97#define PERF_EXTIRQ_CFG_REG 0x14 136#define PERF_EXTIRQ_CFG_REG_6338 0x14
137#define PERF_EXTIRQ_CFG_REG_6348 0x14
138#define PERF_EXTIRQ_CFG_REG_6358 0x14
139#define PERF_EXTIRQ_CFG_REG_6368 0x18
140
141#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
142
143/* for 6348 only */
144#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
145#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
146#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
147#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
148#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
149#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
150#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
151#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
152
153/* for all others */
98#define EXTIRQ_CFG_SENSE(x) (1 << (x)) 154#define EXTIRQ_CFG_SENSE(x) (1 << (x))
99#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) 155#define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
100#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) 156#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
101#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) 157#define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
102#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) 158#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
103#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) 159#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
104 160#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
105#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) 161#define EXTIRQ_CFG_MASK_ALL (0xf << 12)
106#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
107 162
108/* Soft Reset register */ 163/* Soft Reset register */
109#define PERF_SOFTRESET_REG 0x28 164#define PERF_SOFTRESET_REG 0x28
165#define PERF_SOFTRESET_6368_REG 0x10
110 166
111#define SOFTRESET_6338_SPI_MASK (1 << 0) 167#define SOFTRESET_6338_SPI_MASK (1 << 0)
112#define SOFTRESET_6338_ENET_MASK (1 << 2) 168#define SOFTRESET_6338_ENET_MASK (1 << 2)
@@ -147,6 +203,15 @@
147 SOFTRESET_6348_ACLC_MASK | \ 203 SOFTRESET_6348_ACLC_MASK | \
148 SOFTRESET_6348_ADSLMIPSPLL_MASK) 204 SOFTRESET_6348_ADSLMIPSPLL_MASK)
149 205
206#define SOFTRESET_6368_SPI_MASK (1 << 0)
207#define SOFTRESET_6368_MPI_MASK (1 << 3)
208#define SOFTRESET_6368_EPHY_MASK (1 << 6)
209#define SOFTRESET_6368_SAR_MASK (1 << 7)
210#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
211#define SOFTRESET_6368_USBS_MASK (1 << 11)
212#define SOFTRESET_6368_USBH_MASK (1 << 12)
213#define SOFTRESET_6368_PCM_MASK (1 << 13)
214
150/* MIPS PLL control register */ 215/* MIPS PLL control register */
151#define PERF_MIPSPLLCTL_REG 0x34 216#define PERF_MIPSPLLCTL_REG 0x34
152#define MIPSPLLCTL_N1_SHIFT 20 217#define MIPSPLLCTL_N1_SHIFT 20
@@ -372,6 +437,7 @@
372#define GPIO_CTL_LO_REG 0x4 437#define GPIO_CTL_LO_REG 0x4
373#define GPIO_DATA_HI_REG 0x8 438#define GPIO_DATA_HI_REG 0x8
374#define GPIO_DATA_LO_REG 0xC 439#define GPIO_DATA_LO_REG 0xC
440#define GPIO_DATA_LO_REG_6345 0x8
375 441
376/* GPIO mux registers and constants */ 442/* GPIO mux registers and constants */
377#define GPIO_MODE_REG 0x18 443#define GPIO_MODE_REG 0x18
@@ -402,6 +468,44 @@
402#define GPIO_MODE_6358_SERIAL_LED (1 << 10) 468#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
403#define GPIO_MODE_6358_UTOPIA (1 << 12) 469#define GPIO_MODE_6358_UTOPIA (1 << 12)
404 470
471#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
472#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
473#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
474#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
475#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
476#define GPIO_MODE_6368_INET_LED (1 << 5)
477#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
478#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
479#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
480#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
481#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
482#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
483#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
484#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
485#define GPIO_MODE_6368_USBD_LED (1 << 14)
486#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
487#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
488#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
489#define GPIO_MODE_6368_PCI_INTB (1 << 18)
490#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
491#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
492#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
493#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
494#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
495#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
496#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
497#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
498#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
499#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
500#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
501#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
502
503
504#define GPIO_BASEMODE_6368_REG 0x38
505#define GPIO_BASEMODE_6368_UART2 0x1
506#define GPIO_BASEMODE_6368_GPIO 0x0
507#define GPIO_BASEMODE_6368_MASK 0x7
508/* those bits must be kept as read in gpio basemode register*/
405 509
406/************************************************************************* 510/*************************************************************************
407 * _REG relative to RSET_ENET 511 * _REG relative to RSET_ENET
@@ -548,6 +652,56 @@
548 652
549 653
550/************************************************************************* 654/*************************************************************************
655 * _REG relative to RSET_ENETDMAC
656 *************************************************************************/
657
658/* Channel Configuration register */
659#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
660#define ENETDMAC_CHANCFG_EN_SHIFT 0
661#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
662#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
663#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
664
665/* Interrupt Control/Status register */
666#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
667#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
668#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
669#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
670
671/* Interrupt Mask register */
672#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
673
674/* Maximum Burst Length */
675#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
676
677
678/*************************************************************************
679 * _REG relative to RSET_ENETDMAS
680 *************************************************************************/
681
682/* Ring Start Address register */
683#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
684
685/* State Ram Word 2 */
686#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
687
688/* State Ram Word 3 */
689#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
690
691/* State Ram Word 4 */
692#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
693
694
695/*************************************************************************
696 * _REG relative to RSET_ENETSW
697 *************************************************************************/
698
699/* MIB register */
700#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
701#define ENETSW_MIB_REG_COUNT 47
702
703
704/*************************************************************************
551 * _REG relative to RSET_OHCI_PRIV 705 * _REG relative to RSET_OHCI_PRIV
552 *************************************************************************/ 706 *************************************************************************/
553 707
@@ -562,7 +716,9 @@
562 * _REG relative to RSET_USBH_PRIV 716 * _REG relative to RSET_USBH_PRIV
563 *************************************************************************/ 717 *************************************************************************/
564 718
565#define USBH_PRIV_SWAP_REG 0x0 719#define USBH_PRIV_SWAP_6358_REG 0x0
720#define USBH_PRIV_SWAP_6368_REG 0x1c
721
566#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 722#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
567#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 723#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
568#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 724#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
@@ -572,7 +728,13 @@
572#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 728#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
573#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 729#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
574 730
575#define USBH_PRIV_TEST_REG 0x24 731#define USBH_PRIV_TEST_6358_REG 0x24
732#define USBH_PRIV_TEST_6368_REG 0x14
733
734#define USBH_PRIV_SETUP_6368_REG 0x28
735#define USBH_PRIV_SETUP_IOC_SHIFT 4
736#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
737
576 738
577 739
578/************************************************************************* 740/*************************************************************************
@@ -734,6 +896,8 @@
734#define SDRAM_CFG_BANK_SHIFT 13 896#define SDRAM_CFG_BANK_SHIFT 13
735#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 897#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
736 898
899#define SDRAM_MBASE_REG 0xc
900
737#define SDRAM_PRIO_REG 0x2C 901#define SDRAM_PRIO_REG 0x2C
738#define SDRAM_PRIO_MIPS_SHIFT 29 902#define SDRAM_PRIO_MIPS_SHIFT 29
739#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 903#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -768,4 +932,45 @@
768#define DMIPSPLLCFG_N2_SHIFT 29 932#define DMIPSPLLCFG_N2_SHIFT 29
769#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 933#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
770 934
935#define DDR_DMIPSPLLCFG_6368_REG 0x20
936#define DMIPSPLLCFG_6368_P1_SHIFT 0
937#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
938#define DMIPSPLLCFG_6368_P2_SHIFT 4
939#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
940#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
941#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
942
943#define DDR_DMIPSPLLDIV_6368_REG 0x24
944#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
945#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
946
947
948/*************************************************************************
949 * _REG relative to RSET_M2M
950 *************************************************************************/
951
952#define M2M_RX 0
953#define M2M_TX 1
954
955#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
956#define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
957#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
958
959#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
960#define M2M_CTRL_ENABLE_MASK (1 << 0)
961#define M2M_CTRL_IRQEN_MASK (1 << 1)
962#define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
963#define M2M_CTRL_DONE_CLR_MASK (1 << 7)
964#define M2M_CTRL_NOINC_MASK (1 << 8)
965#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
966#define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
967#define M2M_CTRL_ENDIAN_MASK (1 << 11)
968
969#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
970#define M2M_STAT_DONE (1 << 0)
971#define M2M_STAT_ERROR (1 << 1)
972
973#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
974#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
975
771#endif /* BCM63XX_REGS_H_ */ 976#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 00000000000..ef94ba73646
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,42 @@
1#ifndef BCM63XX_IOREMAP_H_
2#define BCM63XX_IOREMAP_H_
3
4#include <bcm63xx_cpu.h>
5
6static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
7{
8 return phys_addr;
9}
10
11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{
13 switch (bcm63xx_get_cpu_id()) {
14 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID:
17 case BCM6358_CPU_ID:
18 if (offset >= 0xfff00000)
19 return 1;
20 break;
21 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1;
24 break;
25 }
26 return 0;
27}
28
29static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
30 unsigned long flags)
31{
32 if (is_bcm63xx_internal_registers(offset))
33 return (void __iomem *)offset;
34 return NULL;
35}
36
37static inline int plat_iounmap(const volatile void __iomem *addr)
38{
39 return is_bcm63xx_internal_registers((unsigned long)addr);
40}
41
42#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
new file mode 100644
index 00000000000..9332e788a5c
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_BCM63XX_IRQ_H
2#define __ASM_MACH_BCM63XX_IRQ_H
3
4#define NR_IRQS 128
5#define MIPS_CPU_IRQ_BASE 0
6
7#endif
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 618d2de02ed..bb9fc23d853 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,6 +34,8 @@
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000 34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000 35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36 36
37#define DB1300_BCSR_PHYS_ADDR 0x19800000
38#define DB1300_BCSR_HEXLED_OFS 0x00400000
37 39
38enum bcsr_id { 40enum bcsr_id {
39 /* BCSR base 1 */ 41 /* BCSR base 1 */
@@ -105,6 +107,7 @@ enum bcsr_whoami_boards {
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 107 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2, 108 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200, 109 BCSR_WHOAMI_DB1200,
110 BCSR_WHOAMI_DB1300,
108}; 111};
109 112
110/* STATUS reg. Unless otherwise noted, they're valid on all boards. 113/* STATUS reg. Unless otherwise noted, they're valid on all boards.
@@ -118,12 +121,12 @@ enum bcsr_whoami_boards {
118#define BCSR_STATUS_SRAMWIDTH 0x0080 121#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100 122#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400 123#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ 124#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */
122#define BCSR_STATUS_SD1WP 0x0800 125#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 126#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 127#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ 128#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ 129#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 130#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 131#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000 132#define BCSR_STATUS_FLASHDEN 0xC000
@@ -133,6 +136,11 @@ enum bcsr_whoami_boards {
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 136#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 137#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135 138
139#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */
140#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */
141#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */
142#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */
143#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */
136 144
137/* DB/PB1000,1100,1500,1550 */ 145/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001 146#define BCSR_RESETS_PHY0 0x0001
@@ -155,17 +163,17 @@ enum bcsr_whoami_boards {
155#define BCSR_BOARD_GPIO200RST 0x0400 163#define BCSR_BOARD_GPIO200RST 0x0400
156#define BCSR_BOARD_PCICLKOUT 0x0800 164#define BCSR_BOARD_PCICLKOUT 0x0800
157#define BCSR_BOARD_PCICFG 0x1000 165#define BCSR_BOARD_PCICFG 0x1000
158#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ 166#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */
159#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 167#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 168#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161 169
162 170
163/* DB/PB1200 */ 171/* DB/PB1200/1300 */
164#define BCSR_RESETS_ETH 0x0001 172#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002 173#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004 174#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008 175#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */ 176#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */
169/* Not resets but in the same register */ 177/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 178#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 179#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
@@ -174,13 +182,22 @@ enum bcsr_whoami_boards {
174#define BCSR_RESETS_SPISEL 0x4000 182#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 183#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176 184
185#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */
186#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */
187#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */
188#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */
189#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */
190#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */
191#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */
192
177#define BCSR_BOARD_LCDVEE 0x0001 193#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002 194#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004 195#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010 196#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020 197#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040 198#define BCSR_BOARD_SD0PWR 0x0040
183 199#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */
200#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */
184 201
185#define BCSR_SWITCHES_DIP 0x00FF 202#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080 203#define BCSR_SWITCHES_DIP_1 0x0080
@@ -214,7 +231,10 @@ enum bcsr_whoami_boards {
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 231#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 232#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 233#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217 234#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */
235#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */
236#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */
237#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */
218 238
219 239
220 240
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c..b2a8319521e 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
43#define BCSR_INT_PC1EJECT 0x0800 43#define BCSR_INT_PC1EJECT 0x0800
44#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
45#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
46#define BCSR_INT_SD1INSERT 0x4000
47#define BCSR_INT_SD1EJECT 0x8000
46 48
47#define IDE_PHYS_ADDR 0x18800000
48#define IDE_REG_SHIFT 5 49#define IDE_REG_SHIFT 5
49 50
50#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR 51#define DB1200_IDE_PHYS_ADDR 0x18800000
51#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) 52#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
52#define DB1200_ETH_PHYS_ADDR 0x19000300 53#define DB1200_ETH_PHYS_ADDR 0x19000300
53#define DB1200_NAND_PHYS_ADDR 0x20000000 54#define DB1200_NAND_PHYS_ADDR 0x20000000
54 55
56#define PB1200_IDE_PHYS_ADDR 0x0C800000
57#define PB1200_ETH_PHYS_ADDR 0x0D000300
58#define PB1200_NAND_PHYS_ADDR 0x1C000000
59
55/* 60/*
56 * External Interrupts for DBAu1200 as of 8/6/2004. 61 * External Interrupts for DBAu1200 as of 8/6/2004.
57 * Bit positions in the CPLD registers can be calculated by taking 62 * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
77 DB1200_PC1_EJECT_INT, 82 DB1200_PC1_EJECT_INT,
78 DB1200_SD0_INSERT_INT, 83 DB1200_SD0_INSERT_INT,
79 DB1200_SD0_EJECT_INT, 84 DB1200_SD0_EJECT_INT,
85 PB1200_SD1_INSERT_INT,
86 PB1200_SD1_EJECT_INT,
80 87
81 DB1200_INT_END = DB1200_INT_BEGIN + 15, 88 DB1200_INT_END = DB1200_INT_BEGIN + 15,
82}; 89};
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
new file mode 100644
index 00000000000..7fe5fb3ba87
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -0,0 +1,40 @@
1/*
2 * NetLogic DB1300 board constants
3 */
4
5#ifndef _DB1300_H_
6#define _DB1300_H_
7
8/* FPGA (external mux) interrupt sources */
9#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
10#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
11#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
12#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
13#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
14#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
15#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
16#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
17#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
18#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
19#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
20#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
21#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
22#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
23#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
24#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
25#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
26
27/* SMSC9210 CS */
28#define DB1300_ETH_PHYS_ADDR 0x19000000
29#define DB1300_ETH_PHYS_END 0x197fffff
30
31/* ATA CS */
32#define DB1300_IDE_PHYS_ADDR 0x18800000
33#define DB1300_IDE_REG_SHIFT 5
34#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
35
36/* NAND CS */
37#define DB1300_NAND_PHYS_ADDR 0x20000000
38#define DB1300_NAND_PHYS_END 0x20000fff
39
40#endif /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index a5affb0568e..00000000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
40#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
42#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
43
44#define NAND_PHYS_ADDR 0x20000000
45
46#endif
47
48/*
49 * NAND defines
50 *
51 * Timing values as described in databook, * ns value stripped of the
52 * lower 2 bits.
53 * These defines are here rather than an Au1550 generic file because
54 * the parts chosen on another board may be different and may require
55 * different timings.
56 */
57#define NAND_T_H (18 >> 2)
58#define NAND_T_PUL (30 >> 2)
59#define NAND_T_SU (30 >> 2)
60#define NAND_T_WH (30 >> 2)
61
62/* Bitfield shift amounts */
63#define NAND_T_H_SHIFT 0
64#define NAND_T_PUL_SHIFT 4
65#define NAND_T_SU_SHIFT 8
66#define NAND_T_WH_SHIFT 12
67
68#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
69 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
70 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
71 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
72#define NAND_CS 1
73
74/* Should be done by YAMON */
75#define NAND_STCFG 0x00400005 /* 8-bit NAND */
76#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
77#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
78
79#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 00000000000..15b26693238
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_IRQ_H
9#define __ASM_MACH_GENERIC_IRQ_H
10
11
12#ifdef NR_IRQS
13#undef NR_IRQS
14#endif
15
16#ifndef MIPS_CPU_IRQ_BASE
17#define MIPS_CPU_IRQ_BASE 0
18#endif
19
20/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
21#define NR_IRQS 152
22
23#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 001a8ce17c1..a38f4d43e5e 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -98,7 +98,7 @@ static inline void fd_disable_irq(void)
98static inline int fd_request_irq(void) 98static inline int fd_request_irq(void)
99{ 99{
100 return request_irq(FLOPPY_IRQ, floppy_interrupt, 100 return request_irq(FLOPPY_IRQ, floppy_interrupt,
101 IRQF_DISABLED, "floppy", NULL); 101 0, "floppy", NULL);
102} 102}
103 103
104static inline void fd_free_irq(void) 104static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 56e9ca6ae42..88b5acb7514 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -90,7 +90,7 @@ static inline void fd_disable_irq(void)
90static inline int fd_request_irq(void) 90static inline int fd_request_irq(void)
91{ 91{
92 return request_irq(FLOPPY_IRQ, floppy_interrupt, 92 return request_irq(FLOPPY_IRQ, floppy_interrupt,
93 IRQF_DISABLED, "floppy", NULL); 93 0, "floppy", NULL);
94} 94}
95 95
96static inline void fd_free_irq(void) 96static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b728275b9b..d193fb68cf2 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,24 +24,33 @@
24 24
25#define cpu_has_llsc 1 25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0 26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0 27#define cpu_has_ic_fills_f_dc 1
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0 28#define cpu_has_dsp 0
30#define cpu_has_mipsmt 0 29#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0 30#define cpu_icache_snoops_remote_store 1
32#define cpu_icache_snoops_remote_store 0
33 31
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 32#define cpu_has_64bits 1
36 33
37#define cpu_has_mips32r1 1 34#define cpu_has_mips32r1 1
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 1 35#define cpu_has_mips64r1 1
40#define cpu_has_mips64r2 0
41 36
42#define cpu_has_inclusive_pcaches 0 37#define cpu_has_inclusive_pcaches 0
43 38
44#define cpu_dcache_line_size() 32 39#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
46 41
42#if defined(CONFIG_CPU_XLR)
43#define cpu_has_userlocal 0
44#define cpu_has_dc_aliases 0
45#define cpu_has_mips32r2 0
46#define cpu_has_mips64r2 0
47#elif defined(CONFIG_CPU_XLP)
48#define cpu_has_userlocal 1
49#define cpu_has_mips32r2 1
50#define cpu_has_mips64r2 1
51#define cpu_has_dc_aliases 1
52#else
53#error "Unknown Netlogic CPU"
54#endif
55
47#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ 56#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
deleted file mode 100644
index 622c58710e5..00000000000
--- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
11#define __ASM_MACH_AU1XX_MC146818RTC_H
12
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15
16#define RTC_PORT(x) (0x0c000000 + (x))
17#define RTC_IRQ 8
18#define PB1500_RTC_ADDR 0x0c000000
19
20static inline unsigned char CMOS_READ(unsigned long offset)
21{
22 offset <<= 2;
23 return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
24}
25
26static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
27{
28 offset <<= 2;
29 au_writel(data, offset + PB1500_RTC_ADDR);
30}
31
32#define RTC_ALWAYS_BCD 1
33
34#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
deleted file mode 100644
index 65059255dc1..00000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Alchemy Semi Pb1000 Reference Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1000_H
27#define __ASM_PB1000_H
28
29/* PCMCIA PB1000 specific defines */
30#define PCMCIA_MAX_SOCK 1
31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
32
33#define PB1000_PCR 0xBE000000
34# define PCR_SLOT_0_VPP0 (1 << 0)
35# define PCR_SLOT_0_VPP1 (1 << 1)
36# define PCR_SLOT_0_VCC0 (1 << 2)
37# define PCR_SLOT_0_VCC1 (1 << 3)
38# define PCR_SLOT_0_RST (1 << 4)
39# define PCR_SLOT_1_VPP0 (1 << 8)
40# define PCR_SLOT_1_VPP1 (1 << 9)
41# define PCR_SLOT_1_VCC0 (1 << 10)
42# define PCR_SLOT_1_VCC1 (1 << 11)
43# define PCR_SLOT_1_RST (1 << 12)
44
45#define PB1000_MDR 0xBE000004
46# define MDR_PI (1 << 5) /* PCMCIA int latch */
47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
49
50#define PB1000_ACR1 0xBE000008
51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
65
66#define CPLD_AUX0 0xBE00000C
67#define CPLD_AUX1 0xBE000010
68#define CPLD_AUX2 0xBE000014
69
70/* Voltage levels */
71
72/* VPPEN1 - VPPEN0 */
73#define VPP_GND ((0 << 1) | (0 << 0))
74#define VPP_5V ((1 << 1) | (0 << 0))
75#define VPP_3V ((0 << 1) | (1 << 0))
76#define VPP_12V ((0 << 1) | (1 << 0))
77#define VPP_HIZ ((1 << 1) | (1 << 0))
78
79/* VCCEN1 - VCCEN0 */
80#define VCC_3V ((0 << 1) | (1 << 0))
81#define VCC_5V ((1 << 1) | (0 << 0))
82#define VCC_HIZ ((0 << 1) | (0 << 0))
83
84/* VPP/VCC */
85#define SET_VCC_VPP(VCC, VPP, SLOT) \
86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
87#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
deleted file mode 100644
index 374416adb65..00000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * AMD Alchemy Pb1200 Reference Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
29#include <asm/mach-au1x00/au1xxx_psc.h>
30
31#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
32#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
33#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
34#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
35
36/*
37 * SPI and SMB are muxed on the Pb1200 board.
38 * Refer to board documentation.
39 */
40#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
42/*
43 * AC97 and I2S are muxed on the Pb1200 board.
44 * Refer to board documentation.
45 */
46#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
47#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
48
49
50#define BCSR_SYSTEM_VDDI 0x001F
51#define BCSR_SYSTEM_POWEROFF 0x4000
52#define BCSR_SYSTEM_RESET 0x8000
53
54/* Bit positions for the different interrupt sources */
55#define BCSR_INT_IDE 0x0001
56#define BCSR_INT_ETH 0x0002
57#define BCSR_INT_PC0 0x0004
58#define BCSR_INT_PC0STSCHG 0x0008
59#define BCSR_INT_PC1 0x0010
60#define BCSR_INT_PC1STSCHG 0x0020
61#define BCSR_INT_DC 0x0040
62#define BCSR_INT_FLASHBUSY 0x0080
63#define BCSR_INT_PC0INSERT 0x0100
64#define BCSR_INT_PC0EJECT 0x0200
65#define BCSR_INT_PC1INSERT 0x0400
66#define BCSR_INT_PC1EJECT 0x0800
67#define BCSR_INT_SD0INSERT 0x1000
68#define BCSR_INT_SD0EJECT 0x2000
69#define BCSR_INT_SD1INSERT 0x4000
70#define BCSR_INT_SD1EJECT 0x8000
71
72#define SMC91C111_PHYS_ADDR 0x0D000300
73#define SMC91C111_INT PB1200_ETH_INT
74
75#define IDE_PHYS_ADDR 0x0C800000
76#define IDE_REG_SHIFT 5
77#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
78#define IDE_INT PB1200_IDE_INT
79
80#define NAND_PHYS_ADDR 0x1C000000
81
82/*
83 * Timing values as described in databook, * ns value stripped of
84 * lower 2 bits.
85 * These defines are here rather than an Au1200 generic file because
86 * the parts chosen on another board may be different and may require
87 * different timings.
88 */
89#define NAND_T_H (18 >> 2)
90#define NAND_T_PUL (30 >> 2)
91#define NAND_T_SU (30 >> 2)
92#define NAND_T_WH (30 >> 2)
93
94/* Bitfield shift amounts */
95#define NAND_T_H_SHIFT 0
96#define NAND_T_PUL_SHIFT 4
97#define NAND_T_SU_SHIFT 8
98#define NAND_T_WH_SHIFT 12
99
100#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
101 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
102 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
103 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
104
105/*
106 * External Interrupts for Pb1200 as of 8/6/2004.
107 * Bit positions in the CPLD registers can be calculated by taking
108 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
109 *
110 * Example: IDE bis pos is = 64 - 64
111 * ETH bit pos is = 65 - 64
112 */
113enum external_pb1200_ints {
114 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
115
116 PB1200_IDE_INT = PB1200_INT_BEGIN,
117 PB1200_ETH_INT,
118 PB1200_PC0_INT,
119 PB1200_PC0_STSCHG_INT,
120 PB1200_PC1_INT,
121 PB1200_PC1_STSCHG_INT,
122 PB1200_DC_INT,
123 PB1200_FLASHBUSY_INT,
124 PB1200_PC0_INSERT_INT,
125 PB1200_PC0_EJECT_INT,
126 PB1200_PC1_INSERT_INT,
127 PB1200_PC1_EJECT_INT,
128 PB1200_SD0_INSERT_INT,
129 PB1200_SD0_EJECT_INT,
130 PB1200_SD1_INSERT_INT,
131 PB1200_SD1_EJECT_INT,
132
133 PB1200_INT_END = PB1200_INT_BEGIN + 15
134};
135
136/* NAND chip select */
137#define NAND_CS 1
138
139#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88adebf..00000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * AMD Alchemy Semi PB1550 Reference Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h>
32
33#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
39#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
40#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
41#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
42
43/*
44 * Timing values as described in databook, * ns value stripped of
45 * lower 2 bits.
46 * These defines are here rather than an SOC1550 generic file because
47 * the parts chosen on another board may be different and may require
48 * different timings.
49 */
50#define NAND_T_H (18 >> 2)
51#define NAND_T_PUL (30 >> 2)
52#define NAND_T_SU (30 >> 2)
53#define NAND_T_WH (30 >> 2)
54
55/* Bitfield shift amounts */
56#define NAND_T_H_SHIFT 0
57#define NAND_T_PUL_SHIFT 4
58#define NAND_T_SU_SHIFT 8
59#define NAND_T_WH_SHIFT 12
60
61#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
62 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
63 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
64 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
65
66#define NAND_CS 1
67
68/* Should be done by YAMON */
69#define NAND_STCFG 0x00400005 /* 8-bit NAND */
70#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
71#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
72
73#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2ea7b817feb..7f87d824eeb 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1106,7 +1106,7 @@ do { \
1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1108 1108
1109/* BMIPS4380 */ 1109/* BMIPS43xx */
1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1112 1112
@@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
1667__BUILD_SET_C0(intcontrol) 1667__BUILD_SET_C0(intcontrol)
1668__BUILD_SET_C0(intctl) 1668__BUILD_SET_C0(intctl)
1669__BUILD_SET_C0(srsmap) 1669__BUILD_SET_C0(srsmap)
1670__BUILD_SET_C0(brcm_config_0)
1671__BUILD_SET_C0(brcm_bus_pll)
1672__BUILD_SET_C0(brcm_reset)
1673__BUILD_SET_C0(brcm_cmt_intr)
1674__BUILD_SET_C0(brcm_cmt_ctrl)
1675__BUILD_SET_C0(brcm_config)
1676__BUILD_SET_C0(brcm_mode)
1670 1677
1671#endif /* !__ASSEMBLY__ */ 1678#endif /* !__ASSEMBLY__ */
1672 1679
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02cacd..7467d1d933d 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr)
74} 74}
75#endif 75#endif
76 76
77#ifdef CONFIG_CPU_MIPS32_R1 77#ifdef CONFIG_CPU_BMIPS
78#define MODULE_PROC_FAMILY "BMIPS "
79#elif defined CONFIG_CPU_MIPS32_R1
78#define MODULE_PROC_FAMILY "MIPS32_R1 " 80#define MODULE_PROC_FAMILY "MIPS32_R1 "
79#elif defined CONFIG_CPU_MIPS32_R2 81#elif defined CONFIG_CPU_MIPS32_R2
80#define MODULE_PROC_FAMILY "MIPS32_R2 " 82#define MODULE_PROC_FAMILY "MIPS32_R2 "
@@ -120,6 +122,8 @@ search_module_dbetables(unsigned long addr)
120#define MODULE_PROC_FAMILY "OCTEON " 122#define MODULE_PROC_FAMILY "OCTEON "
121#elif defined CONFIG_CPU_XLR 123#elif defined CONFIG_CPU_XLR
122#define MODULE_PROC_FAMILY "XLR " 124#define MODULE_PROC_FAMILY "XLR "
125#elif defined CONFIG_CPU_XLP
126#define MODULE_PROC_FAMILY "XLP "
123#else 127#else
124#error MODULE_PROC_FAMILY undefined for your processor configuration 128#error MODULE_PROC_FAMILY undefined for your processor configuration
125#endif 129#endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
new file mode 100644
index 00000000000..fdd2f44c7b5
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NETLOGIC_COMMON_H_
36#define _NETLOGIC_COMMON_H_
37
38/*
39 * Common SMP definitions
40 */
41#define RESET_VEC_PHYS 0x1fc00000
42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
43#define BOOT_THREAD_MODE 0
44#define BOOT_NMI_LOCK 4
45#define BOOT_NMI_HANDLER 8
46
47#ifndef __ASSEMBLY__
48struct irq_desc;
49extern struct plat_smp_ops nlm_smp_ops;
50extern char nlm_reset_entry[], nlm_reset_entry_end[];
51void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
52void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
53void nlm_smp_irq_init(void);
54void nlm_boot_secondary_cpus(void);
55int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
56void nlm_rmiboot_preboot(void);
57
58static inline void
59nlm_set_nmi_handler(void *handler)
60{
61 char *reset_data;
62
63 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
64 *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
65}
66
67/*
68 * Misc.
69 */
70unsigned int nlm_get_cpu_frequency(void);
71
72extern unsigned long nlm_common_ebase;
73extern int nlm_threads_per_core;
74extern uint32_t nlm_cpumask, nlm_coremask;
75#endif
76#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
new file mode 100644
index 00000000000..72a0c788b47
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_HALDEFS_H__
36#define __NLM_HAL_HALDEFS_H__
37
38/*
39 * This file contains platform specific memory mapped IO implementation
40 * and will provide a way to read 32/64 bit memory mapped registers in
41 * all ABIs
42 */
43#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
44#error "o32 compile not supported on XLP yet"
45#endif
46/*
47 * For o32 compilation, we have to disable interrupts and enable KX bit to
48 * access 64 bit addresses or data.
49 *
50 * We need to disable interrupts because we save just the lower 32 bits of
51 * registers in interrupt handling. So if we get hit by an interrupt while
52 * using the upper 32 bits of a register, we lose.
53 */
54static inline uint32_t nlm_save_flags_kx(void)
55{
56 return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
57}
58
59static inline uint32_t nlm_save_flags_cop2(void)
60{
61 return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
62}
63
64static inline void nlm_restore_flags(uint32_t sr)
65{
66 write_c0_status(sr);
67}
68
69/*
70 * The n64 implementations are simple, the o32 implementations when they
71 * are added, will have to disable interrupts and enable KX before doing
72 * 64 bit ops.
73 */
74static inline uint32_t
75nlm_read_reg(uint64_t base, uint32_t reg)
76{
77 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
78
79 return *addr;
80}
81
82static inline void
83nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
84{
85 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
86
87 *addr = val;
88}
89
90static inline uint64_t
91nlm_read_reg64(uint64_t base, uint32_t reg)
92{
93 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
94 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
95
96 return *ptr;
97}
98
99static inline void
100nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
101{
102 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
103 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
104
105 *ptr = val;
106}
107
108/*
109 * Routines to store 32/64 bit values to 64 bit addresses,
110 * used when going thru XKPHYS to access registers
111 */
112static inline uint32_t
113nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
114{
115 return nlm_read_reg(base, reg);
116}
117
118static inline void
119nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
120{
121 nlm_write_reg(base, reg, val);
122}
123
124static inline uint64_t
125nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
126{
127 return nlm_read_reg64(base, reg);
128}
129
130static inline void
131nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
132{
133 nlm_write_reg64(base, reg, val);
134}
135
136/* Location where IO base is mapped */
137extern uint64_t nlm_io_base;
138
139#if defined(CONFIG_CPU_XLP)
140static inline uint64_t
141nlm_pcicfg_base(uint32_t devoffset)
142{
143 return nlm_io_base + devoffset;
144}
145
146static inline uint64_t
147nlm_xkphys_map_pcibar0(uint64_t pcibase)
148{
149 uint64_t paddr;
150
151 paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
152 return (uint64_t)0x9000000000000000 | paddr;
153}
154#elif defined(CONFIG_CPU_XLR)
155
156static inline uint64_t
157nlm_mmio_base(uint32_t devoffset)
158{
159 return nlm_io_base + devoffset;
160}
161#endif
162
163#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 00000000000..ca95133f1ad
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,187 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_BRIDGE_H__
36#define __NLM_HAL_BRIDGE_H__
37
38/**
39* @file_name mio.h
40* @author Netlogic Microsystems
41* @brief Basic definitions of XLP memory and io subsystem
42*/
43
44/*
45 * BRIDGE specific registers
46 *
47 * These registers start after the PCIe header, which has 0x40
48 * standard entries
49 */
50#define BRIDGE_MODE 0x00
51#define BRIDGE_PCI_CFG_BASE 0x01
52#define BRIDGE_PCI_CFG_LIMIT 0x02
53#define BRIDGE_PCIE_CFG_BASE 0x03
54#define BRIDGE_PCIE_CFG_LIMIT 0x04
55#define BRIDGE_BUSNUM_BAR0 0x05
56#define BRIDGE_BUSNUM_BAR1 0x06
57#define BRIDGE_BUSNUM_BAR2 0x07
58#define BRIDGE_BUSNUM_BAR3 0x08
59#define BRIDGE_BUSNUM_BAR4 0x09
60#define BRIDGE_BUSNUM_BAR5 0x0a
61#define BRIDGE_BUSNUM_BAR6 0x0b
62#define BRIDGE_FLASH_BAR0 0x0c
63#define BRIDGE_FLASH_BAR1 0x0d
64#define BRIDGE_FLASH_BAR2 0x0e
65#define BRIDGE_FLASH_BAR3 0x0f
66#define BRIDGE_FLASH_LIMIT0 0x10
67#define BRIDGE_FLASH_LIMIT1 0x11
68#define BRIDGE_FLASH_LIMIT2 0x12
69#define BRIDGE_FLASH_LIMIT3 0x13
70
71#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
72#define BRIDGE_DRAM_BAR0 0x14
73#define BRIDGE_DRAM_BAR1 0x15
74#define BRIDGE_DRAM_BAR2 0x16
75#define BRIDGE_DRAM_BAR3 0x17
76#define BRIDGE_DRAM_BAR4 0x18
77#define BRIDGE_DRAM_BAR5 0x19
78#define BRIDGE_DRAM_BAR6 0x1a
79#define BRIDGE_DRAM_BAR7 0x1b
80
81#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
82#define BRIDGE_DRAM_LIMIT0 0x1c
83#define BRIDGE_DRAM_LIMIT1 0x1d
84#define BRIDGE_DRAM_LIMIT2 0x1e
85#define BRIDGE_DRAM_LIMIT3 0x1f
86#define BRIDGE_DRAM_LIMIT4 0x20
87#define BRIDGE_DRAM_LIMIT5 0x21
88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23
90
91#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
94#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
95#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
96#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
99#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
102#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
103#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
104#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
107#define BRIDGE_PCIEMEM_BASE0 0x34
108#define BRIDGE_PCIEMEM_BASE1 0x35
109#define BRIDGE_PCIEMEM_BASE2 0x36
110#define BRIDGE_PCIEMEM_BASE3 0x37
111#define BRIDGE_PCIEMEM_LIMIT0 0x38
112#define BRIDGE_PCIEMEM_LIMIT1 0x39
113#define BRIDGE_PCIEMEM_LIMIT2 0x3a
114#define BRIDGE_PCIEMEM_LIMIT3 0x3b
115#define BRIDGE_PCIEIO_BASE0 0x3c
116#define BRIDGE_PCIEIO_BASE1 0x3d
117#define BRIDGE_PCIEIO_BASE2 0x3e
118#define BRIDGE_PCIEIO_BASE3 0x3f
119#define BRIDGE_PCIEIO_LIMIT0 0x40
120#define BRIDGE_PCIEIO_LIMIT1 0x41
121#define BRIDGE_PCIEIO_LIMIT2 0x42
122#define BRIDGE_PCIEIO_LIMIT3 0x43
123#define BRIDGE_PCIEMEM_BASE4 0x44
124#define BRIDGE_PCIEMEM_BASE5 0x45
125#define BRIDGE_PCIEMEM_BASE6 0x46
126#define BRIDGE_PCIEMEM_LIMIT4 0x47
127#define BRIDGE_PCIEMEM_LIMIT5 0x48
128#define BRIDGE_PCIEMEM_LIMIT6 0x49
129#define BRIDGE_PCIEIO_BASE4 0x4a
130#define BRIDGE_PCIEIO_BASE5 0x4b
131#define BRIDGE_PCIEIO_BASE6 0x4c
132#define BRIDGE_PCIEIO_LIMIT4 0x4d
133#define BRIDGE_PCIEIO_LIMIT5 0x4e
134#define BRIDGE_PCIEIO_LIMIT6 0x4f
135#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
136#define BRIDGE_EVNTCTR1_LOW 0x51
137#define BRIDGE_EVNTCTR1_HI 0x52
138#define BRIDGE_EVNT_CNT_CTL2 0x53
139#define BRIDGE_EVNTCTR2_LOW 0x54
140#define BRIDGE_EVNTCTR2_HI 0x55
141#define BRIDGE_TRACEBUF_MATCH0 0x56
142#define BRIDGE_TRACEBUF_MATCH1 0x57
143#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
144#define BRIDGE_TRACEBUF_MATCH_HI 0x59
145#define BRIDGE_TRACEBUF_CTRL 0x5a
146#define BRIDGE_TRACEBUF_INIT 0x5b
147#define BRIDGE_TRACEBUF_ACCESS 0x5c
148#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
149#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
150#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
151#define BRIDGE_TRACEBUF_READ_DATA3 0x60
152#define BRIDGE_TRACEBUF_STATUS 0x61
153#define BRIDGE_ADDRESS_ERROR0 0x62
154#define BRIDGE_ADDRESS_ERROR1 0x63
155#define BRIDGE_ADDRESS_ERROR2 0x64
156#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
157#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
158#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
159#define BRIDGE_LINE_FLUSH0 0x68
160#define BRIDGE_LINE_FLUSH1 0x69
161#define BRIDGE_NODE_ID 0x6a
162#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
163#define BRIDGE_PCIE0_WEIGHT 0x2c0
164#define BRIDGE_PCIE1_WEIGHT 0x2c1
165#define BRIDGE_PCIE2_WEIGHT 0x2c2
166#define BRIDGE_PCIE3_WEIGHT 0x2c3
167#define BRIDGE_USB_WEIGHT 0x2c4
168#define BRIDGE_NET_WEIGHT 0x2c5
169#define BRIDGE_POE_WEIGHT 0x2c6
170#define BRIDGE_CMS_WEIGHT 0x2c7
171#define BRIDGE_DMAENG_WEIGHT 0x2c8
172#define BRIDGE_SEC_WEIGHT 0x2c9
173#define BRIDGE_COMP_WEIGHT 0x2ca
174#define BRIDGE_GIO_WEIGHT 0x2cb
175#define BRIDGE_FLASH_WEIGHT 0x2cc
176
177#ifndef __ASSEMBLY__
178
179#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
180#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
181#define nlm_get_bridge_pcibase(node) \
182 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
183#define nlm_get_bridge_regbase(node) \
184 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
185
186#endif /* __ASSEMBLY__ */
187#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
new file mode 100644
index 00000000000..bf7d41deb9b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_CPUCONTROL_H__
36#define __NLM_HAL_CPUCONTROL_H__
37
38#define CPU_BLOCKID_IFU 0
39#define CPU_BLOCKID_ICU 1
40#define CPU_BLOCKID_IEU 2
41#define CPU_BLOCKID_LSU 3
42#define CPU_BLOCKID_MMU 4
43#define CPU_BLOCKID_PRF 5
44#define CPU_BLOCKID_SCH 7
45#define CPU_BLOCKID_SCU 8
46#define CPU_BLOCKID_FPU 9
47#define CPU_BLOCKID_MAP 10
48
49#define LSU_DEFEATURE 0x304
50#define LSU_CERRLOG_REGID 0x09
51#define SCHED_DEFEATURE 0x700
52
53/* Offsets of interest from the 'MAP' Block */
54#define MAP_THREADMODE 0x00
55#define MAP_EXT_EBASE_ENABLE 0x04
56#define MAP_CCDI_CONFIG 0x08
57#define MAP_THRD0_CCDI_STATUS 0x0c
58#define MAP_THRD1_CCDI_STATUS 0x10
59#define MAP_THRD2_CCDI_STATUS 0x14
60#define MAP_THRD3_CCDI_STATUS 0x18
61#define MAP_THRD0_DEBUG_MODE 0x1c
62#define MAP_THRD1_DEBUG_MODE 0x20
63#define MAP_THRD2_DEBUG_MODE 0x24
64#define MAP_THRD3_DEBUG_MODE 0x28
65#define MAP_MISC_STATE 0x60
66#define MAP_DEBUG_READ_CTL 0x64
67#define MAP_DEBUG_READ_REG0 0x68
68#define MAP_DEBUG_READ_REG1 0x6c
69
70#define MMU_SETUP 0x400
71#define MMU_LFSRSEED 0x401
72#define MMU_HPW_NUM_PAGE_LVL 0x410
73#define MMU_PGWKR_PGDBASE 0x411
74#define MMU_PGWKR_PGDSHFT 0x412
75#define MMU_PGWKR_PGDMASK 0x413
76#define MMU_PGWKR_PUDSHFT 0x414
77#define MMU_PGWKR_PUDMASK 0x415
78#define MMU_PGWKR_PMDSHFT 0x416
79#define MMU_PGWKR_PMDMASK 0x417
80#define MMU_PGWKR_PTESHFT 0x418
81#define MMU_PGWKR_PTEMASK 0x419
82
83#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
new file mode 100644
index 00000000000..86cc3391e50
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -0,0 +1,153 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_IOMAP_H__
36#define __NLM_HAL_IOMAP_H__
37
38#define XLP_DEFAULT_IO_BASE 0x18000000
39#define NMI_BASE 0xbfc00000
40#define XLP_IO_CLK 133333333
41
42#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
43#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
44#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
45#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
46#define XLP_IO_PCI_HDRSZ 0x100
47#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
48#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
49 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
50
51#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
52/* coherent inter chip */
53#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
54#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
55#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
56#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
57
58#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
59#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
60#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
61#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
62#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
63
64#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
65#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
66#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
67#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
68#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
69#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
70#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
71
72#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
73#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
74
75#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
76
77#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
78#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
79#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
80
81#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
82#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
83#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
84#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
85#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
86#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
87#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
88/* system management */
89#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
90#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
91
92#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
93#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
94#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
95/* SD flash */
96#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
97#define XLP_IO_MMC_OFFSET(node, slot) \
98 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
99
100/* PCI config header register id's */
101#define XLP_PCI_CFGREG0 0x00
102#define XLP_PCI_CFGREG1 0x01
103#define XLP_PCI_CFGREG2 0x02
104#define XLP_PCI_CFGREG3 0x03
105#define XLP_PCI_CFGREG4 0x04
106#define XLP_PCI_CFGREG5 0x05
107#define XLP_PCI_DEVINFO_REG0 0x30
108#define XLP_PCI_DEVINFO_REG1 0x31
109#define XLP_PCI_DEVINFO_REG2 0x32
110#define XLP_PCI_DEVINFO_REG3 0x33
111#define XLP_PCI_DEVINFO_REG4 0x34
112#define XLP_PCI_DEVINFO_REG5 0x35
113#define XLP_PCI_DEVINFO_REG6 0x36
114#define XLP_PCI_DEVINFO_REG7 0x37
115#define XLP_PCI_DEVSCRATCH_REG0 0x38
116#define XLP_PCI_DEVSCRATCH_REG1 0x39
117#define XLP_PCI_DEVSCRATCH_REG2 0x3a
118#define XLP_PCI_DEVSCRATCH_REG3 0x3b
119#define XLP_PCI_MSGSTN_REG 0x3c
120#define XLP_PCI_IRTINFO_REG 0x3d
121#define XLP_PCI_UCODEINFO_REG 0x3e
122#define XLP_PCI_SBB_WT_REG 0x3f
123
124/* PCI IDs for SoC device */
125#define PCI_VENDOR_NETLOGIC 0x184e
126
127#define PCI_DEVICE_ID_NLM_ROOT 0x1001
128#define PCI_DEVICE_ID_NLM_ICI 0x1002
129#define PCI_DEVICE_ID_NLM_PIC 0x1003
130#define PCI_DEVICE_ID_NLM_PCIE 0x1004
131#define PCI_DEVICE_ID_NLM_EHCI 0x1007
132#define PCI_DEVICE_ID_NLM_ILK 0x1008
133#define PCI_DEVICE_ID_NLM_NAE 0x1009
134#define PCI_DEVICE_ID_NLM_POE 0x100A
135#define PCI_DEVICE_ID_NLM_FMN 0x100B
136#define PCI_DEVICE_ID_NLM_RAID 0x100D
137#define PCI_DEVICE_ID_NLM_SAE 0x100D
138#define PCI_DEVICE_ID_NLM_RSA 0x100E
139#define PCI_DEVICE_ID_NLM_CMP 0x100F
140#define PCI_DEVICE_ID_NLM_UART 0x1010
141#define PCI_DEVICE_ID_NLM_I2C 0x1011
142#define PCI_DEVICE_ID_NLM_NOR 0x1015
143#define PCI_DEVICE_ID_NLM_NAND 0x1016
144#define PCI_DEVICE_ID_NLM_MMC 0x1018
145
146#ifndef __ASSEMBLY__
147
148#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
149#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
150
151#endif /* !__ASSEMBLY */
152
153#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
new file mode 100644
index 00000000000..b6628f7ccf7
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -0,0 +1,411 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_HAL_PIC_H
36#define _NLM_HAL_PIC_H
37
38/* PIC Specific registers */
39#define PIC_CTRL 0x00
40
41/* PIC control register defines */
42#define PIC_CTRL_ITV 32 /* interrupt timeout value */
43#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
44#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
45#define PIC_CTRL_STE 10 /* system timer interrupt enable */
46#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
47#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
48#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
49#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
50#define PIC_CTRL_WTE 0 /* watchdog timer enable */
51
52/* PIC Status register defines */
53#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
54#define PIC_ITE_STATUS 32 /* interrupt timeout status */
55#define PIC_STS_STATUS 4 /* System timer interrupt status */
56#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
57#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
58
59/* PIC IPI control register offsets */
60#define PIC_IPICTRL_NMI 32
61#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
62#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
63#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
64
65/* PIC IRT register offsets */
66#define PIC_IRT_ENABLE 31
67#define PIC_IRT_NMI 29
68#define PIC_IRT_SCH 28 /* Scheduling scheme */
69#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
70#define PIC_IRT_DT 19 /* Destination type */
71#define PIC_IRT_DB 16 /* Destination base */
72#define PIC_IRT_DTE 0 /* Destination thread enables */
73
74#define PIC_BYTESWAP 0x02
75#define PIC_STATUS 0x04
76#define PIC_INTR_TIMEOUT 0x06
77#define PIC_ICI0_INTR_TIMEOUT 0x08
78#define PIC_ICI1_INTR_TIMEOUT 0x0a
79#define PIC_ICI2_INTR_TIMEOUT 0x0c
80#define PIC_IPI_CTL 0x0e
81#define PIC_INT_ACK 0x10
82#define PIC_INT_PENDING0 0x12
83#define PIC_INT_PENDING1 0x14
84#define PIC_INT_PENDING2 0x16
85
86#define PIC_WDOG0_MAXVAL 0x18
87#define PIC_WDOG0_COUNT 0x1a
88#define PIC_WDOG0_ENABLE0 0x1c
89#define PIC_WDOG0_ENABLE1 0x1e
90#define PIC_WDOG0_BEATCMD 0x20
91#define PIC_WDOG0_BEAT0 0x22
92#define PIC_WDOG0_BEAT1 0x24
93
94#define PIC_WDOG1_MAXVAL 0x26
95#define PIC_WDOG1_COUNT 0x28
96#define PIC_WDOG1_ENABLE0 0x2a
97#define PIC_WDOG1_ENABLE1 0x2c
98#define PIC_WDOG1_BEATCMD 0x2e
99#define PIC_WDOG1_BEAT0 0x30
100#define PIC_WDOG1_BEAT1 0x32
101
102#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
109
110#define PIC_TIMER0_MAXVAL 0x34
111#define PIC_TIMER1_MAXVAL 0x36
112#define PIC_TIMER2_MAXVAL 0x38
113#define PIC_TIMER3_MAXVAL 0x3a
114#define PIC_TIMER4_MAXVAL 0x3c
115#define PIC_TIMER5_MAXVAL 0x3e
116#define PIC_TIMER6_MAXVAL 0x40
117#define PIC_TIMER7_MAXVAL 0x42
118#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
119
120#define PIC_TIMER0_COUNT 0x44
121#define PIC_TIMER1_COUNT 0x46
122#define PIC_TIMER2_COUNT 0x48
123#define PIC_TIMER3_COUNT 0x4a
124#define PIC_TIMER4_COUNT 0x4c
125#define PIC_TIMER5_COUNT 0x4e
126#define PIC_TIMER6_COUNT 0x50
127#define PIC_TIMER7_COUNT 0x52
128#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
129
130#define PIC_ITE0_N0_N1 0x54
131#define PIC_ITE1_N0_N1 0x58
132#define PIC_ITE2_N0_N1 0x5c
133#define PIC_ITE3_N0_N1 0x60
134#define PIC_ITE4_N0_N1 0x64
135#define PIC_ITE5_N0_N1 0x68
136#define PIC_ITE6_N0_N1 0x6c
137#define PIC_ITE7_N0_N1 0x70
138#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
139
140#define PIC_ITE0_N2_N3 0x56
141#define PIC_ITE1_N2_N3 0x5a
142#define PIC_ITE2_N2_N3 0x5e
143#define PIC_ITE3_N2_N3 0x62
144#define PIC_ITE4_N2_N3 0x66
145#define PIC_ITE5_N2_N3 0x6a
146#define PIC_ITE6_N2_N3 0x6e
147#define PIC_ITE7_N2_N3 0x72
148#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
149
150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
154
155/*
156 * IRT Map
157 */
158#define PIC_NUM_IRTS 160
159
160#define PIC_IRT_WD_0_INDEX 0
161#define PIC_IRT_WD_1_INDEX 1
162#define PIC_IRT_WD_NMI_0_INDEX 2
163#define PIC_IRT_WD_NMI_1_INDEX 3
164#define PIC_IRT_TIMER_0_INDEX 4
165#define PIC_IRT_TIMER_1_INDEX 5
166#define PIC_IRT_TIMER_2_INDEX 6
167#define PIC_IRT_TIMER_3_INDEX 7
168#define PIC_IRT_TIMER_4_INDEX 8
169#define PIC_IRT_TIMER_5_INDEX 9
170#define PIC_IRT_TIMER_6_INDEX 10
171#define PIC_IRT_TIMER_7_INDEX 11
172#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
173#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
174
175
176/* 11 and 12 */
177#define PIC_NUM_MSG_Q_IRTS 32
178#define PIC_IRT_MSG_Q0_INDEX 12
179#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
180/* 12 to 43 */
181#define PIC_IRT_MSG_0_INDEX 44
182#define PIC_IRT_MSG_1_INDEX 45
183/* 44 and 45 */
184#define PIC_NUM_PCIE_MSIX_IRTS 32
185#define PIC_IRT_PCIE_MSIX_0_INDEX 46
186#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
187/* 46 to 77 */
188#define PIC_NUM_PCIE_LINK_IRTS 4
189#define PIC_IRT_PCIE_LINK_0_INDEX 78
190#define PIC_IRT_PCIE_LINK_1_INDEX 79
191#define PIC_IRT_PCIE_LINK_2_INDEX 80
192#define PIC_IRT_PCIE_LINK_3_INDEX 81
193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194/* 78 to 81 */
195#define PIC_NUM_NA_IRTS 32
196/* 82 to 113 */
197#define PIC_IRT_NA_0_INDEX 82
198#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX)
199#define PIC_IRT_POE_INDEX 114
200
201#define PIC_NUM_USB_IRTS 6
202#define PIC_IRT_USB_0_INDEX 115
203#define PIC_IRT_EHCI_0_INDEX 115
204#define PIC_IRT_EHCI_1_INDEX 118
205#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
206/* 115 to 120 */
207#define PIC_IRT_GDX_INDEX 121
208#define PIC_IRT_SEC_INDEX 122
209#define PIC_IRT_RSA_INDEX 123
210
211#define PIC_NUM_COMP_IRTS 4
212#define PIC_IRT_COMP_0_INDEX 124
213#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX)
214/* 124 to 127 */
215#define PIC_IRT_GBU_INDEX 128
216#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */
217#define PIC_IRT_ICC_1_INDEX 130
218#define PIC_IRT_ICC_2_INDEX 131
219#define PIC_IRT_CAM_INDEX 132
220#define PIC_IRT_UART_0_INDEX 133
221#define PIC_IRT_UART_1_INDEX 134
222#define PIC_IRT_I2C_0_INDEX 135
223#define PIC_IRT_I2C_1_INDEX 136
224#define PIC_IRT_SYS_0_INDEX 137
225#define PIC_IRT_SYS_1_INDEX 138
226#define PIC_IRT_JTAG_INDEX 139
227#define PIC_IRT_PIC_INDEX 140
228#define PIC_IRT_NBU_INDEX 141
229#define PIC_IRT_TCU_INDEX 142
230#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */
231#define PIC_IRT_DMC_0_INDEX 144
232#define PIC_IRT_DMC_1_INDEX 145
233
234#define PIC_NUM_GPIO_IRTS 4
235#define PIC_IRT_GPIO_0_INDEX 146
236#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX)
237
238/* 146 to 149 */
239#define PIC_IRT_NOR_INDEX 150
240#define PIC_IRT_NAND_INDEX 151
241#define PIC_IRT_SPI_INDEX 152
242#define PIC_IRT_MMC_INDEX 153
243
244#define PIC_CLOCK_TIMER 7
245#define PIC_IRQ_BASE 8
246
247#if !defined(LOCORE) && !defined(__ASSEMBLY__)
248
249#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
250#define PIC_IRT_LAST_IRQ 63
251#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
252
253/*
254 * Misc
255 */
256#define PIC_IRT_VALID 1
257#define PIC_LOCAL_SCHEDULING 1
258#define PIC_GLOBAL_SCHEDULING 0
259
260#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
261#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
262#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
263#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
264
265/* IRT and h/w interrupt routines */
266static inline int
267nlm_pic_read_irt(uint64_t base, int irt_index)
268{
269 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
270}
271
272static inline uint64_t
273nlm_pic_read_control(uint64_t base)
274{
275 return nlm_read_pic_reg(base, PIC_CTRL);
276}
277
278static inline void
279nlm_pic_write_control(uint64_t base, uint64_t control)
280{
281 nlm_write_pic_reg(base, PIC_CTRL, control);
282}
283
284static inline void
285nlm_pic_update_control(uint64_t base, uint64_t control)
286{
287 uint64_t val;
288
289 val = nlm_read_pic_reg(base, PIC_CTRL);
290 nlm_write_pic_reg(base, PIC_CTRL, control | val);
291}
292
293static inline void
294nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
295{
296 uint64_t val;
297
298 val = nlm_read_pic_reg(base, PIC_IRT(irt));
299 val |= cpu & 0xf;
300 if (cpu > 15)
301 val |= 1 << 16;
302 nlm_write_pic_reg(base, PIC_IRT(irt), val);
303}
304
305static inline void
306nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
307 int sch, int vec, int dt, int db, int dte)
308{
309 uint64_t val;
310
311 val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
312 ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
313 ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
314 (dte & 0xffff);
315
316 nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
317}
318
319static inline void
320nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
321 int sch, int vec, int cpu)
322{
323 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
324 (cpu >> 4), /* thread group */
325 1 << (cpu & 0xf)); /* thread mask */
326}
327
328static inline uint64_t
329nlm_pic_read_timer(uint64_t base, int timer)
330{
331 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
332}
333
334static inline void
335nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
336{
337 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
338}
339
340static inline void
341nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
342{
343 uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
344 int en;
345
346 en = (irq > 0);
347 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
348 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
349 en, 0, 0, irq, cpu);
350
351 /* enable the timer */
352 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
353 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
354}
355
356static inline void
357nlm_pic_enable_irt(uint64_t base, int irt)
358{
359 uint64_t reg;
360
361 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
362 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
363}
364
365static inline void
366nlm_pic_disable_irt(uint64_t base, int irt)
367{
368 uint32_t reg;
369
370 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
371 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
372}
373
374static inline void
375nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
376{
377 uint64_t ipi;
378 int node, ncpu;
379
380 node = hwt / 32;
381 ncpu = hwt & 0x1f;
382 ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
383 (1 << (ncpu & 0xf));
384 if (ncpu > 15)
385 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
386
387 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
388}
389
390static inline void
391nlm_pic_ack(uint64_t base, int irt_num)
392{
393 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
394
395 /* Ack the Status register for Watchdog & System timers */
396 if (irt_num < 12)
397 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
398}
399
400static inline void
401nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
402{
403 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0);
404}
405
406extern uint64_t nlm_pic_base;
407int nlm_irq_to_irt(int irq);
408int nlm_irt_to_irq(int irt);
409
410#endif /* __ASSEMBLY__ */
411#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
new file mode 100644
index 00000000000..21432f7d89b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -0,0 +1,129 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_SYS_H__
36#define __NLM_HAL_SYS_H__
37
38/**
39* @file_name sys.h
40* @author Netlogic Microsystems
41* @brief HAL for System configuration registers
42*/
43#define SYS_CHIP_RESET 0x00
44#define SYS_POWER_ON_RESET_CFG 0x01
45#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
46#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
47#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
48#define SYS_EFUSE_DEVICE_CFG3 0x05
49#define SYS_EFUSE_DEVICE_CFG4 0x06
50#define SYS_EFUSE_DEVICE_CFG5 0x07
51#define SYS_EFUSE_DEVICE_CFG6 0x08
52#define SYS_EFUSE_DEVICE_CFG7 0x09
53#define SYS_PLL_CTRL 0x0a
54#define SYS_CPU_RESET 0x0b
55#define SYS_CPU_NONCOHERENT_MODE 0x0d
56#define SYS_CORE_DFS_DIS_CTRL 0x0e
57#define SYS_CORE_DFS_RST_CTRL 0x0f
58#define SYS_CORE_DFS_BYP_CTRL 0x10
59#define SYS_CORE_DFS_PHA_CTRL 0x11
60#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
61#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
62#define SYS_CORE_DFS_DIV_VALUE 0x14
63#define SYS_RESET 0x15
64#define SYS_DFS_DIS_CTRL 0x16
65#define SYS_DFS_RST_CTRL 0x17
66#define SYS_DFS_BYP_CTRL 0x18
67#define SYS_DFS_DIV_INC_CTRL 0x19
68#define SYS_DFS_DIV_DEC_CTRL 0x1a
69#define SYS_DFS_DIV_VALUE0 0x1b
70#define SYS_DFS_DIV_VALUE1 0x1c
71#define SYS_SENSE_AMP_DLY 0x1d
72#define SYS_SOC_SENSE_AMP_DLY 0x1e
73#define SYS_CTRL0 0x1f
74#define SYS_CTRL1 0x20
75#define SYS_TIMEOUT_BS1 0x21
76#define SYS_BYTE_SWAP 0x22
77#define SYS_VRM_VID 0x23
78#define SYS_PWR_RAM_CMD 0x24
79#define SYS_PWR_RAM_ADDR 0x25
80#define SYS_PWR_RAM_DATA0 0x26
81#define SYS_PWR_RAM_DATA1 0x27
82#define SYS_PWR_RAM_DATA2 0x28
83#define SYS_PWR_UCODE 0x29
84#define SYS_CPU0_PWR_STATUS 0x2a
85#define SYS_CPU1_PWR_STATUS 0x2b
86#define SYS_CPU2_PWR_STATUS 0x2c
87#define SYS_CPU3_PWR_STATUS 0x2d
88#define SYS_CPU4_PWR_STATUS 0x2e
89#define SYS_CPU5_PWR_STATUS 0x2f
90#define SYS_CPU6_PWR_STATUS 0x30
91#define SYS_CPU7_PWR_STATUS 0x31
92#define SYS_STATUS 0x32
93#define SYS_INT_POL 0x33
94#define SYS_INT_TYPE 0x34
95#define SYS_INT_STATUS 0x35
96#define SYS_INT_MASK0 0x36
97#define SYS_INT_MASK1 0x37
98#define SYS_UCO_S_ECC 0x38
99#define SYS_UCO_M_ECC 0x39
100#define SYS_UCO_ADDR 0x3a
101#define SYS_UCO_INSTR 0x3b
102#define SYS_MEM_BIST0 0x3c
103#define SYS_MEM_BIST1 0x3d
104#define SYS_MEM_BIST2 0x3e
105#define SYS_MEM_BIST3 0x3f
106#define SYS_MEM_BIST4 0x40
107#define SYS_MEM_BIST5 0x41
108#define SYS_MEM_BIST6 0x42
109#define SYS_MEM_BIST7 0x43
110#define SYS_MEM_BIST8 0x44
111#define SYS_MEM_BIST9 0x45
112#define SYS_MEM_BIST10 0x46
113#define SYS_MEM_BIST11 0x47
114#define SYS_MEM_BIST12 0x48
115#define SYS_SCRTCH0 0x49
116#define SYS_SCRTCH1 0x4a
117#define SYS_SCRTCH2 0x4b
118#define SYS_SCRTCH3 0x4c
119
120#ifndef __ASSEMBLY__
121
122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
123#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126
127extern uint64_t nlm_sys_base;
128#endif
129#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
new file mode 100644
index 00000000000..6a7046ca094
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -0,0 +1,191 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __XLP_HAL_UART_H__
36#define __XLP_HAL_UART_H__
37
38/* UART Specific registers */
39#define UART_RX_DATA 0x00
40#define UART_TX_DATA 0x00
41
42#define UART_INT_EN 0x01
43#define UART_INT_ID 0x02
44#define UART_FIFO_CTL 0x02
45#define UART_LINE_CTL 0x03
46#define UART_MODEM_CTL 0x04
47#define UART_LINE_STS 0x05
48#define UART_MODEM_STS 0x06
49
50#define UART_DIVISOR0 0x00
51#define UART_DIVISOR1 0x01
52
53#define BASE_BAUD (XLP_IO_CLK/16)
54#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
55
56/* LCR mask values */
57#define LCR_5BITS 0x00
58#define LCR_6BITS 0x01
59#define LCR_7BITS 0x02
60#define LCR_8BITS 0x03
61#define LCR_STOPB 0x04
62#define LCR_PENAB 0x08
63#define LCR_PODD 0x00
64#define LCR_PEVEN 0x10
65#define LCR_PONE 0x20
66#define LCR_PZERO 0x30
67#define LCR_SBREAK 0x40
68#define LCR_EFR_ENABLE 0xbf
69#define LCR_DLAB 0x80
70
71/* MCR mask values */
72#define MCR_DTR 0x01
73#define MCR_RTS 0x02
74#define MCR_DRS 0x04
75#define MCR_IE 0x08
76#define MCR_LOOPBACK 0x10
77
78/* FCR mask values */
79#define FCR_RCV_RST 0x02
80#define FCR_XMT_RST 0x04
81#define FCR_RX_LOW 0x00
82#define FCR_RX_MEDL 0x40
83#define FCR_RX_MEDH 0x80
84#define FCR_RX_HIGH 0xc0
85
86/* IER mask values */
87#define IER_ERXRDY 0x1
88#define IER_ETXRDY 0x2
89#define IER_ERLS 0x4
90#define IER_EMSC 0x8
91
92#if !defined(LOCORE) && !defined(__ASSEMBLY__)
93
94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96#define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
98#define nlm_get_uart_regbase(node, inst) \
99 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
100
101static inline void
102nlm_uart_set_baudrate(uint64_t base, int baud)
103{
104 uint32_t lcr;
105
106 lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
107
108 /* enable divisor register, and write baud values */
109 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
110 nlm_write_uart_reg(base, UART_DIVISOR0,
111 (BAUD_DIVISOR(baud) & 0xff));
112 nlm_write_uart_reg(base, UART_DIVISOR1,
113 ((BAUD_DIVISOR(baud) >> 8) & 0xff));
114
115 /* restore default lcr */
116 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
117}
118
119static inline void
120nlm_uart_outbyte(uint64_t base, char c)
121{
122 uint32_t lsr;
123
124 for (;;) {
125 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
126 if (lsr & 0x20)
127 break;
128 }
129
130 nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
131}
132
133static inline char
134nlm_uart_inbyte(uint64_t base)
135{
136 int data, lsr;
137
138 for (;;) {
139 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
140 if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
141 data = 0;
142 break;
143 }
144 if (lsr & 0x01) { /* Rx data */
145 data = nlm_read_uart_reg(base, UART_RX_DATA);
146 break;
147 }
148 }
149
150 return (char)data;
151}
152
153static inline int
154nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
155 int parity, int int_en, int loopback)
156{
157 uint32_t lcr;
158
159 lcr = 0;
160 if (databits >= 8)
161 lcr |= LCR_8BITS;
162 else if (databits == 7)
163 lcr |= LCR_7BITS;
164 else if (databits == 6)
165 lcr |= LCR_6BITS;
166 else
167 lcr |= LCR_5BITS;
168
169 if (stopbits > 1)
170 lcr |= LCR_STOPB;
171
172 lcr |= parity << 3;
173
174 /* setup default lcr */
175 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
176
177 /* Reset the FIFOs */
178 nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
179
180 nlm_uart_set_baudrate(base, baud);
181
182 if (loopback)
183 nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
184
185 if (int_en)
186 nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
187
188 return 0;
189}
190#endif /* !LOCORE && !__ASSEMBLY__ */
191#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
new file mode 100644
index 00000000000..1540588e396
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_HAL_XLP_H
36#define _NLM_HAL_XLP_H
37
38#define PIC_UART_0_IRQ 17
39#define PIC_UART_1_IRQ 18
40
41#ifndef __ASSEMBLY__
42
43/* SMP support functions */
44void xlp_boot_core0_siblings(void);
45void xlp_wakeup_secondary_cpus(void);
46
47void xlp_mmu_init(void);
48void nlm_hal_init(void);
49
50#endif /* !__ASSEMBLY__ */
51#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e3a4dd5304..2e768f032e8 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -106,26 +106,4 @@
106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
108 108
109#ifndef __ASSEMBLY__
110#include <linux/types.h>
111#include <asm/byteorder.h>
112
113typedef volatile __u32 nlm_reg_t;
114extern unsigned long netlogic_io_base;
115
116/* FIXME read once in write_reg */
117#ifdef CONFIG_CPU_LITTLE_ENDIAN
118#define netlogic_read_reg(base, offset) ((base)[(offset)])
119#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
120#else
121#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
122#define netlogic_write_reg(base, offset, value) \
123 ((base)[(offset)] = cpu_to_be32((value)))
124#endif
125
126#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
127#define netlogic_write_reg_le32(base, offset, value) \
128 ((base)[(offset)] = cpu_to_le32((value)))
129#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
130#endif /* __ASSEMBLY__ */
131#endif 109#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
new file mode 100644
index 00000000000..7e39d40be4f
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef ASM_RMI_MSIDEF_H
36#define ASM_RMI_MSIDEF_H
37
38/*
39 * Constants for Intel APIC based MSI messages.
40 * Adapted for the RMI XLR using identical defines
41 */
42
43/*
44 * Shifts for MSI data
45 */
46
47#define MSI_DATA_VECTOR_SHIFT 0
48#define MSI_DATA_VECTOR_MASK 0x000000ff
49#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \
50 MSI_DATA_VECTOR_MASK)
51
52#define MSI_DATA_DELIVERY_MODE_SHIFT 8
53#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
54#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
55
56#define MSI_DATA_LEVEL_SHIFT 14
57#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
58#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
59
60#define MSI_DATA_TRIGGER_SHIFT 15
61#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
62#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
63
64/*
65 * Shift/mask fields for msi address
66 */
67
68#define MSI_ADDR_BASE_HI 0
69#define MSI_ADDR_BASE_LO 0xfee00000
70
71#define MSI_ADDR_DEST_MODE_SHIFT 2
72#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
73#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
74
75#define MSI_ADDR_REDIRECTION_SHIFT 3
76#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
77#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
78
79#define MSI_ADDR_DEST_ID_SHIFT 12
80#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
81#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
82 MSI_ADDR_DEST_ID_MASK)
83
84#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 5cceb746f08..868013e62f3 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,39 +193,72 @@
193/* end XLS */ 193/* end XLS */
194 194
195#ifndef __ASSEMBLY__ 195#ifndef __ASSEMBLY__
196static inline void pic_send_ipi(u32 ipi) 196
197#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
198 ((irq) <= PIC_TIMER_7_IRQ))
199#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
200 ((irq) <= PIC_IRT_LAST_IRQ))
201
202static inline int
203nlm_irq_to_irt(int irq)
197{ 204{
198 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 205 if (PIC_IRQ_IS_IRT(irq) == 0)
206 return -1;
199 207
200 netlogic_write_reg(mmio, PIC_IPI, ipi); 208 return PIC_IRQ_TO_INTR(irq);
201} 209}
202 210
203static inline u32 pic_read_control(void) 211static inline int
212nlm_irt_to_irq(int irt)
204{ 213{
205 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
206 214
207 return netlogic_read_reg(mmio, PIC_CTRL); 215 return PIC_INTR_TO_IRQ(irt);
208} 216}
209 217
210static inline void pic_write_control(u32 control) 218static inline void
219nlm_pic_enable_irt(uint64_t base, int irt)
211{ 220{
212 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 221 uint32_t reg;
213 222
214 netlogic_write_reg(mmio, PIC_CTRL, control); 223 reg = nlm_read_reg(base, PIC_IRT_1(irt));
224 nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
215} 225}
216 226
217static inline void pic_update_control(u32 control) 227static inline void
228nlm_pic_disable_irt(uint64_t base, int irt)
218{ 229{
219 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 230 uint32_t reg;
220 231
221 netlogic_write_reg(mmio, PIC_CTRL, 232 reg = nlm_read_reg(base, PIC_IRT_1(irt));
222 (control | netlogic_read_reg(mmio, PIC_CTRL))); 233 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
223} 234}
224 235
225#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ 236static inline void
226 ((irq) <= PIC_TIMER_7_IRQ)) 237nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
227#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ 238{
228 ((irq) <= PIC_IRT_LAST_IRQ)) 239 unsigned int tid, pid;
229#endif 240
241 tid = hwt & 0x3;
242 pid = (hwt >> 2) & 0x07;
243 nlm_write_reg(base, PIC_IPI,
244 (pid << 20) | (tid << 16) | (nmi << 8) | irq);
245}
246
247static inline void
248nlm_pic_ack(uint64_t base, int irt)
249{
250 nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
251}
230 252
253static inline void
254nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
255{
256 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
257 /* local scheduling, invalid, level by default */
258 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq);
260}
261
262extern uint64_t nlm_pic_base;
263#endif
231#endif /* _ASM_NLM_XLR_PIC_H */ 264#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index 3e6372692a0..ff4a17b0bf7 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -40,17 +40,8 @@ struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int); 40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int); 41void nlm_xlr_uart_out(struct uart_port *, int, int);
42 42
43/* SMP support functions */ 43/* SMP helpers */
44struct irq_desc; 44void xlr_wakeup_secondary_cpus(void);
45void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
46void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
47int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
48void nlm_smp_irq_init(void);
49void nlm_boot_smp_nmi(void);
50void prom_pre_boot_secondary_cpus(void);
51
52extern struct plat_smp_ops nlm_smp_ops;
53extern unsigned long nlm_common_ebase;
54 45
55/* XLS B silicon "Rook" */ 46/* XLS B silicon "Rook" */
56static inline unsigned int nlm_chip_is_xls_b(void) 47static inline unsigned int nlm_chip_is_xls_b(void)
diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
new file mode 100644
index 00000000000..3c74d826e2e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
@@ -0,0 +1,274 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2009 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Typedefs and defines for working with Octeon physical addresses.
30 *
31 */
32#ifndef __CVMX_ADDRESS_H__
33#define __CVMX_ADDRESS_H__
34
35#if 0
36typedef enum {
37 CVMX_MIPS_SPACE_XKSEG = 3LL,
38 CVMX_MIPS_SPACE_XKPHYS = 2LL,
39 CVMX_MIPS_SPACE_XSSEG = 1LL,
40 CVMX_MIPS_SPACE_XUSEG = 0LL
41} cvmx_mips_space_t;
42#endif
43
44typedef enum {
45 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
46 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
47 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
48 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
49} cvmx_mips_xkseg_space_t;
50
51/* decodes <14:13> of a kseg3 window address */
52typedef enum {
53 CVMX_ADD_WIN_SCR = 0L,
54 /* see cvmx_add_win_dma_dec_t for further decode */
55 CVMX_ADD_WIN_DMA = 1L,
56 CVMX_ADD_WIN_UNUSED = 2L,
57 CVMX_ADD_WIN_UNUSED2 = 3L
58} cvmx_add_win_dec_t;
59
60/* decode within DMA space */
61typedef enum {
62 /*
63 * Add store data to the write buffer entry, allocating it if
64 * necessary.
65 */
66 CVMX_ADD_WIN_DMA_ADD = 0L,
67 /* send out the write buffer entry to DRAM */
68 CVMX_ADD_WIN_DMA_SENDMEM = 1L,
69 /* store data must be normal DRAM memory space address in this case */
70 /* send out the write buffer entry as an IOBDMA command */
71 CVMX_ADD_WIN_DMA_SENDDMA = 2L,
72 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
73 /* send out the write buffer entry as an IO write */
74 CVMX_ADD_WIN_DMA_SENDIO = 3L,
75 /* store data must be normal IO space address in this case */
76 /* send out a single-tick command on the NCB bus */
77 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
78 /* no write buffer data needed/used */
79} cvmx_add_win_dma_dec_t;
80
81/*
82 * Physical Address Decode
83 *
84 * Octeon-I HW never interprets this X (<39:36> reserved
85 * for future expansion), software should set to 0.
86 *
87 * - 0x0 XXX0 0000 0000 to DRAM Cached
88 * - 0x0 XXX0 0FFF FFFF
89 *
90 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
91 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
92 *
93 * - 0x0 XXX0 2000 0000 to DRAM Cached
94 * - 0x0 XXXF FFFF FFFF
95 *
96 * - 0x1 00X0 0000 0000 to Boot Bus Uncached
97 * - 0x1 00XF FFFF FFFF
98 *
99 * - 0x1 01X0 0000 0000 to Other NCB Uncached
100 * - 0x1 FFXF FFFF FFFF devices
101 *
102 * Decode of all Octeon addresses
103 */
104typedef union {
105
106 uint64_t u64;
107 /* mapped or unmapped virtual address */
108 struct {
109 uint64_t R:2;
110 uint64_t offset:62;
111 } sva;
112
113 /* mapped USEG virtual addresses (typically) */
114 struct {
115 uint64_t zeroes:33;
116 uint64_t offset:31;
117 } suseg;
118
119 /* mapped or unmapped virtual address */
120 struct {
121 uint64_t ones:33;
122 uint64_t sp:2;
123 uint64_t offset:29;
124 } sxkseg;
125
126 /*
127 * physical address accessed through xkphys unmapped virtual
128 * address.
129 */
130 struct {
131 uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
132 uint64_t cca:3; /* ignored by octeon */
133 uint64_t mbz:10;
134 uint64_t pa:49; /* physical address */
135 } sxkphys;
136
137 /* physical address */
138 struct {
139 uint64_t mbz:15;
140 /* if set, the address is uncached and resides on MCB bus */
141 uint64_t is_io:1;
142 /*
143 * the hardware ignores this field when is_io==0, else
144 * device ID.
145 */
146 uint64_t did:8;
147 /* the hardware ignores <39:36> in Octeon I */
148 uint64_t unaddr:4;
149 uint64_t offset:36;
150 } sphys;
151
152 /* physical mem address */
153 struct {
154 /* techically, <47:40> are dont-cares */
155 uint64_t zeroes:24;
156 /* the hardware ignores <39:36> in Octeon I */
157 uint64_t unaddr:4;
158 uint64_t offset:36;
159 } smem;
160
161 /* physical IO address */
162 struct {
163 uint64_t mem_region:2;
164 uint64_t mbz:13;
165 /* 1 in this case */
166 uint64_t is_io:1;
167 /*
168 * The hardware ignores this field when is_io==0, else
169 * device ID.
170 */
171 uint64_t did:8;
172 /* the hardware ignores <39:36> in Octeon I */
173 uint64_t unaddr:4;
174 uint64_t offset:36;
175 } sio;
176
177 /*
178 * Scratchpad virtual address - accessed through a window at
179 * the end of kseg3
180 */
181 struct {
182 uint64_t ones:49;
183 /* CVMX_ADD_WIN_SCR (0) in this case */
184 cvmx_add_win_dec_t csrdec:2;
185 uint64_t addr:13;
186 } sscr;
187
188 /* there should only be stores to IOBDMA space, no loads */
189 /*
190 * IOBDMA virtual address - accessed through a window at the
191 * end of kseg3
192 */
193 struct {
194 uint64_t ones:49;
195 uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */
196 uint64_t unused2:3;
197 uint64_t type:3;
198 uint64_t addr:7;
199 } sdma;
200
201 struct {
202 uint64_t didspace:24;
203 uint64_t unused:40;
204 } sfilldidspace;
205
206} cvmx_addr_t;
207
208/* These macros for used by 32 bit applications */
209
210#define CVMX_MIPS32_SPACE_KSEG0 1l
211#define CVMX_ADD_SEG32(segment, add) \
212 (((int32_t)segment << 31) | (int32_t)(add))
213
214/*
215 * Currently all IOs are performed using XKPHYS addressing. Linux uses
216 * the CvmMemCtl register to enable XKPHYS addressing to IO space from
217 * user mode. Future OSes may need to change the upper bits of IO
218 * addresses. The following define controls the upper two bits for all
219 * IO addresses generated by the simple executive library.
220 */
221#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
222
223/* These macros simplify the process of creating common IO addresses */
224#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
225#ifndef CVMX_ADD_IO_SEG
226#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
227#endif
228#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
229#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
230#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
231
232 /* from include/ncb_rsl_id.v */
233#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
234#define CVMX_OCT_DID_GMX0 1ULL
235#define CVMX_OCT_DID_GMX1 2ULL
236#define CVMX_OCT_DID_PCI 3ULL
237#define CVMX_OCT_DID_KEY 4ULL
238#define CVMX_OCT_DID_FPA 5ULL
239#define CVMX_OCT_DID_DFA 6ULL
240#define CVMX_OCT_DID_ZIP 7ULL
241#define CVMX_OCT_DID_RNG 8ULL
242#define CVMX_OCT_DID_IPD 9ULL
243#define CVMX_OCT_DID_PKT 10ULL
244#define CVMX_OCT_DID_TIM 11ULL
245#define CVMX_OCT_DID_TAG 12ULL
246 /* the rest are not on the IO bus */
247#define CVMX_OCT_DID_L2C 16ULL
248#define CVMX_OCT_DID_LMC 17ULL
249#define CVMX_OCT_DID_SPX0 18ULL
250#define CVMX_OCT_DID_SPX1 19ULL
251#define CVMX_OCT_DID_PIP 20ULL
252#define CVMX_OCT_DID_ASX0 22ULL
253#define CVMX_OCT_DID_ASX1 23ULL
254#define CVMX_OCT_DID_IOB 30ULL
255
256#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
257#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
258#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
259#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
260#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
261#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
262#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
263#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
264#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
265#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
266#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
267#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
268#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
269#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
270#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
271#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
272#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
273
274#endif /* __CVMX_ADDRESS_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
new file mode 100644
index 00000000000..91415a85e8d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
@@ -0,0 +1,475 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_ASXX_DEFS_H__
29#define __CVMX_ASXX_DEFS_H__
30
31#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull))
33#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull))
35#define CVMX_ASXX_INT_EN(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_ASXX_INT_REG(block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull))
41#define CVMX_ASXX_PRT_LOOP(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_ASXX_RLD_BYPASS(block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_ASXX_RLD_COMP(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_ASXX_RLD_DATA_DRV(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_ASXX_RLD_SETTING(block_id) \
62 CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull))
63#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
65#define CVMX_ASXX_RX_PRT_EN(block_id) \
66 CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull))
67#define CVMX_ASXX_RX_WOL(block_id) \
68 CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull))
69#define CVMX_ASXX_RX_WOL_MSK(block_id) \
70 CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull))
71#define CVMX_ASXX_RX_WOL_POWOK(block_id) \
72 CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull))
73#define CVMX_ASXX_RX_WOL_SIG(block_id) \
74 CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull))
75#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
76 CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
77#define CVMX_ASXX_TX_COMP_BYP(block_id) \
78 CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull))
79#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
80 CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
81#define CVMX_ASXX_TX_PRT_EN(block_id) \
82 CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull))
83
84union cvmx_asxx_gmii_rx_clk_set {
85 uint64_t u64;
86 struct cvmx_asxx_gmii_rx_clk_set_s {
87 uint64_t reserved_5_63:59;
88 uint64_t setting:5;
89 } s;
90 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
91 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
92 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
93};
94
95union cvmx_asxx_gmii_rx_dat_set {
96 uint64_t u64;
97 struct cvmx_asxx_gmii_rx_dat_set_s {
98 uint64_t reserved_5_63:59;
99 uint64_t setting:5;
100 } s;
101 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
102 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
103 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
104};
105
106union cvmx_asxx_int_en {
107 uint64_t u64;
108 struct cvmx_asxx_int_en_s {
109 uint64_t reserved_12_63:52;
110 uint64_t txpsh:4;
111 uint64_t txpop:4;
112 uint64_t ovrflw:4;
113 } s;
114 struct cvmx_asxx_int_en_cn30xx {
115 uint64_t reserved_11_63:53;
116 uint64_t txpsh:3;
117 uint64_t reserved_7_7:1;
118 uint64_t txpop:3;
119 uint64_t reserved_3_3:1;
120 uint64_t ovrflw:3;
121 } cn30xx;
122 struct cvmx_asxx_int_en_cn30xx cn31xx;
123 struct cvmx_asxx_int_en_s cn38xx;
124 struct cvmx_asxx_int_en_s cn38xxp2;
125 struct cvmx_asxx_int_en_cn30xx cn50xx;
126 struct cvmx_asxx_int_en_s cn58xx;
127 struct cvmx_asxx_int_en_s cn58xxp1;
128};
129
130union cvmx_asxx_int_reg {
131 uint64_t u64;
132 struct cvmx_asxx_int_reg_s {
133 uint64_t reserved_12_63:52;
134 uint64_t txpsh:4;
135 uint64_t txpop:4;
136 uint64_t ovrflw:4;
137 } s;
138 struct cvmx_asxx_int_reg_cn30xx {
139 uint64_t reserved_11_63:53;
140 uint64_t txpsh:3;
141 uint64_t reserved_7_7:1;
142 uint64_t txpop:3;
143 uint64_t reserved_3_3:1;
144 uint64_t ovrflw:3;
145 } cn30xx;
146 struct cvmx_asxx_int_reg_cn30xx cn31xx;
147 struct cvmx_asxx_int_reg_s cn38xx;
148 struct cvmx_asxx_int_reg_s cn38xxp2;
149 struct cvmx_asxx_int_reg_cn30xx cn50xx;
150 struct cvmx_asxx_int_reg_s cn58xx;
151 struct cvmx_asxx_int_reg_s cn58xxp1;
152};
153
154union cvmx_asxx_mii_rx_dat_set {
155 uint64_t u64;
156 struct cvmx_asxx_mii_rx_dat_set_s {
157 uint64_t reserved_5_63:59;
158 uint64_t setting:5;
159 } s;
160 struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
161 struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
162};
163
164union cvmx_asxx_prt_loop {
165 uint64_t u64;
166 struct cvmx_asxx_prt_loop_s {
167 uint64_t reserved_8_63:56;
168 uint64_t ext_loop:4;
169 uint64_t int_loop:4;
170 } s;
171 struct cvmx_asxx_prt_loop_cn30xx {
172 uint64_t reserved_7_63:57;
173 uint64_t ext_loop:3;
174 uint64_t reserved_3_3:1;
175 uint64_t int_loop:3;
176 } cn30xx;
177 struct cvmx_asxx_prt_loop_cn30xx cn31xx;
178 struct cvmx_asxx_prt_loop_s cn38xx;
179 struct cvmx_asxx_prt_loop_s cn38xxp2;
180 struct cvmx_asxx_prt_loop_cn30xx cn50xx;
181 struct cvmx_asxx_prt_loop_s cn58xx;
182 struct cvmx_asxx_prt_loop_s cn58xxp1;
183};
184
185union cvmx_asxx_rld_bypass {
186 uint64_t u64;
187 struct cvmx_asxx_rld_bypass_s {
188 uint64_t reserved_1_63:63;
189 uint64_t bypass:1;
190 } s;
191 struct cvmx_asxx_rld_bypass_s cn38xx;
192 struct cvmx_asxx_rld_bypass_s cn38xxp2;
193 struct cvmx_asxx_rld_bypass_s cn58xx;
194 struct cvmx_asxx_rld_bypass_s cn58xxp1;
195};
196
197union cvmx_asxx_rld_bypass_setting {
198 uint64_t u64;
199 struct cvmx_asxx_rld_bypass_setting_s {
200 uint64_t reserved_5_63:59;
201 uint64_t setting:5;
202 } s;
203 struct cvmx_asxx_rld_bypass_setting_s cn38xx;
204 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
205 struct cvmx_asxx_rld_bypass_setting_s cn58xx;
206 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
207};
208
209union cvmx_asxx_rld_comp {
210 uint64_t u64;
211 struct cvmx_asxx_rld_comp_s {
212 uint64_t reserved_9_63:55;
213 uint64_t pctl:5;
214 uint64_t nctl:4;
215 } s;
216 struct cvmx_asxx_rld_comp_cn38xx {
217 uint64_t reserved_8_63:56;
218 uint64_t pctl:4;
219 uint64_t nctl:4;
220 } cn38xx;
221 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
222 struct cvmx_asxx_rld_comp_s cn58xx;
223 struct cvmx_asxx_rld_comp_s cn58xxp1;
224};
225
226union cvmx_asxx_rld_data_drv {
227 uint64_t u64;
228 struct cvmx_asxx_rld_data_drv_s {
229 uint64_t reserved_8_63:56;
230 uint64_t pctl:4;
231 uint64_t nctl:4;
232 } s;
233 struct cvmx_asxx_rld_data_drv_s cn38xx;
234 struct cvmx_asxx_rld_data_drv_s cn38xxp2;
235 struct cvmx_asxx_rld_data_drv_s cn58xx;
236 struct cvmx_asxx_rld_data_drv_s cn58xxp1;
237};
238
239union cvmx_asxx_rld_fcram_mode {
240 uint64_t u64;
241 struct cvmx_asxx_rld_fcram_mode_s {
242 uint64_t reserved_1_63:63;
243 uint64_t mode:1;
244 } s;
245 struct cvmx_asxx_rld_fcram_mode_s cn38xx;
246 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
247};
248
249union cvmx_asxx_rld_nctl_strong {
250 uint64_t u64;
251 struct cvmx_asxx_rld_nctl_strong_s {
252 uint64_t reserved_5_63:59;
253 uint64_t nctl:5;
254 } s;
255 struct cvmx_asxx_rld_nctl_strong_s cn38xx;
256 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
257 struct cvmx_asxx_rld_nctl_strong_s cn58xx;
258 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
259};
260
261union cvmx_asxx_rld_nctl_weak {
262 uint64_t u64;
263 struct cvmx_asxx_rld_nctl_weak_s {
264 uint64_t reserved_5_63:59;
265 uint64_t nctl:5;
266 } s;
267 struct cvmx_asxx_rld_nctl_weak_s cn38xx;
268 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
269 struct cvmx_asxx_rld_nctl_weak_s cn58xx;
270 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
271};
272
273union cvmx_asxx_rld_pctl_strong {
274 uint64_t u64;
275 struct cvmx_asxx_rld_pctl_strong_s {
276 uint64_t reserved_5_63:59;
277 uint64_t pctl:5;
278 } s;
279 struct cvmx_asxx_rld_pctl_strong_s cn38xx;
280 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
281 struct cvmx_asxx_rld_pctl_strong_s cn58xx;
282 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
283};
284
285union cvmx_asxx_rld_pctl_weak {
286 uint64_t u64;
287 struct cvmx_asxx_rld_pctl_weak_s {
288 uint64_t reserved_5_63:59;
289 uint64_t pctl:5;
290 } s;
291 struct cvmx_asxx_rld_pctl_weak_s cn38xx;
292 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
293 struct cvmx_asxx_rld_pctl_weak_s cn58xx;
294 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
295};
296
297union cvmx_asxx_rld_setting {
298 uint64_t u64;
299 struct cvmx_asxx_rld_setting_s {
300 uint64_t reserved_13_63:51;
301 uint64_t dfaset:5;
302 uint64_t dfalag:1;
303 uint64_t dfalead:1;
304 uint64_t dfalock:1;
305 uint64_t setting:5;
306 } s;
307 struct cvmx_asxx_rld_setting_cn38xx {
308 uint64_t reserved_5_63:59;
309 uint64_t setting:5;
310 } cn38xx;
311 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
312 struct cvmx_asxx_rld_setting_s cn58xx;
313 struct cvmx_asxx_rld_setting_s cn58xxp1;
314};
315
316union cvmx_asxx_rx_clk_setx {
317 uint64_t u64;
318 struct cvmx_asxx_rx_clk_setx_s {
319 uint64_t reserved_5_63:59;
320 uint64_t setting:5;
321 } s;
322 struct cvmx_asxx_rx_clk_setx_s cn30xx;
323 struct cvmx_asxx_rx_clk_setx_s cn31xx;
324 struct cvmx_asxx_rx_clk_setx_s cn38xx;
325 struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
326 struct cvmx_asxx_rx_clk_setx_s cn50xx;
327 struct cvmx_asxx_rx_clk_setx_s cn58xx;
328 struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
329};
330
331union cvmx_asxx_rx_prt_en {
332 uint64_t u64;
333 struct cvmx_asxx_rx_prt_en_s {
334 uint64_t reserved_4_63:60;
335 uint64_t prt_en:4;
336 } s;
337 struct cvmx_asxx_rx_prt_en_cn30xx {
338 uint64_t reserved_3_63:61;
339 uint64_t prt_en:3;
340 } cn30xx;
341 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
342 struct cvmx_asxx_rx_prt_en_s cn38xx;
343 struct cvmx_asxx_rx_prt_en_s cn38xxp2;
344 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
345 struct cvmx_asxx_rx_prt_en_s cn58xx;
346 struct cvmx_asxx_rx_prt_en_s cn58xxp1;
347};
348
349union cvmx_asxx_rx_wol {
350 uint64_t u64;
351 struct cvmx_asxx_rx_wol_s {
352 uint64_t reserved_2_63:62;
353 uint64_t status:1;
354 uint64_t enable:1;
355 } s;
356 struct cvmx_asxx_rx_wol_s cn38xx;
357 struct cvmx_asxx_rx_wol_s cn38xxp2;
358};
359
360union cvmx_asxx_rx_wol_msk {
361 uint64_t u64;
362 struct cvmx_asxx_rx_wol_msk_s {
363 uint64_t msk:64;
364 } s;
365 struct cvmx_asxx_rx_wol_msk_s cn38xx;
366 struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
367};
368
369union cvmx_asxx_rx_wol_powok {
370 uint64_t u64;
371 struct cvmx_asxx_rx_wol_powok_s {
372 uint64_t reserved_1_63:63;
373 uint64_t powerok:1;
374 } s;
375 struct cvmx_asxx_rx_wol_powok_s cn38xx;
376 struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
377};
378
379union cvmx_asxx_rx_wol_sig {
380 uint64_t u64;
381 struct cvmx_asxx_rx_wol_sig_s {
382 uint64_t reserved_32_63:32;
383 uint64_t sig:32;
384 } s;
385 struct cvmx_asxx_rx_wol_sig_s cn38xx;
386 struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
387};
388
389union cvmx_asxx_tx_clk_setx {
390 uint64_t u64;
391 struct cvmx_asxx_tx_clk_setx_s {
392 uint64_t reserved_5_63:59;
393 uint64_t setting:5;
394 } s;
395 struct cvmx_asxx_tx_clk_setx_s cn30xx;
396 struct cvmx_asxx_tx_clk_setx_s cn31xx;
397 struct cvmx_asxx_tx_clk_setx_s cn38xx;
398 struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
399 struct cvmx_asxx_tx_clk_setx_s cn50xx;
400 struct cvmx_asxx_tx_clk_setx_s cn58xx;
401 struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
402};
403
404union cvmx_asxx_tx_comp_byp {
405 uint64_t u64;
406 struct cvmx_asxx_tx_comp_byp_s {
407 uint64_t reserved_0_63:64;
408 } s;
409 struct cvmx_asxx_tx_comp_byp_cn30xx {
410 uint64_t reserved_9_63:55;
411 uint64_t bypass:1;
412 uint64_t pctl:4;
413 uint64_t nctl:4;
414 } cn30xx;
415 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
416 struct cvmx_asxx_tx_comp_byp_cn38xx {
417 uint64_t reserved_8_63:56;
418 uint64_t pctl:4;
419 uint64_t nctl:4;
420 } cn38xx;
421 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
422 struct cvmx_asxx_tx_comp_byp_cn50xx {
423 uint64_t reserved_17_63:47;
424 uint64_t bypass:1;
425 uint64_t reserved_13_15:3;
426 uint64_t pctl:5;
427 uint64_t reserved_5_7:3;
428 uint64_t nctl:5;
429 } cn50xx;
430 struct cvmx_asxx_tx_comp_byp_cn58xx {
431 uint64_t reserved_13_63:51;
432 uint64_t pctl:5;
433 uint64_t reserved_5_7:3;
434 uint64_t nctl:5;
435 } cn58xx;
436 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
437};
438
439union cvmx_asxx_tx_hi_waterx {
440 uint64_t u64;
441 struct cvmx_asxx_tx_hi_waterx_s {
442 uint64_t reserved_4_63:60;
443 uint64_t mark:4;
444 } s;
445 struct cvmx_asxx_tx_hi_waterx_cn30xx {
446 uint64_t reserved_3_63:61;
447 uint64_t mark:3;
448 } cn30xx;
449 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
450 struct cvmx_asxx_tx_hi_waterx_s cn38xx;
451 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
452 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
453 struct cvmx_asxx_tx_hi_waterx_s cn58xx;
454 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
455};
456
457union cvmx_asxx_tx_prt_en {
458 uint64_t u64;
459 struct cvmx_asxx_tx_prt_en_s {
460 uint64_t reserved_4_63:60;
461 uint64_t prt_en:4;
462 } s;
463 struct cvmx_asxx_tx_prt_en_cn30xx {
464 uint64_t reserved_3_63:61;
465 uint64_t prt_en:3;
466 } cn30xx;
467 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
468 struct cvmx_asxx_tx_prt_en_s cn38xx;
469 struct cvmx_asxx_tx_prt_en_s cn38xxp2;
470 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
471 struct cvmx_asxx_tx_prt_en_s cn58xx;
472 struct cvmx_asxx_tx_prt_en_s cn58xxp1;
473};
474
475#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 4e4c3a8282d..1db1dc2724c 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -39,7 +39,7 @@
39 * versions. 39 * versions.
40 */ 40 */
41#define CVMX_BOOTINFO_MAJ_VER 1 41#define CVMX_BOOTINFO_MAJ_VER 1
42#define CVMX_BOOTINFO_MIN_VER 2 42#define CVMX_BOOTINFO_MIN_VER 3
43 43
44#if (CVMX_BOOTINFO_MAJ_VER == 1) 44#if (CVMX_BOOTINFO_MAJ_VER == 1)
45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20 45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
@@ -116,7 +116,13 @@ struct cvmx_bootinfo {
116 */ 116 */
117 uint32_t config_flags; 117 uint32_t config_flags;
118#endif 118#endif
119 119#if (CVMX_BOOTINFO_MIN_VER >= 3)
120 /*
121 * Address of the OF Flattened Device Tree structure
122 * describing the board.
123 */
124 uint64_t fdt_addr;
125#endif
120}; 126};
121 127
122#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) 128#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
@@ -164,6 +170,22 @@ enum cvmx_board_types_enum {
164 /* Special 'generic' board type, supports many boards */ 170 /* Special 'generic' board type, supports many boards */
165 CVMX_BOARD_TYPE_GENERIC = 28, 171 CVMX_BOARD_TYPE_GENERIC = 28,
166 CVMX_BOARD_TYPE_EBH5610 = 29, 172 CVMX_BOARD_TYPE_EBH5610 = 29,
173 CVMX_BOARD_TYPE_LANAI2_A = 30,
174 CVMX_BOARD_TYPE_LANAI2_U = 31,
175 CVMX_BOARD_TYPE_EBB5600 = 32,
176 CVMX_BOARD_TYPE_EBB6300 = 33,
177 CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
178 CVMX_BOARD_TYPE_LANAI2_G = 35,
179 CVMX_BOARD_TYPE_EBT5810 = 36,
180 CVMX_BOARD_TYPE_NIC10E = 37,
181 CVMX_BOARD_TYPE_EP6300C = 38,
182 CVMX_BOARD_TYPE_EBB6800 = 39,
183 CVMX_BOARD_TYPE_NIC4E = 40,
184 CVMX_BOARD_TYPE_NIC2E = 41,
185 CVMX_BOARD_TYPE_EBB6600 = 42,
186 CVMX_BOARD_TYPE_REDWING = 43,
187 CVMX_BOARD_TYPE_NIC68_4 = 44,
188 CVMX_BOARD_TYPE_NIC10E_66 = 45,
167 CVMX_BOARD_TYPE_MAX, 189 CVMX_BOARD_TYPE_MAX,
168 190
169 /* 191 /*
@@ -181,6 +203,23 @@ enum cvmx_board_types_enum {
181 CVMX_BOARD_TYPE_CUST_NS0216 = 10002, 203 CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
182 CVMX_BOARD_TYPE_CUST_NB5 = 10003, 204 CVMX_BOARD_TYPE_CUST_NB5 = 10003,
183 CVMX_BOARD_TYPE_CUST_WMR500 = 10004, 205 CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
206 CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
207 CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
208 CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
209 CVMX_BOARD_TYPE_CUST_GST104 = 10008,
210 CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
211 CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
212 CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
213 CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
214 CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
215 CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
216 CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
217 CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
218 CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
219 CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
220 CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
221 CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
222 CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
184 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, 223 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
185 224
186 /* 225 /*
@@ -241,6 +280,22 @@ static inline const char *cvmx_board_type_to_string(enum
241 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200) 280 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC) 281 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610) 282 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
283 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
284 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
285 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
286 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
287 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
288 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
289 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
290 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
291 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
292 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
293 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
294 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
295 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
296 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
297 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
298 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
244 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) 299 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
245 300
246 /* Customer boards listed here */ 301 /* Customer boards listed here */
@@ -249,6 +304,23 @@ static inline const char *cvmx_board_type_to_string(enum
249 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216) 304 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
250 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5) 305 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
251 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500) 306 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
307 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
308 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
309 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
310 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
311 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
312 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
313 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
314 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
315 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
316 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
317 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
318 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
319 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
320 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
321 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
322 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
323 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
252 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX) 324 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
253 325
254 /* Customer private range */ 326 /* Customer private range */
@@ -265,9 +337,9 @@ static inline const char *cvmx_chip_type_to_string(enum
265{ 337{
266 switch (type) { 338 switch (type) {
267 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL) 339 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
268 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED) 340 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
269 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE) 341 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
270 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX) 342 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
271 } 343 }
272 return "Unsupported Chip"; 344 return "Unsupported Chip";
273} 345}
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
new file mode 100644
index 00000000000..614653b686a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -0,0 +1,617 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Support functions for managing command queues used for
31 * various hardware blocks.
32 *
33 * The common command queue infrastructure abstracts out the
34 * software necessary for adding to Octeon's chained queue
35 * structures. These structures are used for commands to the
36 * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each
37 * hardware unit takes commands and CSRs of different types,
38 * they all use basic linked command buffers to store the
39 * pending request. In general, users of the CVMX API don't
40 * call cvmx-cmd-queue functions directly. Instead the hardware
41 * unit specific wrapper should be used. The wrappers perform
42 * unit specific validation and CSR writes to submit the
43 * commands.
44 *
45 * Even though most software will never directly interact with
46 * cvmx-cmd-queue, knowledge of its internal working can help
47 * in diagnosing performance problems and help with debugging.
48 *
49 * Command queue pointers are stored in a global named block
50 * called "cvmx_cmd_queues". Except for the PKO queues, each
51 * hardware queue is stored in its own cache line to reduce SMP
52 * contention on spin locks. The PKO queues are stored such that
53 * every 16th queue is next to each other in memory. This scheme
54 * allows for queues being in separate cache lines when there
55 * are low number of queues per port. With 16 queues per port,
56 * the first queue for each port is in the same cache area. The
57 * second queues for each port are in another area, etc. This
58 * allows software to implement very efficient lockless PKO with
59 * 16 queues per port using a minimum of cache lines per core.
60 * All queues for a given core will be isolated in the same
61 * cache area.
62 *
63 * In addition to the memory pointer layout, cvmx-cmd-queue
64 * provides an optimized fair ll/sc locking mechanism for the
65 * queues. The lock uses a "ticket / now serving" model to
66 * maintain fair order on contended locks. In addition, it uses
67 * predicted locking time to limit cache contention. When a core
68 * know it must wait in line for a lock, it spins on the
69 * internal cycle counter to completely eliminate any causes of
70 * bus traffic.
71 *
72 */
73
74#ifndef __CVMX_CMD_QUEUE_H__
75#define __CVMX_CMD_QUEUE_H__
76
77#include <linux/prefetch.h>
78
79#include "cvmx-fpa.h"
80/**
81 * By default we disable the max depth support. Most programs
82 * don't use it and it slows down the command queue processing
83 * significantly.
84 */
85#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
86#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
87#endif
88
89/**
90 * Enumeration representing all hardware blocks that use command
91 * queues. Each hardware block has up to 65536 sub identifiers for
92 * multiple command queues. Not all chips support all hardware
93 * units.
94 */
95typedef enum {
96 CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
97
98#define CVMX_CMD_QUEUE_PKO(queue) \
99 ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
100
101 CVMX_CMD_QUEUE_ZIP = 0x10000,
102 CVMX_CMD_QUEUE_DFA = 0x20000,
103 CVMX_CMD_QUEUE_RAID = 0x30000,
104 CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
105
106#define CVMX_CMD_QUEUE_DMA(queue) \
107 ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue))))
108
109 CVMX_CMD_QUEUE_END = 0x50000,
110} cvmx_cmd_queue_id_t;
111
112/**
113 * Command write operations can fail if the command queue needs
114 * a new buffer and the associated FPA pool is empty. It can also
115 * fail if the number of queued command words reaches the maximum
116 * set at initialization.
117 */
118typedef enum {
119 CVMX_CMD_QUEUE_SUCCESS = 0,
120 CVMX_CMD_QUEUE_NO_MEMORY = -1,
121 CVMX_CMD_QUEUE_FULL = -2,
122 CVMX_CMD_QUEUE_INVALID_PARAM = -3,
123 CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
124} cvmx_cmd_queue_result_t;
125
126typedef struct {
127 /* You have lock when this is your ticket */
128 uint8_t now_serving;
129 uint64_t unused1:24;
130 /* Maximum outstanding command words */
131 uint32_t max_depth;
132 /* FPA pool buffers come from */
133 uint64_t fpa_pool:3;
134 /* Top of command buffer pointer shifted 7 */
135 uint64_t base_ptr_div128:29;
136 uint64_t unused2:6;
137 /* FPA buffer size in 64bit words minus 1 */
138 uint64_t pool_size_m1:13;
139 /* Number of commands already used in buffer */
140 uint64_t index:13;
141} __cvmx_cmd_queue_state_t;
142
143/**
144 * This structure contains the global state of all command queues.
145 * It is stored in a bootmem named block and shared by all
146 * applications running on Octeon. Tickets are stored in a differnet
147 * cahce line that queue information to reduce the contention on the
148 * ll/sc used to get a ticket. If this is not the case, the update
149 * of queue state causes the ll/sc to fail quite often.
150 */
151typedef struct {
152 uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256];
153 __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256];
154} __cvmx_cmd_queue_all_state_t;
155
156/**
157 * Initialize a command queue for use. The initial FPA buffer is
158 * allocated and the hardware unit is configured to point to the
159 * new command queue.
160 *
161 * @queue_id: Hardware command queue to initialize.
162 * @max_depth: Maximum outstanding commands that can be queued.
163 * @fpa_pool: FPA pool the command queues should come from.
164 * @pool_size: Size of each buffer in the FPA pool (bytes)
165 *
166 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
167 */
168cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
169 int max_depth, int fpa_pool,
170 int pool_size);
171
172/**
173 * Shutdown a queue a free it's command buffers to the FPA. The
174 * hardware connected to the queue must be stopped before this
175 * function is called.
176 *
177 * @queue_id: Queue to shutdown
178 *
179 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
180 */
181cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
182
183/**
184 * Return the number of command words pending in the queue. This
185 * function may be relatively slow for some hardware units.
186 *
187 * @queue_id: Hardware command queue to query
188 *
189 * Returns Number of outstanding commands
190 */
191int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
192
193/**
194 * Return the command buffer to be written to. The purpose of this
195 * function is to allow CVMX routine access t othe low level buffer
196 * for initial hardware setup. User applications should not call this
197 * function directly.
198 *
199 * @queue_id: Command queue to query
200 *
201 * Returns Command buffer or NULL on failure
202 */
203void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
204
205/**
206 * Get the index into the state arrays for the supplied queue id.
207 *
208 * @queue_id: Queue ID to get an index for
209 *
210 * Returns Index into the state arrays
211 */
212static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
213{
214 /*
215 * Warning: This code currently only works with devices that
216 * have 256 queues or less. Devices with more than 16 queues
217 * are laid out in memory to allow cores quick access to
218 * every 16th queue. This reduces cache thrashing when you are
219 * running 16 queues per port to support lockless operation.
220 */
221 int unit = queue_id >> 16;
222 int q = (queue_id >> 4) & 0xf;
223 int core = queue_id & 0xf;
224 return unit * 256 + core * 16 + q;
225}
226
227/**
228 * Lock the supplied queue so nobody else is updating it at the same
229 * time as us.
230 *
231 * @queue_id: Queue ID to lock
232 * @qptr: Pointer to the queue's global state
233 */
234static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
235 __cvmx_cmd_queue_state_t *qptr)
236{
237 extern __cvmx_cmd_queue_all_state_t
238 *__cvmx_cmd_queue_state_ptr;
239 int tmp;
240 int my_ticket;
241 prefetch(qptr);
242 asm volatile (
243 ".set push\n"
244 ".set noreorder\n"
245 "1:\n"
246 /* Atomic add one to ticket_ptr */
247 "ll %[my_ticket], %[ticket_ptr]\n"
248 /* and store the original value */
249 "li %[ticket], 1\n"
250 /* in my_ticket */
251 "baddu %[ticket], %[my_ticket]\n"
252 "sc %[ticket], %[ticket_ptr]\n"
253 "beqz %[ticket], 1b\n"
254 " nop\n"
255 /* Load the current now_serving ticket */
256 "lbu %[ticket], %[now_serving]\n"
257 "2:\n"
258 /* Jump out if now_serving == my_ticket */
259 "beq %[ticket], %[my_ticket], 4f\n"
260 /* Find out how many tickets are in front of me */
261 " subu %[ticket], %[my_ticket], %[ticket]\n"
262 /* Use tickets in front of me minus one to delay */
263 "subu %[ticket], 1\n"
264 /* Delay will be ((tickets in front)-1)*32 loops */
265 "cins %[ticket], %[ticket], 5, 7\n"
266 "3:\n"
267 /* Loop here until our ticket might be up */
268 "bnez %[ticket], 3b\n"
269 " subu %[ticket], 1\n"
270 /* Jump back up to check out ticket again */
271 "b 2b\n"
272 /* Load the current now_serving ticket */
273 " lbu %[ticket], %[now_serving]\n"
274 "4:\n"
275 ".set pop\n" :
276 [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
277 [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
278 [my_ticket] "=r"(my_ticket)
279 );
280}
281
282/**
283 * Unlock the queue, flushing all writes.
284 *
285 * @qptr: Queue to unlock
286 */
287static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
288{
289 qptr->now_serving++;
290 CVMX_SYNCWS;
291}
292
293/**
294 * Get the queue state structure for the given queue id
295 *
296 * @queue_id: Queue id to get
297 *
298 * Returns Queue structure or NULL on failure
299 */
300static inline __cvmx_cmd_queue_state_t
301 *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
302{
303 extern __cvmx_cmd_queue_all_state_t
304 *__cvmx_cmd_queue_state_ptr;
305 return &__cvmx_cmd_queue_state_ptr->
306 state[__cvmx_cmd_queue_get_index(queue_id)];
307}
308
309/**
310 * Write an arbitrary number of command words to a command queue.
311 * This is a generic function; the fixed number of command word
312 * functions yield higher performance.
313 *
314 * @queue_id: Hardware command queue to write to
315 * @use_locking:
316 * Use internal locking to ensure exclusive access for queue
317 * updates. If you don't use this locking you must ensure
318 * exclusivity some other way. Locking is strongly recommended.
319 * @cmd_count: Number of command words to write
320 * @cmds: Array of commands to write
321 *
322 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
323 */
324static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t
325 queue_id,
326 int use_locking,
327 int cmd_count,
328 uint64_t *cmds)
329{
330 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
331
332 /* Make sure nobody else is updating the same queue */
333 if (likely(use_locking))
334 __cvmx_cmd_queue_lock(queue_id, qptr);
335
336 /*
337 * If a max queue length was specified then make sure we don't
338 * exceed it. If any part of the command would be below the
339 * limit we allow it.
340 */
341 if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
342 if (unlikely
343 (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
344 if (likely(use_locking))
345 __cvmx_cmd_queue_unlock(qptr);
346 return CVMX_CMD_QUEUE_FULL;
347 }
348 }
349
350 /*
351 * Normally there is plenty of room in the current buffer for
352 * the command.
353 */
354 if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) {
355 uint64_t *ptr =
356 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
357 base_ptr_div128 << 7);
358 ptr += qptr->index;
359 qptr->index += cmd_count;
360 while (cmd_count--)
361 *ptr++ = *cmds++;
362 } else {
363 uint64_t *ptr;
364 int count;
365 /*
366 * We need a new command buffer. Fail if there isn't
367 * one available.
368 */
369 uint64_t *new_buffer =
370 (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
371 if (unlikely(new_buffer == NULL)) {
372 if (likely(use_locking))
373 __cvmx_cmd_queue_unlock(qptr);
374 return CVMX_CMD_QUEUE_NO_MEMORY;
375 }
376 ptr =
377 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
378 base_ptr_div128 << 7);
379 /*
380 * Figure out how many command words will fit in this
381 * buffer. One location will be needed for the next
382 * buffer pointer.
383 */
384 count = qptr->pool_size_m1 - qptr->index;
385 ptr += qptr->index;
386 cmd_count -= count;
387 while (count--)
388 *ptr++ = *cmds++;
389 *ptr = cvmx_ptr_to_phys(new_buffer);
390 /*
391 * The current buffer is full and has a link to the
392 * next buffer. Time to write the rest of the commands
393 * into the new buffer.
394 */
395 qptr->base_ptr_div128 = *ptr >> 7;
396 qptr->index = cmd_count;
397 ptr = new_buffer;
398 while (cmd_count--)
399 *ptr++ = *cmds++;
400 }
401
402 /* All updates are complete. Release the lock and return */
403 if (likely(use_locking))
404 __cvmx_cmd_queue_unlock(qptr);
405 return CVMX_CMD_QUEUE_SUCCESS;
406}
407
408/**
409 * Simple function to write two command words to a command
410 * queue.
411 *
412 * @queue_id: Hardware command queue to write to
413 * @use_locking:
414 * Use internal locking to ensure exclusive access for queue
415 * updates. If you don't use this locking you must ensure
416 * exclusivity some other way. Locking is strongly recommended.
417 * @cmd1: Command
418 * @cmd2: Command
419 *
420 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
421 */
422static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t
423 queue_id,
424 int use_locking,
425 uint64_t cmd1,
426 uint64_t cmd2)
427{
428 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
429
430 /* Make sure nobody else is updating the same queue */
431 if (likely(use_locking))
432 __cvmx_cmd_queue_lock(queue_id, qptr);
433
434 /*
435 * If a max queue length was specified then make sure we don't
436 * exceed it. If any part of the command would be below the
437 * limit we allow it.
438 */
439 if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
440 if (unlikely
441 (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
442 if (likely(use_locking))
443 __cvmx_cmd_queue_unlock(qptr);
444 return CVMX_CMD_QUEUE_FULL;
445 }
446 }
447
448 /*
449 * Normally there is plenty of room in the current buffer for
450 * the command.
451 */
452 if (likely(qptr->index + 2 < qptr->pool_size_m1)) {
453 uint64_t *ptr =
454 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
455 base_ptr_div128 << 7);
456 ptr += qptr->index;
457 qptr->index += 2;
458 ptr[0] = cmd1;
459 ptr[1] = cmd2;
460 } else {
461 uint64_t *ptr;
462 /*
463 * Figure out how many command words will fit in this
464 * buffer. One location will be needed for the next
465 * buffer pointer.
466 */
467 int count = qptr->pool_size_m1 - qptr->index;
468 /*
469 * We need a new command buffer. Fail if there isn't
470 * one available.
471 */
472 uint64_t *new_buffer =
473 (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
474 if (unlikely(new_buffer == NULL)) {
475 if (likely(use_locking))
476 __cvmx_cmd_queue_unlock(qptr);
477 return CVMX_CMD_QUEUE_NO_MEMORY;
478 }
479 count--;
480 ptr =
481 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
482 base_ptr_div128 << 7);
483 ptr += qptr->index;
484 *ptr++ = cmd1;
485 if (likely(count))
486 *ptr++ = cmd2;
487 *ptr = cvmx_ptr_to_phys(new_buffer);
488 /*
489 * The current buffer is full and has a link to the
490 * next buffer. Time to write the rest of the commands
491 * into the new buffer.
492 */
493 qptr->base_ptr_div128 = *ptr >> 7;
494 qptr->index = 0;
495 if (unlikely(count == 0)) {
496 qptr->index = 1;
497 new_buffer[0] = cmd2;
498 }
499 }
500
501 /* All updates are complete. Release the lock and return */
502 if (likely(use_locking))
503 __cvmx_cmd_queue_unlock(qptr);
504 return CVMX_CMD_QUEUE_SUCCESS;
505}
506
507/**
508 * Simple function to write three command words to a command
509 * queue.
510 *
511 * @queue_id: Hardware command queue to write to
512 * @use_locking:
513 * Use internal locking to ensure exclusive access for queue
514 * updates. If you don't use this locking you must ensure
515 * exclusivity some other way. Locking is strongly recommended.
516 * @cmd1: Command
517 * @cmd2: Command
518 * @cmd3: Command
519 *
520 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
521 */
522static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t
523 queue_id,
524 int use_locking,
525 uint64_t cmd1,
526 uint64_t cmd2,
527 uint64_t cmd3)
528{
529 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
530
531 /* Make sure nobody else is updating the same queue */
532 if (likely(use_locking))
533 __cvmx_cmd_queue_lock(queue_id, qptr);
534
535 /*
536 * If a max queue length was specified then make sure we don't
537 * exceed it. If any part of the command would be below the
538 * limit we allow it.
539 */
540 if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
541 if (unlikely
542 (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
543 if (likely(use_locking))
544 __cvmx_cmd_queue_unlock(qptr);
545 return CVMX_CMD_QUEUE_FULL;
546 }
547 }
548
549 /*
550 * Normally there is plenty of room in the current buffer for
551 * the command.
552 */
553 if (likely(qptr->index + 3 < qptr->pool_size_m1)) {
554 uint64_t *ptr =
555 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
556 base_ptr_div128 << 7);
557 ptr += qptr->index;
558 qptr->index += 3;
559 ptr[0] = cmd1;
560 ptr[1] = cmd2;
561 ptr[2] = cmd3;
562 } else {
563 uint64_t *ptr;
564 /*
565 * Figure out how many command words will fit in this
566 * buffer. One location will be needed for the next
567 * buffer pointer
568 */
569 int count = qptr->pool_size_m1 - qptr->index;
570 /*
571 * We need a new command buffer. Fail if there isn't
572 * one available
573 */
574 uint64_t *new_buffer =
575 (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
576 if (unlikely(new_buffer == NULL)) {
577 if (likely(use_locking))
578 __cvmx_cmd_queue_unlock(qptr);
579 return CVMX_CMD_QUEUE_NO_MEMORY;
580 }
581 count--;
582 ptr =
583 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
584 base_ptr_div128 << 7);
585 ptr += qptr->index;
586 *ptr++ = cmd1;
587 if (count) {
588 *ptr++ = cmd2;
589 if (count > 1)
590 *ptr++ = cmd3;
591 }
592 *ptr = cvmx_ptr_to_phys(new_buffer);
593 /*
594 * The current buffer is full and has a link to the
595 * next buffer. Time to write the rest of the commands
596 * into the new buffer.
597 */
598 qptr->base_ptr_div128 = *ptr >> 7;
599 qptr->index = 0;
600 ptr = new_buffer;
601 if (count == 0) {
602 *ptr++ = cmd2;
603 qptr->index++;
604 }
605 if (count < 2) {
606 *ptr++ = cmd3;
607 qptr->index++;
608 }
609 }
610
611 /* All updates are complete. Release the lock and return */
612 if (likely(use_locking))
613 __cvmx_cmd_queue_unlock(qptr);
614 return CVMX_CMD_QUEUE_SUCCESS;
615}
616
617#endif /* __CVMX_CMD_QUEUE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h
new file mode 100644
index 00000000000..26835d1b43b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-config.h
@@ -0,0 +1,168 @@
1#ifndef __CVMX_CONFIG_H__
2#define __CVMX_CONFIG_H__
3
4/************************* Config Specific Defines ************************/
5#define CVMX_LLM_NUM_PORTS 1
6#define CVMX_NULL_POINTER_PROTECT 1
7#define CVMX_ENABLE_DEBUG_PRINTS 1
8/* PKO queues per port for interface 0 (ports 0-15) */
9#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
10/* PKO queues per port for interface 1 (ports 16-31) */
11#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
12/* Limit on the number of PKO ports enabled for interface 0 */
13#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
14/* Limit on the number of PKO ports enabled for interface 1 */
15#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
16/* PKO queues per port for PCI (ports 32-35) */
17#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
18/* PKO queues per port for Loop devices (ports 36-39) */
19#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
20
21/************************* FPA allocation *********************************/
22/* Pool sizes in bytes, must be multiple of a cache line */
23#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
24#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
25#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
26#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
27#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
28#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
29#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
30#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
31
32/* Pools in use */
33/* Packet buffers */
34#define CVMX_FPA_PACKET_POOL (0)
35#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
36/* Work queue entrys */
37#define CVMX_FPA_WQE_POOL (1)
38#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
39/* PKO queue command buffers */
40#define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
41#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
42
43/************************* FAU allocation ********************************/
44/* The fetch and add registers are allocated here. They are arranged
45 * in order of descending size so that all alignment constraints are
46 * automatically met. The enums are linked so that the following enum
47 * continues allocating where the previous one left off, so the
48 * numbering within each enum always starts with zero. The macros
49 * take care of the address increment size, so the values entered
50 * always increase by 1. FAU registers are accessed with byte
51 * addresses.
52 */
53
54#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
55typedef enum {
56 CVMX_FAU_REG_64_START = 0,
57 CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0),
58} cvmx_fau_reg_64_t;
59
60#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
61typedef enum {
62 CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END,
63 CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0),
64} cvmx_fau_reg_32_t;
65
66#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
67typedef enum {
68 CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END,
69 CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0),
70} cvmx_fau_reg_16_t;
71
72#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
73typedef enum {
74 CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END,
75 CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0),
76} cvmx_fau_reg_8_t;
77
78/*
79 * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
80 * available FAU address that is not allocated in cvmx-config.h. This
81 * is 64 bit aligned.
82 */
83#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
84#define CVMX_FAU_REG_END (2048)
85
86/********************** scratch memory allocation *************************/
87/* Scratchpad memory allocation. Note that these are byte memory
88 * addresses. Some uses of scratchpad (IOBDMA for example) require
89 * the use of 8-byte aligned addresses, so proper alignment needs to
90 * be taken into account.
91 */
92/* Generic scratch iobdma area */
93#define CVMX_SCR_SCRATCH (0)
94/* First location available after cvmx-config.h allocated region. */
95#define CVMX_SCR_REG_AVAIL_BASE (8)
96
97/*
98 * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
99 * before the beginning of the packet. If necessary, override the
100 * default here. See the IPD section of the hardware manual for MBUFF
101 * SKIP details.
102 */
103#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
104
105/*
106 * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
107 * in each chained packet element. If necessary, override the default
108 * here.
109 */
110#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
111
112/*
113 * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
114 * enabled for all input ports. This controls if IPD sends
115 * backpressure to all ports if Octeon's FPA pools don't have enough
116 * packet or work queue entries. Even when this is off, it is still
117 * possible to get backpressure from individual hardware ports. When
118 * configuring backpressure, also check
119 * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
120 * the default here.
121 */
122#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
123
124/*
125 * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
126 * function. Once it is enabled the hardware starts accepting
127 * packets. You might want to skip the IPD enable if configuration
128 * changes are need from the default helper setup. If necessary,
129 * override the default here.
130 */
131#define CVMX_HELPER_ENABLE_IPD 0
132
133/*
134 * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
135 * to incoming packets.
136 */
137#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
138
139#define CVMX_ENABLE_PARAMETER_CHECKING 0
140
141/*
142 * The following select which fields are used by the PIP to generate
143 * the tag on INPUT
144 * 0: don't include
145 * 1: include
146 */
147#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0
148#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0
149#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0
150#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0
151#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0
152#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0
153#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0
154#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0
155#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0
156#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0
157#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1
158
159/* Select skip mode for input ports */
160#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2
161
162/*
163 * Force backpressure to be disabled. This overrides all other
164 * backpressure configuration.
165 */
166#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
167
168#endif /* __CVMX_CONFIG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
new file mode 100644
index 00000000000..abbf42d05e5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
@@ -0,0 +1,72 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_DBG_DEFS_H__
29#define __CVMX_DBG_DEFS_H__
30
31#define CVMX_DBG_DATA \
32 CVMX_ADD_IO_SEG(0x00011F00000001E8ull)
33
34union cvmx_dbg_data {
35 uint64_t u64;
36 struct cvmx_dbg_data_s {
37 uint64_t reserved_23_63:41;
38 uint64_t c_mul:5;
39 uint64_t dsel_ext:1;
40 uint64_t data:17;
41 } s;
42 struct cvmx_dbg_data_cn30xx {
43 uint64_t reserved_31_63:33;
44 uint64_t pll_mul:3;
45 uint64_t reserved_23_27:5;
46 uint64_t c_mul:5;
47 uint64_t dsel_ext:1;
48 uint64_t data:17;
49 } cn30xx;
50 struct cvmx_dbg_data_cn30xx cn31xx;
51 struct cvmx_dbg_data_cn38xx {
52 uint64_t reserved_29_63:35;
53 uint64_t d_mul:4;
54 uint64_t dclk_mul2:1;
55 uint64_t cclk_div2:1;
56 uint64_t c_mul:5;
57 uint64_t dsel_ext:1;
58 uint64_t data:17;
59 } cn38xx;
60 struct cvmx_dbg_data_cn38xx cn38xxp2;
61 struct cvmx_dbg_data_cn30xx cn50xx;
62 struct cvmx_dbg_data_cn58xx {
63 uint64_t reserved_29_63:35;
64 uint64_t rem:6;
65 uint64_t c_mul:5;
66 uint64_t dsel_ext:1;
67 uint64_t data:17;
68 } cn58xx;
69 struct cvmx_dbg_data_cn58xx cn58xxp1;
70};
71
72#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
new file mode 100644
index 00000000000..c34ad04789c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -0,0 +1,643 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_DPI_DEFS_H__
29#define __CVMX_DPI_DEFS_H__
30
31#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
59
60union cvmx_dpi_bist_status {
61 uint64_t u64;
62 struct cvmx_dpi_bist_status_s {
63 uint64_t reserved_47_63:17;
64 uint64_t bist:47;
65 } s;
66 struct cvmx_dpi_bist_status_s cn61xx;
67 struct cvmx_dpi_bist_status_cn63xx {
68 uint64_t reserved_45_63:19;
69 uint64_t bist:45;
70 } cn63xx;
71 struct cvmx_dpi_bist_status_cn63xxp1 {
72 uint64_t reserved_37_63:27;
73 uint64_t bist:37;
74 } cn63xxp1;
75 struct cvmx_dpi_bist_status_s cn66xx;
76 struct cvmx_dpi_bist_status_cn63xx cn68xx;
77 struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
78};
79
80union cvmx_dpi_ctl {
81 uint64_t u64;
82 struct cvmx_dpi_ctl_s {
83 uint64_t reserved_2_63:62;
84 uint64_t clk:1;
85 uint64_t en:1;
86 } s;
87 struct cvmx_dpi_ctl_cn61xx {
88 uint64_t reserved_1_63:63;
89 uint64_t en:1;
90 } cn61xx;
91 struct cvmx_dpi_ctl_s cn63xx;
92 struct cvmx_dpi_ctl_s cn63xxp1;
93 struct cvmx_dpi_ctl_s cn66xx;
94 struct cvmx_dpi_ctl_s cn68xx;
95 struct cvmx_dpi_ctl_s cn68xxp1;
96};
97
98union cvmx_dpi_dmax_counts {
99 uint64_t u64;
100 struct cvmx_dpi_dmax_counts_s {
101 uint64_t reserved_39_63:25;
102 uint64_t fcnt:7;
103 uint64_t dbell:32;
104 } s;
105 struct cvmx_dpi_dmax_counts_s cn61xx;
106 struct cvmx_dpi_dmax_counts_s cn63xx;
107 struct cvmx_dpi_dmax_counts_s cn63xxp1;
108 struct cvmx_dpi_dmax_counts_s cn66xx;
109 struct cvmx_dpi_dmax_counts_s cn68xx;
110 struct cvmx_dpi_dmax_counts_s cn68xxp1;
111};
112
113union cvmx_dpi_dmax_dbell {
114 uint64_t u64;
115 struct cvmx_dpi_dmax_dbell_s {
116 uint64_t reserved_16_63:48;
117 uint64_t dbell:16;
118 } s;
119 struct cvmx_dpi_dmax_dbell_s cn61xx;
120 struct cvmx_dpi_dmax_dbell_s cn63xx;
121 struct cvmx_dpi_dmax_dbell_s cn63xxp1;
122 struct cvmx_dpi_dmax_dbell_s cn66xx;
123 struct cvmx_dpi_dmax_dbell_s cn68xx;
124 struct cvmx_dpi_dmax_dbell_s cn68xxp1;
125};
126
127union cvmx_dpi_dmax_err_rsp_status {
128 uint64_t u64;
129 struct cvmx_dpi_dmax_err_rsp_status_s {
130 uint64_t reserved_6_63:58;
131 uint64_t status:6;
132 } s;
133 struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
134 struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
135 struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
136 struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
137};
138
139union cvmx_dpi_dmax_ibuff_saddr {
140 uint64_t u64;
141 struct cvmx_dpi_dmax_ibuff_saddr_s {
142 uint64_t reserved_62_63:2;
143 uint64_t csize:14;
144 uint64_t reserved_41_47:7;
145 uint64_t idle:1;
146 uint64_t saddr:33;
147 uint64_t reserved_0_6:7;
148 } s;
149 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
150 uint64_t reserved_62_63:2;
151 uint64_t csize:14;
152 uint64_t reserved_41_47:7;
153 uint64_t idle:1;
154 uint64_t reserved_36_39:4;
155 uint64_t saddr:29;
156 uint64_t reserved_0_6:7;
157 } cn61xx;
158 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
159 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
160 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
161 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
162 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
163};
164
165union cvmx_dpi_dmax_iflight {
166 uint64_t u64;
167 struct cvmx_dpi_dmax_iflight_s {
168 uint64_t reserved_3_63:61;
169 uint64_t cnt:3;
170 } s;
171 struct cvmx_dpi_dmax_iflight_s cn61xx;
172 struct cvmx_dpi_dmax_iflight_s cn66xx;
173 struct cvmx_dpi_dmax_iflight_s cn68xx;
174 struct cvmx_dpi_dmax_iflight_s cn68xxp1;
175};
176
177union cvmx_dpi_dmax_naddr {
178 uint64_t u64;
179 struct cvmx_dpi_dmax_naddr_s {
180 uint64_t reserved_40_63:24;
181 uint64_t addr:40;
182 } s;
183 struct cvmx_dpi_dmax_naddr_cn61xx {
184 uint64_t reserved_36_63:28;
185 uint64_t addr:36;
186 } cn61xx;
187 struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
188 struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
189 struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
190 struct cvmx_dpi_dmax_naddr_s cn68xx;
191 struct cvmx_dpi_dmax_naddr_s cn68xxp1;
192};
193
194union cvmx_dpi_dmax_reqbnk0 {
195 uint64_t u64;
196 struct cvmx_dpi_dmax_reqbnk0_s {
197 uint64_t state:64;
198 } s;
199 struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
200 struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
201 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
202 struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
203 struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
204 struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
205};
206
207union cvmx_dpi_dmax_reqbnk1 {
208 uint64_t u64;
209 struct cvmx_dpi_dmax_reqbnk1_s {
210 uint64_t state:64;
211 } s;
212 struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
213 struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
214 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
215 struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
216 struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
217 struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
218};
219
220union cvmx_dpi_dma_control {
221 uint64_t u64;
222 struct cvmx_dpi_dma_control_s {
223 uint64_t reserved_62_63:2;
224 uint64_t dici_mode:1;
225 uint64_t pkt_en1:1;
226 uint64_t ffp_dis:1;
227 uint64_t commit_mode:1;
228 uint64_t pkt_hp:1;
229 uint64_t pkt_en:1;
230 uint64_t reserved_54_55:2;
231 uint64_t dma_enb:6;
232 uint64_t reserved_34_47:14;
233 uint64_t b0_lend:1;
234 uint64_t dwb_denb:1;
235 uint64_t dwb_ichk:9;
236 uint64_t fpa_que:3;
237 uint64_t o_add1:1;
238 uint64_t o_ro:1;
239 uint64_t o_ns:1;
240 uint64_t o_es:2;
241 uint64_t o_mode:1;
242 uint64_t reserved_0_13:14;
243 } s;
244 struct cvmx_dpi_dma_control_s cn61xx;
245 struct cvmx_dpi_dma_control_cn63xx {
246 uint64_t reserved_61_63:3;
247 uint64_t pkt_en1:1;
248 uint64_t ffp_dis:1;
249 uint64_t commit_mode:1;
250 uint64_t pkt_hp:1;
251 uint64_t pkt_en:1;
252 uint64_t reserved_54_55:2;
253 uint64_t dma_enb:6;
254 uint64_t reserved_34_47:14;
255 uint64_t b0_lend:1;
256 uint64_t dwb_denb:1;
257 uint64_t dwb_ichk:9;
258 uint64_t fpa_que:3;
259 uint64_t o_add1:1;
260 uint64_t o_ro:1;
261 uint64_t o_ns:1;
262 uint64_t o_es:2;
263 uint64_t o_mode:1;
264 uint64_t reserved_0_13:14;
265 } cn63xx;
266 struct cvmx_dpi_dma_control_cn63xxp1 {
267 uint64_t reserved_59_63:5;
268 uint64_t commit_mode:1;
269 uint64_t pkt_hp:1;
270 uint64_t pkt_en:1;
271 uint64_t reserved_54_55:2;
272 uint64_t dma_enb:6;
273 uint64_t reserved_34_47:14;
274 uint64_t b0_lend:1;
275 uint64_t dwb_denb:1;
276 uint64_t dwb_ichk:9;
277 uint64_t fpa_que:3;
278 uint64_t o_add1:1;
279 uint64_t o_ro:1;
280 uint64_t o_ns:1;
281 uint64_t o_es:2;
282 uint64_t o_mode:1;
283 uint64_t reserved_0_13:14;
284 } cn63xxp1;
285 struct cvmx_dpi_dma_control_cn63xx cn66xx;
286 struct cvmx_dpi_dma_control_s cn68xx;
287 struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
288};
289
290union cvmx_dpi_dma_engx_en {
291 uint64_t u64;
292 struct cvmx_dpi_dma_engx_en_s {
293 uint64_t reserved_8_63:56;
294 uint64_t qen:8;
295 } s;
296 struct cvmx_dpi_dma_engx_en_s cn61xx;
297 struct cvmx_dpi_dma_engx_en_s cn63xx;
298 struct cvmx_dpi_dma_engx_en_s cn63xxp1;
299 struct cvmx_dpi_dma_engx_en_s cn66xx;
300 struct cvmx_dpi_dma_engx_en_s cn68xx;
301 struct cvmx_dpi_dma_engx_en_s cn68xxp1;
302};
303
304union cvmx_dpi_dma_ppx_cnt {
305 uint64_t u64;
306 struct cvmx_dpi_dma_ppx_cnt_s {
307 uint64_t reserved_16_63:48;
308 uint64_t cnt:16;
309 } s;
310 struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
311 struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
312};
313
314union cvmx_dpi_engx_buf {
315 uint64_t u64;
316 struct cvmx_dpi_engx_buf_s {
317 uint64_t reserved_37_63:27;
318 uint64_t compblks:5;
319 uint64_t reserved_9_31:23;
320 uint64_t base:5;
321 uint64_t blks:4;
322 } s;
323 struct cvmx_dpi_engx_buf_s cn61xx;
324 struct cvmx_dpi_engx_buf_cn63xx {
325 uint64_t reserved_8_63:56;
326 uint64_t base:4;
327 uint64_t blks:4;
328 } cn63xx;
329 struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
330 struct cvmx_dpi_engx_buf_s cn66xx;
331 struct cvmx_dpi_engx_buf_s cn68xx;
332 struct cvmx_dpi_engx_buf_s cn68xxp1;
333};
334
335union cvmx_dpi_info_reg {
336 uint64_t u64;
337 struct cvmx_dpi_info_reg_s {
338 uint64_t reserved_8_63:56;
339 uint64_t ffp:4;
340 uint64_t reserved_2_3:2;
341 uint64_t ncb:1;
342 uint64_t rsl:1;
343 } s;
344 struct cvmx_dpi_info_reg_s cn61xx;
345 struct cvmx_dpi_info_reg_s cn63xx;
346 struct cvmx_dpi_info_reg_cn63xxp1 {
347 uint64_t reserved_2_63:62;
348 uint64_t ncb:1;
349 uint64_t rsl:1;
350 } cn63xxp1;
351 struct cvmx_dpi_info_reg_s cn66xx;
352 struct cvmx_dpi_info_reg_s cn68xx;
353 struct cvmx_dpi_info_reg_s cn68xxp1;
354};
355
356union cvmx_dpi_int_en {
357 uint64_t u64;
358 struct cvmx_dpi_int_en_s {
359 uint64_t reserved_28_63:36;
360 uint64_t sprt3_rst:1;
361 uint64_t sprt2_rst:1;
362 uint64_t sprt1_rst:1;
363 uint64_t sprt0_rst:1;
364 uint64_t reserved_23_23:1;
365 uint64_t req_badfil:1;
366 uint64_t req_inull:1;
367 uint64_t req_anull:1;
368 uint64_t req_undflw:1;
369 uint64_t req_ovrflw:1;
370 uint64_t req_badlen:1;
371 uint64_t req_badadr:1;
372 uint64_t dmadbo:8;
373 uint64_t reserved_2_7:6;
374 uint64_t nfovr:1;
375 uint64_t nderr:1;
376 } s;
377 struct cvmx_dpi_int_en_s cn61xx;
378 struct cvmx_dpi_int_en_cn63xx {
379 uint64_t reserved_26_63:38;
380 uint64_t sprt1_rst:1;
381 uint64_t sprt0_rst:1;
382 uint64_t reserved_23_23:1;
383 uint64_t req_badfil:1;
384 uint64_t req_inull:1;
385 uint64_t req_anull:1;
386 uint64_t req_undflw:1;
387 uint64_t req_ovrflw:1;
388 uint64_t req_badlen:1;
389 uint64_t req_badadr:1;
390 uint64_t dmadbo:8;
391 uint64_t reserved_2_7:6;
392 uint64_t nfovr:1;
393 uint64_t nderr:1;
394 } cn63xx;
395 struct cvmx_dpi_int_en_cn63xx cn63xxp1;
396 struct cvmx_dpi_int_en_s cn66xx;
397 struct cvmx_dpi_int_en_cn63xx cn68xx;
398 struct cvmx_dpi_int_en_cn63xx cn68xxp1;
399};
400
401union cvmx_dpi_int_reg {
402 uint64_t u64;
403 struct cvmx_dpi_int_reg_s {
404 uint64_t reserved_28_63:36;
405 uint64_t sprt3_rst:1;
406 uint64_t sprt2_rst:1;
407 uint64_t sprt1_rst:1;
408 uint64_t sprt0_rst:1;
409 uint64_t reserved_23_23:1;
410 uint64_t req_badfil:1;
411 uint64_t req_inull:1;
412 uint64_t req_anull:1;
413 uint64_t req_undflw:1;
414 uint64_t req_ovrflw:1;
415 uint64_t req_badlen:1;
416 uint64_t req_badadr:1;
417 uint64_t dmadbo:8;
418 uint64_t reserved_2_7:6;
419 uint64_t nfovr:1;
420 uint64_t nderr:1;
421 } s;
422 struct cvmx_dpi_int_reg_s cn61xx;
423 struct cvmx_dpi_int_reg_cn63xx {
424 uint64_t reserved_26_63:38;
425 uint64_t sprt1_rst:1;
426 uint64_t sprt0_rst:1;
427 uint64_t reserved_23_23:1;
428 uint64_t req_badfil:1;
429 uint64_t req_inull:1;
430 uint64_t req_anull:1;
431 uint64_t req_undflw:1;
432 uint64_t req_ovrflw:1;
433 uint64_t req_badlen:1;
434 uint64_t req_badadr:1;
435 uint64_t dmadbo:8;
436 uint64_t reserved_2_7:6;
437 uint64_t nfovr:1;
438 uint64_t nderr:1;
439 } cn63xx;
440 struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
441 struct cvmx_dpi_int_reg_s cn66xx;
442 struct cvmx_dpi_int_reg_cn63xx cn68xx;
443 struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
444};
445
446union cvmx_dpi_ncbx_cfg {
447 uint64_t u64;
448 struct cvmx_dpi_ncbx_cfg_s {
449 uint64_t reserved_6_63:58;
450 uint64_t molr:6;
451 } s;
452 struct cvmx_dpi_ncbx_cfg_s cn61xx;
453 struct cvmx_dpi_ncbx_cfg_s cn66xx;
454 struct cvmx_dpi_ncbx_cfg_s cn68xx;
455};
456
457union cvmx_dpi_pint_info {
458 uint64_t u64;
459 struct cvmx_dpi_pint_info_s {
460 uint64_t reserved_14_63:50;
461 uint64_t iinfo:6;
462 uint64_t reserved_6_7:2;
463 uint64_t sinfo:6;
464 } s;
465 struct cvmx_dpi_pint_info_s cn61xx;
466 struct cvmx_dpi_pint_info_s cn63xx;
467 struct cvmx_dpi_pint_info_s cn63xxp1;
468 struct cvmx_dpi_pint_info_s cn66xx;
469 struct cvmx_dpi_pint_info_s cn68xx;
470 struct cvmx_dpi_pint_info_s cn68xxp1;
471};
472
473union cvmx_dpi_pkt_err_rsp {
474 uint64_t u64;
475 struct cvmx_dpi_pkt_err_rsp_s {
476 uint64_t reserved_1_63:63;
477 uint64_t pkterr:1;
478 } s;
479 struct cvmx_dpi_pkt_err_rsp_s cn61xx;
480 struct cvmx_dpi_pkt_err_rsp_s cn63xx;
481 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
482 struct cvmx_dpi_pkt_err_rsp_s cn66xx;
483 struct cvmx_dpi_pkt_err_rsp_s cn68xx;
484 struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
485};
486
487union cvmx_dpi_req_err_rsp {
488 uint64_t u64;
489 struct cvmx_dpi_req_err_rsp_s {
490 uint64_t reserved_8_63:56;
491 uint64_t qerr:8;
492 } s;
493 struct cvmx_dpi_req_err_rsp_s cn61xx;
494 struct cvmx_dpi_req_err_rsp_s cn63xx;
495 struct cvmx_dpi_req_err_rsp_s cn63xxp1;
496 struct cvmx_dpi_req_err_rsp_s cn66xx;
497 struct cvmx_dpi_req_err_rsp_s cn68xx;
498 struct cvmx_dpi_req_err_rsp_s cn68xxp1;
499};
500
501union cvmx_dpi_req_err_rsp_en {
502 uint64_t u64;
503 struct cvmx_dpi_req_err_rsp_en_s {
504 uint64_t reserved_8_63:56;
505 uint64_t en:8;
506 } s;
507 struct cvmx_dpi_req_err_rsp_en_s cn61xx;
508 struct cvmx_dpi_req_err_rsp_en_s cn63xx;
509 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
510 struct cvmx_dpi_req_err_rsp_en_s cn66xx;
511 struct cvmx_dpi_req_err_rsp_en_s cn68xx;
512 struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
513};
514
515union cvmx_dpi_req_err_rst {
516 uint64_t u64;
517 struct cvmx_dpi_req_err_rst_s {
518 uint64_t reserved_8_63:56;
519 uint64_t qerr:8;
520 } s;
521 struct cvmx_dpi_req_err_rst_s cn61xx;
522 struct cvmx_dpi_req_err_rst_s cn63xx;
523 struct cvmx_dpi_req_err_rst_s cn63xxp1;
524 struct cvmx_dpi_req_err_rst_s cn66xx;
525 struct cvmx_dpi_req_err_rst_s cn68xx;
526 struct cvmx_dpi_req_err_rst_s cn68xxp1;
527};
528
529union cvmx_dpi_req_err_rst_en {
530 uint64_t u64;
531 struct cvmx_dpi_req_err_rst_en_s {
532 uint64_t reserved_8_63:56;
533 uint64_t en:8;
534 } s;
535 struct cvmx_dpi_req_err_rst_en_s cn61xx;
536 struct cvmx_dpi_req_err_rst_en_s cn63xx;
537 struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
538 struct cvmx_dpi_req_err_rst_en_s cn66xx;
539 struct cvmx_dpi_req_err_rst_en_s cn68xx;
540 struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
541};
542
543union cvmx_dpi_req_err_skip_comp {
544 uint64_t u64;
545 struct cvmx_dpi_req_err_skip_comp_s {
546 uint64_t reserved_24_63:40;
547 uint64_t en_rst:8;
548 uint64_t reserved_8_15:8;
549 uint64_t en_rsp:8;
550 } s;
551 struct cvmx_dpi_req_err_skip_comp_s cn61xx;
552 struct cvmx_dpi_req_err_skip_comp_s cn66xx;
553 struct cvmx_dpi_req_err_skip_comp_s cn68xx;
554 struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
555};
556
557union cvmx_dpi_req_gbl_en {
558 uint64_t u64;
559 struct cvmx_dpi_req_gbl_en_s {
560 uint64_t reserved_8_63:56;
561 uint64_t qen:8;
562 } s;
563 struct cvmx_dpi_req_gbl_en_s cn61xx;
564 struct cvmx_dpi_req_gbl_en_s cn63xx;
565 struct cvmx_dpi_req_gbl_en_s cn63xxp1;
566 struct cvmx_dpi_req_gbl_en_s cn66xx;
567 struct cvmx_dpi_req_gbl_en_s cn68xx;
568 struct cvmx_dpi_req_gbl_en_s cn68xxp1;
569};
570
571union cvmx_dpi_sli_prtx_cfg {
572 uint64_t u64;
573 struct cvmx_dpi_sli_prtx_cfg_s {
574 uint64_t reserved_25_63:39;
575 uint64_t halt:1;
576 uint64_t qlm_cfg:4;
577 uint64_t reserved_17_19:3;
578 uint64_t rd_mode:1;
579 uint64_t reserved_14_15:2;
580 uint64_t molr:6;
581 uint64_t mps_lim:1;
582 uint64_t reserved_5_6:2;
583 uint64_t mps:1;
584 uint64_t mrrs_lim:1;
585 uint64_t reserved_2_2:1;
586 uint64_t mrrs:2;
587 } s;
588 struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
589 struct cvmx_dpi_sli_prtx_cfg_cn63xx {
590 uint64_t reserved_25_63:39;
591 uint64_t halt:1;
592 uint64_t reserved_21_23:3;
593 uint64_t qlm_cfg:1;
594 uint64_t reserved_17_19:3;
595 uint64_t rd_mode:1;
596 uint64_t reserved_14_15:2;
597 uint64_t molr:6;
598 uint64_t mps_lim:1;
599 uint64_t reserved_5_6:2;
600 uint64_t mps:1;
601 uint64_t mrrs_lim:1;
602 uint64_t reserved_2_2:1;
603 uint64_t mrrs:2;
604 } cn63xx;
605 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
606 struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
607 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
608 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
609};
610
611union cvmx_dpi_sli_prtx_err {
612 uint64_t u64;
613 struct cvmx_dpi_sli_prtx_err_s {
614 uint64_t addr:61;
615 uint64_t reserved_0_2:3;
616 } s;
617 struct cvmx_dpi_sli_prtx_err_s cn61xx;
618 struct cvmx_dpi_sli_prtx_err_s cn63xx;
619 struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
620 struct cvmx_dpi_sli_prtx_err_s cn66xx;
621 struct cvmx_dpi_sli_prtx_err_s cn68xx;
622 struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
623};
624
625union cvmx_dpi_sli_prtx_err_info {
626 uint64_t u64;
627 struct cvmx_dpi_sli_prtx_err_info_s {
628 uint64_t reserved_9_63:55;
629 uint64_t lock:1;
630 uint64_t reserved_5_7:3;
631 uint64_t type:1;
632 uint64_t reserved_3_3:1;
633 uint64_t reqq:3;
634 } s;
635 struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
636 struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
637 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
638 struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
639 struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
640 struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
641};
642
643#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
new file mode 100644
index 00000000000..a6939fc8ba1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
@@ -0,0 +1,597 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Interface to the hardware Fetch and Add Unit.
30 */
31
32#ifndef __CVMX_FAU_H__
33#define __CVMX_FAU_H__
34
35/*
36 * Octeon Fetch and Add Unit (FAU)
37 */
38
39#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0)
40#define CVMX_FAU_BITS_SCRADDR 63, 56
41#define CVMX_FAU_BITS_LEN 55, 48
42#define CVMX_FAU_BITS_INEVAL 35, 14
43#define CVMX_FAU_BITS_TAGWAIT 13, 13
44#define CVMX_FAU_BITS_NOADD 13, 13
45#define CVMX_FAU_BITS_SIZE 12, 11
46#define CVMX_FAU_BITS_REGISTER 10, 0
47
48typedef enum {
49 CVMX_FAU_OP_SIZE_8 = 0,
50 CVMX_FAU_OP_SIZE_16 = 1,
51 CVMX_FAU_OP_SIZE_32 = 2,
52 CVMX_FAU_OP_SIZE_64 = 3
53} cvmx_fau_op_size_t;
54
55/**
56 * Tagwait return definition. If a timeout occurs, the error
57 * bit will be set. Otherwise the value of the register before
58 * the update will be returned.
59 */
60typedef struct {
61 uint64_t error:1;
62 int64_t value:63;
63} cvmx_fau_tagwait64_t;
64
65/**
66 * Tagwait return definition. If a timeout occurs, the error
67 * bit will be set. Otherwise the value of the register before
68 * the update will be returned.
69 */
70typedef struct {
71 uint64_t error:1;
72 int32_t value:31;
73} cvmx_fau_tagwait32_t;
74
75/**
76 * Tagwait return definition. If a timeout occurs, the error
77 * bit will be set. Otherwise the value of the register before
78 * the update will be returned.
79 */
80typedef struct {
81 uint64_t error:1;
82 int16_t value:15;
83} cvmx_fau_tagwait16_t;
84
85/**
86 * Tagwait return definition. If a timeout occurs, the error
87 * bit will be set. Otherwise the value of the register before
88 * the update will be returned.
89 */
90typedef struct {
91 uint64_t error:1;
92 int8_t value:7;
93} cvmx_fau_tagwait8_t;
94
95/**
96 * Asynchronous tagwait return definition. If a timeout occurs,
97 * the error bit will be set. Otherwise the value of the
98 * register before the update will be returned.
99 */
100typedef union {
101 uint64_t u64;
102 struct {
103 uint64_t invalid:1;
104 uint64_t data:63; /* unpredictable if invalid is set */
105 } s;
106} cvmx_fau_async_tagwait_result_t;
107
108/**
109 * Builds a store I/O address for writing to the FAU
110 *
111 * @noadd: 0 = Store value is atomically added to the current value
112 * 1 = Store value is atomically written over the current value
113 * @reg: FAU atomic register to access. 0 <= reg < 2048.
114 * - Step by 2 for 16 bit access.
115 * - Step by 4 for 32 bit access.
116 * - Step by 8 for 64 bit access.
117 * Returns Address to store for atomic update
118 */
119static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
120{
121 return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
122 cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
123 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
124}
125
126/**
127 * Builds a I/O address for accessing the FAU
128 *
129 * @tagwait: Should the atomic add wait for the current tag switch
130 * operation to complete.
131 * - 0 = Don't wait
132 * - 1 = Wait for tag switch to complete
133 * @reg: FAU atomic register to access. 0 <= reg < 2048.
134 * - Step by 2 for 16 bit access.
135 * - Step by 4 for 32 bit access.
136 * - Step by 8 for 64 bit access.
137 * @value: Signed value to add.
138 * Note: When performing 32 and 64 bit access, only the low
139 * 22 bits are available.
140 * Returns Address to read from for atomic update
141 */
142static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
143 int64_t value)
144{
145 return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
146 cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
147 cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
148 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
149}
150
151/**
152 * Perform an atomic 64 bit add
153 *
154 * @reg: FAU atomic register to access. 0 <= reg < 2048.
155 * - Step by 8 for 64 bit access.
156 * @value: Signed value to add.
157 * Note: Only the low 22 bits are available.
158 * Returns Value of the register before the update
159 */
160static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
161 int64_t value)
162{
163 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
164}
165
166/**
167 * Perform an atomic 32 bit add
168 *
169 * @reg: FAU atomic register to access. 0 <= reg < 2048.
170 * - Step by 4 for 32 bit access.
171 * @value: Signed value to add.
172 * Note: Only the low 22 bits are available.
173 * Returns Value of the register before the update
174 */
175static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
176 int32_t value)
177{
178 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
179}
180
181/**
182 * Perform an atomic 16 bit add
183 *
184 * @reg: FAU atomic register to access. 0 <= reg < 2048.
185 * - Step by 2 for 16 bit access.
186 * @value: Signed value to add.
187 * Returns Value of the register before the update
188 */
189static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
190 int16_t value)
191{
192 return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
193}
194
195/**
196 * Perform an atomic 8 bit add
197 *
198 * @reg: FAU atomic register to access. 0 <= reg < 2048.
199 * @value: Signed value to add.
200 * Returns Value of the register before the update
201 */
202static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
203{
204 return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
205}
206
207/**
208 * Perform an atomic 64 bit add after the current tag switch
209 * completes
210 *
211 * @reg: FAU atomic register to access. 0 <= reg < 2048.
212 * - Step by 8 for 64 bit access.
213 * @value: Signed value to add.
214 * Note: Only the low 22 bits are available.
215 * Returns If a timeout occurs, the error bit will be set. Otherwise
216 * the value of the register before the update will be
217 * returned
218 */
219static inline cvmx_fau_tagwait64_t
220cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
221{
222 union {
223 uint64_t i64;
224 cvmx_fau_tagwait64_t t;
225 } result;
226 result.i64 =
227 cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
228 return result.t;
229}
230
231/**
232 * Perform an atomic 32 bit add after the current tag switch
233 * completes
234 *
235 * @reg: FAU atomic register to access. 0 <= reg < 2048.
236 * - Step by 4 for 32 bit access.
237 * @value: Signed value to add.
238 * Note: Only the low 22 bits are available.
239 * Returns If a timeout occurs, the error bit will be set. Otherwise
240 * the value of the register before the update will be
241 * returned
242 */
243static inline cvmx_fau_tagwait32_t
244cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
245{
246 union {
247 uint64_t i32;
248 cvmx_fau_tagwait32_t t;
249 } result;
250 result.i32 =
251 cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
252 return result.t;
253}
254
255/**
256 * Perform an atomic 16 bit add after the current tag switch
257 * completes
258 *
259 * @reg: FAU atomic register to access. 0 <= reg < 2048.
260 * - Step by 2 for 16 bit access.
261 * @value: Signed value to add.
262 * Returns If a timeout occurs, the error bit will be set. Otherwise
263 * the value of the register before the update will be
264 * returned
265 */
266static inline cvmx_fau_tagwait16_t
267cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
268{
269 union {
270 uint64_t i16;
271 cvmx_fau_tagwait16_t t;
272 } result;
273 result.i16 =
274 cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
275 return result.t;
276}
277
278/**
279 * Perform an atomic 8 bit add after the current tag switch
280 * completes
281 *
282 * @reg: FAU atomic register to access. 0 <= reg < 2048.
283 * @value: Signed value to add.
284 * Returns If a timeout occurs, the error bit will be set. Otherwise
285 * the value of the register before the update will be
286 * returned
287 */
288static inline cvmx_fau_tagwait8_t
289cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
290{
291 union {
292 uint64_t i8;
293 cvmx_fau_tagwait8_t t;
294 } result;
295 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
296 return result.t;
297}
298
299/**
300 * Builds I/O data for async operations
301 *
302 * @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned
303 * @value: Signed value to add.
304 * Note: When performing 32 and 64 bit access, only the low
305 * 22 bits are available.
306 * @tagwait: Should the atomic add wait for the current tag switch
307 * operation to complete.
308 * - 0 = Don't wait
309 * - 1 = Wait for tag switch to complete
310 * @size: The size of the operation:
311 * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits
312 * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
313 * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
314 * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
315 * @reg: FAU atomic register to access. 0 <= reg < 2048.
316 * - Step by 2 for 16 bit access.
317 * - Step by 4 for 32 bit access.
318 * - Step by 8 for 64 bit access.
319 * Returns Data to write using cvmx_send_single
320 */
321static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
322 uint64_t tagwait,
323 cvmx_fau_op_size_t size,
324 uint64_t reg)
325{
326 return CVMX_FAU_LOAD_IO_ADDRESS |
327 cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
328 cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
329 cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
330 cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
331 cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
332 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
333}
334
335/**
336 * Perform an async atomic 64 bit add. The old value is
337 * placed in the scratch memory at byte address scraddr.
338 *
339 * @scraddr: Scratch memory byte address to put response in.
340 * Must be 8 byte aligned.
341 * @reg: FAU atomic register to access. 0 <= reg < 2048.
342 * - Step by 8 for 64 bit access.
343 * @value: Signed value to add.
344 * Note: Only the low 22 bits are available.
345 * Returns Placed in the scratch pad register
346 */
347static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
348 cvmx_fau_reg_64_t reg,
349 int64_t value)
350{
351 cvmx_send_single(__cvmx_fau_iobdma_data
352 (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
353}
354
355/**
356 * Perform an async atomic 32 bit add. The old value is
357 * placed in the scratch memory at byte address scraddr.
358 *
359 * @scraddr: Scratch memory byte address to put response in.
360 * Must be 8 byte aligned.
361 * @reg: FAU atomic register to access. 0 <= reg < 2048.
362 * - Step by 4 for 32 bit access.
363 * @value: Signed value to add.
364 * Note: Only the low 22 bits are available.
365 * Returns Placed in the scratch pad register
366 */
367static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
368 cvmx_fau_reg_32_t reg,
369 int32_t value)
370{
371 cvmx_send_single(__cvmx_fau_iobdma_data
372 (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
373}
374
375/**
376 * Perform an async atomic 16 bit add. The old value is
377 * placed in the scratch memory at byte address scraddr.
378 *
379 * @scraddr: Scratch memory byte address to put response in.
380 * Must be 8 byte aligned.
381 * @reg: FAU atomic register to access. 0 <= reg < 2048.
382 * - Step by 2 for 16 bit access.
383 * @value: Signed value to add.
384 * Returns Placed in the scratch pad register
385 */
386static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr,
387 cvmx_fau_reg_16_t reg,
388 int16_t value)
389{
390 cvmx_send_single(__cvmx_fau_iobdma_data
391 (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
392}
393
394/**
395 * Perform an async atomic 8 bit add. The old value is
396 * placed in the scratch memory at byte address scraddr.
397 *
398 * @scraddr: Scratch memory byte address to put response in.
399 * Must be 8 byte aligned.
400 * @reg: FAU atomic register to access. 0 <= reg < 2048.
401 * @value: Signed value to add.
402 * Returns Placed in the scratch pad register
403 */
404static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr,
405 cvmx_fau_reg_8_t reg,
406 int8_t value)
407{
408 cvmx_send_single(__cvmx_fau_iobdma_data
409 (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
410}
411
412/**
413 * Perform an async atomic 64 bit add after the current tag
414 * switch completes.
415 *
416 * @scraddr: Scratch memory byte address to put response in. Must be
417 * 8 byte aligned. If a timeout occurs, the error bit (63)
418 * will be set. Otherwise the value of the register before
419 * the update will be returned
420 *
421 * @reg: FAU atomic register to access. 0 <= reg < 2048.
422 * - Step by 8 for 64 bit access.
423 * @value: Signed value to add.
424 * Note: Only the low 22 bits are available.
425 * Returns Placed in the scratch pad register
426 */
427static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
428 cvmx_fau_reg_64_t reg,
429 int64_t value)
430{
431 cvmx_send_single(__cvmx_fau_iobdma_data
432 (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
433}
434
435/**
436 * Perform an async atomic 32 bit add after the current tag
437 * switch completes.
438 *
439 * @scraddr: Scratch memory byte address to put response in. Must be
440 * 8 byte aligned. If a timeout occurs, the error bit (63)
441 * will be set. Otherwise the value of the register before
442 * the update will be returned
443 *
444 * @reg: FAU atomic register to access. 0 <= reg < 2048.
445 * - Step by 4 for 32 bit access.
446 * @value: Signed value to add.
447 * Note: Only the low 22 bits are available.
448 * Returns Placed in the scratch pad register
449 */
450static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
451 cvmx_fau_reg_32_t reg,
452 int32_t value)
453{
454 cvmx_send_single(__cvmx_fau_iobdma_data
455 (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
456}
457
458/**
459 * Perform an async atomic 16 bit add after the current tag
460 * switch completes.
461 *
462 * @scraddr: Scratch memory byte address to put response in. Must be
463 * 8 byte aligned. If a timeout occurs, the error bit (63)
464 * will be set. Otherwise the value of the register before
465 * the update will be returned
466 *
467 * @reg: FAU atomic register to access. 0 <= reg < 2048.
468 * - Step by 2 for 16 bit access.
469 * @value: Signed value to add.
470 *
471 * Returns Placed in the scratch pad register
472 */
473static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr,
474 cvmx_fau_reg_16_t reg,
475 int16_t value)
476{
477 cvmx_send_single(__cvmx_fau_iobdma_data
478 (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
479}
480
481/**
482 * Perform an async atomic 8 bit add after the current tag
483 * switch completes.
484 *
485 * @scraddr: Scratch memory byte address to put response in. Must be
486 * 8 byte aligned. If a timeout occurs, the error bit (63)
487 * will be set. Otherwise the value of the register before
488 * the update will be returned
489 *
490 * @reg: FAU atomic register to access. 0 <= reg < 2048.
491 * @value: Signed value to add.
492 *
493 * Returns Placed in the scratch pad register
494 */
495static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr,
496 cvmx_fau_reg_8_t reg,
497 int8_t value)
498{
499 cvmx_send_single(__cvmx_fau_iobdma_data
500 (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
501}
502
503/**
504 * Perform an atomic 64 bit add
505 *
506 * @reg: FAU atomic register to access. 0 <= reg < 2048.
507 * - Step by 8 for 64 bit access.
508 * @value: Signed value to add.
509 */
510static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
511{
512 cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
513}
514
515/**
516 * Perform an atomic 32 bit add
517 *
518 * @reg: FAU atomic register to access. 0 <= reg < 2048.
519 * - Step by 4 for 32 bit access.
520 * @value: Signed value to add.
521 */
522static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
523{
524 cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
525}
526
527/**
528 * Perform an atomic 16 bit add
529 *
530 * @reg: FAU atomic register to access. 0 <= reg < 2048.
531 * - Step by 2 for 16 bit access.
532 * @value: Signed value to add.
533 */
534static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
535{
536 cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
537}
538
539/**
540 * Perform an atomic 8 bit add
541 *
542 * @reg: FAU atomic register to access. 0 <= reg < 2048.
543 * @value: Signed value to add.
544 */
545static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
546{
547 cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
548}
549
550/**
551 * Perform an atomic 64 bit write
552 *
553 * @reg: FAU atomic register to access. 0 <= reg < 2048.
554 * - Step by 8 for 64 bit access.
555 * @value: Signed value to write.
556 */
557static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
558{
559 cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
560}
561
562/**
563 * Perform an atomic 32 bit write
564 *
565 * @reg: FAU atomic register to access. 0 <= reg < 2048.
566 * - Step by 4 for 32 bit access.
567 * @value: Signed value to write.
568 */
569static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
570{
571 cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
572}
573
574/**
575 * Perform an atomic 16 bit write
576 *
577 * @reg: FAU atomic register to access. 0 <= reg < 2048.
578 * - Step by 2 for 16 bit access.
579 * @value: Signed value to write.
580 */
581static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
582{
583 cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
584}
585
586/**
587 * Perform an atomic 8 bit write
588 *
589 * @reg: FAU atomic register to access. 0 <= reg < 2048.
590 * @value: Signed value to write.
591 */
592static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
593{
594 cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
595}
596
597#endif /* __CVMX_FAU_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
new file mode 100644
index 00000000000..bf5546b9011
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
@@ -0,0 +1,403 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_FPA_DEFS_H__
29#define __CVMX_FPA_DEFS_H__
30
31#define CVMX_FPA_BIST_STATUS \
32 CVMX_ADD_IO_SEG(0x00011800280000E8ull)
33#define CVMX_FPA_CTL_STATUS \
34 CVMX_ADD_IO_SEG(0x0001180028000050ull)
35#define CVMX_FPA_FPF0_MARKS \
36 CVMX_ADD_IO_SEG(0x0001180028000000ull)
37#define CVMX_FPA_FPF0_SIZE \
38 CVMX_ADD_IO_SEG(0x0001180028000058ull)
39#define CVMX_FPA_FPF1_MARKS \
40 CVMX_ADD_IO_SEG(0x0001180028000008ull)
41#define CVMX_FPA_FPF2_MARKS \
42 CVMX_ADD_IO_SEG(0x0001180028000010ull)
43#define CVMX_FPA_FPF3_MARKS \
44 CVMX_ADD_IO_SEG(0x0001180028000018ull)
45#define CVMX_FPA_FPF4_MARKS \
46 CVMX_ADD_IO_SEG(0x0001180028000020ull)
47#define CVMX_FPA_FPF5_MARKS \
48 CVMX_ADD_IO_SEG(0x0001180028000028ull)
49#define CVMX_FPA_FPF6_MARKS \
50 CVMX_ADD_IO_SEG(0x0001180028000030ull)
51#define CVMX_FPA_FPF7_MARKS \
52 CVMX_ADD_IO_SEG(0x0001180028000038ull)
53#define CVMX_FPA_FPFX_MARKS(offset) \
54 CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1)
55#define CVMX_FPA_FPFX_SIZE(offset) \
56 CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1)
57#define CVMX_FPA_INT_ENB \
58 CVMX_ADD_IO_SEG(0x0001180028000048ull)
59#define CVMX_FPA_INT_SUM \
60 CVMX_ADD_IO_SEG(0x0001180028000040ull)
61#define CVMX_FPA_QUE0_PAGE_INDEX \
62 CVMX_ADD_IO_SEG(0x00011800280000F0ull)
63#define CVMX_FPA_QUE1_PAGE_INDEX \
64 CVMX_ADD_IO_SEG(0x00011800280000F8ull)
65#define CVMX_FPA_QUE2_PAGE_INDEX \
66 CVMX_ADD_IO_SEG(0x0001180028000100ull)
67#define CVMX_FPA_QUE3_PAGE_INDEX \
68 CVMX_ADD_IO_SEG(0x0001180028000108ull)
69#define CVMX_FPA_QUE4_PAGE_INDEX \
70 CVMX_ADD_IO_SEG(0x0001180028000110ull)
71#define CVMX_FPA_QUE5_PAGE_INDEX \
72 CVMX_ADD_IO_SEG(0x0001180028000118ull)
73#define CVMX_FPA_QUE6_PAGE_INDEX \
74 CVMX_ADD_IO_SEG(0x0001180028000120ull)
75#define CVMX_FPA_QUE7_PAGE_INDEX \
76 CVMX_ADD_IO_SEG(0x0001180028000128ull)
77#define CVMX_FPA_QUEX_AVAILABLE(offset) \
78 CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8))
79#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \
80 CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8))
81#define CVMX_FPA_QUE_ACT \
82 CVMX_ADD_IO_SEG(0x0001180028000138ull)
83#define CVMX_FPA_QUE_EXP \
84 CVMX_ADD_IO_SEG(0x0001180028000130ull)
85#define CVMX_FPA_WART_CTL \
86 CVMX_ADD_IO_SEG(0x00011800280000D8ull)
87#define CVMX_FPA_WART_STATUS \
88 CVMX_ADD_IO_SEG(0x00011800280000E0ull)
89
90union cvmx_fpa_bist_status {
91 uint64_t u64;
92 struct cvmx_fpa_bist_status_s {
93 uint64_t reserved_5_63:59;
94 uint64_t frd:1;
95 uint64_t fpf0:1;
96 uint64_t fpf1:1;
97 uint64_t ffr:1;
98 uint64_t fdr:1;
99 } s;
100 struct cvmx_fpa_bist_status_s cn30xx;
101 struct cvmx_fpa_bist_status_s cn31xx;
102 struct cvmx_fpa_bist_status_s cn38xx;
103 struct cvmx_fpa_bist_status_s cn38xxp2;
104 struct cvmx_fpa_bist_status_s cn50xx;
105 struct cvmx_fpa_bist_status_s cn52xx;
106 struct cvmx_fpa_bist_status_s cn52xxp1;
107 struct cvmx_fpa_bist_status_s cn56xx;
108 struct cvmx_fpa_bist_status_s cn56xxp1;
109 struct cvmx_fpa_bist_status_s cn58xx;
110 struct cvmx_fpa_bist_status_s cn58xxp1;
111};
112
113union cvmx_fpa_ctl_status {
114 uint64_t u64;
115 struct cvmx_fpa_ctl_status_s {
116 uint64_t reserved_18_63:46;
117 uint64_t reset:1;
118 uint64_t use_ldt:1;
119 uint64_t use_stt:1;
120 uint64_t enb:1;
121 uint64_t mem1_err:7;
122 uint64_t mem0_err:7;
123 } s;
124 struct cvmx_fpa_ctl_status_s cn30xx;
125 struct cvmx_fpa_ctl_status_s cn31xx;
126 struct cvmx_fpa_ctl_status_s cn38xx;
127 struct cvmx_fpa_ctl_status_s cn38xxp2;
128 struct cvmx_fpa_ctl_status_s cn50xx;
129 struct cvmx_fpa_ctl_status_s cn52xx;
130 struct cvmx_fpa_ctl_status_s cn52xxp1;
131 struct cvmx_fpa_ctl_status_s cn56xx;
132 struct cvmx_fpa_ctl_status_s cn56xxp1;
133 struct cvmx_fpa_ctl_status_s cn58xx;
134 struct cvmx_fpa_ctl_status_s cn58xxp1;
135};
136
137union cvmx_fpa_fpfx_marks {
138 uint64_t u64;
139 struct cvmx_fpa_fpfx_marks_s {
140 uint64_t reserved_22_63:42;
141 uint64_t fpf_wr:11;
142 uint64_t fpf_rd:11;
143 } s;
144 struct cvmx_fpa_fpfx_marks_s cn38xx;
145 struct cvmx_fpa_fpfx_marks_s cn38xxp2;
146 struct cvmx_fpa_fpfx_marks_s cn56xx;
147 struct cvmx_fpa_fpfx_marks_s cn56xxp1;
148 struct cvmx_fpa_fpfx_marks_s cn58xx;
149 struct cvmx_fpa_fpfx_marks_s cn58xxp1;
150};
151
152union cvmx_fpa_fpfx_size {
153 uint64_t u64;
154 struct cvmx_fpa_fpfx_size_s {
155 uint64_t reserved_11_63:53;
156 uint64_t fpf_siz:11;
157 } s;
158 struct cvmx_fpa_fpfx_size_s cn38xx;
159 struct cvmx_fpa_fpfx_size_s cn38xxp2;
160 struct cvmx_fpa_fpfx_size_s cn56xx;
161 struct cvmx_fpa_fpfx_size_s cn56xxp1;
162 struct cvmx_fpa_fpfx_size_s cn58xx;
163 struct cvmx_fpa_fpfx_size_s cn58xxp1;
164};
165
166union cvmx_fpa_fpf0_marks {
167 uint64_t u64;
168 struct cvmx_fpa_fpf0_marks_s {
169 uint64_t reserved_24_63:40;
170 uint64_t fpf_wr:12;
171 uint64_t fpf_rd:12;
172 } s;
173 struct cvmx_fpa_fpf0_marks_s cn38xx;
174 struct cvmx_fpa_fpf0_marks_s cn38xxp2;
175 struct cvmx_fpa_fpf0_marks_s cn56xx;
176 struct cvmx_fpa_fpf0_marks_s cn56xxp1;
177 struct cvmx_fpa_fpf0_marks_s cn58xx;
178 struct cvmx_fpa_fpf0_marks_s cn58xxp1;
179};
180
181union cvmx_fpa_fpf0_size {
182 uint64_t u64;
183 struct cvmx_fpa_fpf0_size_s {
184 uint64_t reserved_12_63:52;
185 uint64_t fpf_siz:12;
186 } s;
187 struct cvmx_fpa_fpf0_size_s cn38xx;
188 struct cvmx_fpa_fpf0_size_s cn38xxp2;
189 struct cvmx_fpa_fpf0_size_s cn56xx;
190 struct cvmx_fpa_fpf0_size_s cn56xxp1;
191 struct cvmx_fpa_fpf0_size_s cn58xx;
192 struct cvmx_fpa_fpf0_size_s cn58xxp1;
193};
194
195union cvmx_fpa_int_enb {
196 uint64_t u64;
197 struct cvmx_fpa_int_enb_s {
198 uint64_t reserved_28_63:36;
199 uint64_t q7_perr:1;
200 uint64_t q7_coff:1;
201 uint64_t q7_und:1;
202 uint64_t q6_perr:1;
203 uint64_t q6_coff:1;
204 uint64_t q6_und:1;
205 uint64_t q5_perr:1;
206 uint64_t q5_coff:1;
207 uint64_t q5_und:1;
208 uint64_t q4_perr:1;
209 uint64_t q4_coff:1;
210 uint64_t q4_und:1;
211 uint64_t q3_perr:1;
212 uint64_t q3_coff:1;
213 uint64_t q3_und:1;
214 uint64_t q2_perr:1;
215 uint64_t q2_coff:1;
216 uint64_t q2_und:1;
217 uint64_t q1_perr:1;
218 uint64_t q1_coff:1;
219 uint64_t q1_und:1;
220 uint64_t q0_perr:1;
221 uint64_t q0_coff:1;
222 uint64_t q0_und:1;
223 uint64_t fed1_dbe:1;
224 uint64_t fed1_sbe:1;
225 uint64_t fed0_dbe:1;
226 uint64_t fed0_sbe:1;
227 } s;
228 struct cvmx_fpa_int_enb_s cn30xx;
229 struct cvmx_fpa_int_enb_s cn31xx;
230 struct cvmx_fpa_int_enb_s cn38xx;
231 struct cvmx_fpa_int_enb_s cn38xxp2;
232 struct cvmx_fpa_int_enb_s cn50xx;
233 struct cvmx_fpa_int_enb_s cn52xx;
234 struct cvmx_fpa_int_enb_s cn52xxp1;
235 struct cvmx_fpa_int_enb_s cn56xx;
236 struct cvmx_fpa_int_enb_s cn56xxp1;
237 struct cvmx_fpa_int_enb_s cn58xx;
238 struct cvmx_fpa_int_enb_s cn58xxp1;
239};
240
241union cvmx_fpa_int_sum {
242 uint64_t u64;
243 struct cvmx_fpa_int_sum_s {
244 uint64_t reserved_28_63:36;
245 uint64_t q7_perr:1;
246 uint64_t q7_coff:1;
247 uint64_t q7_und:1;
248 uint64_t q6_perr:1;
249 uint64_t q6_coff:1;
250 uint64_t q6_und:1;
251 uint64_t q5_perr:1;
252 uint64_t q5_coff:1;
253 uint64_t q5_und:1;
254 uint64_t q4_perr:1;
255 uint64_t q4_coff:1;
256 uint64_t q4_und:1;
257 uint64_t q3_perr:1;
258 uint64_t q3_coff:1;
259 uint64_t q3_und:1;
260 uint64_t q2_perr:1;
261 uint64_t q2_coff:1;
262 uint64_t q2_und:1;
263 uint64_t q1_perr:1;
264 uint64_t q1_coff:1;
265 uint64_t q1_und:1;
266 uint64_t q0_perr:1;
267 uint64_t q0_coff:1;
268 uint64_t q0_und:1;
269 uint64_t fed1_dbe:1;
270 uint64_t fed1_sbe:1;
271 uint64_t fed0_dbe:1;
272 uint64_t fed0_sbe:1;
273 } s;
274 struct cvmx_fpa_int_sum_s cn30xx;
275 struct cvmx_fpa_int_sum_s cn31xx;
276 struct cvmx_fpa_int_sum_s cn38xx;
277 struct cvmx_fpa_int_sum_s cn38xxp2;
278 struct cvmx_fpa_int_sum_s cn50xx;
279 struct cvmx_fpa_int_sum_s cn52xx;
280 struct cvmx_fpa_int_sum_s cn52xxp1;
281 struct cvmx_fpa_int_sum_s cn56xx;
282 struct cvmx_fpa_int_sum_s cn56xxp1;
283 struct cvmx_fpa_int_sum_s cn58xx;
284 struct cvmx_fpa_int_sum_s cn58xxp1;
285};
286
287union cvmx_fpa_quex_available {
288 uint64_t u64;
289 struct cvmx_fpa_quex_available_s {
290 uint64_t reserved_29_63:35;
291 uint64_t que_siz:29;
292 } s;
293 struct cvmx_fpa_quex_available_s cn30xx;
294 struct cvmx_fpa_quex_available_s cn31xx;
295 struct cvmx_fpa_quex_available_s cn38xx;
296 struct cvmx_fpa_quex_available_s cn38xxp2;
297 struct cvmx_fpa_quex_available_s cn50xx;
298 struct cvmx_fpa_quex_available_s cn52xx;
299 struct cvmx_fpa_quex_available_s cn52xxp1;
300 struct cvmx_fpa_quex_available_s cn56xx;
301 struct cvmx_fpa_quex_available_s cn56xxp1;
302 struct cvmx_fpa_quex_available_s cn58xx;
303 struct cvmx_fpa_quex_available_s cn58xxp1;
304};
305
306union cvmx_fpa_quex_page_index {
307 uint64_t u64;
308 struct cvmx_fpa_quex_page_index_s {
309 uint64_t reserved_25_63:39;
310 uint64_t pg_num:25;
311 } s;
312 struct cvmx_fpa_quex_page_index_s cn30xx;
313 struct cvmx_fpa_quex_page_index_s cn31xx;
314 struct cvmx_fpa_quex_page_index_s cn38xx;
315 struct cvmx_fpa_quex_page_index_s cn38xxp2;
316 struct cvmx_fpa_quex_page_index_s cn50xx;
317 struct cvmx_fpa_quex_page_index_s cn52xx;
318 struct cvmx_fpa_quex_page_index_s cn52xxp1;
319 struct cvmx_fpa_quex_page_index_s cn56xx;
320 struct cvmx_fpa_quex_page_index_s cn56xxp1;
321 struct cvmx_fpa_quex_page_index_s cn58xx;
322 struct cvmx_fpa_quex_page_index_s cn58xxp1;
323};
324
325union cvmx_fpa_que_act {
326 uint64_t u64;
327 struct cvmx_fpa_que_act_s {
328 uint64_t reserved_29_63:35;
329 uint64_t act_que:3;
330 uint64_t act_indx:26;
331 } s;
332 struct cvmx_fpa_que_act_s cn30xx;
333 struct cvmx_fpa_que_act_s cn31xx;
334 struct cvmx_fpa_que_act_s cn38xx;
335 struct cvmx_fpa_que_act_s cn38xxp2;
336 struct cvmx_fpa_que_act_s cn50xx;
337 struct cvmx_fpa_que_act_s cn52xx;
338 struct cvmx_fpa_que_act_s cn52xxp1;
339 struct cvmx_fpa_que_act_s cn56xx;
340 struct cvmx_fpa_que_act_s cn56xxp1;
341 struct cvmx_fpa_que_act_s cn58xx;
342 struct cvmx_fpa_que_act_s cn58xxp1;
343};
344
345union cvmx_fpa_que_exp {
346 uint64_t u64;
347 struct cvmx_fpa_que_exp_s {
348 uint64_t reserved_29_63:35;
349 uint64_t exp_que:3;
350 uint64_t exp_indx:26;
351 } s;
352 struct cvmx_fpa_que_exp_s cn30xx;
353 struct cvmx_fpa_que_exp_s cn31xx;
354 struct cvmx_fpa_que_exp_s cn38xx;
355 struct cvmx_fpa_que_exp_s cn38xxp2;
356 struct cvmx_fpa_que_exp_s cn50xx;
357 struct cvmx_fpa_que_exp_s cn52xx;
358 struct cvmx_fpa_que_exp_s cn52xxp1;
359 struct cvmx_fpa_que_exp_s cn56xx;
360 struct cvmx_fpa_que_exp_s cn56xxp1;
361 struct cvmx_fpa_que_exp_s cn58xx;
362 struct cvmx_fpa_que_exp_s cn58xxp1;
363};
364
365union cvmx_fpa_wart_ctl {
366 uint64_t u64;
367 struct cvmx_fpa_wart_ctl_s {
368 uint64_t reserved_16_63:48;
369 uint64_t ctl:16;
370 } s;
371 struct cvmx_fpa_wart_ctl_s cn30xx;
372 struct cvmx_fpa_wart_ctl_s cn31xx;
373 struct cvmx_fpa_wart_ctl_s cn38xx;
374 struct cvmx_fpa_wart_ctl_s cn38xxp2;
375 struct cvmx_fpa_wart_ctl_s cn50xx;
376 struct cvmx_fpa_wart_ctl_s cn52xx;
377 struct cvmx_fpa_wart_ctl_s cn52xxp1;
378 struct cvmx_fpa_wart_ctl_s cn56xx;
379 struct cvmx_fpa_wart_ctl_s cn56xxp1;
380 struct cvmx_fpa_wart_ctl_s cn58xx;
381 struct cvmx_fpa_wart_ctl_s cn58xxp1;
382};
383
384union cvmx_fpa_wart_status {
385 uint64_t u64;
386 struct cvmx_fpa_wart_status_s {
387 uint64_t reserved_32_63:32;
388 uint64_t status:32;
389 } s;
390 struct cvmx_fpa_wart_status_s cn30xx;
391 struct cvmx_fpa_wart_status_s cn31xx;
392 struct cvmx_fpa_wart_status_s cn38xx;
393 struct cvmx_fpa_wart_status_s cn38xxp2;
394 struct cvmx_fpa_wart_status_s cn50xx;
395 struct cvmx_fpa_wart_status_s cn52xx;
396 struct cvmx_fpa_wart_status_s cn52xxp1;
397 struct cvmx_fpa_wart_status_s cn56xx;
398 struct cvmx_fpa_wart_status_s cn56xxp1;
399 struct cvmx_fpa_wart_status_s cn58xx;
400 struct cvmx_fpa_wart_status_s cn58xxp1;
401};
402
403#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
new file mode 100644
index 00000000000..1f04f965873
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
@@ -0,0 +1,299 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Interface to the hardware Free Pool Allocator.
32 *
33 *
34 */
35
36#ifndef __CVMX_FPA_H__
37#define __CVMX_FPA_H__
38
39#include "cvmx-address.h"
40#include "cvmx-fpa-defs.h"
41
42#define CVMX_FPA_NUM_POOLS 8
43#define CVMX_FPA_MIN_BLOCK_SIZE 128
44#define CVMX_FPA_ALIGNMENT 128
45
46/**
47 * Structure describing the data format used for stores to the FPA.
48 */
49typedef union {
50 uint64_t u64;
51 struct {
52 /*
53 * the (64-bit word) location in scratchpad to write
54 * to (if len != 0)
55 */
56 uint64_t scraddr:8;
57 /* the number of words in the response (0 => no response) */
58 uint64_t len:8;
59 /* the ID of the device on the non-coherent bus */
60 uint64_t did:8;
61 /*
62 * the address that will appear in the first tick on
63 * the NCB bus.
64 */
65 uint64_t addr:40;
66 } s;
67} cvmx_fpa_iobdma_data_t;
68
69/**
70 * Structure describing the current state of a FPA pool.
71 */
72typedef struct {
73 /* Name it was created under */
74 const char *name;
75 /* Size of each block */
76 uint64_t size;
77 /* The base memory address of whole block */
78 void *base;
79 /* The number of elements in the pool at creation */
80 uint64_t starting_element_count;
81} cvmx_fpa_pool_info_t;
82
83/**
84 * Current state of all the pools. Use access functions
85 * instead of using it directly.
86 */
87extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
88
89/* CSR typedefs have been moved to cvmx-csr-*.h */
90
91/**
92 * Return the name of the pool
93 *
94 * @pool: Pool to get the name of
95 * Returns The name
96 */
97static inline const char *cvmx_fpa_get_name(uint64_t pool)
98{
99 return cvmx_fpa_pool_info[pool].name;
100}
101
102/**
103 * Return the base of the pool
104 *
105 * @pool: Pool to get the base of
106 * Returns The base
107 */
108static inline void *cvmx_fpa_get_base(uint64_t pool)
109{
110 return cvmx_fpa_pool_info[pool].base;
111}
112
113/**
114 * Check if a pointer belongs to an FPA pool. Return non-zero
115 * if the supplied pointer is inside the memory controlled by
116 * an FPA pool.
117 *
118 * @pool: Pool to check
119 * @ptr: Pointer to check
120 * Returns Non-zero if pointer is in the pool. Zero if not
121 */
122static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
123{
124 return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
125 ((char *)ptr <
126 ((char *)(cvmx_fpa_pool_info[pool].base)) +
127 cvmx_fpa_pool_info[pool].size *
128 cvmx_fpa_pool_info[pool].starting_element_count));
129}
130
131/**
132 * Enable the FPA for use. Must be performed after any CSR
133 * configuration but before any other FPA functions.
134 */
135static inline void cvmx_fpa_enable(void)
136{
137 union cvmx_fpa_ctl_status status;
138
139 status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
140 if (status.s.enb) {
141 cvmx_dprintf
142 ("Warning: Enabling FPA when FPA already enabled.\n");
143 }
144
145 /*
146 * Do runtime check as we allow pass1 compiled code to run on
147 * pass2 chips.
148 */
149 if (cvmx_octeon_is_pass1()) {
150 union cvmx_fpa_fpfx_marks marks;
151 int i;
152 for (i = 1; i < 8; i++) {
153 marks.u64 =
154 cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
155 marks.s.fpf_wr = 0xe0;
156 cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
157 marks.u64);
158 }
159
160 /* Enforce a 10 cycle delay between config and enable */
161 cvmx_wait(10);
162 }
163
164 /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
165 status.u64 = 0;
166 status.s.enb = 1;
167 cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
168}
169
170/**
171 * Get a new block from the FPA
172 *
173 * @pool: Pool to get the block from
174 * Returns Pointer to the block or NULL on failure
175 */
176static inline void *cvmx_fpa_alloc(uint64_t pool)
177{
178 uint64_t address =
179 cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
180 if (address)
181 return cvmx_phys_to_ptr(address);
182 else
183 return NULL;
184}
185
186/**
187 * Asynchronously get a new block from the FPA
188 *
189 * @scr_addr: Local scratch address to put response in. This is a byte address,
190 * but must be 8 byte aligned.
191 * @pool: Pool to get the block from
192 */
193static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
194{
195 cvmx_fpa_iobdma_data_t data;
196
197 /*
198 * Hardware only uses 64 bit aligned locations, so convert
199 * from byte address to 64-bit index
200 */
201 data.s.scraddr = scr_addr >> 3;
202 data.s.len = 1;
203 data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
204 data.s.addr = 0;
205 cvmx_send_single(data.u64);
206}
207
208/**
209 * Free a block allocated with a FPA pool. Does NOT provide memory
210 * ordering in cases where the memory block was modified by the core.
211 *
212 * @ptr: Block to free
213 * @pool: Pool to put it in
214 * @num_cache_lines:
215 * Cache lines to invalidate
216 */
217static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
218 uint64_t num_cache_lines)
219{
220 cvmx_addr_t newptr;
221 newptr.u64 = cvmx_ptr_to_phys(ptr);
222 newptr.sfilldidspace.didspace =
223 CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
224 /* Prevent GCC from reordering around free */
225 barrier();
226 /* value written is number of cache lines not written back */
227 cvmx_write_io(newptr.u64, num_cache_lines);
228}
229
230/**
231 * Free a block allocated with a FPA pool. Provides required memory
232 * ordering in cases where memory block was modified by core.
233 *
234 * @ptr: Block to free
235 * @pool: Pool to put it in
236 * @num_cache_lines:
237 * Cache lines to invalidate
238 */
239static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
240 uint64_t num_cache_lines)
241{
242 cvmx_addr_t newptr;
243 newptr.u64 = cvmx_ptr_to_phys(ptr);
244 newptr.sfilldidspace.didspace =
245 CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
246 /*
247 * Make sure that any previous writes to memory go out before
248 * we free this buffer. This also serves as a barrier to
249 * prevent GCC from reordering operations to after the
250 * free.
251 */
252 CVMX_SYNCWS;
253 /* value written is number of cache lines not written back */
254 cvmx_write_io(newptr.u64, num_cache_lines);
255}
256
257/**
258 * Setup a FPA pool to control a new block of memory.
259 * This can only be called once per pool. Make sure proper
260 * locking enforces this.
261 *
262 * @pool: Pool to initialize
263 * 0 <= pool < 8
264 * @name: Constant character string to name this pool.
265 * String is not copied.
266 * @buffer: Pointer to the block of memory to use. This must be
267 * accessible by all processors and external hardware.
268 * @block_size: Size for each block controlled by the FPA
269 * @num_blocks: Number of blocks
270 *
271 * Returns 0 on Success,
272 * -1 on failure
273 */
274extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
275 uint64_t block_size, uint64_t num_blocks);
276
277/**
278 * Shutdown a Memory pool and validate that it had all of
279 * the buffers originally placed in it. This should only be
280 * called by one processor after all hardware has finished
281 * using the pool.
282 *
283 * @pool: Pool to shutdown
284 * Returns Zero on success
285 * - Positive is count of missing buffers
286 * - Negative is too many buffers or corrupted pointers
287 */
288extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
289
290/**
291 * Get the size of blocks controlled by the pool
292 * This is resolved to a constant at compile time.
293 *
294 * @pool: Pool to access
295 * Returns Size of the block in bytes
296 */
297uint64_t cvmx_fpa_get_block_size(uint64_t pool);
298
299#endif /* __CVM_FPA_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
new file mode 100644
index 00000000000..946a43a73fd
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
@@ -0,0 +1,2529 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GMXX_DEFS_H__
29#define __CVMX_GMXX_DEFS_H__
30
31#define CVMX_GMXX_BAD_REG(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_GMXX_BIST(block_id) \
34 CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_GMXX_CLK_EN(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_GMXX_HG2_CONTROL(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_GMXX_INF_MODE(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_GMXX_NXA_ADR(block_id) \
42 CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \
44 CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_GMXX_PRTX_CFG(offset, block_id) \
46 CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \
48 CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \
52 CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \
54 CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \
56 CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \
62 CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
63#define CVMX_GMXX_RXX_DECISION(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
65#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \
66 CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
67#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \
68 CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
69#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \
70 CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
71#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \
72 CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
73#define CVMX_GMXX_RXX_IFG(offset, block_id) \
74 CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
75#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \
76 CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
77#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \
78 CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
79#define CVMX_GMXX_RXX_JABBER(offset, block_id) \
80 CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
81#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \
82 CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
83#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \
84 CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
85#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \
86 CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
87#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \
88 CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
89#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \
90 CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
91#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \
92 CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
93#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \
94 CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
95#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \
96 CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
97#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \
98 CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
99#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \
100 CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
101#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \
102 CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
103#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \
104 CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
105#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \
106 CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
107#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \
108 CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
109#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \
110 CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
111#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \
112 CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
113#define CVMX_GMXX_RX_HG2_STATUS(block_id) \
114 CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull))
115#define CVMX_GMXX_RX_PASS_EN(block_id) \
116 CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull))
117#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \
118 CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull))
119#define CVMX_GMXX_RX_PRTS(block_id) \
120 CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull))
121#define CVMX_GMXX_RX_PRT_INFO(block_id) \
122 CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull))
123#define CVMX_GMXX_RX_TX_STATUS(block_id) \
124 CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull))
125#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \
126 CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull))
127#define CVMX_GMXX_RX_XAUI_CTL(block_id) \
128 CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull))
129#define CVMX_GMXX_SMACX(offset, block_id) \
130 CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
131#define CVMX_GMXX_STAT_BP(block_id) \
132 CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull))
133#define CVMX_GMXX_TXX_APPEND(offset, block_id) \
134 CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
135#define CVMX_GMXX_TXX_BURST(offset, block_id) \
136 CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
137#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \
138 CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
139#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \
140 CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
141#define CVMX_GMXX_TXX_CLK(offset, block_id) \
142 CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
143#define CVMX_GMXX_TXX_CTL(offset, block_id) \
144 CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
145#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \
146 CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
147#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \
148 CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
149#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \
150 CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
151#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \
152 CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
153#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \
154 CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
155#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \
156 CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
157#define CVMX_GMXX_TXX_SLOT(offset, block_id) \
158 CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
159#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \
160 CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
161#define CVMX_GMXX_TXX_STAT0(offset, block_id) \
162 CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
163#define CVMX_GMXX_TXX_STAT1(offset, block_id) \
164 CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
165#define CVMX_GMXX_TXX_STAT2(offset, block_id) \
166 CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
167#define CVMX_GMXX_TXX_STAT3(offset, block_id) \
168 CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
169#define CVMX_GMXX_TXX_STAT4(offset, block_id) \
170 CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
171#define CVMX_GMXX_TXX_STAT5(offset, block_id) \
172 CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
173#define CVMX_GMXX_TXX_STAT6(offset, block_id) \
174 CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
175#define CVMX_GMXX_TXX_STAT7(offset, block_id) \
176 CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
177#define CVMX_GMXX_TXX_STAT8(offset, block_id) \
178 CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
179#define CVMX_GMXX_TXX_STAT9(offset, block_id) \
180 CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
181#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \
182 CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
183#define CVMX_GMXX_TXX_THRESH(offset, block_id) \
184 CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
185#define CVMX_GMXX_TX_BP(block_id) \
186 CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull))
187#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \
188 CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull))
189#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \
190 CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull))
191#define CVMX_GMXX_TX_CORRUPT(block_id) \
192 CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull))
193#define CVMX_GMXX_TX_HG2_REG1(block_id) \
194 CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull))
195#define CVMX_GMXX_TX_HG2_REG2(block_id) \
196 CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull))
197#define CVMX_GMXX_TX_IFG(block_id) \
198 CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull))
199#define CVMX_GMXX_TX_INT_EN(block_id) \
200 CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull))
201#define CVMX_GMXX_TX_INT_REG(block_id) \
202 CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull))
203#define CVMX_GMXX_TX_JAM(block_id) \
204 CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull))
205#define CVMX_GMXX_TX_LFSR(block_id) \
206 CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull))
207#define CVMX_GMXX_TX_OVR_BP(block_id) \
208 CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull))
209#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \
210 CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull))
211#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \
212 CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull))
213#define CVMX_GMXX_TX_PRTS(block_id) \
214 CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull))
215#define CVMX_GMXX_TX_SPI_CTL(block_id) \
216 CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull))
217#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \
218 CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull))
219#define CVMX_GMXX_TX_SPI_MAX(block_id) \
220 CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull))
221#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \
222 CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
223#define CVMX_GMXX_TX_SPI_THRESH(block_id) \
224 CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull))
225#define CVMX_GMXX_TX_XAUI_CTL(block_id) \
226 CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull))
227#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \
228 CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull))
229
230union cvmx_gmxx_bad_reg {
231 uint64_t u64;
232 struct cvmx_gmxx_bad_reg_s {
233 uint64_t reserved_31_63:33;
234 uint64_t inb_nxa:4;
235 uint64_t statovr:1;
236 uint64_t loststat:4;
237 uint64_t reserved_18_21:4;
238 uint64_t out_ovr:16;
239 uint64_t ncb_ovr:1;
240 uint64_t out_col:1;
241 } s;
242 struct cvmx_gmxx_bad_reg_cn30xx {
243 uint64_t reserved_31_63:33;
244 uint64_t inb_nxa:4;
245 uint64_t statovr:1;
246 uint64_t reserved_25_25:1;
247 uint64_t loststat:3;
248 uint64_t reserved_5_21:17;
249 uint64_t out_ovr:3;
250 uint64_t reserved_0_1:2;
251 } cn30xx;
252 struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
253 struct cvmx_gmxx_bad_reg_s cn38xx;
254 struct cvmx_gmxx_bad_reg_s cn38xxp2;
255 struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
256 struct cvmx_gmxx_bad_reg_cn52xx {
257 uint64_t reserved_31_63:33;
258 uint64_t inb_nxa:4;
259 uint64_t statovr:1;
260 uint64_t loststat:4;
261 uint64_t reserved_6_21:16;
262 uint64_t out_ovr:4;
263 uint64_t reserved_0_1:2;
264 } cn52xx;
265 struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
266 struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
267 struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
268 struct cvmx_gmxx_bad_reg_s cn58xx;
269 struct cvmx_gmxx_bad_reg_s cn58xxp1;
270};
271
272union cvmx_gmxx_bist {
273 uint64_t u64;
274 struct cvmx_gmxx_bist_s {
275 uint64_t reserved_17_63:47;
276 uint64_t status:17;
277 } s;
278 struct cvmx_gmxx_bist_cn30xx {
279 uint64_t reserved_10_63:54;
280 uint64_t status:10;
281 } cn30xx;
282 struct cvmx_gmxx_bist_cn30xx cn31xx;
283 struct cvmx_gmxx_bist_cn30xx cn38xx;
284 struct cvmx_gmxx_bist_cn30xx cn38xxp2;
285 struct cvmx_gmxx_bist_cn50xx {
286 uint64_t reserved_12_63:52;
287 uint64_t status:12;
288 } cn50xx;
289 struct cvmx_gmxx_bist_cn52xx {
290 uint64_t reserved_16_63:48;
291 uint64_t status:16;
292 } cn52xx;
293 struct cvmx_gmxx_bist_cn52xx cn52xxp1;
294 struct cvmx_gmxx_bist_cn52xx cn56xx;
295 struct cvmx_gmxx_bist_cn52xx cn56xxp1;
296 struct cvmx_gmxx_bist_s cn58xx;
297 struct cvmx_gmxx_bist_s cn58xxp1;
298};
299
300union cvmx_gmxx_clk_en {
301 uint64_t u64;
302 struct cvmx_gmxx_clk_en_s {
303 uint64_t reserved_1_63:63;
304 uint64_t clk_en:1;
305 } s;
306 struct cvmx_gmxx_clk_en_s cn52xx;
307 struct cvmx_gmxx_clk_en_s cn52xxp1;
308 struct cvmx_gmxx_clk_en_s cn56xx;
309 struct cvmx_gmxx_clk_en_s cn56xxp1;
310};
311
312union cvmx_gmxx_hg2_control {
313 uint64_t u64;
314 struct cvmx_gmxx_hg2_control_s {
315 uint64_t reserved_19_63:45;
316 uint64_t hg2tx_en:1;
317 uint64_t hg2rx_en:1;
318 uint64_t phys_en:1;
319 uint64_t logl_en:16;
320 } s;
321 struct cvmx_gmxx_hg2_control_s cn52xx;
322 struct cvmx_gmxx_hg2_control_s cn52xxp1;
323 struct cvmx_gmxx_hg2_control_s cn56xx;
324};
325
326union cvmx_gmxx_inf_mode {
327 uint64_t u64;
328 struct cvmx_gmxx_inf_mode_s {
329 uint64_t reserved_10_63:54;
330 uint64_t speed:2;
331 uint64_t reserved_6_7:2;
332 uint64_t mode:2;
333 uint64_t reserved_3_3:1;
334 uint64_t p0mii:1;
335 uint64_t en:1;
336 uint64_t type:1;
337 } s;
338 struct cvmx_gmxx_inf_mode_cn30xx {
339 uint64_t reserved_3_63:61;
340 uint64_t p0mii:1;
341 uint64_t en:1;
342 uint64_t type:1;
343 } cn30xx;
344 struct cvmx_gmxx_inf_mode_cn31xx {
345 uint64_t reserved_2_63:62;
346 uint64_t en:1;
347 uint64_t type:1;
348 } cn31xx;
349 struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
350 struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
351 struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
352 struct cvmx_gmxx_inf_mode_cn52xx {
353 uint64_t reserved_10_63:54;
354 uint64_t speed:2;
355 uint64_t reserved_6_7:2;
356 uint64_t mode:2;
357 uint64_t reserved_2_3:2;
358 uint64_t en:1;
359 uint64_t type:1;
360 } cn52xx;
361 struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
362 struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
363 struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
364 struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
365 struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
366};
367
368union cvmx_gmxx_nxa_adr {
369 uint64_t u64;
370 struct cvmx_gmxx_nxa_adr_s {
371 uint64_t reserved_6_63:58;
372 uint64_t prt:6;
373 } s;
374 struct cvmx_gmxx_nxa_adr_s cn30xx;
375 struct cvmx_gmxx_nxa_adr_s cn31xx;
376 struct cvmx_gmxx_nxa_adr_s cn38xx;
377 struct cvmx_gmxx_nxa_adr_s cn38xxp2;
378 struct cvmx_gmxx_nxa_adr_s cn50xx;
379 struct cvmx_gmxx_nxa_adr_s cn52xx;
380 struct cvmx_gmxx_nxa_adr_s cn52xxp1;
381 struct cvmx_gmxx_nxa_adr_s cn56xx;
382 struct cvmx_gmxx_nxa_adr_s cn56xxp1;
383 struct cvmx_gmxx_nxa_adr_s cn58xx;
384 struct cvmx_gmxx_nxa_adr_s cn58xxp1;
385};
386
387union cvmx_gmxx_prtx_cbfc_ctl {
388 uint64_t u64;
389 struct cvmx_gmxx_prtx_cbfc_ctl_s {
390 uint64_t phys_en:16;
391 uint64_t logl_en:16;
392 uint64_t phys_bp:16;
393 uint64_t reserved_4_15:12;
394 uint64_t bck_en:1;
395 uint64_t drp_en:1;
396 uint64_t tx_en:1;
397 uint64_t rx_en:1;
398 } s;
399 struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
400 struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
401};
402
403union cvmx_gmxx_prtx_cfg {
404 uint64_t u64;
405 struct cvmx_gmxx_prtx_cfg_s {
406 uint64_t reserved_14_63:50;
407 uint64_t tx_idle:1;
408 uint64_t rx_idle:1;
409 uint64_t reserved_9_11:3;
410 uint64_t speed_msb:1;
411 uint64_t reserved_4_7:4;
412 uint64_t slottime:1;
413 uint64_t duplex:1;
414 uint64_t speed:1;
415 uint64_t en:1;
416 } s;
417 struct cvmx_gmxx_prtx_cfg_cn30xx {
418 uint64_t reserved_4_63:60;
419 uint64_t slottime:1;
420 uint64_t duplex:1;
421 uint64_t speed:1;
422 uint64_t en:1;
423 } cn30xx;
424 struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
425 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
426 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
427 struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
428 struct cvmx_gmxx_prtx_cfg_s cn52xx;
429 struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
430 struct cvmx_gmxx_prtx_cfg_s cn56xx;
431 struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
432 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
433 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
434};
435
436union cvmx_gmxx_rxx_adr_cam0 {
437 uint64_t u64;
438 struct cvmx_gmxx_rxx_adr_cam0_s {
439 uint64_t adr:64;
440 } s;
441 struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
442 struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
443 struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
444 struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
445 struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
446 struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
447 struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
448 struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
449 struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
450 struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
451 struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
452};
453
454union cvmx_gmxx_rxx_adr_cam1 {
455 uint64_t u64;
456 struct cvmx_gmxx_rxx_adr_cam1_s {
457 uint64_t adr:64;
458 } s;
459 struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
460 struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
461 struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
462 struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
463 struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
464 struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
465 struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
466 struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
467 struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
468 struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
469 struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
470};
471
472union cvmx_gmxx_rxx_adr_cam2 {
473 uint64_t u64;
474 struct cvmx_gmxx_rxx_adr_cam2_s {
475 uint64_t adr:64;
476 } s;
477 struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
478 struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
479 struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
480 struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
481 struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
482 struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
483 struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
484 struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
485 struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
486 struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
487 struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
488};
489
490union cvmx_gmxx_rxx_adr_cam3 {
491 uint64_t u64;
492 struct cvmx_gmxx_rxx_adr_cam3_s {
493 uint64_t adr:64;
494 } s;
495 struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
496 struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
497 struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
498 struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
499 struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
500 struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
501 struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
502 struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
503 struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
504 struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
505 struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
506};
507
508union cvmx_gmxx_rxx_adr_cam4 {
509 uint64_t u64;
510 struct cvmx_gmxx_rxx_adr_cam4_s {
511 uint64_t adr:64;
512 } s;
513 struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
514 struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
515 struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
516 struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
517 struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
518 struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
519 struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
520 struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
521 struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
522 struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
523 struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
524};
525
526union cvmx_gmxx_rxx_adr_cam5 {
527 uint64_t u64;
528 struct cvmx_gmxx_rxx_adr_cam5_s {
529 uint64_t adr:64;
530 } s;
531 struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
532 struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
533 struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
534 struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
535 struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
536 struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
537 struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
538 struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
539 struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
540 struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
541 struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
542};
543
544union cvmx_gmxx_rxx_adr_cam_en {
545 uint64_t u64;
546 struct cvmx_gmxx_rxx_adr_cam_en_s {
547 uint64_t reserved_8_63:56;
548 uint64_t en:8;
549 } s;
550 struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
551 struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
552 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
553 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
554 struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
555 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
556 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
557 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
558 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
559 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
560 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
561};
562
563union cvmx_gmxx_rxx_adr_ctl {
564 uint64_t u64;
565 struct cvmx_gmxx_rxx_adr_ctl_s {
566 uint64_t reserved_4_63:60;
567 uint64_t cam_mode:1;
568 uint64_t mcst:2;
569 uint64_t bcst:1;
570 } s;
571 struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
572 struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
573 struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
574 struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
575 struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
576 struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
577 struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
578 struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
579 struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
580 struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
581 struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
582};
583
584union cvmx_gmxx_rxx_decision {
585 uint64_t u64;
586 struct cvmx_gmxx_rxx_decision_s {
587 uint64_t reserved_5_63:59;
588 uint64_t cnt:5;
589 } s;
590 struct cvmx_gmxx_rxx_decision_s cn30xx;
591 struct cvmx_gmxx_rxx_decision_s cn31xx;
592 struct cvmx_gmxx_rxx_decision_s cn38xx;
593 struct cvmx_gmxx_rxx_decision_s cn38xxp2;
594 struct cvmx_gmxx_rxx_decision_s cn50xx;
595 struct cvmx_gmxx_rxx_decision_s cn52xx;
596 struct cvmx_gmxx_rxx_decision_s cn52xxp1;
597 struct cvmx_gmxx_rxx_decision_s cn56xx;
598 struct cvmx_gmxx_rxx_decision_s cn56xxp1;
599 struct cvmx_gmxx_rxx_decision_s cn58xx;
600 struct cvmx_gmxx_rxx_decision_s cn58xxp1;
601};
602
603union cvmx_gmxx_rxx_frm_chk {
604 uint64_t u64;
605 struct cvmx_gmxx_rxx_frm_chk_s {
606 uint64_t reserved_10_63:54;
607 uint64_t niberr:1;
608 uint64_t skperr:1;
609 uint64_t rcverr:1;
610 uint64_t lenerr:1;
611 uint64_t alnerr:1;
612 uint64_t fcserr:1;
613 uint64_t jabber:1;
614 uint64_t maxerr:1;
615 uint64_t carext:1;
616 uint64_t minerr:1;
617 } s;
618 struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
619 struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
620 struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
621 struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
622 struct cvmx_gmxx_rxx_frm_chk_cn50xx {
623 uint64_t reserved_10_63:54;
624 uint64_t niberr:1;
625 uint64_t skperr:1;
626 uint64_t rcverr:1;
627 uint64_t reserved_6_6:1;
628 uint64_t alnerr:1;
629 uint64_t fcserr:1;
630 uint64_t jabber:1;
631 uint64_t reserved_2_2:1;
632 uint64_t carext:1;
633 uint64_t reserved_0_0:1;
634 } cn50xx;
635 struct cvmx_gmxx_rxx_frm_chk_cn52xx {
636 uint64_t reserved_9_63:55;
637 uint64_t skperr:1;
638 uint64_t rcverr:1;
639 uint64_t reserved_5_6:2;
640 uint64_t fcserr:1;
641 uint64_t jabber:1;
642 uint64_t reserved_2_2:1;
643 uint64_t carext:1;
644 uint64_t reserved_0_0:1;
645 } cn52xx;
646 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
647 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
648 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
649 struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
650 struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
651};
652
653union cvmx_gmxx_rxx_frm_ctl {
654 uint64_t u64;
655 struct cvmx_gmxx_rxx_frm_ctl_s {
656 uint64_t reserved_11_63:53;
657 uint64_t null_dis:1;
658 uint64_t pre_align:1;
659 uint64_t pad_len:1;
660 uint64_t vlan_len:1;
661 uint64_t pre_free:1;
662 uint64_t ctl_smac:1;
663 uint64_t ctl_mcst:1;
664 uint64_t ctl_bck:1;
665 uint64_t ctl_drp:1;
666 uint64_t pre_strp:1;
667 uint64_t pre_chk:1;
668 } s;
669 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
670 uint64_t reserved_9_63:55;
671 uint64_t pad_len:1;
672 uint64_t vlan_len:1;
673 uint64_t pre_free:1;
674 uint64_t ctl_smac:1;
675 uint64_t ctl_mcst:1;
676 uint64_t ctl_bck:1;
677 uint64_t ctl_drp:1;
678 uint64_t pre_strp:1;
679 uint64_t pre_chk:1;
680 } cn30xx;
681 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
682 uint64_t reserved_8_63:56;
683 uint64_t vlan_len:1;
684 uint64_t pre_free:1;
685 uint64_t ctl_smac:1;
686 uint64_t ctl_mcst:1;
687 uint64_t ctl_bck:1;
688 uint64_t ctl_drp:1;
689 uint64_t pre_strp:1;
690 uint64_t pre_chk:1;
691 } cn31xx;
692 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
693 struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
694 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
695 uint64_t reserved_11_63:53;
696 uint64_t null_dis:1;
697 uint64_t pre_align:1;
698 uint64_t reserved_7_8:2;
699 uint64_t pre_free:1;
700 uint64_t ctl_smac:1;
701 uint64_t ctl_mcst:1;
702 uint64_t ctl_bck:1;
703 uint64_t ctl_drp:1;
704 uint64_t pre_strp:1;
705 uint64_t pre_chk:1;
706 } cn50xx;
707 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
708 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
709 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
710 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
711 uint64_t reserved_10_63:54;
712 uint64_t pre_align:1;
713 uint64_t reserved_7_8:2;
714 uint64_t pre_free:1;
715 uint64_t ctl_smac:1;
716 uint64_t ctl_mcst:1;
717 uint64_t ctl_bck:1;
718 uint64_t ctl_drp:1;
719 uint64_t pre_strp:1;
720 uint64_t pre_chk:1;
721 } cn56xxp1;
722 struct cvmx_gmxx_rxx_frm_ctl_s cn58xx;
723 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
724};
725
726union cvmx_gmxx_rxx_frm_max {
727 uint64_t u64;
728 struct cvmx_gmxx_rxx_frm_max_s {
729 uint64_t reserved_16_63:48;
730 uint64_t len:16;
731 } s;
732 struct cvmx_gmxx_rxx_frm_max_s cn30xx;
733 struct cvmx_gmxx_rxx_frm_max_s cn31xx;
734 struct cvmx_gmxx_rxx_frm_max_s cn38xx;
735 struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
736 struct cvmx_gmxx_rxx_frm_max_s cn58xx;
737 struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
738};
739
740union cvmx_gmxx_rxx_frm_min {
741 uint64_t u64;
742 struct cvmx_gmxx_rxx_frm_min_s {
743 uint64_t reserved_16_63:48;
744 uint64_t len:16;
745 } s;
746 struct cvmx_gmxx_rxx_frm_min_s cn30xx;
747 struct cvmx_gmxx_rxx_frm_min_s cn31xx;
748 struct cvmx_gmxx_rxx_frm_min_s cn38xx;
749 struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
750 struct cvmx_gmxx_rxx_frm_min_s cn58xx;
751 struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
752};
753
754union cvmx_gmxx_rxx_ifg {
755 uint64_t u64;
756 struct cvmx_gmxx_rxx_ifg_s {
757 uint64_t reserved_4_63:60;
758 uint64_t ifg:4;
759 } s;
760 struct cvmx_gmxx_rxx_ifg_s cn30xx;
761 struct cvmx_gmxx_rxx_ifg_s cn31xx;
762 struct cvmx_gmxx_rxx_ifg_s cn38xx;
763 struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
764 struct cvmx_gmxx_rxx_ifg_s cn50xx;
765 struct cvmx_gmxx_rxx_ifg_s cn52xx;
766 struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
767 struct cvmx_gmxx_rxx_ifg_s cn56xx;
768 struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
769 struct cvmx_gmxx_rxx_ifg_s cn58xx;
770 struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
771};
772
773union cvmx_gmxx_rxx_int_en {
774 uint64_t u64;
775 struct cvmx_gmxx_rxx_int_en_s {
776 uint64_t reserved_29_63:35;
777 uint64_t hg2cc:1;
778 uint64_t hg2fld:1;
779 uint64_t undat:1;
780 uint64_t uneop:1;
781 uint64_t unsop:1;
782 uint64_t bad_term:1;
783 uint64_t bad_seq:1;
784 uint64_t rem_fault:1;
785 uint64_t loc_fault:1;
786 uint64_t pause_drp:1;
787 uint64_t phy_dupx:1;
788 uint64_t phy_spd:1;
789 uint64_t phy_link:1;
790 uint64_t ifgerr:1;
791 uint64_t coldet:1;
792 uint64_t falerr:1;
793 uint64_t rsverr:1;
794 uint64_t pcterr:1;
795 uint64_t ovrerr:1;
796 uint64_t niberr:1;
797 uint64_t skperr:1;
798 uint64_t rcverr:1;
799 uint64_t lenerr:1;
800 uint64_t alnerr:1;
801 uint64_t fcserr:1;
802 uint64_t jabber:1;
803 uint64_t maxerr:1;
804 uint64_t carext:1;
805 uint64_t minerr:1;
806 } s;
807 struct cvmx_gmxx_rxx_int_en_cn30xx {
808 uint64_t reserved_19_63:45;
809 uint64_t phy_dupx:1;
810 uint64_t phy_spd:1;
811 uint64_t phy_link:1;
812 uint64_t ifgerr:1;
813 uint64_t coldet:1;
814 uint64_t falerr:1;
815 uint64_t rsverr:1;
816 uint64_t pcterr:1;
817 uint64_t ovrerr:1;
818 uint64_t niberr:1;
819 uint64_t skperr:1;
820 uint64_t rcverr:1;
821 uint64_t lenerr:1;
822 uint64_t alnerr:1;
823 uint64_t fcserr:1;
824 uint64_t jabber:1;
825 uint64_t maxerr:1;
826 uint64_t carext:1;
827 uint64_t minerr:1;
828 } cn30xx;
829 struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
830 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
831 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
832 struct cvmx_gmxx_rxx_int_en_cn50xx {
833 uint64_t reserved_20_63:44;
834 uint64_t pause_drp:1;
835 uint64_t phy_dupx:1;
836 uint64_t phy_spd:1;
837 uint64_t phy_link:1;
838 uint64_t ifgerr:1;
839 uint64_t coldet:1;
840 uint64_t falerr:1;
841 uint64_t rsverr:1;
842 uint64_t pcterr:1;
843 uint64_t ovrerr:1;
844 uint64_t niberr:1;
845 uint64_t skperr:1;
846 uint64_t rcverr:1;
847 uint64_t reserved_6_6:1;
848 uint64_t alnerr:1;
849 uint64_t fcserr:1;
850 uint64_t jabber:1;
851 uint64_t reserved_2_2:1;
852 uint64_t carext:1;
853 uint64_t reserved_0_0:1;
854 } cn50xx;
855 struct cvmx_gmxx_rxx_int_en_cn52xx {
856 uint64_t reserved_29_63:35;
857 uint64_t hg2cc:1;
858 uint64_t hg2fld:1;
859 uint64_t undat:1;
860 uint64_t uneop:1;
861 uint64_t unsop:1;
862 uint64_t bad_term:1;
863 uint64_t bad_seq:1;
864 uint64_t rem_fault:1;
865 uint64_t loc_fault:1;
866 uint64_t pause_drp:1;
867 uint64_t reserved_16_18:3;
868 uint64_t ifgerr:1;
869 uint64_t coldet:1;
870 uint64_t falerr:1;
871 uint64_t rsverr:1;
872 uint64_t pcterr:1;
873 uint64_t ovrerr:1;
874 uint64_t reserved_9_9:1;
875 uint64_t skperr:1;
876 uint64_t rcverr:1;
877 uint64_t reserved_5_6:2;
878 uint64_t fcserr:1;
879 uint64_t jabber:1;
880 uint64_t reserved_2_2:1;
881 uint64_t carext:1;
882 uint64_t reserved_0_0:1;
883 } cn52xx;
884 struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
885 struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
886 struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
887 uint64_t reserved_27_63:37;
888 uint64_t undat:1;
889 uint64_t uneop:1;
890 uint64_t unsop:1;
891 uint64_t bad_term:1;
892 uint64_t bad_seq:1;
893 uint64_t rem_fault:1;
894 uint64_t loc_fault:1;
895 uint64_t pause_drp:1;
896 uint64_t reserved_16_18:3;
897 uint64_t ifgerr:1;
898 uint64_t coldet:1;
899 uint64_t falerr:1;
900 uint64_t rsverr:1;
901 uint64_t pcterr:1;
902 uint64_t ovrerr:1;
903 uint64_t reserved_9_9:1;
904 uint64_t skperr:1;
905 uint64_t rcverr:1;
906 uint64_t reserved_5_6:2;
907 uint64_t fcserr:1;
908 uint64_t jabber:1;
909 uint64_t reserved_2_2:1;
910 uint64_t carext:1;
911 uint64_t reserved_0_0:1;
912 } cn56xxp1;
913 struct cvmx_gmxx_rxx_int_en_cn58xx {
914 uint64_t reserved_20_63:44;
915 uint64_t pause_drp:1;
916 uint64_t phy_dupx:1;
917 uint64_t phy_spd:1;
918 uint64_t phy_link:1;
919 uint64_t ifgerr:1;
920 uint64_t coldet:1;
921 uint64_t falerr:1;
922 uint64_t rsverr:1;
923 uint64_t pcterr:1;
924 uint64_t ovrerr:1;
925 uint64_t niberr:1;
926 uint64_t skperr:1;
927 uint64_t rcverr:1;
928 uint64_t lenerr:1;
929 uint64_t alnerr:1;
930 uint64_t fcserr:1;
931 uint64_t jabber:1;
932 uint64_t maxerr:1;
933 uint64_t carext:1;
934 uint64_t minerr:1;
935 } cn58xx;
936 struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
937};
938
939union cvmx_gmxx_rxx_int_reg {
940 uint64_t u64;
941 struct cvmx_gmxx_rxx_int_reg_s {
942 uint64_t reserved_29_63:35;
943 uint64_t hg2cc:1;
944 uint64_t hg2fld:1;
945 uint64_t undat:1;
946 uint64_t uneop:1;
947 uint64_t unsop:1;
948 uint64_t bad_term:1;
949 uint64_t bad_seq:1;
950 uint64_t rem_fault:1;
951 uint64_t loc_fault:1;
952 uint64_t pause_drp:1;
953 uint64_t phy_dupx:1;
954 uint64_t phy_spd:1;
955 uint64_t phy_link:1;
956 uint64_t ifgerr:1;
957 uint64_t coldet:1;
958 uint64_t falerr:1;
959 uint64_t rsverr:1;
960 uint64_t pcterr:1;
961 uint64_t ovrerr:1;
962 uint64_t niberr:1;
963 uint64_t skperr:1;
964 uint64_t rcverr:1;
965 uint64_t lenerr:1;
966 uint64_t alnerr:1;
967 uint64_t fcserr:1;
968 uint64_t jabber:1;
969 uint64_t maxerr:1;
970 uint64_t carext:1;
971 uint64_t minerr:1;
972 } s;
973 struct cvmx_gmxx_rxx_int_reg_cn30xx {
974 uint64_t reserved_19_63:45;
975 uint64_t phy_dupx:1;
976 uint64_t phy_spd:1;
977 uint64_t phy_link:1;
978 uint64_t ifgerr:1;
979 uint64_t coldet:1;
980 uint64_t falerr:1;
981 uint64_t rsverr:1;
982 uint64_t pcterr:1;
983 uint64_t ovrerr:1;
984 uint64_t niberr:1;
985 uint64_t skperr:1;
986 uint64_t rcverr:1;
987 uint64_t lenerr:1;
988 uint64_t alnerr:1;
989 uint64_t fcserr:1;
990 uint64_t jabber:1;
991 uint64_t maxerr:1;
992 uint64_t carext:1;
993 uint64_t minerr:1;
994 } cn30xx;
995 struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
996 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
997 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
998 struct cvmx_gmxx_rxx_int_reg_cn50xx {
999 uint64_t reserved_20_63:44;
1000 uint64_t pause_drp:1;
1001 uint64_t phy_dupx:1;
1002 uint64_t phy_spd:1;
1003 uint64_t phy_link:1;
1004 uint64_t ifgerr:1;
1005 uint64_t coldet:1;
1006 uint64_t falerr:1;
1007 uint64_t rsverr:1;
1008 uint64_t pcterr:1;
1009 uint64_t ovrerr:1;
1010 uint64_t niberr:1;
1011 uint64_t skperr:1;
1012 uint64_t rcverr:1;
1013 uint64_t reserved_6_6:1;
1014 uint64_t alnerr:1;
1015 uint64_t fcserr:1;
1016 uint64_t jabber:1;
1017 uint64_t reserved_2_2:1;
1018 uint64_t carext:1;
1019 uint64_t reserved_0_0:1;
1020 } cn50xx;
1021 struct cvmx_gmxx_rxx_int_reg_cn52xx {
1022 uint64_t reserved_29_63:35;
1023 uint64_t hg2cc:1;
1024 uint64_t hg2fld:1;
1025 uint64_t undat:1;
1026 uint64_t uneop:1;
1027 uint64_t unsop:1;
1028 uint64_t bad_term:1;
1029 uint64_t bad_seq:1;
1030 uint64_t rem_fault:1;
1031 uint64_t loc_fault:1;
1032 uint64_t pause_drp:1;
1033 uint64_t reserved_16_18:3;
1034 uint64_t ifgerr:1;
1035 uint64_t coldet:1;
1036 uint64_t falerr:1;
1037 uint64_t rsverr:1;
1038 uint64_t pcterr:1;
1039 uint64_t ovrerr:1;
1040 uint64_t reserved_9_9:1;
1041 uint64_t skperr:1;
1042 uint64_t rcverr:1;
1043 uint64_t reserved_5_6:2;
1044 uint64_t fcserr:1;
1045 uint64_t jabber:1;
1046 uint64_t reserved_2_2:1;
1047 uint64_t carext:1;
1048 uint64_t reserved_0_0:1;
1049 } cn52xx;
1050 struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
1051 struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
1052 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
1053 uint64_t reserved_27_63:37;
1054 uint64_t undat:1;
1055 uint64_t uneop:1;
1056 uint64_t unsop:1;
1057 uint64_t bad_term:1;
1058 uint64_t bad_seq:1;
1059 uint64_t rem_fault:1;
1060 uint64_t loc_fault:1;
1061 uint64_t pause_drp:1;
1062 uint64_t reserved_16_18:3;
1063 uint64_t ifgerr:1;
1064 uint64_t coldet:1;
1065 uint64_t falerr:1;
1066 uint64_t rsverr:1;
1067 uint64_t pcterr:1;
1068 uint64_t ovrerr:1;
1069 uint64_t reserved_9_9:1;
1070 uint64_t skperr:1;
1071 uint64_t rcverr:1;
1072 uint64_t reserved_5_6:2;
1073 uint64_t fcserr:1;
1074 uint64_t jabber:1;
1075 uint64_t reserved_2_2:1;
1076 uint64_t carext:1;
1077 uint64_t reserved_0_0:1;
1078 } cn56xxp1;
1079 struct cvmx_gmxx_rxx_int_reg_cn58xx {
1080 uint64_t reserved_20_63:44;
1081 uint64_t pause_drp:1;
1082 uint64_t phy_dupx:1;
1083 uint64_t phy_spd:1;
1084 uint64_t phy_link:1;
1085 uint64_t ifgerr:1;
1086 uint64_t coldet:1;
1087 uint64_t falerr:1;
1088 uint64_t rsverr:1;
1089 uint64_t pcterr:1;
1090 uint64_t ovrerr:1;
1091 uint64_t niberr:1;
1092 uint64_t skperr:1;
1093 uint64_t rcverr:1;
1094 uint64_t lenerr:1;
1095 uint64_t alnerr:1;
1096 uint64_t fcserr:1;
1097 uint64_t jabber:1;
1098 uint64_t maxerr:1;
1099 uint64_t carext:1;
1100 uint64_t minerr:1;
1101 } cn58xx;
1102 struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
1103};
1104
1105union cvmx_gmxx_rxx_jabber {
1106 uint64_t u64;
1107 struct cvmx_gmxx_rxx_jabber_s {
1108 uint64_t reserved_16_63:48;
1109 uint64_t cnt:16;
1110 } s;
1111 struct cvmx_gmxx_rxx_jabber_s cn30xx;
1112 struct cvmx_gmxx_rxx_jabber_s cn31xx;
1113 struct cvmx_gmxx_rxx_jabber_s cn38xx;
1114 struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
1115 struct cvmx_gmxx_rxx_jabber_s cn50xx;
1116 struct cvmx_gmxx_rxx_jabber_s cn52xx;
1117 struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
1118 struct cvmx_gmxx_rxx_jabber_s cn56xx;
1119 struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
1120 struct cvmx_gmxx_rxx_jabber_s cn58xx;
1121 struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
1122};
1123
1124union cvmx_gmxx_rxx_pause_drop_time {
1125 uint64_t u64;
1126 struct cvmx_gmxx_rxx_pause_drop_time_s {
1127 uint64_t reserved_16_63:48;
1128 uint64_t status:16;
1129 } s;
1130 struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
1131 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
1132 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
1133 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
1134 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
1135 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
1136 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
1137};
1138
1139union cvmx_gmxx_rxx_rx_inbnd {
1140 uint64_t u64;
1141 struct cvmx_gmxx_rxx_rx_inbnd_s {
1142 uint64_t reserved_4_63:60;
1143 uint64_t duplex:1;
1144 uint64_t speed:2;
1145 uint64_t status:1;
1146 } s;
1147 struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
1148 struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
1149 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
1150 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
1151 struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
1152 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
1153 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
1154};
1155
1156union cvmx_gmxx_rxx_stats_ctl {
1157 uint64_t u64;
1158 struct cvmx_gmxx_rxx_stats_ctl_s {
1159 uint64_t reserved_1_63:63;
1160 uint64_t rd_clr:1;
1161 } s;
1162 struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
1163 struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
1164 struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
1165 struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
1166 struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
1167 struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
1168 struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
1169 struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
1170 struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
1171 struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
1172 struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
1173};
1174
1175union cvmx_gmxx_rxx_stats_octs {
1176 uint64_t u64;
1177 struct cvmx_gmxx_rxx_stats_octs_s {
1178 uint64_t reserved_48_63:16;
1179 uint64_t cnt:48;
1180 } s;
1181 struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
1182 struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
1183 struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
1184 struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
1185 struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
1186 struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
1187 struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
1188 struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
1189 struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
1190 struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
1191 struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
1192};
1193
1194union cvmx_gmxx_rxx_stats_octs_ctl {
1195 uint64_t u64;
1196 struct cvmx_gmxx_rxx_stats_octs_ctl_s {
1197 uint64_t reserved_48_63:16;
1198 uint64_t cnt:48;
1199 } s;
1200 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
1201 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
1202 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
1203 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
1204 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
1205 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
1206 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
1207 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
1208 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
1209 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
1210 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
1211};
1212
1213union cvmx_gmxx_rxx_stats_octs_dmac {
1214 uint64_t u64;
1215 struct cvmx_gmxx_rxx_stats_octs_dmac_s {
1216 uint64_t reserved_48_63:16;
1217 uint64_t cnt:48;
1218 } s;
1219 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
1220 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
1221 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
1222 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
1223 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
1224 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
1225 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
1226 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
1227 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
1228 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
1229 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
1230};
1231
1232union cvmx_gmxx_rxx_stats_octs_drp {
1233 uint64_t u64;
1234 struct cvmx_gmxx_rxx_stats_octs_drp_s {
1235 uint64_t reserved_48_63:16;
1236 uint64_t cnt:48;
1237 } s;
1238 struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
1239 struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
1240 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
1241 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
1242 struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
1243 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
1244 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
1245 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
1246 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
1247 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
1248 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
1249};
1250
1251union cvmx_gmxx_rxx_stats_pkts {
1252 uint64_t u64;
1253 struct cvmx_gmxx_rxx_stats_pkts_s {
1254 uint64_t reserved_32_63:32;
1255 uint64_t cnt:32;
1256 } s;
1257 struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
1258 struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
1259 struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
1260 struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
1261 struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
1262 struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
1263 struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
1264 struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
1265 struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
1266 struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
1267 struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
1268};
1269
1270union cvmx_gmxx_rxx_stats_pkts_bad {
1271 uint64_t u64;
1272 struct cvmx_gmxx_rxx_stats_pkts_bad_s {
1273 uint64_t reserved_32_63:32;
1274 uint64_t cnt:32;
1275 } s;
1276 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
1277 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
1278 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
1279 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
1280 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
1281 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
1282 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
1283 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
1284 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
1285 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
1286 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
1287};
1288
1289union cvmx_gmxx_rxx_stats_pkts_ctl {
1290 uint64_t u64;
1291 struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
1292 uint64_t reserved_32_63:32;
1293 uint64_t cnt:32;
1294 } s;
1295 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
1296 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
1297 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
1298 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
1299 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
1300 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
1301 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
1302 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
1303 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
1304 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
1305 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
1306};
1307
1308union cvmx_gmxx_rxx_stats_pkts_dmac {
1309 uint64_t u64;
1310 struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
1311 uint64_t reserved_32_63:32;
1312 uint64_t cnt:32;
1313 } s;
1314 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
1315 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
1316 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
1317 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
1318 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
1319 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
1320 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
1321 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
1322 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
1323 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
1324 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
1325};
1326
1327union cvmx_gmxx_rxx_stats_pkts_drp {
1328 uint64_t u64;
1329 struct cvmx_gmxx_rxx_stats_pkts_drp_s {
1330 uint64_t reserved_32_63:32;
1331 uint64_t cnt:32;
1332 } s;
1333 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
1334 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
1335 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
1336 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
1337 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
1338 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
1339 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
1340 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
1341 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
1342 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
1343 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
1344};
1345
1346union cvmx_gmxx_rxx_udd_skp {
1347 uint64_t u64;
1348 struct cvmx_gmxx_rxx_udd_skp_s {
1349 uint64_t reserved_9_63:55;
1350 uint64_t fcssel:1;
1351 uint64_t reserved_7_7:1;
1352 uint64_t len:7;
1353 } s;
1354 struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
1355 struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
1356 struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
1357 struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
1358 struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
1359 struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
1360 struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
1361 struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
1362 struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
1363 struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
1364 struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
1365};
1366
1367union cvmx_gmxx_rx_bp_dropx {
1368 uint64_t u64;
1369 struct cvmx_gmxx_rx_bp_dropx_s {
1370 uint64_t reserved_6_63:58;
1371 uint64_t mark:6;
1372 } s;
1373 struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
1374 struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
1375 struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
1376 struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
1377 struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
1378 struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
1379 struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
1380 struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
1381 struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
1382 struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
1383 struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
1384};
1385
1386union cvmx_gmxx_rx_bp_offx {
1387 uint64_t u64;
1388 struct cvmx_gmxx_rx_bp_offx_s {
1389 uint64_t reserved_6_63:58;
1390 uint64_t mark:6;
1391 } s;
1392 struct cvmx_gmxx_rx_bp_offx_s cn30xx;
1393 struct cvmx_gmxx_rx_bp_offx_s cn31xx;
1394 struct cvmx_gmxx_rx_bp_offx_s cn38xx;
1395 struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
1396 struct cvmx_gmxx_rx_bp_offx_s cn50xx;
1397 struct cvmx_gmxx_rx_bp_offx_s cn52xx;
1398 struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
1399 struct cvmx_gmxx_rx_bp_offx_s cn56xx;
1400 struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
1401 struct cvmx_gmxx_rx_bp_offx_s cn58xx;
1402 struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
1403};
1404
1405union cvmx_gmxx_rx_bp_onx {
1406 uint64_t u64;
1407 struct cvmx_gmxx_rx_bp_onx_s {
1408 uint64_t reserved_9_63:55;
1409 uint64_t mark:9;
1410 } s;
1411 struct cvmx_gmxx_rx_bp_onx_s cn30xx;
1412 struct cvmx_gmxx_rx_bp_onx_s cn31xx;
1413 struct cvmx_gmxx_rx_bp_onx_s cn38xx;
1414 struct cvmx_gmxx_rx_bp_onx_s cn38xxp2;
1415 struct cvmx_gmxx_rx_bp_onx_s cn50xx;
1416 struct cvmx_gmxx_rx_bp_onx_s cn52xx;
1417 struct cvmx_gmxx_rx_bp_onx_s cn52xxp1;
1418 struct cvmx_gmxx_rx_bp_onx_s cn56xx;
1419 struct cvmx_gmxx_rx_bp_onx_s cn56xxp1;
1420 struct cvmx_gmxx_rx_bp_onx_s cn58xx;
1421 struct cvmx_gmxx_rx_bp_onx_s cn58xxp1;
1422};
1423
1424union cvmx_gmxx_rx_hg2_status {
1425 uint64_t u64;
1426 struct cvmx_gmxx_rx_hg2_status_s {
1427 uint64_t reserved_48_63:16;
1428 uint64_t phtim2go:16;
1429 uint64_t xof:16;
1430 uint64_t lgtim2go:16;
1431 } s;
1432 struct cvmx_gmxx_rx_hg2_status_s cn52xx;
1433 struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
1434 struct cvmx_gmxx_rx_hg2_status_s cn56xx;
1435};
1436
1437union cvmx_gmxx_rx_pass_en {
1438 uint64_t u64;
1439 struct cvmx_gmxx_rx_pass_en_s {
1440 uint64_t reserved_16_63:48;
1441 uint64_t en:16;
1442 } s;
1443 struct cvmx_gmxx_rx_pass_en_s cn38xx;
1444 struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
1445 struct cvmx_gmxx_rx_pass_en_s cn58xx;
1446 struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
1447};
1448
1449union cvmx_gmxx_rx_pass_mapx {
1450 uint64_t u64;
1451 struct cvmx_gmxx_rx_pass_mapx_s {
1452 uint64_t reserved_4_63:60;
1453 uint64_t dprt:4;
1454 } s;
1455 struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
1456 struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
1457 struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
1458 struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
1459};
1460
1461union cvmx_gmxx_rx_prt_info {
1462 uint64_t u64;
1463 struct cvmx_gmxx_rx_prt_info_s {
1464 uint64_t reserved_32_63:32;
1465 uint64_t drop:16;
1466 uint64_t commit:16;
1467 } s;
1468 struct cvmx_gmxx_rx_prt_info_cn30xx {
1469 uint64_t reserved_19_63:45;
1470 uint64_t drop:3;
1471 uint64_t reserved_3_15:13;
1472 uint64_t commit:3;
1473 } cn30xx;
1474 struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
1475 struct cvmx_gmxx_rx_prt_info_s cn38xx;
1476 struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
1477 struct cvmx_gmxx_rx_prt_info_cn52xx {
1478 uint64_t reserved_20_63:44;
1479 uint64_t drop:4;
1480 uint64_t reserved_4_15:12;
1481 uint64_t commit:4;
1482 } cn52xx;
1483 struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
1484 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
1485 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
1486 struct cvmx_gmxx_rx_prt_info_s cn58xx;
1487 struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
1488};
1489
1490union cvmx_gmxx_rx_prts {
1491 uint64_t u64;
1492 struct cvmx_gmxx_rx_prts_s {
1493 uint64_t reserved_3_63:61;
1494 uint64_t prts:3;
1495 } s;
1496 struct cvmx_gmxx_rx_prts_s cn30xx;
1497 struct cvmx_gmxx_rx_prts_s cn31xx;
1498 struct cvmx_gmxx_rx_prts_s cn38xx;
1499 struct cvmx_gmxx_rx_prts_s cn38xxp2;
1500 struct cvmx_gmxx_rx_prts_s cn50xx;
1501 struct cvmx_gmxx_rx_prts_s cn52xx;
1502 struct cvmx_gmxx_rx_prts_s cn52xxp1;
1503 struct cvmx_gmxx_rx_prts_s cn56xx;
1504 struct cvmx_gmxx_rx_prts_s cn56xxp1;
1505 struct cvmx_gmxx_rx_prts_s cn58xx;
1506 struct cvmx_gmxx_rx_prts_s cn58xxp1;
1507};
1508
1509union cvmx_gmxx_rx_tx_status {
1510 uint64_t u64;
1511 struct cvmx_gmxx_rx_tx_status_s {
1512 uint64_t reserved_7_63:57;
1513 uint64_t tx:3;
1514 uint64_t reserved_3_3:1;
1515 uint64_t rx:3;
1516 } s;
1517 struct cvmx_gmxx_rx_tx_status_s cn30xx;
1518 struct cvmx_gmxx_rx_tx_status_s cn31xx;
1519 struct cvmx_gmxx_rx_tx_status_s cn50xx;
1520};
1521
1522union cvmx_gmxx_rx_xaui_bad_col {
1523 uint64_t u64;
1524 struct cvmx_gmxx_rx_xaui_bad_col_s {
1525 uint64_t reserved_40_63:24;
1526 uint64_t val:1;
1527 uint64_t state:3;
1528 uint64_t lane_rxc:4;
1529 uint64_t lane_rxd:32;
1530 } s;
1531 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
1532 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
1533 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
1534 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
1535};
1536
1537union cvmx_gmxx_rx_xaui_ctl {
1538 uint64_t u64;
1539 struct cvmx_gmxx_rx_xaui_ctl_s {
1540 uint64_t reserved_2_63:62;
1541 uint64_t status:2;
1542 } s;
1543 struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
1544 struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
1545 struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
1546 struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
1547};
1548
1549union cvmx_gmxx_smacx {
1550 uint64_t u64;
1551 struct cvmx_gmxx_smacx_s {
1552 uint64_t reserved_48_63:16;
1553 uint64_t smac:48;
1554 } s;
1555 struct cvmx_gmxx_smacx_s cn30xx;
1556 struct cvmx_gmxx_smacx_s cn31xx;
1557 struct cvmx_gmxx_smacx_s cn38xx;
1558 struct cvmx_gmxx_smacx_s cn38xxp2;
1559 struct cvmx_gmxx_smacx_s cn50xx;
1560 struct cvmx_gmxx_smacx_s cn52xx;
1561 struct cvmx_gmxx_smacx_s cn52xxp1;
1562 struct cvmx_gmxx_smacx_s cn56xx;
1563 struct cvmx_gmxx_smacx_s cn56xxp1;
1564 struct cvmx_gmxx_smacx_s cn58xx;
1565 struct cvmx_gmxx_smacx_s cn58xxp1;
1566};
1567
1568union cvmx_gmxx_stat_bp {
1569 uint64_t u64;
1570 struct cvmx_gmxx_stat_bp_s {
1571 uint64_t reserved_17_63:47;
1572 uint64_t bp:1;
1573 uint64_t cnt:16;
1574 } s;
1575 struct cvmx_gmxx_stat_bp_s cn30xx;
1576 struct cvmx_gmxx_stat_bp_s cn31xx;
1577 struct cvmx_gmxx_stat_bp_s cn38xx;
1578 struct cvmx_gmxx_stat_bp_s cn38xxp2;
1579 struct cvmx_gmxx_stat_bp_s cn50xx;
1580 struct cvmx_gmxx_stat_bp_s cn52xx;
1581 struct cvmx_gmxx_stat_bp_s cn52xxp1;
1582 struct cvmx_gmxx_stat_bp_s cn56xx;
1583 struct cvmx_gmxx_stat_bp_s cn56xxp1;
1584 struct cvmx_gmxx_stat_bp_s cn58xx;
1585 struct cvmx_gmxx_stat_bp_s cn58xxp1;
1586};
1587
1588union cvmx_gmxx_txx_append {
1589 uint64_t u64;
1590 struct cvmx_gmxx_txx_append_s {
1591 uint64_t reserved_4_63:60;
1592 uint64_t force_fcs:1;
1593 uint64_t fcs:1;
1594 uint64_t pad:1;
1595 uint64_t preamble:1;
1596 } s;
1597 struct cvmx_gmxx_txx_append_s cn30xx;
1598 struct cvmx_gmxx_txx_append_s cn31xx;
1599 struct cvmx_gmxx_txx_append_s cn38xx;
1600 struct cvmx_gmxx_txx_append_s cn38xxp2;
1601 struct cvmx_gmxx_txx_append_s cn50xx;
1602 struct cvmx_gmxx_txx_append_s cn52xx;
1603 struct cvmx_gmxx_txx_append_s cn52xxp1;
1604 struct cvmx_gmxx_txx_append_s cn56xx;
1605 struct cvmx_gmxx_txx_append_s cn56xxp1;
1606 struct cvmx_gmxx_txx_append_s cn58xx;
1607 struct cvmx_gmxx_txx_append_s cn58xxp1;
1608};
1609
1610union cvmx_gmxx_txx_burst {
1611 uint64_t u64;
1612 struct cvmx_gmxx_txx_burst_s {
1613 uint64_t reserved_16_63:48;
1614 uint64_t burst:16;
1615 } s;
1616 struct cvmx_gmxx_txx_burst_s cn30xx;
1617 struct cvmx_gmxx_txx_burst_s cn31xx;
1618 struct cvmx_gmxx_txx_burst_s cn38xx;
1619 struct cvmx_gmxx_txx_burst_s cn38xxp2;
1620 struct cvmx_gmxx_txx_burst_s cn50xx;
1621 struct cvmx_gmxx_txx_burst_s cn52xx;
1622 struct cvmx_gmxx_txx_burst_s cn52xxp1;
1623 struct cvmx_gmxx_txx_burst_s cn56xx;
1624 struct cvmx_gmxx_txx_burst_s cn56xxp1;
1625 struct cvmx_gmxx_txx_burst_s cn58xx;
1626 struct cvmx_gmxx_txx_burst_s cn58xxp1;
1627};
1628
1629union cvmx_gmxx_txx_cbfc_xoff {
1630 uint64_t u64;
1631 struct cvmx_gmxx_txx_cbfc_xoff_s {
1632 uint64_t reserved_16_63:48;
1633 uint64_t xoff:16;
1634 } s;
1635 struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
1636 struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
1637};
1638
1639union cvmx_gmxx_txx_cbfc_xon {
1640 uint64_t u64;
1641 struct cvmx_gmxx_txx_cbfc_xon_s {
1642 uint64_t reserved_16_63:48;
1643 uint64_t xon:16;
1644 } s;
1645 struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
1646 struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
1647};
1648
1649union cvmx_gmxx_txx_clk {
1650 uint64_t u64;
1651 struct cvmx_gmxx_txx_clk_s {
1652 uint64_t reserved_6_63:58;
1653 uint64_t clk_cnt:6;
1654 } s;
1655 struct cvmx_gmxx_txx_clk_s cn30xx;
1656 struct cvmx_gmxx_txx_clk_s cn31xx;
1657 struct cvmx_gmxx_txx_clk_s cn38xx;
1658 struct cvmx_gmxx_txx_clk_s cn38xxp2;
1659 struct cvmx_gmxx_txx_clk_s cn50xx;
1660 struct cvmx_gmxx_txx_clk_s cn58xx;
1661 struct cvmx_gmxx_txx_clk_s cn58xxp1;
1662};
1663
1664union cvmx_gmxx_txx_ctl {
1665 uint64_t u64;
1666 struct cvmx_gmxx_txx_ctl_s {
1667 uint64_t reserved_2_63:62;
1668 uint64_t xsdef_en:1;
1669 uint64_t xscol_en:1;
1670 } s;
1671 struct cvmx_gmxx_txx_ctl_s cn30xx;
1672 struct cvmx_gmxx_txx_ctl_s cn31xx;
1673 struct cvmx_gmxx_txx_ctl_s cn38xx;
1674 struct cvmx_gmxx_txx_ctl_s cn38xxp2;
1675 struct cvmx_gmxx_txx_ctl_s cn50xx;
1676 struct cvmx_gmxx_txx_ctl_s cn52xx;
1677 struct cvmx_gmxx_txx_ctl_s cn52xxp1;
1678 struct cvmx_gmxx_txx_ctl_s cn56xx;
1679 struct cvmx_gmxx_txx_ctl_s cn56xxp1;
1680 struct cvmx_gmxx_txx_ctl_s cn58xx;
1681 struct cvmx_gmxx_txx_ctl_s cn58xxp1;
1682};
1683
1684union cvmx_gmxx_txx_min_pkt {
1685 uint64_t u64;
1686 struct cvmx_gmxx_txx_min_pkt_s {
1687 uint64_t reserved_8_63:56;
1688 uint64_t min_size:8;
1689 } s;
1690 struct cvmx_gmxx_txx_min_pkt_s cn30xx;
1691 struct cvmx_gmxx_txx_min_pkt_s cn31xx;
1692 struct cvmx_gmxx_txx_min_pkt_s cn38xx;
1693 struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
1694 struct cvmx_gmxx_txx_min_pkt_s cn50xx;
1695 struct cvmx_gmxx_txx_min_pkt_s cn52xx;
1696 struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
1697 struct cvmx_gmxx_txx_min_pkt_s cn56xx;
1698 struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
1699 struct cvmx_gmxx_txx_min_pkt_s cn58xx;
1700 struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
1701};
1702
1703union cvmx_gmxx_txx_pause_pkt_interval {
1704 uint64_t u64;
1705 struct cvmx_gmxx_txx_pause_pkt_interval_s {
1706 uint64_t reserved_16_63:48;
1707 uint64_t interval:16;
1708 } s;
1709 struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
1710 struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
1711 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
1712 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
1713 struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
1714 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
1715 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
1716 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
1717 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
1718 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
1719 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
1720};
1721
1722union cvmx_gmxx_txx_pause_pkt_time {
1723 uint64_t u64;
1724 struct cvmx_gmxx_txx_pause_pkt_time_s {
1725 uint64_t reserved_16_63:48;
1726 uint64_t time:16;
1727 } s;
1728 struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
1729 struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
1730 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
1731 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
1732 struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
1733 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
1734 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
1735 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
1736 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
1737 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
1738 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
1739};
1740
1741union cvmx_gmxx_txx_pause_togo {
1742 uint64_t u64;
1743 struct cvmx_gmxx_txx_pause_togo_s {
1744 uint64_t reserved_32_63:32;
1745 uint64_t msg_time:16;
1746 uint64_t time:16;
1747 } s;
1748 struct cvmx_gmxx_txx_pause_togo_cn30xx {
1749 uint64_t reserved_16_63:48;
1750 uint64_t time:16;
1751 } cn30xx;
1752 struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
1753 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
1754 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
1755 struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
1756 struct cvmx_gmxx_txx_pause_togo_s cn52xx;
1757 struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
1758 struct cvmx_gmxx_txx_pause_togo_s cn56xx;
1759 struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
1760 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
1761 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
1762};
1763
1764union cvmx_gmxx_txx_pause_zero {
1765 uint64_t u64;
1766 struct cvmx_gmxx_txx_pause_zero_s {
1767 uint64_t reserved_1_63:63;
1768 uint64_t send:1;
1769 } s;
1770 struct cvmx_gmxx_txx_pause_zero_s cn30xx;
1771 struct cvmx_gmxx_txx_pause_zero_s cn31xx;
1772 struct cvmx_gmxx_txx_pause_zero_s cn38xx;
1773 struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
1774 struct cvmx_gmxx_txx_pause_zero_s cn50xx;
1775 struct cvmx_gmxx_txx_pause_zero_s cn52xx;
1776 struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
1777 struct cvmx_gmxx_txx_pause_zero_s cn56xx;
1778 struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
1779 struct cvmx_gmxx_txx_pause_zero_s cn58xx;
1780 struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
1781};
1782
1783union cvmx_gmxx_txx_sgmii_ctl {
1784 uint64_t u64;
1785 struct cvmx_gmxx_txx_sgmii_ctl_s {
1786 uint64_t reserved_1_63:63;
1787 uint64_t align:1;
1788 } s;
1789 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
1790 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
1791 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
1792 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
1793};
1794
1795union cvmx_gmxx_txx_slot {
1796 uint64_t u64;
1797 struct cvmx_gmxx_txx_slot_s {
1798 uint64_t reserved_10_63:54;
1799 uint64_t slot:10;
1800 } s;
1801 struct cvmx_gmxx_txx_slot_s cn30xx;
1802 struct cvmx_gmxx_txx_slot_s cn31xx;
1803 struct cvmx_gmxx_txx_slot_s cn38xx;
1804 struct cvmx_gmxx_txx_slot_s cn38xxp2;
1805 struct cvmx_gmxx_txx_slot_s cn50xx;
1806 struct cvmx_gmxx_txx_slot_s cn52xx;
1807 struct cvmx_gmxx_txx_slot_s cn52xxp1;
1808 struct cvmx_gmxx_txx_slot_s cn56xx;
1809 struct cvmx_gmxx_txx_slot_s cn56xxp1;
1810 struct cvmx_gmxx_txx_slot_s cn58xx;
1811 struct cvmx_gmxx_txx_slot_s cn58xxp1;
1812};
1813
1814union cvmx_gmxx_txx_soft_pause {
1815 uint64_t u64;
1816 struct cvmx_gmxx_txx_soft_pause_s {
1817 uint64_t reserved_16_63:48;
1818 uint64_t time:16;
1819 } s;
1820 struct cvmx_gmxx_txx_soft_pause_s cn30xx;
1821 struct cvmx_gmxx_txx_soft_pause_s cn31xx;
1822 struct cvmx_gmxx_txx_soft_pause_s cn38xx;
1823 struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
1824 struct cvmx_gmxx_txx_soft_pause_s cn50xx;
1825 struct cvmx_gmxx_txx_soft_pause_s cn52xx;
1826 struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
1827 struct cvmx_gmxx_txx_soft_pause_s cn56xx;
1828 struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
1829 struct cvmx_gmxx_txx_soft_pause_s cn58xx;
1830 struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
1831};
1832
1833union cvmx_gmxx_txx_stat0 {
1834 uint64_t u64;
1835 struct cvmx_gmxx_txx_stat0_s {
1836 uint64_t xsdef:32;
1837 uint64_t xscol:32;
1838 } s;
1839 struct cvmx_gmxx_txx_stat0_s cn30xx;
1840 struct cvmx_gmxx_txx_stat0_s cn31xx;
1841 struct cvmx_gmxx_txx_stat0_s cn38xx;
1842 struct cvmx_gmxx_txx_stat0_s cn38xxp2;
1843 struct cvmx_gmxx_txx_stat0_s cn50xx;
1844 struct cvmx_gmxx_txx_stat0_s cn52xx;
1845 struct cvmx_gmxx_txx_stat0_s cn52xxp1;
1846 struct cvmx_gmxx_txx_stat0_s cn56xx;
1847 struct cvmx_gmxx_txx_stat0_s cn56xxp1;
1848 struct cvmx_gmxx_txx_stat0_s cn58xx;
1849 struct cvmx_gmxx_txx_stat0_s cn58xxp1;
1850};
1851
1852union cvmx_gmxx_txx_stat1 {
1853 uint64_t u64;
1854 struct cvmx_gmxx_txx_stat1_s {
1855 uint64_t scol:32;
1856 uint64_t mcol:32;
1857 } s;
1858 struct cvmx_gmxx_txx_stat1_s cn30xx;
1859 struct cvmx_gmxx_txx_stat1_s cn31xx;
1860 struct cvmx_gmxx_txx_stat1_s cn38xx;
1861 struct cvmx_gmxx_txx_stat1_s cn38xxp2;
1862 struct cvmx_gmxx_txx_stat1_s cn50xx;
1863 struct cvmx_gmxx_txx_stat1_s cn52xx;
1864 struct cvmx_gmxx_txx_stat1_s cn52xxp1;
1865 struct cvmx_gmxx_txx_stat1_s cn56xx;
1866 struct cvmx_gmxx_txx_stat1_s cn56xxp1;
1867 struct cvmx_gmxx_txx_stat1_s cn58xx;
1868 struct cvmx_gmxx_txx_stat1_s cn58xxp1;
1869};
1870
1871union cvmx_gmxx_txx_stat2 {
1872 uint64_t u64;
1873 struct cvmx_gmxx_txx_stat2_s {
1874 uint64_t reserved_48_63:16;
1875 uint64_t octs:48;
1876 } s;
1877 struct cvmx_gmxx_txx_stat2_s cn30xx;
1878 struct cvmx_gmxx_txx_stat2_s cn31xx;
1879 struct cvmx_gmxx_txx_stat2_s cn38xx;
1880 struct cvmx_gmxx_txx_stat2_s cn38xxp2;
1881 struct cvmx_gmxx_txx_stat2_s cn50xx;
1882 struct cvmx_gmxx_txx_stat2_s cn52xx;
1883 struct cvmx_gmxx_txx_stat2_s cn52xxp1;
1884 struct cvmx_gmxx_txx_stat2_s cn56xx;
1885 struct cvmx_gmxx_txx_stat2_s cn56xxp1;
1886 struct cvmx_gmxx_txx_stat2_s cn58xx;
1887 struct cvmx_gmxx_txx_stat2_s cn58xxp1;
1888};
1889
1890union cvmx_gmxx_txx_stat3 {
1891 uint64_t u64;
1892 struct cvmx_gmxx_txx_stat3_s {
1893 uint64_t reserved_32_63:32;
1894 uint64_t pkts:32;
1895 } s;
1896 struct cvmx_gmxx_txx_stat3_s cn30xx;
1897 struct cvmx_gmxx_txx_stat3_s cn31xx;
1898 struct cvmx_gmxx_txx_stat3_s cn38xx;
1899 struct cvmx_gmxx_txx_stat3_s cn38xxp2;
1900 struct cvmx_gmxx_txx_stat3_s cn50xx;
1901 struct cvmx_gmxx_txx_stat3_s cn52xx;
1902 struct cvmx_gmxx_txx_stat3_s cn52xxp1;
1903 struct cvmx_gmxx_txx_stat3_s cn56xx;
1904 struct cvmx_gmxx_txx_stat3_s cn56xxp1;
1905 struct cvmx_gmxx_txx_stat3_s cn58xx;
1906 struct cvmx_gmxx_txx_stat3_s cn58xxp1;
1907};
1908
1909union cvmx_gmxx_txx_stat4 {
1910 uint64_t u64;
1911 struct cvmx_gmxx_txx_stat4_s {
1912 uint64_t hist1:32;
1913 uint64_t hist0:32;
1914 } s;
1915 struct cvmx_gmxx_txx_stat4_s cn30xx;
1916 struct cvmx_gmxx_txx_stat4_s cn31xx;
1917 struct cvmx_gmxx_txx_stat4_s cn38xx;
1918 struct cvmx_gmxx_txx_stat4_s cn38xxp2;
1919 struct cvmx_gmxx_txx_stat4_s cn50xx;
1920 struct cvmx_gmxx_txx_stat4_s cn52xx;
1921 struct cvmx_gmxx_txx_stat4_s cn52xxp1;
1922 struct cvmx_gmxx_txx_stat4_s cn56xx;
1923 struct cvmx_gmxx_txx_stat4_s cn56xxp1;
1924 struct cvmx_gmxx_txx_stat4_s cn58xx;
1925 struct cvmx_gmxx_txx_stat4_s cn58xxp1;
1926};
1927
1928union cvmx_gmxx_txx_stat5 {
1929 uint64_t u64;
1930 struct cvmx_gmxx_txx_stat5_s {
1931 uint64_t hist3:32;
1932 uint64_t hist2:32;
1933 } s;
1934 struct cvmx_gmxx_txx_stat5_s cn30xx;
1935 struct cvmx_gmxx_txx_stat5_s cn31xx;
1936 struct cvmx_gmxx_txx_stat5_s cn38xx;
1937 struct cvmx_gmxx_txx_stat5_s cn38xxp2;
1938 struct cvmx_gmxx_txx_stat5_s cn50xx;
1939 struct cvmx_gmxx_txx_stat5_s cn52xx;
1940 struct cvmx_gmxx_txx_stat5_s cn52xxp1;
1941 struct cvmx_gmxx_txx_stat5_s cn56xx;
1942 struct cvmx_gmxx_txx_stat5_s cn56xxp1;
1943 struct cvmx_gmxx_txx_stat5_s cn58xx;
1944 struct cvmx_gmxx_txx_stat5_s cn58xxp1;
1945};
1946
1947union cvmx_gmxx_txx_stat6 {
1948 uint64_t u64;
1949 struct cvmx_gmxx_txx_stat6_s {
1950 uint64_t hist5:32;
1951 uint64_t hist4:32;
1952 } s;
1953 struct cvmx_gmxx_txx_stat6_s cn30xx;
1954 struct cvmx_gmxx_txx_stat6_s cn31xx;
1955 struct cvmx_gmxx_txx_stat6_s cn38xx;
1956 struct cvmx_gmxx_txx_stat6_s cn38xxp2;
1957 struct cvmx_gmxx_txx_stat6_s cn50xx;
1958 struct cvmx_gmxx_txx_stat6_s cn52xx;
1959 struct cvmx_gmxx_txx_stat6_s cn52xxp1;
1960 struct cvmx_gmxx_txx_stat6_s cn56xx;
1961 struct cvmx_gmxx_txx_stat6_s cn56xxp1;
1962 struct cvmx_gmxx_txx_stat6_s cn58xx;
1963 struct cvmx_gmxx_txx_stat6_s cn58xxp1;
1964};
1965
1966union cvmx_gmxx_txx_stat7 {
1967 uint64_t u64;
1968 struct cvmx_gmxx_txx_stat7_s {
1969 uint64_t hist7:32;
1970 uint64_t hist6:32;
1971 } s;
1972 struct cvmx_gmxx_txx_stat7_s cn30xx;
1973 struct cvmx_gmxx_txx_stat7_s cn31xx;
1974 struct cvmx_gmxx_txx_stat7_s cn38xx;
1975 struct cvmx_gmxx_txx_stat7_s cn38xxp2;
1976 struct cvmx_gmxx_txx_stat7_s cn50xx;
1977 struct cvmx_gmxx_txx_stat7_s cn52xx;
1978 struct cvmx_gmxx_txx_stat7_s cn52xxp1;
1979 struct cvmx_gmxx_txx_stat7_s cn56xx;
1980 struct cvmx_gmxx_txx_stat7_s cn56xxp1;
1981 struct cvmx_gmxx_txx_stat7_s cn58xx;
1982 struct cvmx_gmxx_txx_stat7_s cn58xxp1;
1983};
1984
1985union cvmx_gmxx_txx_stat8 {
1986 uint64_t u64;
1987 struct cvmx_gmxx_txx_stat8_s {
1988 uint64_t mcst:32;
1989 uint64_t bcst:32;
1990 } s;
1991 struct cvmx_gmxx_txx_stat8_s cn30xx;
1992 struct cvmx_gmxx_txx_stat8_s cn31xx;
1993 struct cvmx_gmxx_txx_stat8_s cn38xx;
1994 struct cvmx_gmxx_txx_stat8_s cn38xxp2;
1995 struct cvmx_gmxx_txx_stat8_s cn50xx;
1996 struct cvmx_gmxx_txx_stat8_s cn52xx;
1997 struct cvmx_gmxx_txx_stat8_s cn52xxp1;
1998 struct cvmx_gmxx_txx_stat8_s cn56xx;
1999 struct cvmx_gmxx_txx_stat8_s cn56xxp1;
2000 struct cvmx_gmxx_txx_stat8_s cn58xx;
2001 struct cvmx_gmxx_txx_stat8_s cn58xxp1;
2002};
2003
2004union cvmx_gmxx_txx_stat9 {
2005 uint64_t u64;
2006 struct cvmx_gmxx_txx_stat9_s {
2007 uint64_t undflw:32;
2008 uint64_t ctl:32;
2009 } s;
2010 struct cvmx_gmxx_txx_stat9_s cn30xx;
2011 struct cvmx_gmxx_txx_stat9_s cn31xx;
2012 struct cvmx_gmxx_txx_stat9_s cn38xx;
2013 struct cvmx_gmxx_txx_stat9_s cn38xxp2;
2014 struct cvmx_gmxx_txx_stat9_s cn50xx;
2015 struct cvmx_gmxx_txx_stat9_s cn52xx;
2016 struct cvmx_gmxx_txx_stat9_s cn52xxp1;
2017 struct cvmx_gmxx_txx_stat9_s cn56xx;
2018 struct cvmx_gmxx_txx_stat9_s cn56xxp1;
2019 struct cvmx_gmxx_txx_stat9_s cn58xx;
2020 struct cvmx_gmxx_txx_stat9_s cn58xxp1;
2021};
2022
2023union cvmx_gmxx_txx_stats_ctl {
2024 uint64_t u64;
2025 struct cvmx_gmxx_txx_stats_ctl_s {
2026 uint64_t reserved_1_63:63;
2027 uint64_t rd_clr:1;
2028 } s;
2029 struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
2030 struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
2031 struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
2032 struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
2033 struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
2034 struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
2035 struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
2036 struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
2037 struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
2038 struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
2039 struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
2040};
2041
2042union cvmx_gmxx_txx_thresh {
2043 uint64_t u64;
2044 struct cvmx_gmxx_txx_thresh_s {
2045 uint64_t reserved_9_63:55;
2046 uint64_t cnt:9;
2047 } s;
2048 struct cvmx_gmxx_txx_thresh_cn30xx {
2049 uint64_t reserved_7_63:57;
2050 uint64_t cnt:7;
2051 } cn30xx;
2052 struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
2053 struct cvmx_gmxx_txx_thresh_s cn38xx;
2054 struct cvmx_gmxx_txx_thresh_s cn38xxp2;
2055 struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
2056 struct cvmx_gmxx_txx_thresh_s cn52xx;
2057 struct cvmx_gmxx_txx_thresh_s cn52xxp1;
2058 struct cvmx_gmxx_txx_thresh_s cn56xx;
2059 struct cvmx_gmxx_txx_thresh_s cn56xxp1;
2060 struct cvmx_gmxx_txx_thresh_s cn58xx;
2061 struct cvmx_gmxx_txx_thresh_s cn58xxp1;
2062};
2063
2064union cvmx_gmxx_tx_bp {
2065 uint64_t u64;
2066 struct cvmx_gmxx_tx_bp_s {
2067 uint64_t reserved_4_63:60;
2068 uint64_t bp:4;
2069 } s;
2070 struct cvmx_gmxx_tx_bp_cn30xx {
2071 uint64_t reserved_3_63:61;
2072 uint64_t bp:3;
2073 } cn30xx;
2074 struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
2075 struct cvmx_gmxx_tx_bp_s cn38xx;
2076 struct cvmx_gmxx_tx_bp_s cn38xxp2;
2077 struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
2078 struct cvmx_gmxx_tx_bp_s cn52xx;
2079 struct cvmx_gmxx_tx_bp_s cn52xxp1;
2080 struct cvmx_gmxx_tx_bp_s cn56xx;
2081 struct cvmx_gmxx_tx_bp_s cn56xxp1;
2082 struct cvmx_gmxx_tx_bp_s cn58xx;
2083 struct cvmx_gmxx_tx_bp_s cn58xxp1;
2084};
2085
2086union cvmx_gmxx_tx_clk_mskx {
2087 uint64_t u64;
2088 struct cvmx_gmxx_tx_clk_mskx_s {
2089 uint64_t reserved_1_63:63;
2090 uint64_t msk:1;
2091 } s;
2092 struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
2093 struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
2094};
2095
2096union cvmx_gmxx_tx_col_attempt {
2097 uint64_t u64;
2098 struct cvmx_gmxx_tx_col_attempt_s {
2099 uint64_t reserved_5_63:59;
2100 uint64_t limit:5;
2101 } s;
2102 struct cvmx_gmxx_tx_col_attempt_s cn30xx;
2103 struct cvmx_gmxx_tx_col_attempt_s cn31xx;
2104 struct cvmx_gmxx_tx_col_attempt_s cn38xx;
2105 struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
2106 struct cvmx_gmxx_tx_col_attempt_s cn50xx;
2107 struct cvmx_gmxx_tx_col_attempt_s cn52xx;
2108 struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
2109 struct cvmx_gmxx_tx_col_attempt_s cn56xx;
2110 struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
2111 struct cvmx_gmxx_tx_col_attempt_s cn58xx;
2112 struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
2113};
2114
2115union cvmx_gmxx_tx_corrupt {
2116 uint64_t u64;
2117 struct cvmx_gmxx_tx_corrupt_s {
2118 uint64_t reserved_4_63:60;
2119 uint64_t corrupt:4;
2120 } s;
2121 struct cvmx_gmxx_tx_corrupt_cn30xx {
2122 uint64_t reserved_3_63:61;
2123 uint64_t corrupt:3;
2124 } cn30xx;
2125 struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
2126 struct cvmx_gmxx_tx_corrupt_s cn38xx;
2127 struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
2128 struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
2129 struct cvmx_gmxx_tx_corrupt_s cn52xx;
2130 struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
2131 struct cvmx_gmxx_tx_corrupt_s cn56xx;
2132 struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
2133 struct cvmx_gmxx_tx_corrupt_s cn58xx;
2134 struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
2135};
2136
2137union cvmx_gmxx_tx_hg2_reg1 {
2138 uint64_t u64;
2139 struct cvmx_gmxx_tx_hg2_reg1_s {
2140 uint64_t reserved_16_63:48;
2141 uint64_t tx_xof:16;
2142 } s;
2143 struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
2144 struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
2145 struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
2146};
2147
2148union cvmx_gmxx_tx_hg2_reg2 {
2149 uint64_t u64;
2150 struct cvmx_gmxx_tx_hg2_reg2_s {
2151 uint64_t reserved_16_63:48;
2152 uint64_t tx_xon:16;
2153 } s;
2154 struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
2155 struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
2156 struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
2157};
2158
2159union cvmx_gmxx_tx_ifg {
2160 uint64_t u64;
2161 struct cvmx_gmxx_tx_ifg_s {
2162 uint64_t reserved_8_63:56;
2163 uint64_t ifg2:4;
2164 uint64_t ifg1:4;
2165 } s;
2166 struct cvmx_gmxx_tx_ifg_s cn30xx;
2167 struct cvmx_gmxx_tx_ifg_s cn31xx;
2168 struct cvmx_gmxx_tx_ifg_s cn38xx;
2169 struct cvmx_gmxx_tx_ifg_s cn38xxp2;
2170 struct cvmx_gmxx_tx_ifg_s cn50xx;
2171 struct cvmx_gmxx_tx_ifg_s cn52xx;
2172 struct cvmx_gmxx_tx_ifg_s cn52xxp1;
2173 struct cvmx_gmxx_tx_ifg_s cn56xx;
2174 struct cvmx_gmxx_tx_ifg_s cn56xxp1;
2175 struct cvmx_gmxx_tx_ifg_s cn58xx;
2176 struct cvmx_gmxx_tx_ifg_s cn58xxp1;
2177};
2178
2179union cvmx_gmxx_tx_int_en {
2180 uint64_t u64;
2181 struct cvmx_gmxx_tx_int_en_s {
2182 uint64_t reserved_20_63:44;
2183 uint64_t late_col:4;
2184 uint64_t xsdef:4;
2185 uint64_t xscol:4;
2186 uint64_t reserved_6_7:2;
2187 uint64_t undflw:4;
2188 uint64_t ncb_nxa:1;
2189 uint64_t pko_nxa:1;
2190 } s;
2191 struct cvmx_gmxx_tx_int_en_cn30xx {
2192 uint64_t reserved_19_63:45;
2193 uint64_t late_col:3;
2194 uint64_t reserved_15_15:1;
2195 uint64_t xsdef:3;
2196 uint64_t reserved_11_11:1;
2197 uint64_t xscol:3;
2198 uint64_t reserved_5_7:3;
2199 uint64_t undflw:3;
2200 uint64_t reserved_1_1:1;
2201 uint64_t pko_nxa:1;
2202 } cn30xx;
2203 struct cvmx_gmxx_tx_int_en_cn31xx {
2204 uint64_t reserved_15_63:49;
2205 uint64_t xsdef:3;
2206 uint64_t reserved_11_11:1;
2207 uint64_t xscol:3;
2208 uint64_t reserved_5_7:3;
2209 uint64_t undflw:3;
2210 uint64_t reserved_1_1:1;
2211 uint64_t pko_nxa:1;
2212 } cn31xx;
2213 struct cvmx_gmxx_tx_int_en_s cn38xx;
2214 struct cvmx_gmxx_tx_int_en_cn38xxp2 {
2215 uint64_t reserved_16_63:48;
2216 uint64_t xsdef:4;
2217 uint64_t xscol:4;
2218 uint64_t reserved_6_7:2;
2219 uint64_t undflw:4;
2220 uint64_t ncb_nxa:1;
2221 uint64_t pko_nxa:1;
2222 } cn38xxp2;
2223 struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
2224 struct cvmx_gmxx_tx_int_en_cn52xx {
2225 uint64_t reserved_20_63:44;
2226 uint64_t late_col:4;
2227 uint64_t xsdef:4;
2228 uint64_t xscol:4;
2229 uint64_t reserved_6_7:2;
2230 uint64_t undflw:4;
2231 uint64_t reserved_1_1:1;
2232 uint64_t pko_nxa:1;
2233 } cn52xx;
2234 struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
2235 struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
2236 struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
2237 struct cvmx_gmxx_tx_int_en_s cn58xx;
2238 struct cvmx_gmxx_tx_int_en_s cn58xxp1;
2239};
2240
2241union cvmx_gmxx_tx_int_reg {
2242 uint64_t u64;
2243 struct cvmx_gmxx_tx_int_reg_s {
2244 uint64_t reserved_20_63:44;
2245 uint64_t late_col:4;
2246 uint64_t xsdef:4;
2247 uint64_t xscol:4;
2248 uint64_t reserved_6_7:2;
2249 uint64_t undflw:4;
2250 uint64_t ncb_nxa:1;
2251 uint64_t pko_nxa:1;
2252 } s;
2253 struct cvmx_gmxx_tx_int_reg_cn30xx {
2254 uint64_t reserved_19_63:45;
2255 uint64_t late_col:3;
2256 uint64_t reserved_15_15:1;
2257 uint64_t xsdef:3;
2258 uint64_t reserved_11_11:1;
2259 uint64_t xscol:3;
2260 uint64_t reserved_5_7:3;
2261 uint64_t undflw:3;
2262 uint64_t reserved_1_1:1;
2263 uint64_t pko_nxa:1;
2264 } cn30xx;
2265 struct cvmx_gmxx_tx_int_reg_cn31xx {
2266 uint64_t reserved_15_63:49;
2267 uint64_t xsdef:3;
2268 uint64_t reserved_11_11:1;
2269 uint64_t xscol:3;
2270 uint64_t reserved_5_7:3;
2271 uint64_t undflw:3;
2272 uint64_t reserved_1_1:1;
2273 uint64_t pko_nxa:1;
2274 } cn31xx;
2275 struct cvmx_gmxx_tx_int_reg_s cn38xx;
2276 struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
2277 uint64_t reserved_16_63:48;
2278 uint64_t xsdef:4;
2279 uint64_t xscol:4;
2280 uint64_t reserved_6_7:2;
2281 uint64_t undflw:4;
2282 uint64_t ncb_nxa:1;
2283 uint64_t pko_nxa:1;
2284 } cn38xxp2;
2285 struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
2286 struct cvmx_gmxx_tx_int_reg_cn52xx {
2287 uint64_t reserved_20_63:44;
2288 uint64_t late_col:4;
2289 uint64_t xsdef:4;
2290 uint64_t xscol:4;
2291 uint64_t reserved_6_7:2;
2292 uint64_t undflw:4;
2293 uint64_t reserved_1_1:1;
2294 uint64_t pko_nxa:1;
2295 } cn52xx;
2296 struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
2297 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
2298 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
2299 struct cvmx_gmxx_tx_int_reg_s cn58xx;
2300 struct cvmx_gmxx_tx_int_reg_s cn58xxp1;
2301};
2302
2303union cvmx_gmxx_tx_jam {
2304 uint64_t u64;
2305 struct cvmx_gmxx_tx_jam_s {
2306 uint64_t reserved_8_63:56;
2307 uint64_t jam:8;
2308 } s;
2309 struct cvmx_gmxx_tx_jam_s cn30xx;
2310 struct cvmx_gmxx_tx_jam_s cn31xx;
2311 struct cvmx_gmxx_tx_jam_s cn38xx;
2312 struct cvmx_gmxx_tx_jam_s cn38xxp2;
2313 struct cvmx_gmxx_tx_jam_s cn50xx;
2314 struct cvmx_gmxx_tx_jam_s cn52xx;
2315 struct cvmx_gmxx_tx_jam_s cn52xxp1;
2316 struct cvmx_gmxx_tx_jam_s cn56xx;
2317 struct cvmx_gmxx_tx_jam_s cn56xxp1;
2318 struct cvmx_gmxx_tx_jam_s cn58xx;
2319 struct cvmx_gmxx_tx_jam_s cn58xxp1;
2320};
2321
2322union cvmx_gmxx_tx_lfsr {
2323 uint64_t u64;
2324 struct cvmx_gmxx_tx_lfsr_s {
2325 uint64_t reserved_16_63:48;
2326 uint64_t lfsr:16;
2327 } s;
2328 struct cvmx_gmxx_tx_lfsr_s cn30xx;
2329 struct cvmx_gmxx_tx_lfsr_s cn31xx;
2330 struct cvmx_gmxx_tx_lfsr_s cn38xx;
2331 struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
2332 struct cvmx_gmxx_tx_lfsr_s cn50xx;
2333 struct cvmx_gmxx_tx_lfsr_s cn52xx;
2334 struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
2335 struct cvmx_gmxx_tx_lfsr_s cn56xx;
2336 struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
2337 struct cvmx_gmxx_tx_lfsr_s cn58xx;
2338 struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
2339};
2340
2341union cvmx_gmxx_tx_ovr_bp {
2342 uint64_t u64;
2343 struct cvmx_gmxx_tx_ovr_bp_s {
2344 uint64_t reserved_48_63:16;
2345 uint64_t tx_prt_bp:16;
2346 uint64_t reserved_12_31:20;
2347 uint64_t en:4;
2348 uint64_t bp:4;
2349 uint64_t ign_full:4;
2350 } s;
2351 struct cvmx_gmxx_tx_ovr_bp_cn30xx {
2352 uint64_t reserved_11_63:53;
2353 uint64_t en:3;
2354 uint64_t reserved_7_7:1;
2355 uint64_t bp:3;
2356 uint64_t reserved_3_3:1;
2357 uint64_t ign_full:3;
2358 } cn30xx;
2359 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
2360 struct cvmx_gmxx_tx_ovr_bp_cn38xx {
2361 uint64_t reserved_12_63:52;
2362 uint64_t en:4;
2363 uint64_t bp:4;
2364 uint64_t ign_full:4;
2365 } cn38xx;
2366 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
2367 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
2368 struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
2369 struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
2370 struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
2371 struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
2372 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
2373 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
2374};
2375
2376union cvmx_gmxx_tx_pause_pkt_dmac {
2377 uint64_t u64;
2378 struct cvmx_gmxx_tx_pause_pkt_dmac_s {
2379 uint64_t reserved_48_63:16;
2380 uint64_t dmac:48;
2381 } s;
2382 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
2383 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
2384 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
2385 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
2386 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
2387 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
2388 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
2389 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
2390 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
2391 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
2392 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
2393};
2394
2395union cvmx_gmxx_tx_pause_pkt_type {
2396 uint64_t u64;
2397 struct cvmx_gmxx_tx_pause_pkt_type_s {
2398 uint64_t reserved_16_63:48;
2399 uint64_t type:16;
2400 } s;
2401 struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
2402 struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
2403 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
2404 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
2405 struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
2406 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
2407 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
2408 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
2409 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
2410 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
2411 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
2412};
2413
2414union cvmx_gmxx_tx_prts {
2415 uint64_t u64;
2416 struct cvmx_gmxx_tx_prts_s {
2417 uint64_t reserved_5_63:59;
2418 uint64_t prts:5;
2419 } s;
2420 struct cvmx_gmxx_tx_prts_s cn30xx;
2421 struct cvmx_gmxx_tx_prts_s cn31xx;
2422 struct cvmx_gmxx_tx_prts_s cn38xx;
2423 struct cvmx_gmxx_tx_prts_s cn38xxp2;
2424 struct cvmx_gmxx_tx_prts_s cn50xx;
2425 struct cvmx_gmxx_tx_prts_s cn52xx;
2426 struct cvmx_gmxx_tx_prts_s cn52xxp1;
2427 struct cvmx_gmxx_tx_prts_s cn56xx;
2428 struct cvmx_gmxx_tx_prts_s cn56xxp1;
2429 struct cvmx_gmxx_tx_prts_s cn58xx;
2430 struct cvmx_gmxx_tx_prts_s cn58xxp1;
2431};
2432
2433union cvmx_gmxx_tx_spi_ctl {
2434 uint64_t u64;
2435 struct cvmx_gmxx_tx_spi_ctl_s {
2436 uint64_t reserved_2_63:62;
2437 uint64_t tpa_clr:1;
2438 uint64_t cont_pkt:1;
2439 } s;
2440 struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
2441 struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
2442 struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
2443 struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
2444};
2445
2446union cvmx_gmxx_tx_spi_drain {
2447 uint64_t u64;
2448 struct cvmx_gmxx_tx_spi_drain_s {
2449 uint64_t reserved_16_63:48;
2450 uint64_t drain:16;
2451 } s;
2452 struct cvmx_gmxx_tx_spi_drain_s cn38xx;
2453 struct cvmx_gmxx_tx_spi_drain_s cn58xx;
2454 struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
2455};
2456
2457union cvmx_gmxx_tx_spi_max {
2458 uint64_t u64;
2459 struct cvmx_gmxx_tx_spi_max_s {
2460 uint64_t reserved_23_63:41;
2461 uint64_t slice:7;
2462 uint64_t max2:8;
2463 uint64_t max1:8;
2464 } s;
2465 struct cvmx_gmxx_tx_spi_max_cn38xx {
2466 uint64_t reserved_16_63:48;
2467 uint64_t max2:8;
2468 uint64_t max1:8;
2469 } cn38xx;
2470 struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
2471 struct cvmx_gmxx_tx_spi_max_s cn58xx;
2472 struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
2473};
2474
2475union cvmx_gmxx_tx_spi_roundx {
2476 uint64_t u64;
2477 struct cvmx_gmxx_tx_spi_roundx_s {
2478 uint64_t reserved_16_63:48;
2479 uint64_t round:16;
2480 } s;
2481 struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
2482 struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
2483};
2484
2485union cvmx_gmxx_tx_spi_thresh {
2486 uint64_t u64;
2487 struct cvmx_gmxx_tx_spi_thresh_s {
2488 uint64_t reserved_6_63:58;
2489 uint64_t thresh:6;
2490 } s;
2491 struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
2492 struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
2493 struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
2494 struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
2495};
2496
2497union cvmx_gmxx_tx_xaui_ctl {
2498 uint64_t u64;
2499 struct cvmx_gmxx_tx_xaui_ctl_s {
2500 uint64_t reserved_11_63:53;
2501 uint64_t hg_pause_hgi:2;
2502 uint64_t hg_en:1;
2503 uint64_t reserved_7_7:1;
2504 uint64_t ls_byp:1;
2505 uint64_t ls:2;
2506 uint64_t reserved_2_3:2;
2507 uint64_t uni_en:1;
2508 uint64_t dic_en:1;
2509 } s;
2510 struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
2511 struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
2512 struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
2513 struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
2514};
2515
2516union cvmx_gmxx_xaui_ext_loopback {
2517 uint64_t u64;
2518 struct cvmx_gmxx_xaui_ext_loopback_s {
2519 uint64_t reserved_5_63:59;
2520 uint64_t en:1;
2521 uint64_t thresh:4;
2522 } s;
2523 struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
2524 struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
2525 struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
2526 struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
2527};
2528
2529#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
new file mode 100644
index 00000000000..88527fa835c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -0,0 +1,157 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Helper functions to abstract board specific data about
31 * network ports from the rest of the cvmx-helper files.
32 *
33 */
34#ifndef __CVMX_HELPER_BOARD_H__
35#define __CVMX_HELPER_BOARD_H__
36
37#include "cvmx-helper.h"
38
39typedef enum {
40 set_phy_link_flags_autoneg = 0x1,
41 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
42 set_phy_link_flags_flow_control_enable = 0x1 << 1,
43 set_phy_link_flags_flow_control_disable = 0x2 << 1,
44 set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */
45} cvmx_helper_board_set_phy_link_flags_types_t;
46
47/*
48 * Fake IPD port, the RGMII/MII interface may use different PHY, use
49 * this macro to return appropriate MIX address to read the PHY.
50 */
51#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10
52
53/**
54 * cvmx_override_board_link_get(int ipd_port) is a function
55 * pointer. It is meant to allow customization of the process of
56 * talking to a PHY to determine link speed. It is called every
57 * time a PHY must be polled for link status. Users should set
58 * this pointer to a function before calling any cvmx-helper
59 * operations.
60 */
61extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port);
62
63/**
64 * Return the MII PHY address associated with the given IPD
65 * port. A result of -1 means there isn't a MII capable PHY
66 * connected to this port. On chips supporting multiple MII
67 * busses the bus number is encoded in bits <15:8>.
68 *
69 * This function must be modifed for every new Octeon board.
70 * Internally it uses switch statements based on the cvmx_sysinfo
71 * data to determine board types and revisions. It relys on the
72 * fact that every Octeon board receives a unique board type
73 * enumeration from the bootloader.
74 *
75 * @ipd_port: Octeon IPD port to get the MII address for.
76 *
77 * Returns MII PHY address and bus number or -1.
78 */
79extern int cvmx_helper_board_get_mii_address(int ipd_port);
80
81/**
82 * This function as a board specific method of changing the PHY
83 * speed, duplex, and autonegotiation. This programs the PHY and
84 * not Octeon. This can be used to force Octeon's links to
85 * specific settings.
86 *
87 * @phy_addr: The address of the PHY to program
88 * @link_flags:
89 * Flags to control autonegotiation. Bit 0 is autonegotiation
90 * enable/disable to maintain backware compatibility.
91 * @link_info: Link speed to program. If the speed is zero and autonegotiation
92 * is enabled, all possible negotiation speeds are advertised.
93 *
94 * Returns Zero on success, negative on failure
95 */
96int cvmx_helper_board_link_set_phy(int phy_addr,
97 cvmx_helper_board_set_phy_link_flags_types_t
98 link_flags,
99 cvmx_helper_link_info_t link_info);
100
101/**
102 * This function is the board specific method of determining an
103 * ethernet ports link speed. Most Octeon boards have Marvell PHYs
104 * and are handled by the fall through case. This function must be
105 * updated for boards that don't have the normal Marvell PHYs.
106 *
107 * This function must be modifed for every new Octeon board.
108 * Internally it uses switch statements based on the cvmx_sysinfo
109 * data to determine board types and revisions. It relys on the
110 * fact that every Octeon board receives a unique board type
111 * enumeration from the bootloader.
112 *
113 * @ipd_port: IPD input port associated with the port we want to get link
114 * status for.
115 *
116 * Returns The ports link status. If the link isn't fully resolved, this must
117 * return zero.
118 */
119extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
120
121/**
122 * This function is called by cvmx_helper_interface_probe() after it
123 * determines the number of ports Octeon can support on a specific
124 * interface. This function is the per board location to override
125 * this value. It is called with the number of ports Octeon might
126 * support and should return the number of actual ports on the
127 * board.
128 *
129 * This function must be modifed for every new Octeon board.
130 * Internally it uses switch statements based on the cvmx_sysinfo
131 * data to determine board types and revisions. It relys on the
132 * fact that every Octeon board receives a unique board type
133 * enumeration from the bootloader.
134 *
135 * @interface: Interface to probe
136 * @supported_ports:
137 * Number of ports Octeon supports.
138 *
139 * Returns Number of ports the actual board supports. Many times this will
140 * simple be "support_ports".
141 */
142extern int __cvmx_helper_board_interface_probe(int interface,
143 int supported_ports);
144
145/**
146 * Enable packet input/output from the hardware. This function is
147 * called after by cvmx_helper_packet_hardware_enable() to
148 * perform board specific initialization. For most boards
149 * nothing is needed.
150 *
151 * @interface: Interface to enable
152 *
153 * Returns Zero on success, negative on failure
154 */
155extern int __cvmx_helper_board_hardware_enable(int interface);
156
157#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
new file mode 100644
index 00000000000..5ff8c93198d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
@@ -0,0 +1,64 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper functions for FPA setup.
32 *
33 */
34#ifndef __CVMX_HELPER_H_FPA__
35#define __CVMX_HELPER_H_FPA__
36
37/**
38 * Allocate memory and initialize the FPA pools using memory
39 * from cvmx-bootmem. Sizes of each element in the pools is
40 * controlled by the cvmx-config.h header file. Specifying
41 * zero for any parameter will cause that FPA pool to not be
42 * setup. This is useful if you aren't using some of the
43 * hardware and want to save memory.
44 *
45 * @packet_buffers:
46 * Number of packet buffers to allocate
47 * @work_queue_entries:
48 * Number of work queue entries
49 * @pko_buffers:
50 * PKO Command buffers. You should at minimum have two per
51 * each PKO queue.
52 * @tim_buffers:
53 * TIM ring buffer command queues. At least two per timer bucket
54 * is recommened.
55 * @dfa_buffers:
56 * DFA command buffer. A relatively small (32 for example)
57 * number should work.
58 * Returns Zero on success, non-zero if out of memory
59 */
60extern int cvmx_helper_initialize_fpa(int packet_buffers,
61 int work_queue_entries, int pko_buffers,
62 int tim_buffers, int dfa_buffers);
63
64#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
new file mode 100644
index 00000000000..077f0e9d3b2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
@@ -0,0 +1,60 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as published by
11 * the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
16 * See the GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this file; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * or visit http://www.gnu.org/licenses/.
22 *
23 * This file may also be available under a different license from Cavium.
24 * Contact Cavium Networks for more information
25 ***********************license end**************************************/
26
27/**
28 * @file
29 *
30 * Functions for LOOP initialization, configuration,
31 * and monitoring.
32 *
33 */
34#ifndef __CVMX_HELPER_LOOP_H__
35#define __CVMX_HELPER_LOOP_H__
36
37/**
38 * Probe a LOOP interface and determine the number of ports
39 * connected to it. The LOOP interface should still be down after
40 * this call.
41 *
42 * @interface: Interface to probe
43 *
44 * Returns Number of ports on the interface. Zero to disable.
45 */
46extern int __cvmx_helper_loop_probe(int interface);
47static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; }
48
49/**
50 * Bringup and enable a LOOP interface. After this call packet
51 * I/O should be fully functional. This is called with IPD
52 * enabled but PKO disabled.
53 *
54 * @interface: Interface to bring up
55 *
56 * Returns Zero on success, negative on failure
57 */
58extern int __cvmx_helper_loop_enable(int interface);
59
60#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
new file mode 100644
index 00000000000..8df4c7fafdb
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
@@ -0,0 +1,61 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for NPI initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_NPI_H__
36#define __CVMX_HELPER_NPI_H__
37
38/**
39 * Probe a NPI interface and determine the number of ports
40 * connected to it. The NPI interface should still be down after
41 * this call.
42 *
43 * @interface: Interface to probe
44 *
45 * Returns Number of ports on the interface. Zero to disable.
46 */
47extern int __cvmx_helper_npi_probe(int interface);
48#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe
49
50/**
51 * Bringup and enable a NPI interface. After this call packet
52 * I/O should be fully functional. This is called with IPD
53 * enabled but PKO disabled.
54 *
55 * @interface: Interface to bring up
56 *
57 * Returns Zero on success, negative on failure
58 */
59extern int __cvmx_helper_npi_enable(int interface);
60
61#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
new file mode 100644
index 00000000000..78295ba0050
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -0,0 +1,111 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for RGMII/GMII/MII initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_RGMII_H__
36#define __CVMX_HELPER_RGMII_H__
37
38/**
39 * Probe RGMII ports and determine the number present
40 *
41 * @interface: Interface to probe
42 *
43 * Returns Number of RGMII/GMII/MII ports (0-4).
44 */
45extern int __cvmx_helper_rgmii_probe(int interface);
46#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe
47
48/**
49 * Put an RGMII interface in loopback mode. Internal packets sent
50 * out will be received back again on the same port. Externally
51 * received packets will echo back out.
52 *
53 * @port: IPD port number to loop.
54 */
55extern void cvmx_helper_rgmii_internal_loopback(int port);
56
57/**
58 * Configure all of the ASX, GMX, and PKO regsiters required
59 * to get RGMII to function on the supplied interface.
60 *
61 * @interface: PKO Interface to configure (0 or 1)
62 *
63 * Returns Zero on success
64 */
65extern int __cvmx_helper_rgmii_enable(int interface);
66
67/**
68 * Return the link state of an IPD/PKO port as returned by
69 * auto negotiation. The result of this function may not match
70 * Octeon's link config if auto negotiation has changed since
71 * the last call to cvmx_helper_link_set().
72 *
73 * @ipd_port: IPD/PKO port to query
74 *
75 * Returns Link state
76 */
77extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port);
78
79/**
80 * Configure an IPD/PKO port for the specified link state. This
81 * function does not influence auto negotiation at the PHY level.
82 * The passed link state must always match the link state returned
83 * by cvmx_helper_link_get(). It is normally best to use
84 * cvmx_helper_link_autoconf() instead.
85 *
86 * @ipd_port: IPD/PKO port to configure
87 * @link_info: The new link state
88 *
89 * Returns Zero on success, negative on failure
90 */
91extern int __cvmx_helper_rgmii_link_set(int ipd_port,
92 cvmx_helper_link_info_t link_info);
93
94/**
95 * Configure a port for internal and/or external loopback. Internal loopback
96 * causes packets sent by the port to be received by Octeon. External loopback
97 * causes packets received from the wire to sent out again.
98 *
99 * @ipd_port: IPD/PKO port to loopback.
100 * @enable_internal:
101 * Non zero if you want internal loopback
102 * @enable_external:
103 * Non zero if you want external loopback
104 *
105 * Returns Zero on success, negative on failure.
106 */
107extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port,
108 int enable_internal,
109 int enable_external);
110
111#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
new file mode 100644
index 00000000000..9a9b6c103ed
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -0,0 +1,105 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for SGMII initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_SGMII_H__
36#define __CVMX_HELPER_SGMII_H__
37
38/**
39 * Probe a SGMII interface and determine the number of ports
40 * connected to it. The SGMII interface should still be down after
41 * this call.
42 *
43 * @interface: Interface to probe
44 *
45 * Returns Number of ports on the interface. Zero to disable.
46 */
47extern int __cvmx_helper_sgmii_probe(int interface);
48extern int __cvmx_helper_sgmii_enumerate(int interface);
49
50/**
51 * Bringup and enable a SGMII interface. After this call packet
52 * I/O should be fully functional. This is called with IPD
53 * enabled but PKO disabled.
54 *
55 * @interface: Interface to bring up
56 *
57 * Returns Zero on success, negative on failure
58 */
59extern int __cvmx_helper_sgmii_enable(int interface);
60
61/**
62 * Return the link state of an IPD/PKO port as returned by
63 * auto negotiation. The result of this function may not match
64 * Octeon's link config if auto negotiation has changed since
65 * the last call to cvmx_helper_link_set().
66 *
67 * @ipd_port: IPD/PKO port to query
68 *
69 * Returns Link state
70 */
71extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port);
72
73/**
74 * Configure an IPD/PKO port for the specified link state. This
75 * function does not influence auto negotiation at the PHY level.
76 * The passed link state must always match the link state returned
77 * by cvmx_helper_link_get(). It is normally best to use
78 * cvmx_helper_link_autoconf() instead.
79 *
80 * @ipd_port: IPD/PKO port to configure
81 * @link_info: The new link state
82 *
83 * Returns Zero on success, negative on failure
84 */
85extern int __cvmx_helper_sgmii_link_set(int ipd_port,
86 cvmx_helper_link_info_t link_info);
87
88/**
89 * Configure a port for internal and/or external loopback. Internal loopback
90 * causes packets sent by the port to be received by Octeon. External loopback
91 * causes packets received from the wire to sent out again.
92 *
93 * @ipd_port: IPD/PKO port to loopback.
94 * @enable_internal:
95 * Non zero if you want internal loopback
96 * @enable_external:
97 * Non zero if you want external loopback
98 *
99 * Returns Zero on success, negative on failure.
100 */
101extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port,
102 int enable_internal,
103 int enable_external);
104
105#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
new file mode 100644
index 00000000000..9f1c6b968f9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
@@ -0,0 +1,85 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Functions for SPI initialization, configuration,
30 * and monitoring.
31 */
32#ifndef __CVMX_HELPER_SPI_H__
33#define __CVMX_HELPER_SPI_H__
34
35/**
36 * Probe a SPI interface and determine the number of ports
37 * connected to it. The SPI interface should still be down after
38 * this call.
39 *
40 * @interface: Interface to probe
41 *
42 * Returns Number of ports on the interface. Zero to disable.
43 */
44extern int __cvmx_helper_spi_probe(int interface);
45extern int __cvmx_helper_spi_enumerate(int interface);
46
47/**
48 * Bringup and enable a SPI interface. After this call packet I/O
49 * should be fully functional. This is called with IPD enabled but
50 * PKO disabled.
51 *
52 * @interface: Interface to bring up
53 *
54 * Returns Zero on success, negative on failure
55 */
56extern int __cvmx_helper_spi_enable(int interface);
57
58/**
59 * Return the link state of an IPD/PKO port as returned by
60 * auto negotiation. The result of this function may not match
61 * Octeon's link config if auto negotiation has changed since
62 * the last call to cvmx_helper_link_set().
63 *
64 * @ipd_port: IPD/PKO port to query
65 *
66 * Returns Link state
67 */
68extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port);
69
70/**
71 * Configure an IPD/PKO port for the specified link state. This
72 * function does not influence auto negotiation at the PHY level.
73 * The passed link state must always match the link state returned
74 * by cvmx_helper_link_get(). It is normally best to use
75 * cvmx_helper_link_autoconf() instead.
76 *
77 * @ipd_port: IPD/PKO port to configure
78 * @link_info: The new link state
79 *
80 * Returns Zero on success, negative on failure
81 */
82extern int __cvmx_helper_spi_link_set(int ipd_port,
83 cvmx_helper_link_info_t link_info);
84
85#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
new file mode 100644
index 00000000000..6a6e52fc22c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
@@ -0,0 +1,215 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Small helper utilities.
31 *
32 */
33
34#ifndef __CVMX_HELPER_UTIL_H__
35#define __CVMX_HELPER_UTIL_H__
36
37/**
38 * Convert a interface mode into a human readable string
39 *
40 * @mode: Mode to convert
41 *
42 * Returns String
43 */
44extern const char
45 *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
46
47/**
48 * Debug routine to dump the packet structure to the console
49 *
50 * @work: Work queue entry containing the packet to dump
51 * Returns
52 */
53extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
54
55/**
56 * Setup Random Early Drop on a specific input queue
57 *
58 * @queue: Input queue to setup RED on (0-7)
59 * @pass_thresh:
60 * Packets will begin slowly dropping when there are less than
61 * this many packet buffers free in FPA 0.
62 * @drop_thresh:
63 * All incomming packets will be dropped when there are less
64 * than this many free packet buffers in FPA 0.
65 * Returns Zero on success. Negative on failure
66 */
67extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
68 int drop_thresh);
69
70/**
71 * Setup Random Early Drop to automatically begin dropping packets.
72 *
73 * @pass_thresh:
74 * Packets will begin slowly dropping when there are less than
75 * this many packet buffers free in FPA 0.
76 * @drop_thresh:
77 * All incomming packets will be dropped when there are less
78 * than this many free packet buffers in FPA 0.
79 * Returns Zero on success. Negative on failure
80 */
81extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
82
83/**
84 * Get the version of the CVMX libraries.
85 *
86 * Returns Version string. Note this buffer is allocated statically
87 * and will be shared by all callers.
88 */
89extern const char *cvmx_helper_get_version(void);
90
91/**
92 * Setup the common GMX settings that determine the number of
93 * ports. These setting apply to almost all configurations of all
94 * chips.
95 *
96 * @interface: Interface to configure
97 * @num_ports: Number of ports on the interface
98 *
99 * Returns Zero on success, negative on failure
100 */
101extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
102
103/**
104 * Returns the IPD/PKO port number for a port on the given
105 * interface.
106 *
107 * @interface: Interface to use
108 * @port: Port on the interface
109 *
110 * Returns IPD/PKO port number
111 */
112extern int cvmx_helper_get_ipd_port(int interface, int port);
113
114/**
115 * Returns the IPD/PKO port number for the first port on the given
116 * interface.
117 *
118 * @interface: Interface to use
119 *
120 * Returns IPD/PKO port number
121 */
122static inline int cvmx_helper_get_first_ipd_port(int interface)
123{
124 return cvmx_helper_get_ipd_port(interface, 0);
125}
126
127/**
128 * Returns the IPD/PKO port number for the last port on the given
129 * interface.
130 *
131 * @interface: Interface to use
132 *
133 * Returns IPD/PKO port number
134 */
135static inline int cvmx_helper_get_last_ipd_port(int interface)
136{
137 extern int cvmx_helper_ports_on_interface(int interface);
138
139 return cvmx_helper_get_first_ipd_port(interface) +
140 cvmx_helper_ports_on_interface(interface) - 1;
141}
142
143/**
144 * Free the packet buffers contained in a work queue entry.
145 * The work queue entry is not freed.
146 *
147 * @work: Work queue entry with packet to free
148 */
149static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
150{
151 uint64_t number_buffers;
152 union cvmx_buf_ptr buffer_ptr;
153 union cvmx_buf_ptr next_buffer_ptr;
154 uint64_t start_of_buffer;
155
156 number_buffers = work->word2.s.bufs;
157 if (number_buffers == 0)
158 return;
159 buffer_ptr = work->packet_ptr;
160
161 /*
162 * Since the number of buffers is not zero, we know this is
163 * not a dynamic short packet. We need to check if it is a
164 * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
165 * true, we need to free all buffers except for the first
166 * one. The caller doesn't expect their WQE pointer to be
167 * freed
168 */
169 start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
170 if (cvmx_ptr_to_phys(work) == start_of_buffer) {
171 next_buffer_ptr =
172 *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
173 buffer_ptr = next_buffer_ptr;
174 number_buffers--;
175 }
176
177 while (number_buffers--) {
178 /*
179 * Remember the back pointer is in cache lines, not
180 * 64bit words
181 */
182 start_of_buffer =
183 ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
184 /*
185 * Read pointer to next buffer before we free the
186 * current buffer.
187 */
188 next_buffer_ptr =
189 *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
190 cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
191 buffer_ptr.s.pool, 0);
192 buffer_ptr = next_buffer_ptr;
193 }
194}
195
196/**
197 * Returns the interface number for an IPD/PKO port number.
198 *
199 * @ipd_port: IPD/PKO port number
200 *
201 * Returns Interface number
202 */
203extern int cvmx_helper_get_interface_num(int ipd_port);
204
205/**
206 * Returns the interface index number for an IPD/PKO port
207 * number.
208 *
209 * @ipd_port: IPD/PKO port number
210 *
211 * Returns Interface index number
212 */
213extern int cvmx_helper_get_interface_index_num(int ipd_port);
214
215#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
new file mode 100644
index 00000000000..f6fbc4f45b5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -0,0 +1,104 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for XAUI initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_XAUI_H__
36#define __CVMX_HELPER_XAUI_H__
37
38/**
39 * Probe a XAUI interface and determine the number of ports
40 * connected to it. The XAUI interface should still be down
41 * after this call.
42 *
43 * @interface: Interface to probe
44 *
45 * Returns Number of ports on the interface. Zero to disable.
46 */
47extern int __cvmx_helper_xaui_probe(int interface);
48extern int __cvmx_helper_xaui_enumerate(int interface);
49
50/**
51 * Bringup and enable a XAUI interface. After this call packet
52 * I/O should be fully functional. This is called with IPD
53 * enabled but PKO disabled.
54 *
55 * @interface: Interface to bring up
56 *
57 * Returns Zero on success, negative on failure
58 */
59extern int __cvmx_helper_xaui_enable(int interface);
60
61/**
62 * Return the link state of an IPD/PKO port as returned by
63 * auto negotiation. The result of this function may not match
64 * Octeon's link config if auto negotiation has changed since
65 * the last call to cvmx_helper_link_set().
66 *
67 * @ipd_port: IPD/PKO port to query
68 *
69 * Returns Link state
70 */
71extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port);
72
73/**
74 * Configure an IPD/PKO port for the specified link state. This
75 * function does not influence auto negotiation at the PHY level.
76 * The passed link state must always match the link state returned
77 * by cvmx_helper_link_get(). It is normally best to use
78 * cvmx_helper_link_autoconf() instead.
79 *
80 * @ipd_port: IPD/PKO port to configure
81 * @link_info: The new link state
82 *
83 * Returns Zero on success, negative on failure
84 */
85extern int __cvmx_helper_xaui_link_set(int ipd_port,
86 cvmx_helper_link_info_t link_info);
87
88/**
89 * Configure a port for internal and/or external loopback. Internal loopback
90 * causes packets sent by the port to be received by Octeon. External loopback
91 * causes packets received from the wire to sent out again.
92 *
93 * @ipd_port: IPD/PKO port to loopback.
94 * @enable_internal:
95 * Non zero if you want internal loopback
96 * @enable_external:
97 * Non zero if you want external loopback
98 *
99 * Returns Zero on success, negative on failure.
100 */
101extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
102 int enable_internal,
103 int enable_external);
104#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
new file mode 100644
index 00000000000..3169cd79f2a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -0,0 +1,228 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Helper functions for common, but complicated tasks.
31 *
32 */
33
34#ifndef __CVMX_HELPER_H__
35#define __CVMX_HELPER_H__
36
37#include "cvmx-config.h"
38#include "cvmx-fpa.h"
39#include "cvmx-wqe.h"
40
41typedef enum {
42 CVMX_HELPER_INTERFACE_MODE_DISABLED,
43 CVMX_HELPER_INTERFACE_MODE_RGMII,
44 CVMX_HELPER_INTERFACE_MODE_GMII,
45 CVMX_HELPER_INTERFACE_MODE_SPI,
46 CVMX_HELPER_INTERFACE_MODE_PCIE,
47 CVMX_HELPER_INTERFACE_MODE_XAUI,
48 CVMX_HELPER_INTERFACE_MODE_SGMII,
49 CVMX_HELPER_INTERFACE_MODE_PICMG,
50 CVMX_HELPER_INTERFACE_MODE_NPI,
51 CVMX_HELPER_INTERFACE_MODE_LOOP,
52} cvmx_helper_interface_mode_t;
53
54typedef union {
55 uint64_t u64;
56 struct {
57 uint64_t reserved_20_63:44;
58 uint64_t link_up:1; /**< Is the physical link up? */
59 uint64_t full_duplex:1; /**< 1 if the link is full duplex */
60 uint64_t speed:18; /**< Speed of the link in Mbps */
61 } s;
62} cvmx_helper_link_info_t;
63
64#include "cvmx-helper-fpa.h"
65
66#include <asm/octeon/cvmx-helper-errata.h>
67#include "cvmx-helper-loop.h"
68#include "cvmx-helper-npi.h"
69#include "cvmx-helper-rgmii.h"
70#include "cvmx-helper-sgmii.h"
71#include "cvmx-helper-spi.h"
72#include "cvmx-helper-util.h"
73#include "cvmx-helper-xaui.h"
74
75/**
76 * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
77 * priorities[16]) is a function pointer. It is meant to allow
78 * customization of the PKO queue priorities based on the port
79 * number. Users should set this pointer to a function before
80 * calling any cvmx-helper operations.
81 */
82extern void (*cvmx_override_pko_queue_priority) (int pko_port,
83 uint64_t priorities[16]);
84
85/**
86 * cvmx_override_ipd_port_setup(int ipd_port) is a function
87 * pointer. It is meant to allow customization of the IPD port
88 * setup before packet input/output comes online. It is called
89 * after cvmx-helper does the default IPD configuration, but
90 * before IPD is enabled. Users should set this pointer to a
91 * function before calling any cvmx-helper operations.
92 */
93extern void (*cvmx_override_ipd_port_setup) (int ipd_port);
94
95/**
96 * This function enables the IPD and also enables the packet interfaces.
97 * The packet interfaces (RGMII and SPI) must be enabled after the
98 * IPD. This should be called by the user program after any additional
99 * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
100 * is not set in the executive-config.h file.
101 *
102 * Returns 0 on success
103 * -1 on failure
104 */
105extern int cvmx_helper_ipd_and_packet_input_enable(void);
106
107/**
108 * Initialize the PIP, IPD, and PKO hardware to support
109 * simple priority based queues for the ethernet ports. Each
110 * port is configured with a number of priority queues based
111 * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
112 * priority than the previous.
113 *
114 * Returns Zero on success, non-zero on failure
115 */
116extern int cvmx_helper_initialize_packet_io_global(void);
117
118/**
119 * Does core local initialization for packet io
120 *
121 * Returns Zero on success, non-zero on failure
122 */
123extern int cvmx_helper_initialize_packet_io_local(void);
124
125/**
126 * Returns the number of ports on the given interface.
127 * The interface must be initialized before the port count
128 * can be returned.
129 *
130 * @interface: Which interface to return port count for.
131 *
132 * Returns Port count for interface
133 * -1 for uninitialized interface
134 */
135extern int cvmx_helper_ports_on_interface(int interface);
136
137/**
138 * Return the number of interfaces the chip has. Each interface
139 * may have multiple ports. Most chips support two interfaces,
140 * but the CNX0XX and CNX1XX are exceptions. These only support
141 * one interface.
142 *
143 * Returns Number of interfaces on chip
144 */
145extern int cvmx_helper_get_number_of_interfaces(void);
146
147/**
148 * Get the operating mode of an interface. Depending on the Octeon
149 * chip and configuration, this function returns an enumeration
150 * of the type of packet I/O supported by an interface.
151 *
152 * @interface: Interface to probe
153 *
154 * Returns Mode of the interface. Unknown or unsupported interfaces return
155 * DISABLED.
156 */
157extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
158 interface);
159
160/**
161 * Auto configure an IPD/PKO port link state and speed. This
162 * function basically does the equivalent of:
163 * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
164 *
165 * @ipd_port: IPD/PKO port to auto configure
166 *
167 * Returns Link state after configure
168 */
169extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port);
170
171/**
172 * Return the link state of an IPD/PKO port as returned by
173 * auto negotiation. The result of this function may not match
174 * Octeon's link config if auto negotiation has changed since
175 * the last call to cvmx_helper_link_set().
176 *
177 * @ipd_port: IPD/PKO port to query
178 *
179 * Returns Link state
180 */
181extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port);
182
183/**
184 * Configure an IPD/PKO port for the specified link state. This
185 * function does not influence auto negotiation at the PHY level.
186 * The passed link state must always match the link state returned
187 * by cvmx_helper_link_get(). It is normally best to use
188 * cvmx_helper_link_autoconf() instead.
189 *
190 * @ipd_port: IPD/PKO port to configure
191 * @link_info: The new link state
192 *
193 * Returns Zero on success, negative on failure
194 */
195extern int cvmx_helper_link_set(int ipd_port,
196 cvmx_helper_link_info_t link_info);
197
198/**
199 * This function probes an interface to determine the actual
200 * number of hardware ports connected to it. It doesn't setup the
201 * ports or enable them. The main goal here is to set the global
202 * interface_port_count[interface] correctly. Hardware setup of the
203 * ports will be performed later.
204 *
205 * @interface: Interface to probe
206 *
207 * Returns Zero on success, negative on failure
208 */
209extern int cvmx_helper_interface_probe(int interface);
210extern int cvmx_helper_interface_enumerate(int interface);
211
212/**
213 * Configure a port for internal and/or external loopback. Internal loopback
214 * causes packets sent by the port to be received by Octeon. External loopback
215 * causes packets received from the wire to sent out again.
216 *
217 * @ipd_port: IPD/PKO port to loopback.
218 * @enable_internal:
219 * Non zero if you want internal loopback
220 * @enable_external:
221 * Non zero if you want external loopback
222 *
223 * Returns Zero on success, negative on failure.
224 */
225extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal,
226 int enable_external);
227
228#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
new file mode 100644
index 00000000000..115a552c5c7
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
@@ -0,0 +1,338 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Interface to the hardware Input Packet Data unit.
31 */
32
33#ifndef __CVMX_IPD_H__
34#define __CVMX_IPD_H__
35
36#include <asm/octeon/octeon-feature.h>
37
38#include <asm/octeon/cvmx-ipd-defs.h>
39
40enum cvmx_ipd_mode {
41 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
42 CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */
43 CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
44 CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
45};
46
47#ifndef CVMX_ENABLE_LEN_M8_FIX
48#define CVMX_ENABLE_LEN_M8_FIX 0
49#endif
50
51/* CSR typedefs have been moved to cvmx-csr-*.h */
52typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t;
53typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t;
54
55typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
56typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
57
58/**
59 * Configure IPD
60 *
61 * @mbuff_size: Packets buffer size in 8 byte words
62 * @first_mbuff_skip:
63 * Number of 8 byte words to skip in the first buffer
64 * @not_first_mbuff_skip:
65 * Number of 8 byte words to skip in each following buffer
66 * @first_back: Must be same as first_mbuff_skip / 128
67 * @second_back:
68 * Must be same as not_first_mbuff_skip / 128
69 * @wqe_fpa_pool:
70 * FPA pool to get work entries from
71 * @cache_mode:
72 * @back_pres_enable_flag:
73 * Enable or disable port back pressure
74 */
75static inline void cvmx_ipd_config(uint64_t mbuff_size,
76 uint64_t first_mbuff_skip,
77 uint64_t not_first_mbuff_skip,
78 uint64_t first_back,
79 uint64_t second_back,
80 uint64_t wqe_fpa_pool,
81 enum cvmx_ipd_mode cache_mode,
82 uint64_t back_pres_enable_flag)
83{
84 cvmx_ipd_mbuff_first_skip_t first_skip;
85 cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
86 union cvmx_ipd_packet_mbuff_size size;
87 cvmx_ipd_first_next_ptr_back_t first_back_struct;
88 cvmx_ipd_second_next_ptr_back_t second_back_struct;
89 union cvmx_ipd_wqe_fpa_queue wqe_pool;
90 union cvmx_ipd_ctl_status ipd_ctl_reg;
91
92 first_skip.u64 = 0;
93 first_skip.s.skip_sz = first_mbuff_skip;
94 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
95
96 not_first_skip.u64 = 0;
97 not_first_skip.s.skip_sz = not_first_mbuff_skip;
98 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
99
100 size.u64 = 0;
101 size.s.mb_size = mbuff_size;
102 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
103
104 first_back_struct.u64 = 0;
105 first_back_struct.s.back = first_back;
106 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
107
108 second_back_struct.u64 = 0;
109 second_back_struct.s.back = second_back;
110 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64);
111
112 wqe_pool.u64 = 0;
113 wqe_pool.s.wqe_pool = wqe_fpa_pool;
114 cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
115
116 ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
117 ipd_ctl_reg.s.opc_mode = cache_mode;
118 ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
119 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
120
121 /* Note: the example RED code that used to be here has been moved to
122 cvmx_helper_setup_red */
123}
124
125/**
126 * Enable IPD
127 */
128static inline void cvmx_ipd_enable(void)
129{
130 union cvmx_ipd_ctl_status ipd_reg;
131 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
132 if (ipd_reg.s.ipd_en) {
133 cvmx_dprintf
134 ("Warning: Enabling IPD when IPD already enabled.\n");
135 }
136 ipd_reg.s.ipd_en = 1;
137#if CVMX_ENABLE_LEN_M8_FIX
138 if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
139 ipd_reg.s.len_m8 = TRUE;
140#endif
141 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
142}
143
144/**
145 * Disable IPD
146 */
147static inline void cvmx_ipd_disable(void)
148{
149 union cvmx_ipd_ctl_status ipd_reg;
150 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
151 ipd_reg.s.ipd_en = 0;
152 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
153}
154
155/**
156 * Supportive function for cvmx_fpa_shutdown_pool.
157 */
158static inline void cvmx_ipd_free_ptr(void)
159{
160 /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
161 if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
162 && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
163 int no_wptr = 0;
164 union cvmx_ipd_ptr_count ipd_ptr_count;
165 ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
166
167 /* Handle Work Queue Entry in cn56xx and cn52xx */
168 if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
169 union cvmx_ipd_ctl_status ipd_ctl_status;
170 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
171 if (ipd_ctl_status.s.no_wptr)
172 no_wptr = 1;
173 }
174
175 /* Free the prefetched WQE */
176 if (ipd_ptr_count.s.wqev_cnt) {
177 union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid;
178 ipd_wqe_ptr_valid.u64 =
179 cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
180 if (no_wptr)
181 cvmx_fpa_free(cvmx_phys_to_ptr
182 ((uint64_t) ipd_wqe_ptr_valid.s.
183 ptr << 7), CVMX_FPA_PACKET_POOL,
184 0);
185 else
186 cvmx_fpa_free(cvmx_phys_to_ptr
187 ((uint64_t) ipd_wqe_ptr_valid.s.
188 ptr << 7), CVMX_FPA_WQE_POOL, 0);
189 }
190
191 /* Free all WQE in the fifo */
192 if (ipd_ptr_count.s.wqe_pcnt) {
193 int i;
194 union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
195 ipd_pwp_ptr_fifo_ctl.u64 =
196 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
197 for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
198 ipd_pwp_ptr_fifo_ctl.s.cena = 0;
199 ipd_pwp_ptr_fifo_ctl.s.raddr =
200 ipd_pwp_ptr_fifo_ctl.s.max_cnts +
201 (ipd_pwp_ptr_fifo_ctl.s.wraddr +
202 i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
203 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
204 ipd_pwp_ptr_fifo_ctl.u64);
205 ipd_pwp_ptr_fifo_ctl.u64 =
206 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
207 if (no_wptr)
208 cvmx_fpa_free(cvmx_phys_to_ptr
209 ((uint64_t)
210 ipd_pwp_ptr_fifo_ctl.s.
211 ptr << 7),
212 CVMX_FPA_PACKET_POOL, 0);
213 else
214 cvmx_fpa_free(cvmx_phys_to_ptr
215 ((uint64_t)
216 ipd_pwp_ptr_fifo_ctl.s.
217 ptr << 7),
218 CVMX_FPA_WQE_POOL, 0);
219 }
220 ipd_pwp_ptr_fifo_ctl.s.cena = 1;
221 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
222 ipd_pwp_ptr_fifo_ctl.u64);
223 }
224
225 /* Free the prefetched packet */
226 if (ipd_ptr_count.s.pktv_cnt) {
227 union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid;
228 ipd_pkt_ptr_valid.u64 =
229 cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
230 cvmx_fpa_free(cvmx_phys_to_ptr
231 (ipd_pkt_ptr_valid.s.ptr << 7),
232 CVMX_FPA_PACKET_POOL, 0);
233 }
234
235 /* Free the per port prefetched packets */
236 if (1) {
237 int i;
238 union cvmx_ipd_prc_port_ptr_fifo_ctl
239 ipd_prc_port_ptr_fifo_ctl;
240 ipd_prc_port_ptr_fifo_ctl.u64 =
241 cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
242
243 for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
244 i++) {
245 ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
246 ipd_prc_port_ptr_fifo_ctl.s.raddr =
247 i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
248 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
249 ipd_prc_port_ptr_fifo_ctl.u64);
250 ipd_prc_port_ptr_fifo_ctl.u64 =
251 cvmx_read_csr
252 (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
253 cvmx_fpa_free(cvmx_phys_to_ptr
254 ((uint64_t)
255 ipd_prc_port_ptr_fifo_ctl.s.
256 ptr << 7), CVMX_FPA_PACKET_POOL,
257 0);
258 }
259 ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
260 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
261 ipd_prc_port_ptr_fifo_ctl.u64);
262 }
263
264 /* Free all packets in the holding fifo */
265 if (ipd_ptr_count.s.pfif_cnt) {
266 int i;
267 union cvmx_ipd_prc_hold_ptr_fifo_ctl
268 ipd_prc_hold_ptr_fifo_ctl;
269
270 ipd_prc_hold_ptr_fifo_ctl.u64 =
271 cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
272
273 for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
274 ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
275 ipd_prc_hold_ptr_fifo_ctl.s.raddr =
276 (ipd_prc_hold_ptr_fifo_ctl.s.praddr +
277 i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
278 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
279 ipd_prc_hold_ptr_fifo_ctl.u64);
280 ipd_prc_hold_ptr_fifo_ctl.u64 =
281 cvmx_read_csr
282 (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
283 cvmx_fpa_free(cvmx_phys_to_ptr
284 ((uint64_t)
285 ipd_prc_hold_ptr_fifo_ctl.s.
286 ptr << 7), CVMX_FPA_PACKET_POOL,
287 0);
288 }
289 ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
290 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
291 ipd_prc_hold_ptr_fifo_ctl.u64);
292 }
293
294 /* Free all packets in the fifo */
295 if (ipd_ptr_count.s.pkt_pcnt) {
296 int i;
297 union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
298 ipd_pwp_ptr_fifo_ctl.u64 =
299 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
300
301 for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
302 ipd_pwp_ptr_fifo_ctl.s.cena = 0;
303 ipd_pwp_ptr_fifo_ctl.s.raddr =
304 (ipd_pwp_ptr_fifo_ctl.s.praddr +
305 i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
306 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
307 ipd_pwp_ptr_fifo_ctl.u64);
308 ipd_pwp_ptr_fifo_ctl.u64 =
309 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
310 cvmx_fpa_free(cvmx_phys_to_ptr
311 ((uint64_t) ipd_pwp_ptr_fifo_ctl.
312 s.ptr << 7),
313 CVMX_FPA_PACKET_POOL, 0);
314 }
315 ipd_pwp_ptr_fifo_ctl.s.cena = 1;
316 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
317 ipd_pwp_ptr_fifo_ctl.u64);
318 }
319
320 /* Reset the IPD to get all buffers out of it */
321 {
322 union cvmx_ipd_ctl_status ipd_ctl_status;
323 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
324 ipd_ctl_status.s.reset = 1;
325 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
326 }
327
328 /* Reset the PIP */
329 {
330 union cvmx_pip_sft_rst pip_sft_rst;
331 pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
332 pip_sft_rst.s.rst = 1;
333 cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
334 }
335 }
336}
337
338#endif /* __CVMX_IPD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h
new file mode 100644
index 00000000000..d88ab8d8e37
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mdio.h
@@ -0,0 +1,506 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
31 * clause 22 and clause 45 operations.
32 *
33 */
34
35#ifndef __CVMX_MIO_H__
36#define __CVMX_MIO_H__
37
38#include "cvmx-smix-defs.h"
39
40/**
41 * PHY register 0 from the 802.3 spec
42 */
43#define CVMX_MDIO_PHY_REG_CONTROL 0
44typedef union {
45 uint16_t u16;
46 struct {
47 uint16_t reset:1;
48 uint16_t loopback:1;
49 uint16_t speed_lsb:1;
50 uint16_t autoneg_enable:1;
51 uint16_t power_down:1;
52 uint16_t isolate:1;
53 uint16_t restart_autoneg:1;
54 uint16_t duplex:1;
55 uint16_t collision_test:1;
56 uint16_t speed_msb:1;
57 uint16_t unidirectional_enable:1;
58 uint16_t reserved_0_4:5;
59 } s;
60} cvmx_mdio_phy_reg_control_t;
61
62/**
63 * PHY register 1 from the 802.3 spec
64 */
65#define CVMX_MDIO_PHY_REG_STATUS 1
66typedef union {
67 uint16_t u16;
68 struct {
69 uint16_t capable_100base_t4:1;
70 uint16_t capable_100base_x_full:1;
71 uint16_t capable_100base_x_half:1;
72 uint16_t capable_10_full:1;
73 uint16_t capable_10_half:1;
74 uint16_t capable_100base_t2_full:1;
75 uint16_t capable_100base_t2_half:1;
76 uint16_t capable_extended_status:1;
77 uint16_t capable_unidirectional:1;
78 uint16_t capable_mf_preamble_suppression:1;
79 uint16_t autoneg_complete:1;
80 uint16_t remote_fault:1;
81 uint16_t capable_autoneg:1;
82 uint16_t link_status:1;
83 uint16_t jabber_detect:1;
84 uint16_t capable_extended_registers:1;
85
86 } s;
87} cvmx_mdio_phy_reg_status_t;
88
89/**
90 * PHY register 2 from the 802.3 spec
91 */
92#define CVMX_MDIO_PHY_REG_ID1 2
93typedef union {
94 uint16_t u16;
95 struct {
96 uint16_t oui_bits_3_18;
97 } s;
98} cvmx_mdio_phy_reg_id1_t;
99
100/**
101 * PHY register 3 from the 802.3 spec
102 */
103#define CVMX_MDIO_PHY_REG_ID2 3
104typedef union {
105 uint16_t u16;
106 struct {
107 uint16_t oui_bits_19_24:6;
108 uint16_t model:6;
109 uint16_t revision:4;
110 } s;
111} cvmx_mdio_phy_reg_id2_t;
112
113/**
114 * PHY register 4 from the 802.3 spec
115 */
116#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
117typedef union {
118 uint16_t u16;
119 struct {
120 uint16_t next_page:1;
121 uint16_t reserved_14:1;
122 uint16_t remote_fault:1;
123 uint16_t reserved_12:1;
124 uint16_t asymmetric_pause:1;
125 uint16_t pause:1;
126 uint16_t advert_100base_t4:1;
127 uint16_t advert_100base_tx_full:1;
128 uint16_t advert_100base_tx_half:1;
129 uint16_t advert_10base_tx_full:1;
130 uint16_t advert_10base_tx_half:1;
131 uint16_t selector:5;
132 } s;
133} cvmx_mdio_phy_reg_autoneg_adver_t;
134
135/**
136 * PHY register 5 from the 802.3 spec
137 */
138#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
139typedef union {
140 uint16_t u16;
141 struct {
142 uint16_t next_page:1;
143 uint16_t ack:1;
144 uint16_t remote_fault:1;
145 uint16_t reserved_12:1;
146 uint16_t asymmetric_pause:1;
147 uint16_t pause:1;
148 uint16_t advert_100base_t4:1;
149 uint16_t advert_100base_tx_full:1;
150 uint16_t advert_100base_tx_half:1;
151 uint16_t advert_10base_tx_full:1;
152 uint16_t advert_10base_tx_half:1;
153 uint16_t selector:5;
154 } s;
155} cvmx_mdio_phy_reg_link_partner_ability_t;
156
157/**
158 * PHY register 6 from the 802.3 spec
159 */
160#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
161typedef union {
162 uint16_t u16;
163 struct {
164 uint16_t reserved_5_15:11;
165 uint16_t parallel_detection_fault:1;
166 uint16_t link_partner_next_page_capable:1;
167 uint16_t local_next_page_capable:1;
168 uint16_t page_received:1;
169 uint16_t link_partner_autoneg_capable:1;
170
171 } s;
172} cvmx_mdio_phy_reg_autoneg_expansion_t;
173
174/**
175 * PHY register 9 from the 802.3 spec
176 */
177#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
178typedef union {
179 uint16_t u16;
180 struct {
181 uint16_t test_mode:3;
182 uint16_t manual_master_slave:1;
183 uint16_t master:1;
184 uint16_t port_type:1;
185 uint16_t advert_1000base_t_full:1;
186 uint16_t advert_1000base_t_half:1;
187 uint16_t reserved_0_7:8;
188 } s;
189} cvmx_mdio_phy_reg_control_1000_t;
190
191/**
192 * PHY register 10 from the 802.3 spec
193 */
194#define CVMX_MDIO_PHY_REG_STATUS_1000 10
195typedef union {
196 uint16_t u16;
197 struct {
198 uint16_t master_slave_fault:1;
199 uint16_t is_master:1;
200 uint16_t local_receiver_ok:1;
201 uint16_t remote_receiver_ok:1;
202 uint16_t remote_capable_1000base_t_full:1;
203 uint16_t remote_capable_1000base_t_half:1;
204 uint16_t reserved_8_9:2;
205 uint16_t idle_error_count:8;
206 } s;
207} cvmx_mdio_phy_reg_status_1000_t;
208
209/**
210 * PHY register 15 from the 802.3 spec
211 */
212#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
213typedef union {
214 uint16_t u16;
215 struct {
216 uint16_t capable_1000base_x_full:1;
217 uint16_t capable_1000base_x_half:1;
218 uint16_t capable_1000base_t_full:1;
219 uint16_t capable_1000base_t_half:1;
220 uint16_t reserved_0_11:12;
221 } s;
222} cvmx_mdio_phy_reg_extended_status_t;
223
224/**
225 * PHY register 13 from the 802.3 spec
226 */
227#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
228typedef union {
229 uint16_t u16;
230 struct {
231 uint16_t function:2;
232 uint16_t reserved_5_13:9;
233 uint16_t devad:5;
234 } s;
235} cvmx_mdio_phy_reg_mmd_control_t;
236
237/**
238 * PHY register 14 from the 802.3 spec
239 */
240#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
241typedef union {
242 uint16_t u16;
243 struct {
244 uint16_t address_data:16;
245 } s;
246} cvmx_mdio_phy_reg_mmd_address_data_t;
247
248/* Operating request encodings. */
249#define MDIO_CLAUSE_22_WRITE 0
250#define MDIO_CLAUSE_22_READ 1
251
252#define MDIO_CLAUSE_45_ADDRESS 0
253#define MDIO_CLAUSE_45_WRITE 1
254#define MDIO_CLAUSE_45_READ_INC 2
255#define MDIO_CLAUSE_45_READ 3
256
257/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
258#define CVMX_MMD_DEVICE_PMA_PMD 1
259#define CVMX_MMD_DEVICE_WIS 2
260#define CVMX_MMD_DEVICE_PCS 3
261#define CVMX_MMD_DEVICE_PHY_XS 4
262#define CVMX_MMD_DEVICE_DTS_XS 5
263#define CVMX_MMD_DEVICE_TC 6
264#define CVMX_MMD_DEVICE_CL22_EXT 29
265#define CVMX_MMD_DEVICE_VENDOR_1 30
266#define CVMX_MMD_DEVICE_VENDOR_2 31
267
268/* Helper function to put MDIO interface into clause 45 mode */
269static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
270{
271 union cvmx_smix_clk smi_clk;
272 /* Put bus into clause 45 mode */
273 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
274 smi_clk.s.mode = 1;
275 smi_clk.s.preamble = 1;
276 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
277}
278
279/* Helper function to put MDIO interface into clause 22 mode */
280static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
281{
282 union cvmx_smix_clk smi_clk;
283 /* Put bus into clause 22 mode */
284 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
285 smi_clk.s.mode = 0;
286 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
287}
288
289/**
290 * Perform an MII read. This function is used to read PHY
291 * registers controlling auto negotiation.
292 *
293 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
294 * support multiple busses.
295 * @phy_id: The MII phy id
296 * @location: Register location to read
297 *
298 * Returns Result from the read or -1 on failure
299 */
300static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
301{
302 union cvmx_smix_cmd smi_cmd;
303 union cvmx_smix_rd_dat smi_rd;
304 int timeout = 1000;
305
306 if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
307 __cvmx_mdio_set_clause22_mode(bus_id);
308
309 smi_cmd.u64 = 0;
310 smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
311 smi_cmd.s.phy_adr = phy_id;
312 smi_cmd.s.reg_adr = location;
313 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
314
315 do {
316 cvmx_wait(1000);
317 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
318 } while (smi_rd.s.pending && timeout--);
319
320 if (smi_rd.s.val)
321 return smi_rd.s.dat;
322 else
323 return -1;
324}
325
326/**
327 * Perform an MII write. This function is used to write PHY
328 * registers controlling auto negotiation.
329 *
330 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
331 * support multiple busses.
332 * @phy_id: The MII phy id
333 * @location: Register location to write
334 * @val: Value to write
335 *
336 * Returns -1 on error
337 * 0 on success
338 */
339static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
340{
341 union cvmx_smix_cmd smi_cmd;
342 union cvmx_smix_wr_dat smi_wr;
343 int timeout = 1000;
344
345 if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
346 __cvmx_mdio_set_clause22_mode(bus_id);
347
348 smi_wr.u64 = 0;
349 smi_wr.s.dat = val;
350 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
351
352 smi_cmd.u64 = 0;
353 smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
354 smi_cmd.s.phy_adr = phy_id;
355 smi_cmd.s.reg_adr = location;
356 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
357
358 do {
359 cvmx_wait(1000);
360 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
361 } while (smi_wr.s.pending && --timeout);
362 if (timeout <= 0)
363 return -1;
364
365 return 0;
366}
367
368/**
369 * Perform an IEEE 802.3 clause 45 MII read. This function is used to
370 * read PHY registers controlling auto negotiation.
371 *
372 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
373 * support multiple busses.
374 * @phy_id: The MII phy id
375 * @device: MDIO Managable Device (MMD) id
376 * @location: Register location to read
377 *
378 * Returns Result from the read or -1 on failure
379 */
380
381static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
382 int location)
383{
384 union cvmx_smix_cmd smi_cmd;
385 union cvmx_smix_rd_dat smi_rd;
386 union cvmx_smix_wr_dat smi_wr;
387 int timeout = 1000;
388
389 if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
390 return -1;
391
392 __cvmx_mdio_set_clause45_mode(bus_id);
393
394 smi_wr.u64 = 0;
395 smi_wr.s.dat = location;
396 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
397
398 smi_cmd.u64 = 0;
399 smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
400 smi_cmd.s.phy_adr = phy_id;
401 smi_cmd.s.reg_adr = device;
402 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
403
404 do {
405 cvmx_wait(1000);
406 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
407 } while (smi_wr.s.pending && --timeout);
408 if (timeout <= 0) {
409 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
410 "device %2d register %2d TIME OUT(address)\n",
411 bus_id, phy_id, device, location);
412 return -1;
413 }
414
415 smi_cmd.u64 = 0;
416 smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
417 smi_cmd.s.phy_adr = phy_id;
418 smi_cmd.s.reg_adr = device;
419 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
420
421 do {
422 cvmx_wait(1000);
423 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
424 } while (smi_rd.s.pending && --timeout);
425
426 if (timeout <= 0) {
427 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
428 "device %2d register %2d TIME OUT(data)\n",
429 bus_id, phy_id, device, location);
430 return -1;
431 }
432
433 if (smi_rd.s.val)
434 return smi_rd.s.dat;
435 else {
436 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
437 "device %2d register %2d INVALID READ\n",
438 bus_id, phy_id, device, location);
439 return -1;
440 }
441}
442
443/**
444 * Perform an IEEE 802.3 clause 45 MII write. This function is used to
445 * write PHY registers controlling auto negotiation.
446 *
447 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
448 * support multiple busses.
449 * @phy_id: The MII phy id
450 * @device: MDIO Managable Device (MMD) id
451 * @location: Register location to write
452 * @val: Value to write
453 *
454 * Returns -1 on error
455 * 0 on success
456 */
457static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
458 int location, int val)
459{
460 union cvmx_smix_cmd smi_cmd;
461 union cvmx_smix_wr_dat smi_wr;
462 int timeout = 1000;
463
464 if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
465 return -1;
466
467 __cvmx_mdio_set_clause45_mode(bus_id);
468
469 smi_wr.u64 = 0;
470 smi_wr.s.dat = location;
471 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
472
473 smi_cmd.u64 = 0;
474 smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
475 smi_cmd.s.phy_adr = phy_id;
476 smi_cmd.s.reg_adr = device;
477 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
478
479 do {
480 cvmx_wait(1000);
481 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
482 } while (smi_wr.s.pending && --timeout);
483 if (timeout <= 0)
484 return -1;
485
486 smi_wr.u64 = 0;
487 smi_wr.s.dat = val;
488 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
489
490 smi_cmd.u64 = 0;
491 smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
492 smi_cmd.s.phy_adr = phy_id;
493 smi_cmd.s.reg_adr = device;
494 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
495
496 do {
497 cvmx_wait(1000);
498 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
499 } while (smi_wr.s.pending && --timeout);
500 if (timeout <= 0)
501 return -1;
502
503 return 0;
504}
505
506#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 52b14a333ad..b1774126736 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -43,6 +43,22 @@
43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) 43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) 44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) 45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
46#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
47#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
48#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
49#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
50#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
51#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
52#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
53#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
54#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
55#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
56#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
57#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
58#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
59#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
60#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
61#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
46#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) 62#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
47#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) 63#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
48#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) 64#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
@@ -60,6 +76,7 @@
60#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) 76#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
61#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) 77#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
62#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) 78#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
79#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
63#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) 80#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
64#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) 81#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
65#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) 82#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
@@ -68,14 +85,25 @@
68#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) 85#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
69#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) 86#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
70#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) 87#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
88#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
89#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
90#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
91#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
71#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) 92#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
72#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) 93#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
73#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) 94#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
74#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) 95#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
75#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) 96#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
97#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
98#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
99#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
100#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
76#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) 101#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
102#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
77#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) 103#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
78#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) 104#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
105#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
106#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
79#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) 107#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
80#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) 108#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
81#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) 109#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
@@ -183,11 +211,21 @@ union cvmx_mio_boot_bist_stat {
183 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 211 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
184 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 212 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
185 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 213 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
214 struct cvmx_mio_boot_bist_stat_cn61xx {
215 uint64_t reserved_12_63:52;
216 uint64_t stat:12;
217 } cn61xx;
186 struct cvmx_mio_boot_bist_stat_cn63xx { 218 struct cvmx_mio_boot_bist_stat_cn63xx {
187 uint64_t reserved_9_63:55; 219 uint64_t reserved_9_63:55;
188 uint64_t stat:9; 220 uint64_t stat:9;
189 } cn63xx; 221 } cn63xx;
190 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; 222 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
223 struct cvmx_mio_boot_bist_stat_cn66xx {
224 uint64_t reserved_10_63:54;
225 uint64_t stat:10;
226 } cn66xx;
227 struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
228 struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
191}; 229};
192 230
193union cvmx_mio_boot_comp { 231union cvmx_mio_boot_comp {
@@ -204,12 +242,16 @@ union cvmx_mio_boot_comp {
204 struct cvmx_mio_boot_comp_cn50xx cn52xxp1; 242 struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
205 struct cvmx_mio_boot_comp_cn50xx cn56xx; 243 struct cvmx_mio_boot_comp_cn50xx cn56xx;
206 struct cvmx_mio_boot_comp_cn50xx cn56xxp1; 244 struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
207 struct cvmx_mio_boot_comp_cn63xx { 245 struct cvmx_mio_boot_comp_cn61xx {
208 uint64_t reserved_12_63:52; 246 uint64_t reserved_12_63:52;
209 uint64_t pctl:6; 247 uint64_t pctl:6;
210 uint64_t nctl:6; 248 uint64_t nctl:6;
211 } cn63xx; 249 } cn61xx;
212 struct cvmx_mio_boot_comp_cn63xx cn63xxp1; 250 struct cvmx_mio_boot_comp_cn61xx cn63xx;
251 struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
252 struct cvmx_mio_boot_comp_cn61xx cn66xx;
253 struct cvmx_mio_boot_comp_cn61xx cn68xx;
254 struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
213}; 255};
214 256
215union cvmx_mio_boot_dma_cfgx { 257union cvmx_mio_boot_dma_cfgx {
@@ -230,8 +272,12 @@ union cvmx_mio_boot_dma_cfgx {
230 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 272 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
231 struct cvmx_mio_boot_dma_cfgx_s cn56xx; 273 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
232 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 274 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
275 struct cvmx_mio_boot_dma_cfgx_s cn61xx;
233 struct cvmx_mio_boot_dma_cfgx_s cn63xx; 276 struct cvmx_mio_boot_dma_cfgx_s cn63xx;
234 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1; 277 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
278 struct cvmx_mio_boot_dma_cfgx_s cn66xx;
279 struct cvmx_mio_boot_dma_cfgx_s cn68xx;
280 struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
235}; 281};
236 282
237union cvmx_mio_boot_dma_intx { 283union cvmx_mio_boot_dma_intx {
@@ -245,8 +291,12 @@ union cvmx_mio_boot_dma_intx {
245 struct cvmx_mio_boot_dma_intx_s cn52xxp1; 291 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
246 struct cvmx_mio_boot_dma_intx_s cn56xx; 292 struct cvmx_mio_boot_dma_intx_s cn56xx;
247 struct cvmx_mio_boot_dma_intx_s cn56xxp1; 293 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
294 struct cvmx_mio_boot_dma_intx_s cn61xx;
248 struct cvmx_mio_boot_dma_intx_s cn63xx; 295 struct cvmx_mio_boot_dma_intx_s cn63xx;
249 struct cvmx_mio_boot_dma_intx_s cn63xxp1; 296 struct cvmx_mio_boot_dma_intx_s cn63xxp1;
297 struct cvmx_mio_boot_dma_intx_s cn66xx;
298 struct cvmx_mio_boot_dma_intx_s cn68xx;
299 struct cvmx_mio_boot_dma_intx_s cn68xxp1;
250}; 300};
251 301
252union cvmx_mio_boot_dma_int_enx { 302union cvmx_mio_boot_dma_int_enx {
@@ -260,8 +310,12 @@ union cvmx_mio_boot_dma_int_enx {
260 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 310 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
261 struct cvmx_mio_boot_dma_int_enx_s cn56xx; 311 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
262 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 312 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
313 struct cvmx_mio_boot_dma_int_enx_s cn61xx;
263 struct cvmx_mio_boot_dma_int_enx_s cn63xx; 314 struct cvmx_mio_boot_dma_int_enx_s cn63xx;
264 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1; 315 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
316 struct cvmx_mio_boot_dma_int_enx_s cn66xx;
317 struct cvmx_mio_boot_dma_int_enx_s cn68xx;
318 struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
265}; 319};
266 320
267union cvmx_mio_boot_dma_timx { 321union cvmx_mio_boot_dma_timx {
@@ -287,8 +341,12 @@ union cvmx_mio_boot_dma_timx {
287 struct cvmx_mio_boot_dma_timx_s cn52xxp1; 341 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
288 struct cvmx_mio_boot_dma_timx_s cn56xx; 342 struct cvmx_mio_boot_dma_timx_s cn56xx;
289 struct cvmx_mio_boot_dma_timx_s cn56xxp1; 343 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
344 struct cvmx_mio_boot_dma_timx_s cn61xx;
290 struct cvmx_mio_boot_dma_timx_s cn63xx; 345 struct cvmx_mio_boot_dma_timx_s cn63xx;
291 struct cvmx_mio_boot_dma_timx_s cn63xxp1; 346 struct cvmx_mio_boot_dma_timx_s cn63xxp1;
347 struct cvmx_mio_boot_dma_timx_s cn66xx;
348 struct cvmx_mio_boot_dma_timx_s cn68xx;
349 struct cvmx_mio_boot_dma_timx_s cn68xxp1;
292}; 350};
293 351
294union cvmx_mio_boot_err { 352union cvmx_mio_boot_err {
@@ -309,8 +367,12 @@ union cvmx_mio_boot_err {
309 struct cvmx_mio_boot_err_s cn56xxp1; 367 struct cvmx_mio_boot_err_s cn56xxp1;
310 struct cvmx_mio_boot_err_s cn58xx; 368 struct cvmx_mio_boot_err_s cn58xx;
311 struct cvmx_mio_boot_err_s cn58xxp1; 369 struct cvmx_mio_boot_err_s cn58xxp1;
370 struct cvmx_mio_boot_err_s cn61xx;
312 struct cvmx_mio_boot_err_s cn63xx; 371 struct cvmx_mio_boot_err_s cn63xx;
313 struct cvmx_mio_boot_err_s cn63xxp1; 372 struct cvmx_mio_boot_err_s cn63xxp1;
373 struct cvmx_mio_boot_err_s cn66xx;
374 struct cvmx_mio_boot_err_s cn68xx;
375 struct cvmx_mio_boot_err_s cn68xxp1;
314}; 376};
315 377
316union cvmx_mio_boot_int { 378union cvmx_mio_boot_int {
@@ -331,8 +393,12 @@ union cvmx_mio_boot_int {
331 struct cvmx_mio_boot_int_s cn56xxp1; 393 struct cvmx_mio_boot_int_s cn56xxp1;
332 struct cvmx_mio_boot_int_s cn58xx; 394 struct cvmx_mio_boot_int_s cn58xx;
333 struct cvmx_mio_boot_int_s cn58xxp1; 395 struct cvmx_mio_boot_int_s cn58xxp1;
396 struct cvmx_mio_boot_int_s cn61xx;
334 struct cvmx_mio_boot_int_s cn63xx; 397 struct cvmx_mio_boot_int_s cn63xx;
335 struct cvmx_mio_boot_int_s cn63xxp1; 398 struct cvmx_mio_boot_int_s cn63xxp1;
399 struct cvmx_mio_boot_int_s cn66xx;
400 struct cvmx_mio_boot_int_s cn68xx;
401 struct cvmx_mio_boot_int_s cn68xxp1;
336}; 402};
337 403
338union cvmx_mio_boot_loc_adr { 404union cvmx_mio_boot_loc_adr {
@@ -353,8 +419,12 @@ union cvmx_mio_boot_loc_adr {
353 struct cvmx_mio_boot_loc_adr_s cn56xxp1; 419 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
354 struct cvmx_mio_boot_loc_adr_s cn58xx; 420 struct cvmx_mio_boot_loc_adr_s cn58xx;
355 struct cvmx_mio_boot_loc_adr_s cn58xxp1; 421 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
422 struct cvmx_mio_boot_loc_adr_s cn61xx;
356 struct cvmx_mio_boot_loc_adr_s cn63xx; 423 struct cvmx_mio_boot_loc_adr_s cn63xx;
357 struct cvmx_mio_boot_loc_adr_s cn63xxp1; 424 struct cvmx_mio_boot_loc_adr_s cn63xxp1;
425 struct cvmx_mio_boot_loc_adr_s cn66xx;
426 struct cvmx_mio_boot_loc_adr_s cn68xx;
427 struct cvmx_mio_boot_loc_adr_s cn68xxp1;
358}; 428};
359 429
360union cvmx_mio_boot_loc_cfgx { 430union cvmx_mio_boot_loc_cfgx {
@@ -377,8 +447,12 @@ union cvmx_mio_boot_loc_cfgx {
377 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 447 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
378 struct cvmx_mio_boot_loc_cfgx_s cn58xx; 448 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
379 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 449 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
450 struct cvmx_mio_boot_loc_cfgx_s cn61xx;
380 struct cvmx_mio_boot_loc_cfgx_s cn63xx; 451 struct cvmx_mio_boot_loc_cfgx_s cn63xx;
381 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1; 452 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
453 struct cvmx_mio_boot_loc_cfgx_s cn66xx;
454 struct cvmx_mio_boot_loc_cfgx_s cn68xx;
455 struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
382}; 456};
383 457
384union cvmx_mio_boot_loc_dat { 458union cvmx_mio_boot_loc_dat {
@@ -397,14 +471,19 @@ union cvmx_mio_boot_loc_dat {
397 struct cvmx_mio_boot_loc_dat_s cn56xxp1; 471 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
398 struct cvmx_mio_boot_loc_dat_s cn58xx; 472 struct cvmx_mio_boot_loc_dat_s cn58xx;
399 struct cvmx_mio_boot_loc_dat_s cn58xxp1; 473 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
474 struct cvmx_mio_boot_loc_dat_s cn61xx;
400 struct cvmx_mio_boot_loc_dat_s cn63xx; 475 struct cvmx_mio_boot_loc_dat_s cn63xx;
401 struct cvmx_mio_boot_loc_dat_s cn63xxp1; 476 struct cvmx_mio_boot_loc_dat_s cn63xxp1;
477 struct cvmx_mio_boot_loc_dat_s cn66xx;
478 struct cvmx_mio_boot_loc_dat_s cn68xx;
479 struct cvmx_mio_boot_loc_dat_s cn68xxp1;
402}; 480};
403 481
404union cvmx_mio_boot_pin_defs { 482union cvmx_mio_boot_pin_defs {
405 uint64_t u64; 483 uint64_t u64;
406 struct cvmx_mio_boot_pin_defs_s { 484 struct cvmx_mio_boot_pin_defs_s {
407 uint64_t reserved_16_63:48; 485 uint64_t reserved_32_63:32;
486 uint64_t user1:16;
408 uint64_t ale:1; 487 uint64_t ale:1;
409 uint64_t width:1; 488 uint64_t width:1;
410 uint64_t dmack_p2:1; 489 uint64_t dmack_p2:1;
@@ -412,7 +491,7 @@ union cvmx_mio_boot_pin_defs {
412 uint64_t dmack_p0:1; 491 uint64_t dmack_p0:1;
413 uint64_t term:2; 492 uint64_t term:2;
414 uint64_t nand:1; 493 uint64_t nand:1;
415 uint64_t reserved_0_7:8; 494 uint64_t user0:8;
416 } s; 495 } s;
417 struct cvmx_mio_boot_pin_defs_cn52xx { 496 struct cvmx_mio_boot_pin_defs_cn52xx {
418 uint64_t reserved_16_63:48; 497 uint64_t reserved_16_63:48;
@@ -435,8 +514,23 @@ union cvmx_mio_boot_pin_defs {
435 uint64_t term:2; 514 uint64_t term:2;
436 uint64_t reserved_0_8:9; 515 uint64_t reserved_0_8:9;
437 } cn56xx; 516 } cn56xx;
517 struct cvmx_mio_boot_pin_defs_cn61xx {
518 uint64_t reserved_32_63:32;
519 uint64_t user1:16;
520 uint64_t ale:1;
521 uint64_t width:1;
522 uint64_t reserved_13_13:1;
523 uint64_t dmack_p1:1;
524 uint64_t dmack_p0:1;
525 uint64_t term:2;
526 uint64_t nand:1;
527 uint64_t user0:8;
528 } cn61xx;
438 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; 529 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
439 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; 530 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
531 struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
532 struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
533 struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
440}; 534};
441 535
442union cvmx_mio_boot_reg_cfgx { 536union cvmx_mio_boot_reg_cfgx {
@@ -498,8 +592,12 @@ union cvmx_mio_boot_reg_cfgx {
498 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 592 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
499 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 593 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
500 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 594 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
595 struct cvmx_mio_boot_reg_cfgx_s cn61xx;
501 struct cvmx_mio_boot_reg_cfgx_s cn63xx; 596 struct cvmx_mio_boot_reg_cfgx_s cn63xx;
502 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1; 597 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
598 struct cvmx_mio_boot_reg_cfgx_s cn66xx;
599 struct cvmx_mio_boot_reg_cfgx_s cn68xx;
600 struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
503}; 601};
504 602
505union cvmx_mio_boot_reg_timx { 603union cvmx_mio_boot_reg_timx {
@@ -544,8 +642,12 @@ union cvmx_mio_boot_reg_timx {
544 struct cvmx_mio_boot_reg_timx_s cn56xxp1; 642 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
545 struct cvmx_mio_boot_reg_timx_s cn58xx; 643 struct cvmx_mio_boot_reg_timx_s cn58xx;
546 struct cvmx_mio_boot_reg_timx_s cn58xxp1; 644 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
645 struct cvmx_mio_boot_reg_timx_s cn61xx;
547 struct cvmx_mio_boot_reg_timx_s cn63xx; 646 struct cvmx_mio_boot_reg_timx_s cn63xx;
548 struct cvmx_mio_boot_reg_timx_s cn63xxp1; 647 struct cvmx_mio_boot_reg_timx_s cn63xxp1;
648 struct cvmx_mio_boot_reg_timx_s cn66xx;
649 struct cvmx_mio_boot_reg_timx_s cn68xx;
650 struct cvmx_mio_boot_reg_timx_s cn68xxp1;
549}; 651};
550 652
551union cvmx_mio_boot_thr { 653union cvmx_mio_boot_thr {
@@ -574,8 +676,231 @@ union cvmx_mio_boot_thr {
574 struct cvmx_mio_boot_thr_s cn56xxp1; 676 struct cvmx_mio_boot_thr_s cn56xxp1;
575 struct cvmx_mio_boot_thr_cn30xx cn58xx; 677 struct cvmx_mio_boot_thr_cn30xx cn58xx;
576 struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 678 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
679 struct cvmx_mio_boot_thr_s cn61xx;
577 struct cvmx_mio_boot_thr_s cn63xx; 680 struct cvmx_mio_boot_thr_s cn63xx;
578 struct cvmx_mio_boot_thr_s cn63xxp1; 681 struct cvmx_mio_boot_thr_s cn63xxp1;
682 struct cvmx_mio_boot_thr_s cn66xx;
683 struct cvmx_mio_boot_thr_s cn68xx;
684 struct cvmx_mio_boot_thr_s cn68xxp1;
685};
686
687union cvmx_mio_emm_buf_dat {
688 uint64_t u64;
689 struct cvmx_mio_emm_buf_dat_s {
690 uint64_t dat:64;
691 } s;
692 struct cvmx_mio_emm_buf_dat_s cn61xx;
693};
694
695union cvmx_mio_emm_buf_idx {
696 uint64_t u64;
697 struct cvmx_mio_emm_buf_idx_s {
698 uint64_t reserved_17_63:47;
699 uint64_t inc:1;
700 uint64_t reserved_7_15:9;
701 uint64_t buf_num:1;
702 uint64_t offset:6;
703 } s;
704 struct cvmx_mio_emm_buf_idx_s cn61xx;
705};
706
707union cvmx_mio_emm_cfg {
708 uint64_t u64;
709 struct cvmx_mio_emm_cfg_s {
710 uint64_t reserved_17_63:47;
711 uint64_t boot_fail:1;
712 uint64_t reserved_4_15:12;
713 uint64_t bus_ena:4;
714 } s;
715 struct cvmx_mio_emm_cfg_s cn61xx;
716};
717
718union cvmx_mio_emm_cmd {
719 uint64_t u64;
720 struct cvmx_mio_emm_cmd_s {
721 uint64_t reserved_62_63:2;
722 uint64_t bus_id:2;
723 uint64_t cmd_val:1;
724 uint64_t reserved_56_58:3;
725 uint64_t dbuf:1;
726 uint64_t offset:6;
727 uint64_t reserved_43_48:6;
728 uint64_t ctype_xor:2;
729 uint64_t rtype_xor:3;
730 uint64_t cmd_idx:6;
731 uint64_t arg:32;
732 } s;
733 struct cvmx_mio_emm_cmd_s cn61xx;
734};
735
736union cvmx_mio_emm_dma {
737 uint64_t u64;
738 struct cvmx_mio_emm_dma_s {
739 uint64_t reserved_62_63:2;
740 uint64_t bus_id:2;
741 uint64_t dma_val:1;
742 uint64_t sector:1;
743 uint64_t dat_null:1;
744 uint64_t thres:6;
745 uint64_t rel_wr:1;
746 uint64_t rw:1;
747 uint64_t multi:1;
748 uint64_t block_cnt:16;
749 uint64_t card_addr:32;
750 } s;
751 struct cvmx_mio_emm_dma_s cn61xx;
752};
753
754union cvmx_mio_emm_int {
755 uint64_t u64;
756 struct cvmx_mio_emm_int_s {
757 uint64_t reserved_7_63:57;
758 uint64_t switch_err:1;
759 uint64_t switch_done:1;
760 uint64_t dma_err:1;
761 uint64_t cmd_err:1;
762 uint64_t dma_done:1;
763 uint64_t cmd_done:1;
764 uint64_t buf_done:1;
765 } s;
766 struct cvmx_mio_emm_int_s cn61xx;
767};
768
769union cvmx_mio_emm_int_en {
770 uint64_t u64;
771 struct cvmx_mio_emm_int_en_s {
772 uint64_t reserved_7_63:57;
773 uint64_t switch_err:1;
774 uint64_t switch_done:1;
775 uint64_t dma_err:1;
776 uint64_t cmd_err:1;
777 uint64_t dma_done:1;
778 uint64_t cmd_done:1;
779 uint64_t buf_done:1;
780 } s;
781 struct cvmx_mio_emm_int_en_s cn61xx;
782};
783
784union cvmx_mio_emm_modex {
785 uint64_t u64;
786 struct cvmx_mio_emm_modex_s {
787 uint64_t reserved_49_63:15;
788 uint64_t hs_timing:1;
789 uint64_t reserved_43_47:5;
790 uint64_t bus_width:3;
791 uint64_t reserved_36_39:4;
792 uint64_t power_class:4;
793 uint64_t clk_hi:16;
794 uint64_t clk_lo:16;
795 } s;
796 struct cvmx_mio_emm_modex_s cn61xx;
797};
798
799union cvmx_mio_emm_rca {
800 uint64_t u64;
801 struct cvmx_mio_emm_rca_s {
802 uint64_t reserved_16_63:48;
803 uint64_t card_rca:16;
804 } s;
805 struct cvmx_mio_emm_rca_s cn61xx;
806};
807
808union cvmx_mio_emm_rsp_hi {
809 uint64_t u64;
810 struct cvmx_mio_emm_rsp_hi_s {
811 uint64_t dat:64;
812 } s;
813 struct cvmx_mio_emm_rsp_hi_s cn61xx;
814};
815
816union cvmx_mio_emm_rsp_lo {
817 uint64_t u64;
818 struct cvmx_mio_emm_rsp_lo_s {
819 uint64_t dat:64;
820 } s;
821 struct cvmx_mio_emm_rsp_lo_s cn61xx;
822};
823
824union cvmx_mio_emm_rsp_sts {
825 uint64_t u64;
826 struct cvmx_mio_emm_rsp_sts_s {
827 uint64_t reserved_62_63:2;
828 uint64_t bus_id:2;
829 uint64_t cmd_val:1;
830 uint64_t switch_val:1;
831 uint64_t dma_val:1;
832 uint64_t dma_pend:1;
833 uint64_t reserved_29_55:27;
834 uint64_t dbuf_err:1;
835 uint64_t reserved_24_27:4;
836 uint64_t dbuf:1;
837 uint64_t blk_timeout:1;
838 uint64_t blk_crc_err:1;
839 uint64_t rsp_busybit:1;
840 uint64_t stp_timeout:1;
841 uint64_t stp_crc_err:1;
842 uint64_t stp_bad_sts:1;
843 uint64_t stp_val:1;
844 uint64_t rsp_timeout:1;
845 uint64_t rsp_crc_err:1;
846 uint64_t rsp_bad_sts:1;
847 uint64_t rsp_val:1;
848 uint64_t rsp_type:3;
849 uint64_t cmd_type:2;
850 uint64_t cmd_idx:6;
851 uint64_t cmd_done:1;
852 } s;
853 struct cvmx_mio_emm_rsp_sts_s cn61xx;
854};
855
856union cvmx_mio_emm_sample {
857 uint64_t u64;
858 struct cvmx_mio_emm_sample_s {
859 uint64_t reserved_26_63:38;
860 uint64_t cmd_cnt:10;
861 uint64_t reserved_10_15:6;
862 uint64_t dat_cnt:10;
863 } s;
864 struct cvmx_mio_emm_sample_s cn61xx;
865};
866
867union cvmx_mio_emm_sts_mask {
868 uint64_t u64;
869 struct cvmx_mio_emm_sts_mask_s {
870 uint64_t reserved_32_63:32;
871 uint64_t sts_msk:32;
872 } s;
873 struct cvmx_mio_emm_sts_mask_s cn61xx;
874};
875
876union cvmx_mio_emm_switch {
877 uint64_t u64;
878 struct cvmx_mio_emm_switch_s {
879 uint64_t reserved_62_63:2;
880 uint64_t bus_id:2;
881 uint64_t switch_exe:1;
882 uint64_t switch_err0:1;
883 uint64_t switch_err1:1;
884 uint64_t switch_err2:1;
885 uint64_t reserved_49_55:7;
886 uint64_t hs_timing:1;
887 uint64_t reserved_43_47:5;
888 uint64_t bus_width:3;
889 uint64_t reserved_36_39:4;
890 uint64_t power_class:4;
891 uint64_t clk_hi:16;
892 uint64_t clk_lo:16;
893 } s;
894 struct cvmx_mio_emm_switch_s cn61xx;
895};
896
897union cvmx_mio_emm_wdog {
898 uint64_t u64;
899 struct cvmx_mio_emm_wdog_s {
900 uint64_t reserved_26_63:38;
901 uint64_t clk_cnt:26;
902 } s;
903 struct cvmx_mio_emm_wdog_s cn61xx;
579}; 904};
580 905
581union cvmx_mio_fus_bnk_datx { 906union cvmx_mio_fus_bnk_datx {
@@ -590,8 +915,12 @@ union cvmx_mio_fus_bnk_datx {
590 struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 915 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
591 struct cvmx_mio_fus_bnk_datx_s cn58xx; 916 struct cvmx_mio_fus_bnk_datx_s cn58xx;
592 struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 917 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
918 struct cvmx_mio_fus_bnk_datx_s cn61xx;
593 struct cvmx_mio_fus_bnk_datx_s cn63xx; 919 struct cvmx_mio_fus_bnk_datx_s cn63xx;
594 struct cvmx_mio_fus_bnk_datx_s cn63xxp1; 920 struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
921 struct cvmx_mio_fus_bnk_datx_s cn66xx;
922 struct cvmx_mio_fus_bnk_datx_s cn68xx;
923 struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
595}; 924};
596 925
597union cvmx_mio_fus_dat0 { 926union cvmx_mio_fus_dat0 {
@@ -611,8 +940,12 @@ union cvmx_mio_fus_dat0 {
611 struct cvmx_mio_fus_dat0_s cn56xxp1; 940 struct cvmx_mio_fus_dat0_s cn56xxp1;
612 struct cvmx_mio_fus_dat0_s cn58xx; 941 struct cvmx_mio_fus_dat0_s cn58xx;
613 struct cvmx_mio_fus_dat0_s cn58xxp1; 942 struct cvmx_mio_fus_dat0_s cn58xxp1;
943 struct cvmx_mio_fus_dat0_s cn61xx;
614 struct cvmx_mio_fus_dat0_s cn63xx; 944 struct cvmx_mio_fus_dat0_s cn63xx;
615 struct cvmx_mio_fus_dat0_s cn63xxp1; 945 struct cvmx_mio_fus_dat0_s cn63xxp1;
946 struct cvmx_mio_fus_dat0_s cn66xx;
947 struct cvmx_mio_fus_dat0_s cn68xx;
948 struct cvmx_mio_fus_dat0_s cn68xxp1;
616}; 949};
617 950
618union cvmx_mio_fus_dat1 { 951union cvmx_mio_fus_dat1 {
@@ -632,14 +965,21 @@ union cvmx_mio_fus_dat1 {
632 struct cvmx_mio_fus_dat1_s cn56xxp1; 965 struct cvmx_mio_fus_dat1_s cn56xxp1;
633 struct cvmx_mio_fus_dat1_s cn58xx; 966 struct cvmx_mio_fus_dat1_s cn58xx;
634 struct cvmx_mio_fus_dat1_s cn58xxp1; 967 struct cvmx_mio_fus_dat1_s cn58xxp1;
968 struct cvmx_mio_fus_dat1_s cn61xx;
635 struct cvmx_mio_fus_dat1_s cn63xx; 969 struct cvmx_mio_fus_dat1_s cn63xx;
636 struct cvmx_mio_fus_dat1_s cn63xxp1; 970 struct cvmx_mio_fus_dat1_s cn63xxp1;
971 struct cvmx_mio_fus_dat1_s cn66xx;
972 struct cvmx_mio_fus_dat1_s cn68xx;
973 struct cvmx_mio_fus_dat1_s cn68xxp1;
637}; 974};
638 975
639union cvmx_mio_fus_dat2 { 976union cvmx_mio_fus_dat2 {
640 uint64_t u64; 977 uint64_t u64;
641 struct cvmx_mio_fus_dat2_s { 978 struct cvmx_mio_fus_dat2_s {
642 uint64_t reserved_35_63:29; 979 uint64_t reserved_48_63:16;
980 uint64_t fus118:1;
981 uint64_t rom_info:10;
982 uint64_t power_limit:2;
643 uint64_t dorm_crypto:1; 983 uint64_t dorm_crypto:1;
644 uint64_t fus318:1; 984 uint64_t fus318:1;
645 uint64_t raid_en:1; 985 uint64_t raid_en:1;
@@ -747,6 +1087,23 @@ union cvmx_mio_fus_dat2 {
747 uint64_t pp_dis:16; 1087 uint64_t pp_dis:16;
748 } cn58xx; 1088 } cn58xx;
749 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 1089 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
1090 struct cvmx_mio_fus_dat2_cn61xx {
1091 uint64_t reserved_48_63:16;
1092 uint64_t fus118:1;
1093 uint64_t rom_info:10;
1094 uint64_t power_limit:2;
1095 uint64_t dorm_crypto:1;
1096 uint64_t fus318:1;
1097 uint64_t raid_en:1;
1098 uint64_t reserved_29_31:3;
1099 uint64_t nodfa_cp2:1;
1100 uint64_t nomul:1;
1101 uint64_t nocrypto:1;
1102 uint64_t reserved_24_25:2;
1103 uint64_t chip_id:8;
1104 uint64_t reserved_4_15:12;
1105 uint64_t pp_dis:4;
1106 } cn61xx;
750 struct cvmx_mio_fus_dat2_cn63xx { 1107 struct cvmx_mio_fus_dat2_cn63xx {
751 uint64_t reserved_35_63:29; 1108 uint64_t reserved_35_63:29;
752 uint64_t dorm_crypto:1; 1109 uint64_t dorm_crypto:1;
@@ -762,6 +1119,38 @@ union cvmx_mio_fus_dat2 {
762 uint64_t pp_dis:6; 1119 uint64_t pp_dis:6;
763 } cn63xx; 1120 } cn63xx;
764 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; 1121 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
1122 struct cvmx_mio_fus_dat2_cn66xx {
1123 uint64_t reserved_48_63:16;
1124 uint64_t fus118:1;
1125 uint64_t rom_info:10;
1126 uint64_t power_limit:2;
1127 uint64_t dorm_crypto:1;
1128 uint64_t fus318:1;
1129 uint64_t raid_en:1;
1130 uint64_t reserved_29_31:3;
1131 uint64_t nodfa_cp2:1;
1132 uint64_t nomul:1;
1133 uint64_t nocrypto:1;
1134 uint64_t reserved_24_25:2;
1135 uint64_t chip_id:8;
1136 uint64_t reserved_10_15:6;
1137 uint64_t pp_dis:10;
1138 } cn66xx;
1139 struct cvmx_mio_fus_dat2_cn68xx {
1140 uint64_t reserved_37_63:27;
1141 uint64_t power_limit:2;
1142 uint64_t dorm_crypto:1;
1143 uint64_t fus318:1;
1144 uint64_t raid_en:1;
1145 uint64_t reserved_29_31:3;
1146 uint64_t nodfa_cp2:1;
1147 uint64_t nomul:1;
1148 uint64_t nocrypto:1;
1149 uint64_t reserved_24_25:2;
1150 uint64_t chip_id:8;
1151 uint64_t reserved_0_15:16;
1152 } cn68xx;
1153 struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
765}; 1154};
766 1155
767union cvmx_mio_fus_dat3 { 1156union cvmx_mio_fus_dat3 {
@@ -834,7 +1223,7 @@ union cvmx_mio_fus_dat3 {
834 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 1223 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
835 struct cvmx_mio_fus_dat3_cn38xx cn58xx; 1224 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
836 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 1225 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
837 struct cvmx_mio_fus_dat3_cn63xx { 1226 struct cvmx_mio_fus_dat3_cn61xx {
838 uint64_t reserved_58_63:6; 1227 uint64_t reserved_58_63:6;
839 uint64_t pll_ctl:10; 1228 uint64_t pll_ctl:10;
840 uint64_t dfa_info_dte:3; 1229 uint64_t dfa_info_dte:3;
@@ -853,8 +1242,12 @@ union cvmx_mio_fus_dat3 {
853 uint64_t nozip:1; 1242 uint64_t nozip:1;
854 uint64_t nodfa_dte:1; 1243 uint64_t nodfa_dte:1;
855 uint64_t reserved_0_23:24; 1244 uint64_t reserved_0_23:24;
856 } cn63xx; 1245 } cn61xx;
857 struct cvmx_mio_fus_dat3_cn63xx cn63xxp1; 1246 struct cvmx_mio_fus_dat3_cn61xx cn63xx;
1247 struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
1248 struct cvmx_mio_fus_dat3_cn61xx cn66xx;
1249 struct cvmx_mio_fus_dat3_cn61xx cn68xx;
1250 struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
858}; 1251};
859 1252
860union cvmx_mio_fus_ema { 1253union cvmx_mio_fus_ema {
@@ -875,8 +1268,12 @@ union cvmx_mio_fus_ema {
875 uint64_t ema:2; 1268 uint64_t ema:2;
876 } cn58xx; 1269 } cn58xx;
877 struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 1270 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
1271 struct cvmx_mio_fus_ema_s cn61xx;
878 struct cvmx_mio_fus_ema_s cn63xx; 1272 struct cvmx_mio_fus_ema_s cn63xx;
879 struct cvmx_mio_fus_ema_s cn63xxp1; 1273 struct cvmx_mio_fus_ema_s cn63xxp1;
1274 struct cvmx_mio_fus_ema_s cn66xx;
1275 struct cvmx_mio_fus_ema_s cn68xx;
1276 struct cvmx_mio_fus_ema_s cn68xxp1;
880}; 1277};
881 1278
882union cvmx_mio_fus_pdf { 1279union cvmx_mio_fus_pdf {
@@ -890,14 +1287,21 @@ union cvmx_mio_fus_pdf {
890 struct cvmx_mio_fus_pdf_s cn56xx; 1287 struct cvmx_mio_fus_pdf_s cn56xx;
891 struct cvmx_mio_fus_pdf_s cn56xxp1; 1288 struct cvmx_mio_fus_pdf_s cn56xxp1;
892 struct cvmx_mio_fus_pdf_s cn58xx; 1289 struct cvmx_mio_fus_pdf_s cn58xx;
1290 struct cvmx_mio_fus_pdf_s cn61xx;
893 struct cvmx_mio_fus_pdf_s cn63xx; 1291 struct cvmx_mio_fus_pdf_s cn63xx;
894 struct cvmx_mio_fus_pdf_s cn63xxp1; 1292 struct cvmx_mio_fus_pdf_s cn63xxp1;
1293 struct cvmx_mio_fus_pdf_s cn66xx;
1294 struct cvmx_mio_fus_pdf_s cn68xx;
1295 struct cvmx_mio_fus_pdf_s cn68xxp1;
895}; 1296};
896 1297
897union cvmx_mio_fus_pll { 1298union cvmx_mio_fus_pll {
898 uint64_t u64; 1299 uint64_t u64;
899 struct cvmx_mio_fus_pll_s { 1300 struct cvmx_mio_fus_pll_s {
900 uint64_t reserved_8_63:56; 1301 uint64_t reserved_48_63:16;
1302 uint64_t rclk_align_r:8;
1303 uint64_t rclk_align_l:8;
1304 uint64_t reserved_8_31:24;
901 uint64_t c_cout_rst:1; 1305 uint64_t c_cout_rst:1;
902 uint64_t c_cout_sel:2; 1306 uint64_t c_cout_sel:2;
903 uint64_t pnr_cout_rst:1; 1307 uint64_t pnr_cout_rst:1;
@@ -916,8 +1320,20 @@ union cvmx_mio_fus_pll {
916 struct cvmx_mio_fus_pll_cn50xx cn56xxp1; 1320 struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
917 struct cvmx_mio_fus_pll_cn50xx cn58xx; 1321 struct cvmx_mio_fus_pll_cn50xx cn58xx;
918 struct cvmx_mio_fus_pll_cn50xx cn58xxp1; 1322 struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
919 struct cvmx_mio_fus_pll_s cn63xx; 1323 struct cvmx_mio_fus_pll_cn61xx {
920 struct cvmx_mio_fus_pll_s cn63xxp1; 1324 uint64_t reserved_8_63:56;
1325 uint64_t c_cout_rst:1;
1326 uint64_t c_cout_sel:2;
1327 uint64_t pnr_cout_rst:1;
1328 uint64_t pnr_cout_sel:2;
1329 uint64_t rfslip:1;
1330 uint64_t fbslip:1;
1331 } cn61xx;
1332 struct cvmx_mio_fus_pll_cn61xx cn63xx;
1333 struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
1334 struct cvmx_mio_fus_pll_cn61xx cn66xx;
1335 struct cvmx_mio_fus_pll_s cn68xx;
1336 struct cvmx_mio_fus_pll_s cn68xxp1;
921}; 1337};
922 1338
923union cvmx_mio_fus_prog { 1339union cvmx_mio_fus_prog {
@@ -941,8 +1357,12 @@ union cvmx_mio_fus_prog {
941 struct cvmx_mio_fus_prog_cn30xx cn56xxp1; 1357 struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
942 struct cvmx_mio_fus_prog_cn30xx cn58xx; 1358 struct cvmx_mio_fus_prog_cn30xx cn58xx;
943 struct cvmx_mio_fus_prog_cn30xx cn58xxp1; 1359 struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
1360 struct cvmx_mio_fus_prog_s cn61xx;
944 struct cvmx_mio_fus_prog_s cn63xx; 1361 struct cvmx_mio_fus_prog_s cn63xx;
945 struct cvmx_mio_fus_prog_s cn63xxp1; 1362 struct cvmx_mio_fus_prog_s cn63xxp1;
1363 struct cvmx_mio_fus_prog_s cn66xx;
1364 struct cvmx_mio_fus_prog_s cn68xx;
1365 struct cvmx_mio_fus_prog_s cn68xxp1;
946}; 1366};
947 1367
948union cvmx_mio_fus_prog_times { 1368union cvmx_mio_fus_prog_times {
@@ -969,7 +1389,7 @@ union cvmx_mio_fus_prog_times {
969 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1; 1389 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
970 struct cvmx_mio_fus_prog_times_cn50xx cn58xx; 1390 struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
971 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; 1391 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
972 struct cvmx_mio_fus_prog_times_cn63xx { 1392 struct cvmx_mio_fus_prog_times_cn61xx {
973 uint64_t reserved_35_63:29; 1393 uint64_t reserved_35_63:29;
974 uint64_t vgate_pin:1; 1394 uint64_t vgate_pin:1;
975 uint64_t fsrc_pin:1; 1395 uint64_t fsrc_pin:1;
@@ -978,8 +1398,12 @@ union cvmx_mio_fus_prog_times {
978 uint64_t sclk_lo:4; 1398 uint64_t sclk_lo:4;
979 uint64_t sclk_hi:15; 1399 uint64_t sclk_hi:15;
980 uint64_t setup:6; 1400 uint64_t setup:6;
981 } cn63xx; 1401 } cn61xx;
982 struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1; 1402 struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
1403 struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
1404 struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
1405 struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
1406 struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
983}; 1407};
984 1408
985union cvmx_mio_fus_rcmd { 1409union cvmx_mio_fus_rcmd {
@@ -1013,8 +1437,12 @@ union cvmx_mio_fus_rcmd {
1013 struct cvmx_mio_fus_rcmd_s cn56xxp1; 1437 struct cvmx_mio_fus_rcmd_s cn56xxp1;
1014 struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 1438 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
1015 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 1439 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
1440 struct cvmx_mio_fus_rcmd_s cn61xx;
1016 struct cvmx_mio_fus_rcmd_s cn63xx; 1441 struct cvmx_mio_fus_rcmd_s cn63xx;
1017 struct cvmx_mio_fus_rcmd_s cn63xxp1; 1442 struct cvmx_mio_fus_rcmd_s cn63xxp1;
1443 struct cvmx_mio_fus_rcmd_s cn66xx;
1444 struct cvmx_mio_fus_rcmd_s cn68xx;
1445 struct cvmx_mio_fus_rcmd_s cn68xxp1;
1018}; 1446};
1019 1447
1020union cvmx_mio_fus_read_times { 1448union cvmx_mio_fus_read_times {
@@ -1027,8 +1455,12 @@ union cvmx_mio_fus_read_times {
1027 uint64_t sdh:4; 1455 uint64_t sdh:4;
1028 uint64_t setup:10; 1456 uint64_t setup:10;
1029 } s; 1457 } s;
1458 struct cvmx_mio_fus_read_times_s cn61xx;
1030 struct cvmx_mio_fus_read_times_s cn63xx; 1459 struct cvmx_mio_fus_read_times_s cn63xx;
1031 struct cvmx_mio_fus_read_times_s cn63xxp1; 1460 struct cvmx_mio_fus_read_times_s cn63xxp1;
1461 struct cvmx_mio_fus_read_times_s cn66xx;
1462 struct cvmx_mio_fus_read_times_s cn68xx;
1463 struct cvmx_mio_fus_read_times_s cn68xxp1;
1032}; 1464};
1033 1465
1034union cvmx_mio_fus_repair_res0 { 1466union cvmx_mio_fus_repair_res0 {
@@ -1040,8 +1472,12 @@ union cvmx_mio_fus_repair_res0 {
1040 uint64_t repair1:18; 1472 uint64_t repair1:18;
1041 uint64_t repair0:18; 1473 uint64_t repair0:18;
1042 } s; 1474 } s;
1475 struct cvmx_mio_fus_repair_res0_s cn61xx;
1043 struct cvmx_mio_fus_repair_res0_s cn63xx; 1476 struct cvmx_mio_fus_repair_res0_s cn63xx;
1044 struct cvmx_mio_fus_repair_res0_s cn63xxp1; 1477 struct cvmx_mio_fus_repair_res0_s cn63xxp1;
1478 struct cvmx_mio_fus_repair_res0_s cn66xx;
1479 struct cvmx_mio_fus_repair_res0_s cn68xx;
1480 struct cvmx_mio_fus_repair_res0_s cn68xxp1;
1045}; 1481};
1046 1482
1047union cvmx_mio_fus_repair_res1 { 1483union cvmx_mio_fus_repair_res1 {
@@ -1052,8 +1488,12 @@ union cvmx_mio_fus_repair_res1 {
1052 uint64_t repair4:18; 1488 uint64_t repair4:18;
1053 uint64_t repair3:18; 1489 uint64_t repair3:18;
1054 } s; 1490 } s;
1491 struct cvmx_mio_fus_repair_res1_s cn61xx;
1055 struct cvmx_mio_fus_repair_res1_s cn63xx; 1492 struct cvmx_mio_fus_repair_res1_s cn63xx;
1056 struct cvmx_mio_fus_repair_res1_s cn63xxp1; 1493 struct cvmx_mio_fus_repair_res1_s cn63xxp1;
1494 struct cvmx_mio_fus_repair_res1_s cn66xx;
1495 struct cvmx_mio_fus_repair_res1_s cn68xx;
1496 struct cvmx_mio_fus_repair_res1_s cn68xxp1;
1057}; 1497};
1058 1498
1059union cvmx_mio_fus_repair_res2 { 1499union cvmx_mio_fus_repair_res2 {
@@ -1062,8 +1502,12 @@ union cvmx_mio_fus_repair_res2 {
1062 uint64_t reserved_18_63:46; 1502 uint64_t reserved_18_63:46;
1063 uint64_t repair6:18; 1503 uint64_t repair6:18;
1064 } s; 1504 } s;
1505 struct cvmx_mio_fus_repair_res2_s cn61xx;
1065 struct cvmx_mio_fus_repair_res2_s cn63xx; 1506 struct cvmx_mio_fus_repair_res2_s cn63xx;
1066 struct cvmx_mio_fus_repair_res2_s cn63xxp1; 1507 struct cvmx_mio_fus_repair_res2_s cn63xxp1;
1508 struct cvmx_mio_fus_repair_res2_s cn66xx;
1509 struct cvmx_mio_fus_repair_res2_s cn68xx;
1510 struct cvmx_mio_fus_repair_res2_s cn68xxp1;
1067}; 1511};
1068 1512
1069union cvmx_mio_fus_spr_repair_res { 1513union cvmx_mio_fus_spr_repair_res {
@@ -1084,8 +1528,12 @@ union cvmx_mio_fus_spr_repair_res {
1084 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 1528 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
1085 struct cvmx_mio_fus_spr_repair_res_s cn58xx; 1529 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
1086 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 1530 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
1531 struct cvmx_mio_fus_spr_repair_res_s cn61xx;
1087 struct cvmx_mio_fus_spr_repair_res_s cn63xx; 1532 struct cvmx_mio_fus_spr_repair_res_s cn63xx;
1088 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1; 1533 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
1534 struct cvmx_mio_fus_spr_repair_res_s cn66xx;
1535 struct cvmx_mio_fus_spr_repair_res_s cn68xx;
1536 struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
1089}; 1537};
1090 1538
1091union cvmx_mio_fus_spr_repair_sum { 1539union cvmx_mio_fus_spr_repair_sum {
@@ -1104,8 +1552,22 @@ union cvmx_mio_fus_spr_repair_sum {
1104 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 1552 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
1105 struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 1553 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
1106 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 1554 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
1555 struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
1107 struct cvmx_mio_fus_spr_repair_sum_s cn63xx; 1556 struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
1108 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1; 1557 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
1558 struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
1559 struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
1560 struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
1561};
1562
1563union cvmx_mio_fus_tgg {
1564 uint64_t u64;
1565 struct cvmx_mio_fus_tgg_s {
1566 uint64_t val:1;
1567 uint64_t dat:63;
1568 } s;
1569 struct cvmx_mio_fus_tgg_s cn61xx;
1570 struct cvmx_mio_fus_tgg_s cn66xx;
1109}; 1571};
1110 1572
1111union cvmx_mio_fus_unlock { 1573union cvmx_mio_fus_unlock {
@@ -1141,11 +1603,15 @@ union cvmx_mio_fus_wadr {
1141 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 1603 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
1142 struct cvmx_mio_fus_wadr_cn50xx cn58xx; 1604 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
1143 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 1605 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
1144 struct cvmx_mio_fus_wadr_cn63xx { 1606 struct cvmx_mio_fus_wadr_cn61xx {
1145 uint64_t reserved_4_63:60; 1607 uint64_t reserved_4_63:60;
1146 uint64_t addr:4; 1608 uint64_t addr:4;
1147 } cn63xx; 1609 } cn61xx;
1148 struct cvmx_mio_fus_wadr_cn63xx cn63xxp1; 1610 struct cvmx_mio_fus_wadr_cn61xx cn63xx;
1611 struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
1612 struct cvmx_mio_fus_wadr_cn61xx cn66xx;
1613 struct cvmx_mio_fus_wadr_cn61xx cn68xx;
1614 struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
1149}; 1615};
1150 1616
1151union cvmx_mio_gpio_comp { 1617union cvmx_mio_gpio_comp {
@@ -1155,8 +1621,12 @@ union cvmx_mio_gpio_comp {
1155 uint64_t pctl:6; 1621 uint64_t pctl:6;
1156 uint64_t nctl:6; 1622 uint64_t nctl:6;
1157 } s; 1623 } s;
1624 struct cvmx_mio_gpio_comp_s cn61xx;
1158 struct cvmx_mio_gpio_comp_s cn63xx; 1625 struct cvmx_mio_gpio_comp_s cn63xx;
1159 struct cvmx_mio_gpio_comp_s cn63xxp1; 1626 struct cvmx_mio_gpio_comp_s cn63xxp1;
1627 struct cvmx_mio_gpio_comp_s cn66xx;
1628 struct cvmx_mio_gpio_comp_s cn68xx;
1629 struct cvmx_mio_gpio_comp_s cn68xxp1;
1160}; 1630};
1161 1631
1162union cvmx_mio_ndf_dma_cfg { 1632union cvmx_mio_ndf_dma_cfg {
@@ -1174,8 +1644,12 @@ union cvmx_mio_ndf_dma_cfg {
1174 uint64_t adr:36; 1644 uint64_t adr:36;
1175 } s; 1645 } s;
1176 struct cvmx_mio_ndf_dma_cfg_s cn52xx; 1646 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
1647 struct cvmx_mio_ndf_dma_cfg_s cn61xx;
1177 struct cvmx_mio_ndf_dma_cfg_s cn63xx; 1648 struct cvmx_mio_ndf_dma_cfg_s cn63xx;
1178 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1; 1649 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
1650 struct cvmx_mio_ndf_dma_cfg_s cn66xx;
1651 struct cvmx_mio_ndf_dma_cfg_s cn68xx;
1652 struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
1179}; 1653};
1180 1654
1181union cvmx_mio_ndf_dma_int { 1655union cvmx_mio_ndf_dma_int {
@@ -1185,8 +1659,12 @@ union cvmx_mio_ndf_dma_int {
1185 uint64_t done:1; 1659 uint64_t done:1;
1186 } s; 1660 } s;
1187 struct cvmx_mio_ndf_dma_int_s cn52xx; 1661 struct cvmx_mio_ndf_dma_int_s cn52xx;
1662 struct cvmx_mio_ndf_dma_int_s cn61xx;
1188 struct cvmx_mio_ndf_dma_int_s cn63xx; 1663 struct cvmx_mio_ndf_dma_int_s cn63xx;
1189 struct cvmx_mio_ndf_dma_int_s cn63xxp1; 1664 struct cvmx_mio_ndf_dma_int_s cn63xxp1;
1665 struct cvmx_mio_ndf_dma_int_s cn66xx;
1666 struct cvmx_mio_ndf_dma_int_s cn68xx;
1667 struct cvmx_mio_ndf_dma_int_s cn68xxp1;
1190}; 1668};
1191 1669
1192union cvmx_mio_ndf_dma_int_en { 1670union cvmx_mio_ndf_dma_int_en {
@@ -1196,8 +1674,12 @@ union cvmx_mio_ndf_dma_int_en {
1196 uint64_t done:1; 1674 uint64_t done:1;
1197 } s; 1675 } s;
1198 struct cvmx_mio_ndf_dma_int_en_s cn52xx; 1676 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
1677 struct cvmx_mio_ndf_dma_int_en_s cn61xx;
1199 struct cvmx_mio_ndf_dma_int_en_s cn63xx; 1678 struct cvmx_mio_ndf_dma_int_en_s cn63xx;
1200 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1; 1679 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
1680 struct cvmx_mio_ndf_dma_int_en_s cn66xx;
1681 struct cvmx_mio_ndf_dma_int_en_s cn68xx;
1682 struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
1201}; 1683};
1202 1684
1203union cvmx_mio_pll_ctl { 1685union cvmx_mio_pll_ctl {
@@ -1220,10 +1702,63 @@ union cvmx_mio_pll_setting {
1220 struct cvmx_mio_pll_setting_s cn31xx; 1702 struct cvmx_mio_pll_setting_s cn31xx;
1221}; 1703};
1222 1704
1705union cvmx_mio_ptp_ckout_hi_incr {
1706 uint64_t u64;
1707 struct cvmx_mio_ptp_ckout_hi_incr_s {
1708 uint64_t nanosec:32;
1709 uint64_t frnanosec:32;
1710 } s;
1711 struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
1712 struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
1713 struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
1714};
1715
1716union cvmx_mio_ptp_ckout_lo_incr {
1717 uint64_t u64;
1718 struct cvmx_mio_ptp_ckout_lo_incr_s {
1719 uint64_t nanosec:32;
1720 uint64_t frnanosec:32;
1721 } s;
1722 struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
1723 struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
1724 struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
1725};
1726
1727union cvmx_mio_ptp_ckout_thresh_hi {
1728 uint64_t u64;
1729 struct cvmx_mio_ptp_ckout_thresh_hi_s {
1730 uint64_t nanosec:64;
1731 } s;
1732 struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
1733 struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
1734 struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
1735};
1736
1737union cvmx_mio_ptp_ckout_thresh_lo {
1738 uint64_t u64;
1739 struct cvmx_mio_ptp_ckout_thresh_lo_s {
1740 uint64_t reserved_32_63:32;
1741 uint64_t frnanosec:32;
1742 } s;
1743 struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
1744 struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
1745 struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
1746};
1747
1223union cvmx_mio_ptp_clock_cfg { 1748union cvmx_mio_ptp_clock_cfg {
1224 uint64_t u64; 1749 uint64_t u64;
1225 struct cvmx_mio_ptp_clock_cfg_s { 1750 struct cvmx_mio_ptp_clock_cfg_s {
1226 uint64_t reserved_24_63:40; 1751 uint64_t reserved_42_63:22;
1752 uint64_t pps:1;
1753 uint64_t ckout:1;
1754 uint64_t ext_clk_edge:2;
1755 uint64_t ckout_out4:1;
1756 uint64_t pps_out:5;
1757 uint64_t pps_inv:1;
1758 uint64_t pps_en:1;
1759 uint64_t ckout_out:4;
1760 uint64_t ckout_inv:1;
1761 uint64_t ckout_en:1;
1227 uint64_t evcnt_in:6; 1762 uint64_t evcnt_in:6;
1228 uint64_t evcnt_edge:1; 1763 uint64_t evcnt_edge:1;
1229 uint64_t evcnt_en:1; 1764 uint64_t evcnt_en:1;
@@ -1234,8 +1769,42 @@ union cvmx_mio_ptp_clock_cfg {
1234 uint64_t ext_clk_en:1; 1769 uint64_t ext_clk_en:1;
1235 uint64_t ptp_en:1; 1770 uint64_t ptp_en:1;
1236 } s; 1771 } s;
1237 struct cvmx_mio_ptp_clock_cfg_s cn63xx; 1772 struct cvmx_mio_ptp_clock_cfg_s cn61xx;
1238 struct cvmx_mio_ptp_clock_cfg_s cn63xxp1; 1773 struct cvmx_mio_ptp_clock_cfg_cn63xx {
1774 uint64_t reserved_24_63:40;
1775 uint64_t evcnt_in:6;
1776 uint64_t evcnt_edge:1;
1777 uint64_t evcnt_en:1;
1778 uint64_t tstmp_in:6;
1779 uint64_t tstmp_edge:1;
1780 uint64_t tstmp_en:1;
1781 uint64_t ext_clk_in:6;
1782 uint64_t ext_clk_en:1;
1783 uint64_t ptp_en:1;
1784 } cn63xx;
1785 struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
1786 struct cvmx_mio_ptp_clock_cfg_cn66xx {
1787 uint64_t reserved_40_63:24;
1788 uint64_t ext_clk_edge:2;
1789 uint64_t ckout_out4:1;
1790 uint64_t pps_out:5;
1791 uint64_t pps_inv:1;
1792 uint64_t pps_en:1;
1793 uint64_t ckout_out:4;
1794 uint64_t ckout_inv:1;
1795 uint64_t ckout_en:1;
1796 uint64_t evcnt_in:6;
1797 uint64_t evcnt_edge:1;
1798 uint64_t evcnt_en:1;
1799 uint64_t tstmp_in:6;
1800 uint64_t tstmp_edge:1;
1801 uint64_t tstmp_en:1;
1802 uint64_t ext_clk_in:6;
1803 uint64_t ext_clk_en:1;
1804 uint64_t ptp_en:1;
1805 } cn66xx;
1806 struct cvmx_mio_ptp_clock_cfg_s cn68xx;
1807 struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
1239}; 1808};
1240 1809
1241union cvmx_mio_ptp_clock_comp { 1810union cvmx_mio_ptp_clock_comp {
@@ -1244,8 +1813,12 @@ union cvmx_mio_ptp_clock_comp {
1244 uint64_t nanosec:32; 1813 uint64_t nanosec:32;
1245 uint64_t frnanosec:32; 1814 uint64_t frnanosec:32;
1246 } s; 1815 } s;
1816 struct cvmx_mio_ptp_clock_comp_s cn61xx;
1247 struct cvmx_mio_ptp_clock_comp_s cn63xx; 1817 struct cvmx_mio_ptp_clock_comp_s cn63xx;
1248 struct cvmx_mio_ptp_clock_comp_s cn63xxp1; 1818 struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
1819 struct cvmx_mio_ptp_clock_comp_s cn66xx;
1820 struct cvmx_mio_ptp_clock_comp_s cn68xx;
1821 struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
1249}; 1822};
1250 1823
1251union cvmx_mio_ptp_clock_hi { 1824union cvmx_mio_ptp_clock_hi {
@@ -1253,8 +1826,12 @@ union cvmx_mio_ptp_clock_hi {
1253 struct cvmx_mio_ptp_clock_hi_s { 1826 struct cvmx_mio_ptp_clock_hi_s {
1254 uint64_t nanosec:64; 1827 uint64_t nanosec:64;
1255 } s; 1828 } s;
1829 struct cvmx_mio_ptp_clock_hi_s cn61xx;
1256 struct cvmx_mio_ptp_clock_hi_s cn63xx; 1830 struct cvmx_mio_ptp_clock_hi_s cn63xx;
1257 struct cvmx_mio_ptp_clock_hi_s cn63xxp1; 1831 struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
1832 struct cvmx_mio_ptp_clock_hi_s cn66xx;
1833 struct cvmx_mio_ptp_clock_hi_s cn68xx;
1834 struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
1258}; 1835};
1259 1836
1260union cvmx_mio_ptp_clock_lo { 1837union cvmx_mio_ptp_clock_lo {
@@ -1263,8 +1840,12 @@ union cvmx_mio_ptp_clock_lo {
1263 uint64_t reserved_32_63:32; 1840 uint64_t reserved_32_63:32;
1264 uint64_t frnanosec:32; 1841 uint64_t frnanosec:32;
1265 } s; 1842 } s;
1843 struct cvmx_mio_ptp_clock_lo_s cn61xx;
1266 struct cvmx_mio_ptp_clock_lo_s cn63xx; 1844 struct cvmx_mio_ptp_clock_lo_s cn63xx;
1267 struct cvmx_mio_ptp_clock_lo_s cn63xxp1; 1845 struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
1846 struct cvmx_mio_ptp_clock_lo_s cn66xx;
1847 struct cvmx_mio_ptp_clock_lo_s cn68xx;
1848 struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
1268}; 1849};
1269 1850
1270union cvmx_mio_ptp_evt_cnt { 1851union cvmx_mio_ptp_evt_cnt {
@@ -1272,8 +1853,55 @@ union cvmx_mio_ptp_evt_cnt {
1272 struct cvmx_mio_ptp_evt_cnt_s { 1853 struct cvmx_mio_ptp_evt_cnt_s {
1273 uint64_t cntr:64; 1854 uint64_t cntr:64;
1274 } s; 1855 } s;
1856 struct cvmx_mio_ptp_evt_cnt_s cn61xx;
1275 struct cvmx_mio_ptp_evt_cnt_s cn63xx; 1857 struct cvmx_mio_ptp_evt_cnt_s cn63xx;
1276 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1; 1858 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
1859 struct cvmx_mio_ptp_evt_cnt_s cn66xx;
1860 struct cvmx_mio_ptp_evt_cnt_s cn68xx;
1861 struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
1862};
1863
1864union cvmx_mio_ptp_pps_hi_incr {
1865 uint64_t u64;
1866 struct cvmx_mio_ptp_pps_hi_incr_s {
1867 uint64_t nanosec:32;
1868 uint64_t frnanosec:32;
1869 } s;
1870 struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
1871 struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
1872 struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
1873};
1874
1875union cvmx_mio_ptp_pps_lo_incr {
1876 uint64_t u64;
1877 struct cvmx_mio_ptp_pps_lo_incr_s {
1878 uint64_t nanosec:32;
1879 uint64_t frnanosec:32;
1880 } s;
1881 struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
1882 struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
1883 struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
1884};
1885
1886union cvmx_mio_ptp_pps_thresh_hi {
1887 uint64_t u64;
1888 struct cvmx_mio_ptp_pps_thresh_hi_s {
1889 uint64_t nanosec:64;
1890 } s;
1891 struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
1892 struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
1893 struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
1894};
1895
1896union cvmx_mio_ptp_pps_thresh_lo {
1897 uint64_t u64;
1898 struct cvmx_mio_ptp_pps_thresh_lo_s {
1899 uint64_t reserved_32_63:32;
1900 uint64_t frnanosec:32;
1901 } s;
1902 struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
1903 struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
1904 struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
1277}; 1905};
1278 1906
1279union cvmx_mio_ptp_timestamp { 1907union cvmx_mio_ptp_timestamp {
@@ -1281,14 +1909,52 @@ union cvmx_mio_ptp_timestamp {
1281 struct cvmx_mio_ptp_timestamp_s { 1909 struct cvmx_mio_ptp_timestamp_s {
1282 uint64_t nanosec:64; 1910 uint64_t nanosec:64;
1283 } s; 1911 } s;
1912 struct cvmx_mio_ptp_timestamp_s cn61xx;
1284 struct cvmx_mio_ptp_timestamp_s cn63xx; 1913 struct cvmx_mio_ptp_timestamp_s cn63xx;
1285 struct cvmx_mio_ptp_timestamp_s cn63xxp1; 1914 struct cvmx_mio_ptp_timestamp_s cn63xxp1;
1915 struct cvmx_mio_ptp_timestamp_s cn66xx;
1916 struct cvmx_mio_ptp_timestamp_s cn68xx;
1917 struct cvmx_mio_ptp_timestamp_s cn68xxp1;
1918};
1919
1920union cvmx_mio_qlmx_cfg {
1921 uint64_t u64;
1922 struct cvmx_mio_qlmx_cfg_s {
1923 uint64_t reserved_12_63:52;
1924 uint64_t qlm_spd:4;
1925 uint64_t reserved_4_7:4;
1926 uint64_t qlm_cfg:4;
1927 } s;
1928 struct cvmx_mio_qlmx_cfg_cn61xx {
1929 uint64_t reserved_12_63:52;
1930 uint64_t qlm_spd:4;
1931 uint64_t reserved_2_7:6;
1932 uint64_t qlm_cfg:2;
1933 } cn61xx;
1934 struct cvmx_mio_qlmx_cfg_s cn66xx;
1935 struct cvmx_mio_qlmx_cfg_cn68xx {
1936 uint64_t reserved_12_63:52;
1937 uint64_t qlm_spd:4;
1938 uint64_t reserved_3_7:5;
1939 uint64_t qlm_cfg:3;
1940 } cn68xx;
1941 struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
1286}; 1942};
1287 1943
1288union cvmx_mio_rst_boot { 1944union cvmx_mio_rst_boot {
1289 uint64_t u64; 1945 uint64_t u64;
1290 struct cvmx_mio_rst_boot_s { 1946 struct cvmx_mio_rst_boot_s {
1291 uint64_t reserved_36_63:28; 1947 uint64_t chipkill:1;
1948 uint64_t jtcsrdis:1;
1949 uint64_t ejtagdis:1;
1950 uint64_t romen:1;
1951 uint64_t ckill_ppdis:1;
1952 uint64_t jt_tstmode:1;
1953 uint64_t reserved_50_57:8;
1954 uint64_t lboot_ext:2;
1955 uint64_t reserved_44_47:4;
1956 uint64_t qlm4_spd:4;
1957 uint64_t qlm3_spd:4;
1292 uint64_t c_mul:6; 1958 uint64_t c_mul:6;
1293 uint64_t pnr_mul:6; 1959 uint64_t pnr_mul:6;
1294 uint64_t qlm2_spd:4; 1960 uint64_t qlm2_spd:4;
@@ -1298,32 +1964,168 @@ union cvmx_mio_rst_boot {
1298 uint64_t rboot:1; 1964 uint64_t rboot:1;
1299 uint64_t rboot_pin:1; 1965 uint64_t rboot_pin:1;
1300 } s; 1966 } s;
1301 struct cvmx_mio_rst_boot_s cn63xx; 1967 struct cvmx_mio_rst_boot_cn61xx {
1302 struct cvmx_mio_rst_boot_s cn63xxp1; 1968 uint64_t chipkill:1;
1969 uint64_t jtcsrdis:1;
1970 uint64_t ejtagdis:1;
1971 uint64_t romen:1;
1972 uint64_t ckill_ppdis:1;
1973 uint64_t jt_tstmode:1;
1974 uint64_t reserved_50_57:8;
1975 uint64_t lboot_ext:2;
1976 uint64_t reserved_36_47:12;
1977 uint64_t c_mul:6;
1978 uint64_t pnr_mul:6;
1979 uint64_t qlm2_spd:4;
1980 uint64_t qlm1_spd:4;
1981 uint64_t qlm0_spd:4;
1982 uint64_t lboot:10;
1983 uint64_t rboot:1;
1984 uint64_t rboot_pin:1;
1985 } cn61xx;
1986 struct cvmx_mio_rst_boot_cn63xx {
1987 uint64_t reserved_36_63:28;
1988 uint64_t c_mul:6;
1989 uint64_t pnr_mul:6;
1990 uint64_t qlm2_spd:4;
1991 uint64_t qlm1_spd:4;
1992 uint64_t qlm0_spd:4;
1993 uint64_t lboot:10;
1994 uint64_t rboot:1;
1995 uint64_t rboot_pin:1;
1996 } cn63xx;
1997 struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
1998 struct cvmx_mio_rst_boot_cn66xx {
1999 uint64_t chipkill:1;
2000 uint64_t jtcsrdis:1;
2001 uint64_t ejtagdis:1;
2002 uint64_t romen:1;
2003 uint64_t ckill_ppdis:1;
2004 uint64_t reserved_50_58:9;
2005 uint64_t lboot_ext:2;
2006 uint64_t reserved_36_47:12;
2007 uint64_t c_mul:6;
2008 uint64_t pnr_mul:6;
2009 uint64_t qlm2_spd:4;
2010 uint64_t qlm1_spd:4;
2011 uint64_t qlm0_spd:4;
2012 uint64_t lboot:10;
2013 uint64_t rboot:1;
2014 uint64_t rboot_pin:1;
2015 } cn66xx;
2016 struct cvmx_mio_rst_boot_cn68xx {
2017 uint64_t reserved_59_63:5;
2018 uint64_t jt_tstmode:1;
2019 uint64_t reserved_44_57:14;
2020 uint64_t qlm4_spd:4;
2021 uint64_t qlm3_spd:4;
2022 uint64_t c_mul:6;
2023 uint64_t pnr_mul:6;
2024 uint64_t qlm2_spd:4;
2025 uint64_t qlm1_spd:4;
2026 uint64_t qlm0_spd:4;
2027 uint64_t lboot:10;
2028 uint64_t rboot:1;
2029 uint64_t rboot_pin:1;
2030 } cn68xx;
2031 struct cvmx_mio_rst_boot_cn68xxp1 {
2032 uint64_t reserved_44_63:20;
2033 uint64_t qlm4_spd:4;
2034 uint64_t qlm3_spd:4;
2035 uint64_t c_mul:6;
2036 uint64_t pnr_mul:6;
2037 uint64_t qlm2_spd:4;
2038 uint64_t qlm1_spd:4;
2039 uint64_t qlm0_spd:4;
2040 uint64_t lboot:10;
2041 uint64_t rboot:1;
2042 uint64_t rboot_pin:1;
2043 } cn68xxp1;
1303}; 2044};
1304 2045
1305union cvmx_mio_rst_cfg { 2046union cvmx_mio_rst_cfg {
1306 uint64_t u64; 2047 uint64_t u64;
1307 struct cvmx_mio_rst_cfg_s { 2048 struct cvmx_mio_rst_cfg_s {
2049 uint64_t reserved_3_63:61;
2050 uint64_t cntl_clr_bist:1;
2051 uint64_t warm_clr_bist:1;
2052 uint64_t soft_clr_bist:1;
2053 } s;
2054 struct cvmx_mio_rst_cfg_cn61xx {
1308 uint64_t bist_delay:58; 2055 uint64_t bist_delay:58;
1309 uint64_t reserved_3_5:3; 2056 uint64_t reserved_3_5:3;
1310 uint64_t cntl_clr_bist:1; 2057 uint64_t cntl_clr_bist:1;
1311 uint64_t warm_clr_bist:1; 2058 uint64_t warm_clr_bist:1;
1312 uint64_t soft_clr_bist:1; 2059 uint64_t soft_clr_bist:1;
1313 } s; 2060 } cn61xx;
1314 struct cvmx_mio_rst_cfg_s cn63xx; 2061 struct cvmx_mio_rst_cfg_cn61xx cn63xx;
1315 struct cvmx_mio_rst_cfg_cn63xxp1 { 2062 struct cvmx_mio_rst_cfg_cn63xxp1 {
1316 uint64_t bist_delay:58; 2063 uint64_t bist_delay:58;
1317 uint64_t reserved_2_5:4; 2064 uint64_t reserved_2_5:4;
1318 uint64_t warm_clr_bist:1; 2065 uint64_t warm_clr_bist:1;
1319 uint64_t soft_clr_bist:1; 2066 uint64_t soft_clr_bist:1;
1320 } cn63xxp1; 2067 } cn63xxp1;
2068 struct cvmx_mio_rst_cfg_cn61xx cn66xx;
2069 struct cvmx_mio_rst_cfg_cn68xx {
2070 uint64_t bist_delay:56;
2071 uint64_t reserved_3_7:5;
2072 uint64_t cntl_clr_bist:1;
2073 uint64_t warm_clr_bist:1;
2074 uint64_t soft_clr_bist:1;
2075 } cn68xx;
2076 struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
2077};
2078
2079union cvmx_mio_rst_ckill {
2080 uint64_t u64;
2081 struct cvmx_mio_rst_ckill_s {
2082 uint64_t reserved_47_63:17;
2083 uint64_t timer:47;
2084 } s;
2085 struct cvmx_mio_rst_ckill_s cn61xx;
2086 struct cvmx_mio_rst_ckill_s cn66xx;
2087};
2088
2089union cvmx_mio_rst_cntlx {
2090 uint64_t u64;
2091 struct cvmx_mio_rst_cntlx_s {
2092 uint64_t reserved_13_63:51;
2093 uint64_t in_rev_ln:1;
2094 uint64_t rev_lanes:1;
2095 uint64_t gen1_only:1;
2096 uint64_t prst_link:1;
2097 uint64_t rst_done:1;
2098 uint64_t rst_link:1;
2099 uint64_t host_mode:1;
2100 uint64_t prtmode:2;
2101 uint64_t rst_drv:1;
2102 uint64_t rst_rcv:1;
2103 uint64_t rst_chip:1;
2104 uint64_t rst_val:1;
2105 } s;
2106 struct cvmx_mio_rst_cntlx_s cn61xx;
2107 struct cvmx_mio_rst_cntlx_cn66xx {
2108 uint64_t reserved_10_63:54;
2109 uint64_t prst_link:1;
2110 uint64_t rst_done:1;
2111 uint64_t rst_link:1;
2112 uint64_t host_mode:1;
2113 uint64_t prtmode:2;
2114 uint64_t rst_drv:1;
2115 uint64_t rst_rcv:1;
2116 uint64_t rst_chip:1;
2117 uint64_t rst_val:1;
2118 } cn66xx;
2119 struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
1321}; 2120};
1322 2121
1323union cvmx_mio_rst_ctlx { 2122union cvmx_mio_rst_ctlx {
1324 uint64_t u64; 2123 uint64_t u64;
1325 struct cvmx_mio_rst_ctlx_s { 2124 struct cvmx_mio_rst_ctlx_s {
1326 uint64_t reserved_10_63:54; 2125 uint64_t reserved_13_63:51;
2126 uint64_t in_rev_ln:1;
2127 uint64_t rev_lanes:1;
2128 uint64_t gen1_only:1;
1327 uint64_t prst_link:1; 2129 uint64_t prst_link:1;
1328 uint64_t rst_done:1; 2130 uint64_t rst_done:1;
1329 uint64_t rst_link:1; 2131 uint64_t rst_link:1;
@@ -1334,7 +2136,19 @@ union cvmx_mio_rst_ctlx {
1334 uint64_t rst_chip:1; 2136 uint64_t rst_chip:1;
1335 uint64_t rst_val:1; 2137 uint64_t rst_val:1;
1336 } s; 2138 } s;
1337 struct cvmx_mio_rst_ctlx_s cn63xx; 2139 struct cvmx_mio_rst_ctlx_s cn61xx;
2140 struct cvmx_mio_rst_ctlx_cn63xx {
2141 uint64_t reserved_10_63:54;
2142 uint64_t prst_link:1;
2143 uint64_t rst_done:1;
2144 uint64_t rst_link:1;
2145 uint64_t host_mode:1;
2146 uint64_t prtmode:2;
2147 uint64_t rst_drv:1;
2148 uint64_t rst_rcv:1;
2149 uint64_t rst_chip:1;
2150 uint64_t rst_val:1;
2151 } cn63xx;
1338 struct cvmx_mio_rst_ctlx_cn63xxp1 { 2152 struct cvmx_mio_rst_ctlx_cn63xxp1 {
1339 uint64_t reserved_9_63:55; 2153 uint64_t reserved_9_63:55;
1340 uint64_t rst_done:1; 2154 uint64_t rst_done:1;
@@ -1346,17 +2160,24 @@ union cvmx_mio_rst_ctlx {
1346 uint64_t rst_chip:1; 2160 uint64_t rst_chip:1;
1347 uint64_t rst_val:1; 2161 uint64_t rst_val:1;
1348 } cn63xxp1; 2162 } cn63xxp1;
2163 struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
2164 struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
2165 struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
1349}; 2166};
1350 2167
1351union cvmx_mio_rst_delay { 2168union cvmx_mio_rst_delay {
1352 uint64_t u64; 2169 uint64_t u64;
1353 struct cvmx_mio_rst_delay_s { 2170 struct cvmx_mio_rst_delay_s {
1354 uint64_t reserved_32_63:32; 2171 uint64_t reserved_32_63:32;
1355 uint64_t soft_rst_dly:16;
1356 uint64_t warm_rst_dly:16; 2172 uint64_t warm_rst_dly:16;
2173 uint64_t soft_rst_dly:16;
1357 } s; 2174 } s;
2175 struct cvmx_mio_rst_delay_s cn61xx;
1358 struct cvmx_mio_rst_delay_s cn63xx; 2176 struct cvmx_mio_rst_delay_s cn63xx;
1359 struct cvmx_mio_rst_delay_s cn63xxp1; 2177 struct cvmx_mio_rst_delay_s cn63xxp1;
2178 struct cvmx_mio_rst_delay_s cn66xx;
2179 struct cvmx_mio_rst_delay_s cn68xx;
2180 struct cvmx_mio_rst_delay_s cn68xxp1;
1360}; 2181};
1361 2182
1362union cvmx_mio_rst_int { 2183union cvmx_mio_rst_int {
@@ -1365,12 +2186,25 @@ union cvmx_mio_rst_int {
1365 uint64_t reserved_10_63:54; 2186 uint64_t reserved_10_63:54;
1366 uint64_t perst1:1; 2187 uint64_t perst1:1;
1367 uint64_t perst0:1; 2188 uint64_t perst0:1;
1368 uint64_t reserved_2_7:6; 2189 uint64_t reserved_4_7:4;
2190 uint64_t rst_link3:1;
2191 uint64_t rst_link2:1;
1369 uint64_t rst_link1:1; 2192 uint64_t rst_link1:1;
1370 uint64_t rst_link0:1; 2193 uint64_t rst_link0:1;
1371 } s; 2194 } s;
1372 struct cvmx_mio_rst_int_s cn63xx; 2195 struct cvmx_mio_rst_int_cn61xx {
1373 struct cvmx_mio_rst_int_s cn63xxp1; 2196 uint64_t reserved_10_63:54;
2197 uint64_t perst1:1;
2198 uint64_t perst0:1;
2199 uint64_t reserved_2_7:6;
2200 uint64_t rst_link1:1;
2201 uint64_t rst_link0:1;
2202 } cn61xx;
2203 struct cvmx_mio_rst_int_cn61xx cn63xx;
2204 struct cvmx_mio_rst_int_cn61xx cn63xxp1;
2205 struct cvmx_mio_rst_int_s cn66xx;
2206 struct cvmx_mio_rst_int_cn61xx cn68xx;
2207 struct cvmx_mio_rst_int_cn61xx cn68xxp1;
1374}; 2208};
1375 2209
1376union cvmx_mio_rst_int_en { 2210union cvmx_mio_rst_int_en {
@@ -1379,12 +2213,25 @@ union cvmx_mio_rst_int_en {
1379 uint64_t reserved_10_63:54; 2213 uint64_t reserved_10_63:54;
1380 uint64_t perst1:1; 2214 uint64_t perst1:1;
1381 uint64_t perst0:1; 2215 uint64_t perst0:1;
1382 uint64_t reserved_2_7:6; 2216 uint64_t reserved_4_7:4;
2217 uint64_t rst_link3:1;
2218 uint64_t rst_link2:1;
1383 uint64_t rst_link1:1; 2219 uint64_t rst_link1:1;
1384 uint64_t rst_link0:1; 2220 uint64_t rst_link0:1;
1385 } s; 2221 } s;
1386 struct cvmx_mio_rst_int_en_s cn63xx; 2222 struct cvmx_mio_rst_int_en_cn61xx {
1387 struct cvmx_mio_rst_int_en_s cn63xxp1; 2223 uint64_t reserved_10_63:54;
2224 uint64_t perst1:1;
2225 uint64_t perst0:1;
2226 uint64_t reserved_2_7:6;
2227 uint64_t rst_link1:1;
2228 uint64_t rst_link0:1;
2229 } cn61xx;
2230 struct cvmx_mio_rst_int_en_cn61xx cn63xx;
2231 struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
2232 struct cvmx_mio_rst_int_en_s cn66xx;
2233 struct cvmx_mio_rst_int_en_cn61xx cn68xx;
2234 struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
1388}; 2235};
1389 2236
1390union cvmx_mio_twsx_int { 2237union cvmx_mio_twsx_int {
@@ -1424,8 +2271,12 @@ union cvmx_mio_twsx_int {
1424 struct cvmx_mio_twsx_int_s cn56xxp1; 2271 struct cvmx_mio_twsx_int_s cn56xxp1;
1425 struct cvmx_mio_twsx_int_s cn58xx; 2272 struct cvmx_mio_twsx_int_s cn58xx;
1426 struct cvmx_mio_twsx_int_s cn58xxp1; 2273 struct cvmx_mio_twsx_int_s cn58xxp1;
2274 struct cvmx_mio_twsx_int_s cn61xx;
1427 struct cvmx_mio_twsx_int_s cn63xx; 2275 struct cvmx_mio_twsx_int_s cn63xx;
1428 struct cvmx_mio_twsx_int_s cn63xxp1; 2276 struct cvmx_mio_twsx_int_s cn63xxp1;
2277 struct cvmx_mio_twsx_int_s cn66xx;
2278 struct cvmx_mio_twsx_int_s cn68xx;
2279 struct cvmx_mio_twsx_int_s cn68xxp1;
1429}; 2280};
1430 2281
1431union cvmx_mio_twsx_sw_twsi { 2282union cvmx_mio_twsx_sw_twsi {
@@ -1455,8 +2306,12 @@ union cvmx_mio_twsx_sw_twsi {
1455 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 2306 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
1456 struct cvmx_mio_twsx_sw_twsi_s cn58xx; 2307 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
1457 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 2308 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
2309 struct cvmx_mio_twsx_sw_twsi_s cn61xx;
1458 struct cvmx_mio_twsx_sw_twsi_s cn63xx; 2310 struct cvmx_mio_twsx_sw_twsi_s cn63xx;
1459 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1; 2311 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
2312 struct cvmx_mio_twsx_sw_twsi_s cn66xx;
2313 struct cvmx_mio_twsx_sw_twsi_s cn68xx;
2314 struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
1460}; 2315};
1461 2316
1462union cvmx_mio_twsx_sw_twsi_ext { 2317union cvmx_mio_twsx_sw_twsi_ext {
@@ -1477,8 +2332,12 @@ union cvmx_mio_twsx_sw_twsi_ext {
1477 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 2332 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
1478 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 2333 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
1479 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 2334 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
2335 struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
1480 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx; 2336 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
1481 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1; 2337 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
2338 struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
2339 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
2340 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
1482}; 2341};
1483 2342
1484union cvmx_mio_twsx_twsi_sw { 2343union cvmx_mio_twsx_twsi_sw {
@@ -1499,8 +2358,12 @@ union cvmx_mio_twsx_twsi_sw {
1499 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 2358 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
1500 struct cvmx_mio_twsx_twsi_sw_s cn58xx; 2359 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
1501 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 2360 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
2361 struct cvmx_mio_twsx_twsi_sw_s cn61xx;
1502 struct cvmx_mio_twsx_twsi_sw_s cn63xx; 2362 struct cvmx_mio_twsx_twsi_sw_s cn63xx;
1503 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1; 2363 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
2364 struct cvmx_mio_twsx_twsi_sw_s cn66xx;
2365 struct cvmx_mio_twsx_twsi_sw_s cn68xx;
2366 struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
1504}; 2367};
1505 2368
1506union cvmx_mio_uartx_dlh { 2369union cvmx_mio_uartx_dlh {
@@ -1520,8 +2383,12 @@ union cvmx_mio_uartx_dlh {
1520 struct cvmx_mio_uartx_dlh_s cn56xxp1; 2383 struct cvmx_mio_uartx_dlh_s cn56xxp1;
1521 struct cvmx_mio_uartx_dlh_s cn58xx; 2384 struct cvmx_mio_uartx_dlh_s cn58xx;
1522 struct cvmx_mio_uartx_dlh_s cn58xxp1; 2385 struct cvmx_mio_uartx_dlh_s cn58xxp1;
2386 struct cvmx_mio_uartx_dlh_s cn61xx;
1523 struct cvmx_mio_uartx_dlh_s cn63xx; 2387 struct cvmx_mio_uartx_dlh_s cn63xx;
1524 struct cvmx_mio_uartx_dlh_s cn63xxp1; 2388 struct cvmx_mio_uartx_dlh_s cn63xxp1;
2389 struct cvmx_mio_uartx_dlh_s cn66xx;
2390 struct cvmx_mio_uartx_dlh_s cn68xx;
2391 struct cvmx_mio_uartx_dlh_s cn68xxp1;
1525}; 2392};
1526 2393
1527union cvmx_mio_uartx_dll { 2394union cvmx_mio_uartx_dll {
@@ -1541,8 +2408,12 @@ union cvmx_mio_uartx_dll {
1541 struct cvmx_mio_uartx_dll_s cn56xxp1; 2408 struct cvmx_mio_uartx_dll_s cn56xxp1;
1542 struct cvmx_mio_uartx_dll_s cn58xx; 2409 struct cvmx_mio_uartx_dll_s cn58xx;
1543 struct cvmx_mio_uartx_dll_s cn58xxp1; 2410 struct cvmx_mio_uartx_dll_s cn58xxp1;
2411 struct cvmx_mio_uartx_dll_s cn61xx;
1544 struct cvmx_mio_uartx_dll_s cn63xx; 2412 struct cvmx_mio_uartx_dll_s cn63xx;
1545 struct cvmx_mio_uartx_dll_s cn63xxp1; 2413 struct cvmx_mio_uartx_dll_s cn63xxp1;
2414 struct cvmx_mio_uartx_dll_s cn66xx;
2415 struct cvmx_mio_uartx_dll_s cn68xx;
2416 struct cvmx_mio_uartx_dll_s cn68xxp1;
1546}; 2417};
1547 2418
1548union cvmx_mio_uartx_far { 2419union cvmx_mio_uartx_far {
@@ -1562,8 +2433,12 @@ union cvmx_mio_uartx_far {
1562 struct cvmx_mio_uartx_far_s cn56xxp1; 2433 struct cvmx_mio_uartx_far_s cn56xxp1;
1563 struct cvmx_mio_uartx_far_s cn58xx; 2434 struct cvmx_mio_uartx_far_s cn58xx;
1564 struct cvmx_mio_uartx_far_s cn58xxp1; 2435 struct cvmx_mio_uartx_far_s cn58xxp1;
2436 struct cvmx_mio_uartx_far_s cn61xx;
1565 struct cvmx_mio_uartx_far_s cn63xx; 2437 struct cvmx_mio_uartx_far_s cn63xx;
1566 struct cvmx_mio_uartx_far_s cn63xxp1; 2438 struct cvmx_mio_uartx_far_s cn63xxp1;
2439 struct cvmx_mio_uartx_far_s cn66xx;
2440 struct cvmx_mio_uartx_far_s cn68xx;
2441 struct cvmx_mio_uartx_far_s cn68xxp1;
1567}; 2442};
1568 2443
1569union cvmx_mio_uartx_fcr { 2444union cvmx_mio_uartx_fcr {
@@ -1588,8 +2463,12 @@ union cvmx_mio_uartx_fcr {
1588 struct cvmx_mio_uartx_fcr_s cn56xxp1; 2463 struct cvmx_mio_uartx_fcr_s cn56xxp1;
1589 struct cvmx_mio_uartx_fcr_s cn58xx; 2464 struct cvmx_mio_uartx_fcr_s cn58xx;
1590 struct cvmx_mio_uartx_fcr_s cn58xxp1; 2465 struct cvmx_mio_uartx_fcr_s cn58xxp1;
2466 struct cvmx_mio_uartx_fcr_s cn61xx;
1591 struct cvmx_mio_uartx_fcr_s cn63xx; 2467 struct cvmx_mio_uartx_fcr_s cn63xx;
1592 struct cvmx_mio_uartx_fcr_s cn63xxp1; 2468 struct cvmx_mio_uartx_fcr_s cn63xxp1;
2469 struct cvmx_mio_uartx_fcr_s cn66xx;
2470 struct cvmx_mio_uartx_fcr_s cn68xx;
2471 struct cvmx_mio_uartx_fcr_s cn68xxp1;
1593}; 2472};
1594 2473
1595union cvmx_mio_uartx_htx { 2474union cvmx_mio_uartx_htx {
@@ -1609,8 +2488,12 @@ union cvmx_mio_uartx_htx {
1609 struct cvmx_mio_uartx_htx_s cn56xxp1; 2488 struct cvmx_mio_uartx_htx_s cn56xxp1;
1610 struct cvmx_mio_uartx_htx_s cn58xx; 2489 struct cvmx_mio_uartx_htx_s cn58xx;
1611 struct cvmx_mio_uartx_htx_s cn58xxp1; 2490 struct cvmx_mio_uartx_htx_s cn58xxp1;
2491 struct cvmx_mio_uartx_htx_s cn61xx;
1612 struct cvmx_mio_uartx_htx_s cn63xx; 2492 struct cvmx_mio_uartx_htx_s cn63xx;
1613 struct cvmx_mio_uartx_htx_s cn63xxp1; 2493 struct cvmx_mio_uartx_htx_s cn63xxp1;
2494 struct cvmx_mio_uartx_htx_s cn66xx;
2495 struct cvmx_mio_uartx_htx_s cn68xx;
2496 struct cvmx_mio_uartx_htx_s cn68xxp1;
1614}; 2497};
1615 2498
1616union cvmx_mio_uartx_ier { 2499union cvmx_mio_uartx_ier {
@@ -1635,8 +2518,12 @@ union cvmx_mio_uartx_ier {
1635 struct cvmx_mio_uartx_ier_s cn56xxp1; 2518 struct cvmx_mio_uartx_ier_s cn56xxp1;
1636 struct cvmx_mio_uartx_ier_s cn58xx; 2519 struct cvmx_mio_uartx_ier_s cn58xx;
1637 struct cvmx_mio_uartx_ier_s cn58xxp1; 2520 struct cvmx_mio_uartx_ier_s cn58xxp1;
2521 struct cvmx_mio_uartx_ier_s cn61xx;
1638 struct cvmx_mio_uartx_ier_s cn63xx; 2522 struct cvmx_mio_uartx_ier_s cn63xx;
1639 struct cvmx_mio_uartx_ier_s cn63xxp1; 2523 struct cvmx_mio_uartx_ier_s cn63xxp1;
2524 struct cvmx_mio_uartx_ier_s cn66xx;
2525 struct cvmx_mio_uartx_ier_s cn68xx;
2526 struct cvmx_mio_uartx_ier_s cn68xxp1;
1640}; 2527};
1641 2528
1642union cvmx_mio_uartx_iir { 2529union cvmx_mio_uartx_iir {
@@ -1658,8 +2545,12 @@ union cvmx_mio_uartx_iir {
1658 struct cvmx_mio_uartx_iir_s cn56xxp1; 2545 struct cvmx_mio_uartx_iir_s cn56xxp1;
1659 struct cvmx_mio_uartx_iir_s cn58xx; 2546 struct cvmx_mio_uartx_iir_s cn58xx;
1660 struct cvmx_mio_uartx_iir_s cn58xxp1; 2547 struct cvmx_mio_uartx_iir_s cn58xxp1;
2548 struct cvmx_mio_uartx_iir_s cn61xx;
1661 struct cvmx_mio_uartx_iir_s cn63xx; 2549 struct cvmx_mio_uartx_iir_s cn63xx;
1662 struct cvmx_mio_uartx_iir_s cn63xxp1; 2550 struct cvmx_mio_uartx_iir_s cn63xxp1;
2551 struct cvmx_mio_uartx_iir_s cn66xx;
2552 struct cvmx_mio_uartx_iir_s cn68xx;
2553 struct cvmx_mio_uartx_iir_s cn68xxp1;
1663}; 2554};
1664 2555
1665union cvmx_mio_uartx_lcr { 2556union cvmx_mio_uartx_lcr {
@@ -1685,8 +2576,12 @@ union cvmx_mio_uartx_lcr {
1685 struct cvmx_mio_uartx_lcr_s cn56xxp1; 2576 struct cvmx_mio_uartx_lcr_s cn56xxp1;
1686 struct cvmx_mio_uartx_lcr_s cn58xx; 2577 struct cvmx_mio_uartx_lcr_s cn58xx;
1687 struct cvmx_mio_uartx_lcr_s cn58xxp1; 2578 struct cvmx_mio_uartx_lcr_s cn58xxp1;
2579 struct cvmx_mio_uartx_lcr_s cn61xx;
1688 struct cvmx_mio_uartx_lcr_s cn63xx; 2580 struct cvmx_mio_uartx_lcr_s cn63xx;
1689 struct cvmx_mio_uartx_lcr_s cn63xxp1; 2581 struct cvmx_mio_uartx_lcr_s cn63xxp1;
2582 struct cvmx_mio_uartx_lcr_s cn66xx;
2583 struct cvmx_mio_uartx_lcr_s cn68xx;
2584 struct cvmx_mio_uartx_lcr_s cn68xxp1;
1690}; 2585};
1691 2586
1692union cvmx_mio_uartx_lsr { 2587union cvmx_mio_uartx_lsr {
@@ -1713,8 +2608,12 @@ union cvmx_mio_uartx_lsr {
1713 struct cvmx_mio_uartx_lsr_s cn56xxp1; 2608 struct cvmx_mio_uartx_lsr_s cn56xxp1;
1714 struct cvmx_mio_uartx_lsr_s cn58xx; 2609 struct cvmx_mio_uartx_lsr_s cn58xx;
1715 struct cvmx_mio_uartx_lsr_s cn58xxp1; 2610 struct cvmx_mio_uartx_lsr_s cn58xxp1;
2611 struct cvmx_mio_uartx_lsr_s cn61xx;
1716 struct cvmx_mio_uartx_lsr_s cn63xx; 2612 struct cvmx_mio_uartx_lsr_s cn63xx;
1717 struct cvmx_mio_uartx_lsr_s cn63xxp1; 2613 struct cvmx_mio_uartx_lsr_s cn63xxp1;
2614 struct cvmx_mio_uartx_lsr_s cn66xx;
2615 struct cvmx_mio_uartx_lsr_s cn68xx;
2616 struct cvmx_mio_uartx_lsr_s cn68xxp1;
1718}; 2617};
1719 2618
1720union cvmx_mio_uartx_mcr { 2619union cvmx_mio_uartx_mcr {
@@ -1739,8 +2638,12 @@ union cvmx_mio_uartx_mcr {
1739 struct cvmx_mio_uartx_mcr_s cn56xxp1; 2638 struct cvmx_mio_uartx_mcr_s cn56xxp1;
1740 struct cvmx_mio_uartx_mcr_s cn58xx; 2639 struct cvmx_mio_uartx_mcr_s cn58xx;
1741 struct cvmx_mio_uartx_mcr_s cn58xxp1; 2640 struct cvmx_mio_uartx_mcr_s cn58xxp1;
2641 struct cvmx_mio_uartx_mcr_s cn61xx;
1742 struct cvmx_mio_uartx_mcr_s cn63xx; 2642 struct cvmx_mio_uartx_mcr_s cn63xx;
1743 struct cvmx_mio_uartx_mcr_s cn63xxp1; 2643 struct cvmx_mio_uartx_mcr_s cn63xxp1;
2644 struct cvmx_mio_uartx_mcr_s cn66xx;
2645 struct cvmx_mio_uartx_mcr_s cn68xx;
2646 struct cvmx_mio_uartx_mcr_s cn68xxp1;
1744}; 2647};
1745 2648
1746union cvmx_mio_uartx_msr { 2649union cvmx_mio_uartx_msr {
@@ -1767,8 +2670,12 @@ union cvmx_mio_uartx_msr {
1767 struct cvmx_mio_uartx_msr_s cn56xxp1; 2670 struct cvmx_mio_uartx_msr_s cn56xxp1;
1768 struct cvmx_mio_uartx_msr_s cn58xx; 2671 struct cvmx_mio_uartx_msr_s cn58xx;
1769 struct cvmx_mio_uartx_msr_s cn58xxp1; 2672 struct cvmx_mio_uartx_msr_s cn58xxp1;
2673 struct cvmx_mio_uartx_msr_s cn61xx;
1770 struct cvmx_mio_uartx_msr_s cn63xx; 2674 struct cvmx_mio_uartx_msr_s cn63xx;
1771 struct cvmx_mio_uartx_msr_s cn63xxp1; 2675 struct cvmx_mio_uartx_msr_s cn63xxp1;
2676 struct cvmx_mio_uartx_msr_s cn66xx;
2677 struct cvmx_mio_uartx_msr_s cn68xx;
2678 struct cvmx_mio_uartx_msr_s cn68xxp1;
1772}; 2679};
1773 2680
1774union cvmx_mio_uartx_rbr { 2681union cvmx_mio_uartx_rbr {
@@ -1788,8 +2695,12 @@ union cvmx_mio_uartx_rbr {
1788 struct cvmx_mio_uartx_rbr_s cn56xxp1; 2695 struct cvmx_mio_uartx_rbr_s cn56xxp1;
1789 struct cvmx_mio_uartx_rbr_s cn58xx; 2696 struct cvmx_mio_uartx_rbr_s cn58xx;
1790 struct cvmx_mio_uartx_rbr_s cn58xxp1; 2697 struct cvmx_mio_uartx_rbr_s cn58xxp1;
2698 struct cvmx_mio_uartx_rbr_s cn61xx;
1791 struct cvmx_mio_uartx_rbr_s cn63xx; 2699 struct cvmx_mio_uartx_rbr_s cn63xx;
1792 struct cvmx_mio_uartx_rbr_s cn63xxp1; 2700 struct cvmx_mio_uartx_rbr_s cn63xxp1;
2701 struct cvmx_mio_uartx_rbr_s cn66xx;
2702 struct cvmx_mio_uartx_rbr_s cn68xx;
2703 struct cvmx_mio_uartx_rbr_s cn68xxp1;
1793}; 2704};
1794 2705
1795union cvmx_mio_uartx_rfl { 2706union cvmx_mio_uartx_rfl {
@@ -1809,8 +2720,12 @@ union cvmx_mio_uartx_rfl {
1809 struct cvmx_mio_uartx_rfl_s cn56xxp1; 2720 struct cvmx_mio_uartx_rfl_s cn56xxp1;
1810 struct cvmx_mio_uartx_rfl_s cn58xx; 2721 struct cvmx_mio_uartx_rfl_s cn58xx;
1811 struct cvmx_mio_uartx_rfl_s cn58xxp1; 2722 struct cvmx_mio_uartx_rfl_s cn58xxp1;
2723 struct cvmx_mio_uartx_rfl_s cn61xx;
1812 struct cvmx_mio_uartx_rfl_s cn63xx; 2724 struct cvmx_mio_uartx_rfl_s cn63xx;
1813 struct cvmx_mio_uartx_rfl_s cn63xxp1; 2725 struct cvmx_mio_uartx_rfl_s cn63xxp1;
2726 struct cvmx_mio_uartx_rfl_s cn66xx;
2727 struct cvmx_mio_uartx_rfl_s cn68xx;
2728 struct cvmx_mio_uartx_rfl_s cn68xxp1;
1814}; 2729};
1815 2730
1816union cvmx_mio_uartx_rfw { 2731union cvmx_mio_uartx_rfw {
@@ -1832,8 +2747,12 @@ union cvmx_mio_uartx_rfw {
1832 struct cvmx_mio_uartx_rfw_s cn56xxp1; 2747 struct cvmx_mio_uartx_rfw_s cn56xxp1;
1833 struct cvmx_mio_uartx_rfw_s cn58xx; 2748 struct cvmx_mio_uartx_rfw_s cn58xx;
1834 struct cvmx_mio_uartx_rfw_s cn58xxp1; 2749 struct cvmx_mio_uartx_rfw_s cn58xxp1;
2750 struct cvmx_mio_uartx_rfw_s cn61xx;
1835 struct cvmx_mio_uartx_rfw_s cn63xx; 2751 struct cvmx_mio_uartx_rfw_s cn63xx;
1836 struct cvmx_mio_uartx_rfw_s cn63xxp1; 2752 struct cvmx_mio_uartx_rfw_s cn63xxp1;
2753 struct cvmx_mio_uartx_rfw_s cn66xx;
2754 struct cvmx_mio_uartx_rfw_s cn68xx;
2755 struct cvmx_mio_uartx_rfw_s cn68xxp1;
1837}; 2756};
1838 2757
1839union cvmx_mio_uartx_sbcr { 2758union cvmx_mio_uartx_sbcr {
@@ -1853,8 +2772,12 @@ union cvmx_mio_uartx_sbcr {
1853 struct cvmx_mio_uartx_sbcr_s cn56xxp1; 2772 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
1854 struct cvmx_mio_uartx_sbcr_s cn58xx; 2773 struct cvmx_mio_uartx_sbcr_s cn58xx;
1855 struct cvmx_mio_uartx_sbcr_s cn58xxp1; 2774 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
2775 struct cvmx_mio_uartx_sbcr_s cn61xx;
1856 struct cvmx_mio_uartx_sbcr_s cn63xx; 2776 struct cvmx_mio_uartx_sbcr_s cn63xx;
1857 struct cvmx_mio_uartx_sbcr_s cn63xxp1; 2777 struct cvmx_mio_uartx_sbcr_s cn63xxp1;
2778 struct cvmx_mio_uartx_sbcr_s cn66xx;
2779 struct cvmx_mio_uartx_sbcr_s cn68xx;
2780 struct cvmx_mio_uartx_sbcr_s cn68xxp1;
1858}; 2781};
1859 2782
1860union cvmx_mio_uartx_scr { 2783union cvmx_mio_uartx_scr {
@@ -1874,8 +2797,12 @@ union cvmx_mio_uartx_scr {
1874 struct cvmx_mio_uartx_scr_s cn56xxp1; 2797 struct cvmx_mio_uartx_scr_s cn56xxp1;
1875 struct cvmx_mio_uartx_scr_s cn58xx; 2798 struct cvmx_mio_uartx_scr_s cn58xx;
1876 struct cvmx_mio_uartx_scr_s cn58xxp1; 2799 struct cvmx_mio_uartx_scr_s cn58xxp1;
2800 struct cvmx_mio_uartx_scr_s cn61xx;
1877 struct cvmx_mio_uartx_scr_s cn63xx; 2801 struct cvmx_mio_uartx_scr_s cn63xx;
1878 struct cvmx_mio_uartx_scr_s cn63xxp1; 2802 struct cvmx_mio_uartx_scr_s cn63xxp1;
2803 struct cvmx_mio_uartx_scr_s cn66xx;
2804 struct cvmx_mio_uartx_scr_s cn68xx;
2805 struct cvmx_mio_uartx_scr_s cn68xxp1;
1879}; 2806};
1880 2807
1881union cvmx_mio_uartx_sfe { 2808union cvmx_mio_uartx_sfe {
@@ -1895,8 +2822,12 @@ union cvmx_mio_uartx_sfe {
1895 struct cvmx_mio_uartx_sfe_s cn56xxp1; 2822 struct cvmx_mio_uartx_sfe_s cn56xxp1;
1896 struct cvmx_mio_uartx_sfe_s cn58xx; 2823 struct cvmx_mio_uartx_sfe_s cn58xx;
1897 struct cvmx_mio_uartx_sfe_s cn58xxp1; 2824 struct cvmx_mio_uartx_sfe_s cn58xxp1;
2825 struct cvmx_mio_uartx_sfe_s cn61xx;
1898 struct cvmx_mio_uartx_sfe_s cn63xx; 2826 struct cvmx_mio_uartx_sfe_s cn63xx;
1899 struct cvmx_mio_uartx_sfe_s cn63xxp1; 2827 struct cvmx_mio_uartx_sfe_s cn63xxp1;
2828 struct cvmx_mio_uartx_sfe_s cn66xx;
2829 struct cvmx_mio_uartx_sfe_s cn68xx;
2830 struct cvmx_mio_uartx_sfe_s cn68xxp1;
1900}; 2831};
1901 2832
1902union cvmx_mio_uartx_srr { 2833union cvmx_mio_uartx_srr {
@@ -1918,8 +2849,12 @@ union cvmx_mio_uartx_srr {
1918 struct cvmx_mio_uartx_srr_s cn56xxp1; 2849 struct cvmx_mio_uartx_srr_s cn56xxp1;
1919 struct cvmx_mio_uartx_srr_s cn58xx; 2850 struct cvmx_mio_uartx_srr_s cn58xx;
1920 struct cvmx_mio_uartx_srr_s cn58xxp1; 2851 struct cvmx_mio_uartx_srr_s cn58xxp1;
2852 struct cvmx_mio_uartx_srr_s cn61xx;
1921 struct cvmx_mio_uartx_srr_s cn63xx; 2853 struct cvmx_mio_uartx_srr_s cn63xx;
1922 struct cvmx_mio_uartx_srr_s cn63xxp1; 2854 struct cvmx_mio_uartx_srr_s cn63xxp1;
2855 struct cvmx_mio_uartx_srr_s cn66xx;
2856 struct cvmx_mio_uartx_srr_s cn68xx;
2857 struct cvmx_mio_uartx_srr_s cn68xxp1;
1923}; 2858};
1924 2859
1925union cvmx_mio_uartx_srt { 2860union cvmx_mio_uartx_srt {
@@ -1939,8 +2874,12 @@ union cvmx_mio_uartx_srt {
1939 struct cvmx_mio_uartx_srt_s cn56xxp1; 2874 struct cvmx_mio_uartx_srt_s cn56xxp1;
1940 struct cvmx_mio_uartx_srt_s cn58xx; 2875 struct cvmx_mio_uartx_srt_s cn58xx;
1941 struct cvmx_mio_uartx_srt_s cn58xxp1; 2876 struct cvmx_mio_uartx_srt_s cn58xxp1;
2877 struct cvmx_mio_uartx_srt_s cn61xx;
1942 struct cvmx_mio_uartx_srt_s cn63xx; 2878 struct cvmx_mio_uartx_srt_s cn63xx;
1943 struct cvmx_mio_uartx_srt_s cn63xxp1; 2879 struct cvmx_mio_uartx_srt_s cn63xxp1;
2880 struct cvmx_mio_uartx_srt_s cn66xx;
2881 struct cvmx_mio_uartx_srt_s cn68xx;
2882 struct cvmx_mio_uartx_srt_s cn68xxp1;
1944}; 2883};
1945 2884
1946union cvmx_mio_uartx_srts { 2885union cvmx_mio_uartx_srts {
@@ -1960,8 +2899,12 @@ union cvmx_mio_uartx_srts {
1960 struct cvmx_mio_uartx_srts_s cn56xxp1; 2899 struct cvmx_mio_uartx_srts_s cn56xxp1;
1961 struct cvmx_mio_uartx_srts_s cn58xx; 2900 struct cvmx_mio_uartx_srts_s cn58xx;
1962 struct cvmx_mio_uartx_srts_s cn58xxp1; 2901 struct cvmx_mio_uartx_srts_s cn58xxp1;
2902 struct cvmx_mio_uartx_srts_s cn61xx;
1963 struct cvmx_mio_uartx_srts_s cn63xx; 2903 struct cvmx_mio_uartx_srts_s cn63xx;
1964 struct cvmx_mio_uartx_srts_s cn63xxp1; 2904 struct cvmx_mio_uartx_srts_s cn63xxp1;
2905 struct cvmx_mio_uartx_srts_s cn66xx;
2906 struct cvmx_mio_uartx_srts_s cn68xx;
2907 struct cvmx_mio_uartx_srts_s cn68xxp1;
1965}; 2908};
1966 2909
1967union cvmx_mio_uartx_stt { 2910union cvmx_mio_uartx_stt {
@@ -1981,8 +2924,12 @@ union cvmx_mio_uartx_stt {
1981 struct cvmx_mio_uartx_stt_s cn56xxp1; 2924 struct cvmx_mio_uartx_stt_s cn56xxp1;
1982 struct cvmx_mio_uartx_stt_s cn58xx; 2925 struct cvmx_mio_uartx_stt_s cn58xx;
1983 struct cvmx_mio_uartx_stt_s cn58xxp1; 2926 struct cvmx_mio_uartx_stt_s cn58xxp1;
2927 struct cvmx_mio_uartx_stt_s cn61xx;
1984 struct cvmx_mio_uartx_stt_s cn63xx; 2928 struct cvmx_mio_uartx_stt_s cn63xx;
1985 struct cvmx_mio_uartx_stt_s cn63xxp1; 2929 struct cvmx_mio_uartx_stt_s cn63xxp1;
2930 struct cvmx_mio_uartx_stt_s cn66xx;
2931 struct cvmx_mio_uartx_stt_s cn68xx;
2932 struct cvmx_mio_uartx_stt_s cn68xxp1;
1986}; 2933};
1987 2934
1988union cvmx_mio_uartx_tfl { 2935union cvmx_mio_uartx_tfl {
@@ -2002,8 +2949,12 @@ union cvmx_mio_uartx_tfl {
2002 struct cvmx_mio_uartx_tfl_s cn56xxp1; 2949 struct cvmx_mio_uartx_tfl_s cn56xxp1;
2003 struct cvmx_mio_uartx_tfl_s cn58xx; 2950 struct cvmx_mio_uartx_tfl_s cn58xx;
2004 struct cvmx_mio_uartx_tfl_s cn58xxp1; 2951 struct cvmx_mio_uartx_tfl_s cn58xxp1;
2952 struct cvmx_mio_uartx_tfl_s cn61xx;
2005 struct cvmx_mio_uartx_tfl_s cn63xx; 2953 struct cvmx_mio_uartx_tfl_s cn63xx;
2006 struct cvmx_mio_uartx_tfl_s cn63xxp1; 2954 struct cvmx_mio_uartx_tfl_s cn63xxp1;
2955 struct cvmx_mio_uartx_tfl_s cn66xx;
2956 struct cvmx_mio_uartx_tfl_s cn68xx;
2957 struct cvmx_mio_uartx_tfl_s cn68xxp1;
2007}; 2958};
2008 2959
2009union cvmx_mio_uartx_tfr { 2960union cvmx_mio_uartx_tfr {
@@ -2023,8 +2974,12 @@ union cvmx_mio_uartx_tfr {
2023 struct cvmx_mio_uartx_tfr_s cn56xxp1; 2974 struct cvmx_mio_uartx_tfr_s cn56xxp1;
2024 struct cvmx_mio_uartx_tfr_s cn58xx; 2975 struct cvmx_mio_uartx_tfr_s cn58xx;
2025 struct cvmx_mio_uartx_tfr_s cn58xxp1; 2976 struct cvmx_mio_uartx_tfr_s cn58xxp1;
2977 struct cvmx_mio_uartx_tfr_s cn61xx;
2026 struct cvmx_mio_uartx_tfr_s cn63xx; 2978 struct cvmx_mio_uartx_tfr_s cn63xx;
2027 struct cvmx_mio_uartx_tfr_s cn63xxp1; 2979 struct cvmx_mio_uartx_tfr_s cn63xxp1;
2980 struct cvmx_mio_uartx_tfr_s cn66xx;
2981 struct cvmx_mio_uartx_tfr_s cn68xx;
2982 struct cvmx_mio_uartx_tfr_s cn68xxp1;
2028}; 2983};
2029 2984
2030union cvmx_mio_uartx_thr { 2985union cvmx_mio_uartx_thr {
@@ -2044,8 +2999,12 @@ union cvmx_mio_uartx_thr {
2044 struct cvmx_mio_uartx_thr_s cn56xxp1; 2999 struct cvmx_mio_uartx_thr_s cn56xxp1;
2045 struct cvmx_mio_uartx_thr_s cn58xx; 3000 struct cvmx_mio_uartx_thr_s cn58xx;
2046 struct cvmx_mio_uartx_thr_s cn58xxp1; 3001 struct cvmx_mio_uartx_thr_s cn58xxp1;
3002 struct cvmx_mio_uartx_thr_s cn61xx;
2047 struct cvmx_mio_uartx_thr_s cn63xx; 3003 struct cvmx_mio_uartx_thr_s cn63xx;
2048 struct cvmx_mio_uartx_thr_s cn63xxp1; 3004 struct cvmx_mio_uartx_thr_s cn63xxp1;
3005 struct cvmx_mio_uartx_thr_s cn66xx;
3006 struct cvmx_mio_uartx_thr_s cn68xx;
3007 struct cvmx_mio_uartx_thr_s cn68xxp1;
2049}; 3008};
2050 3009
2051union cvmx_mio_uartx_usr { 3010union cvmx_mio_uartx_usr {
@@ -2069,8 +3028,12 @@ union cvmx_mio_uartx_usr {
2069 struct cvmx_mio_uartx_usr_s cn56xxp1; 3028 struct cvmx_mio_uartx_usr_s cn56xxp1;
2070 struct cvmx_mio_uartx_usr_s cn58xx; 3029 struct cvmx_mio_uartx_usr_s cn58xx;
2071 struct cvmx_mio_uartx_usr_s cn58xxp1; 3030 struct cvmx_mio_uartx_usr_s cn58xxp1;
3031 struct cvmx_mio_uartx_usr_s cn61xx;
2072 struct cvmx_mio_uartx_usr_s cn63xx; 3032 struct cvmx_mio_uartx_usr_s cn63xx;
2073 struct cvmx_mio_uartx_usr_s cn63xxp1; 3033 struct cvmx_mio_uartx_usr_s cn63xxp1;
3034 struct cvmx_mio_uartx_usr_s cn66xx;
3035 struct cvmx_mio_uartx_usr_s cn68xx;
3036 struct cvmx_mio_uartx_usr_s cn68xxp1;
2074}; 3037};
2075 3038
2076union cvmx_mio_uart2_dlh { 3039union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 9899a9d2ba7..a3075f733ca 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -65,7 +65,7 @@
65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) 65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) 66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) 67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12) 68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) 69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) 70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) 71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index f8cb88902ef..7b1dc8b74e5 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -116,8 +116,12 @@ union cvmx_pciercx_cfg000 {
116 struct cvmx_pciercx_cfg000_s cn52xxp1; 116 struct cvmx_pciercx_cfg000_s cn52xxp1;
117 struct cvmx_pciercx_cfg000_s cn56xx; 117 struct cvmx_pciercx_cfg000_s cn56xx;
118 struct cvmx_pciercx_cfg000_s cn56xxp1; 118 struct cvmx_pciercx_cfg000_s cn56xxp1;
119 struct cvmx_pciercx_cfg000_s cn61xx;
119 struct cvmx_pciercx_cfg000_s cn63xx; 120 struct cvmx_pciercx_cfg000_s cn63xx;
120 struct cvmx_pciercx_cfg000_s cn63xxp1; 121 struct cvmx_pciercx_cfg000_s cn63xxp1;
122 struct cvmx_pciercx_cfg000_s cn66xx;
123 struct cvmx_pciercx_cfg000_s cn68xx;
124 struct cvmx_pciercx_cfg000_s cn68xxp1;
121}; 125};
122 126
123union cvmx_pciercx_cfg001 { 127union cvmx_pciercx_cfg001 {
@@ -152,8 +156,12 @@ union cvmx_pciercx_cfg001 {
152 struct cvmx_pciercx_cfg001_s cn52xxp1; 156 struct cvmx_pciercx_cfg001_s cn52xxp1;
153 struct cvmx_pciercx_cfg001_s cn56xx; 157 struct cvmx_pciercx_cfg001_s cn56xx;
154 struct cvmx_pciercx_cfg001_s cn56xxp1; 158 struct cvmx_pciercx_cfg001_s cn56xxp1;
159 struct cvmx_pciercx_cfg001_s cn61xx;
155 struct cvmx_pciercx_cfg001_s cn63xx; 160 struct cvmx_pciercx_cfg001_s cn63xx;
156 struct cvmx_pciercx_cfg001_s cn63xxp1; 161 struct cvmx_pciercx_cfg001_s cn63xxp1;
162 struct cvmx_pciercx_cfg001_s cn66xx;
163 struct cvmx_pciercx_cfg001_s cn68xx;
164 struct cvmx_pciercx_cfg001_s cn68xxp1;
157}; 165};
158 166
159union cvmx_pciercx_cfg002 { 167union cvmx_pciercx_cfg002 {
@@ -168,8 +176,12 @@ union cvmx_pciercx_cfg002 {
168 struct cvmx_pciercx_cfg002_s cn52xxp1; 176 struct cvmx_pciercx_cfg002_s cn52xxp1;
169 struct cvmx_pciercx_cfg002_s cn56xx; 177 struct cvmx_pciercx_cfg002_s cn56xx;
170 struct cvmx_pciercx_cfg002_s cn56xxp1; 178 struct cvmx_pciercx_cfg002_s cn56xxp1;
179 struct cvmx_pciercx_cfg002_s cn61xx;
171 struct cvmx_pciercx_cfg002_s cn63xx; 180 struct cvmx_pciercx_cfg002_s cn63xx;
172 struct cvmx_pciercx_cfg002_s cn63xxp1; 181 struct cvmx_pciercx_cfg002_s cn63xxp1;
182 struct cvmx_pciercx_cfg002_s cn66xx;
183 struct cvmx_pciercx_cfg002_s cn68xx;
184 struct cvmx_pciercx_cfg002_s cn68xxp1;
173}; 185};
174 186
175union cvmx_pciercx_cfg003 { 187union cvmx_pciercx_cfg003 {
@@ -185,8 +197,12 @@ union cvmx_pciercx_cfg003 {
185 struct cvmx_pciercx_cfg003_s cn52xxp1; 197 struct cvmx_pciercx_cfg003_s cn52xxp1;
186 struct cvmx_pciercx_cfg003_s cn56xx; 198 struct cvmx_pciercx_cfg003_s cn56xx;
187 struct cvmx_pciercx_cfg003_s cn56xxp1; 199 struct cvmx_pciercx_cfg003_s cn56xxp1;
200 struct cvmx_pciercx_cfg003_s cn61xx;
188 struct cvmx_pciercx_cfg003_s cn63xx; 201 struct cvmx_pciercx_cfg003_s cn63xx;
189 struct cvmx_pciercx_cfg003_s cn63xxp1; 202 struct cvmx_pciercx_cfg003_s cn63xxp1;
203 struct cvmx_pciercx_cfg003_s cn66xx;
204 struct cvmx_pciercx_cfg003_s cn68xx;
205 struct cvmx_pciercx_cfg003_s cn68xxp1;
190}; 206};
191 207
192union cvmx_pciercx_cfg004 { 208union cvmx_pciercx_cfg004 {
@@ -198,8 +214,12 @@ union cvmx_pciercx_cfg004 {
198 struct cvmx_pciercx_cfg004_s cn52xxp1; 214 struct cvmx_pciercx_cfg004_s cn52xxp1;
199 struct cvmx_pciercx_cfg004_s cn56xx; 215 struct cvmx_pciercx_cfg004_s cn56xx;
200 struct cvmx_pciercx_cfg004_s cn56xxp1; 216 struct cvmx_pciercx_cfg004_s cn56xxp1;
217 struct cvmx_pciercx_cfg004_s cn61xx;
201 struct cvmx_pciercx_cfg004_s cn63xx; 218 struct cvmx_pciercx_cfg004_s cn63xx;
202 struct cvmx_pciercx_cfg004_s cn63xxp1; 219 struct cvmx_pciercx_cfg004_s cn63xxp1;
220 struct cvmx_pciercx_cfg004_s cn66xx;
221 struct cvmx_pciercx_cfg004_s cn68xx;
222 struct cvmx_pciercx_cfg004_s cn68xxp1;
203}; 223};
204 224
205union cvmx_pciercx_cfg005 { 225union cvmx_pciercx_cfg005 {
@@ -211,8 +231,12 @@ union cvmx_pciercx_cfg005 {
211 struct cvmx_pciercx_cfg005_s cn52xxp1; 231 struct cvmx_pciercx_cfg005_s cn52xxp1;
212 struct cvmx_pciercx_cfg005_s cn56xx; 232 struct cvmx_pciercx_cfg005_s cn56xx;
213 struct cvmx_pciercx_cfg005_s cn56xxp1; 233 struct cvmx_pciercx_cfg005_s cn56xxp1;
234 struct cvmx_pciercx_cfg005_s cn61xx;
214 struct cvmx_pciercx_cfg005_s cn63xx; 235 struct cvmx_pciercx_cfg005_s cn63xx;
215 struct cvmx_pciercx_cfg005_s cn63xxp1; 236 struct cvmx_pciercx_cfg005_s cn63xxp1;
237 struct cvmx_pciercx_cfg005_s cn66xx;
238 struct cvmx_pciercx_cfg005_s cn68xx;
239 struct cvmx_pciercx_cfg005_s cn68xxp1;
216}; 240};
217 241
218union cvmx_pciercx_cfg006 { 242union cvmx_pciercx_cfg006 {
@@ -227,8 +251,12 @@ union cvmx_pciercx_cfg006 {
227 struct cvmx_pciercx_cfg006_s cn52xxp1; 251 struct cvmx_pciercx_cfg006_s cn52xxp1;
228 struct cvmx_pciercx_cfg006_s cn56xx; 252 struct cvmx_pciercx_cfg006_s cn56xx;
229 struct cvmx_pciercx_cfg006_s cn56xxp1; 253 struct cvmx_pciercx_cfg006_s cn56xxp1;
254 struct cvmx_pciercx_cfg006_s cn61xx;
230 struct cvmx_pciercx_cfg006_s cn63xx; 255 struct cvmx_pciercx_cfg006_s cn63xx;
231 struct cvmx_pciercx_cfg006_s cn63xxp1; 256 struct cvmx_pciercx_cfg006_s cn63xxp1;
257 struct cvmx_pciercx_cfg006_s cn66xx;
258 struct cvmx_pciercx_cfg006_s cn68xx;
259 struct cvmx_pciercx_cfg006_s cn68xxp1;
232}; 260};
233 261
234union cvmx_pciercx_cfg007 { 262union cvmx_pciercx_cfg007 {
@@ -256,8 +284,12 @@ union cvmx_pciercx_cfg007 {
256 struct cvmx_pciercx_cfg007_s cn52xxp1; 284 struct cvmx_pciercx_cfg007_s cn52xxp1;
257 struct cvmx_pciercx_cfg007_s cn56xx; 285 struct cvmx_pciercx_cfg007_s cn56xx;
258 struct cvmx_pciercx_cfg007_s cn56xxp1; 286 struct cvmx_pciercx_cfg007_s cn56xxp1;
287 struct cvmx_pciercx_cfg007_s cn61xx;
259 struct cvmx_pciercx_cfg007_s cn63xx; 288 struct cvmx_pciercx_cfg007_s cn63xx;
260 struct cvmx_pciercx_cfg007_s cn63xxp1; 289 struct cvmx_pciercx_cfg007_s cn63xxp1;
290 struct cvmx_pciercx_cfg007_s cn66xx;
291 struct cvmx_pciercx_cfg007_s cn68xx;
292 struct cvmx_pciercx_cfg007_s cn68xxp1;
261}; 293};
262 294
263union cvmx_pciercx_cfg008 { 295union cvmx_pciercx_cfg008 {
@@ -272,8 +304,12 @@ union cvmx_pciercx_cfg008 {
272 struct cvmx_pciercx_cfg008_s cn52xxp1; 304 struct cvmx_pciercx_cfg008_s cn52xxp1;
273 struct cvmx_pciercx_cfg008_s cn56xx; 305 struct cvmx_pciercx_cfg008_s cn56xx;
274 struct cvmx_pciercx_cfg008_s cn56xxp1; 306 struct cvmx_pciercx_cfg008_s cn56xxp1;
307 struct cvmx_pciercx_cfg008_s cn61xx;
275 struct cvmx_pciercx_cfg008_s cn63xx; 308 struct cvmx_pciercx_cfg008_s cn63xx;
276 struct cvmx_pciercx_cfg008_s cn63xxp1; 309 struct cvmx_pciercx_cfg008_s cn63xxp1;
310 struct cvmx_pciercx_cfg008_s cn66xx;
311 struct cvmx_pciercx_cfg008_s cn68xx;
312 struct cvmx_pciercx_cfg008_s cn68xxp1;
277}; 313};
278 314
279union cvmx_pciercx_cfg009 { 315union cvmx_pciercx_cfg009 {
@@ -290,8 +326,12 @@ union cvmx_pciercx_cfg009 {
290 struct cvmx_pciercx_cfg009_s cn52xxp1; 326 struct cvmx_pciercx_cfg009_s cn52xxp1;
291 struct cvmx_pciercx_cfg009_s cn56xx; 327 struct cvmx_pciercx_cfg009_s cn56xx;
292 struct cvmx_pciercx_cfg009_s cn56xxp1; 328 struct cvmx_pciercx_cfg009_s cn56xxp1;
329 struct cvmx_pciercx_cfg009_s cn61xx;
293 struct cvmx_pciercx_cfg009_s cn63xx; 330 struct cvmx_pciercx_cfg009_s cn63xx;
294 struct cvmx_pciercx_cfg009_s cn63xxp1; 331 struct cvmx_pciercx_cfg009_s cn63xxp1;
332 struct cvmx_pciercx_cfg009_s cn66xx;
333 struct cvmx_pciercx_cfg009_s cn68xx;
334 struct cvmx_pciercx_cfg009_s cn68xxp1;
295}; 335};
296 336
297union cvmx_pciercx_cfg010 { 337union cvmx_pciercx_cfg010 {
@@ -303,8 +343,12 @@ union cvmx_pciercx_cfg010 {
303 struct cvmx_pciercx_cfg010_s cn52xxp1; 343 struct cvmx_pciercx_cfg010_s cn52xxp1;
304 struct cvmx_pciercx_cfg010_s cn56xx; 344 struct cvmx_pciercx_cfg010_s cn56xx;
305 struct cvmx_pciercx_cfg010_s cn56xxp1; 345 struct cvmx_pciercx_cfg010_s cn56xxp1;
346 struct cvmx_pciercx_cfg010_s cn61xx;
306 struct cvmx_pciercx_cfg010_s cn63xx; 347 struct cvmx_pciercx_cfg010_s cn63xx;
307 struct cvmx_pciercx_cfg010_s cn63xxp1; 348 struct cvmx_pciercx_cfg010_s cn63xxp1;
349 struct cvmx_pciercx_cfg010_s cn66xx;
350 struct cvmx_pciercx_cfg010_s cn68xx;
351 struct cvmx_pciercx_cfg010_s cn68xxp1;
308}; 352};
309 353
310union cvmx_pciercx_cfg011 { 354union cvmx_pciercx_cfg011 {
@@ -316,8 +360,12 @@ union cvmx_pciercx_cfg011 {
316 struct cvmx_pciercx_cfg011_s cn52xxp1; 360 struct cvmx_pciercx_cfg011_s cn52xxp1;
317 struct cvmx_pciercx_cfg011_s cn56xx; 361 struct cvmx_pciercx_cfg011_s cn56xx;
318 struct cvmx_pciercx_cfg011_s cn56xxp1; 362 struct cvmx_pciercx_cfg011_s cn56xxp1;
363 struct cvmx_pciercx_cfg011_s cn61xx;
319 struct cvmx_pciercx_cfg011_s cn63xx; 364 struct cvmx_pciercx_cfg011_s cn63xx;
320 struct cvmx_pciercx_cfg011_s cn63xxp1; 365 struct cvmx_pciercx_cfg011_s cn63xxp1;
366 struct cvmx_pciercx_cfg011_s cn66xx;
367 struct cvmx_pciercx_cfg011_s cn68xx;
368 struct cvmx_pciercx_cfg011_s cn68xxp1;
321}; 369};
322 370
323union cvmx_pciercx_cfg012 { 371union cvmx_pciercx_cfg012 {
@@ -330,8 +378,12 @@ union cvmx_pciercx_cfg012 {
330 struct cvmx_pciercx_cfg012_s cn52xxp1; 378 struct cvmx_pciercx_cfg012_s cn52xxp1;
331 struct cvmx_pciercx_cfg012_s cn56xx; 379 struct cvmx_pciercx_cfg012_s cn56xx;
332 struct cvmx_pciercx_cfg012_s cn56xxp1; 380 struct cvmx_pciercx_cfg012_s cn56xxp1;
381 struct cvmx_pciercx_cfg012_s cn61xx;
333 struct cvmx_pciercx_cfg012_s cn63xx; 382 struct cvmx_pciercx_cfg012_s cn63xx;
334 struct cvmx_pciercx_cfg012_s cn63xxp1; 383 struct cvmx_pciercx_cfg012_s cn63xxp1;
384 struct cvmx_pciercx_cfg012_s cn66xx;
385 struct cvmx_pciercx_cfg012_s cn68xx;
386 struct cvmx_pciercx_cfg012_s cn68xxp1;
335}; 387};
336 388
337union cvmx_pciercx_cfg013 { 389union cvmx_pciercx_cfg013 {
@@ -344,8 +396,12 @@ union cvmx_pciercx_cfg013 {
344 struct cvmx_pciercx_cfg013_s cn52xxp1; 396 struct cvmx_pciercx_cfg013_s cn52xxp1;
345 struct cvmx_pciercx_cfg013_s cn56xx; 397 struct cvmx_pciercx_cfg013_s cn56xx;
346 struct cvmx_pciercx_cfg013_s cn56xxp1; 398 struct cvmx_pciercx_cfg013_s cn56xxp1;
399 struct cvmx_pciercx_cfg013_s cn61xx;
347 struct cvmx_pciercx_cfg013_s cn63xx; 400 struct cvmx_pciercx_cfg013_s cn63xx;
348 struct cvmx_pciercx_cfg013_s cn63xxp1; 401 struct cvmx_pciercx_cfg013_s cn63xxp1;
402 struct cvmx_pciercx_cfg013_s cn66xx;
403 struct cvmx_pciercx_cfg013_s cn68xx;
404 struct cvmx_pciercx_cfg013_s cn68xxp1;
349}; 405};
350 406
351union cvmx_pciercx_cfg014 { 407union cvmx_pciercx_cfg014 {
@@ -357,8 +413,12 @@ union cvmx_pciercx_cfg014 {
357 struct cvmx_pciercx_cfg014_s cn52xxp1; 413 struct cvmx_pciercx_cfg014_s cn52xxp1;
358 struct cvmx_pciercx_cfg014_s cn56xx; 414 struct cvmx_pciercx_cfg014_s cn56xx;
359 struct cvmx_pciercx_cfg014_s cn56xxp1; 415 struct cvmx_pciercx_cfg014_s cn56xxp1;
416 struct cvmx_pciercx_cfg014_s cn61xx;
360 struct cvmx_pciercx_cfg014_s cn63xx; 417 struct cvmx_pciercx_cfg014_s cn63xx;
361 struct cvmx_pciercx_cfg014_s cn63xxp1; 418 struct cvmx_pciercx_cfg014_s cn63xxp1;
419 struct cvmx_pciercx_cfg014_s cn66xx;
420 struct cvmx_pciercx_cfg014_s cn68xx;
421 struct cvmx_pciercx_cfg014_s cn68xxp1;
362}; 422};
363 423
364union cvmx_pciercx_cfg015 { 424union cvmx_pciercx_cfg015 {
@@ -384,8 +444,12 @@ union cvmx_pciercx_cfg015 {
384 struct cvmx_pciercx_cfg015_s cn52xxp1; 444 struct cvmx_pciercx_cfg015_s cn52xxp1;
385 struct cvmx_pciercx_cfg015_s cn56xx; 445 struct cvmx_pciercx_cfg015_s cn56xx;
386 struct cvmx_pciercx_cfg015_s cn56xxp1; 446 struct cvmx_pciercx_cfg015_s cn56xxp1;
447 struct cvmx_pciercx_cfg015_s cn61xx;
387 struct cvmx_pciercx_cfg015_s cn63xx; 448 struct cvmx_pciercx_cfg015_s cn63xx;
388 struct cvmx_pciercx_cfg015_s cn63xxp1; 449 struct cvmx_pciercx_cfg015_s cn63xxp1;
450 struct cvmx_pciercx_cfg015_s cn66xx;
451 struct cvmx_pciercx_cfg015_s cn68xx;
452 struct cvmx_pciercx_cfg015_s cn68xxp1;
389}; 453};
390 454
391union cvmx_pciercx_cfg016 { 455union cvmx_pciercx_cfg016 {
@@ -406,8 +470,12 @@ union cvmx_pciercx_cfg016 {
406 struct cvmx_pciercx_cfg016_s cn52xxp1; 470 struct cvmx_pciercx_cfg016_s cn52xxp1;
407 struct cvmx_pciercx_cfg016_s cn56xx; 471 struct cvmx_pciercx_cfg016_s cn56xx;
408 struct cvmx_pciercx_cfg016_s cn56xxp1; 472 struct cvmx_pciercx_cfg016_s cn56xxp1;
473 struct cvmx_pciercx_cfg016_s cn61xx;
409 struct cvmx_pciercx_cfg016_s cn63xx; 474 struct cvmx_pciercx_cfg016_s cn63xx;
410 struct cvmx_pciercx_cfg016_s cn63xxp1; 475 struct cvmx_pciercx_cfg016_s cn63xxp1;
476 struct cvmx_pciercx_cfg016_s cn66xx;
477 struct cvmx_pciercx_cfg016_s cn68xx;
478 struct cvmx_pciercx_cfg016_s cn68xxp1;
411}; 479};
412 480
413union cvmx_pciercx_cfg017 { 481union cvmx_pciercx_cfg017 {
@@ -430,14 +498,19 @@ union cvmx_pciercx_cfg017 {
430 struct cvmx_pciercx_cfg017_s cn52xxp1; 498 struct cvmx_pciercx_cfg017_s cn52xxp1;
431 struct cvmx_pciercx_cfg017_s cn56xx; 499 struct cvmx_pciercx_cfg017_s cn56xx;
432 struct cvmx_pciercx_cfg017_s cn56xxp1; 500 struct cvmx_pciercx_cfg017_s cn56xxp1;
501 struct cvmx_pciercx_cfg017_s cn61xx;
433 struct cvmx_pciercx_cfg017_s cn63xx; 502 struct cvmx_pciercx_cfg017_s cn63xx;
434 struct cvmx_pciercx_cfg017_s cn63xxp1; 503 struct cvmx_pciercx_cfg017_s cn63xxp1;
504 struct cvmx_pciercx_cfg017_s cn66xx;
505 struct cvmx_pciercx_cfg017_s cn68xx;
506 struct cvmx_pciercx_cfg017_s cn68xxp1;
435}; 507};
436 508
437union cvmx_pciercx_cfg020 { 509union cvmx_pciercx_cfg020 {
438 uint32_t u32; 510 uint32_t u32;
439 struct cvmx_pciercx_cfg020_s { 511 struct cvmx_pciercx_cfg020_s {
440 uint32_t reserved_24_31:8; 512 uint32_t reserved_25_31:7;
513 uint32_t pvm:1;
441 uint32_t m64:1; 514 uint32_t m64:1;
442 uint32_t mme:3; 515 uint32_t mme:3;
443 uint32_t mmc:3; 516 uint32_t mmc:3;
@@ -445,12 +518,24 @@ union cvmx_pciercx_cfg020 {
445 uint32_t ncp:8; 518 uint32_t ncp:8;
446 uint32_t msicid:8; 519 uint32_t msicid:8;
447 } s; 520 } s;
448 struct cvmx_pciercx_cfg020_s cn52xx; 521 struct cvmx_pciercx_cfg020_cn52xx {
449 struct cvmx_pciercx_cfg020_s cn52xxp1; 522 uint32_t reserved_24_31:8;
450 struct cvmx_pciercx_cfg020_s cn56xx; 523 uint32_t m64:1;
451 struct cvmx_pciercx_cfg020_s cn56xxp1; 524 uint32_t mme:3;
452 struct cvmx_pciercx_cfg020_s cn63xx; 525 uint32_t mmc:3;
453 struct cvmx_pciercx_cfg020_s cn63xxp1; 526 uint32_t msien:1;
527 uint32_t ncp:8;
528 uint32_t msicid:8;
529 } cn52xx;
530 struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
531 struct cvmx_pciercx_cfg020_cn52xx cn56xx;
532 struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
533 struct cvmx_pciercx_cfg020_s cn61xx;
534 struct cvmx_pciercx_cfg020_cn52xx cn63xx;
535 struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
536 struct cvmx_pciercx_cfg020_cn52xx cn66xx;
537 struct cvmx_pciercx_cfg020_cn52xx cn68xx;
538 struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
454}; 539};
455 540
456union cvmx_pciercx_cfg021 { 541union cvmx_pciercx_cfg021 {
@@ -463,8 +548,12 @@ union cvmx_pciercx_cfg021 {
463 struct cvmx_pciercx_cfg021_s cn52xxp1; 548 struct cvmx_pciercx_cfg021_s cn52xxp1;
464 struct cvmx_pciercx_cfg021_s cn56xx; 549 struct cvmx_pciercx_cfg021_s cn56xx;
465 struct cvmx_pciercx_cfg021_s cn56xxp1; 550 struct cvmx_pciercx_cfg021_s cn56xxp1;
551 struct cvmx_pciercx_cfg021_s cn61xx;
466 struct cvmx_pciercx_cfg021_s cn63xx; 552 struct cvmx_pciercx_cfg021_s cn63xx;
467 struct cvmx_pciercx_cfg021_s cn63xxp1; 553 struct cvmx_pciercx_cfg021_s cn63xxp1;
554 struct cvmx_pciercx_cfg021_s cn66xx;
555 struct cvmx_pciercx_cfg021_s cn68xx;
556 struct cvmx_pciercx_cfg021_s cn68xxp1;
468}; 557};
469 558
470union cvmx_pciercx_cfg022 { 559union cvmx_pciercx_cfg022 {
@@ -476,8 +565,12 @@ union cvmx_pciercx_cfg022 {
476 struct cvmx_pciercx_cfg022_s cn52xxp1; 565 struct cvmx_pciercx_cfg022_s cn52xxp1;
477 struct cvmx_pciercx_cfg022_s cn56xx; 566 struct cvmx_pciercx_cfg022_s cn56xx;
478 struct cvmx_pciercx_cfg022_s cn56xxp1; 567 struct cvmx_pciercx_cfg022_s cn56xxp1;
568 struct cvmx_pciercx_cfg022_s cn61xx;
479 struct cvmx_pciercx_cfg022_s cn63xx; 569 struct cvmx_pciercx_cfg022_s cn63xx;
480 struct cvmx_pciercx_cfg022_s cn63xxp1; 570 struct cvmx_pciercx_cfg022_s cn63xxp1;
571 struct cvmx_pciercx_cfg022_s cn66xx;
572 struct cvmx_pciercx_cfg022_s cn68xx;
573 struct cvmx_pciercx_cfg022_s cn68xxp1;
481}; 574};
482 575
483union cvmx_pciercx_cfg023 { 576union cvmx_pciercx_cfg023 {
@@ -490,8 +583,12 @@ union cvmx_pciercx_cfg023 {
490 struct cvmx_pciercx_cfg023_s cn52xxp1; 583 struct cvmx_pciercx_cfg023_s cn52xxp1;
491 struct cvmx_pciercx_cfg023_s cn56xx; 584 struct cvmx_pciercx_cfg023_s cn56xx;
492 struct cvmx_pciercx_cfg023_s cn56xxp1; 585 struct cvmx_pciercx_cfg023_s cn56xxp1;
586 struct cvmx_pciercx_cfg023_s cn61xx;
493 struct cvmx_pciercx_cfg023_s cn63xx; 587 struct cvmx_pciercx_cfg023_s cn63xx;
494 struct cvmx_pciercx_cfg023_s cn63xxp1; 588 struct cvmx_pciercx_cfg023_s cn63xxp1;
589 struct cvmx_pciercx_cfg023_s cn66xx;
590 struct cvmx_pciercx_cfg023_s cn68xx;
591 struct cvmx_pciercx_cfg023_s cn68xxp1;
495}; 592};
496 593
497union cvmx_pciercx_cfg028 { 594union cvmx_pciercx_cfg028 {
@@ -509,8 +606,12 @@ union cvmx_pciercx_cfg028 {
509 struct cvmx_pciercx_cfg028_s cn52xxp1; 606 struct cvmx_pciercx_cfg028_s cn52xxp1;
510 struct cvmx_pciercx_cfg028_s cn56xx; 607 struct cvmx_pciercx_cfg028_s cn56xx;
511 struct cvmx_pciercx_cfg028_s cn56xxp1; 608 struct cvmx_pciercx_cfg028_s cn56xxp1;
609 struct cvmx_pciercx_cfg028_s cn61xx;
512 struct cvmx_pciercx_cfg028_s cn63xx; 610 struct cvmx_pciercx_cfg028_s cn63xx;
513 struct cvmx_pciercx_cfg028_s cn63xxp1; 611 struct cvmx_pciercx_cfg028_s cn63xxp1;
612 struct cvmx_pciercx_cfg028_s cn66xx;
613 struct cvmx_pciercx_cfg028_s cn68xx;
614 struct cvmx_pciercx_cfg028_s cn68xxp1;
514}; 615};
515 616
516union cvmx_pciercx_cfg029 { 617union cvmx_pciercx_cfg029 {
@@ -532,8 +633,12 @@ union cvmx_pciercx_cfg029 {
532 struct cvmx_pciercx_cfg029_s cn52xxp1; 633 struct cvmx_pciercx_cfg029_s cn52xxp1;
533 struct cvmx_pciercx_cfg029_s cn56xx; 634 struct cvmx_pciercx_cfg029_s cn56xx;
534 struct cvmx_pciercx_cfg029_s cn56xxp1; 635 struct cvmx_pciercx_cfg029_s cn56xxp1;
636 struct cvmx_pciercx_cfg029_s cn61xx;
535 struct cvmx_pciercx_cfg029_s cn63xx; 637 struct cvmx_pciercx_cfg029_s cn63xx;
536 struct cvmx_pciercx_cfg029_s cn63xxp1; 638 struct cvmx_pciercx_cfg029_s cn63xxp1;
639 struct cvmx_pciercx_cfg029_s cn66xx;
640 struct cvmx_pciercx_cfg029_s cn68xx;
641 struct cvmx_pciercx_cfg029_s cn68xxp1;
537}; 642};
538 643
539union cvmx_pciercx_cfg030 { 644union cvmx_pciercx_cfg030 {
@@ -563,15 +668,20 @@ union cvmx_pciercx_cfg030 {
563 struct cvmx_pciercx_cfg030_s cn52xxp1; 668 struct cvmx_pciercx_cfg030_s cn52xxp1;
564 struct cvmx_pciercx_cfg030_s cn56xx; 669 struct cvmx_pciercx_cfg030_s cn56xx;
565 struct cvmx_pciercx_cfg030_s cn56xxp1; 670 struct cvmx_pciercx_cfg030_s cn56xxp1;
671 struct cvmx_pciercx_cfg030_s cn61xx;
566 struct cvmx_pciercx_cfg030_s cn63xx; 672 struct cvmx_pciercx_cfg030_s cn63xx;
567 struct cvmx_pciercx_cfg030_s cn63xxp1; 673 struct cvmx_pciercx_cfg030_s cn63xxp1;
674 struct cvmx_pciercx_cfg030_s cn66xx;
675 struct cvmx_pciercx_cfg030_s cn68xx;
676 struct cvmx_pciercx_cfg030_s cn68xxp1;
568}; 677};
569 678
570union cvmx_pciercx_cfg031 { 679union cvmx_pciercx_cfg031 {
571 uint32_t u32; 680 uint32_t u32;
572 struct cvmx_pciercx_cfg031_s { 681 struct cvmx_pciercx_cfg031_s {
573 uint32_t pnum:8; 682 uint32_t pnum:8;
574 uint32_t reserved_22_23:2; 683 uint32_t reserved_23_23:1;
684 uint32_t aspm:1;
575 uint32_t lbnc:1; 685 uint32_t lbnc:1;
576 uint32_t dllarc:1; 686 uint32_t dllarc:1;
577 uint32_t sderc:1; 687 uint32_t sderc:1;
@@ -582,12 +692,28 @@ union cvmx_pciercx_cfg031 {
582 uint32_t mlw:6; 692 uint32_t mlw:6;
583 uint32_t mls:4; 693 uint32_t mls:4;
584 } s; 694 } s;
585 struct cvmx_pciercx_cfg031_s cn52xx; 695 struct cvmx_pciercx_cfg031_cn52xx {
586 struct cvmx_pciercx_cfg031_s cn52xxp1; 696 uint32_t pnum:8;
587 struct cvmx_pciercx_cfg031_s cn56xx; 697 uint32_t reserved_22_23:2;
588 struct cvmx_pciercx_cfg031_s cn56xxp1; 698 uint32_t lbnc:1;
589 struct cvmx_pciercx_cfg031_s cn63xx; 699 uint32_t dllarc:1;
590 struct cvmx_pciercx_cfg031_s cn63xxp1; 700 uint32_t sderc:1;
701 uint32_t cpm:1;
702 uint32_t l1el:3;
703 uint32_t l0el:3;
704 uint32_t aslpms:2;
705 uint32_t mlw:6;
706 uint32_t mls:4;
707 } cn52xx;
708 struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
709 struct cvmx_pciercx_cfg031_cn52xx cn56xx;
710 struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
711 struct cvmx_pciercx_cfg031_s cn61xx;
712 struct cvmx_pciercx_cfg031_cn52xx cn63xx;
713 struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
714 struct cvmx_pciercx_cfg031_s cn66xx;
715 struct cvmx_pciercx_cfg031_s cn68xx;
716 struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
591}; 717};
592 718
593union cvmx_pciercx_cfg032 { 719union cvmx_pciercx_cfg032 {
@@ -618,8 +744,12 @@ union cvmx_pciercx_cfg032 {
618 struct cvmx_pciercx_cfg032_s cn52xxp1; 744 struct cvmx_pciercx_cfg032_s cn52xxp1;
619 struct cvmx_pciercx_cfg032_s cn56xx; 745 struct cvmx_pciercx_cfg032_s cn56xx;
620 struct cvmx_pciercx_cfg032_s cn56xxp1; 746 struct cvmx_pciercx_cfg032_s cn56xxp1;
747 struct cvmx_pciercx_cfg032_s cn61xx;
621 struct cvmx_pciercx_cfg032_s cn63xx; 748 struct cvmx_pciercx_cfg032_s cn63xx;
622 struct cvmx_pciercx_cfg032_s cn63xxp1; 749 struct cvmx_pciercx_cfg032_s cn63xxp1;
750 struct cvmx_pciercx_cfg032_s cn66xx;
751 struct cvmx_pciercx_cfg032_s cn68xx;
752 struct cvmx_pciercx_cfg032_s cn68xxp1;
623}; 753};
624 754
625union cvmx_pciercx_cfg033 { 755union cvmx_pciercx_cfg033 {
@@ -642,8 +772,12 @@ union cvmx_pciercx_cfg033 {
642 struct cvmx_pciercx_cfg033_s cn52xxp1; 772 struct cvmx_pciercx_cfg033_s cn52xxp1;
643 struct cvmx_pciercx_cfg033_s cn56xx; 773 struct cvmx_pciercx_cfg033_s cn56xx;
644 struct cvmx_pciercx_cfg033_s cn56xxp1; 774 struct cvmx_pciercx_cfg033_s cn56xxp1;
775 struct cvmx_pciercx_cfg033_s cn61xx;
645 struct cvmx_pciercx_cfg033_s cn63xx; 776 struct cvmx_pciercx_cfg033_s cn63xx;
646 struct cvmx_pciercx_cfg033_s cn63xxp1; 777 struct cvmx_pciercx_cfg033_s cn63xxp1;
778 struct cvmx_pciercx_cfg033_s cn66xx;
779 struct cvmx_pciercx_cfg033_s cn68xx;
780 struct cvmx_pciercx_cfg033_s cn68xxp1;
647}; 781};
648 782
649union cvmx_pciercx_cfg034 { 783union cvmx_pciercx_cfg034 {
@@ -676,8 +810,12 @@ union cvmx_pciercx_cfg034 {
676 struct cvmx_pciercx_cfg034_s cn52xxp1; 810 struct cvmx_pciercx_cfg034_s cn52xxp1;
677 struct cvmx_pciercx_cfg034_s cn56xx; 811 struct cvmx_pciercx_cfg034_s cn56xx;
678 struct cvmx_pciercx_cfg034_s cn56xxp1; 812 struct cvmx_pciercx_cfg034_s cn56xxp1;
813 struct cvmx_pciercx_cfg034_s cn61xx;
679 struct cvmx_pciercx_cfg034_s cn63xx; 814 struct cvmx_pciercx_cfg034_s cn63xx;
680 struct cvmx_pciercx_cfg034_s cn63xxp1; 815 struct cvmx_pciercx_cfg034_s cn63xxp1;
816 struct cvmx_pciercx_cfg034_s cn66xx;
817 struct cvmx_pciercx_cfg034_s cn68xx;
818 struct cvmx_pciercx_cfg034_s cn68xxp1;
681}; 819};
682 820
683union cvmx_pciercx_cfg035 { 821union cvmx_pciercx_cfg035 {
@@ -696,8 +834,12 @@ union cvmx_pciercx_cfg035 {
696 struct cvmx_pciercx_cfg035_s cn52xxp1; 834 struct cvmx_pciercx_cfg035_s cn52xxp1;
697 struct cvmx_pciercx_cfg035_s cn56xx; 835 struct cvmx_pciercx_cfg035_s cn56xx;
698 struct cvmx_pciercx_cfg035_s cn56xxp1; 836 struct cvmx_pciercx_cfg035_s cn56xxp1;
837 struct cvmx_pciercx_cfg035_s cn61xx;
699 struct cvmx_pciercx_cfg035_s cn63xx; 838 struct cvmx_pciercx_cfg035_s cn63xx;
700 struct cvmx_pciercx_cfg035_s cn63xxp1; 839 struct cvmx_pciercx_cfg035_s cn63xxp1;
840 struct cvmx_pciercx_cfg035_s cn66xx;
841 struct cvmx_pciercx_cfg035_s cn68xx;
842 struct cvmx_pciercx_cfg035_s cn68xxp1;
701}; 843};
702 844
703union cvmx_pciercx_cfg036 { 845union cvmx_pciercx_cfg036 {
@@ -712,38 +854,95 @@ union cvmx_pciercx_cfg036 {
712 struct cvmx_pciercx_cfg036_s cn52xxp1; 854 struct cvmx_pciercx_cfg036_s cn52xxp1;
713 struct cvmx_pciercx_cfg036_s cn56xx; 855 struct cvmx_pciercx_cfg036_s cn56xx;
714 struct cvmx_pciercx_cfg036_s cn56xxp1; 856 struct cvmx_pciercx_cfg036_s cn56xxp1;
857 struct cvmx_pciercx_cfg036_s cn61xx;
715 struct cvmx_pciercx_cfg036_s cn63xx; 858 struct cvmx_pciercx_cfg036_s cn63xx;
716 struct cvmx_pciercx_cfg036_s cn63xxp1; 859 struct cvmx_pciercx_cfg036_s cn63xxp1;
860 struct cvmx_pciercx_cfg036_s cn66xx;
861 struct cvmx_pciercx_cfg036_s cn68xx;
862 struct cvmx_pciercx_cfg036_s cn68xxp1;
717}; 863};
718 864
719union cvmx_pciercx_cfg037 { 865union cvmx_pciercx_cfg037 {
720 uint32_t u32; 866 uint32_t u32;
721 struct cvmx_pciercx_cfg037_s { 867 struct cvmx_pciercx_cfg037_s {
722 uint32_t reserved_5_31:27; 868 uint32_t reserved_14_31:18;
869 uint32_t tph:2;
870 uint32_t reserved_11_11:1;
871 uint32_t noroprpr:1;
872 uint32_t atom128s:1;
873 uint32_t atom64s:1;
874 uint32_t atom32s:1;
875 uint32_t atom_ops:1;
876 uint32_t reserved_5_5:1;
723 uint32_t ctds:1; 877 uint32_t ctds:1;
724 uint32_t ctrs:4; 878 uint32_t ctrs:4;
725 } s; 879 } s;
726 struct cvmx_pciercx_cfg037_s cn52xx; 880 struct cvmx_pciercx_cfg037_cn52xx {
727 struct cvmx_pciercx_cfg037_s cn52xxp1; 881 uint32_t reserved_5_31:27;
728 struct cvmx_pciercx_cfg037_s cn56xx; 882 uint32_t ctds:1;
729 struct cvmx_pciercx_cfg037_s cn56xxp1; 883 uint32_t ctrs:4;
730 struct cvmx_pciercx_cfg037_s cn63xx; 884 } cn52xx;
731 struct cvmx_pciercx_cfg037_s cn63xxp1; 885 struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
886 struct cvmx_pciercx_cfg037_cn52xx cn56xx;
887 struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
888 struct cvmx_pciercx_cfg037_cn61xx {
889 uint32_t reserved_14_31:18;
890 uint32_t tph:2;
891 uint32_t reserved_11_11:1;
892 uint32_t noroprpr:1;
893 uint32_t atom128s:1;
894 uint32_t atom64s:1;
895 uint32_t atom32s:1;
896 uint32_t atom_ops:1;
897 uint32_t ari_fw:1;
898 uint32_t ctds:1;
899 uint32_t ctrs:4;
900 } cn61xx;
901 struct cvmx_pciercx_cfg037_cn52xx cn63xx;
902 struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
903 struct cvmx_pciercx_cfg037_cn66xx {
904 uint32_t reserved_14_31:18;
905 uint32_t tph:2;
906 uint32_t reserved_11_11:1;
907 uint32_t noroprpr:1;
908 uint32_t atom128s:1;
909 uint32_t atom64s:1;
910 uint32_t atom32s:1;
911 uint32_t atom_ops:1;
912 uint32_t ari:1;
913 uint32_t ctds:1;
914 uint32_t ctrs:4;
915 } cn66xx;
916 struct cvmx_pciercx_cfg037_cn66xx cn68xx;
917 struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
732}; 918};
733 919
734union cvmx_pciercx_cfg038 { 920union cvmx_pciercx_cfg038 {
735 uint32_t u32; 921 uint32_t u32;
736 struct cvmx_pciercx_cfg038_s { 922 struct cvmx_pciercx_cfg038_s {
737 uint32_t reserved_5_31:27; 923 uint32_t reserved_10_31:22;
924 uint32_t id0_cp:1;
925 uint32_t id0_rq:1;
926 uint32_t atom_op_eb:1;
927 uint32_t atom_op:1;
928 uint32_t ari:1;
738 uint32_t ctd:1; 929 uint32_t ctd:1;
739 uint32_t ctv:4; 930 uint32_t ctv:4;
740 } s; 931 } s;
741 struct cvmx_pciercx_cfg038_s cn52xx; 932 struct cvmx_pciercx_cfg038_cn52xx {
742 struct cvmx_pciercx_cfg038_s cn52xxp1; 933 uint32_t reserved_5_31:27;
743 struct cvmx_pciercx_cfg038_s cn56xx; 934 uint32_t ctd:1;
744 struct cvmx_pciercx_cfg038_s cn56xxp1; 935 uint32_t ctv:4;
745 struct cvmx_pciercx_cfg038_s cn63xx; 936 } cn52xx;
746 struct cvmx_pciercx_cfg038_s cn63xxp1; 937 struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
938 struct cvmx_pciercx_cfg038_cn52xx cn56xx;
939 struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
940 struct cvmx_pciercx_cfg038_s cn61xx;
941 struct cvmx_pciercx_cfg038_cn52xx cn63xx;
942 struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
943 struct cvmx_pciercx_cfg038_s cn66xx;
944 struct cvmx_pciercx_cfg038_s cn68xx;
945 struct cvmx_pciercx_cfg038_s cn68xxp1;
747}; 946};
748 947
749union cvmx_pciercx_cfg039 { 948union cvmx_pciercx_cfg039 {
@@ -760,8 +959,12 @@ union cvmx_pciercx_cfg039 {
760 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; 959 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
761 struct cvmx_pciercx_cfg039_cn52xx cn56xx; 960 struct cvmx_pciercx_cfg039_cn52xx cn56xx;
762 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1; 961 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
962 struct cvmx_pciercx_cfg039_s cn61xx;
763 struct cvmx_pciercx_cfg039_s cn63xx; 963 struct cvmx_pciercx_cfg039_s cn63xx;
764 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1; 964 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
965 struct cvmx_pciercx_cfg039_s cn66xx;
966 struct cvmx_pciercx_cfg039_s cn68xx;
967 struct cvmx_pciercx_cfg039_s cn68xxp1;
765}; 968};
766 969
767union cvmx_pciercx_cfg040 { 970union cvmx_pciercx_cfg040 {
@@ -785,8 +988,12 @@ union cvmx_pciercx_cfg040 {
785 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 988 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
786 struct cvmx_pciercx_cfg040_cn52xx cn56xx; 989 struct cvmx_pciercx_cfg040_cn52xx cn56xx;
787 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 990 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
991 struct cvmx_pciercx_cfg040_s cn61xx;
788 struct cvmx_pciercx_cfg040_s cn63xx; 992 struct cvmx_pciercx_cfg040_s cn63xx;
789 struct cvmx_pciercx_cfg040_s cn63xxp1; 993 struct cvmx_pciercx_cfg040_s cn63xxp1;
994 struct cvmx_pciercx_cfg040_s cn66xx;
995 struct cvmx_pciercx_cfg040_s cn68xx;
996 struct cvmx_pciercx_cfg040_s cn68xxp1;
790}; 997};
791 998
792union cvmx_pciercx_cfg041 { 999union cvmx_pciercx_cfg041 {
@@ -798,8 +1005,12 @@ union cvmx_pciercx_cfg041 {
798 struct cvmx_pciercx_cfg041_s cn52xxp1; 1005 struct cvmx_pciercx_cfg041_s cn52xxp1;
799 struct cvmx_pciercx_cfg041_s cn56xx; 1006 struct cvmx_pciercx_cfg041_s cn56xx;
800 struct cvmx_pciercx_cfg041_s cn56xxp1; 1007 struct cvmx_pciercx_cfg041_s cn56xxp1;
1008 struct cvmx_pciercx_cfg041_s cn61xx;
801 struct cvmx_pciercx_cfg041_s cn63xx; 1009 struct cvmx_pciercx_cfg041_s cn63xx;
802 struct cvmx_pciercx_cfg041_s cn63xxp1; 1010 struct cvmx_pciercx_cfg041_s cn63xxp1;
1011 struct cvmx_pciercx_cfg041_s cn66xx;
1012 struct cvmx_pciercx_cfg041_s cn68xx;
1013 struct cvmx_pciercx_cfg041_s cn68xxp1;
803}; 1014};
804 1015
805union cvmx_pciercx_cfg042 { 1016union cvmx_pciercx_cfg042 {
@@ -811,8 +1022,12 @@ union cvmx_pciercx_cfg042 {
811 struct cvmx_pciercx_cfg042_s cn52xxp1; 1022 struct cvmx_pciercx_cfg042_s cn52xxp1;
812 struct cvmx_pciercx_cfg042_s cn56xx; 1023 struct cvmx_pciercx_cfg042_s cn56xx;
813 struct cvmx_pciercx_cfg042_s cn56xxp1; 1024 struct cvmx_pciercx_cfg042_s cn56xxp1;
1025 struct cvmx_pciercx_cfg042_s cn61xx;
814 struct cvmx_pciercx_cfg042_s cn63xx; 1026 struct cvmx_pciercx_cfg042_s cn63xx;
815 struct cvmx_pciercx_cfg042_s cn63xxp1; 1027 struct cvmx_pciercx_cfg042_s cn63xxp1;
1028 struct cvmx_pciercx_cfg042_s cn66xx;
1029 struct cvmx_pciercx_cfg042_s cn68xx;
1030 struct cvmx_pciercx_cfg042_s cn68xxp1;
816}; 1031};
817 1032
818union cvmx_pciercx_cfg064 { 1033union cvmx_pciercx_cfg064 {
@@ -826,14 +1041,20 @@ union cvmx_pciercx_cfg064 {
826 struct cvmx_pciercx_cfg064_s cn52xxp1; 1041 struct cvmx_pciercx_cfg064_s cn52xxp1;
827 struct cvmx_pciercx_cfg064_s cn56xx; 1042 struct cvmx_pciercx_cfg064_s cn56xx;
828 struct cvmx_pciercx_cfg064_s cn56xxp1; 1043 struct cvmx_pciercx_cfg064_s cn56xxp1;
1044 struct cvmx_pciercx_cfg064_s cn61xx;
829 struct cvmx_pciercx_cfg064_s cn63xx; 1045 struct cvmx_pciercx_cfg064_s cn63xx;
830 struct cvmx_pciercx_cfg064_s cn63xxp1; 1046 struct cvmx_pciercx_cfg064_s cn63xxp1;
1047 struct cvmx_pciercx_cfg064_s cn66xx;
1048 struct cvmx_pciercx_cfg064_s cn68xx;
1049 struct cvmx_pciercx_cfg064_s cn68xxp1;
831}; 1050};
832 1051
833union cvmx_pciercx_cfg065 { 1052union cvmx_pciercx_cfg065 {
834 uint32_t u32; 1053 uint32_t u32;
835 struct cvmx_pciercx_cfg065_s { 1054 struct cvmx_pciercx_cfg065_s {
836 uint32_t reserved_21_31:11; 1055 uint32_t reserved_25_31:7;
1056 uint32_t uatombs:1;
1057 uint32_t reserved_21_23:3;
837 uint32_t ures:1; 1058 uint32_t ures:1;
838 uint32_t ecrces:1; 1059 uint32_t ecrces:1;
839 uint32_t mtlps:1; 1060 uint32_t mtlps:1;
@@ -848,18 +1069,39 @@ union cvmx_pciercx_cfg065 {
848 uint32_t dlpes:1; 1069 uint32_t dlpes:1;
849 uint32_t reserved_0_3:4; 1070 uint32_t reserved_0_3:4;
850 } s; 1071 } s;
851 struct cvmx_pciercx_cfg065_s cn52xx; 1072 struct cvmx_pciercx_cfg065_cn52xx {
852 struct cvmx_pciercx_cfg065_s cn52xxp1; 1073 uint32_t reserved_21_31:11;
853 struct cvmx_pciercx_cfg065_s cn56xx; 1074 uint32_t ures:1;
854 struct cvmx_pciercx_cfg065_s cn56xxp1; 1075 uint32_t ecrces:1;
855 struct cvmx_pciercx_cfg065_s cn63xx; 1076 uint32_t mtlps:1;
856 struct cvmx_pciercx_cfg065_s cn63xxp1; 1077 uint32_t ros:1;
1078 uint32_t ucs:1;
1079 uint32_t cas:1;
1080 uint32_t cts:1;
1081 uint32_t fcpes:1;
1082 uint32_t ptlps:1;
1083 uint32_t reserved_6_11:6;
1084 uint32_t sdes:1;
1085 uint32_t dlpes:1;
1086 uint32_t reserved_0_3:4;
1087 } cn52xx;
1088 struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
1089 struct cvmx_pciercx_cfg065_cn52xx cn56xx;
1090 struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
1091 struct cvmx_pciercx_cfg065_s cn61xx;
1092 struct cvmx_pciercx_cfg065_cn52xx cn63xx;
1093 struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
1094 struct cvmx_pciercx_cfg065_s cn66xx;
1095 struct cvmx_pciercx_cfg065_s cn68xx;
1096 struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
857}; 1097};
858 1098
859union cvmx_pciercx_cfg066 { 1099union cvmx_pciercx_cfg066 {
860 uint32_t u32; 1100 uint32_t u32;
861 struct cvmx_pciercx_cfg066_s { 1101 struct cvmx_pciercx_cfg066_s {
862 uint32_t reserved_21_31:11; 1102 uint32_t reserved_25_31:7;
1103 uint32_t uatombm:1;
1104 uint32_t reserved_21_23:3;
863 uint32_t urem:1; 1105 uint32_t urem:1;
864 uint32_t ecrcem:1; 1106 uint32_t ecrcem:1;
865 uint32_t mtlpm:1; 1107 uint32_t mtlpm:1;
@@ -874,18 +1116,39 @@ union cvmx_pciercx_cfg066 {
874 uint32_t dlpem:1; 1116 uint32_t dlpem:1;
875 uint32_t reserved_0_3:4; 1117 uint32_t reserved_0_3:4;
876 } s; 1118 } s;
877 struct cvmx_pciercx_cfg066_s cn52xx; 1119 struct cvmx_pciercx_cfg066_cn52xx {
878 struct cvmx_pciercx_cfg066_s cn52xxp1; 1120 uint32_t reserved_21_31:11;
879 struct cvmx_pciercx_cfg066_s cn56xx; 1121 uint32_t urem:1;
880 struct cvmx_pciercx_cfg066_s cn56xxp1; 1122 uint32_t ecrcem:1;
881 struct cvmx_pciercx_cfg066_s cn63xx; 1123 uint32_t mtlpm:1;
882 struct cvmx_pciercx_cfg066_s cn63xxp1; 1124 uint32_t rom:1;
1125 uint32_t ucm:1;
1126 uint32_t cam:1;
1127 uint32_t ctm:1;
1128 uint32_t fcpem:1;
1129 uint32_t ptlpm:1;
1130 uint32_t reserved_6_11:6;
1131 uint32_t sdem:1;
1132 uint32_t dlpem:1;
1133 uint32_t reserved_0_3:4;
1134 } cn52xx;
1135 struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
1136 struct cvmx_pciercx_cfg066_cn52xx cn56xx;
1137 struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
1138 struct cvmx_pciercx_cfg066_s cn61xx;
1139 struct cvmx_pciercx_cfg066_cn52xx cn63xx;
1140 struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
1141 struct cvmx_pciercx_cfg066_s cn66xx;
1142 struct cvmx_pciercx_cfg066_s cn68xx;
1143 struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
883}; 1144};
884 1145
885union cvmx_pciercx_cfg067 { 1146union cvmx_pciercx_cfg067 {
886 uint32_t u32; 1147 uint32_t u32;
887 struct cvmx_pciercx_cfg067_s { 1148 struct cvmx_pciercx_cfg067_s {
888 uint32_t reserved_21_31:11; 1149 uint32_t reserved_25_31:7;
1150 uint32_t uatombs:1;
1151 uint32_t reserved_21_23:3;
889 uint32_t ures:1; 1152 uint32_t ures:1;
890 uint32_t ecrces:1; 1153 uint32_t ecrces:1;
891 uint32_t mtlps:1; 1154 uint32_t mtlps:1;
@@ -900,12 +1163,31 @@ union cvmx_pciercx_cfg067 {
900 uint32_t dlpes:1; 1163 uint32_t dlpes:1;
901 uint32_t reserved_0_3:4; 1164 uint32_t reserved_0_3:4;
902 } s; 1165 } s;
903 struct cvmx_pciercx_cfg067_s cn52xx; 1166 struct cvmx_pciercx_cfg067_cn52xx {
904 struct cvmx_pciercx_cfg067_s cn52xxp1; 1167 uint32_t reserved_21_31:11;
905 struct cvmx_pciercx_cfg067_s cn56xx; 1168 uint32_t ures:1;
906 struct cvmx_pciercx_cfg067_s cn56xxp1; 1169 uint32_t ecrces:1;
907 struct cvmx_pciercx_cfg067_s cn63xx; 1170 uint32_t mtlps:1;
908 struct cvmx_pciercx_cfg067_s cn63xxp1; 1171 uint32_t ros:1;
1172 uint32_t ucs:1;
1173 uint32_t cas:1;
1174 uint32_t cts:1;
1175 uint32_t fcpes:1;
1176 uint32_t ptlps:1;
1177 uint32_t reserved_6_11:6;
1178 uint32_t sdes:1;
1179 uint32_t dlpes:1;
1180 uint32_t reserved_0_3:4;
1181 } cn52xx;
1182 struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
1183 struct cvmx_pciercx_cfg067_cn52xx cn56xx;
1184 struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
1185 struct cvmx_pciercx_cfg067_s cn61xx;
1186 struct cvmx_pciercx_cfg067_cn52xx cn63xx;
1187 struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
1188 struct cvmx_pciercx_cfg067_s cn66xx;
1189 struct cvmx_pciercx_cfg067_s cn68xx;
1190 struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
909}; 1191};
910 1192
911union cvmx_pciercx_cfg068 { 1193union cvmx_pciercx_cfg068 {
@@ -925,8 +1207,12 @@ union cvmx_pciercx_cfg068 {
925 struct cvmx_pciercx_cfg068_s cn52xxp1; 1207 struct cvmx_pciercx_cfg068_s cn52xxp1;
926 struct cvmx_pciercx_cfg068_s cn56xx; 1208 struct cvmx_pciercx_cfg068_s cn56xx;
927 struct cvmx_pciercx_cfg068_s cn56xxp1; 1209 struct cvmx_pciercx_cfg068_s cn56xxp1;
1210 struct cvmx_pciercx_cfg068_s cn61xx;
928 struct cvmx_pciercx_cfg068_s cn63xx; 1211 struct cvmx_pciercx_cfg068_s cn63xx;
929 struct cvmx_pciercx_cfg068_s cn63xxp1; 1212 struct cvmx_pciercx_cfg068_s cn63xxp1;
1213 struct cvmx_pciercx_cfg068_s cn66xx;
1214 struct cvmx_pciercx_cfg068_s cn68xx;
1215 struct cvmx_pciercx_cfg068_s cn68xxp1;
930}; 1216};
931 1217
932union cvmx_pciercx_cfg069 { 1218union cvmx_pciercx_cfg069 {
@@ -946,8 +1232,12 @@ union cvmx_pciercx_cfg069 {
946 struct cvmx_pciercx_cfg069_s cn52xxp1; 1232 struct cvmx_pciercx_cfg069_s cn52xxp1;
947 struct cvmx_pciercx_cfg069_s cn56xx; 1233 struct cvmx_pciercx_cfg069_s cn56xx;
948 struct cvmx_pciercx_cfg069_s cn56xxp1; 1234 struct cvmx_pciercx_cfg069_s cn56xxp1;
1235 struct cvmx_pciercx_cfg069_s cn61xx;
949 struct cvmx_pciercx_cfg069_s cn63xx; 1236 struct cvmx_pciercx_cfg069_s cn63xx;
950 struct cvmx_pciercx_cfg069_s cn63xxp1; 1237 struct cvmx_pciercx_cfg069_s cn63xxp1;
1238 struct cvmx_pciercx_cfg069_s cn66xx;
1239 struct cvmx_pciercx_cfg069_s cn68xx;
1240 struct cvmx_pciercx_cfg069_s cn68xxp1;
951}; 1241};
952 1242
953union cvmx_pciercx_cfg070 { 1243union cvmx_pciercx_cfg070 {
@@ -964,8 +1254,12 @@ union cvmx_pciercx_cfg070 {
964 struct cvmx_pciercx_cfg070_s cn52xxp1; 1254 struct cvmx_pciercx_cfg070_s cn52xxp1;
965 struct cvmx_pciercx_cfg070_s cn56xx; 1255 struct cvmx_pciercx_cfg070_s cn56xx;
966 struct cvmx_pciercx_cfg070_s cn56xxp1; 1256 struct cvmx_pciercx_cfg070_s cn56xxp1;
1257 struct cvmx_pciercx_cfg070_s cn61xx;
967 struct cvmx_pciercx_cfg070_s cn63xx; 1258 struct cvmx_pciercx_cfg070_s cn63xx;
968 struct cvmx_pciercx_cfg070_s cn63xxp1; 1259 struct cvmx_pciercx_cfg070_s cn63xxp1;
1260 struct cvmx_pciercx_cfg070_s cn66xx;
1261 struct cvmx_pciercx_cfg070_s cn68xx;
1262 struct cvmx_pciercx_cfg070_s cn68xxp1;
969}; 1263};
970 1264
971union cvmx_pciercx_cfg071 { 1265union cvmx_pciercx_cfg071 {
@@ -977,8 +1271,12 @@ union cvmx_pciercx_cfg071 {
977 struct cvmx_pciercx_cfg071_s cn52xxp1; 1271 struct cvmx_pciercx_cfg071_s cn52xxp1;
978 struct cvmx_pciercx_cfg071_s cn56xx; 1272 struct cvmx_pciercx_cfg071_s cn56xx;
979 struct cvmx_pciercx_cfg071_s cn56xxp1; 1273 struct cvmx_pciercx_cfg071_s cn56xxp1;
1274 struct cvmx_pciercx_cfg071_s cn61xx;
980 struct cvmx_pciercx_cfg071_s cn63xx; 1275 struct cvmx_pciercx_cfg071_s cn63xx;
981 struct cvmx_pciercx_cfg071_s cn63xxp1; 1276 struct cvmx_pciercx_cfg071_s cn63xxp1;
1277 struct cvmx_pciercx_cfg071_s cn66xx;
1278 struct cvmx_pciercx_cfg071_s cn68xx;
1279 struct cvmx_pciercx_cfg071_s cn68xxp1;
982}; 1280};
983 1281
984union cvmx_pciercx_cfg072 { 1282union cvmx_pciercx_cfg072 {
@@ -990,8 +1288,12 @@ union cvmx_pciercx_cfg072 {
990 struct cvmx_pciercx_cfg072_s cn52xxp1; 1288 struct cvmx_pciercx_cfg072_s cn52xxp1;
991 struct cvmx_pciercx_cfg072_s cn56xx; 1289 struct cvmx_pciercx_cfg072_s cn56xx;
992 struct cvmx_pciercx_cfg072_s cn56xxp1; 1290 struct cvmx_pciercx_cfg072_s cn56xxp1;
1291 struct cvmx_pciercx_cfg072_s cn61xx;
993 struct cvmx_pciercx_cfg072_s cn63xx; 1292 struct cvmx_pciercx_cfg072_s cn63xx;
994 struct cvmx_pciercx_cfg072_s cn63xxp1; 1293 struct cvmx_pciercx_cfg072_s cn63xxp1;
1294 struct cvmx_pciercx_cfg072_s cn66xx;
1295 struct cvmx_pciercx_cfg072_s cn68xx;
1296 struct cvmx_pciercx_cfg072_s cn68xxp1;
995}; 1297};
996 1298
997union cvmx_pciercx_cfg073 { 1299union cvmx_pciercx_cfg073 {
@@ -1003,8 +1305,12 @@ union cvmx_pciercx_cfg073 {
1003 struct cvmx_pciercx_cfg073_s cn52xxp1; 1305 struct cvmx_pciercx_cfg073_s cn52xxp1;
1004 struct cvmx_pciercx_cfg073_s cn56xx; 1306 struct cvmx_pciercx_cfg073_s cn56xx;
1005 struct cvmx_pciercx_cfg073_s cn56xxp1; 1307 struct cvmx_pciercx_cfg073_s cn56xxp1;
1308 struct cvmx_pciercx_cfg073_s cn61xx;
1006 struct cvmx_pciercx_cfg073_s cn63xx; 1309 struct cvmx_pciercx_cfg073_s cn63xx;
1007 struct cvmx_pciercx_cfg073_s cn63xxp1; 1310 struct cvmx_pciercx_cfg073_s cn63xxp1;
1311 struct cvmx_pciercx_cfg073_s cn66xx;
1312 struct cvmx_pciercx_cfg073_s cn68xx;
1313 struct cvmx_pciercx_cfg073_s cn68xxp1;
1008}; 1314};
1009 1315
1010union cvmx_pciercx_cfg074 { 1316union cvmx_pciercx_cfg074 {
@@ -1016,8 +1322,12 @@ union cvmx_pciercx_cfg074 {
1016 struct cvmx_pciercx_cfg074_s cn52xxp1; 1322 struct cvmx_pciercx_cfg074_s cn52xxp1;
1017 struct cvmx_pciercx_cfg074_s cn56xx; 1323 struct cvmx_pciercx_cfg074_s cn56xx;
1018 struct cvmx_pciercx_cfg074_s cn56xxp1; 1324 struct cvmx_pciercx_cfg074_s cn56xxp1;
1325 struct cvmx_pciercx_cfg074_s cn61xx;
1019 struct cvmx_pciercx_cfg074_s cn63xx; 1326 struct cvmx_pciercx_cfg074_s cn63xx;
1020 struct cvmx_pciercx_cfg074_s cn63xxp1; 1327 struct cvmx_pciercx_cfg074_s cn63xxp1;
1328 struct cvmx_pciercx_cfg074_s cn66xx;
1329 struct cvmx_pciercx_cfg074_s cn68xx;
1330 struct cvmx_pciercx_cfg074_s cn68xxp1;
1021}; 1331};
1022 1332
1023union cvmx_pciercx_cfg075 { 1333union cvmx_pciercx_cfg075 {
@@ -1032,8 +1342,12 @@ union cvmx_pciercx_cfg075 {
1032 struct cvmx_pciercx_cfg075_s cn52xxp1; 1342 struct cvmx_pciercx_cfg075_s cn52xxp1;
1033 struct cvmx_pciercx_cfg075_s cn56xx; 1343 struct cvmx_pciercx_cfg075_s cn56xx;
1034 struct cvmx_pciercx_cfg075_s cn56xxp1; 1344 struct cvmx_pciercx_cfg075_s cn56xxp1;
1345 struct cvmx_pciercx_cfg075_s cn61xx;
1035 struct cvmx_pciercx_cfg075_s cn63xx; 1346 struct cvmx_pciercx_cfg075_s cn63xx;
1036 struct cvmx_pciercx_cfg075_s cn63xxp1; 1347 struct cvmx_pciercx_cfg075_s cn63xxp1;
1348 struct cvmx_pciercx_cfg075_s cn66xx;
1349 struct cvmx_pciercx_cfg075_s cn68xx;
1350 struct cvmx_pciercx_cfg075_s cn68xxp1;
1037}; 1351};
1038 1352
1039union cvmx_pciercx_cfg076 { 1353union cvmx_pciercx_cfg076 {
@@ -1053,8 +1367,12 @@ union cvmx_pciercx_cfg076 {
1053 struct cvmx_pciercx_cfg076_s cn52xxp1; 1367 struct cvmx_pciercx_cfg076_s cn52xxp1;
1054 struct cvmx_pciercx_cfg076_s cn56xx; 1368 struct cvmx_pciercx_cfg076_s cn56xx;
1055 struct cvmx_pciercx_cfg076_s cn56xxp1; 1369 struct cvmx_pciercx_cfg076_s cn56xxp1;
1370 struct cvmx_pciercx_cfg076_s cn61xx;
1056 struct cvmx_pciercx_cfg076_s cn63xx; 1371 struct cvmx_pciercx_cfg076_s cn63xx;
1057 struct cvmx_pciercx_cfg076_s cn63xxp1; 1372 struct cvmx_pciercx_cfg076_s cn63xxp1;
1373 struct cvmx_pciercx_cfg076_s cn66xx;
1374 struct cvmx_pciercx_cfg076_s cn68xx;
1375 struct cvmx_pciercx_cfg076_s cn68xxp1;
1058}; 1376};
1059 1377
1060union cvmx_pciercx_cfg077 { 1378union cvmx_pciercx_cfg077 {
@@ -1067,8 +1385,12 @@ union cvmx_pciercx_cfg077 {
1067 struct cvmx_pciercx_cfg077_s cn52xxp1; 1385 struct cvmx_pciercx_cfg077_s cn52xxp1;
1068 struct cvmx_pciercx_cfg077_s cn56xx; 1386 struct cvmx_pciercx_cfg077_s cn56xx;
1069 struct cvmx_pciercx_cfg077_s cn56xxp1; 1387 struct cvmx_pciercx_cfg077_s cn56xxp1;
1388 struct cvmx_pciercx_cfg077_s cn61xx;
1070 struct cvmx_pciercx_cfg077_s cn63xx; 1389 struct cvmx_pciercx_cfg077_s cn63xx;
1071 struct cvmx_pciercx_cfg077_s cn63xxp1; 1390 struct cvmx_pciercx_cfg077_s cn63xxp1;
1391 struct cvmx_pciercx_cfg077_s cn66xx;
1392 struct cvmx_pciercx_cfg077_s cn68xx;
1393 struct cvmx_pciercx_cfg077_s cn68xxp1;
1072}; 1394};
1073 1395
1074union cvmx_pciercx_cfg448 { 1396union cvmx_pciercx_cfg448 {
@@ -1081,8 +1403,12 @@ union cvmx_pciercx_cfg448 {
1081 struct cvmx_pciercx_cfg448_s cn52xxp1; 1403 struct cvmx_pciercx_cfg448_s cn52xxp1;
1082 struct cvmx_pciercx_cfg448_s cn56xx; 1404 struct cvmx_pciercx_cfg448_s cn56xx;
1083 struct cvmx_pciercx_cfg448_s cn56xxp1; 1405 struct cvmx_pciercx_cfg448_s cn56xxp1;
1406 struct cvmx_pciercx_cfg448_s cn61xx;
1084 struct cvmx_pciercx_cfg448_s cn63xx; 1407 struct cvmx_pciercx_cfg448_s cn63xx;
1085 struct cvmx_pciercx_cfg448_s cn63xxp1; 1408 struct cvmx_pciercx_cfg448_s cn63xxp1;
1409 struct cvmx_pciercx_cfg448_s cn66xx;
1410 struct cvmx_pciercx_cfg448_s cn68xx;
1411 struct cvmx_pciercx_cfg448_s cn68xxp1;
1086}; 1412};
1087 1413
1088union cvmx_pciercx_cfg449 { 1414union cvmx_pciercx_cfg449 {
@@ -1094,8 +1420,12 @@ union cvmx_pciercx_cfg449 {
1094 struct cvmx_pciercx_cfg449_s cn52xxp1; 1420 struct cvmx_pciercx_cfg449_s cn52xxp1;
1095 struct cvmx_pciercx_cfg449_s cn56xx; 1421 struct cvmx_pciercx_cfg449_s cn56xx;
1096 struct cvmx_pciercx_cfg449_s cn56xxp1; 1422 struct cvmx_pciercx_cfg449_s cn56xxp1;
1423 struct cvmx_pciercx_cfg449_s cn61xx;
1097 struct cvmx_pciercx_cfg449_s cn63xx; 1424 struct cvmx_pciercx_cfg449_s cn63xx;
1098 struct cvmx_pciercx_cfg449_s cn63xxp1; 1425 struct cvmx_pciercx_cfg449_s cn63xxp1;
1426 struct cvmx_pciercx_cfg449_s cn66xx;
1427 struct cvmx_pciercx_cfg449_s cn68xx;
1428 struct cvmx_pciercx_cfg449_s cn68xxp1;
1099}; 1429};
1100 1430
1101union cvmx_pciercx_cfg450 { 1431union cvmx_pciercx_cfg450 {
@@ -1112,26 +1442,42 @@ union cvmx_pciercx_cfg450 {
1112 struct cvmx_pciercx_cfg450_s cn52xxp1; 1442 struct cvmx_pciercx_cfg450_s cn52xxp1;
1113 struct cvmx_pciercx_cfg450_s cn56xx; 1443 struct cvmx_pciercx_cfg450_s cn56xx;
1114 struct cvmx_pciercx_cfg450_s cn56xxp1; 1444 struct cvmx_pciercx_cfg450_s cn56xxp1;
1445 struct cvmx_pciercx_cfg450_s cn61xx;
1115 struct cvmx_pciercx_cfg450_s cn63xx; 1446 struct cvmx_pciercx_cfg450_s cn63xx;
1116 struct cvmx_pciercx_cfg450_s cn63xxp1; 1447 struct cvmx_pciercx_cfg450_s cn63xxp1;
1448 struct cvmx_pciercx_cfg450_s cn66xx;
1449 struct cvmx_pciercx_cfg450_s cn68xx;
1450 struct cvmx_pciercx_cfg450_s cn68xxp1;
1117}; 1451};
1118 1452
1119union cvmx_pciercx_cfg451 { 1453union cvmx_pciercx_cfg451 {
1120 uint32_t u32; 1454 uint32_t u32;
1121 struct cvmx_pciercx_cfg451_s { 1455 struct cvmx_pciercx_cfg451_s {
1122 uint32_t reserved_30_31:2; 1456 uint32_t reserved_31_31:1;
1457 uint32_t easpml1:1;
1123 uint32_t l1el:3; 1458 uint32_t l1el:3;
1124 uint32_t l0el:3; 1459 uint32_t l0el:3;
1125 uint32_t n_fts_cc:8; 1460 uint32_t n_fts_cc:8;
1126 uint32_t n_fts:8; 1461 uint32_t n_fts:8;
1127 uint32_t ack_freq:8; 1462 uint32_t ack_freq:8;
1128 } s; 1463 } s;
1129 struct cvmx_pciercx_cfg451_s cn52xx; 1464 struct cvmx_pciercx_cfg451_cn52xx {
1130 struct cvmx_pciercx_cfg451_s cn52xxp1; 1465 uint32_t reserved_30_31:2;
1131 struct cvmx_pciercx_cfg451_s cn56xx; 1466 uint32_t l1el:3;
1132 struct cvmx_pciercx_cfg451_s cn56xxp1; 1467 uint32_t l0el:3;
1133 struct cvmx_pciercx_cfg451_s cn63xx; 1468 uint32_t n_fts_cc:8;
1134 struct cvmx_pciercx_cfg451_s cn63xxp1; 1469 uint32_t n_fts:8;
1470 uint32_t ack_freq:8;
1471 } cn52xx;
1472 struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
1473 struct cvmx_pciercx_cfg451_cn52xx cn56xx;
1474 struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
1475 struct cvmx_pciercx_cfg451_s cn61xx;
1476 struct cvmx_pciercx_cfg451_cn52xx cn63xx;
1477 struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
1478 struct cvmx_pciercx_cfg451_s cn66xx;
1479 struct cvmx_pciercx_cfg451_s cn68xx;
1480 struct cvmx_pciercx_cfg451_s cn68xxp1;
1135}; 1481};
1136 1482
1137union cvmx_pciercx_cfg452 { 1483union cvmx_pciercx_cfg452 {
@@ -1155,8 +1501,24 @@ union cvmx_pciercx_cfg452 {
1155 struct cvmx_pciercx_cfg452_s cn52xxp1; 1501 struct cvmx_pciercx_cfg452_s cn52xxp1;
1156 struct cvmx_pciercx_cfg452_s cn56xx; 1502 struct cvmx_pciercx_cfg452_s cn56xx;
1157 struct cvmx_pciercx_cfg452_s cn56xxp1; 1503 struct cvmx_pciercx_cfg452_s cn56xxp1;
1504 struct cvmx_pciercx_cfg452_cn61xx {
1505 uint32_t reserved_22_31:10;
1506 uint32_t lme:6;
1507 uint32_t reserved_8_15:8;
1508 uint32_t flm:1;
1509 uint32_t reserved_6_6:1;
1510 uint32_t dllle:1;
1511 uint32_t reserved_4_4:1;
1512 uint32_t ra:1;
1513 uint32_t le:1;
1514 uint32_t sd:1;
1515 uint32_t omr:1;
1516 } cn61xx;
1158 struct cvmx_pciercx_cfg452_s cn63xx; 1517 struct cvmx_pciercx_cfg452_s cn63xx;
1159 struct cvmx_pciercx_cfg452_s cn63xxp1; 1518 struct cvmx_pciercx_cfg452_s cn63xxp1;
1519 struct cvmx_pciercx_cfg452_cn61xx cn66xx;
1520 struct cvmx_pciercx_cfg452_cn61xx cn68xx;
1521 struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
1160}; 1522};
1161 1523
1162union cvmx_pciercx_cfg453 { 1524union cvmx_pciercx_cfg453 {
@@ -1172,13 +1534,26 @@ union cvmx_pciercx_cfg453 {
1172 struct cvmx_pciercx_cfg453_s cn52xxp1; 1534 struct cvmx_pciercx_cfg453_s cn52xxp1;
1173 struct cvmx_pciercx_cfg453_s cn56xx; 1535 struct cvmx_pciercx_cfg453_s cn56xx;
1174 struct cvmx_pciercx_cfg453_s cn56xxp1; 1536 struct cvmx_pciercx_cfg453_s cn56xxp1;
1537 struct cvmx_pciercx_cfg453_s cn61xx;
1175 struct cvmx_pciercx_cfg453_s cn63xx; 1538 struct cvmx_pciercx_cfg453_s cn63xx;
1176 struct cvmx_pciercx_cfg453_s cn63xxp1; 1539 struct cvmx_pciercx_cfg453_s cn63xxp1;
1540 struct cvmx_pciercx_cfg453_s cn66xx;
1541 struct cvmx_pciercx_cfg453_s cn68xx;
1542 struct cvmx_pciercx_cfg453_s cn68xxp1;
1177}; 1543};
1178 1544
1179union cvmx_pciercx_cfg454 { 1545union cvmx_pciercx_cfg454 {
1180 uint32_t u32; 1546 uint32_t u32;
1181 struct cvmx_pciercx_cfg454_s { 1547 struct cvmx_pciercx_cfg454_s {
1548 uint32_t cx_nfunc:3;
1549 uint32_t tmfcwt:5;
1550 uint32_t tmanlt:5;
1551 uint32_t tmrt:5;
1552 uint32_t reserved_11_13:3;
1553 uint32_t nskps:3;
1554 uint32_t reserved_0_7:8;
1555 } s;
1556 struct cvmx_pciercx_cfg454_cn52xx {
1182 uint32_t reserved_29_31:3; 1557 uint32_t reserved_29_31:3;
1183 uint32_t tmfcwt:5; 1558 uint32_t tmfcwt:5;
1184 uint32_t tmanlt:5; 1559 uint32_t tmanlt:5;
@@ -1187,13 +1562,23 @@ union cvmx_pciercx_cfg454 {
1187 uint32_t nskps:3; 1562 uint32_t nskps:3;
1188 uint32_t reserved_4_7:4; 1563 uint32_t reserved_4_7:4;
1189 uint32_t ntss:4; 1564 uint32_t ntss:4;
1190 } s; 1565 } cn52xx;
1191 struct cvmx_pciercx_cfg454_s cn52xx; 1566 struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
1192 struct cvmx_pciercx_cfg454_s cn52xxp1; 1567 struct cvmx_pciercx_cfg454_cn52xx cn56xx;
1193 struct cvmx_pciercx_cfg454_s cn56xx; 1568 struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
1194 struct cvmx_pciercx_cfg454_s cn56xxp1; 1569 struct cvmx_pciercx_cfg454_cn61xx {
1195 struct cvmx_pciercx_cfg454_s cn63xx; 1570 uint32_t cx_nfunc:3;
1196 struct cvmx_pciercx_cfg454_s cn63xxp1; 1571 uint32_t tmfcwt:5;
1572 uint32_t tmanlt:5;
1573 uint32_t tmrt:5;
1574 uint32_t reserved_8_13:6;
1575 uint32_t mfuncn:8;
1576 } cn61xx;
1577 struct cvmx_pciercx_cfg454_cn52xx cn63xx;
1578 struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
1579 struct cvmx_pciercx_cfg454_cn61xx cn66xx;
1580 struct cvmx_pciercx_cfg454_cn61xx cn68xx;
1581 struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
1197}; 1582};
1198 1583
1199union cvmx_pciercx_cfg455 { 1584union cvmx_pciercx_cfg455 {
@@ -1223,23 +1608,37 @@ union cvmx_pciercx_cfg455 {
1223 struct cvmx_pciercx_cfg455_s cn52xxp1; 1608 struct cvmx_pciercx_cfg455_s cn52xxp1;
1224 struct cvmx_pciercx_cfg455_s cn56xx; 1609 struct cvmx_pciercx_cfg455_s cn56xx;
1225 struct cvmx_pciercx_cfg455_s cn56xxp1; 1610 struct cvmx_pciercx_cfg455_s cn56xxp1;
1611 struct cvmx_pciercx_cfg455_s cn61xx;
1226 struct cvmx_pciercx_cfg455_s cn63xx; 1612 struct cvmx_pciercx_cfg455_s cn63xx;
1227 struct cvmx_pciercx_cfg455_s cn63xxp1; 1613 struct cvmx_pciercx_cfg455_s cn63xxp1;
1614 struct cvmx_pciercx_cfg455_s cn66xx;
1615 struct cvmx_pciercx_cfg455_s cn68xx;
1616 struct cvmx_pciercx_cfg455_s cn68xxp1;
1228}; 1617};
1229 1618
1230union cvmx_pciercx_cfg456 { 1619union cvmx_pciercx_cfg456 {
1231 uint32_t u32; 1620 uint32_t u32;
1232 struct cvmx_pciercx_cfg456_s { 1621 struct cvmx_pciercx_cfg456_s {
1233 uint32_t reserved_2_31:30; 1622 uint32_t reserved_4_31:28;
1623 uint32_t m_handle_flush:1;
1624 uint32_t m_dabort_4ucpl:1;
1234 uint32_t m_vend1_drp:1; 1625 uint32_t m_vend1_drp:1;
1235 uint32_t m_vend0_drp:1; 1626 uint32_t m_vend0_drp:1;
1236 } s; 1627 } s;
1237 struct cvmx_pciercx_cfg456_s cn52xx; 1628 struct cvmx_pciercx_cfg456_cn52xx {
1238 struct cvmx_pciercx_cfg456_s cn52xxp1; 1629 uint32_t reserved_2_31:30;
1239 struct cvmx_pciercx_cfg456_s cn56xx; 1630 uint32_t m_vend1_drp:1;
1240 struct cvmx_pciercx_cfg456_s cn56xxp1; 1631 uint32_t m_vend0_drp:1;
1241 struct cvmx_pciercx_cfg456_s cn63xx; 1632 } cn52xx;
1242 struct cvmx_pciercx_cfg456_s cn63xxp1; 1633 struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
1634 struct cvmx_pciercx_cfg456_cn52xx cn56xx;
1635 struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
1636 struct cvmx_pciercx_cfg456_s cn61xx;
1637 struct cvmx_pciercx_cfg456_cn52xx cn63xx;
1638 struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
1639 struct cvmx_pciercx_cfg456_s cn66xx;
1640 struct cvmx_pciercx_cfg456_s cn68xx;
1641 struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
1243}; 1642};
1244 1643
1245union cvmx_pciercx_cfg458 { 1644union cvmx_pciercx_cfg458 {
@@ -1251,8 +1650,12 @@ union cvmx_pciercx_cfg458 {
1251 struct cvmx_pciercx_cfg458_s cn52xxp1; 1650 struct cvmx_pciercx_cfg458_s cn52xxp1;
1252 struct cvmx_pciercx_cfg458_s cn56xx; 1651 struct cvmx_pciercx_cfg458_s cn56xx;
1253 struct cvmx_pciercx_cfg458_s cn56xxp1; 1652 struct cvmx_pciercx_cfg458_s cn56xxp1;
1653 struct cvmx_pciercx_cfg458_s cn61xx;
1254 struct cvmx_pciercx_cfg458_s cn63xx; 1654 struct cvmx_pciercx_cfg458_s cn63xx;
1255 struct cvmx_pciercx_cfg458_s cn63xxp1; 1655 struct cvmx_pciercx_cfg458_s cn63xxp1;
1656 struct cvmx_pciercx_cfg458_s cn66xx;
1657 struct cvmx_pciercx_cfg458_s cn68xx;
1658 struct cvmx_pciercx_cfg458_s cn68xxp1;
1256}; 1659};
1257 1660
1258union cvmx_pciercx_cfg459 { 1661union cvmx_pciercx_cfg459 {
@@ -1264,8 +1667,12 @@ union cvmx_pciercx_cfg459 {
1264 struct cvmx_pciercx_cfg459_s cn52xxp1; 1667 struct cvmx_pciercx_cfg459_s cn52xxp1;
1265 struct cvmx_pciercx_cfg459_s cn56xx; 1668 struct cvmx_pciercx_cfg459_s cn56xx;
1266 struct cvmx_pciercx_cfg459_s cn56xxp1; 1669 struct cvmx_pciercx_cfg459_s cn56xxp1;
1670 struct cvmx_pciercx_cfg459_s cn61xx;
1267 struct cvmx_pciercx_cfg459_s cn63xx; 1671 struct cvmx_pciercx_cfg459_s cn63xx;
1268 struct cvmx_pciercx_cfg459_s cn63xxp1; 1672 struct cvmx_pciercx_cfg459_s cn63xxp1;
1673 struct cvmx_pciercx_cfg459_s cn66xx;
1674 struct cvmx_pciercx_cfg459_s cn68xx;
1675 struct cvmx_pciercx_cfg459_s cn68xxp1;
1269}; 1676};
1270 1677
1271union cvmx_pciercx_cfg460 { 1678union cvmx_pciercx_cfg460 {
@@ -1279,8 +1686,12 @@ union cvmx_pciercx_cfg460 {
1279 struct cvmx_pciercx_cfg460_s cn52xxp1; 1686 struct cvmx_pciercx_cfg460_s cn52xxp1;
1280 struct cvmx_pciercx_cfg460_s cn56xx; 1687 struct cvmx_pciercx_cfg460_s cn56xx;
1281 struct cvmx_pciercx_cfg460_s cn56xxp1; 1688 struct cvmx_pciercx_cfg460_s cn56xxp1;
1689 struct cvmx_pciercx_cfg460_s cn61xx;
1282 struct cvmx_pciercx_cfg460_s cn63xx; 1690 struct cvmx_pciercx_cfg460_s cn63xx;
1283 struct cvmx_pciercx_cfg460_s cn63xxp1; 1691 struct cvmx_pciercx_cfg460_s cn63xxp1;
1692 struct cvmx_pciercx_cfg460_s cn66xx;
1693 struct cvmx_pciercx_cfg460_s cn68xx;
1694 struct cvmx_pciercx_cfg460_s cn68xxp1;
1284}; 1695};
1285 1696
1286union cvmx_pciercx_cfg461 { 1697union cvmx_pciercx_cfg461 {
@@ -1294,8 +1705,12 @@ union cvmx_pciercx_cfg461 {
1294 struct cvmx_pciercx_cfg461_s cn52xxp1; 1705 struct cvmx_pciercx_cfg461_s cn52xxp1;
1295 struct cvmx_pciercx_cfg461_s cn56xx; 1706 struct cvmx_pciercx_cfg461_s cn56xx;
1296 struct cvmx_pciercx_cfg461_s cn56xxp1; 1707 struct cvmx_pciercx_cfg461_s cn56xxp1;
1708 struct cvmx_pciercx_cfg461_s cn61xx;
1297 struct cvmx_pciercx_cfg461_s cn63xx; 1709 struct cvmx_pciercx_cfg461_s cn63xx;
1298 struct cvmx_pciercx_cfg461_s cn63xxp1; 1710 struct cvmx_pciercx_cfg461_s cn63xxp1;
1711 struct cvmx_pciercx_cfg461_s cn66xx;
1712 struct cvmx_pciercx_cfg461_s cn68xx;
1713 struct cvmx_pciercx_cfg461_s cn68xxp1;
1299}; 1714};
1300 1715
1301union cvmx_pciercx_cfg462 { 1716union cvmx_pciercx_cfg462 {
@@ -1309,8 +1724,12 @@ union cvmx_pciercx_cfg462 {
1309 struct cvmx_pciercx_cfg462_s cn52xxp1; 1724 struct cvmx_pciercx_cfg462_s cn52xxp1;
1310 struct cvmx_pciercx_cfg462_s cn56xx; 1725 struct cvmx_pciercx_cfg462_s cn56xx;
1311 struct cvmx_pciercx_cfg462_s cn56xxp1; 1726 struct cvmx_pciercx_cfg462_s cn56xxp1;
1727 struct cvmx_pciercx_cfg462_s cn61xx;
1312 struct cvmx_pciercx_cfg462_s cn63xx; 1728 struct cvmx_pciercx_cfg462_s cn63xx;
1313 struct cvmx_pciercx_cfg462_s cn63xxp1; 1729 struct cvmx_pciercx_cfg462_s cn63xxp1;
1730 struct cvmx_pciercx_cfg462_s cn66xx;
1731 struct cvmx_pciercx_cfg462_s cn68xx;
1732 struct cvmx_pciercx_cfg462_s cn68xxp1;
1314}; 1733};
1315 1734
1316union cvmx_pciercx_cfg463 { 1735union cvmx_pciercx_cfg463 {
@@ -1325,8 +1744,12 @@ union cvmx_pciercx_cfg463 {
1325 struct cvmx_pciercx_cfg463_s cn52xxp1; 1744 struct cvmx_pciercx_cfg463_s cn52xxp1;
1326 struct cvmx_pciercx_cfg463_s cn56xx; 1745 struct cvmx_pciercx_cfg463_s cn56xx;
1327 struct cvmx_pciercx_cfg463_s cn56xxp1; 1746 struct cvmx_pciercx_cfg463_s cn56xxp1;
1747 struct cvmx_pciercx_cfg463_s cn61xx;
1328 struct cvmx_pciercx_cfg463_s cn63xx; 1748 struct cvmx_pciercx_cfg463_s cn63xx;
1329 struct cvmx_pciercx_cfg463_s cn63xxp1; 1749 struct cvmx_pciercx_cfg463_s cn63xxp1;
1750 struct cvmx_pciercx_cfg463_s cn66xx;
1751 struct cvmx_pciercx_cfg463_s cn68xx;
1752 struct cvmx_pciercx_cfg463_s cn68xxp1;
1330}; 1753};
1331 1754
1332union cvmx_pciercx_cfg464 { 1755union cvmx_pciercx_cfg464 {
@@ -1341,8 +1764,12 @@ union cvmx_pciercx_cfg464 {
1341 struct cvmx_pciercx_cfg464_s cn52xxp1; 1764 struct cvmx_pciercx_cfg464_s cn52xxp1;
1342 struct cvmx_pciercx_cfg464_s cn56xx; 1765 struct cvmx_pciercx_cfg464_s cn56xx;
1343 struct cvmx_pciercx_cfg464_s cn56xxp1; 1766 struct cvmx_pciercx_cfg464_s cn56xxp1;
1767 struct cvmx_pciercx_cfg464_s cn61xx;
1344 struct cvmx_pciercx_cfg464_s cn63xx; 1768 struct cvmx_pciercx_cfg464_s cn63xx;
1345 struct cvmx_pciercx_cfg464_s cn63xxp1; 1769 struct cvmx_pciercx_cfg464_s cn63xxp1;
1770 struct cvmx_pciercx_cfg464_s cn66xx;
1771 struct cvmx_pciercx_cfg464_s cn68xx;
1772 struct cvmx_pciercx_cfg464_s cn68xxp1;
1346}; 1773};
1347 1774
1348union cvmx_pciercx_cfg465 { 1775union cvmx_pciercx_cfg465 {
@@ -1357,8 +1784,12 @@ union cvmx_pciercx_cfg465 {
1357 struct cvmx_pciercx_cfg465_s cn52xxp1; 1784 struct cvmx_pciercx_cfg465_s cn52xxp1;
1358 struct cvmx_pciercx_cfg465_s cn56xx; 1785 struct cvmx_pciercx_cfg465_s cn56xx;
1359 struct cvmx_pciercx_cfg465_s cn56xxp1; 1786 struct cvmx_pciercx_cfg465_s cn56xxp1;
1787 struct cvmx_pciercx_cfg465_s cn61xx;
1360 struct cvmx_pciercx_cfg465_s cn63xx; 1788 struct cvmx_pciercx_cfg465_s cn63xx;
1361 struct cvmx_pciercx_cfg465_s cn63xxp1; 1789 struct cvmx_pciercx_cfg465_s cn63xxp1;
1790 struct cvmx_pciercx_cfg465_s cn66xx;
1791 struct cvmx_pciercx_cfg465_s cn68xx;
1792 struct cvmx_pciercx_cfg465_s cn68xxp1;
1362}; 1793};
1363 1794
1364union cvmx_pciercx_cfg466 { 1795union cvmx_pciercx_cfg466 {
@@ -1376,8 +1807,12 @@ union cvmx_pciercx_cfg466 {
1376 struct cvmx_pciercx_cfg466_s cn52xxp1; 1807 struct cvmx_pciercx_cfg466_s cn52xxp1;
1377 struct cvmx_pciercx_cfg466_s cn56xx; 1808 struct cvmx_pciercx_cfg466_s cn56xx;
1378 struct cvmx_pciercx_cfg466_s cn56xxp1; 1809 struct cvmx_pciercx_cfg466_s cn56xxp1;
1810 struct cvmx_pciercx_cfg466_s cn61xx;
1379 struct cvmx_pciercx_cfg466_s cn63xx; 1811 struct cvmx_pciercx_cfg466_s cn63xx;
1380 struct cvmx_pciercx_cfg466_s cn63xxp1; 1812 struct cvmx_pciercx_cfg466_s cn63xxp1;
1813 struct cvmx_pciercx_cfg466_s cn66xx;
1814 struct cvmx_pciercx_cfg466_s cn68xx;
1815 struct cvmx_pciercx_cfg466_s cn68xxp1;
1381}; 1816};
1382 1817
1383union cvmx_pciercx_cfg467 { 1818union cvmx_pciercx_cfg467 {
@@ -1393,8 +1828,12 @@ union cvmx_pciercx_cfg467 {
1393 struct cvmx_pciercx_cfg467_s cn52xxp1; 1828 struct cvmx_pciercx_cfg467_s cn52xxp1;
1394 struct cvmx_pciercx_cfg467_s cn56xx; 1829 struct cvmx_pciercx_cfg467_s cn56xx;
1395 struct cvmx_pciercx_cfg467_s cn56xxp1; 1830 struct cvmx_pciercx_cfg467_s cn56xxp1;
1831 struct cvmx_pciercx_cfg467_s cn61xx;
1396 struct cvmx_pciercx_cfg467_s cn63xx; 1832 struct cvmx_pciercx_cfg467_s cn63xx;
1397 struct cvmx_pciercx_cfg467_s cn63xxp1; 1833 struct cvmx_pciercx_cfg467_s cn63xxp1;
1834 struct cvmx_pciercx_cfg467_s cn66xx;
1835 struct cvmx_pciercx_cfg467_s cn68xx;
1836 struct cvmx_pciercx_cfg467_s cn68xxp1;
1398}; 1837};
1399 1838
1400union cvmx_pciercx_cfg468 { 1839union cvmx_pciercx_cfg468 {
@@ -1410,8 +1849,12 @@ union cvmx_pciercx_cfg468 {
1410 struct cvmx_pciercx_cfg468_s cn52xxp1; 1849 struct cvmx_pciercx_cfg468_s cn52xxp1;
1411 struct cvmx_pciercx_cfg468_s cn56xx; 1850 struct cvmx_pciercx_cfg468_s cn56xx;
1412 struct cvmx_pciercx_cfg468_s cn56xxp1; 1851 struct cvmx_pciercx_cfg468_s cn56xxp1;
1852 struct cvmx_pciercx_cfg468_s cn61xx;
1413 struct cvmx_pciercx_cfg468_s cn63xx; 1853 struct cvmx_pciercx_cfg468_s cn63xx;
1414 struct cvmx_pciercx_cfg468_s cn63xxp1; 1854 struct cvmx_pciercx_cfg468_s cn63xxp1;
1855 struct cvmx_pciercx_cfg468_s cn66xx;
1856 struct cvmx_pciercx_cfg468_s cn68xx;
1857 struct cvmx_pciercx_cfg468_s cn68xxp1;
1415}; 1858};
1416 1859
1417union cvmx_pciercx_cfg490 { 1860union cvmx_pciercx_cfg490 {
@@ -1426,8 +1869,12 @@ union cvmx_pciercx_cfg490 {
1426 struct cvmx_pciercx_cfg490_s cn52xxp1; 1869 struct cvmx_pciercx_cfg490_s cn52xxp1;
1427 struct cvmx_pciercx_cfg490_s cn56xx; 1870 struct cvmx_pciercx_cfg490_s cn56xx;
1428 struct cvmx_pciercx_cfg490_s cn56xxp1; 1871 struct cvmx_pciercx_cfg490_s cn56xxp1;
1872 struct cvmx_pciercx_cfg490_s cn61xx;
1429 struct cvmx_pciercx_cfg490_s cn63xx; 1873 struct cvmx_pciercx_cfg490_s cn63xx;
1430 struct cvmx_pciercx_cfg490_s cn63xxp1; 1874 struct cvmx_pciercx_cfg490_s cn63xxp1;
1875 struct cvmx_pciercx_cfg490_s cn66xx;
1876 struct cvmx_pciercx_cfg490_s cn68xx;
1877 struct cvmx_pciercx_cfg490_s cn68xxp1;
1431}; 1878};
1432 1879
1433union cvmx_pciercx_cfg491 { 1880union cvmx_pciercx_cfg491 {
@@ -1442,8 +1889,12 @@ union cvmx_pciercx_cfg491 {
1442 struct cvmx_pciercx_cfg491_s cn52xxp1; 1889 struct cvmx_pciercx_cfg491_s cn52xxp1;
1443 struct cvmx_pciercx_cfg491_s cn56xx; 1890 struct cvmx_pciercx_cfg491_s cn56xx;
1444 struct cvmx_pciercx_cfg491_s cn56xxp1; 1891 struct cvmx_pciercx_cfg491_s cn56xxp1;
1892 struct cvmx_pciercx_cfg491_s cn61xx;
1445 struct cvmx_pciercx_cfg491_s cn63xx; 1893 struct cvmx_pciercx_cfg491_s cn63xx;
1446 struct cvmx_pciercx_cfg491_s cn63xxp1; 1894 struct cvmx_pciercx_cfg491_s cn63xxp1;
1895 struct cvmx_pciercx_cfg491_s cn66xx;
1896 struct cvmx_pciercx_cfg491_s cn68xx;
1897 struct cvmx_pciercx_cfg491_s cn68xxp1;
1447}; 1898};
1448 1899
1449union cvmx_pciercx_cfg492 { 1900union cvmx_pciercx_cfg492 {
@@ -1458,8 +1909,12 @@ union cvmx_pciercx_cfg492 {
1458 struct cvmx_pciercx_cfg492_s cn52xxp1; 1909 struct cvmx_pciercx_cfg492_s cn52xxp1;
1459 struct cvmx_pciercx_cfg492_s cn56xx; 1910 struct cvmx_pciercx_cfg492_s cn56xx;
1460 struct cvmx_pciercx_cfg492_s cn56xxp1; 1911 struct cvmx_pciercx_cfg492_s cn56xxp1;
1912 struct cvmx_pciercx_cfg492_s cn61xx;
1461 struct cvmx_pciercx_cfg492_s cn63xx; 1913 struct cvmx_pciercx_cfg492_s cn63xx;
1462 struct cvmx_pciercx_cfg492_s cn63xxp1; 1914 struct cvmx_pciercx_cfg492_s cn63xxp1;
1915 struct cvmx_pciercx_cfg492_s cn66xx;
1916 struct cvmx_pciercx_cfg492_s cn68xx;
1917 struct cvmx_pciercx_cfg492_s cn68xxp1;
1463}; 1918};
1464 1919
1465union cvmx_pciercx_cfg515 { 1920union cvmx_pciercx_cfg515 {
@@ -1473,8 +1928,12 @@ union cvmx_pciercx_cfg515 {
1473 uint32_t le:9; 1928 uint32_t le:9;
1474 uint32_t n_fts:8; 1929 uint32_t n_fts:8;
1475 } s; 1930 } s;
1931 struct cvmx_pciercx_cfg515_s cn61xx;
1476 struct cvmx_pciercx_cfg515_s cn63xx; 1932 struct cvmx_pciercx_cfg515_s cn63xx;
1477 struct cvmx_pciercx_cfg515_s cn63xxp1; 1933 struct cvmx_pciercx_cfg515_s cn63xxp1;
1934 struct cvmx_pciercx_cfg515_s cn66xx;
1935 struct cvmx_pciercx_cfg515_s cn68xx;
1936 struct cvmx_pciercx_cfg515_s cn68xxp1;
1478}; 1937};
1479 1938
1480union cvmx_pciercx_cfg516 { 1939union cvmx_pciercx_cfg516 {
@@ -1486,8 +1945,12 @@ union cvmx_pciercx_cfg516 {
1486 struct cvmx_pciercx_cfg516_s cn52xxp1; 1945 struct cvmx_pciercx_cfg516_s cn52xxp1;
1487 struct cvmx_pciercx_cfg516_s cn56xx; 1946 struct cvmx_pciercx_cfg516_s cn56xx;
1488 struct cvmx_pciercx_cfg516_s cn56xxp1; 1947 struct cvmx_pciercx_cfg516_s cn56xxp1;
1948 struct cvmx_pciercx_cfg516_s cn61xx;
1489 struct cvmx_pciercx_cfg516_s cn63xx; 1949 struct cvmx_pciercx_cfg516_s cn63xx;
1490 struct cvmx_pciercx_cfg516_s cn63xxp1; 1950 struct cvmx_pciercx_cfg516_s cn63xxp1;
1951 struct cvmx_pciercx_cfg516_s cn66xx;
1952 struct cvmx_pciercx_cfg516_s cn68xx;
1953 struct cvmx_pciercx_cfg516_s cn68xxp1;
1491}; 1954};
1492 1955
1493union cvmx_pciercx_cfg517 { 1956union cvmx_pciercx_cfg517 {
@@ -1499,8 +1962,12 @@ union cvmx_pciercx_cfg517 {
1499 struct cvmx_pciercx_cfg517_s cn52xxp1; 1962 struct cvmx_pciercx_cfg517_s cn52xxp1;
1500 struct cvmx_pciercx_cfg517_s cn56xx; 1963 struct cvmx_pciercx_cfg517_s cn56xx;
1501 struct cvmx_pciercx_cfg517_s cn56xxp1; 1964 struct cvmx_pciercx_cfg517_s cn56xxp1;
1965 struct cvmx_pciercx_cfg517_s cn61xx;
1502 struct cvmx_pciercx_cfg517_s cn63xx; 1966 struct cvmx_pciercx_cfg517_s cn63xx;
1503 struct cvmx_pciercx_cfg517_s cn63xxp1; 1967 struct cvmx_pciercx_cfg517_s cn63xxp1;
1968 struct cvmx_pciercx_cfg517_s cn66xx;
1969 struct cvmx_pciercx_cfg517_s cn68xx;
1970 struct cvmx_pciercx_cfg517_s cn68xxp1;
1504}; 1971};
1505 1972
1506#endif 1973#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
new file mode 100644
index 00000000000..d45952df5f5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
@@ -0,0 +1,370 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCSX_DEFS_H__
29#define __CVMX_PCSX_DEFS_H__
30
31#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_PCSX_INTX_REG(offset, block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \
62 CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
63#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
65
66union cvmx_pcsx_anx_adv_reg {
67 uint64_t u64;
68 struct cvmx_pcsx_anx_adv_reg_s {
69 uint64_t reserved_16_63:48;
70 uint64_t np:1;
71 uint64_t reserved_14_14:1;
72 uint64_t rem_flt:2;
73 uint64_t reserved_9_11:3;
74 uint64_t pause:2;
75 uint64_t hfd:1;
76 uint64_t fd:1;
77 uint64_t reserved_0_4:5;
78 } s;
79 struct cvmx_pcsx_anx_adv_reg_s cn52xx;
80 struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
81 struct cvmx_pcsx_anx_adv_reg_s cn56xx;
82 struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
83};
84
85union cvmx_pcsx_anx_ext_st_reg {
86 uint64_t u64;
87 struct cvmx_pcsx_anx_ext_st_reg_s {
88 uint64_t reserved_16_63:48;
89 uint64_t thou_xfd:1;
90 uint64_t thou_xhd:1;
91 uint64_t thou_tfd:1;
92 uint64_t thou_thd:1;
93 uint64_t reserved_0_11:12;
94 } s;
95 struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
96 struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
97 struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
98 struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
99};
100
101union cvmx_pcsx_anx_lp_abil_reg {
102 uint64_t u64;
103 struct cvmx_pcsx_anx_lp_abil_reg_s {
104 uint64_t reserved_16_63:48;
105 uint64_t np:1;
106 uint64_t ack:1;
107 uint64_t rem_flt:2;
108 uint64_t reserved_9_11:3;
109 uint64_t pause:2;
110 uint64_t hfd:1;
111 uint64_t fd:1;
112 uint64_t reserved_0_4:5;
113 } s;
114 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
115 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
116 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
117 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
118};
119
120union cvmx_pcsx_anx_results_reg {
121 uint64_t u64;
122 struct cvmx_pcsx_anx_results_reg_s {
123 uint64_t reserved_7_63:57;
124 uint64_t pause:2;
125 uint64_t spd:2;
126 uint64_t an_cpt:1;
127 uint64_t dup:1;
128 uint64_t link_ok:1;
129 } s;
130 struct cvmx_pcsx_anx_results_reg_s cn52xx;
131 struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
132 struct cvmx_pcsx_anx_results_reg_s cn56xx;
133 struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
134};
135
136union cvmx_pcsx_intx_en_reg {
137 uint64_t u64;
138 struct cvmx_pcsx_intx_en_reg_s {
139 uint64_t reserved_12_63:52;
140 uint64_t dup:1;
141 uint64_t sync_bad_en:1;
142 uint64_t an_bad_en:1;
143 uint64_t rxlock_en:1;
144 uint64_t rxbad_en:1;
145 uint64_t rxerr_en:1;
146 uint64_t txbad_en:1;
147 uint64_t txfifo_en:1;
148 uint64_t txfifu_en:1;
149 uint64_t an_err_en:1;
150 uint64_t xmit_en:1;
151 uint64_t lnkspd_en:1;
152 } s;
153 struct cvmx_pcsx_intx_en_reg_s cn52xx;
154 struct cvmx_pcsx_intx_en_reg_s cn52xxp1;
155 struct cvmx_pcsx_intx_en_reg_s cn56xx;
156 struct cvmx_pcsx_intx_en_reg_s cn56xxp1;
157};
158
159union cvmx_pcsx_intx_reg {
160 uint64_t u64;
161 struct cvmx_pcsx_intx_reg_s {
162 uint64_t reserved_12_63:52;
163 uint64_t dup:1;
164 uint64_t sync_bad:1;
165 uint64_t an_bad:1;
166 uint64_t rxlock:1;
167 uint64_t rxbad:1;
168 uint64_t rxerr:1;
169 uint64_t txbad:1;
170 uint64_t txfifo:1;
171 uint64_t txfifu:1;
172 uint64_t an_err:1;
173 uint64_t xmit:1;
174 uint64_t lnkspd:1;
175 } s;
176 struct cvmx_pcsx_intx_reg_s cn52xx;
177 struct cvmx_pcsx_intx_reg_s cn52xxp1;
178 struct cvmx_pcsx_intx_reg_s cn56xx;
179 struct cvmx_pcsx_intx_reg_s cn56xxp1;
180};
181
182union cvmx_pcsx_linkx_timer_count_reg {
183 uint64_t u64;
184 struct cvmx_pcsx_linkx_timer_count_reg_s {
185 uint64_t reserved_16_63:48;
186 uint64_t count:16;
187 } s;
188 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
189 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
190 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
191 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
192};
193
194union cvmx_pcsx_log_anlx_reg {
195 uint64_t u64;
196 struct cvmx_pcsx_log_anlx_reg_s {
197 uint64_t reserved_4_63:60;
198 uint64_t lafifovfl:1;
199 uint64_t la_en:1;
200 uint64_t pkt_sz:2;
201 } s;
202 struct cvmx_pcsx_log_anlx_reg_s cn52xx;
203 struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
204 struct cvmx_pcsx_log_anlx_reg_s cn56xx;
205 struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
206};
207
208union cvmx_pcsx_miscx_ctl_reg {
209 uint64_t u64;
210 struct cvmx_pcsx_miscx_ctl_reg_s {
211 uint64_t reserved_13_63:51;
212 uint64_t sgmii:1;
213 uint64_t gmxeno:1;
214 uint64_t loopbck2:1;
215 uint64_t mac_phy:1;
216 uint64_t mode:1;
217 uint64_t an_ovrd:1;
218 uint64_t samp_pt:7;
219 } s;
220 struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
221 struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
222 struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
223 struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
224};
225
226union cvmx_pcsx_mrx_control_reg {
227 uint64_t u64;
228 struct cvmx_pcsx_mrx_control_reg_s {
229 uint64_t reserved_16_63:48;
230 uint64_t reset:1;
231 uint64_t loopbck1:1;
232 uint64_t spdlsb:1;
233 uint64_t an_en:1;
234 uint64_t pwr_dn:1;
235 uint64_t reserved_10_10:1;
236 uint64_t rst_an:1;
237 uint64_t dup:1;
238 uint64_t coltst:1;
239 uint64_t spdmsb:1;
240 uint64_t uni:1;
241 uint64_t reserved_0_4:5;
242 } s;
243 struct cvmx_pcsx_mrx_control_reg_s cn52xx;
244 struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
245 struct cvmx_pcsx_mrx_control_reg_s cn56xx;
246 struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
247};
248
249union cvmx_pcsx_mrx_status_reg {
250 uint64_t u64;
251 struct cvmx_pcsx_mrx_status_reg_s {
252 uint64_t reserved_16_63:48;
253 uint64_t hun_t4:1;
254 uint64_t hun_xfd:1;
255 uint64_t hun_xhd:1;
256 uint64_t ten_fd:1;
257 uint64_t ten_hd:1;
258 uint64_t hun_t2fd:1;
259 uint64_t hun_t2hd:1;
260 uint64_t ext_st:1;
261 uint64_t reserved_7_7:1;
262 uint64_t prb_sup:1;
263 uint64_t an_cpt:1;
264 uint64_t rm_flt:1;
265 uint64_t an_abil:1;
266 uint64_t lnk_st:1;
267 uint64_t reserved_1_1:1;
268 uint64_t extnd:1;
269 } s;
270 struct cvmx_pcsx_mrx_status_reg_s cn52xx;
271 struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
272 struct cvmx_pcsx_mrx_status_reg_s cn56xx;
273 struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
274};
275
276union cvmx_pcsx_rxx_states_reg {
277 uint64_t u64;
278 struct cvmx_pcsx_rxx_states_reg_s {
279 uint64_t reserved_16_63:48;
280 uint64_t rx_bad:1;
281 uint64_t rx_st:5;
282 uint64_t sync_bad:1;
283 uint64_t sync:4;
284 uint64_t an_bad:1;
285 uint64_t an_st:4;
286 } s;
287 struct cvmx_pcsx_rxx_states_reg_s cn52xx;
288 struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
289 struct cvmx_pcsx_rxx_states_reg_s cn56xx;
290 struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
291};
292
293union cvmx_pcsx_rxx_sync_reg {
294 uint64_t u64;
295 struct cvmx_pcsx_rxx_sync_reg_s {
296 uint64_t reserved_2_63:62;
297 uint64_t sync:1;
298 uint64_t bit_lock:1;
299 } s;
300 struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
301 struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
302 struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
303 struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
304};
305
306union cvmx_pcsx_sgmx_an_adv_reg {
307 uint64_t u64;
308 struct cvmx_pcsx_sgmx_an_adv_reg_s {
309 uint64_t reserved_16_63:48;
310 uint64_t link:1;
311 uint64_t ack:1;
312 uint64_t reserved_13_13:1;
313 uint64_t dup:1;
314 uint64_t speed:2;
315 uint64_t reserved_1_9:9;
316 uint64_t one:1;
317 } s;
318 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
319 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
320 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
321 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
322};
323
324union cvmx_pcsx_sgmx_lp_adv_reg {
325 uint64_t u64;
326 struct cvmx_pcsx_sgmx_lp_adv_reg_s {
327 uint64_t reserved_16_63:48;
328 uint64_t link:1;
329 uint64_t reserved_13_14:2;
330 uint64_t dup:1;
331 uint64_t speed:2;
332 uint64_t reserved_1_9:9;
333 uint64_t one:1;
334 } s;
335 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
336 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
337 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
338 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
339};
340
341union cvmx_pcsx_txx_states_reg {
342 uint64_t u64;
343 struct cvmx_pcsx_txx_states_reg_s {
344 uint64_t reserved_7_63:57;
345 uint64_t xmit:2;
346 uint64_t tx_bad:1;
347 uint64_t ord_st:4;
348 } s;
349 struct cvmx_pcsx_txx_states_reg_s cn52xx;
350 struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
351 struct cvmx_pcsx_txx_states_reg_s cn56xx;
352 struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
353};
354
355union cvmx_pcsx_tx_rxx_polarity_reg {
356 uint64_t u64;
357 struct cvmx_pcsx_tx_rxx_polarity_reg_s {
358 uint64_t reserved_4_63:60;
359 uint64_t rxovrd:1;
360 uint64_t autorxpl:1;
361 uint64_t rxplrt:1;
362 uint64_t txplrt:1;
363 } s;
364 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
365 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
366 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
367 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
368};
369
370#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
new file mode 100644
index 00000000000..55d120fe8ae
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
@@ -0,0 +1,316 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCSXX_DEFS_H__
29#define __CVMX_PCSXX_DEFS_H__
30
31#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_PCSXX_CONTROL1_REG(block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_PCSXX_CONTROL2_REG(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_PCSXX_INT_EN_REG(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_PCSXX_INT_REG(block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_PCSXX_LOG_ANL_REG(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_PCSXX_MISC_CTL_REG(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_PCSXX_STATUS1_REG(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_PCSXX_STATUS2_REG(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull))
61
62union cvmx_pcsxx_10gbx_status_reg {
63 uint64_t u64;
64 struct cvmx_pcsxx_10gbx_status_reg_s {
65 uint64_t reserved_13_63:51;
66 uint64_t alignd:1;
67 uint64_t pattst:1;
68 uint64_t reserved_4_10:7;
69 uint64_t l3sync:1;
70 uint64_t l2sync:1;
71 uint64_t l1sync:1;
72 uint64_t l0sync:1;
73 } s;
74 struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
75 struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
76 struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
77 struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
78};
79
80union cvmx_pcsxx_bist_status_reg {
81 uint64_t u64;
82 struct cvmx_pcsxx_bist_status_reg_s {
83 uint64_t reserved_1_63:63;
84 uint64_t bist_status:1;
85 } s;
86 struct cvmx_pcsxx_bist_status_reg_s cn52xx;
87 struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
88 struct cvmx_pcsxx_bist_status_reg_s cn56xx;
89 struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
90};
91
92union cvmx_pcsxx_bit_lock_status_reg {
93 uint64_t u64;
94 struct cvmx_pcsxx_bit_lock_status_reg_s {
95 uint64_t reserved_4_63:60;
96 uint64_t bitlck3:1;
97 uint64_t bitlck2:1;
98 uint64_t bitlck1:1;
99 uint64_t bitlck0:1;
100 } s;
101 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
102 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
103 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
104 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
105};
106
107union cvmx_pcsxx_control1_reg {
108 uint64_t u64;
109 struct cvmx_pcsxx_control1_reg_s {
110 uint64_t reserved_16_63:48;
111 uint64_t reset:1;
112 uint64_t loopbck1:1;
113 uint64_t spdsel1:1;
114 uint64_t reserved_12_12:1;
115 uint64_t lo_pwr:1;
116 uint64_t reserved_7_10:4;
117 uint64_t spdsel0:1;
118 uint64_t spd:4;
119 uint64_t reserved_0_1:2;
120 } s;
121 struct cvmx_pcsxx_control1_reg_s cn52xx;
122 struct cvmx_pcsxx_control1_reg_s cn52xxp1;
123 struct cvmx_pcsxx_control1_reg_s cn56xx;
124 struct cvmx_pcsxx_control1_reg_s cn56xxp1;
125};
126
127union cvmx_pcsxx_control2_reg {
128 uint64_t u64;
129 struct cvmx_pcsxx_control2_reg_s {
130 uint64_t reserved_2_63:62;
131 uint64_t type:2;
132 } s;
133 struct cvmx_pcsxx_control2_reg_s cn52xx;
134 struct cvmx_pcsxx_control2_reg_s cn52xxp1;
135 struct cvmx_pcsxx_control2_reg_s cn56xx;
136 struct cvmx_pcsxx_control2_reg_s cn56xxp1;
137};
138
139union cvmx_pcsxx_int_en_reg {
140 uint64_t u64;
141 struct cvmx_pcsxx_int_en_reg_s {
142 uint64_t reserved_6_63:58;
143 uint64_t algnlos_en:1;
144 uint64_t synlos_en:1;
145 uint64_t bitlckls_en:1;
146 uint64_t rxsynbad_en:1;
147 uint64_t rxbad_en:1;
148 uint64_t txflt_en:1;
149 } s;
150 struct cvmx_pcsxx_int_en_reg_s cn52xx;
151 struct cvmx_pcsxx_int_en_reg_s cn52xxp1;
152 struct cvmx_pcsxx_int_en_reg_s cn56xx;
153 struct cvmx_pcsxx_int_en_reg_s cn56xxp1;
154};
155
156union cvmx_pcsxx_int_reg {
157 uint64_t u64;
158 struct cvmx_pcsxx_int_reg_s {
159 uint64_t reserved_6_63:58;
160 uint64_t algnlos:1;
161 uint64_t synlos:1;
162 uint64_t bitlckls:1;
163 uint64_t rxsynbad:1;
164 uint64_t rxbad:1;
165 uint64_t txflt:1;
166 } s;
167 struct cvmx_pcsxx_int_reg_s cn52xx;
168 struct cvmx_pcsxx_int_reg_s cn52xxp1;
169 struct cvmx_pcsxx_int_reg_s cn56xx;
170 struct cvmx_pcsxx_int_reg_s cn56xxp1;
171};
172
173union cvmx_pcsxx_log_anl_reg {
174 uint64_t u64;
175 struct cvmx_pcsxx_log_anl_reg_s {
176 uint64_t reserved_7_63:57;
177 uint64_t enc_mode:1;
178 uint64_t drop_ln:2;
179 uint64_t lafifovfl:1;
180 uint64_t la_en:1;
181 uint64_t pkt_sz:2;
182 } s;
183 struct cvmx_pcsxx_log_anl_reg_s cn52xx;
184 struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
185 struct cvmx_pcsxx_log_anl_reg_s cn56xx;
186 struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
187};
188
189union cvmx_pcsxx_misc_ctl_reg {
190 uint64_t u64;
191 struct cvmx_pcsxx_misc_ctl_reg_s {
192 uint64_t reserved_4_63:60;
193 uint64_t tx_swap:1;
194 uint64_t rx_swap:1;
195 uint64_t xaui:1;
196 uint64_t gmxeno:1;
197 } s;
198 struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
199 struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
200 struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
201 struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
202};
203
204union cvmx_pcsxx_rx_sync_states_reg {
205 uint64_t u64;
206 struct cvmx_pcsxx_rx_sync_states_reg_s {
207 uint64_t reserved_16_63:48;
208 uint64_t sync3st:4;
209 uint64_t sync2st:4;
210 uint64_t sync1st:4;
211 uint64_t sync0st:4;
212 } s;
213 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
214 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
215 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
216 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
217};
218
219union cvmx_pcsxx_spd_abil_reg {
220 uint64_t u64;
221 struct cvmx_pcsxx_spd_abil_reg_s {
222 uint64_t reserved_2_63:62;
223 uint64_t tenpasst:1;
224 uint64_t tengb:1;
225 } s;
226 struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
227 struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
228 struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
229 struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
230};
231
232union cvmx_pcsxx_status1_reg {
233 uint64_t u64;
234 struct cvmx_pcsxx_status1_reg_s {
235 uint64_t reserved_8_63:56;
236 uint64_t flt:1;
237 uint64_t reserved_3_6:4;
238 uint64_t rcv_lnk:1;
239 uint64_t lpable:1;
240 uint64_t reserved_0_0:1;
241 } s;
242 struct cvmx_pcsxx_status1_reg_s cn52xx;
243 struct cvmx_pcsxx_status1_reg_s cn52xxp1;
244 struct cvmx_pcsxx_status1_reg_s cn56xx;
245 struct cvmx_pcsxx_status1_reg_s cn56xxp1;
246};
247
248union cvmx_pcsxx_status2_reg {
249 uint64_t u64;
250 struct cvmx_pcsxx_status2_reg_s {
251 uint64_t reserved_16_63:48;
252 uint64_t dev:2;
253 uint64_t reserved_12_13:2;
254 uint64_t xmtflt:1;
255 uint64_t rcvflt:1;
256 uint64_t reserved_3_9:7;
257 uint64_t tengb_w:1;
258 uint64_t tengb_x:1;
259 uint64_t tengb_r:1;
260 } s;
261 struct cvmx_pcsxx_status2_reg_s cn52xx;
262 struct cvmx_pcsxx_status2_reg_s cn52xxp1;
263 struct cvmx_pcsxx_status2_reg_s cn56xx;
264 struct cvmx_pcsxx_status2_reg_s cn56xxp1;
265};
266
267union cvmx_pcsxx_tx_rx_polarity_reg {
268 uint64_t u64;
269 struct cvmx_pcsxx_tx_rx_polarity_reg_s {
270 uint64_t reserved_10_63:54;
271 uint64_t xor_rxplrt:4;
272 uint64_t xor_txplrt:4;
273 uint64_t rxplrt:1;
274 uint64_t txplrt:1;
275 } s;
276 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
277 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
278 uint64_t reserved_2_63:62;
279 uint64_t rxplrt:1;
280 uint64_t txplrt:1;
281 } cn52xxp1;
282 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
283 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
284};
285
286union cvmx_pcsxx_tx_rx_states_reg {
287 uint64_t u64;
288 struct cvmx_pcsxx_tx_rx_states_reg_s {
289 uint64_t reserved_14_63:50;
290 uint64_t term_err:1;
291 uint64_t syn3bad:1;
292 uint64_t syn2bad:1;
293 uint64_t syn1bad:1;
294 uint64_t syn0bad:1;
295 uint64_t rxbad:1;
296 uint64_t algn_st:3;
297 uint64_t rx_st:2;
298 uint64_t tx_st:3;
299 } s;
300 struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
301 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
302 uint64_t reserved_13_63:51;
303 uint64_t syn3bad:1;
304 uint64_t syn2bad:1;
305 uint64_t syn1bad:1;
306 uint64_t syn0bad:1;
307 uint64_t rxbad:1;
308 uint64_t algn_st:3;
309 uint64_t rx_st:2;
310 uint64_t tx_st:3;
311 } cn52xxp1;
312 struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
313 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
314};
315
316#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
new file mode 100644
index 00000000000..be189a2585e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -0,0 +1,509 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PEMX_DEFS_H__
29#define __CVMX_PEMX_DEFS_H__
30
31#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
32#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
33#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
34#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
35#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
36#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
37#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
38#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
39#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
40#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
41#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
42#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
43#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
44#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
45#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
46#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
47#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
48#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
49#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
50#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
51#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
52#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
53
54union cvmx_pemx_bar1_indexx {
55 uint64_t u64;
56 struct cvmx_pemx_bar1_indexx_s {
57 uint64_t reserved_20_63:44;
58 uint64_t addr_idx:16;
59 uint64_t ca:1;
60 uint64_t end_swp:2;
61 uint64_t addr_v:1;
62 } s;
63 struct cvmx_pemx_bar1_indexx_s cn61xx;
64 struct cvmx_pemx_bar1_indexx_s cn63xx;
65 struct cvmx_pemx_bar1_indexx_s cn63xxp1;
66 struct cvmx_pemx_bar1_indexx_s cn66xx;
67 struct cvmx_pemx_bar1_indexx_s cn68xx;
68 struct cvmx_pemx_bar1_indexx_s cn68xxp1;
69};
70
71union cvmx_pemx_bar2_mask {
72 uint64_t u64;
73 struct cvmx_pemx_bar2_mask_s {
74 uint64_t reserved_38_63:26;
75 uint64_t mask:35;
76 uint64_t reserved_0_2:3;
77 } s;
78 struct cvmx_pemx_bar2_mask_s cn61xx;
79 struct cvmx_pemx_bar2_mask_s cn66xx;
80 struct cvmx_pemx_bar2_mask_s cn68xx;
81 struct cvmx_pemx_bar2_mask_s cn68xxp1;
82};
83
84union cvmx_pemx_bar_ctl {
85 uint64_t u64;
86 struct cvmx_pemx_bar_ctl_s {
87 uint64_t reserved_7_63:57;
88 uint64_t bar1_siz:3;
89 uint64_t bar2_enb:1;
90 uint64_t bar2_esx:2;
91 uint64_t bar2_cax:1;
92 } s;
93 struct cvmx_pemx_bar_ctl_s cn61xx;
94 struct cvmx_pemx_bar_ctl_s cn63xx;
95 struct cvmx_pemx_bar_ctl_s cn63xxp1;
96 struct cvmx_pemx_bar_ctl_s cn66xx;
97 struct cvmx_pemx_bar_ctl_s cn68xx;
98 struct cvmx_pemx_bar_ctl_s cn68xxp1;
99};
100
101union cvmx_pemx_bist_status {
102 uint64_t u64;
103 struct cvmx_pemx_bist_status_s {
104 uint64_t reserved_8_63:56;
105 uint64_t retry:1;
106 uint64_t rqdata0:1;
107 uint64_t rqdata1:1;
108 uint64_t rqdata2:1;
109 uint64_t rqdata3:1;
110 uint64_t rqhdr1:1;
111 uint64_t rqhdr0:1;
112 uint64_t sot:1;
113 } s;
114 struct cvmx_pemx_bist_status_s cn61xx;
115 struct cvmx_pemx_bist_status_s cn63xx;
116 struct cvmx_pemx_bist_status_s cn63xxp1;
117 struct cvmx_pemx_bist_status_s cn66xx;
118 struct cvmx_pemx_bist_status_s cn68xx;
119 struct cvmx_pemx_bist_status_s cn68xxp1;
120};
121
122union cvmx_pemx_bist_status2 {
123 uint64_t u64;
124 struct cvmx_pemx_bist_status2_s {
125 uint64_t reserved_10_63:54;
126 uint64_t e2p_cpl:1;
127 uint64_t e2p_n:1;
128 uint64_t e2p_p:1;
129 uint64_t peai_p2e:1;
130 uint64_t pef_tpf1:1;
131 uint64_t pef_tpf0:1;
132 uint64_t pef_tnf:1;
133 uint64_t pef_tcf1:1;
134 uint64_t pef_tc0:1;
135 uint64_t ppf:1;
136 } s;
137 struct cvmx_pemx_bist_status2_s cn61xx;
138 struct cvmx_pemx_bist_status2_s cn63xx;
139 struct cvmx_pemx_bist_status2_s cn63xxp1;
140 struct cvmx_pemx_bist_status2_s cn66xx;
141 struct cvmx_pemx_bist_status2_s cn68xx;
142 struct cvmx_pemx_bist_status2_s cn68xxp1;
143};
144
145union cvmx_pemx_cfg_rd {
146 uint64_t u64;
147 struct cvmx_pemx_cfg_rd_s {
148 uint64_t data:32;
149 uint64_t addr:32;
150 } s;
151 struct cvmx_pemx_cfg_rd_s cn61xx;
152 struct cvmx_pemx_cfg_rd_s cn63xx;
153 struct cvmx_pemx_cfg_rd_s cn63xxp1;
154 struct cvmx_pemx_cfg_rd_s cn66xx;
155 struct cvmx_pemx_cfg_rd_s cn68xx;
156 struct cvmx_pemx_cfg_rd_s cn68xxp1;
157};
158
159union cvmx_pemx_cfg_wr {
160 uint64_t u64;
161 struct cvmx_pemx_cfg_wr_s {
162 uint64_t data:32;
163 uint64_t addr:32;
164 } s;
165 struct cvmx_pemx_cfg_wr_s cn61xx;
166 struct cvmx_pemx_cfg_wr_s cn63xx;
167 struct cvmx_pemx_cfg_wr_s cn63xxp1;
168 struct cvmx_pemx_cfg_wr_s cn66xx;
169 struct cvmx_pemx_cfg_wr_s cn68xx;
170 struct cvmx_pemx_cfg_wr_s cn68xxp1;
171};
172
173union cvmx_pemx_cpl_lut_valid {
174 uint64_t u64;
175 struct cvmx_pemx_cpl_lut_valid_s {
176 uint64_t reserved_32_63:32;
177 uint64_t tag:32;
178 } s;
179 struct cvmx_pemx_cpl_lut_valid_s cn61xx;
180 struct cvmx_pemx_cpl_lut_valid_s cn63xx;
181 struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
182 struct cvmx_pemx_cpl_lut_valid_s cn66xx;
183 struct cvmx_pemx_cpl_lut_valid_s cn68xx;
184 struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
185};
186
187union cvmx_pemx_ctl_status {
188 uint64_t u64;
189 struct cvmx_pemx_ctl_status_s {
190 uint64_t reserved_48_63:16;
191 uint64_t auto_sd:1;
192 uint64_t dnum:5;
193 uint64_t pbus:8;
194 uint64_t reserved_32_33:2;
195 uint64_t cfg_rtry:16;
196 uint64_t reserved_12_15:4;
197 uint64_t pm_xtoff:1;
198 uint64_t pm_xpme:1;
199 uint64_t ob_p_cmd:1;
200 uint64_t reserved_7_8:2;
201 uint64_t nf_ecrc:1;
202 uint64_t dly_one:1;
203 uint64_t lnk_enb:1;
204 uint64_t ro_ctlp:1;
205 uint64_t fast_lm:1;
206 uint64_t inv_ecrc:1;
207 uint64_t inv_lcrc:1;
208 } s;
209 struct cvmx_pemx_ctl_status_s cn61xx;
210 struct cvmx_pemx_ctl_status_s cn63xx;
211 struct cvmx_pemx_ctl_status_s cn63xxp1;
212 struct cvmx_pemx_ctl_status_s cn66xx;
213 struct cvmx_pemx_ctl_status_s cn68xx;
214 struct cvmx_pemx_ctl_status_s cn68xxp1;
215};
216
217union cvmx_pemx_dbg_info {
218 uint64_t u64;
219 struct cvmx_pemx_dbg_info_s {
220 uint64_t reserved_31_63:33;
221 uint64_t ecrc_e:1;
222 uint64_t rawwpp:1;
223 uint64_t racpp:1;
224 uint64_t ramtlp:1;
225 uint64_t rarwdns:1;
226 uint64_t caar:1;
227 uint64_t racca:1;
228 uint64_t racur:1;
229 uint64_t rauc:1;
230 uint64_t rqo:1;
231 uint64_t fcuv:1;
232 uint64_t rpe:1;
233 uint64_t fcpvwt:1;
234 uint64_t dpeoosd:1;
235 uint64_t rtwdle:1;
236 uint64_t rdwdle:1;
237 uint64_t mre:1;
238 uint64_t rte:1;
239 uint64_t acto:1;
240 uint64_t rvdm:1;
241 uint64_t rumep:1;
242 uint64_t rptamrc:1;
243 uint64_t rpmerc:1;
244 uint64_t rfemrc:1;
245 uint64_t rnfemrc:1;
246 uint64_t rcemrc:1;
247 uint64_t rpoison:1;
248 uint64_t recrce:1;
249 uint64_t rtlplle:1;
250 uint64_t rtlpmal:1;
251 uint64_t spoison:1;
252 } s;
253 struct cvmx_pemx_dbg_info_s cn61xx;
254 struct cvmx_pemx_dbg_info_s cn63xx;
255 struct cvmx_pemx_dbg_info_s cn63xxp1;
256 struct cvmx_pemx_dbg_info_s cn66xx;
257 struct cvmx_pemx_dbg_info_s cn68xx;
258 struct cvmx_pemx_dbg_info_s cn68xxp1;
259};
260
261union cvmx_pemx_dbg_info_en {
262 uint64_t u64;
263 struct cvmx_pemx_dbg_info_en_s {
264 uint64_t reserved_31_63:33;
265 uint64_t ecrc_e:1;
266 uint64_t rawwpp:1;
267 uint64_t racpp:1;
268 uint64_t ramtlp:1;
269 uint64_t rarwdns:1;
270 uint64_t caar:1;
271 uint64_t racca:1;
272 uint64_t racur:1;
273 uint64_t rauc:1;
274 uint64_t rqo:1;
275 uint64_t fcuv:1;
276 uint64_t rpe:1;
277 uint64_t fcpvwt:1;
278 uint64_t dpeoosd:1;
279 uint64_t rtwdle:1;
280 uint64_t rdwdle:1;
281 uint64_t mre:1;
282 uint64_t rte:1;
283 uint64_t acto:1;
284 uint64_t rvdm:1;
285 uint64_t rumep:1;
286 uint64_t rptamrc:1;
287 uint64_t rpmerc:1;
288 uint64_t rfemrc:1;
289 uint64_t rnfemrc:1;
290 uint64_t rcemrc:1;
291 uint64_t rpoison:1;
292 uint64_t recrce:1;
293 uint64_t rtlplle:1;
294 uint64_t rtlpmal:1;
295 uint64_t spoison:1;
296 } s;
297 struct cvmx_pemx_dbg_info_en_s cn61xx;
298 struct cvmx_pemx_dbg_info_en_s cn63xx;
299 struct cvmx_pemx_dbg_info_en_s cn63xxp1;
300 struct cvmx_pemx_dbg_info_en_s cn66xx;
301 struct cvmx_pemx_dbg_info_en_s cn68xx;
302 struct cvmx_pemx_dbg_info_en_s cn68xxp1;
303};
304
305union cvmx_pemx_diag_status {
306 uint64_t u64;
307 struct cvmx_pemx_diag_status_s {
308 uint64_t reserved_4_63:60;
309 uint64_t pm_dst:1;
310 uint64_t pm_stat:1;
311 uint64_t pm_en:1;
312 uint64_t aux_en:1;
313 } s;
314 struct cvmx_pemx_diag_status_s cn61xx;
315 struct cvmx_pemx_diag_status_s cn63xx;
316 struct cvmx_pemx_diag_status_s cn63xxp1;
317 struct cvmx_pemx_diag_status_s cn66xx;
318 struct cvmx_pemx_diag_status_s cn68xx;
319 struct cvmx_pemx_diag_status_s cn68xxp1;
320};
321
322union cvmx_pemx_inb_read_credits {
323 uint64_t u64;
324 struct cvmx_pemx_inb_read_credits_s {
325 uint64_t reserved_6_63:58;
326 uint64_t num:6;
327 } s;
328 struct cvmx_pemx_inb_read_credits_s cn61xx;
329 struct cvmx_pemx_inb_read_credits_s cn66xx;
330 struct cvmx_pemx_inb_read_credits_s cn68xx;
331};
332
333union cvmx_pemx_int_enb {
334 uint64_t u64;
335 struct cvmx_pemx_int_enb_s {
336 uint64_t reserved_14_63:50;
337 uint64_t crs_dr:1;
338 uint64_t crs_er:1;
339 uint64_t rdlk:1;
340 uint64_t exc:1;
341 uint64_t un_bx:1;
342 uint64_t un_b2:1;
343 uint64_t un_b1:1;
344 uint64_t up_bx:1;
345 uint64_t up_b2:1;
346 uint64_t up_b1:1;
347 uint64_t pmem:1;
348 uint64_t pmei:1;
349 uint64_t se:1;
350 uint64_t aeri:1;
351 } s;
352 struct cvmx_pemx_int_enb_s cn61xx;
353 struct cvmx_pemx_int_enb_s cn63xx;
354 struct cvmx_pemx_int_enb_s cn63xxp1;
355 struct cvmx_pemx_int_enb_s cn66xx;
356 struct cvmx_pemx_int_enb_s cn68xx;
357 struct cvmx_pemx_int_enb_s cn68xxp1;
358};
359
360union cvmx_pemx_int_enb_int {
361 uint64_t u64;
362 struct cvmx_pemx_int_enb_int_s {
363 uint64_t reserved_14_63:50;
364 uint64_t crs_dr:1;
365 uint64_t crs_er:1;
366 uint64_t rdlk:1;
367 uint64_t exc:1;
368 uint64_t un_bx:1;
369 uint64_t un_b2:1;
370 uint64_t un_b1:1;
371 uint64_t up_bx:1;
372 uint64_t up_b2:1;
373 uint64_t up_b1:1;
374 uint64_t pmem:1;
375 uint64_t pmei:1;
376 uint64_t se:1;
377 uint64_t aeri:1;
378 } s;
379 struct cvmx_pemx_int_enb_int_s cn61xx;
380 struct cvmx_pemx_int_enb_int_s cn63xx;
381 struct cvmx_pemx_int_enb_int_s cn63xxp1;
382 struct cvmx_pemx_int_enb_int_s cn66xx;
383 struct cvmx_pemx_int_enb_int_s cn68xx;
384 struct cvmx_pemx_int_enb_int_s cn68xxp1;
385};
386
387union cvmx_pemx_int_sum {
388 uint64_t u64;
389 struct cvmx_pemx_int_sum_s {
390 uint64_t reserved_14_63:50;
391 uint64_t crs_dr:1;
392 uint64_t crs_er:1;
393 uint64_t rdlk:1;
394 uint64_t exc:1;
395 uint64_t un_bx:1;
396 uint64_t un_b2:1;
397 uint64_t un_b1:1;
398 uint64_t up_bx:1;
399 uint64_t up_b2:1;
400 uint64_t up_b1:1;
401 uint64_t pmem:1;
402 uint64_t pmei:1;
403 uint64_t se:1;
404 uint64_t aeri:1;
405 } s;
406 struct cvmx_pemx_int_sum_s cn61xx;
407 struct cvmx_pemx_int_sum_s cn63xx;
408 struct cvmx_pemx_int_sum_s cn63xxp1;
409 struct cvmx_pemx_int_sum_s cn66xx;
410 struct cvmx_pemx_int_sum_s cn68xx;
411 struct cvmx_pemx_int_sum_s cn68xxp1;
412};
413
414union cvmx_pemx_p2n_bar0_start {
415 uint64_t u64;
416 struct cvmx_pemx_p2n_bar0_start_s {
417 uint64_t addr:50;
418 uint64_t reserved_0_13:14;
419 } s;
420 struct cvmx_pemx_p2n_bar0_start_s cn61xx;
421 struct cvmx_pemx_p2n_bar0_start_s cn63xx;
422 struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
423 struct cvmx_pemx_p2n_bar0_start_s cn66xx;
424 struct cvmx_pemx_p2n_bar0_start_s cn68xx;
425 struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
426};
427
428union cvmx_pemx_p2n_bar1_start {
429 uint64_t u64;
430 struct cvmx_pemx_p2n_bar1_start_s {
431 uint64_t addr:38;
432 uint64_t reserved_0_25:26;
433 } s;
434 struct cvmx_pemx_p2n_bar1_start_s cn61xx;
435 struct cvmx_pemx_p2n_bar1_start_s cn63xx;
436 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
437 struct cvmx_pemx_p2n_bar1_start_s cn66xx;
438 struct cvmx_pemx_p2n_bar1_start_s cn68xx;
439 struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
440};
441
442union cvmx_pemx_p2n_bar2_start {
443 uint64_t u64;
444 struct cvmx_pemx_p2n_bar2_start_s {
445 uint64_t addr:23;
446 uint64_t reserved_0_40:41;
447 } s;
448 struct cvmx_pemx_p2n_bar2_start_s cn61xx;
449 struct cvmx_pemx_p2n_bar2_start_s cn63xx;
450 struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
451 struct cvmx_pemx_p2n_bar2_start_s cn66xx;
452 struct cvmx_pemx_p2n_bar2_start_s cn68xx;
453 struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
454};
455
456union cvmx_pemx_p2p_barx_end {
457 uint64_t u64;
458 struct cvmx_pemx_p2p_barx_end_s {
459 uint64_t addr:52;
460 uint64_t reserved_0_11:12;
461 } s;
462 struct cvmx_pemx_p2p_barx_end_s cn63xx;
463 struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
464 struct cvmx_pemx_p2p_barx_end_s cn66xx;
465 struct cvmx_pemx_p2p_barx_end_s cn68xx;
466 struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
467};
468
469union cvmx_pemx_p2p_barx_start {
470 uint64_t u64;
471 struct cvmx_pemx_p2p_barx_start_s {
472 uint64_t addr:52;
473 uint64_t reserved_0_11:12;
474 } s;
475 struct cvmx_pemx_p2p_barx_start_s cn63xx;
476 struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
477 struct cvmx_pemx_p2p_barx_start_s cn66xx;
478 struct cvmx_pemx_p2p_barx_start_s cn68xx;
479 struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
480};
481
482union cvmx_pemx_tlp_credits {
483 uint64_t u64;
484 struct cvmx_pemx_tlp_credits_s {
485 uint64_t reserved_56_63:8;
486 uint64_t peai_ppf:8;
487 uint64_t pem_cpl:8;
488 uint64_t pem_np:8;
489 uint64_t pem_p:8;
490 uint64_t sli_cpl:8;
491 uint64_t sli_np:8;
492 uint64_t sli_p:8;
493 } s;
494 struct cvmx_pemx_tlp_credits_cn61xx {
495 uint64_t reserved_56_63:8;
496 uint64_t peai_ppf:8;
497 uint64_t reserved_24_47:24;
498 uint64_t sli_cpl:8;
499 uint64_t sli_np:8;
500 uint64_t sli_p:8;
501 } cn61xx;
502 struct cvmx_pemx_tlp_credits_s cn63xx;
503 struct cvmx_pemx_tlp_credits_s cn63xxp1;
504 struct cvmx_pemx_tlp_credits_s cn66xx;
505 struct cvmx_pemx_tlp_credits_s cn68xx;
506 struct cvmx_pemx_tlp_credits_s cn68xxp1;
507};
508
509#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ab8679d89a..4438d211988 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -25,13 +25,6 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27 27
28/**
29 * cvmx-pexp-defs.h
30 *
31 * Configuration and status register (CSR) definitions for
32 * OCTEON PEXP.
33 *
34 */
35#ifndef __CVMX_PEXP_DEFS_H__ 28#ifndef __CVMX_PEXP_DEFS_H__
36#define __CVMX_PEXP_DEFS_H__ 29#define __CVMX_PEXP_DEFS_H__
37 30
@@ -139,7 +132,7 @@
139#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull)) 132#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
140#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull)) 133#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
141#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull)) 134#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
142#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16) 135#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
143#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull)) 136#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
144#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull)) 137#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
145#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull)) 138#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
@@ -152,7 +145,10 @@
152#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull)) 145#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
153#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull)) 146#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
154#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull)) 147#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
148#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
149#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
155#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull)) 150#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
151#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
156#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull)) 152#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
157#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12) 153#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
158#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull)) 154#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
@@ -206,6 +202,7 @@
206#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull)) 202#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
207#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull)) 203#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
208#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull)) 204#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
205#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
209#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull)) 206#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
210#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull)) 207#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
211#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull)) 208#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
@@ -214,12 +211,14 @@
214#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull)) 211#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
215#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull)) 212#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
216#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull)) 213#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
217#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16) 214#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
215#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
218#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull)) 216#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
219#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull)) 217#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
220#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull)) 218#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
221#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull)) 219#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
222#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull)) 220#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
221#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
223#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull)) 222#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
224 223
225#endif 224#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
new file mode 100644
index 00000000000..5a369100ca6
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
@@ -0,0 +1,1267 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PIP_DEFS_H__
29#define __CVMX_PIP_DEFS_H__
30
31/*
32 * Enumeration representing the amount of packet processing
33 * and validation performed by the input hardware.
34 */
35enum cvmx_pip_port_parse_mode {
36 /*
37 * Packet input doesn't perform any processing of the input
38 * packet.
39 */
40 CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,
41 /*
42 * Full packet processing is performed with pointer starting
43 * at the L2 (ethernet MAC) header.
44 */
45 CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
46 /*
47 * Input packets are assumed to be IP. Results from non IP
48 * packets is undefined. Pointers reference the beginning of
49 * the IP header.
50 */
51 CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull
52};
53
54#define CVMX_PIP_BCK_PRS \
55 CVMX_ADD_IO_SEG(0x00011800A0000038ull)
56#define CVMX_PIP_BIST_STATUS \
57 CVMX_ADD_IO_SEG(0x00011800A0000000ull)
58#define CVMX_PIP_CRC_CTLX(offset) \
59 CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8))
60#define CVMX_PIP_CRC_IVX(offset) \
61 CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8))
62#define CVMX_PIP_DEC_IPSECX(offset) \
63 CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8))
64#define CVMX_PIP_DSA_SRC_GRP \
65 CVMX_ADD_IO_SEG(0x00011800A0000190ull)
66#define CVMX_PIP_DSA_VID_GRP \
67 CVMX_ADD_IO_SEG(0x00011800A0000198ull)
68#define CVMX_PIP_FRM_LEN_CHKX(offset) \
69 CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8))
70#define CVMX_PIP_GBL_CFG \
71 CVMX_ADD_IO_SEG(0x00011800A0000028ull)
72#define CVMX_PIP_GBL_CTL \
73 CVMX_ADD_IO_SEG(0x00011800A0000020ull)
74#define CVMX_PIP_HG_PRI_QOS \
75 CVMX_ADD_IO_SEG(0x00011800A00001A0ull)
76#define CVMX_PIP_INT_EN \
77 CVMX_ADD_IO_SEG(0x00011800A0000010ull)
78#define CVMX_PIP_INT_REG \
79 CVMX_ADD_IO_SEG(0x00011800A0000008ull)
80#define CVMX_PIP_IP_OFFSET \
81 CVMX_ADD_IO_SEG(0x00011800A0000060ull)
82#define CVMX_PIP_PRT_CFGX(offset) \
83 CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8))
84#define CVMX_PIP_PRT_TAGX(offset) \
85 CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8))
86#define CVMX_PIP_QOS_DIFFX(offset) \
87 CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8))
88#define CVMX_PIP_QOS_VLANX(offset) \
89 CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8))
90#define CVMX_PIP_QOS_WATCHX(offset) \
91 CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8))
92#define CVMX_PIP_RAW_WORD \
93 CVMX_ADD_IO_SEG(0x00011800A00000B0ull)
94#define CVMX_PIP_SFT_RST \
95 CVMX_ADD_IO_SEG(0x00011800A0000030ull)
96#define CVMX_PIP_STAT0_PRTX(offset) \
97 CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80))
98#define CVMX_PIP_STAT1_PRTX(offset) \
99 CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80))
100#define CVMX_PIP_STAT2_PRTX(offset) \
101 CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80))
102#define CVMX_PIP_STAT3_PRTX(offset) \
103 CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80))
104#define CVMX_PIP_STAT4_PRTX(offset) \
105 CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80))
106#define CVMX_PIP_STAT5_PRTX(offset) \
107 CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80))
108#define CVMX_PIP_STAT6_PRTX(offset) \
109 CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80))
110#define CVMX_PIP_STAT7_PRTX(offset) \
111 CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80))
112#define CVMX_PIP_STAT8_PRTX(offset) \
113 CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80))
114#define CVMX_PIP_STAT9_PRTX(offset) \
115 CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80))
116#define CVMX_PIP_STAT_CTL \
117 CVMX_ADD_IO_SEG(0x00011800A0000018ull)
118#define CVMX_PIP_STAT_INB_ERRSX(offset) \
119 CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32))
120#define CVMX_PIP_STAT_INB_OCTSX(offset) \
121 CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32))
122#define CVMX_PIP_STAT_INB_PKTSX(offset) \
123 CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32))
124#define CVMX_PIP_TAG_INCX(offset) \
125 CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8))
126#define CVMX_PIP_TAG_MASK \
127 CVMX_ADD_IO_SEG(0x00011800A0000070ull)
128#define CVMX_PIP_TAG_SECRET \
129 CVMX_ADD_IO_SEG(0x00011800A0000068ull)
130#define CVMX_PIP_TODO_ENTRY \
131 CVMX_ADD_IO_SEG(0x00011800A0000078ull)
132
133union cvmx_pip_bck_prs {
134 uint64_t u64;
135 struct cvmx_pip_bck_prs_s {
136 uint64_t bckprs:1;
137 uint64_t reserved_13_62:50;
138 uint64_t hiwater:5;
139 uint64_t reserved_5_7:3;
140 uint64_t lowater:5;
141 } s;
142 struct cvmx_pip_bck_prs_s cn38xx;
143 struct cvmx_pip_bck_prs_s cn38xxp2;
144 struct cvmx_pip_bck_prs_s cn56xx;
145 struct cvmx_pip_bck_prs_s cn56xxp1;
146 struct cvmx_pip_bck_prs_s cn58xx;
147 struct cvmx_pip_bck_prs_s cn58xxp1;
148};
149
150union cvmx_pip_bist_status {
151 uint64_t u64;
152 struct cvmx_pip_bist_status_s {
153 uint64_t reserved_18_63:46;
154 uint64_t bist:18;
155 } s;
156 struct cvmx_pip_bist_status_s cn30xx;
157 struct cvmx_pip_bist_status_s cn31xx;
158 struct cvmx_pip_bist_status_s cn38xx;
159 struct cvmx_pip_bist_status_s cn38xxp2;
160 struct cvmx_pip_bist_status_cn50xx {
161 uint64_t reserved_17_63:47;
162 uint64_t bist:17;
163 } cn50xx;
164 struct cvmx_pip_bist_status_s cn52xx;
165 struct cvmx_pip_bist_status_s cn52xxp1;
166 struct cvmx_pip_bist_status_s cn56xx;
167 struct cvmx_pip_bist_status_s cn56xxp1;
168 struct cvmx_pip_bist_status_s cn58xx;
169 struct cvmx_pip_bist_status_s cn58xxp1;
170};
171
172union cvmx_pip_crc_ctlx {
173 uint64_t u64;
174 struct cvmx_pip_crc_ctlx_s {
175 uint64_t reserved_2_63:62;
176 uint64_t invres:1;
177 uint64_t reflect:1;
178 } s;
179 struct cvmx_pip_crc_ctlx_s cn38xx;
180 struct cvmx_pip_crc_ctlx_s cn38xxp2;
181 struct cvmx_pip_crc_ctlx_s cn58xx;
182 struct cvmx_pip_crc_ctlx_s cn58xxp1;
183};
184
185union cvmx_pip_crc_ivx {
186 uint64_t u64;
187 struct cvmx_pip_crc_ivx_s {
188 uint64_t reserved_32_63:32;
189 uint64_t iv:32;
190 } s;
191 struct cvmx_pip_crc_ivx_s cn38xx;
192 struct cvmx_pip_crc_ivx_s cn38xxp2;
193 struct cvmx_pip_crc_ivx_s cn58xx;
194 struct cvmx_pip_crc_ivx_s cn58xxp1;
195};
196
197union cvmx_pip_dec_ipsecx {
198 uint64_t u64;
199 struct cvmx_pip_dec_ipsecx_s {
200 uint64_t reserved_18_63:46;
201 uint64_t tcp:1;
202 uint64_t udp:1;
203 uint64_t dprt:16;
204 } s;
205 struct cvmx_pip_dec_ipsecx_s cn30xx;
206 struct cvmx_pip_dec_ipsecx_s cn31xx;
207 struct cvmx_pip_dec_ipsecx_s cn38xx;
208 struct cvmx_pip_dec_ipsecx_s cn38xxp2;
209 struct cvmx_pip_dec_ipsecx_s cn50xx;
210 struct cvmx_pip_dec_ipsecx_s cn52xx;
211 struct cvmx_pip_dec_ipsecx_s cn52xxp1;
212 struct cvmx_pip_dec_ipsecx_s cn56xx;
213 struct cvmx_pip_dec_ipsecx_s cn56xxp1;
214 struct cvmx_pip_dec_ipsecx_s cn58xx;
215 struct cvmx_pip_dec_ipsecx_s cn58xxp1;
216};
217
218union cvmx_pip_dsa_src_grp {
219 uint64_t u64;
220 struct cvmx_pip_dsa_src_grp_s {
221 uint64_t map15:4;
222 uint64_t map14:4;
223 uint64_t map13:4;
224 uint64_t map12:4;
225 uint64_t map11:4;
226 uint64_t map10:4;
227 uint64_t map9:4;
228 uint64_t map8:4;
229 uint64_t map7:4;
230 uint64_t map6:4;
231 uint64_t map5:4;
232 uint64_t map4:4;
233 uint64_t map3:4;
234 uint64_t map2:4;
235 uint64_t map1:4;
236 uint64_t map0:4;
237 } s;
238 struct cvmx_pip_dsa_src_grp_s cn52xx;
239 struct cvmx_pip_dsa_src_grp_s cn52xxp1;
240 struct cvmx_pip_dsa_src_grp_s cn56xx;
241};
242
243union cvmx_pip_dsa_vid_grp {
244 uint64_t u64;
245 struct cvmx_pip_dsa_vid_grp_s {
246 uint64_t map15:4;
247 uint64_t map14:4;
248 uint64_t map13:4;
249 uint64_t map12:4;
250 uint64_t map11:4;
251 uint64_t map10:4;
252 uint64_t map9:4;
253 uint64_t map8:4;
254 uint64_t map7:4;
255 uint64_t map6:4;
256 uint64_t map5:4;
257 uint64_t map4:4;
258 uint64_t map3:4;
259 uint64_t map2:4;
260 uint64_t map1:4;
261 uint64_t map0:4;
262 } s;
263 struct cvmx_pip_dsa_vid_grp_s cn52xx;
264 struct cvmx_pip_dsa_vid_grp_s cn52xxp1;
265 struct cvmx_pip_dsa_vid_grp_s cn56xx;
266};
267
268union cvmx_pip_frm_len_chkx {
269 uint64_t u64;
270 struct cvmx_pip_frm_len_chkx_s {
271 uint64_t reserved_32_63:32;
272 uint64_t maxlen:16;
273 uint64_t minlen:16;
274 } s;
275 struct cvmx_pip_frm_len_chkx_s cn50xx;
276 struct cvmx_pip_frm_len_chkx_s cn52xx;
277 struct cvmx_pip_frm_len_chkx_s cn52xxp1;
278 struct cvmx_pip_frm_len_chkx_s cn56xx;
279 struct cvmx_pip_frm_len_chkx_s cn56xxp1;
280};
281
282union cvmx_pip_gbl_cfg {
283 uint64_t u64;
284 struct cvmx_pip_gbl_cfg_s {
285 uint64_t reserved_19_63:45;
286 uint64_t tag_syn:1;
287 uint64_t ip6_udp:1;
288 uint64_t max_l2:1;
289 uint64_t reserved_11_15:5;
290 uint64_t raw_shf:3;
291 uint64_t reserved_3_7:5;
292 uint64_t nip_shf:3;
293 } s;
294 struct cvmx_pip_gbl_cfg_s cn30xx;
295 struct cvmx_pip_gbl_cfg_s cn31xx;
296 struct cvmx_pip_gbl_cfg_s cn38xx;
297 struct cvmx_pip_gbl_cfg_s cn38xxp2;
298 struct cvmx_pip_gbl_cfg_s cn50xx;
299 struct cvmx_pip_gbl_cfg_s cn52xx;
300 struct cvmx_pip_gbl_cfg_s cn52xxp1;
301 struct cvmx_pip_gbl_cfg_s cn56xx;
302 struct cvmx_pip_gbl_cfg_s cn56xxp1;
303 struct cvmx_pip_gbl_cfg_s cn58xx;
304 struct cvmx_pip_gbl_cfg_s cn58xxp1;
305};
306
307union cvmx_pip_gbl_ctl {
308 uint64_t u64;
309 struct cvmx_pip_gbl_ctl_s {
310 uint64_t reserved_27_63:37;
311 uint64_t dsa_grp_tvid:1;
312 uint64_t dsa_grp_scmd:1;
313 uint64_t dsa_grp_sid:1;
314 uint64_t reserved_21_23:3;
315 uint64_t ring_en:1;
316 uint64_t reserved_17_19:3;
317 uint64_t ignrs:1;
318 uint64_t vs_wqe:1;
319 uint64_t vs_qos:1;
320 uint64_t l2_mal:1;
321 uint64_t tcp_flag:1;
322 uint64_t l4_len:1;
323 uint64_t l4_chk:1;
324 uint64_t l4_prt:1;
325 uint64_t l4_mal:1;
326 uint64_t reserved_6_7:2;
327 uint64_t ip6_eext:2;
328 uint64_t ip4_opts:1;
329 uint64_t ip_hop:1;
330 uint64_t ip_mal:1;
331 uint64_t ip_chk:1;
332 } s;
333 struct cvmx_pip_gbl_ctl_cn30xx {
334 uint64_t reserved_17_63:47;
335 uint64_t ignrs:1;
336 uint64_t vs_wqe:1;
337 uint64_t vs_qos:1;
338 uint64_t l2_mal:1;
339 uint64_t tcp_flag:1;
340 uint64_t l4_len:1;
341 uint64_t l4_chk:1;
342 uint64_t l4_prt:1;
343 uint64_t l4_mal:1;
344 uint64_t reserved_6_7:2;
345 uint64_t ip6_eext:2;
346 uint64_t ip4_opts:1;
347 uint64_t ip_hop:1;
348 uint64_t ip_mal:1;
349 uint64_t ip_chk:1;
350 } cn30xx;
351 struct cvmx_pip_gbl_ctl_cn30xx cn31xx;
352 struct cvmx_pip_gbl_ctl_cn30xx cn38xx;
353 struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;
354 struct cvmx_pip_gbl_ctl_cn30xx cn50xx;
355 struct cvmx_pip_gbl_ctl_s cn52xx;
356 struct cvmx_pip_gbl_ctl_s cn52xxp1;
357 struct cvmx_pip_gbl_ctl_s cn56xx;
358 struct cvmx_pip_gbl_ctl_cn56xxp1 {
359 uint64_t reserved_21_63:43;
360 uint64_t ring_en:1;
361 uint64_t reserved_17_19:3;
362 uint64_t ignrs:1;
363 uint64_t vs_wqe:1;
364 uint64_t vs_qos:1;
365 uint64_t l2_mal:1;
366 uint64_t tcp_flag:1;
367 uint64_t l4_len:1;
368 uint64_t l4_chk:1;
369 uint64_t l4_prt:1;
370 uint64_t l4_mal:1;
371 uint64_t reserved_6_7:2;
372 uint64_t ip6_eext:2;
373 uint64_t ip4_opts:1;
374 uint64_t ip_hop:1;
375 uint64_t ip_mal:1;
376 uint64_t ip_chk:1;
377 } cn56xxp1;
378 struct cvmx_pip_gbl_ctl_cn30xx cn58xx;
379 struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;
380};
381
382union cvmx_pip_hg_pri_qos {
383 uint64_t u64;
384 struct cvmx_pip_hg_pri_qos_s {
385 uint64_t reserved_11_63:53;
386 uint64_t qos:3;
387 uint64_t reserved_6_7:2;
388 uint64_t pri:6;
389 } s;
390 struct cvmx_pip_hg_pri_qos_s cn52xx;
391 struct cvmx_pip_hg_pri_qos_s cn52xxp1;
392 struct cvmx_pip_hg_pri_qos_s cn56xx;
393};
394
395union cvmx_pip_int_en {
396 uint64_t u64;
397 struct cvmx_pip_int_en_s {
398 uint64_t reserved_13_63:51;
399 uint64_t punyerr:1;
400 uint64_t lenerr:1;
401 uint64_t maxerr:1;
402 uint64_t minerr:1;
403 uint64_t beperr:1;
404 uint64_t feperr:1;
405 uint64_t todoovr:1;
406 uint64_t skprunt:1;
407 uint64_t badtag:1;
408 uint64_t prtnxa:1;
409 uint64_t bckprs:1;
410 uint64_t crcerr:1;
411 uint64_t pktdrp:1;
412 } s;
413 struct cvmx_pip_int_en_cn30xx {
414 uint64_t reserved_9_63:55;
415 uint64_t beperr:1;
416 uint64_t feperr:1;
417 uint64_t todoovr:1;
418 uint64_t skprunt:1;
419 uint64_t badtag:1;
420 uint64_t prtnxa:1;
421 uint64_t bckprs:1;
422 uint64_t crcerr:1;
423 uint64_t pktdrp:1;
424 } cn30xx;
425 struct cvmx_pip_int_en_cn30xx cn31xx;
426 struct cvmx_pip_int_en_cn30xx cn38xx;
427 struct cvmx_pip_int_en_cn30xx cn38xxp2;
428 struct cvmx_pip_int_en_cn50xx {
429 uint64_t reserved_12_63:52;
430 uint64_t lenerr:1;
431 uint64_t maxerr:1;
432 uint64_t minerr:1;
433 uint64_t beperr:1;
434 uint64_t feperr:1;
435 uint64_t todoovr:1;
436 uint64_t skprunt:1;
437 uint64_t badtag:1;
438 uint64_t prtnxa:1;
439 uint64_t bckprs:1;
440 uint64_t reserved_1_1:1;
441 uint64_t pktdrp:1;
442 } cn50xx;
443 struct cvmx_pip_int_en_cn52xx {
444 uint64_t reserved_13_63:51;
445 uint64_t punyerr:1;
446 uint64_t lenerr:1;
447 uint64_t maxerr:1;
448 uint64_t minerr:1;
449 uint64_t beperr:1;
450 uint64_t feperr:1;
451 uint64_t todoovr:1;
452 uint64_t skprunt:1;
453 uint64_t badtag:1;
454 uint64_t prtnxa:1;
455 uint64_t bckprs:1;
456 uint64_t reserved_1_1:1;
457 uint64_t pktdrp:1;
458 } cn52xx;
459 struct cvmx_pip_int_en_cn52xx cn52xxp1;
460 struct cvmx_pip_int_en_s cn56xx;
461 struct cvmx_pip_int_en_cn56xxp1 {
462 uint64_t reserved_12_63:52;
463 uint64_t lenerr:1;
464 uint64_t maxerr:1;
465 uint64_t minerr:1;
466 uint64_t beperr:1;
467 uint64_t feperr:1;
468 uint64_t todoovr:1;
469 uint64_t skprunt:1;
470 uint64_t badtag:1;
471 uint64_t prtnxa:1;
472 uint64_t bckprs:1;
473 uint64_t crcerr:1;
474 uint64_t pktdrp:1;
475 } cn56xxp1;
476 struct cvmx_pip_int_en_cn58xx {
477 uint64_t reserved_13_63:51;
478 uint64_t punyerr:1;
479 uint64_t reserved_9_11:3;
480 uint64_t beperr:1;
481 uint64_t feperr:1;
482 uint64_t todoovr:1;
483 uint64_t skprunt:1;
484 uint64_t badtag:1;
485 uint64_t prtnxa:1;
486 uint64_t bckprs:1;
487 uint64_t crcerr:1;
488 uint64_t pktdrp:1;
489 } cn58xx;
490 struct cvmx_pip_int_en_cn30xx cn58xxp1;
491};
492
493union cvmx_pip_int_reg {
494 uint64_t u64;
495 struct cvmx_pip_int_reg_s {
496 uint64_t reserved_13_63:51;
497 uint64_t punyerr:1;
498 uint64_t lenerr:1;
499 uint64_t maxerr:1;
500 uint64_t minerr:1;
501 uint64_t beperr:1;
502 uint64_t feperr:1;
503 uint64_t todoovr:1;
504 uint64_t skprunt:1;
505 uint64_t badtag:1;
506 uint64_t prtnxa:1;
507 uint64_t bckprs:1;
508 uint64_t crcerr:1;
509 uint64_t pktdrp:1;
510 } s;
511 struct cvmx_pip_int_reg_cn30xx {
512 uint64_t reserved_9_63:55;
513 uint64_t beperr:1;
514 uint64_t feperr:1;
515 uint64_t todoovr:1;
516 uint64_t skprunt:1;
517 uint64_t badtag:1;
518 uint64_t prtnxa:1;
519 uint64_t bckprs:1;
520 uint64_t crcerr:1;
521 uint64_t pktdrp:1;
522 } cn30xx;
523 struct cvmx_pip_int_reg_cn30xx cn31xx;
524 struct cvmx_pip_int_reg_cn30xx cn38xx;
525 struct cvmx_pip_int_reg_cn30xx cn38xxp2;
526 struct cvmx_pip_int_reg_cn50xx {
527 uint64_t reserved_12_63:52;
528 uint64_t lenerr:1;
529 uint64_t maxerr:1;
530 uint64_t minerr:1;
531 uint64_t beperr:1;
532 uint64_t feperr:1;
533 uint64_t todoovr:1;
534 uint64_t skprunt:1;
535 uint64_t badtag:1;
536 uint64_t prtnxa:1;
537 uint64_t bckprs:1;
538 uint64_t reserved_1_1:1;
539 uint64_t pktdrp:1;
540 } cn50xx;
541 struct cvmx_pip_int_reg_cn52xx {
542 uint64_t reserved_13_63:51;
543 uint64_t punyerr:1;
544 uint64_t lenerr:1;
545 uint64_t maxerr:1;
546 uint64_t minerr:1;
547 uint64_t beperr:1;
548 uint64_t feperr:1;
549 uint64_t todoovr:1;
550 uint64_t skprunt:1;
551 uint64_t badtag:1;
552 uint64_t prtnxa:1;
553 uint64_t bckprs:1;
554 uint64_t reserved_1_1:1;
555 uint64_t pktdrp:1;
556 } cn52xx;
557 struct cvmx_pip_int_reg_cn52xx cn52xxp1;
558 struct cvmx_pip_int_reg_s cn56xx;
559 struct cvmx_pip_int_reg_cn56xxp1 {
560 uint64_t reserved_12_63:52;
561 uint64_t lenerr:1;
562 uint64_t maxerr:1;
563 uint64_t minerr:1;
564 uint64_t beperr:1;
565 uint64_t feperr:1;
566 uint64_t todoovr:1;
567 uint64_t skprunt:1;
568 uint64_t badtag:1;
569 uint64_t prtnxa:1;
570 uint64_t bckprs:1;
571 uint64_t crcerr:1;
572 uint64_t pktdrp:1;
573 } cn56xxp1;
574 struct cvmx_pip_int_reg_cn58xx {
575 uint64_t reserved_13_63:51;
576 uint64_t punyerr:1;
577 uint64_t reserved_9_11:3;
578 uint64_t beperr:1;
579 uint64_t feperr:1;
580 uint64_t todoovr:1;
581 uint64_t skprunt:1;
582 uint64_t badtag:1;
583 uint64_t prtnxa:1;
584 uint64_t bckprs:1;
585 uint64_t crcerr:1;
586 uint64_t pktdrp:1;
587 } cn58xx;
588 struct cvmx_pip_int_reg_cn30xx cn58xxp1;
589};
590
591union cvmx_pip_ip_offset {
592 uint64_t u64;
593 struct cvmx_pip_ip_offset_s {
594 uint64_t reserved_3_63:61;
595 uint64_t offset:3;
596 } s;
597 struct cvmx_pip_ip_offset_s cn30xx;
598 struct cvmx_pip_ip_offset_s cn31xx;
599 struct cvmx_pip_ip_offset_s cn38xx;
600 struct cvmx_pip_ip_offset_s cn38xxp2;
601 struct cvmx_pip_ip_offset_s cn50xx;
602 struct cvmx_pip_ip_offset_s cn52xx;
603 struct cvmx_pip_ip_offset_s cn52xxp1;
604 struct cvmx_pip_ip_offset_s cn56xx;
605 struct cvmx_pip_ip_offset_s cn56xxp1;
606 struct cvmx_pip_ip_offset_s cn58xx;
607 struct cvmx_pip_ip_offset_s cn58xxp1;
608};
609
610union cvmx_pip_prt_cfgx {
611 uint64_t u64;
612 struct cvmx_pip_prt_cfgx_s {
613 uint64_t reserved_53_63:11;
614 uint64_t pad_len:1;
615 uint64_t vlan_len:1;
616 uint64_t lenerr_en:1;
617 uint64_t maxerr_en:1;
618 uint64_t minerr_en:1;
619 uint64_t grp_wat_47:4;
620 uint64_t qos_wat_47:4;
621 uint64_t reserved_37_39:3;
622 uint64_t rawdrp:1;
623 uint64_t tag_inc:2;
624 uint64_t dyn_rs:1;
625 uint64_t inst_hdr:1;
626 uint64_t grp_wat:4;
627 uint64_t hg_qos:1;
628 uint64_t qos:3;
629 uint64_t qos_wat:4;
630 uint64_t qos_vsel:1;
631 uint64_t qos_vod:1;
632 uint64_t qos_diff:1;
633 uint64_t qos_vlan:1;
634 uint64_t reserved_13_15:3;
635 uint64_t crc_en:1;
636 uint64_t higig_en:1;
637 uint64_t dsa_en:1;
638 uint64_t mode:2;
639 uint64_t reserved_7_7:1;
640 uint64_t skip:7;
641 } s;
642 struct cvmx_pip_prt_cfgx_cn30xx {
643 uint64_t reserved_37_63:27;
644 uint64_t rawdrp:1;
645 uint64_t tag_inc:2;
646 uint64_t dyn_rs:1;
647 uint64_t inst_hdr:1;
648 uint64_t grp_wat:4;
649 uint64_t reserved_27_27:1;
650 uint64_t qos:3;
651 uint64_t qos_wat:4;
652 uint64_t reserved_18_19:2;
653 uint64_t qos_diff:1;
654 uint64_t qos_vlan:1;
655 uint64_t reserved_10_15:6;
656 uint64_t mode:2;
657 uint64_t reserved_7_7:1;
658 uint64_t skip:7;
659 } cn30xx;
660 struct cvmx_pip_prt_cfgx_cn30xx cn31xx;
661 struct cvmx_pip_prt_cfgx_cn38xx {
662 uint64_t reserved_37_63:27;
663 uint64_t rawdrp:1;
664 uint64_t tag_inc:2;
665 uint64_t dyn_rs:1;
666 uint64_t inst_hdr:1;
667 uint64_t grp_wat:4;
668 uint64_t reserved_27_27:1;
669 uint64_t qos:3;
670 uint64_t qos_wat:4;
671 uint64_t reserved_18_19:2;
672 uint64_t qos_diff:1;
673 uint64_t qos_vlan:1;
674 uint64_t reserved_13_15:3;
675 uint64_t crc_en:1;
676 uint64_t reserved_10_11:2;
677 uint64_t mode:2;
678 uint64_t reserved_7_7:1;
679 uint64_t skip:7;
680 } cn38xx;
681 struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;
682 struct cvmx_pip_prt_cfgx_cn50xx {
683 uint64_t reserved_53_63:11;
684 uint64_t pad_len:1;
685 uint64_t vlan_len:1;
686 uint64_t lenerr_en:1;
687 uint64_t maxerr_en:1;
688 uint64_t minerr_en:1;
689 uint64_t grp_wat_47:4;
690 uint64_t qos_wat_47:4;
691 uint64_t reserved_37_39:3;
692 uint64_t rawdrp:1;
693 uint64_t tag_inc:2;
694 uint64_t dyn_rs:1;
695 uint64_t inst_hdr:1;
696 uint64_t grp_wat:4;
697 uint64_t reserved_27_27:1;
698 uint64_t qos:3;
699 uint64_t qos_wat:4;
700 uint64_t reserved_19_19:1;
701 uint64_t qos_vod:1;
702 uint64_t qos_diff:1;
703 uint64_t qos_vlan:1;
704 uint64_t reserved_13_15:3;
705 uint64_t crc_en:1;
706 uint64_t reserved_10_11:2;
707 uint64_t mode:2;
708 uint64_t reserved_7_7:1;
709 uint64_t skip:7;
710 } cn50xx;
711 struct cvmx_pip_prt_cfgx_s cn52xx;
712 struct cvmx_pip_prt_cfgx_s cn52xxp1;
713 struct cvmx_pip_prt_cfgx_s cn56xx;
714 struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;
715 struct cvmx_pip_prt_cfgx_cn58xx {
716 uint64_t reserved_37_63:27;
717 uint64_t rawdrp:1;
718 uint64_t tag_inc:2;
719 uint64_t dyn_rs:1;
720 uint64_t inst_hdr:1;
721 uint64_t grp_wat:4;
722 uint64_t reserved_27_27:1;
723 uint64_t qos:3;
724 uint64_t qos_wat:4;
725 uint64_t reserved_19_19:1;
726 uint64_t qos_vod:1;
727 uint64_t qos_diff:1;
728 uint64_t qos_vlan:1;
729 uint64_t reserved_13_15:3;
730 uint64_t crc_en:1;
731 uint64_t reserved_10_11:2;
732 uint64_t mode:2;
733 uint64_t reserved_7_7:1;
734 uint64_t skip:7;
735 } cn58xx;
736 struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;
737};
738
739union cvmx_pip_prt_tagx {
740 uint64_t u64;
741 struct cvmx_pip_prt_tagx_s {
742 uint64_t reserved_40_63:24;
743 uint64_t grptagbase:4;
744 uint64_t grptagmask:4;
745 uint64_t grptag:1;
746 uint64_t grptag_mskip:1;
747 uint64_t tag_mode:2;
748 uint64_t inc_vs:2;
749 uint64_t inc_vlan:1;
750 uint64_t inc_prt_flag:1;
751 uint64_t ip6_dprt_flag:1;
752 uint64_t ip4_dprt_flag:1;
753 uint64_t ip6_sprt_flag:1;
754 uint64_t ip4_sprt_flag:1;
755 uint64_t ip6_nxth_flag:1;
756 uint64_t ip4_pctl_flag:1;
757 uint64_t ip6_dst_flag:1;
758 uint64_t ip4_dst_flag:1;
759 uint64_t ip6_src_flag:1;
760 uint64_t ip4_src_flag:1;
761 uint64_t tcp6_tag_type:2;
762 uint64_t tcp4_tag_type:2;
763 uint64_t ip6_tag_type:2;
764 uint64_t ip4_tag_type:2;
765 uint64_t non_tag_type:2;
766 uint64_t grp:4;
767 } s;
768 struct cvmx_pip_prt_tagx_cn30xx {
769 uint64_t reserved_40_63:24;
770 uint64_t grptagbase:4;
771 uint64_t grptagmask:4;
772 uint64_t grptag:1;
773 uint64_t reserved_30_30:1;
774 uint64_t tag_mode:2;
775 uint64_t inc_vs:2;
776 uint64_t inc_vlan:1;
777 uint64_t inc_prt_flag:1;
778 uint64_t ip6_dprt_flag:1;
779 uint64_t ip4_dprt_flag:1;
780 uint64_t ip6_sprt_flag:1;
781 uint64_t ip4_sprt_flag:1;
782 uint64_t ip6_nxth_flag:1;
783 uint64_t ip4_pctl_flag:1;
784 uint64_t ip6_dst_flag:1;
785 uint64_t ip4_dst_flag:1;
786 uint64_t ip6_src_flag:1;
787 uint64_t ip4_src_flag:1;
788 uint64_t tcp6_tag_type:2;
789 uint64_t tcp4_tag_type:2;
790 uint64_t ip6_tag_type:2;
791 uint64_t ip4_tag_type:2;
792 uint64_t non_tag_type:2;
793 uint64_t grp:4;
794 } cn30xx;
795 struct cvmx_pip_prt_tagx_cn30xx cn31xx;
796 struct cvmx_pip_prt_tagx_cn30xx cn38xx;
797 struct cvmx_pip_prt_tagx_cn30xx cn38xxp2;
798 struct cvmx_pip_prt_tagx_s cn50xx;
799 struct cvmx_pip_prt_tagx_s cn52xx;
800 struct cvmx_pip_prt_tagx_s cn52xxp1;
801 struct cvmx_pip_prt_tagx_s cn56xx;
802 struct cvmx_pip_prt_tagx_s cn56xxp1;
803 struct cvmx_pip_prt_tagx_cn30xx cn58xx;
804 struct cvmx_pip_prt_tagx_cn30xx cn58xxp1;
805};
806
807union cvmx_pip_qos_diffx {
808 uint64_t u64;
809 struct cvmx_pip_qos_diffx_s {
810 uint64_t reserved_3_63:61;
811 uint64_t qos:3;
812 } s;
813 struct cvmx_pip_qos_diffx_s cn30xx;
814 struct cvmx_pip_qos_diffx_s cn31xx;
815 struct cvmx_pip_qos_diffx_s cn38xx;
816 struct cvmx_pip_qos_diffx_s cn38xxp2;
817 struct cvmx_pip_qos_diffx_s cn50xx;
818 struct cvmx_pip_qos_diffx_s cn52xx;
819 struct cvmx_pip_qos_diffx_s cn52xxp1;
820 struct cvmx_pip_qos_diffx_s cn56xx;
821 struct cvmx_pip_qos_diffx_s cn56xxp1;
822 struct cvmx_pip_qos_diffx_s cn58xx;
823 struct cvmx_pip_qos_diffx_s cn58xxp1;
824};
825
826union cvmx_pip_qos_vlanx {
827 uint64_t u64;
828 struct cvmx_pip_qos_vlanx_s {
829 uint64_t reserved_7_63:57;
830 uint64_t qos1:3;
831 uint64_t reserved_3_3:1;
832 uint64_t qos:3;
833 } s;
834 struct cvmx_pip_qos_vlanx_cn30xx {
835 uint64_t reserved_3_63:61;
836 uint64_t qos:3;
837 } cn30xx;
838 struct cvmx_pip_qos_vlanx_cn30xx cn31xx;
839 struct cvmx_pip_qos_vlanx_cn30xx cn38xx;
840 struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;
841 struct cvmx_pip_qos_vlanx_cn30xx cn50xx;
842 struct cvmx_pip_qos_vlanx_s cn52xx;
843 struct cvmx_pip_qos_vlanx_s cn52xxp1;
844 struct cvmx_pip_qos_vlanx_s cn56xx;
845 struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;
846 struct cvmx_pip_qos_vlanx_cn30xx cn58xx;
847 struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;
848};
849
850union cvmx_pip_qos_watchx {
851 uint64_t u64;
852 struct cvmx_pip_qos_watchx_s {
853 uint64_t reserved_48_63:16;
854 uint64_t mask:16;
855 uint64_t reserved_28_31:4;
856 uint64_t grp:4;
857 uint64_t reserved_23_23:1;
858 uint64_t qos:3;
859 uint64_t reserved_19_19:1;
860 uint64_t match_type:3;
861 uint64_t match_value:16;
862 } s;
863 struct cvmx_pip_qos_watchx_cn30xx {
864 uint64_t reserved_48_63:16;
865 uint64_t mask:16;
866 uint64_t reserved_28_31:4;
867 uint64_t grp:4;
868 uint64_t reserved_23_23:1;
869 uint64_t qos:3;
870 uint64_t reserved_18_19:2;
871 uint64_t match_type:2;
872 uint64_t match_value:16;
873 } cn30xx;
874 struct cvmx_pip_qos_watchx_cn30xx cn31xx;
875 struct cvmx_pip_qos_watchx_cn30xx cn38xx;
876 struct cvmx_pip_qos_watchx_cn30xx cn38xxp2;
877 struct cvmx_pip_qos_watchx_s cn50xx;
878 struct cvmx_pip_qos_watchx_s cn52xx;
879 struct cvmx_pip_qos_watchx_s cn52xxp1;
880 struct cvmx_pip_qos_watchx_s cn56xx;
881 struct cvmx_pip_qos_watchx_s cn56xxp1;
882 struct cvmx_pip_qos_watchx_cn30xx cn58xx;
883 struct cvmx_pip_qos_watchx_cn30xx cn58xxp1;
884};
885
886union cvmx_pip_raw_word {
887 uint64_t u64;
888 struct cvmx_pip_raw_word_s {
889 uint64_t reserved_56_63:8;
890 uint64_t word:56;
891 } s;
892 struct cvmx_pip_raw_word_s cn30xx;
893 struct cvmx_pip_raw_word_s cn31xx;
894 struct cvmx_pip_raw_word_s cn38xx;
895 struct cvmx_pip_raw_word_s cn38xxp2;
896 struct cvmx_pip_raw_word_s cn50xx;
897 struct cvmx_pip_raw_word_s cn52xx;
898 struct cvmx_pip_raw_word_s cn52xxp1;
899 struct cvmx_pip_raw_word_s cn56xx;
900 struct cvmx_pip_raw_word_s cn56xxp1;
901 struct cvmx_pip_raw_word_s cn58xx;
902 struct cvmx_pip_raw_word_s cn58xxp1;
903};
904
905union cvmx_pip_sft_rst {
906 uint64_t u64;
907 struct cvmx_pip_sft_rst_s {
908 uint64_t reserved_1_63:63;
909 uint64_t rst:1;
910 } s;
911 struct cvmx_pip_sft_rst_s cn30xx;
912 struct cvmx_pip_sft_rst_s cn31xx;
913 struct cvmx_pip_sft_rst_s cn38xx;
914 struct cvmx_pip_sft_rst_s cn50xx;
915 struct cvmx_pip_sft_rst_s cn52xx;
916 struct cvmx_pip_sft_rst_s cn52xxp1;
917 struct cvmx_pip_sft_rst_s cn56xx;
918 struct cvmx_pip_sft_rst_s cn56xxp1;
919 struct cvmx_pip_sft_rst_s cn58xx;
920 struct cvmx_pip_sft_rst_s cn58xxp1;
921};
922
923union cvmx_pip_stat0_prtx {
924 uint64_t u64;
925 struct cvmx_pip_stat0_prtx_s {
926 uint64_t drp_pkts:32;
927 uint64_t drp_octs:32;
928 } s;
929 struct cvmx_pip_stat0_prtx_s cn30xx;
930 struct cvmx_pip_stat0_prtx_s cn31xx;
931 struct cvmx_pip_stat0_prtx_s cn38xx;
932 struct cvmx_pip_stat0_prtx_s cn38xxp2;
933 struct cvmx_pip_stat0_prtx_s cn50xx;
934 struct cvmx_pip_stat0_prtx_s cn52xx;
935 struct cvmx_pip_stat0_prtx_s cn52xxp1;
936 struct cvmx_pip_stat0_prtx_s cn56xx;
937 struct cvmx_pip_stat0_prtx_s cn56xxp1;
938 struct cvmx_pip_stat0_prtx_s cn58xx;
939 struct cvmx_pip_stat0_prtx_s cn58xxp1;
940};
941
942union cvmx_pip_stat1_prtx {
943 uint64_t u64;
944 struct cvmx_pip_stat1_prtx_s {
945 uint64_t reserved_48_63:16;
946 uint64_t octs:48;
947 } s;
948 struct cvmx_pip_stat1_prtx_s cn30xx;
949 struct cvmx_pip_stat1_prtx_s cn31xx;
950 struct cvmx_pip_stat1_prtx_s cn38xx;
951 struct cvmx_pip_stat1_prtx_s cn38xxp2;
952 struct cvmx_pip_stat1_prtx_s cn50xx;
953 struct cvmx_pip_stat1_prtx_s cn52xx;
954 struct cvmx_pip_stat1_prtx_s cn52xxp1;
955 struct cvmx_pip_stat1_prtx_s cn56xx;
956 struct cvmx_pip_stat1_prtx_s cn56xxp1;
957 struct cvmx_pip_stat1_prtx_s cn58xx;
958 struct cvmx_pip_stat1_prtx_s cn58xxp1;
959};
960
961union cvmx_pip_stat2_prtx {
962 uint64_t u64;
963 struct cvmx_pip_stat2_prtx_s {
964 uint64_t pkts:32;
965 uint64_t raw:32;
966 } s;
967 struct cvmx_pip_stat2_prtx_s cn30xx;
968 struct cvmx_pip_stat2_prtx_s cn31xx;
969 struct cvmx_pip_stat2_prtx_s cn38xx;
970 struct cvmx_pip_stat2_prtx_s cn38xxp2;
971 struct cvmx_pip_stat2_prtx_s cn50xx;
972 struct cvmx_pip_stat2_prtx_s cn52xx;
973 struct cvmx_pip_stat2_prtx_s cn52xxp1;
974 struct cvmx_pip_stat2_prtx_s cn56xx;
975 struct cvmx_pip_stat2_prtx_s cn56xxp1;
976 struct cvmx_pip_stat2_prtx_s cn58xx;
977 struct cvmx_pip_stat2_prtx_s cn58xxp1;
978};
979
980union cvmx_pip_stat3_prtx {
981 uint64_t u64;
982 struct cvmx_pip_stat3_prtx_s {
983 uint64_t bcst:32;
984 uint64_t mcst:32;
985 } s;
986 struct cvmx_pip_stat3_prtx_s cn30xx;
987 struct cvmx_pip_stat3_prtx_s cn31xx;
988 struct cvmx_pip_stat3_prtx_s cn38xx;
989 struct cvmx_pip_stat3_prtx_s cn38xxp2;
990 struct cvmx_pip_stat3_prtx_s cn50xx;
991 struct cvmx_pip_stat3_prtx_s cn52xx;
992 struct cvmx_pip_stat3_prtx_s cn52xxp1;
993 struct cvmx_pip_stat3_prtx_s cn56xx;
994 struct cvmx_pip_stat3_prtx_s cn56xxp1;
995 struct cvmx_pip_stat3_prtx_s cn58xx;
996 struct cvmx_pip_stat3_prtx_s cn58xxp1;
997};
998
999union cvmx_pip_stat4_prtx {
1000 uint64_t u64;
1001 struct cvmx_pip_stat4_prtx_s {
1002 uint64_t h65to127:32;
1003 uint64_t h64:32;
1004 } s;
1005 struct cvmx_pip_stat4_prtx_s cn30xx;
1006 struct cvmx_pip_stat4_prtx_s cn31xx;
1007 struct cvmx_pip_stat4_prtx_s cn38xx;
1008 struct cvmx_pip_stat4_prtx_s cn38xxp2;
1009 struct cvmx_pip_stat4_prtx_s cn50xx;
1010 struct cvmx_pip_stat4_prtx_s cn52xx;
1011 struct cvmx_pip_stat4_prtx_s cn52xxp1;
1012 struct cvmx_pip_stat4_prtx_s cn56xx;
1013 struct cvmx_pip_stat4_prtx_s cn56xxp1;
1014 struct cvmx_pip_stat4_prtx_s cn58xx;
1015 struct cvmx_pip_stat4_prtx_s cn58xxp1;
1016};
1017
1018union cvmx_pip_stat5_prtx {
1019 uint64_t u64;
1020 struct cvmx_pip_stat5_prtx_s {
1021 uint64_t h256to511:32;
1022 uint64_t h128to255:32;
1023 } s;
1024 struct cvmx_pip_stat5_prtx_s cn30xx;
1025 struct cvmx_pip_stat5_prtx_s cn31xx;
1026 struct cvmx_pip_stat5_prtx_s cn38xx;
1027 struct cvmx_pip_stat5_prtx_s cn38xxp2;
1028 struct cvmx_pip_stat5_prtx_s cn50xx;
1029 struct cvmx_pip_stat5_prtx_s cn52xx;
1030 struct cvmx_pip_stat5_prtx_s cn52xxp1;
1031 struct cvmx_pip_stat5_prtx_s cn56xx;
1032 struct cvmx_pip_stat5_prtx_s cn56xxp1;
1033 struct cvmx_pip_stat5_prtx_s cn58xx;
1034 struct cvmx_pip_stat5_prtx_s cn58xxp1;
1035};
1036
1037union cvmx_pip_stat6_prtx {
1038 uint64_t u64;
1039 struct cvmx_pip_stat6_prtx_s {
1040 uint64_t h1024to1518:32;
1041 uint64_t h512to1023:32;
1042 } s;
1043 struct cvmx_pip_stat6_prtx_s cn30xx;
1044 struct cvmx_pip_stat6_prtx_s cn31xx;
1045 struct cvmx_pip_stat6_prtx_s cn38xx;
1046 struct cvmx_pip_stat6_prtx_s cn38xxp2;
1047 struct cvmx_pip_stat6_prtx_s cn50xx;
1048 struct cvmx_pip_stat6_prtx_s cn52xx;
1049 struct cvmx_pip_stat6_prtx_s cn52xxp1;
1050 struct cvmx_pip_stat6_prtx_s cn56xx;
1051 struct cvmx_pip_stat6_prtx_s cn56xxp1;
1052 struct cvmx_pip_stat6_prtx_s cn58xx;
1053 struct cvmx_pip_stat6_prtx_s cn58xxp1;
1054};
1055
1056union cvmx_pip_stat7_prtx {
1057 uint64_t u64;
1058 struct cvmx_pip_stat7_prtx_s {
1059 uint64_t fcs:32;
1060 uint64_t h1519:32;
1061 } s;
1062 struct cvmx_pip_stat7_prtx_s cn30xx;
1063 struct cvmx_pip_stat7_prtx_s cn31xx;
1064 struct cvmx_pip_stat7_prtx_s cn38xx;
1065 struct cvmx_pip_stat7_prtx_s cn38xxp2;
1066 struct cvmx_pip_stat7_prtx_s cn50xx;
1067 struct cvmx_pip_stat7_prtx_s cn52xx;
1068 struct cvmx_pip_stat7_prtx_s cn52xxp1;
1069 struct cvmx_pip_stat7_prtx_s cn56xx;
1070 struct cvmx_pip_stat7_prtx_s cn56xxp1;
1071 struct cvmx_pip_stat7_prtx_s cn58xx;
1072 struct cvmx_pip_stat7_prtx_s cn58xxp1;
1073};
1074
1075union cvmx_pip_stat8_prtx {
1076 uint64_t u64;
1077 struct cvmx_pip_stat8_prtx_s {
1078 uint64_t frag:32;
1079 uint64_t undersz:32;
1080 } s;
1081 struct cvmx_pip_stat8_prtx_s cn30xx;
1082 struct cvmx_pip_stat8_prtx_s cn31xx;
1083 struct cvmx_pip_stat8_prtx_s cn38xx;
1084 struct cvmx_pip_stat8_prtx_s cn38xxp2;
1085 struct cvmx_pip_stat8_prtx_s cn50xx;
1086 struct cvmx_pip_stat8_prtx_s cn52xx;
1087 struct cvmx_pip_stat8_prtx_s cn52xxp1;
1088 struct cvmx_pip_stat8_prtx_s cn56xx;
1089 struct cvmx_pip_stat8_prtx_s cn56xxp1;
1090 struct cvmx_pip_stat8_prtx_s cn58xx;
1091 struct cvmx_pip_stat8_prtx_s cn58xxp1;
1092};
1093
1094union cvmx_pip_stat9_prtx {
1095 uint64_t u64;
1096 struct cvmx_pip_stat9_prtx_s {
1097 uint64_t jabber:32;
1098 uint64_t oversz:32;
1099 } s;
1100 struct cvmx_pip_stat9_prtx_s cn30xx;
1101 struct cvmx_pip_stat9_prtx_s cn31xx;
1102 struct cvmx_pip_stat9_prtx_s cn38xx;
1103 struct cvmx_pip_stat9_prtx_s cn38xxp2;
1104 struct cvmx_pip_stat9_prtx_s cn50xx;
1105 struct cvmx_pip_stat9_prtx_s cn52xx;
1106 struct cvmx_pip_stat9_prtx_s cn52xxp1;
1107 struct cvmx_pip_stat9_prtx_s cn56xx;
1108 struct cvmx_pip_stat9_prtx_s cn56xxp1;
1109 struct cvmx_pip_stat9_prtx_s cn58xx;
1110 struct cvmx_pip_stat9_prtx_s cn58xxp1;
1111};
1112
1113union cvmx_pip_stat_ctl {
1114 uint64_t u64;
1115 struct cvmx_pip_stat_ctl_s {
1116 uint64_t reserved_1_63:63;
1117 uint64_t rdclr:1;
1118 } s;
1119 struct cvmx_pip_stat_ctl_s cn30xx;
1120 struct cvmx_pip_stat_ctl_s cn31xx;
1121 struct cvmx_pip_stat_ctl_s cn38xx;
1122 struct cvmx_pip_stat_ctl_s cn38xxp2;
1123 struct cvmx_pip_stat_ctl_s cn50xx;
1124 struct cvmx_pip_stat_ctl_s cn52xx;
1125 struct cvmx_pip_stat_ctl_s cn52xxp1;
1126 struct cvmx_pip_stat_ctl_s cn56xx;
1127 struct cvmx_pip_stat_ctl_s cn56xxp1;
1128 struct cvmx_pip_stat_ctl_s cn58xx;
1129 struct cvmx_pip_stat_ctl_s cn58xxp1;
1130};
1131
1132union cvmx_pip_stat_inb_errsx {
1133 uint64_t u64;
1134 struct cvmx_pip_stat_inb_errsx_s {
1135 uint64_t reserved_16_63:48;
1136 uint64_t errs:16;
1137 } s;
1138 struct cvmx_pip_stat_inb_errsx_s cn30xx;
1139 struct cvmx_pip_stat_inb_errsx_s cn31xx;
1140 struct cvmx_pip_stat_inb_errsx_s cn38xx;
1141 struct cvmx_pip_stat_inb_errsx_s cn38xxp2;
1142 struct cvmx_pip_stat_inb_errsx_s cn50xx;
1143 struct cvmx_pip_stat_inb_errsx_s cn52xx;
1144 struct cvmx_pip_stat_inb_errsx_s cn52xxp1;
1145 struct cvmx_pip_stat_inb_errsx_s cn56xx;
1146 struct cvmx_pip_stat_inb_errsx_s cn56xxp1;
1147 struct cvmx_pip_stat_inb_errsx_s cn58xx;
1148 struct cvmx_pip_stat_inb_errsx_s cn58xxp1;
1149};
1150
1151union cvmx_pip_stat_inb_octsx {
1152 uint64_t u64;
1153 struct cvmx_pip_stat_inb_octsx_s {
1154 uint64_t reserved_48_63:16;
1155 uint64_t octs:48;
1156 } s;
1157 struct cvmx_pip_stat_inb_octsx_s cn30xx;
1158 struct cvmx_pip_stat_inb_octsx_s cn31xx;
1159 struct cvmx_pip_stat_inb_octsx_s cn38xx;
1160 struct cvmx_pip_stat_inb_octsx_s cn38xxp2;
1161 struct cvmx_pip_stat_inb_octsx_s cn50xx;
1162 struct cvmx_pip_stat_inb_octsx_s cn52xx;
1163 struct cvmx_pip_stat_inb_octsx_s cn52xxp1;
1164 struct cvmx_pip_stat_inb_octsx_s cn56xx;
1165 struct cvmx_pip_stat_inb_octsx_s cn56xxp1;
1166 struct cvmx_pip_stat_inb_octsx_s cn58xx;
1167 struct cvmx_pip_stat_inb_octsx_s cn58xxp1;
1168};
1169
1170union cvmx_pip_stat_inb_pktsx {
1171 uint64_t u64;
1172 struct cvmx_pip_stat_inb_pktsx_s {
1173 uint64_t reserved_32_63:32;
1174 uint64_t pkts:32;
1175 } s;
1176 struct cvmx_pip_stat_inb_pktsx_s cn30xx;
1177 struct cvmx_pip_stat_inb_pktsx_s cn31xx;
1178 struct cvmx_pip_stat_inb_pktsx_s cn38xx;
1179 struct cvmx_pip_stat_inb_pktsx_s cn38xxp2;
1180 struct cvmx_pip_stat_inb_pktsx_s cn50xx;
1181 struct cvmx_pip_stat_inb_pktsx_s cn52xx;
1182 struct cvmx_pip_stat_inb_pktsx_s cn52xxp1;
1183 struct cvmx_pip_stat_inb_pktsx_s cn56xx;
1184 struct cvmx_pip_stat_inb_pktsx_s cn56xxp1;
1185 struct cvmx_pip_stat_inb_pktsx_s cn58xx;
1186 struct cvmx_pip_stat_inb_pktsx_s cn58xxp1;
1187};
1188
1189union cvmx_pip_tag_incx {
1190 uint64_t u64;
1191 struct cvmx_pip_tag_incx_s {
1192 uint64_t reserved_8_63:56;
1193 uint64_t en:8;
1194 } s;
1195 struct cvmx_pip_tag_incx_s cn30xx;
1196 struct cvmx_pip_tag_incx_s cn31xx;
1197 struct cvmx_pip_tag_incx_s cn38xx;
1198 struct cvmx_pip_tag_incx_s cn38xxp2;
1199 struct cvmx_pip_tag_incx_s cn50xx;
1200 struct cvmx_pip_tag_incx_s cn52xx;
1201 struct cvmx_pip_tag_incx_s cn52xxp1;
1202 struct cvmx_pip_tag_incx_s cn56xx;
1203 struct cvmx_pip_tag_incx_s cn56xxp1;
1204 struct cvmx_pip_tag_incx_s cn58xx;
1205 struct cvmx_pip_tag_incx_s cn58xxp1;
1206};
1207
1208union cvmx_pip_tag_mask {
1209 uint64_t u64;
1210 struct cvmx_pip_tag_mask_s {
1211 uint64_t reserved_16_63:48;
1212 uint64_t mask:16;
1213 } s;
1214 struct cvmx_pip_tag_mask_s cn30xx;
1215 struct cvmx_pip_tag_mask_s cn31xx;
1216 struct cvmx_pip_tag_mask_s cn38xx;
1217 struct cvmx_pip_tag_mask_s cn38xxp2;
1218 struct cvmx_pip_tag_mask_s cn50xx;
1219 struct cvmx_pip_tag_mask_s cn52xx;
1220 struct cvmx_pip_tag_mask_s cn52xxp1;
1221 struct cvmx_pip_tag_mask_s cn56xx;
1222 struct cvmx_pip_tag_mask_s cn56xxp1;
1223 struct cvmx_pip_tag_mask_s cn58xx;
1224 struct cvmx_pip_tag_mask_s cn58xxp1;
1225};
1226
1227union cvmx_pip_tag_secret {
1228 uint64_t u64;
1229 struct cvmx_pip_tag_secret_s {
1230 uint64_t reserved_32_63:32;
1231 uint64_t dst:16;
1232 uint64_t src:16;
1233 } s;
1234 struct cvmx_pip_tag_secret_s cn30xx;
1235 struct cvmx_pip_tag_secret_s cn31xx;
1236 struct cvmx_pip_tag_secret_s cn38xx;
1237 struct cvmx_pip_tag_secret_s cn38xxp2;
1238 struct cvmx_pip_tag_secret_s cn50xx;
1239 struct cvmx_pip_tag_secret_s cn52xx;
1240 struct cvmx_pip_tag_secret_s cn52xxp1;
1241 struct cvmx_pip_tag_secret_s cn56xx;
1242 struct cvmx_pip_tag_secret_s cn56xxp1;
1243 struct cvmx_pip_tag_secret_s cn58xx;
1244 struct cvmx_pip_tag_secret_s cn58xxp1;
1245};
1246
1247union cvmx_pip_todo_entry {
1248 uint64_t u64;
1249 struct cvmx_pip_todo_entry_s {
1250 uint64_t val:1;
1251 uint64_t reserved_62_62:1;
1252 uint64_t entry:62;
1253 } s;
1254 struct cvmx_pip_todo_entry_s cn30xx;
1255 struct cvmx_pip_todo_entry_s cn31xx;
1256 struct cvmx_pip_todo_entry_s cn38xx;
1257 struct cvmx_pip_todo_entry_s cn38xxp2;
1258 struct cvmx_pip_todo_entry_s cn50xx;
1259 struct cvmx_pip_todo_entry_s cn52xx;
1260 struct cvmx_pip_todo_entry_s cn52xxp1;
1261 struct cvmx_pip_todo_entry_s cn56xx;
1262 struct cvmx_pip_todo_entry_s cn56xxp1;
1263 struct cvmx_pip_todo_entry_s cn58xx;
1264 struct cvmx_pip_todo_entry_s cn58xxp1;
1265};
1266
1267#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
new file mode 100644
index 00000000000..78dbce8f2c5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pip.h
@@ -0,0 +1,524 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Interface to the hardware Packet Input Processing unit.
30 *
31 */
32
33#ifndef __CVMX_PIP_H__
34#define __CVMX_PIP_H__
35
36#include "cvmx-wqe.h"
37#include "cvmx-fpa.h"
38#include "cvmx-pip-defs.h"
39
40#define CVMX_PIP_NUM_INPUT_PORTS 40
41#define CVMX_PIP_NUM_WATCHERS 4
42
43/*
44 * Encodes the different error and exception codes
45 */
46typedef enum {
47 CVMX_PIP_L4_NO_ERR = 0ull,
48 /*
49 * 1 = TCP (UDP) packet not long enough to cover TCP (UDP)
50 * header
51 */
52 CVMX_PIP_L4_MAL_ERR = 1ull,
53 /* 2 = TCP/UDP checksum failure */
54 CVMX_PIP_CHK_ERR = 2ull,
55 /*
56 * 3 = TCP/UDP length check (TCP/UDP length does not match IP
57 * length).
58 */
59 CVMX_PIP_L4_LENGTH_ERR = 3ull,
60 /* 4 = illegal TCP/UDP port (either source or dest port is zero) */
61 CVMX_PIP_BAD_PRT_ERR = 4ull,
62 /* 8 = TCP flags = FIN only */
63 CVMX_PIP_TCP_FLG8_ERR = 8ull,
64 /* 9 = TCP flags = 0 */
65 CVMX_PIP_TCP_FLG9_ERR = 9ull,
66 /* 10 = TCP flags = FIN+RST+* */
67 CVMX_PIP_TCP_FLG10_ERR = 10ull,
68 /* 11 = TCP flags = SYN+URG+* */
69 CVMX_PIP_TCP_FLG11_ERR = 11ull,
70 /* 12 = TCP flags = SYN+RST+* */
71 CVMX_PIP_TCP_FLG12_ERR = 12ull,
72 /* 13 = TCP flags = SYN+FIN+* */
73 CVMX_PIP_TCP_FLG13_ERR = 13ull
74} cvmx_pip_l4_err_t;
75
76typedef enum {
77
78 CVMX_PIP_IP_NO_ERR = 0ull,
79 /* 1 = not IPv4 or IPv6 */
80 CVMX_PIP_NOT_IP = 1ull,
81 /* 2 = IPv4 header checksum violation */
82 CVMX_PIP_IPV4_HDR_CHK = 2ull,
83 /* 3 = malformed (packet not long enough to cover IP hdr) */
84 CVMX_PIP_IP_MAL_HDR = 3ull,
85 /* 4 = malformed (packet not long enough to cover len in IP hdr) */
86 CVMX_PIP_IP_MAL_PKT = 4ull,
87 /* 5 = TTL / hop count equal zero */
88 CVMX_PIP_TTL_HOP = 5ull,
89 /* 6 = IPv4 options / IPv6 early extension headers */
90 CVMX_PIP_OPTS = 6ull
91} cvmx_pip_ip_exc_t;
92
93/**
94 * NOTES
95 * late collision (data received before collision)
96 * late collisions cannot be detected by the receiver
97 * they would appear as JAM bits which would appear as bad FCS
98 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
99 */
100typedef enum {
101 /* No error */
102 CVMX_PIP_RX_NO_ERR = 0ull,
103 /* RGM+SPI 1 = partially received packet (buffering/bandwidth
104 * not adequate) */
105 CVMX_PIP_PARTIAL_ERR = 1ull,
106 /* RGM+SPI 2 = receive packet too large and truncated */
107 CVMX_PIP_JABBER_ERR = 2ull,
108 /*
109 * RGM 3 = max frame error (pkt len > max frame len) (with FCS
110 * error)
111 */
112 CVMX_PIP_OVER_FCS_ERR = 3ull,
113 /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
114 CVMX_PIP_OVER_ERR = 4ull,
115 /*
116 * RGM 5 = nibble error (data not byte multiple - 100M and 10M
117 * only)
118 */
119 CVMX_PIP_ALIGN_ERR = 5ull,
120 /*
121 * RGM 6 = min frame error (pkt len < min frame len) (with FCS
122 * error)
123 */
124 CVMX_PIP_UNDER_FCS_ERR = 6ull,
125 /* RGM 7 = FCS error */
126 CVMX_PIP_GMX_FCS_ERR = 7ull,
127 /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
128 CVMX_PIP_UNDER_ERR = 8ull,
129 /* RGM 9 = Frame carrier extend error */
130 CVMX_PIP_EXTEND_ERR = 9ull,
131 /*
132 * RGM 10 = length mismatch (len did not match len in L2
133 * length/type)
134 */
135 CVMX_PIP_LENGTH_ERR = 10ull,
136 /* RGM 11 = Frame error (some or all data bits marked err) */
137 CVMX_PIP_DAT_ERR = 11ull,
138 /* SPI 11 = DIP4 error */
139 CVMX_PIP_DIP_ERR = 11ull,
140 /*
141 * RGM 12 = packet was not large enough to pass the skipper -
142 * no inspection could occur.
143 */
144 CVMX_PIP_SKIP_ERR = 12ull,
145 /*
146 * RGM 13 = studder error (data not repeated - 100M and 10M
147 * only)
148 */
149 CVMX_PIP_NIBBLE_ERR = 13ull,
150 /* RGM+SPI 16 = FCS error */
151 CVMX_PIP_PIP_FCS = 16L,
152 /*
153 * RGM+SPI+PCI 17 = packet was not large enough to pass the
154 * skipper - no inspection could occur.
155 */
156 CVMX_PIP_PIP_SKIP_ERR = 17L,
157 /*
158 * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to
159 * cover L2 hdr).
160 */
161 CVMX_PIP_PIP_L2_MAL_HDR = 18L
162 /*
163 * NOTES: xx = late collision (data received before collision)
164 * late collisions cannot be detected by the receiver
165 * they would appear as JAM bits which would appear as
166 * bad FCS or carrier extend error which is
167 * CVMX_PIP_EXTEND_ERR
168 */
169} cvmx_pip_rcv_err_t;
170
171/**
172 * This defines the err_code field errors in the work Q entry
173 */
174typedef union {
175 cvmx_pip_l4_err_t l4_err;
176 cvmx_pip_ip_exc_t ip_exc;
177 cvmx_pip_rcv_err_t rcv_err;
178} cvmx_pip_err_t;
179
180/**
181 * Status statistics for a port
182 */
183typedef struct {
184 /* Inbound octets marked to be dropped by the IPD */
185 uint32_t dropped_octets;
186 /* Inbound packets marked to be dropped by the IPD */
187 uint32_t dropped_packets;
188 /* RAW PCI Packets received by PIP per port */
189 uint32_t pci_raw_packets;
190 /* Number of octets processed by PIP */
191 uint32_t octets;
192 /* Number of packets processed by PIP */
193 uint32_t packets;
194 /*
195 * Number of indentified L2 multicast packets. Does not
196 * include broadcast packets. Only includes packets whose
197 * parse mode is SKIP_TO_L2
198 */
199 uint32_t multicast_packets;
200 /*
201 * Number of indentified L2 broadcast packets. Does not
202 * include multicast packets. Only includes packets whose
203 * parse mode is SKIP_TO_L2
204 */
205 uint32_t broadcast_packets;
206 /* Number of 64B packets */
207 uint32_t len_64_packets;
208 /* Number of 65-127B packets */
209 uint32_t len_65_127_packets;
210 /* Number of 128-255B packets */
211 uint32_t len_128_255_packets;
212 /* Number of 256-511B packets */
213 uint32_t len_256_511_packets;
214 /* Number of 512-1023B packets */
215 uint32_t len_512_1023_packets;
216 /* Number of 1024-1518B packets */
217 uint32_t len_1024_1518_packets;
218 /* Number of 1519-max packets */
219 uint32_t len_1519_max_packets;
220 /* Number of packets with FCS or Align opcode errors */
221 uint32_t fcs_align_err_packets;
222 /* Number of packets with length < min */
223 uint32_t runt_packets;
224 /* Number of packets with length < min and FCS error */
225 uint32_t runt_crc_packets;
226 /* Number of packets with length > max */
227 uint32_t oversize_packets;
228 /* Number of packets with length > max and FCS error */
229 uint32_t oversize_crc_packets;
230 /* Number of packets without GMX/SPX/PCI errors received by PIP */
231 uint32_t inb_packets;
232 /*
233 * Total number of octets from all packets received by PIP,
234 * including CRC
235 */
236 uint64_t inb_octets;
237 /* Number of packets with GMX/SPX/PCI errors received by PIP */
238 uint16_t inb_errors;
239} cvmx_pip_port_status_t;
240
241/**
242 * Definition of the PIP custom header that can be prepended
243 * to a packet by external hardware.
244 */
245typedef union {
246 uint64_t u64;
247 struct {
248 /*
249 * Documented as R - Set if the Packet is RAWFULL. If
250 * set, this header must be the full 8 bytes.
251 */
252 uint64_t rawfull:1;
253 /* Must be zero */
254 uint64_t reserved0:5;
255 /* PIP parse mode for this packet */
256 uint64_t parse_mode:2;
257 /* Must be zero */
258 uint64_t reserved1:1;
259 /*
260 * Skip amount, including this header, to the
261 * beginning of the packet
262 */
263 uint64_t skip_len:7;
264 /* Must be zero */
265 uint64_t reserved2:6;
266 /* POW input queue for this packet */
267 uint64_t qos:3;
268 /* POW input group for this packet */
269 uint64_t grp:4;
270 /*
271 * Flag to store this packet in the work queue entry,
272 * if possible
273 */
274 uint64_t rs:1;
275 /* POW input tag type */
276 uint64_t tag_type:2;
277 /* POW input tag */
278 uint64_t tag:32;
279 } s;
280} cvmx_pip_pkt_inst_hdr_t;
281
282/* CSR typedefs have been moved to cvmx-csr-*.h */
283
284/**
285 * Configure an ethernet input port
286 *
287 * @port_num: Port number to configure
288 * @port_cfg: Port hardware configuration
289 * @port_tag_cfg:
290 * Port POW tagging configuration
291 */
292static inline void cvmx_pip_config_port(uint64_t port_num,
293 union cvmx_pip_prt_cfgx port_cfg,
294 union cvmx_pip_prt_tagx port_tag_cfg)
295{
296 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
297 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
298}
299#if 0
300/**
301 * @deprecated This function is a thin wrapper around the Pass1 version
302 * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
303 * setting the group that is incompatible with this function,
304 * the preferred upgrade path is to use the CSR directly.
305 *
306 * Configure the global QoS packet watchers. Each watcher is
307 * capable of matching a field in a packet to determine the
308 * QoS queue for scheduling.
309 *
310 * @watcher: Watcher number to configure (0 - 3).
311 * @match_type: Watcher match type
312 * @match_value:
313 * Value the watcher will match against
314 * @qos: QoS queue for packets matching this watcher
315 */
316static inline void cvmx_pip_config_watcher(uint64_t watcher,
317 cvmx_pip_qos_watch_types match_type,
318 uint64_t match_value, uint64_t qos)
319{
320 cvmx_pip_port_watcher_cfg_t watcher_config;
321
322 watcher_config.u64 = 0;
323 watcher_config.s.match_type = match_type;
324 watcher_config.s.match_value = match_value;
325 watcher_config.s.qos = qos;
326
327 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
328}
329#endif
330/**
331 * Configure the VLAN priority to QoS queue mapping.
332 *
333 * @vlan_priority:
334 * VLAN priority (0-7)
335 * @qos: QoS queue for packets matching this watcher
336 */
337static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
338 uint64_t qos)
339{
340 union cvmx_pip_qos_vlanx pip_qos_vlanx;
341 pip_qos_vlanx.u64 = 0;
342 pip_qos_vlanx.s.qos = qos;
343 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
344}
345
346/**
347 * Configure the Diffserv to QoS queue mapping.
348 *
349 * @diffserv: Diffserv field value (0-63)
350 * @qos: QoS queue for packets matching this watcher
351 */
352static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
353{
354 union cvmx_pip_qos_diffx pip_qos_diffx;
355 pip_qos_diffx.u64 = 0;
356 pip_qos_diffx.s.qos = qos;
357 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
358}
359
360/**
361 * Get the status counters for a port.
362 *
363 * @port_num: Port number to get statistics for.
364 * @clear: Set to 1 to clear the counters after they are read
365 * @status: Where to put the results.
366 */
367static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
368 cvmx_pip_port_status_t *status)
369{
370 union cvmx_pip_stat_ctl pip_stat_ctl;
371 union cvmx_pip_stat0_prtx stat0;
372 union cvmx_pip_stat1_prtx stat1;
373 union cvmx_pip_stat2_prtx stat2;
374 union cvmx_pip_stat3_prtx stat3;
375 union cvmx_pip_stat4_prtx stat4;
376 union cvmx_pip_stat5_prtx stat5;
377 union cvmx_pip_stat6_prtx stat6;
378 union cvmx_pip_stat7_prtx stat7;
379 union cvmx_pip_stat8_prtx stat8;
380 union cvmx_pip_stat9_prtx stat9;
381 union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx;
382 union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx;
383 union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx;
384
385 pip_stat_ctl.u64 = 0;
386 pip_stat_ctl.s.rdclr = clear;
387 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
388
389 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
390 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
391 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
392 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
393 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
394 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
395 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
396 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
397 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
398 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
399 pip_stat_inb_pktsx.u64 =
400 cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
401 pip_stat_inb_octsx.u64 =
402 cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
403 pip_stat_inb_errsx.u64 =
404 cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
405
406 status->dropped_octets = stat0.s.drp_octs;
407 status->dropped_packets = stat0.s.drp_pkts;
408 status->octets = stat1.s.octs;
409 status->pci_raw_packets = stat2.s.raw;
410 status->packets = stat2.s.pkts;
411 status->multicast_packets = stat3.s.mcst;
412 status->broadcast_packets = stat3.s.bcst;
413 status->len_64_packets = stat4.s.h64;
414 status->len_65_127_packets = stat4.s.h65to127;
415 status->len_128_255_packets = stat5.s.h128to255;
416 status->len_256_511_packets = stat5.s.h256to511;
417 status->len_512_1023_packets = stat6.s.h512to1023;
418 status->len_1024_1518_packets = stat6.s.h1024to1518;
419 status->len_1519_max_packets = stat7.s.h1519;
420 status->fcs_align_err_packets = stat7.s.fcs;
421 status->runt_packets = stat8.s.undersz;
422 status->runt_crc_packets = stat8.s.frag;
423 status->oversize_packets = stat9.s.oversz;
424 status->oversize_crc_packets = stat9.s.jabber;
425 status->inb_packets = pip_stat_inb_pktsx.s.pkts;
426 status->inb_octets = pip_stat_inb_octsx.s.octs;
427 status->inb_errors = pip_stat_inb_errsx.s.errs;
428
429 if (cvmx_octeon_is_pass1()) {
430 /*
431 * Kludge to fix Octeon Pass 1 errata - Drop counts
432 * don't work.
433 */
434 if (status->inb_packets > status->packets)
435 status->dropped_packets =
436 status->inb_packets - status->packets;
437 else
438 status->dropped_packets = 0;
439 if (status->inb_octets - status->inb_packets * 4 >
440 status->octets)
441 status->dropped_octets =
442 status->inb_octets - status->inb_packets * 4 -
443 status->octets;
444 else
445 status->dropped_octets = 0;
446 }
447}
448
449/**
450 * Configure the hardware CRC engine
451 *
452 * @interface: Interface to configure (0 or 1)
453 * @invert_result:
454 * Invert the result of the CRC
455 * @reflect: Reflect
456 * @initialization_vector:
457 * CRC initialization vector
458 */
459static inline void cvmx_pip_config_crc(uint64_t interface,
460 uint64_t invert_result, uint64_t reflect,
461 uint32_t initialization_vector)
462{
463 if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
464 union cvmx_pip_crc_ctlx config;
465 union cvmx_pip_crc_ivx pip_crc_ivx;
466
467 config.u64 = 0;
468 config.s.invres = invert_result;
469 config.s.reflect = reflect;
470 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
471
472 pip_crc_ivx.u64 = 0;
473 pip_crc_ivx.s.iv = initialization_vector;
474 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
475 }
476}
477
478/**
479 * Clear all bits in a tag mask. This should be called on
480 * startup before any calls to cvmx_pip_tag_mask_set. Each bit
481 * set in the final mask represent a byte used in the packet for
482 * tag generation.
483 *
484 * @mask_index: Which tag mask to clear (0..3)
485 */
486static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
487{
488 uint64_t index;
489 union cvmx_pip_tag_incx pip_tag_incx;
490 pip_tag_incx.u64 = 0;
491 pip_tag_incx.s.en = 0;
492 for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
493 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
494}
495
496/**
497 * Sets a range of bits in the tag mask. The tag mask is used
498 * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
499 * There are four separate masks that can be configured.
500 *
501 * @mask_index: Which tag mask to modify (0..3)
502 * @offset: Offset into the bitmask to set bits at. Use the GCC macro
503 * offsetof() to determine the offsets into packet headers.
504 * For example, offsetof(ethhdr, protocol) returns the offset
505 * of the ethernet protocol field. The bitmask selects which
506 * bytes to include the the tag, with bit offset X selecting
507 * byte at offset X from the beginning of the packet data.
508 * @len: Number of bytes to include. Usually this is the sizeof()
509 * the field.
510 */
511static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
512 uint64_t len)
513{
514 while (len--) {
515 union cvmx_pip_tag_incx pip_tag_incx;
516 uint64_t index = mask_index * 16 + offset / 8;
517 pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
518 pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
519 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
520 offset++;
521 }
522}
523
524#endif /* __CVMX_PIP_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
new file mode 100644
index 00000000000..50e779cf1ad
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
@@ -0,0 +1,1133 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PKO_DEFS_H__
29#define __CVMX_PKO_DEFS_H__
30
31#define CVMX_PKO_MEM_COUNT0 \
32 CVMX_ADD_IO_SEG(0x0001180050001080ull)
33#define CVMX_PKO_MEM_COUNT1 \
34 CVMX_ADD_IO_SEG(0x0001180050001088ull)
35#define CVMX_PKO_MEM_DEBUG0 \
36 CVMX_ADD_IO_SEG(0x0001180050001100ull)
37#define CVMX_PKO_MEM_DEBUG1 \
38 CVMX_ADD_IO_SEG(0x0001180050001108ull)
39#define CVMX_PKO_MEM_DEBUG10 \
40 CVMX_ADD_IO_SEG(0x0001180050001150ull)
41#define CVMX_PKO_MEM_DEBUG11 \
42 CVMX_ADD_IO_SEG(0x0001180050001158ull)
43#define CVMX_PKO_MEM_DEBUG12 \
44 CVMX_ADD_IO_SEG(0x0001180050001160ull)
45#define CVMX_PKO_MEM_DEBUG13 \
46 CVMX_ADD_IO_SEG(0x0001180050001168ull)
47#define CVMX_PKO_MEM_DEBUG14 \
48 CVMX_ADD_IO_SEG(0x0001180050001170ull)
49#define CVMX_PKO_MEM_DEBUG2 \
50 CVMX_ADD_IO_SEG(0x0001180050001110ull)
51#define CVMX_PKO_MEM_DEBUG3 \
52 CVMX_ADD_IO_SEG(0x0001180050001118ull)
53#define CVMX_PKO_MEM_DEBUG4 \
54 CVMX_ADD_IO_SEG(0x0001180050001120ull)
55#define CVMX_PKO_MEM_DEBUG5 \
56 CVMX_ADD_IO_SEG(0x0001180050001128ull)
57#define CVMX_PKO_MEM_DEBUG6 \
58 CVMX_ADD_IO_SEG(0x0001180050001130ull)
59#define CVMX_PKO_MEM_DEBUG7 \
60 CVMX_ADD_IO_SEG(0x0001180050001138ull)
61#define CVMX_PKO_MEM_DEBUG8 \
62 CVMX_ADD_IO_SEG(0x0001180050001140ull)
63#define CVMX_PKO_MEM_DEBUG9 \
64 CVMX_ADD_IO_SEG(0x0001180050001148ull)
65#define CVMX_PKO_MEM_PORT_PTRS \
66 CVMX_ADD_IO_SEG(0x0001180050001010ull)
67#define CVMX_PKO_MEM_PORT_QOS \
68 CVMX_ADD_IO_SEG(0x0001180050001018ull)
69#define CVMX_PKO_MEM_PORT_RATE0 \
70 CVMX_ADD_IO_SEG(0x0001180050001020ull)
71#define CVMX_PKO_MEM_PORT_RATE1 \
72 CVMX_ADD_IO_SEG(0x0001180050001028ull)
73#define CVMX_PKO_MEM_QUEUE_PTRS \
74 CVMX_ADD_IO_SEG(0x0001180050001000ull)
75#define CVMX_PKO_MEM_QUEUE_QOS \
76 CVMX_ADD_IO_SEG(0x0001180050001008ull)
77#define CVMX_PKO_REG_BIST_RESULT \
78 CVMX_ADD_IO_SEG(0x0001180050000080ull)
79#define CVMX_PKO_REG_CMD_BUF \
80 CVMX_ADD_IO_SEG(0x0001180050000010ull)
81#define CVMX_PKO_REG_CRC_CTLX(offset) \
82 CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8))
83#define CVMX_PKO_REG_CRC_ENABLE \
84 CVMX_ADD_IO_SEG(0x0001180050000020ull)
85#define CVMX_PKO_REG_CRC_IVX(offset) \
86 CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8))
87#define CVMX_PKO_REG_DEBUG0 \
88 CVMX_ADD_IO_SEG(0x0001180050000098ull)
89#define CVMX_PKO_REG_DEBUG1 \
90 CVMX_ADD_IO_SEG(0x00011800500000A0ull)
91#define CVMX_PKO_REG_DEBUG2 \
92 CVMX_ADD_IO_SEG(0x00011800500000A8ull)
93#define CVMX_PKO_REG_DEBUG3 \
94 CVMX_ADD_IO_SEG(0x00011800500000B0ull)
95#define CVMX_PKO_REG_ENGINE_INFLIGHT \
96 CVMX_ADD_IO_SEG(0x0001180050000050ull)
97#define CVMX_PKO_REG_ENGINE_THRESH \
98 CVMX_ADD_IO_SEG(0x0001180050000058ull)
99#define CVMX_PKO_REG_ERROR \
100 CVMX_ADD_IO_SEG(0x0001180050000088ull)
101#define CVMX_PKO_REG_FLAGS \
102 CVMX_ADD_IO_SEG(0x0001180050000000ull)
103#define CVMX_PKO_REG_GMX_PORT_MODE \
104 CVMX_ADD_IO_SEG(0x0001180050000018ull)
105#define CVMX_PKO_REG_INT_MASK \
106 CVMX_ADD_IO_SEG(0x0001180050000090ull)
107#define CVMX_PKO_REG_QUEUE_MODE \
108 CVMX_ADD_IO_SEG(0x0001180050000048ull)
109#define CVMX_PKO_REG_QUEUE_PTRS1 \
110 CVMX_ADD_IO_SEG(0x0001180050000100ull)
111#define CVMX_PKO_REG_READ_IDX \
112 CVMX_ADD_IO_SEG(0x0001180050000008ull)
113
114union cvmx_pko_mem_count0 {
115 uint64_t u64;
116 struct cvmx_pko_mem_count0_s {
117 uint64_t reserved_32_63:32;
118 uint64_t count:32;
119 } s;
120 struct cvmx_pko_mem_count0_s cn30xx;
121 struct cvmx_pko_mem_count0_s cn31xx;
122 struct cvmx_pko_mem_count0_s cn38xx;
123 struct cvmx_pko_mem_count0_s cn38xxp2;
124 struct cvmx_pko_mem_count0_s cn50xx;
125 struct cvmx_pko_mem_count0_s cn52xx;
126 struct cvmx_pko_mem_count0_s cn52xxp1;
127 struct cvmx_pko_mem_count0_s cn56xx;
128 struct cvmx_pko_mem_count0_s cn56xxp1;
129 struct cvmx_pko_mem_count0_s cn58xx;
130 struct cvmx_pko_mem_count0_s cn58xxp1;
131};
132
133union cvmx_pko_mem_count1 {
134 uint64_t u64;
135 struct cvmx_pko_mem_count1_s {
136 uint64_t reserved_48_63:16;
137 uint64_t count:48;
138 } s;
139 struct cvmx_pko_mem_count1_s cn30xx;
140 struct cvmx_pko_mem_count1_s cn31xx;
141 struct cvmx_pko_mem_count1_s cn38xx;
142 struct cvmx_pko_mem_count1_s cn38xxp2;
143 struct cvmx_pko_mem_count1_s cn50xx;
144 struct cvmx_pko_mem_count1_s cn52xx;
145 struct cvmx_pko_mem_count1_s cn52xxp1;
146 struct cvmx_pko_mem_count1_s cn56xx;
147 struct cvmx_pko_mem_count1_s cn56xxp1;
148 struct cvmx_pko_mem_count1_s cn58xx;
149 struct cvmx_pko_mem_count1_s cn58xxp1;
150};
151
152union cvmx_pko_mem_debug0 {
153 uint64_t u64;
154 struct cvmx_pko_mem_debug0_s {
155 uint64_t fau:28;
156 uint64_t cmd:14;
157 uint64_t segs:6;
158 uint64_t size:16;
159 } s;
160 struct cvmx_pko_mem_debug0_s cn30xx;
161 struct cvmx_pko_mem_debug0_s cn31xx;
162 struct cvmx_pko_mem_debug0_s cn38xx;
163 struct cvmx_pko_mem_debug0_s cn38xxp2;
164 struct cvmx_pko_mem_debug0_s cn50xx;
165 struct cvmx_pko_mem_debug0_s cn52xx;
166 struct cvmx_pko_mem_debug0_s cn52xxp1;
167 struct cvmx_pko_mem_debug0_s cn56xx;
168 struct cvmx_pko_mem_debug0_s cn56xxp1;
169 struct cvmx_pko_mem_debug0_s cn58xx;
170 struct cvmx_pko_mem_debug0_s cn58xxp1;
171};
172
173union cvmx_pko_mem_debug1 {
174 uint64_t u64;
175 struct cvmx_pko_mem_debug1_s {
176 uint64_t i:1;
177 uint64_t back:4;
178 uint64_t pool:3;
179 uint64_t size:16;
180 uint64_t ptr:40;
181 } s;
182 struct cvmx_pko_mem_debug1_s cn30xx;
183 struct cvmx_pko_mem_debug1_s cn31xx;
184 struct cvmx_pko_mem_debug1_s cn38xx;
185 struct cvmx_pko_mem_debug1_s cn38xxp2;
186 struct cvmx_pko_mem_debug1_s cn50xx;
187 struct cvmx_pko_mem_debug1_s cn52xx;
188 struct cvmx_pko_mem_debug1_s cn52xxp1;
189 struct cvmx_pko_mem_debug1_s cn56xx;
190 struct cvmx_pko_mem_debug1_s cn56xxp1;
191 struct cvmx_pko_mem_debug1_s cn58xx;
192 struct cvmx_pko_mem_debug1_s cn58xxp1;
193};
194
195union cvmx_pko_mem_debug10 {
196 uint64_t u64;
197 struct cvmx_pko_mem_debug10_s {
198 uint64_t reserved_0_63:64;
199 } s;
200 struct cvmx_pko_mem_debug10_cn30xx {
201 uint64_t fau:28;
202 uint64_t cmd:14;
203 uint64_t segs:6;
204 uint64_t size:16;
205 } cn30xx;
206 struct cvmx_pko_mem_debug10_cn30xx cn31xx;
207 struct cvmx_pko_mem_debug10_cn30xx cn38xx;
208 struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
209 struct cvmx_pko_mem_debug10_cn50xx {
210 uint64_t reserved_49_63:15;
211 uint64_t ptrs1:17;
212 uint64_t reserved_17_31:15;
213 uint64_t ptrs2:17;
214 } cn50xx;
215 struct cvmx_pko_mem_debug10_cn50xx cn52xx;
216 struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
217 struct cvmx_pko_mem_debug10_cn50xx cn56xx;
218 struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
219 struct cvmx_pko_mem_debug10_cn50xx cn58xx;
220 struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
221};
222
223union cvmx_pko_mem_debug11 {
224 uint64_t u64;
225 struct cvmx_pko_mem_debug11_s {
226 uint64_t i:1;
227 uint64_t back:4;
228 uint64_t pool:3;
229 uint64_t size:16;
230 uint64_t reserved_0_39:40;
231 } s;
232 struct cvmx_pko_mem_debug11_cn30xx {
233 uint64_t i:1;
234 uint64_t back:4;
235 uint64_t pool:3;
236 uint64_t size:16;
237 uint64_t ptr:40;
238 } cn30xx;
239 struct cvmx_pko_mem_debug11_cn30xx cn31xx;
240 struct cvmx_pko_mem_debug11_cn30xx cn38xx;
241 struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
242 struct cvmx_pko_mem_debug11_cn50xx {
243 uint64_t reserved_23_63:41;
244 uint64_t maj:1;
245 uint64_t uid:3;
246 uint64_t sop:1;
247 uint64_t len:1;
248 uint64_t chk:1;
249 uint64_t cnt:13;
250 uint64_t mod:3;
251 } cn50xx;
252 struct cvmx_pko_mem_debug11_cn50xx cn52xx;
253 struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
254 struct cvmx_pko_mem_debug11_cn50xx cn56xx;
255 struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
256 struct cvmx_pko_mem_debug11_cn50xx cn58xx;
257 struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
258};
259
260union cvmx_pko_mem_debug12 {
261 uint64_t u64;
262 struct cvmx_pko_mem_debug12_s {
263 uint64_t reserved_0_63:64;
264 } s;
265 struct cvmx_pko_mem_debug12_cn30xx {
266 uint64_t data:64;
267 } cn30xx;
268 struct cvmx_pko_mem_debug12_cn30xx cn31xx;
269 struct cvmx_pko_mem_debug12_cn30xx cn38xx;
270 struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
271 struct cvmx_pko_mem_debug12_cn50xx {
272 uint64_t fau:28;
273 uint64_t cmd:14;
274 uint64_t segs:6;
275 uint64_t size:16;
276 } cn50xx;
277 struct cvmx_pko_mem_debug12_cn50xx cn52xx;
278 struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
279 struct cvmx_pko_mem_debug12_cn50xx cn56xx;
280 struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
281 struct cvmx_pko_mem_debug12_cn50xx cn58xx;
282 struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
283};
284
285union cvmx_pko_mem_debug13 {
286 uint64_t u64;
287 struct cvmx_pko_mem_debug13_s {
288 uint64_t i:1;
289 uint64_t back:4;
290 uint64_t pool:3;
291 uint64_t reserved_0_55:56;
292 } s;
293 struct cvmx_pko_mem_debug13_cn30xx {
294 uint64_t reserved_51_63:13;
295 uint64_t widx:17;
296 uint64_t ridx2:17;
297 uint64_t widx2:17;
298 } cn30xx;
299 struct cvmx_pko_mem_debug13_cn30xx cn31xx;
300 struct cvmx_pko_mem_debug13_cn30xx cn38xx;
301 struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
302 struct cvmx_pko_mem_debug13_cn50xx {
303 uint64_t i:1;
304 uint64_t back:4;
305 uint64_t pool:3;
306 uint64_t size:16;
307 uint64_t ptr:40;
308 } cn50xx;
309 struct cvmx_pko_mem_debug13_cn50xx cn52xx;
310 struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
311 struct cvmx_pko_mem_debug13_cn50xx cn56xx;
312 struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
313 struct cvmx_pko_mem_debug13_cn50xx cn58xx;
314 struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
315};
316
317union cvmx_pko_mem_debug14 {
318 uint64_t u64;
319 struct cvmx_pko_mem_debug14_s {
320 uint64_t reserved_0_63:64;
321 } s;
322 struct cvmx_pko_mem_debug14_cn30xx {
323 uint64_t reserved_17_63:47;
324 uint64_t ridx:17;
325 } cn30xx;
326 struct cvmx_pko_mem_debug14_cn30xx cn31xx;
327 struct cvmx_pko_mem_debug14_cn30xx cn38xx;
328 struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
329 struct cvmx_pko_mem_debug14_cn52xx {
330 uint64_t data:64;
331 } cn52xx;
332 struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
333 struct cvmx_pko_mem_debug14_cn52xx cn56xx;
334 struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
335};
336
337union cvmx_pko_mem_debug2 {
338 uint64_t u64;
339 struct cvmx_pko_mem_debug2_s {
340 uint64_t i:1;
341 uint64_t back:4;
342 uint64_t pool:3;
343 uint64_t size:16;
344 uint64_t ptr:40;
345 } s;
346 struct cvmx_pko_mem_debug2_s cn30xx;
347 struct cvmx_pko_mem_debug2_s cn31xx;
348 struct cvmx_pko_mem_debug2_s cn38xx;
349 struct cvmx_pko_mem_debug2_s cn38xxp2;
350 struct cvmx_pko_mem_debug2_s cn50xx;
351 struct cvmx_pko_mem_debug2_s cn52xx;
352 struct cvmx_pko_mem_debug2_s cn52xxp1;
353 struct cvmx_pko_mem_debug2_s cn56xx;
354 struct cvmx_pko_mem_debug2_s cn56xxp1;
355 struct cvmx_pko_mem_debug2_s cn58xx;
356 struct cvmx_pko_mem_debug2_s cn58xxp1;
357};
358
359union cvmx_pko_mem_debug3 {
360 uint64_t u64;
361 struct cvmx_pko_mem_debug3_s {
362 uint64_t reserved_0_63:64;
363 } s;
364 struct cvmx_pko_mem_debug3_cn30xx {
365 uint64_t i:1;
366 uint64_t back:4;
367 uint64_t pool:3;
368 uint64_t size:16;
369 uint64_t ptr:40;
370 } cn30xx;
371 struct cvmx_pko_mem_debug3_cn30xx cn31xx;
372 struct cvmx_pko_mem_debug3_cn30xx cn38xx;
373 struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
374 struct cvmx_pko_mem_debug3_cn50xx {
375 uint64_t data:64;
376 } cn50xx;
377 struct cvmx_pko_mem_debug3_cn50xx cn52xx;
378 struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
379 struct cvmx_pko_mem_debug3_cn50xx cn56xx;
380 struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
381 struct cvmx_pko_mem_debug3_cn50xx cn58xx;
382 struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
383};
384
385union cvmx_pko_mem_debug4 {
386 uint64_t u64;
387 struct cvmx_pko_mem_debug4_s {
388 uint64_t reserved_0_63:64;
389 } s;
390 struct cvmx_pko_mem_debug4_cn30xx {
391 uint64_t data:64;
392 } cn30xx;
393 struct cvmx_pko_mem_debug4_cn30xx cn31xx;
394 struct cvmx_pko_mem_debug4_cn30xx cn38xx;
395 struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
396 struct cvmx_pko_mem_debug4_cn50xx {
397 uint64_t cmnd_segs:3;
398 uint64_t cmnd_siz:16;
399 uint64_t cmnd_off:6;
400 uint64_t uid:3;
401 uint64_t dread_sop:1;
402 uint64_t init_dwrite:1;
403 uint64_t chk_once:1;
404 uint64_t chk_mode:1;
405 uint64_t active:1;
406 uint64_t static_p:1;
407 uint64_t qos:3;
408 uint64_t qcb_ridx:5;
409 uint64_t qid_off_max:4;
410 uint64_t qid_off:4;
411 uint64_t qid_base:8;
412 uint64_t wait:1;
413 uint64_t minor:2;
414 uint64_t major:3;
415 } cn50xx;
416 struct cvmx_pko_mem_debug4_cn52xx {
417 uint64_t curr_siz:8;
418 uint64_t curr_off:16;
419 uint64_t cmnd_segs:6;
420 uint64_t cmnd_siz:16;
421 uint64_t cmnd_off:6;
422 uint64_t uid:2;
423 uint64_t dread_sop:1;
424 uint64_t init_dwrite:1;
425 uint64_t chk_once:1;
426 uint64_t chk_mode:1;
427 uint64_t wait:1;
428 uint64_t minor:2;
429 uint64_t major:3;
430 } cn52xx;
431 struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
432 struct cvmx_pko_mem_debug4_cn52xx cn56xx;
433 struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
434 struct cvmx_pko_mem_debug4_cn50xx cn58xx;
435 struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
436};
437
438union cvmx_pko_mem_debug5 {
439 uint64_t u64;
440 struct cvmx_pko_mem_debug5_s {
441 uint64_t reserved_0_63:64;
442 } s;
443 struct cvmx_pko_mem_debug5_cn30xx {
444 uint64_t dwri_mod:1;
445 uint64_t dwri_sop:1;
446 uint64_t dwri_len:1;
447 uint64_t dwri_cnt:13;
448 uint64_t cmnd_siz:16;
449 uint64_t uid:1;
450 uint64_t xfer_wor:1;
451 uint64_t xfer_dwr:1;
452 uint64_t cbuf_fre:1;
453 uint64_t reserved_27_27:1;
454 uint64_t chk_mode:1;
455 uint64_t active:1;
456 uint64_t qos:3;
457 uint64_t qcb_ridx:5;
458 uint64_t qid_off:3;
459 uint64_t qid_base:7;
460 uint64_t wait:1;
461 uint64_t minor:2;
462 uint64_t major:4;
463 } cn30xx;
464 struct cvmx_pko_mem_debug5_cn30xx cn31xx;
465 struct cvmx_pko_mem_debug5_cn30xx cn38xx;
466 struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
467 struct cvmx_pko_mem_debug5_cn50xx {
468 uint64_t curr_ptr:29;
469 uint64_t curr_siz:16;
470 uint64_t curr_off:16;
471 uint64_t cmnd_segs:3;
472 } cn50xx;
473 struct cvmx_pko_mem_debug5_cn52xx {
474 uint64_t reserved_54_63:10;
475 uint64_t nxt_inflt:6;
476 uint64_t curr_ptr:40;
477 uint64_t curr_siz:8;
478 } cn52xx;
479 struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
480 struct cvmx_pko_mem_debug5_cn52xx cn56xx;
481 struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
482 struct cvmx_pko_mem_debug5_cn50xx cn58xx;
483 struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
484};
485
486union cvmx_pko_mem_debug6 {
487 uint64_t u64;
488 struct cvmx_pko_mem_debug6_s {
489 uint64_t reserved_37_63:27;
490 uint64_t qid_offres:4;
491 uint64_t qid_offths:4;
492 uint64_t preempter:1;
493 uint64_t preemptee:1;
494 uint64_t preempted:1;
495 uint64_t active:1;
496 uint64_t statc:1;
497 uint64_t qos:3;
498 uint64_t qcb_ridx:5;
499 uint64_t qid_offmax:4;
500 uint64_t reserved_0_11:12;
501 } s;
502 struct cvmx_pko_mem_debug6_cn30xx {
503 uint64_t reserved_11_63:53;
504 uint64_t qid_offm:3;
505 uint64_t static_p:1;
506 uint64_t work_min:3;
507 uint64_t dwri_chk:1;
508 uint64_t dwri_uid:1;
509 uint64_t dwri_mod:2;
510 } cn30xx;
511 struct cvmx_pko_mem_debug6_cn30xx cn31xx;
512 struct cvmx_pko_mem_debug6_cn30xx cn38xx;
513 struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
514 struct cvmx_pko_mem_debug6_cn50xx {
515 uint64_t reserved_11_63:53;
516 uint64_t curr_ptr:11;
517 } cn50xx;
518 struct cvmx_pko_mem_debug6_cn52xx {
519 uint64_t reserved_37_63:27;
520 uint64_t qid_offres:4;
521 uint64_t qid_offths:4;
522 uint64_t preempter:1;
523 uint64_t preemptee:1;
524 uint64_t preempted:1;
525 uint64_t active:1;
526 uint64_t statc:1;
527 uint64_t qos:3;
528 uint64_t qcb_ridx:5;
529 uint64_t qid_offmax:4;
530 uint64_t qid_off:4;
531 uint64_t qid_base:8;
532 } cn52xx;
533 struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
534 struct cvmx_pko_mem_debug6_cn52xx cn56xx;
535 struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
536 struct cvmx_pko_mem_debug6_cn50xx cn58xx;
537 struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
538};
539
540union cvmx_pko_mem_debug7 {
541 uint64_t u64;
542 struct cvmx_pko_mem_debug7_s {
543 uint64_t qos:5;
544 uint64_t tail:1;
545 uint64_t reserved_0_57:58;
546 } s;
547 struct cvmx_pko_mem_debug7_cn30xx {
548 uint64_t reserved_58_63:6;
549 uint64_t dwb:9;
550 uint64_t start:33;
551 uint64_t size:16;
552 } cn30xx;
553 struct cvmx_pko_mem_debug7_cn30xx cn31xx;
554 struct cvmx_pko_mem_debug7_cn30xx cn38xx;
555 struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
556 struct cvmx_pko_mem_debug7_cn50xx {
557 uint64_t qos:5;
558 uint64_t tail:1;
559 uint64_t buf_siz:13;
560 uint64_t buf_ptr:33;
561 uint64_t qcb_widx:6;
562 uint64_t qcb_ridx:6;
563 } cn50xx;
564 struct cvmx_pko_mem_debug7_cn50xx cn52xx;
565 struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
566 struct cvmx_pko_mem_debug7_cn50xx cn56xx;
567 struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
568 struct cvmx_pko_mem_debug7_cn50xx cn58xx;
569 struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
570};
571
572union cvmx_pko_mem_debug8 {
573 uint64_t u64;
574 struct cvmx_pko_mem_debug8_s {
575 uint64_t reserved_59_63:5;
576 uint64_t tail:1;
577 uint64_t buf_siz:13;
578 uint64_t reserved_0_44:45;
579 } s;
580 struct cvmx_pko_mem_debug8_cn30xx {
581 uint64_t qos:5;
582 uint64_t tail:1;
583 uint64_t buf_siz:13;
584 uint64_t buf_ptr:33;
585 uint64_t qcb_widx:6;
586 uint64_t qcb_ridx:6;
587 } cn30xx;
588 struct cvmx_pko_mem_debug8_cn30xx cn31xx;
589 struct cvmx_pko_mem_debug8_cn30xx cn38xx;
590 struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
591 struct cvmx_pko_mem_debug8_cn50xx {
592 uint64_t reserved_28_63:36;
593 uint64_t doorbell:20;
594 uint64_t reserved_6_7:2;
595 uint64_t static_p:1;
596 uint64_t s_tail:1;
597 uint64_t static_q:1;
598 uint64_t qos:3;
599 } cn50xx;
600 struct cvmx_pko_mem_debug8_cn52xx {
601 uint64_t reserved_29_63:35;
602 uint64_t preempter:1;
603 uint64_t doorbell:20;
604 uint64_t reserved_7_7:1;
605 uint64_t preemptee:1;
606 uint64_t static_p:1;
607 uint64_t s_tail:1;
608 uint64_t static_q:1;
609 uint64_t qos:3;
610 } cn52xx;
611 struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
612 struct cvmx_pko_mem_debug8_cn52xx cn56xx;
613 struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
614 struct cvmx_pko_mem_debug8_cn50xx cn58xx;
615 struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
616};
617
618union cvmx_pko_mem_debug9 {
619 uint64_t u64;
620 struct cvmx_pko_mem_debug9_s {
621 uint64_t reserved_49_63:15;
622 uint64_t ptrs0:17;
623 uint64_t reserved_0_31:32;
624 } s;
625 struct cvmx_pko_mem_debug9_cn30xx {
626 uint64_t reserved_28_63:36;
627 uint64_t doorbell:20;
628 uint64_t reserved_5_7:3;
629 uint64_t s_tail:1;
630 uint64_t static_q:1;
631 uint64_t qos:3;
632 } cn30xx;
633 struct cvmx_pko_mem_debug9_cn30xx cn31xx;
634 struct cvmx_pko_mem_debug9_cn38xx {
635 uint64_t reserved_28_63:36;
636 uint64_t doorbell:20;
637 uint64_t reserved_6_7:2;
638 uint64_t static_p:1;
639 uint64_t s_tail:1;
640 uint64_t static_q:1;
641 uint64_t qos:3;
642 } cn38xx;
643 struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
644 struct cvmx_pko_mem_debug9_cn50xx {
645 uint64_t reserved_49_63:15;
646 uint64_t ptrs0:17;
647 uint64_t reserved_17_31:15;
648 uint64_t ptrs3:17;
649 } cn50xx;
650 struct cvmx_pko_mem_debug9_cn50xx cn52xx;
651 struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
652 struct cvmx_pko_mem_debug9_cn50xx cn56xx;
653 struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
654 struct cvmx_pko_mem_debug9_cn50xx cn58xx;
655 struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
656};
657
658union cvmx_pko_mem_port_ptrs {
659 uint64_t u64;
660 struct cvmx_pko_mem_port_ptrs_s {
661 uint64_t reserved_62_63:2;
662 uint64_t static_p:1;
663 uint64_t qos_mask:8;
664 uint64_t reserved_16_52:37;
665 uint64_t bp_port:6;
666 uint64_t eid:4;
667 uint64_t pid:6;
668 } s;
669 struct cvmx_pko_mem_port_ptrs_s cn52xx;
670 struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
671 struct cvmx_pko_mem_port_ptrs_s cn56xx;
672 struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
673};
674
675union cvmx_pko_mem_port_qos {
676 uint64_t u64;
677 struct cvmx_pko_mem_port_qos_s {
678 uint64_t reserved_61_63:3;
679 uint64_t qos_mask:8;
680 uint64_t reserved_10_52:43;
681 uint64_t eid:4;
682 uint64_t pid:6;
683 } s;
684 struct cvmx_pko_mem_port_qos_s cn52xx;
685 struct cvmx_pko_mem_port_qos_s cn52xxp1;
686 struct cvmx_pko_mem_port_qos_s cn56xx;
687 struct cvmx_pko_mem_port_qos_s cn56xxp1;
688};
689
690union cvmx_pko_mem_port_rate0 {
691 uint64_t u64;
692 struct cvmx_pko_mem_port_rate0_s {
693 uint64_t reserved_51_63:13;
694 uint64_t rate_word:19;
695 uint64_t rate_pkt:24;
696 uint64_t reserved_6_7:2;
697 uint64_t pid:6;
698 } s;
699 struct cvmx_pko_mem_port_rate0_s cn52xx;
700 struct cvmx_pko_mem_port_rate0_s cn52xxp1;
701 struct cvmx_pko_mem_port_rate0_s cn56xx;
702 struct cvmx_pko_mem_port_rate0_s cn56xxp1;
703};
704
705union cvmx_pko_mem_port_rate1 {
706 uint64_t u64;
707 struct cvmx_pko_mem_port_rate1_s {
708 uint64_t reserved_32_63:32;
709 uint64_t rate_lim:24;
710 uint64_t reserved_6_7:2;
711 uint64_t pid:6;
712 } s;
713 struct cvmx_pko_mem_port_rate1_s cn52xx;
714 struct cvmx_pko_mem_port_rate1_s cn52xxp1;
715 struct cvmx_pko_mem_port_rate1_s cn56xx;
716 struct cvmx_pko_mem_port_rate1_s cn56xxp1;
717};
718
719union cvmx_pko_mem_queue_ptrs {
720 uint64_t u64;
721 struct cvmx_pko_mem_queue_ptrs_s {
722 uint64_t s_tail:1;
723 uint64_t static_p:1;
724 uint64_t static_q:1;
725 uint64_t qos_mask:8;
726 uint64_t buf_ptr:36;
727 uint64_t tail:1;
728 uint64_t index:3;
729 uint64_t port:6;
730 uint64_t queue:7;
731 } s;
732 struct cvmx_pko_mem_queue_ptrs_s cn30xx;
733 struct cvmx_pko_mem_queue_ptrs_s cn31xx;
734 struct cvmx_pko_mem_queue_ptrs_s cn38xx;
735 struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
736 struct cvmx_pko_mem_queue_ptrs_s cn50xx;
737 struct cvmx_pko_mem_queue_ptrs_s cn52xx;
738 struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
739 struct cvmx_pko_mem_queue_ptrs_s cn56xx;
740 struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
741 struct cvmx_pko_mem_queue_ptrs_s cn58xx;
742 struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
743};
744
745union cvmx_pko_mem_queue_qos {
746 uint64_t u64;
747 struct cvmx_pko_mem_queue_qos_s {
748 uint64_t reserved_61_63:3;
749 uint64_t qos_mask:8;
750 uint64_t reserved_13_52:40;
751 uint64_t pid:6;
752 uint64_t qid:7;
753 } s;
754 struct cvmx_pko_mem_queue_qos_s cn30xx;
755 struct cvmx_pko_mem_queue_qos_s cn31xx;
756 struct cvmx_pko_mem_queue_qos_s cn38xx;
757 struct cvmx_pko_mem_queue_qos_s cn38xxp2;
758 struct cvmx_pko_mem_queue_qos_s cn50xx;
759 struct cvmx_pko_mem_queue_qos_s cn52xx;
760 struct cvmx_pko_mem_queue_qos_s cn52xxp1;
761 struct cvmx_pko_mem_queue_qos_s cn56xx;
762 struct cvmx_pko_mem_queue_qos_s cn56xxp1;
763 struct cvmx_pko_mem_queue_qos_s cn58xx;
764 struct cvmx_pko_mem_queue_qos_s cn58xxp1;
765};
766
767union cvmx_pko_reg_bist_result {
768 uint64_t u64;
769 struct cvmx_pko_reg_bist_result_s {
770 uint64_t reserved_0_63:64;
771 } s;
772 struct cvmx_pko_reg_bist_result_cn30xx {
773 uint64_t reserved_27_63:37;
774 uint64_t psb2:5;
775 uint64_t count:1;
776 uint64_t rif:1;
777 uint64_t wif:1;
778 uint64_t ncb:1;
779 uint64_t out:1;
780 uint64_t crc:1;
781 uint64_t chk:1;
782 uint64_t qsb:2;
783 uint64_t qcb:2;
784 uint64_t pdb:4;
785 uint64_t psb:7;
786 } cn30xx;
787 struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
788 struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
789 struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
790 struct cvmx_pko_reg_bist_result_cn50xx {
791 uint64_t reserved_33_63:31;
792 uint64_t csr:1;
793 uint64_t iob:1;
794 uint64_t out_crc:1;
795 uint64_t out_ctl:3;
796 uint64_t out_sta:1;
797 uint64_t out_wif:1;
798 uint64_t prt_chk:3;
799 uint64_t prt_nxt:1;
800 uint64_t prt_psb:6;
801 uint64_t ncb_inb:2;
802 uint64_t prt_qcb:2;
803 uint64_t prt_qsb:3;
804 uint64_t dat_dat:4;
805 uint64_t dat_ptr:4;
806 } cn50xx;
807 struct cvmx_pko_reg_bist_result_cn52xx {
808 uint64_t reserved_35_63:29;
809 uint64_t csr:1;
810 uint64_t iob:1;
811 uint64_t out_dat:1;
812 uint64_t out_ctl:3;
813 uint64_t out_sta:1;
814 uint64_t out_wif:1;
815 uint64_t prt_chk:3;
816 uint64_t prt_nxt:1;
817 uint64_t prt_psb:8;
818 uint64_t ncb_inb:2;
819 uint64_t prt_qcb:2;
820 uint64_t prt_qsb:3;
821 uint64_t prt_ctl:2;
822 uint64_t dat_dat:2;
823 uint64_t dat_ptr:4;
824 } cn52xx;
825 struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
826 struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
827 struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
828 struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
829 struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
830};
831
832union cvmx_pko_reg_cmd_buf {
833 uint64_t u64;
834 struct cvmx_pko_reg_cmd_buf_s {
835 uint64_t reserved_23_63:41;
836 uint64_t pool:3;
837 uint64_t reserved_13_19:7;
838 uint64_t size:13;
839 } s;
840 struct cvmx_pko_reg_cmd_buf_s cn30xx;
841 struct cvmx_pko_reg_cmd_buf_s cn31xx;
842 struct cvmx_pko_reg_cmd_buf_s cn38xx;
843 struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
844 struct cvmx_pko_reg_cmd_buf_s cn50xx;
845 struct cvmx_pko_reg_cmd_buf_s cn52xx;
846 struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
847 struct cvmx_pko_reg_cmd_buf_s cn56xx;
848 struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
849 struct cvmx_pko_reg_cmd_buf_s cn58xx;
850 struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
851};
852
853union cvmx_pko_reg_crc_ctlx {
854 uint64_t u64;
855 struct cvmx_pko_reg_crc_ctlx_s {
856 uint64_t reserved_2_63:62;
857 uint64_t invres:1;
858 uint64_t refin:1;
859 } s;
860 struct cvmx_pko_reg_crc_ctlx_s cn38xx;
861 struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
862 struct cvmx_pko_reg_crc_ctlx_s cn58xx;
863 struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
864};
865
866union cvmx_pko_reg_crc_enable {
867 uint64_t u64;
868 struct cvmx_pko_reg_crc_enable_s {
869 uint64_t reserved_32_63:32;
870 uint64_t enable:32;
871 } s;
872 struct cvmx_pko_reg_crc_enable_s cn38xx;
873 struct cvmx_pko_reg_crc_enable_s cn38xxp2;
874 struct cvmx_pko_reg_crc_enable_s cn58xx;
875 struct cvmx_pko_reg_crc_enable_s cn58xxp1;
876};
877
878union cvmx_pko_reg_crc_ivx {
879 uint64_t u64;
880 struct cvmx_pko_reg_crc_ivx_s {
881 uint64_t reserved_32_63:32;
882 uint64_t iv:32;
883 } s;
884 struct cvmx_pko_reg_crc_ivx_s cn38xx;
885 struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
886 struct cvmx_pko_reg_crc_ivx_s cn58xx;
887 struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
888};
889
890union cvmx_pko_reg_debug0 {
891 uint64_t u64;
892 struct cvmx_pko_reg_debug0_s {
893 uint64_t asserts:64;
894 } s;
895 struct cvmx_pko_reg_debug0_cn30xx {
896 uint64_t reserved_17_63:47;
897 uint64_t asserts:17;
898 } cn30xx;
899 struct cvmx_pko_reg_debug0_cn30xx cn31xx;
900 struct cvmx_pko_reg_debug0_cn30xx cn38xx;
901 struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
902 struct cvmx_pko_reg_debug0_s cn50xx;
903 struct cvmx_pko_reg_debug0_s cn52xx;
904 struct cvmx_pko_reg_debug0_s cn52xxp1;
905 struct cvmx_pko_reg_debug0_s cn56xx;
906 struct cvmx_pko_reg_debug0_s cn56xxp1;
907 struct cvmx_pko_reg_debug0_s cn58xx;
908 struct cvmx_pko_reg_debug0_s cn58xxp1;
909};
910
911union cvmx_pko_reg_debug1 {
912 uint64_t u64;
913 struct cvmx_pko_reg_debug1_s {
914 uint64_t asserts:64;
915 } s;
916 struct cvmx_pko_reg_debug1_s cn50xx;
917 struct cvmx_pko_reg_debug1_s cn52xx;
918 struct cvmx_pko_reg_debug1_s cn52xxp1;
919 struct cvmx_pko_reg_debug1_s cn56xx;
920 struct cvmx_pko_reg_debug1_s cn56xxp1;
921 struct cvmx_pko_reg_debug1_s cn58xx;
922 struct cvmx_pko_reg_debug1_s cn58xxp1;
923};
924
925union cvmx_pko_reg_debug2 {
926 uint64_t u64;
927 struct cvmx_pko_reg_debug2_s {
928 uint64_t asserts:64;
929 } s;
930 struct cvmx_pko_reg_debug2_s cn50xx;
931 struct cvmx_pko_reg_debug2_s cn52xx;
932 struct cvmx_pko_reg_debug2_s cn52xxp1;
933 struct cvmx_pko_reg_debug2_s cn56xx;
934 struct cvmx_pko_reg_debug2_s cn56xxp1;
935 struct cvmx_pko_reg_debug2_s cn58xx;
936 struct cvmx_pko_reg_debug2_s cn58xxp1;
937};
938
939union cvmx_pko_reg_debug3 {
940 uint64_t u64;
941 struct cvmx_pko_reg_debug3_s {
942 uint64_t asserts:64;
943 } s;
944 struct cvmx_pko_reg_debug3_s cn50xx;
945 struct cvmx_pko_reg_debug3_s cn52xx;
946 struct cvmx_pko_reg_debug3_s cn52xxp1;
947 struct cvmx_pko_reg_debug3_s cn56xx;
948 struct cvmx_pko_reg_debug3_s cn56xxp1;
949 struct cvmx_pko_reg_debug3_s cn58xx;
950 struct cvmx_pko_reg_debug3_s cn58xxp1;
951};
952
953union cvmx_pko_reg_engine_inflight {
954 uint64_t u64;
955 struct cvmx_pko_reg_engine_inflight_s {
956 uint64_t reserved_40_63:24;
957 uint64_t engine9:4;
958 uint64_t engine8:4;
959 uint64_t engine7:4;
960 uint64_t engine6:4;
961 uint64_t engine5:4;
962 uint64_t engine4:4;
963 uint64_t engine3:4;
964 uint64_t engine2:4;
965 uint64_t engine1:4;
966 uint64_t engine0:4;
967 } s;
968 struct cvmx_pko_reg_engine_inflight_s cn52xx;
969 struct cvmx_pko_reg_engine_inflight_s cn52xxp1;
970 struct cvmx_pko_reg_engine_inflight_s cn56xx;
971 struct cvmx_pko_reg_engine_inflight_s cn56xxp1;
972};
973
974union cvmx_pko_reg_engine_thresh {
975 uint64_t u64;
976 struct cvmx_pko_reg_engine_thresh_s {
977 uint64_t reserved_10_63:54;
978 uint64_t mask:10;
979 } s;
980 struct cvmx_pko_reg_engine_thresh_s cn52xx;
981 struct cvmx_pko_reg_engine_thresh_s cn52xxp1;
982 struct cvmx_pko_reg_engine_thresh_s cn56xx;
983 struct cvmx_pko_reg_engine_thresh_s cn56xxp1;
984};
985
986union cvmx_pko_reg_error {
987 uint64_t u64;
988 struct cvmx_pko_reg_error_s {
989 uint64_t reserved_3_63:61;
990 uint64_t currzero:1;
991 uint64_t doorbell:1;
992 uint64_t parity:1;
993 } s;
994 struct cvmx_pko_reg_error_cn30xx {
995 uint64_t reserved_2_63:62;
996 uint64_t doorbell:1;
997 uint64_t parity:1;
998 } cn30xx;
999 struct cvmx_pko_reg_error_cn30xx cn31xx;
1000 struct cvmx_pko_reg_error_cn30xx cn38xx;
1001 struct cvmx_pko_reg_error_cn30xx cn38xxp2;
1002 struct cvmx_pko_reg_error_s cn50xx;
1003 struct cvmx_pko_reg_error_s cn52xx;
1004 struct cvmx_pko_reg_error_s cn52xxp1;
1005 struct cvmx_pko_reg_error_s cn56xx;
1006 struct cvmx_pko_reg_error_s cn56xxp1;
1007 struct cvmx_pko_reg_error_s cn58xx;
1008 struct cvmx_pko_reg_error_s cn58xxp1;
1009};
1010
1011union cvmx_pko_reg_flags {
1012 uint64_t u64;
1013 struct cvmx_pko_reg_flags_s {
1014 uint64_t reserved_4_63:60;
1015 uint64_t reset:1;
1016 uint64_t store_be:1;
1017 uint64_t ena_dwb:1;
1018 uint64_t ena_pko:1;
1019 } s;
1020 struct cvmx_pko_reg_flags_s cn30xx;
1021 struct cvmx_pko_reg_flags_s cn31xx;
1022 struct cvmx_pko_reg_flags_s cn38xx;
1023 struct cvmx_pko_reg_flags_s cn38xxp2;
1024 struct cvmx_pko_reg_flags_s cn50xx;
1025 struct cvmx_pko_reg_flags_s cn52xx;
1026 struct cvmx_pko_reg_flags_s cn52xxp1;
1027 struct cvmx_pko_reg_flags_s cn56xx;
1028 struct cvmx_pko_reg_flags_s cn56xxp1;
1029 struct cvmx_pko_reg_flags_s cn58xx;
1030 struct cvmx_pko_reg_flags_s cn58xxp1;
1031};
1032
1033union cvmx_pko_reg_gmx_port_mode {
1034 uint64_t u64;
1035 struct cvmx_pko_reg_gmx_port_mode_s {
1036 uint64_t reserved_6_63:58;
1037 uint64_t mode1:3;
1038 uint64_t mode0:3;
1039 } s;
1040 struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
1041 struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
1042 struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
1043 struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
1044 struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
1045 struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
1046 struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
1047 struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
1048 struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
1049 struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
1050 struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
1051};
1052
1053union cvmx_pko_reg_int_mask {
1054 uint64_t u64;
1055 struct cvmx_pko_reg_int_mask_s {
1056 uint64_t reserved_3_63:61;
1057 uint64_t currzero:1;
1058 uint64_t doorbell:1;
1059 uint64_t parity:1;
1060 } s;
1061 struct cvmx_pko_reg_int_mask_cn30xx {
1062 uint64_t reserved_2_63:62;
1063 uint64_t doorbell:1;
1064 uint64_t parity:1;
1065 } cn30xx;
1066 struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
1067 struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
1068 struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
1069 struct cvmx_pko_reg_int_mask_s cn50xx;
1070 struct cvmx_pko_reg_int_mask_s cn52xx;
1071 struct cvmx_pko_reg_int_mask_s cn52xxp1;
1072 struct cvmx_pko_reg_int_mask_s cn56xx;
1073 struct cvmx_pko_reg_int_mask_s cn56xxp1;
1074 struct cvmx_pko_reg_int_mask_s cn58xx;
1075 struct cvmx_pko_reg_int_mask_s cn58xxp1;
1076};
1077
1078union cvmx_pko_reg_queue_mode {
1079 uint64_t u64;
1080 struct cvmx_pko_reg_queue_mode_s {
1081 uint64_t reserved_2_63:62;
1082 uint64_t mode:2;
1083 } s;
1084 struct cvmx_pko_reg_queue_mode_s cn30xx;
1085 struct cvmx_pko_reg_queue_mode_s cn31xx;
1086 struct cvmx_pko_reg_queue_mode_s cn38xx;
1087 struct cvmx_pko_reg_queue_mode_s cn38xxp2;
1088 struct cvmx_pko_reg_queue_mode_s cn50xx;
1089 struct cvmx_pko_reg_queue_mode_s cn52xx;
1090 struct cvmx_pko_reg_queue_mode_s cn52xxp1;
1091 struct cvmx_pko_reg_queue_mode_s cn56xx;
1092 struct cvmx_pko_reg_queue_mode_s cn56xxp1;
1093 struct cvmx_pko_reg_queue_mode_s cn58xx;
1094 struct cvmx_pko_reg_queue_mode_s cn58xxp1;
1095};
1096
1097union cvmx_pko_reg_queue_ptrs1 {
1098 uint64_t u64;
1099 struct cvmx_pko_reg_queue_ptrs1_s {
1100 uint64_t reserved_2_63:62;
1101 uint64_t idx3:1;
1102 uint64_t qid7:1;
1103 } s;
1104 struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
1105 struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
1106 struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
1107 struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
1108 struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
1109 struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
1110 struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
1111};
1112
1113union cvmx_pko_reg_read_idx {
1114 uint64_t u64;
1115 struct cvmx_pko_reg_read_idx_s {
1116 uint64_t reserved_16_63:48;
1117 uint64_t inc:8;
1118 uint64_t index:8;
1119 } s;
1120 struct cvmx_pko_reg_read_idx_s cn30xx;
1121 struct cvmx_pko_reg_read_idx_s cn31xx;
1122 struct cvmx_pko_reg_read_idx_s cn38xx;
1123 struct cvmx_pko_reg_read_idx_s cn38xxp2;
1124 struct cvmx_pko_reg_read_idx_s cn50xx;
1125 struct cvmx_pko_reg_read_idx_s cn52xx;
1126 struct cvmx_pko_reg_read_idx_s cn52xxp1;
1127 struct cvmx_pko_reg_read_idx_s cn56xx;
1128 struct cvmx_pko_reg_read_idx_s cn56xxp1;
1129 struct cvmx_pko_reg_read_idx_s cn58xx;
1130 struct cvmx_pko_reg_read_idx_s cn58xxp1;
1131};
1132
1133#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
new file mode 100644
index 00000000000..de3412aada5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -0,0 +1,610 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Interface to the hardware Packet Output unit.
31 *
32 * Starting with SDK 1.7.0, the PKO output functions now support
33 * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
34 * function similarly to previous SDKs by using POW atomic tags
35 * to preserve ordering and exclusivity. As a new option, you
36 * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
37 * memory based locking instead. This locking has the advantage
38 * of not affecting the tag state but doesn't preserve packet
39 * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
40 * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
41 * with hand tuned fast path code.
42 *
43 * Some of other SDK differences visible to the command command
44 * queuing:
45 * - PKO indexes are no longer stored in the FAU. A large
46 * percentage of the FAU register block used to be tied up
47 * maintaining PKO queue pointers. These are now stored in a
48 * global named block.
49 * - The PKO <b>use_locking</b> parameter can now have a global
50 * effect. Since all application use the same named block,
51 * queue locking correctly applies across all operating
52 * systems when using CVMX_PKO_LOCK_CMD_QUEUE.
53 * - PKO 3 word commands are now supported. Use
54 * cvmx_pko_send_packet_finish3().
55 *
56 */
57
58#ifndef __CVMX_PKO_H__
59#define __CVMX_PKO_H__
60
61#include "cvmx-fpa.h"
62#include "cvmx-pow.h"
63#include "cvmx-cmd-queue.h"
64#include "cvmx-pko-defs.h"
65
66/* Adjust the command buffer size by 1 word so that in the case of using only
67 * two word PKO commands no command words stradle buffers. The useful values
68 * for this are 0 and 1. */
69#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
70
71#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
72#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
73 OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
74 OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
75 (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
76 OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
77#define CVMX_PKO_NUM_OUTPUT_PORTS 40
78/* use this for queues that are not used */
79#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
80#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9
81#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF
82#define CVMX_PKO_MAX_QUEUE_DEPTH 0
83
84typedef enum {
85 CVMX_PKO_SUCCESS,
86 CVMX_PKO_INVALID_PORT,
87 CVMX_PKO_INVALID_QUEUE,
88 CVMX_PKO_INVALID_PRIORITY,
89 CVMX_PKO_NO_MEMORY,
90 CVMX_PKO_PORT_ALREADY_SETUP,
91 CVMX_PKO_CMD_QUEUE_INIT_ERROR
92} cvmx_pko_status_t;
93
94/**
95 * This enumeration represents the differnet locking modes supported by PKO.
96 */
97typedef enum {
98 /*
99 * PKO doesn't do any locking. It is the responsibility of the
100 * application to make sure that no other core is accessing
101 * the same queue at the same time
102 */
103 CVMX_PKO_LOCK_NONE = 0,
104 /*
105 * PKO performs an atomic tagswitch to insure exclusive access
106 * to the output queue. This will maintain packet ordering on
107 * output.
108 */
109 CVMX_PKO_LOCK_ATOMIC_TAG = 1,
110 /*
111 * PKO uses the common command queue locks to insure exclusive
112 * access to the output queue. This is a memory based
113 * ll/sc. This is the most portable locking mechanism.
114 */
115 CVMX_PKO_LOCK_CMD_QUEUE = 2,
116} cvmx_pko_lock_t;
117
118typedef struct {
119 uint32_t packets;
120 uint64_t octets;
121 uint64_t doorbell;
122} cvmx_pko_port_status_t;
123
124/**
125 * This structure defines the address to use on a packet enqueue
126 */
127typedef union {
128 uint64_t u64;
129 struct {
130 /* Must CVMX_IO_SEG */
131 uint64_t mem_space:2;
132 /* Must be zero */
133 uint64_t reserved:13;
134 /* Must be one */
135 uint64_t is_io:1;
136 /* The ID of the device on the non-coherent bus */
137 uint64_t did:8;
138 /* Must be zero */
139 uint64_t reserved2:4;
140 /* Must be zero */
141 uint64_t reserved3:18;
142 /*
143 * The hardware likes to have the output port in
144 * addition to the output queue,
145 */
146 uint64_t port:6;
147 /*
148 * The output queue to send the packet to (0-127 are
149 * legal)
150 */
151 uint64_t queue:9;
152 /* Must be zero */
153 uint64_t reserved4:3;
154 } s;
155} cvmx_pko_doorbell_address_t;
156
157/**
158 * Structure of the first packet output command word.
159 */
160typedef union {
161 uint64_t u64;
162 struct {
163 /*
164 * The size of the reg1 operation - could be 8, 16,
165 * 32, or 64 bits.
166 */
167 uint64_t size1:2;
168 /*
169 * The size of the reg0 operation - could be 8, 16,
170 * 32, or 64 bits.
171 */
172 uint64_t size0:2;
173 /*
174 * If set, subtract 1, if clear, subtract packet
175 * size.
176 */
177 uint64_t subone1:1;
178 /*
179 * The register, subtract will be done if reg1 is
180 * non-zero.
181 */
182 uint64_t reg1:11;
183 /* If set, subtract 1, if clear, subtract packet size */
184 uint64_t subone0:1;
185 /* The register, subtract will be done if reg0 is non-zero */
186 uint64_t reg0:11;
187 /*
188 * When set, interpret segment pointer and segment
189 * bytes in little endian order.
190 */
191 uint64_t le:1;
192 /*
193 * When set, packet data not allocated in L2 cache by
194 * PKO.
195 */
196 uint64_t n2:1;
197 /*
198 * If set and rsp is set, word3 contains a pointer to
199 * a work queue entry.
200 */
201 uint64_t wqp:1;
202 /* If set, the hardware will send a response when done */
203 uint64_t rsp:1;
204 /*
205 * If set, the supplied pkt_ptr is really a pointer to
206 * a list of pkt_ptr's.
207 */
208 uint64_t gather:1;
209 /*
210 * If ipoffp1 is non zero, (ipoffp1-1) is the number
211 * of bytes to IP header, and the hardware will
212 * calculate and insert the UDP/TCP checksum.
213 */
214 uint64_t ipoffp1:7;
215 /*
216 * If set, ignore the I bit (force to zero) from all
217 * pointer structures.
218 */
219 uint64_t ignore_i:1;
220 /*
221 * If clear, the hardware will attempt to free the
222 * buffers containing the packet.
223 */
224 uint64_t dontfree:1;
225 /*
226 * The total number of segs in the packet, if gather
227 * set, also gather list length.
228 */
229 uint64_t segs:6;
230 /* Including L2, but no trailing CRC */
231 uint64_t total_bytes:16;
232 } s;
233} cvmx_pko_command_word0_t;
234
235/* CSR typedefs have been moved to cvmx-csr-*.h */
236
237/**
238 * Definition of internal state for Packet output processing
239 */
240typedef struct {
241 /* ptr to start of buffer, offset kept in FAU reg */
242 uint64_t *start_ptr;
243} cvmx_pko_state_elem_t;
244
245/**
246 * Call before any other calls to initialize the packet
247 * output system.
248 */
249extern void cvmx_pko_initialize_global(void);
250extern int cvmx_pko_initialize_local(void);
251
252/**
253 * Enables the packet output hardware. It must already be
254 * configured.
255 */
256extern void cvmx_pko_enable(void);
257
258/**
259 * Disables the packet output. Does not affect any configuration.
260 */
261extern void cvmx_pko_disable(void);
262
263/**
264 * Shutdown and free resources required by packet output.
265 */
266
267extern void cvmx_pko_shutdown(void);
268
269/**
270 * Configure a output port and the associated queues for use.
271 *
272 * @port: Port to configure.
273 * @base_queue: First queue number to associate with this port.
274 * @num_queues: Number of queues t oassociate with this port
275 * @priority: Array of priority levels for each queue. Values are
276 * allowed to be 1-8. A value of 8 get 8 times the traffic
277 * of a value of 1. There must be num_queues elements in the
278 * array.
279 */
280extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
281 uint64_t base_queue,
282 uint64_t num_queues,
283 const uint64_t priority[]);
284
285/**
286 * Ring the packet output doorbell. This tells the packet
287 * output hardware that "len" command words have been added
288 * to its pending list. This command includes the required
289 * CVMX_SYNCWS before the doorbell ring.
290 *
291 * @port: Port the packet is for
292 * @queue: Queue the packet is for
293 * @len: Length of the command in 64 bit words
294 */
295static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
296 uint64_t len)
297{
298 cvmx_pko_doorbell_address_t ptr;
299
300 ptr.u64 = 0;
301 ptr.s.mem_space = CVMX_IO_SEG;
302 ptr.s.did = CVMX_OCT_DID_PKT_SEND;
303 ptr.s.is_io = 1;
304 ptr.s.port = port;
305 ptr.s.queue = queue;
306 /*
307 * Need to make sure output queue data is in DRAM before
308 * doorbell write.
309 */
310 CVMX_SYNCWS;
311 cvmx_write_io(ptr.u64, len);
312}
313
314/**
315 * Prepare to send a packet. This may initiate a tag switch to
316 * get exclusive access to the output queue structure, and
317 * performs other prep work for the packet send operation.
318 *
319 * cvmx_pko_send_packet_finish() MUST be called after this function is called,
320 * and must be called with the same port/queue/use_locking arguments.
321 *
322 * The use_locking parameter allows the caller to use three
323 * possible locking modes.
324 * - CVMX_PKO_LOCK_NONE
325 * - PKO doesn't do any locking. It is the responsibility
326 * of the application to make sure that no other core
327 * is accessing the same queue at the same time.
328 * - CVMX_PKO_LOCK_ATOMIC_TAG
329 * - PKO performs an atomic tagswitch to insure exclusive
330 * access to the output queue. This will maintain
331 * packet ordering on output.
332 * - CVMX_PKO_LOCK_CMD_QUEUE
333 * - PKO uses the common command queue locks to insure
334 * exclusive access to the output queue. This is a
335 * memory based ll/sc. This is the most portable
336 * locking mechanism.
337 *
338 * NOTE: If atomic locking is used, the POW entry CANNOT be
339 * descheduled, as it does not contain a valid WQE pointer.
340 *
341 * @port: Port to send it on
342 * @queue: Queue to use
343 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
344 * CVMX_PKO_LOCK_CMD_QUEUE
345 */
346
347static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
348 cvmx_pko_lock_t use_locking)
349{
350 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
351 /*
352 * Must do a full switch here to handle all cases. We
353 * use a fake WQE pointer, as the POW does not access
354 * this memory. The WQE pointer and group are only
355 * used if this work is descheduled, which is not
356 * supported by the
357 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
358 * combination. Note that this is a special case in
359 * which these fake values can be used - this is not a
360 * general technique.
361 */
362 uint32_t tag =
363 CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
364 CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
365 (CVMX_TAG_SUBGROUP_MASK & queue);
366 cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag,
367 CVMX_POW_TAG_TYPE_ATOMIC, 0);
368 }
369}
370
371/**
372 * Complete packet output. cvmx_pko_send_packet_prepare() must be
373 * called exactly once before this, and the same parameters must be
374 * passed to both cvmx_pko_send_packet_prepare() and
375 * cvmx_pko_send_packet_finish().
376 *
377 * @port: Port to send it on
378 * @queue: Queue to use
379 * @pko_command:
380 * PKO HW command word
381 * @packet: Packet to send
382 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
383 * CVMX_PKO_LOCK_CMD_QUEUE
384 *
385 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
386 * failure of output
387 */
388static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
389 uint64_t port,
390 uint64_t queue,
391 cvmx_pko_command_word0_t pko_command,
392 union cvmx_buf_ptr packet,
393 cvmx_pko_lock_t use_locking)
394{
395 cvmx_cmd_queue_result_t result;
396 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
397 cvmx_pow_tag_sw_wait();
398 result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
399 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
400 pko_command.u64, packet.u64);
401 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
402 cvmx_pko_doorbell(port, queue, 2);
403 return CVMX_PKO_SUCCESS;
404 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
405 || (result == CVMX_CMD_QUEUE_FULL)) {
406 return CVMX_PKO_NO_MEMORY;
407 } else {
408 return CVMX_PKO_INVALID_QUEUE;
409 }
410}
411
412/**
413 * Complete packet output. cvmx_pko_send_packet_prepare() must be
414 * called exactly once before this, and the same parameters must be
415 * passed to both cvmx_pko_send_packet_prepare() and
416 * cvmx_pko_send_packet_finish().
417 *
418 * @port: Port to send it on
419 * @queue: Queue to use
420 * @pko_command:
421 * PKO HW command word
422 * @packet: Packet to send
423 * @addr: Plysical address of a work queue entry or physical address
424 * to zero on complete.
425 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
426 * CVMX_PKO_LOCK_CMD_QUEUE
427 *
428 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
429 * failure of output
430 */
431static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
432 uint64_t port,
433 uint64_t queue,
434 cvmx_pko_command_word0_t pko_command,
435 union cvmx_buf_ptr packet,
436 uint64_t addr,
437 cvmx_pko_lock_t use_locking)
438{
439 cvmx_cmd_queue_result_t result;
440 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
441 cvmx_pow_tag_sw_wait();
442 result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
443 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
444 pko_command.u64, packet.u64, addr);
445 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
446 cvmx_pko_doorbell(port, queue, 3);
447 return CVMX_PKO_SUCCESS;
448 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
449 || (result == CVMX_CMD_QUEUE_FULL)) {
450 return CVMX_PKO_NO_MEMORY;
451 } else {
452 return CVMX_PKO_INVALID_QUEUE;
453 }
454}
455
456/**
457 * Return the pko output queue associated with a port and a specific core.
458 * In normal mode (PKO lockless operation is disabled), the value returned
459 * is the base queue.
460 *
461 * @port: Port number
462 * @core: Core to get queue for
463 *
464 * Returns Core-specific output queue
465 */
466static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
467{
468#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
469#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
470#endif
471#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
472#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
473#endif
474
475 if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
476 return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
477 else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
478 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
479 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
480 16) *
481 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
482 else if ((port >= 32) && (port < 36))
483 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
484 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
485 CVMX_PKO_MAX_PORTS_INTERFACE1 *
486 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
487 32) *
488 CVMX_PKO_QUEUES_PER_PORT_PCI;
489 else if ((port >= 36) && (port < 40))
490 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
491 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
492 CVMX_PKO_MAX_PORTS_INTERFACE1 *
493 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
494 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
495 36) *
496 CVMX_PKO_QUEUES_PER_PORT_LOOP;
497 else
498 /* Given the limit on the number of ports we can map to
499 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
500 * divided among all cores), the remaining unmapped ports
501 * are assigned an illegal queue number */
502 return CVMX_PKO_ILLEGAL_QUEUE;
503}
504
505/**
506 * For a given port number, return the base pko output queue
507 * for the port.
508 *
509 * @port: Port number
510 * Returns Base output queue
511 */
512static inline int cvmx_pko_get_base_queue(int port)
513{
514 return cvmx_pko_get_base_queue_per_core(port, 0);
515}
516
517/**
518 * For a given port number, return the number of pko output queues.
519 *
520 * @port: Port number
521 * Returns Number of output queues
522 */
523static inline int cvmx_pko_get_num_queues(int port)
524{
525 if (port < 16)
526 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
527 else if (port < 32)
528 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
529 else if (port < 36)
530 return CVMX_PKO_QUEUES_PER_PORT_PCI;
531 else if (port < 40)
532 return CVMX_PKO_QUEUES_PER_PORT_LOOP;
533 else
534 return 0;
535}
536
537/**
538 * Get the status counters for a port.
539 *
540 * @port_num: Port number to get statistics for.
541 * @clear: Set to 1 to clear the counters after they are read
542 * @status: Where to put the results.
543 */
544static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
545 cvmx_pko_port_status_t *status)
546{
547 union cvmx_pko_reg_read_idx pko_reg_read_idx;
548 union cvmx_pko_mem_count0 pko_mem_count0;
549 union cvmx_pko_mem_count1 pko_mem_count1;
550
551 pko_reg_read_idx.u64 = 0;
552 pko_reg_read_idx.s.index = port_num;
553 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
554
555 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
556 status->packets = pko_mem_count0.s.count;
557 if (clear) {
558 pko_mem_count0.s.count = port_num;
559 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
560 }
561
562 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
563 status->octets = pko_mem_count1.s.count;
564 if (clear) {
565 pko_mem_count1.s.count = port_num;
566 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
567 }
568
569 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
570 union cvmx_pko_mem_debug9 debug9;
571 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
572 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
573 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
574 status->doorbell = debug9.cn38xx.doorbell;
575 } else {
576 union cvmx_pko_mem_debug8 debug8;
577 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
578 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
579 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
580 status->doorbell = debug8.cn58xx.doorbell;
581 }
582}
583
584/**
585 * Rate limit a PKO port to a max packets/sec. This function is only
586 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
587 *
588 * @port: Port to rate limit
589 * @packets_s: Maximum packet/sec
590 * @burst: Maximum number of packets to burst in a row before rate
591 * limiting cuts in.
592 *
593 * Returns Zero on success, negative on failure
594 */
595extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
596
597/**
598 * Rate limit a PKO port to a max bits/sec. This function is only
599 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
600 *
601 * @port: Port to rate limit
602 * @bits_s: PKO rate limit in bits/sec
603 * @burst: Maximum number of bits to burst before rate
604 * limiting cuts in.
605 *
606 * Returns Zero on success, negative on failure
607 */
608extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
609
610#endif /* __CVMX_PKO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
new file mode 100644
index 00000000000..999aefe3274
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -0,0 +1,1982 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Interface to the hardware Packet Order / Work unit.
30 *
31 * New, starting with SDK 1.7.0, cvmx-pow supports a number of
32 * extended consistency checks. The define
33 * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW
34 * internal state checks to find common programming errors. If
35 * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default
36 * enabled. For example, cvmx-pow will check for the following
37 * program errors or POW state inconsistency.
38 * - Requesting a POW operation with an active tag switch in
39 * progress.
40 * - Waiting for a tag switch to complete for an excessively
41 * long period. This is normally a sign of an error in locking
42 * causing deadlock.
43 * - Illegal tag switches from NULL_NULL.
44 * - Illegal tag switches from NULL.
45 * - Illegal deschedule request.
46 * - WQE pointer not matching the one attached to the core by
47 * the POW.
48 *
49 */
50
51#ifndef __CVMX_POW_H__
52#define __CVMX_POW_H__
53
54#include <asm/octeon/cvmx-pow-defs.h>
55
56#include "cvmx-scratch.h"
57#include "cvmx-wqe.h"
58
59/* Default to having all POW constancy checks turned on */
60#ifndef CVMX_ENABLE_POW_CHECKS
61#define CVMX_ENABLE_POW_CHECKS 1
62#endif
63
64enum cvmx_pow_tag_type {
65 /* Tag ordering is maintained */
66 CVMX_POW_TAG_TYPE_ORDERED = 0L,
67 /* Tag ordering is maintained, and at most one PP has the tag */
68 CVMX_POW_TAG_TYPE_ATOMIC = 1L,
69 /*
70 * The work queue entry from the order - NEVER tag switch from
71 * NULL to NULL
72 */
73 CVMX_POW_TAG_TYPE_NULL = 2L,
74 /* A tag switch to NULL, and there is no space reserved in POW
75 * - NEVER tag switch to NULL_NULL
76 * - NEVER tag switch from NULL_NULL
77 * - NULL_NULL is entered at the beginning of time and on a deschedule.
78 * - NULL_NULL can be exited by a new work request. A NULL_SWITCH
79 * load can also switch the state to NULL
80 */
81 CVMX_POW_TAG_TYPE_NULL_NULL = 3L
82};
83
84/**
85 * Wait flag values for pow functions.
86 */
87typedef enum {
88 CVMX_POW_WAIT = 1,
89 CVMX_POW_NO_WAIT = 0,
90} cvmx_pow_wait_t;
91
92/**
93 * POW tag operations. These are used in the data stored to the POW.
94 */
95typedef enum {
96 /*
97 * switch the tag (only) for this PP
98 * - the previous tag should be non-NULL in this case
99 * - tag switch response required
100 * - fields used: op, type, tag
101 */
102 CVMX_POW_TAG_OP_SWTAG = 0L,
103 /*
104 * switch the tag for this PP, with full information
105 * - this should be used when the previous tag is NULL
106 * - tag switch response required
107 * - fields used: address, op, grp, type, tag
108 */
109 CVMX_POW_TAG_OP_SWTAG_FULL = 1L,
110 /*
111 * switch the tag (and/or group) for this PP and de-schedule
112 * - OK to keep the tag the same and only change the group
113 * - fields used: op, no_sched, grp, type, tag
114 */
115 CVMX_POW_TAG_OP_SWTAG_DESCH = 2L,
116 /*
117 * just de-schedule
118 * - fields used: op, no_sched
119 */
120 CVMX_POW_TAG_OP_DESCH = 3L,
121 /*
122 * create an entirely new work queue entry
123 * - fields used: address, op, qos, grp, type, tag
124 */
125 CVMX_POW_TAG_OP_ADDWQ = 4L,
126 /*
127 * just update the work queue pointer and grp for this PP
128 * - fields used: address, op, grp
129 */
130 CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L,
131 /*
132 * set the no_sched bit on the de-schedule list
133 *
134 * - does nothing if the selected entry is not on the
135 * de-schedule list
136 *
137 * - does nothing if the stored work queue pointer does not
138 * match the address field
139 *
140 * - fields used: address, index, op
141 *
142 * Before issuing a *_NSCHED operation, SW must guarantee
143 * that all prior deschedules and set/clr NSCHED operations
144 * are complete and all prior switches are complete. The
145 * hardware provides the opsdone bit and swdone bit for SW
146 * polling. After issuing a *_NSCHED operation, SW must
147 * guarantee that the set/clr NSCHED is complete before any
148 * subsequent operations.
149 */
150 CVMX_POW_TAG_OP_SET_NSCHED = 6L,
151 /*
152 * clears the no_sched bit on the de-schedule list
153 *
154 * - does nothing if the selected entry is not on the
155 * de-schedule list
156 *
157 * - does nothing if the stored work queue pointer does not
158 * match the address field
159 *
160 * - fields used: address, index, op
161 *
162 * Before issuing a *_NSCHED operation, SW must guarantee that
163 * all prior deschedules and set/clr NSCHED operations are
164 * complete and all prior switches are complete. The hardware
165 * provides the opsdone bit and swdone bit for SW
166 * polling. After issuing a *_NSCHED operation, SW must
167 * guarantee that the set/clr NSCHED is complete before any
168 * subsequent operations.
169 */
170 CVMX_POW_TAG_OP_CLR_NSCHED = 7L,
171 /* do nothing */
172 CVMX_POW_TAG_OP_NOP = 15L
173} cvmx_pow_tag_op_t;
174
175/**
176 * This structure defines the store data on a store to POW
177 */
178typedef union {
179 uint64_t u64;
180 struct {
181 /*
182 * Don't reschedule this entry. no_sched is used for
183 * CVMX_POW_TAG_OP_SWTAG_DESCH and
184 * CVMX_POW_TAG_OP_DESCH
185 */
186 uint64_t no_sched:1;
187 uint64_t unused:2;
188 /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
189 uint64_t index:13;
190 /* The operation to perform */
191 cvmx_pow_tag_op_t op:4;
192 uint64_t unused2:2;
193 /*
194 * The QOS level for the packet. qos is only used for
195 * CVMX_POW_TAG_OP_ADDWQ
196 */
197 uint64_t qos:3;
198 /*
199 * The group that the work queue entry will be
200 * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ,
201 * CVMX_POW_TAG_OP_SWTAG_FULL,
202 * CVMX_POW_TAG_OP_SWTAG_DESCH, and
203 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP
204 */
205 uint64_t grp:4;
206 /*
207 * The type of the tag. type is used for everything
208 * except CVMX_POW_TAG_OP_DESCH,
209 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
210 * CVMX_POW_TAG_OP_*_NSCHED
211 */
212 uint64_t type:3;
213 /*
214 * The actual tag. tag is used for everything except
215 * CVMX_POW_TAG_OP_DESCH,
216 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
217 * CVMX_POW_TAG_OP_*_NSCHED
218 */
219 uint64_t tag:32;
220 } s;
221} cvmx_pow_tag_req_t;
222
223/**
224 * This structure describes the address to load stuff from POW
225 */
226typedef union {
227 uint64_t u64;
228
229 /**
230 * Address for new work request loads (did<2:0> == 0)
231 */
232 struct {
233 /* Mips64 address region. Should be CVMX_IO_SEG */
234 uint64_t mem_region:2;
235 /* Must be zero */
236 uint64_t reserved_49_61:13;
237 /* Must be one */
238 uint64_t is_io:1;
239 /* the ID of POW -- did<2:0> == 0 in this case */
240 uint64_t did:8;
241 /* Must be zero */
242 uint64_t reserved_4_39:36;
243 /*
244 * If set, don't return load response until work is
245 * available.
246 */
247 uint64_t wait:1;
248 /* Must be zero */
249 uint64_t reserved_0_2:3;
250 } swork;
251
252 /**
253 * Address for loads to get POW internal status
254 */
255 struct {
256 /* Mips64 address region. Should be CVMX_IO_SEG */
257 uint64_t mem_region:2;
258 /* Must be zero */
259 uint64_t reserved_49_61:13;
260 /* Must be one */
261 uint64_t is_io:1;
262 /* the ID of POW -- did<2:0> == 1 in this case */
263 uint64_t did:8;
264 /* Must be zero */
265 uint64_t reserved_10_39:30;
266 /* The core id to get status for */
267 uint64_t coreid:4;
268 /*
269 * If set and get_cur is set, return reverse tag-list
270 * pointer rather than forward tag-list pointer.
271 */
272 uint64_t get_rev:1;
273 /*
274 * If set, return current status rather than pending
275 * status.
276 */
277 uint64_t get_cur:1;
278 /*
279 * If set, get the work-queue pointer rather than
280 * tag/type.
281 */
282 uint64_t get_wqp:1;
283 /* Must be zero */
284 uint64_t reserved_0_2:3;
285 } sstatus;
286
287 /**
288 * Address for memory loads to get POW internal state
289 */
290 struct {
291 /* Mips64 address region. Should be CVMX_IO_SEG */
292 uint64_t mem_region:2;
293 /* Must be zero */
294 uint64_t reserved_49_61:13;
295 /* Must be one */
296 uint64_t is_io:1;
297 /* the ID of POW -- did<2:0> == 2 in this case */
298 uint64_t did:8;
299 /* Must be zero */
300 uint64_t reserved_16_39:24;
301 /* POW memory index */
302 uint64_t index:11;
303 /*
304 * If set, return deschedule information rather than
305 * the standard response for work-queue index (invalid
306 * if the work-queue entry is not on the deschedule
307 * list).
308 */
309 uint64_t get_des:1;
310 /*
311 * If set, get the work-queue pointer rather than
312 * tag/type (no effect when get_des set).
313 */
314 uint64_t get_wqp:1;
315 /* Must be zero */
316 uint64_t reserved_0_2:3;
317 } smemload;
318
319 /**
320 * Address for index/pointer loads
321 */
322 struct {
323 /* Mips64 address region. Should be CVMX_IO_SEG */
324 uint64_t mem_region:2;
325 /* Must be zero */
326 uint64_t reserved_49_61:13;
327 /* Must be one */
328 uint64_t is_io:1;
329 /* the ID of POW -- did<2:0> == 3 in this case */
330 uint64_t did:8;
331 /* Must be zero */
332 uint64_t reserved_9_39:31;
333 /*
334 * when {get_rmt ==0 AND get_des_get_tail == 0}, this
335 * field selects one of eight POW internal-input
336 * queues (0-7), one per QOS level; values 8-15 are
337 * illegal in this case; when {get_rmt ==0 AND
338 * get_des_get_tail == 1}, this field selects one of
339 * 16 deschedule lists (per group); when get_rmt ==1,
340 * this field selects one of 16 memory-input queue
341 * lists. The two memory-input queue lists associated
342 * with each QOS level are:
343 *
344 * - qosgrp = 0, qosgrp = 8: QOS0
345 * - qosgrp = 1, qosgrp = 9: QOS1
346 * - qosgrp = 2, qosgrp = 10: QOS2
347 * - qosgrp = 3, qosgrp = 11: QOS3
348 * - qosgrp = 4, qosgrp = 12: QOS4
349 * - qosgrp = 5, qosgrp = 13: QOS5
350 * - qosgrp = 6, qosgrp = 14: QOS6
351 * - qosgrp = 7, qosgrp = 15: QOS7
352 */
353 uint64_t qosgrp:4;
354 /*
355 * If set and get_rmt is clear, return deschedule list
356 * indexes rather than indexes for the specified qos
357 * level; if set and get_rmt is set, return the tail
358 * pointer rather than the head pointer for the
359 * specified qos level.
360 */
361 uint64_t get_des_get_tail:1;
362 /*
363 * If set, return remote pointers rather than the
364 * local indexes for the specified qos level.
365 */
366 uint64_t get_rmt:1;
367 /* Must be zero */
368 uint64_t reserved_0_2:3;
369 } sindexload;
370
371 /**
372 * address for NULL_RD request (did<2:0> == 4) when this is read,
373 * HW attempts to change the state to NULL if it is NULL_NULL (the
374 * hardware cannot switch from NULL_NULL to NULL if a POW entry is
375 * not available - software may need to recover by finishing
376 * another piece of work before a POW entry can ever become
377 * available.)
378 */
379 struct {
380 /* Mips64 address region. Should be CVMX_IO_SEG */
381 uint64_t mem_region:2;
382 /* Must be zero */
383 uint64_t reserved_49_61:13;
384 /* Must be one */
385 uint64_t is_io:1;
386 /* the ID of POW -- did<2:0> == 4 in this case */
387 uint64_t did:8;
388 /* Must be zero */
389 uint64_t reserved_0_39:40;
390 } snull_rd;
391} cvmx_pow_load_addr_t;
392
393/**
394 * This structure defines the response to a load/SENDSINGLE to POW
395 * (except CSR reads)
396 */
397typedef union {
398 uint64_t u64;
399
400 /**
401 * Response to new work request loads
402 */
403 struct {
404 /*
405 * Set when no new work queue entry was returned. *
406 * If there was de-scheduled work, the HW will
407 * definitely return it. When this bit is set, it
408 * could mean either mean:
409 *
410 * - There was no work, or
411 *
412 * - There was no work that the HW could find. This
413 * case can happen, regardless of the wait bit value
414 * in the original request, when there is work in
415 * the IQ's that is too deep down the list.
416 */
417 uint64_t no_work:1;
418 /* Must be zero */
419 uint64_t reserved_40_62:23;
420 /* 36 in O1 -- the work queue pointer */
421 uint64_t addr:40;
422 } s_work;
423
424 /**
425 * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
426 */
427 struct {
428 uint64_t reserved_62_63:2;
429 /* Set when there is a pending non-NULL SWTAG or
430 * SWTAG_FULL, and the POW entry has not left the list
431 * for the original tag. */
432 uint64_t pend_switch:1;
433 /* Set when SWTAG_FULL and pend_switch is set. */
434 uint64_t pend_switch_full:1;
435 /*
436 * Set when there is a pending NULL SWTAG, or an
437 * implicit switch to NULL.
438 */
439 uint64_t pend_switch_null:1;
440 /* Set when there is a pending DESCHED or SWTAG_DESCHED. */
441 uint64_t pend_desched:1;
442 /*
443 * Set when there is a pending SWTAG_DESCHED and
444 * pend_desched is set.
445 */
446 uint64_t pend_desched_switch:1;
447 /* Set when nosched is desired and pend_desched is set. */
448 uint64_t pend_nosched:1;
449 /* Set when there is a pending GET_WORK. */
450 uint64_t pend_new_work:1;
451 /*
452 * When pend_new_work is set, this bit indicates that
453 * the wait bit was set.
454 */
455 uint64_t pend_new_work_wait:1;
456 /* Set when there is a pending NULL_RD. */
457 uint64_t pend_null_rd:1;
458 /* Set when there is a pending CLR_NSCHED. */
459 uint64_t pend_nosched_clr:1;
460 uint64_t reserved_51:1;
461 /* This is the index when pend_nosched_clr is set. */
462 uint64_t pend_index:11;
463 /*
464 * This is the new_grp when (pend_desched AND
465 * pend_desched_switch) is set.
466 */
467 uint64_t pend_grp:4;
468 uint64_t reserved_34_35:2;
469 /*
470 * This is the tag type when pend_switch or
471 * (pend_desched AND pend_desched_switch) are set.
472 */
473 uint64_t pend_type:2;
474 /*
475 * - this is the tag when pend_switch or (pend_desched
476 * AND pend_desched_switch) are set.
477 */
478 uint64_t pend_tag:32;
479 } s_sstatus0;
480
481 /**
482 * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
483 */
484 struct {
485 uint64_t reserved_62_63:2;
486 /*
487 * Set when there is a pending non-NULL SWTAG or
488 * SWTAG_FULL, and the POW entry has not left the list
489 * for the original tag.
490 */
491 uint64_t pend_switch:1;
492 /* Set when SWTAG_FULL and pend_switch is set. */
493 uint64_t pend_switch_full:1;
494 /*
495 * Set when there is a pending NULL SWTAG, or an
496 * implicit switch to NULL.
497 */
498 uint64_t pend_switch_null:1;
499 /*
500 * Set when there is a pending DESCHED or
501 * SWTAG_DESCHED.
502 */
503 uint64_t pend_desched:1;
504 /*
505 * Set when there is a pending SWTAG_DESCHED and
506 * pend_desched is set.
507 */
508 uint64_t pend_desched_switch:1;
509 /* Set when nosched is desired and pend_desched is set. */
510 uint64_t pend_nosched:1;
511 /* Set when there is a pending GET_WORK. */
512 uint64_t pend_new_work:1;
513 /*
514 * When pend_new_work is set, this bit indicates that
515 * the wait bit was set.
516 */
517 uint64_t pend_new_work_wait:1;
518 /* Set when there is a pending NULL_RD. */
519 uint64_t pend_null_rd:1;
520 /* Set when there is a pending CLR_NSCHED. */
521 uint64_t pend_nosched_clr:1;
522 uint64_t reserved_51:1;
523 /* This is the index when pend_nosched_clr is set. */
524 uint64_t pend_index:11;
525 /*
526 * This is the new_grp when (pend_desched AND
527 * pend_desched_switch) is set.
528 */
529 uint64_t pend_grp:4;
530 /* This is the wqp when pend_nosched_clr is set. */
531 uint64_t pend_wqp:36;
532 } s_sstatus1;
533
534 /**
535 * Result for a POW Status Load (when get_cur==1, get_wqp==0, and
536 * get_rev==0)
537 */
538 struct {
539 uint64_t reserved_62_63:2;
540 /*
541 * Points to the next POW entry in the tag list when
542 * tail == 0 (and tag_type is not NULL or NULL_NULL).
543 */
544 uint64_t link_index:11;
545 /* The POW entry attached to the core. */
546 uint64_t index:11;
547 /*
548 * The group attached to the core (updated when new
549 * tag list entered on SWTAG_FULL).
550 */
551 uint64_t grp:4;
552 /*
553 * Set when this POW entry is at the head of its tag
554 * list (also set when in the NULL or NULL_NULL
555 * state).
556 */
557 uint64_t head:1;
558 /*
559 * Set when this POW entry is at the tail of its tag
560 * list (also set when in the NULL or NULL_NULL
561 * state).
562 */
563 uint64_t tail:1;
564 /*
565 * The tag type attached to the core (updated when new
566 * tag list entered on SWTAG, SWTAG_FULL, or
567 * SWTAG_DESCHED).
568 */
569 uint64_t tag_type:2;
570 /*
571 * The tag attached to the core (updated when new tag
572 * list entered on SWTAG, SWTAG_FULL, or
573 * SWTAG_DESCHED).
574 */
575 uint64_t tag:32;
576 } s_sstatus2;
577
578 /**
579 * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
580 */
581 struct {
582 uint64_t reserved_62_63:2;
583 /*
584 * Points to the prior POW entry in the tag list when
585 * head == 0 (and tag_type is not NULL or
586 * NULL_NULL). This field is unpredictable when the
587 * core's state is NULL or NULL_NULL.
588 */
589 uint64_t revlink_index:11;
590 /* The POW entry attached to the core. */
591 uint64_t index:11;
592 /*
593 * The group attached to the core (updated when new
594 * tag list entered on SWTAG_FULL).
595 */
596 uint64_t grp:4;
597 /* Set when this POW entry is at the head of its tag
598 * list (also set when in the NULL or NULL_NULL
599 * state).
600 */
601 uint64_t head:1;
602 /*
603 * Set when this POW entry is at the tail of its tag
604 * list (also set when in the NULL or NULL_NULL
605 * state).
606 */
607 uint64_t tail:1;
608 /*
609 * The tag type attached to the core (updated when new
610 * tag list entered on SWTAG, SWTAG_FULL, or
611 * SWTAG_DESCHED).
612 */
613 uint64_t tag_type:2;
614 /*
615 * The tag attached to the core (updated when new tag
616 * list entered on SWTAG, SWTAG_FULL, or
617 * SWTAG_DESCHED).
618 */
619 uint64_t tag:32;
620 } s_sstatus3;
621
622 /**
623 * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
624 * get_rev==0)
625 */
626 struct {
627 uint64_t reserved_62_63:2;
628 /*
629 * Points to the next POW entry in the tag list when
630 * tail == 0 (and tag_type is not NULL or NULL_NULL).
631 */
632 uint64_t link_index:11;
633 /* The POW entry attached to the core. */
634 uint64_t index:11;
635 /*
636 * The group attached to the core (updated when new
637 * tag list entered on SWTAG_FULL).
638 */
639 uint64_t grp:4;
640 /*
641 * The wqp attached to the core (updated when new tag
642 * list entered on SWTAG_FULL).
643 */
644 uint64_t wqp:36;
645 } s_sstatus4;
646
647 /**
648 * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
649 * get_rev==1)
650 */
651 struct {
652 uint64_t reserved_62_63:2;
653 /*
654 * Points to the prior POW entry in the tag list when
655 * head == 0 (and tag_type is not NULL or
656 * NULL_NULL). This field is unpredictable when the
657 * core's state is NULL or NULL_NULL.
658 */
659 uint64_t revlink_index:11;
660 /* The POW entry attached to the core. */
661 uint64_t index:11;
662 /*
663 * The group attached to the core (updated when new
664 * tag list entered on SWTAG_FULL).
665 */
666 uint64_t grp:4;
667 /*
668 * The wqp attached to the core (updated when new tag
669 * list entered on SWTAG_FULL).
670 */
671 uint64_t wqp:36;
672 } s_sstatus5;
673
674 /**
675 * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
676 */
677 struct {
678 uint64_t reserved_51_63:13;
679 /*
680 * The next entry in the input, free, descheduled_head
681 * list (unpredictable if entry is the tail of the
682 * list).
683 */
684 uint64_t next_index:11;
685 /* The group of the POW entry. */
686 uint64_t grp:4;
687 uint64_t reserved_35:1;
688 /*
689 * Set when this POW entry is at the tail of its tag
690 * list (also set when in the NULL or NULL_NULL
691 * state).
692 */
693 uint64_t tail:1;
694 /* The tag type of the POW entry. */
695 uint64_t tag_type:2;
696 /* The tag of the POW entry. */
697 uint64_t tag:32;
698 } s_smemload0;
699
700 /**
701 * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
702 */
703 struct {
704 uint64_t reserved_51_63:13;
705 /*
706 * The next entry in the input, free, descheduled_head
707 * list (unpredictable if entry is the tail of the
708 * list).
709 */
710 uint64_t next_index:11;
711 /* The group of the POW entry. */
712 uint64_t grp:4;
713 /* The WQP held in the POW entry. */
714 uint64_t wqp:36;
715 } s_smemload1;
716
717 /**
718 * Result For POW Memory Load (get_des == 1)
719 */
720 struct {
721 uint64_t reserved_51_63:13;
722 /*
723 * The next entry in the tag list connected to the
724 * descheduled head.
725 */
726 uint64_t fwd_index:11;
727 /* The group of the POW entry. */
728 uint64_t grp:4;
729 /* The nosched bit for the POW entry. */
730 uint64_t nosched:1;
731 /* There is a pending tag switch */
732 uint64_t pend_switch:1;
733 /*
734 * The next tag type for the new tag list when
735 * pend_switch is set.
736 */
737 uint64_t pend_type:2;
738 /*
739 * The next tag for the new tag list when pend_switch
740 * is set.
741 */
742 uint64_t pend_tag:32;
743 } s_smemload2;
744
745 /**
746 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
747 */
748 struct {
749 uint64_t reserved_52_63:12;
750 /*
751 * set when there is one or more POW entries on the
752 * free list.
753 */
754 uint64_t free_val:1;
755 /*
756 * set when there is exactly one POW entry on the free
757 * list.
758 */
759 uint64_t free_one:1;
760 uint64_t reserved_49:1;
761 /*
762 * when free_val is set, indicates the first entry on
763 * the free list.
764 */
765 uint64_t free_head:11;
766 uint64_t reserved_37:1;
767 /*
768 * when free_val is set, indicates the last entry on
769 * the free list.
770 */
771 uint64_t free_tail:11;
772 /*
773 * set when there is one or more POW entries on the
774 * input Q list selected by qosgrp.
775 */
776 uint64_t loc_val:1;
777 /*
778 * set when there is exactly one POW entry on the
779 * input Q list selected by qosgrp.
780 */
781 uint64_t loc_one:1;
782 uint64_t reserved_23:1;
783 /*
784 * when loc_val is set, indicates the first entry on
785 * the input Q list selected by qosgrp.
786 */
787 uint64_t loc_head:11;
788 uint64_t reserved_11:1;
789 /*
790 * when loc_val is set, indicates the last entry on
791 * the input Q list selected by qosgrp.
792 */
793 uint64_t loc_tail:11;
794 } sindexload0;
795
796 /**
797 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
798 */
799 struct {
800 uint64_t reserved_52_63:12;
801 /*
802 * set when there is one or more POW entries on the
803 * nosched list.
804 */
805 uint64_t nosched_val:1;
806 /*
807 * set when there is exactly one POW entry on the
808 * nosched list.
809 */
810 uint64_t nosched_one:1;
811 uint64_t reserved_49:1;
812 /*
813 * when nosched_val is set, indicates the first entry
814 * on the nosched list.
815 */
816 uint64_t nosched_head:11;
817 uint64_t reserved_37:1;
818 /*
819 * when nosched_val is set, indicates the last entry
820 * on the nosched list.
821 */
822 uint64_t nosched_tail:11;
823 /*
824 * set when there is one or more descheduled heads on
825 * the descheduled list selected by qosgrp.
826 */
827 uint64_t des_val:1;
828 /*
829 * set when there is exactly one descheduled head on
830 * the descheduled list selected by qosgrp.
831 */
832 uint64_t des_one:1;
833 uint64_t reserved_23:1;
834 /*
835 * when des_val is set, indicates the first
836 * descheduled head on the descheduled list selected
837 * by qosgrp.
838 */
839 uint64_t des_head:11;
840 uint64_t reserved_11:1;
841 /*
842 * when des_val is set, indicates the last descheduled
843 * head on the descheduled list selected by qosgrp.
844 */
845 uint64_t des_tail:11;
846 } sindexload1;
847
848 /**
849 * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
850 */
851 struct {
852 uint64_t reserved_39_63:25;
853 /*
854 * Set when this DRAM list is the current head
855 * (i.e. is the next to be reloaded when the POW
856 * hardware reloads a POW entry from DRAM). The POW
857 * hardware alternates between the two DRAM lists
858 * associated with a QOS level when it reloads work
859 * from DRAM into the POW unit.
860 */
861 uint64_t rmt_is_head:1;
862 /*
863 * Set when the DRAM portion of the input Q list
864 * selected by qosgrp contains one or more pieces of
865 * work.
866 */
867 uint64_t rmt_val:1;
868 /*
869 * Set when the DRAM portion of the input Q list
870 * selected by qosgrp contains exactly one piece of
871 * work.
872 */
873 uint64_t rmt_one:1;
874 /*
875 * When rmt_val is set, indicates the first piece of
876 * work on the DRAM input Q list selected by
877 * qosgrp.
878 */
879 uint64_t rmt_head:36;
880 } sindexload2;
881
882 /**
883 * Result For POW Index/Pointer Load (get_rmt ==
884 * 1/get_des_get_tail == 1)
885 */
886 struct {
887 uint64_t reserved_39_63:25;
888 /*
889 * set when this DRAM list is the current head
890 * (i.e. is the next to be reloaded when the POW
891 * hardware reloads a POW entry from DRAM). The POW
892 * hardware alternates between the two DRAM lists
893 * associated with a QOS level when it reloads work
894 * from DRAM into the POW unit.
895 */
896 uint64_t rmt_is_head:1;
897 /*
898 * set when the DRAM portion of the input Q list
899 * selected by qosgrp contains one or more pieces of
900 * work.
901 */
902 uint64_t rmt_val:1;
903 /*
904 * set when the DRAM portion of the input Q list
905 * selected by qosgrp contains exactly one piece of
906 * work.
907 */
908 uint64_t rmt_one:1;
909 /*
910 * when rmt_val is set, indicates the last piece of
911 * work on the DRAM input Q list selected by
912 * qosgrp.
913 */
914 uint64_t rmt_tail:36;
915 } sindexload3;
916
917 /**
918 * Response to NULL_RD request loads
919 */
920 struct {
921 uint64_t unused:62;
922 /* of type cvmx_pow_tag_type_t. state is one of the
923 * following:
924 *
925 * - CVMX_POW_TAG_TYPE_ORDERED
926 * - CVMX_POW_TAG_TYPE_ATOMIC
927 * - CVMX_POW_TAG_TYPE_NULL
928 * - CVMX_POW_TAG_TYPE_NULL_NULL
929 */
930 uint64_t state:2;
931 } s_null_rd;
932
933} cvmx_pow_tag_load_resp_t;
934
935/**
936 * This structure describes the address used for stores to the POW.
937 * The store address is meaningful on stores to the POW. The
938 * hardware assumes that an aligned 64-bit store was used for all
939 * these stores. Note the assumption that the work queue entry is
940 * aligned on an 8-byte boundary (since the low-order 3 address bits
941 * must be zero). Note that not all fields are used by all
942 * operations.
943 *
944 * NOTE: The following is the behavior of the pending switch bit at the PP
945 * for POW stores (i.e. when did<7:3> == 0xc)
946 * - did<2:0> == 0 => pending switch bit is set
947 * - did<2:0> == 1 => no affect on the pending switch bit
948 * - did<2:0> == 3 => pending switch bit is cleared
949 * - did<2:0> == 7 => no affect on the pending switch bit
950 * - did<2:0> == others => must not be used
951 * - No other loads/stores have an affect on the pending switch bit
952 * - The switch bus from POW can clear the pending switch bit
953 *
954 * NOTE: did<2:0> == 2 is used by the HW for a special single-cycle
955 * ADDWQ command that only contains the pointer). SW must never use
956 * did<2:0> == 2.
957 */
958typedef union {
959 /**
960 * Unsigned 64 bit integer representation of store address
961 */
962 uint64_t u64;
963
964 struct {
965 /* Memory region. Should be CVMX_IO_SEG in most cases */
966 uint64_t mem_reg:2;
967 uint64_t reserved_49_61:13; /* Must be zero */
968 uint64_t is_io:1; /* Must be one */
969 /* Device ID of POW. Note that different sub-dids are used. */
970 uint64_t did:8;
971 uint64_t reserved_36_39:4; /* Must be zero */
972 /* Address field. addr<2:0> must be zero */
973 uint64_t addr:36;
974 } stag;
975} cvmx_pow_tag_store_addr_t;
976
977/**
978 * decode of the store data when an IOBDMA SENDSINGLE is sent to POW
979 */
980typedef union {
981 uint64_t u64;
982
983 struct {
984 /*
985 * the (64-bit word) location in scratchpad to write
986 * to (if len != 0)
987 */
988 uint64_t scraddr:8;
989 /* the number of words in the response (0 => no response) */
990 uint64_t len:8;
991 /* the ID of the device on the non-coherent bus */
992 uint64_t did:8;
993 uint64_t unused:36;
994 /* if set, don't return load response until work is available */
995 uint64_t wait:1;
996 uint64_t unused2:3;
997 } s;
998
999} cvmx_pow_iobdma_store_t;
1000
1001/* CSR typedefs have been moved to cvmx-csr-*.h */
1002
1003/**
1004 * Get the POW tag for this core. This returns the current
1005 * tag type, tag, group, and POW entry index associated with
1006 * this core. Index is only valid if the tag type isn't NULL_NULL.
1007 * If a tag switch is pending this routine returns the tag before
1008 * the tag switch, not after.
1009 *
1010 * Returns Current tag
1011 */
1012static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void)
1013{
1014 cvmx_pow_load_addr_t load_addr;
1015 cvmx_pow_tag_load_resp_t load_resp;
1016 cvmx_pow_tag_req_t result;
1017
1018 load_addr.u64 = 0;
1019 load_addr.sstatus.mem_region = CVMX_IO_SEG;
1020 load_addr.sstatus.is_io = 1;
1021 load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
1022 load_addr.sstatus.coreid = cvmx_get_core_num();
1023 load_addr.sstatus.get_cur = 1;
1024 load_resp.u64 = cvmx_read_csr(load_addr.u64);
1025 result.u64 = 0;
1026 result.s.grp = load_resp.s_sstatus2.grp;
1027 result.s.index = load_resp.s_sstatus2.index;
1028 result.s.type = load_resp.s_sstatus2.tag_type;
1029 result.s.tag = load_resp.s_sstatus2.tag;
1030 return result;
1031}
1032
1033/**
1034 * Get the POW WQE for this core. This returns the work queue
1035 * entry currently associated with this core.
1036 *
1037 * Returns WQE pointer
1038 */
1039static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void)
1040{
1041 cvmx_pow_load_addr_t load_addr;
1042 cvmx_pow_tag_load_resp_t load_resp;
1043
1044 load_addr.u64 = 0;
1045 load_addr.sstatus.mem_region = CVMX_IO_SEG;
1046 load_addr.sstatus.is_io = 1;
1047 load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
1048 load_addr.sstatus.coreid = cvmx_get_core_num();
1049 load_addr.sstatus.get_cur = 1;
1050 load_addr.sstatus.get_wqp = 1;
1051 load_resp.u64 = cvmx_read_csr(load_addr.u64);
1052 return (cvmx_wqe_t *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
1053}
1054
1055#ifndef CVMX_MF_CHORD
1056#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30)
1057#endif
1058
1059/**
1060 * Print a warning if a tag switch is pending for this core
1061 *
1062 * @function: Function name checking for a pending tag switch
1063 */
1064static inline void __cvmx_pow_warn_if_pending_switch(const char *function)
1065{
1066 uint64_t switch_complete;
1067 CVMX_MF_CHORD(switch_complete);
1068 if (!switch_complete)
1069 pr_warning("%s called with tag switch in progress\n", function);
1070}
1071
1072/**
1073 * Waits for a tag switch to complete by polling the completion bit.
1074 * Note that switches to NULL complete immediately and do not need
1075 * to be waited for.
1076 */
1077static inline void cvmx_pow_tag_sw_wait(void)
1078{
1079 const uint64_t MAX_CYCLES = 1ull << 31;
1080 uint64_t switch_complete;
1081 uint64_t start_cycle = cvmx_get_cycle();
1082 while (1) {
1083 CVMX_MF_CHORD(switch_complete);
1084 if (unlikely(switch_complete))
1085 break;
1086 if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) {
1087 pr_warning("Tag switch is taking a long time, "
1088 "possible deadlock\n");
1089 start_cycle = -MAX_CYCLES - 1;
1090 }
1091 }
1092}
1093
1094/**
1095 * Synchronous work request. Requests work from the POW.
1096 * This function does NOT wait for previous tag switches to complete,
1097 * so the caller must ensure that there is not a pending tag switch.
1098 *
1099 * @wait: When set, call stalls until work becomes avaiable, or times out.
1100 * If not set, returns immediately.
1101 *
1102 * Returns Returns the WQE pointer from POW. Returns NULL if no work
1103 * was available.
1104 */
1105static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
1106 wait)
1107{
1108 cvmx_pow_load_addr_t ptr;
1109 cvmx_pow_tag_load_resp_t result;
1110
1111 if (CVMX_ENABLE_POW_CHECKS)
1112 __cvmx_pow_warn_if_pending_switch(__func__);
1113
1114 ptr.u64 = 0;
1115 ptr.swork.mem_region = CVMX_IO_SEG;
1116 ptr.swork.is_io = 1;
1117 ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG;
1118 ptr.swork.wait = wait;
1119
1120 result.u64 = cvmx_read_csr(ptr.u64);
1121
1122 if (result.s_work.no_work)
1123 return NULL;
1124 else
1125 return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
1126}
1127
1128/**
1129 * Synchronous work request. Requests work from the POW.
1130 * This function waits for any previous tag switch to complete before
1131 * requesting the new work.
1132 *
1133 * @wait: When set, call stalls until work becomes avaiable, or times out.
1134 * If not set, returns immediately.
1135 *
1136 * Returns Returns the WQE pointer from POW. Returns NULL if no work
1137 * was available.
1138 */
1139static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1140{
1141 if (CVMX_ENABLE_POW_CHECKS)
1142 __cvmx_pow_warn_if_pending_switch(__func__);
1143
1144 /* Must not have a switch pending when requesting work */
1145 cvmx_pow_tag_sw_wait();
1146 return cvmx_pow_work_request_sync_nocheck(wait);
1147
1148}
1149
1150/**
1151 * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state.
1152 * This function waits for any previous tag switch to complete before
1153 * requesting the null_rd.
1154 *
1155 * Returns Returns the POW state of type cvmx_pow_tag_type_t.
1156 */
1157static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
1158{
1159 cvmx_pow_load_addr_t ptr;
1160 cvmx_pow_tag_load_resp_t result;
1161
1162 if (CVMX_ENABLE_POW_CHECKS)
1163 __cvmx_pow_warn_if_pending_switch(__func__);
1164
1165 /* Must not have a switch pending when requesting work */
1166 cvmx_pow_tag_sw_wait();
1167
1168 ptr.u64 = 0;
1169 ptr.snull_rd.mem_region = CVMX_IO_SEG;
1170 ptr.snull_rd.is_io = 1;
1171 ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD;
1172
1173 result.u64 = cvmx_read_csr(ptr.u64);
1174
1175 return (enum cvmx_pow_tag_type) result.s_null_rd.state;
1176}
1177
1178/**
1179 * Asynchronous work request. Work is requested from the POW unit,
1180 * and should later be checked with function
1181 * cvmx_pow_work_response_async. This function does NOT wait for
1182 * previous tag switches to complete, so the caller must ensure that
1183 * there is not a pending tag switch.
1184 *
1185 * @scr_addr: Scratch memory address that response will be returned
1186 * to, which is either a valid WQE, or a response with the
1187 * invalid bit set. Byte address, must be 8 byte aligned.
1188 *
1189 * @wait: 1 to cause response to wait for work to become available (or
1190 * timeout), 0 to cause response to return immediately
1191 */
1192static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1193 cvmx_pow_wait_t wait)
1194{
1195 cvmx_pow_iobdma_store_t data;
1196
1197 if (CVMX_ENABLE_POW_CHECKS)
1198 __cvmx_pow_warn_if_pending_switch(__func__);
1199
1200 /* scr_addr must be 8 byte aligned */
1201 data.s.scraddr = scr_addr >> 3;
1202 data.s.len = 1;
1203 data.s.did = CVMX_OCT_DID_TAG_SWTAG;
1204 data.s.wait = wait;
1205 cvmx_send_single(data.u64);
1206}
1207
1208/**
1209 * Asynchronous work request. Work is requested from the POW unit,
1210 * and should later be checked with function
1211 * cvmx_pow_work_response_async. This function waits for any previous
1212 * tag switch to complete before requesting the new work.
1213 *
1214 * @scr_addr: Scratch memory address that response will be returned
1215 * to, which is either a valid WQE, or a response with the
1216 * invalid bit set. Byte address, must be 8 byte aligned.
1217 *
1218 * @wait: 1 to cause response to wait for work to become available (or
1219 * timeout), 0 to cause response to return immediately
1220 */
1221static inline void cvmx_pow_work_request_async(int scr_addr,
1222 cvmx_pow_wait_t wait)
1223{
1224 if (CVMX_ENABLE_POW_CHECKS)
1225 __cvmx_pow_warn_if_pending_switch(__func__);
1226
1227 /* Must not have a switch pending when requesting work */
1228 cvmx_pow_tag_sw_wait();
1229 cvmx_pow_work_request_async_nocheck(scr_addr, wait);
1230}
1231
1232/**
1233 * Gets result of asynchronous work request. Performs a IOBDMA sync
1234 * to wait for the response.
1235 *
1236 * @scr_addr: Scratch memory address to get result from Byte address,
1237 * must be 8 byte aligned.
1238 *
1239 * Returns Returns the WQE from the scratch register, or NULL if no
1240 * work was available.
1241 */
1242static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr)
1243{
1244 cvmx_pow_tag_load_resp_t result;
1245
1246 CVMX_SYNCIOBDMA;
1247 result.u64 = cvmx_scratch_read64(scr_addr);
1248
1249 if (result.s_work.no_work)
1250 return NULL;
1251 else
1252 return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
1253}
1254
1255/**
1256 * Checks if a work queue entry pointer returned by a work
1257 * request is valid. It may be invalid due to no work
1258 * being available or due to a timeout.
1259 *
1260 * @wqe_ptr: pointer to a work queue entry returned by the POW
1261 *
1262 * Returns 0 if pointer is valid
1263 * 1 if invalid (no work was returned)
1264 */
1265static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr)
1266{
1267 return wqe_ptr == NULL;
1268}
1269
1270/**
1271 * Starts a tag switch to the provided tag value and tag type.
1272 * Completion for the tag switch must be checked for separately. This
1273 * function does NOT update the work queue entry in dram to match tag
1274 * value and type, so the application must keep track of these if they
1275 * are important to the application. This tag switch command must not
1276 * be used for switches to NULL, as the tag switch pending bit will be
1277 * set by the switch request, but never cleared by the hardware.
1278 *
1279 * NOTE: This should not be used when switching from a NULL tag. Use
1280 * cvmx_pow_tag_sw_full() instead.
1281 *
1282 * This function does no checks, so the caller must ensure that any
1283 * previous tag switch has completed.
1284 *
1285 * @tag: new tag value
1286 * @tag_type: new tag type (ordered or atomic)
1287 */
1288static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag,
1289 enum cvmx_pow_tag_type tag_type)
1290{
1291 cvmx_addr_t ptr;
1292 cvmx_pow_tag_req_t tag_req;
1293
1294 if (CVMX_ENABLE_POW_CHECKS) {
1295 cvmx_pow_tag_req_t current_tag;
1296 __cvmx_pow_warn_if_pending_switch(__func__);
1297 current_tag = cvmx_pow_get_current_tag();
1298 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1299 pr_warning("%s called with NULL_NULL tag\n",
1300 __func__);
1301 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1302 pr_warning("%s called with NULL tag\n", __func__);
1303 if ((current_tag.s.type == tag_type)
1304 && (current_tag.s.tag == tag))
1305 pr_warning("%s called to perform a tag switch to the "
1306 "same tag\n",
1307 __func__);
1308 if (tag_type == CVMX_POW_TAG_TYPE_NULL)
1309 pr_warning("%s called to perform a tag switch to "
1310 "NULL. Use cvmx_pow_tag_sw_null() instead\n",
1311 __func__);
1312 }
1313
1314 /*
1315 * Note that WQE in DRAM is not updated here, as the POW does
1316 * not read from DRAM once the WQE is in flight. See hardware
1317 * manual for complete details. It is the application's
1318 * responsibility to keep track of the current tag value if
1319 * that is important.
1320 */
1321
1322 tag_req.u64 = 0;
1323 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
1324 tag_req.s.tag = tag;
1325 tag_req.s.type = tag_type;
1326
1327 ptr.u64 = 0;
1328 ptr.sio.mem_region = CVMX_IO_SEG;
1329 ptr.sio.is_io = 1;
1330 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
1331
1332 /* once this store arrives at POW, it will attempt the switch
1333 software must wait for the switch to complete separately */
1334 cvmx_write_io(ptr.u64, tag_req.u64);
1335}
1336
1337/**
1338 * Starts a tag switch to the provided tag value and tag type.
1339 * Completion for the tag switch must be checked for separately. This
1340 * function does NOT update the work queue entry in dram to match tag
1341 * value and type, so the application must keep track of these if they
1342 * are important to the application. This tag switch command must not
1343 * be used for switches to NULL, as the tag switch pending bit will be
1344 * set by the switch request, but never cleared by the hardware.
1345 *
1346 * NOTE: This should not be used when switching from a NULL tag. Use
1347 * cvmx_pow_tag_sw_full() instead.
1348 *
1349 * This function waits for any previous tag switch to complete, and also
1350 * displays an error on tag switches to NULL.
1351 *
1352 * @tag: new tag value
1353 * @tag_type: new tag type (ordered or atomic)
1354 */
1355static inline void cvmx_pow_tag_sw(uint32_t tag,
1356 enum cvmx_pow_tag_type tag_type)
1357{
1358 if (CVMX_ENABLE_POW_CHECKS)
1359 __cvmx_pow_warn_if_pending_switch(__func__);
1360
1361 /*
1362 * Note that WQE in DRAM is not updated here, as the POW does
1363 * not read from DRAM once the WQE is in flight. See hardware
1364 * manual for complete details. It is the application's
1365 * responsibility to keep track of the current tag value if
1366 * that is important.
1367 */
1368
1369 /*
1370 * Ensure that there is not a pending tag switch, as a tag
1371 * switch cannot be started if a previous switch is still
1372 * pending.
1373 */
1374 cvmx_pow_tag_sw_wait();
1375 cvmx_pow_tag_sw_nocheck(tag, tag_type);
1376}
1377
1378/**
1379 * Starts a tag switch to the provided tag value and tag type.
1380 * Completion for the tag switch must be checked for separately. This
1381 * function does NOT update the work queue entry in dram to match tag
1382 * value and type, so the application must keep track of these if they
1383 * are important to the application. This tag switch command must not
1384 * be used for switches to NULL, as the tag switch pending bit will be
1385 * set by the switch request, but never cleared by the hardware.
1386 *
1387 * This function must be used for tag switches from NULL.
1388 *
1389 * This function does no checks, so the caller must ensure that any
1390 * previous tag switch has completed.
1391 *
1392 * @wqp: pointer to work queue entry to submit. This entry is
1393 * updated to match the other parameters
1394 * @tag: tag value to be assigned to work queue entry
1395 * @tag_type: type of tag
1396 * @group: group value for the work queue entry.
1397 */
1398static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag,
1399 enum cvmx_pow_tag_type tag_type,
1400 uint64_t group)
1401{
1402 cvmx_addr_t ptr;
1403 cvmx_pow_tag_req_t tag_req;
1404
1405 if (CVMX_ENABLE_POW_CHECKS) {
1406 cvmx_pow_tag_req_t current_tag;
1407 __cvmx_pow_warn_if_pending_switch(__func__);
1408 current_tag = cvmx_pow_get_current_tag();
1409 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1410 pr_warning("%s called with NULL_NULL tag\n",
1411 __func__);
1412 if ((current_tag.s.type == tag_type)
1413 && (current_tag.s.tag == tag))
1414 pr_warning("%s called to perform a tag switch to "
1415 "the same tag\n",
1416 __func__);
1417 if (tag_type == CVMX_POW_TAG_TYPE_NULL)
1418 pr_warning("%s called to perform a tag switch to "
1419 "NULL. Use cvmx_pow_tag_sw_null() instead\n",
1420 __func__);
1421 if (wqp != cvmx_phys_to_ptr(0x80))
1422 if (wqp != cvmx_pow_get_current_wqp())
1423 pr_warning("%s passed WQE(%p) doesn't match "
1424 "the address in the POW(%p)\n",
1425 __func__, wqp,
1426 cvmx_pow_get_current_wqp());
1427 }
1428
1429 /*
1430 * Note that WQE in DRAM is not updated here, as the POW does
1431 * not read from DRAM once the WQE is in flight. See hardware
1432 * manual for complete details. It is the application's
1433 * responsibility to keep track of the current tag value if
1434 * that is important.
1435 */
1436
1437 tag_req.u64 = 0;
1438 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL;
1439 tag_req.s.tag = tag;
1440 tag_req.s.type = tag_type;
1441 tag_req.s.grp = group;
1442
1443 ptr.u64 = 0;
1444 ptr.sio.mem_region = CVMX_IO_SEG;
1445 ptr.sio.is_io = 1;
1446 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
1447 ptr.sio.offset = CAST64(wqp);
1448
1449 /*
1450 * once this store arrives at POW, it will attempt the switch
1451 * software must wait for the switch to complete separately.
1452 */
1453 cvmx_write_io(ptr.u64, tag_req.u64);
1454}
1455
1456/**
1457 * Starts a tag switch to the provided tag value and tag type.
1458 * Completion for the tag switch must be checked for separately. This
1459 * function does NOT update the work queue entry in dram to match tag
1460 * value and type, so the application must keep track of these if they
1461 * are important to the application. This tag switch command must not
1462 * be used for switches to NULL, as the tag switch pending bit will be
1463 * set by the switch request, but never cleared by the hardware.
1464 *
1465 * This function must be used for tag switches from NULL.
1466 *
1467 * This function waits for any pending tag switches to complete
1468 * before requesting the tag switch.
1469 *
1470 * @wqp: pointer to work queue entry to submit. This entry is updated
1471 * to match the other parameters
1472 * @tag: tag value to be assigned to work queue entry
1473 * @tag_type: type of tag
1474 * @group: group value for the work queue entry.
1475 */
1476static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag,
1477 enum cvmx_pow_tag_type tag_type,
1478 uint64_t group)
1479{
1480 if (CVMX_ENABLE_POW_CHECKS)
1481 __cvmx_pow_warn_if_pending_switch(__func__);
1482
1483 /*
1484 * Ensure that there is not a pending tag switch, as a tag
1485 * switch cannot be started if a previous switch is still
1486 * pending.
1487 */
1488 cvmx_pow_tag_sw_wait();
1489 cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group);
1490}
1491
1492/**
1493 * Switch to a NULL tag, which ends any ordering or
1494 * synchronization provided by the POW for the current
1495 * work queue entry. This operation completes immediately,
1496 * so completion should not be waited for.
1497 * This function does NOT wait for previous tag switches to complete,
1498 * so the caller must ensure that any previous tag switches have completed.
1499 */
1500static inline void cvmx_pow_tag_sw_null_nocheck(void)
1501{
1502 cvmx_addr_t ptr;
1503 cvmx_pow_tag_req_t tag_req;
1504
1505 if (CVMX_ENABLE_POW_CHECKS) {
1506 cvmx_pow_tag_req_t current_tag;
1507 __cvmx_pow_warn_if_pending_switch(__func__);
1508 current_tag = cvmx_pow_get_current_tag();
1509 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1510 pr_warning("%s called with NULL_NULL tag\n",
1511 __func__);
1512 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1513 pr_warning("%s called when we already have a "
1514 "NULL tag\n",
1515 __func__);
1516 }
1517
1518 tag_req.u64 = 0;
1519 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
1520 tag_req.s.type = CVMX_POW_TAG_TYPE_NULL;
1521
1522 ptr.u64 = 0;
1523 ptr.sio.mem_region = CVMX_IO_SEG;
1524 ptr.sio.is_io = 1;
1525 ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
1526
1527 cvmx_write_io(ptr.u64, tag_req.u64);
1528
1529 /* switch to NULL completes immediately */
1530}
1531
1532/**
1533 * Switch to a NULL tag, which ends any ordering or
1534 * synchronization provided by the POW for the current
1535 * work queue entry. This operation completes immediately,
1536 * so completion should not be waited for.
1537 * This function waits for any pending tag switches to complete
1538 * before requesting the switch to NULL.
1539 */
1540static inline void cvmx_pow_tag_sw_null(void)
1541{
1542 if (CVMX_ENABLE_POW_CHECKS)
1543 __cvmx_pow_warn_if_pending_switch(__func__);
1544
1545 /*
1546 * Ensure that there is not a pending tag switch, as a tag
1547 * switch cannot be started if a previous switch is still
1548 * pending.
1549 */
1550 cvmx_pow_tag_sw_wait();
1551 cvmx_pow_tag_sw_null_nocheck();
1552
1553 /* switch to NULL completes immediately */
1554}
1555
1556/**
1557 * Submits work to an input queue. This function updates the work
1558 * queue entry in DRAM to match the arguments given. Note that the
1559 * tag provided is for the work queue entry submitted, and is
1560 * unrelated to the tag that the core currently holds.
1561 *
1562 * @wqp: pointer to work queue entry to submit. This entry is
1563 * updated to match the other parameters
1564 * @tag: tag value to be assigned to work queue entry
1565 * @tag_type: type of tag
1566 * @qos: Input queue to add to.
1567 * @grp: group value for the work queue entry.
1568 */
1569static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
1570 enum cvmx_pow_tag_type tag_type,
1571 uint64_t qos, uint64_t grp)
1572{
1573 cvmx_addr_t ptr;
1574 cvmx_pow_tag_req_t tag_req;
1575
1576 wqp->qos = qos;
1577 wqp->tag = tag;
1578 wqp->tag_type = tag_type;
1579 wqp->grp = grp;
1580
1581 tag_req.u64 = 0;
1582 tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;
1583 tag_req.s.type = tag_type;
1584 tag_req.s.tag = tag;
1585 tag_req.s.qos = qos;
1586 tag_req.s.grp = grp;
1587
1588 ptr.u64 = 0;
1589 ptr.sio.mem_region = CVMX_IO_SEG;
1590 ptr.sio.is_io = 1;
1591 ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
1592 ptr.sio.offset = cvmx_ptr_to_phys(wqp);
1593
1594 /*
1595 * SYNC write to memory before the work submit. This is
1596 * necessary as POW may read values from DRAM at this time.
1597 */
1598 CVMX_SYNCWS;
1599 cvmx_write_io(ptr.u64, tag_req.u64);
1600}
1601
1602/**
1603 * This function sets the group mask for a core. The group mask
1604 * indicates which groups each core will accept work from. There are
1605 * 16 groups.
1606 *
1607 * @core_num: core to apply mask to
1608 * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid,
1609 * representing groups 0-15.
1610 * Each 1 bit in the mask enables the core to accept work from
1611 * the corresponding group.
1612 */
1613static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
1614{
1615 union cvmx_pow_pp_grp_mskx grp_msk;
1616
1617 grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
1618 grp_msk.s.grp_msk = mask;
1619 cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
1620}
1621
1622/**
1623 * This function sets POW static priorities for a core. Each input queue has
1624 * an associated priority value.
1625 *
1626 * @core_num: core to apply priorities to
1627 * @priority: Vector of 8 priorities, one per POW Input Queue (0-7).
1628 * Highest priority is 0 and lowest is 7. A priority value
1629 * of 0xF instructs POW to skip the Input Queue when
1630 * scheduling to this specific core.
1631 * NOTE: priorities should not have gaps in values, meaning
1632 * {0,1,1,1,1,1,1,1} is a valid configuration while
1633 * {0,2,2,2,2,2,2,2} is not.
1634 */
1635static inline void cvmx_pow_set_priority(uint64_t core_num,
1636 const uint8_t priority[])
1637{
1638 /* POW priorities are supported on CN5xxx and later */
1639 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
1640 union cvmx_pow_pp_grp_mskx grp_msk;
1641
1642 grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
1643 grp_msk.s.qos0_pri = priority[0];
1644 grp_msk.s.qos1_pri = priority[1];
1645 grp_msk.s.qos2_pri = priority[2];
1646 grp_msk.s.qos3_pri = priority[3];
1647 grp_msk.s.qos4_pri = priority[4];
1648 grp_msk.s.qos5_pri = priority[5];
1649 grp_msk.s.qos6_pri = priority[6];
1650 grp_msk.s.qos7_pri = priority[7];
1651
1652 /* Detect gaps between priorities and flag error */
1653 {
1654 int i;
1655 uint32_t prio_mask = 0;
1656
1657 for (i = 0; i < 8; i++)
1658 if (priority[i] != 0xF)
1659 prio_mask |= 1 << priority[i];
1660
1661 if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) {
1662 pr_err("POW static priorities should be "
1663 "contiguous (0x%llx)\n",
1664 (unsigned long long)prio_mask);
1665 return;
1666 }
1667 }
1668
1669 cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
1670 }
1671}
1672
1673/**
1674 * Performs a tag switch and then an immediate deschedule. This completes
1675 * immediately, so completion must not be waited for. This function does NOT
1676 * update the wqe in DRAM to match arguments.
1677 *
1678 * This function does NOT wait for any prior tag switches to complete, so the
1679 * calling code must do this.
1680 *
1681 * Note the following CAVEAT of the Octeon HW behavior when
1682 * re-scheduling DE-SCHEDULEd items whose (next) state is
1683 * ORDERED:
1684 * - If there are no switches pending at the time that the
1685 * HW executes the de-schedule, the HW will only re-schedule
1686 * the head of the FIFO associated with the given tag. This
1687 * means that in many respects, the HW treats this ORDERED
1688 * tag as an ATOMIC tag. Note that in the SWTAG_DESCH
1689 * case (to an ORDERED tag), the HW will do the switch
1690 * before the deschedule whenever it is possible to do
1691 * the switch immediately, so it may often look like
1692 * this case.
1693 * - If there is a pending switch to ORDERED at the time
1694 * the HW executes the de-schedule, the HW will perform
1695 * the switch at the time it re-schedules, and will be
1696 * able to reschedule any/all of the entries with the
1697 * same tag.
1698 * Due to this behavior, the RECOMMENDATION to software is
1699 * that they have a (next) state of ATOMIC when they
1700 * DE-SCHEDULE. If an ORDERED tag is what was really desired,
1701 * SW can choose to immediately switch to an ORDERED tag
1702 * after the work (that has an ATOMIC tag) is re-scheduled.
1703 * Note that since there are never any tag switches pending
1704 * when the HW re-schedules, this switch can be IMMEDIATE upon
1705 * the reception of the pointer during the re-schedule.
1706 *
1707 * @tag: New tag value
1708 * @tag_type: New tag type
1709 * @group: New group value
1710 * @no_sched: Control whether this work queue entry will be rescheduled.
1711 * - 1 : don't schedule this work
1712 * - 0 : allow this work to be scheduled.
1713 */
1714static inline void cvmx_pow_tag_sw_desched_nocheck(
1715 uint32_t tag,
1716 enum cvmx_pow_tag_type tag_type,
1717 uint64_t group,
1718 uint64_t no_sched)
1719{
1720 cvmx_addr_t ptr;
1721 cvmx_pow_tag_req_t tag_req;
1722
1723 if (CVMX_ENABLE_POW_CHECKS) {
1724 cvmx_pow_tag_req_t current_tag;
1725 __cvmx_pow_warn_if_pending_switch(__func__);
1726 current_tag = cvmx_pow_get_current_tag();
1727 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1728 pr_warning("%s called with NULL_NULL tag\n",
1729 __func__);
1730 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1731 pr_warning("%s called with NULL tag. Deschedule not "
1732 "allowed from NULL state\n",
1733 __func__);
1734 if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC)
1735 && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC))
1736 pr_warning("%s called where neither the before or "
1737 "after tag is ATOMIC\n",
1738 __func__);
1739 }
1740
1741 tag_req.u64 = 0;
1742 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
1743 tag_req.s.tag = tag;
1744 tag_req.s.type = tag_type;
1745 tag_req.s.grp = group;
1746 tag_req.s.no_sched = no_sched;
1747
1748 ptr.u64 = 0;
1749 ptr.sio.mem_region = CVMX_IO_SEG;
1750 ptr.sio.is_io = 1;
1751 ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
1752 /*
1753 * since TAG3 is used, this store will clear the local pending
1754 * switch bit.
1755 */
1756 cvmx_write_io(ptr.u64, tag_req.u64);
1757}
1758
1759/**
1760 * Performs a tag switch and then an immediate deschedule. This completes
1761 * immediately, so completion must not be waited for. This function does NOT
1762 * update the wqe in DRAM to match arguments.
1763 *
1764 * This function waits for any prior tag switches to complete, so the
1765 * calling code may call this function with a pending tag switch.
1766 *
1767 * Note the following CAVEAT of the Octeon HW behavior when
1768 * re-scheduling DE-SCHEDULEd items whose (next) state is
1769 * ORDERED:
1770 * - If there are no switches pending at the time that the
1771 * HW executes the de-schedule, the HW will only re-schedule
1772 * the head of the FIFO associated with the given tag. This
1773 * means that in many respects, the HW treats this ORDERED
1774 * tag as an ATOMIC tag. Note that in the SWTAG_DESCH
1775 * case (to an ORDERED tag), the HW will do the switch
1776 * before the deschedule whenever it is possible to do
1777 * the switch immediately, so it may often look like
1778 * this case.
1779 * - If there is a pending switch to ORDERED at the time
1780 * the HW executes the de-schedule, the HW will perform
1781 * the switch at the time it re-schedules, and will be
1782 * able to reschedule any/all of the entries with the
1783 * same tag.
1784 * Due to this behavior, the RECOMMENDATION to software is
1785 * that they have a (next) state of ATOMIC when they
1786 * DE-SCHEDULE. If an ORDERED tag is what was really desired,
1787 * SW can choose to immediately switch to an ORDERED tag
1788 * after the work (that has an ATOMIC tag) is re-scheduled.
1789 * Note that since there are never any tag switches pending
1790 * when the HW re-schedules, this switch can be IMMEDIATE upon
1791 * the reception of the pointer during the re-schedule.
1792 *
1793 * @tag: New tag value
1794 * @tag_type: New tag type
1795 * @group: New group value
1796 * @no_sched: Control whether this work queue entry will be rescheduled.
1797 * - 1 : don't schedule this work
1798 * - 0 : allow this work to be scheduled.
1799 */
1800static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
1801 enum cvmx_pow_tag_type tag_type,
1802 uint64_t group, uint64_t no_sched)
1803{
1804 if (CVMX_ENABLE_POW_CHECKS)
1805 __cvmx_pow_warn_if_pending_switch(__func__);
1806
1807 /* Need to make sure any writes to the work queue entry are complete */
1808 CVMX_SYNCWS;
1809 /*
1810 * Ensure that there is not a pending tag switch, as a tag
1811 * switch cannot be started if a previous switch is still
1812 * pending.
1813 */
1814 cvmx_pow_tag_sw_wait();
1815 cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched);
1816}
1817
1818/**
1819 * Descchedules the current work queue entry.
1820 *
1821 * @no_sched: no schedule flag value to be set on the work queue
1822 * entry. If this is set the entry will not be
1823 * rescheduled.
1824 */
1825static inline void cvmx_pow_desched(uint64_t no_sched)
1826{
1827 cvmx_addr_t ptr;
1828 cvmx_pow_tag_req_t tag_req;
1829
1830 if (CVMX_ENABLE_POW_CHECKS) {
1831 cvmx_pow_tag_req_t current_tag;
1832 __cvmx_pow_warn_if_pending_switch(__func__);
1833 current_tag = cvmx_pow_get_current_tag();
1834 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1835 pr_warning("%s called with NULL_NULL tag\n",
1836 __func__);
1837 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1838 pr_warning("%s called with NULL tag. Deschedule not "
1839 "expected from NULL state\n",
1840 __func__);
1841 }
1842
1843 /* Need to make sure any writes to the work queue entry are complete */
1844 CVMX_SYNCWS;
1845
1846 tag_req.u64 = 0;
1847 tag_req.s.op = CVMX_POW_TAG_OP_DESCH;
1848 tag_req.s.no_sched = no_sched;
1849
1850 ptr.u64 = 0;
1851 ptr.sio.mem_region = CVMX_IO_SEG;
1852 ptr.sio.is_io = 1;
1853 ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
1854 /*
1855 * since TAG3 is used, this store will clear the local pending
1856 * switch bit.
1857 */
1858 cvmx_write_io(ptr.u64, tag_req.u64);
1859}
1860
1861/****************************************************
1862* Define usage of bits within the 32 bit tag values.
1863*****************************************************/
1864
1865/*
1866 * Number of bits of the tag used by software. The SW bits are always
1867 * a contiguous block of the high starting at bit 31. The hardware
1868 * bits are always the low bits. By default, the top 8 bits of the
1869 * tag are reserved for software, and the low 24 are set by the IPD
1870 * unit.
1871 */
1872#define CVMX_TAG_SW_BITS (8)
1873#define CVMX_TAG_SW_SHIFT (32 - CVMX_TAG_SW_BITS)
1874
1875/* Below is the list of values for the top 8 bits of the tag. */
1876/*
1877 * Tag values with top byte of this value are reserved for internal
1878 * executive uses.
1879 */
1880#define CVMX_TAG_SW_BITS_INTERNAL 0x1
1881/* The executive divides the remaining 24 bits as follows:
1882 * - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup
1883 *
1884 * - the lower 16 bits (bits 15 - 0 of the tag) define are the value
1885 * with the subgroup
1886 *
1887 * Note that this section describes the format of tags generated by
1888 * software - refer to the hardware documentation for a description of
1889 * the tags values generated by the packet input hardware. Subgroups
1890 * are defined here.
1891 */
1892/* Mask for the value portion of the tag */
1893#define CVMX_TAG_SUBGROUP_MASK 0xFFFF
1894#define CVMX_TAG_SUBGROUP_SHIFT 16
1895#define CVMX_TAG_SUBGROUP_PKO 0x1
1896
1897/* End of executive tag subgroup definitions */
1898
1899/*
1900 * The remaining values software bit values 0x2 - 0xff are available
1901 * for application use.
1902 */
1903
1904/**
1905 * This function creates a 32 bit tag value from the two values provided.
1906 *
1907 * @sw_bits: The upper bits (number depends on configuration) are set
1908 * to this value. The remainder of bits are set by the
1909 * hw_bits parameter.
1910 *
1911 * @hw_bits: The lower bits (number depends on configuration) are set
1912 * to this value. The remainder of bits are set by the
1913 * sw_bits parameter.
1914 *
1915 * Returns 32 bit value of the combined hw and sw bits.
1916 */
1917static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits)
1918{
1919 return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) <<
1920 CVMX_TAG_SW_SHIFT) |
1921 (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS));
1922}
1923
1924/**
1925 * Extracts the bits allocated for software use from the tag
1926 *
1927 * @tag: 32 bit tag value
1928 *
1929 * Returns N bit software tag value, where N is configurable with the
1930 * CVMX_TAG_SW_BITS define
1931 */
1932static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag)
1933{
1934 return (tag >> (32 - CVMX_TAG_SW_BITS)) &
1935 cvmx_build_mask(CVMX_TAG_SW_BITS);
1936}
1937
1938/**
1939 *
1940 * Extracts the bits allocated for hardware use from the tag
1941 *
1942 * @tag: 32 bit tag value
1943 *
1944 * Returns (32 - N) bit software tag value, where N is configurable
1945 * with the CVMX_TAG_SW_BITS define
1946 */
1947static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag)
1948{
1949 return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS);
1950}
1951
1952/**
1953 * Store the current POW internal state into the supplied
1954 * buffer. It is recommended that you pass a buffer of at least
1955 * 128KB. The format of the capture may change based on SDK
1956 * version and Octeon chip.
1957 *
1958 * @buffer: Buffer to store capture into
1959 * @buffer_size:
1960 * The size of the supplied buffer
1961 *
1962 * Returns Zero on success, negative on failure
1963 */
1964extern int cvmx_pow_capture(void *buffer, int buffer_size);
1965
1966/**
1967 * Dump a POW capture to the console in a human readable format.
1968 *
1969 * @buffer: POW capture from cvmx_pow_capture()
1970 * @buffer_size:
1971 * Size of the buffer
1972 */
1973extern void cvmx_pow_display(void *buffer, int buffer_size);
1974
1975/**
1976 * Return the number of POW entries supported by this chip
1977 *
1978 * Returns Number of POW entries
1979 */
1980extern int cvmx_pow_get_num_entries(void);
1981
1982#endif /* __CVMX_POW_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h
new file mode 100644
index 00000000000..96b70cfd624
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-scratch.h
@@ -0,0 +1,139 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * This file provides support for the processor local scratch memory.
31 * Scratch memory is byte addressable - all addresses are byte addresses.
32 *
33 */
34
35#ifndef __CVMX_SCRATCH_H__
36#define __CVMX_SCRATCH_H__
37
38/*
39 * Note: This define must be a long, not a long long in order to
40 * compile without warnings for both 32bit and 64bit.
41 */
42#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */
43
44/**
45 * Reads an 8 bit value from the processor local scratchpad memory.
46 *
47 * @address: byte address to read from
48 *
49 * Returns value read
50 */
51static inline uint8_t cvmx_scratch_read8(uint64_t address)
52{
53 return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address);
54}
55
56/**
57 * Reads a 16 bit value from the processor local scratchpad memory.
58 *
59 * @address: byte address to read from
60 *
61 * Returns value read
62 */
63static inline uint16_t cvmx_scratch_read16(uint64_t address)
64{
65 return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address);
66}
67
68/**
69 * Reads a 32 bit value from the processor local scratchpad memory.
70 *
71 * @address: byte address to read from
72 *
73 * Returns value read
74 */
75static inline uint32_t cvmx_scratch_read32(uint64_t address)
76{
77 return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address);
78}
79
80/**
81 * Reads a 64 bit value from the processor local scratchpad memory.
82 *
83 * @address: byte address to read from
84 *
85 * Returns value read
86 */
87static inline uint64_t cvmx_scratch_read64(uint64_t address)
88{
89 return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address);
90}
91
92/**
93 * Writes an 8 bit value to the processor local scratchpad memory.
94 *
95 * @address: byte address to write to
96 * @value: value to write
97 */
98static inline void cvmx_scratch_write8(uint64_t address, uint64_t value)
99{
100 *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) =
101 (uint8_t) value;
102}
103
104/**
105 * Writes a 32 bit value to the processor local scratchpad memory.
106 *
107 * @address: byte address to write to
108 * @value: value to write
109 */
110static inline void cvmx_scratch_write16(uint64_t address, uint64_t value)
111{
112 *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) =
113 (uint16_t) value;
114}
115
116/**
117 * Writes a 16 bit value to the processor local scratchpad memory.
118 *
119 * @address: byte address to write to
120 * @value: value to write
121 */
122static inline void cvmx_scratch_write32(uint64_t address, uint64_t value)
123{
124 *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) =
125 (uint32_t) value;
126}
127
128/**
129 * Writes a 64 bit value to the processor local scratchpad memory.
130 *
131 * @address: byte address to write to
132 * @value: value to write
133 */
134static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
135{
136 *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value;
137}
138
139#endif /* __CVMX_SCRATCH_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
new file mode 100644
index 00000000000..7c6c901d3d2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -0,0 +1,2172 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__
30
31#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
32#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
33#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
34#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
35#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
36#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
37#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
38#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
39#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
40#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
41#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
42#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
43#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
44#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
45#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
46#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
47#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
48#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
49#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
50#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
51#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
52#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
53#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
54#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
55#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
56#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
57#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
58#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
59#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
60#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
61#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
62#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
63#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
64#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
65#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
66#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
67#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
68#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
69#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
70#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
71#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
72#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
73#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
74#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
75#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
76#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
77#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
78#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
79#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
80#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
81#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
82#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
83#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
84#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
85#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
86#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
87#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
88#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
89#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
90#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
91#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
92#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
93#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
94#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
95#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
96#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
97#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
98#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
99#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
100#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
101#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
102#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
103#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
104#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
105#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
106#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
107#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
108#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
109#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
110#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
111#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
112#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
113#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
114#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
115#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
116#define CVMX_SLI_STATE1 (0x0000000000000620ull)
117#define CVMX_SLI_STATE2 (0x0000000000000630ull)
118#define CVMX_SLI_STATE3 (0x0000000000000640ull)
119#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
120#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
121#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
122#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
123#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
124#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
125#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
126
127union cvmx_sli_bist_status {
128 uint64_t u64;
129 struct cvmx_sli_bist_status_s {
130 uint64_t reserved_32_63:32;
131 uint64_t ncb_req:1;
132 uint64_t n2p0_c:1;
133 uint64_t n2p0_o:1;
134 uint64_t n2p1_c:1;
135 uint64_t n2p1_o:1;
136 uint64_t cpl_p0:1;
137 uint64_t cpl_p1:1;
138 uint64_t reserved_19_24:6;
139 uint64_t p2n0_c0:1;
140 uint64_t p2n0_c1:1;
141 uint64_t p2n0_n:1;
142 uint64_t p2n0_p0:1;
143 uint64_t p2n0_p1:1;
144 uint64_t p2n1_c0:1;
145 uint64_t p2n1_c1:1;
146 uint64_t p2n1_n:1;
147 uint64_t p2n1_p0:1;
148 uint64_t p2n1_p1:1;
149 uint64_t reserved_6_8:3;
150 uint64_t dsi1_1:1;
151 uint64_t dsi1_0:1;
152 uint64_t dsi0_1:1;
153 uint64_t dsi0_0:1;
154 uint64_t msi:1;
155 uint64_t ncb_cmd:1;
156 } s;
157 struct cvmx_sli_bist_status_cn61xx {
158 uint64_t reserved_31_63:33;
159 uint64_t n2p0_c:1;
160 uint64_t n2p0_o:1;
161 uint64_t reserved_27_28:2;
162 uint64_t cpl_p0:1;
163 uint64_t cpl_p1:1;
164 uint64_t reserved_19_24:6;
165 uint64_t p2n0_c0:1;
166 uint64_t p2n0_c1:1;
167 uint64_t p2n0_n:1;
168 uint64_t p2n0_p0:1;
169 uint64_t p2n0_p1:1;
170 uint64_t p2n1_c0:1;
171 uint64_t p2n1_c1:1;
172 uint64_t p2n1_n:1;
173 uint64_t p2n1_p0:1;
174 uint64_t p2n1_p1:1;
175 uint64_t reserved_6_8:3;
176 uint64_t dsi1_1:1;
177 uint64_t dsi1_0:1;
178 uint64_t dsi0_1:1;
179 uint64_t dsi0_0:1;
180 uint64_t msi:1;
181 uint64_t ncb_cmd:1;
182 } cn61xx;
183 struct cvmx_sli_bist_status_cn63xx {
184 uint64_t reserved_31_63:33;
185 uint64_t n2p0_c:1;
186 uint64_t n2p0_o:1;
187 uint64_t n2p1_c:1;
188 uint64_t n2p1_o:1;
189 uint64_t cpl_p0:1;
190 uint64_t cpl_p1:1;
191 uint64_t reserved_19_24:6;
192 uint64_t p2n0_c0:1;
193 uint64_t p2n0_c1:1;
194 uint64_t p2n0_n:1;
195 uint64_t p2n0_p0:1;
196 uint64_t p2n0_p1:1;
197 uint64_t p2n1_c0:1;
198 uint64_t p2n1_c1:1;
199 uint64_t p2n1_n:1;
200 uint64_t p2n1_p0:1;
201 uint64_t p2n1_p1:1;
202 uint64_t reserved_6_8:3;
203 uint64_t dsi1_1:1;
204 uint64_t dsi1_0:1;
205 uint64_t dsi0_1:1;
206 uint64_t dsi0_0:1;
207 uint64_t msi:1;
208 uint64_t ncb_cmd:1;
209 } cn63xx;
210 struct cvmx_sli_bist_status_cn63xx cn63xxp1;
211 struct cvmx_sli_bist_status_cn61xx cn66xx;
212 struct cvmx_sli_bist_status_s cn68xx;
213 struct cvmx_sli_bist_status_s cn68xxp1;
214};
215
216union cvmx_sli_ctl_portx {
217 uint64_t u64;
218 struct cvmx_sli_ctl_portx_s {
219 uint64_t reserved_22_63:42;
220 uint64_t intd:1;
221 uint64_t intc:1;
222 uint64_t intb:1;
223 uint64_t inta:1;
224 uint64_t dis_port:1;
225 uint64_t waitl_com:1;
226 uint64_t intd_map:2;
227 uint64_t intc_map:2;
228 uint64_t intb_map:2;
229 uint64_t inta_map:2;
230 uint64_t ctlp_ro:1;
231 uint64_t reserved_6_6:1;
232 uint64_t ptlp_ro:1;
233 uint64_t reserved_1_4:4;
234 uint64_t wait_com:1;
235 } s;
236 struct cvmx_sli_ctl_portx_s cn61xx;
237 struct cvmx_sli_ctl_portx_s cn63xx;
238 struct cvmx_sli_ctl_portx_s cn63xxp1;
239 struct cvmx_sli_ctl_portx_s cn66xx;
240 struct cvmx_sli_ctl_portx_s cn68xx;
241 struct cvmx_sli_ctl_portx_s cn68xxp1;
242};
243
244union cvmx_sli_ctl_status {
245 uint64_t u64;
246 struct cvmx_sli_ctl_status_s {
247 uint64_t reserved_20_63:44;
248 uint64_t p1_ntags:6;
249 uint64_t p0_ntags:6;
250 uint64_t chip_rev:8;
251 } s;
252 struct cvmx_sli_ctl_status_cn61xx {
253 uint64_t reserved_14_63:50;
254 uint64_t p0_ntags:6;
255 uint64_t chip_rev:8;
256 } cn61xx;
257 struct cvmx_sli_ctl_status_s cn63xx;
258 struct cvmx_sli_ctl_status_s cn63xxp1;
259 struct cvmx_sli_ctl_status_cn61xx cn66xx;
260 struct cvmx_sli_ctl_status_s cn68xx;
261 struct cvmx_sli_ctl_status_s cn68xxp1;
262};
263
264union cvmx_sli_data_out_cnt {
265 uint64_t u64;
266 struct cvmx_sli_data_out_cnt_s {
267 uint64_t reserved_44_63:20;
268 uint64_t p1_ucnt:16;
269 uint64_t p1_fcnt:6;
270 uint64_t p0_ucnt:16;
271 uint64_t p0_fcnt:6;
272 } s;
273 struct cvmx_sli_data_out_cnt_s cn61xx;
274 struct cvmx_sli_data_out_cnt_s cn63xx;
275 struct cvmx_sli_data_out_cnt_s cn63xxp1;
276 struct cvmx_sli_data_out_cnt_s cn66xx;
277 struct cvmx_sli_data_out_cnt_s cn68xx;
278 struct cvmx_sli_data_out_cnt_s cn68xxp1;
279};
280
281union cvmx_sli_dbg_data {
282 uint64_t u64;
283 struct cvmx_sli_dbg_data_s {
284 uint64_t reserved_18_63:46;
285 uint64_t dsel_ext:1;
286 uint64_t data:17;
287 } s;
288 struct cvmx_sli_dbg_data_s cn61xx;
289 struct cvmx_sli_dbg_data_s cn63xx;
290 struct cvmx_sli_dbg_data_s cn63xxp1;
291 struct cvmx_sli_dbg_data_s cn66xx;
292 struct cvmx_sli_dbg_data_s cn68xx;
293 struct cvmx_sli_dbg_data_s cn68xxp1;
294};
295
296union cvmx_sli_dbg_select {
297 uint64_t u64;
298 struct cvmx_sli_dbg_select_s {
299 uint64_t reserved_33_63:31;
300 uint64_t adbg_sel:1;
301 uint64_t dbg_sel:32;
302 } s;
303 struct cvmx_sli_dbg_select_s cn61xx;
304 struct cvmx_sli_dbg_select_s cn63xx;
305 struct cvmx_sli_dbg_select_s cn63xxp1;
306 struct cvmx_sli_dbg_select_s cn66xx;
307 struct cvmx_sli_dbg_select_s cn68xx;
308 struct cvmx_sli_dbg_select_s cn68xxp1;
309};
310
311union cvmx_sli_dmax_cnt {
312 uint64_t u64;
313 struct cvmx_sli_dmax_cnt_s {
314 uint64_t reserved_32_63:32;
315 uint64_t cnt:32;
316 } s;
317 struct cvmx_sli_dmax_cnt_s cn61xx;
318 struct cvmx_sli_dmax_cnt_s cn63xx;
319 struct cvmx_sli_dmax_cnt_s cn63xxp1;
320 struct cvmx_sli_dmax_cnt_s cn66xx;
321 struct cvmx_sli_dmax_cnt_s cn68xx;
322 struct cvmx_sli_dmax_cnt_s cn68xxp1;
323};
324
325union cvmx_sli_dmax_int_level {
326 uint64_t u64;
327 struct cvmx_sli_dmax_int_level_s {
328 uint64_t time:32;
329 uint64_t cnt:32;
330 } s;
331 struct cvmx_sli_dmax_int_level_s cn61xx;
332 struct cvmx_sli_dmax_int_level_s cn63xx;
333 struct cvmx_sli_dmax_int_level_s cn63xxp1;
334 struct cvmx_sli_dmax_int_level_s cn66xx;
335 struct cvmx_sli_dmax_int_level_s cn68xx;
336 struct cvmx_sli_dmax_int_level_s cn68xxp1;
337};
338
339union cvmx_sli_dmax_tim {
340 uint64_t u64;
341 struct cvmx_sli_dmax_tim_s {
342 uint64_t reserved_32_63:32;
343 uint64_t tim:32;
344 } s;
345 struct cvmx_sli_dmax_tim_s cn61xx;
346 struct cvmx_sli_dmax_tim_s cn63xx;
347 struct cvmx_sli_dmax_tim_s cn63xxp1;
348 struct cvmx_sli_dmax_tim_s cn66xx;
349 struct cvmx_sli_dmax_tim_s cn68xx;
350 struct cvmx_sli_dmax_tim_s cn68xxp1;
351};
352
353union cvmx_sli_int_enb_ciu {
354 uint64_t u64;
355 struct cvmx_sli_int_enb_ciu_s {
356 uint64_t reserved_62_63:2;
357 uint64_t pipe_err:1;
358 uint64_t ill_pad:1;
359 uint64_t sprt3_err:1;
360 uint64_t sprt2_err:1;
361 uint64_t sprt1_err:1;
362 uint64_t sprt0_err:1;
363 uint64_t pins_err:1;
364 uint64_t pop_err:1;
365 uint64_t pdi_err:1;
366 uint64_t pgl_err:1;
367 uint64_t pin_bp:1;
368 uint64_t pout_err:1;
369 uint64_t psldbof:1;
370 uint64_t pidbof:1;
371 uint64_t reserved_38_47:10;
372 uint64_t dtime:2;
373 uint64_t dcnt:2;
374 uint64_t dmafi:2;
375 uint64_t reserved_28_31:4;
376 uint64_t m3_un_wi:1;
377 uint64_t m3_un_b0:1;
378 uint64_t m3_up_wi:1;
379 uint64_t m3_up_b0:1;
380 uint64_t m2_un_wi:1;
381 uint64_t m2_un_b0:1;
382 uint64_t m2_up_wi:1;
383 uint64_t m2_up_b0:1;
384 uint64_t reserved_18_19:2;
385 uint64_t mio_int1:1;
386 uint64_t mio_int0:1;
387 uint64_t m1_un_wi:1;
388 uint64_t m1_un_b0:1;
389 uint64_t m1_up_wi:1;
390 uint64_t m1_up_b0:1;
391 uint64_t m0_un_wi:1;
392 uint64_t m0_un_b0:1;
393 uint64_t m0_up_wi:1;
394 uint64_t m0_up_b0:1;
395 uint64_t reserved_6_7:2;
396 uint64_t ptime:1;
397 uint64_t pcnt:1;
398 uint64_t iob2big:1;
399 uint64_t bar0_to:1;
400 uint64_t reserved_1_1:1;
401 uint64_t rml_to:1;
402 } s;
403 struct cvmx_sli_int_enb_ciu_cn61xx {
404 uint64_t reserved_61_63:3;
405 uint64_t ill_pad:1;
406 uint64_t sprt3_err:1;
407 uint64_t sprt2_err:1;
408 uint64_t sprt1_err:1;
409 uint64_t sprt0_err:1;
410 uint64_t pins_err:1;
411 uint64_t pop_err:1;
412 uint64_t pdi_err:1;
413 uint64_t pgl_err:1;
414 uint64_t pin_bp:1;
415 uint64_t pout_err:1;
416 uint64_t psldbof:1;
417 uint64_t pidbof:1;
418 uint64_t reserved_38_47:10;
419 uint64_t dtime:2;
420 uint64_t dcnt:2;
421 uint64_t dmafi:2;
422 uint64_t reserved_28_31:4;
423 uint64_t m3_un_wi:1;
424 uint64_t m3_un_b0:1;
425 uint64_t m3_up_wi:1;
426 uint64_t m3_up_b0:1;
427 uint64_t m2_un_wi:1;
428 uint64_t m2_un_b0:1;
429 uint64_t m2_up_wi:1;
430 uint64_t m2_up_b0:1;
431 uint64_t reserved_18_19:2;
432 uint64_t mio_int1:1;
433 uint64_t mio_int0:1;
434 uint64_t m1_un_wi:1;
435 uint64_t m1_un_b0:1;
436 uint64_t m1_up_wi:1;
437 uint64_t m1_up_b0:1;
438 uint64_t m0_un_wi:1;
439 uint64_t m0_un_b0:1;
440 uint64_t m0_up_wi:1;
441 uint64_t m0_up_b0:1;
442 uint64_t reserved_6_7:2;
443 uint64_t ptime:1;
444 uint64_t pcnt:1;
445 uint64_t iob2big:1;
446 uint64_t bar0_to:1;
447 uint64_t reserved_1_1:1;
448 uint64_t rml_to:1;
449 } cn61xx;
450 struct cvmx_sli_int_enb_ciu_cn63xx {
451 uint64_t reserved_61_63:3;
452 uint64_t ill_pad:1;
453 uint64_t reserved_58_59:2;
454 uint64_t sprt1_err:1;
455 uint64_t sprt0_err:1;
456 uint64_t pins_err:1;
457 uint64_t pop_err:1;
458 uint64_t pdi_err:1;
459 uint64_t pgl_err:1;
460 uint64_t pin_bp:1;
461 uint64_t pout_err:1;
462 uint64_t psldbof:1;
463 uint64_t pidbof:1;
464 uint64_t reserved_38_47:10;
465 uint64_t dtime:2;
466 uint64_t dcnt:2;
467 uint64_t dmafi:2;
468 uint64_t reserved_18_31:14;
469 uint64_t mio_int1:1;
470 uint64_t mio_int0:1;
471 uint64_t m1_un_wi:1;
472 uint64_t m1_un_b0:1;
473 uint64_t m1_up_wi:1;
474 uint64_t m1_up_b0:1;
475 uint64_t m0_un_wi:1;
476 uint64_t m0_un_b0:1;
477 uint64_t m0_up_wi:1;
478 uint64_t m0_up_b0:1;
479 uint64_t reserved_6_7:2;
480 uint64_t ptime:1;
481 uint64_t pcnt:1;
482 uint64_t iob2big:1;
483 uint64_t bar0_to:1;
484 uint64_t reserved_1_1:1;
485 uint64_t rml_to:1;
486 } cn63xx;
487 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
488 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
489 struct cvmx_sli_int_enb_ciu_cn68xx {
490 uint64_t reserved_62_63:2;
491 uint64_t pipe_err:1;
492 uint64_t ill_pad:1;
493 uint64_t reserved_58_59:2;
494 uint64_t sprt1_err:1;
495 uint64_t sprt0_err:1;
496 uint64_t pins_err:1;
497 uint64_t pop_err:1;
498 uint64_t pdi_err:1;
499 uint64_t pgl_err:1;
500 uint64_t reserved_51_51:1;
501 uint64_t pout_err:1;
502 uint64_t psldbof:1;
503 uint64_t pidbof:1;
504 uint64_t reserved_38_47:10;
505 uint64_t dtime:2;
506 uint64_t dcnt:2;
507 uint64_t dmafi:2;
508 uint64_t reserved_18_31:14;
509 uint64_t mio_int1:1;
510 uint64_t mio_int0:1;
511 uint64_t m1_un_wi:1;
512 uint64_t m1_un_b0:1;
513 uint64_t m1_up_wi:1;
514 uint64_t m1_up_b0:1;
515 uint64_t m0_un_wi:1;
516 uint64_t m0_un_b0:1;
517 uint64_t m0_up_wi:1;
518 uint64_t m0_up_b0:1;
519 uint64_t reserved_6_7:2;
520 uint64_t ptime:1;
521 uint64_t pcnt:1;
522 uint64_t iob2big:1;
523 uint64_t bar0_to:1;
524 uint64_t reserved_1_1:1;
525 uint64_t rml_to:1;
526 } cn68xx;
527 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
528};
529
530union cvmx_sli_int_enb_portx {
531 uint64_t u64;
532 struct cvmx_sli_int_enb_portx_s {
533 uint64_t reserved_62_63:2;
534 uint64_t pipe_err:1;
535 uint64_t ill_pad:1;
536 uint64_t sprt3_err:1;
537 uint64_t sprt2_err:1;
538 uint64_t sprt1_err:1;
539 uint64_t sprt0_err:1;
540 uint64_t pins_err:1;
541 uint64_t pop_err:1;
542 uint64_t pdi_err:1;
543 uint64_t pgl_err:1;
544 uint64_t pin_bp:1;
545 uint64_t pout_err:1;
546 uint64_t psldbof:1;
547 uint64_t pidbof:1;
548 uint64_t reserved_38_47:10;
549 uint64_t dtime:2;
550 uint64_t dcnt:2;
551 uint64_t dmafi:2;
552 uint64_t reserved_28_31:4;
553 uint64_t m3_un_wi:1;
554 uint64_t m3_un_b0:1;
555 uint64_t m3_up_wi:1;
556 uint64_t m3_up_b0:1;
557 uint64_t m2_un_wi:1;
558 uint64_t m2_un_b0:1;
559 uint64_t m2_up_wi:1;
560 uint64_t m2_up_b0:1;
561 uint64_t mac1_int:1;
562 uint64_t mac0_int:1;
563 uint64_t mio_int1:1;
564 uint64_t mio_int0:1;
565 uint64_t m1_un_wi:1;
566 uint64_t m1_un_b0:1;
567 uint64_t m1_up_wi:1;
568 uint64_t m1_up_b0:1;
569 uint64_t m0_un_wi:1;
570 uint64_t m0_un_b0:1;
571 uint64_t m0_up_wi:1;
572 uint64_t m0_up_b0:1;
573 uint64_t reserved_6_7:2;
574 uint64_t ptime:1;
575 uint64_t pcnt:1;
576 uint64_t iob2big:1;
577 uint64_t bar0_to:1;
578 uint64_t reserved_1_1:1;
579 uint64_t rml_to:1;
580 } s;
581 struct cvmx_sli_int_enb_portx_cn61xx {
582 uint64_t reserved_61_63:3;
583 uint64_t ill_pad:1;
584 uint64_t sprt3_err:1;
585 uint64_t sprt2_err:1;
586 uint64_t sprt1_err:1;
587 uint64_t sprt0_err:1;
588 uint64_t pins_err:1;
589 uint64_t pop_err:1;
590 uint64_t pdi_err:1;
591 uint64_t pgl_err:1;
592 uint64_t pin_bp:1;
593 uint64_t pout_err:1;
594 uint64_t psldbof:1;
595 uint64_t pidbof:1;
596 uint64_t reserved_38_47:10;
597 uint64_t dtime:2;
598 uint64_t dcnt:2;
599 uint64_t dmafi:2;
600 uint64_t reserved_28_31:4;
601 uint64_t m3_un_wi:1;
602 uint64_t m3_un_b0:1;
603 uint64_t m3_up_wi:1;
604 uint64_t m3_up_b0:1;
605 uint64_t m2_un_wi:1;
606 uint64_t m2_un_b0:1;
607 uint64_t m2_up_wi:1;
608 uint64_t m2_up_b0:1;
609 uint64_t mac1_int:1;
610 uint64_t mac0_int:1;
611 uint64_t mio_int1:1;
612 uint64_t mio_int0:1;
613 uint64_t m1_un_wi:1;
614 uint64_t m1_un_b0:1;
615 uint64_t m1_up_wi:1;
616 uint64_t m1_up_b0:1;
617 uint64_t m0_un_wi:1;
618 uint64_t m0_un_b0:1;
619 uint64_t m0_up_wi:1;
620 uint64_t m0_up_b0:1;
621 uint64_t reserved_6_7:2;
622 uint64_t ptime:1;
623 uint64_t pcnt:1;
624 uint64_t iob2big:1;
625 uint64_t bar0_to:1;
626 uint64_t reserved_1_1:1;
627 uint64_t rml_to:1;
628 } cn61xx;
629 struct cvmx_sli_int_enb_portx_cn63xx {
630 uint64_t reserved_61_63:3;
631 uint64_t ill_pad:1;
632 uint64_t reserved_58_59:2;
633 uint64_t sprt1_err:1;
634 uint64_t sprt0_err:1;
635 uint64_t pins_err:1;
636 uint64_t pop_err:1;
637 uint64_t pdi_err:1;
638 uint64_t pgl_err:1;
639 uint64_t pin_bp:1;
640 uint64_t pout_err:1;
641 uint64_t psldbof:1;
642 uint64_t pidbof:1;
643 uint64_t reserved_38_47:10;
644 uint64_t dtime:2;
645 uint64_t dcnt:2;
646 uint64_t dmafi:2;
647 uint64_t reserved_20_31:12;
648 uint64_t mac1_int:1;
649 uint64_t mac0_int:1;
650 uint64_t mio_int1:1;
651 uint64_t mio_int0:1;
652 uint64_t m1_un_wi:1;
653 uint64_t m1_un_b0:1;
654 uint64_t m1_up_wi:1;
655 uint64_t m1_up_b0:1;
656 uint64_t m0_un_wi:1;
657 uint64_t m0_un_b0:1;
658 uint64_t m0_up_wi:1;
659 uint64_t m0_up_b0:1;
660 uint64_t reserved_6_7:2;
661 uint64_t ptime:1;
662 uint64_t pcnt:1;
663 uint64_t iob2big:1;
664 uint64_t bar0_to:1;
665 uint64_t reserved_1_1:1;
666 uint64_t rml_to:1;
667 } cn63xx;
668 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
669 struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
670 struct cvmx_sli_int_enb_portx_cn68xx {
671 uint64_t reserved_62_63:2;
672 uint64_t pipe_err:1;
673 uint64_t ill_pad:1;
674 uint64_t reserved_58_59:2;
675 uint64_t sprt1_err:1;
676 uint64_t sprt0_err:1;
677 uint64_t pins_err:1;
678 uint64_t pop_err:1;
679 uint64_t pdi_err:1;
680 uint64_t pgl_err:1;
681 uint64_t reserved_51_51:1;
682 uint64_t pout_err:1;
683 uint64_t psldbof:1;
684 uint64_t pidbof:1;
685 uint64_t reserved_38_47:10;
686 uint64_t dtime:2;
687 uint64_t dcnt:2;
688 uint64_t dmafi:2;
689 uint64_t reserved_20_31:12;
690 uint64_t mac1_int:1;
691 uint64_t mac0_int:1;
692 uint64_t mio_int1:1;
693 uint64_t mio_int0:1;
694 uint64_t m1_un_wi:1;
695 uint64_t m1_un_b0:1;
696 uint64_t m1_up_wi:1;
697 uint64_t m1_up_b0:1;
698 uint64_t m0_un_wi:1;
699 uint64_t m0_un_b0:1;
700 uint64_t m0_up_wi:1;
701 uint64_t m0_up_b0:1;
702 uint64_t reserved_6_7:2;
703 uint64_t ptime:1;
704 uint64_t pcnt:1;
705 uint64_t iob2big:1;
706 uint64_t bar0_to:1;
707 uint64_t reserved_1_1:1;
708 uint64_t rml_to:1;
709 } cn68xx;
710 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
711};
712
713union cvmx_sli_int_sum {
714 uint64_t u64;
715 struct cvmx_sli_int_sum_s {
716 uint64_t reserved_62_63:2;
717 uint64_t pipe_err:1;
718 uint64_t ill_pad:1;
719 uint64_t sprt3_err:1;
720 uint64_t sprt2_err:1;
721 uint64_t sprt1_err:1;
722 uint64_t sprt0_err:1;
723 uint64_t pins_err:1;
724 uint64_t pop_err:1;
725 uint64_t pdi_err:1;
726 uint64_t pgl_err:1;
727 uint64_t pin_bp:1;
728 uint64_t pout_err:1;
729 uint64_t psldbof:1;
730 uint64_t pidbof:1;
731 uint64_t reserved_38_47:10;
732 uint64_t dtime:2;
733 uint64_t dcnt:2;
734 uint64_t dmafi:2;
735 uint64_t reserved_28_31:4;
736 uint64_t m3_un_wi:1;
737 uint64_t m3_un_b0:1;
738 uint64_t m3_up_wi:1;
739 uint64_t m3_up_b0:1;
740 uint64_t m2_un_wi:1;
741 uint64_t m2_un_b0:1;
742 uint64_t m2_up_wi:1;
743 uint64_t m2_up_b0:1;
744 uint64_t mac1_int:1;
745 uint64_t mac0_int:1;
746 uint64_t mio_int1:1;
747 uint64_t mio_int0:1;
748 uint64_t m1_un_wi:1;
749 uint64_t m1_un_b0:1;
750 uint64_t m1_up_wi:1;
751 uint64_t m1_up_b0:1;
752 uint64_t m0_un_wi:1;
753 uint64_t m0_un_b0:1;
754 uint64_t m0_up_wi:1;
755 uint64_t m0_up_b0:1;
756 uint64_t reserved_6_7:2;
757 uint64_t ptime:1;
758 uint64_t pcnt:1;
759 uint64_t iob2big:1;
760 uint64_t bar0_to:1;
761 uint64_t reserved_1_1:1;
762 uint64_t rml_to:1;
763 } s;
764 struct cvmx_sli_int_sum_cn61xx {
765 uint64_t reserved_61_63:3;
766 uint64_t ill_pad:1;
767 uint64_t sprt3_err:1;
768 uint64_t sprt2_err:1;
769 uint64_t sprt1_err:1;
770 uint64_t sprt0_err:1;
771 uint64_t pins_err:1;
772 uint64_t pop_err:1;
773 uint64_t pdi_err:1;
774 uint64_t pgl_err:1;
775 uint64_t pin_bp:1;
776 uint64_t pout_err:1;
777 uint64_t psldbof:1;
778 uint64_t pidbof:1;
779 uint64_t reserved_38_47:10;
780 uint64_t dtime:2;
781 uint64_t dcnt:2;
782 uint64_t dmafi:2;
783 uint64_t reserved_28_31:4;
784 uint64_t m3_un_wi:1;
785 uint64_t m3_un_b0:1;
786 uint64_t m3_up_wi:1;
787 uint64_t m3_up_b0:1;
788 uint64_t m2_un_wi:1;
789 uint64_t m2_un_b0:1;
790 uint64_t m2_up_wi:1;
791 uint64_t m2_up_b0:1;
792 uint64_t mac1_int:1;
793 uint64_t mac0_int:1;
794 uint64_t mio_int1:1;
795 uint64_t mio_int0:1;
796 uint64_t m1_un_wi:1;
797 uint64_t m1_un_b0:1;
798 uint64_t m1_up_wi:1;
799 uint64_t m1_up_b0:1;
800 uint64_t m0_un_wi:1;
801 uint64_t m0_un_b0:1;
802 uint64_t m0_up_wi:1;
803 uint64_t m0_up_b0:1;
804 uint64_t reserved_6_7:2;
805 uint64_t ptime:1;
806 uint64_t pcnt:1;
807 uint64_t iob2big:1;
808 uint64_t bar0_to:1;
809 uint64_t reserved_1_1:1;
810 uint64_t rml_to:1;
811 } cn61xx;
812 struct cvmx_sli_int_sum_cn63xx {
813 uint64_t reserved_61_63:3;
814 uint64_t ill_pad:1;
815 uint64_t reserved_58_59:2;
816 uint64_t sprt1_err:1;
817 uint64_t sprt0_err:1;
818 uint64_t pins_err:1;
819 uint64_t pop_err:1;
820 uint64_t pdi_err:1;
821 uint64_t pgl_err:1;
822 uint64_t pin_bp:1;
823 uint64_t pout_err:1;
824 uint64_t psldbof:1;
825 uint64_t pidbof:1;
826 uint64_t reserved_38_47:10;
827 uint64_t dtime:2;
828 uint64_t dcnt:2;
829 uint64_t dmafi:2;
830 uint64_t reserved_20_31:12;
831 uint64_t mac1_int:1;
832 uint64_t mac0_int:1;
833 uint64_t mio_int1:1;
834 uint64_t mio_int0:1;
835 uint64_t m1_un_wi:1;
836 uint64_t m1_un_b0:1;
837 uint64_t m1_up_wi:1;
838 uint64_t m1_up_b0:1;
839 uint64_t m0_un_wi:1;
840 uint64_t m0_un_b0:1;
841 uint64_t m0_up_wi:1;
842 uint64_t m0_up_b0:1;
843 uint64_t reserved_6_7:2;
844 uint64_t ptime:1;
845 uint64_t pcnt:1;
846 uint64_t iob2big:1;
847 uint64_t bar0_to:1;
848 uint64_t reserved_1_1:1;
849 uint64_t rml_to:1;
850 } cn63xx;
851 struct cvmx_sli_int_sum_cn63xx cn63xxp1;
852 struct cvmx_sli_int_sum_cn61xx cn66xx;
853 struct cvmx_sli_int_sum_cn68xx {
854 uint64_t reserved_62_63:2;
855 uint64_t pipe_err:1;
856 uint64_t ill_pad:1;
857 uint64_t reserved_58_59:2;
858 uint64_t sprt1_err:1;
859 uint64_t sprt0_err:1;
860 uint64_t pins_err:1;
861 uint64_t pop_err:1;
862 uint64_t pdi_err:1;
863 uint64_t pgl_err:1;
864 uint64_t reserved_51_51:1;
865 uint64_t pout_err:1;
866 uint64_t psldbof:1;
867 uint64_t pidbof:1;
868 uint64_t reserved_38_47:10;
869 uint64_t dtime:2;
870 uint64_t dcnt:2;
871 uint64_t dmafi:2;
872 uint64_t reserved_20_31:12;
873 uint64_t mac1_int:1;
874 uint64_t mac0_int:1;
875 uint64_t mio_int1:1;
876 uint64_t mio_int0:1;
877 uint64_t m1_un_wi:1;
878 uint64_t m1_un_b0:1;
879 uint64_t m1_up_wi:1;
880 uint64_t m1_up_b0:1;
881 uint64_t m0_un_wi:1;
882 uint64_t m0_un_b0:1;
883 uint64_t m0_up_wi:1;
884 uint64_t m0_up_b0:1;
885 uint64_t reserved_6_7:2;
886 uint64_t ptime:1;
887 uint64_t pcnt:1;
888 uint64_t iob2big:1;
889 uint64_t bar0_to:1;
890 uint64_t reserved_1_1:1;
891 uint64_t rml_to:1;
892 } cn68xx;
893 struct cvmx_sli_int_sum_cn68xx cn68xxp1;
894};
895
896union cvmx_sli_last_win_rdata0 {
897 uint64_t u64;
898 struct cvmx_sli_last_win_rdata0_s {
899 uint64_t data:64;
900 } s;
901 struct cvmx_sli_last_win_rdata0_s cn61xx;
902 struct cvmx_sli_last_win_rdata0_s cn63xx;
903 struct cvmx_sli_last_win_rdata0_s cn63xxp1;
904 struct cvmx_sli_last_win_rdata0_s cn66xx;
905 struct cvmx_sli_last_win_rdata0_s cn68xx;
906 struct cvmx_sli_last_win_rdata0_s cn68xxp1;
907};
908
909union cvmx_sli_last_win_rdata1 {
910 uint64_t u64;
911 struct cvmx_sli_last_win_rdata1_s {
912 uint64_t data:64;
913 } s;
914 struct cvmx_sli_last_win_rdata1_s cn61xx;
915 struct cvmx_sli_last_win_rdata1_s cn63xx;
916 struct cvmx_sli_last_win_rdata1_s cn63xxp1;
917 struct cvmx_sli_last_win_rdata1_s cn66xx;
918 struct cvmx_sli_last_win_rdata1_s cn68xx;
919 struct cvmx_sli_last_win_rdata1_s cn68xxp1;
920};
921
922union cvmx_sli_last_win_rdata2 {
923 uint64_t u64;
924 struct cvmx_sli_last_win_rdata2_s {
925 uint64_t data:64;
926 } s;
927 struct cvmx_sli_last_win_rdata2_s cn61xx;
928 struct cvmx_sli_last_win_rdata2_s cn66xx;
929};
930
931union cvmx_sli_last_win_rdata3 {
932 uint64_t u64;
933 struct cvmx_sli_last_win_rdata3_s {
934 uint64_t data:64;
935 } s;
936 struct cvmx_sli_last_win_rdata3_s cn61xx;
937 struct cvmx_sli_last_win_rdata3_s cn66xx;
938};
939
940union cvmx_sli_mac_credit_cnt {
941 uint64_t u64;
942 struct cvmx_sli_mac_credit_cnt_s {
943 uint64_t reserved_54_63:10;
944 uint64_t p1_c_d:1;
945 uint64_t p1_n_d:1;
946 uint64_t p1_p_d:1;
947 uint64_t p0_c_d:1;
948 uint64_t p0_n_d:1;
949 uint64_t p0_p_d:1;
950 uint64_t p1_ccnt:8;
951 uint64_t p1_ncnt:8;
952 uint64_t p1_pcnt:8;
953 uint64_t p0_ccnt:8;
954 uint64_t p0_ncnt:8;
955 uint64_t p0_pcnt:8;
956 } s;
957 struct cvmx_sli_mac_credit_cnt_s cn61xx;
958 struct cvmx_sli_mac_credit_cnt_s cn63xx;
959 struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
960 uint64_t reserved_48_63:16;
961 uint64_t p1_ccnt:8;
962 uint64_t p1_ncnt:8;
963 uint64_t p1_pcnt:8;
964 uint64_t p0_ccnt:8;
965 uint64_t p0_ncnt:8;
966 uint64_t p0_pcnt:8;
967 } cn63xxp1;
968 struct cvmx_sli_mac_credit_cnt_s cn66xx;
969 struct cvmx_sli_mac_credit_cnt_s cn68xx;
970 struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
971};
972
973union cvmx_sli_mac_credit_cnt2 {
974 uint64_t u64;
975 struct cvmx_sli_mac_credit_cnt2_s {
976 uint64_t reserved_54_63:10;
977 uint64_t p3_c_d:1;
978 uint64_t p3_n_d:1;
979 uint64_t p3_p_d:1;
980 uint64_t p2_c_d:1;
981 uint64_t p2_n_d:1;
982 uint64_t p2_p_d:1;
983 uint64_t p3_ccnt:8;
984 uint64_t p3_ncnt:8;
985 uint64_t p3_pcnt:8;
986 uint64_t p2_ccnt:8;
987 uint64_t p2_ncnt:8;
988 uint64_t p2_pcnt:8;
989 } s;
990 struct cvmx_sli_mac_credit_cnt2_s cn61xx;
991 struct cvmx_sli_mac_credit_cnt2_s cn66xx;
992};
993
994union cvmx_sli_mac_number {
995 uint64_t u64;
996 struct cvmx_sli_mac_number_s {
997 uint64_t reserved_9_63:55;
998 uint64_t a_mode:1;
999 uint64_t num:8;
1000 } s;
1001 struct cvmx_sli_mac_number_s cn61xx;
1002 struct cvmx_sli_mac_number_cn63xx {
1003 uint64_t reserved_8_63:56;
1004 uint64_t num:8;
1005 } cn63xx;
1006 struct cvmx_sli_mac_number_s cn66xx;
1007 struct cvmx_sli_mac_number_cn63xx cn68xx;
1008 struct cvmx_sli_mac_number_cn63xx cn68xxp1;
1009};
1010
1011union cvmx_sli_mem_access_ctl {
1012 uint64_t u64;
1013 struct cvmx_sli_mem_access_ctl_s {
1014 uint64_t reserved_14_63:50;
1015 uint64_t max_word:4;
1016 uint64_t timer:10;
1017 } s;
1018 struct cvmx_sli_mem_access_ctl_s cn61xx;
1019 struct cvmx_sli_mem_access_ctl_s cn63xx;
1020 struct cvmx_sli_mem_access_ctl_s cn63xxp1;
1021 struct cvmx_sli_mem_access_ctl_s cn66xx;
1022 struct cvmx_sli_mem_access_ctl_s cn68xx;
1023 struct cvmx_sli_mem_access_ctl_s cn68xxp1;
1024};
1025
1026union cvmx_sli_mem_access_subidx {
1027 uint64_t u64;
1028 struct cvmx_sli_mem_access_subidx_s {
1029 uint64_t reserved_43_63:21;
1030 uint64_t zero:1;
1031 uint64_t port:3;
1032 uint64_t nmerge:1;
1033 uint64_t esr:2;
1034 uint64_t esw:2;
1035 uint64_t wtype:2;
1036 uint64_t rtype:2;
1037 uint64_t reserved_0_29:30;
1038 } s;
1039 struct cvmx_sli_mem_access_subidx_cn61xx {
1040 uint64_t reserved_43_63:21;
1041 uint64_t zero:1;
1042 uint64_t port:3;
1043 uint64_t nmerge:1;
1044 uint64_t esr:2;
1045 uint64_t esw:2;
1046 uint64_t wtype:2;
1047 uint64_t rtype:2;
1048 uint64_t ba:30;
1049 } cn61xx;
1050 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
1051 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
1052 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
1053 struct cvmx_sli_mem_access_subidx_cn68xx {
1054 uint64_t reserved_43_63:21;
1055 uint64_t zero:1;
1056 uint64_t port:3;
1057 uint64_t nmerge:1;
1058 uint64_t esr:2;
1059 uint64_t esw:2;
1060 uint64_t wtype:2;
1061 uint64_t rtype:2;
1062 uint64_t ba:28;
1063 uint64_t reserved_0_1:2;
1064 } cn68xx;
1065 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
1066};
1067
1068union cvmx_sli_msi_enb0 {
1069 uint64_t u64;
1070 struct cvmx_sli_msi_enb0_s {
1071 uint64_t enb:64;
1072 } s;
1073 struct cvmx_sli_msi_enb0_s cn61xx;
1074 struct cvmx_sli_msi_enb0_s cn63xx;
1075 struct cvmx_sli_msi_enb0_s cn63xxp1;
1076 struct cvmx_sli_msi_enb0_s cn66xx;
1077 struct cvmx_sli_msi_enb0_s cn68xx;
1078 struct cvmx_sli_msi_enb0_s cn68xxp1;
1079};
1080
1081union cvmx_sli_msi_enb1 {
1082 uint64_t u64;
1083 struct cvmx_sli_msi_enb1_s {
1084 uint64_t enb:64;
1085 } s;
1086 struct cvmx_sli_msi_enb1_s cn61xx;
1087 struct cvmx_sli_msi_enb1_s cn63xx;
1088 struct cvmx_sli_msi_enb1_s cn63xxp1;
1089 struct cvmx_sli_msi_enb1_s cn66xx;
1090 struct cvmx_sli_msi_enb1_s cn68xx;
1091 struct cvmx_sli_msi_enb1_s cn68xxp1;
1092};
1093
1094union cvmx_sli_msi_enb2 {
1095 uint64_t u64;
1096 struct cvmx_sli_msi_enb2_s {
1097 uint64_t enb:64;
1098 } s;
1099 struct cvmx_sli_msi_enb2_s cn61xx;
1100 struct cvmx_sli_msi_enb2_s cn63xx;
1101 struct cvmx_sli_msi_enb2_s cn63xxp1;
1102 struct cvmx_sli_msi_enb2_s cn66xx;
1103 struct cvmx_sli_msi_enb2_s cn68xx;
1104 struct cvmx_sli_msi_enb2_s cn68xxp1;
1105};
1106
1107union cvmx_sli_msi_enb3 {
1108 uint64_t u64;
1109 struct cvmx_sli_msi_enb3_s {
1110 uint64_t enb:64;
1111 } s;
1112 struct cvmx_sli_msi_enb3_s cn61xx;
1113 struct cvmx_sli_msi_enb3_s cn63xx;
1114 struct cvmx_sli_msi_enb3_s cn63xxp1;
1115 struct cvmx_sli_msi_enb3_s cn66xx;
1116 struct cvmx_sli_msi_enb3_s cn68xx;
1117 struct cvmx_sli_msi_enb3_s cn68xxp1;
1118};
1119
1120union cvmx_sli_msi_rcv0 {
1121 uint64_t u64;
1122 struct cvmx_sli_msi_rcv0_s {
1123 uint64_t intr:64;
1124 } s;
1125 struct cvmx_sli_msi_rcv0_s cn61xx;
1126 struct cvmx_sli_msi_rcv0_s cn63xx;
1127 struct cvmx_sli_msi_rcv0_s cn63xxp1;
1128 struct cvmx_sli_msi_rcv0_s cn66xx;
1129 struct cvmx_sli_msi_rcv0_s cn68xx;
1130 struct cvmx_sli_msi_rcv0_s cn68xxp1;
1131};
1132
1133union cvmx_sli_msi_rcv1 {
1134 uint64_t u64;
1135 struct cvmx_sli_msi_rcv1_s {
1136 uint64_t intr:64;
1137 } s;
1138 struct cvmx_sli_msi_rcv1_s cn61xx;
1139 struct cvmx_sli_msi_rcv1_s cn63xx;
1140 struct cvmx_sli_msi_rcv1_s cn63xxp1;
1141 struct cvmx_sli_msi_rcv1_s cn66xx;
1142 struct cvmx_sli_msi_rcv1_s cn68xx;
1143 struct cvmx_sli_msi_rcv1_s cn68xxp1;
1144};
1145
1146union cvmx_sli_msi_rcv2 {
1147 uint64_t u64;
1148 struct cvmx_sli_msi_rcv2_s {
1149 uint64_t intr:64;
1150 } s;
1151 struct cvmx_sli_msi_rcv2_s cn61xx;
1152 struct cvmx_sli_msi_rcv2_s cn63xx;
1153 struct cvmx_sli_msi_rcv2_s cn63xxp1;
1154 struct cvmx_sli_msi_rcv2_s cn66xx;
1155 struct cvmx_sli_msi_rcv2_s cn68xx;
1156 struct cvmx_sli_msi_rcv2_s cn68xxp1;
1157};
1158
1159union cvmx_sli_msi_rcv3 {
1160 uint64_t u64;
1161 struct cvmx_sli_msi_rcv3_s {
1162 uint64_t intr:64;
1163 } s;
1164 struct cvmx_sli_msi_rcv3_s cn61xx;
1165 struct cvmx_sli_msi_rcv3_s cn63xx;
1166 struct cvmx_sli_msi_rcv3_s cn63xxp1;
1167 struct cvmx_sli_msi_rcv3_s cn66xx;
1168 struct cvmx_sli_msi_rcv3_s cn68xx;
1169 struct cvmx_sli_msi_rcv3_s cn68xxp1;
1170};
1171
1172union cvmx_sli_msi_rd_map {
1173 uint64_t u64;
1174 struct cvmx_sli_msi_rd_map_s {
1175 uint64_t reserved_16_63:48;
1176 uint64_t rd_int:8;
1177 uint64_t msi_int:8;
1178 } s;
1179 struct cvmx_sli_msi_rd_map_s cn61xx;
1180 struct cvmx_sli_msi_rd_map_s cn63xx;
1181 struct cvmx_sli_msi_rd_map_s cn63xxp1;
1182 struct cvmx_sli_msi_rd_map_s cn66xx;
1183 struct cvmx_sli_msi_rd_map_s cn68xx;
1184 struct cvmx_sli_msi_rd_map_s cn68xxp1;
1185};
1186
1187union cvmx_sli_msi_w1c_enb0 {
1188 uint64_t u64;
1189 struct cvmx_sli_msi_w1c_enb0_s {
1190 uint64_t clr:64;
1191 } s;
1192 struct cvmx_sli_msi_w1c_enb0_s cn61xx;
1193 struct cvmx_sli_msi_w1c_enb0_s cn63xx;
1194 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
1195 struct cvmx_sli_msi_w1c_enb0_s cn66xx;
1196 struct cvmx_sli_msi_w1c_enb0_s cn68xx;
1197 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
1198};
1199
1200union cvmx_sli_msi_w1c_enb1 {
1201 uint64_t u64;
1202 struct cvmx_sli_msi_w1c_enb1_s {
1203 uint64_t clr:64;
1204 } s;
1205 struct cvmx_sli_msi_w1c_enb1_s cn61xx;
1206 struct cvmx_sli_msi_w1c_enb1_s cn63xx;
1207 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
1208 struct cvmx_sli_msi_w1c_enb1_s cn66xx;
1209 struct cvmx_sli_msi_w1c_enb1_s cn68xx;
1210 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
1211};
1212
1213union cvmx_sli_msi_w1c_enb2 {
1214 uint64_t u64;
1215 struct cvmx_sli_msi_w1c_enb2_s {
1216 uint64_t clr:64;
1217 } s;
1218 struct cvmx_sli_msi_w1c_enb2_s cn61xx;
1219 struct cvmx_sli_msi_w1c_enb2_s cn63xx;
1220 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
1221 struct cvmx_sli_msi_w1c_enb2_s cn66xx;
1222 struct cvmx_sli_msi_w1c_enb2_s cn68xx;
1223 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
1224};
1225
1226union cvmx_sli_msi_w1c_enb3 {
1227 uint64_t u64;
1228 struct cvmx_sli_msi_w1c_enb3_s {
1229 uint64_t clr:64;
1230 } s;
1231 struct cvmx_sli_msi_w1c_enb3_s cn61xx;
1232 struct cvmx_sli_msi_w1c_enb3_s cn63xx;
1233 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
1234 struct cvmx_sli_msi_w1c_enb3_s cn66xx;
1235 struct cvmx_sli_msi_w1c_enb3_s cn68xx;
1236 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
1237};
1238
1239union cvmx_sli_msi_w1s_enb0 {
1240 uint64_t u64;
1241 struct cvmx_sli_msi_w1s_enb0_s {
1242 uint64_t set:64;
1243 } s;
1244 struct cvmx_sli_msi_w1s_enb0_s cn61xx;
1245 struct cvmx_sli_msi_w1s_enb0_s cn63xx;
1246 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
1247 struct cvmx_sli_msi_w1s_enb0_s cn66xx;
1248 struct cvmx_sli_msi_w1s_enb0_s cn68xx;
1249 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
1250};
1251
1252union cvmx_sli_msi_w1s_enb1 {
1253 uint64_t u64;
1254 struct cvmx_sli_msi_w1s_enb1_s {
1255 uint64_t set:64;
1256 } s;
1257 struct cvmx_sli_msi_w1s_enb1_s cn61xx;
1258 struct cvmx_sli_msi_w1s_enb1_s cn63xx;
1259 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
1260 struct cvmx_sli_msi_w1s_enb1_s cn66xx;
1261 struct cvmx_sli_msi_w1s_enb1_s cn68xx;
1262 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
1263};
1264
1265union cvmx_sli_msi_w1s_enb2 {
1266 uint64_t u64;
1267 struct cvmx_sli_msi_w1s_enb2_s {
1268 uint64_t set:64;
1269 } s;
1270 struct cvmx_sli_msi_w1s_enb2_s cn61xx;
1271 struct cvmx_sli_msi_w1s_enb2_s cn63xx;
1272 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
1273 struct cvmx_sli_msi_w1s_enb2_s cn66xx;
1274 struct cvmx_sli_msi_w1s_enb2_s cn68xx;
1275 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
1276};
1277
1278union cvmx_sli_msi_w1s_enb3 {
1279 uint64_t u64;
1280 struct cvmx_sli_msi_w1s_enb3_s {
1281 uint64_t set:64;
1282 } s;
1283 struct cvmx_sli_msi_w1s_enb3_s cn61xx;
1284 struct cvmx_sli_msi_w1s_enb3_s cn63xx;
1285 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
1286 struct cvmx_sli_msi_w1s_enb3_s cn66xx;
1287 struct cvmx_sli_msi_w1s_enb3_s cn68xx;
1288 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
1289};
1290
1291union cvmx_sli_msi_wr_map {
1292 uint64_t u64;
1293 struct cvmx_sli_msi_wr_map_s {
1294 uint64_t reserved_16_63:48;
1295 uint64_t ciu_int:8;
1296 uint64_t msi_int:8;
1297 } s;
1298 struct cvmx_sli_msi_wr_map_s cn61xx;
1299 struct cvmx_sli_msi_wr_map_s cn63xx;
1300 struct cvmx_sli_msi_wr_map_s cn63xxp1;
1301 struct cvmx_sli_msi_wr_map_s cn66xx;
1302 struct cvmx_sli_msi_wr_map_s cn68xx;
1303 struct cvmx_sli_msi_wr_map_s cn68xxp1;
1304};
1305
1306union cvmx_sli_pcie_msi_rcv {
1307 uint64_t u64;
1308 struct cvmx_sli_pcie_msi_rcv_s {
1309 uint64_t reserved_8_63:56;
1310 uint64_t intr:8;
1311 } s;
1312 struct cvmx_sli_pcie_msi_rcv_s cn61xx;
1313 struct cvmx_sli_pcie_msi_rcv_s cn63xx;
1314 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
1315 struct cvmx_sli_pcie_msi_rcv_s cn66xx;
1316 struct cvmx_sli_pcie_msi_rcv_s cn68xx;
1317 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
1318};
1319
1320union cvmx_sli_pcie_msi_rcv_b1 {
1321 uint64_t u64;
1322 struct cvmx_sli_pcie_msi_rcv_b1_s {
1323 uint64_t reserved_16_63:48;
1324 uint64_t intr:8;
1325 uint64_t reserved_0_7:8;
1326 } s;
1327 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
1328 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
1329 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
1330 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
1331 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
1332 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
1333};
1334
1335union cvmx_sli_pcie_msi_rcv_b2 {
1336 uint64_t u64;
1337 struct cvmx_sli_pcie_msi_rcv_b2_s {
1338 uint64_t reserved_24_63:40;
1339 uint64_t intr:8;
1340 uint64_t reserved_0_15:16;
1341 } s;
1342 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
1343 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
1344 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
1345 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
1346 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
1347 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
1348};
1349
1350union cvmx_sli_pcie_msi_rcv_b3 {
1351 uint64_t u64;
1352 struct cvmx_sli_pcie_msi_rcv_b3_s {
1353 uint64_t reserved_32_63:32;
1354 uint64_t intr:8;
1355 uint64_t reserved_0_23:24;
1356 } s;
1357 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
1358 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
1359 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
1360 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
1361 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
1362 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
1363};
1364
1365union cvmx_sli_pktx_cnts {
1366 uint64_t u64;
1367 struct cvmx_sli_pktx_cnts_s {
1368 uint64_t reserved_54_63:10;
1369 uint64_t timer:22;
1370 uint64_t cnt:32;
1371 } s;
1372 struct cvmx_sli_pktx_cnts_s cn61xx;
1373 struct cvmx_sli_pktx_cnts_s cn63xx;
1374 struct cvmx_sli_pktx_cnts_s cn63xxp1;
1375 struct cvmx_sli_pktx_cnts_s cn66xx;
1376 struct cvmx_sli_pktx_cnts_s cn68xx;
1377 struct cvmx_sli_pktx_cnts_s cn68xxp1;
1378};
1379
1380union cvmx_sli_pktx_in_bp {
1381 uint64_t u64;
1382 struct cvmx_sli_pktx_in_bp_s {
1383 uint64_t wmark:32;
1384 uint64_t cnt:32;
1385 } s;
1386 struct cvmx_sli_pktx_in_bp_s cn61xx;
1387 struct cvmx_sli_pktx_in_bp_s cn63xx;
1388 struct cvmx_sli_pktx_in_bp_s cn63xxp1;
1389 struct cvmx_sli_pktx_in_bp_s cn66xx;
1390};
1391
1392union cvmx_sli_pktx_instr_baddr {
1393 uint64_t u64;
1394 struct cvmx_sli_pktx_instr_baddr_s {
1395 uint64_t addr:61;
1396 uint64_t reserved_0_2:3;
1397 } s;
1398 struct cvmx_sli_pktx_instr_baddr_s cn61xx;
1399 struct cvmx_sli_pktx_instr_baddr_s cn63xx;
1400 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
1401 struct cvmx_sli_pktx_instr_baddr_s cn66xx;
1402 struct cvmx_sli_pktx_instr_baddr_s cn68xx;
1403 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
1404};
1405
1406union cvmx_sli_pktx_instr_baoff_dbell {
1407 uint64_t u64;
1408 struct cvmx_sli_pktx_instr_baoff_dbell_s {
1409 uint64_t aoff:32;
1410 uint64_t dbell:32;
1411 } s;
1412 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
1413 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
1414 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
1415 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
1416 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
1417 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
1418};
1419
1420union cvmx_sli_pktx_instr_fifo_rsize {
1421 uint64_t u64;
1422 struct cvmx_sli_pktx_instr_fifo_rsize_s {
1423 uint64_t max:9;
1424 uint64_t rrp:9;
1425 uint64_t wrp:9;
1426 uint64_t fcnt:5;
1427 uint64_t rsize:32;
1428 } s;
1429 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
1430 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
1431 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
1432 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
1433 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
1434 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
1435};
1436
1437union cvmx_sli_pktx_instr_header {
1438 uint64_t u64;
1439 struct cvmx_sli_pktx_instr_header_s {
1440 uint64_t reserved_44_63:20;
1441 uint64_t pbp:1;
1442 uint64_t reserved_38_42:5;
1443 uint64_t rparmode:2;
1444 uint64_t reserved_35_35:1;
1445 uint64_t rskp_len:7;
1446 uint64_t rngrpext:2;
1447 uint64_t rnqos:1;
1448 uint64_t rngrp:1;
1449 uint64_t rntt:1;
1450 uint64_t rntag:1;
1451 uint64_t use_ihdr:1;
1452 uint64_t reserved_16_20:5;
1453 uint64_t par_mode:2;
1454 uint64_t reserved_13_13:1;
1455 uint64_t skp_len:7;
1456 uint64_t ngrpext:2;
1457 uint64_t nqos:1;
1458 uint64_t ngrp:1;
1459 uint64_t ntt:1;
1460 uint64_t ntag:1;
1461 } s;
1462 struct cvmx_sli_pktx_instr_header_cn61xx {
1463 uint64_t reserved_44_63:20;
1464 uint64_t pbp:1;
1465 uint64_t reserved_38_42:5;
1466 uint64_t rparmode:2;
1467 uint64_t reserved_35_35:1;
1468 uint64_t rskp_len:7;
1469 uint64_t reserved_26_27:2;
1470 uint64_t rnqos:1;
1471 uint64_t rngrp:1;
1472 uint64_t rntt:1;
1473 uint64_t rntag:1;
1474 uint64_t use_ihdr:1;
1475 uint64_t reserved_16_20:5;
1476 uint64_t par_mode:2;
1477 uint64_t reserved_13_13:1;
1478 uint64_t skp_len:7;
1479 uint64_t reserved_4_5:2;
1480 uint64_t nqos:1;
1481 uint64_t ngrp:1;
1482 uint64_t ntt:1;
1483 uint64_t ntag:1;
1484 } cn61xx;
1485 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
1486 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
1487 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
1488 struct cvmx_sli_pktx_instr_header_s cn68xx;
1489 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
1490};
1491
1492union cvmx_sli_pktx_out_size {
1493 uint64_t u64;
1494 struct cvmx_sli_pktx_out_size_s {
1495 uint64_t reserved_23_63:41;
1496 uint64_t isize:7;
1497 uint64_t bsize:16;
1498 } s;
1499 struct cvmx_sli_pktx_out_size_s cn61xx;
1500 struct cvmx_sli_pktx_out_size_s cn63xx;
1501 struct cvmx_sli_pktx_out_size_s cn63xxp1;
1502 struct cvmx_sli_pktx_out_size_s cn66xx;
1503 struct cvmx_sli_pktx_out_size_s cn68xx;
1504 struct cvmx_sli_pktx_out_size_s cn68xxp1;
1505};
1506
1507union cvmx_sli_pktx_slist_baddr {
1508 uint64_t u64;
1509 struct cvmx_sli_pktx_slist_baddr_s {
1510 uint64_t addr:60;
1511 uint64_t reserved_0_3:4;
1512 } s;
1513 struct cvmx_sli_pktx_slist_baddr_s cn61xx;
1514 struct cvmx_sli_pktx_slist_baddr_s cn63xx;
1515 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
1516 struct cvmx_sli_pktx_slist_baddr_s cn66xx;
1517 struct cvmx_sli_pktx_slist_baddr_s cn68xx;
1518 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
1519};
1520
1521union cvmx_sli_pktx_slist_baoff_dbell {
1522 uint64_t u64;
1523 struct cvmx_sli_pktx_slist_baoff_dbell_s {
1524 uint64_t aoff:32;
1525 uint64_t dbell:32;
1526 } s;
1527 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
1528 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
1529 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
1530 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
1531 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
1532 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
1533};
1534
1535union cvmx_sli_pktx_slist_fifo_rsize {
1536 uint64_t u64;
1537 struct cvmx_sli_pktx_slist_fifo_rsize_s {
1538 uint64_t reserved_32_63:32;
1539 uint64_t rsize:32;
1540 } s;
1541 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
1542 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
1543 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
1544 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
1545 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
1546 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
1547};
1548
1549union cvmx_sli_pkt_cnt_int {
1550 uint64_t u64;
1551 struct cvmx_sli_pkt_cnt_int_s {
1552 uint64_t reserved_32_63:32;
1553 uint64_t port:32;
1554 } s;
1555 struct cvmx_sli_pkt_cnt_int_s cn61xx;
1556 struct cvmx_sli_pkt_cnt_int_s cn63xx;
1557 struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
1558 struct cvmx_sli_pkt_cnt_int_s cn66xx;
1559 struct cvmx_sli_pkt_cnt_int_s cn68xx;
1560 struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
1561};
1562
1563union cvmx_sli_pkt_cnt_int_enb {
1564 uint64_t u64;
1565 struct cvmx_sli_pkt_cnt_int_enb_s {
1566 uint64_t reserved_32_63:32;
1567 uint64_t port:32;
1568 } s;
1569 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
1570 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
1571 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
1572 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
1573 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
1574 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
1575};
1576
1577union cvmx_sli_pkt_ctl {
1578 uint64_t u64;
1579 struct cvmx_sli_pkt_ctl_s {
1580 uint64_t reserved_5_63:59;
1581 uint64_t ring_en:1;
1582 uint64_t pkt_bp:4;
1583 } s;
1584 struct cvmx_sli_pkt_ctl_s cn61xx;
1585 struct cvmx_sli_pkt_ctl_s cn63xx;
1586 struct cvmx_sli_pkt_ctl_s cn63xxp1;
1587 struct cvmx_sli_pkt_ctl_s cn66xx;
1588 struct cvmx_sli_pkt_ctl_s cn68xx;
1589 struct cvmx_sli_pkt_ctl_s cn68xxp1;
1590};
1591
1592union cvmx_sli_pkt_data_out_es {
1593 uint64_t u64;
1594 struct cvmx_sli_pkt_data_out_es_s {
1595 uint64_t es:64;
1596 } s;
1597 struct cvmx_sli_pkt_data_out_es_s cn61xx;
1598 struct cvmx_sli_pkt_data_out_es_s cn63xx;
1599 struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
1600 struct cvmx_sli_pkt_data_out_es_s cn66xx;
1601 struct cvmx_sli_pkt_data_out_es_s cn68xx;
1602 struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
1603};
1604
1605union cvmx_sli_pkt_data_out_ns {
1606 uint64_t u64;
1607 struct cvmx_sli_pkt_data_out_ns_s {
1608 uint64_t reserved_32_63:32;
1609 uint64_t nsr:32;
1610 } s;
1611 struct cvmx_sli_pkt_data_out_ns_s cn61xx;
1612 struct cvmx_sli_pkt_data_out_ns_s cn63xx;
1613 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
1614 struct cvmx_sli_pkt_data_out_ns_s cn66xx;
1615 struct cvmx_sli_pkt_data_out_ns_s cn68xx;
1616 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
1617};
1618
1619union cvmx_sli_pkt_data_out_ror {
1620 uint64_t u64;
1621 struct cvmx_sli_pkt_data_out_ror_s {
1622 uint64_t reserved_32_63:32;
1623 uint64_t ror:32;
1624 } s;
1625 struct cvmx_sli_pkt_data_out_ror_s cn61xx;
1626 struct cvmx_sli_pkt_data_out_ror_s cn63xx;
1627 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
1628 struct cvmx_sli_pkt_data_out_ror_s cn66xx;
1629 struct cvmx_sli_pkt_data_out_ror_s cn68xx;
1630 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
1631};
1632
1633union cvmx_sli_pkt_dpaddr {
1634 uint64_t u64;
1635 struct cvmx_sli_pkt_dpaddr_s {
1636 uint64_t reserved_32_63:32;
1637 uint64_t dptr:32;
1638 } s;
1639 struct cvmx_sli_pkt_dpaddr_s cn61xx;
1640 struct cvmx_sli_pkt_dpaddr_s cn63xx;
1641 struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
1642 struct cvmx_sli_pkt_dpaddr_s cn66xx;
1643 struct cvmx_sli_pkt_dpaddr_s cn68xx;
1644 struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
1645};
1646
1647union cvmx_sli_pkt_in_bp {
1648 uint64_t u64;
1649 struct cvmx_sli_pkt_in_bp_s {
1650 uint64_t reserved_32_63:32;
1651 uint64_t bp:32;
1652 } s;
1653 struct cvmx_sli_pkt_in_bp_s cn61xx;
1654 struct cvmx_sli_pkt_in_bp_s cn63xx;
1655 struct cvmx_sli_pkt_in_bp_s cn63xxp1;
1656 struct cvmx_sli_pkt_in_bp_s cn66xx;
1657};
1658
1659union cvmx_sli_pkt_in_donex_cnts {
1660 uint64_t u64;
1661 struct cvmx_sli_pkt_in_donex_cnts_s {
1662 uint64_t reserved_32_63:32;
1663 uint64_t cnt:32;
1664 } s;
1665 struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
1666 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
1667 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
1668 struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
1669 struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
1670 struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
1671};
1672
1673union cvmx_sli_pkt_in_instr_counts {
1674 uint64_t u64;
1675 struct cvmx_sli_pkt_in_instr_counts_s {
1676 uint64_t wr_cnt:32;
1677 uint64_t rd_cnt:32;
1678 } s;
1679 struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
1680 struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
1681 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
1682 struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
1683 struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
1684 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
1685};
1686
1687union cvmx_sli_pkt_in_pcie_port {
1688 uint64_t u64;
1689 struct cvmx_sli_pkt_in_pcie_port_s {
1690 uint64_t pp:64;
1691 } s;
1692 struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
1693 struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
1694 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
1695 struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
1696 struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
1697 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
1698};
1699
1700union cvmx_sli_pkt_input_control {
1701 uint64_t u64;
1702 struct cvmx_sli_pkt_input_control_s {
1703 uint64_t prd_erst:1;
1704 uint64_t prd_rds:7;
1705 uint64_t gii_erst:1;
1706 uint64_t gii_rds:7;
1707 uint64_t reserved_41_47:7;
1708 uint64_t prc_idle:1;
1709 uint64_t reserved_24_39:16;
1710 uint64_t pin_rst:1;
1711 uint64_t pkt_rr:1;
1712 uint64_t pbp_dhi:13;
1713 uint64_t d_nsr:1;
1714 uint64_t d_esr:2;
1715 uint64_t d_ror:1;
1716 uint64_t use_csr:1;
1717 uint64_t nsr:1;
1718 uint64_t esr:2;
1719 uint64_t ror:1;
1720 } s;
1721 struct cvmx_sli_pkt_input_control_s cn61xx;
1722 struct cvmx_sli_pkt_input_control_cn63xx {
1723 uint64_t reserved_23_63:41;
1724 uint64_t pkt_rr:1;
1725 uint64_t pbp_dhi:13;
1726 uint64_t d_nsr:1;
1727 uint64_t d_esr:2;
1728 uint64_t d_ror:1;
1729 uint64_t use_csr:1;
1730 uint64_t nsr:1;
1731 uint64_t esr:2;
1732 uint64_t ror:1;
1733 } cn63xx;
1734 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
1735 struct cvmx_sli_pkt_input_control_s cn66xx;
1736 struct cvmx_sli_pkt_input_control_s cn68xx;
1737 struct cvmx_sli_pkt_input_control_s cn68xxp1;
1738};
1739
1740union cvmx_sli_pkt_instr_enb {
1741 uint64_t u64;
1742 struct cvmx_sli_pkt_instr_enb_s {
1743 uint64_t reserved_32_63:32;
1744 uint64_t enb:32;
1745 } s;
1746 struct cvmx_sli_pkt_instr_enb_s cn61xx;
1747 struct cvmx_sli_pkt_instr_enb_s cn63xx;
1748 struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
1749 struct cvmx_sli_pkt_instr_enb_s cn66xx;
1750 struct cvmx_sli_pkt_instr_enb_s cn68xx;
1751 struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
1752};
1753
1754union cvmx_sli_pkt_instr_rd_size {
1755 uint64_t u64;
1756 struct cvmx_sli_pkt_instr_rd_size_s {
1757 uint64_t rdsize:64;
1758 } s;
1759 struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
1760 struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
1761 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
1762 struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
1763 struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
1764 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
1765};
1766
1767union cvmx_sli_pkt_instr_size {
1768 uint64_t u64;
1769 struct cvmx_sli_pkt_instr_size_s {
1770 uint64_t reserved_32_63:32;
1771 uint64_t is_64b:32;
1772 } s;
1773 struct cvmx_sli_pkt_instr_size_s cn61xx;
1774 struct cvmx_sli_pkt_instr_size_s cn63xx;
1775 struct cvmx_sli_pkt_instr_size_s cn63xxp1;
1776 struct cvmx_sli_pkt_instr_size_s cn66xx;
1777 struct cvmx_sli_pkt_instr_size_s cn68xx;
1778 struct cvmx_sli_pkt_instr_size_s cn68xxp1;
1779};
1780
1781union cvmx_sli_pkt_int_levels {
1782 uint64_t u64;
1783 struct cvmx_sli_pkt_int_levels_s {
1784 uint64_t reserved_54_63:10;
1785 uint64_t time:22;
1786 uint64_t cnt:32;
1787 } s;
1788 struct cvmx_sli_pkt_int_levels_s cn61xx;
1789 struct cvmx_sli_pkt_int_levels_s cn63xx;
1790 struct cvmx_sli_pkt_int_levels_s cn63xxp1;
1791 struct cvmx_sli_pkt_int_levels_s cn66xx;
1792 struct cvmx_sli_pkt_int_levels_s cn68xx;
1793 struct cvmx_sli_pkt_int_levels_s cn68xxp1;
1794};
1795
1796union cvmx_sli_pkt_iptr {
1797 uint64_t u64;
1798 struct cvmx_sli_pkt_iptr_s {
1799 uint64_t reserved_32_63:32;
1800 uint64_t iptr:32;
1801 } s;
1802 struct cvmx_sli_pkt_iptr_s cn61xx;
1803 struct cvmx_sli_pkt_iptr_s cn63xx;
1804 struct cvmx_sli_pkt_iptr_s cn63xxp1;
1805 struct cvmx_sli_pkt_iptr_s cn66xx;
1806 struct cvmx_sli_pkt_iptr_s cn68xx;
1807 struct cvmx_sli_pkt_iptr_s cn68xxp1;
1808};
1809
1810union cvmx_sli_pkt_out_bmode {
1811 uint64_t u64;
1812 struct cvmx_sli_pkt_out_bmode_s {
1813 uint64_t reserved_32_63:32;
1814 uint64_t bmode:32;
1815 } s;
1816 struct cvmx_sli_pkt_out_bmode_s cn61xx;
1817 struct cvmx_sli_pkt_out_bmode_s cn63xx;
1818 struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
1819 struct cvmx_sli_pkt_out_bmode_s cn66xx;
1820 struct cvmx_sli_pkt_out_bmode_s cn68xx;
1821 struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
1822};
1823
1824union cvmx_sli_pkt_out_bp_en {
1825 uint64_t u64;
1826 struct cvmx_sli_pkt_out_bp_en_s {
1827 uint64_t reserved_32_63:32;
1828 uint64_t bp_en:32;
1829 } s;
1830 struct cvmx_sli_pkt_out_bp_en_s cn68xx;
1831 struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
1832};
1833
1834union cvmx_sli_pkt_out_enb {
1835 uint64_t u64;
1836 struct cvmx_sli_pkt_out_enb_s {
1837 uint64_t reserved_32_63:32;
1838 uint64_t enb:32;
1839 } s;
1840 struct cvmx_sli_pkt_out_enb_s cn61xx;
1841 struct cvmx_sli_pkt_out_enb_s cn63xx;
1842 struct cvmx_sli_pkt_out_enb_s cn63xxp1;
1843 struct cvmx_sli_pkt_out_enb_s cn66xx;
1844 struct cvmx_sli_pkt_out_enb_s cn68xx;
1845 struct cvmx_sli_pkt_out_enb_s cn68xxp1;
1846};
1847
1848union cvmx_sli_pkt_output_wmark {
1849 uint64_t u64;
1850 struct cvmx_sli_pkt_output_wmark_s {
1851 uint64_t reserved_32_63:32;
1852 uint64_t wmark:32;
1853 } s;
1854 struct cvmx_sli_pkt_output_wmark_s cn61xx;
1855 struct cvmx_sli_pkt_output_wmark_s cn63xx;
1856 struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
1857 struct cvmx_sli_pkt_output_wmark_s cn66xx;
1858 struct cvmx_sli_pkt_output_wmark_s cn68xx;
1859 struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
1860};
1861
1862union cvmx_sli_pkt_pcie_port {
1863 uint64_t u64;
1864 struct cvmx_sli_pkt_pcie_port_s {
1865 uint64_t pp:64;
1866 } s;
1867 struct cvmx_sli_pkt_pcie_port_s cn61xx;
1868 struct cvmx_sli_pkt_pcie_port_s cn63xx;
1869 struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
1870 struct cvmx_sli_pkt_pcie_port_s cn66xx;
1871 struct cvmx_sli_pkt_pcie_port_s cn68xx;
1872 struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
1873};
1874
1875union cvmx_sli_pkt_port_in_rst {
1876 uint64_t u64;
1877 struct cvmx_sli_pkt_port_in_rst_s {
1878 uint64_t in_rst:32;
1879 uint64_t out_rst:32;
1880 } s;
1881 struct cvmx_sli_pkt_port_in_rst_s cn61xx;
1882 struct cvmx_sli_pkt_port_in_rst_s cn63xx;
1883 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
1884 struct cvmx_sli_pkt_port_in_rst_s cn66xx;
1885 struct cvmx_sli_pkt_port_in_rst_s cn68xx;
1886 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
1887};
1888
1889union cvmx_sli_pkt_slist_es {
1890 uint64_t u64;
1891 struct cvmx_sli_pkt_slist_es_s {
1892 uint64_t es:64;
1893 } s;
1894 struct cvmx_sli_pkt_slist_es_s cn61xx;
1895 struct cvmx_sli_pkt_slist_es_s cn63xx;
1896 struct cvmx_sli_pkt_slist_es_s cn63xxp1;
1897 struct cvmx_sli_pkt_slist_es_s cn66xx;
1898 struct cvmx_sli_pkt_slist_es_s cn68xx;
1899 struct cvmx_sli_pkt_slist_es_s cn68xxp1;
1900};
1901
1902union cvmx_sli_pkt_slist_ns {
1903 uint64_t u64;
1904 struct cvmx_sli_pkt_slist_ns_s {
1905 uint64_t reserved_32_63:32;
1906 uint64_t nsr:32;
1907 } s;
1908 struct cvmx_sli_pkt_slist_ns_s cn61xx;
1909 struct cvmx_sli_pkt_slist_ns_s cn63xx;
1910 struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
1911 struct cvmx_sli_pkt_slist_ns_s cn66xx;
1912 struct cvmx_sli_pkt_slist_ns_s cn68xx;
1913 struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
1914};
1915
1916union cvmx_sli_pkt_slist_ror {
1917 uint64_t u64;
1918 struct cvmx_sli_pkt_slist_ror_s {
1919 uint64_t reserved_32_63:32;
1920 uint64_t ror:32;
1921 } s;
1922 struct cvmx_sli_pkt_slist_ror_s cn61xx;
1923 struct cvmx_sli_pkt_slist_ror_s cn63xx;
1924 struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
1925 struct cvmx_sli_pkt_slist_ror_s cn66xx;
1926 struct cvmx_sli_pkt_slist_ror_s cn68xx;
1927 struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
1928};
1929
1930union cvmx_sli_pkt_time_int {
1931 uint64_t u64;
1932 struct cvmx_sli_pkt_time_int_s {
1933 uint64_t reserved_32_63:32;
1934 uint64_t port:32;
1935 } s;
1936 struct cvmx_sli_pkt_time_int_s cn61xx;
1937 struct cvmx_sli_pkt_time_int_s cn63xx;
1938 struct cvmx_sli_pkt_time_int_s cn63xxp1;
1939 struct cvmx_sli_pkt_time_int_s cn66xx;
1940 struct cvmx_sli_pkt_time_int_s cn68xx;
1941 struct cvmx_sli_pkt_time_int_s cn68xxp1;
1942};
1943
1944union cvmx_sli_pkt_time_int_enb {
1945 uint64_t u64;
1946 struct cvmx_sli_pkt_time_int_enb_s {
1947 uint64_t reserved_32_63:32;
1948 uint64_t port:32;
1949 } s;
1950 struct cvmx_sli_pkt_time_int_enb_s cn61xx;
1951 struct cvmx_sli_pkt_time_int_enb_s cn63xx;
1952 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
1953 struct cvmx_sli_pkt_time_int_enb_s cn66xx;
1954 struct cvmx_sli_pkt_time_int_enb_s cn68xx;
1955 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
1956};
1957
1958union cvmx_sli_portx_pkind {
1959 uint64_t u64;
1960 struct cvmx_sli_portx_pkind_s {
1961 uint64_t reserved_25_63:39;
1962 uint64_t rpk_enb:1;
1963 uint64_t reserved_22_23:2;
1964 uint64_t pkindr:6;
1965 uint64_t reserved_14_15:2;
1966 uint64_t bpkind:6;
1967 uint64_t reserved_6_7:2;
1968 uint64_t pkind:6;
1969 } s;
1970 struct cvmx_sli_portx_pkind_s cn68xx;
1971 struct cvmx_sli_portx_pkind_cn68xxp1 {
1972 uint64_t reserved_14_63:50;
1973 uint64_t bpkind:6;
1974 uint64_t reserved_6_7:2;
1975 uint64_t pkind:6;
1976 } cn68xxp1;
1977};
1978
1979union cvmx_sli_s2m_portx_ctl {
1980 uint64_t u64;
1981 struct cvmx_sli_s2m_portx_ctl_s {
1982 uint64_t reserved_5_63:59;
1983 uint64_t wind_d:1;
1984 uint64_t bar0_d:1;
1985 uint64_t mrrs:3;
1986 } s;
1987 struct cvmx_sli_s2m_portx_ctl_s cn61xx;
1988 struct cvmx_sli_s2m_portx_ctl_s cn63xx;
1989 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
1990 struct cvmx_sli_s2m_portx_ctl_s cn66xx;
1991 struct cvmx_sli_s2m_portx_ctl_s cn68xx;
1992 struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
1993};
1994
1995union cvmx_sli_scratch_1 {
1996 uint64_t u64;
1997 struct cvmx_sli_scratch_1_s {
1998 uint64_t data:64;
1999 } s;
2000 struct cvmx_sli_scratch_1_s cn61xx;
2001 struct cvmx_sli_scratch_1_s cn63xx;
2002 struct cvmx_sli_scratch_1_s cn63xxp1;
2003 struct cvmx_sli_scratch_1_s cn66xx;
2004 struct cvmx_sli_scratch_1_s cn68xx;
2005 struct cvmx_sli_scratch_1_s cn68xxp1;
2006};
2007
2008union cvmx_sli_scratch_2 {
2009 uint64_t u64;
2010 struct cvmx_sli_scratch_2_s {
2011 uint64_t data:64;
2012 } s;
2013 struct cvmx_sli_scratch_2_s cn61xx;
2014 struct cvmx_sli_scratch_2_s cn63xx;
2015 struct cvmx_sli_scratch_2_s cn63xxp1;
2016 struct cvmx_sli_scratch_2_s cn66xx;
2017 struct cvmx_sli_scratch_2_s cn68xx;
2018 struct cvmx_sli_scratch_2_s cn68xxp1;
2019};
2020
2021union cvmx_sli_state1 {
2022 uint64_t u64;
2023 struct cvmx_sli_state1_s {
2024 uint64_t cpl1:12;
2025 uint64_t cpl0:12;
2026 uint64_t arb:1;
2027 uint64_t csr:39;
2028 } s;
2029 struct cvmx_sli_state1_s cn61xx;
2030 struct cvmx_sli_state1_s cn63xx;
2031 struct cvmx_sli_state1_s cn63xxp1;
2032 struct cvmx_sli_state1_s cn66xx;
2033 struct cvmx_sli_state1_s cn68xx;
2034 struct cvmx_sli_state1_s cn68xxp1;
2035};
2036
2037union cvmx_sli_state2 {
2038 uint64_t u64;
2039 struct cvmx_sli_state2_s {
2040 uint64_t reserved_56_63:8;
2041 uint64_t nnp1:8;
2042 uint64_t reserved_47_47:1;
2043 uint64_t rac:1;
2044 uint64_t csm1:15;
2045 uint64_t csm0:15;
2046 uint64_t nnp0:8;
2047 uint64_t nnd:8;
2048 } s;
2049 struct cvmx_sli_state2_s cn61xx;
2050 struct cvmx_sli_state2_s cn63xx;
2051 struct cvmx_sli_state2_s cn63xxp1;
2052 struct cvmx_sli_state2_s cn66xx;
2053 struct cvmx_sli_state2_s cn68xx;
2054 struct cvmx_sli_state2_s cn68xxp1;
2055};
2056
2057union cvmx_sli_state3 {
2058 uint64_t u64;
2059 struct cvmx_sli_state3_s {
2060 uint64_t reserved_56_63:8;
2061 uint64_t psm1:15;
2062 uint64_t psm0:15;
2063 uint64_t nsm1:13;
2064 uint64_t nsm0:13;
2065 } s;
2066 struct cvmx_sli_state3_s cn61xx;
2067 struct cvmx_sli_state3_s cn63xx;
2068 struct cvmx_sli_state3_s cn63xxp1;
2069 struct cvmx_sli_state3_s cn66xx;
2070 struct cvmx_sli_state3_s cn68xx;
2071 struct cvmx_sli_state3_s cn68xxp1;
2072};
2073
2074union cvmx_sli_tx_pipe {
2075 uint64_t u64;
2076 struct cvmx_sli_tx_pipe_s {
2077 uint64_t reserved_24_63:40;
2078 uint64_t nump:8;
2079 uint64_t reserved_7_15:9;
2080 uint64_t base:7;
2081 } s;
2082 struct cvmx_sli_tx_pipe_s cn68xx;
2083 struct cvmx_sli_tx_pipe_s cn68xxp1;
2084};
2085
2086union cvmx_sli_win_rd_addr {
2087 uint64_t u64;
2088 struct cvmx_sli_win_rd_addr_s {
2089 uint64_t reserved_51_63:13;
2090 uint64_t ld_cmd:2;
2091 uint64_t iobit:1;
2092 uint64_t rd_addr:48;
2093 } s;
2094 struct cvmx_sli_win_rd_addr_s cn61xx;
2095 struct cvmx_sli_win_rd_addr_s cn63xx;
2096 struct cvmx_sli_win_rd_addr_s cn63xxp1;
2097 struct cvmx_sli_win_rd_addr_s cn66xx;
2098 struct cvmx_sli_win_rd_addr_s cn68xx;
2099 struct cvmx_sli_win_rd_addr_s cn68xxp1;
2100};
2101
2102union cvmx_sli_win_rd_data {
2103 uint64_t u64;
2104 struct cvmx_sli_win_rd_data_s {
2105 uint64_t rd_data:64;
2106 } s;
2107 struct cvmx_sli_win_rd_data_s cn61xx;
2108 struct cvmx_sli_win_rd_data_s cn63xx;
2109 struct cvmx_sli_win_rd_data_s cn63xxp1;
2110 struct cvmx_sli_win_rd_data_s cn66xx;
2111 struct cvmx_sli_win_rd_data_s cn68xx;
2112 struct cvmx_sli_win_rd_data_s cn68xxp1;
2113};
2114
2115union cvmx_sli_win_wr_addr {
2116 uint64_t u64;
2117 struct cvmx_sli_win_wr_addr_s {
2118 uint64_t reserved_49_63:15;
2119 uint64_t iobit:1;
2120 uint64_t wr_addr:45;
2121 uint64_t reserved_0_2:3;
2122 } s;
2123 struct cvmx_sli_win_wr_addr_s cn61xx;
2124 struct cvmx_sli_win_wr_addr_s cn63xx;
2125 struct cvmx_sli_win_wr_addr_s cn63xxp1;
2126 struct cvmx_sli_win_wr_addr_s cn66xx;
2127 struct cvmx_sli_win_wr_addr_s cn68xx;
2128 struct cvmx_sli_win_wr_addr_s cn68xxp1;
2129};
2130
2131union cvmx_sli_win_wr_data {
2132 uint64_t u64;
2133 struct cvmx_sli_win_wr_data_s {
2134 uint64_t wr_data:64;
2135 } s;
2136 struct cvmx_sli_win_wr_data_s cn61xx;
2137 struct cvmx_sli_win_wr_data_s cn63xx;
2138 struct cvmx_sli_win_wr_data_s cn63xxp1;
2139 struct cvmx_sli_win_wr_data_s cn66xx;
2140 struct cvmx_sli_win_wr_data_s cn68xx;
2141 struct cvmx_sli_win_wr_data_s cn68xxp1;
2142};
2143
2144union cvmx_sli_win_wr_mask {
2145 uint64_t u64;
2146 struct cvmx_sli_win_wr_mask_s {
2147 uint64_t reserved_8_63:56;
2148 uint64_t wr_mask:8;
2149 } s;
2150 struct cvmx_sli_win_wr_mask_s cn61xx;
2151 struct cvmx_sli_win_wr_mask_s cn63xx;
2152 struct cvmx_sli_win_wr_mask_s cn63xxp1;
2153 struct cvmx_sli_win_wr_mask_s cn66xx;
2154 struct cvmx_sli_win_wr_mask_s cn68xx;
2155 struct cvmx_sli_win_wr_mask_s cn68xxp1;
2156};
2157
2158union cvmx_sli_window_ctl {
2159 uint64_t u64;
2160 struct cvmx_sli_window_ctl_s {
2161 uint64_t reserved_32_63:32;
2162 uint64_t time:32;
2163 } s;
2164 struct cvmx_sli_window_ctl_s cn61xx;
2165 struct cvmx_sli_window_ctl_s cn63xx;
2166 struct cvmx_sli_window_ctl_s cn63xxp1;
2167 struct cvmx_sli_window_ctl_s cn66xx;
2168 struct cvmx_sli_window_ctl_s cn68xx;
2169 struct cvmx_sli_window_ctl_s cn68xxp1;
2170};
2171
2172#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h
new file mode 100644
index 00000000000..e814648953a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spi.h
@@ -0,0 +1,269 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * This file contains defines for the SPI interface
31 */
32#ifndef __CVMX_SPI_H__
33#define __CVMX_SPI_H__
34
35#include "cvmx-gmxx-defs.h"
36
37/* CSR typedefs have been moved to cvmx-csr-*.h */
38
39typedef enum {
40 CVMX_SPI_MODE_UNKNOWN = 0,
41 CVMX_SPI_MODE_TX_HALFPLEX = 1,
42 CVMX_SPI_MODE_RX_HALFPLEX = 2,
43 CVMX_SPI_MODE_DUPLEX = 3
44} cvmx_spi_mode_t;
45
46/** Callbacks structure to customize SPI4 initialization sequence */
47typedef struct {
48 /** Called to reset SPI4 DLL */
49 int (*reset_cb) (int interface, cvmx_spi_mode_t mode);
50
51 /** Called to setup calendar */
52 int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode,
53 int num_ports);
54
55 /** Called for Tx and Rx clock detection */
56 int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode,
57 int timeout);
58
59 /** Called to perform link training */
60 int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout);
61
62 /** Called for calendar data synchronization */
63 int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode,
64 int timeout);
65
66 /** Called when interface is up */
67 int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode);
68
69} cvmx_spi_callbacks_t;
70
71/**
72 * Return true if the supplied interface is configured for SPI
73 *
74 * @interface: Interface to check
75 * Returns True if interface is SPI
76 */
77static inline int cvmx_spi_is_spi_interface(int interface)
78{
79 uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
80 return (gmxState & 0x2) && (gmxState & 0x1);
81}
82
83/**
84 * Initialize and start the SPI interface.
85 *
86 * @interface: The identifier of the packet interface to configure and
87 * use as a SPI interface.
88 * @mode: The operating mode for the SPI interface. The interface
89 * can operate as a full duplex (both Tx and Rx data paths
90 * active) or as a halfplex (either the Tx data path is
91 * active or the Rx data path is active, but not both).
92 * @timeout: Timeout to wait for clock synchronization in seconds
93 * @num_ports: Number of SPI ports to configure
94 *
95 * Returns Zero on success, negative of failure.
96 */
97extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode,
98 int timeout, int num_ports);
99
100/**
101 * This routine restarts the SPI interface after it has lost synchronization
102 * with its corespondant system.
103 *
104 * @interface: The identifier of the packet interface to configure and
105 * use as a SPI interface.
106 * @mode: The operating mode for the SPI interface. The interface
107 * can operate as a full duplex (both Tx and Rx data paths
108 * active) or as a halfplex (either the Tx data path is
109 * active or the Rx data path is active, but not both).
110 * @timeout: Timeout to wait for clock synchronization in seconds
111 * Returns Zero on success, negative of failure.
112 */
113extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode,
114 int timeout);
115
116/**
117 * Return non-zero if the SPI interface has a SPI4000 attached
118 *
119 * @interface: SPI interface the SPI4000 is connected to
120 *
121 * Returns
122 */
123static inline int cvmx_spi4000_is_present(int interface)
124{
125 return 0;
126}
127
128/**
129 * Initialize the SPI4000 for use
130 *
131 * @interface: SPI interface the SPI4000 is connected to
132 */
133static inline int cvmx_spi4000_initialize(int interface)
134{
135 return 0;
136}
137
138/**
139 * Poll all the SPI4000 port and check its speed
140 *
141 * @interface: Interface the SPI4000 is on
142 * @port: Port to poll (0-9)
143 * Returns Status of the port. 0=down. All other values the port is up.
144 */
145static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
146 int interface,
147 int port)
148{
149 union cvmx_gmxx_rxx_rx_inbnd r;
150 r.u64 = 0;
151 return r;
152}
153
154/**
155 * Get current SPI4 initialization callbacks
156 *
157 * @callbacks: Pointer to the callbacks structure.to fill
158 *
159 * Returns Pointer to cvmx_spi_callbacks_t structure.
160 */
161extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks);
162
163/**
164 * Set new SPI4 initialization callbacks
165 *
166 * @new_callbacks: Pointer to an updated callbacks structure.
167 */
168extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks);
169
170/**
171 * Callback to perform SPI4 reset
172 *
173 * @interface: The identifier of the packet interface to configure and
174 * use as a SPI interface.
175 * @mode: The operating mode for the SPI interface. The interface
176 * can operate as a full duplex (both Tx and Rx data paths
177 * active) or as a halfplex (either the Tx data path is
178 * active or the Rx data path is active, but not both).
179 *
180 * Returns Zero on success, non-zero error code on failure (will cause
181 * SPI initialization to abort)
182 */
183extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode);
184
185/**
186 * Callback to setup calendar and miscellaneous settings before clock
187 * detection
188 *
189 * @interface: The identifier of the packet interface to configure and
190 * use as a SPI interface.
191 * @mode: The operating mode for the SPI interface. The interface
192 * can operate as a full duplex (both Tx and Rx data paths
193 * active) or as a halfplex (either the Tx data path is
194 * active or the Rx data path is active, but not both).
195 * @num_ports: Number of ports to configure on SPI
196 *
197 * Returns Zero on success, non-zero error code on failure (will cause
198 * SPI initialization to abort)
199 */
200extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
201 int num_ports);
202
203/**
204 * Callback to perform clock detection
205 *
206 * @interface: The identifier of the packet interface to configure and
207 * use as a SPI interface.
208 * @mode: The operating mode for the SPI interface. The interface
209 * can operate as a full duplex (both Tx and Rx data paths
210 * active) or as a halfplex (either the Tx data path is
211 * active or the Rx data path is active, but not both).
212 * @timeout: Timeout to wait for clock synchronization in seconds
213 *
214 * Returns Zero on success, non-zero error code on failure (will cause
215 * SPI initialization to abort)
216 */
217extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode,
218 int timeout);
219
220/**
221 * Callback to perform link training
222 *
223 * @interface: The identifier of the packet interface to configure and
224 * use as a SPI interface.
225 * @mode: The operating mode for the SPI interface. The interface
226 * can operate as a full duplex (both Tx and Rx data paths
227 * active) or as a halfplex (either the Tx data path is
228 * active or the Rx data path is active, but not both).
229 * @timeout: Timeout to wait for link to be trained (in seconds)
230 *
231 * Returns Zero on success, non-zero error code on failure (will cause
232 * SPI initialization to abort)
233 */
234extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode,
235 int timeout);
236
237/**
238 * Callback to perform calendar data synchronization
239 *
240 * @interface: The identifier of the packet interface to configure and
241 * use as a SPI interface.
242 * @mode: The operating mode for the SPI interface. The interface
243 * can operate as a full duplex (both Tx and Rx data paths
244 * active) or as a halfplex (either the Tx data path is
245 * active or the Rx data path is active, but not both).
246 * @timeout: Timeout to wait for calendar data in seconds
247 *
248 * Returns Zero on success, non-zero error code on failure (will cause
249 * SPI initialization to abort)
250 */
251extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode,
252 int timeout);
253
254/**
255 * Callback to handle interface up
256 *
257 * @interface: The identifier of the packet interface to configure and
258 * use as a SPI interface.
259 * @mode: The operating mode for the SPI interface. The interface
260 * can operate as a full duplex (both Tx and Rx data paths
261 * active) or as a halfplex (either the Tx data path is
262 * active or the Rx data path is active, but not both).
263 *
264 * Returns Zero on success, non-zero error code on failure (will cause
265 * SPI initialization to abort)
266 */
267extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode);
268
269#endif /* __CVMX_SPI_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
new file mode 100644
index 00000000000..b16940e32c8
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
@@ -0,0 +1,347 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SPXX_DEFS_H__
29#define __CVMX_SPXX_DEFS_H__
30
31#define CVMX_SPXX_BCKPRS_CNT(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_SPXX_BIST_STAT(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_SPXX_CLK_CTL(block_id) \
36 CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_SPXX_CLK_STAT(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \
40 CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \
42 CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_SPXX_DRV_CTL(block_id) \
44 CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_SPXX_ERR_CTL(block_id) \
46 CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_SPXX_INT_DAT(block_id) \
48 CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_SPXX_INT_MSK(block_id) \
50 CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_SPXX_INT_REG(block_id) \
52 CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_SPXX_INT_SYNC(block_id) \
54 CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_SPXX_TPA_ACC(block_id) \
56 CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_SPXX_TPA_MAX(block_id) \
58 CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_SPXX_TPA_SEL(block_id) \
60 CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_SPXX_TRN4_CTL(block_id) \
62 CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull))
63
64union cvmx_spxx_bckprs_cnt {
65 uint64_t u64;
66 struct cvmx_spxx_bckprs_cnt_s {
67 uint64_t reserved_32_63:32;
68 uint64_t cnt:32;
69 } s;
70 struct cvmx_spxx_bckprs_cnt_s cn38xx;
71 struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
72 struct cvmx_spxx_bckprs_cnt_s cn58xx;
73 struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
74};
75
76union cvmx_spxx_bist_stat {
77 uint64_t u64;
78 struct cvmx_spxx_bist_stat_s {
79 uint64_t reserved_3_63:61;
80 uint64_t stat2:1;
81 uint64_t stat1:1;
82 uint64_t stat0:1;
83 } s;
84 struct cvmx_spxx_bist_stat_s cn38xx;
85 struct cvmx_spxx_bist_stat_s cn38xxp2;
86 struct cvmx_spxx_bist_stat_s cn58xx;
87 struct cvmx_spxx_bist_stat_s cn58xxp1;
88};
89
90union cvmx_spxx_clk_ctl {
91 uint64_t u64;
92 struct cvmx_spxx_clk_ctl_s {
93 uint64_t reserved_17_63:47;
94 uint64_t seetrn:1;
95 uint64_t reserved_12_15:4;
96 uint64_t clkdly:5;
97 uint64_t runbist:1;
98 uint64_t statdrv:1;
99 uint64_t statrcv:1;
100 uint64_t sndtrn:1;
101 uint64_t drptrn:1;
102 uint64_t rcvtrn:1;
103 uint64_t srxdlck:1;
104 } s;
105 struct cvmx_spxx_clk_ctl_s cn38xx;
106 struct cvmx_spxx_clk_ctl_s cn38xxp2;
107 struct cvmx_spxx_clk_ctl_s cn58xx;
108 struct cvmx_spxx_clk_ctl_s cn58xxp1;
109};
110
111union cvmx_spxx_clk_stat {
112 uint64_t u64;
113 struct cvmx_spxx_clk_stat_s {
114 uint64_t reserved_11_63:53;
115 uint64_t stxcal:1;
116 uint64_t reserved_9_9:1;
117 uint64_t srxtrn:1;
118 uint64_t s4clk1:1;
119 uint64_t s4clk0:1;
120 uint64_t d4clk1:1;
121 uint64_t d4clk0:1;
122 uint64_t reserved_0_3:4;
123 } s;
124 struct cvmx_spxx_clk_stat_s cn38xx;
125 struct cvmx_spxx_clk_stat_s cn38xxp2;
126 struct cvmx_spxx_clk_stat_s cn58xx;
127 struct cvmx_spxx_clk_stat_s cn58xxp1;
128};
129
130union cvmx_spxx_dbg_deskew_ctl {
131 uint64_t u64;
132 struct cvmx_spxx_dbg_deskew_ctl_s {
133 uint64_t reserved_30_63:34;
134 uint64_t fallnop:1;
135 uint64_t fall8:1;
136 uint64_t reserved_26_27:2;
137 uint64_t sstep_go:1;
138 uint64_t sstep:1;
139 uint64_t reserved_22_23:2;
140 uint64_t clrdly:1;
141 uint64_t dec:1;
142 uint64_t inc:1;
143 uint64_t mux:1;
144 uint64_t offset:5;
145 uint64_t bitsel:5;
146 uint64_t offdly:6;
147 uint64_t dllfrc:1;
148 uint64_t dlldis:1;
149 } s;
150 struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
151 struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
152 struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
153 struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
154};
155
156union cvmx_spxx_dbg_deskew_state {
157 uint64_t u64;
158 struct cvmx_spxx_dbg_deskew_state_s {
159 uint64_t reserved_9_63:55;
160 uint64_t testres:1;
161 uint64_t unxterm:1;
162 uint64_t muxsel:2;
163 uint64_t offset:5;
164 } s;
165 struct cvmx_spxx_dbg_deskew_state_s cn38xx;
166 struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
167 struct cvmx_spxx_dbg_deskew_state_s cn58xx;
168 struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
169};
170
171union cvmx_spxx_drv_ctl {
172 uint64_t u64;
173 struct cvmx_spxx_drv_ctl_s {
174 uint64_t reserved_0_63:64;
175 } s;
176 struct cvmx_spxx_drv_ctl_cn38xx {
177 uint64_t reserved_16_63:48;
178 uint64_t stx4ncmp:4;
179 uint64_t stx4pcmp:4;
180 uint64_t srx4cmp:8;
181 } cn38xx;
182 struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
183 struct cvmx_spxx_drv_ctl_cn58xx {
184 uint64_t reserved_24_63:40;
185 uint64_t stx4ncmp:4;
186 uint64_t stx4pcmp:4;
187 uint64_t reserved_10_15:6;
188 uint64_t srx4cmp:10;
189 } cn58xx;
190 struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
191};
192
193union cvmx_spxx_err_ctl {
194 uint64_t u64;
195 struct cvmx_spxx_err_ctl_s {
196 uint64_t reserved_9_63:55;
197 uint64_t prtnxa:1;
198 uint64_t dipcls:1;
199 uint64_t dippay:1;
200 uint64_t reserved_4_5:2;
201 uint64_t errcnt:4;
202 } s;
203 struct cvmx_spxx_err_ctl_s cn38xx;
204 struct cvmx_spxx_err_ctl_s cn38xxp2;
205 struct cvmx_spxx_err_ctl_s cn58xx;
206 struct cvmx_spxx_err_ctl_s cn58xxp1;
207};
208
209union cvmx_spxx_int_dat {
210 uint64_t u64;
211 struct cvmx_spxx_int_dat_s {
212 uint64_t reserved_32_63:32;
213 uint64_t mul:1;
214 uint64_t reserved_14_30:17;
215 uint64_t calbnk:2;
216 uint64_t rsvop:4;
217 uint64_t prt:8;
218 } s;
219 struct cvmx_spxx_int_dat_s cn38xx;
220 struct cvmx_spxx_int_dat_s cn38xxp2;
221 struct cvmx_spxx_int_dat_s cn58xx;
222 struct cvmx_spxx_int_dat_s cn58xxp1;
223};
224
225union cvmx_spxx_int_msk {
226 uint64_t u64;
227 struct cvmx_spxx_int_msk_s {
228 uint64_t reserved_12_63:52;
229 uint64_t calerr:1;
230 uint64_t syncerr:1;
231 uint64_t diperr:1;
232 uint64_t tpaovr:1;
233 uint64_t rsverr:1;
234 uint64_t drwnng:1;
235 uint64_t clserr:1;
236 uint64_t spiovr:1;
237 uint64_t reserved_2_3:2;
238 uint64_t abnorm:1;
239 uint64_t prtnxa:1;
240 } s;
241 struct cvmx_spxx_int_msk_s cn38xx;
242 struct cvmx_spxx_int_msk_s cn38xxp2;
243 struct cvmx_spxx_int_msk_s cn58xx;
244 struct cvmx_spxx_int_msk_s cn58xxp1;
245};
246
247union cvmx_spxx_int_reg {
248 uint64_t u64;
249 struct cvmx_spxx_int_reg_s {
250 uint64_t reserved_32_63:32;
251 uint64_t spf:1;
252 uint64_t reserved_12_30:19;
253 uint64_t calerr:1;
254 uint64_t syncerr:1;
255 uint64_t diperr:1;
256 uint64_t tpaovr:1;
257 uint64_t rsverr:1;
258 uint64_t drwnng:1;
259 uint64_t clserr:1;
260 uint64_t spiovr:1;
261 uint64_t reserved_2_3:2;
262 uint64_t abnorm:1;
263 uint64_t prtnxa:1;
264 } s;
265 struct cvmx_spxx_int_reg_s cn38xx;
266 struct cvmx_spxx_int_reg_s cn38xxp2;
267 struct cvmx_spxx_int_reg_s cn58xx;
268 struct cvmx_spxx_int_reg_s cn58xxp1;
269};
270
271union cvmx_spxx_int_sync {
272 uint64_t u64;
273 struct cvmx_spxx_int_sync_s {
274 uint64_t reserved_12_63:52;
275 uint64_t calerr:1;
276 uint64_t syncerr:1;
277 uint64_t diperr:1;
278 uint64_t tpaovr:1;
279 uint64_t rsverr:1;
280 uint64_t drwnng:1;
281 uint64_t clserr:1;
282 uint64_t spiovr:1;
283 uint64_t reserved_2_3:2;
284 uint64_t abnorm:1;
285 uint64_t prtnxa:1;
286 } s;
287 struct cvmx_spxx_int_sync_s cn38xx;
288 struct cvmx_spxx_int_sync_s cn38xxp2;
289 struct cvmx_spxx_int_sync_s cn58xx;
290 struct cvmx_spxx_int_sync_s cn58xxp1;
291};
292
293union cvmx_spxx_tpa_acc {
294 uint64_t u64;
295 struct cvmx_spxx_tpa_acc_s {
296 uint64_t reserved_32_63:32;
297 uint64_t cnt:32;
298 } s;
299 struct cvmx_spxx_tpa_acc_s cn38xx;
300 struct cvmx_spxx_tpa_acc_s cn38xxp2;
301 struct cvmx_spxx_tpa_acc_s cn58xx;
302 struct cvmx_spxx_tpa_acc_s cn58xxp1;
303};
304
305union cvmx_spxx_tpa_max {
306 uint64_t u64;
307 struct cvmx_spxx_tpa_max_s {
308 uint64_t reserved_32_63:32;
309 uint64_t max:32;
310 } s;
311 struct cvmx_spxx_tpa_max_s cn38xx;
312 struct cvmx_spxx_tpa_max_s cn38xxp2;
313 struct cvmx_spxx_tpa_max_s cn58xx;
314 struct cvmx_spxx_tpa_max_s cn58xxp1;
315};
316
317union cvmx_spxx_tpa_sel {
318 uint64_t u64;
319 struct cvmx_spxx_tpa_sel_s {
320 uint64_t reserved_4_63:60;
321 uint64_t prtsel:4;
322 } s;
323 struct cvmx_spxx_tpa_sel_s cn38xx;
324 struct cvmx_spxx_tpa_sel_s cn38xxp2;
325 struct cvmx_spxx_tpa_sel_s cn58xx;
326 struct cvmx_spxx_tpa_sel_s cn58xxp1;
327};
328
329union cvmx_spxx_trn4_ctl {
330 uint64_t u64;
331 struct cvmx_spxx_trn4_ctl_s {
332 uint64_t reserved_13_63:51;
333 uint64_t trntest:1;
334 uint64_t jitter:3;
335 uint64_t clr_boot:1;
336 uint64_t set_boot:1;
337 uint64_t maxdist:5;
338 uint64_t macro_en:1;
339 uint64_t mux_en:1;
340 } s;
341 struct cvmx_spxx_trn4_ctl_s cn38xx;
342 struct cvmx_spxx_trn4_ctl_s cn38xxp2;
343 struct cvmx_spxx_trn4_ctl_s cn58xx;
344 struct cvmx_spxx_trn4_ctl_s cn58xxp1;
345};
346
347#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
new file mode 100644
index 00000000000..7be7e9ed746
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -0,0 +1,1036 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SRIOX_DEFS_H__
29#define __CVMX_SRIOX_DEFS_H__
30
31#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
32#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
33#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
34#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
35#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
36#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
37#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
38#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
39#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
40#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
41#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
42#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
43#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
44#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
45#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
46#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
47#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
48#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
49#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
50#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
51#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
52#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
53#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
54#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
55#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
56#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
57#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
58#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
59#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
60#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
61#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
62#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
63#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
64#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
65#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
66#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
67#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
68#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
69#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
70#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
71#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
72#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
73#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
74#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
75#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
76#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
77#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
78
79union cvmx_sriox_acc_ctrl {
80 uint64_t u64;
81 struct cvmx_sriox_acc_ctrl_s {
82 uint64_t reserved_7_63:57;
83 uint64_t deny_adr2:1;
84 uint64_t deny_adr1:1;
85 uint64_t deny_adr0:1;
86 uint64_t reserved_3_3:1;
87 uint64_t deny_bar2:1;
88 uint64_t deny_bar1:1;
89 uint64_t deny_bar0:1;
90 } s;
91 struct cvmx_sriox_acc_ctrl_cn63xx {
92 uint64_t reserved_3_63:61;
93 uint64_t deny_bar2:1;
94 uint64_t deny_bar1:1;
95 uint64_t deny_bar0:1;
96 } cn63xx;
97 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
98 struct cvmx_sriox_acc_ctrl_s cn66xx;
99};
100
101union cvmx_sriox_asmbly_id {
102 uint64_t u64;
103 struct cvmx_sriox_asmbly_id_s {
104 uint64_t reserved_32_63:32;
105 uint64_t assy_id:16;
106 uint64_t assy_ven:16;
107 } s;
108 struct cvmx_sriox_asmbly_id_s cn63xx;
109 struct cvmx_sriox_asmbly_id_s cn63xxp1;
110 struct cvmx_sriox_asmbly_id_s cn66xx;
111};
112
113union cvmx_sriox_asmbly_info {
114 uint64_t u64;
115 struct cvmx_sriox_asmbly_info_s {
116 uint64_t reserved_32_63:32;
117 uint64_t assy_rev:16;
118 uint64_t reserved_0_15:16;
119 } s;
120 struct cvmx_sriox_asmbly_info_s cn63xx;
121 struct cvmx_sriox_asmbly_info_s cn63xxp1;
122 struct cvmx_sriox_asmbly_info_s cn66xx;
123};
124
125union cvmx_sriox_bell_resp_ctrl {
126 uint64_t u64;
127 struct cvmx_sriox_bell_resp_ctrl_s {
128 uint64_t reserved_6_63:58;
129 uint64_t rp1_sid:1;
130 uint64_t rp0_sid:2;
131 uint64_t rp1_pid:1;
132 uint64_t rp0_pid:2;
133 } s;
134 struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
135 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
136 struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
137};
138
139union cvmx_sriox_bist_status {
140 uint64_t u64;
141 struct cvmx_sriox_bist_status_s {
142 uint64_t reserved_45_63:19;
143 uint64_t lram:1;
144 uint64_t mram:2;
145 uint64_t cram:2;
146 uint64_t bell:2;
147 uint64_t otag:2;
148 uint64_t itag:1;
149 uint64_t ofree:1;
150 uint64_t rtn:2;
151 uint64_t obulk:4;
152 uint64_t optrs:4;
153 uint64_t oarb2:2;
154 uint64_t rxbuf2:2;
155 uint64_t oarb:2;
156 uint64_t ispf:1;
157 uint64_t ospf:1;
158 uint64_t txbuf:2;
159 uint64_t rxbuf:2;
160 uint64_t imsg:5;
161 uint64_t omsg:7;
162 } s;
163 struct cvmx_sriox_bist_status_cn63xx {
164 uint64_t reserved_44_63:20;
165 uint64_t mram:2;
166 uint64_t cram:2;
167 uint64_t bell:2;
168 uint64_t otag:2;
169 uint64_t itag:1;
170 uint64_t ofree:1;
171 uint64_t rtn:2;
172 uint64_t obulk:4;
173 uint64_t optrs:4;
174 uint64_t oarb2:2;
175 uint64_t rxbuf2:2;
176 uint64_t oarb:2;
177 uint64_t ispf:1;
178 uint64_t ospf:1;
179 uint64_t txbuf:2;
180 uint64_t rxbuf:2;
181 uint64_t imsg:5;
182 uint64_t omsg:7;
183 } cn63xx;
184 struct cvmx_sriox_bist_status_cn63xxp1 {
185 uint64_t reserved_44_63:20;
186 uint64_t mram:2;
187 uint64_t cram:2;
188 uint64_t bell:2;
189 uint64_t otag:2;
190 uint64_t itag:1;
191 uint64_t ofree:1;
192 uint64_t rtn:2;
193 uint64_t obulk:4;
194 uint64_t optrs:4;
195 uint64_t reserved_20_23:4;
196 uint64_t oarb:2;
197 uint64_t ispf:1;
198 uint64_t ospf:1;
199 uint64_t txbuf:2;
200 uint64_t rxbuf:2;
201 uint64_t imsg:5;
202 uint64_t omsg:7;
203 } cn63xxp1;
204 struct cvmx_sriox_bist_status_s cn66xx;
205};
206
207union cvmx_sriox_imsg_ctrl {
208 uint64_t u64;
209 struct cvmx_sriox_imsg_ctrl_s {
210 uint64_t reserved_32_63:32;
211 uint64_t to_mode:1;
212 uint64_t reserved_30_30:1;
213 uint64_t rsp_thr:6;
214 uint64_t reserved_22_23:2;
215 uint64_t rp1_sid:1;
216 uint64_t rp0_sid:2;
217 uint64_t rp1_pid:1;
218 uint64_t rp0_pid:2;
219 uint64_t reserved_15_15:1;
220 uint64_t prt_sel:3;
221 uint64_t lttr:4;
222 uint64_t prio:4;
223 uint64_t mbox:4;
224 } s;
225 struct cvmx_sriox_imsg_ctrl_s cn63xx;
226 struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
227 struct cvmx_sriox_imsg_ctrl_s cn66xx;
228};
229
230union cvmx_sriox_imsg_inst_hdrx {
231 uint64_t u64;
232 struct cvmx_sriox_imsg_inst_hdrx_s {
233 uint64_t r:1;
234 uint64_t reserved_58_62:5;
235 uint64_t pm:2;
236 uint64_t reserved_55_55:1;
237 uint64_t sl:7;
238 uint64_t reserved_46_47:2;
239 uint64_t nqos:1;
240 uint64_t ngrp:1;
241 uint64_t ntt:1;
242 uint64_t ntag:1;
243 uint64_t reserved_35_41:7;
244 uint64_t rs:1;
245 uint64_t tt:2;
246 uint64_t tag:32;
247 } s;
248 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
249 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
250 struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
251};
252
253union cvmx_sriox_imsg_qos_grpx {
254 uint64_t u64;
255 struct cvmx_sriox_imsg_qos_grpx_s {
256 uint64_t reserved_63_63:1;
257 uint64_t qos7:3;
258 uint64_t grp7:4;
259 uint64_t reserved_55_55:1;
260 uint64_t qos6:3;
261 uint64_t grp6:4;
262 uint64_t reserved_47_47:1;
263 uint64_t qos5:3;
264 uint64_t grp5:4;
265 uint64_t reserved_39_39:1;
266 uint64_t qos4:3;
267 uint64_t grp4:4;
268 uint64_t reserved_31_31:1;
269 uint64_t qos3:3;
270 uint64_t grp3:4;
271 uint64_t reserved_23_23:1;
272 uint64_t qos2:3;
273 uint64_t grp2:4;
274 uint64_t reserved_15_15:1;
275 uint64_t qos1:3;
276 uint64_t grp1:4;
277 uint64_t reserved_7_7:1;
278 uint64_t qos0:3;
279 uint64_t grp0:4;
280 } s;
281 struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
282 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
283 struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
284};
285
286union cvmx_sriox_imsg_statusx {
287 uint64_t u64;
288 struct cvmx_sriox_imsg_statusx_s {
289 uint64_t val1:1;
290 uint64_t err1:1;
291 uint64_t toe1:1;
292 uint64_t toc1:1;
293 uint64_t prt1:1;
294 uint64_t reserved_58_58:1;
295 uint64_t tt1:1;
296 uint64_t dis1:1;
297 uint64_t seg1:4;
298 uint64_t mbox1:2;
299 uint64_t lttr1:2;
300 uint64_t sid1:16;
301 uint64_t val0:1;
302 uint64_t err0:1;
303 uint64_t toe0:1;
304 uint64_t toc0:1;
305 uint64_t prt0:1;
306 uint64_t reserved_26_26:1;
307 uint64_t tt0:1;
308 uint64_t dis0:1;
309 uint64_t seg0:4;
310 uint64_t mbox0:2;
311 uint64_t lttr0:2;
312 uint64_t sid0:16;
313 } s;
314 struct cvmx_sriox_imsg_statusx_s cn63xx;
315 struct cvmx_sriox_imsg_statusx_s cn63xxp1;
316 struct cvmx_sriox_imsg_statusx_s cn66xx;
317};
318
319union cvmx_sriox_imsg_vport_thr {
320 uint64_t u64;
321 struct cvmx_sriox_imsg_vport_thr_s {
322 uint64_t reserved_54_63:10;
323 uint64_t max_tot:6;
324 uint64_t reserved_46_47:2;
325 uint64_t max_s1:6;
326 uint64_t reserved_38_39:2;
327 uint64_t max_s0:6;
328 uint64_t sp_vport:1;
329 uint64_t reserved_20_30:11;
330 uint64_t buf_thr:4;
331 uint64_t reserved_14_15:2;
332 uint64_t max_p1:6;
333 uint64_t reserved_6_7:2;
334 uint64_t max_p0:6;
335 } s;
336 struct cvmx_sriox_imsg_vport_thr_s cn63xx;
337 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
338 struct cvmx_sriox_imsg_vport_thr_s cn66xx;
339};
340
341union cvmx_sriox_imsg_vport_thr2 {
342 uint64_t u64;
343 struct cvmx_sriox_imsg_vport_thr2_s {
344 uint64_t reserved_46_63:18;
345 uint64_t max_s3:6;
346 uint64_t reserved_38_39:2;
347 uint64_t max_s2:6;
348 uint64_t reserved_0_31:32;
349 } s;
350 struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
351};
352
353union cvmx_sriox_int2_enable {
354 uint64_t u64;
355 struct cvmx_sriox_int2_enable_s {
356 uint64_t reserved_1_63:63;
357 uint64_t pko_rst:1;
358 } s;
359 struct cvmx_sriox_int2_enable_s cn63xx;
360 struct cvmx_sriox_int2_enable_s cn66xx;
361};
362
363union cvmx_sriox_int2_reg {
364 uint64_t u64;
365 struct cvmx_sriox_int2_reg_s {
366 uint64_t reserved_32_63:32;
367 uint64_t int_sum:1;
368 uint64_t reserved_1_30:30;
369 uint64_t pko_rst:1;
370 } s;
371 struct cvmx_sriox_int2_reg_s cn63xx;
372 struct cvmx_sriox_int2_reg_s cn66xx;
373};
374
375union cvmx_sriox_int_enable {
376 uint64_t u64;
377 struct cvmx_sriox_int_enable_s {
378 uint64_t reserved_27_63:37;
379 uint64_t zero_pkt:1;
380 uint64_t ttl_tout:1;
381 uint64_t fail:1;
382 uint64_t degrade:1;
383 uint64_t mac_buf:1;
384 uint64_t f_error:1;
385 uint64_t rtry_err:1;
386 uint64_t pko_err:1;
387 uint64_t omsg_err:1;
388 uint64_t omsg1:1;
389 uint64_t omsg0:1;
390 uint64_t link_up:1;
391 uint64_t link_dwn:1;
392 uint64_t phy_erb:1;
393 uint64_t log_erb:1;
394 uint64_t soft_rx:1;
395 uint64_t soft_tx:1;
396 uint64_t mce_rx:1;
397 uint64_t mce_tx:1;
398 uint64_t wr_done:1;
399 uint64_t sli_err:1;
400 uint64_t deny_wr:1;
401 uint64_t bar_err:1;
402 uint64_t maint_op:1;
403 uint64_t rxbell:1;
404 uint64_t bell_err:1;
405 uint64_t txbell:1;
406 } s;
407 struct cvmx_sriox_int_enable_s cn63xx;
408 struct cvmx_sriox_int_enable_cn63xxp1 {
409 uint64_t reserved_22_63:42;
410 uint64_t f_error:1;
411 uint64_t rtry_err:1;
412 uint64_t pko_err:1;
413 uint64_t omsg_err:1;
414 uint64_t omsg1:1;
415 uint64_t omsg0:1;
416 uint64_t link_up:1;
417 uint64_t link_dwn:1;
418 uint64_t phy_erb:1;
419 uint64_t log_erb:1;
420 uint64_t soft_rx:1;
421 uint64_t soft_tx:1;
422 uint64_t mce_rx:1;
423 uint64_t mce_tx:1;
424 uint64_t wr_done:1;
425 uint64_t sli_err:1;
426 uint64_t deny_wr:1;
427 uint64_t bar_err:1;
428 uint64_t maint_op:1;
429 uint64_t rxbell:1;
430 uint64_t bell_err:1;
431 uint64_t txbell:1;
432 } cn63xxp1;
433 struct cvmx_sriox_int_enable_s cn66xx;
434};
435
436union cvmx_sriox_int_info0 {
437 uint64_t u64;
438 struct cvmx_sriox_int_info0_s {
439 uint64_t cmd:4;
440 uint64_t type:4;
441 uint64_t tag:8;
442 uint64_t reserved_42_47:6;
443 uint64_t length:10;
444 uint64_t status:3;
445 uint64_t reserved_16_28:13;
446 uint64_t be0:8;
447 uint64_t be1:8;
448 } s;
449 struct cvmx_sriox_int_info0_s cn63xx;
450 struct cvmx_sriox_int_info0_s cn63xxp1;
451 struct cvmx_sriox_int_info0_s cn66xx;
452};
453
454union cvmx_sriox_int_info1 {
455 uint64_t u64;
456 struct cvmx_sriox_int_info1_s {
457 uint64_t info1:64;
458 } s;
459 struct cvmx_sriox_int_info1_s cn63xx;
460 struct cvmx_sriox_int_info1_s cn63xxp1;
461 struct cvmx_sriox_int_info1_s cn66xx;
462};
463
464union cvmx_sriox_int_info2 {
465 uint64_t u64;
466 struct cvmx_sriox_int_info2_s {
467 uint64_t prio:2;
468 uint64_t tt:1;
469 uint64_t sis:1;
470 uint64_t ssize:4;
471 uint64_t did:16;
472 uint64_t xmbox:4;
473 uint64_t mbox:2;
474 uint64_t letter:2;
475 uint64_t rsrvd:30;
476 uint64_t lns:1;
477 uint64_t intr:1;
478 } s;
479 struct cvmx_sriox_int_info2_s cn63xx;
480 struct cvmx_sriox_int_info2_s cn63xxp1;
481 struct cvmx_sriox_int_info2_s cn66xx;
482};
483
484union cvmx_sriox_int_info3 {
485 uint64_t u64;
486 struct cvmx_sriox_int_info3_s {
487 uint64_t prio:2;
488 uint64_t tt:2;
489 uint64_t type:4;
490 uint64_t other:48;
491 uint64_t reserved_0_7:8;
492 } s;
493 struct cvmx_sriox_int_info3_s cn63xx;
494 struct cvmx_sriox_int_info3_s cn63xxp1;
495 struct cvmx_sriox_int_info3_s cn66xx;
496};
497
498union cvmx_sriox_int_reg {
499 uint64_t u64;
500 struct cvmx_sriox_int_reg_s {
501 uint64_t reserved_32_63:32;
502 uint64_t int2_sum:1;
503 uint64_t reserved_27_30:4;
504 uint64_t zero_pkt:1;
505 uint64_t ttl_tout:1;
506 uint64_t fail:1;
507 uint64_t degrad:1;
508 uint64_t mac_buf:1;
509 uint64_t f_error:1;
510 uint64_t rtry_err:1;
511 uint64_t pko_err:1;
512 uint64_t omsg_err:1;
513 uint64_t omsg1:1;
514 uint64_t omsg0:1;
515 uint64_t link_up:1;
516 uint64_t link_dwn:1;
517 uint64_t phy_erb:1;
518 uint64_t log_erb:1;
519 uint64_t soft_rx:1;
520 uint64_t soft_tx:1;
521 uint64_t mce_rx:1;
522 uint64_t mce_tx:1;
523 uint64_t wr_done:1;
524 uint64_t sli_err:1;
525 uint64_t deny_wr:1;
526 uint64_t bar_err:1;
527 uint64_t maint_op:1;
528 uint64_t rxbell:1;
529 uint64_t bell_err:1;
530 uint64_t txbell:1;
531 } s;
532 struct cvmx_sriox_int_reg_s cn63xx;
533 struct cvmx_sriox_int_reg_cn63xxp1 {
534 uint64_t reserved_22_63:42;
535 uint64_t f_error:1;
536 uint64_t rtry_err:1;
537 uint64_t pko_err:1;
538 uint64_t omsg_err:1;
539 uint64_t omsg1:1;
540 uint64_t omsg0:1;
541 uint64_t link_up:1;
542 uint64_t link_dwn:1;
543 uint64_t phy_erb:1;
544 uint64_t log_erb:1;
545 uint64_t soft_rx:1;
546 uint64_t soft_tx:1;
547 uint64_t mce_rx:1;
548 uint64_t mce_tx:1;
549 uint64_t wr_done:1;
550 uint64_t sli_err:1;
551 uint64_t deny_wr:1;
552 uint64_t bar_err:1;
553 uint64_t maint_op:1;
554 uint64_t rxbell:1;
555 uint64_t bell_err:1;
556 uint64_t txbell:1;
557 } cn63xxp1;
558 struct cvmx_sriox_int_reg_s cn66xx;
559};
560
561union cvmx_sriox_ip_feature {
562 uint64_t u64;
563 struct cvmx_sriox_ip_feature_s {
564 uint64_t ops:32;
565 uint64_t reserved_15_31:17;
566 uint64_t no_vmin:1;
567 uint64_t a66:1;
568 uint64_t a50:1;
569 uint64_t reserved_11_11:1;
570 uint64_t tx_flow:1;
571 uint64_t pt_width:2;
572 uint64_t tx_pol:4;
573 uint64_t rx_pol:4;
574 } s;
575 struct cvmx_sriox_ip_feature_cn63xx {
576 uint64_t ops:32;
577 uint64_t reserved_14_31:18;
578 uint64_t a66:1;
579 uint64_t a50:1;
580 uint64_t reserved_11_11:1;
581 uint64_t tx_flow:1;
582 uint64_t pt_width:2;
583 uint64_t tx_pol:4;
584 uint64_t rx_pol:4;
585 } cn63xx;
586 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
587 struct cvmx_sriox_ip_feature_s cn66xx;
588};
589
590union cvmx_sriox_mac_buffers {
591 uint64_t u64;
592 struct cvmx_sriox_mac_buffers_s {
593 uint64_t reserved_56_63:8;
594 uint64_t tx_enb:8;
595 uint64_t reserved_44_47:4;
596 uint64_t tx_inuse:4;
597 uint64_t tx_stat:8;
598 uint64_t reserved_24_31:8;
599 uint64_t rx_enb:8;
600 uint64_t reserved_12_15:4;
601 uint64_t rx_inuse:4;
602 uint64_t rx_stat:8;
603 } s;
604 struct cvmx_sriox_mac_buffers_s cn63xx;
605 struct cvmx_sriox_mac_buffers_s cn66xx;
606};
607
608union cvmx_sriox_maint_op {
609 uint64_t u64;
610 struct cvmx_sriox_maint_op_s {
611 uint64_t wr_data:32;
612 uint64_t reserved_27_31:5;
613 uint64_t fail:1;
614 uint64_t pending:1;
615 uint64_t op:1;
616 uint64_t addr:24;
617 } s;
618 struct cvmx_sriox_maint_op_s cn63xx;
619 struct cvmx_sriox_maint_op_s cn63xxp1;
620 struct cvmx_sriox_maint_op_s cn66xx;
621};
622
623union cvmx_sriox_maint_rd_data {
624 uint64_t u64;
625 struct cvmx_sriox_maint_rd_data_s {
626 uint64_t reserved_33_63:31;
627 uint64_t valid:1;
628 uint64_t rd_data:32;
629 } s;
630 struct cvmx_sriox_maint_rd_data_s cn63xx;
631 struct cvmx_sriox_maint_rd_data_s cn63xxp1;
632 struct cvmx_sriox_maint_rd_data_s cn66xx;
633};
634
635union cvmx_sriox_mce_tx_ctl {
636 uint64_t u64;
637 struct cvmx_sriox_mce_tx_ctl_s {
638 uint64_t reserved_1_63:63;
639 uint64_t mce:1;
640 } s;
641 struct cvmx_sriox_mce_tx_ctl_s cn63xx;
642 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
643 struct cvmx_sriox_mce_tx_ctl_s cn66xx;
644};
645
646union cvmx_sriox_mem_op_ctrl {
647 uint64_t u64;
648 struct cvmx_sriox_mem_op_ctrl_s {
649 uint64_t reserved_10_63:54;
650 uint64_t rr_ro:1;
651 uint64_t w_ro:1;
652 uint64_t reserved_6_7:2;
653 uint64_t rp1_sid:1;
654 uint64_t rp0_sid:2;
655 uint64_t rp1_pid:1;
656 uint64_t rp0_pid:2;
657 } s;
658 struct cvmx_sriox_mem_op_ctrl_s cn63xx;
659 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
660 struct cvmx_sriox_mem_op_ctrl_s cn66xx;
661};
662
663union cvmx_sriox_omsg_ctrlx {
664 uint64_t u64;
665 struct cvmx_sriox_omsg_ctrlx_s {
666 uint64_t testmode:1;
667 uint64_t reserved_37_62:26;
668 uint64_t silo_max:5;
669 uint64_t rtry_thr:16;
670 uint64_t rtry_en:1;
671 uint64_t reserved_11_14:4;
672 uint64_t idm_tt:1;
673 uint64_t idm_sis:1;
674 uint64_t idm_did:1;
675 uint64_t lttr_sp:4;
676 uint64_t lttr_mp:4;
677 } s;
678 struct cvmx_sriox_omsg_ctrlx_s cn63xx;
679 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
680 uint64_t testmode:1;
681 uint64_t reserved_32_62:31;
682 uint64_t rtry_thr:16;
683 uint64_t rtry_en:1;
684 uint64_t reserved_11_14:4;
685 uint64_t idm_tt:1;
686 uint64_t idm_sis:1;
687 uint64_t idm_did:1;
688 uint64_t lttr_sp:4;
689 uint64_t lttr_mp:4;
690 } cn63xxp1;
691 struct cvmx_sriox_omsg_ctrlx_s cn66xx;
692};
693
694union cvmx_sriox_omsg_done_countsx {
695 uint64_t u64;
696 struct cvmx_sriox_omsg_done_countsx_s {
697 uint64_t reserved_32_63:32;
698 uint64_t bad:16;
699 uint64_t good:16;
700 } s;
701 struct cvmx_sriox_omsg_done_countsx_s cn63xx;
702 struct cvmx_sriox_omsg_done_countsx_s cn66xx;
703};
704
705union cvmx_sriox_omsg_fmp_mrx {
706 uint64_t u64;
707 struct cvmx_sriox_omsg_fmp_mrx_s {
708 uint64_t reserved_15_63:49;
709 uint64_t ctlr_sp:1;
710 uint64_t ctlr_fmp:1;
711 uint64_t ctlr_nmp:1;
712 uint64_t id_sp:1;
713 uint64_t id_fmp:1;
714 uint64_t id_nmp:1;
715 uint64_t id_psd:1;
716 uint64_t mbox_sp:1;
717 uint64_t mbox_fmp:1;
718 uint64_t mbox_nmp:1;
719 uint64_t mbox_psd:1;
720 uint64_t all_sp:1;
721 uint64_t all_fmp:1;
722 uint64_t all_nmp:1;
723 uint64_t all_psd:1;
724 } s;
725 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
726 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
727 struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
728};
729
730union cvmx_sriox_omsg_nmp_mrx {
731 uint64_t u64;
732 struct cvmx_sriox_omsg_nmp_mrx_s {
733 uint64_t reserved_15_63:49;
734 uint64_t ctlr_sp:1;
735 uint64_t ctlr_fmp:1;
736 uint64_t ctlr_nmp:1;
737 uint64_t id_sp:1;
738 uint64_t id_fmp:1;
739 uint64_t id_nmp:1;
740 uint64_t reserved_8_8:1;
741 uint64_t mbox_sp:1;
742 uint64_t mbox_fmp:1;
743 uint64_t mbox_nmp:1;
744 uint64_t reserved_4_4:1;
745 uint64_t all_sp:1;
746 uint64_t all_fmp:1;
747 uint64_t all_nmp:1;
748 uint64_t reserved_0_0:1;
749 } s;
750 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
751 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
752 struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
753};
754
755union cvmx_sriox_omsg_portx {
756 uint64_t u64;
757 struct cvmx_sriox_omsg_portx_s {
758 uint64_t reserved_32_63:32;
759 uint64_t enable:1;
760 uint64_t reserved_3_30:28;
761 uint64_t port:3;
762 } s;
763 struct cvmx_sriox_omsg_portx_cn63xx {
764 uint64_t reserved_32_63:32;
765 uint64_t enable:1;
766 uint64_t reserved_2_30:29;
767 uint64_t port:2;
768 } cn63xx;
769 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
770 struct cvmx_sriox_omsg_portx_s cn66xx;
771};
772
773union cvmx_sriox_omsg_silo_thr {
774 uint64_t u64;
775 struct cvmx_sriox_omsg_silo_thr_s {
776 uint64_t reserved_5_63:59;
777 uint64_t tot_silo:5;
778 } s;
779 struct cvmx_sriox_omsg_silo_thr_s cn63xx;
780 struct cvmx_sriox_omsg_silo_thr_s cn66xx;
781};
782
783union cvmx_sriox_omsg_sp_mrx {
784 uint64_t u64;
785 struct cvmx_sriox_omsg_sp_mrx_s {
786 uint64_t reserved_16_63:48;
787 uint64_t xmbox_sp:1;
788 uint64_t ctlr_sp:1;
789 uint64_t ctlr_fmp:1;
790 uint64_t ctlr_nmp:1;
791 uint64_t id_sp:1;
792 uint64_t id_fmp:1;
793 uint64_t id_nmp:1;
794 uint64_t id_psd:1;
795 uint64_t mbox_sp:1;
796 uint64_t mbox_fmp:1;
797 uint64_t mbox_nmp:1;
798 uint64_t mbox_psd:1;
799 uint64_t all_sp:1;
800 uint64_t all_fmp:1;
801 uint64_t all_nmp:1;
802 uint64_t all_psd:1;
803 } s;
804 struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
805 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
806 struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
807};
808
809union cvmx_sriox_priox_in_use {
810 uint64_t u64;
811 struct cvmx_sriox_priox_in_use_s {
812 uint64_t reserved_32_63:32;
813 uint64_t end_cnt:16;
814 uint64_t start_cnt:16;
815 } s;
816 struct cvmx_sriox_priox_in_use_s cn63xx;
817 struct cvmx_sriox_priox_in_use_s cn66xx;
818};
819
820union cvmx_sriox_rx_bell {
821 uint64_t u64;
822 struct cvmx_sriox_rx_bell_s {
823 uint64_t reserved_48_63:16;
824 uint64_t data:16;
825 uint64_t src_id:16;
826 uint64_t count:8;
827 uint64_t reserved_5_7:3;
828 uint64_t dest_id:1;
829 uint64_t id16:1;
830 uint64_t reserved_2_2:1;
831 uint64_t priority:2;
832 } s;
833 struct cvmx_sriox_rx_bell_s cn63xx;
834 struct cvmx_sriox_rx_bell_s cn63xxp1;
835 struct cvmx_sriox_rx_bell_s cn66xx;
836};
837
838union cvmx_sriox_rx_bell_seq {
839 uint64_t u64;
840 struct cvmx_sriox_rx_bell_seq_s {
841 uint64_t reserved_40_63:24;
842 uint64_t count:8;
843 uint64_t seq:32;
844 } s;
845 struct cvmx_sriox_rx_bell_seq_s cn63xx;
846 struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
847 struct cvmx_sriox_rx_bell_seq_s cn66xx;
848};
849
850union cvmx_sriox_rx_status {
851 uint64_t u64;
852 struct cvmx_sriox_rx_status_s {
853 uint64_t rtn_pr3:8;
854 uint64_t rtn_pr2:8;
855 uint64_t rtn_pr1:8;
856 uint64_t reserved_28_39:12;
857 uint64_t mbox:4;
858 uint64_t comp:8;
859 uint64_t reserved_13_15:3;
860 uint64_t n_post:5;
861 uint64_t post:8;
862 } s;
863 struct cvmx_sriox_rx_status_s cn63xx;
864 struct cvmx_sriox_rx_status_s cn63xxp1;
865 struct cvmx_sriox_rx_status_s cn66xx;
866};
867
868union cvmx_sriox_s2m_typex {
869 uint64_t u64;
870 struct cvmx_sriox_s2m_typex_s {
871 uint64_t reserved_19_63:45;
872 uint64_t wr_op:3;
873 uint64_t reserved_15_15:1;
874 uint64_t rd_op:3;
875 uint64_t wr_prior:2;
876 uint64_t rd_prior:2;
877 uint64_t reserved_6_7:2;
878 uint64_t src_id:1;
879 uint64_t id16:1;
880 uint64_t reserved_2_3:2;
881 uint64_t iaow_sel:2;
882 } s;
883 struct cvmx_sriox_s2m_typex_s cn63xx;
884 struct cvmx_sriox_s2m_typex_s cn63xxp1;
885 struct cvmx_sriox_s2m_typex_s cn66xx;
886};
887
888union cvmx_sriox_seq {
889 uint64_t u64;
890 struct cvmx_sriox_seq_s {
891 uint64_t reserved_32_63:32;
892 uint64_t seq:32;
893 } s;
894 struct cvmx_sriox_seq_s cn63xx;
895 struct cvmx_sriox_seq_s cn63xxp1;
896 struct cvmx_sriox_seq_s cn66xx;
897};
898
899union cvmx_sriox_status_reg {
900 uint64_t u64;
901 struct cvmx_sriox_status_reg_s {
902 uint64_t reserved_2_63:62;
903 uint64_t access:1;
904 uint64_t srio:1;
905 } s;
906 struct cvmx_sriox_status_reg_s cn63xx;
907 struct cvmx_sriox_status_reg_s cn63xxp1;
908 struct cvmx_sriox_status_reg_s cn66xx;
909};
910
911union cvmx_sriox_tag_ctrl {
912 uint64_t u64;
913 struct cvmx_sriox_tag_ctrl_s {
914 uint64_t reserved_17_63:47;
915 uint64_t o_clr:1;
916 uint64_t reserved_13_15:3;
917 uint64_t otag:5;
918 uint64_t reserved_5_7:3;
919 uint64_t itag:5;
920 } s;
921 struct cvmx_sriox_tag_ctrl_s cn63xx;
922 struct cvmx_sriox_tag_ctrl_s cn63xxp1;
923 struct cvmx_sriox_tag_ctrl_s cn66xx;
924};
925
926union cvmx_sriox_tlp_credits {
927 uint64_t u64;
928 struct cvmx_sriox_tlp_credits_s {
929 uint64_t reserved_28_63:36;
930 uint64_t mbox:4;
931 uint64_t comp:8;
932 uint64_t reserved_13_15:3;
933 uint64_t n_post:5;
934 uint64_t post:8;
935 } s;
936 struct cvmx_sriox_tlp_credits_s cn63xx;
937 struct cvmx_sriox_tlp_credits_s cn63xxp1;
938 struct cvmx_sriox_tlp_credits_s cn66xx;
939};
940
941union cvmx_sriox_tx_bell {
942 uint64_t u64;
943 struct cvmx_sriox_tx_bell_s {
944 uint64_t reserved_48_63:16;
945 uint64_t data:16;
946 uint64_t dest_id:16;
947 uint64_t reserved_9_15:7;
948 uint64_t pending:1;
949 uint64_t reserved_5_7:3;
950 uint64_t src_id:1;
951 uint64_t id16:1;
952 uint64_t reserved_2_2:1;
953 uint64_t priority:2;
954 } s;
955 struct cvmx_sriox_tx_bell_s cn63xx;
956 struct cvmx_sriox_tx_bell_s cn63xxp1;
957 struct cvmx_sriox_tx_bell_s cn66xx;
958};
959
960union cvmx_sriox_tx_bell_info {
961 uint64_t u64;
962 struct cvmx_sriox_tx_bell_info_s {
963 uint64_t reserved_48_63:16;
964 uint64_t data:16;
965 uint64_t dest_id:16;
966 uint64_t reserved_8_15:8;
967 uint64_t timeout:1;
968 uint64_t error:1;
969 uint64_t retry:1;
970 uint64_t src_id:1;
971 uint64_t id16:1;
972 uint64_t reserved_2_2:1;
973 uint64_t priority:2;
974 } s;
975 struct cvmx_sriox_tx_bell_info_s cn63xx;
976 struct cvmx_sriox_tx_bell_info_s cn63xxp1;
977 struct cvmx_sriox_tx_bell_info_s cn66xx;
978};
979
980union cvmx_sriox_tx_ctrl {
981 uint64_t u64;
982 struct cvmx_sriox_tx_ctrl_s {
983 uint64_t reserved_53_63:11;
984 uint64_t tag_th2:5;
985 uint64_t reserved_45_47:3;
986 uint64_t tag_th1:5;
987 uint64_t reserved_37_39:3;
988 uint64_t tag_th0:5;
989 uint64_t reserved_20_31:12;
990 uint64_t tx_th2:4;
991 uint64_t reserved_12_15:4;
992 uint64_t tx_th1:4;
993 uint64_t reserved_4_7:4;
994 uint64_t tx_th0:4;
995 } s;
996 struct cvmx_sriox_tx_ctrl_s cn63xx;
997 struct cvmx_sriox_tx_ctrl_s cn63xxp1;
998 struct cvmx_sriox_tx_ctrl_s cn66xx;
999};
1000
1001union cvmx_sriox_tx_emphasis {
1002 uint64_t u64;
1003 struct cvmx_sriox_tx_emphasis_s {
1004 uint64_t reserved_4_63:60;
1005 uint64_t emph:4;
1006 } s;
1007 struct cvmx_sriox_tx_emphasis_s cn63xx;
1008 struct cvmx_sriox_tx_emphasis_s cn66xx;
1009};
1010
1011union cvmx_sriox_tx_status {
1012 uint64_t u64;
1013 struct cvmx_sriox_tx_status_s {
1014 uint64_t reserved_32_63:32;
1015 uint64_t s2m_pr3:8;
1016 uint64_t s2m_pr2:8;
1017 uint64_t s2m_pr1:8;
1018 uint64_t s2m_pr0:8;
1019 } s;
1020 struct cvmx_sriox_tx_status_s cn63xx;
1021 struct cvmx_sriox_tx_status_s cn63xxp1;
1022 struct cvmx_sriox_tx_status_s cn66xx;
1023};
1024
1025union cvmx_sriox_wr_done_counts {
1026 uint64_t u64;
1027 struct cvmx_sriox_wr_done_counts_s {
1028 uint64_t reserved_32_63:32;
1029 uint64_t bad:16;
1030 uint64_t good:16;
1031 } s;
1032 struct cvmx_sriox_wr_done_counts_s cn63xx;
1033 struct cvmx_sriox_wr_done_counts_s cn66xx;
1034};
1035
1036#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
new file mode 100644
index 00000000000..d82b366c279
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
@@ -0,0 +1,126 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SRXX_DEFS_H__
29#define __CVMX_SRXX_DEFS_H__
30
31#define CVMX_SRXX_COM_CTL(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_SRXX_IGN_RX_FULL(block_id) \
34 CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_SRXX_SPI4_CALX(offset, block_id) \
36 CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_SRXX_SPI4_STAT(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_SRXX_SW_TICK_CTL(block_id) \
40 CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_SRXX_SW_TICK_DAT(block_id) \
42 CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull))
43
44union cvmx_srxx_com_ctl {
45 uint64_t u64;
46 struct cvmx_srxx_com_ctl_s {
47 uint64_t reserved_8_63:56;
48 uint64_t prts:4;
49 uint64_t st_en:1;
50 uint64_t reserved_1_2:2;
51 uint64_t inf_en:1;
52 } s;
53 struct cvmx_srxx_com_ctl_s cn38xx;
54 struct cvmx_srxx_com_ctl_s cn38xxp2;
55 struct cvmx_srxx_com_ctl_s cn58xx;
56 struct cvmx_srxx_com_ctl_s cn58xxp1;
57};
58
59union cvmx_srxx_ign_rx_full {
60 uint64_t u64;
61 struct cvmx_srxx_ign_rx_full_s {
62 uint64_t reserved_16_63:48;
63 uint64_t ignore:16;
64 } s;
65 struct cvmx_srxx_ign_rx_full_s cn38xx;
66 struct cvmx_srxx_ign_rx_full_s cn38xxp2;
67 struct cvmx_srxx_ign_rx_full_s cn58xx;
68 struct cvmx_srxx_ign_rx_full_s cn58xxp1;
69};
70
71union cvmx_srxx_spi4_calx {
72 uint64_t u64;
73 struct cvmx_srxx_spi4_calx_s {
74 uint64_t reserved_17_63:47;
75 uint64_t oddpar:1;
76 uint64_t prt3:4;
77 uint64_t prt2:4;
78 uint64_t prt1:4;
79 uint64_t prt0:4;
80 } s;
81 struct cvmx_srxx_spi4_calx_s cn38xx;
82 struct cvmx_srxx_spi4_calx_s cn38xxp2;
83 struct cvmx_srxx_spi4_calx_s cn58xx;
84 struct cvmx_srxx_spi4_calx_s cn58xxp1;
85};
86
87union cvmx_srxx_spi4_stat {
88 uint64_t u64;
89 struct cvmx_srxx_spi4_stat_s {
90 uint64_t reserved_16_63:48;
91 uint64_t m:8;
92 uint64_t reserved_7_7:1;
93 uint64_t len:7;
94 } s;
95 struct cvmx_srxx_spi4_stat_s cn38xx;
96 struct cvmx_srxx_spi4_stat_s cn38xxp2;
97 struct cvmx_srxx_spi4_stat_s cn58xx;
98 struct cvmx_srxx_spi4_stat_s cn58xxp1;
99};
100
101union cvmx_srxx_sw_tick_ctl {
102 uint64_t u64;
103 struct cvmx_srxx_sw_tick_ctl_s {
104 uint64_t reserved_14_63:50;
105 uint64_t eop:1;
106 uint64_t sop:1;
107 uint64_t mod:4;
108 uint64_t opc:4;
109 uint64_t adr:4;
110 } s;
111 struct cvmx_srxx_sw_tick_ctl_s cn38xx;
112 struct cvmx_srxx_sw_tick_ctl_s cn58xx;
113 struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
114};
115
116union cvmx_srxx_sw_tick_dat {
117 uint64_t u64;
118 struct cvmx_srxx_sw_tick_dat_s {
119 uint64_t dat:64;
120 } s;
121 struct cvmx_srxx_sw_tick_dat_s cn38xx;
122 struct cvmx_srxx_sw_tick_dat_s cn58xx;
123 struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
124};
125
126#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
new file mode 100644
index 00000000000..4f209b62cae
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
@@ -0,0 +1,292 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_STXX_DEFS_H__
29#define __CVMX_STXX_DEFS_H__
30
31#define CVMX_STXX_ARB_CTL(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_STXX_BCKPRS_CNT(block_id) \
34 CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_STXX_COM_CTL(block_id) \
36 CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_STXX_DIP_CNT(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_STXX_IGN_CAL(block_id) \
40 CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_STXX_INT_MSK(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_STXX_INT_REG(block_id) \
44 CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_STXX_INT_SYNC(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_STXX_MIN_BST(block_id) \
48 CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_STXX_SPI4_CALX(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_STXX_SPI4_DAT(block_id) \
52 CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_STXX_SPI4_STAT(block_id) \
54 CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_STXX_STAT_BYTES_HI(block_id) \
56 CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_STXX_STAT_BYTES_LO(block_id) \
58 CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_STXX_STAT_CTL(block_id) \
60 CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_STXX_STAT_PKT_XMT(block_id) \
62 CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull))
63
64union cvmx_stxx_arb_ctl {
65 uint64_t u64;
66 struct cvmx_stxx_arb_ctl_s {
67 uint64_t reserved_6_63:58;
68 uint64_t mintrn:1;
69 uint64_t reserved_4_4:1;
70 uint64_t igntpa:1;
71 uint64_t reserved_0_2:3;
72 } s;
73 struct cvmx_stxx_arb_ctl_s cn38xx;
74 struct cvmx_stxx_arb_ctl_s cn38xxp2;
75 struct cvmx_stxx_arb_ctl_s cn58xx;
76 struct cvmx_stxx_arb_ctl_s cn58xxp1;
77};
78
79union cvmx_stxx_bckprs_cnt {
80 uint64_t u64;
81 struct cvmx_stxx_bckprs_cnt_s {
82 uint64_t reserved_32_63:32;
83 uint64_t cnt:32;
84 } s;
85 struct cvmx_stxx_bckprs_cnt_s cn38xx;
86 struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
87 struct cvmx_stxx_bckprs_cnt_s cn58xx;
88 struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
89};
90
91union cvmx_stxx_com_ctl {
92 uint64_t u64;
93 struct cvmx_stxx_com_ctl_s {
94 uint64_t reserved_4_63:60;
95 uint64_t st_en:1;
96 uint64_t reserved_1_2:2;
97 uint64_t inf_en:1;
98 } s;
99 struct cvmx_stxx_com_ctl_s cn38xx;
100 struct cvmx_stxx_com_ctl_s cn38xxp2;
101 struct cvmx_stxx_com_ctl_s cn58xx;
102 struct cvmx_stxx_com_ctl_s cn58xxp1;
103};
104
105union cvmx_stxx_dip_cnt {
106 uint64_t u64;
107 struct cvmx_stxx_dip_cnt_s {
108 uint64_t reserved_8_63:56;
109 uint64_t frmmax:4;
110 uint64_t dipmax:4;
111 } s;
112 struct cvmx_stxx_dip_cnt_s cn38xx;
113 struct cvmx_stxx_dip_cnt_s cn38xxp2;
114 struct cvmx_stxx_dip_cnt_s cn58xx;
115 struct cvmx_stxx_dip_cnt_s cn58xxp1;
116};
117
118union cvmx_stxx_ign_cal {
119 uint64_t u64;
120 struct cvmx_stxx_ign_cal_s {
121 uint64_t reserved_16_63:48;
122 uint64_t igntpa:16;
123 } s;
124 struct cvmx_stxx_ign_cal_s cn38xx;
125 struct cvmx_stxx_ign_cal_s cn38xxp2;
126 struct cvmx_stxx_ign_cal_s cn58xx;
127 struct cvmx_stxx_ign_cal_s cn58xxp1;
128};
129
130union cvmx_stxx_int_msk {
131 uint64_t u64;
132 struct cvmx_stxx_int_msk_s {
133 uint64_t reserved_8_63:56;
134 uint64_t frmerr:1;
135 uint64_t unxfrm:1;
136 uint64_t nosync:1;
137 uint64_t diperr:1;
138 uint64_t datovr:1;
139 uint64_t ovrbst:1;
140 uint64_t calpar1:1;
141 uint64_t calpar0:1;
142 } s;
143 struct cvmx_stxx_int_msk_s cn38xx;
144 struct cvmx_stxx_int_msk_s cn38xxp2;
145 struct cvmx_stxx_int_msk_s cn58xx;
146 struct cvmx_stxx_int_msk_s cn58xxp1;
147};
148
149union cvmx_stxx_int_reg {
150 uint64_t u64;
151 struct cvmx_stxx_int_reg_s {
152 uint64_t reserved_9_63:55;
153 uint64_t syncerr:1;
154 uint64_t frmerr:1;
155 uint64_t unxfrm:1;
156 uint64_t nosync:1;
157 uint64_t diperr:1;
158 uint64_t datovr:1;
159 uint64_t ovrbst:1;
160 uint64_t calpar1:1;
161 uint64_t calpar0:1;
162 } s;
163 struct cvmx_stxx_int_reg_s cn38xx;
164 struct cvmx_stxx_int_reg_s cn38xxp2;
165 struct cvmx_stxx_int_reg_s cn58xx;
166 struct cvmx_stxx_int_reg_s cn58xxp1;
167};
168
169union cvmx_stxx_int_sync {
170 uint64_t u64;
171 struct cvmx_stxx_int_sync_s {
172 uint64_t reserved_8_63:56;
173 uint64_t frmerr:1;
174 uint64_t unxfrm:1;
175 uint64_t nosync:1;
176 uint64_t diperr:1;
177 uint64_t datovr:1;
178 uint64_t ovrbst:1;
179 uint64_t calpar1:1;
180 uint64_t calpar0:1;
181 } s;
182 struct cvmx_stxx_int_sync_s cn38xx;
183 struct cvmx_stxx_int_sync_s cn38xxp2;
184 struct cvmx_stxx_int_sync_s cn58xx;
185 struct cvmx_stxx_int_sync_s cn58xxp1;
186};
187
188union cvmx_stxx_min_bst {
189 uint64_t u64;
190 struct cvmx_stxx_min_bst_s {
191 uint64_t reserved_9_63:55;
192 uint64_t minb:9;
193 } s;
194 struct cvmx_stxx_min_bst_s cn38xx;
195 struct cvmx_stxx_min_bst_s cn38xxp2;
196 struct cvmx_stxx_min_bst_s cn58xx;
197 struct cvmx_stxx_min_bst_s cn58xxp1;
198};
199
200union cvmx_stxx_spi4_calx {
201 uint64_t u64;
202 struct cvmx_stxx_spi4_calx_s {
203 uint64_t reserved_17_63:47;
204 uint64_t oddpar:1;
205 uint64_t prt3:4;
206 uint64_t prt2:4;
207 uint64_t prt1:4;
208 uint64_t prt0:4;
209 } s;
210 struct cvmx_stxx_spi4_calx_s cn38xx;
211 struct cvmx_stxx_spi4_calx_s cn38xxp2;
212 struct cvmx_stxx_spi4_calx_s cn58xx;
213 struct cvmx_stxx_spi4_calx_s cn58xxp1;
214};
215
216union cvmx_stxx_spi4_dat {
217 uint64_t u64;
218 struct cvmx_stxx_spi4_dat_s {
219 uint64_t reserved_32_63:32;
220 uint64_t alpha:16;
221 uint64_t max_t:16;
222 } s;
223 struct cvmx_stxx_spi4_dat_s cn38xx;
224 struct cvmx_stxx_spi4_dat_s cn38xxp2;
225 struct cvmx_stxx_spi4_dat_s cn58xx;
226 struct cvmx_stxx_spi4_dat_s cn58xxp1;
227};
228
229union cvmx_stxx_spi4_stat {
230 uint64_t u64;
231 struct cvmx_stxx_spi4_stat_s {
232 uint64_t reserved_16_63:48;
233 uint64_t m:8;
234 uint64_t reserved_7_7:1;
235 uint64_t len:7;
236 } s;
237 struct cvmx_stxx_spi4_stat_s cn38xx;
238 struct cvmx_stxx_spi4_stat_s cn38xxp2;
239 struct cvmx_stxx_spi4_stat_s cn58xx;
240 struct cvmx_stxx_spi4_stat_s cn58xxp1;
241};
242
243union cvmx_stxx_stat_bytes_hi {
244 uint64_t u64;
245 struct cvmx_stxx_stat_bytes_hi_s {
246 uint64_t reserved_32_63:32;
247 uint64_t cnt:32;
248 } s;
249 struct cvmx_stxx_stat_bytes_hi_s cn38xx;
250 struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
251 struct cvmx_stxx_stat_bytes_hi_s cn58xx;
252 struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
253};
254
255union cvmx_stxx_stat_bytes_lo {
256 uint64_t u64;
257 struct cvmx_stxx_stat_bytes_lo_s {
258 uint64_t reserved_32_63:32;
259 uint64_t cnt:32;
260 } s;
261 struct cvmx_stxx_stat_bytes_lo_s cn38xx;
262 struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
263 struct cvmx_stxx_stat_bytes_lo_s cn58xx;
264 struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
265};
266
267union cvmx_stxx_stat_ctl {
268 uint64_t u64;
269 struct cvmx_stxx_stat_ctl_s {
270 uint64_t reserved_5_63:59;
271 uint64_t clr:1;
272 uint64_t bckprs:4;
273 } s;
274 struct cvmx_stxx_stat_ctl_s cn38xx;
275 struct cvmx_stxx_stat_ctl_s cn38xxp2;
276 struct cvmx_stxx_stat_ctl_s cn58xx;
277 struct cvmx_stxx_stat_ctl_s cn58xxp1;
278};
279
280union cvmx_stxx_stat_pkt_xmt {
281 uint64_t u64;
282 struct cvmx_stxx_stat_pkt_xmt_s {
283 uint64_t reserved_32_63:32;
284 uint64_t cnt:32;
285 } s;
286 struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
287 struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
288 struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
289 struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
290};
291
292#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
new file mode 100644
index 00000000000..653610953d2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
@@ -0,0 +1,397 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * This header file defines the work queue entry (wqe) data structure.
31 * Since this is a commonly used structure that depends on structures
32 * from several hardware blocks, those definitions have been placed
33 * in this file to create a single point of definition of the wqe
34 * format.
35 * Data structures are still named according to the block that they
36 * relate to.
37 *
38 */
39
40#ifndef __CVMX_WQE_H__
41#define __CVMX_WQE_H__
42
43#include "cvmx-packet.h"
44
45
46#define OCT_TAG_TYPE_STRING(x) \
47 (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \
48 (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \
49 (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \
50 "NULL_NULL")))
51
52/**
53 * HW decode / err_code in work queue entry
54 */
55typedef union {
56 uint64_t u64;
57
58 /* Use this struct if the hardware determines that the packet is IP */
59 struct {
60 /* HW sets this to the number of buffers used by this packet */
61 uint64_t bufs:8;
62 /* HW sets to the number of L2 bytes prior to the IP */
63 uint64_t ip_offset:8;
64 /* set to 1 if we found DSA/VLAN in the L2 */
65 uint64_t vlan_valid:1;
66 /* Set to 1 if the DSA/VLAN tag is stacked */
67 uint64_t vlan_stacked:1;
68 uint64_t unassigned:1;
69 /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
70 uint64_t vlan_cfi:1;
71 /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
72 uint64_t vlan_id:12;
73 /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
74 uint64_t pr:4;
75 uint64_t unassigned2:8;
76 /* the packet needs to be decompressed */
77 uint64_t dec_ipcomp:1;
78 /* the packet is either TCP or UDP */
79 uint64_t tcp_or_udp:1;
80 /* the packet needs to be decrypted (ESP or AH) */
81 uint64_t dec_ipsec:1;
82 /* the packet is IPv6 */
83 uint64_t is_v6:1;
84
85 /*
86 * (rcv_error, not_IP, IP_exc, is_frag, L4_error,
87 * software, etc.).
88 */
89
90 /*
91 * reserved for software use, hardware will clear on
92 * packet creation.
93 */
94 uint64_t software:1;
95 /* exceptional conditions below */
96 /* the receive interface hardware detected an L4 error
97 * (only applies if !is_frag) (only applies if
98 * !rcv_error && !not_IP && !IP_exc && !is_frag)
99 * failure indicated in err_code below, decode:
100 *
101 * - 1 = Malformed L4
102 * - 2 = L4 Checksum Error: the L4 checksum value is
103 * - 3 = UDP Length Error: The UDP length field would
104 * make the UDP data longer than what remains in
105 * the IP packet (as defined by the IP header
106 * length field).
107 * - 4 = Bad L4 Port: either the source or destination
108 * TCP/UDP port is 0.
109 * - 8 = TCP FIN Only: the packet is TCP and only the
110 * FIN flag set.
111 * - 9 = TCP No Flags: the packet is TCP and no flags
112 * are set.
113 * - 10 = TCP FIN RST: the packet is TCP and both FIN
114 * and RST are set.
115 * - 11 = TCP SYN URG: the packet is TCP and both SYN
116 * and URG are set.
117 * - 12 = TCP SYN RST: the packet is TCP and both SYN
118 * and RST are set.
119 * - 13 = TCP SYN FIN: the packet is TCP and both SYN
120 * and FIN are set.
121 */
122 uint64_t L4_error:1;
123 /* set if the packet is a fragment */
124 uint64_t is_frag:1;
125 /* the receive interface hardware detected an IP error
126 * / exception (only applies if !rcv_error && !not_IP)
127 * failure indicated in err_code below, decode:
128 *
129 * - 1 = Not IP: the IP version field is neither 4 nor
130 * 6.
131 * - 2 = IPv4 Header Checksum Error: the IPv4 header
132 * has a checksum violation.
133 * - 3 = IP Malformed Header: the packet is not long
134 * enough to contain the IP header.
135 * - 4 = IP Malformed: the packet is not long enough
136 * to contain the bytes indicated by the IP
137 * header. Pad is allowed.
138 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
139 * Hop Count field are zero.
140 * - 6 = IP Options
141 */
142 uint64_t IP_exc:1;
143 /*
144 * Set if the hardware determined that the packet is a
145 * broadcast.
146 */
147 uint64_t is_bcast:1;
148 /*
149 * St if the hardware determined that the packet is a
150 * multi-cast.
151 */
152 uint64_t is_mcast:1;
153 /*
154 * Set if the packet may not be IP (must be zero in
155 * this case).
156 */
157 uint64_t not_IP:1;
158 /*
159 * The receive interface hardware detected a receive
160 * error (must be zero in this case).
161 */
162 uint64_t rcv_error:1;
163 /* lower err_code = first-level descriptor of the
164 * work */
165 /* zero for packet submitted by hardware that isn't on
166 * the slow path */
167 /* type is cvmx_pip_err_t */
168 uint64_t err_code:8;
169 } s;
170
171 /* use this to get at the 16 vlan bits */
172 struct {
173 uint64_t unused1:16;
174 uint64_t vlan:16;
175 uint64_t unused2:32;
176 } svlan;
177
178 /*
179 * use this struct if the hardware could not determine that
180 * the packet is ip.
181 */
182 struct {
183 /*
184 * HW sets this to the number of buffers used by this
185 * packet.
186 */
187 uint64_t bufs:8;
188 uint64_t unused:8;
189 /* set to 1 if we found DSA/VLAN in the L2 */
190 uint64_t vlan_valid:1;
191 /* Set to 1 if the DSA/VLAN tag is stacked */
192 uint64_t vlan_stacked:1;
193 uint64_t unassigned:1;
194 /*
195 * HW sets to the DSA/VLAN CFI flag (valid when
196 * vlan_valid)
197 */
198 uint64_t vlan_cfi:1;
199 /*
200 * HW sets to the DSA/VLAN_ID field (valid when
201 * vlan_valid).
202 */
203 uint64_t vlan_id:12;
204 /*
205 * Ring Identifier (if PCIe). Requires
206 * PIP_GBL_CTL[RING_EN]=1
207 */
208 uint64_t pr:4;
209 uint64_t unassigned2:12;
210 /*
211 * reserved for software use, hardware will clear on
212 * packet creation.
213 */
214 uint64_t software:1;
215 uint64_t unassigned3:1;
216 /*
217 * set if the hardware determined that the packet is
218 * rarp.
219 */
220 uint64_t is_rarp:1;
221 /*
222 * set if the hardware determined that the packet is
223 * arp
224 */
225 uint64_t is_arp:1;
226 /*
227 * set if the hardware determined that the packet is a
228 * broadcast.
229 */
230 uint64_t is_bcast:1;
231 /*
232 * set if the hardware determined that the packet is a
233 * multi-cast
234 */
235 uint64_t is_mcast:1;
236 /*
237 * set if the packet may not be IP (must be one in
238 * this case)
239 */
240 uint64_t not_IP:1;
241 /* The receive interface hardware detected a receive
242 * error. Failure indicated in err_code below,
243 * decode:
244 *
245 * - 1 = partial error: a packet was partially
246 * received, but internal buffering / bandwidth
247 * was not adequate to receive the entire
248 * packet.
249 * - 2 = jabber error: the RGMII packet was too large
250 * and is truncated.
251 * - 3 = overrun error: the RGMII packet is longer
252 * than allowed and had an FCS error.
253 * - 4 = oversize error: the RGMII packet is longer
254 * than allowed.
255 * - 5 = alignment error: the RGMII packet is not an
256 * integer number of bytes
257 * and had an FCS error (100M and 10M only).
258 * - 6 = fragment error: the RGMII packet is shorter
259 * than allowed and had an FCS error.
260 * - 7 = GMX FCS error: the RGMII packet had an FCS
261 * error.
262 * - 8 = undersize error: the RGMII packet is shorter
263 * than allowed.
264 * - 9 = extend error: the RGMII packet had an extend
265 * error.
266 * - 10 = length mismatch error: the RGMII packet had
267 * a length that did not match the length field
268 * in the L2 HDR.
269 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
270 * packet had one or more data reception errors
271 * (RXERR) or the SPI4 packet had one or more
272 * DIP4 errors.
273 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
274 * packet was not large enough to cover the
275 * skipped bytes or the SPI4 packet was
276 * terminated with an About EOPS.
277 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
278 * RGMII packet had a studder error (data not
279 * repeated - 10/100M only) or the SPI4 packet
280 * was sent to an NXA.
281 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
282 * - 17 = Skip error: a packet was not large enough to
283 * cover the skipped bytes.
284 * - 18 = L2 header malformed: the packet is not long
285 * enough to contain the L2.
286 */
287
288 uint64_t rcv_error:1;
289 /*
290 * lower err_code = first-level descriptor of the
291 * work
292 */
293 /*
294 * zero for packet submitted by hardware that isn't on
295 * the slow path
296 */
297 /* type is cvmx_pip_err_t (union, so can't use directly */
298 uint64_t err_code:8;
299 } snoip;
300
301} cvmx_pip_wqe_word2;
302
303/**
304 * Work queue entry format
305 *
306 * must be 8-byte aligned
307 */
308typedef struct {
309
310 /*****************************************************************
311 * WORD 0
312 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
313 */
314
315 /**
316 * raw chksum result generated by the HW
317 */
318 uint16_t hw_chksum;
319 /**
320 * Field unused by hardware - available for software
321 */
322 uint8_t unused;
323 /**
324 * Next pointer used by hardware for list maintenance.
325 * May be written/read by HW before the work queue
326 * entry is scheduled to a PP
327 * (Only 36 bits used in Octeon 1)
328 */
329 uint64_t next_ptr:40;
330
331 /*****************************************************************
332 * WORD 1
333 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
334 */
335
336 /**
337 * HW sets to the total number of bytes in the packet
338 */
339 uint64_t len:16;
340 /**
341 * HW sets this to input physical port
342 */
343 uint64_t ipprt:6;
344
345 /**
346 * HW sets this to what it thought the priority of the input packet was
347 */
348 uint64_t qos:3;
349
350 /**
351 * the group that the work queue entry will be scheduled to
352 */
353 uint64_t grp:4;
354 /**
355 * the type of the tag (ORDERED, ATOMIC, NULL)
356 */
357 uint64_t tag_type:3;
358 /**
359 * the synchronization/ordering tag
360 */
361 uint64_t tag:32;
362
363 /**
364 * WORD 2 HW WRITE: the following 64-bits are filled in by
365 * hardware when a packet arrives This indicates a variety of
366 * status and error conditions.
367 */
368 cvmx_pip_wqe_word2 word2;
369
370 /**
371 * Pointer to the first segment of the packet.
372 */
373 union cvmx_buf_ptr packet_ptr;
374
375 /**
376 * HW WRITE: octeon will fill in a programmable amount from the
377 * packet, up to (at most, but perhaps less) the amount
378 * needed to fill the work queue entry to 128 bytes
379 *
380 * If the packet is recognized to be IP, the hardware starts
381 * (except that the IPv4 header is padded for appropriate
382 * alignment) writing here where the IP header starts. If the
383 * packet is not recognized to be IP, the hardware starts
384 * writing the beginning of the packet here.
385 */
386 uint8_t packet_data[96];
387
388 /**
389 * If desired, SW can make the work Q entry any length. For the
390 * purposes of discussion here, Assume 128B always, as this is all that
391 * the hardware deals with.
392 *
393 */
394
395} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
396
397#endif /* __CVMX_WQE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 7e1286706d4..740be97a325 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -31,6 +31,27 @@
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/string.h> 32#include <linux/string.h>
33 33
34enum cvmx_mips_space {
35 CVMX_MIPS_SPACE_XKSEG = 3LL,
36 CVMX_MIPS_SPACE_XKPHYS = 2LL,
37 CVMX_MIPS_SPACE_XSSEG = 1LL,
38 CVMX_MIPS_SPACE_XUSEG = 0LL
39};
40
41/* These macros for use when using 32 bit pointers. */
42#define CVMX_MIPS32_SPACE_KSEG0 1l
43#define CVMX_ADD_SEG32(segment, add) \
44 (((int32_t)segment << 31) | (int32_t)(add))
45
46#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
47
48/* These macros simplify the process of creating common IO addresses */
49#define CVMX_ADD_SEG(segment, add) \
50 ((((uint64_t)segment) << 62) | (add))
51#ifndef CVMX_ADD_IO_SEG
52#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
53#endif
54
34#include "cvmx-asm.h" 55#include "cvmx-asm.h"
35#include "cvmx-packet.h" 56#include "cvmx-packet.h"
36#include "cvmx-sysinfo.h" 57#include "cvmx-sysinfo.h"
@@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
129 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit; 150 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
130} 151}
131 152
132enum cvmx_mips_space {
133 CVMX_MIPS_SPACE_XKSEG = 3LL,
134 CVMX_MIPS_SPACE_XKPHYS = 2LL,
135 CVMX_MIPS_SPACE_XSSEG = 1LL,
136 CVMX_MIPS_SPACE_XUSEG = 0LL
137};
138
139/* These macros for use when using 32 bit pointers. */
140#define CVMX_MIPS32_SPACE_KSEG0 1l
141#define CVMX_ADD_SEG32(segment, add) \
142 (((int32_t)segment << 31) | (int32_t)(add))
143
144#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
145
146/* These macros simplify the process of creating common IO addresses */
147#define CVMX_ADD_SEG(segment, add) \
148 ((((uint64_t)segment) << 62) | (add))
149#ifndef CVMX_ADD_IO_SEG
150#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
151#endif
152
153/** 153/**
154 * Convert a memory pointer (void*) into a hardware compatible 154 * Convert a memory pointer (void*) into a hardware compatible
155 * memory address (uint64_t). Octeon hardware widgets don't 155 * memory address (uint64_t). Octeon hardware widgets don't
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index cba6fbed9f4..8008da2f877 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -31,8 +31,14 @@
31 31
32#ifndef __OCTEON_FEATURE_H__ 32#ifndef __OCTEON_FEATURE_H__
33#define __OCTEON_FEATURE_H__ 33#define __OCTEON_FEATURE_H__
34#include <asm/octeon/cvmx-mio-defs.h>
35#include <asm/octeon/cvmx-rnm-defs.h>
34 36
35enum octeon_feature { 37enum octeon_feature {
38 /* CN68XX uses port kinds for packet interface */
39 OCTEON_FEATURE_PKND,
40 /* CN68XX has different fields in word0 - word2 */
41 OCTEON_FEATURE_CN68XX_WQE,
36 /* 42 /*
37 * Octeon models in the CN5XXX family and higher support 43 * Octeon models in the CN5XXX family and higher support
38 * atomic add instructions to memory (saa/saad). 44 * atomic add instructions to memory (saa/saad).
@@ -42,8 +48,13 @@ enum octeon_feature {
42 OCTEON_FEATURE_ZIP, 48 OCTEON_FEATURE_ZIP,
43 /* Does this Octeon support crypto acceleration using COP2? */ 49 /* Does this Octeon support crypto acceleration using COP2? */
44 OCTEON_FEATURE_CRYPTO, 50 OCTEON_FEATURE_CRYPTO,
51 OCTEON_FEATURE_DORM_CRYPTO,
45 /* Does this Octeon support PCI express? */ 52 /* Does this Octeon support PCI express? */
46 OCTEON_FEATURE_PCIE, 53 OCTEON_FEATURE_PCIE,
54 /* Does this Octeon support SRIOs */
55 OCTEON_FEATURE_SRIO,
56 /* Does this Octeon support Interlaken */
57 OCTEON_FEATURE_ILK,
47 /* Some Octeon models support internal memory for storing 58 /* Some Octeon models support internal memory for storing
48 * cryptographic keys */ 59 * cryptographic keys */
49 OCTEON_FEATURE_KEY_MEMORY, 60 OCTEON_FEATURE_KEY_MEMORY,
@@ -64,6 +75,15 @@ enum octeon_feature {
64 /* Octeon MDIO block supports clause 45 transactions for 10 75 /* Octeon MDIO block supports clause 45 transactions for 10
65 * Gig support */ 76 * Gig support */
66 OCTEON_FEATURE_MDIO_CLAUSE_45, 77 OCTEON_FEATURE_MDIO_CLAUSE_45,
78 /*
79 * CN52XX and CN56XX used a block named NPEI for PCIe
80 * access. Newer chips replaced this with SLI+DPI.
81 */
82 OCTEON_FEATURE_NPEI,
83 OCTEON_FEATURE_HFA,
84 OCTEON_FEATURE_DFM,
85 OCTEON_FEATURE_CIU2,
86 OCTEON_MAX_FEATURE
67}; 87};
68 88
69static inline int cvmx_fuse_read(int fuse); 89static inline int cvmx_fuse_read(int fuse);
@@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature)
96 return !cvmx_fuse_read(121); 116 return !cvmx_fuse_read(121);
97 117
98 case OCTEON_FEATURE_CRYPTO: 118 case OCTEON_FEATURE_CRYPTO:
99 return !cvmx_fuse_read(90); 119 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
120 union cvmx_mio_fus_dat2 fus_2;
121 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
122 if (fus_2.s.nocrypto || fus_2.s.nomul) {
123 return 0;
124 } else if (!fus_2.s.dorm_crypto) {
125 return 1;
126 } else {
127 union cvmx_rnm_ctl_status st;
128 st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
129 return st.s.eer_val;
130 }
131 } else {
132 return !cvmx_fuse_read(90);
133 }
134
135 case OCTEON_FEATURE_DORM_CRYPTO:
136 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
137 union cvmx_mio_fus_dat2 fus_2;
138 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
139 return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
140 } else {
141 return 0;
142 }
100 143
101 case OCTEON_FEATURE_PCIE: 144 case OCTEON_FEATURE_PCIE:
102 case OCTEON_FEATURE_MGMT_PORT:
103 case OCTEON_FEATURE_RAID:
104 return OCTEON_IS_MODEL(OCTEON_CN56XX) 145 return OCTEON_IS_MODEL(OCTEON_CN56XX)
105 || OCTEON_IS_MODEL(OCTEON_CN52XX); 146 || OCTEON_IS_MODEL(OCTEON_CN52XX)
147 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
148
149 case OCTEON_FEATURE_SRIO:
150 return OCTEON_IS_MODEL(OCTEON_CN63XX)
151 || OCTEON_IS_MODEL(OCTEON_CN66XX);
152
153 case OCTEON_FEATURE_ILK:
154 return (OCTEON_IS_MODEL(OCTEON_CN68XX));
106 155
107 case OCTEON_FEATURE_KEY_MEMORY: 156 case OCTEON_FEATURE_KEY_MEMORY:
157 return OCTEON_IS_MODEL(OCTEON_CN38XX)
158 || OCTEON_IS_MODEL(OCTEON_CN58XX)
159 || OCTEON_IS_MODEL(OCTEON_CN56XX)
160 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
161
108 case OCTEON_FEATURE_LED_CONTROLLER: 162 case OCTEON_FEATURE_LED_CONTROLLER:
109 return OCTEON_IS_MODEL(OCTEON_CN38XX) 163 return OCTEON_IS_MODEL(OCTEON_CN38XX)
110 || OCTEON_IS_MODEL(OCTEON_CN58XX) 164 || OCTEON_IS_MODEL(OCTEON_CN58XX)
111 || OCTEON_IS_MODEL(OCTEON_CN56XX); 165 || OCTEON_IS_MODEL(OCTEON_CN56XX);
166
112 case OCTEON_FEATURE_TRA: 167 case OCTEON_FEATURE_TRA:
113 return !(OCTEON_IS_MODEL(OCTEON_CN30XX) 168 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
114 || OCTEON_IS_MODEL(OCTEON_CN50XX)); 169 || OCTEON_IS_MODEL(OCTEON_CN50XX));
170 case OCTEON_FEATURE_MGMT_PORT:
171 return OCTEON_IS_MODEL(OCTEON_CN56XX)
172 || OCTEON_IS_MODEL(OCTEON_CN52XX)
173 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
174
175 case OCTEON_FEATURE_RAID:
176 return OCTEON_IS_MODEL(OCTEON_CN56XX)
177 || OCTEON_IS_MODEL(OCTEON_CN52XX)
178 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
179
115 case OCTEON_FEATURE_USB: 180 case OCTEON_FEATURE_USB:
116 return !(OCTEON_IS_MODEL(OCTEON_CN38XX) 181 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
117 || OCTEON_IS_MODEL(OCTEON_CN58XX)); 182 || OCTEON_IS_MODEL(OCTEON_CN58XX));
183
118 case OCTEON_FEATURE_NO_WPTR: 184 case OCTEON_FEATURE_NO_WPTR:
119 return (OCTEON_IS_MODEL(OCTEON_CN56XX) 185 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
120 || OCTEON_IS_MODEL(OCTEON_CN52XX)) 186 || OCTEON_IS_MODEL(OCTEON_CN52XX)
121 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 187 || OCTEON_IS_MODEL(OCTEON_CN6XXX))
122 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); 188 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
189 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
190
123 case OCTEON_FEATURE_DFA: 191 case OCTEON_FEATURE_DFA:
124 if (!OCTEON_IS_MODEL(OCTEON_CN38XX) 192 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
125 && !OCTEON_IS_MODEL(OCTEON_CN31XX) 193 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
@@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature)
127 return 0; 195 return 0;
128 else if (OCTEON_IS_MODEL(OCTEON_CN3020)) 196 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
129 return 0; 197 return 0;
130 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
131 return 1;
132 else 198 else
133 return !cvmx_fuse_read(120); 199 return !cvmx_fuse_read(120);
200
201 case OCTEON_FEATURE_HFA:
202 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
203 return 0;
204 else
205 return !cvmx_fuse_read(90);
206
207 case OCTEON_FEATURE_DFM:
208 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
209 || OCTEON_IS_MODEL(OCTEON_CN66XX)))
210 return 0;
211 else
212 return !cvmx_fuse_read(90);
213
134 case OCTEON_FEATURE_MDIO_CLAUSE_45: 214 case OCTEON_FEATURE_MDIO_CLAUSE_45:
135 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) 215 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
136 || OCTEON_IS_MODEL(OCTEON_CN58XX) 216 || OCTEON_IS_MODEL(OCTEON_CN58XX)
137 || OCTEON_IS_MODEL(OCTEON_CN50XX)); 217 || OCTEON_IS_MODEL(OCTEON_CN50XX));
218
219 case OCTEON_FEATURE_NPEI:
220 return OCTEON_IS_MODEL(OCTEON_CN56XX)
221 || OCTEON_IS_MODEL(OCTEON_CN52XX);
222
223 case OCTEON_FEATURE_PKND:
224 return OCTEON_IS_MODEL(OCTEON_CN68XX);
225
226 case OCTEON_FEATURE_CN68XX_WQE:
227 return OCTEON_IS_MODEL(OCTEON_CN68XX);
228
229 case OCTEON_FEATURE_CIU2:
230 return OCTEON_IS_MODEL(OCTEON_CN68XX);
231
232 default:
233 break;
138 } 234 }
139 return 0; 235 return 0;
140} 236}
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 700f88e31ca..4e338a4d942 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -24,14 +24,6 @@
24 * This file may also be available under a different license from Cavium. 24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27
28/*
29 *
30 * File defining different Octeon model IDs and macros to
31 * compare them.
32 *
33 */
34
35#ifndef __OCTEON_MODEL_H__ 27#ifndef __OCTEON_MODEL_H__
36#define __OCTEON_MODEL_H__ 28#define __OCTEON_MODEL_H__
37 29
@@ -52,6 +44,8 @@
52 * for internal use only, and may change without notice. 44 * for internal use only, and may change without notice.
53 */ 45 */
54 46
47#define OCTEON_FAMILY_MASK 0x00ffff00
48
55/* Flag bits in top byte */ 49/* Flag bits in top byte */
56/* Ignores revision in model checks */ 50/* Ignores revision in model checks */
57#define OM_IGNORE_REVISION 0x01000000 51#define OM_IGNORE_REVISION 0x01000000
@@ -63,21 +57,48 @@
63#define OM_IGNORE_MINOR_REVISION 0x08000000 57#define OM_IGNORE_MINOR_REVISION 0x08000000
64#define OM_FLAG_MASK 0xff000000 58#define OM_FLAG_MASK 0xff000000
65 59
66#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn5XXX Octeon models. */ 60/* Match all cn5XXX Octeon models. */
67#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* Match all cn6XXX Octeon models. */ 61#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000
62/* Match all cn6XXX Octeon models. */
63#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
68 64
69/* 65/*
70 * CN6XXX models with new revision encoding 66 * CN6XXX models with new revision encoding
71 */ 67 */
68#define OCTEON_CN68XX_PASS1_0 0x000d9100
69#define OCTEON_CN68XX_PASS1_1 0x000d9101
70#define OCTEON_CN68XX_PASS1_2 0x000d9102
71#define OCTEON_CN68XX_PASS2_0 0x000d9108
72
73#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
74#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
75#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
76
77#define OCTEON_CN68XX_PASS1 OCTEON_CN68XX_PASS1_X
78#define OCTEON_CN68XX_PASS2 OCTEON_CN68XX_PASS2_X
79
80#define OCTEON_CN66XX_PASS1_0 0x000d9200
81#define OCTEON_CN66XX_PASS1_2 0x000d9202
82
83#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
84#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
85
72#define OCTEON_CN63XX_PASS1_0 0x000d9000 86#define OCTEON_CN63XX_PASS1_0 0x000d9000
73#define OCTEON_CN63XX_PASS1_1 0x000d9001 87#define OCTEON_CN63XX_PASS1_1 0x000d9001
74#define OCTEON_CN63XX_PASS1_2 0x000d9002 88#define OCTEON_CN63XX_PASS1_2 0x000d9002
75#define OCTEON_CN63XX_PASS2_0 0x000d9008 89#define OCTEON_CN63XX_PASS2_0 0x000d9008
90#define OCTEON_CN63XX_PASS2_1 0x000d9009
91#define OCTEON_CN63XX_PASS2_2 0x000d900a
76 92
77#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) 93#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
78#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 94#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
79#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) 95#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
80 96
97#define OCTEON_CN61XX_PASS1_0 0x000d9300
98
99#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
100#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
101
81/* 102/*
82 * CN5XXX models with new revision encoding 103 * CN5XXX models with new revision encoding
83 */ 104 */
@@ -90,10 +111,8 @@
90#define OCTEON_CN58XX_PASS2_3 0x000d030b 111#define OCTEON_CN58XX_PASS2_3 0x000d030b
91 112
92#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) 113#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
93#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \ 114#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
94 | OM_IGNORE_MINOR_REVISION) 115#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
95#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
96 | OM_IGNORE_MINOR_REVISION)
97#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X 116#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
98#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X 117#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
99 118
@@ -103,10 +122,8 @@
103#define OCTEON_CN56XX_PASS2_1 0x000d0409 122#define OCTEON_CN56XX_PASS2_1 0x000d0409
104 123
105#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) 124#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
106#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \ 125#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
107 | OM_IGNORE_MINOR_REVISION) 126#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
108#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
109 | OM_IGNORE_MINOR_REVISION)
110#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X 127#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
111#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X 128#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
112 129
@@ -125,8 +142,7 @@
125#define OCTEON_CN50XX_PASS1_0 0x000d0600 142#define OCTEON_CN50XX_PASS1_0 0x000d0600
126 143
127#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) 144#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
128#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \ 145#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
129 | OM_IGNORE_MINOR_REVISION)
130#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X 146#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
131 147
132/* 148/*
@@ -138,10 +154,8 @@
138#define OCTEON_CN52XX_PASS2_0 0x000d0708 154#define OCTEON_CN52XX_PASS2_0 0x000d0708
139 155
140#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) 156#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
141#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \ 157#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
142 | OM_IGNORE_MINOR_REVISION) 158#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
143#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
144 | OM_IGNORE_MINOR_REVISION)
145#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X 159#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
146#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X 160#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
147 161
@@ -174,28 +188,23 @@
174#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) 188#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
175#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) 189#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
176#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) 190#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
177#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \ 191#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
178 | OM_CHECK_SUBMODEL)
179 192
180#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) 193#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
181#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) 194#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
182#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) 195#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
183#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \ 196#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
184 | OM_CHECK_SUBMODEL)
185 197
186#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) 198#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
187#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) 199#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
188#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) 200#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
189#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \ 201#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
190 | OM_CHECK_SUBMODEL)
191
192
193
194/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
195#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
196 | OM_MATCH_PREVIOUS_MODELS \
197 | OM_IGNORE_REVISION)
198 202
203/*
204 * This matches the complete family of CN3xxx CPUs, and not subsequent
205 * models
206 */
207#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
199#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) 208#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
200#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) 209#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
201 210
@@ -221,90 +230,55 @@
221#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 230#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
222#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f 231#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
223#define OCTEON_38XX_MODEL_MASK 0x00ffff10 232#define OCTEON_38XX_MODEL_MASK 0x00ffff10
224#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \ 233#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
225 | OCTEON_38XX_MODEL_MASK)
226 234
227/* CN5XXX and later use different layout of bits in the revision ID field */ 235/* CN5XXX and later use different layout of bits in the revision ID field */
228#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK 236#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
229#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f 237#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
230#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 238#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
231#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \ 239#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
232 | OCTEON_58XX_MODEL_MASK) 240#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
233#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
234 & 0x00fffff8)
235#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 241#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0
236 242
237#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
238
239/* NOTE: This is for internal (to this file) use only. */
240static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
241 uint32_t chip_model)
242{
243 uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
244
245 if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
246 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
247 __OCTEON_MATCH_MASK__(chip_model, arg_model,
248 OCTEON_38XX_MODEL_MASK))
249 return 1;
250 if (((arg_model & OM_FLAG_MASK) == 0) &&
251 __OCTEON_MATCH_MASK__(chip_model, arg_model,
252 OCTEON_38XX_FAMILY_REV_MASK))
253 return 1;
254 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
255 __OCTEON_MATCH_MASK__(chip_model, arg_model,
256 OCTEON_38XX_FAMILY_MASK))
257 return 1;
258 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
259 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
260 OCTEON_38XX_MODEL_REV_MASK))
261 return 1;
262 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
263 ((chip_model & OCTEON_38XX_MODEL_MASK) <
264 (arg_model & OCTEON_38XX_MODEL_MASK)))
265 return 1;
266 } else {
267 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
268 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
269 OCTEON_58XX_MODEL_MASK))
270 return 1;
271 if (((arg_model & OM_FLAG_MASK) == 0) &&
272 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
273 OCTEON_58XX_FAMILY_REV_MASK))
274 return 1;
275 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
276 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
277 OCTEON_58XX_MODEL_MINOR_REV_MASK))
278 return 1;
279 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
280 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
281 OCTEON_58XX_FAMILY_MASK))
282 return 1;
283 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
284 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
285 OCTEON_58XX_MODEL_REV_MASK))
286 return 1;
287
288 if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
289 ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
290 return 1;
291
292 if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
293 ((chip_model) >= OCTEON_CN63XX_PASS1_0))
294 return 1;
295
296 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
297 ((chip_model & OCTEON_58XX_MODEL_MASK) <
298 (arg_model & OCTEON_58XX_MODEL_MASK)))
299 return 1;
300 }
301 return 0;
302}
303
304/* forward declarations */ 243/* forward declarations */
305static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); 244static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
306static inline uint64_t cvmx_read_csr(uint64_t csr_addr); 245static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
307 246
247#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
248
249/* NOTE: This for internal use only! */
250#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \
251((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \
252 ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
253 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
254 ((((arg_model) & (OM_FLAG_MASK)) == 0) \
255 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
256 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
257 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
258 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
259 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
260 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
261 && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
262 )) || \
263 (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \
264 ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
265 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
266 ((((arg_model) & (OM_FLAG_MASK)) == 0) \
267 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
268 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
269 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
270 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
271 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
272 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
273 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
274 ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
275 && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
276 ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
277 && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
278 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
279 && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
280 )))
281
308/* NOTE: This for internal use only!!!!! */ 282/* NOTE: This for internal use only!!!!! */
309static inline int __octeon_is_model_runtime__(uint32_t model) 283static inline int __octeon_is_model_runtime__(uint32_t model)
310{ 284{
@@ -312,22 +286,25 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
312 286
313 /* 287 /*
314 * Check for special case of mismarked 3005 samples. We only 288 * Check for special case of mismarked 3005 samples. We only
315 * need to check if the sub model isn't being ignored. 289 * need to check if the sub model isn't being ignored
316 */ 290 */
317 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) { 291 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
318 if (cpuid == OCTEON_CN3010_PASS1 \ 292 if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
319 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
320 cpuid |= 0x10; 293 cpuid |= 0x10;
321 } 294 }
322 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); 295 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
323} 296}
324 297
325/* 298/*
326 * The OCTEON_IS_MODEL macro should be used for all Octeon model 299 * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
327 * checking done in a program. This should be kept runtime if at all 300 * in a program.
328 * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be 301 * This should be kept runtime if at all possible and must be conditionalized
329 * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking 302 * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
330 * support is required. 303 *
304 * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
305 * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
306 * I.e.:
307 * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
331 */ 308 */
332#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) 309#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
333#define OCTEON_IS_COMMON_BINARY() 1 310#define OCTEON_IS_COMMON_BINARY() 1
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index fba2ba200f5..c66734bd338 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -56,7 +56,8 @@ enum octeon_dma_bar_type {
56 OCTEON_DMA_BAR_TYPE_INVALID, 56 OCTEON_DMA_BAR_TYPE_INVALID,
57 OCTEON_DMA_BAR_TYPE_SMALL, 57 OCTEON_DMA_BAR_TYPE_SMALL,
58 OCTEON_DMA_BAR_TYPE_BIG, 58 OCTEON_DMA_BAR_TYPE_BIG,
59 OCTEON_DMA_BAR_TYPE_PCIE 59 OCTEON_DMA_BAR_TYPE_PCIE,
60 OCTEON_DMA_BAR_TYPE_PCIE2
60}; 61};
61 62
62/* 63/*
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e59cd1ac09c..d41790928c6 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -38,6 +38,14 @@
38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT) 38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
39#define HPAGE_MASK (~(HPAGE_SIZE - 1)) 39#define HPAGE_MASK (~(HPAGE_SIZE - 1))
40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
41#else /* !CONFIG_HUGETLB_PAGE */
42# ifndef BUILD_BUG
43# define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0)
44# endif
45#define HPAGE_SHIFT ({BUILD_BUG(); 0; })
46#define HPAGE_SIZE ({BUILD_BUG(); 0; })
47#define HPAGE_MASK ({BUILD_BUG(); 0; })
48#define HUGETLB_PAGE_ORDER ({BUILD_BUG(); 0; })
41#endif /* CONFIG_HUGETLB_PAGE */ 49#endif /* CONFIG_HUGETLB_PAGE */
42 50
43#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 8a153d2fa62..5d56bb23034 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -19,23 +19,7 @@
19#include <asm-generic/pgtable-nopmd.h> 19#include <asm-generic/pgtable-nopmd.h>
20 20
21/* 21/*
22 * - add_wired_entry() add a fixed TLB entry, and move wired register 22 * Basically we have the same two-level (which is the logical three level
23 */
24extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
25 unsigned long entryhi, unsigned long pagemask);
26
27/*
28 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
29 * starting at the top and working down. This is for populating the
30 * TLB before trap_init() puts the TLB miss handler in place. It
31 * should be used only for entries matching the actual page tables,
32 * to prevent inconsistencies.
33 */
34extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
35 unsigned long entryhi, unsigned long pagemask);
36
37
38/* Basically we have the same two-level (which is the logical three level
39 * Linux page table layout folded) page tables as the i386. Some day 23 * Linux page table layout folded) page tables as the i386. Some day
40 * when we have proper page coloring support we can have a 1% quicker 24 * when we have proper page coloring support we can have a 1% quicker
41 * tlb refill handling mechanism, but for now it is a bit slower but 25 * tlb refill handling mechanism, but for now it is a bit slower but
diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h
new file mode 100644
index 00000000000..3a452282cba
--- /dev/null
+++ b/arch/mips/include/asm/tlbmisc.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_TLBMISC_H
2#define __ASM_TLBMISC_H
3
4/*
5 * - add_wired_entry() add a fixed TLB entry, and move wired register
6 */
7extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
8 unsigned long entryhi, unsigned long pagemask);
9
10#endif /* __ASM_TLBMISC_H */
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 90ff2f497c5..ff74aec3561 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,5 +24,18 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
24extern void (*board_nmi_handler_setup)(void); 24extern void (*board_nmi_handler_setup)(void);
25extern void (*board_ejtag_handler_setup)(void); 25extern void (*board_ejtag_handler_setup)(void);
26extern void (*board_bind_eic_interrupt)(int irq, int regset); 26extern void (*board_bind_eic_interrupt)(int irq, int regset);
27extern void (*board_ebase_setup)(void);
28
29extern int register_nmi_notifier(struct notifier_block *nb);
30
31#define nmi_notifier(fn, pri) \
32({ \
33 static struct notifier_block fn##_nb = { \
34 .notifier_call = fn, \
35 .priority = pri \
36 }; \
37 \
38 register_nmi_notifier(&fn##_nb); \
39})
27 40
28#endif /* _ASM_TRAPS_H */ 41#endif /* _ASM_TRAPS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 15:18:35 -0400