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-rw-r--r--arch/mips/include/asm/atomic.h52
-rw-r--r--arch/mips/include/asm/compat.h7
-rw-r--r--arch/mips/include/asm/mach-rc32434/gpio.h5
-rw-r--r--arch/mips/include/asm/mach-rc32434/irq.h3
-rw-r--r--arch/mips/include/asm/mach-rc32434/rb.h3
-rw-r--r--arch/mips/include/asm/ptrace.h2
-rw-r--r--arch/mips/include/asm/seccomp.h1
-rw-r--r--arch/mips/include/asm/spinlock.h1
-rw-r--r--arch/mips/include/asm/termios.h100
-rw-r--r--arch/mips/include/asm/txx9/tx4939.h1
10 files changed, 115 insertions, 60 deletions
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index c996c3b4d07..1b332e15ab5 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -50,7 +50,7 @@
50static __inline__ void atomic_add(int i, atomic_t * v) 50static __inline__ void atomic_add(int i, atomic_t * v)
51{ 51{
52 if (cpu_has_llsc && R10000_LLSC_WAR) { 52 if (cpu_has_llsc && R10000_LLSC_WAR) {
53 unsigned long temp; 53 int temp;
54 54
55 __asm__ __volatile__( 55 __asm__ __volatile__(
56 " .set mips3 \n" 56 " .set mips3 \n"
@@ -62,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
62 : "=&r" (temp), "=m" (v->counter) 62 : "=&r" (temp), "=m" (v->counter)
63 : "Ir" (i), "m" (v->counter)); 63 : "Ir" (i), "m" (v->counter));
64 } else if (cpu_has_llsc) { 64 } else if (cpu_has_llsc) {
65 unsigned long temp; 65 int temp;
66 66
67 __asm__ __volatile__( 67 __asm__ __volatile__(
68 " .set mips3 \n" 68 " .set mips3 \n"
@@ -95,7 +95,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
95static __inline__ void atomic_sub(int i, atomic_t * v) 95static __inline__ void atomic_sub(int i, atomic_t * v)
96{ 96{
97 if (cpu_has_llsc && R10000_LLSC_WAR) { 97 if (cpu_has_llsc && R10000_LLSC_WAR) {
98 unsigned long temp; 98 int temp;
99 99
100 __asm__ __volatile__( 100 __asm__ __volatile__(
101 " .set mips3 \n" 101 " .set mips3 \n"
@@ -107,7 +107,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
107 : "=&r" (temp), "=m" (v->counter) 107 : "=&r" (temp), "=m" (v->counter)
108 : "Ir" (i), "m" (v->counter)); 108 : "Ir" (i), "m" (v->counter));
109 } else if (cpu_has_llsc) { 109 } else if (cpu_has_llsc) {
110 unsigned long temp; 110 int temp;
111 111
112 __asm__ __volatile__( 112 __asm__ __volatile__(
113 " .set mips3 \n" 113 " .set mips3 \n"
@@ -135,12 +135,12 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
135 */ 135 */
136static __inline__ int atomic_add_return(int i, atomic_t * v) 136static __inline__ int atomic_add_return(int i, atomic_t * v)
137{ 137{
138 unsigned long result; 138 int result;
139 139
140 smp_llsc_mb(); 140 smp_llsc_mb();
141 141
142 if (cpu_has_llsc && R10000_LLSC_WAR) { 142 if (cpu_has_llsc && R10000_LLSC_WAR) {
143 unsigned long temp; 143 int temp;
144 144
145 __asm__ __volatile__( 145 __asm__ __volatile__(
146 " .set mips3 \n" 146 " .set mips3 \n"
@@ -154,7 +154,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
154 : "Ir" (i), "m" (v->counter) 154 : "Ir" (i), "m" (v->counter)
155 : "memory"); 155 : "memory");
156 } else if (cpu_has_llsc) { 156 } else if (cpu_has_llsc) {
157 unsigned long temp; 157 int temp;
158 158
159 __asm__ __volatile__( 159 __asm__ __volatile__(
160 " .set mips3 \n" 160 " .set mips3 \n"
@@ -187,12 +187,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
187 187
188static __inline__ int atomic_sub_return(int i, atomic_t * v) 188static __inline__ int atomic_sub_return(int i, atomic_t * v)
189{ 189{
190 unsigned long result; 190 int result;
191 191
192 smp_llsc_mb(); 192 smp_llsc_mb();
193 193
194 if (cpu_has_llsc && R10000_LLSC_WAR) { 194 if (cpu_has_llsc && R10000_LLSC_WAR) {
195 unsigned long temp; 195 int temp;
196 196
197 __asm__ __volatile__( 197 __asm__ __volatile__(
198 " .set mips3 \n" 198 " .set mips3 \n"
@@ -206,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
206 : "Ir" (i), "m" (v->counter) 206 : "Ir" (i), "m" (v->counter)
207 : "memory"); 207 : "memory");
208 } else if (cpu_has_llsc) { 208 } else if (cpu_has_llsc) {
209 unsigned long temp; 209 int temp;
210 210
211 __asm__ __volatile__( 211 __asm__ __volatile__(
212 " .set mips3 \n" 212 " .set mips3 \n"
@@ -247,12 +247,12 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
247 */ 247 */
248static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 248static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
249{ 249{
250 unsigned long result; 250 int result;
251 251
252 smp_llsc_mb(); 252 smp_llsc_mb();
253 253
254 if (cpu_has_llsc && R10000_LLSC_WAR) { 254 if (cpu_has_llsc && R10000_LLSC_WAR) {
255 unsigned long temp; 255 int temp;
256 256
257 __asm__ __volatile__( 257 __asm__ __volatile__(
258 " .set mips3 \n" 258 " .set mips3 \n"
@@ -270,7 +270,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
270 : "Ir" (i), "m" (v->counter) 270 : "Ir" (i), "m" (v->counter)
271 : "memory"); 271 : "memory");
272 } else if (cpu_has_llsc) { 272 } else if (cpu_has_llsc) {
273 unsigned long temp; 273 int temp;
274 274
275 __asm__ __volatile__( 275 __asm__ __volatile__(
276 " .set mips3 \n" 276 " .set mips3 \n"
@@ -429,7 +429,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
429static __inline__ void atomic64_add(long i, atomic64_t * v) 429static __inline__ void atomic64_add(long i, atomic64_t * v)
430{ 430{
431 if (cpu_has_llsc && R10000_LLSC_WAR) { 431 if (cpu_has_llsc && R10000_LLSC_WAR) {
432 unsigned long temp; 432 long temp;
433 433
434 __asm__ __volatile__( 434 __asm__ __volatile__(
435 " .set mips3 \n" 435 " .set mips3 \n"
@@ -441,7 +441,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
441 : "=&r" (temp), "=m" (v->counter) 441 : "=&r" (temp), "=m" (v->counter)
442 : "Ir" (i), "m" (v->counter)); 442 : "Ir" (i), "m" (v->counter));
443 } else if (cpu_has_llsc) { 443 } else if (cpu_has_llsc) {
444 unsigned long temp; 444 long temp;
445 445
446 __asm__ __volatile__( 446 __asm__ __volatile__(
447 " .set mips3 \n" 447 " .set mips3 \n"
@@ -474,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
474static __inline__ void atomic64_sub(long i, atomic64_t * v) 474static __inline__ void atomic64_sub(long i, atomic64_t * v)
475{ 475{
476 if (cpu_has_llsc && R10000_LLSC_WAR) { 476 if (cpu_has_llsc && R10000_LLSC_WAR) {
477 unsigned long temp; 477 long temp;
478 478
479 __asm__ __volatile__( 479 __asm__ __volatile__(
480 " .set mips3 \n" 480 " .set mips3 \n"
@@ -486,7 +486,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
486 : "=&r" (temp), "=m" (v->counter) 486 : "=&r" (temp), "=m" (v->counter)
487 : "Ir" (i), "m" (v->counter)); 487 : "Ir" (i), "m" (v->counter));
488 } else if (cpu_has_llsc) { 488 } else if (cpu_has_llsc) {
489 unsigned long temp; 489 long temp;
490 490
491 __asm__ __volatile__( 491 __asm__ __volatile__(
492 " .set mips3 \n" 492 " .set mips3 \n"
@@ -514,12 +514,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
514 */ 514 */
515static __inline__ long atomic64_add_return(long i, atomic64_t * v) 515static __inline__ long atomic64_add_return(long i, atomic64_t * v)
516{ 516{
517 unsigned long result; 517 long result;
518 518
519 smp_llsc_mb(); 519 smp_llsc_mb();
520 520
521 if (cpu_has_llsc && R10000_LLSC_WAR) { 521 if (cpu_has_llsc && R10000_LLSC_WAR) {
522 unsigned long temp; 522 long temp;
523 523
524 __asm__ __volatile__( 524 __asm__ __volatile__(
525 " .set mips3 \n" 525 " .set mips3 \n"
@@ -533,7 +533,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
533 : "Ir" (i), "m" (v->counter) 533 : "Ir" (i), "m" (v->counter)
534 : "memory"); 534 : "memory");
535 } else if (cpu_has_llsc) { 535 } else if (cpu_has_llsc) {
536 unsigned long temp; 536 long temp;
537 537
538 __asm__ __volatile__( 538 __asm__ __volatile__(
539 " .set mips3 \n" 539 " .set mips3 \n"
@@ -566,12 +566,12 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
566 566
567static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 567static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
568{ 568{
569 unsigned long result; 569 long result;
570 570
571 smp_llsc_mb(); 571 smp_llsc_mb();
572 572
573 if (cpu_has_llsc && R10000_LLSC_WAR) { 573 if (cpu_has_llsc && R10000_LLSC_WAR) {
574 unsigned long temp; 574 long temp;
575 575
576 __asm__ __volatile__( 576 __asm__ __volatile__(
577 " .set mips3 \n" 577 " .set mips3 \n"
@@ -585,7 +585,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
585 : "Ir" (i), "m" (v->counter) 585 : "Ir" (i), "m" (v->counter)
586 : "memory"); 586 : "memory");
587 } else if (cpu_has_llsc) { 587 } else if (cpu_has_llsc) {
588 unsigned long temp; 588 long temp;
589 589
590 __asm__ __volatile__( 590 __asm__ __volatile__(
591 " .set mips3 \n" 591 " .set mips3 \n"
@@ -626,12 +626,12 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
626 */ 626 */
627static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 627static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
628{ 628{
629 unsigned long result; 629 long result;
630 630
631 smp_llsc_mb(); 631 smp_llsc_mb();
632 632
633 if (cpu_has_llsc && R10000_LLSC_WAR) { 633 if (cpu_has_llsc && R10000_LLSC_WAR) {
634 unsigned long temp; 634 long temp;
635 635
636 __asm__ __volatile__( 636 __asm__ __volatile__(
637 " .set mips3 \n" 637 " .set mips3 \n"
@@ -649,7 +649,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
649 : "Ir" (i), "m" (v->counter) 649 : "Ir" (i), "m" (v->counter)
650 : "memory"); 650 : "memory");
651 } else if (cpu_has_llsc) { 651 } else if (cpu_has_llsc) {
652 unsigned long temp; 652 long temp;
653 653
654 __asm__ __volatile__( 654 __asm__ __volatile__(
655 " .set mips3 \n" 655 " .set mips3 \n"
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index ac5d541368e..6c5b40905dd 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -3,6 +3,8 @@
3/* 3/*
4 * Architecture specific compatibility types 4 * Architecture specific compatibility types
5 */ 5 */
6#include <linux/seccomp.h>
7#include <linux/thread_info.h>
6#include <linux/types.h> 8#include <linux/types.h>
7#include <asm/page.h> 9#include <asm/page.h>
8#include <asm/ptrace.h> 10#include <asm/ptrace.h>
@@ -218,4 +220,9 @@ struct compat_shmid64_ds {
218 compat_ulong_t __unused2; 220 compat_ulong_t __unused2;
219}; 221};
220 222
223static inline int is_compat_task(void)
224{
225 return test_thread_flag(TIF_32BIT);
226}
227
221#endif /* _ASM_COMPAT_H */ 228#endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index b5cf6457305..3cb50d17b62 100644
--- a/arch/mips/include/asm/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -80,11 +80,8 @@ struct rb532_gpio_reg {
80/* Compact Flash GPIO pin */ 80/* Compact Flash GPIO pin */
81#define CF_GPIO_NUM 13 81#define CF_GPIO_NUM 13
82 82
83extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
84extern unsigned get_434_reg(unsigned reg_offs);
85extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
86extern unsigned char get_latch_u5(void);
87extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); 83extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
88extern void rb532_gpio_set_istat(int bit, unsigned gpio); 84extern void rb532_gpio_set_istat(int bit, unsigned gpio);
85extern void rb532_gpio_set_func(unsigned gpio);
89 86
90#endif /* _RC32434_GPIO_H_ */ 87#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
index 56738d8ec4e..023a5b100ed 100644
--- a/arch/mips/include/asm/mach-rc32434/irq.h
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -30,4 +30,7 @@
30#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) 30#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
31#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) 31#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
32 32
33#define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE
34#define GPIO_MAPPED_IRQ_GROUP 4
35
33#endif /* __ASM_RC32434_IRQ_H */ 36#endif /* __ASM_RC32434_IRQ_H */
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index f25a8491670..6dc5f8df1f3 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -83,4 +83,7 @@ struct mpmc_device {
83 void __iomem *base; 83 void __iomem *base;
84}; 84};
85 85
86extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
87extern unsigned char get_latch_u5(void);
88
86#endif /* __ASM_RC32434_RB_H */ 89#endif /* __ASM_RC32434_RB_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 1f30d16d466..ce47118e52b 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -105,7 +105,7 @@ struct pt_watch_regs {
105 enum pt_watch_style style; 105 enum pt_watch_style style;
106 union { 106 union {
107 struct mips32_watch_regs mips32; 107 struct mips32_watch_regs mips32;
108 struct mips32_watch_regs mips64; 108 struct mips64_watch_regs mips64;
109 }; 109 };
110}; 110};
111 111
diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h
index 36ed4407025..a6772e9507f 100644
--- a/arch/mips/include/asm/seccomp.h
+++ b/arch/mips/include/asm/seccomp.h
@@ -1,6 +1,5 @@
1#ifndef __ASM_SECCOMP_H 1#ifndef __ASM_SECCOMP_H
2 2
3#include <linux/thread_info.h>
4#include <linux/unistd.h> 3#include <linux/unistd.h>
5 4
6#define __NR_seccomp_read __NR_read 5#define __NR_seccomp_read __NR_read
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 1a1f320c30d..0884947ebe2 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -51,6 +51,7 @@ static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
51 51
52 return (((counters >> 14) - counters) & 0x1fff) > 1; 52 return (((counters >> 14) - counters) & 0x1fff) > 1;
53} 53}
54#define __raw_spin_is_contended __raw_spin_is_contended
54 55
55static inline void __raw_spin_lock(raw_spinlock_t *lock) 56static inline void __raw_spin_lock(raw_spinlock_t *lock)
56{ 57{
diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h
index a275661fa7e..8f77f774a2a 100644
--- a/arch/mips/include/asm/termios.h
+++ b/arch/mips/include/asm/termios.h
@@ -9,6 +9,7 @@
9#ifndef _ASM_TERMIOS_H 9#ifndef _ASM_TERMIOS_H
10#define _ASM_TERMIOS_H 10#define _ASM_TERMIOS_H
11 11
12#include <linux/errno.h>
12#include <asm/termbits.h> 13#include <asm/termbits.h>
13#include <asm/ioctls.h> 14#include <asm/ioctls.h>
14 15
@@ -94,38 +95,81 @@ struct termio {
94/* 95/*
95 * Translate a "termio" structure into a "termios". Ugh. 96 * Translate a "termio" structure into a "termios". Ugh.
96 */ 97 */
97#define user_termio_to_kernel_termios(termios, termio) \ 98static inline int user_termio_to_kernel_termios(struct ktermios *termios,
98({ \ 99 struct termio __user *termio)
99 unsigned short tmp; \ 100{
100 get_user(tmp, &(termio)->c_iflag); \ 101 unsigned short iflag, oflag, cflag, lflag;
101 (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ 102 unsigned int err;
102 get_user(tmp, &(termio)->c_oflag); \ 103
103 (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ 104 if (!access_ok(VERIFY_READ, termio, sizeof(struct termio)))
104 get_user(tmp, &(termio)->c_cflag); \ 105 return -EFAULT;
105 (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ 106
106 get_user(tmp, &(termio)->c_lflag); \ 107 err = __get_user(iflag, &termio->c_iflag);
107 (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ 108 termios->c_iflag = (termios->c_iflag & 0xffff0000) | iflag;
108 get_user((termios)->c_line, &(termio)->c_line); \ 109 err |=__get_user(oflag, &termio->c_oflag);
109 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ 110 termios->c_oflag = (termios->c_oflag & 0xffff0000) | oflag;
110}) 111 err |=__get_user(cflag, &termio->c_cflag);
112 termios->c_cflag = (termios->c_cflag & 0xffff0000) | cflag;
113 err |=__get_user(lflag, &termio->c_lflag);
114 termios->c_lflag = (termios->c_lflag & 0xffff0000) | lflag;
115 err |=__get_user(termios->c_line, &termio->c_line);
116 if (err)
117 return -EFAULT;
118
119 if (__copy_from_user(termios->c_cc, termio->c_cc, NCC))
120 return -EFAULT;
121
122 return 0;
123}
111 124
112/* 125/*
113 * Translate a "termios" structure into a "termio". Ugh. 126 * Translate a "termios" structure into a "termio". Ugh.
114 */ 127 */
115#define kernel_termios_to_user_termio(termio, termios) \ 128static inline int kernel_termios_to_user_termio(struct termio __user *termio,
116({ \ 129 struct ktermios *termios)
117 put_user((termios)->c_iflag, &(termio)->c_iflag); \ 130{
118 put_user((termios)->c_oflag, &(termio)->c_oflag); \ 131 int err;
119 put_user((termios)->c_cflag, &(termio)->c_cflag); \ 132
120 put_user((termios)->c_lflag, &(termio)->c_lflag); \ 133 if (!access_ok(VERIFY_WRITE, termio, sizeof(struct termio)))
121 put_user((termios)->c_line, &(termio)->c_line); \ 134 return -EFAULT;
122 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ 135
123}) 136 err = __put_user(termios->c_iflag, &termio->c_iflag);
124 137 err |= __put_user(termios->c_oflag, &termio->c_oflag);
125#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) 138 err |= __put_user(termios->c_cflag, &termio->c_cflag);
126#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) 139 err |= __put_user(termios->c_lflag, &termio->c_lflag);
127#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) 140 err |= __put_user(termios->c_line, &termio->c_line);
128#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) 141 if (err)
142 return -EFAULT;
143
144 if (__copy_to_user(termio->c_cc, termios->c_cc, NCC))
145 return -EFAULT;
146
147 return 0;
148}
149
150static inline int user_termios_to_kernel_termios(struct ktermios __user *k,
151 struct termios2 *u)
152{
153 return copy_from_user(k, u, sizeof(struct termios2)) ? -EFAULT : 0;
154}
155
156static inline int kernel_termios_to_user_termios(struct termios2 __user *u,
157 struct ktermios *k)
158{
159 return copy_to_user(u, k, sizeof(struct termios2)) ? -EFAULT : 0;
160}
161
162static inline int user_termios_to_kernel_termios_1(struct ktermios *k,
163 struct termios __user *u)
164{
165 return copy_from_user(k, u, sizeof(struct termios)) ? -EFAULT : 0;
166}
167
168static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
169 struct ktermios *k)
170{
171 return copy_to_user(u, k, sizeof(struct termios)) ? -EFAULT : 0;
172}
129 173
130#endif /* defined(__KERNEL__) */ 174#endif /* defined(__KERNEL__) */
131 175
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index 88badb42301..964ef7ede26 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -541,5 +541,6 @@ void tx4939_irq_init(void);
541int tx4939_irq(void); 541int tx4939_irq(void);
542void tx4939_mtd_init(int ch); 542void tx4939_mtd_init(int ch);
543void tx4939_ata_init(void); 543void tx4939_ata_init(void);
544void tx4939_rtc_init(void);
544 545
545#endif /* __ASM_TXX9_TX4939_H */ 546#endif /* __ASM_TXX9_TX4939_H */