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Diffstat (limited to 'arch/mips/include/asm/netlogic/xlr/pic.h')
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h67
1 files changed, 18 insertions, 49 deletions
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 9a691b1f91b..5cceb746f08 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,70 +193,39 @@
193/* end XLS */ 193/* end XLS */
194 194
195#ifndef __ASSEMBLY__ 195#ifndef __ASSEMBLY__
196 196static inline void pic_send_ipi(u32 ipi)
197#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
198 ((irq) <= PIC_TIMER_7_IRQ))
199#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
200 ((irq) <= PIC_IRT_LAST_IRQ))
201
202static inline int
203nlm_irq_to_irt(int irq)
204{
205 if (PIC_IRQ_IS_IRT(irq) == 0)
206 return -1;
207
208 return PIC_IRQ_TO_INTR(irq);
209}
210
211static inline int
212nlm_irt_to_irq(int irt)
213{ 197{
198 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
214 199
215 return PIC_INTR_TO_IRQ(irt); 200 netlogic_write_reg(mmio, PIC_IPI, ipi);
216} 201}
217 202
218static inline void 203static inline u32 pic_read_control(void)
219nlm_pic_enable_irt(uint64_t base, int irt)
220{ 204{
221 uint32_t reg; 205 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
222 206
223 reg = nlm_read_reg(base, PIC_IRT_1(irt)); 207 return netlogic_read_reg(mmio, PIC_CTRL);
224 nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
225} 208}
226 209
227static inline void 210static inline void pic_write_control(u32 control)
228nlm_pic_disable_irt(uint64_t base, int irt)
229{ 211{
230 uint32_t reg; 212 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
231 213
232 reg = nlm_read_reg(base, PIC_IRT_1(irt)); 214 netlogic_write_reg(mmio, PIC_CTRL, control);
233 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
234} 215}
235 216
236static inline void 217static inline void pic_update_control(u32 control)
237nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
238{ 218{
239 unsigned int tid, pid; 219 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
240 220
241 tid = hwt & 0x3; 221 netlogic_write_reg(mmio, PIC_CTRL,
242 pid = (hwt >> 2) & 0x07; 222 (control | netlogic_read_reg(mmio, PIC_CTRL)));
243 nlm_write_reg(base, PIC_IPI,
244 (pid << 20) | (tid << 16) | (nmi << 8) | irq);
245} 223}
246 224
247static inline void 225#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
248nlm_pic_ack(uint64_t base, int irt) 226 ((irq) <= PIC_TIMER_7_IRQ))
249{ 227#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
250 nlm_write_reg(base, PIC_INT_ACK, 1u << irt); 228 ((irq) <= PIC_IRT_LAST_IRQ))
251}
252
253static inline void
254nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
255{
256 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
257 /* local scheduling, invalid, level by default */
258 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq);
260}
261#endif 229#endif
230
262#endif /* _ASM_NLM_XLR_PIC_H */ 231#endif /* _ASM_NLM_XLR_PIC_H */