diff options
Diffstat (limited to 'arch/mips/include/asm/mach-powertv')
-rw-r--r-- | arch/mips/include/asm/mach-powertv/asic.h | 107 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-powertv/asic_regs.h | 155 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-powertv/dma-coherence.h | 119 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-powertv/interrupts.h | 254 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-powertv/ioremap.h | 90 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-powertv/irq.h | 25 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-powertv/powertv-clock.h | 29 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-powertv/war.h | 28 |
8 files changed, 807 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h new file mode 100644 index 00000000000..bcad43a93eb --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic.h | |||
@@ -0,0 +1,107 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Cisco Systems, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
17 | */ | ||
18 | |||
19 | #ifndef _ASM_MACH_POWERTV_ASIC_H | ||
20 | #define _ASM_MACH_POWERTV_ASIC_H | ||
21 | |||
22 | #include <linux/ioport.h> | ||
23 | #include <asm/mach-powertv/asic_regs.h> | ||
24 | |||
25 | #define DVR_CAPABLE (1<<0) | ||
26 | #define PCIE_CAPABLE (1<<1) | ||
27 | #define FFS_CAPABLE (1<<2) | ||
28 | #define DISPLAY_CAPABLE (1<<3) | ||
29 | |||
30 | /* Platform Family types | ||
31 | * For compitability, the new value must be added in the end */ | ||
32 | enum family_type { | ||
33 | FAMILY_8500, | ||
34 | FAMILY_8500RNG, | ||
35 | FAMILY_4500, | ||
36 | FAMILY_1500, | ||
37 | FAMILY_8600, | ||
38 | FAMILY_4600, | ||
39 | FAMILY_4600VZA, | ||
40 | FAMILY_8600VZB, | ||
41 | FAMILY_1500VZE, | ||
42 | FAMILY_1500VZF, | ||
43 | FAMILIES | ||
44 | }; | ||
45 | |||
46 | /* Register maps for each ASIC */ | ||
47 | extern const struct register_map calliope_register_map; | ||
48 | extern const struct register_map cronus_register_map; | ||
49 | extern const struct register_map zeus_register_map; | ||
50 | |||
51 | extern struct resource dvr_cronus_resources[]; | ||
52 | extern struct resource dvr_zeus_resources[]; | ||
53 | extern struct resource non_dvr_calliope_resources[]; | ||
54 | extern struct resource non_dvr_cronus_resources[]; | ||
55 | extern struct resource non_dvr_cronuslite_resources[]; | ||
56 | extern struct resource non_dvr_vz_calliope_resources[]; | ||
57 | extern struct resource non_dvr_vze_calliope_resources[]; | ||
58 | extern struct resource non_dvr_vzf_calliope_resources[]; | ||
59 | extern struct resource non_dvr_zeus_resources[]; | ||
60 | |||
61 | extern void powertv_platform_init(void); | ||
62 | extern void platform_alloc_bootmem(void); | ||
63 | extern enum asic_type platform_get_asic(void); | ||
64 | extern enum family_type platform_get_family(void); | ||
65 | extern int platform_supports_dvr(void); | ||
66 | extern int platform_supports_ffs(void); | ||
67 | extern int platform_supports_pcie(void); | ||
68 | extern int platform_supports_display(void); | ||
69 | extern void configure_platform(void); | ||
70 | extern void platform_configure_usb_ehci(void); | ||
71 | extern void platform_unconfigure_usb_ehci(void); | ||
72 | extern void platform_configure_usb_ohci(void); | ||
73 | extern void platform_unconfigure_usb_ohci(void); | ||
74 | |||
75 | /* Platform Resources */ | ||
76 | #define ASIC_RESOURCE_GET_EXISTS 1 | ||
77 | extern struct resource *asic_resource_get(const char *name); | ||
78 | extern void platform_release_memory(void *baddr, int size); | ||
79 | |||
80 | /* Reboot Cause */ | ||
81 | extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); | ||
82 | extern void set_locked_reboot_cause(char code, unsigned int data, | ||
83 | unsigned int data2); | ||
84 | |||
85 | enum sys_reboot_type { | ||
86 | sys_unknown_reboot = 0x00, /* Unknown reboot cause */ | ||
87 | sys_davic_change = 0x01, /* Reboot due to change in DAVIC | ||
88 | * mode */ | ||
89 | sys_user_reboot = 0x02, /* Reboot initiated by user */ | ||
90 | sys_system_reboot = 0x03, /* Reboot initiated by OS */ | ||
91 | sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ | ||
92 | sys_silent_reboot = 0x05, /* Silent reboot */ | ||
93 | sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ | ||
94 | sys_power_up_reboot = 0x07, /* Power on bootup. Older | ||
95 | * drivers may report as | ||
96 | * userReboot. */ | ||
97 | sys_code_change = 0x08, /* Reboot to take code change. | ||
98 | * Older drivers may report as | ||
99 | * userReboot. */ | ||
100 | sys_hardware_reset = 0x09, /* HW watchdog or front-panel | ||
101 | * reset button reset. Older | ||
102 | * drivers may report as | ||
103 | * userReboot. */ | ||
104 | sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ | ||
105 | }; | ||
106 | |||
107 | #endif /* _ASM_MACH_POWERTV_ASIC_H */ | ||
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h new file mode 100644 index 00000000000..9a65c93782f --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h | |||
@@ -0,0 +1,155 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Cisco Systems, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
17 | */ | ||
18 | |||
19 | #ifndef __ASM_MACH_POWERTV_ASIC_H_ | ||
20 | #define __ASM_MACH_POWERTV_ASIC_H_ | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | /* ASIC types */ | ||
24 | enum asic_type { | ||
25 | ASIC_UNKNOWN, | ||
26 | ASIC_ZEUS, | ||
27 | ASIC_CALLIOPE, | ||
28 | ASIC_CRONUS, | ||
29 | ASIC_CRONUSLITE, | ||
30 | ASICS | ||
31 | }; | ||
32 | |||
33 | /* hardcoded values read from Chip Version registers */ | ||
34 | #define CRONUS_10 0x0B4C1C20 | ||
35 | #define CRONUS_11 0x0B4C1C21 | ||
36 | #define CRONUSLITE_10 0x0B4C1C40 | ||
37 | |||
38 | #define NAND_FLASH_BASE 0x03000000 | ||
39 | #define ZEUS_IO_BASE 0x09000000 | ||
40 | #define CALLIOPE_IO_BASE 0x08000000 | ||
41 | #define CRONUS_IO_BASE 0x09000000 | ||
42 | #define ASIC_IO_SIZE 0x01000000 | ||
43 | |||
44 | /* Definitions for backward compatibility */ | ||
45 | #define UART1_INTSTAT uart1_intstat | ||
46 | #define UART1_INTEN uart1_inten | ||
47 | #define UART1_CONFIG1 uart1_config1 | ||
48 | #define UART1_CONFIG2 uart1_config2 | ||
49 | #define UART1_DIVISORHI uart1_divisorhi | ||
50 | #define UART1_DIVISORLO uart1_divisorlo | ||
51 | #define UART1_DATA uart1_data | ||
52 | #define UART1_STATUS uart1_status | ||
53 | |||
54 | /* ASIC register enumeration */ | ||
55 | struct register_map { | ||
56 | u32 eic_slow0_strt_add; | ||
57 | u32 eic_cfg_bits; | ||
58 | u32 eic_ready_status; | ||
59 | |||
60 | u32 chipver3; | ||
61 | u32 chipver2; | ||
62 | u32 chipver1; | ||
63 | u32 chipver0; | ||
64 | |||
65 | u32 uart1_intstat; | ||
66 | u32 uart1_inten; | ||
67 | u32 uart1_config1; | ||
68 | u32 uart1_config2; | ||
69 | u32 uart1_divisorhi; | ||
70 | u32 uart1_divisorlo; | ||
71 | u32 uart1_data; | ||
72 | u32 uart1_status; | ||
73 | |||
74 | u32 int_stat_3; | ||
75 | u32 int_stat_2; | ||
76 | u32 int_stat_1; | ||
77 | u32 int_stat_0; | ||
78 | u32 int_config; | ||
79 | u32 int_int_scan; | ||
80 | u32 ien_int_3; | ||
81 | u32 ien_int_2; | ||
82 | u32 ien_int_1; | ||
83 | u32 ien_int_0; | ||
84 | u32 int_level_3_3; | ||
85 | u32 int_level_3_2; | ||
86 | u32 int_level_3_1; | ||
87 | u32 int_level_3_0; | ||
88 | u32 int_level_2_3; | ||
89 | u32 int_level_2_2; | ||
90 | u32 int_level_2_1; | ||
91 | u32 int_level_2_0; | ||
92 | u32 int_level_1_3; | ||
93 | u32 int_level_1_2; | ||
94 | u32 int_level_1_1; | ||
95 | u32 int_level_1_0; | ||
96 | u32 int_level_0_3; | ||
97 | u32 int_level_0_2; | ||
98 | u32 int_level_0_1; | ||
99 | u32 int_level_0_0; | ||
100 | u32 int_docsis_en; | ||
101 | |||
102 | u32 mips_pll_setup; | ||
103 | u32 usb_fs; | ||
104 | u32 test_bus; | ||
105 | u32 crt_spare; | ||
106 | u32 usb2_ohci_int_mask; | ||
107 | u32 usb2_strap; | ||
108 | u32 ehci_hcapbase; | ||
109 | u32 ohci_hc_revision; | ||
110 | u32 bcm1_bs_lmi_steer; | ||
111 | u32 usb2_control; | ||
112 | u32 usb2_stbus_obc; | ||
113 | u32 usb2_stbus_mess_size; | ||
114 | u32 usb2_stbus_chunk_size; | ||
115 | |||
116 | u32 pcie_regs; | ||
117 | u32 tim_ch; | ||
118 | u32 tim_cl; | ||
119 | u32 gpio_dout; | ||
120 | u32 gpio_din; | ||
121 | u32 gpio_dir; | ||
122 | u32 watchdog; | ||
123 | u32 front_panel; | ||
124 | |||
125 | u32 register_maps; | ||
126 | }; | ||
127 | |||
128 | extern enum asic_type asic; | ||
129 | extern const struct register_map *register_map; | ||
130 | extern unsigned long asic_phy_base; /* Physical address of ASIC */ | ||
131 | extern unsigned long asic_base; /* Virtual address of ASIC */ | ||
132 | |||
133 | /* | ||
134 | * Macros to interface to registers through their ioremapped address | ||
135 | * asic_reg_offset Returns the offset of a given register from the start | ||
136 | * of the ASIC address space | ||
137 | * asic_reg_phys_addr Returns the physical address of the given register | ||
138 | * asic_reg_addr Returns the iomapped virtual address of the given | ||
139 | * register. | ||
140 | */ | ||
141 | #define asic_reg_offset(x) (register_map->x) | ||
142 | #define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x)) | ||
143 | #define asic_reg_addr(x) \ | ||
144 | ((unsigned int *) (asic_base + asic_reg_offset(x))) | ||
145 | |||
146 | /* | ||
147 | * The asic_reg macro is gone. It should be replaced by either asic_read or | ||
148 | * asic_write, as appropriate. | ||
149 | */ | ||
150 | |||
151 | #define asic_read(x) readl(asic_reg_addr(x)) | ||
152 | #define asic_write(v, x) writel(v, asic_reg_addr(x)) | ||
153 | |||
154 | extern void asic_irq_init(void); | ||
155 | #endif | ||
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h new file mode 100644 index 00000000000..5b8d5ebeb83 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h | |||
@@ -0,0 +1,119 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Version from mach-generic modified to support PowerTV port | ||
7 | * Portions Copyright (C) 2009 Cisco Systems, Inc. | ||
8 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H | ||
13 | #define __ASM_MACH_POWERTV_DMA_COHERENCE_H | ||
14 | |||
15 | #include <linux/sched.h> | ||
16 | #include <linux/version.h> | ||
17 | #include <linux/device.h> | ||
18 | #include <asm/mach-powertv/asic.h> | ||
19 | |||
20 | static inline bool is_kseg2(void *addr) | ||
21 | { | ||
22 | return (unsigned long)addr >= KSEG2; | ||
23 | } | ||
24 | |||
25 | static inline unsigned long virt_to_phys_from_pte(void *addr) | ||
26 | { | ||
27 | pgd_t *pgd; | ||
28 | pud_t *pud; | ||
29 | pmd_t *pmd; | ||
30 | pte_t *ptep, pte; | ||
31 | |||
32 | unsigned long virt_addr = (unsigned long)addr; | ||
33 | unsigned long phys_addr = 0UL; | ||
34 | |||
35 | /* get the page global directory. */ | ||
36 | pgd = pgd_offset_k(virt_addr); | ||
37 | |||
38 | if (!pgd_none(*pgd)) { | ||
39 | /* get the page upper directory */ | ||
40 | pud = pud_offset(pgd, virt_addr); | ||
41 | if (!pud_none(*pud)) { | ||
42 | /* get the page middle directory */ | ||
43 | pmd = pmd_offset(pud, virt_addr); | ||
44 | if (!pmd_none(*pmd)) { | ||
45 | /* get a pointer to the page table entry */ | ||
46 | ptep = pte_offset(pmd, virt_addr); | ||
47 | pte = *ptep; | ||
48 | /* check for a valid page */ | ||
49 | if (pte_present(pte)) { | ||
50 | /* get the physical address the page is | ||
51 | * refering to */ | ||
52 | phys_addr = (unsigned long) | ||
53 | page_to_phys(pte_page(pte)); | ||
54 | /* add the offset within the page */ | ||
55 | phys_addr |= (virt_addr & ~PAGE_MASK); | ||
56 | } | ||
57 | } | ||
58 | } | ||
59 | } | ||
60 | |||
61 | return phys_addr; | ||
62 | } | ||
63 | |||
64 | static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, | ||
65 | size_t size) | ||
66 | { | ||
67 | if (is_kseg2(addr)) | ||
68 | return phys_to_bus(virt_to_phys_from_pte(addr)); | ||
69 | else | ||
70 | return phys_to_bus(virt_to_phys(addr)); | ||
71 | } | ||
72 | |||
73 | static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, | ||
74 | struct page *page) | ||
75 | { | ||
76 | return phys_to_bus(page_to_phys(page)); | ||
77 | } | ||
78 | |||
79 | static inline unsigned long plat_dma_addr_to_phys(struct device *dev, | ||
80 | dma_addr_t dma_addr) | ||
81 | { | ||
82 | return bus_to_phys(dma_addr); | ||
83 | } | ||
84 | |||
85 | static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, | ||
86 | size_t size, enum dma_data_direction direction) | ||
87 | { | ||
88 | } | ||
89 | |||
90 | static inline int plat_dma_supported(struct device *dev, u64 mask) | ||
91 | { | ||
92 | /* | ||
93 | * we fall back to GFP_DMA when the mask isn't all 1s, | ||
94 | * so we can't guarantee allocations that must be | ||
95 | * within a tighter range than GFP_DMA.. | ||
96 | */ | ||
97 | if (mask < DMA_BIT_MASK(24)) | ||
98 | return 0; | ||
99 | |||
100 | return 1; | ||
101 | } | ||
102 | |||
103 | static inline void plat_extra_sync_for_device(struct device *dev) | ||
104 | { | ||
105 | return; | ||
106 | } | ||
107 | |||
108 | static inline int plat_dma_mapping_error(struct device *dev, | ||
109 | dma_addr_t dma_addr) | ||
110 | { | ||
111 | return 0; | ||
112 | } | ||
113 | |||
114 | static inline int plat_device_is_coherent(struct device *dev) | ||
115 | { | ||
116 | return 0; | ||
117 | } | ||
118 | |||
119 | #endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ | ||
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h new file mode 100644 index 00000000000..629a5741365 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/interrupts.h | |||
@@ -0,0 +1,254 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Cisco Systems, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
17 | */ | ||
18 | |||
19 | #ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ | ||
20 | #define _ASM_MACH_POWERTV_INTERRUPTS_H_ | ||
21 | |||
22 | /* | ||
23 | * Defines for all of the interrupt lines | ||
24 | */ | ||
25 | |||
26 | /* Definitions for backward compatibility */ | ||
27 | #define kIrq_Uart1 irq_uart1 | ||
28 | |||
29 | #define ibase 0 | ||
30 | |||
31 | /*------------- Register: int_stat_3 */ | ||
32 | /* 126 unused (bit 31) */ | ||
33 | #define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ | ||
34 | #define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ | ||
35 | #define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ | ||
36 | #define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ | ||
37 | #define irq_fdma_gp (ibase+122) /* FDMA GP Output */ | ||
38 | #define irq_mips_pic (ibase+121) /* MIPS Performance Counter | ||
39 | * Interrupt */ | ||
40 | #define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ | ||
41 | #define irq_memory_protect (ibase+119) /* Memory Protection Interrupt | ||
42 | * -- Ored by glue logic inside | ||
43 | * SPARC ILC (see | ||
44 | * INT_MEM_PROT_STAT, below, | ||
45 | * for individual interrupts) | ||
46 | */ | ||
47 | /* 118 unused (bit 22) */ | ||
48 | #define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by | ||
49 | * glue logic inside SPARC ILC | ||
50 | * (see INT_SBAG_STAT, below, | ||
51 | * for individual interrupts) */ | ||
52 | #define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ | ||
53 | #define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ | ||
54 | /* 114 unused (bit 18) */ | ||
55 | #define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- | ||
56 | * Ored by glue logic inside | ||
57 | * SPARC ILC (see | ||
58 | * INT_MAILBOX_STAT, below, for | ||
59 | * individual interrupts) */ | ||
60 | #define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ | ||
61 | #define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ | ||
62 | #define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse | ||
63 | * Status 3 */ | ||
64 | #define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse | ||
65 | * Status 3 */ | ||
66 | #define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 | ||
67 | * Interrupt */ | ||
68 | #define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 | ||
69 | * Interrupt */ | ||
70 | #define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE | ||
71 | * Interrupt */ | ||
72 | #define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 | ||
73 | * Interrupt */ | ||
74 | #define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 | ||
75 | * Interrupt */ | ||
76 | #define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE | ||
77 | * Interrupt */ | ||
78 | #define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ | ||
79 | #define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA | ||
80 | * Interrupt */ | ||
81 | #define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ | ||
82 | #define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ | ||
83 | #define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ | ||
84 | #define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ | ||
85 | #define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ | ||
86 | #define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ | ||
87 | /*------------- Register: int_stat_2 */ | ||
88 | #define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ | ||
89 | #define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ | ||
90 | #define irq_timer2 (ibase+93) /* Programmable Timer | ||
91 | * Interrupt 2 */ | ||
92 | #define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ | ||
93 | #define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ | ||
94 | #define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ | ||
95 | #define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ | ||
96 | #define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ | ||
97 | #define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ | ||
98 | #define irq_sata (ibase+87) /* SATA 1 Interrupt */ | ||
99 | #define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ | ||
100 | #define irq_dtcp (ibase+86) /* DTCP Interrupt */ | ||
101 | #define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ | ||
102 | /* 84 unused (bit 20) */ | ||
103 | /* 83 unused (bit 19) */ | ||
104 | /* 82 unused (bit 18) */ | ||
105 | #define irq_sata2 (ibase+81) /* SATA2 Interrupt */ | ||
106 | #define irq_uart2 (ibase+80) /* UART2 Interrupt */ | ||
107 | #define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 | ||
108 | * Host module) */ | ||
109 | #define irq_pod (ibase+78) /* POD Interrupt */ | ||
110 | #define irq_slave_usb (ibase+77) /* Slave USB */ | ||
111 | #define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ | ||
112 | #define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ | ||
113 | #define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ | ||
114 | #define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ | ||
115 | #define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ | ||
116 | #define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ | ||
117 | #define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ | ||
118 | #define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ | ||
119 | #define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ | ||
120 | /* 67 unused (bit 03) */ | ||
121 | /* 66 unused (bit 02) */ | ||
122 | /* 65 unused (bit 01) */ | ||
123 | /* 64 unused (bit 00) */ | ||
124 | /*------------- Register: int_stat_1 */ | ||
125 | /* 63 unused (bit 31) */ | ||
126 | /* 62 unused (bit 30) */ | ||
127 | /* 61 unused (bit 29) */ | ||
128 | /* 60 unused (bit 28) */ | ||
129 | /* 59 unused (bit 27) */ | ||
130 | /* 58 unused (bit 26) */ | ||
131 | /* 57 unused (bit 25) */ | ||
132 | /* 56 unused (bit 24) */ | ||
133 | #define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory | ||
134 | * Interrupt */ | ||
135 | #define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit | ||
136 | * Interrupt */ | ||
137 | #define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit | ||
138 | * Interrupt */ | ||
139 | #define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error | ||
140 | * Interrupt */ | ||
141 | #define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive | ||
142 | * Interrupt */ | ||
143 | #define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive | ||
144 | * Interrupt */ | ||
145 | #define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error | ||
146 | * Interrupt */ | ||
147 | #define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play | ||
148 | * Interrupt */ | ||
149 | #define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error | ||
150 | * Interrupt */ | ||
151 | #define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High | ||
152 | * (Chans 63-32) */ | ||
153 | #define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low | ||
154 | * (Chans 31-0) */ | ||
155 | #define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High | ||
156 | * (Chans 63-32) */ | ||
157 | #define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low | ||
158 | * (Chans 31-0) */ | ||
159 | #define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error | ||
160 | * Interrupt */ | ||
161 | #define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ | ||
162 | #define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready | ||
163 | * Interrupt */ | ||
164 | #define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ | ||
165 | #define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O | ||
166 | * Module */ | ||
167 | #define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O | ||
168 | * Module (ABE_intN) */ | ||
169 | #define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or | ||
170 | * Discontinuity 1 */ | ||
171 | #define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or | ||
172 | * Discontinuity 2 */ | ||
173 | #define irq_parse_peierr (ibase+34) /* PID Parser Error Detect | ||
174 | * (PEI) */ | ||
175 | #define irq_parse_cont_err (ibase+33) /* PID Parser continuity error | ||
176 | * detect */ | ||
177 | #define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ | ||
178 | /*------------- Register: int_stat_0 */ | ||
179 | #define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O | ||
180 | * Module */ | ||
181 | #define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O | ||
182 | * Module */ | ||
183 | #define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha | ||
184 | * (chan 3) Transmission | ||
185 | * Completed OK */ | ||
186 | #define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) | ||
187 | * Transmission Completed OK */ | ||
188 | #define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation | ||
189 | * (chan 1) Transmission | ||
190 | * Completed OK */ | ||
191 | #define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha | ||
192 | * (chan 3)Transmission | ||
193 | * completed with Errors. */ | ||
194 | #define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) | ||
195 | * Transmission completed with | ||
196 | * Errors. */ | ||
197 | #define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation | ||
198 | * (chan 1) Transmission | ||
199 | * completed with Errors */ | ||
200 | #define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha | ||
201 | * for N times. Aloha retry | ||
202 | * timeout for channel 3. */ | ||
203 | #define irq_timer1 (ibase+22) /* Programmable Timer | ||
204 | * Interrupt */ | ||
205 | #define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ | ||
206 | #define irq_i2c (ibase+20) /* I2C Module Interrupt */ | ||
207 | #define irq_spi (ibase+19) /* SPI Module Interrupt */ | ||
208 | #define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ | ||
209 | #define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or | ||
210 | * Splice Detect Interrupt */ | ||
211 | #define irq_se_micro (ibase+16) /* Secure Micro I/F Module | ||
212 | * Interrupt */ | ||
213 | #define irq_uart1 (ibase+15) /* UART Interrupt */ | ||
214 | #define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ | ||
215 | #define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ | ||
216 | #define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ | ||
217 | #define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ | ||
218 | #define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error | ||
219 | * Interrupt */ | ||
220 | /* 9 unused (bit 09) */ | ||
221 | /* 8 unused (bit 08) */ | ||
222 | #define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error | ||
223 | * Interrupt */ | ||
224 | #define irq_psilength_err (ibase+6) /* QAM PSI Length Error | ||
225 | * Interrupt */ | ||
226 | #define irq_esfforward (ibase+5) /* ESF Interrupt Mark From | ||
227 | * Forward Path Reference - | ||
228 | * every 3ms when forward Mbits | ||
229 | * and forward slot control | ||
230 | * bytes are updated. */ | ||
231 | #define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from | ||
232 | * Reverse Path Reference - | ||
233 | * delayed from forward mark by | ||
234 | * the ranging delay plus a | ||
235 | * fixed amount. When reverse | ||
236 | * Mbits and reverse slot | ||
237 | * control bytes are updated. | ||
238 | * Occurs every 3ms for 3.0M and | ||
239 | * 1.554 M upstream rates and | ||
240 | * every 6 ms for 256K upstream | ||
241 | * rate. */ | ||
242 | #define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on | ||
243 | * Channel 1. */ | ||
244 | #define irq_reservation (ibase+2) /* Partial (or Incremental) | ||
245 | * Reservation Message Completed | ||
246 | * or Slotted aloha verify for | ||
247 | * channel 1. */ | ||
248 | #define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify | ||
249 | * Interrupt or Reservation | ||
250 | * increment completed for | ||
251 | * channel 3. */ | ||
252 | #define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ | ||
253 | #endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ | ||
254 | |||
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h new file mode 100644 index 00000000000..e6276d5146e --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/ioremap.h | |||
@@ -0,0 +1,90 @@ | |||
1 | /* | ||
2 | * This program is free software; you can redistribute it and/or | ||
3 | * modify it under the terms of the GNU General Public License | ||
4 | * as published by the Free Software Foundation; either version | ||
5 | * 2 of the License, or (at your option) any later version. | ||
6 | * | ||
7 | * Portions Copyright (C) Cisco Systems, Inc. | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_POWERTV_IOREMAP_H | ||
10 | #define __ASM_MACH_POWERTV_IOREMAP_H | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | |||
14 | #define LOW_MEM_BOUNDARY_PHYS 0x20000000 | ||
15 | #define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1)) | ||
16 | |||
17 | /* | ||
18 | * The bus addresses are different than the physical addresses that | ||
19 | * the processor sees by an offset. This offset varies by ASIC | ||
20 | * version. Define a variable to hold the offset and some macros to | ||
21 | * make the conversion simpler. */ | ||
22 | extern unsigned long phys_to_bus_offset; | ||
23 | |||
24 | #ifdef CONFIG_HIGHMEM | ||
25 | #define MEM_GAP_PHYS 0x60000000 | ||
26 | /* | ||
27 | * TODO: We will use the hard code for conversion between physical and | ||
28 | * bus until the bootloader releases their device tree to us. | ||
29 | */ | ||
30 | #define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \ | ||
31 | ((x) + phys_to_bus_offset) : (x)) | ||
32 | #define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \ | ||
33 | ((x) - phys_to_bus_offset) : (x)) | ||
34 | #else | ||
35 | #define phys_to_bus(x) ((x) + phys_to_bus_offset) | ||
36 | #define bus_to_phys(x) ((x) - phys_to_bus_offset) | ||
37 | #endif | ||
38 | |||
39 | /* | ||
40 | * Determine whether the address we are given is for an ASIC device | ||
41 | * Params: addr Address to check | ||
42 | * Returns: Zero if the address is not for ASIC devices, non-zero | ||
43 | * if it is. | ||
44 | */ | ||
45 | static inline int asic_is_device_addr(phys_t addr) | ||
46 | { | ||
47 | return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK); | ||
48 | } | ||
49 | |||
50 | /* | ||
51 | * Determine whether the address we are given is external RAM mappable | ||
52 | * into KSEG1. | ||
53 | * Params: addr Address to check | ||
54 | * Returns: Zero if the address is not for external RAM and | ||
55 | */ | ||
56 | static inline int asic_is_lowmem_ram_addr(phys_t addr) | ||
57 | { | ||
58 | /* | ||
59 | * The RAM always starts at the following address in the processor's | ||
60 | * physical address space | ||
61 | */ | ||
62 | static const phys_t phys_ram_base = 0x10000000; | ||
63 | phys_t bus_ram_base; | ||
64 | |||
65 | bus_ram_base = phys_to_bus_offset + phys_ram_base; | ||
66 | |||
67 | return addr >= bus_ram_base && | ||
68 | addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base)); | ||
69 | } | ||
70 | |||
71 | /* | ||
72 | * Allow physical addresses to be fixed up to help peripherals located | ||
73 | * outside the low 32-bit range -- generic pass-through version. | ||
74 | */ | ||
75 | static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) | ||
76 | { | ||
77 | return phys_addr; | ||
78 | } | ||
79 | |||
80 | static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, | ||
81 | unsigned long flags) | ||
82 | { | ||
83 | return NULL; | ||
84 | } | ||
85 | |||
86 | static inline int plat_iounmap(const volatile void __iomem *addr) | ||
87 | { | ||
88 | return 0; | ||
89 | } | ||
90 | #endif /* __ASM_MACH_POWERTV_IOREMAP_H */ | ||
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h new file mode 100644 index 00000000000..4bd5d0c61a9 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/irq.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Cisco Systems, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
17 | */ | ||
18 | |||
19 | #ifndef _ASM_MACH_POWERTV_IRQ_H | ||
20 | #define _ASM_MACH_POWERTV_IRQ_H | ||
21 | #include <asm/mach-powertv/interrupts.h> | ||
22 | |||
23 | #define MIPS_CPU_IRQ_BASE ibase | ||
24 | #define NR_IRQS 127 | ||
25 | #endif | ||
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h new file mode 100644 index 00000000000..6f3e9a0fcf8 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Cisco Systems, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
17 | */ | ||
18 | /* | ||
19 | * Local definitions for the powertv PCI code | ||
20 | */ | ||
21 | |||
22 | #ifndef _POWERTV_PCI_POWERTV_PCI_H_ | ||
23 | #define _POWERTV_PCI_POWERTV_PCI_H_ | ||
24 | extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); | ||
25 | extern int asic_pcie_init(void); | ||
26 | extern int asic_pcie_init(void); | ||
27 | |||
28 | extern int log_level; | ||
29 | #endif | ||
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h new file mode 100644 index 00000000000..7ac05ecc512 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/war.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * This version for the PowerTV platform copied from the Malta version. | ||
7 | * | ||
8 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
9 | * Portions copyright (C) 2009 Cisco Systems, Inc. | ||
10 | */ | ||
11 | #ifndef __ASM_MACH_POWERTV_WAR_H | ||
12 | #define __ASM_MACH_POWERTV_WAR_H | ||
13 | |||
14 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
15 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
16 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
17 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
18 | #define BCM1250_M3_WAR 0 | ||
19 | #define SIBYTE_1956_WAR 0 | ||
20 | #define MIPS4K_ICACHE_REFILL_WAR 1 | ||
21 | #define MIPS_CACHE_SYNC_WAR 1 | ||
22 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
23 | #define RM9000_CDEX_SMP_WAR 0 | ||
24 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
25 | #define R10000_LLSC_WAR 0 | ||
26 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
27 | |||
28 | #endif /* __ASM_MACH_POWERTV_WAR_H */ | ||