6 files changed, 202 insertions, 4 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index cda1c8070b2..2f0becb4ec8 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
 #include <linux/bitops.h>
 
 #define AR71XX_APB_BASE         0x18000000
+#define AR71XX_EHCI_BASE        0x1b000000
+#define AR71XX_EHCI_SIZE        0x1000
+#define AR71XX_OHCI_BASE        0x1c000000
+#define AR71XX_OHCI_SIZE        0x1000
 #define AR71XX_SPI_BASE         0x1f000000
 #define AR71XX_SPI_SIZE         0x01000000
 
@@ -27,6 +31,8 @@
 #define AR71XX_DDR_CTRL_SIZE    0x100
 #define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
 #define AR71XX_UART_SIZE        0x100
+#define AR71XX_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE    0x100
 #define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
 #define AR71XX_GPIO_SIZE        0x100
 #define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
@@ -34,9 +40,26 @@
 #define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
 #define AR71XX_RESET_SIZE       0x100
 
+#define AR7240_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE    0x100
+#define AR7240_OHCI_BASE        0x1b000000
+#define AR7240_OHCI_SIZE        0x1000
+
+#define AR724X_EHCI_BASE        0x1b000000
+#define AR724X_EHCI_SIZE        0x1000
+
+#define AR913X_EHCI_BASE        0x1b000000
+#define AR913X_EHCI_SIZE        0x1000
 #define AR913X_WMAC_BASE        (AR71XX_APB_BASE + 0x000C0000)
 #define AR913X_WMAC_SIZE        0x30000
 
+#define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE        0x14
+#define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE        0x20000
+#define AR933X_EHCI_BASE        0x1b000000
+#define AR933X_EHCI_SIZE        0x1000
+
 /*
  * DDR_CTRL block
  */
@@ -63,6 +86,11 @@
 #define AR913X_DDR_REG_FLUSH_USB        0x84
 #define AR913X_DDR_REG_FLUSH_WMAC       0x88
 
+#define AR933X_DDR_REG_FLUSH_GE0        0x7c
+#define AR933X_DDR_REG_FLUSH_GE1        0x80
+#define AR933X_DDR_REG_FLUSH_USB        0x84
+#define AR933X_DDR_REG_FLUSH_WMAC       0x88
+
 /*
  * PLL block
  */
@@ -104,6 +132,30 @@
 #define AR913X_AHB_DIV_SHIFT            19
 #define AR913X_AHB_DIV_MASK             0x1
 
+#define AR933X_PLL_CPU_CONFIG_REG       0x00
+#define AR933X_PLL_CLOCK_CTRL_REG       0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS            BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ       0x00
+#define AR71XX_USB_CTRL_REG_CONFIG      0x04
+
 /*
  * RESET block
  */
@@ -130,6 +182,13 @@
 
 #define AR724X_RESET_REG_RESET_MODULE           0x1c
 
+#define AR933X_RESET_REG_RESET_MODULE           0x1c
+#define AR933X_RESET_REG_BOOTSTRAP              0xac
+
+#define MISC_INT_ETHSW                  BIT(12)
+#define MISC_INT_TIMER4                 BIT(10)
+#define MISC_INT_TIMER3                 BIT(9)
+#define MISC_INT_TIMER2                 BIT(8)
 #define MISC_INT_DMA                    BIT(7)
 #define MISC_INT_OHCI                   BIT(6)
 #define MISC_INT_PERFC                  BIT(5)
@@ -158,14 +217,29 @@
 #define AR71XX_RESET_PCI_BUS            BIT(1)
 #define AR71XX_RESET_PCI_CORE           BIT(0)
 
+#define AR7240_RESET_USB_HOST           BIT(5)
+#define AR7240_RESET_OHCI_DLL           BIT(3)
+
 #define AR724X_RESET_GE1_MDIO           BIT(23)
 #define AR724X_RESET_GE0_MDIO           BIT(22)
 #define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
 #define AR724X_RESET_PCIE_PHY           BIT(7)
 #define AR724X_RESET_PCIE               BIT(6)
-#define AR724X_RESET_OHCI_DLL           BIT(3)
+#define AR724X_RESET_USB_HOST           BIT(5)
+#define AR724X_RESET_USB_PHY            BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE    BIT(3)
 
 #define AR913X_RESET_AMBA2WMAC          BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE    BIT(10)
+#define AR913X_RESET_USB_HOST           BIT(5)
+#define AR913X_RESET_USB_PHY            BIT(4)
+
+#define AR933X_RESET_WMAC               BIT(11)
+#define AR933X_RESET_USB_HOST           BIT(5)
+#define AR933X_RESET_USB_PHY            BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE    BIT(3)
+
+#define AR933X_BOOTSTRAP_REF_CLK_40     BIT(0)
 
 #define REV_ID_MAJOR_MASK               0xfff0
 #define REV_ID_MAJOR_AR71XX             0x00a0
@@ -173,6 +247,8 @@
 #define REV_ID_MAJOR_AR7240             0x00c0
 #define REV_ID_MAJOR_AR7241             0x0100
 #define REV_ID_MAJOR_AR7242             0x1100
+#define REV_ID_MAJOR_AR9330             0x0110
+#define REV_ID_MAJOR_AR9331             0x1110
 
 #define AR71XX_REV_ID_MINOR_MASK        0x3
 #define AR71XX_REV_ID_MINOR_AR7130      0x0
@@ -187,6 +263,8 @@
 #define AR913X_REV_ID_REVISION_MASK     0x3
 #define AR913X_REV_ID_REVISION_SHIFT    2
 
+#define AR933X_REV_ID_REVISION_MASK     0x3
+
 #define AR724X_REV_ID_REVISION_MASK     0x3
 
 /*
@@ -229,5 +307,6 @@
 #define AR71XX_GPIO_COUNT               16
 #define AR724X_GPIO_COUNT               18
 #define AR913X_GPIO_COUNT               22
+#define AR933X_GPIO_COUNT               30
 
 #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 00000000000..52730555937
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,67 @@
+/*
+ *  Atheros AR933X UART defines
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __AR933X_UART_H
+#define __AR933X_UART_H
+
+#define AR933X_UART_REGS_SIZE           20
+#define AR933X_UART_FIFO_SIZE           16
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLOCK_REG           0x08
+#define AR933X_UART_INT_REG             0x0c
+#define AR933X_UART_INT_EN_REG          0x10
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+
+#define AR933X_UART_CS_PARITY_S         0
+#define AR933X_UART_CS_PARITY_M         0x3
+#define   AR933X_UART_CS_PARITY_NONE    0
+#define   AR933X_UART_CS_PARITY_ODD     1
+#define   AR933X_UART_CS_PARITY_EVEN    2
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define   AR933X_UART_CS_IF_MODE_NONE   0
+#define   AR933X_UART_CS_IF_MODE_DTE    1
+#define   AR933X_UART_CS_IF_MODE_DCE    2
+#define AR933X_UART_CS_FLOW_CTRL_S      4
+#define AR933X_UART_CS_FLOW_CTRL_M      0x3
+#define AR933X_UART_CS_DMA_EN           BIT(6)
+#define AR933X_UART_CS_TX_READY_ORIDE   BIT(7)
+#define AR933X_UART_CS_RX_READY_ORIDE   BIT(8)
+#define AR933X_UART_CS_TX_READY         BIT(9)
+#define AR933X_UART_CS_RX_BREAK         BIT(10)
+#define AR933X_UART_CS_TX_BREAK         BIT(11)
+#define AR933X_UART_CS_HOST_INT         BIT(12)
+#define AR933X_UART_CS_HOST_INT_EN      BIT(13)
+#define AR933X_UART_CS_TX_BUSY          BIT(14)
+#define AR933X_UART_CS_RX_BUSY          BIT(15)
+
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+#define AR933X_UART_CLOCK_SCALE_M       0xfff
+#define AR933X_UART_CLOCK_SCALE_S       16
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+
+#define AR933X_UART_INT_RX_VALID        BIT(0)
+#define AR933X_UART_INT_TX_READY        BIT(1)
+#define AR933X_UART_INT_RX_FRAMING_ERR  BIT(2)
+#define AR933X_UART_INT_RX_OFLOW_ERR    BIT(3)
+#define AR933X_UART_INT_TX_OFLOW_ERR    BIT(4)
+#define AR933X_UART_INT_RX_PARITY_ERR   BIT(5)
+#define AR933X_UART_INT_RX_BREAK_ON     BIT(6)
+#define AR933X_UART_INT_RX_BREAK_OFF    BIT(7)
+#define AR933X_UART_INT_RX_FULL         BIT(8)
+#define AR933X_UART_INT_TX_EMPTY        BIT(9)
+#define AR933X_UART_INT_ALLINTS         0x3ff
+
+#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
new file mode 100644
index 00000000000..6cb30f2b719
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
@@ -0,0 +1,18 @@
+/*
+ *  Platform data definition for Atheros AR933X UART
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR933X_UART_PLATFORM_H
+#define _AR933X_UART_PLATFORM_H
+
+struct ar933x_uart_platform_data {
+        unsigned        uartclk;
+};
+
+#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 6a9f168506f..6d0c6c9d562 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,10 +26,13 @@ enum ath79_soc_type {
         ATH79_SOC_AR7241,
         ATH79_SOC_AR7242,
         ATH79_SOC_AR9130,
-        ATH79_SOC_AR9132
+        ATH79_SOC_AR9132,
+        ATH79_SOC_AR9330,
+        ATH79_SOC_AR9331,
 };
 
 extern enum ath79_soc_type ath79_soc;
+extern unsigned int ath79_soc_rev;
 
 static inline int soc_is_ar71xx(void)
 {
@@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
                 ath79_soc == ATH79_SOC_AR9132);
 }
 
+static inline int soc_is_ar933x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9330 ||
+                ath79_soc == ATH79_SOC_AR9331);
+}
+
 extern void __iomem *ath79_ddr_base;
 extern void __iomem *ath79_pll_base;
 extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 189bc6eb9c1..519958fe4e3 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,10 @@
 #define __ASM_MACH_ATH79_IRQ_H
 
 #define MIPS_CPU_IRQ_BASE       0
-#define NR_IRQS                 16
+#define NR_IRQS                 40
 
 #define ATH79_MISC_IRQ_BASE     8
-#define ATH79_MISC_IRQ_COUNT    8
+#define ATH79_MISC_IRQ_COUNT    32
 
 #define ATH79_CPU_IRQ_IP2       (MIPS_CPU_IRQ_BASE + 2)
 #define ATH79_CPU_IRQ_USB       (MIPS_CPU_IRQ_BASE + 3)
@@ -30,6 +30,10 @@
 #define ATH79_MISC_IRQ_PERFC    (ATH79_MISC_IRQ_BASE + 5)
 #define ATH79_MISC_IRQ_OHCI     (ATH79_MISC_IRQ_BASE + 6)
 #define ATH79_MISC_IRQ_DMA      (ATH79_MISC_IRQ_BASE + 7)
+#define ATH79_MISC_IRQ_TIMER2   (ATH79_MISC_IRQ_BASE + 8)
+#define ATH79_MISC_IRQ_TIMER3   (ATH79_MISC_IRQ_BASE + 9)
+#define ATH79_MISC_IRQ_TIMER4   (ATH79_MISC_IRQ_BASE + 10)
+#define ATH79_MISC_IRQ_ETHSW    (ATH79_MISC_IRQ_BASE + 12)
 
 #include_next <irq.h>
 
diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 00000000000..454885fa30c
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
+/*
+ *  Atheros 724x PCI support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
+#define __ASM_MACH_ATH79_PCI_ATH724X_H
+
+struct ath724x_pci_data {
+        int irq;
+        void *pdata;
+};
+
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
+
+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */