diff options
Diffstat (limited to 'arch/mips/alchemy/devboards/db1x00')
-rw-r--r-- | arch/mips/alchemy/devboards/db1x00/Makefile | 8 | ||||
-rw-r--r-- | arch/mips/alchemy/devboards/db1x00/board_setup.c | 229 | ||||
-rw-r--r-- | arch/mips/alchemy/devboards/db1x00/platform.c | 316 |
3 files changed, 0 insertions, 553 deletions
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile deleted file mode 100644 index 613c0c0c8be..00000000000 --- a/arch/mips/alchemy/devboards/db1x00/Makefile +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | # | ||
2 | # Copyright 2000, 2008 MontaVista Software Inc. | ||
3 | # Author: MontaVista Software, Inc. <source@mvista.com> | ||
4 | # | ||
5 | # Makefile for the Alchemy Semiconductor DBAu1xx0 boards. | ||
6 | # | ||
7 | |||
8 | obj-y := board_setup.o platform.o | ||
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c deleted file mode 100644 index 7cd36e631f6..00000000000 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ /dev/null | |||
@@ -1,229 +0,0 @@ | |||
1 | /* | ||
2 | * | ||
3 | * BRIEF MODULE DESCRIPTION | ||
4 | * Alchemy Db1x00 board setup. | ||
5 | * | ||
6 | * Copyright 2000, 2008 MontaVista Software Inc. | ||
7 | * Author: MontaVista Software, Inc. <source@mvista.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | * | ||
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License along | ||
26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
28 | */ | ||
29 | |||
30 | #include <linux/gpio.h> | ||
31 | #include <linux/init.h> | ||
32 | #include <linux/interrupt.h> | ||
33 | #include <linux/pm.h> | ||
34 | |||
35 | #include <asm/mach-au1x00/au1000.h> | ||
36 | #include <asm/mach-au1x00/au1xxx_eth.h> | ||
37 | #include <asm/mach-db1x00/db1x00.h> | ||
38 | #include <asm/mach-db1x00/bcsr.h> | ||
39 | #include <asm/reboot.h> | ||
40 | |||
41 | #include <prom.h> | ||
42 | |||
43 | #ifdef CONFIG_MIPS_BOSPORUS | ||
44 | char irq_tab_alchemy[][5] __initdata = { | ||
45 | [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ | ||
46 | [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */ | ||
47 | [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ | ||
48 | }; | ||
49 | |||
50 | /* | ||
51 | * Micrel/Kendin 5 port switch attached to MAC0, | ||
52 | * MAC0 is associated with PHY address 5 (== WAN port) | ||
53 | * MAC1 is not associated with any PHY, since it's connected directly | ||
54 | * to the switch. | ||
55 | * no interrupts are used | ||
56 | */ | ||
57 | static struct au1000_eth_platform_data eth0_pdata = { | ||
58 | .phy_static_config = 1, | ||
59 | .phy_addr = 5, | ||
60 | }; | ||
61 | |||
62 | static void bosporus_power_off(void) | ||
63 | { | ||
64 | while (1) | ||
65 | asm volatile (".set mips3 ; wait ; .set mips0"); | ||
66 | } | ||
67 | |||
68 | const char *get_system_type(void) | ||
69 | { | ||
70 | return "Alchemy Bosporus Gateway Reference"; | ||
71 | } | ||
72 | #endif | ||
73 | |||
74 | |||
75 | #ifdef CONFIG_MIPS_MIRAGE | ||
76 | static void mirage_power_off(void) | ||
77 | { | ||
78 | alchemy_gpio_direction_output(210, 1); | ||
79 | } | ||
80 | |||
81 | const char *get_system_type(void) | ||
82 | { | ||
83 | return "Alchemy Mirage"; | ||
84 | } | ||
85 | #endif | ||
86 | |||
87 | |||
88 | #if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) | ||
89 | static void mips_softreset(void) | ||
90 | { | ||
91 | asm volatile ("jr\t%0" : : "r"(0xbfc00000)); | ||
92 | } | ||
93 | |||
94 | #else | ||
95 | |||
96 | const char *get_system_type(void) | ||
97 | { | ||
98 | return "Alchemy Db1x00"; | ||
99 | } | ||
100 | #endif | ||
101 | |||
102 | |||
103 | void __init board_setup(void) | ||
104 | { | ||
105 | unsigned long bcsr1, bcsr2; | ||
106 | |||
107 | bcsr1 = DB1000_BCSR_PHYS_ADDR; | ||
108 | bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS; | ||
109 | |||
110 | #ifdef CONFIG_MIPS_DB1000 | ||
111 | printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); | ||
112 | #endif | ||
113 | #ifdef CONFIG_MIPS_DB1500 | ||
114 | printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); | ||
115 | #endif | ||
116 | #ifdef CONFIG_MIPS_DB1100 | ||
117 | printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); | ||
118 | #endif | ||
119 | #ifdef CONFIG_MIPS_BOSPORUS | ||
120 | au1xxx_override_eth_cfg(0, ð0_pdata); | ||
121 | |||
122 | printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); | ||
123 | #endif | ||
124 | #ifdef CONFIG_MIPS_MIRAGE | ||
125 | printk(KERN_INFO "AMD Alchemy Mirage Board\n"); | ||
126 | #endif | ||
127 | #ifdef CONFIG_MIPS_DB1550 | ||
128 | printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); | ||
129 | |||
130 | bcsr1 = DB1550_BCSR_PHYS_ADDR; | ||
131 | bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS; | ||
132 | #endif | ||
133 | |||
134 | /* initialize board register space */ | ||
135 | bcsr_init(bcsr1, bcsr2); | ||
136 | |||
137 | #if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) | ||
138 | { | ||
139 | u32 pin_func; | ||
140 | |||
141 | /* Set IRFIRSEL instead of GPIO15 */ | ||
142 | pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; | ||
143 | au_writel(pin_func, SYS_PINFUNC); | ||
144 | /* Power off until the driver is in use */ | ||
145 | bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, | ||
146 | BCSR_RESETS_IRDA_MODE_OFF); | ||
147 | } | ||
148 | #endif | ||
149 | bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ | ||
150 | |||
151 | /* Enable GPIO[31:0] inputs */ | ||
152 | alchemy_gpio1_input_enable(); | ||
153 | |||
154 | #ifdef CONFIG_MIPS_MIRAGE | ||
155 | { | ||
156 | u32 pin_func; | ||
157 | |||
158 | /* GPIO[20] is output */ | ||
159 | alchemy_gpio_direction_output(20, 0); | ||
160 | |||
161 | /* Set GPIO[210:208] instead of SSI_0 */ | ||
162 | pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; | ||
163 | |||
164 | /* Set GPIO[215:211] for LEDs */ | ||
165 | pin_func |= 5 << 2; | ||
166 | |||
167 | /* Set GPIO[214:213] for more LEDs */ | ||
168 | pin_func |= 5 << 12; | ||
169 | |||
170 | /* Set GPIO[207:200] instead of PCMCIA/LCD */ | ||
171 | pin_func |= SYS_PF_LCD | SYS_PF_PC; | ||
172 | au_writel(pin_func, SYS_PINFUNC); | ||
173 | |||
174 | /* | ||
175 | * Enable speaker amplifier. This should | ||
176 | * be part of the audio driver. | ||
177 | */ | ||
178 | alchemy_gpio_direction_output(209, 1); | ||
179 | |||
180 | pm_power_off = mirage_power_off; | ||
181 | _machine_halt = mirage_power_off; | ||
182 | _machine_restart = (void(*)(char *))mips_softreset; | ||
183 | } | ||
184 | #endif | ||
185 | |||
186 | #ifdef CONFIG_MIPS_BOSPORUS | ||
187 | pm_power_off = bosporus_power_off; | ||
188 | _machine_halt = bosporus_power_off; | ||
189 | _machine_restart = (void(*)(char *))mips_softreset; | ||
190 | #endif | ||
191 | au_sync(); | ||
192 | } | ||
193 | |||
194 | static int __init db1x00_init_irq(void) | ||
195 | { | ||
196 | #if defined(CONFIG_MIPS_MIRAGE) | ||
197 | irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ | ||
198 | #elif defined(CONFIG_MIPS_DB1550) | ||
199 | irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | ||
200 | irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ | ||
201 | irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | ||
202 | irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | ||
203 | irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | ||
204 | irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | ||
205 | #elif defined(CONFIG_MIPS_DB1500) | ||
206 | irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | ||
207 | irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ | ||
208 | irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | ||
209 | irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | ||
210 | irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | ||
211 | irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | ||
212 | #elif defined(CONFIG_MIPS_DB1100) | ||
213 | irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | ||
214 | irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ | ||
215 | irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | ||
216 | irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | ||
217 | irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | ||
218 | irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | ||
219 | #elif defined(CONFIG_MIPS_DB1000) | ||
220 | irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | ||
221 | irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ | ||
222 | irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | ||
223 | irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | ||
224 | irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | ||
225 | irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | ||
226 | #endif | ||
227 | return 0; | ||
228 | } | ||
229 | arch_initcall(db1x00_init_irq); | ||
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c deleted file mode 100644 index 9e6b3d442ac..00000000000 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ /dev/null | |||
@@ -1,316 +0,0 @@ | |||
1 | /* | ||
2 | * DBAu1xxx board platform device registration | ||
3 | * | ||
4 | * Copyright (C) 2009 Manuel Lauss | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
19 | */ | ||
20 | |||
21 | #include <linux/init.h> | ||
22 | #include <linux/interrupt.h> | ||
23 | #include <linux/dma-mapping.h> | ||
24 | #include <linux/platform_device.h> | ||
25 | |||
26 | #include <asm/mach-au1x00/au1000.h> | ||
27 | #include <asm/mach-au1x00/au1000_dma.h> | ||
28 | #include <asm/mach-db1x00/bcsr.h> | ||
29 | #include "../platform.h" | ||
30 | |||
31 | struct pci_dev; | ||
32 | |||
33 | /* DB1xxx PCMCIA interrupt sources: | ||
34 | * CD0/1 GPIO0/3 | ||
35 | * STSCHG0/1 GPIO1/4 | ||
36 | * CARD0/1 GPIO2/5 | ||
37 | * Db1550: 0/1, 21/22, 3/5 | ||
38 | */ | ||
39 | |||
40 | #define DB1XXX_HAS_PCMCIA | ||
41 | #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) | ||
42 | |||
43 | #if defined(CONFIG_MIPS_DB1000) | ||
44 | #define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT | ||
45 | #define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT | ||
46 | #define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT | ||
47 | #define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT | ||
48 | #define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT | ||
49 | #define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT | ||
50 | #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ | ||
51 | #define BOARD_FLASH_WIDTH 4 /* 32-bits */ | ||
52 | #elif defined(CONFIG_MIPS_DB1100) | ||
53 | #define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT | ||
54 | #define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT | ||
55 | #define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT | ||
56 | #define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT | ||
57 | #define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT | ||
58 | #define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT | ||
59 | #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ | ||
60 | #define BOARD_FLASH_WIDTH 4 /* 32-bits */ | ||
61 | #elif defined(CONFIG_MIPS_DB1500) | ||
62 | #define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT | ||
63 | #define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT | ||
64 | #define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT | ||
65 | #define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT | ||
66 | #define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT | ||
67 | #define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT | ||
68 | #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ | ||
69 | #define BOARD_FLASH_WIDTH 4 /* 32-bits */ | ||
70 | #elif defined(CONFIG_MIPS_DB1550) | ||
71 | #define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT | ||
72 | #define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT | ||
73 | #define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT | ||
74 | #define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT | ||
75 | #define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT | ||
76 | #define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT | ||
77 | #define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ | ||
78 | #define BOARD_FLASH_WIDTH 4 /* 32-bits */ | ||
79 | #else | ||
80 | /* other board: no PCMCIA */ | ||
81 | #undef DB1XXX_HAS_PCMCIA | ||
82 | #undef F_SWAPPED | ||
83 | #define F_SWAPPED 0 | ||
84 | #if defined(CONFIG_MIPS_BOSPORUS) | ||
85 | #define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ | ||
86 | #define BOARD_FLASH_WIDTH 2 /* 16-bits */ | ||
87 | #elif defined(CONFIG_MIPS_MIRAGE) | ||
88 | #define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ | ||
89 | #define BOARD_FLASH_WIDTH 4 /* 32-bits */ | ||
90 | #endif | ||
91 | #endif | ||
92 | |||
93 | #ifdef CONFIG_PCI | ||
94 | #ifdef CONFIG_MIPS_DB1500 | ||
95 | static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) | ||
96 | { | ||
97 | if ((slot < 12) || (slot > 13) || pin == 0) | ||
98 | return -1; | ||
99 | if (slot == 12) | ||
100 | return (pin == 1) ? AU1500_PCI_INTA : 0xff; | ||
101 | if (slot == 13) { | ||
102 | switch (pin) { | ||
103 | case 1: return AU1500_PCI_INTA; | ||
104 | case 2: return AU1500_PCI_INTB; | ||
105 | case 3: return AU1500_PCI_INTC; | ||
106 | case 4: return AU1500_PCI_INTD; | ||
107 | } | ||
108 | } | ||
109 | return -1; | ||
110 | } | ||
111 | #endif | ||
112 | |||
113 | #ifdef CONFIG_MIPS_DB1550 | ||
114 | static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) | ||
115 | { | ||
116 | if ((slot < 11) || (slot > 13) || pin == 0) | ||
117 | return -1; | ||
118 | if (slot == 11) | ||
119 | return (pin == 1) ? AU1550_PCI_INTC : 0xff; | ||
120 | if (slot == 12) { | ||
121 | switch (pin) { | ||
122 | case 1: return AU1550_PCI_INTB; | ||
123 | case 2: return AU1550_PCI_INTC; | ||
124 | case 3: return AU1550_PCI_INTD; | ||
125 | case 4: return AU1550_PCI_INTA; | ||
126 | } | ||
127 | } | ||
128 | if (slot == 13) { | ||
129 | switch (pin) { | ||
130 | case 1: return AU1550_PCI_INTA; | ||
131 | case 2: return AU1550_PCI_INTB; | ||
132 | case 3: return AU1550_PCI_INTC; | ||
133 | case 4: return AU1550_PCI_INTD; | ||
134 | } | ||
135 | } | ||
136 | return -1; | ||
137 | } | ||
138 | #endif | ||
139 | |||
140 | #ifdef CONFIG_MIPS_BOSPORUS | ||
141 | static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) | ||
142 | { | ||
143 | if ((slot < 11) || (slot > 13) || pin == 0) | ||
144 | return -1; | ||
145 | if (slot == 12) | ||
146 | return (pin == 1) ? AU1500_PCI_INTA : 0xff; | ||
147 | if (slot == 11) { | ||
148 | switch (pin) { | ||
149 | case 1: return AU1500_PCI_INTA; | ||
150 | case 2: return AU1500_PCI_INTB; | ||
151 | default: return 0xff; | ||
152 | } | ||
153 | } | ||
154 | if (slot == 13) { | ||
155 | switch (pin) { | ||
156 | case 1: return AU1500_PCI_INTA; | ||
157 | case 2: return AU1500_PCI_INTB; | ||
158 | case 3: return AU1500_PCI_INTC; | ||
159 | case 4: return AU1500_PCI_INTD; | ||
160 | } | ||
161 | } | ||
162 | return -1; | ||
163 | } | ||
164 | #endif | ||
165 | |||
166 | #ifdef CONFIG_MIPS_MIRAGE | ||
167 | static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) | ||
168 | { | ||
169 | if ((slot < 11) || (slot > 13) || pin == 0) | ||
170 | return -1; | ||
171 | if (slot == 11) | ||
172 | return (pin == 1) ? AU1500_PCI_INTD : 0xff; | ||
173 | if (slot == 12) | ||
174 | return (pin == 3) ? AU1500_PCI_INTC : 0xff; | ||
175 | if (slot == 13) { | ||
176 | switch (pin) { | ||
177 | case 1: return AU1500_PCI_INTA; | ||
178 | case 2: return AU1500_PCI_INTB; | ||
179 | default: return 0xff; | ||
180 | } | ||
181 | } | ||
182 | return -1; | ||
183 | } | ||
184 | #endif | ||
185 | |||
186 | static struct resource alchemy_pci_host_res[] = { | ||
187 | [0] = { | ||
188 | .start = AU1500_PCI_PHYS_ADDR, | ||
189 | .end = AU1500_PCI_PHYS_ADDR + 0xfff, | ||
190 | .flags = IORESOURCE_MEM, | ||
191 | }, | ||
192 | }; | ||
193 | |||
194 | static struct alchemy_pci_platdata db1xxx_pci_pd = { | ||
195 | .board_map_irq = db1xxx_map_pci_irq, | ||
196 | }; | ||
197 | |||
198 | static struct platform_device db1xxx_pci_host_dev = { | ||
199 | .dev.platform_data = &db1xxx_pci_pd, | ||
200 | .name = "alchemy-pci", | ||
201 | .id = 0, | ||
202 | .num_resources = ARRAY_SIZE(alchemy_pci_host_res), | ||
203 | .resource = alchemy_pci_host_res, | ||
204 | }; | ||
205 | |||
206 | static int __init db15x0_pci_init(void) | ||
207 | { | ||
208 | return platform_device_register(&db1xxx_pci_host_dev); | ||
209 | } | ||
210 | /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ | ||
211 | arch_initcall(db15x0_pci_init); | ||
212 | #endif | ||
213 | |||
214 | #ifdef CONFIG_MIPS_DB1100 | ||
215 | static struct resource au1100_lcd_resources[] = { | ||
216 | [0] = { | ||
217 | .start = AU1100_LCD_PHYS_ADDR, | ||
218 | .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, | ||
219 | .flags = IORESOURCE_MEM, | ||
220 | }, | ||
221 | [1] = { | ||
222 | .start = AU1100_LCD_INT, | ||
223 | .end = AU1100_LCD_INT, | ||
224 | .flags = IORESOURCE_IRQ, | ||
225 | } | ||
226 | }; | ||
227 | |||
228 | static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); | ||
229 | |||
230 | static struct platform_device au1100_lcd_device = { | ||
231 | .name = "au1100-lcd", | ||
232 | .id = 0, | ||
233 | .dev = { | ||
234 | .dma_mask = &au1100_lcd_dmamask, | ||
235 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
236 | }, | ||
237 | .num_resources = ARRAY_SIZE(au1100_lcd_resources), | ||
238 | .resource = au1100_lcd_resources, | ||
239 | }; | ||
240 | #endif | ||
241 | |||
242 | static struct resource alchemy_ac97c_res[] = { | ||
243 | [0] = { | ||
244 | .start = AU1000_AC97_PHYS_ADDR, | ||
245 | .end = AU1000_AC97_PHYS_ADDR + 0xfff, | ||
246 | .flags = IORESOURCE_MEM, | ||
247 | }, | ||
248 | [1] = { | ||
249 | .start = DMA_ID_AC97C_TX, | ||
250 | .end = DMA_ID_AC97C_TX, | ||
251 | .flags = IORESOURCE_DMA, | ||
252 | }, | ||
253 | [2] = { | ||
254 | .start = DMA_ID_AC97C_RX, | ||
255 | .end = DMA_ID_AC97C_RX, | ||
256 | .flags = IORESOURCE_DMA, | ||
257 | }, | ||
258 | }; | ||
259 | |||
260 | static struct platform_device alchemy_ac97c_dev = { | ||
261 | .name = "alchemy-ac97c", | ||
262 | .id = -1, | ||
263 | .resource = alchemy_ac97c_res, | ||
264 | .num_resources = ARRAY_SIZE(alchemy_ac97c_res), | ||
265 | }; | ||
266 | |||
267 | static struct platform_device alchemy_ac97c_dma_dev = { | ||
268 | .name = "alchemy-pcm-dma", | ||
269 | .id = 0, | ||
270 | }; | ||
271 | |||
272 | static struct platform_device db1x00_codec_dev = { | ||
273 | .name = "ac97-codec", | ||
274 | .id = -1, | ||
275 | }; | ||
276 | |||
277 | static struct platform_device db1x00_audio_dev = { | ||
278 | .name = "db1000-audio", | ||
279 | }; | ||
280 | |||
281 | static int __init db1xxx_dev_init(void) | ||
282 | { | ||
283 | #ifdef DB1XXX_HAS_PCMCIA | ||
284 | db1x_register_pcmcia_socket( | ||
285 | AU1000_PCMCIA_ATTR_PHYS_ADDR, | ||
286 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, | ||
287 | AU1000_PCMCIA_MEM_PHYS_ADDR, | ||
288 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, | ||
289 | AU1000_PCMCIA_IO_PHYS_ADDR, | ||
290 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, | ||
291 | DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0, | ||
292 | /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0); | ||
293 | |||
294 | db1x_register_pcmcia_socket( | ||
295 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, | ||
296 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, | ||
297 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, | ||
298 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, | ||
299 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, | ||
300 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, | ||
301 | DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, | ||
302 | /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); | ||
303 | #endif | ||
304 | #ifdef CONFIG_MIPS_DB1100 | ||
305 | platform_device_register(&au1100_lcd_device); | ||
306 | #endif | ||
307 | db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); | ||
308 | |||
309 | platform_device_register(&db1x00_codec_dev); | ||
310 | platform_device_register(&alchemy_ac97c_dma_dev); | ||
311 | platform_device_register(&alchemy_ac97c_dev); | ||
312 | platform_device_register(&db1x00_audio_dev); | ||
313 | |||
314 | return 0; | ||
315 | } | ||
316 | device_initcall(db1xxx_dev_init); | ||