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-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c19
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c55
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c62
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c98
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c70
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h34
6 files changed, 52 insertions, 286 deletions
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index ccab4c689dc..c04df43f639 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -265,29 +265,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
265/* SPI flash chip (m25p64) */ 265/* SPI flash chip (m25p64) */
266static struct bfin5xx_spi_chip spi_flash_chip_info = { 266static struct bfin5xx_spi_chip spi_flash_chip_info = {
267 .enable_dma = 0, /* use dma transfer with this chip*/ 267 .enable_dma = 0, /* use dma transfer with this chip*/
268 .bits_per_word = 8,
269};
270#endif
271
272#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
273 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
274static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
275 .enable_dma = 0,
276 .bits_per_word = 16,
277}; 268};
278#endif 269#endif
279 270
280#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 271#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
281static struct bfin5xx_spi_chip mmc_spi_chip_info = { 272static struct bfin5xx_spi_chip mmc_spi_chip_info = {
282 .enable_dma = 0, 273 .enable_dma = 0,
283 .bits_per_word = 8,
284};
285#endif
286
287#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
288static struct bfin5xx_spi_chip spidev_chip_info = {
289 .enable_dma = 0,
290 .bits_per_word = 8,
291}; 274};
292#endif 275#endif
293 276
@@ -328,7 +311,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
328 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 311 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
329 .bus_num = 0, 312 .bus_num = 0,
330 .chip_select = 4, 313 .chip_select = 4,
331 .controller_data = &ad1836_spi_chip_info,
332 }, 314 },
333#endif 315#endif
334#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 316#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -347,7 +329,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
347 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 329 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
348 .bus_num = 0, 330 .bus_num = 0,
349 .chip_select = 1, 331 .chip_select = 1,
350 .controller_data = &spidev_chip_info,
351 }, 332 },
352#endif 333#endif
353}; 334};
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index c9d6dc88f0e..6400341cc23 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -354,40 +354,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
354/* SPI flash chip (m25p64) */ 354/* SPI flash chip (m25p64) */
355static struct bfin5xx_spi_chip spi_flash_chip_info = { 355static struct bfin5xx_spi_chip spi_flash_chip_info = {
356 .enable_dma = 0, /* use dma transfer with this chip*/ 356 .enable_dma = 0, /* use dma transfer with this chip*/
357 .bits_per_word = 8,
358};
359#endif
360
361#if defined(CONFIG_BFIN_SPI_ADC) \
362 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
363/* SPI ADC chip */
364static struct bfin5xx_spi_chip spi_adc_chip_info = {
365 .enable_dma = 1, /* use dma transfer with this chip*/
366 .bits_per_word = 16,
367};
368#endif
369
370#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
371 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
372static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
373 .enable_dma = 0,
374 .bits_per_word = 16,
375}; 357};
376#endif 358#endif
377 359
378#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 360#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
379static struct bfin5xx_spi_chip mmc_spi_chip_info = { 361static struct bfin5xx_spi_chip mmc_spi_chip_info = {
380 .enable_dma = 0, 362 .enable_dma = 0,
381 .bits_per_word = 8,
382}; 363};
383#endif 364#endif
384 365
385#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 366#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
386static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
387 .enable_dma = 0,
388 .bits_per_word = 16,
389};
390
391static const struct ad7877_platform_data bfin_ad7877_ts_info = { 367static const struct ad7877_platform_data bfin_ad7877_ts_info = {
392 .model = 7877, 368 .model = 7877,
393 .vref_delay_usecs = 50, /* internal, no capacitor */ 369 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -403,21 +379,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
403}; 379};
404#endif 380#endif
405 381
406#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
407 && defined(CONFIG_SND_SOC_WM8731_SPI)
408static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
409 .enable_dma = 0,
410 .bits_per_word = 16,
411};
412#endif
413
414#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
415static struct bfin5xx_spi_chip spidev_chip_info = {
416 .enable_dma = 0,
417 .bits_per_word = 8,
418};
419#endif
420
421static struct spi_board_info bfin_spi_board_info[] __initdata = { 382static struct spi_board_info bfin_spi_board_info[] __initdata = {
422#if defined(CONFIG_MTD_M25P80) \ 383#if defined(CONFIG_MTD_M25P80) \
423 || defined(CONFIG_MTD_M25P80_MODULE) 384 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -433,18 +394,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
433 }, 394 },
434#endif 395#endif
435 396
436#if defined(CONFIG_BFIN_SPI_ADC) \
437 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
438 {
439 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
440 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
441 .bus_num = 0, /* Framework bus number */
442 .chip_select = 1, /* Framework chip select. */
443 .platform_data = NULL, /* No spi_driver specific config */
444 .controller_data = &spi_adc_chip_info,
445 },
446#endif
447
448#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ 397#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
449 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 398 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
450 { 399 {
@@ -452,7 +401,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
452 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 401 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
453 .bus_num = 0, 402 .bus_num = 0,
454 .chip_select = 4, 403 .chip_select = 4,
455 .controller_data = &ad1836_spi_chip_info,
456 }, 404 },
457#endif 405#endif
458#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 406#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -473,7 +421,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
473 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 421 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
474 .bus_num = 0, 422 .bus_num = 0,
475 .chip_select = 2, 423 .chip_select = 2,
476 .controller_data = &spi_ad7877_chip_info,
477 }, 424 },
478#endif 425#endif
479#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ 426#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -483,7 +430,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
483 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 430 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
484 .bus_num = 0, 431 .bus_num = 0,
485 .chip_select = 5, 432 .chip_select = 5,
486 .controller_data = &spi_wm8731_chip_info,
487 .mode = SPI_MODE_0, 433 .mode = SPI_MODE_0,
488 }, 434 },
489#endif 435#endif
@@ -493,7 +439,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
493 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 439 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
494 .bus_num = 0, 440 .bus_num = 0,
495 .chip_select = 1, 441 .chip_select = 1,
496 .controller_data = &spidev_chip_info,
497 }, 442 },
498#endif 443#endif
499}; 444};
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index b7101aa6e3a..6dbb1b40376 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -253,32 +253,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
253/* SPI flash chip (sst25wf040) */ 253/* SPI flash chip (sst25wf040) */
254static struct bfin5xx_spi_chip spi_flash_chip_info = { 254static struct bfin5xx_spi_chip spi_flash_chip_info = {
255 .enable_dma = 0, /* use dma transfer with this chip*/ 255 .enable_dma = 0, /* use dma transfer with this chip*/
256 .bits_per_word = 8,
257};
258#endif
259
260#if defined(CONFIG_BFIN_SPI_ADC) \
261 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
262/* SPI ADC chip */
263static struct bfin5xx_spi_chip spi_adc_chip_info = {
264 .enable_dma = 1, /* use dma transfer with this chip*/
265 .bits_per_word = 16,
266}; 256};
267#endif 257#endif
268 258
269#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 259#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
270static struct bfin5xx_spi_chip mmc_spi_chip_info = { 260static struct bfin5xx_spi_chip mmc_spi_chip_info = {
271 .enable_dma = 0, 261 .enable_dma = 0,
272 .bits_per_word = 8,
273}; 262};
274#endif 263#endif
275 264
276#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 265#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
277static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
278 .enable_dma = 0,
279 .bits_per_word = 16,
280};
281
282static const struct ad7877_platform_data bfin_ad7877_ts_info = { 266static const struct ad7877_platform_data bfin_ad7877_ts_info = {
283 .model = 7877, 267 .model = 7877,
284 .vref_delay_usecs = 50, /* internal, no capacitor */ 268 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -311,35 +295,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
311}; 295};
312#endif 296#endif
313 297
314#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
315static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
316 .enable_dma = 0,
317 .bits_per_word = 16,
318};
319#endif
320
321#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
322 && defined(CONFIG_SND_SOC_WM8731_SPI)
323static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
324 .enable_dma = 0,
325 .bits_per_word = 16,
326};
327#endif
328
329#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
330static struct bfin5xx_spi_chip spidev_chip_info = {
331 .enable_dma = 0,
332 .bits_per_word = 8,
333};
334#endif
335
336#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
337static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
338 .enable_dma = 0,
339 .bits_per_word = 8,
340};
341#endif
342
343static struct spi_board_info bfin_spi_board_info[] __initdata = { 298static struct spi_board_info bfin_spi_board_info[] __initdata = {
344#if defined(CONFIG_MTD_M25P80) \ 299#if defined(CONFIG_MTD_M25P80) \
345 || defined(CONFIG_MTD_M25P80_MODULE) 300 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -355,18 +310,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
355 }, 310 },
356#endif 311#endif
357 312
358#if defined(CONFIG_BFIN_SPI_ADC) \
359 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
360 {
361 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
362 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
363 .bus_num = 0, /* Framework bus number */
364 .chip_select = 1, /* Framework chip select. */
365 .platform_data = NULL, /* No spi_driver specific config */
366 .controller_data = &spi_adc_chip_info,
367 },
368#endif
369
370#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 313#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
371 { 314 {
372 .modalias = "mmc_spi", 315 .modalias = "mmc_spi",
@@ -385,7 +328,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
385 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 328 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
386 .bus_num = 0, 329 .bus_num = 0,
387 .chip_select = 2, 330 .chip_select = 2,
388 .controller_data = &spi_ad7877_chip_info,
389 }, 331 },
390#endif 332#endif
391#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) 333#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -396,7 +338,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
396 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 338 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
397 .bus_num = 0, 339 .bus_num = 0,
398 .chip_select = 5, 340 .chip_select = 5,
399 .controller_data = &spi_ad7879_chip_info,
400 .mode = SPI_CPHA | SPI_CPOL, 341 .mode = SPI_CPHA | SPI_CPOL,
401 }, 342 },
402#endif 343#endif
@@ -407,7 +348,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
407 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 348 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
408 .bus_num = 0, 349 .bus_num = 0,
409 .chip_select = 5, 350 .chip_select = 5,
410 .controller_data = &spi_wm8731_chip_info,
411 .mode = SPI_MODE_0, 351 .mode = SPI_MODE_0,
412 }, 352 },
413#endif 353#endif
@@ -417,7 +357,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
417 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 357 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
418 .bus_num = 0, 358 .bus_num = 0,
419 .chip_select = 1, 359 .chip_select = 1,
420 .controller_data = &spidev_chip_info,
421 }, 360 },
422#endif 361#endif
423#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 362#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -426,7 +365,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
426 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 365 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
427 .bus_num = 0, 366 .bus_num = 0,
428 .chip_select = 1, 367 .chip_select = 1,
429 .controller_data = &lq035q1_spi_chip_info,
430 .mode = SPI_CPHA | SPI_CPOL, 368 .mode = SPI_CPHA | SPI_CPOL,
431 }, 369 },
432#endif 370#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index e67ac772066..4e9dc9cf824 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -409,6 +409,9 @@ static struct resource net2272_bfin_resources[] = {
409 .end = 0x20300000 + 0x100, 409 .end = 0x20300000 + 0x100,
410 .flags = IORESOURCE_MEM, 410 .flags = IORESOURCE_MEM,
411 }, { 411 }, {
412 .start = 1,
413 .flags = IORESOURCE_BUS,
414 }, {
412 .start = IRQ_PF7, 415 .start = IRQ_PF7,
413 .end = IRQ_PF7, 416 .end = IRQ_PF7,
414 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 417 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -448,40 +451,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
448/* SPI flash chip (m25p64) */ 451/* SPI flash chip (m25p64) */
449static struct bfin5xx_spi_chip spi_flash_chip_info = { 452static struct bfin5xx_spi_chip spi_flash_chip_info = {
450 .enable_dma = 0, /* use dma transfer with this chip*/ 453 .enable_dma = 0, /* use dma transfer with this chip*/
451 .bits_per_word = 8,
452};
453#endif
454
455#if defined(CONFIG_BFIN_SPI_ADC) \
456 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
457/* SPI ADC chip */
458static struct bfin5xx_spi_chip spi_adc_chip_info = {
459 .enable_dma = 1, /* use dma transfer with this chip*/
460 .bits_per_word = 16,
461};
462#endif
463
464#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
465 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
466static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
467 .enable_dma = 0,
468 .bits_per_word = 16,
469}; 454};
470#endif 455#endif
471 456
472#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 457#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
473static struct bfin5xx_spi_chip mmc_spi_chip_info = { 458static struct bfin5xx_spi_chip mmc_spi_chip_info = {
474 .enable_dma = 0, 459 .enable_dma = 0,
475 .bits_per_word = 8,
476}; 460};
477#endif 461#endif
478 462
479#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 463#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
480static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
481 .enable_dma = 0,
482 .bits_per_word = 16,
483};
484
485static const struct ad7877_platform_data bfin_ad7877_ts_info = { 464static const struct ad7877_platform_data bfin_ad7877_ts_info = {
486 .model = 7877, 465 .model = 7877,
487 .vref_delay_usecs = 50, /* internal, no capacitor */ 466 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -513,20 +492,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
513}; 492};
514#endif 493#endif
515 494
516#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
517static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
518 .enable_dma = 0,
519 .bits_per_word = 16,
520};
521#endif
522
523#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
524static struct bfin5xx_spi_chip spidev_chip_info = {
525 .enable_dma = 0,
526 .bits_per_word = 8,
527};
528#endif
529
530#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ 495#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
531 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 496 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
532 497
@@ -574,9 +539,25 @@ static struct resource bfin_snd_resources[][4] = {
574 BFIN_SND_RES(0), 539 BFIN_SND_RES(0),
575 BFIN_SND_RES(1), 540 BFIN_SND_RES(1),
576}; 541};
542#endif
577 543
578static struct platform_device bfin_pcm = { 544#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
579 .name = "bfin-pcm-audio", 545static struct platform_device bfin_i2s_pcm = {
546 .name = "bfin-i2s-pcm-audio",
547 .id = -1,
548};
549#endif
550
551#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
552static struct platform_device bfin_tdm_pcm = {
553 .name = "bfin-tdm-pcm-audio",
554 .id = -1,
555};
556#endif
557
558#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
559static struct platform_device bfin_ac97_pcm = {
560 .name = "bfin-ac97-pcm-audio",
580 .id = -1, 561 .id = -1,
581}; 562};
582#endif 563#endif
@@ -605,13 +586,6 @@ static struct platform_device bfin_tdm = {
605}; 586};
606#endif 587#endif
607 588
608#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
609static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
610 .enable_dma = 0,
611 .bits_per_word = 8,
612};
613#endif
614
615static struct spi_board_info bfin_spi_board_info[] __initdata = { 589static struct spi_board_info bfin_spi_board_info[] __initdata = {
616#if defined(CONFIG_MTD_M25P80) \ 590#if defined(CONFIG_MTD_M25P80) \
617 || defined(CONFIG_MTD_M25P80_MODULE) 591 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -627,18 +601,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
627 }, 601 },
628#endif 602#endif
629 603
630#if defined(CONFIG_BFIN_SPI_ADC) \
631 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
632 {
633 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
634 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
635 .bus_num = 0, /* Framework bus number */
636 .chip_select = 1, /* Framework chip select. */
637 .platform_data = NULL, /* No spi_driver specific config */
638 .controller_data = &spi_adc_chip_info,
639 },
640#endif
641
642#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ 604#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
643 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 605 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
644 { 606 {
@@ -647,7 +609,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
647 .bus_num = 0, 609 .bus_num = 0,
648 .chip_select = 4, 610 .chip_select = 4,
649 .platform_data = "ad1836", 611 .platform_data = "ad1836",
650 .controller_data = &ad1836_spi_chip_info,
651 .mode = SPI_MODE_3, 612 .mode = SPI_MODE_3,
652 }, 613 },
653#endif 614#endif
@@ -670,7 +631,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
670 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 631 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
671 .bus_num = 0, 632 .bus_num = 0,
672 .chip_select = 2, 633 .chip_select = 2,
673 .controller_data = &spi_ad7877_chip_info,
674 }, 634 },
675#endif 635#endif
676#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) 636#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -681,7 +641,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
681 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 641 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
682 .bus_num = 0, 642 .bus_num = 0,
683 .chip_select = 3, 643 .chip_select = 3,
684 .controller_data = &spi_ad7879_chip_info,
685 .mode = SPI_CPHA | SPI_CPOL, 644 .mode = SPI_CPHA | SPI_CPOL,
686 }, 645 },
687#endif 646#endif
@@ -691,7 +650,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
691 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 650 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
692 .bus_num = 0, 651 .bus_num = 0,
693 .chip_select = 1, 652 .chip_select = 1,
694 .controller_data = &spidev_chip_info,
695 }, 653 },
696#endif 654#endif
697#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 655#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -700,7 +658,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
700 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 658 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
701 .bus_num = 0, 659 .bus_num = 0,
702 .chip_select = 7, 660 .chip_select = 7,
703 .controller_data = &lq035q1_spi_chip_info,
704 .mode = SPI_CPHA | SPI_CPOL, 661 .mode = SPI_CPHA | SPI_CPOL,
705 }, 662 },
706#endif 663#endif
@@ -1276,9 +1233,16 @@ static struct platform_device *stamp_devices[] __initdata = {
1276 &ezkit_flash_device, 1233 &ezkit_flash_device,
1277#endif 1234#endif
1278 1235
1279#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ 1236#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1280 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 1237 &bfin_i2s_pcm,
1281 &bfin_pcm, 1238#endif
1239
1240#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1241 &bfin_tdm_pcm,
1242#endif
1243
1244#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1245 &bfin_ac97_pcm,
1282#endif 1246#endif
1283 1247
1284#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 1248#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 18d303dd562..ec4bc7429c9 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -314,29 +314,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
314/* SPI flash chip (m25p64) */ 314/* SPI flash chip (m25p64) */
315static struct bfin5xx_spi_chip spi_flash_chip_info = { 315static struct bfin5xx_spi_chip spi_flash_chip_info = {
316 .enable_dma = 0, /* use dma transfer with this chip*/ 316 .enable_dma = 0, /* use dma transfer with this chip*/
317 .bits_per_word = 8,
318};
319#endif
320
321#if defined(CONFIG_BFIN_SPI_ADC) \
322 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
323/* SPI ADC chip */
324static struct bfin5xx_spi_chip spi_adc_chip_info = {
325 .enable_dma = 0, /* use dma transfer with this chip*/
326/*
327 * tll6527m V1.0 does not support native spi slave selects
328 * hence DMA mode will not be useful since the ADC needs
329 * CS to toggle for each sample and cs_change_per_word
330 * seems to be removed from spi_bfin5xx.c
331 */
332 .bits_per_word = 16,
333}; 317};
334#endif 318#endif
335 319
336#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 320#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
337static struct bfin5xx_spi_chip mmc_spi_chip_info = { 321static struct bfin5xx_spi_chip mmc_spi_chip_info = {
338 .enable_dma = 0, 322 .enable_dma = 0,
339 .bits_per_word = 8,
340}; 323};
341#endif 324#endif
342 325
@@ -359,21 +342,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
359}; 342};
360#endif 343#endif
361 344
362#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
363 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
364static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
365 .enable_dma = 0,
366 .bits_per_word = 16,
367};
368#endif
369
370#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
371static struct bfin5xx_spi_chip spidev_chip_info = {
372 .enable_dma = 0,
373 .bits_per_word = 8,
374};
375#endif
376
377#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 345#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
378static struct platform_device bfin_i2s = { 346static struct platform_device bfin_i2s = {
379 .name = "bfin-i2s", 347 .name = "bfin-i2s",
@@ -382,24 +350,7 @@ static struct platform_device bfin_i2s = {
382}; 350};
383#endif 351#endif
384 352
385#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
386static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
387 .enable_dma = 0,
388 .bits_per_word = 8,
389};
390#endif
391
392#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE) 353#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
393static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
394 .enable_dma = 0,
395 .bits_per_word = 8,
396};
397
398static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
399 .enable_dma = 0,
400 .bits_per_word = 8,
401};
402
403#include <linux/spi/mcp23s08.h> 354#include <linux/spi/mcp23s08.h>
404static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = { 355static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
405 .chip[0].is_present = true, 356 .chip[0].is_present = true,
@@ -429,22 +380,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
429 }, 380 },
430#endif 381#endif
431 382
432#if defined(CONFIG_BFIN_SPI_ADC)
433 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
434 {
435 .modalias = "bfin_spi_adc",
436 /* Name of spi_driver for this device */
437 .max_speed_hz = 10000000,
438 /* max spi clock (SCK) speed in HZ */
439 .bus_num = 0, /* Framework bus number */
440 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
441 /* Framework chip select. */
442 .platform_data = NULL, /* No spi_driver specific config */
443 .controller_data = &spi_adc_chip_info,
444 .mode = SPI_MODE_0,
445 },
446#endif
447
448#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 383#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
449 { 384 {
450 .modalias = "mmc_spi", 385 .modalias = "mmc_spi",
@@ -470,7 +405,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
470 /* max spi clock (SCK) speed in HZ */ 405 /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0, 406 .bus_num = 0,
472 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS, 407 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
473 .controller_data = &spi_ad7879_chip_info,
474 .mode = SPI_CPHA | SPI_CPOL, 408 .mode = SPI_CPHA | SPI_CPOL,
475 }, 409 },
476#endif 410#endif
@@ -482,7 +416,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
482 .bus_num = 0, 416 .bus_num = 0,
483 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS, 417 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
484 .mode = SPI_CPHA | SPI_CPOL, 418 .mode = SPI_CPHA | SPI_CPOL,
485 .controller_data = &spidev_chip_info,
486 }, 419 },
487#endif 420#endif
488#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 421#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -491,7 +424,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
491 .max_speed_hz = 20000000, 424 .max_speed_hz = 20000000,
492 .bus_num = 0, 425 .bus_num = 0,
493 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS, 426 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
494 .controller_data = &lq035q1_spi_chip_info,
495 .mode = SPI_CPHA | SPI_CPOL, 427 .mode = SPI_CPHA | SPI_CPOL,
496 }, 428 },
497#endif 429#endif
@@ -502,7 +434,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
502 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 434 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
503 .bus_num = 0, 435 .bus_num = 0,
504 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS, 436 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
505 .controller_data = &spi_mcp23s08_sys_chip_info,
506 .mode = SPI_CPHA | SPI_CPOL, 437 .mode = SPI_CPHA | SPI_CPOL,
507 }, 438 },
508 { 439 {
@@ -511,7 +442,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
511 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 442 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
512 .bus_num = 0, 443 .bus_num = 0,
513 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS, 444 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
514 .controller_data = &spi_mcp23s08_usr_chip_info,
515 .mode = SPI_CPHA | SPI_CPOL, 445 .mode = SPI_CPHA | SPI_CPOL,
516 }, 446 },
517#endif 447#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index e66a7e89cd3..688470611e1 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -11,8 +11,8 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List 14 * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List 15 * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -57,7 +57,7 @@
57/* Incorrect Access of OTP_STATUS During otp_write() Function */ 57/* Incorrect Access of OTP_STATUS During otp_write() Function */
58#define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) 58#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
59/* Host DMA Boot Modes Are Not Functional */ 59/* Host DMA Boot Modes Are Not Functional */
60#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) 60#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
61/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 61/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
62#define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) 62#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
63/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 63/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
@@ -135,7 +135,7 @@
135/* Incorrect Default Internal Voltage Regulator Setting */ 135/* Incorrect Default Internal Voltage Regulator Setting */
136#define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) 136#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
137/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ 137/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
138#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) 138#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
139/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ 139/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
140#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) 140#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
141/* DEB2_URGENT Bit Not Functional */ 141/* DEB2_URGENT Bit Not Functional */
@@ -181,11 +181,11 @@
181/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 181/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
182#define ANOMALY_05000443 (1) 182#define ANOMALY_05000443 (1)
183/* The WURESET Bit in the SYSCR Register is not Functional */ 183/* The WURESET Bit in the SYSCR Register is not Functional */
184#define ANOMALY_05000445 (1) 184#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
185/* USB DMA Mode 1 Short Packet Data Corruption */ 185/* USB DMA Short Packet Data Corruption */
186#define ANOMALY_05000450 (1) 186#define ANOMALY_05000450 (1)
187/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ 187/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
188#define ANOMALY_05000451 (1) 188#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
189/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ 189/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
190#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) 190#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
191/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 191/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
@@ -198,19 +198,19 @@
198#define ANOMALY_05000461 (1) 198#define ANOMALY_05000461 (1)
199/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 199/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
200#define ANOMALY_05000462 (1) 200#define ANOMALY_05000462 (1)
201/* USB Rx DMA hang */ 201/* USB Rx DMA Hang */
202#define ANOMALY_05000465 (1) 202#define ANOMALY_05000465 (1)
203/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ 203/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
204#define ANOMALY_05000466 (1) 204#define ANOMALY_05000466 (1)
205/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 205/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
206#define ANOMALY_05000467 (1) 206#define ANOMALY_05000467 (1)
207/* PLL Latches Incorrect Settings During Reset */ 207/* PLL Latches Incorrect Settings During Reset */
208#define ANOMALY_05000469 (1) 208#define ANOMALY_05000469 (1)
209/* Incorrect Default MSEL Value in PLL_CTL */ 209/* Incorrect Default MSEL Value in PLL_CTL */
210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) 210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
211/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 211/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
212#define ANOMALY_05000473 (1) 212#define ANOMALY_05000473 (1)
213/* Possible Lockup Condition whem Modifying PLL from External Memory */ 213/* Possible Lockup Condition when Modifying PLL from External Memory */
214#define ANOMALY_05000475 (1) 214#define ANOMALY_05000475 (1)
215/* TESTSET Instruction Cannot Be Interrupted */ 215/* TESTSET Instruction Cannot Be Interrupted */
216#define ANOMALY_05000477 (1) 216#define ANOMALY_05000477 (1)
@@ -219,11 +219,19 @@
219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ 219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
220#define ANOMALY_05000483 (1) 220#define ANOMALY_05000483 (1)
221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) 222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
223/* The CODEC Zero-Cross Detect Feature is not Functional */ 223/* The CODEC Zero-Cross Detect Feature is not Functional */
224#define ANOMALY_05000487 (1) 224#define ANOMALY_05000487 (1)
225/* IFLUSH sucks at life */ 225/* SPI Master Boot Can Fail Under Certain Conditions */
226#define ANOMALY_05000490 (1)
227/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
226#define ANOMALY_05000491 (1) 228#define ANOMALY_05000491 (1)
229/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
230#define ANOMALY_05000494 (1)
231/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
232#define ANOMALY_05000498 (1)
233/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
234#define ANOMALY_05000501 (1)
227 235
228/* Anomalies that don't exist on this proc */ 236/* Anomalies that don't exist on this proc */
229#define ANOMALY_05000099 (0) 237#define ANOMALY_05000099 (0)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-10 09:04:59 -0400