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-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c521
1 files changed, 114 insertions, 407 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 2debc900e24..0e28f759573 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -20,445 +20,152 @@
20 * to the Free Software Foundation, Inc., 20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */ 22 */
23
23#include <linux/module.h> 24#include <linux/module.h>
24 25
25#include <asm/blackfin.h> 26#include <asm/blackfin.h>
26#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
27#include <asm/cplb.h> 28#include <asm/cplb.h>
28#include <asm/cplbinit.h> 29#include <asm/cplbinit.h>
30#include <asm/mem_map.h>
29 31
30#define CPLB_MEM CONFIG_MAX_MEM_SIZE 32struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
31 33struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
32/*
33* Number of required data CPLB switchtable entries
34* MEMSIZE / 4 (we mostly install 4M page size CPLBs
35* approx 16 for smaller 1MB page size CPLBs for allignment purposes
36* 1 for L1 Data Memory
37* possibly 1 for L2 Data Memory
38* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
39* 1 for ASYNC Memory
40*/
41#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
42 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
43
44/*
45* Number of required instruction CPLB switchtable entries
46* MEMSIZE / 4 (we mostly install 4M page size CPLBs
47* approx 12 for smaller 1MB page size CPLBs for allignment purposes
48* 1 for L1 Instruction Memory
49* possibly 1 for L2 Instruction Memory
50* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
51*/
52#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
53
54
55u_long icplb_table[MAX_CPLBS + 1];
56u_long dcplb_table[MAX_CPLBS + 1];
57
58#ifdef CONFIG_CPLB_SWITCH_TAB_L1
59# define PDT_ATTR __attribute__((l1_data))
60#else
61# define PDT_ATTR
62#endif
63
64u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
65u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
66 34
67#ifdef CONFIG_CPLB_INFO 35int first_switched_icplb PDT_ATTR;
68u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR; 36int first_switched_dcplb PDT_ATTR;
69u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
70#endif
71 37
72struct s_cplb { 38struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
73 struct cplb_tab init_i; 39struct cplb_boundary icplb_bounds[7] PDT_ATTR;
74 struct cplb_tab init_d;
75 struct cplb_tab switch_i;
76 struct cplb_tab switch_d;
77};
78 40
79#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) 41int icplb_nr_bounds PDT_ATTR;
80static struct cplb_desc cplb_data[] = { 42int dcplb_nr_bounds PDT_ATTR;
81 {
82 .start = 0,
83 .end = SIZE_1K,
84 .psize = SIZE_1K,
85 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
86 .i_conf = SDRAM_OOPS,
87 .d_conf = SDRAM_OOPS,
88#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
89 .valid = 1,
90#else
91 .valid = 0,
92#endif
93 .name = "Zero Pointer Guard Page",
94 },
95 {
96 .start = L1_CODE_START,
97 .end = L1_CODE_START + L1_CODE_LENGTH,
98 .psize = SIZE_4M,
99 .attr = INITIAL_T | SWITCH_T | I_CPLB,
100 .i_conf = L1_IMEMORY,
101 .d_conf = 0,
102 .valid = 1,
103 .name = "L1 I-Memory",
104 },
105 {
106 .start = L1_DATA_A_START,
107 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
108 .psize = SIZE_4M,
109 .attr = INITIAL_T | SWITCH_T | D_CPLB,
110 .i_conf = 0,
111 .d_conf = L1_DMEMORY,
112#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
113 .valid = 1,
114#else
115 .valid = 0,
116#endif
117 .name = "L1 D-Memory",
118 },
119 {
120 .start = 0,
121 .end = 0, /* dynamic */
122 .psize = 0,
123 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
124 .i_conf = SDRAM_IGENERIC,
125 .d_conf = SDRAM_DGENERIC,
126 .valid = 1,
127 .name = "Kernel Memory",
128 },
129 {
130 .start = 0, /* dynamic */
131 .end = 0, /* dynamic */
132 .psize = 0,
133 .attr = INITIAL_T | SWITCH_T | D_CPLB,
134 .i_conf = SDRAM_IGENERIC,
135 .d_conf = SDRAM_DNON_CHBL,
136 .valid = 1,
137 .name = "uClinux MTD Memory",
138 },
139 {
140 .start = 0, /* dynamic */
141 .end = 0, /* dynamic */
142 .psize = SIZE_1M,
143 .attr = INITIAL_T | SWITCH_T | D_CPLB,
144 .d_conf = SDRAM_DNON_CHBL,
145 .valid = 1,
146 .name = "Uncached DMA Zone",
147 },
148 {
149 .start = 0, /* dynamic */
150 .end = 0, /* dynamic */
151 .psize = 0,
152 .attr = SWITCH_T | D_CPLB,
153 .i_conf = 0, /* dynamic */
154 .d_conf = 0, /* dynamic */
155 .valid = 1,
156 .name = "Reserved Memory",
157 },
158 {
159 .start = ASYNC_BANK0_BASE,
160 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
161 .psize = 0,
162 .attr = SWITCH_T | D_CPLB,
163 .d_conf = SDRAM_EBIU,
164 .valid = 1,
165 .name = "Asynchronous Memory Banks",
166 },
167 {
168 .start = L2_START,
169 .end = L2_START + L2_LENGTH,
170 .psize = SIZE_1M,
171 .attr = SWITCH_T | I_CPLB | D_CPLB,
172 .i_conf = L2_IMEMORY,
173 .d_conf = L2_DMEMORY,
174 .valid = (L2_LENGTH > 0),
175 .name = "L2 Memory",
176 },
177 {
178 .start = BOOT_ROM_START,
179 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
180 .psize = SIZE_1M,
181 .attr = SWITCH_T | I_CPLB | D_CPLB,
182 .i_conf = SDRAM_IGENERIC,
183 .d_conf = SDRAM_DGENERIC,
184 .valid = 1,
185 .name = "On-Chip BootROM",
186 },
187};
188 43
189static u16 __init lock_kernel_check(u32 start, u32 end) 44void __init generate_cplb_tables_cpu(unsigned int cpu)
190{ 45{
191 if (start >= (u32)_end || end <= (u32)_stext) 46 int i_d, i_i;
192 return 0; 47 unsigned long addr;
193 48
194 /* This cplb block overlapped with kernel area. */ 49 struct cplb_entry *d_tbl = dcplb_tbl[cpu];
195 return IN_KERNEL; 50 struct cplb_entry *i_tbl = icplb_tbl[cpu];
196}
197 51
198static unsigned short __init 52 printk(KERN_INFO "NOMPU: setting up cplb tables\n");
199fill_cplbtab(struct cplb_tab *table,
200 unsigned long start, unsigned long end,
201 unsigned long block_size, unsigned long cplb_data)
202{
203 int i;
204 53
205 switch (block_size) { 54 i_d = i_i = 0;
206 case SIZE_4M:
207 i = 3;
208 break;
209 case SIZE_1M:
210 i = 2;
211 break;
212 case SIZE_4K:
213 i = 1;
214 break;
215 case SIZE_1K:
216 default:
217 i = 0;
218 break;
219 }
220
221 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
222
223 while ((start < end) && (table->pos < table->size)) {
224 55
225 table->tab[table->pos++] = start; 56 /* Set up the zero page. */
57 d_tbl[i_d].addr = 0;
58 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
226 59
227 if (lock_kernel_check(start, start + block_size) == IN_KERNEL) 60 /* Cover kernel memory with 4M pages. */
228 table->tab[table->pos++] = 61 addr = 0;
229 cplb_data | CPLB_LOCK | CPLB_DIRTY;
230 else
231 table->tab[table->pos++] = cplb_data;
232 62
233 start += block_size; 63 for (; addr < memory_start; addr += 4 * 1024 * 1024) {
64 d_tbl[i_d].addr = addr;
65 d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
66 i_tbl[i_i].addr = addr;
67 i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
234 } 68 }
235 return 0;
236}
237 69
238static unsigned short __init 70 /* Cover L1 memory. One 4M area for code and data each is enough. */
239close_cplbtab(struct cplb_tab *table) 71 if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
240{ 72 d_tbl[i_d].addr = L1_DATA_A_START;
241 73 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
242 while (table->pos < table->size) {
243
244 table->tab[table->pos++] = 0;
245 table->tab[table->pos++] = 0; /* !CPLB_VALID */
246 } 74 }
247 return 0; 75 i_tbl[i_i].addr = L1_CODE_START;
248} 76 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
249 77
250/* helper function */ 78 first_switched_dcplb = i_d;
251static void __init 79 first_switched_icplb = i_i;
252__fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
253{
254 if (cplb_data[i].psize) {
255 fill_cplbtab(t,
256 cplb_data[i].start,
257 cplb_data[i].end,
258 cplb_data[i].psize,
259 cplb_data[i].i_conf);
260 } else {
261#if defined(CONFIG_BFIN_ICACHE)
262 if (ANOMALY_05000263 && i == SDRAM_KERN) {
263 fill_cplbtab(t,
264 cplb_data[i].start,
265 cplb_data[i].end,
266 SIZE_4M,
267 cplb_data[i].i_conf);
268 } else
269#endif
270 {
271 fill_cplbtab(t,
272 cplb_data[i].start,
273 a_start,
274 SIZE_1M,
275 cplb_data[i].i_conf);
276 fill_cplbtab(t,
277 a_start,
278 a_end,
279 SIZE_4M,
280 cplb_data[i].i_conf);
281 fill_cplbtab(t, a_end,
282 cplb_data[i].end,
283 SIZE_1M,
284 cplb_data[i].i_conf);
285 }
286 }
287}
288 80
289static void __init 81 BUG_ON(first_switched_dcplb > MAX_CPLBS);
290__fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) 82 BUG_ON(first_switched_icplb > MAX_CPLBS);
291{ 83
292 if (cplb_data[i].psize) { 84 while (i_d < MAX_CPLBS)
293 fill_cplbtab(t, 85 d_tbl[i_d++].data = 0;
294 cplb_data[i].start, 86 while (i_i < MAX_CPLBS)
295 cplb_data[i].end, 87 i_tbl[i_i++].data = 0;
296 cplb_data[i].psize,
297 cplb_data[i].d_conf);
298 } else {
299 fill_cplbtab(t,
300 cplb_data[i].start,
301 a_start, SIZE_1M,
302 cplb_data[i].d_conf);
303 fill_cplbtab(t, a_start,
304 a_end, SIZE_4M,
305 cplb_data[i].d_conf);
306 fill_cplbtab(t, a_end,
307 cplb_data[i].end,
308 SIZE_1M,
309 cplb_data[i].d_conf);
310 }
311} 88}
312 89
313void __init generate_cplb_tables(void) 90void __init generate_cplb_tables_all(void)
314{ 91{
92 int i_d, i_i;
315 93
316 u16 i, j, process; 94 i_d = 0;
317 u32 a_start, a_end, as, ae, as_1m; 95 /* Normal RAM, including MTD FS. */
318
319 struct cplb_tab *t_i = NULL;
320 struct cplb_tab *t_d = NULL;
321 struct s_cplb cplb;
322
323 printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
324
325 cplb.init_i.size = MAX_CPLBS;
326 cplb.init_d.size = MAX_CPLBS;
327 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
328 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
329
330 cplb.init_i.pos = 0;
331 cplb.init_d.pos = 0;
332 cplb.switch_i.pos = 0;
333 cplb.switch_d.pos = 0;
334
335 cplb.init_i.tab = icplb_table;
336 cplb.init_d.tab = dcplb_table;
337 cplb.switch_i.tab = ipdt_table;
338 cplb.switch_d.tab = dpdt_table;
339
340 cplb_data[SDRAM_KERN].end = memory_end;
341
342#ifdef CONFIG_MTD_UCLINUX 96#ifdef CONFIG_MTD_UCLINUX
343 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start; 97 dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size;
344 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
345 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
346# if defined(CONFIG_ROMFS_FS)
347 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
348
349 /*
350 * The ROMFS_FS size is often not multiple of 1MB.
351 * This can cause multiple CPLB sets covering the same memory area.
352 * This will then cause multiple CPLB hit exceptions.
353 * Workaround: We ensure a contiguous memory area by extending the kernel
354 * memory section over the mtd section.
355 * For ROMFS_FS memory must be covered with ICPLBs anyways.
356 * So there is no difference between kernel and mtd memory setup.
357 */
358
359 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
360 cplb_data[SDRAM_RAM_MTD].valid = 0;
361
362# endif
363#else 98#else
364 cplb_data[SDRAM_RAM_MTD].valid = 0; 99 dcplb_bounds[i_d].eaddr = memory_end;
365#endif 100#endif
101 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
102 /* DMA uncached region. */
103 if (DMA_UNCACHED_REGION) {
104 dcplb_bounds[i_d].eaddr = _ramend;
105 dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
106 }
107 if (_ramend != physical_mem_end) {
108 /* Reserved memory. */
109 dcplb_bounds[i_d].eaddr = physical_mem_end;
110 dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
111 SDRAM_DGENERIC : SDRAM_DNON_CHBL);
112 }
113 /* Addressing hole up to the async bank. */
114 dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
115 dcplb_bounds[i_d++].data = 0;
116 /* ASYNC banks. */
117 dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
118 dcplb_bounds[i_d++].data = SDRAM_EBIU;
119 /* Addressing hole up to BootROM. */
120 dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
121 dcplb_bounds[i_d++].data = 0;
122 /* BootROM -- largest one should be less than 1 meg. */
123 dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
124 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
125 if (L2_LENGTH) {
126 /* Addressing hole up to L2 SRAM. */
127 dcplb_bounds[i_d].eaddr = L2_START;
128 dcplb_bounds[i_d++].data = 0;
129 /* L2 SRAM. */
130 dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
131 dcplb_bounds[i_d++].data = L2_DMEMORY;
132 }
133 dcplb_nr_bounds = i_d;
134 BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
366 135
367 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION; 136 i_i = 0;
368 cplb_data[SDRAM_DMAZ].end = _ramend; 137 /* Normal RAM, including MTD FS. */
369
370 cplb_data[RES_MEM].start = _ramend;
371 cplb_data[RES_MEM].end = physical_mem_end;
372
373 if (reserved_mem_dcache_on)
374 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
375 else
376 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
377
378 if (reserved_mem_icache_on)
379 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
380 else
381 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
382
383 for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
384 if (!cplb_data[i].valid)
385 continue;
386
387 as_1m = cplb_data[i].start % SIZE_1M;
388
389 /* We need to make sure all sections are properly 1M aligned
390 * However between Kernel Memory and the Kernel mtd section, depending on the
391 * rootfs size, there can be overlapping memory areas.
392 */
393
394 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
395#ifdef CONFIG_MTD_UCLINUX 138#ifdef CONFIG_MTD_UCLINUX
396 if (i == SDRAM_RAM_MTD) { 139 icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size;
397 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start) 140#else
398 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M; 141 icplb_bounds[i_i].eaddr = memory_end;
399 else
400 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
401 } else
402#endif 142#endif
403 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n", 143 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
404 cplb_data[i].name, cplb_data[i].start); 144 /* DMA uncached region. */
405 } 145 if (DMA_UNCACHED_REGION) {
406 146 icplb_bounds[i_i].eaddr = _ramend;
407 as = cplb_data[i].start % SIZE_4M; 147 icplb_bounds[i_i++].data = 0;
408 ae = cplb_data[i].end % SIZE_4M;
409
410 if (as)
411 a_start = cplb_data[i].start + (SIZE_4M - (as));
412 else
413 a_start = cplb_data[i].start;
414
415 a_end = cplb_data[i].end - ae;
416
417 for (j = INITIAL_T; j <= SWITCH_T; j++) {
418
419 switch (j) {
420 case INITIAL_T:
421 if (cplb_data[i].attr & INITIAL_T) {
422 t_i = &cplb.init_i;
423 t_d = &cplb.init_d;
424 process = 1;
425 } else
426 process = 0;
427 break;
428 case SWITCH_T:
429 if (cplb_data[i].attr & SWITCH_T) {
430 t_i = &cplb.switch_i;
431 t_d = &cplb.switch_d;
432 process = 1;
433 } else
434 process = 0;
435 break;
436 default:
437 process = 0;
438 break;
439 }
440
441 if (!process)
442 continue;
443 if (cplb_data[i].attr & I_CPLB)
444 __fill_code_cplbtab(t_i, i, a_start, a_end);
445
446 if (cplb_data[i].attr & D_CPLB)
447 __fill_data_cplbtab(t_d, i, a_start, a_end);
448 }
449 } 148 }
450 149 if (_ramend != physical_mem_end) {
451/* close tables */ 150 /* Reserved memory. */
452 151 icplb_bounds[i_i].eaddr = physical_mem_end;
453 close_cplbtab(&cplb.init_i); 152 icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
454 close_cplbtab(&cplb.init_d); 153 SDRAM_IGENERIC : SDRAM_INON_CHBL);
455 154 }
456 cplb.init_i.tab[cplb.init_i.pos] = -1; 155 /* Addressing hole up to BootROM. */
457 cplb.init_d.tab[cplb.init_d.pos] = -1; 156 icplb_bounds[i_i].eaddr = BOOT_ROM_START;
458 cplb.switch_i.tab[cplb.switch_i.pos] = -1; 157 icplb_bounds[i_i++].data = 0;
459 cplb.switch_d.tab[cplb.switch_d.pos] = -1; 158 /* BootROM -- largest one should be less than 1 meg. */
460 159 icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
160 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
161 if (L2_LENGTH) {
162 /* Addressing hole up to L2 SRAM, including the async bank. */
163 icplb_bounds[i_i].eaddr = L2_START;
164 icplb_bounds[i_i++].data = 0;
165 /* L2 SRAM. */
166 icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
167 icplb_bounds[i_i++].data = L2_IMEMORY;
168 }
169 icplb_nr_bounds = i_i;
170 BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
461} 171}
462
463#endif
464
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