264 files changed, 3521 insertions, 5020 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5b9f78b570e..44c16f06173 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -468,7 +468,7 @@ config ARCH_IXP4XX
 
 config ARCH_DOVE
         bool "Marvell Dove"
-        select CPU_V6K
+        select CPU_V7
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
@@ -694,7 +694,7 @@ config ARCH_S3C2410
           the Samsung SMDK2410 development board (and derivatives).
 
           Note, the S3C2416 and the S3C2450 are so close that they even share
-          the same SoC ID code. This means that there is no seperate machine
+          the same SoC ID code. This means that there is no separate machine
           directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
 
 config ARCH_S3C64XX
@@ -1540,7 +1540,6 @@ config HIGHMEM
 config HIGHPTE
         bool "Allocate 2nd-level pagetables from highmem"
         depends on HIGHMEM
-        depends on !OUTER_CACHE
 
 config HW_PERF_EVENTS
         bool "Enable hardware performance counter support for perf events"
@@ -2012,6 +2011,8 @@ source "kernel/power/Kconfig"
 
 config ARCH_SUSPEND_POSSIBLE
         depends on !ARCH_S5P64X0 && !ARCH_S5P6442
+        depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
+                CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
         def_bool y
 
 endmenu
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index 901e6dff843..2cef8e13f9f 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -34,7 +34,7 @@ config PROCESSOR_ID
           used instead of the auto-probing which utilizes the register.
 
 config REMAP_VECTORS_TO_RAM
-        bool 'Install vectors to the begining of RAM' if DRAM_BASE
+        bool 'Install vectors to the beginning of RAM' if DRAM_BASE
         depends on DRAM_BASE
         help
           The kernel needs to change the hardware exception vectors.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 494224a9b45..03d01d783e3 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -63,17 +63,6 @@ config DEBUG_USER
               8 - SIGSEGV faults
              16 - SIGBUS faults
 
-config DEBUG_ERRORS
-        bool "Verbose kernel error messages"
-        depends on DEBUG_KERNEL
-        help
-          This option controls verbose debugging information which can be
-          printed when the kernel detects an internal error. This debugging
-          information is useful to kernel hackers when tracking down problems,
-          but mostly meaningless to other people. It's safe to say Y unless
-          you are concerned with the code size or don't want to see these
-          messages.
-
 config DEBUG_STACK_USAGE
         bool "Enable stack utilization instrumentation"
         depends on DEBUG_KERNEL
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 8ebbb511c78..23aad072230 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -74,7 +74,7 @@ ZTEXTADDR	:= $(CONFIG_ZBOOT_ROM_TEXT)
 ZBSSADDR        := $(CONFIG_ZBOOT_ROM_BSS)
 else
 ZTEXTADDR       := 0
-ZBSSADDR        := ALIGN(4)
+ZBSSADDR        := ALIGN(8)
 endif
 
 SEDFLAGS        = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
@@ -98,8 +98,6 @@ endif
 ccflags-y := -fpic -fno-builtin
 asflags-y := -Wa,-march=all
 
-# Provide size of uncompressed kernel to the decompressor via a linker symbol.
-LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image)
 # Supply ZRELADDR to the decompressor via a linker symbol.
 ifneq ($(CONFIG_AUTO_ZRELADDR),y)
 LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
@@ -122,10 +120,23 @@ lib1funcs = $(obj)/lib1funcs.o
 $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
         $(call cmd,shipped)
 
+# We need to prevent any GOTOFF relocs being used with references
+# to symbols in the .bss section since we cannot relocate them
+# independently from the rest at run time.  This can be achieved by
+# ensuring that no private .bss symbols exist, as global symbols
+# always have a GOT entry which is what we need.
+# The .data section is already discarded by the linker script so no need
+# to bother about it here.
+check_for_bad_syms = \
+bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \
+[ -z "$$bad_syms" ] || \
+  ( echo "following symbols must have non local/private scope:" >&2; \
+    echo "$$bad_syms" >&2; rm -f $@; false )
+
 $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
                 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
         $(call if_changed,ld)
-        @:
+        @$(check_for_bad_syms)
 
 $(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE
         $(call if_changed,$(suffix_y))
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 4c72a97bc3e..07be5a2f830 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -44,7 +44,7 @@ extern void error(char *);
 #include "../../../../lib/decompress_unlzma.c"
 #endif
 
-void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
+int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
 {
-        decompress(input, len, NULL, NULL, output, NULL, error);
+        return decompress(input, len, NULL, NULL, output, NULL, error);
 }
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index adf583cd0c3..c363458a4e6 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -179,16 +179,29 @@ not_angel:
                 bl      cache_on
 
 restart:        adr     r0, LC0
-                ldmia   r0, {r1, r2, r3, r5, r6, r9, r11, r12}
-                ldr     sp, [r0, #32]
+                ldmia   r0, {r1, r2, r3, r6, r10, r11, r12}
+                ldr     sp, [r0, #28]
 
                 /*
                  * We might be running at a different address.  We need
                  * to fix up various pointers.
                  */
                 sub     r0, r0, r1              @ calculate the delta offset
-                add     r5, r5, r0              @ _start
                 add     r6, r6, r0              @ _edata
+                add     r10, r10, r0            @ inflated kernel size location
+
+                /*
+                 * The kernel build system appends the size of the
+                 * decompressed kernel at the end of the compressed data
+                 * in little-endian form.
+                 */
+                ldrb    r9, [r10, #0]
+                ldrb    lr, [r10, #1]
+                orr     r9, r9, lr, lsl #8
+                ldrb    lr, [r10, #2]
+                ldrb    r10, [r10, #3]
+                orr     r9, r9, lr, lsl #16
+                orr     r9, r9, r10, lsl #24
 
 #ifndef CONFIG_ZBOOT_ROM
                 /* malloc space is above the relocated stack (64k max) */
@@ -206,31 +219,40 @@ restart:	adr	r0, LC0
 /*
  * Check to see if we will overwrite ourselves.
  *   r4  = final kernel address
- *   r5  = start of this image
  *   r9  = size of decompressed image
  *   r10 = end of this image, including  bss/stack/malloc space if non XIP
  * We basically want:
- *   r4 >= r10 -> OK
- *   r4 + image length <= r5 -> OK
+ *   r4 - 16k page directory >= r10 -> OK
+ *   r4 + image length <= current position (pc) -> OK
  */
+                add     r10, r10, #16384
                 cmp     r4, r10
                 bhs     wont_overwrite
                 add     r10, r4, r9
-                cmp     r10, r5
+   ARM(         cmp     r10, pc         )
+ THUMB(         mov     lr, pc          )
+ THUMB(         cmp     r10, lr         )
                 bls     wont_overwrite
 
 /*
  * Relocate ourselves past the end of the decompressed kernel.
- *   r5  = start of this image
  *   r6  = _edata
  *   r10 = end of the decompressed kernel
  * Because we always copy ahead, we need to do it from the end and go
  * backward in case the source and destination overlap.
  */
-                /* Round up to next 256-byte boundary. */
-                add     r10, r10, #256
+                /*
+                 * Bump to the next 256-byte boundary with the size of
+                 * the relocation code added. This avoids overwriting
+                 * ourself when the offset is small.
+                 */
+                add     r10, r10, #((reloc_code_end - restart + 256) & ~255)
                 bic     r10, r10, #255
 
+                /* Get start of code we want to copy and align it down. */
+                adr     r5, restart
+                bic     r5, r5, #31
+
                 sub     r9, r6, r5              @ size to copy
                 add     r9, r9, #31             @ rounded up to a multiple
                 bic     r9, r9, #31             @ ... of 32 bytes
@@ -245,6 +267,11 @@ restart:	adr	r0, LC0
                 /* Preserve offset to relocated code. */
                 sub     r6, r9, r6
 
+#ifndef CONFIG_ZBOOT_ROM
+                /* cache_clean_flush may use the stack, so relocate it */
+                add     sp, sp, r6
+#endif
+
                 bl      cache_clean_flush
 
                 adr     r0, BSYM(restart)
@@ -333,12 +360,11 @@ not_relocated:	mov	r0, #0
 LC0:            .word   LC0                     @ r1
                 .word   __bss_start             @ r2
                 .word   _end                    @ r3
-                .word   _start                  @ r5
                 .word   _edata                  @ r6
-                .word   _image_size             @ r9
+                .word   input_data_end - 4      @ r10 (inflated size location)
                 .word   _got_start              @ r11
                 .word   _got_end                @ ip
-                .word   user_stack_end          @ sp
+                .word   .L_user_stack_end       @ sp
                 .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
@@ -735,12 +761,6 @@ proc_types:
                 W(b)    __armv4_mmu_cache_off
                 W(b)    __armv6_mmu_cache_flush
 
-                .word   0x560f5810              @ Marvell PJ4 ARMv6
-                .word   0xff0ffff0
-                W(b)    __armv4_mmu_cache_on
-                W(b)    __armv4_mmu_cache_off
-                W(b)    __armv6_mmu_cache_flush
-
                 .word   0x000f0000              @ new CPU Id
                 .word   0x000f0000
                 W(b)    __armv7_mmu_cache_on
@@ -1062,8 +1082,9 @@ memdump:	mov	r12, r0
 #endif
 
                 .ltorg
+reloc_code_end:
 
                 .align
                 .section ".stack", "aw", %nobits
-user_stack:     .space  4096
-user_stack_end:
+.L_user_stack:  .space  4096
+.L_user_stack_end:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 2df38263124..832d37236c5 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -26,8 +26,6 @@ unsigned int __machine_arch_type;
 #include <linux/linkage.h>
 #include <asm/string.h>
 
-#include <asm/unaligned.h>
-
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -139,13 +137,12 @@ void *memcpy(void *__dest, __const void *__src, size_t __n)
 }
 
 /*
- * gzip delarations
+ * gzip declarations
  */
 extern char input_data[];
 extern char input_data_end[];
 
 unsigned char *output_data;
-unsigned long output_ptr;
 
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
@@ -170,15 +167,15 @@ asmlinkage void __div0(void)
         error("Attempting division by 0!");
 }
 
-extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
+extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
 
 
-unsigned long
+void
 decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
                 unsigned long free_mem_ptr_end_p,
                 int arch_id)
 {
-        unsigned char *tmp;
+        int ret;
 
         output_data             = (unsigned char *)output_start;
         free_mem_ptr            = free_mem_ptr_p;
@@ -187,12 +184,11 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
 
         arch_decomp_setup();
 
-        tmp = (unsigned char *) (((unsigned long)input_data_end) - 4);
-        output_ptr = get_unaligned_le32(tmp);
-
         putstr("Uncompressing Linux...");
-        do_decompress(input_data, input_data_end - input_data,
-                        output_data, error);
-        putstr(" done, booting the kernel.\n");
-        return output_ptr;
+        ret = do_decompress(input_data, input_data_end - input_data,
+                            output_data, error);
+        if (ret)
+                error("decompressor returned an error");
+        else
+                putstr(" done, booting the kernel.\n");
 }
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index 5309909d728..ea80abe7884 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -54,6 +54,7 @@ SECTIONS
   .bss                  : { *(.bss) }
   _end = .;
 
+  . = ALIGN(8);         /* the stack must be 64-bit aligned */
   .stack                : { *(.stack) }
 
   .stab 0               : { *(.stab) }
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e7521bca2c3..6ea9b6f3607 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -16,5 +16,4 @@ obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
 obj-$(CONFIG_ARCH_IXP2000)      += uengine.o
 obj-$(CONFIG_ARCH_IXP23XX)      += uengine.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
-obj-$(CONFIG_COMMON_CLKDEV)     += clkdev.o
 obj-$(CONFIG_ARM_TIMER_SP804)   += timer-sp.o
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f70ec7dadeb..4ddd0a6ac7f 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -49,7 +49,7 @@ struct gic_chip_data {
  * Default make them NULL.
  */
 struct irq_chip gic_arch_extn = {
-        .irq_ack        = NULL,
+        .irq_eoi        = NULL,
         .irq_mask       = NULL,
         .irq_unmask     = NULL,
         .irq_retrigger  = NULL,
@@ -84,21 +84,12 @@ static inline unsigned int gic_irq(struct irq_data *d)
 /*
  * Routines to acknowledge, disable and enable interrupts
  */
-static void gic_ack_irq(struct irq_data *d)
-{
-        spin_lock(&irq_controller_lock);
-        if (gic_arch_extn.irq_ack)
-                gic_arch_extn.irq_ack(d);
-        writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
-        spin_unlock(&irq_controller_lock);
-}
-
 static void gic_mask_irq(struct irq_data *d)
 {
         u32 mask = 1 << (d->irq % 32);
 
         spin_lock(&irq_controller_lock);
-        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
+        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
         if (gic_arch_extn.irq_mask)
                 gic_arch_extn.irq_mask(d);
         spin_unlock(&irq_controller_lock);
@@ -111,10 +102,21 @@ static void gic_unmask_irq(struct irq_data *d)
         spin_lock(&irq_controller_lock);
         if (gic_arch_extn.irq_unmask)
                 gic_arch_extn.irq_unmask(d);
-        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
+        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
         spin_unlock(&irq_controller_lock);
 }
 
+static void gic_eoi_irq(struct irq_data *d)
+{
+        if (gic_arch_extn.irq_eoi) {
+                spin_lock(&irq_controller_lock);
+                gic_arch_extn.irq_eoi(d);
+                spin_unlock(&irq_controller_lock);
+        }
+
+        writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
+}
+
 static int gic_set_type(struct irq_data *d, unsigned int type)
 {
         void __iomem *base = gic_dist_base(d);
@@ -138,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
         if (gic_arch_extn.irq_set_type)
                 gic_arch_extn.irq_set_type(d, type);
 
-        val = readl(base + GIC_DIST_CONFIG + confoff);
+        val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
         if (type == IRQ_TYPE_LEVEL_HIGH)
                 val &= ~confmask;
         else if (type == IRQ_TYPE_EDGE_RISING)
@@ -148,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
          * As recommended by the spec, disable the interrupt before changing
          * the configuration
          */
-        if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
-                writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+        if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
                 enabled = true;
         }
 
-        writel(val, base + GIC_DIST_CONFIG + confoff);
+        writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
 
         if (enabled)
-                writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
 
         spin_unlock(&irq_controller_lock);
 
@@ -188,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 
         spin_lock(&irq_controller_lock);
         d->node = cpu;
-        val = readl(reg) & ~mask;
-        writel(val | bit, reg);
+        val = readl_relaxed(reg) & ~mask;
+        writel_relaxed(val | bit, reg);
         spin_unlock(&irq_controller_lock);
 
         return 0;
@@ -218,11 +220,10 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         unsigned int cascade_irq, gic_irq;
         unsigned long status;
 
-        /* primary controller ack'ing */
-        chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         spin_lock(&irq_controller_lock);
-        status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
+        status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
         spin_unlock(&irq_controller_lock);
 
         gic_irq = (status & 0x3ff);
@@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(cascade_irq);
 
  out:
-        /* primary controller unmasking */
-        chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(chip, desc);
 }
 
 static struct irq_chip gic_chip = {
         .name                   = "GIC",
-        .irq_ack                = gic_ack_irq,
         .irq_mask               = gic_mask_irq,
         .irq_unmask             = gic_unmask_irq,
+        .irq_eoi                = gic_eoi_irq,
         .irq_set_type           = gic_set_type,
         .irq_retrigger          = gic_retrigger,
 #ifdef CONFIG_SMP
@@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
         cpumask |= cpumask << 8;
         cpumask |= cpumask << 16;
 
-        writel(0, base + GIC_DIST_CTRL);
+        writel_relaxed(0, base + GIC_DIST_CTRL);
 
         /*
          * Find out how many interrupts are supported.
          * The GIC only supports up to 1020 interrupt sources.
          */
-        gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
+        gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
         gic_irqs = (gic_irqs + 1) * 32;
         if (gic_irqs > 1020)
                 gic_irqs = 1020;
@@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
          * Set all global interrupts to be level triggered, active low.
          */
         for (i = 32; i < gic_irqs; i += 16)
-                writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
+                writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
 
         /*
          * Set all global interrupts to this CPU only.
          */
         for (i = 32; i < gic_irqs; i += 4)
-                writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+                writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 
         /*
          * Set priority on all global interrupts.
          */
         for (i = 32; i < gic_irqs; i += 4)
-                writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
+                writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 
         /*
          * Disable all interrupts.  Leave the PPI and SGIs alone
          * as these enables are banked registers.
          */
         for (i = 32; i < gic_irqs; i += 32)
-                writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+                writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 
         /*
          * Limit number of interrupts registered to the platform maximum
@@ -319,12 +319,12 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
          * Setup the Linux IRQ subsystem.
          */
         for (i = irq_start; i < irq_limit; i++) {
-                irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
+                irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
                 irq_set_chip_data(i, gic);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 
-        writel(1, base + GIC_DIST_CTRL);
+        writel_relaxed(1, base + GIC_DIST_CTRL);
 }
 
 static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
@@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
          * Deal with the banked PPI and SGI interrupts - disable all
          * PPI interrupts, ensure all SGI interrupts are enabled.
          */
-        writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
-        writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+        writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+        writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
 
         /*
          * Set priority on PPI and SGI interrupts
          */
         for (i = 0; i < 32; i += 4)
-                writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+                writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
 
-        writel(0xf0, base + GIC_CPU_PRIMASK);
-        writel(1, base + GIC_CPU_CTRL);
+        writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
+        writel_relaxed(1, base + GIC_CPU_CTRL);
 }
 
 void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
@@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 {
         unsigned long map = *cpus_addr(*mask);
 
+        /*
+         * Ensure that stores to Normal memory are visible to the
+         * other CPUs before issuing the IPI.
+         */
+        dsb();
+
         /* this always happens on GIC0 */
-        writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
+        writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
 }
 #endif
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index 8f0f86db360..97912fa4878 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1045,7 +1045,7 @@ static inline int _loop(unsigned dry_run, u8 buf[],
         unsigned lcnt0, lcnt1, ljmp0, ljmp1;
         struct _arg_LPEND lpend;
 
-        /* Max iterations possibile in DMALP is 256 */
+        /* Max iterations possible in DMALP is 256 */
         if (*bursts >= 256*256) {
                 lcnt1 = 256;
                 lcnt0 = 256;
@@ -1446,7 +1446,7 @@ int pl330_update(const struct pl330_info *pi)
         }
 
         for (ev = 0; ev < pi->pcfg.num_events; ev++) {
-                if (val & (1 << ev)) { /* Event occured */
+                if (val & (1 << ev)) { /* Event occurred */
                         struct pl330_thread *thrd;
                         u32 inten = readl(regs + INTEN);
                         int active;
diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig
new file mode 100644
index 00000000000..c55e9212fcb
--- /dev/null
+++ b/arch/arm/configs/at91x40_defconfig
@@ -0,0 +1,48 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EMBEDDED=y
+# CONFIG_HOTPLUG is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_FUTEX is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_MMU is not set
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91X40=y
+CONFIG_MACH_AT91EB01=y
+CONFIG_AT91_EARLY_USART0=y
+CONFIG_CPU_ARM7TDMI=y
+CONFIG_SET_MEM_PARAM=y
+CONFIG_DRAM_BASE=0x01000000
+CONFIG_DRAM_SIZE=0x00400000
+CONFIG_FLASH_MEM_BASE=0x01400000
+CONFIG_PROCESSOR_ID=0x14000040
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_BINFMT_FLAT=y
+# CONFIG_SUSPEND is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 54bf5eec801..40db34cf277 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_DOVE=y
 CONFIG_MACH_DOVE_DB=y
-CONFIG_CPU_V6=y
-CONFIG_CPU_32v6K=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_AEABI=y
@@ -44,7 +42,6 @@ CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
@@ -59,12 +56,12 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -72,12 +69,10 @@ CONFIG_I2C_MV64XXX=y
 CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_STORAGE=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MV=y
@@ -86,7 +81,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -110,23 +104,19 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_CBC=y
 CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_DES=y
 CONFIG_CRYPTO_TEA=y
 CONFIG_CRYPTO_TWOFISH=y
 CONFIG_CRYPTO_DEFLATE=y
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index ed5bc9e05a4..cd4458f6417 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -2,6 +2,7 @@
 #define __ASM_ARM_CPUTYPE_H
 
 #include <linux/stringify.h>
+#include <linux/kernel.h>
 
 #define CPUID_ID        0
 #define CPUID_CACHETYPE 1
diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h
index ee5e03efc1b..3ad4c10d0d8 100644
--- a/arch/arm/include/asm/fpstate.h
+++ b/arch/arm/include/asm/fpstate.h
@@ -18,7 +18,7 @@
  * VFP storage area has:
  *  - FPEXC, FPSCR, FPINST and FPINST2.
  *  - 16 or 32 double precision data registers
- *  - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6)
+ *  - an implementation-dependent word of state for FLDMX/FSTMX (pre-ARMv6)
  * 
  *  FPEXC will always be non-zero once the VFP has been used in this process.
  */
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index c7afbc552c7..7e30874377e 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -126,7 +126,7 @@
 #endif
 
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
-#error Unknown cache maintainence model
+#error Unknown cache maintenance model
 #endif
 
 #ifndef MULTI_CACHE
diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h
index 0ec35d1698a..fbf71d75ec8 100644
--- a/arch/arm/include/asm/glue.h
+++ b/arch/arm/include/asm/glue.h
@@ -10,8 +10,8 @@
  *
  *  This file provides the glue to stick the processor-specific bits
  *  into the kernel in an efficient manner.  The idea is to use branches
- *  when we're only targetting one class of TLB, or indirect calls
- *  when we're targetting multiple classes of TLBs.
+ *  when we're only targeting one class of TLB, or indirect calls
+ *  when we're targeting multiple classes of TLBs.
  */
 #ifdef __KERNEL__
 
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index f35b86e68dd..e4a04e4e562 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -16,7 +16,7 @@
  * make it not entierly compatible with the PL080 specification from
  * ARM. When in doubt, check the Samsung documentation first.
  *
- * The Samsung defines are PL080S, and add an extra controll register,
+ * The Samsung defines are PL080S, and add an extra control register,
  * the ability to move more than 2^11 counts of data and some extra
  * OneNAND features.
 */
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h
index bb8a19bd582..e46bdd0097e 100644
--- a/arch/arm/include/asm/kprobes.h
+++ b/arch/arm/include/asm/kprobes.h
@@ -39,10 +39,13 @@ typedef u32 kprobe_opcode_t;
 struct kprobe;
 typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *);
 
+typedef unsigned long (kprobe_check_cc)(unsigned long);
+
 /* Architecture specific copy of original instruction. */
 struct arch_specific_insn {
         kprobe_opcode_t         *insn;
         kprobe_insn_handler_t   *insn_handler;
+        kprobe_check_cc         *insn_check_cc;
 };
 
 struct prev_kprobe {
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9a87823642d..885be097769 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -249,7 +249,7 @@ do {									\
  * cache totally.  This means that the cache becomes inconsistent, and,
  * since we use normal loads/stores as well, this is really bad.
  * Typically, this causes oopsen in filp_close, but could have other,
- * more disasterous effects.  There are two work-arounds:
+ * more disastrous effects.  There are two work-arounds:
  *  1. Disable interrupts and emulate the atomic swap
  *  2. Clean the cache, perform atomic swap, flush the cache
  *
diff --git a/arch/arm/include/asm/thread_notify.h b/arch/arm/include/asm/thread_notify.h
index c4391ba2035..1dc98067589 100644
--- a/arch/arm/include/asm/thread_notify.h
+++ b/arch/arm/include/asm/thread_notify.h
@@ -43,6 +43,7 @@ static inline void thread_notify(unsigned long rc, struct thread_info *thread)
 #define THREAD_NOTIFY_FLUSH     0
 #define THREAD_NOTIFY_EXIT      1
 #define THREAD_NOTIFY_SWITCH    2
+#define THREAD_NOTIFY_COPY      3
 
 #endif
 #endif
diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h
index 47f023aa849..14749aec94b 100644
--- a/arch/arm/include/asm/ucontext.h
+++ b/arch/arm/include/asm/ucontext.h
@@ -47,7 +47,7 @@ struct crunch_sigframe {
 #endif
 
 #ifdef CONFIG_IWMMXT
-/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */
+/* iwmmxt_area is 0x98 bytes long, preceded by 8 bytes of signature */
 #define IWMMXT_MAGIC            0x12ef842a
 #define IWMMXT_STORAGE_SIZE     (IWMMXT_SIZE + 8)
 
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index c891eb76c0e..87dbe3e2197 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -396,6 +396,10 @@
 #define __NR_fanotify_init              (__NR_SYSCALL_BASE+367)
 #define __NR_fanotify_mark              (__NR_SYSCALL_BASE+368)
 #define __NR_prlimit64                  (__NR_SYSCALL_BASE+369)
+#define __NR_name_to_handle_at          (__NR_SYSCALL_BASE+370)
+#define __NR_open_by_handle_at          (__NR_SYSCALL_BASE+371)
+#define __NR_clock_adjtime              (__NR_SYSCALL_BASE+372)
+#define __NR_syncfs                     (__NR_SYSCALL_BASE+373)
 
 /*
  * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 74554f1742d..8d95446150a 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES)		+= armksyms.o module.o
 obj-$(CONFIG_ARTHUR)            += arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
-obj-$(CONFIG_PM)                += sleep.o
+obj-$(CONFIG_PM_SLEEP)          += sleep.o
 obj-$(CONFIG_HAVE_SCHED_CLOCK)  += sched_clock.o
 obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 5c26eccef99..7fbf28c35bb 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -379,6 +379,10 @@
                 CALL(sys_fanotify_init)
                 CALL(sys_fanotify_mark)
                 CALL(sys_prlimit64)
+/* 370 */       CALL(sys_name_to_handle_at)
+                CALL(sys_open_by_handle_at)
+                CALL(sys_clock_adjtime)
+                CALL(sys_syncfs)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c
index d4a0da1e48f..9b05c6a0dce 100644
--- a/arch/arm/kernel/elf.c
+++ b/arch/arm/kernel/elf.c
@@ -40,15 +40,22 @@ EXPORT_SYMBOL(elf_check_arch);
 void elf_set_personality(const struct elf32_hdr *x)
 {
         unsigned int eflags = x->e_flags;
-        unsigned int personality = PER_LINUX_32BIT;
+        unsigned int personality = current->personality & ~PER_MASK;
+
+        /*
+         * We only support Linux ELF executables, so always set the
+         * personality to LINUX.
+         */
+        personality |= PER_LINUX;
 
         /*
          * APCS-26 is only valid for OABI executables
          */
-        if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) {
-                if (eflags & EF_ARM_APCS_26)
-                        personality = PER_LINUX;
-        }
+        if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN &&
+            (eflags & EF_ARM_APCS_26))
+                personality &= ~ADDR_LIMIT_32BIT;
+        else
+                personality |= ADDR_LIMIT_32BIT;
 
         set_personality(personality);
 
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 8dbc126f715..87acc25d7a3 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -868,6 +868,13 @@ static void reset_ctrl_regs(void *info)
                  */
                 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
                 isb();
+
+                /*
+                 * Clear any configured vector-catch events before
+                 * enabling monitor mode.
+                 */
+                asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
+                isb();
         }
 
         if (enable_monitor_mode())
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 23891317dc4..15eeff6aea0 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -34,9 +34,6 @@
  *
  *   *) If the PC is written to by the instruction, the
  *      instruction must be fully simulated in software.
- *      If it is a conditional instruction, the handler
- *      will use insn[0] to copy its condition code to
- *      set r0 to 1 and insn[1] to "mov pc, lr" to return.
  *
  *   *) Otherwise, a modified form of the instruction is
  *      directly executed.  Its handler calls the
@@ -68,13 +65,17 @@
 
 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
 
+#define is_r15(insn, bitpos) (((insn) & (0xf << bitpos)) == (0xf << bitpos))
+
+/*
+ * Test if load/store instructions writeback the address register.
+ * if P (bit 24) == 0 or W (bit 21) == 1
+ */
+#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
+
 #define PSR_fs  (PSR_f|PSR_s)
 
 #define KPROBE_RETURN_INSTRUCTION       0xe1a0f00e      /* mov pc, lr */
-#define SET_R0_TRUE_INSTRUCTION         0xe3a00001      /* mov  r0, #1 */
-
-#define truecc_insn(insn)       (((insn) & 0xf0000000) | \
-                                 (SET_R0_TRUE_INSTRUCTION & 0x0fffffff))
 
 typedef long (insn_0arg_fn_t)(void);
 typedef long (insn_1arg_fn_t)(long);
@@ -419,14 +420,10 @@ insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
 
 static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
 {
-        insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
         kprobe_opcode_t insn = p->opcode;
         long iaddr = (long)p->addr;
         int disp  = branch_displacement(insn);
 
-        if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
-                return;
-
         if (insn & (1 << 24))
                 regs->ARM_lr = iaddr + 4;
 
@@ -446,14 +443,10 @@ static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
 
 static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
 {
-        insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
         kprobe_opcode_t insn = p->opcode;
         int rm = insn & 0xf;
         long rmv = regs->uregs[rm];
 
-        if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
-                return;
-
         if (insn & (1 << 5))
                 regs->ARM_lr = (long)p->addr + 4;
 
@@ -463,9 +456,16 @@ static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
                 regs->ARM_cpsr |= PSR_T_BIT;
 }
 
+static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs)
+{
+        kprobe_opcode_t insn = p->opcode;
+        int rd = (insn >> 12) & 0xf;
+        unsigned long mask = 0xf8ff03df; /* Mask out execution state */
+        regs->uregs[rd] = regs->ARM_cpsr & mask;
+}
+
 static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
 {
-        insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
         kprobe_opcode_t insn = p->opcode;
         int rn = (insn >> 16) & 0xf;
         int lbit = insn & (1 << 20);
@@ -476,9 +476,6 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
         int reg_bit_vector;
         int reg_count;
 
-        if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
-                return;
-
         reg_count = 0;
         reg_bit_vector = insn & 0xffff;
         while (reg_bit_vector) {
@@ -510,11 +507,6 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
 
 static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
 {
-        insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
-
-        if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
-                return;
-
         regs->ARM_pc = (long)p->addr + str_pc_offset;
         simulate_ldm1stm1(p, regs);
         regs->ARM_pc = (long)p->addr + 4;
@@ -525,24 +517,16 @@ static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
         regs->uregs[12] = regs->uregs[13];
 }
 
-static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs)
-{
-        insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
-        kprobe_opcode_t insn = p->opcode;
-        int rn = (insn >> 16) & 0xf;
-        long rnv = regs->uregs[rn];
-
-        /* Save Rn in case of writeback. */
-        regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
-}
-
 static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
 {
         insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
         kprobe_opcode_t insn = p->opcode;
+        long ppc = (long)p->addr + 8;
         int rd = (insn >> 12) & 0xf;
         int rn = (insn >> 16) & 0xf;
         int rm = insn & 0xf;  /* rm may be invalid, don't care. */
+        long rmv = (rm == 15) ? ppc : regs->uregs[rm];
+        long rnv = (rn == 15) ? ppc : regs->uregs[rn];
 
         /* Not following the C calling convention here, so need asm(). */
         __asm__ __volatile__ (
@@ -554,29 +538,36 @@ static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
                 "str    r0, %[rn]       \n\t"   /* in case of writeback */
                 "str    r2, %[rd0]      \n\t"
                 "str    r3, %[rd1]      \n\t"
-                : [rn]  "+m" (regs->uregs[rn]),
+                : [rn]  "+m" (rnv),
                   [rd0] "=m" (regs->uregs[rd]),
                   [rd1] "=m" (regs->uregs[rd+1])
-                : [rm]   "m" (regs->uregs[rm]),
+                : [rm]   "m" (rmv),
                   [cpsr] "r" (regs->ARM_cpsr),
                   [i_fn] "r" (i_fn)
                 : "r0", "r1", "r2", "r3", "lr", "cc"
         );
+        if (is_writeback(insn))
+                regs->uregs[rn] = rnv;
 }
 
 static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs)
 {
         insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0];
         kprobe_opcode_t insn = p->opcode;
+        long ppc = (long)p->addr + 8;
         int rd = (insn >> 12) & 0xf;
         int rn = (insn >> 16) & 0xf;
         int rm  = insn & 0xf;
-        long rnv = regs->uregs[rn];
-        long rmv = regs->uregs[rm];  /* rm/rmv may be invalid, don't care. */
+        long rnv = (rn == 15) ? ppc : regs->uregs[rn];
+        /* rm/rmv may be invalid, don't care. */
+        long rmv = (rm == 15) ? ppc : regs->uregs[rm];
+        long rnv_wb;
 
-        regs->uregs[rn] = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
+        rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
                                                regs->uregs[rd+1],
                                                regs->ARM_cpsr, i_fn);
+        if (is_writeback(insn))
+                regs->uregs[rn] = rnv_wb;
 }
 
 static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
@@ -630,31 +621,6 @@ static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
                 regs->uregs[rn] = rnv_wb;  /* Save Rn in case of writeback. */
 }
 
-static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs)
-{
-        insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0];
-        kprobe_opcode_t insn = p->opcode;
-        union reg_pair fnr;
-        int rd = (insn >> 12) & 0xf;
-        int rn = (insn >> 16) & 0xf;
-
-        fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn);
-        regs->uregs[rn] = fnr.r0;
-        regs->uregs[rd] = fnr.r1;
-}
-
-static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs)
-{
-        insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
-        kprobe_opcode_t insn = p->opcode;
-        int rd = (insn >> 12) & 0xf;
-        int rn = (insn >> 16) & 0xf;
-        long rnv = regs->uregs[rn];
-        long rdv = regs->uregs[rd];
-
-        insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn);
-}
-
 static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs)
 {
         insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
@@ -688,32 +654,32 @@ static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs)
         insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
 }
 
-static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs)
+static void __kprobes emulate_nop(struct kprobe *p, struct pt_regs *regs)
 {
-        insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
-        kprobe_opcode_t insn = p->opcode;
-        int rd = (insn >> 12) & 0xf;
-
-        regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
 }
 
-static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs)
+static void __kprobes
+emulate_rd12_modify(struct kprobe *p, struct pt_regs *regs)
 {
         insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
         kprobe_opcode_t insn = p->opcode;
-        int ird = (insn >> 12) & 0xf;
+        int rd = (insn >> 12) & 0xf;
+        long rdv = regs->uregs[rd];
 
-        insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn);
+        regs->uregs[rd] = insnslot_1arg_rflags(rdv, regs->ARM_cpsr, i_fn);
 }
 
-static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs)
+static void __kprobes
+emulate_rd12rn0_modify(struct kprobe *p, struct pt_regs *regs)
 {
-        insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
+        insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
         kprobe_opcode_t insn = p->opcode;
-        int rn = (insn >> 16) & 0xf;
+        int rd = (insn >> 12) & 0xf;
+        int rn = insn & 0xf;
+        long rdv = regs->uregs[rd];
         long rnv = regs->uregs[rn];
 
-        insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
+        regs->uregs[rd] = insnslot_2arg_rflags(rdv, rnv, regs->ARM_cpsr, i_fn);
 }
 
 static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs)
@@ -819,6 +785,17 @@ emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs)
 }
 
 static void __kprobes
+emulate_alu_tests_imm(struct kprobe *p, struct pt_regs *regs)
+{
+        insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
+        kprobe_opcode_t insn = p->opcode;
+        int rn = (insn >> 16) & 0xf;
+        long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
+
+        insnslot_1arg_rwflags(rnv, &regs->ARM_cpsr, i_fn);
+}
+
+static void __kprobes
 emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs)
 {
         insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
@@ -854,14 +831,34 @@ emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs)
                 insnslot_3arg_rwflags(rnv, rmv, rsv, &regs->ARM_cpsr, i_fn);
 }
 
+static void __kprobes
+emulate_alu_tests(struct kprobe *p, struct pt_regs *regs)
+{
+        insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
+        kprobe_opcode_t insn = p->opcode;
+        long ppc = (long)p->addr + 8;
+        int rn = (insn >> 16) & 0xf;
+        int rs = (insn >> 8) & 0xf;     /* rs/rsv may be invalid, don't care. */
+        int rm = insn & 0xf;
+        long rnv = (rn == 15) ? ppc : regs->uregs[rn];
+        long rmv = (rm == 15) ? ppc : regs->uregs[rm];
+        long rsv = regs->uregs[rs];
+
+        insnslot_3arg_rwflags(rnv, rmv, rsv, &regs->ARM_cpsr, i_fn);
+}
+
 static enum kprobe_insn __kprobes
 prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
-        int ibit = (insn & (1 << 26)) ? 25 : 22;
+        int not_imm = (insn & (1 << 26)) ? (insn & (1 << 25))
+                                         : (~insn & (1 << 22));
+
+        if (is_writeback(insn) && is_r15(insn, 16))
+                return INSN_REJECTED;   /* Writeback to PC */
 
         insn &= 0xfff00fff;
         insn |= 0x00001000;     /* Rn = r0, Rd = r1 */
-        if (insn & (1 << ibit)) {
+        if (not_imm) {
                 insn &= ~0xf;
                 insn |= 2;      /* Rm = r2 */
         }
@@ -871,20 +868,40 @@ prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 }
 
 static enum kprobe_insn __kprobes
-prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+prep_emulate_rd12_modify(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
-        insn &= 0xffff0ff0;     /* Rd = r0, Rm = r0 */
+        if (is_r15(insn, 12))
+                return INSN_REJECTED;   /* Rd is PC */
+
+        insn &= 0xffff0fff;     /* Rd = r0 */
         asi->insn[0] = insn;
-        asi->insn_handler = emulate_rd12rm0;
+        asi->insn_handler = emulate_rd12_modify;
         return INSN_GOOD;
 }
 
 static enum kprobe_insn __kprobes
-prep_emulate_rd12(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+prep_emulate_rd12rn0_modify(kprobe_opcode_t insn,
+                            struct arch_specific_insn *asi)
 {
-        insn &= 0xffff0fff;     /* Rd = r0 */
+        if (is_r15(insn, 12))
+                return INSN_REJECTED;   /* Rd is PC */
+
+        insn &= 0xffff0ff0;     /* Rd = r0 */
+        insn |= 0x00000001;     /* Rn = r1 */
+        asi->insn[0] = insn;
+        asi->insn_handler = emulate_rd12rn0_modify;
+        return INSN_GOOD;
+}
+
+static enum kprobe_insn __kprobes
+prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+{
+        if (is_r15(insn, 12))
+                return INSN_REJECTED;   /* Rd is PC */
+
+        insn &= 0xffff0ff0;     /* Rd = r0, Rm = r0 */
         asi->insn[0] = insn;
-        asi->insn_handler = emulate_rd12;
+        asi->insn_handler = emulate_rd12rm0;
         return INSN_GOOD;
 }
 
@@ -892,6 +909,9 @@ static enum kprobe_insn __kprobes
 prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn,
                                 struct arch_specific_insn *asi)
 {
+        if (is_r15(insn, 12))
+                return INSN_REJECTED;   /* Rd is PC */
+
         insn &= 0xfff00ff0;     /* Rd = r0, Rn = r0 */
         insn |= 0x00000001;     /* Rm = r1 */
         asi->insn[0] = insn;
@@ -903,6 +923,9 @@ static enum kprobe_insn __kprobes
 prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn,
                                struct arch_specific_insn *asi)
 {
+        if (is_r15(insn, 16))
+                return INSN_REJECTED;   /* Rd is PC */
+
         insn &= 0xfff0f0f0;     /* Rd = r0, Rs = r0 */
         insn |= 0x00000001;     /* Rm = r1          */
         asi->insn[0] = insn;
@@ -914,6 +937,9 @@ static enum kprobe_insn __kprobes
 prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn,
                                    struct arch_specific_insn *asi)
 {
+        if (is_r15(insn, 16))
+                return INSN_REJECTED;   /* Rd is PC */
+
         insn &= 0xfff000f0;     /* Rd = r0, Rn = r0 */
         insn |= 0x00000102;     /* Rs = r1, Rm = r2 */
         asi->insn[0] = insn;
@@ -925,6 +951,9 @@ static enum kprobe_insn __kprobes
 prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
                                        struct arch_specific_insn *asi)
 {
+        if (is_r15(insn, 16) || is_r15(insn, 12))
+                return INSN_REJECTED;   /* RdHi or RdLo is PC */
+
         insn &= 0xfff000f0;     /* RdHi = r0, RdLo = r1 */
         insn |= 0x00001203;     /* Rs = r2, Rm = r3 */
         asi->insn[0] = insn;
@@ -945,20 +974,13 @@ prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
 static enum kprobe_insn __kprobes
 space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
-        /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */
-        /* RFE           : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */
-        /* SRS           : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */
-        if ((insn & 0xfff30020) == 0xf1020000 ||
-            (insn & 0xfe500f00) == 0xf8100a00 ||
-            (insn & 0xfe5f0f00) == 0xf84d0500)
-                return INSN_REJECTED;
-
-        /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */
-        if ((insn & 0xfd700000) == 0xf4500000) {
-                insn &= 0xfff0ffff;     /* Rn = r0 */
-                asi->insn[0] = insn;
-                asi->insn_handler = emulate_rn16;
-                return INSN_GOOD;
+        /* memory hint : 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx : */
+        /* PLDI        : 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx : */
+        /* PLDW        : 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx : */
+        /* PLD         : 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx : */
+        if ((insn & 0xfe300000) == 0xf4100000) {
+                asi->insn_handler = emulate_nop;
+                return INSN_GOOD_NO_SLOT;
         }
 
         /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */
@@ -967,41 +989,22 @@ space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi)
                 return INSN_GOOD_NO_SLOT;
         }
 
-        /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
-        /* CDP2   : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
-        if ((insn & 0xffff00f0) == 0xf1010000 ||
-            (insn & 0xff000010) == 0xfe000000) {
-                asi->insn[0] = insn;
-                asi->insn_handler = emulate_none;
-                return INSN_GOOD;
-        }
+        /* CPS   : 1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */
+        /* SETEND: 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
 
+        /* SRS   : 1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
+        /* RFE   : 1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
+
+        /* Coprocessor instructions... */
         /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
         /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
-        if ((insn & 0xffe00000) == 0xfc400000) {
-                insn &= 0xfff00fff;     /* Rn = r0 */
-                insn |= 0x00001000;     /* Rd = r1 */
-                asi->insn[0] = insn;
-                asi->insn_handler =
-                        (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
-                return INSN_GOOD;
-        }
+        /* LDC2  : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
+        /* STC2  : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
+        /* CDP2  : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
+        /* MCR2  : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
+        /* MRC2  : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
 
-        /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
-        /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
-        if ((insn & 0xfe000000) == 0xfc000000) {
-                insn &= 0xfff0ffff;      /* Rn = r0 */
-                asi->insn[0] = insn;
-                asi->insn_handler = emulate_ldcstc;
-                return INSN_GOOD;
-        }
-
-        /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
-        /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
-        insn &= 0xffff0fff;     /* Rd = r0 */
-        asi->insn[0]      = insn;
-        asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
-        return INSN_GOOD;
+        return INSN_REJECTED;
 }
 
 static enum kprobe_insn __kprobes
@@ -1010,19 +1013,18 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
         /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */
         if ((insn & 0x0f900010) == 0x01000000) {
 
-                /* BXJ  : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
-                /* MSR  : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
-                if ((insn & 0x0ff000f0) == 0x01200020 ||
-                    (insn & 0x0fb000f0) == 0x01200000)
-                        return INSN_REJECTED;
-
-                /* MRS : cccc 0001 0x00 xxxx xxxx xxxx 0000 xxxx */
-                if ((insn & 0x0fb00010) == 0x01000000)
-                        return prep_emulate_rd12(insn, asi);
+                /* MRS cpsr : cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
+                if ((insn & 0x0ff000f0) == 0x01000000) {
+                        if (is_r15(insn, 12))
+                                return INSN_REJECTED;   /* Rd is PC */
+                        asi->insn_handler = simulate_mrs;
+                        return INSN_GOOD_NO_SLOT;
+                }
 
                 /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
                 if ((insn & 0x0ff00090) == 0x01400080)
-                        return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
+                        return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn,
+                                                                        asi);
 
                 /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
                 /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
@@ -1031,24 +1033,29 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
                         return prep_emulate_rd16rs8rm0_wflags(insn, asi);
 
                 /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */
-                /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 0x00 xxxx : Q */
-                return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
+                /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx : Q */
+                if ((insn & 0x0ff00090) == 0x01000080 ||
+                    (insn & 0x0ff000b0) == 0x01200080)
+                        return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
+
+                /* BXJ      : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
+                /* MSR      : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
+                /* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
 
+                /* Other instruction encodings aren't yet defined */
+                return INSN_REJECTED;
         }
 
         /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */
         else if ((insn & 0x0f900090) == 0x01000010) {
 
-                /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
-                if ((insn & 0xfff000f0) == 0xe1200070)
-                        return INSN_REJECTED;
-
                 /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
                 /* BX     : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
                 if ((insn & 0x0ff000d0) == 0x01200010) {
-                        asi->insn[0] = truecc_insn(insn);
+                        if ((insn & 0x0ff000ff) == 0x0120003f)
+                                return INSN_REJECTED; /* BLX pc */
                         asi->insn_handler = simulate_blx2bx;
-                        return INSN_GOOD;
+                        return INSN_GOOD_NO_SLOT;
                 }
 
                 /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
@@ -1059,17 +1066,27 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
                 /* QSUB    : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */
                 /* QDADD   : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */
                 /* QDSUB   : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */
-                return prep_emulate_rd12rn16rm0_wflags(insn, asi);
+                if ((insn & 0x0f9000f0) == 0x01000050)
+                        return prep_emulate_rd12rn16rm0_wflags(insn, asi);
+
+                /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
+                /* SMC  : cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */
+
+                /* Other instruction encodings aren't yet defined */
+                return INSN_REJECTED;
         }
 
         /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
-        else if ((insn & 0x0f000090) == 0x00000090) {
+        else if ((insn & 0x0f0000f0) == 0x00000090) {
 
                 /* MUL    : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx :   */
                 /* MULS   : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */
                 /* MLA    : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx :   */
                 /* MLAS   : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */
                 /* UMAAL  : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx :   */
+                /* undef  : cccc 0000 0101 xxxx xxxx xxxx 1001 xxxx :   */
+                /* MLS    : cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx :   */
+                /* undef  : cccc 0000 0111 xxxx xxxx xxxx 1001 xxxx :   */
                 /* UMULL  : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx :   */
                 /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */
                 /* UMLAL  : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx :   */
@@ -1078,13 +1095,15 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
                 /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */
                 /* SMLAL  : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx :   */
                 /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */
-                if ((insn & 0x0fe000f0) == 0x00000090) {
-                       return prep_emulate_rd16rs8rm0_wflags(insn, asi);
-                } else if  ((insn & 0x0fe000f0) == 0x00200090) {
-                       return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
-                } else {
-                       return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
-                }
+                if ((insn & 0x00d00000) == 0x00500000)
+                        return INSN_REJECTED;
+                else if ((insn & 0x00e00000) == 0x00000000)
+                        return prep_emulate_rd16rs8rm0_wflags(insn, asi);
+                else if ((insn & 0x00a00000) == 0x00200000)
+                        return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
+                else
+                        return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn,
+                                                                        asi);
         }
 
         /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
@@ -1092,23 +1111,45 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 
                 /* SWP   : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */
                 /* SWPB  : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */
-                /* LDRD  : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
-                /* STRD  : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
+                /* ???   : cccc 0001 0x01 xxxx xxxx xxxx 1001 xxxx */
+                /* ???   : cccc 0001 0x10 xxxx xxxx xxxx 1001 xxxx */
+                /* ???   : cccc 0001 0x11 xxxx xxxx xxxx 1001 xxxx */
                 /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */
                 /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */
+                /* STREXD: cccc 0001 1010 xxxx xxxx xxxx 1001 xxxx */
+                /* LDREXD: cccc 0001 1011 xxxx xxxx xxxx 1001 xxxx */
+                /* STREXB: cccc 0001 1100 xxxx xxxx xxxx 1001 xxxx */
+                /* LDREXB: cccc 0001 1101 xxxx xxxx xxxx 1001 xxxx */
+                /* STREXH: cccc 0001 1110 xxxx xxxx xxxx 1001 xxxx */
+                /* LDREXH: cccc 0001 1111 xxxx xxxx xxxx 1001 xxxx */
+
+                /* LDRD  : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
+                /* STRD  : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
                 /* LDRH  : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */
                 /* STRH  : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */
                 /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */
                 /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */
-                if ((insn & 0x0fb000f0) == 0x01000090) {
-                        /* SWP/SWPB */
-                        return prep_emulate_rd12rn16rm0_wflags(insn, asi);
+                if ((insn & 0x0f0000f0) == 0x01000090) {
+                        if ((insn & 0x0fb000f0) == 0x01000090) {
+                                /* SWP/SWPB */
+                                return prep_emulate_rd12rn16rm0_wflags(insn,
+                                                                        asi);
+                        } else {
+                                /* STREX/LDREX variants and unallocaed space */
+                                return INSN_REJECTED;
+                        }
+
                 } else if ((insn & 0x0e1000d0) == 0x00000d0) {
                         /* STRD/LDRD */
+                        if ((insn & 0x0000e000) == 0x0000e000)
+                                return INSN_REJECTED;   /* Rd is LR or PC */
+                        if (is_writeback(insn) && is_r15(insn, 16))
+                                return INSN_REJECTED;   /* Writeback to PC */
+
                         insn &= 0xfff00fff;
                         insn |= 0x00002000;     /* Rn = r0, Rd = r2 */
-                        if (insn & (1 << 22)) {
-                                /* I bit */
+                        if (!(insn & (1 << 22))) {
+                                /* Register index */
                                 insn &= ~0xf;
                                 insn |= 1;      /* Rm = r1 */
                         }
@@ -1118,6 +1159,9 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
                         return INSN_GOOD;
                 }
 
+                /* LDRH/STRH/LDRSB/LDRSH */
+                if (is_r15(insn, 12))
+                        return INSN_REJECTED;   /* Rd is PC */
                 return prep_emulate_ldr_str(insn, asi);
         }
 
@@ -1125,7 +1169,7 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 
         /*
          * ALU op with S bit and Rd == 15 :
-         *      cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
+         *      cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
          */
         if ((insn & 0x0e10f000) == 0x0010f000)
                 return INSN_REJECTED;
@@ -1154,22 +1198,61 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
                 insn |= 0x00000200;     /* Rs = r2 */
         }
         asi->insn[0] = insn;
-        asi->insn_handler = (insn & (1 << 20)) ?  /* S-bit */
+
+        if ((insn & 0x0f900000) == 0x01100000) {
+                /*
+                 * TST : cccc 0001 0001 xxxx xxxx xxxx xxxx xxxx
+                 * TEQ : cccc 0001 0011 xxxx xxxx xxxx xxxx xxxx
+                 * CMP : cccc 0001 0101 xxxx xxxx xxxx xxxx xxxx
+                 * CMN : cccc 0001 0111 xxxx xxxx xxxx xxxx xxxx
+                 */
+                asi->insn_handler = emulate_alu_tests;
+        } else {
+                /* ALU ops which write to Rd */
+                asi->insn_handler = (insn & (1 << 20)) ?  /* S-bit */
                                 emulate_alu_rwflags : emulate_alu_rflags;
+        }
         return INSN_GOOD;
 }
 
 static enum kprobe_insn __kprobes
 space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
+        /* MOVW  : cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */
+        /* MOVT  : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */
+        if ((insn & 0x0fb00000) == 0x03000000)
+                return prep_emulate_rd12_modify(insn, asi);
+
+        /* hints : cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */
+        if ((insn & 0x0fff0000) == 0x03200000) {
+                unsigned op2 = insn & 0x000000ff;
+                if (op2 == 0x01 || op2 == 0x04) {
+                        /* YIELD : cccc 0011 0010 0000 xxxx xxxx 0000 0001 */
+                        /* SEV   : cccc 0011 0010 0000 xxxx xxxx 0000 0100 */
+                        asi->insn[0] = insn;
+                        asi->insn_handler = emulate_none;
+                        return INSN_GOOD;
+                } else if (op2 <= 0x03) {
+                        /* NOP   : cccc 0011 0010 0000 xxxx xxxx 0000 0000 */
+                        /* WFE   : cccc 0011 0010 0000 xxxx xxxx 0000 0010 */
+                        /* WFI   : cccc 0011 0010 0000 xxxx xxxx 0000 0011 */
+                        /*
+                         * We make WFE and WFI true NOPs to avoid stalls due
+                         * to missing events whilst processing the probe.
+                         */
+                        asi->insn_handler = emulate_nop;
+                        return INSN_GOOD_NO_SLOT;
+                }
+                /* For DBG and unallocated hints it's safest to reject them */
+                return INSN_REJECTED;
+        }
+
         /*
          * MSR   : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
-         * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
          * ALU op with S bit and Rd == 15 :
          *         cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
          */
         if ((insn & 0x0fb00000) == 0x03200000 ||        /* MSR */
-            (insn & 0x0ff00000) == 0x03400000 ||        /* Undef */
             (insn & 0x0e10f000) == 0x0210f000)          /* ALU s-bit, R15  */
                 return INSN_REJECTED;
 
@@ -1180,10 +1263,22 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
          * *S (bit 20) updates condition codes
          * ADC/SBC/RSC reads the C flag
          */
-        insn &= 0xffff0fff;     /* Rd = r0 */
+        insn &= 0xfff00fff;     /* Rn = r0 and Rd = r0 */
         asi->insn[0] = insn;
-        asi->insn_handler = (insn & (1 << 20)) ?  /* S-bit */
+
+        if ((insn & 0x0f900000) == 0x03100000) {
+                /*
+                 * TST : cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx
+                 * TEQ : cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx
+                 * CMP : cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx
+                 * CMN : cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx
+                 */
+                asi->insn_handler = emulate_alu_tests_imm;
+        } else {
+                /* ALU ops which write to Rd */
+                asi->insn_handler = (insn & (1 << 20)) ?  /* S-bit */
                         emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
+        }
         return INSN_GOOD;
 }
 
@@ -1192,6 +1287,8 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
         /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */
         if ((insn & 0x0ff000f0) == 0x068000b0) {
+                if (is_r15(insn, 12))
+                        return INSN_REJECTED;   /* Rd is PC */
                 insn &= 0xfff00ff0;     /* Rd = r0, Rn = r0 */
                 insn |= 0x00000001;     /* Rm = r1 */
                 asi->insn[0] = insn;
@@ -1205,6 +1302,8 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
         /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */
         if ((insn & 0x0fa00030) == 0x06a00010 ||
             (insn & 0x0fb000f0) == 0x06a00030) {
+                if (is_r15(insn, 12))
+                        return INSN_REJECTED;   /* Rd is PC */
                 insn &= 0xffff0ff0;     /* Rd = r0, Rm = r0 */
                 asi->insn[0] = insn;
                 asi->insn_handler = emulate_sat;
@@ -1213,57 +1312,101 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 
         /* REV    : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
         /* REV16  : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
+        /* RBIT   : cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
         /* REVSH  : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
         if ((insn & 0x0ff00070) == 0x06b00030 ||
-            (insn & 0x0ff000f0) == 0x06f000b0)
+            (insn & 0x0ff00070) == 0x06f00030)
                 return prep_emulate_rd12rm0(insn, asi);
 
+        /* ???       : cccc 0110 0000 xxxx xxxx xxxx xxx1 xxxx :   */
         /* SADD16    : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */
         /* SADDSUBX  : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */
         /* SSUBADDX  : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */
         /* SSUB16    : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */
         /* SADD8     : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */
+        /* ???       : cccc 0110 0001 xxxx xxxx xxxx 1011 xxxx :   */
+        /* ???       : cccc 0110 0001 xxxx xxxx xxxx 1101 xxxx :   */
         /* SSUB8     : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */
         /* QADD16    : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx :   */
         /* QADDSUBX  : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx :   */
         /* QSUBADDX  : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx :   */
         /* QSUB16    : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx :   */
         /* QADD8     : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx :   */
+        /* ???       : cccc 0110 0010 xxxx xxxx xxxx 1011 xxxx :   */
+        /* ???       : cccc 0110 0010 xxxx xxxx xxxx 1101 xxxx :   */
         /* QSUB8     : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx :   */
         /* SHADD16   : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx :   */
         /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx :   */
         /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx :   */
         /* SHSUB16   : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx :   */
         /* SHADD8    : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx :   */
+        /* ???       : cccc 0110 0011 xxxx xxxx xxxx 1011 xxxx :   */
+        /* ???       : cccc 0110 0011 xxxx xxxx xxxx 1101 xxxx :   */
         /* SHSUB8    : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx :   */
+        /* ???       : cccc 0110 0100 xxxx xxxx xxxx xxx1 xxxx :   */
         /* UADD16    : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */
         /* UADDSUBX  : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */
         /* USUBADDX  : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */
         /* USUB16    : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */
         /* UADD8     : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */
+        /* ???       : cccc 0110 0101 xxxx xxxx xxxx 1011 xxxx :   */
+        /* ???       : cccc 0110 0101 xxxx xxxx xxxx 1101 xxxx :   */
         /* USUB8     : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */
         /* UQADD16   : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx :   */
         /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx :   */
         /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx :   */
         /* UQSUB16   : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx :   */
         /* UQADD8    : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx :   */
+        /* ???       : cccc 0110 0110 xxxx xxxx xxxx 1011 xxxx :   */
+        /* ???       : cccc 0110 0110 xxxx xxxx xxxx 1101 xxxx :   */
         /* UQSUB8    : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx :   */
         /* UHADD16   : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx :   */
         /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx :   */
         /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx :   */
         /* UHSUB16   : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx :   */
         /* UHADD8    : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx :   */
+        /* ???       : cccc 0110 0111 xxxx xxxx xxxx 1011 xxxx :   */
+        /* ???       : cccc 0110 0111 xxxx xxxx xxxx 1101 xxxx :   */
         /* UHSUB8    : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx :   */
+        if ((insn & 0x0f800010) == 0x06000010) {
+                if ((insn & 0x00300000) == 0x00000000 ||
+                    (insn & 0x000000e0) == 0x000000a0 ||
+                    (insn & 0x000000e0) == 0x000000c0)
+                        return INSN_REJECTED;   /* Unallocated space */
+                return prep_emulate_rd12rn16rm0_wflags(insn, asi);
+        }
+
         /* PKHBT     : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx :   */
         /* PKHTB     : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx :   */
+        if ((insn & 0x0ff00030) == 0x06800010)
+                return prep_emulate_rd12rn16rm0_wflags(insn, asi);
+
         /* SXTAB16   : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx :   */
-        /* SXTB      : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx :   */
+        /* SXTB16    : cccc 0110 1000 1111 xxxx xxxx 0111 xxxx :   */
+        /* ???       : cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx :   */
         /* SXTAB     : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx :   */
+        /* SXTB      : cccc 0110 1010 1111 xxxx xxxx 0111 xxxx :   */
         /* SXTAH     : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx :   */
+        /* SXTH      : cccc 0110 1011 1111 xxxx xxxx 0111 xxxx :   */
         /* UXTAB16   : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx :   */
+        /* UXTB16    : cccc 0110 1100 1111 xxxx xxxx 0111 xxxx :   */
+        /* ???       : cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx :   */
         /* UXTAB     : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx :   */
+        /* UXTB      : cccc 0110 1110 1111 xxxx xxxx 0111 xxxx :   */
         /* UXTAH     : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx :   */
-        return prep_emulate_rd12rn16rm0_wflags(insn, asi);
+        /* UXTH      : cccc 0110 1111 1111 xxxx xxxx 0111 xxxx :   */
+        if ((insn & 0x0f8000f0) == 0x06800070) {
+                if ((insn & 0x00300000) == 0x00100000)
+                        return INSN_REJECTED;   /* Unallocated space */
+
+                if ((insn & 0x000f0000) == 0x000f0000)
+                        return prep_emulate_rd12rm0(insn, asi);
+                else
+                        return prep_emulate_rd12rn16rm0_wflags(insn, asi);
+        }
+
+        /* Other instruction encodings aren't yet defined */
+        return INSN_REJECTED;
 }
 
 static enum kprobe_insn __kprobes
@@ -1273,29 +1416,49 @@ space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
         if ((insn & 0x0ff000f0) == 0x03f000f0)
                 return INSN_REJECTED;
 
-        /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
-        /* USAD8  : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
-        if ((insn & 0x0ff000f0) == 0x07800010)
-                 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
-
         /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
         /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
         if ((insn & 0x0ff00090) == 0x07400010)
                 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
 
         /* SMLAD  : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */
+        /* SMUAD  : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
         /* SMLSD  : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */
+        /* SMUSD  : cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx :  */
         /* SMMLA  : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx :  */
-        /* SMMLS  : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx :  */
+        /* SMMUL  : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx :  */
+        /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx :  */
+        /* USAD8  : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx :  */
         if ((insn & 0x0ff00090) == 0x07000010 ||
             (insn & 0x0ff000d0) == 0x07500010 ||
-            (insn & 0x0ff000d0) == 0x075000d0)
+            (insn & 0x0ff000f0) == 0x07800010) {
+
+                if ((insn & 0x0000f000) == 0x0000f000)
+                        return prep_emulate_rd16rs8rm0_wflags(insn, asi);
+                else
+                        return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
+        }
+
+        /* SMMLS  : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx :  */
+        if ((insn & 0x0ff000d0) == 0x075000d0)
                 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
 
-        /* SMUSD  : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :  */
-        /* SMUAD  : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
-        /* SMMUL  : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx :  */
-        return prep_emulate_rd16rs8rm0_wflags(insn, asi);
+        /* SBFX   : cccc 0111 101x xxxx xxxx xxxx x101 xxxx :  */
+        /* UBFX   : cccc 0111 111x xxxx xxxx xxxx x101 xxxx :  */
+        if ((insn & 0x0fa00070) == 0x07a00050)
+                return prep_emulate_rd12rm0(insn, asi);
+
+        /* BFI    : cccc 0111 110x xxxx xxxx xxxx x001 xxxx :  */
+        /* BFC    : cccc 0111 110x xxxx xxxx xxxx x001 1111 :  */
+        if ((insn & 0x0fe00070) == 0x07c00010) {
+
+                if ((insn & 0x0000000f) == 0x0000000f)
+                        return prep_emulate_rd12_modify(insn, asi);
+                else
+                        return prep_emulate_rd12rn0_modify(insn, asi);
+        }
+
+        return INSN_REJECTED;
 }
 
 static enum kprobe_insn __kprobes
@@ -1309,6 +1472,10 @@ space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
         /* STRB  : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */
         /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
         /* STRT  : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
+
+        if ((insn & 0x00500000) == 0x00500000 && is_r15(insn, 12))
+                return INSN_REJECTED;   /* LDRB into PC */
+
         return prep_emulate_ldr_str(insn, asi);
 }
 
@@ -1323,10 +1490,9 @@ space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 
         /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
         /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
-        asi->insn[0] = truecc_insn(insn);
         asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */
                                 simulate_stm1_pc : simulate_ldm1stm1;
-        return INSN_GOOD;
+        return INSN_GOOD_NO_SLOT;
 }
 
 static enum kprobe_insn __kprobes
@@ -1334,58 +1500,117 @@ space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
         /* B  : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
         /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
-        asi->insn[0] = truecc_insn(insn);
         asi->insn_handler = simulate_bbl;
-        return INSN_GOOD;
+        return INSN_GOOD_NO_SLOT;
 }
 
 static enum kprobe_insn __kprobes
-space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+space_cccc_11xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
+        /* Coprocessor instructions... */
         /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
         /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
-        insn &= 0xfff00fff;
-        insn |= 0x00001000;     /* Rn = r0, Rd = r1 */
-        asi->insn[0] = insn;
-        asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
-        return INSN_GOOD;
+        /* LDC  : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
+        /* STC  : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
+        /* CDP  : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
+        /* MCR  : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
+        /* MRC  : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
+
+        /* SVC  : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
+
+        return INSN_REJECTED;
 }
 
-static enum kprobe_insn __kprobes
-space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+static unsigned long __kprobes __check_eq(unsigned long cpsr)
 {
-        /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
-        /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
-        insn &= 0xfff0ffff;     /* Rn = r0 */
-        asi->insn[0] = insn;
-        asi->insn_handler = emulate_ldcstc;
-        return INSN_GOOD;
+        return cpsr & PSR_Z_BIT;
 }
 
-static enum kprobe_insn __kprobes
-space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+static unsigned long __kprobes __check_ne(unsigned long cpsr)
 {
-        /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
-        /* SWI  : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
-        if ((insn & 0xfff000f0) == 0xe1200070 ||
-            (insn & 0x0f000000) == 0x0f000000)
-                return INSN_REJECTED;
+        return (~cpsr) & PSR_Z_BIT;
+}
 
-        /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
-        if ((insn & 0x0f000010) == 0x0e000000) {
-                asi->insn[0] = insn;
-                asi->insn_handler = emulate_none;
-                return INSN_GOOD;
-        }
+static unsigned long __kprobes __check_cs(unsigned long cpsr)
+{
+        return cpsr & PSR_C_BIT;
+}
 
-        /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
-        /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
-        insn &= 0xffff0fff;     /* Rd = r0 */
-        asi->insn[0] = insn;
-        asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
-        return INSN_GOOD;
+static unsigned long __kprobes __check_cc(unsigned long cpsr)
+{
+        return (~cpsr) & PSR_C_BIT;
+}
+
+static unsigned long __kprobes __check_mi(unsigned long cpsr)
+{
+        return cpsr & PSR_N_BIT;
+}
+
+static unsigned long __kprobes __check_pl(unsigned long cpsr)
+{
+        return (~cpsr) & PSR_N_BIT;
+}
+
+static unsigned long __kprobes __check_vs(unsigned long cpsr)
+{
+        return cpsr & PSR_V_BIT;
+}
+
+static unsigned long __kprobes __check_vc(unsigned long cpsr)
+{
+        return (~cpsr) & PSR_V_BIT;
+}
+
+static unsigned long __kprobes __check_hi(unsigned long cpsr)
+{
+        cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
+        return cpsr & PSR_C_BIT;
 }
 
+static unsigned long __kprobes __check_ls(unsigned long cpsr)
+{
+        cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
+        return (~cpsr) & PSR_C_BIT;
+}
+
+static unsigned long __kprobes __check_ge(unsigned long cpsr)
+{
+        cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        return (~cpsr) & PSR_N_BIT;
+}
+
+static unsigned long __kprobes __check_lt(unsigned long cpsr)
+{
+        cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        return cpsr & PSR_N_BIT;
+}
+
+static unsigned long __kprobes __check_gt(unsigned long cpsr)
+{
+        unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        temp |= (cpsr << 1);                     /* PSR_N_BIT |= PSR_Z_BIT */
+        return (~temp) & PSR_N_BIT;
+}
+
+static unsigned long __kprobes __check_le(unsigned long cpsr)
+{
+        unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        temp |= (cpsr << 1);                     /* PSR_N_BIT |= PSR_Z_BIT */
+        return temp & PSR_N_BIT;
+}
+
+static unsigned long __kprobes __check_al(unsigned long cpsr)
+{
+        return true;
+}
+
+static kprobe_check_cc * const condition_checks[16] = {
+        &__check_eq, &__check_ne, &__check_cs, &__check_cc,
+        &__check_mi, &__check_pl, &__check_vs, &__check_vc,
+        &__check_hi, &__check_ls, &__check_ge, &__check_lt,
+        &__check_gt, &__check_le, &__check_al, &__check_al
+};
+
 /* Return:
  *   INSN_REJECTED     If instruction is one not allowed to kprobe,
  *   INSN_GOOD         If instruction is supported and uses instruction slot,
@@ -1401,133 +1626,45 @@ space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 enum kprobe_insn __kprobes
 arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
+        asi->insn_check_cc = condition_checks[insn>>28];
         asi->insn[1] = KPROBE_RETURN_INSTRUCTION;
 
-        if ((insn & 0xf0000000) == 0xf0000000) {
+        if ((insn & 0xf0000000) == 0xf0000000)
 
                 return space_1111(insn, asi);
 
-        } else if ((insn & 0x0e000000) == 0x00000000) {
+        else if ((insn & 0x0e000000) == 0x00000000)
 
                 return space_cccc_000x(insn, asi);
 
-        } else if ((insn & 0x0e000000) == 0x02000000) {
+        else if ((insn & 0x0e000000) == 0x02000000)
 
                 return space_cccc_001x(insn, asi);
 
-        } else if ((insn & 0x0f000010) == 0x06000010) {
+        else if ((insn & 0x0f000010) == 0x06000010)
 
                 return space_cccc_0110__1(insn, asi);
 
-        } else if ((insn & 0x0f000010) == 0x07000010) {
+        else if ((insn & 0x0f000010) == 0x07000010)
 
                 return space_cccc_0111__1(insn, asi);
 
-        } else if ((insn & 0x0c000000) == 0x04000000) {
+        else if ((insn & 0x0c000000) == 0x04000000)
 
                 return space_cccc_01xx(insn, asi);
 
-        } else if ((insn & 0x0e000000) == 0x08000000) {
+        else if ((insn & 0x0e000000) == 0x08000000)
 
                 return space_cccc_100x(insn, asi);
 
-        } else if ((insn & 0x0e000000) == 0x0a000000) {
+        else if ((insn & 0x0e000000) == 0x0a000000)
 
                 return space_cccc_101x(insn, asi);
 
-        } else if ((insn & 0x0fe00000) == 0x0c400000) {
-
-                return space_cccc_1100_010x(insn, asi);
-
-        } else if ((insn & 0x0e000000) == 0x0c000000) {
-
-                return space_cccc_110x(insn, asi);
-
-        }
-
-        return space_cccc_111x(insn, asi);
+        return space_cccc_11xx(insn, asi);
 }
 
 void __init arm_kprobe_decode_init(void)
 {
         find_str_pc_offset();
 }
-
-
-/*
- * All ARM instructions listed below.
- *
- * Instructions and their general purpose registers are given.
- * If a particular register may not use R15, it is prefixed with a "!".
- * If marked with a "*" means the value returned by reading R15
- * is implementation defined.
- *
- * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ
- *     TST: Rd, Rn, Rm, !Rs
- * BX: Rm
- * BLX(2): !Rm
- * BX: Rm (R15 legal, but discouraged)
- * BXJ: !Rm,
- * CLZ: !Rd, !Rm
- * CPY: Rd, Rm
- * LDC/2,STC/2 immediate offset & unindex: Rn
- * LDC/2,STC/2 immediate pre/post-indexed: !Rn
- * LDM(1/3): !Rn, register_list
- * LDM(2): !Rn, !register_list
- * LDR,STR,PLD immediate offset: Rd, Rn
- * LDR,STR,PLD register offset: Rd, Rn, !Rm
- * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm
- * LDR,STR immediate pre/post-indexed: Rd, !Rn
- * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm
- * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm
- * LDRB,STRB immediate offset: !Rd, Rn
- * LDRB,STRB register offset: !Rd, Rn, !Rm
- * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm
- * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn
- * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm
- * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm
- * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn
- * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm
- * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm
- * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn
- * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm
- * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn
- * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm
- * LDREX: !Rd, !Rn
- * MCR/2: !Rd
- * MCRR/2,MRRC/2: !Rd, !Rn
- * MLA: !Rd, !Rn, !Rm, !Rs
- * MOV: Rd
- * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register)
- * MRS,MSR: !Rd
- * MUL: !Rd, !Rm, !Rs
- * PKH{BT,TB}: !Rd, !Rn, !Rm
- * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn
- * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn
- * REV/16/SH: !Rd, !Rm
- * RFE: !Rn
- * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm
- * SEL: !Rd, !Rn, !Rm
- * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs
- * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs
- * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs
- * SSAT/16: !Rd, !Rm
- * STM(1/2): !Rn, register_list* (R15 in reg list not recommended)
- * STRT immediate pre/post-indexed: Rd*, !Rn
- * STRT register pre/post-indexed: Rd*, !Rn, !Rm
- * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm
- * STREX: !Rd, !Rn, !Rm
- * SWP/B: !Rd, !Rn, !Rm
- * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm
- * {S,U}XT{B,B16,H}: !Rd, !Rm
- * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs
- * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs
- *
- * May transfer control by writing R15 (possible mode changes or alternate
- * mode accesses marked by "*"):
- * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY,
- * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI*
- *
- * Instructions that do not take general registers, nor transfer control:
- * CDP/2, SETEND, SRS*
- */
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index 2ba7deb3072..1656c87501c 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -134,7 +134,8 @@ static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs,
                                  struct kprobe_ctlblk *kcb)
 {
         regs->ARM_pc += 4;
-        p->ainsn.insn_handler(p, regs);
+        if (p->ainsn.insn_check_cc(regs->ARM_cpsr))
+                p->ainsn.insn_handler(p, regs);
 }
 
 /*
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 69cfee0fe00..139e3c82736 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -221,7 +221,7 @@ again:
         prev_raw_count &= armpmu->max_period;
 
         if (overflow)
-                delta = armpmu->max_period - prev_raw_count + new_raw_count;
+                delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
         else
                 delta = new_raw_count - prev_raw_count;
 
@@ -746,7 +746,8 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 
         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 
-        while (tail && !((unsigned long)tail & 0x3))
+        while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
+               tail && !((unsigned long)tail & 0x3))
                 tail = user_backtrace(tail, entry);
 }
 
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 94bbedbed63..5e1e5419722 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -372,6 +372,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
         if (clone_flags & CLONE_SETTLS)
                 thread->tp_value = regs->ARM_r3;
 
+        thread_notify(THREAD_NOTIFY_COPY, thread);
+
         return 0;
 }
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 2bf27f364d0..8182f45ca49 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -767,12 +767,20 @@ long arch_ptrace(struct task_struct *child, long request,
 
 #ifdef CONFIG_HAVE_HW_BREAKPOINT
                 case PTRACE_GETHBPREGS:
+                        if (ptrace_get_breakpoints(child) < 0)
+                                return -ESRCH;
+
                         ret = ptrace_gethbpregs(child, addr,
                                                 (unsigned long __user *)data);
+                        ptrace_put_breakpoints(child);
                         break;
                 case PTRACE_SETHBPREGS:
+                        if (ptrace_get_breakpoints(child) < 0)
+                                return -ESRCH;
+
                         ret = ptrace_sethbpregs(child, addr,
                                                 (unsigned long __user *)data);
+                        ptrace_put_breakpoints(child);
                         break;
 #endif
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 8fe05ad932e..f29b8a29b17 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -479,7 +479,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode,
 {
 }
 
-static void broadcast_timer_setup(struct clock_event_device *evt)
+static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
 {
         evt->name       = "dummy_timer";
         evt->features   = CLOCK_EVT_FEAT_ONESHOT |
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index 7a576092291..40ee7e5045e 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -158,7 +158,7 @@ static int emulate_swpX(unsigned int address, unsigned int *data,
 
         if (res == 0) {
                 /*
-                 * Barrier also required between aquiring a lock for a
+                 * Barrier also required between acquiring a lock for a
                  * protected resource and accessing the resource. Inserted for
                  * same reason as above.
                  */
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index 4ad8da15ef2..af0aaebf4de 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -311,7 +311,7 @@ asmlinkage long sys_oabi_semtimedop(int semid,
         long err;
         int i;
 
-        if (nsops < 1)
+        if (nsops < 1 || nsops > SEMOPM)
                 return -EINVAL;
         sops = kmalloc(sizeof(*sops) * nsops, GFP_KERNEL);
         if (!sops)
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index f0000e188c8..3b54ad19d48 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -410,8 +410,7 @@ static int bad_syscall(int n, struct pt_regs *regs)
         struct thread_info *thread = current_thread_info();
         siginfo_t info;
 
-        if (current->personality != PER_LINUX &&
-            current->personality != PER_LINUX_32BIT &&
+        if ((current->personality & PER_MASK) != PER_LINUX &&
             thread->exec_domain->handler) {
                 thread->exec_domain->handler(n, regs);
                 return regs->ARM_r0;
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 19390231a0e..2d299bf5d72 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -83,6 +83,7 @@ config ARCH_AT91CAP9
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 config ARCH_AT572D940HF
         bool "AT572D940HF"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 2e74a19874d..295e1e77fa6 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -76,7 +76,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
         .pullup_pin     = AT91_PIN_PD9,
 };
 
-/* FIXME: user dependant */
+/* FIXME: user dependent */
 // static struct at91_cf_data __initdata carmeva_cf_data = {
 //      .det_pin        = AT91_PIN_PB0,
 //      .rst_pin        = AT91_PIN_PC5,
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 1f9d3cb64c5..d8df59a3426 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -30,6 +30,11 @@
 #include <mach/board.h>
 #include "generic.h"
 
+static void __init at91eb01_init_irq(void)
+{
+        at91x40_init_interrupts(NULL);
+}
+
 static void __init at91eb01_map_io(void)
 {
         at91x40_initialize(40000000);
@@ -38,7 +43,7 @@ static void __init at91eb01_map_io(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
         /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
         .timer          = &at91x40_timer,
-        .init_irq       = at91x40_init_interrupts,
+        .init_irq       = at91eb01_init_irq,
         .map_io         = at91eb01_map_io,
 MACHINE_END
 
diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h
index 27ac6f550fe..02182c16a02 100644
--- a/arch/arm/mach-at91/include/mach/at91_mci.h
+++ b/arch/arm/mach-at91/include/mach/at91_mci.h
@@ -102,7 +102,7 @@
 #define         AT91_MCI_RDIRE          (1 << 17)       /* Response Direction Error */
 #define         AT91_MCI_RCRCE          (1 << 18)       /* Response CRC Error */
 #define         AT91_MCI_RENDE          (1 << 19)       /* Response End Bit Error */
-#define         AT91_MCI_RTOE           (1 << 20)       /* Reponse Time-out Error */
+#define         AT91_MCI_RTOE           (1 << 20)       /* Response Time-out Error */
 #define         AT91_MCI_DCRCE          (1 << 21)       /* Data CRC Error */
 #define         AT91_MCI_DTOE           (1 << 22)       /* Data Time-out Error */
 #define         AT91_MCI_OVRE           (1 << 30)       /* Overrun */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 3bef931d0b1..0700f212530 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -27,6 +27,7 @@
 #define ARCH_ID_AT91SAM9G45     0x819b05a0
 #define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
 #define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
+#define ARCH_ID_AT91SAM9X5      0x819a05a0
 #define ARCH_ID_AT91CAP9        0x039A03A0
 
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
@@ -55,6 +56,12 @@ static inline unsigned long at91_cpu_fully_identify(void)
 #define ARCH_EXID_AT91SAM9G46   0x00000003
 #define ARCH_EXID_AT91SAM9G45   0x00000004
 
+#define ARCH_EXID_AT91SAM9G15   0x00000000
+#define ARCH_EXID_AT91SAM9G35   0x00000001
+#define ARCH_EXID_AT91SAM9X35   0x00000002
+#define ARCH_EXID_AT91SAM9G25   0x00000003
+#define ARCH_EXID_AT91SAM9X25   0x00000004
+
 static inline unsigned long at91_exid_identify(void)
 {
         return at91_sys_read(AT91_DBGU_EXID);
@@ -143,6 +150,27 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91sam9m11()    (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT91SAM9X5
+#define cpu_is_at91sam9x5()     (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
+#define cpu_is_at91sam9g15()    (cpu_is_at91sam9x5() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
+#define cpu_is_at91sam9g35()    (cpu_is_at91sam9x5() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
+#define cpu_is_at91sam9x35()    (cpu_is_at91sam9x5() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
+#define cpu_is_at91sam9g25()    (cpu_is_at91sam9x5() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
+#define cpu_is_at91sam9x25()    (cpu_is_at91sam9x5() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
+#else
+#define cpu_is_at91sam9x5()     (0)
+#define cpu_is_at91sam9g15()    (0)
+#define cpu_is_at91sam9g35()    (0)
+#define cpu_is_at91sam9x35()    (0)
+#define cpu_is_at91sam9g25()    (0)
+#define cpu_is_at91sam9x25()    (0)
+#endif
+
 #ifdef CONFIG_ARCH_AT91CAP9
 #define cpu_is_at91cap9()       (at91_cpu_identify() == ARCH_ID_AT91CAP9)
 #define cpu_is_at91cap9_revB()  (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index ddeb6453675..056dc6674b6 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -208,7 +208,7 @@ extern void at91_gpio_resume(void);
 
 /*-------------------------------------------------------------------------*/
 
-/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should
+/* wrappers for "new style" GPIO calls. the old AT91-specific ones should
  * eventually be removed (along with this errno.h inclusion), and the
  * gpio request/free calls should probably be implemented.
  */
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index 77f84b40dda..a1f328357aa 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -551,7 +551,7 @@ int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Config
 
 /****************************************************************************/
 /**
-*  @brief   Check the existance of pending descriptor
+*  @brief   Check the existence of pending descriptor
 *
 *  This function confirmes if there is any pending descriptor in the chain
 *  to program the channel
@@ -775,7 +775,7 @@ int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA Cha
 /**
 *  @brief   Read data DMAed to memory
 *
-*  This function will read data that has been DMAed to memory while transfering from:
+*  This function will read data that has been DMAed to memory while transferring from:
 *          - Memory to memory
 *          - Peripheral to memory
 *
@@ -941,7 +941,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configurat
 /**
 *  @brief   Sets channel specific user data
 *
-*  This function associates user data to a specif DMA channel
+*  This function associates user data to a specific DMA channel
 *
 */
 /****************************************************************************/
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index 8d1baf3f468..d87ad30dda3 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -629,7 +629,7 @@ EXPORT_SYMBOL(dma_get_device_descriptor_ring);
 *   Configures a DMA channel.
 *
 *   @return
-*       >= 0    - Initialization was successfull.
+*       >= 0    - Initialization was successful.
 *
 *       -EBUSY  - Device is currently being used.
 *       -ENODEV - Device handed in is invalid.
@@ -673,7 +673,7 @@ static int ConfigChannel(DMA_Handle_t handle)
 /**
 *   Initializes all of the data structures associated with the DMA.
 *   @return
-*       >= 0    - Initialization was successfull.
+*       >= 0    - Initialization was successful.
 *
 *       -EBUSY  - Device is currently being used.
 *       -ENODEV - Device handed in is invalid.
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
index 6c8da2b9fc1..e6a1dc484ca 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -362,7 +362,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configurati
 /**
 *  @brief   Read data DMA transferred to memory
 *
-*  This function will read data that has been DMAed to memory while transfering from:
+*  This function will read data that has been DMAed to memory while transferring from:
 *          - Memory to memory
 *          - Peripheral to memory
 *
@@ -446,7 +446,7 @@ void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handle *
 
 /****************************************************************************/
 /**
-*  @brief   Check the existance of pending descriptor
+*  @brief   Check the existence of pending descriptor
 *
 *  This function confirmes if there is any pending descriptor in the chain
 *  to program the channel
@@ -542,7 +542,7 @@ dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
 /**
 *  @brief   Sets channel specific user data
 *
-*  This function associates user data to a specif DMA channel
+*  This function associates user data to a specific DMA channel
 *
 */
 /****************************************************************************/
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
index 70eaea866cf..161973385fa 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -180,7 +180,7 @@ typedef enum {
 
 #define chipcHw_XTAL_FREQ_Hz                    25000000        /* Reference clock frequency in Hz */
 
-/* Programable pin defines */
+/* Programmable pin defines */
 #define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
                                                                              /* GPIO pin 0 - 60 */
 #define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 0)        /* UART Transmit */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
index c78833acb37..03238c29900 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -832,7 +832,7 @@ static inline void chipcHw_setUsbDevice(void)
 
 /****************************************************************************/
 /**
-*  @brief   Lower layer funtion to enable/disable a clock of a certain device
+*  @brief   Lower layer function to enable/disable a clock of a certain device
 *
 *  This function enables/disables a core clock
 *
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
index e01fc4607c9..0aeb6a6fe7f 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -109,9 +109,9 @@
 #define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
 
 /* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM       27    /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */
+#define INTCHW_INTC1_DDRVPMP_BITNUM       27    /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
 #define INTCHW_INTC1_DDRVPMT_BITNUM       26    /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM          26    /* DDR and PLL clock phase relationship interupt (For A0 only)) */
+#define INTCHW_INTC1_DDRP_BITNUM          26    /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
 #define INTCHW_INTC1_RTC2_BITNUM          25    /* Real time clock tamper interrupt */
 #define INTCHW_INTC1_VDEC_BITNUM          24    /* Hantro Video Decoder interrupt */
 /* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
index 06a355481ea..0992842caa7 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -88,7 +88,7 @@
 /* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
 /* Enable wait pin during burst write or read */
 #define REG_UMI_TCR_WAITEN              0x80000000
-/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */
+/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
 #define REG_UMI_TCR_LOWFREQ             0x40000000
 /* 1=synch write, 0=async write */
 #define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 32f147998cd..c0deacae778 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -63,6 +63,7 @@ config MACH_DAVINCI_EVM
         depends on ARCH_DAVINCI_DM644x
         select MISC_DEVICES
         select EEPROM_AT24
+        select I2C
         help
           Configure this option to specify the whether the board used
           for development is a DM644x EVM
@@ -72,6 +73,7 @@ config MACH_SFFSDR
         depends on ARCH_DAVINCI_DM644x
         select MISC_DEVICES
         select EEPROM_AT24
+        select I2C
         help
           Say Y here to select the Lyrtech Small Form Factor
           Software Defined Radio (SFFSDR) board.
@@ -105,6 +107,7 @@ config MACH_DAVINCI_DM6467_EVM
         select MACH_DAVINCI_DM6467TEVM
         select MISC_DEVICES
         select EEPROM_AT24
+        select I2C
         help
           Configure this option to specify the whether the board used
           for development is a DM6467 EVM
@@ -118,6 +121,7 @@ config MACH_DAVINCI_DM365_EVM
         depends on ARCH_DAVINCI_DM365
         select MISC_DEVICES
         select EEPROM_AT24
+        select I2C
         help
           Configure this option to specify whether the board used
           for development is a DM365 EVM
@@ -129,6 +133,7 @@ config MACH_DAVINCI_DA830_EVM
         select GPIO_PCF857X
         select MISC_DEVICES
         select EEPROM_AT24
+        select I2C
         help
           Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
 
@@ -205,6 +210,7 @@ config MACH_MITYOMAPL138
         depends on ARCH_DAVINCI_DA850
         select MISC_DEVICES
         select EEPROM_AT24
+        select I2C
         help
           Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
           System on Module.  Information on this SoM may be found at
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 2aa79c54f98..606a6f27ed6 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -29,7 +29,7 @@
 #include <mach/mux.h>
 #include <mach/spi.h>
 
-#define MITYOMAPL138_PHY_ID             "0:03"
+#define MITYOMAPL138_PHY_ID             ""
 
 #define FACTORY_CONFIG_MAGIC    0x012C0138
 #define FACTORY_CONFIG_VERSION  0x00010001
@@ -414,7 +414,7 @@ static struct resource mityomapl138_nandflash_resource[] = {
 
 static struct platform_device mityomapl138_nandflash_device = {
         .name           = "davinci_nand",
-        .id             = 0,
+        .id             = 1,
         .dev            = {
                 .platform_data  = &mityomapl138_nandflash_data,
         },
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 6c389ff1020..3e7be2de96d 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -11,7 +11,7 @@
  * DM644X-EVM board. It has:
  *      DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
  *      USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
- *      Additionaly realtime clock, IR remote control receiver,
+ *      Additionally realtime clock, IR remote control receiver,
  *      IR Blaster based on MSP430 (firmware although is different
  *      from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
  *      with PATA interface, two muxed red-green leds.
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 4a68c2b1ec1..0a95be1512b 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -167,7 +167,7 @@ static int davinci_cpu_init(struct cpufreq_policy *policy)
         /*
          * Time measurement across the target() function yields ~1500-1800us
          * time taken with no drivers on notification list.
-         * Setting the latency to 2000 us to accomodate addition of drivers
+         * Setting the latency to 2000 us to accommodate addition of drivers
          * to pre/post change notification list.
          */
         policy->cpuinfo.transition_latency = 2000 * 1000;
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 68fe4c289d7..b95b9196dee 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1123,7 +1123,7 @@ void __init da850_init(void)
          * This helps keeping the peripherals on this domain insulated
          * from CPU frequency changes caused by DVFS. The firmware sets
          * both PLL0 and PLL1 to the same frequency so, there should not
-         * be any noticible change even in non-DVFS use cases.
+         * be any noticeable change even in non-DVFS use cases.
          */
         da850_set_async3_src(1);
 
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 625d4b66718..58a02dc7b15 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -39,7 +39,8 @@
 #define DA8XX_GPIO_BASE                 0x01e26000
 #define DA8XX_I2C1_BASE                 0x01e28000
 #define DA8XX_SPI0_BASE                 0x01c41000
-#define DA8XX_SPI1_BASE                 0x01f0e000
+#define DA830_SPI1_BASE                 0x01e12000
+#define DA850_SPI1_BASE                 0x01f0e000
 
 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
@@ -762,8 +763,8 @@ static struct resource da8xx_spi0_resources[] = {
 
 static struct resource da8xx_spi1_resources[] = {
         [0] = {
-                .start  = DA8XX_SPI1_BASE,
-                .end    = DA8XX_SPI1_BASE + SZ_4K - 1,
+                .start  = DA830_SPI1_BASE,
+                .end    = DA830_SPI1_BASE + SZ_4K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -832,5 +833,10 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info,
 
         da8xx_spi_pdata[instance].num_chipselect = len;
 
+        if (instance == 1 && cpu_is_davinci_da850()) {
+                da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
+                da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
+        }
+
         return platform_device_register(&da8xx_spi_device[instance]);
 }
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 76364d1345d..a3a94e9c937 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -314,7 +314,7 @@ static struct clk timer2_clk = {
         .name = "timer2",
         .parent = &pll1_aux_clk,
         .lpsc = DAVINCI_LPSC_TIMER2,
-        .usecount = 1,              /* REVISIT: why cant' this be disabled? */
+        .usecount = 1,              /* REVISIT: why can't this be disabled? */
 };
 
 static struct clk timer3_clk = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 9a2376b3137..4c82c271629 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -274,7 +274,7 @@ static struct clk timer2_clk = {
         .name = "timer2",
         .parent = &pll1_aux_clk,
         .lpsc = DAVINCI_LPSC_TIMER2,
-        .usecount = 1,              /* REVISIT: why cant' this be disabled? */
+        .usecount = 1,              /* REVISIT: why can't this be disabled? */
 };
 
 static struct clk_lookup dm644x_clks[] = {
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index cea6b897204..957fb87e832 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -4,7 +4,7 @@
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
  * Defines the cpu_is_*() macros for runtime detection of DaVinci
- * device type.  In addtion, if support for a given device is not
+ * device type.  In addition, if support for a given device is not
  * compiled in to the kernel, the macros return 0 so that
  * resulting code can be optimized out.
  *
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 9f1befc5ac3..f8b7ea4f623 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -24,6 +24,9 @@
 
 #define UART_SHIFT      2
 
+#define davinci_uart_v2p(x)     ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
+#define davinci_uart_p2v(x)     ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
+
                 .pushsection .data
 davinci_uart_phys:      .word   0
 davinci_uart_virt:      .word   0
@@ -34,7 +37,7 @@ davinci_uart_virt:	.word	0
                 /* Use davinci_uart_phys/virt if already configured */
 10:             mrc     p15, 0, \rp, c1, c0
                 tst     \rp, #1                 @ MMU enabled?
-                ldreq   \rp, =__virt_to_phys(davinci_uart_phys)
+                ldreq   \rp, =davinci_uart_v2p(davinci_uart_phys)
                 ldrne   \rp, =davinci_uart_phys
                 add     \rv, \rp, #4            @ davinci_uart_virt
                 ldr     \rp, [\rp, #0]
@@ -48,18 +51,18 @@ davinci_uart_virt:	.word	0
                 tst     \rp, #1                 @ MMU enabled?
 
                 /* Copy uart phys address from decompressor uart info */
-                ldreq   \rv, =__virt_to_phys(davinci_uart_phys)
+                ldreq   \rv, =davinci_uart_v2p(davinci_uart_phys)
                 ldrne   \rv, =davinci_uart_phys
                 ldreq   \rp, =DAVINCI_UART_INFO
-                ldrne   \rp, =__phys_to_virt(DAVINCI_UART_INFO)
+                ldrne   \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
                 ldr     \rp, [\rp, #0]
                 str     \rp, [\rv]
 
                 /* Copy uart virt address from decompressor uart info */
-                ldreq   \rv, =__virt_to_phys(davinci_uart_virt)
+                ldreq   \rv, =davinci_uart_v2p(davinci_uart_virt)
                 ldrne   \rv, =davinci_uart_virt
                 ldreq   \rp, =DAVINCI_UART_INFO
-                ldrne   \rp, =__phys_to_virt(DAVINCI_UART_INFO)
+                ldrne   \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
                 ldr     \rp, [\rp, #4]
                 str     \rp, [\rv]
 
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 8051110b8ac..c9e6ce185a6 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -22,7 +22,7 @@
  *
  * This area sits just below the page tables (see arch/arm/kernel/head.S).
  */
-#define DAVINCI_UART_INFO       (PHYS_OFFSET + 0x3ff8)
+#define DAVINCI_UART_INFO       (PLAT_PHYS_OFFSET + 0x3ff8)
 
 #define DAVINCI_UART0_BASE      (IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE      (IO_PHYS + 0x20400)
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 47723e8d75a..78d80683cdc 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,8 +25,7 @@
 
 #include <mach/serial.h>
 
-static u32 *uart;
-static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+u32 *uart;
 
 /* PORT_16C550A, in polled non-fifo mode */
 static void putc(char c)
@@ -44,6 +43,8 @@ static inline void flush(void)
 
 static inline void set_uart_info(u32 phys, void * __iomem virt)
 {
+        u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+
         uart = (u32 *)phys;
         uart_info[0] = phys;
         uart_info[1] = (u32)virt;
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index e6269a6e001..bfe68ec4e1a 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -29,8 +29,6 @@
 #include <mach/common.h>
 #include <asm/mach/irq.h>
 
-#define IRQ_BIT(irq)            ((irq) & 0x1f)
-
 #define FIQ_REG0_OFFSET         0x0000
 #define FIQ_REG1_OFFSET         0x0004
 #define IRQ_REG0_OFFSET         0x0008
@@ -42,78 +40,33 @@
 #define IRQ_INTPRI0_REG_OFFSET  0x0030
 #define IRQ_INTPRI7_REG_OFFSET  0x004C
 
-static inline unsigned int davinci_irq_readl(int offset)
-{
-        return __raw_readl(davinci_intc_base + offset);
-}
-
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
         __raw_writel(value, davinci_intc_base + offset);
 }
 
-/* Disable interrupt */
-static void davinci_mask_irq(struct irq_data *d)
+static __init void
+davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 {
-        unsigned int mask;
-        u32 l;
-
-        mask = 1 << IRQ_BIT(d->irq);
-
-        if (d->irq > 31) {
-                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-                l &= ~mask;
-                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-        } else {
-                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-                l &= ~mask;
-                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-        }
-}
-
-/* Enable interrupt */
-static void davinci_unmask_irq(struct irq_data *d)
-{
-        unsigned int mask;
-        u32 l;
-
-        mask = 1 << IRQ_BIT(d->irq);
-
-        if (d->irq > 31) {
-                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-                l |= mask;
-                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-        } else {
-                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-                l |= mask;
-                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-        }
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+
+        ct->regs.ack = IRQ_REG0_OFFSET;
+        ct->regs.mask = IRQ_ENT_REG0_OFFSET;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-/* EOI interrupt */
-static void davinci_ack_irq(struct irq_data *d)
-{
-        unsigned int mask;
-
-        mask = 1 << IRQ_BIT(d->irq);
-
-        if (d->irq > 31)
-                davinci_irq_writel(mask, IRQ_REG1_OFFSET);
-        else
-                davinci_irq_writel(mask, IRQ_REG0_OFFSET);
-}
-
-static struct irq_chip davinci_irq_chip_0 = {
-        .name           = "AINTC",
-        .irq_ack        = davinci_ack_irq,
-        .irq_mask       = davinci_mask_irq,
-        .irq_unmask     = davinci_unmask_irq,
-};
-
 /* ARM Interrupt Controller Initialization */
 void __init davinci_irq_init(void)
 {
-        unsigned i;
+        unsigned i, j;
         const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
 
         davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
@@ -144,7 +97,6 @@ void __init davinci_irq_init(void)
         davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 
         for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
-                unsigned        j;
                 u32             pri;
 
                 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
@@ -152,13 +104,8 @@ void __init davinci_irq_init(void)
                 davinci_irq_writel(pri, i);
         }
 
-        /* set up genirq dispatch for ARM INTC */
-        for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
-                irq_set_chip(i, &davinci_irq_chip_0);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                if (i != IRQ_TINT1_TINT34)
-                        irq_set_handler(i, handle_edge_irq);
-                else
-                        irq_set_handler(i, handle_level_irq);
-        }
+        for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
+                davinci_alloc_gc(davinci_intc_base + j, i, 32);
+
+        irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e06a88f1f81..5ed51b84c1b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,10 +16,8 @@
 #include <linux/serial_8250.h>
 #include <linux/clk.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
-#include <linux/spi/orion_spi.h>
+#include <linux/serial_8250.h>
 #include <linux/gpio.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -32,11 +30,12 @@
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
-#include <plat/mv_xor.h>
-#include <plat/ehci-orion.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
+static int get_tclk(void);
+
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -70,463 +69,106 @@ void __init dove_map_io(void)
 }
 
 /*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data dove_ehci_data = {
-        .dram           = &dove_mbus_dram_info,
-        .phy_version    = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-/*****************************************************************************
  * EHCI0
  ****************************************************************************/
-static struct resource dove_ehci0_resources[] = {
-        {
-                .start  = DOVE_USB0_PHYS_BASE,
-                .end    = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_USB0,
-                .end    = IRQ_DOVE_USB0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_ehci0 = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &dove_ehci_data,
-        },
-        .resource       = dove_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(dove_ehci0_resources),
-};
-
 void __init dove_ehci0_init(void)
 {
-        platform_device_register(&dove_ehci0);
+        orion_ehci_init(&dove_mbus_dram_info,
+                        DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
 }
 
 /*****************************************************************************
  * EHCI1
  ****************************************************************************/
-static struct resource dove_ehci1_resources[] = {
-        {
-                .start  = DOVE_USB1_PHYS_BASE,
-                .end    = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_USB1,
-                .end    = IRQ_DOVE_USB1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_ehci1 = {
-        .name           = "orion-ehci",
-        .id             = 1,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &dove_ehci_data,
-        },
-        .resource       = dove_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(dove_ehci1_resources),
-};
-
 void __init dove_ehci1_init(void)
 {
-        platform_device_register(&dove_ehci1);
+        orion_ehci_1_init(&dove_mbus_dram_info,
+                          DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
 }
 
 /*****************************************************************************
  * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
-        .t_clk          = 0,
-        .dram           = &dove_mbus_dram_info,
-};
-
-static struct resource dove_ge00_shared_resources[] = {
-        {
-                .name   = "ge00 base",
-                .start  = DOVE_GE00_PHYS_BASE + 0x2000,
-                .end    = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device dove_ge00_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &dove_ge00_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = dove_ge00_shared_resources,
-};
-
-static struct resource dove_ge00_resources[] = {
-        {
-                .name   = "ge00 irq",
-                .start  = IRQ_DOVE_GE00_SUM,
-                .end    = IRQ_DOVE_GE00_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_ge00 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = dove_ge00_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &dove_ge00_shared;
-        dove_ge00.dev.platform_data = eth_data;
-
-        platform_device_register(&dove_ge00_shared);
-        platform_device_register(&dove_ge00);
+        orion_ge00_init(eth_data, &dove_mbus_dram_info,
+                        DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
+                        0, get_tclk());
 }
 
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static struct resource dove_rtc_resource[] = {
-        {
-                .start  = DOVE_RTC_PHYS_BASE,
-                .end    = DOVE_RTC_PHYS_BASE + 32 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_RTC,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
 void __init dove_rtc_init(void)
 {
-        platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
+        orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
 }
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource dove_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = DOVE_SATA_PHYS_BASE,
-                .end    = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_DOVE_SATA,
-                .end    = IRQ_DOVE_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(dove_sata_resources),
-        .resource       = dove_sata_resources,
-};
-
 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        sata_data->dram = &dove_mbus_dram_info;
-        dove_sata.dev.platform_data = sata_data;
-        platform_device_register(&dove_sata);
+        orion_sata_init(sata_data, &dove_mbus_dram_info,
+                        DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
+
 }
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart0_data[] = {
-        {
-                .mapbase        = DOVE_UART0_PHYS_BASE,
-                .membase        = (char *)DOVE_UART0_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart0_resources[] = {
-        {
-                .start          = DOVE_UART0_PHYS_BASE,
-                .end            = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_0,
-                .end            = IRQ_DOVE_UART_0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = dove_uart0_data,
-        },
-        .resource               = dove_uart0_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart0_resources),
-};
-
 void __init dove_uart0_init(void)
 {
-        platform_device_register(&dove_uart0);
+        orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
+                         IRQ_DOVE_UART_0, get_tclk());
 }
 
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart1_data[] = {
-        {
-                .mapbase        = DOVE_UART1_PHYS_BASE,
-                .membase        = (char *)DOVE_UART1_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart1_resources[] = {
-        {
-                .start          = DOVE_UART1_PHYS_BASE,
-                .end            = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_1,
-                .end            = IRQ_DOVE_UART_1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = dove_uart1_data,
-        },
-        .resource               = dove_uart1_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart1_resources),
-};
-
 void __init dove_uart1_init(void)
 {
-        platform_device_register(&dove_uart1);
+        orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
+                         IRQ_DOVE_UART_1, get_tclk());
 }
 
 /*****************************************************************************
  * UART2
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart2_data[] = {
-        {
-                .mapbase        = DOVE_UART2_PHYS_BASE,
-                .membase        = (char *)DOVE_UART2_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_2,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart2_resources[] = {
-        {
-                .start          = DOVE_UART2_PHYS_BASE,
-                .end            = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_2,
-                .end            = IRQ_DOVE_UART_2,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart2 = {
-        .name                   = "serial8250",
-        .id                     = 2,
-        .dev                    = {
-                .platform_data  = dove_uart2_data,
-        },
-        .resource               = dove_uart2_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart2_resources),
-};
-
 void __init dove_uart2_init(void)
 {
-        platform_device_register(&dove_uart2);
+        orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
+                         IRQ_DOVE_UART_2, get_tclk());
 }
 
 /*****************************************************************************
  * UART3
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart3_data[] = {
-        {
-                .mapbase        = DOVE_UART3_PHYS_BASE,
-                .membase        = (char *)DOVE_UART3_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_3,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart3_resources[] = {
-        {
-                .start          = DOVE_UART3_PHYS_BASE,
-                .end            = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_3,
-                .end            = IRQ_DOVE_UART_3,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart3 = {
-        .name                   = "serial8250",
-        .id                     = 3,
-        .dev                    = {
-                .platform_data  = dove_uart3_data,
-        },
-        .resource               = dove_uart3_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart3_resources),
-};
-
 void __init dove_uart3_init(void)
 {
-        platform_device_register(&dove_uart3);
+        orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
+                         IRQ_DOVE_UART_3, get_tclk());
 }
 
 /*****************************************************************************
- * SPI0
+ * SPI
  ****************************************************************************/
-static struct orion_spi_info dove_spi0_data = {
-        .tclk           = 0,
-};
-
-static struct resource dove_spi0_resources[] = {
-        {
-                .start  = DOVE_SPI0_PHYS_BASE,
-                .end    = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_SPI0,
-                .end    = IRQ_DOVE_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_spi0 = {
-        .name           = "orion_spi",
-        .id             = 0,
-        .resource       = dove_spi0_resources,
-        .dev            = {
-                .platform_data  = &dove_spi0_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_spi0_resources),
-};
-
 void __init dove_spi0_init(void)
 {
-        platform_device_register(&dove_spi0);
+        orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
 }
 
-/*****************************************************************************
- * SPI1
- ****************************************************************************/
-static struct orion_spi_info dove_spi1_data = {
-        .tclk           = 0,
-};
-
-static struct resource dove_spi1_resources[] = {
-        {
-                .start  = DOVE_SPI1_PHYS_BASE,
-                .end    = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_SPI1,
-                .end    = IRQ_DOVE_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_spi1 = {
-        .name           = "orion_spi",
-        .id             = 1,
-        .resource       = dove_spi1_resources,
-        .dev            = {
-                .platform_data  = &dove_spi1_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_spi1_resources),
-};
-
 void __init dove_spi1_init(void)
 {
-        platform_device_register(&dove_spi1);
+        orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
 }
 
 /*****************************************************************************
  * I2C
  ****************************************************************************/
-static struct mv64xxx_i2c_pdata dove_i2c_data = {
-        .freq_m         = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource dove_i2c_resources[] = {
-        {
-                .name   = "i2c base",
-                .start  = DOVE_I2C_PHYS_BASE,
-                .end    = DOVE_I2C_PHYS_BASE + 0x20 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "i2c irq",
-                .start  = IRQ_DOVE_I2C,
-                .end    = IRQ_DOVE_I2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_i2c = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(dove_i2c_resources),
-        .resource       = dove_i2c_resources,
-        .dev            = {
-                .platform_data = &dove_i2c_data,
-        },
-};
-
 void __init dove_i2c_init(void)
 {
-        platform_device_register(&dove_i2c);
+        orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
 }
 
 /*****************************************************************************
@@ -554,208 +196,22 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
- * XOR
- ****************************************************************************/
-static struct mv_xor_platform_shared_data dove_xor_shared_data = {
-        .dram           = &dove_mbus_dram_info,
-};
-
-/*****************************************************************************
  * XOR 0
  ****************************************************************************/
-static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
-
-static struct resource dove_xor0_shared_resources[] = {
-        {
-                .name   = "xor 0 low",
-                .start  = DOVE_XOR0_PHYS_BASE,
-                .end    = DOVE_XOR0_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 0 high",
-                .start  = DOVE_XOR0_HIGH_PHYS_BASE,
-                .end    = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device dove_xor0_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data = &dove_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_xor0_shared_resources),
-        .resource       = dove_xor0_shared_resources,
-};
-
-static struct resource dove_xor00_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_00,
-                .end    = IRQ_DOVE_XOR_00,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor00_data = {
-        .shared         = &dove_xor0_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor00_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(dove_xor00_resources),
-        .resource       = dove_xor00_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor00_data,
-        },
-};
-
-static struct resource dove_xor01_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_01,
-                .end    = IRQ_DOVE_XOR_01,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor01_data = {
-        .shared         = &dove_xor0_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor01_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(dove_xor01_resources),
-        .resource       = dove_xor01_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor01_data,
-        },
-};
-
 void __init dove_xor0_init(void)
 {
-        platform_device_register(&dove_xor0_shared);
-
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
-        platform_device_register(&dove_xor00_channel);
-
-        dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
-        platform_device_register(&dove_xor01_channel);
+        orion_xor0_init(&dove_mbus_dram_info,
+                        DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
+                        IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
 }
 
 /*****************************************************************************
  * XOR 1
  ****************************************************************************/
-static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource dove_xor1_shared_resources[] = {
-        {
-                .name   = "xor 0 low",
-                .start  = DOVE_XOR1_PHYS_BASE,
-                .end    = DOVE_XOR1_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 0 high",
-                .start  = DOVE_XOR1_HIGH_PHYS_BASE,
-                .end    = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device dove_xor1_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data = &dove_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_xor1_shared_resources),
-        .resource       = dove_xor1_shared_resources,
-};
-
-static struct resource dove_xor10_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_10,
-                .end    = IRQ_DOVE_XOR_10,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor10_data = {
-        .shared         = &dove_xor1_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor10_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(dove_xor10_resources),
-        .resource       = dove_xor10_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor10_data,
-        },
-};
-
-static struct resource dove_xor11_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_11,
-                .end    = IRQ_DOVE_XOR_11,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor11_data = {
-        .shared         = &dove_xor1_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor11_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(dove_xor11_resources),
-        .resource       = dove_xor11_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor11_data,
-        },
-};
-
 void __init dove_xor1_init(void)
 {
-        platform_device_register(&dove_xor1_shared);
-
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
-        platform_device_register(&dove_xor10_channel);
-
-        dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
-        platform_device_register(&dove_xor11_channel);
+        orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
+                        IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
 }
 
 /*****************************************************************************
@@ -833,14 +289,6 @@ void __init dove_init(void)
 #endif
         dove_setup_cpu_mbus();
 
-        dove_ge00_shared_data.t_clk = tclk;
-        dove_uart0_data[0].uartclk = tclk;
-        dove_uart1_data[0].uartclk = tclk;
-        dove_uart2_data[0].uartclk = tclk;
-        dove_uart3_data[0].uartclk = tclk;
-        dove_spi0_data.tclk = tclk;
-        dove_spi1_data.tclk = tclk;
-
         /* internal devices that every board has */
         dove_rtc_init();
         dove_xor0_init();
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index c66c7634690..51e0e411c9c 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -11,24 +11,17 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
-
+#include <plat/mpp.h>
 #include <mach/dove.h>
-
 #include "mpp.h"
 
-#define MPP_NR_REGS 4
-#define MPP_CTRL(i)     ((i) == 3 ?                             \
-                         DOVE_MPP_CTRL4_VIRT_BASE :             \
-                         DOVE_MPP_VIRT_BASE + (i) * 4)
-#define PMU_SIG_REGS 2
-#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
-
 struct dove_mpp_grp {
         int start;
         int end;
 };
 
-static struct dove_mpp_grp dove_mpp_grp[] = {
+/* Map a group to a range of GPIO pins in that group */
+static const struct dove_mpp_grp dove_mpp_grp[] = {
         [MPP_24_39] = {
                 .start  = 24,
                 .end    = 39,
@@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
                 .end    = 45,
         },
         [MPP_46_51] = {
-                .start  = 40,
-                .end    = 45,
+                .start  = 46,
+                .end    = 51,
         },
         [MPP_58_61] = {
                 .start  = 58,
@@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
         },
 };
 
+/* Enable gpio for a range of pins. mode should be a combination of
+   GPIO_OUTPUT_OK | GPIO_INPUT_OK */
 static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
 {
         int i;
@@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
                 orion_gpio_set_valid(i, gpio_mode);
 }
 
+/* Dump all the extra MPP registers. The platform code will dump the
+   registers for pins 0-23. */
 static void dove_mpp_dump_regs(void)
 {
-#ifdef DEBUG
-        int i;
+        pr_debug("PMU_CTRL4_CTRL: %08x\n",
+                 readl(DOVE_MPP_CTRL4_VIRT_BASE));
 
-        pr_debug("MPP_CTRL regs:");
-        for (i = 0; i < MPP_NR_REGS; i++)
-                printk(" %08x", readl(MPP_CTRL(i)));
-        printk("\n");
+        pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
+                 readl(DOVE_PMU_MPP_GENERAL_CTRL));
 
-        pr_debug("PMU_SIG_CTRL regs:");
-        for (i = 0; i < PMU_SIG_REGS; i++)
-                printk(" %08x", readl(PMU_SIG_CTRL(i)));
-        printk("\n");
-
-        pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
         pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
-#endif
 }
 
 static void dove_mpp_cfg_nfc(int sel)
@@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel)
 
 static void dove_mpp_cfg_au1(int sel)
 {
-        u32 mpp_ctrl4           = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
         u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
         u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
         u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
@@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
         writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
 }
 
-static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
-{
-        int start = dove_mpp_grp[num].start;
-        int end = dove_mpp_grp[num].end;
-        int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
-
-        *mpp_ctrl &= ~(0x1 << num);
-        *mpp_ctrl |= sel << num;
-
-        dove_mpp_gpio_mode(start, end, gpio_mode);
-}
-
-void __init dove_mpp_conf(unsigned int *mpp_list)
+/* Configure the group registers, enabling GPIO if sel indicates the
+   pin is to be used for GPIO */
+static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
 {
-        u32 mpp_ctrl[MPP_NR_REGS];
-        u32 pmu_mpp_ctrl = 0;
-        u32 pmu_sig_ctrl[PMU_SIG_REGS];
-        int i;
-
-        for (i = 0; i < MPP_NR_REGS; i++)
-                mpp_ctrl[i] = readl(MPP_CTRL(i));
-
-        for (i = 0; i < PMU_SIG_REGS; i++)
-                pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
-
-        pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        int gpio_mode;
 
-        dove_mpp_dump_regs();
-
-        for ( ; *mpp_list != MPP_END; mpp_list++) {
-                unsigned int num = MPP_NUM(*mpp_list);
-                unsigned int sel = MPP_SEL(*mpp_list);
-                int shift, gpio_mode;
-
-                if (num > MPP_MAX) {
-                        pr_err("dove: invalid MPP number (%u)\n", num);
-                        continue;
-                }
-
-                if (*mpp_list & MPP_NFC_MASK) {
-                        dove_mpp_cfg_nfc(sel);
-                        continue;
-                }
+        for ( ; *mpp_grp_list; mpp_grp_list++) {
+                unsigned int num = MPP_NUM(*mpp_grp_list);
+                unsigned int sel = MPP_SEL(*mpp_grp_list);
 
-                if (*mpp_list & MPP_AU1_MASK) {
-                        dove_mpp_cfg_au1(sel);
+                if (num > MPP_GRP_MAX) {
+                        pr_err("dove: invalid MPP GRP number (%u)\n", num);
                         continue;
                 }
 
-                if (*mpp_list & MPP_GRP_MASK) {
-                        dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
-                        continue;
-                }
-
-                shift = (num & 7) << 2;
-                if (*mpp_list & MPP_PMU_MASK) {
-                        pmu_mpp_ctrl |= (0x1 << num);
-                        pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
-                        pmu_sig_ctrl[num / 8] |= 0xf << shift;
-                        gpio_mode = 0;
-                } else {
-                        mpp_ctrl[num / 8] &= ~(0xf << shift);
-                        mpp_ctrl[num / 8] |= sel << shift;
-                        gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
-                }
+                mpp_ctrl4 &= ~(0x1 << num);
+                mpp_ctrl4 |= sel << num;
 
-                orion_gpio_set_valid(num, gpio_mode);
+                gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
+                dove_mpp_gpio_mode(dove_mpp_grp[num].start,
+                                   dove_mpp_grp[num].end, gpio_mode);
         }
+        writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
+}
 
-        for (i = 0; i < MPP_NR_REGS; i++)
-                writel(mpp_ctrl[i], MPP_CTRL(i));
+/* Configure the various MPP pins on Dove */
+void __init dove_mpp_conf(unsigned int *mpp_list,
+                          unsigned int *mpp_grp_list,
+                          unsigned int grp_au1_52_57,
+                          unsigned int grp_nfc_64_71)
+{
+        dove_mpp_dump_regs();
 
-        for (i = 0; i < PMU_SIG_REGS; i++)
-                writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
+        /* Use platform code for pins 0-23 */
+        orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
 
-        writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
+        dove_mpp_conf_grp(mpp_grp_list);
+        dove_mpp_cfg_au1(grp_au1_52_57);
+        dove_mpp_cfg_nfc(grp_nfc_64_71);
 
         dove_mpp_dump_regs();
 }
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
index 2a43ce413b1..fbec7c52bfa 100644
--- a/arch/arm/mach-dove/mpp.h
+++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
 #ifndef __ARCH_DOVE_MPP_CODED_H
 #define __ARCH_DOVE_MPP_CODED_H
 
-#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) (      \
-/* MPP/group number */          ((_num) & 0xff) |               \
-/* MPP select value */          (((_mode) & 0xf) << 8) |        \
-/* MPP PMU */                   ((!!(_pmu)) << 12) |            \
-/* group flag */                ((!!(_grp)) << 13) |            \
-/* AU1 flag */                  ((!!(_au1)) << 14) |            \
-/* NFCE flag */                 ((!!(_nfc)) << 15))
-
-#define MPP_MAX 71
-
-#define MPP_NUM(x)    ((x) & 0xff)
-#define MPP_SEL(x)    (((x) >> 8) & 0xf)
-
-#define MPP_PMU_MASK            MPP(0, 0x0, 1, 0, 0, 0)
-#define MPP_GRP_MASK            MPP(0, 0x0, 0, 1, 0, 0)
-#define MPP_AU1_MASK            MPP(0, 0x0, 0, 0, 1, 0)
-#define MPP_NFC_MASK            MPP(0, 0x0, 0, 0, 0, 1)
-
-#define MPP_END                 MPP(0xff, 0xf, 1, 1, 1, 1)
-
-#define MPP_PMU_DRIVE_0         0x1
-#define MPP_PMU_DRIVE_1         0x2
-#define MPP_PMU_SDI             0x3
-#define MPP_PMU_CPU_PWRDWN      0x4
-#define MPP_PMU_STBY_PWRDWN     0x5
-#define MPP_PMU_CORE_PWR_GOOD   0x8
-#define MPP_PMU_BAT_FAULT       0xa
-#define MPP_PMU_EXT0_WU         0xb
-#define MPP_PMU_EXT1_WU         0xc
-#define MPP_PMU_EXT2_WU         0xd
-#define MPP_PMU_BLINK           0xe
-#define MPP_PMU(_num, _mode)    MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
-
-#define MPP_PIN(_num, _mode)    MPP((_num), (_mode), 0, 0, 0, 0)
-#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 1, 0, 0)
-#define MPP_GRP_AU1(_mode)      MPP(0, (_mode), 0, 0, 1, 0)
-#define MPP_GRP_NFC(_mode)      MPP(0, (_mode), 0, 0, 0, 1)
-
-#define MPP0_GPIO0              MPP_PIN(0, 0x0)
-#define MPP0_UA2_RTSn           MPP_PIN(0, 0x2)
-#define MPP0_SDIO0_CD           MPP_PIN(0, 0x3)
-#define MPP0_LCD0_PWM           MPP_PIN(0, 0xf)
-
-#define MPP1_GPIO1              MPP_PIN(1, 0x0)
-#define MPP1_UA2_CTSn           MPP_PIN(1, 0x2)
-#define MPP1_SDIO0_WP           MPP_PIN(1, 0x3)
-#define MPP1_LCD1_PWM           MPP_PIN(1, 0xf)
-
-#define MPP2_GPIO2              MPP_PIN(2, 0x0)
-#define MPP2_SATA_PRESENT       MPP_PIN(2, 0x1)
-#define MPP2_UA2_TXD            MPP_PIN(2, 0x2)
-#define MPP2_SDIO0_BUS_POWER    MPP_PIN(2, 0x3)
-#define MPP2_UA_RTSn1           MPP_PIN(2, 0x4)
-
-#define MPP3_GPIO3              MPP_PIN(3, 0x0)
-#define MPP3_SATA_ACT           MPP_PIN(3, 0x1)
-#define MPP3_UA2_RXD            MPP_PIN(3, 0x2)
-#define MPP3_SDIO0_LED_CTRL     MPP_PIN(3, 0x3)
-#define MPP3_UA_CTSn1           MPP_PIN(3, 0x4)
-#define MPP3_SPI_LCD_CS1        MPP_PIN(3, 0xf)
-
-#define MPP4_GPIO4              MPP_PIN(4, 0x0)
-#define MPP4_UA3_RTSn           MPP_PIN(4, 0x2)
-#define MPP4_SDIO1_CD           MPP_PIN(4, 0x3)
-#define MPP4_SPI_1_MISO         MPP_PIN(4, 0x4)
-
-#define MPP5_GPIO5              MPP_PIN(5, 0x0)
-#define MPP5_UA3_CTSn           MPP_PIN(5, 0x2)
-#define MPP5_SDIO1_WP           MPP_PIN(5, 0x3)
-#define MPP5_SPI_1_CS           MPP_PIN(5, 0x4)
-
-#define MPP6_GPIO6              MPP_PIN(6, 0x0)
-#define MPP6_UA3_TXD            MPP_PIN(6, 0x2)
-#define MPP6_SDIO1_BUS_POWER    MPP_PIN(6, 0x3)
-#define MPP6_SPI_1_MOSI         MPP_PIN(6, 0x4)
-
-#define MPP7_GPIO7              MPP_PIN(7, 0x0)
-#define MPP7_UA3_RXD            MPP_PIN(7, 0x2)
-#define MPP7_SDIO1_LED_CTRL     MPP_PIN(7, 0x3)
-#define MPP7_SPI_1_SCK          MPP_PIN(7, 0x4)
-
-#define MPP8_GPIO8              MPP_PIN(8, 0x0)
-#define MPP8_WD_RST_OUT         MPP_PIN(8, 0x1)
-
-#define MPP9_GPIO9              MPP_PIN(9, 0x0)
-#define MPP9_PEX1_CLKREQn       MPP_PIN(9, 0x5)
-
-#define MPP10_GPIO10            MPP_PIN(10, 0x0)
-#define MPP10_SSP_SCLK          MPP_PIN(10, 0x5)
-
-#define MPP11_GPIO11            MPP_PIN(11, 0x0)
-#define MPP11_SATA_PRESENT      MPP_PIN(11, 0x1)
-#define MPP11_SATA_ACT          MPP_PIN(11, 0x2)
-#define MPP11_SDIO0_LED_CTRL    MPP_PIN(11, 0x3)
-#define MPP11_SDIO1_LED_CTRL    MPP_PIN(11, 0x4)
-#define MPP11_PEX0_CLKREQn      MPP_PIN(11, 0x5)
-
-#define MPP12_GPIO12            MPP_PIN(12, 0x0)
-#define MPP12_SATA_ACT          MPP_PIN(12, 0x1)
-#define MPP12_UA2_RTSn          MPP_PIN(12, 0x2)
-#define MPP12_AD0_I2S_EXT_MCLK  MPP_PIN(12, 0x3)
-#define MPP12_SDIO1_CD          MPP_PIN(12, 0x4)
-
-#define MPP13_GPIO13            MPP_PIN(13, 0x0)
-#define MPP13_UA2_CTSn          MPP_PIN(13, 0x2)
-#define MPP13_AD1_I2S_EXT_MCLK  MPP_PIN(13, 0x3)
-#define MPP13_SDIO1WP           MPP_PIN(13, 0x4)
-#define MPP13_SSP_EXTCLK        MPP_PIN(13, 0x5)
-
-#define MPP14_GPIO14            MPP_PIN(14, 0x0)
-#define MPP14_UA2_TXD           MPP_PIN(14, 0x2)
-#define MPP14_SDIO1_BUS_POWER   MPP_PIN(14, 0x4)
-#define MPP14_SSP_RXD           MPP_PIN(14, 0x5)
-
-#define MPP15_GPIO15            MPP_PIN(15, 0x0)
-#define MPP15_UA2_RXD           MPP_PIN(15, 0x2)
-#define MPP15_SDIO1_LED_CTRL    MPP_PIN(15, 0x4)
-#define MPP15_SSP_SFRM          MPP_PIN(15, 0x5)
-
-#define MPP16_GPIO16            MPP_PIN(16, 0x0)
-#define MPP16_UA3_RTSn          MPP_PIN(16, 0x2)
-#define MPP16_SDIO0_CD          MPP_PIN(16, 0x3)
-#define MPP16_SPI_LCD_CS1       MPP_PIN(16, 0x4)
-#define MPP16_AC97_SDATA_IN1    MPP_PIN(16, 0x5)
-
-#define MPP17_GPIO17            MPP_PIN(17, 0x0)
-#define MPP17_AC97_SYSCLK_OUT   MPP_PIN(17, 0x1)
-#define MPP17_UA3_CTSn          MPP_PIN(17, 0x2)
-#define MPP17_SDIO0_WP          MPP_PIN(17, 0x3)
-#define MPP17_TW_SDA2           MPP_PIN(17, 0x4)
-#define MPP17_AC97_SDATA_IN2    MPP_PIN(17, 0x5)
-
-#define MPP18_GPIO18            MPP_PIN(18, 0x0)
-#define MPP18_UA3_TXD           MPP_PIN(18, 0x2)
-#define MPP18_SDIO0_BUS_POWER   MPP_PIN(18, 0x3)
-#define MPP18_LCD0_PWM          MPP_PIN(18, 0x4)
-#define MPP18_AC_SDATA_IN3      MPP_PIN(18, 0x5)
-
-#define MPP19_GPIO19            MPP_PIN(19, 0x0)
-#define MPP19_UA3_RXD           MPP_PIN(19, 0x2)
-#define MPP19_SDIO0_LED_CTRL    MPP_PIN(19, 0x3)
-#define MPP19_TW_SCK2           MPP_PIN(19, 0x4)
-
-#define MPP20_GPIO20            MPP_PIN(20, 0x0)
-#define MPP20_AC97_SYSCLK_OUT   MPP_PIN(20, 0x1)
-#define MPP20_SPI_LCD_MISO      MPP_PIN(20, 0x2)
-#define MPP20_SDIO1_CD          MPP_PIN(20, 0x3)
-#define MPP20_SDIO0_CD          MPP_PIN(20, 0x5)
-#define MPP20_SPI_1_MISO        MPP_PIN(20, 0x6)
-
-#define MPP21_GPIO21            MPP_PIN(21, 0x0)
-#define MPP21_UA1_RTSn          MPP_PIN(21, 0x1)
-#define MPP21_SPI_LCD_CS0       MPP_PIN(21, 0x2)
-#define MPP21_SDIO1_WP          MPP_PIN(21, 0x3)
-#define MPP21_SSP_SFRM          MPP_PIN(21, 0x4)
-#define MPP21_SDIO0_WP          MPP_PIN(21, 0x5)
-#define MPP21_SPI_1_CS          MPP_PIN(21, 0x6)
-
-#define MPP22_GPIO22            MPP_PIN(22, 0x0)
-#define MPP22_UA1_CTSn          MPP_PIN(22, 0x1)
-#define MPP22_SPI_LCD_MOSI      MPP_PIN(22, 0x2)
-#define MPP22_SDIO1_BUS_POWER   MPP_PIN(22, 0x3)
-#define MPP22_SSP_TXD           MPP_PIN(22, 0x4)
-#define MPP22_SDIO0_BUS_POWER   MPP_PIN(22, 0x5)
-#define MPP22_SPI_1_MOSI        MPP_PIN(22, 0x6)
-
-#define MPP23_GPIO23            MPP_PIN(23, 0x0)
-#define MPP23_SPI_LCD_SCK       MPP_PIN(23, 0x2)
-#define MPP23_SDIO1_LED_CTRL    MPP_PIN(23, 0x3)
-#define MPP23_SSP_SCLK          MPP_PIN(23, 0x4)
-#define MPP23_SDIO0_LED_CTRL    MPP_PIN(23, 0x5)
-#define MPP23_SPI_1_SCK         MPP_PIN(23, 0x6)
+#define MPP(_num, _sel, _in, _out) ( \
+        /* MPP number */                ((_num) & 0xff) | \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
+        /* may be input signal */       ((!!(_in)) << 12) | \
+        /* may be output signal */      ((!!(_out)) << 13))
+
+#define MPP0_GPIO0              MPP(0, 0x0, 1, 1)
+#define MPP0_UA2_RTSn           MPP(0, 0x2, 0, 0)
+#define MPP0_SDIO0_CD           MPP(0, 0x3, 0, 0)
+#define MPP0_LCD0_PWM           MPP(0, 0xf, 0, 0)
+
+#define MPP1_GPIO1              MPP(1, 0x0, 1, 1)
+#define MPP1_UA2_CTSn           MPP(1, 0x2, 0, 0)
+#define MPP1_SDIO0_WP           MPP(1, 0x3, 0, 0)
+#define MPP1_LCD1_PWM           MPP(1, 0xf, 0, 0)
+
+#define MPP2_GPIO2              MPP(2, 0x0, 1, 1)
+#define MPP2_SATA_PRESENT       MPP(2, 0x1, 0, 0)
+#define MPP2_UA2_TXD            MPP(2, 0x2, 0, 0)
+#define MPP2_SDIO0_BUS_POWER    MPP(2, 0x3, 0, 0)
+#define MPP2_UA_RTSn1           MPP(2, 0x4, 0, 0)
+
+#define MPP3_GPIO3              MPP(3, 0x0, 1, 1)
+#define MPP3_SATA_ACT           MPP(3, 0x1, 0, 0)
+#define MPP3_UA2_RXD            MPP(3, 0x2, 0, 0)
+#define MPP3_SDIO0_LED_CTRL     MPP(3, 0x3, 0, 0)
+#define MPP3_UA_CTSn1           MPP(3, 0x4, 0, 0)
+#define MPP3_SPI_LCD_CS1        MPP(3, 0xf, 0, 0)
+
+#define MPP4_GPIO4              MPP(4, 0x0, 1, 1)
+#define MPP4_UA3_RTSn           MPP(4, 0x2, 0, 0)
+#define MPP4_SDIO1_CD           MPP(4, 0x3, 0, 0)
+#define MPP4_SPI_1_MISO         MPP(4, 0x4, 0, 0)
+
+#define MPP5_GPIO5              MPP(5, 0x0, 1, 1)
+#define MPP5_UA3_CTSn           MPP(5, 0x2, 0, 0)
+#define MPP5_SDIO1_WP           MPP(5, 0x3, 0, 0)
+#define MPP5_SPI_1_CS           MPP(5, 0x4, 0, 0)
+
+#define MPP6_GPIO6              MPP(6, 0x0, 1, 1)
+#define MPP6_UA3_TXD            MPP(6, 0x2, 0, 0)
+#define MPP6_SDIO1_BUS_POWER    MPP(6, 0x3, 0, 0)
+#define MPP6_SPI_1_MOSI         MPP(6, 0x4, 0, 0)
+
+#define MPP7_GPIO7              MPP(7, 0x0, 1, 1)
+#define MPP7_UA3_RXD            MPP(7, 0x2, 0, 0)
+#define MPP7_SDIO1_LED_CTRL     MPP(7, 0x3, 0, 0)
+#define MPP7_SPI_1_SCK          MPP(7, 0x4, 0, 0)
+
+#define MPP8_GPIO8              MPP(8, 0x0, 1, 1)
+#define MPP8_WD_RST_OUT         MPP(8, 0x1, 0, 0)
+
+#define MPP9_GPIO9              MPP(9, 0x0, 1, 1)
+#define MPP9_PEX1_CLKREQn       MPP(9, 0x5, 0, 0)
+
+#define MPP10_GPIO10            MPP(10, 0x0, 1, 1)
+#define MPP10_SSP_SCLK          MPP(10, 0x5, 0, 0)
+
+#define MPP11_GPIO11            MPP(11, 0x0, 1, 1)
+#define MPP11_SATA_PRESENT      MPP(11, 0x1, 0, 0)
+#define MPP11_SATA_ACT          MPP(11, 0x2, 0, 0)
+#define MPP11_SDIO0_LED_CTRL    MPP(11, 0x3, 0, 0)
+#define MPP11_SDIO1_LED_CTRL    MPP(11, 0x4, 0, 0)
+#define MPP11_PEX0_CLKREQn      MPP(11, 0x5, 0, 0)
+
+#define MPP12_GPIO12            MPP(12, 0x0, 1, 1)
+#define MPP12_SATA_ACT          MPP(12, 0x1, 0, 0)
+#define MPP12_UA2_RTSn          MPP(12, 0x2, 0, 0)
+#define MPP12_AD0_I2S_EXT_MCLK  MPP(12, 0x3, 0, 0)
+#define MPP12_SDIO1_CD          MPP(12, 0x4, 0, 0)
+
+#define MPP13_GPIO13            MPP(13, 0x0, 1, 1)
+#define MPP13_UA2_CTSn          MPP(13, 0x2, 0, 0)
+#define MPP13_AD1_I2S_EXT_MCLK  MPP(13, 0x3, 0, 0)
+#define MPP13_SDIO1WP           MPP(13, 0x4, 0, 0)
+#define MPP13_SSP_EXTCLK        MPP(13, 0x5, 0, 0)
+
+#define MPP14_GPIO14            MPP(14, 0x0, 1, 1)
+#define MPP14_UA2_TXD           MPP(14, 0x2, 0, 0)
+#define MPP14_SDIO1_BUS_POWER   MPP(14, 0x4, 0, 0)
+#define MPP14_SSP_RXD           MPP(14, 0x5, 0, 0)
+
+#define MPP15_GPIO15            MPP(15, 0x0, 1, 1)
+#define MPP15_UA2_RXD           MPP(15, 0x2, 0, 0)
+#define MPP15_SDIO1_LED_CTRL    MPP(15, 0x4, 0, 0)
+#define MPP15_SSP_SFRM          MPP(15, 0x5, 0, 0)
+
+#define MPP16_GPIO16            MPP(16, 0x0, 1, 1)
+#define MPP16_UA3_RTSn          MPP(16, 0x2, 0, 0)
+#define MPP16_SDIO0_CD          MPP(16, 0x3, 0, 0)
+#define MPP16_SPI_LCD_CS1       MPP(16, 0x4, 0, 0)
+#define MPP16_AC97_SDATA_IN1    MPP(16, 0x5, 0, 0)
+
+#define MPP17_GPIO17            MPP(17, 0x0, 1, 1)
+#define MPP17_AC97_SYSCLK_OUT   MPP(17, 0x1, 0, 0)
+#define MPP17_UA3_CTSn          MPP(17, 0x2, 0, 0)
+#define MPP17_SDIO0_WP          MPP(17, 0x3, 0, 0)
+#define MPP17_TW_SDA2           MPP(17, 0x4, 0, 0)
+#define MPP17_AC97_SDATA_IN2    MPP(17, 0x5, 0, 0)
+
+#define MPP18_GPIO18            MPP(18, 0x0, 1, 1)
+#define MPP18_UA3_TXD           MPP(18, 0x2, 0, 0)
+#define MPP18_SDIO0_BUS_POWER   MPP(18, 0x3, 0, 0)
+#define MPP18_LCD0_PWM          MPP(18, 0x4, 0, 0)
+#define MPP18_AC_SDATA_IN3      MPP(18, 0x5, 0, 0)
+
+#define MPP19_GPIO19            MPP(19, 0x0, 1, 1)
+#define MPP19_UA3_RXD           MPP(19, 0x2, 0, 0)
+#define MPP19_SDIO0_LED_CTRL    MPP(19, 0x3, 0, 0)
+#define MPP19_TW_SCK2           MPP(19, 0x4, 0, 0)
+
+#define MPP20_GPIO20            MPP(20, 0x0, 1, 1)
+#define MPP20_AC97_SYSCLK_OUT   MPP(20, 0x1, 0, 0)
+#define MPP20_SPI_LCD_MISO      MPP(20, 0x2, 0, 0)
+#define MPP20_SDIO1_CD          MPP(20, 0x3, 0, 0)
+#define MPP20_SDIO0_CD          MPP(20, 0x5, 0, 0)
+#define MPP20_SPI_1_MISO        MPP(20, 0x6, 0, 0)
+
+#define MPP21_GPIO21            MPP(21, 0x0, 1, 1)
+#define MPP21_UA1_RTSn          MPP(21, 0x1, 0, 0)
+#define MPP21_SPI_LCD_CS0       MPP(21, 0x2, 0, 0)
+#define MPP21_SDIO1_WP          MPP(21, 0x3, 0, 0)
+#define MPP21_SSP_SFRM          MPP(21, 0x4, 0, 0)
+#define MPP21_SDIO0_WP          MPP(21, 0x5, 0, 0)
+#define MPP21_SPI_1_CS          MPP(21, 0x6, 0, 0)
+
+#define MPP22_GPIO22            MPP(22, 0x0, 1, 1)
+#define MPP22_UA1_CTSn          MPP(22, 0x1, 0, 0)
+#define MPP22_SPI_LCD_MOSI      MPP(22, 0x2, 0, 0)
+#define MPP22_SDIO1_BUS_POWER   MPP(22, 0x3, 0, 0)
+#define MPP22_SSP_TXD           MPP(22, 0x4, 0, 0)
+#define MPP22_SDIO0_BUS_POWER   MPP(22, 0x5, 0, 0)
+#define MPP22_SPI_1_MOSI        MPP(22, 0x6, 0, 0)
+
+#define MPP23_GPIO23            MPP(23, 0x0, 1, 1)
+#define MPP23_SPI_LCD_SCK       MPP(23, 0x2, 0, 0)
+#define MPP23_SDIO1_LED_CTRL    MPP(23, 0x3, 0, 0)
+#define MPP23_SSP_SCLK          MPP(23, 0x4, 0, 0)
+#define MPP23_SDIO0_LED_CTRL    MPP(23, 0x5, 0, 0)
+#define MPP23_SPI_1_SCK         MPP(23, 0x6, 0, 0)
+
+#define MPP_MAX                 23
+
+#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 0)
 
 /* for MPP groups _num is a group index */
 enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
         MPP_46_51 = 1,
         MPP_58_61 = 5,
         MPP_62_63 = 4,
+        MPP_GRP_MAX = 5,
 };
 
-#define MPP24_39_GPIO           MPP_GRP(MPP_24_39, 0x1)
-#define MPP24_39_CAM            MPP_GRP(MPP_24_39, 0x0)
+#define MPP_GRP_24_39_GPIO              MPP_GRP(MPP_24_39, 0x1)
+#define MPP_GRP_24_39_CAM               MPP_GRP(MPP_24_39, 0x0)
 
-#define MPP40_45_GPIO           MPP_GRP(MPP_40_45, 0x1)
-#define MPP40_45_SD0            MPP_GRP(MPP_40_45, 0x0)
+#define MPP_GRP_40_45_GPIO              MPP_GRP(MPP_40_45, 0x1)
+#define MPP_GRP_40_45_SD0               MPP_GRP(MPP_40_45, 0x0)
 
-#define MPP46_51_GPIO           MPP_GRP(MPP_46_51, 0x1)
-#define MPP46_51_SD1            MPP_GRP(MPP_46_51, 0x0)
+#define MPP_GRP_46_51_GPIO              MPP_GRP(MPP_46_51, 0x1)
+#define MPP_GRP_46_51_SD1               MPP_GRP(MPP_46_51, 0x0)
 
-#define MPP58_61_GPIO           MPP_GRP(MPP_58_61, 0x1)
-#define MPP58_61_SPI            MPP_GRP(MPP_58_61, 0x0)
+#define MPP_GRP_58_61_GPIO              MPP_GRP(MPP_58_61, 0x1)
+#define MPP_GRP_58_61_SPI               MPP_GRP(MPP_58_61, 0x0)
 
-#define MPP62_63_GPIO           MPP_GRP(MPP_62_63, 0x1)
-#define MPP62_63_UA1            MPP_GRP(MPP_62_63, 0x0)
+#define MPP_GRP_62_63_GPIO              MPP_GRP(MPP_62_63, 0x1)
+#define MPP_GRP_62_63_UA1               MPP_GRP(MPP_62_63, 0x0)
 
 /* The MPP[64:71] control differs from other groups */
-#define MPP64_71_GPO            MPP_GRP_NFC(0x1)
-#define MPP64_71_NFC            MPP_GRP_NFC(0x0)
+#define MPP_GRP_NFC_64_71_GPO           0x1
+#define MPP_GRP_NFC_64_71_NFC           0x0
 
 /*
  * The MPP[52:57] functionality is encoded by 4 bits in different
  * registers. The _num field in this case encodes those bits in
  * correspodence with Table 135 of 88AP510 Functional specification
  */
-#define MPP52_57_AU1            MPP_GRP_AU1(0x0)
-#define MPP52_57_AU1_GPIO57     MPP_GRP_AU1(0x2)
-#define MPP52_57_GPIO           MPP_GRP_AU1(0xa)
-#define MPP52_57_TW_GPIO        MPP_GRP_AU1(0xb)
-#define MPP52_57_AU1_SSP        MPP_GRP_AU1(0xc)
-#define MPP52_57_SSP_GPIO       MPP_GRP_AU1(0xe)
-#define MPP52_57_SSP_TW         MPP_GRP_AU1(0xf)
-
-void dove_mpp_conf(unsigned int *mpp_list);
+#define MPP_GRP_AU1_52_57_AU1           0x0
+#define MPP_GRP_AU1_52_57_AU1_GPIO57    0x2
+#define MPP_GRP_AU1_52_57_GPIO          0xa
+#define MPP_GRP_AU1_52_57_TW_GPIO       0xb
+#define MPP_GRP_AU1_52_57_AU1_SSP       0xc
+#define MPP_GRP_AU1_52_57_SSP_GPIO      0xe
+#define MPP_GRP_AU1_52_57_SSP_TW        0xf
+
+void dove_mpp_conf(unsigned int *mpp_list,
+                   unsigned int *mpp_grp_list,
+                   unsigned int grp_au1_52_57,
+                   unsigned int grp_nfc_64_71);
 
 #endif  /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 180b8a9d0d2..a5a9ff70b19 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -101,7 +101,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         /*
-         * map discontiguous hw irq range to continous sw irq range:
+         * map discontiguous hw irq range to continuous sw irq range:
          *
          *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
          */
diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h
index 939728b38d4..be9266b10fd 100644
--- a/arch/arm/mach-exynos4/include/mach/gpio.h
+++ b/arch/arm/mach-exynos4/include/mach/gpio.h
@@ -18,7 +18,7 @@
 #define gpio_cansleep   __gpio_cansleep
 #define gpio_to_irq     __gpio_to_irq
 
-/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
+/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
 
 /* GPIO bank sizes */
 #define EXYNOS4_GPIO_A0_NR      (8)
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index f488b66d680..5a2758ab055 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -59,8 +59,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         unsigned int cascade_irq, combiner_irq;
         unsigned long status;
 
-        /* primary controller ack'ing */
-        chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         spin_lock(&irq_controller_lock);
         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(cascade_irq);
 
  out:
-        /* primary controller unmasking */
-        chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(chip, desc);
 }
 
 static struct irq_chip combiner_chip = {
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index af82a8fbb68..14ac10b7ec0 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -276,7 +276,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
         /* update interrupt count buffer */
         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
 
-        /* enable MCT tick interupt */
+        /* enable MCT tick interrupt */
         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 
         tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
index 1b3d3a2de95..e8d08bf8965 100644
--- a/arch/arm/mach-exynos4/setup-sdhci-gpio.c
+++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
@@ -38,14 +38,14 @@ void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
         switch (width) {
         case 8:
                 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                        /* Data pin GPK1[3:6] to special-funtion 3 */
+                        /* Data pin GPK1[3:6] to special-function 3 */
                         s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
                         s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
                         s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
                 }
         case 4:
                 for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
-                        /* Data pin GPK0[3:6] to special-funtion 2 */
+                        /* Data pin GPK0[3:6] to special-function 2 */
                         s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
                         s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
                         s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
index 85f9433d483..1e83f8cf236 100644
--- a/arch/arm/mach-exynos4/setup-sdhci.c
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -35,7 +35,7 @@ void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
 {
         u32 ctrl2, ctrl3;
 
-        /* don't need to alter anything acording to card-type */
+        /* don't need to alter anything according to card-type */
 
         ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
 
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
index 5483f61a806..0efa2624723 100644
--- a/arch/arm/mach-gemini/include/mach/uncompress.h
+++ b/arch/arm/mach-gemini/include/mach/uncompress.h
@@ -16,7 +16,7 @@
 #include <linux/serial_reg.h>
 #include <mach/hardware.h>
 
-static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE;
+static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE;
 
 /*
  * The following code assumes the serial port has already been
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 773ea0c95b9..ba3dae352a2 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -225,7 +225,7 @@ static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
 /* This routine checks the status of the last configuration cycle.  If an error
  * was detected it returns >0, else it returns a 0.  The errors being checked
  * are parity, master abort, target abort (master and target).  These types of
- * errors occure during a config cycle where there is no device, like during
+ * errors occur during a config cycle where there is no device, like during
  * the discovery stage.
  */
 static int iop13xx_atux_pci_status(int clear)
@@ -332,7 +332,7 @@ static struct pci_ops iop13xx_atux_ops = {
 /* This routine checks the status of the last configuration cycle.  If an error
  * was detected it returns >0, else it returns a 0.  The errors being checked
  * are parity, master abort, target abort (master and target).  These types of
- * errors occure during a config cycle where there is no device, like during
+ * errors occur during a config cycle where there is no device, like during
  * the discovery stage.
  */
 static int iop13xx_atue_pci_status(int clear)
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
index b247551b6f5..4fd715496f4 100644
--- a/arch/arm/mach-iop32x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
 #include <linux/serial_reg.h>
 #include <mach/hardware.h>
 
-static volatile u8 *uart_base;
+volatile u8 *uart_base;
 
 #define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
 
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
index b42423f6330..f99bb848c5a 100644
--- a/arch/arm/mach-iop33x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
 #include <linux/serial_reg.h>
 #include <mach/hardware.h>
 
-static volatile u32 *uart_base;
+volatile u32 *uart_base;
 
 #define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 2db0078a8cf..219d7c1dcdb 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -19,7 +19,7 @@
 
 #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
 
-static volatile u32* uart_base;
+volatile u32* uart_base;
 
 static inline void putc(int c)
 {
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 20e71df3e3b..f3248cfbe51 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -13,11 +13,9 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
-#include <linux/spi/orion_spi.h>
+#include <linux/dma-mapping.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -28,11 +26,9 @@
 #include <mach/bridge-regs.h>
 #include <plat/audio.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
 #include <plat/mvsdio.h>
-#include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
-#include <plat/orion_wdt.h>
+#include <plat/common.h>
 #include <plat/time.h>
 #include "common.h"
 
@@ -69,210 +65,52 @@ void __init kirkwood_map_io(void)
  * registered.  Some reserved bits must be set to 1.
  */
 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
-        
-
-/*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data kirkwood_ehci_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-        .phy_version    = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
 
 
 /*****************************************************************************
  * EHCI0
  ****************************************************************************/
-static struct resource kirkwood_ehci_resources[] = {
-        {
-                .start  = USB_PHYS_BASE,
-                .end    = USB_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_KIRKWOOD_USB,
-                .end    = IRQ_KIRKWOOD_USB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ehci = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &kirkwood_ehci_data,
-        },
-        .resource       = kirkwood_ehci_resources,
-        .num_resources  = ARRAY_SIZE(kirkwood_ehci_resources),
-};
-
 void __init kirkwood_ehci_init(void)
 {
         kirkwood_clk_ctrl |= CGC_USB0;
-        platform_device_register(&kirkwood_ehci);
+        orion_ehci_init(&kirkwood_mbus_dram_info,
+                        USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
 }
 
 
 /*****************************************************************************
  * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-};
-
-static struct resource kirkwood_ge00_shared_resources[] = {
-        {
-                .name   = "ge00 base",
-                .start  = GE00_PHYS_BASE + 0x2000,
-                .end    = GE00_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "ge00 err irq",
-                .start  = IRQ_KIRKWOOD_GE00_ERR,
-                .end    = IRQ_KIRKWOOD_GE00_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge00_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &kirkwood_ge00_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_ge00_shared_resources),
-        .resource       = kirkwood_ge00_shared_resources,
-};
-
-static struct resource kirkwood_ge00_resources[] = {
-        {
-                .name   = "ge00 irq",
-                .start  = IRQ_KIRKWOOD_GE00_SUM,
-                .end    = IRQ_KIRKWOOD_GE00_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge00 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = kirkwood_ge00_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
         kirkwood_clk_ctrl |= CGC_GE0;
-        eth_data->shared = &kirkwood_ge00_shared;
-        kirkwood_ge00.dev.platform_data = eth_data;
 
-        platform_device_register(&kirkwood_ge00_shared);
-        platform_device_register(&kirkwood_ge00);
+        orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
+                        GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
+                        IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * GE01
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-        .shared_smi     = &kirkwood_ge00_shared,
-};
-
-static struct resource kirkwood_ge01_shared_resources[] = {
-        {
-                .name   = "ge01 base",
-                .start  = GE01_PHYS_BASE + 0x2000,
-                .end    = GE01_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "ge01 err irq",
-                .start  = IRQ_KIRKWOOD_GE01_ERR,
-                .end    = IRQ_KIRKWOOD_GE01_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge01_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &kirkwood_ge01_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_ge01_shared_resources),
-        .resource       = kirkwood_ge01_shared_resources,
-};
-
-static struct resource kirkwood_ge01_resources[] = {
-        {
-                .name   = "ge01 irq",
-                .start  = IRQ_KIRKWOOD_GE01_SUM,
-                .end    = IRQ_KIRKWOOD_GE01_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge01 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = kirkwood_ge01_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
+
         kirkwood_clk_ctrl |= CGC_GE1;
-        eth_data->shared = &kirkwood_ge01_shared;
-        kirkwood_ge01.dev.platform_data = eth_data;
 
-        platform_device_register(&kirkwood_ge01_shared);
-        platform_device_register(&kirkwood_ge01);
+        orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
+                        GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
+                        IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * Ethernet switch
  ****************************************************************************/
-static struct resource kirkwood_switch_resources[] = {
-        {
-                .start  = 0,
-                .end    = 0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_switch_device = {
-        .name           = "dsa",
-        .id             = 0,
-        .num_resources  = 0,
-        .resource       = kirkwood_switch_resources,
-};
-
 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
 {
-        int i;
-
-        if (irq != NO_IRQ) {
-                kirkwood_switch_resources[0].start = irq;
-                kirkwood_switch_resources[0].end = irq;
-                kirkwood_switch_device.num_resources = 1;
-        }
-
-        d->netdev = &kirkwood_ge00.dev;
-        for (i = 0; i < d->nr_chips; i++)
-                d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
-        kirkwood_switch_device.dev.platform_data = d;
-
-        platform_device_register(&kirkwood_switch_device);
+        orion_ge00_switch_init(d, irq);
 }
 
 
@@ -325,53 +163,23 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static struct resource kirkwood_rtc_resource = {
-        .start  = RTC_PHYS_BASE,
-        .end    = RTC_PHYS_BASE + SZ_16 - 1,
-        .flags  = IORESOURCE_MEM,
-};
-
 static void __init kirkwood_rtc_init(void)
 {
-        platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
+        orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
 
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource kirkwood_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = SATA_PHYS_BASE,
-                .end    = SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_KIRKWOOD_SATA,
-                .end    = IRQ_KIRKWOOD_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_sata_resources),
-        .resource       = kirkwood_sata_resources,
-};
-
 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 {
         kirkwood_clk_ctrl |= CGC_SATA0;
         if (sata_data->n_ports > 1)
                 kirkwood_clk_ctrl |= CGC_SATA1;
-        sata_data->dram = &kirkwood_mbus_dram_info;
-        kirkwood_sata.dev.platform_data = sata_data;
-        platform_device_register(&kirkwood_sata);
+
+        orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
+                        SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
 }
 
 
@@ -391,14 +199,14 @@ static struct resource mvsdio_resources[] = {
         },
 };
 
-static u64 mvsdio_dmamask = 0xffffffffUL;
+static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device kirkwood_sdio = {
         .name           = "mvsdio",
         .id             = -1,
         .dev            = {
                 .dma_mask = &mvsdio_dmamask,
-                .coherent_dma_mask = 0xffffffff,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(mvsdio_resources),
         .resource       = mvsdio_resources,
@@ -423,424 +231,84 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 /*****************************************************************************
  * SPI
  ****************************************************************************/
-static struct orion_spi_info kirkwood_spi_plat_data = {
-};
-
-static struct resource kirkwood_spi_resources[] = {
-        {
-                .start  = SPI_PHYS_BASE,
-                .end    = SPI_PHYS_BASE + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_spi = {
-        .name           = "orion_spi",
-        .id             = 0,
-        .resource       = kirkwood_spi_resources,
-        .dev            = {
-                .platform_data  = &kirkwood_spi_plat_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_spi_resources),
-};
-
 void __init kirkwood_spi_init()
 {
         kirkwood_clk_ctrl |= CGC_RUNIT;
-        platform_device_register(&kirkwood_spi);
+        orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * I2C
  ****************************************************************************/
-static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource kirkwood_i2c_resources[] = {
-        {
-                .start  = I2C_PHYS_BASE,
-                .end    = I2C_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_KIRKWOOD_TWSI,
-                .end    = IRQ_KIRKWOOD_TWSI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_i2c = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(kirkwood_i2c_resources),
-        .resource       = kirkwood_i2c_resources,
-        .dev            = {
-                .platform_data  = &kirkwood_i2c_pdata,
-        },
-};
-
 void __init kirkwood_i2c_init(void)
 {
-        platform_device_register(&kirkwood_i2c);
+        orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
 }
 
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port kirkwood_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_KIRKWOOD_UART_0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource kirkwood_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_KIRKWOOD_UART_0,
-                .end            = IRQ_KIRKWOOD_UART_0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = kirkwood_uart0_data,
-        },
-        .resource               = kirkwood_uart0_resources,
-        .num_resources          = ARRAY_SIZE(kirkwood_uart0_resources),
-};
 
 void __init kirkwood_uart0_init(void)
 {
-        platform_device_register(&kirkwood_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port kirkwood_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_KIRKWOOD_UART_1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource kirkwood_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_KIRKWOOD_UART_1,
-                .end            = IRQ_KIRKWOOD_UART_1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = kirkwood_uart1_data,
-        },
-        .resource               = kirkwood_uart1_resources,
-        .num_resources          = ARRAY_SIZE(kirkwood_uart1_resources),
-};
-
 void __init kirkwood_uart1_init(void)
 {
-        platform_device_register(&kirkwood_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
 }
 
-
 /*****************************************************************************
  * Cryptographic Engines and Security Accelerator (CESA)
  ****************************************************************************/
-
-static struct resource kirkwood_crypto_res[] = {
-        {
-                .name   = "regs",
-                .start  = CRYPTO_PHYS_BASE,
-                .end    = CRYPTO_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sram",
-                .start  = KIRKWOOD_SRAM_PHYS_BASE,
-                .end    = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "crypto interrupt",
-                .start  = IRQ_KIRKWOOD_CRYPTO,
-                .end    = IRQ_KIRKWOOD_CRYPTO,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_crypto_device = {
-        .name           = "mv_crypto",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(kirkwood_crypto_res),
-        .resource       = kirkwood_crypto_res,
-};
-
 void __init kirkwood_crypto_init(void)
 {
         kirkwood_clk_ctrl |= CGC_CRYPTO;
-        platform_device_register(&kirkwood_crypto_device);
+        orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
+                          KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
 }
 
 
 /*****************************************************************************
- * XOR
- ****************************************************************************/
-static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-};
-
-static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
-
-
-/*****************************************************************************
  * XOR0
  ****************************************************************************/
-static struct resource kirkwood_xor0_shared_resources[] = {
-        {
-                .name   = "xor 0 low",
-                .start  = XOR0_PHYS_BASE,
-                .end    = XOR0_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 0 high",
-                .start  = XOR0_HIGH_PHYS_BASE,
-                .end    = XOR0_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_xor0_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data = &kirkwood_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_xor0_shared_resources),
-        .resource       = kirkwood_xor0_shared_resources,
-};
-
-static struct resource kirkwood_xor00_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_00,
-                .end    = IRQ_KIRKWOOD_XOR_00,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor00_data = {
-        .shared         = &kirkwood_xor0_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor00_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor00_resources),
-        .resource       = kirkwood_xor00_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor00_data,
-        },
-};
-
-static struct resource kirkwood_xor01_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_01,
-                .end    = IRQ_KIRKWOOD_XOR_01,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor01_data = {
-        .shared         = &kirkwood_xor0_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor01_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor01_resources),
-        .resource       = kirkwood_xor01_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor01_data,
-        },
-};
-
 static void __init kirkwood_xor0_init(void)
 {
         kirkwood_clk_ctrl |= CGC_XOR0;
-        platform_device_register(&kirkwood_xor0_shared);
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
-        platform_device_register(&kirkwood_xor00_channel);
-
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
-        platform_device_register(&kirkwood_xor01_channel);
+        orion_xor0_init(&kirkwood_mbus_dram_info,
+                        XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
+                        IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
 }
 
 
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static struct resource kirkwood_xor1_shared_resources[] = {
-        {
-                .name   = "xor 1 low",
-                .start  = XOR1_PHYS_BASE,
-                .end    = XOR1_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 1 high",
-                .start  = XOR1_HIGH_PHYS_BASE,
-                .end    = XOR1_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_xor1_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data = &kirkwood_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_xor1_shared_resources),
-        .resource       = kirkwood_xor1_shared_resources,
-};
-
-static struct resource kirkwood_xor10_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_10,
-                .end    = IRQ_KIRKWOOD_XOR_10,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor10_data = {
-        .shared         = &kirkwood_xor1_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor10_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor10_resources),
-        .resource       = kirkwood_xor10_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor10_data,
-        },
-};
-
-static struct resource kirkwood_xor11_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_11,
-                .end    = IRQ_KIRKWOOD_XOR_11,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor11_data = {
-        .shared         = &kirkwood_xor1_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor11_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor11_resources),
-        .resource       = kirkwood_xor11_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor11_data,
-        },
-};
-
 static void __init kirkwood_xor1_init(void)
 {
         kirkwood_clk_ctrl |= CGC_XOR1;
-        platform_device_register(&kirkwood_xor1_shared);
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
-        platform_device_register(&kirkwood_xor10_channel);
-
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
-        platform_device_register(&kirkwood_xor11_channel);
+        orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
+                        IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
 }
 
 
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static struct orion_wdt_platform_data kirkwood_wdt_data = {
-        .tclk           = 0,
-};
-
-static struct platform_device kirkwood_wdt_device = {
-        .name           = "orion_wdt",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &kirkwood_wdt_data,
-        },
-        .num_resources  = 0,
-};
-
 static void __init kirkwood_wdt_init(void)
 {
-        kirkwood_wdt_data.tclk = kirkwood_tclk;
-        platform_device_register(&kirkwood_wdt_device);
+        orion_wdt_init(kirkwood_tclk);
 }
 
 
@@ -984,11 +452,6 @@ void __init kirkwood_init(void)
 {
         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
                 kirkwood_id(), kirkwood_tclk);
-        kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
-        kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
-        kirkwood_spi_plat_data.tclk = kirkwood_tclk;
-        kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
-        kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
         kirkwood_i2s_data.tclk = kirkwood_tclk;
 
         /*
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 9da2eb59180..2bf8161e3b5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -51,6 +51,7 @@
 #define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
 #define IRQ_KIRKWOOD_GE00_ERR   46
 #define IRQ_KIRKWOOD_GE01_ERR   47
+#define IRQ_KIRKWOOD_RTC        53
 
 /*
  * KIRKWOOD General Purpose Pins
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 7ce20184806..b0a7d979a8e 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <asm/gpio.h>
 #include <mach/hardware.h>
+#include <plat/mpp.h>
 #include "common.h"
 #include "mpp.h"
 
@@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void)
         return 0;
 }
 
-#define MPP_CTRL(i)     (DEV_BUS_VIRT_BASE + (i) * 4)
-#define MPP_NR_REGS     (1 + MPP_MAX/8)
-
 void __init kirkwood_mpp_conf(unsigned int *mpp_list)
 {
-        u32 mpp_ctrl[MPP_NR_REGS];
-        unsigned int variant_mask;
-        int i;
-
-        variant_mask = kirkwood_variant();
-        if (!variant_mask)
-                return;
-
-        printk(KERN_DEBUG "initial MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                mpp_ctrl[i] = readl(MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
-
-        for ( ; *mpp_list; mpp_list++) {
-                unsigned int num = MPP_NUM(*mpp_list);
-                unsigned int sel = MPP_SEL(*mpp_list);
-                int shift, gpio_mode;
-
-                if (num > MPP_MAX) {
-                        printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
-                                        "number (%u)\n", num);
-                        continue;
-                }
-                if (!(*mpp_list & variant_mask)) {
-                        printk(KERN_WARNING
-                               "kirkwood_mpp_conf: requested MPP%u config "
-                               "unavailable on this hardware\n", num);
-                        continue;
-                }
-
-                shift = (num & 7) << 2;
-                mpp_ctrl[num / 8] &= ~(0xf << shift);
-                mpp_ctrl[num / 8] |= sel << shift;
-
-                gpio_mode = 0;
-                if (*mpp_list & MPP_INPUT_MASK)
-                        gpio_mode |= GPIO_INPUT_OK;
-                if (*mpp_list & MPP_OUTPUT_MASK)
-                        gpio_mode |= GPIO_OUTPUT_OK;
-                if (sel != 0)
-                        gpio_mode = 0;
-                orion_gpio_set_valid(num, gpio_mode);
-        }
-
-        printk(KERN_DEBUG "  final MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                writel(mpp_ctrl[i], MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
+        orion_mpp_conf(mpp_list, kirkwood_variant(),
+                       MPP_MAX, DEV_BUS_VIRT_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index 9b0a94d85c3..ac787957e2d 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -22,14 +22,8 @@
         /* available on F6281 */        ((!!(_F6281)) << 17) | \
         /* available on F6282 */        ((!!(_F6282)) << 18))
 
-#define MPP_NUM(x)      ((x) & 0xff)
-#define MPP_SEL(x)      (((x) >> 8) & 0xf)
-
                                 /*   num sel  i  o  6180 6190 6192 6281 6282 */
 
-#define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
-#define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
-
 #define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
 #define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
 #define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
index f781164e623..24294b2bc46 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.c
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -15,7 +15,7 @@
 
 /****************************************************************************
  * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
- *     partitions on the device because we want to keep compatability with
+ *     partitions on the device because we want to keep compatibility with
  *     the QNAP firmware.
  * Layout as used by QNAP:
  *  0x00000000-0x00080000 : "U-Boot"
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index e41e909cf8f..5f02664db81 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/dma-mapping.h>
 #include <asm/page.h>
 #include <asm/timex.h>
 #include <asm/mach/map.h>
@@ -22,6 +22,7 @@
 #include <mach/loki.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -43,116 +44,28 @@ void __init loki_map_io(void)
 
 
 /*****************************************************************************
- * GE0
+ * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
-        .t_clk          = LOKI_TCLK,
-        .dram           = &loki_mbus_dram_info,
-};
-
-static struct resource loki_ge0_shared_resources[] = {
-        {
-                .name   = "ge0 base",
-                .start  = GE0_PHYS_BASE + 0x2000,
-                .end    = GE0_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device loki_ge0_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &loki_ge0_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = loki_ge0_shared_resources,
-};
-
-static struct resource loki_ge0_resources[] = {
-        {
-                .name   = "ge0 irq",
-                .start  = IRQ_LOKI_GBE_A_INT,
-                .end    = IRQ_LOKI_GBE_A_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_ge0 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = loki_ge0_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &loki_ge0_shared;
-        loki_ge0.dev.platform_data = eth_data;
-
         writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
-        platform_device_register(&loki_ge0_shared);
-        platform_device_register(&loki_ge0);
+
+        orion_ge00_init(eth_data, &loki_mbus_dram_info,
+                        GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
+                        0, LOKI_TCLK);
 }
 
 
 /*****************************************************************************
- * GE1
+ * GE01
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
-        .t_clk          = LOKI_TCLK,
-        .dram           = &loki_mbus_dram_info,
-};
-
-static struct resource loki_ge1_shared_resources[] = {
-        {
-                .name   = "ge1 base",
-                .start  = GE1_PHYS_BASE + 0x2000,
-                .end    = GE1_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device loki_ge1_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &loki_ge1_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = loki_ge1_shared_resources,
-};
-
-static struct resource loki_ge1_resources[] = {
-        {
-                .name   = "ge1 irq",
-                .start  = IRQ_LOKI_GBE_B_INT,
-                .end    = IRQ_LOKI_GBE_B_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_ge1 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = loki_ge1_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &loki_ge1_shared;
-        loki_ge1.dev.platform_data = eth_data;
-
         writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
-        platform_device_register(&loki_ge1_shared);
-        platform_device_register(&loki_ge1);
+
+        orion_ge01_init(eth_data, &loki_mbus_dram_info,
+                        GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
+                        0, LOKI_TCLK);
 }
 
 
@@ -187,7 +100,7 @@ static struct platform_device loki_sas = {
         .name           = "mvsas",
         .id             = 0,
         .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(loki_sas_resources),
         .resource       = loki_sas_resources,
@@ -203,88 +116,19 @@ void __init loki_sas_init(void)
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port loki_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_LOKI_UART0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = LOKI_TCLK,
-        }, {
-        },
-};
-
-static struct resource loki_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_LOKI_UART0,
-                .end            = IRQ_LOKI_UART0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = loki_uart0_data,
-        },
-        .resource               = loki_uart0_resources,
-        .num_resources          = ARRAY_SIZE(loki_uart0_resources),
-};
-
 void __init loki_uart0_init(void)
 {
-        platform_device_register(&loki_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_LOKI_UART0, LOKI_TCLK);
 }
 
-
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port loki_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_LOKI_UART1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = LOKI_TCLK,
-        }, {
-        },
-};
-
-static struct resource loki_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_LOKI_UART1,
-                .end            = IRQ_LOKI_UART1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = loki_uart1_data,
-        },
-        .resource               = loki_uart1_resources,
-        .num_resources          = ARRAY_SIZE(loki_uart1_resources),
-};
-
 void __init loki_uart1_init(void)
 {
-        platform_device_register(&loki_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_LOKI_UART1, LOKI_TCLK);
 }
 
 
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index e76d41bb705..b9c80597b7b 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -41,7 +41,7 @@
  * DRAM clocking and refresh are slightly different for systems with DDR
  * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
  * SDRAM will still be accessible in direct-run mode. In DDR based systems,
- * a transistion to direct-run mode will stop all DDR accesses (no clocks).
+ * a transition to direct-run mode will stop all DDR accesses (no clocks).
  * Because of this, the code to switch power modes and the code to enter
  * and exit DRAM self-refresh modes must not be executed in DRAM. A small
  * section of IRAM is used instead for this.
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
index ee8b02ed801..7bfb827f3fe 100644
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -10,7 +10,7 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPIO_REG(x)     (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
 
-#define NR_BUILTIN_GPIO (192)
+#define NR_BUILTIN_GPIO         IRQ_GPIO_NUM
 
 #define gpio_to_bank(gpio)      ((gpio) >> 5)
 #define gpio_to_irq(gpio)       (IRQ_GPIO_START + (gpio))
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index 4621067c772..713be155a44 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -8,6 +8,15 @@
 #define MFP_DRIVE_MEDIUM        (0x2 << 13)
 #define MFP_DRIVE_FAST          (0x3 << 13)
 
+#undef MFP_CFG
+#undef MFP_CFG_DRV
+
+#define MFP_CFG(pin, af)                \
+        (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
+
+#define MFP_CFG_DRV(pin, af, drv)       \
+        (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
+
 /* GPIO */
 #define GPIO0_GPIO              MFP_CFG(GPIO0, AF5)
 #define GPIO1_GPIO              MFP_CFG(GPIO1, AF5)
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index 85bd8a2d84b..d6daeb7e4ef 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -14,7 +14,7 @@
 #define UART2_BASE      (APB_PHYS_BASE + 0x17000)
 #define UART3_BASE      (APB_PHYS_BASE + 0x18000)
 
-static volatile unsigned long *UART;
+volatile unsigned long *UART;
 
 static inline void putc(char c)
 {
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index aeb9ae23e6c..99833b9485c 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -9,7 +9,7 @@
  *   2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
  *   2008-10-08: Bin Yang <bin.yang@marvell.com>
  *
- * The timers module actually includes three timers, each timer with upto
+ * The timers module actually includes three timers, each timer with up to
  * three match comparators. Timer #0 is used here in free-running mode as
  * the clock source, and match comparator #1 used as clock event device.
  *
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
index 7ffbd987eb5..805d4ee53f7 100644
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ b/arch/arm/mach-msm/acpuclock-arm11.c
@@ -343,7 +343,7 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
                 }
         }
 
-        /* Set wait states for CPU inbetween frequency changes */
+        /* Set wait states for CPU between frequency changes */
         reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
         reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
         writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 7f568611547..6a96911b0ad 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -160,10 +160,7 @@ static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
 
 static void __init qsd8x50_init_mmc(void)
 {
-        if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa())
-                vreg_mmc = vreg_get(NULL, "gp6");
-        else
-                vreg_mmc = vreg_get(NULL, "gp5");
+        vreg_mmc = vreg_get(NULL, "gp5");
 
         if (IS_ERR(vreg_mmc)) {
                 pr_err("vreg get for vreg_mmc failed (%ld)\n",
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 56a964e52ad..cc9c4fd7ccc 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -27,6 +27,9 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
+
+#include <asm/mach/irq.h>
+
 #include <mach/msm_iomap.h>
 #include "gpiomux.h"
 
@@ -309,8 +312,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
  */
 static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_data *data = irq_desc_get_irq_data(desc);
         unsigned long i;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+
+        chained_irq_enter(chip, desc);
 
         for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
              i < NR_GPIO_IRQS;
@@ -319,7 +324,8 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
                         generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
                                                            i));
         }
-        data->chip->irq_ack(data);
+
+        chained_irq_exit(chip, desc);
 }
 
 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
index cfa808dd489..232f97a0450 100644
--- a/arch/arm/mach-msm/scm.c
+++ b/arch/arm/mach-msm/scm.c
@@ -46,7 +46,7 @@ static DEFINE_MUTEX(scm_lock);
  * @id: command to be executed
  * @buf: buffer returned from scm_get_command_buffer()
  *
- * An SCM command is layed out in memory as follows:
+ * An SCM command is laid out in memory as follows:
  *
  *      ------------------- <--- struct scm_command
  *      | command header  |
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 56f920c55b6..38b95e949d1 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -269,7 +269,7 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
 
         /* Use existing clock_event for cpu 0 */
         if (!smp_processor_id())
-                return;
+                return 0;
 
         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 44fb4e55be0..23d3980ef59 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -13,8 +13,6 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/ethtool.h>
 #include <asm/mach/map.h>
@@ -22,11 +20,12 @@
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
+static int get_tclk(void);
 
 /*****************************************************************************
  * Common bits
@@ -168,285 +167,62 @@ void __init mv78xx0_map_io(void)
 /*****************************************************************************
  * EHCI
  ****************************************************************************/
-static struct orion_ehci_data mv78xx0_ehci_data = {
-        .dram           = &mv78xx0_mbus_dram_info,
-        .phy_version    = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
-
-/*****************************************************************************
- * EHCI0
- ****************************************************************************/
-static struct resource mv78xx0_ehci0_resources[] = {
-        {
-                .start  = USB0_PHYS_BASE,
-                .end    = USB0_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_USB_0,
-                .end    = IRQ_MV78XX0_USB_0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ehci0 = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &mv78xx0_ehci_data,
-        },
-        .resource       = mv78xx0_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(mv78xx0_ehci0_resources),
-};
-
 void __init mv78xx0_ehci0_init(void)
 {
-        platform_device_register(&mv78xx0_ehci0);
+        orion_ehci_init(&mv78xx0_mbus_dram_info,
+                        USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
 }
 
 
 /*****************************************************************************
  * EHCI1
  ****************************************************************************/
-static struct resource mv78xx0_ehci1_resources[] = {
-        {
-                .start  = USB1_PHYS_BASE,
-                .end    = USB1_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_USB_1,
-                .end    = IRQ_MV78XX0_USB_1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ehci1 = {
-        .name           = "orion-ehci",
-        .id             = 1,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &mv78xx0_ehci_data,
-        },
-        .resource       = mv78xx0_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(mv78xx0_ehci1_resources),
-};
-
 void __init mv78xx0_ehci1_init(void)
 {
-        platform_device_register(&mv78xx0_ehci1);
+        orion_ehci_1_init(&mv78xx0_mbus_dram_info,
+                          USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 }
 
 
 /*****************************************************************************
  * EHCI2
  ****************************************************************************/
-static struct resource mv78xx0_ehci2_resources[] = {
-        {
-                .start  = USB2_PHYS_BASE,
-                .end    = USB2_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_USB_2,
-                .end    = IRQ_MV78XX0_USB_2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ehci2 = {
-        .name           = "orion-ehci",
-        .id             = 2,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &mv78xx0_ehci_data,
-        },
-        .resource       = mv78xx0_ehci2_resources,
-        .num_resources  = ARRAY_SIZE(mv78xx0_ehci2_resources),
-};
-
 void __init mv78xx0_ehci2_init(void)
 {
-        platform_device_register(&mv78xx0_ehci2);
+        orion_ehci_2_init(&mv78xx0_mbus_dram_info,
+                          USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 }
 
 
 /*****************************************************************************
  * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-};
-
-static struct resource mv78xx0_ge00_shared_resources[] = {
-        {
-                .name   = "ge00 base",
-                .start  = GE00_PHYS_BASE + 0x2000,
-                .end    = GE00_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "ge err irq",
-                .start  = IRQ_MV78XX0_GE_ERR,
-                .end    = IRQ_MV78XX0_GE_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge00_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge00_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
-        .resource       = mv78xx0_ge00_shared_resources,
-};
-
-static struct resource mv78xx0_ge00_resources[] = {
-        {
-                .name   = "ge00 irq",
-                .start  = IRQ_MV78XX0_GE00_SUM,
-                .end    = IRQ_MV78XX0_GE00_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge00 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge00_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &mv78xx0_ge00_shared;
-        mv78xx0_ge00.dev.platform_data = eth_data;
-
-        platform_device_register(&mv78xx0_ge00_shared);
-        platform_device_register(&mv78xx0_ge00);
+        orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
+                        IRQ_MV78XX0_GE_ERR, get_tclk());
 }
 
 
 /*****************************************************************************
  * GE01
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-        .shared_smi     = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge01_shared_resources[] = {
-        {
-                .name   = "ge01 base",
-                .start  = GE01_PHYS_BASE + 0x2000,
-                .end    = GE01_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device mv78xx0_ge01_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge01_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge01_shared_resources,
-};
-
-static struct resource mv78xx0_ge01_resources[] = {
-        {
-                .name   = "ge01 irq",
-                .start  = IRQ_MV78XX0_GE01_SUM,
-                .end    = IRQ_MV78XX0_GE01_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge01 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge01_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &mv78xx0_ge01_shared;
-        mv78xx0_ge01.dev.platform_data = eth_data;
-
-        platform_device_register(&mv78xx0_ge01_shared);
-        platform_device_register(&mv78xx0_ge01);
+        orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
+                        NO_IRQ, get_tclk());
 }
 
 
 /*****************************************************************************
  * GE10
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-        .shared_smi     = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge10_shared_resources[] = {
-        {
-                .name   = "ge10 base",
-                .start  = GE10_PHYS_BASE + 0x2000,
-                .end    = GE10_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device mv78xx0_ge10_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge10_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge10_shared_resources,
-};
-
-static struct resource mv78xx0_ge10_resources[] = {
-        {
-                .name   = "ge10 irq",
-                .start  = IRQ_MV78XX0_GE10_SUM,
-                .end    = IRQ_MV78XX0_GE10_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge10 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 2,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge10_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 {
         u32 dev, rev;
 
-        eth_data->shared = &mv78xx0_ge10_shared;
-        mv78xx0_ge10.dev.platform_data = eth_data;
-
         /*
          * On the Z0, ge10 and ge11 are internally connected back
          * to back, and not brought out.
@@ -458,65 +234,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        platform_device_register(&mv78xx0_ge10_shared);
-        platform_device_register(&mv78xx0_ge10);
+        orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
+                        NO_IRQ, get_tclk());
 }
 
 
 /*****************************************************************************
  * GE11
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-        .shared_smi     = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge11_shared_resources[] = {
-        {
-                .name   = "ge11 base",
-                .start  = GE11_PHYS_BASE + 0x2000,
-                .end    = GE11_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device mv78xx0_ge11_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge11_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge11_shared_resources,
-};
-
-static struct resource mv78xx0_ge11_resources[] = {
-        {
-                .name   = "ge11 irq",
-                .start  = IRQ_MV78XX0_GE11_SUM,
-                .end    = IRQ_MV78XX0_GE11_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge11 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 3,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge11_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 {
         u32 dev, rev;
 
-        eth_data->shared = &mv78xx0_ge11_shared;
-        mv78xx0_ge11.dev.platform_data = eth_data;
-
         /*
          * On the Z0, ge10 and ge11 are internally connected back
          * to back, and not brought out.
@@ -528,293 +258,68 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        platform_device_register(&mv78xx0_ge11_shared);
-        platform_device_register(&mv78xx0_ge11);
+        orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
+                        NO_IRQ, get_tclk());
 }
 
 /*****************************************************************************
- * I2C bus 0
- ****************************************************************************/
-
-static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource mv78xx0_i2c_0_resources[] = {
-        {
-                .start  = I2C_0_PHYS_BASE,
-                .end    = I2C_0_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_I2C_0,
-                .end    = IRQ_MV78XX0_I2C_0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-
-static struct platform_device mv78xx0_i2c_0 = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(mv78xx0_i2c_0_resources),
-        .resource       = mv78xx0_i2c_0_resources,
-        .dev            = {
-                .platform_data  = &mv78xx0_i2c_0_pdata,
-        },
-};
-
-/*****************************************************************************
- * I2C bus 1
+ * I2C
  ****************************************************************************/
-
-static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource mv78xx0_i2c_1_resources[] = {
-        {
-                .start  = I2C_1_PHYS_BASE,
-                .end    = I2C_1_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_I2C_1,
-                .end    = IRQ_MV78XX0_I2C_1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-
-static struct platform_device mv78xx0_i2c_1 = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(mv78xx0_i2c_1_resources),
-        .resource       = mv78xx0_i2c_1_resources,
-        .dev            = {
-                .platform_data  = &mv78xx0_i2c_1_pdata,
-        },
-};
-
 void __init mv78xx0_i2c_init(void)
 {
-        platform_device_register(&mv78xx0_i2c_0);
-        platform_device_register(&mv78xx0_i2c_1);
+        orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
+        orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
 }
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource mv78xx0_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = SATA_PHYS_BASE,
-                .end    = SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_MV78XX0_SATA,
-                .end    = IRQ_MV78XX0_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(mv78xx0_sata_resources),
-        .resource       = mv78xx0_sata_resources,
-};
-
 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        sata_data->dram = &mv78xx0_mbus_dram_info;
-        mv78xx0_sata.dev.platform_data = sata_data;
-        platform_device_register(&mv78xx0_sata);
+        orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
+                        SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 }
 
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_0,
-                .end            = IRQ_MV78XX0_UART_0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart0_data,
-        },
-        .resource               = mv78xx0_uart0_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart0_resources),
-};
-
 void __init mv78xx0_uart0_init(void)
 {
-        platform_device_register(&mv78xx0_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_MV78XX0_UART_0, get_tclk());
 }
 
 
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_1,
-                .end            = IRQ_MV78XX0_UART_1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart1_data,
-        },
-        .resource               = mv78xx0_uart1_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart1_resources),
-};
-
 void __init mv78xx0_uart1_init(void)
 {
-        platform_device_register(&mv78xx0_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_MV78XX0_UART_1, get_tclk());
 }
 
 
 /*****************************************************************************
  * UART2
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart2_data[] = {
-        {
-                .mapbase        = UART2_PHYS_BASE,
-                .membase        = (char *)UART2_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_2,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart2_resources[] = {
-        {
-                .start          = UART2_PHYS_BASE,
-                .end            = UART2_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_2,
-                .end            = IRQ_MV78XX0_UART_2,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart2 = {
-        .name                   = "serial8250",
-        .id                     = 2,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart2_data,
-        },
-        .resource               = mv78xx0_uart2_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart2_resources),
-};
-
 void __init mv78xx0_uart2_init(void)
 {
-        platform_device_register(&mv78xx0_uart2);
+        orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
+                         IRQ_MV78XX0_UART_2, get_tclk());
 }
 
-
 /*****************************************************************************
  * UART3
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart3_data[] = {
-        {
-                .mapbase        = UART3_PHYS_BASE,
-                .membase        = (char *)UART3_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_3,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart3_resources[] = {
-        {
-                .start          = UART3_PHYS_BASE,
-                .end            = UART3_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_3,
-                .end            = IRQ_MV78XX0_UART_3,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart3 = {
-        .name                   = "serial8250",
-        .id                     = 3,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart3_data,
-        },
-        .resource               = mv78xx0_uart3_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart3_resources),
-};
-
 void __init mv78xx0_uart3_init(void)
 {
-        platform_device_register(&mv78xx0_uart3);
+        orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
+                         IRQ_MV78XX0_UART_3, get_tclk());
 }
 
-
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
@@ -895,13 +400,4 @@ void __init mv78xx0_init(void)
 #ifdef CONFIG_CACHE_FEROCEON_L2
         feroceon_l2_init(is_l2_writethrough());
 #endif
-
-        mv78xx0_ge00_shared_data.t_clk = tclk;
-        mv78xx0_ge01_shared_data.t_clk = tclk;
-        mv78xx0_ge10_shared_data.t_clk = tclk;
-        mv78xx0_ge11_shared_data.t_clk = tclk;
-        mv78xx0_uart0_data[0].uartclk = tclk;
-        mv78xx0_uart1_data[0].uartclk = tclk;
-        mv78xx0_uart2_data[0].uartclk = tclk;
-        mv78xx0_uart3_data[0].uartclk = tclk;
 }
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 65b72c454cb..59b7686b920 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <plat/mpp.h>
 #include <asm/gpio.h>
 #include <mach/hardware.h>
 #include "common.h"
@@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void)
         return 0;
 }
 
-#define MPP_CTRL(i)     (DEV_BUS_VIRT_BASE + (i) * 4)
-#define MPP_NR_REGS     (1 + MPP_MAX/8)
-
 void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
 {
-        u32 mpp_ctrl[MPP_NR_REGS];
-        unsigned int variant_mask;
-        int i;
-
-        variant_mask = mv78xx0_variant();
-        if (!variant_mask)
-                return;
-
-        printk(KERN_DEBUG "initial MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                mpp_ctrl[i] = readl(MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
-
-        for ( ; *mpp_list; mpp_list++) {
-                unsigned int num = MPP_NUM(*mpp_list);
-                unsigned int sel = MPP_SEL(*mpp_list);
-                int shift, gpio_mode;
-
-                if (num > MPP_MAX) {
-                        printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP "
-                                        "number (%u)\n", num);
-                        continue;
-                }
-                if (!(*mpp_list & variant_mask)) {
-                        printk(KERN_WARNING
-                                        "mv78xx0_mpp_conf: requested MPP%u config "
-                                        "unavailable on this hardware\n", num);
-                        continue;
-                }
-
-                shift = (num & 7) << 2;
-                mpp_ctrl[num / 8] &= ~(0xf << shift);
-                mpp_ctrl[num / 8] |= sel << shift;
-
-                gpio_mode = 0;
-                if (*mpp_list & MPP_INPUT_MASK)
-                        gpio_mode |= GPIO_INPUT_OK;
-                if (*mpp_list & MPP_OUTPUT_MASK)
-                        gpio_mode |= GPIO_OUTPUT_OK;
-                if (sel != 0)
-                        gpio_mode = 0;
-                orion_gpio_set_valid(num, gpio_mode);
-        }
-
-        printk(KERN_DEBUG "  final MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                writel(mpp_ctrl[i], MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
+        orion_mpp_conf(mpp_list, mv78xx0_variant(),
+                       MPP_MAX, DEV_BUS_VIRT_BASE);
 }
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index 80840b781ea..b61b5092712 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -19,14 +19,8 @@
     /* may be output signal */    ((!!(_out)) << 13) | \
     /* available on A0 */    ((!!(_78100_A0)) << 14))
 
-#define MPP_NUM(x)    ((x) & 0xff)
-#define MPP_SEL(x)    (((x) >> 8) & 0xf)
-
                 /*   num sel  i  o  78100_A0  */
 
-#define MPP_INPUT_MASK        MPP(0, 0x0, 1, 0, 0)
-#define MPP_OUTPUT_MASK        MPP(0, 0x0, 0, 1, 0)
-
 #define MPP_78100_A0_MASK    MPP(0, 0x0, 0, 0, 1)
 
 #define MPP0_GPIO        MPP(0, 0x0, 1, 1, 1)
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index f12a1732d8b..7f8bf653964 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -20,7 +20,7 @@
 
 #include <asm/mach-types.h>
 
-static unsigned long mxs_duart_base;
+unsigned long mxs_duart_base;
 
 #define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
 
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
index 770a68c46e8..00ef4a6d7cb 100644
--- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
@@ -20,7 +20,7 @@ static void putc_dummy(char c, void __iomem *base)
         /* nothing */
 }
 
-static int timeout;
+int timeout;
 
 static void putc_ns9360(char c, void __iomem *base)
 {
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
index 73082cd61e8..381cb9baadd 100644
--- a/arch/arm/mach-nuc93x/include/mach/uncompress.h
+++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h
@@ -27,7 +27,7 @@
 #define arch_decomp_wdog()
 
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-static u32 * uart_base = (u32 *)UART0_PA;
+static u32 * const uart_base = (u32 *)UART0_PA;
 
 static void putc(int ch)
 {
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index 927d5a18176..c1c5fb6a5b4 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -79,7 +79,7 @@
 
 
 /*
- * Register useage
+ * Register usage
  * r8  - temporary
  * r9  - the driver buffer
  * r10 - temporary
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index d41fe2d0616..0ad781db4e6 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -399,7 +399,7 @@ static void __init omap_sx1_init(void)
         sx1_mmc_init();
 
         /* turn on USB power */
-        /* sx1_setusbpower(1); cant do it here because i2c is not ready */
+        /* sx1_setusbpower(1); can't do it here because i2c is not ready */
         gpio_request(1, "A_IRDA_OFF");
         gpio_request(11, "A_SWITCH");
         gpio_request(15, "A_USB_ON");
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index b0f4c231595..36f26c3fa25 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -281,7 +281,7 @@ static inline void omap_init_audio(void) {}
  * Claiming GPIOs, and setting their direction and initial values, is the
  * responsibility of the device drivers.  So is responding to probe().
  *
- * Board-specific knowlege like creating devices or pin setup is to be
+ * Board-specific knowledge like creating devices or pin setup is to be
  * kept out of drivers as much as possible.  In particular, pin setup
  * may be handled by the boot loader, and drivers should expect it will
  * normally have been done by the time they're probed.
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
index 7a2df29400c..23eed0035ed 100644
--- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
+++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
@@ -31,7 +31,7 @@
 #endif
 
 /*
- * These are the offsets from the begining of the fiq_buffer. They are put here
+ * These are the offsets from the beginning of the fiq_buffer. They are put here
  * since the buffer and header need to be accessed by drivers servicing devices
  * which generate GPIO interrupts - e.g. keyboard, modem, hook switch.
  */
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index a45cd640968..512b1520445 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -68,7 +68,7 @@ obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
-AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a
+AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
 
 ifeq ($(CONFIG_PM_VERBOSE),y)
 CFLAGS_pm_bus.o                         += -DDEBUG
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 5f8a2fd0633..34cf982b967 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -696,7 +696,7 @@ static void __init igep2_init(void)
         igep2_init_smsc911x();
 
         /*
-         * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+         * WLAN-BT combo module from MuRata which has a Marvell WLAN
          * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
          */
         igep2_wlan_bt_init();
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index b10db0e6ee6..2cf86c3cb1a 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -440,7 +440,7 @@ static void __init igep3_init(void)
         igep3_leds_init();
 
         /*
-         * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+         * WLAN-BT combo module from MuRata which has a Marvell WLAN
          * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
          */
         igep3_wifi_bt_init();
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index e964895b80e..f8ba20a14e6 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -141,14 +141,19 @@ static void __init rx51_init(void)
 static void __init rx51_map_io(void)
 {
         omap2_set_globals_3xxx();
-        rx51_video_mem_init();
         omap34xx_map_common_io();
 }
 
+static void __init rx51_reserve(void)
+{
+        rx51_video_mem_init();
+        omap_reserve();
+}
+
 MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
         .boot_params    = 0x80000100,
-        .reserve        = omap_reserve,
+        .reserve        = rx51_reserve,
         .map_io         = rx51_map_io,
         .init_early     = rx51_init_early,
         .init_irq       = omap_init_irq,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 276992d3b7f..8c965671b4d 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3116,14 +3116,9 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
         CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
         CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
-        CLK("omapdss_dss",      "dss_clk",                      &dss_dss_clk,   CK_443X),
         CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
-        CLK("omapdss_dss",      "fck",                          &dss_fck,       CK_443X),
-        /*
-         * On OMAP4, DSS ick is a dummy clock; this is needed for compatibility
-         * with OMAP2/3.
-         */
-        CLK("omapdss_dss",      "ick",                          &dummy_ck,      CK_443X),
+        CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
+        CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ab878545bd9..6cb6c03293d 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -258,7 +258,7 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
  * clkdm_init - set up the clockdomain layer
  * @clkdms: optional pointer to an array of clockdomains to register
  * @init_autodeps: optional pointer to an array of autodeps to register
- * @custom_funcs: func pointers for arch specfic implementations
+ * @custom_funcs: func pointers for arch specific implementations
  *
  * Set up internal state.  If a pointer to an array of clockdomains
  * @clkdms was supplied, loop through the list of clockdomains,
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 85b3dce6564..5823584d9cd 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -125,7 +125,7 @@ struct clockdomain {
 };
 
 /**
- * struct clkdm_ops - Arch specfic function implementations
+ * struct clkdm_ops - Arch specific function implementations
  * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
  * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
  * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 9d0dec806e9..38830d8d478 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -247,6 +247,7 @@ struct omap3_cm_regs {
         u32 per_cm_clksel;
         u32 emu_cm_clksel;
         u32 emu_cm_clkstctrl;
+        u32 pll_cm_autoidle;
         u32 pll_cm_autoidle2;
         u32 pll_cm_clksel4;
         u32 pll_cm_clksel5;
@@ -319,6 +320,15 @@ void omap3_cm_save_context(void)
                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
         cm_context.emu_cm_clkstctrl =
                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
+         * In this case, even though this register has been saved in
+         * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
+         * by ourselves. So, we need to save it anyway.
+         */
+        cm_context.pll_cm_autoidle =
+                omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
         cm_context.pll_cm_autoidle2 =
                 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
         cm_context.pll_cm_clksel4 =
@@ -441,6 +451,13 @@ void omap3_cm_restore_context(void)
                                CM_CLKSEL1);
         omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
                                OMAP2_CM_CLKSTCTRL);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
+         * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
+         */
+        omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
+                               CM_AUTOIDLE);
         omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
                                CM_AUTOIDLE2);
         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 69527941902..da53ba3917c 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -316,8 +316,14 @@ void omap3_save_scratchpad_contents(void)
                         omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
         prcm_block_contents.cm_clken_pll =
                         omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        /*
+         * As per erratum i671, ROM code does not respect the PER DPLL
+         * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
+         * Then,  in anycase, clear these bits to avoid extra latencies.
+         */
         prcm_block_contents.cm_autoidle_pll =
-                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+                        omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
+                        ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
         prcm_block_contents.cm_clksel1_pll =
                         omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
         prcm_block_contents.cm_clksel2_pll =
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index a44c5230340..1c240eff391 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -297,8 +297,8 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 
 /**
  * omap3_cpuidle_update_states() - Update the cpuidle states
- * @mpu_deepest_state:  Enable states upto and including this for mpu domain
- * @core_deepest_state: Enable states upto and including this for core domain
+ * @mpu_deepest_state:  Enable states up to and including this for mpu domain
+ * @core_deepest_state: Enable states up to and including this for core domain
  *
  * This goes through the list of states available and enables and disables the
  * validity of C states based on deepest state that can be achieved for the
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 84d1b735fe8..7b855856459 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -253,7 +253,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
                         ARRAY_SIZE(omap_keyboard_latency), 0);
 
         if (IS_ERR(od)) {
-                WARN(1, "Cant build omap_device for %s:%s.\n",
+                WARN(1, "Can't build omap_device for %s:%s.\n",
                                                 name, oh->name);
                 return PTR_ERR(od);
         }
@@ -373,7 +373,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
         od = omap_device_build(name, spi_num, oh, pdata,
                                 sizeof(*pdata), omap_mcspi_latency,
                                 ARRAY_SIZE(omap_mcspi_latency), 0);
-        WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
+        WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n",
                                 name, oh->name);
         kfree(pdata);
         return 0;
@@ -725,7 +725,7 @@ static int __init omap_init_wdt(void)
         od = omap_device_build(dev_name, id, oh, NULL, 0,
                                 omap_wdt_latency,
                                 ARRAY_SIZE(omap_wdt_latency), 0);
-        WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
+        WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n",
                                 dev_name, oh->name);
         return 0;
 }
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 34922b2d2e3..c9ff0e79703 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -262,7 +262,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
                         omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
         kfree(p);
         if (IS_ERR(od)) {
-                pr_err("%s: Cant build omap_device for %s:%s.\n",
+                pr_err("%s: Can't build omap_device for %s:%s.\n",
                         __func__, name, oh->name);
                 return PTR_ERR(od);
         }
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 413de18c1d2..9529842ae05 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -82,7 +82,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
         kfree(pdata);
 
         if (IS_ERR(od)) {
-                WARN(1, "Cant build omap_device for %s:%s.\n",
+                WARN(1, "Can't build omap_device for %s:%s.\n",
                                         name, oh->name);
                 return PTR_ERR(od);
         }
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 137e1a5f3d8..b2f30bed5a2 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -465,7 +465,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
         od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
                 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
         if (IS_ERR(od)) {
-                WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
+                WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
                 kfree(mmc_data->slots[0].name);
                 goto done;
         }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 237e4530abf..3af2b7a1045 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -73,83 +73,18 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
         return __raw_readl(bank->base_reg + reg);
 }
 
-static int previous_irq;
-
-/*
- * On 34xx we can get occasional spurious interrupts if the ack from
- * an interrupt handler does not get posted before we unmask. Warn about
- * the interrupt handlers that need to flush posted writes.
- */
-static int omap_check_spurious(unsigned int irq)
-{
-        u32 sir, spurious;
-
-        sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
-        spurious = sir >> 7;
-
-        if (spurious) {
-                printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
-                                        "posted write for irq %i\n",
-                                        irq, sir, previous_irq);
-                return spurious;
-        }
-
-        return 0;
-}
-
 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
 static void omap_ack_irq(struct irq_data *d)
 {
         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
 }
 
-static void omap_mask_irq(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
-        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
-                int spurious = 0;
-
-                /*
-                 * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
-                 * it is the highest irq number?
-                 */
-                if (irq == INT_34XX_GPT12_IRQ)
-                        spurious = omap_check_spurious(irq);
-
-                if (!spurious)
-                        previous_irq = irq;
-        }
-
-        irq &= (IRQ_BITS_PER_REG - 1);
-
-        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
-}
-
-static void omap_unmask_irq(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
-        irq &= (IRQ_BITS_PER_REG - 1);
-
-        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
-}
-
 static void omap_mask_ack_irq(struct irq_data *d)
 {
-        omap_mask_irq(d);
+        irq_gc_mask_disable_reg(d);
         omap_ack_irq(d);
 }
 
-static struct irq_chip omap_irq_chip = {
-        .name           = "INTC",
-        .irq_ack        = omap_mask_ack_irq,
-        .irq_mask       = omap_mask_irq,
-        .irq_unmask     = omap_unmask_irq,
-};
-
 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 {
         unsigned long tmp;
@@ -186,11 +121,31 @@ int omap_irq_pending(void)
         return 0;
 }
 
+static __init void
+omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
+                                        handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = omap_mask_ack_irq;
+        ct->chip.irq_mask = irq_gc_mask_disable_reg;
+        ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+
+        ct->regs.ack = INTC_CONTROL;
+        ct->regs.enable = INTC_MIR_CLEAR0;
+        ct->regs.disable = INTC_MIR_SET0;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+}
+
 void __init omap_init_irq(void)
 {
         unsigned long nr_of_irqs = 0;
         unsigned int nr_banks = 0;
-        int i;
+        int i, j;
 
         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
                 unsigned long base = 0;
@@ -215,17 +170,15 @@ void __init omap_init_irq(void)
 
                 omap_irq_bank_init_one(bank);
 
+                for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
+                        omap_alloc_gc(bank->base_reg + j, i, 32);
+
                 nr_of_irqs += bank->nr_irqs;
                 nr_banks++;
         }
 
         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
-
-        for (i = 0; i < nr_of_irqs; i++) {
-                irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 565b9064a32..4a6ef6ab845 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -149,7 +149,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                                 ARRAY_SIZE(omap2_mcbsp_latency), false);
         kfree(pdata);
         if (IS_ERR(od))  {
-                pr_err("%s: Cant build omap_device for %s:%s.\n", __func__,
+                pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
                                         name, oh->name);
                 return PTR_ERR(od);
         }
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index bb043cbb388..a4ab1e36431 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -518,7 +518,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
                         seq_printf(s, "/* %s */\n", m->muxnames[mode]);
 
                 /*
-                 * XXX: Might be revisited to support differences accross
+                 * XXX: Might be revisited to support differences across
                  * same OMAP generation.
                  */
                 seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
index adbea0d03e0..9fd93149ebd 100644
--- a/arch/arm/mach-omap2/mux2430.h
+++ b/arch/arm/mach-omap2/mux2430.h
@@ -22,7 +22,7 @@
  * absolute addresses.  The name in the macro is the mode-0 name of
  * the pin.  NOTE: These registers are 8-bits wide.
  *
- * Note that these defines use SDMMC instead of MMC for compability
+ * Note that these defines use SDMMC instead of MMC for compatibility
  * with signal names used in 3630.
  */
 #define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET                0x000
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 8eb3ce1bbfb..c4d0ae87d62 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1639,6 +1639,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
 
 static struct omap_hwmod omap2420_gpio1_hwmod = {
         .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap242x_gpio1_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio1_irqs),
         .main_clk       = "gpios_fck",
@@ -1669,6 +1670,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
 
 static struct omap_hwmod omap2420_gpio2_hwmod = {
         .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap242x_gpio2_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio2_irqs),
         .main_clk       = "gpios_fck",
@@ -1699,6 +1701,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
 
 static struct omap_hwmod omap2420_gpio3_hwmod = {
         .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap242x_gpio3_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio3_irqs),
         .main_clk       = "gpios_fck",
@@ -1729,6 +1732,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
 
 static struct omap_hwmod omap2420_gpio4_hwmod = {
         .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap242x_gpio4_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio4_irqs),
         .main_clk       = "gpios_fck",
@@ -1782,7 +1786,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
 static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
         {
                 .pa_start       = 0x48056000,
-                .pa_end         = 0x4a0560ff,
+                .pa_end         = 0x48056fff,
                 .flags          = ADDR_TYPE_RT
         },
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index a860fb5024c..9682dd519f8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1559,7 +1559,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
                          * I2CHS IP's do not follow the usual pattern.
                          * prcm_reg_id alone cannot be used to program
                          * the iclk and fclk. Needs to be handled using
-                         * additonal flags when clk handling is moved
+                         * additional flags when clk handling is moved
                          * to hwmod framework.
                          */
                         .module_offs = CORE_MOD,
@@ -1742,6 +1742,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
 
 static struct omap_hwmod omap2430_gpio1_hwmod = {
         .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap243x_gpio1_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
         .main_clk       = "gpios_fck",
@@ -1772,6 +1773,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
 
 static struct omap_hwmod omap2430_gpio2_hwmod = {
         .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap243x_gpio2_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
         .main_clk       = "gpios_fck",
@@ -1802,6 +1804,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
 
 static struct omap_hwmod omap2430_gpio3_hwmod = {
         .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap243x_gpio3_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
         .main_clk       = "gpios_fck",
@@ -1832,6 +1835,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
 
 static struct omap_hwmod omap2430_gpio4_hwmod = {
         .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap243x_gpio4_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
         .main_clk       = "gpios_fck",
@@ -1862,6 +1866,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
 
 static struct omap_hwmod omap2430_gpio5_hwmod = {
         .name           = "gpio5",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap243x_gpio5_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
         .main_clk       = "gpio5_fck",
@@ -1915,7 +1920,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
         {
                 .pa_start       = 0x48056000,
-                .pa_end         = 0x4a0560ff,
+                .pa_end         = 0x48056fff,
                 .flags          = ADDR_TYPE_RT
         },
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index b98e2dfcba2..909a84de668 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2141,6 +2141,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
 
 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
         .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio1_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
         .main_clk       = "gpio1_ick",
@@ -2177,6 +2178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
 
 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
         .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio2_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
         .main_clk       = "gpio2_ick",
@@ -2213,6 +2215,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
 
 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
         .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio3_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
         .main_clk       = "gpio3_ick",
@@ -2249,6 +2252,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
 
 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
         .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio4_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
         .main_clk       = "gpio4_ick",
@@ -2285,6 +2289,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
 
 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
         .name           = "gpio5",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio5_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
         .main_clk       = "gpio5_ick",
@@ -2321,6 +2326,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
 
 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
         .name           = "gpio6",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .mpu_irqs       = omap3xxx_gpio6_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
         .main_clk       = "gpio6_ick",
@@ -2386,7 +2392,7 @@ static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
         {
                 .pa_start       = 0x48056000,
-                .pa_end         = 0x4a0560ff,
+                .pa_end         = 0x48056fff,
                 .flags          = ADDR_TYPE_RT
         },
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3e88dd3f8ef..abc548a0c98 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -885,7 +885,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
         {
                 .pa_start       = 0x4a056000,
-                .pa_end         = 0x4a0560ff,
+                .pa_end         = 0x4a056fff,
                 .flags          = ADDR_TYPE_RT
         },
 };
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index 5f2da7565b6..4321e793892 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -196,11 +196,11 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
                 /* No timeout error for debug sources */
         }
 
-        base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source)));
-
         /* identify the error source */
         for (err_source = 0; !(status & (1 << err_source)); err_source++)
                                                                         ;
+
+        base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
         error = omap3_l3_readll(base, L3_ERROR_LOG);
 
         if (error) {
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index e2e605fe913..05f6abc96b0 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -112,12 +112,12 @@ int omap4430_phy_power(struct device *dev, int ID, int on)
                 else
                         /*
                          * Enable VBUS Valid, AValid and IDDIG
-                         * high impedence
+                         * high impedance
                          */
                         __raw_writel(IDDIG | AVALID | VBUSVALID,
                                                 ctrl_base + USBOTGHS_CONTROL);
         } else {
-                /* Enable session END and IDIG to high impedence. */
+                /* Enable session END and IDIG to high impedance. */
                 __raw_writel(SESSEND | IDDIG, ctrl_base +
                                         USBOTGHS_CONTROL);
         }
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 0a8e74e3e81..07d6140baa9 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -308,7 +308,7 @@ int __init omap3_twl_init(void)
  * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
  * in those scenarios this bit is to be cleared (enable = false).
  *
- * Returns 0 on sucess, error is returned if I2C read/write fails.
+ * Returns 0 on success, error is returned if I2C read/write fails.
  */
 int __init omap3_twl_set_sr_bit(bool enable)
 {
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 30af3351c2d..49486f522dc 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -89,6 +89,7 @@ static void omap2_init_processor_devices(void)
         if (cpu_is_omap44xx()) {
                 _init_omap_device("l3_main_1", &l3_dev);
                 _init_omap_device("dsp", &dsp_dev);
+                _init_omap_device("iva", &iva_dev);
         } else {
                 _init_omap_device("l3_main", &l3_dev);
         }
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 49c6513e90d..9af08473bf1 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -196,7 +196,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
 /**
  * pwrdm_init - set up the powerdomain layer
  * @pwrdm_list: array of struct powerdomain pointers to register
- * @custom_funcs: func pointers for arch specfic implementations
+ * @custom_funcs: func pointers for arch specific implementations
  *
  * Loop through the array of powerdomains @pwrdm_list, registering all
  * that are available on the current CPU. If pwrdm_list is supplied
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 027f40bd235..d23d979b9c3 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -121,7 +121,7 @@ struct powerdomain {
 };
 
 /**
- * struct pwrdm_ops - Arch specfic function implementations
+ * struct pwrdm_ops - Arch specific function implementations
  * @pwrdm_set_next_pwrst: Set the target power state for a pd
  * @pwrdm_read_next_pwrst: Read the target power state set for a pd
  * @pwrdm_read_pwrst: Read the current power state of a pd
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 9c9c113788b..469a920a74d 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -72,7 +72,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
 
 /*
  * The USBTLL Save-and-Restore mechanism is broken on
- * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
+ * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
  * needs to be disabled on these chips.
  * Refer: 3430 errata ID i459 and 3630 errata ID i579
  *
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 8f674c9442b..13e24f913dd 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -247,7 +247,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
  * driver register and sr device intializtion API's. Only one call
  * will ultimately succeed.
  *
- * Currenly this function registers interrrupt handler for a particular SR
+ * Currently this function registers interrrupt handler for a particular SR
  * if smartreflex class driver is already registered and has
  * requested for interrupts and the SR interrupt line in present.
  */
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index c6facf7becf..0c1552d9d99 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -114,7 +114,6 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
         sys_clk_speed /= 1000;
 
         /* Generic voltage parameters */
-        vdd->curr_volt = 1200000;
         vdd->volt_scale = vp_forceupdate_scale_voltage;
         vdd->vp_enabled = false;
 
@@ -851,7 +850,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
  * @voltdm:     pointer to the VDD whose voltage is to be reset.
  *
  * This API finds out the correct voltage the voltage domain is supposed
- * to be at and resets the voltage to that level. Should be used expecially
+ * to be at and resets the voltage to that level. Should be used especially
  * while disabling any voltage compensation modules.
  */
 void omap_voltage_reset(struct voltagedomain *voltdm)
@@ -912,7 +911,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
  * This API searches only through the non-compensated voltages int the
  * voltage table.
  * Returns pointer to the voltage table entry corresponding to volt on
- * sucess. Returns -ENODATA if no voltage table exisits for the passed voltage
+ * success. Returns -ENODATA if no voltage table exisits for the passed voltage
  * domain or if there is no matching entry.
  */
 struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 1a5d6a0e260..5ceafdccc45 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -19,7 +19,7 @@
 #include "common.h"
 
 /*
- * The Orion has fully programable address map. There's a separate address
+ * The Orion has fully programmable address map. There's a separate address
  * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
  * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
  * address decode windows that allow it to access any of the Orion resources.
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 986c3bf4e6b..0ab531d047f 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -13,12 +13,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
-#include <linux/spi/orion_spi.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -29,11 +28,9 @@
 #include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
-#include <plat/ehci-orion.h>
-#include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
-#include <plat/orion_wdt.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -70,530 +67,124 @@ void __init orion5x_map_io(void)
 
 
 /*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data orion5x_ehci_data = {
-        .dram           = &orion5x_mbus_dram_info,
-        .phy_version    = EHCI_PHY_ORION,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
-
-/*****************************************************************************
  * EHCI0
  ****************************************************************************/
-static struct resource orion5x_ehci0_resources[] = {
-        {
-                .start  = ORION5X_USB0_PHYS_BASE,
-                .end    = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_USB0_CTRL,
-                .end    = IRQ_ORION5X_USB0_CTRL,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_ehci0 = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &orion5x_ehci_data,
-        },
-        .resource       = orion5x_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(orion5x_ehci0_resources),
-};
-
 void __init orion5x_ehci0_init(void)
 {
-        platform_device_register(&orion5x_ehci0);
+        orion_ehci_init(&orion5x_mbus_dram_info,
+                        ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
 }
 
 
 /*****************************************************************************
  * EHCI1
  ****************************************************************************/
-static struct resource orion5x_ehci1_resources[] = {
-        {
-                .start  = ORION5X_USB1_PHYS_BASE,
-                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_USB1_CTRL,
-                .end    = IRQ_ORION5X_USB1_CTRL,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_ehci1 = {
-        .name           = "orion-ehci",
-        .id             = 1,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &orion5x_ehci_data,
-        },
-        .resource       = orion5x_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(orion5x_ehci1_resources),
-};
-
 void __init orion5x_ehci1_init(void)
 {
-        platform_device_register(&orion5x_ehci1);
+        orion_ehci_1_init(&orion5x_mbus_dram_info,
+                          ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
 }
 
 
 /*****************************************************************************
- * GigE
+ * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
-        .dram           = &orion5x_mbus_dram_info,
-};
-
-static struct resource orion5x_eth_shared_resources[] = {
-        {
-                .start  = ORION5X_ETH_PHYS_BASE + 0x2000,
-                .end    = ORION5X_ETH_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_ETH_ERR,
-                .end    = IRQ_ORION5X_ETH_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_eth_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &orion5x_eth_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_eth_shared_resources),
-        .resource       = orion5x_eth_shared_resources,
-};
-
-static struct resource orion5x_eth_resources[] = {
-        {
-                .name   = "eth irq",
-                .start  = IRQ_ORION5X_ETH_SUM,
-                .end    = IRQ_ORION5X_ETH_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_eth = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = orion5x_eth_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &orion5x_eth_shared;
-        orion5x_eth.dev.platform_data = eth_data;
-
-        platform_device_register(&orion5x_eth_shared);
-        platform_device_register(&orion5x_eth);
+        orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
+                        ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
+                        IRQ_ORION5X_ETH_ERR, orion5x_tclk);
 }
 
 
 /*****************************************************************************
  * Ethernet switch
  ****************************************************************************/
-static struct resource orion5x_switch_resources[] = {
-        {
-                .start  = 0,
-                .end    = 0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_switch_device = {
-        .name           = "dsa",
-        .id             = 0,
-        .num_resources  = 0,
-        .resource       = orion5x_switch_resources,
-};
-
 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 {
-        int i;
-
-        if (irq != NO_IRQ) {
-                orion5x_switch_resources[0].start = irq;
-                orion5x_switch_resources[0].end = irq;
-                orion5x_switch_device.num_resources = 1;
-        }
-
-        d->netdev = &orion5x_eth.dev;
-        for (i = 0; i < d->nr_chips; i++)
-                d->chip[i].mii_bus = &orion5x_eth_shared.dev;
-        orion5x_switch_device.dev.platform_data = d;
-
-        platform_device_register(&orion5x_switch_device);
+        orion_ge00_switch_init(d, irq);
 }
 
 
 /*****************************************************************************
  * I2C
  ****************************************************************************/
-static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource orion5x_i2c_resources[] = {
-        {
-                .start  = I2C_PHYS_BASE,
-                .end    = I2C_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_I2C,
-                .end    = IRQ_ORION5X_I2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_i2c = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(orion5x_i2c_resources),
-        .resource       = orion5x_i2c_resources,
-        .dev            = {
-                .platform_data  = &orion5x_i2c_pdata,
-        },
-};
-
 void __init orion5x_i2c_init(void)
 {
-        platform_device_register(&orion5x_i2c);
+        orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
+
 }
 
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource orion5x_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = ORION5X_SATA_PHYS_BASE,
-                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_ORION5X_SATA,
-                .end    = IRQ_ORION5X_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
-        .resource       = orion5x_sata_resources,
-};
-
 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        sata_data->dram = &orion5x_mbus_dram_info;
-        orion5x_sata.dev.platform_data = sata_data;
-        platform_device_register(&orion5x_sata);
+        orion_sata_init(sata_data, &orion5x_mbus_dram_info,
+                        ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 }
 
 
 /*****************************************************************************
  * SPI
  ****************************************************************************/
-static struct orion_spi_info orion5x_spi_plat_data = {
-        .tclk                   = 0,
-        .enable_clock_fix       = 1,
-};
-
-static struct resource orion5x_spi_resources[] = {
-        {
-                .name   = "spi base",
-                .start  = SPI_PHYS_BASE,
-                .end    = SPI_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device orion5x_spi = {
-        .name           = "orion_spi",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &orion5x_spi_plat_data,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_spi_resources),
-        .resource       = orion5x_spi_resources,
-};
-
 void __init orion5x_spi_init()
 {
-        platform_device_register(&orion5x_spi);
+        orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
 }
 
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port orion5x_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource orion5x_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_ORION5X_UART0,
-                .end            = IRQ_ORION5X_UART0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_uart0 = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = orion5x_uart0_data,
-        },
-        .resource               = orion5x_uart0_resources,
-        .num_resources          = ARRAY_SIZE(orion5x_uart0_resources),
-};
-
 void __init orion5x_uart0_init(void)
 {
-        platform_device_register(&orion5x_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_ORION5X_UART0, orion5x_tclk);
 }
 
-
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port orion5x_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource orion5x_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_ORION5X_UART1,
-                .end            = IRQ_ORION5X_UART1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_uart1 = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM1,
-        .dev                    = {
-                .platform_data  = orion5x_uart1_data,
-        },
-        .resource               = orion5x_uart1_resources,
-        .num_resources          = ARRAY_SIZE(orion5x_uart1_resources),
-};
-
 void __init orion5x_uart1_init(void)
 {
-        platform_device_register(&orion5x_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_ORION5X_UART1, orion5x_tclk);
 }
 
-
 /*****************************************************************************
  * XOR engine
  ****************************************************************************/
-struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
-        .dram           = &orion5x_mbus_dram_info,
-};
-
-static struct resource orion5x_xor_shared_resources[] = {
-        {
-                .name   = "xor low",
-                .start  = ORION5X_XOR_PHYS_BASE,
-                .end    = ORION5X_XOR_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor high",
-                .start  = ORION5X_XOR_PHYS_BASE + 0x200,
-                .end    = ORION5X_XOR_PHYS_BASE + 0x2ff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device orion5x_xor_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &orion5x_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_xor_shared_resources),
-        .resource       = orion5x_xor_shared_resources,
-};
-
-static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
-
-static struct resource orion5x_xor0_resources[] = {
-        [0] = {
-                .start  = IRQ_ORION5X_XOR0,
-                .end    = IRQ_ORION5X_XOR0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data orion5x_xor0_data = {
-        .shared         = &orion5x_xor_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device orion5x_xor0_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(orion5x_xor0_resources),
-        .resource       = orion5x_xor0_resources,
-        .dev            = {
-                .dma_mask               = &orion5x_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &orion5x_xor0_data,
-        },
-};
-
-static struct resource orion5x_xor1_resources[] = {
-        [0] = {
-                .start  = IRQ_ORION5X_XOR1,
-                .end    = IRQ_ORION5X_XOR1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data orion5x_xor1_data = {
-        .shared         = &orion5x_xor_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device orion5x_xor1_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(orion5x_xor1_resources),
-        .resource       = orion5x_xor1_resources,
-        .dev            = {
-                .dma_mask               = &orion5x_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &orion5x_xor1_data,
-        },
-};
-
 void __init orion5x_xor_init(void)
 {
-        platform_device_register(&orion5x_xor_shared);
-
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
-        dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
-        platform_device_register(&orion5x_xor0_channel);
-
-        dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
-        dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
-        platform_device_register(&orion5x_xor1_channel);
+        orion_xor0_init(&orion5x_mbus_dram_info,
+                        ORION5X_XOR_PHYS_BASE,
+                        ORION5X_XOR_PHYS_BASE + 0x200,
+                        IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 }
 
-static struct resource orion5x_crypto_res[] = {
-        {
-                .name   = "regs",
-                .start  = ORION5X_CRYPTO_PHYS_BASE,
-                .end    = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sram",
-                .start  = ORION5X_SRAM_PHYS_BASE,
-                .end    = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "crypto interrupt",
-                .start  = IRQ_ORION5X_CESA,
-                .end    = IRQ_ORION5X_CESA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_crypto_device = {
-        .name           = "mv_crypto",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(orion5x_crypto_res),
-        .resource       = orion5x_crypto_res,
-};
-
-static int __init orion5x_crypto_init(void)
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+static void __init orion5x_crypto_init(void)
 {
         int ret;
 
         ret = orion5x_setup_sram_win();
         if (ret)
-                return ret;
+                return;
 
-        return platform_device_register(&orion5x_crypto_device);
+        orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
+                          SZ_8K, IRQ_ORION5X_CESA);
 }
 
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static struct orion_wdt_platform_data orion5x_wdt_data = {
-        .tclk                   = 0,
-};
-
-static struct platform_device orion5x_wdt_device = {
-        .name           = "orion_wdt",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &orion5x_wdt_data,
-        },
-        .num_resources  = 0,
-};
-
 void __init orion5x_wdt_init(void)
 {
-        orion5x_wdt_data.tclk = orion5x_tclk;
-        platform_device_register(&orion5x_wdt_device);
+        orion_wdt_init(orion5x_tclk);
 }
 
 
@@ -685,11 +276,6 @@ void __init orion5x_init(void)
         orion5x_id(&dev, &rev, &dev_name);
         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 
-        orion5x_eth_shared_data.t_clk = orion5x_tclk;
-        orion5x_spi_plat_data.tclk = orion5x_tclk;
-        orion5x_uart0_data[0].uartclk = orion5x_tclk;
-        orion5x_uart1_data[0].uartclk = orion5x_tclk;
-
         /*
          * Setup Orion address map
          */
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 42580757930..19cf5bf99f1 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -267,28 +267,28 @@ static struct platform_device d2net_gpio_buttons = {
  * General Setup
  ****************************************************************************/
 
-static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },       /* Board ID (bit 0) */
-        {  1, MPP_GPIO },       /* Board ID (bit 1) */
-        {  2, MPP_GPIO },       /* Board ID (bit 2) */
-        {  3, MPP_GPIO },       /* SATA 0 power */
-        {  4, MPP_UNUSED },
-        {  5, MPP_GPIO },       /* Fan fail detection */
-        {  6, MPP_GPIO },       /* Red front LED */
-        {  7, MPP_UNUSED },
-        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
-        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_GPIO },       /* SATA 1 power */
-        { 13, MPP_UNUSED },
-        { 14, MPP_SATA_LED },   /* SATA 0 active */
-        { 15, MPP_SATA_LED },   /* SATA 1 active */
-        { 16, MPP_GPIO },       /* Blue front LED blink control */
-        { 17, MPP_UNUSED },
-        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
-        { 19, MPP_UNUSED },
-        { -1 }
+static unsigned int d2net_mpp_modes[] __initdata = {
+        MPP0_GPIO,      /* Board ID (bit 0) */
+        MPP1_GPIO,      /* Board ID (bit 1) */
+        MPP2_GPIO,      /* Board ID (bit 2) */
+        MPP3_GPIO,      /* SATA 0 power */
+        MPP4_UNUSED,
+        MPP5_GPIO,      /* Fan fail detection */
+        MPP6_GPIO,      /* Red front LED */
+        MPP7_UNUSED,
+        MPP8_GPIO,      /* Rear power switch (on|auto) */
+        MPP9_GPIO,      /* Rear power switch (auto|off) */
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_GPIO,     /* SATA 1 power */
+        MPP13_UNUSED,
+        MPP14_SATA_LED, /* SATA 0 active */
+        MPP15_SATA_LED, /* SATA 1 active */
+        MPP16_GPIO,     /* Blue front LED blink control */
+        MPP17_UNUSED,
+        MPP18_GPIO,     /* Front button (0 = Released, 1 = Pushed ) */
+        MPP19_UNUSED,
+        0,
         /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
         /* 23: Blue front LED off */
         /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index b7d4591214e..f95d3cb01cb 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -298,28 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* USB Over Current */
-        {  1, MPP_GPIO },               /* USB Vbat input */
-        {  2, MPP_PCI_ARB },            /* PCI_REQn[2] */
-        {  3, MPP_PCI_ARB },            /* PCI_GNTn[2] */
-        {  4, MPP_PCI_ARB },            /* PCI_REQn[3] */
-        {  5, MPP_PCI_ARB },            /* PCI_GNTn[3] */
-        {  6, MPP_GPIO },               /* JP0, CON17.2 */
-        {  7, MPP_GPIO },               /* JP1, CON17.1 */
-        {  8, MPP_GPIO },               /* JP2, CON11.2 */
-        {  9, MPP_GPIO },               /* JP3, CON11.3 */
-        { 10, MPP_GPIO },               /* RTC int */
-        { 11, MPP_GPIO },               /* Baud Rate Generator */
-        { 12, MPP_GPIO },               /* PCI int 1 */
-        { 13, MPP_GPIO },               /* PCI int 2 */
-        { 14, MPP_NAND },               /* NAND_REn[2] */
-        { 15, MPP_NAND },               /* NAND_WEn[2] */
-        { 16, MPP_UART },               /* UART1_RX */
-        { 17, MPP_UART },               /* UART1_TX */
-        { 18, MPP_UART },               /* UART1_CTSn */
-        { 19, MPP_UART },               /* UART1_RTSn */
-        { -1 },
+static unsigned int db88f5281_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* USB Over Current */
+        MPP1_GPIO,              /* USB Vbat input */
+        MPP2_PCI_ARB,           /* PCI_REQn[2] */
+        MPP3_PCI_ARB,           /* PCI_GNTn[2] */
+        MPP4_PCI_ARB,           /* PCI_REQn[3] */
+        MPP5_PCI_ARB,           /* PCI_GNTn[3] */
+        MPP6_GPIO,              /* JP0, CON17.2 */
+        MPP7_GPIO,              /* JP1, CON17.1 */
+        MPP8_GPIO,              /* JP2, CON11.2 */
+        MPP9_GPIO,              /* JP3, CON11.3 */
+        MPP10_GPIO,             /* RTC int */
+        MPP11_GPIO,             /* Baud Rate Generator */
+        MPP12_GPIO,             /* PCI int 1 */
+        MPP13_GPIO,             /* PCI int 2 */
+        MPP14_NAND,             /* NAND_REn[2] */
+        MPP15_NAND,             /* NAND_WEn[2] */
+        MPP16_UART,             /* UART1_RX */
+        MPP17_UART,             /* UART1_TX */
+        MPP18_UART,             /* UART1_CTSn */
+        MPP19_UART,             /* UART1_RTSn */
+        0,
 };
 
 static void __init db88f5281_init(void)
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 90ab022eabe..855e0e77d56 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -385,76 +385,76 @@ static struct mv_sata_platform_data dns323_sata_data = {
 /****************************************************************************
  * General Setup
  */
-static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
-        {  0, MPP_PCIE_RST_OUTn },
-        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
-        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
-        {  3, MPP_UNUSED },
-        {  4, MPP_GPIO },               /* power button LED */
-        {  5, MPP_GPIO },               /* power button LED */
-        {  6, MPP_GPIO },               /* GMT G751-2f overtemp */
-        {  7, MPP_GPIO },               /* M41T80 nIRQ/OUT/SQW */
-        {  8, MPP_GPIO },               /* triggers power off */
-        {  9, MPP_GPIO },               /* power button switch */
-        { 10, MPP_GPIO },               /* reset button switch */
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_UNUSED },
-        { 15, MPP_UNUSED },
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int dns323a_mpp_modes[] __initdata = {
+        MPP0_PCIE_RST_OUTn,
+        MPP1_GPIO,              /* right amber LED (sata ch0) */
+        MPP2_GPIO,              /* left amber LED (sata ch1) */
+        MPP3_UNUSED,
+        MPP4_GPIO,              /* power button LED */
+        MPP5_GPIO,              /* power button LED */
+        MPP6_GPIO,              /* GMT G751-2f overtemp */
+        MPP7_GPIO,              /* M41T80 nIRQ/OUT/SQW */
+        MPP8_GPIO,              /* triggers power off */
+        MPP9_GPIO,              /* power button switch */
+        MPP10_GPIO,             /* reset button switch */
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_UNUSED,
+        MPP15_UNUSED,
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
-static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
-        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
-        {  3, MPP_GPIO },               /* system up flag */
-        {  4, MPP_GPIO },               /* power button LED */
-        {  5, MPP_GPIO },               /* power button LED */
-        {  6, MPP_GPIO },               /* GMT G751-2f overtemp */
-        {  7, MPP_GPIO },               /* M41T80 nIRQ/OUT/SQW */
-        {  8, MPP_GPIO },               /* triggers power off */
-        {  9, MPP_GPIO },               /* power button switch */
-        { 10, MPP_GPIO },               /* reset button switch */
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },
-        { 13, MPP_SATA_LED },
-        { 14, MPP_SATA_LED },
-        { 15, MPP_SATA_LED },
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int dns323b_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_GPIO,              /* right amber LED (sata ch0) */
+        MPP2_GPIO,              /* left amber LED (sata ch1) */
+        MPP3_GPIO,              /* system up flag */
+        MPP4_GPIO,              /* power button LED */
+        MPP5_GPIO,              /* power button LED */
+        MPP6_GPIO,              /* GMT G751-2f overtemp */
+        MPP7_GPIO,              /* M41T80 nIRQ/OUT/SQW */
+        MPP8_GPIO,              /* triggers power off */
+        MPP9_GPIO,              /* power button switch */
+        MPP10_GPIO,             /* reset button switch */
+        MPP11_UNUSED,
+        MPP12_SATA_LED,
+        MPP13_SATA_LED,
+        MPP14_SATA_LED,
+        MPP15_SATA_LED,
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
-static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* ? input */
-        {  1, MPP_GPIO },               /* input power switch (0 = pressed) */
-        {  2, MPP_GPIO },               /* output power off */
-        {  3, MPP_UNUSED },             /* ? output */
-        {  4, MPP_UNUSED },             /* ? output */
-        {  5, MPP_UNUSED },             /* ? output */
-        {  6, MPP_UNUSED },             /* ? output */
-        {  7, MPP_UNUSED },             /* ? output */
-        {  8, MPP_GPIO },               /* i/o right amber LED */
-        {  9, MPP_GPIO },               /* i/o left amber LED */
-        { 10, MPP_GPIO },               /* input */
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },
-        { 13, MPP_SATA_LED },
-        { 14, MPP_SATA_LED },
-        { 15, MPP_SATA_LED },
-        { 16, MPP_UNUSED },
-        { 17, MPP_GPIO },               /* power button LED */
-        { 18, MPP_GPIO },               /* fan speed bit 0 */
-        { 19, MPP_GPIO },               /* fan speed bit 1 */
-        { -1 },
+static unsigned int dns323c_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* ? input */
+        MPP1_GPIO,              /* input power switch (0 = pressed) */
+        MPP2_GPIO,              /* output power off */
+        MPP3_UNUSED,            /* ? output */
+        MPP4_UNUSED,            /* ? output */
+        MPP5_UNUSED,            /* ? output */
+        MPP6_UNUSED,            /* ? output */
+        MPP7_UNUSED,            /* ? output */
+        MPP8_GPIO,              /* i/o right amber LED */
+        MPP9_GPIO,              /* i/o left amber LED */
+        MPP10_GPIO,             /* input */
+        MPP11_UNUSED,
+        MPP12_SATA_LED,
+        MPP13_SATA_LED,
+        MPP14_SATA_LED,
+        MPP15_SATA_LED,
+        MPP16_UNUSED,
+        MPP17_GPIO,             /* power button LED */
+        MPP18_GPIO,             /* fan speed bit 0 */
+        MPP19_GPIO,             /* fan speed bit 1 */
+        0,
 };
 
 /* Rev C1 Fan speed notes:
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index d037a90c216..b67cff0d4cf 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -180,31 +180,31 @@ static struct platform_device edmini_v2_gpio_buttons = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_UNUSED },
-        {  2, MPP_UNUSED },
-        {  3, MPP_GPIO },       /* RTC interrupt */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_UNUSED },
-        {  7, MPP_UNUSED },
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },   /* SATA 0 presence */
-        { 13, MPP_SATA_LED },   /* SATA 1 presence */
-        { 14, MPP_SATA_LED },   /* SATA 0 active */
-        { 15, MPP_SATA_LED },   /* SATA 1 active */
+static unsigned int edminiv2_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_UNUSED,
+        MPP2_UNUSED,
+        MPP3_GPIO,      /* RTC interrupt */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_UNUSED,
+        MPP7_UNUSED,
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED, /* SATA 0 presence */
+        MPP13_SATA_LED, /* SATA 1 presence */
+        MPP14_SATA_LED, /* SATA 0 active */
+        MPP15_SATA_LED, /* SATA 1 active */
         /* 16: Power LED control (0 = On, 1 = Off) */
-        { 16, MPP_GPIO },
+        MPP16_GPIO,
         /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
-        { 17, MPP_GPIO },
+        MPP17_GPIO,
         /* 18: Power button status (0 = Released, 1 = Pressed) */
-        { 18, MPP_GPIO },
-        { 19, MPP_UNUSED },
-        { -1 }
+        MPP18_GPIO,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init edmini_v2_init(void)
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 47497c76162..c0eb6462633 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -315,28 +315,28 @@ static void kurobox_pro_power_off(void)
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_UNUSED },
-        {  2, MPP_GPIO },               /* GPIO Micon */
-        {  3, MPP_GPIO },               /* GPIO Rtc */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_NAND },               /* NAND Flash REn */
-        {  7, MPP_NAND },               /* NAND Flash WEn */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_UART },               /* UART1 CTSn */
-        { 19, MPP_UART },               /* UART1 RTSn */
-        { -1 },
+static unsigned int kurobox_pro_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_UNUSED,
+        MPP2_GPIO,              /* GPIO Micon */
+        MPP3_GPIO,              /* GPIO Rtc */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_NAND,              /* NAND Flash REn */
+        MPP7_NAND,              /* NAND Flash WEn */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_UART,             /* UART1 CTSn */
+        MPP19_UART,             /* UART1 RTSn */
+        0,
 };
 
 static void __init kurobox_pro_init(void)
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6ae12aa6d75..5065803ca82 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -251,28 +251,28 @@ static struct platform_device lschl_fan_device = {
  * GPIO Data
  ****************************************************************************/
 
-static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO }, /* LED POWER */
-        {  1, MPP_GPIO }, /* HDD POWER */
-        {  2, MPP_GPIO }, /* LED ALARM */
-        {  3, MPP_GPIO }, /* LED INFO */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_GPIO }, /* FAN LOCK */
-        {  7, MPP_GPIO }, /* SW INIT */
-        {  8, MPP_GPIO }, /* SW POWER */
-        {  9, MPP_GPIO }, /* USB POWER */
-        { 10, MPP_GPIO }, /* SW AUTO POWER */
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_GPIO }, /* FAN HIGH */
-        { 15, MPP_GPIO }, /* SW FUNC */
-        { 16, MPP_GPIO }, /* FAN LOW */
-        { 17, MPP_GPIO }, /* LED FUNC */
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int lschl_mpp_modes[] __initdata = {
+        MPP0_GPIO, /* LED POWER */
+        MPP1_GPIO, /* HDD POWER */
+        MPP2_GPIO, /* LED ALARM */
+        MPP3_GPIO, /* LED INFO */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_GPIO, /* FAN LOCK */
+        MPP7_GPIO, /* SW INIT */
+        MPP8_GPIO, /* SW POWER */
+        MPP9_GPIO, /* USB POWER */
+        MPP10_GPIO, /* SW AUTO POWER */
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_GPIO, /* FAN HIGH */
+        MPP15_GPIO, /* SW FUNC */
+        MPP16_GPIO, /* FAN LOW */
+        MPP17_GPIO, /* LED FUNC */
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init lschl_init(void)
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 7adafd79cf9..8503d0a42d4 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -200,28 +200,28 @@ static void ls_hgl_power_off(void)
 
 #define LS_HGL_GPIO_HDD_POWER   1
 
-static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO }, /* LED_PWR */
-        {  1, MPP_GPIO }, /* HDD_PWR */
-        {  2, MPP_GPIO }, /* LED_ALARM */
-        {  3, MPP_GPIO }, /* LED_INFO */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_GPIO }, /* FAN_LCK */
-        {  7, MPP_GPIO }, /* INIT */
-        {  8, MPP_GPIO }, /* POWER */
-        {  9, MPP_GPIO }, /* USB_PWR */
-        { 10, MPP_GPIO }, /* AUTO_POWER */
-        { 11, MPP_UNUSED }, /* LED_ETH (dummy) */
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_UNUSED },
-        { 15, MPP_GPIO }, /* FUNC */
-        { 16, MPP_UNUSED },
-        { 17, MPP_GPIO }, /* LED_FUNC */
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int ls_hgl_mpp_modes[] __initdata = {
+        MPP0_GPIO, /* LED_PWR */
+        MPP1_GPIO, /* HDD_PWR */
+        MPP2_GPIO, /* LED_ALARM */
+        MPP3_GPIO, /* LED_INFO */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_GPIO, /* FAN_LCK */
+        MPP7_GPIO, /* INIT */
+        MPP8_GPIO, /* POWER */
+        MPP9_GPIO, /* USB_PWR */
+        MPP10_GPIO, /* AUTO_POWER */
+        MPP11_UNUSED, /* LED_ETH (dummy) */
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_UNUSED,
+        MPP15_GPIO, /* FUNC */
+        MPP16_UNUSED,
+        MPP17_GPIO, /* LED_FUNC */
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init ls_hgl_init(void)
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 869958f5c39..9c82723c05c 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -201,28 +201,28 @@ static void lsmini_power_off(void)
 #define LSMINI_GPIO_HDD_POWER0  1
 #define LSMINI_GPIO_HDD_POWER1  19
 
-static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */
-        {  1, MPP_GPIO }, /* HDD_PWR */
-        {  2, MPP_GPIO }, /* LED_ALARM */
-        {  3, MPP_GPIO }, /* LED_INFO */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_UNUSED },
-        {  7, MPP_UNUSED },
-        {  8, MPP_UNUSED },
-        {  9, MPP_GPIO }, /* LED_FUNC */
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED }, /* LED_ETH (dummy) */
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_GPIO }, /* LED_PWR */
-        { 15, MPP_GPIO }, /* FUNC */
-        { 16, MPP_GPIO }, /* USB_PWR */
-        { 17, MPP_GPIO }, /* AUTO_POWER */
-        { 18, MPP_GPIO }, /* POWER */
-        { 19, MPP_GPIO }, /* HDD_PWR1 */
-        { -1 },
+static unsigned int lsmini_mpp_modes[] __initdata = {
+        MPP0_UNUSED, /* LED_RESERVE1 (unused) */
+        MPP1_GPIO, /* HDD_PWR */
+        MPP2_GPIO, /* LED_ALARM */
+        MPP3_GPIO, /* LED_INFO */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_UNUSED,
+        MPP7_UNUSED,
+        MPP8_UNUSED,
+        MPP9_GPIO, /* LED_FUNC */
+        MPP10_UNUSED,
+        MPP11_UNUSED, /* LED_ETH (dummy) */
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_GPIO, /* LED_PWR */
+        MPP15_GPIO, /* FUNC */
+        MPP16_GPIO, /* USB_PWR */
+        MPP17_GPIO, /* AUTO_POWER */
+        MPP18_GPIO, /* POWER */
+        MPP19_GPIO, /* HDD_PWR1 */
+        0,
 };
 
 static void __init lsmini_init(void)
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 2288207726e..f12c41b98d4 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -12,154 +12,34 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
-#include <asm/gpio.h>
 #include <mach/hardware.h>
-#include "common.h"
+#include <plat/mpp.h>
 #include "mpp.h"
+#include "common.h"
 
-static int is_5181l(void)
-{
-        u32 dev;
-        u32 rev;
-
-        orion5x_pcie_id(&dev, &rev);
-
-        return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
-}
-
-static int is_5182(void)
+static unsigned int __init orion5x_variant(void)
 {
         u32 dev;
         u32 rev;
 
         orion5x_pcie_id(&dev, &rev);
 
-        return !!(dev == MV88F5182_DEV_ID);
-}
+        if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0)
+                return MPP_F5181_MASK;
 
-static int is_5281(void)
-{
-        u32 dev;
-        u32 rev;
+        if (dev == MV88F5182_DEV_ID)
+                return MPP_F5182_MASK;
 
-        orion5x_pcie_id(&dev, &rev);
+        if (dev == MV88F5281_DEV_ID)
+                return MPP_F5281_MASK;
 
-        return !!(dev == MV88F5281_DEV_ID);
+        printk(KERN_ERR "MPP setup: unknown orion5x variant "
+               "(dev %#x rev %#x)\n", dev, rev);
+        return 0;
 }
 
-static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
+void __init orion5x_mpp_conf(unsigned int *mpp_list)
 {
-        switch (type) {
-        case MPP_UNUSED:
-        case MPP_GPIO:
-                if (mpp == 0)
-                        return 3;
-                if (mpp >= 1 && mpp <= 15)
-                        return 0;
-                if (mpp >= 16 && mpp <= 19) {
-                        if (is_5182())
-                                return 5;
-                        if (type == MPP_UNUSED)
-                                return 0;
-                }
-                return -1;
-
-        case MPP_PCIE_RST_OUTn:
-                if (mpp == 0)
-                        return 0;
-                return -1;
-
-        case MPP_PCI_ARB:
-                if (mpp >= 0 && mpp <= 7)
-                        return 2;
-                return -1;
-
-        case MPP_PCI_PMEn:
-                if (mpp == 2)
-                        return 3;
-                return -1;
-
-        case MPP_GIGE:
-                if (mpp >= 8 && mpp <= 19)
-                        return 1;
-                return -1;
-
-        case MPP_NAND:
-                if (is_5182() || is_5281()) {
-                        if (mpp >= 4 && mpp <= 7)
-                                return 4;
-                        if (mpp >= 12 && mpp <= 17)
-                                return 4;
-                }
-                return -1;
-
-        case MPP_PCI_CLK:
-                if (is_5181l() && mpp >= 6 && mpp <= 7)
-                        return 5;
-                return -1;
-
-        case MPP_SATA_LED:
-                if (is_5182()) {
-                        if (mpp >= 4 && mpp <= 7)
-                                return 5;
-                        if (mpp >= 12 && mpp <= 15)
-                                return 5;
-                }
-                return -1;
-
-        case MPP_UART:
-                if (mpp >= 16 && mpp <= 19)
-                        return 0;
-                return -1;
-        }
-
-        printk(KERN_INFO "unknown MPP type %d\n", type);
-
-        return -1;
-}
-
-void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
-{
-        u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
-        u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
-        u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
-
-        for ( ; mode->mpp >= 0; mode++) {
-                u32 *reg;
-                int num_type;
-                int shift;
-
-                if (mode->mpp >= 0 && mode->mpp <= 7)
-                        reg = &mpp_0_7_ctrl;
-                else if (mode->mpp >= 8 && mode->mpp <= 15)
-                        reg = &mpp_8_15_ctrl;
-                else if (mode->mpp >= 16 && mode->mpp <= 19)
-                        reg = &mpp_16_19_ctrl;
-                else {
-                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
-                                        "(%d)\n", mode->mpp);
-                        continue;
-                }
-
-                num_type = determine_type_encoding(mode->mpp, mode->type);
-                if (num_type < 0) {
-                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
-                                        "combination (%d, %d)\n", mode->mpp,
-                                        mode->type);
-                        continue;
-                }
-
-                shift = (mode->mpp & 7) << 2;
-                *reg &= ~(0xf << shift);
-                *reg |= (num_type & 0xf) << shift;
-
-                if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182()))
-                        orion_gpio_set_unused(mode->mpp);
-
-                orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
-        }
-
-        writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
-        writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
-        writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
+        orion_mpp_conf(mpp_list, orion5x_variant(),
+                       MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
 }
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index 290e610dc01..eac68978a2c 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -1,74 +1,129 @@
 #ifndef __ARCH_ORION5X_MPP_H
 #define __ARCH_ORION5X_MPP_H
 
-enum orion5x_mpp_type {
-        /*
-         * This MPP is unused.
-         */
-        MPP_UNUSED,
-
-        /*
-         * This MPP pin is used as a generic GPIO pin.  Valid for
-         * MPPs 0-15 and device bus data pins 16-31.  On 5182, also
-         * valid for MPPs 16-19.
-         */
-        MPP_GPIO,
-
-        /*
-         * This MPP is used as PCIe_RST_OUTn pin.  Valid for
-         * MPP 0 only.
-         */
-        MPP_PCIE_RST_OUTn,
-
-        /*
-         * This MPP is used as PCI arbiter pin (REQn/GNTn).
-         * Valid for MPPs 0-7 only.
-         */
-        MPP_PCI_ARB,
-
-        /*
-         * This MPP is used as PCI_PMEn pin.  Valid for MPP 2 only.
-         */
-        MPP_PCI_PMEn,
-
-        /*
-         * This MPP is used as GigE half-duplex (COL, CRS) or GMII
-         * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin.  Valid for
-         * MPPs 8-19 only.
-         */
-        MPP_GIGE,
-
-        /*
-         * This MPP is used as NAND REn/WEn pin.  Valid for MPPs
-         * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
-         */
-        MPP_NAND,
-
-        /*
-         * This MPP is used as a PCI clock output pin.  Valid for
-         * MPPs 6-7 only, and only on the 5181l.
-         */
-        MPP_PCI_CLK,
-
-        /*
-         * This MPP is used as a SATA presence/activity LED.
-         * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
-         */
-        MPP_SATA_LED,
-
-        /*
-         * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
-         * Valid for MPPs 16-19 only.
-         */
-        MPP_UART,
-};
-
-struct orion5x_mpp_mode {
-        int                     mpp;
-        enum orion5x_mpp_type   type;
-};
-
-void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
+#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
+        /* MPP number */                ((_num) & 0xff) | \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
+        /* may be input signal */       ((!!(_in)) << 12) | \
+        /* may be output signal */      ((!!(_out)) << 13) | \
+        /* available on F5181l */       ((!!(_F5181l)) << 14) | \
+        /* available on F5182 */        ((!!(_F5182)) << 15) | \
+        /* available on F5281 */        ((!!(_F5281)) << 16))
 
+                                /* num sel  i  o  5181 5182 5281 */
+
+#define MPP_F5181_MASK          MPP(0,  0x0, 0, 0, 1,   0,   0)
+#define MPP_F5182_MASK          MPP(0,  0x0, 0, 0, 0,   1,   0)
+#define MPP_F5281_MASK          MPP(0,  0x0, 0, 0, 0,   0,   1)
+
+#define MPP0_UNUSED             MPP(0,  0x3, 0, 0, 1,   1,   1)
+#define MPP0_GPIO               MPP(0,  0x3, 1, 1, 1,   1,   1)
+#define MPP0_PCIE_RST_OUTn      MPP(0,  0x0, 0, 0, 1,   1,   1)
+#define MPP0_PCI_ARB            MPP(0,  0x2, 0, 0, 1,   1,   1)
+
+#define MPP1_UNUSED             MPP(1,  0x0, 0, 0, 1,   1,   1)
+#define MPP1_GPIO               MPP(1,  0x0, 1, 1, 1,   1,   1)
+#define MPP1_PCI_ARB            MPP(1,  0x2, 0, 0, 1,   1,   1)
+
+#define MPP2_UNUSED             MPP(2,  0x0, 0, 0, 1,   1,   1)
+#define MPP2_GPIO               MPP(2,  0x0, 1, 1, 1,   1,   1)
+#define MPP2_PCI_ARB            MPP(2,  0x2, 0, 0, 1,   1,   1)
+#define MPP2_PCI_PMEn           MPP(2,  0x3, 0, 0, 1,   1,   1)
+
+#define MPP3_UNUSED             MPP(3,  0x0, 0, 0, 1,   1,   1)
+#define MPP3_GPIO               MPP(3,  0x0, 1, 1, 1,   1,   1)
+#define MPP3_PCI_ARB            MPP(3,  0x2, 0, 0, 1,   1,   1)
+
+#define MPP4_UNUSED             MPP(4,  0x0, 0, 0, 1,   1,   1)
+#define MPP4_GPIO               MPP(4,  0x0, 1, 1, 1,   1,   1)
+#define MPP4_PCI_ARB            MPP(4,  0x2, 0, 0, 1,   1,   1)
+#define MPP4_NAND               MPP(4,  0x4, 0, 0, 0,   1,   1)
+#define MPP4_SATA_LED           MPP(4,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP5_UNUSED             MPP(5,  0x0, 0, 0, 1,   1,   1)
+#define MPP5_GPIO               MPP(5,  0x0, 1, 1, 1,   1,   1)
+#define MPP5_PCI_ARB            MPP(5,  0x2, 0, 0, 1,   1,   1)
+#define MPP5_NAND               MPP(5,  0x4, 0, 0, 0,   1,   1)
+#define MPP5_SATA_LED           MPP(5,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP6_UNUSED             MPP(6,  0x0, 0, 0, 1,   1,   1)
+#define MPP6_GPIO               MPP(6,  0x0, 1, 1, 1,   1,   1)
+#define MPP6_PCI_ARB            MPP(6,  0x2, 0, 0, 1,   1,   1)
+#define MPP6_NAND               MPP(6,  0x4, 0, 0, 0,   1,   1)
+#define MPP6_PCI_CLK            MPP(6,  0x5, 0, 0, 1,   0,   0)
+#define MPP6_SATA_LED           MPP(6,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP7_UNUSED             MPP(7,  0x0, 0, 0, 1,   1,   1)
+#define MPP7_GPIO               MPP(7,  0x0, 1, 1, 1,   1,   1)
+#define MPP7_PCI_ARB            MPP(7,  0x2, 0, 0, 1,   1,   1)
+#define MPP7_NAND               MPP(7,  0x4, 0, 0, 0,   1,   1)
+#define MPP7_PCI_CLK            MPP(7,  0x5, 0, 0, 1,   0,   0)
+#define MPP7_SATA_LED           MPP(7,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP8_UNUSED             MPP(8,  0x0, 0, 0, 1,   1,   1)
+#define MPP8_GPIO               MPP(8,  0x0, 1, 1, 1,   1,   1)
+#define MPP8_GIGE               MPP(8,  0x1, 0, 0, 1,   1,   1)
+
+#define MPP9_UNUSED             MPP(9,  0x0, 0, 0, 1,   1,   1)
+#define MPP9_GPIO               MPP(9,  0x0, 0, 0, 1,   1,   1)
+#define MPP9_GIGE               MPP(9,  0x1, 1, 1, 1,   1,   1)
+
+#define MPP10_UNUSED            MPP(10, 0x0, 0, 0, 1,   1,   1)
+#define MPP10_GPIO              MPP(10, 0x0, 1, 1, 1,   1,   1)
+#define MPP10_GIGE              MPP(10, 0x1, 0, 0, 1,   1,   1)
+
+#define MPP11_UNUSED            MPP(11, 0x0, 0, 0, 1,   1,   1)
+#define MPP11_GPIO              MPP(11, 0x0, 1, 1, 1,   1,   1)
+#define MPP11_GIGE              MPP(11, 0x1, 0, 0, 1,   1,   1)
+
+#define MPP12_UNUSED            MPP(12, 0x0, 0, 0, 1,   1,   1)
+#define MPP12_GPIO              MPP(12, 0x0, 1, 1, 1,   1,   1)
+#define MPP12_GIGE              MPP(12, 0x1, 0, 0, 1,   1,   1)
+#define MPP12_NAND              MPP(12, 0x4, 0, 0, 0,   1,   1)
+#define MPP12_SATA_LED          MPP(12, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP13_UNUSED            MPP(13, 0x0, 0, 0, 1,   1,   1)
+#define MPP13_GPIO              MPP(13, 0x0, 1, 1, 1,   1,   1)
+#define MPP13_GIGE              MPP(13, 0x1, 0, 0, 1,   1,   1)
+#define MPP13_NAND              MPP(13, 0x4, 0, 0, 0,   1,   1)
+#define MPP13_SATA_LED          MPP(13, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP14_UNUSED            MPP(14, 0x0, 0, 0, 1,   1,   1)
+#define MPP14_GPIO              MPP(14, 0x0, 1, 1, 1,   1,   1)
+#define MPP14_GIGE              MPP(14, 0x1, 0, 0, 1,   1,   1)
+#define MPP14_NAND              MPP(14, 0x4, 0, 0, 0,   1,   1)
+#define MPP14_SATA_LED          MPP(14, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP15_UNUSED            MPP(15, 0x0, 0, 0, 1,   1,   1)
+#define MPP15_GPIO              MPP(15, 0x0, 1, 1, 1,   1,   1)
+#define MPP15_GIGE              MPP(15, 0x1, 0, 0, 1,   1,   1)
+#define MPP15_NAND              MPP(15, 0x4, 0, 0, 0,   1,   1)
+#define MPP15_SATA_LED          MPP(15, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP16_UNUSED            MPP(16, 0x0, 0, 0, 1,   1,   1)
+#define MPP16_GPIO              MPP(16, 0x5, 1, 1, 0,   1,   0)
+#define MPP16_GIGE              MPP(16, 0x1, 0, 0, 1,   1,   1)
+#define MPP16_NAND              MPP(16, 0x4, 0, 0, 0,   1,   1)
+#define MPP16_UART              MPP(16, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP17_UNUSED            MPP(17, 0x0, 0, 0, 1,   1,   1)
+#define MPP17_GPIO              MPP(17, 0x5, 1, 1, 0,   1,   0)
+#define MPP17_GIGE              MPP(17, 0x1, 0, 0, 1,   1,   1)
+#define MPP17_NAND              MPP(17, 0x4, 0, 0, 0,   1,   1)
+#define MPP17_UART              MPP(17, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP18_UNUSED            MPP(18, 0x0, 0, 0, 1,   1,   1)
+#define MPP18_GPIO              MPP(18, 0x5, 1, 1, 0,   1,   0)
+#define MPP18_GIGE              MPP(18, 0x1, 0, 0, 1,   1,   1)
+#define MPP18_UART              MPP(18, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP19_UNUSED            MPP(19, 0x0, 0, 0, 1,   1,   1)
+#define MPP19_GPIO              MPP(19, 0x5, 1, 1, 0,   1,   0)
+#define MPP19_GIGE              MPP(19, 0x1, 0, 0, 1,   1,   1)
+#define MPP19_UART              MPP(19, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP_MAX                 19
+
+void orion5x_mpp_conf(unsigned int *mpp_list);
 
 #endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index b43b208153c..59263b73d1e 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -193,28 +193,28 @@ static void mss2_power_off(void)
 /****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Power LED */
-        {  1, MPP_GPIO },               /* Error LED */
-        {  2, MPP_UNUSED },
-        {  3, MPP_GPIO },               /* RTC interrupt */
-        {  4, MPP_GPIO },               /* HDD ind. (Single/Dual)*/
-        {  5, MPP_GPIO },               /* HD0 5V control */
-        {  6, MPP_GPIO },               /* HD0 12V control */
-        {  7, MPP_GPIO },               /* HD1 5V control */
-        {  8, MPP_GPIO },               /* HD1 12V control */
-        {  9, MPP_UNUSED },
-        { 10, MPP_GPIO },               /* Fan control */
-        { 11, MPP_GPIO },               /* Power button */
-        { 12, MPP_GPIO },               /* Reset button */
-        { 13, MPP_UNUSED },
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int mss2_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Power LED */
+        MPP1_GPIO,              /* Error LED */
+        MPP2_UNUSED,
+        MPP3_GPIO,              /* RTC interrupt */
+        MPP4_GPIO,              /* HDD ind. (Single/Dual)*/
+        MPP5_GPIO,              /* HD0 5V control */
+        MPP6_GPIO,              /* HD0 12V control */
+        MPP7_GPIO,              /* HD1 5V control */
+        MPP8_GPIO,              /* HD1 12V control */
+        MPP9_UNUSED,
+        MPP10_GPIO,             /* Fan control */
+        MPP11_GPIO,             /* Power button */
+        MPP12_GPIO,             /* Reset button */
+        MPP13_UNUSED,
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init mss2_init(void)
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index c55d071707f..63ff10c3c46 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -108,28 +108,28 @@ static struct platform_device mv2120_button_device = {
 /****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Sys status LED */
-        {  1, MPP_GPIO },               /* Sys error LED */
-        {  2, MPP_GPIO },               /* OverTemp interrupt */
-        {  3, MPP_GPIO },               /* RTC interrupt */
-        {  4, MPP_GPIO },               /* V_LED 5V */
-        {  5, MPP_GPIO },               /* V_LED 3.3V */
-        {  6, MPP_UNUSED },
-        {  7, MPP_UNUSED },
-        {  8, MPP_GPIO },               /* SATA 0 fail LED */
-        {  9, MPP_GPIO },               /* SATA 1 fail LED */
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UNUSED },
-        { 17, MPP_GPIO },               /* Reset button */
-        { 18, MPP_GPIO },               /* Power button */
-        { 19, MPP_GPIO },               /* Power off */
-        { -1 },
+static unsigned int mv2120_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Sys status LED */
+        MPP1_GPIO,              /* Sys error LED */
+        MPP2_GPIO,              /* OverTemp interrupt */
+        MPP3_GPIO,              /* RTC interrupt */
+        MPP4_GPIO,              /* V_LED 5V */
+        MPP5_GPIO,              /* V_LED 3.3V */
+        MPP6_UNUSED,
+        MPP7_UNUSED,
+        MPP8_GPIO,              /* SATA 0 fail LED */
+        MPP9_GPIO,              /* SATA 1 fail LED */
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UNUSED,
+        MPP17_GPIO,             /* Reset button */
+        MPP18_GPIO,             /* Power button */
+        MPP19_GPIO,             /* Power off */
+        0,
 };
 
 static struct i2c_board_info __initdata mv2120_i2c_rtc = {
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 429ecafe9fd..e43b39cc7fe 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -190,7 +190,7 @@ err_free_1:
  * The power front LEDs (blue and red) and SATA red LEDs are controlled via a
  * single GPIO line and are compatible with the leds-gpio driver.
  *
- * The SATA blue LEDs have some hardware blink capabilities which are detailled
+ * The SATA blue LEDs have some hardware blink capabilities which are detailed
  * in the following array:
  *
  * SATAx blue LED | SATAx activity | LED state
@@ -339,28 +339,28 @@ static struct platform_device net2big_gpio_buttons = {
  * General Setup
  ****************************************************************************/
 
-static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },       /* Raid mode (bit 0) */
-        {  1, MPP_GPIO },       /* USB port 2 fuse (0 = Fail, 1 = Ok) */
-        {  2, MPP_GPIO },       /* Raid mode (bit 1) */
-        {  3, MPP_GPIO },       /* Board ID (bit 0) */
-        {  4, MPP_GPIO },       /* Fan activity (0 = Off, 1 = On) */
-        {  5, MPP_GPIO },       /* Fan fail detection */
-        {  6, MPP_GPIO },       /* Red front LED (0 = Off, 1 = On) */
-        {  7, MPP_GPIO },       /* Disable initial blinking on front LED */
-        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
-        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
-        { 10, MPP_GPIO },       /* SATA 1 red LED (0 = Off, 1 = On) */
-        { 11, MPP_GPIO },       /* SATA 0 red LED (0 = Off, 1 = On) */
-        { 12, MPP_GPIO },       /* Board ID (bit 1) */
-        { 13, MPP_GPIO },       /* SATA 1 blue LED blink control */
-        { 14, MPP_SATA_LED },
-        { 15, MPP_SATA_LED },
-        { 16, MPP_GPIO },       /* Blue front LED control */
-        { 17, MPP_GPIO },       /* SATA 0 blue LED blink control */
-        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
-        { 19, MPP_GPIO },       /* SATA{0,1} power On/Off request */
-        { -1 }
+static unsigned int net2big_mpp_modes[] __initdata = {
+        MPP0_GPIO,      /* Raid mode (bit 0) */
+        MPP1_GPIO,      /* USB port 2 fuse (0 = Fail, 1 = Ok) */
+        MPP2_GPIO,      /* Raid mode (bit 1) */
+        MPP3_GPIO,      /* Board ID (bit 0) */
+        MPP4_GPIO,      /* Fan activity (0 = Off, 1 = On) */
+        MPP5_GPIO,      /* Fan fail detection */
+        MPP6_GPIO,      /* Red front LED (0 = Off, 1 = On) */
+        MPP7_GPIO,      /* Disable initial blinking on front LED */
+        MPP8_GPIO,      /* Rear power switch (on|auto) */
+        MPP9_GPIO,      /* Rear power switch (auto|off) */
+        MPP10_GPIO,     /* SATA 1 red LED (0 = Off, 1 = On) */
+        MPP11_GPIO,     /* SATA 0 red LED (0 = Off, 1 = On) */
+        MPP12_GPIO,     /* Board ID (bit 1) */
+        MPP13_GPIO,     /* SATA 1 blue LED blink control */
+        MPP14_SATA_LED,
+        MPP15_SATA_LED,
+        MPP16_GPIO,     /* Blue front LED control */
+        MPP17_GPIO,     /* SATA 0 blue LED blink control */
+        MPP18_GPIO,     /* Front button (0 = Released, 1 = Pushed ) */
+        MPP19_GPIO,     /* SATA{0,1} power On/Off request */
+        0,
         /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
         /* 23: SATA 0 power status */
         /* 24: Board power off */
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 34310ab56e2..9eec7c2375e 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -64,28 +64,28 @@ static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* LED1 CardBus LED (front panel) */
-        {  1, MPP_GPIO },               /* PCI_intA */
-        {  2, MPP_GPIO },               /* Hard Reset / Factory Init*/
-        {  3, MPP_GPIO },               /* FXS or DAA select */
-        {  4, MPP_GPIO },               /* LED6 - phone LED (front panel) */
-        {  5, MPP_GPIO },               /* LED5 - phone LED (front panel) */
-        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
-        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
-        {  8, MPP_GPIO },               /* CardBus reset */
-        {  9, MPP_GPIO },               /* GE_RXERR */
-        { 10, MPP_GPIO },               /* LED2 MiniPCI LED (front panel) */
-        { 11, MPP_GPIO },               /* Lifeline control */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* LED1 CardBus LED (front panel) */
+        MPP1_GPIO,              /* PCI_intA */
+        MPP2_GPIO,              /* Hard Reset / Factory Init*/
+        MPP3_GPIO,              /* FXS or DAA select */
+        MPP4_GPIO,              /* LED6 - phone LED (front panel) */
+        MPP5_GPIO,              /* LED5 - phone LED (front panel) */
+        MPP6_PCI_CLK,           /* CPU PCI refclk */
+        MPP7_PCI_CLK,           /* PCI/PCIe refclk */
+        MPP8_GPIO,              /* CardBus reset */
+        MPP9_GPIO,              /* GE_RXERR */
+        MPP10_GPIO,             /* LED2 MiniPCI LED (front panel) */
+        MPP11_GPIO,             /* Lifeline control */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c1f79fa014e..0cc90bbfd32 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -65,28 +65,28 @@ static struct platform_device rd88f5181l_ge_nor_boot_flash = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* LED1 */
-        {  1, MPP_GPIO },               /* LED5 */
-        {  2, MPP_GPIO },               /* LED4 */
-        {  3, MPP_GPIO },               /* LED3 */
-        {  4, MPP_GPIO },               /* PCI_intA */
-        {  5, MPP_GPIO },               /* RTC interrupt */
-        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
-        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
-        {  8, MPP_GPIO },               /* 88e6131 interrupt */
-        {  9, MPP_GPIO },               /* GE_RXERR */
-        { 10, MPP_GPIO },               /* PCI_intB */
-        { 11, MPP_GPIO },               /* LED2 */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* LED1 */
+        MPP1_GPIO,              /* LED5 */
+        MPP2_GPIO,              /* LED4 */
+        MPP3_GPIO,              /* LED3 */
+        MPP4_GPIO,              /* PCI_intA */
+        MPP5_GPIO,              /* RTC interrupt */
+        MPP6_PCI_CLK,           /* CPU PCI refclk */
+        MPP7_PCI_CLK,           /* PCI/PCIe refclk */
+        MPP8_GPIO,              /* 88e6131 interrupt */
+        MPP9_GPIO,              /* GE_RXERR */
+        MPP10_GPIO,             /* PCI_intB */
+        MPP11_GPIO,             /* LED2 */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 4fc46772a08..48da39b9bdb 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -241,28 +241,28 @@ static struct mv_sata_platform_data rd88f5182_sata_data = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Debug Led */
-        {  1, MPP_GPIO },               /* Reset Switch */
-        {  2, MPP_UNUSED },
-        {  3, MPP_GPIO },               /* RTC Int */
-        {  4, MPP_GPIO },
-        {  5, MPP_GPIO },
-        {  6, MPP_GPIO },               /* PCI_intA */
-        {  7, MPP_GPIO },               /* PCI_intB */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int rd88f5182_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Debug Led */
+        MPP1_GPIO,              /* Reset Switch */
+        MPP2_UNUSED,
+        MPP3_GPIO,              /* RTC Int */
+        MPP4_GPIO,
+        MPP5_GPIO,
+        MPP6_GPIO,              /* PCI_intA */
+        MPP7_GPIO,              /* PCI_intB */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init rd88f5182_init(void)
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index b080c6966d1..ad2eba9286a 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -27,7 +27,6 @@
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
 #include "common.h"
-#include "mpp.h"
 
 static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
         .phy_addr       = -1,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 61600414391..29ce826c3c2 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -295,28 +295,28 @@ static void tsp2_power_off(void)
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = {
-        {  0, MPP_PCIE_RST_OUTn },
-        {  1, MPP_UNUSED },
-        {  2, MPP_UNUSED },
-        {  3, MPP_UNUSED },
-        {  4, MPP_NAND },               /* BOOT NAND Flash REn */
-        {  5, MPP_NAND },               /* BOOT NAND Flash WEn */
-        {  6, MPP_NAND },               /* BOOT NAND Flash HREn[0] */
-        {  7, MPP_NAND },               /* BOOT NAND Flash WEn[0] */
-        {  8, MPP_GPIO },               /* MICON int */
-        {  9, MPP_GPIO },               /* RTC int */
-        { 10, MPP_UNUSED },
-        { 11, MPP_GPIO },               /* PCI Int A */
-        { 12, MPP_UNUSED },
-        { 13, MPP_GPIO },               /* UPS on UART0 enable */
-        { 14, MPP_GPIO },               /* UPS low battery detection */
-        { 15, MPP_UNUSED },
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_UART },               /* UART1 CTSn */
-        { 19, MPP_UART },               /* UART1 RTSn */
-        { -1 },
+static unsigned int tsp2_mpp_modes[] __initdata = {
+        MPP0_PCIE_RST_OUTn,
+        MPP1_UNUSED,
+        MPP2_UNUSED,
+        MPP3_UNUSED,
+        MPP4_NAND,              /* BOOT NAND Flash REn */
+        MPP5_NAND,              /* BOOT NAND Flash WEn */
+        MPP6_NAND,              /* BOOT NAND Flash HREn[0] */
+        MPP7_NAND,              /* BOOT NAND Flash WEn[0] */
+        MPP8_GPIO,              /* MICON int */
+        MPP9_GPIO,              /* RTC int */
+        MPP10_UNUSED,
+        MPP11_GPIO,             /* PCI Int A */
+        MPP12_UNUSED,
+        MPP13_GPIO,             /* UPS on UART0 enable */
+        MPP14_GPIO,             /* UPS low battery detection */
+        MPP15_UNUSED,
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_UART,             /* UART1 CTSn */
+        MPP19_UART,             /* UART1 RTSn */
+        0,
 };
 
 static void __init tsp2_init(void)
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index f0f43e13ac8..47162fd5f04 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -36,7 +36,7 @@
 
 /****************************************************************************
  * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
- *     partitions on the device because we want to keep compatability with
+ *     partitions on the device because we want to keep compatibility with
  *     existing QNAP firmware.
  *
  * Layout as used by QNAP:
@@ -244,28 +244,28 @@ static struct mv_sata_platform_data qnap_ts209_sata_data = {
 
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_GPIO },               /* USB copy button */
-        {  2, MPP_GPIO },               /* Load defaults button */
-        {  3, MPP_GPIO },               /* GPIO RTC */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_GPIO },               /* PCI Int A */
-        {  7, MPP_GPIO },               /* PCI Int B */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_GPIO },               /* SW_RST */
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int ts209_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_GPIO,              /* USB copy button */
+        MPP2_GPIO,              /* Load defaults button */
+        MPP3_GPIO,              /* GPIO RTC */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_GPIO,              /* PCI Int A */
+        MPP7_GPIO,              /* PCI Int B */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_GPIO,             /* SW_RST */
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init qnap_ts209_init(void)
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 92f393f08fa..5aacc7ac5cf 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -56,7 +56,7 @@
 
 /****************************************************************************
  * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
- *     partitions on the device because we want to keep compatability with
+ *     partitions on the device because we want to keep compatibility with
  *     existing QNAP firmware.
  *
  * Layout as used by QNAP:
@@ -242,28 +242,28 @@ static struct platform_device qnap_ts409_button_device = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_UNUSED },
-        {  2, MPP_UNUSED },
-        {  3, MPP_UNUSED },
-        {  4, MPP_GPIO },               /* HDD 1 status */
-        {  5, MPP_GPIO },               /* HDD 2 status */
-        {  6, MPP_GPIO },               /* HDD 3 status */
-        {  7, MPP_GPIO },               /* HDD 4 status */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_GPIO },               /* RTC int */
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_GPIO },               /* SW_RST */
-        { 15, MPP_GPIO },               /* USB copy button */
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int ts409_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_UNUSED,
+        MPP2_UNUSED,
+        MPP3_UNUSED,
+        MPP4_GPIO,              /* HDD 1 status */
+        MPP5_GPIO,              /* HDD 2 status */
+        MPP6_GPIO,              /* HDD 3 status */
+        MPP7_GPIO,              /* HDD 4 status */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_GPIO,             /* RTC int */
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_GPIO,             /* SW_RST */
+        MPP15_GPIO,             /* USB copy button */
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init qnap_ts409_init(void)
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index edb1dd2d161..6b7b54116f3 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -557,27 +557,27 @@ static struct kobj_attribute ts78xx_fpga_attr =
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_GPIO },               /* JTAG Clock */
-        {  2, MPP_GPIO },               /* JTAG Data In */
-        {  3, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB2B */
-        {  4, MPP_GPIO },               /* JTAG Data Out */
-        {  5, MPP_GPIO },               /* JTAG TMS */
-        {  6, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
-        {  7, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB22B */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_UNUSED },
-        { 15, MPP_UNUSED },
-        { 16, MPP_UART },
-        { 17, MPP_UART },
-        { 18, MPP_UART },
-        { 19, MPP_UART },
+static unsigned int ts78xx_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_GPIO,              /* JTAG Clock */
+        MPP2_GPIO,              /* JTAG Data In */
+        MPP3_GPIO,              /* Lat ECP2 256 FPGA - PB2B */
+        MPP4_GPIO,              /* JTAG Data Out */
+        MPP5_GPIO,              /* JTAG TMS */
+        MPP6_GPIO,              /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
+        MPP7_GPIO,              /* Lat ECP2 256 FPGA - PB22B */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_UNUSED,
+        MPP15_UNUSED,
+        MPP16_UART,
+        MPP17_UART,
+        MPP18_UART,
+        MPP19_UART,
         /*
          * MPP[20] PCI Clock Out 1
          * MPP[21] PCI Clock Out 0
@@ -586,7 +586,7 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
          * MPP[24] Unused
          * MPP[25] Unused
          */
-        { -1 },
+        0,
 };
 
 static void __init ts78xx_init(void)
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 4e5216be074..444a1c7fdfd 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -24,28 +24,28 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Power LED green (0=on) */
-        {  1, MPP_GPIO },               /* Reset Button (0=off) */
-        {  2, MPP_GPIO },               /* Power LED blink (0=off) */
-        {  3, MPP_GPIO },               /* WAN Status LED amber (0=off) */
-        {  4, MPP_GPIO },               /* PCI int */
-        {  5, MPP_GPIO },               /* ??? */
-        {  6, MPP_GPIO },               /* ??? */
-        {  7, MPP_GPIO },               /* ??? */
-        {  8, MPP_UNUSED },             /* ??? */
-        {  9, MPP_GIGE },               /* GE_RXERR */
-        { 10, MPP_UNUSED },             /* ??? */
-        { 11, MPP_UNUSED },             /* ??? */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int wnr854t_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Power LED green (0=on) */
+        MPP1_GPIO,              /* Reset Button (0=off) */
+        MPP2_GPIO,              /* Power LED blink (0=off) */
+        MPP3_GPIO,              /* WAN Status LED amber (0=off) */
+        MPP4_GPIO,              /* PCI int */
+        MPP5_GPIO,              /* ??? */
+        MPP6_GPIO,              /* ??? */
+        MPP7_GPIO,              /* ??? */
+        MPP8_UNUSED,            /* ??? */
+        MPP9_GIGE,              /* GE_RXERR */
+        MPP10_UNUSED,           /* ??? */
+        MPP11_UNUSED,           /* ??? */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 /*
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fab79d09cc5..d1952be0ae1 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -101,28 +101,28 @@ static struct platform_device wrt350n_v2_button_device = {
 /*
  * General setup
  */
-static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Power LED green (0=on) */
-        {  1, MPP_GPIO },               /* Security LED (0=on) */
-        {  2, MPP_GPIO },               /* Internal Button (0=on) */
-        {  3, MPP_GPIO },               /* Reset Button (0=on) */
-        {  4, MPP_GPIO },               /* PCI int */
-        {  5, MPP_GPIO },               /* Power LED orange (0=on) */
-        {  6, MPP_GPIO },               /* USB LED (0=on) */
-        {  7, MPP_GPIO },               /* Wireless LED (0=on) */
-        {  8, MPP_UNUSED },             /* ??? */
-        {  9, MPP_GIGE },               /* GE_RXERR */
-        { 10, MPP_UNUSED },             /* ??? */
-        { 11, MPP_UNUSED },             /* ??? */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Power LED green (0=on) */
+        MPP1_GPIO,              /* Security LED (0=on) */
+        MPP2_GPIO,              /* Internal Button (0=on) */
+        MPP3_GPIO,              /* Reset Button (0=on) */
+        MPP4_GPIO,              /* PCI int */
+        MPP5_GPIO,              /* Power LED orange (0=on) */
+        MPP6_GPIO,              /* USB LED (0=on) */
+        MPP7_GPIO,              /* Wireless LED (0=on) */
+        MPP8_UNUSED,            /* ??? */
+        MPP9_GIGE,              /* GE_RXERR */
+        MPP10_UNUSED,           /* ??? */
+        MPP11_UNUSED,           /* ??? */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 /*
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 6de0ad0eea6..9cdcca59792 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -711,7 +711,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = {
 static struct regulator_init_data bq24022_init_data = {
         .constraints = {
                 .max_uA         = 500000,
-                .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
+                .valid_ops_mask = REGULATOR_CHANGE_CURRENT|REGULATOR_CHANGE_STATUS,
         },
         .num_consumer_supplies  = ARRAY_SIZE(bq24022_consumers),
         .consumer_supplies      = bq24022_consumers,
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index b024a8b3743..c4639502efc 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -99,11 +99,24 @@
 #define GAFR(x)         GPIO_REG(0x54 + (((x) & 0x70) >> 2))
 
 
-#define NR_BUILTIN_GPIO 128
+#define NR_BUILTIN_GPIO         PXA_GPIO_IRQ_NUM
 
 #define gpio_to_bank(gpio)      ((gpio) >> 5)
 #define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
-#define irq_to_gpio(irq)        IRQ_TO_GPIO(irq)
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        int gpio;
+
+        if (irq == IRQ_GPIO0 || irq == IRQ_GPIO1)
+                return irq - IRQ_GPIO0;
+
+        gpio = irq - PXA_GPIO_IRQ_BASE;
+        if (gpio >= 2 && gpio < NR_BUILTIN_GPIO)
+                return gpio;
+
+        return -1;
+}
 
 #ifdef CONFIG_CPU_PXA26x
 /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index a4285fc0087..038402404e3 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -93,9 +93,6 @@
 #define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
 #define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
 
-#define IRQ_TO_GPIO_2_x(i)      ((i) - PXA_GPIO_IRQ_BASE)
-#define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
-
 /*
  * The following interrupts are for board specific purposes. Since
  * the kernel can only run on one machine at a time, we can re-use
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e4fb4668c26..207ecb49a61 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -38,7 +38,7 @@
 #define PCMD(x)         __REG(0x40F50110 + ((x) << 2))
 
 /*
- * Slave Power Managment Unit
+ * Slave Power Management Unit
  */
 #define ASCR            __REG(0x40f40000)       /* Application Subsystem Power Status/Configuration */
 #define ARSR            __REG(0x40f40004)       /* Application Subsystem Reset Status */
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 759b851ec98..5519a34b667 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -16,9 +16,9 @@
 #define BTUART_BASE     (0x40200000)
 #define STUART_BASE     (0x40700000)
 
-static unsigned long uart_base;
-static unsigned int uart_shift;
-static unsigned int uart_is_pxa;
+unsigned long uart_base;
+unsigned int uart_shift;
+unsigned int uart_is_pxa;
 
 static inline unsigned char uart_read(int offset)
 {
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index faa408ab7ad..0641f31a56b 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -64,7 +64,7 @@
 
 /*
  * CPLD registers:
- * Only 4 registers, but spreaded over a 32MB address space.
+ * Only 4 registers, but spread over a 32MB address space.
  * Be gentle, and remap that over 32kB...
  */
 
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index a72993dde2b..9984ef70bd7 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -599,7 +599,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = {
 static struct regulator_init_data bq24022_init_data = {
         .constraints = {
                 .max_uA         = 500000,
-                .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
+                .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
         },
         .num_consumer_supplies  = ARRAY_SIZE(bq24022_consumers),
         .consumer_supplies      = bq24022_consumers,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dd13bb63259..23925db8ff7 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -458,7 +458,7 @@ static struct platform_device strataflash = {
 /*
  * Suspend/Resume bootstrap management
  *
- * MIO A701 reboot sequence is highly ROM dependant. From the one dissassembled,
+ * MIO A701 reboot sequence is highly ROM dependent. From the one dissassembled,
  * this sequence is as follows :
  *   - disables interrupts
  *   - initialize SDRAM (self refresh RAM into active RAM)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 6bde5956358..a4af8c52d7e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -285,7 +285,7 @@ static inline void pxa25x_init_pm(void) {}
 
 static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = IRQ_TO_GPIO(d->irq);
+        int gpio = irq_to_gpio(d->irq);
         uint32_t mask = 0;
 
         if (gpio >= 0 && gpio < 85)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 1cb5d0f9723..909756eaf4b 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -345,7 +345,7 @@ static inline void pxa27x_init_pm(void) {}
  */
 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = IRQ_TO_GPIO(d->irq);
+        int gpio = irq_to_gpio(d->irq);
         uint32_t mask;
 
         if (gpio >= 0 && gpio < 128)
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index 8c9e2c7161c..9cd9bcdad6c 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -66,12 +66,12 @@ extern __attribute__((pure)) struct param_struct *params(void);
 #define params (params())
 
 #ifndef STANDALONE_DEBUG 
-static unsigned long video_num_cols;
-static unsigned long video_num_rows;
-static unsigned long video_x;
-static unsigned long video_y;
-static unsigned char bytes_per_char_v;
-static int white;
+unsigned long video_num_cols;
+unsigned long video_num_rows;
+unsigned long video_x;
+unsigned long video_y;
+unsigned char bytes_per_char_v;
+int white;
 
 /*
  * This does not append a newline
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index cf68136cc66..b2b2a5bb275 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -19,7 +19,7 @@
 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
 
 /* We use `virtual` dma channels to hide the fact we have only a limited
- * number of DMA channels, and not of all of them (dependant on the device)
+ * number of DMA channels, and not of all of them (dependent on the device)
  * can be attached to any DMA source. We therefore let the DMA core handle
  * the allocation of hardware channels to clients.
 */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 7f7c5294796..988a6863e54 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -101,7 +101,7 @@
 #define S3C2410_BANKCON_PMC16           (0x03)
 
 /* bank configurations for banks 0..7, note banks
- * 6 and 7 have differnt configurations depending on
+ * 6 and 7 have different configurations depending on
  * the memory type bits */
 
 #define S3C2410_BANKCON_Tacp2           (0x0 << 2)
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 66f44440d5d..079dcaa602d 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -252,7 +252,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
         .def_trigger    = "",
 };
 
-/* This is the blue LED on the device. Originaly used to indicate GPS activity
+/* This is the blue LED on the device. Originally used to indicate GPS activity
  * by flashing. */
 static struct s3c24xx_led_platdata n35_blue_led_pdata = {
         .name           = "blue_led",
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 0db2411ef4b..716662008ce 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -409,6 +409,10 @@ struct platform_device s3c24xx_pwm_device = {
         .num_resources  = 0,
 };
 
+static struct platform_device gta02_dfbmcs320_device = {
+        .name = "dfbmcs320",
+};
+
 static struct i2c_board_info gta02_i2c_devs[] __initdata = {
         {
                 I2C_BOARD_INFO("pcf50633", 0x73),
@@ -523,6 +527,7 @@ static struct platform_device *gta02_devices[] __initdata = {
         &s3c_device_iis,
         &samsung_asoc_dma,
         &s3c_device_i2c0,
+        &gta02_dfbmcs320_device,
         &gta02_buttons_device,
         &s3c_device_adc,
         &s3c_device_ts,
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index dfedc9c9e00..dd3120df09f 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -155,7 +155,7 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
          * the same timings, however, anything smaller than 1024x768
          * will only be displayed in the top left corner of a 1024x768
          * XGA output unless you add optional dip switches to the shield.
-         * Therefore timings for other resolutions have been ommited here.
+         * Therefore timings for other resolutions have been omitted here.
          */
         [2] = {
                 _LCD_DECLARE(
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index c35585cf8c4..b197171e7d0 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -315,7 +315,7 @@ int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
         case S3C2410_DMAOP_FLUSH:
                 return s3c64xx_dma_flush(chan);
 
-        /* belive PAUSE/RESUME are no-ops */
+        /* believe PAUSE/RESUME are no-ops */
         case S3C2410_DMAOP_PAUSE:
         case S3C2410_DMAOP_RESUME:
         case S3C2410_DMAOP_STARTED:
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 67a145d440f..97660c8141a 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -58,12 +58,7 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
 
         /* add the timer sub-irqs */
-
-        s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
-        s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
-        s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
-        s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
-        s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
+        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 
         s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index c65b229aab2..1608faf870f 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -24,8 +24,8 @@ typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 
 /* uart setup */
 
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
+unsigned int fifo_mask;
+unsigned int fifo_max;
 
 /* forward declerations */
 
@@ -43,7 +43,7 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX         (14)
 
-static unsigned long uart_base;
+unsigned long uart_base;
 
 static __inline__ void get_uart_base(void)
 {
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
index 4be4cc9abf7..07aa4d6054f 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -29,7 +29,7 @@
 #define WPALCON_H                                       (0x19c)
 #define WPALCON_L                                       (0x1a0)
 
-/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
+/* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but
  * different for WPAL2-4
  */
 /* In WPALCON_L (aka WPALCON) */
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
index f16946e456e..be25879bb2e 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci.c
@@ -40,7 +40,7 @@ void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
 {
         u32 ctrl2, ctrl3;
 
-        /* don't need to alter anything acording to card-type */
+        /* don't need to alter anything according to card-type */
 
         writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
 
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
index 1f4b595534c..a5a1e331f8e 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
@@ -18,7 +18,7 @@
 #define gpio_cansleep   __gpio_cansleep
 #define gpio_to_irq     __gpio_to_irq
 
-/* Practically, GPIO banks upto MP03 are the configurable gpio banks */
+/* Practically, GPIO banks up to MP03 are the configurable gpio banks */
 
 /* GPIO bank sizes */
 #define S5PV210_GPIO_A0_NR      (8)
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index 746777d56df..3e3ac05bb7b 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -32,10 +32,10 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 
         switch (width) {
         case 8:
-                /* GPG1[3:6] special-funtion 3 */
+                /* GPG1[3:6] special-function 3 */
                 s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
         case 4:
-                /* GPG0[3:6] special-funtion 2 */
+                /* GPG0[3:6] special-function 2 */
                 s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
         default:
                 break;
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
index c32e202731c..a83b6c909f6 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci.c
@@ -38,7 +38,7 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
 {
         u32 ctrl2, ctrl3;
 
-        /* don't need to alter anything acording to card-type */
+        /* don't need to alter anything according to card-type */
 
         writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
 
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index e697691eed2..41252d22e65 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -50,7 +50,7 @@ led-$(CONFIG_SA1100_SIMPAD)		+= leds-simpad.o
 # LEDs support
 obj-$(CONFIG_LEDS) += $(led-y)
 
-# Miscelaneous functions
+# Miscellaneous functions
 obj-$(CONFIG_PM)                        += pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)                += ssp.o
 
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 07d4e8ba371..aaa8acf76b7 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -68,7 +68,7 @@
  * clock change in ROM and jump to that code from the kernel. The main
  * disadvantage is that the ROM has to be modified, which is not
  * possible on all SA-1100 platforms. Another disadvantage is that
- * jumping to ROM makes clock switching unecessary complicated.
+ * jumping to ROM makes clock switching unnecessary complicated.
  *
  * The idea behind this driver is that the memory configuration can be
  * changed while running from DRAM (even with interrupts turned on!)
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 4f7ea012e1e..bae8296f5db 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -1794,7 +1794,7 @@
                         (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
                          DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
 
-#define DCSR_RUN        0x00000001      /* DMA RUNing                      */
+#define DCSR_RUN        0x00000001      /* DMA running                     */
 #define DCSR_IE         0x00000002      /* DMA Interrupt Enable            */
 #define DCSR_ERROR      0x00000004      /* DMA ERROR                       */
 #define DCSR_DONEA      0x00000008      /* DONE DMA transfer buffer A      */
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index 9d490c66891..f50b00bd18a 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -29,7 +29,7 @@ static unsigned long jornada_ssp_flags;
 /**
  * jornada_ssp_reverse - reverses input byte
  *
- * we need to reverse all data we recieve from the mcu due to its physical location
+ * we need to reverse all data we receive from the mcu due to its physical location
  * returns : 01110111 -> 11101110
  */
 u8 inline jornada_ssp_reverse(u8 byte)
@@ -179,7 +179,7 @@ static int __devinit jornada_ssp_probe(struct platform_device *dev)
 
 static int jornada_ssp_remove(struct platform_device *dev)
 {
-        /* Note that this doesnt actually remove the driver, since theres nothing to remove
+        /* Note that this doesn't actually remove the driver, since theres nothing to remove
          * It just makes sure everything is turned off */
         GPSR = GPIO_GPIO25;
         ssp_exit();
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 783b66fa95f..1e35fa976d6 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -947,7 +947,7 @@ static struct platform_device *ap4evb_devices[] __initdata = {
         &ap4evb_camera,
 };
 
-static int __init hdmi_init_pm_clock(void)
+static void __init hdmi_init_pm_clock(void)
 {
         struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
         int ret;
@@ -988,20 +988,15 @@ static int __init hdmi_init_pm_clock(void)
         pr_debug("PLLC2 set frequency %lu\n", rate);
 
         ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
-        if (ret < 0) {
+        if (ret < 0)
                 pr_err("Cannot set HDMI parent: %d\n", ret);
-                goto out;
-        }
 
 out:
         if (!IS_ERR(hdmi_ick))
                 clk_put(hdmi_ick);
-        return ret;
 }
 
-device_initcall(hdmi_init_pm_clock);
-
-static int __init fsi_init_pm_clock(void)
+static void __init fsi_init_pm_clock(void)
 {
         struct clk *fsia_ick;
         int ret;
@@ -1010,7 +1005,7 @@ static int __init fsi_init_pm_clock(void)
         if (IS_ERR(fsia_ick)) {
                 ret = PTR_ERR(fsia_ick);
                 pr_err("Cannot get FSI ICK: %d\n", ret);
-                return ret;
+                return;
         }
 
         ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
@@ -1018,10 +1013,7 @@ static int __init fsi_init_pm_clock(void)
                 pr_err("Cannot set FSI-A parent: %d\n", ret);
 
         clk_put(fsia_ick);
-
-        return ret;
 }
-device_initcall(fsi_init_pm_clock);
 
 /*
  * FIXME !!
@@ -1348,6 +1340,9 @@ static void __init ap4evb_init(void)
         __raw_writel(srcr4 & ~(1 << 13), SRCR4);
 
         platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
+
+        hdmi_init_pm_clock();
+        fsi_init_pm_clock();
 }
 
 static void __init ap4evb_timer_init(void)
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 8184d4d4f23..7da2ca24229 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -423,7 +423,7 @@ static struct platform_device fsi_hdmi_device = {
         .name           = "sh_fsi2_b_hdmi",
 };
 
-static int __init hdmi_init_pm_clock(void)
+static void __init hdmi_init_pm_clock(void)
 {
         struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
         int ret;
@@ -467,17 +467,13 @@ static int __init hdmi_init_pm_clock(void)
         pr_debug("PLLC2 set frequency %lu\n", rate);
 
         ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
-        if (ret < 0) {
+        if (ret < 0)
                 pr_err("Cannot set HDMI parent: %d\n", ret);
-                goto out;
-        }
 
 out:
         if (!IS_ERR(hdmi_ick))
                 clk_put(hdmi_ick);
-        return ret;
 }
-device_initcall(hdmi_init_pm_clock);
 
 /* USB1 (Host) */
 static void usb1_host_port_power(int port, int power)
@@ -1218,6 +1214,8 @@ static void __init mackerel_init(void)
         sh7372_add_standard_devices();
 
         platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
+
+        hdmi_init_pm_clock();
 }
 
 static void __init mackerel_timer_init(void)
diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h
index e11560a525a..21a59db638b 100644
--- a/arch/arm/mach-shmobile/include/mach/mmc.h
+++ b/arch/arm/mach-shmobile/include/mach/mmc.h
@@ -9,7 +9,7 @@
 
 #ifdef CONFIG_MACH_AP4EVB
 #include "mach/mmc-ap4eb.h"
-#elif CONFIG_MACH_MACKEREL
+#elif defined(CONFIG_MACH_MACKEREL)
 #include "mach/mmc-mackerel.h"
 #else
 #error "unsupported board."
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index 6d6a205bcf9..9320aff0a20 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -13,7 +13,7 @@
 #ifdef CONFIG_MACH_AP4EVB
 #define MACH_TYPE       MACH_TYPE_AP4EVB
 #include "mach/head-ap4evb.txt"
-#elif CONFIG_MACH_MACKEREL
+#elif defined(CONFIG_MACH_MACKEREL)
 #define MACH_TYPE       MACH_TYPE_MACKEREL
 #include "mach/head-mackerel.txt"
 #else
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1afe05038c2..823c703e573 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,7 @@
 obj-y                                   += common.o
 obj-y                                   += devices.o
 obj-y                                   += io.o
-obj-y                                   += irq.o legacy_irq.o
+obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index e945ae28ee7..f4ef5eb317b 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -223,7 +223,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
          *  - Change the source selector to invalid to stop the DMA from
          *    FIFO to memory.
          *  - Read the status register to know the number of pending
-         *    bytes to be transfered.
+         *    bytes to be transferred.
          *  - Finally stop or program the DMA to the next buffer in the
          *    list.
          */
@@ -244,7 +244,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
         if (status & STA_BUSY)
                 req->bytes_transferred -= to_transfer;
 
-        /* In continous transfer mode, DMA only tracks the count of the
+        /* In continuous transfer mode, DMA only tracks the count of the
          * half DMA buffer. So, if the DMA already finished half the DMA
          * then add the half buffer to the completed count.
          *
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 76a3f654220..919d6383773 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -24,6 +24,8 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
+#include <asm/mach/irq.h>
+
 #include <mach/iomap.h>
 #include <mach/suspend.h>
 
@@ -221,8 +223,9 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         int port;
         int pin;
         int unmasked = 0;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
 
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         bank = irq_get_handler_data(irq);
 
@@ -241,7 +244,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                          */
                         if (lvl & (0x100 << pin)) {
                                 unmasked = 1;
-                                desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                                chained_irq_exit(chip, desc);
                         }
 
                         generic_handle_irq(gpio_to_irq(gpio + pin));
@@ -249,7 +252,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 
         if (!unmasked)
-                desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                chained_irq_exit(chip, desc);
 
 }
 
@@ -257,7 +260,8 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 void tegra_gpio_resume(void)
 {
         unsigned long flags;
-        int b, p, i;
+        int b;
+        int p;
 
         local_irq_save(flags);
 
@@ -280,7 +284,8 @@ void tegra_gpio_resume(void)
 void tegra_gpio_suspend(void)
 {
         unsigned long flags;
-        int b, p, i;
+        int b;
+        int p;
 
         local_irq_save(flags);
         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 39011bd9a92..d0132e8031a 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -92,11 +92,11 @@ struct tegra_dma_req {
         /*  This is a called from the DMA ISR context when the DMA is still in
          *  progress and is actively filling same buffer.
          *
-         *  In case of continous mode receive, this threshold is 1/2 the buffer
+         *  In case of continuous mode receive, this threshold is 1/2 the buffer
          *  size. In other cases, this will not even be called as there is no
          *  hardware support for it.
          *
-         * In the case of continous mode receive, if there is next req already
+         * In the case of continuous mode receive, if there is next req already
          * queued, DMA programs the HW to use that req when this req is
          * completed. If there is no "next req" queued, then DMA ISR doesn't do
          * anything before calling this callback.
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
deleted file mode 100644
index d898c0e3d90..00000000000
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/legacy_irq.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-
-void tegra_legacy_mask_irq(unsigned int irq);
-void tegra_legacy_unmask_irq(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-void tegra_legacy_force_irq_set(unsigned int irq);
-void tegra_legacy_force_irq_clr(unsigned int irq);
-int tegra_legacy_force_irq_status(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-unsigned long tegra_legacy_vfiq(int nr);
-unsigned long tegra_legacy_class(int nr);
-int tegra_legacy_irq_set_wake(int irq, int enable);
-void tegra_legacy_irq_set_lp1_wake_mask(void);
-void tegra_legacy_irq_restore_mask(void);
-void tegra_init_legacy_irq(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4330d8995b2..4956c3cea73 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -1,8 +1,8 @@
 /*
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
  *
  * Author:
- *      Colin Cross <ccross@google.com>
+ *      Colin Cross <ccross@android.com>
  *
  * Copyright (C) 2010, NVIDIA Corporation
  *
@@ -18,8 +18,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
@@ -27,134 +25,110 @@
 #include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
-#include <mach/legacy_irq.h>
-#include <mach/suspend.h>
 
 #include "board.h"
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
-#define PMC_WAKE_MASK           0xc
-#define PMC_WAKE_LEVEL          0x10
-#define PMC_WAKE_STATUS         0x14
-#define PMC_SW_WAKE_STATUS      0x18
-#define PMC_DPD_SAMPLE          0x20
+#define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
+#define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
+#define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
+
+#define ICTLR_CPU_IEP_VFIQ      0x08
+#define ICTLR_CPU_IEP_FIR       0x14
+#define ICTLR_CPU_IEP_FIR_SET   0x18
+#define ICTLR_CPU_IEP_FIR_CLR   0x1c
+
+#define ICTLR_CPU_IER           0x20
+#define ICTLR_CPU_IER_SET       0x24
+#define ICTLR_CPU_IER_CLR       0x28
+#define ICTLR_CPU_IEP_CLASS     0x2C
+
+#define ICTLR_COP_IER           0x30
+#define ICTLR_COP_IER_SET       0x34
+#define ICTLR_COP_IER_CLR       0x38
+#define ICTLR_COP_IEP_CLASS     0x3c
+
+#define NUM_ICTLRS 4
+#define FIRST_LEGACY_IRQ 32
+
+static void __iomem *ictlr_reg_base[] = {
+        IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+};
 
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
+{
+        void __iomem *base;
+        u32 mask;
 
-static u32 tegra_lp0_wake_enb;
-static u32 tegra_lp0_wake_level;
-static u32 tegra_lp0_wake_level_any;
+        BUG_ON(irq < FIRST_LEGACY_IRQ ||
+                irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
 
-static void (*tegra_gic_mask_irq)(struct irq_data *d);
-static void (*tegra_gic_unmask_irq)(struct irq_data *d);
-static void (*tegra_gic_ack_irq)(struct irq_data *d);
+        base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
+        mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
 
-/* ensures that sufficient time is passed for a register write to
- * serialize into the 32KHz domain */
-static void pmc_32kwritel(u32 val, unsigned long offs)
-{
-        writel(val, pmc + offs);
-        udelay(130);
+        __raw_writel(mask, base + reg);
 }
 
-int tegra_set_lp1_wake(int irq, int enable)
+static void tegra_mask(struct irq_data *d)
 {
-        return tegra_legacy_irq_set_wake(irq, enable);
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
+
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
 }
 
-void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
+static void tegra_unmask(struct irq_data *d)
 {
-        u32 temp;
-        u32 status;
-        u32 lvl;
-
-        wake_level &= wake_enb;
-        wake_any &= wake_enb;
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
 
-        wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
-        wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
-
-        wake_enb |= tegra_lp0_wake_enb;
-
-        pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
-        temp = readl(pmc + PMC_CTRL);
-        temp |= PMC_CTRL_LATCH_WAKEUPS;
-        pmc_32kwritel(temp, PMC_CTRL);
-        temp &= ~PMC_CTRL_LATCH_WAKEUPS;
-        pmc_32kwritel(temp, PMC_CTRL);
-        status = readl(pmc + PMC_SW_WAKE_STATUS);
-        lvl = readl(pmc + PMC_WAKE_LEVEL);
-
-        /* flip the wakeup trigger for any-edge triggered pads
-         * which are currently asserting as wakeups */
-        lvl ^= status;
-        lvl &= wake_any;
-
-        wake_level |= lvl;
-
-        writel(wake_level, pmc + PMC_WAKE_LEVEL);
-        /* Enable DPD sample to trigger sampling pads data and direction
-         * in which pad will be driven during lp0 mode*/
-        writel(0x1, pmc + PMC_DPD_SAMPLE);
-
-        writel(wake_enb, pmc + PMC_WAKE_MASK);
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
 }
 
-static void tegra_mask(struct irq_data *d)
+static void tegra_ack(struct irq_data *d)
 {
-        tegra_gic_mask_irq(d);
-        tegra_legacy_mask_irq(d->irq);
-}
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
 
-static void tegra_unmask(struct irq_data *d)
-{
-        tegra_gic_unmask_irq(d);
-        tegra_legacy_unmask_irq(d->irq);
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
 }
 
-static void tegra_ack(struct irq_data *d)
+static void tegra_eoi(struct irq_data *d)
 {
-        tegra_legacy_force_irq_clr(d->irq);
-        tegra_gic_ack_irq(d);
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
+
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
 }
 
 static int tegra_retrigger(struct irq_data *d)
 {
-        tegra_legacy_force_irq_set(d->irq);
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return 0;
+
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
+
         return 1;
 }
 
-static struct irq_chip tegra_irq = {
-        .name                   = "PPI",
-        .irq_ack                = tegra_ack,
-        .irq_mask               = tegra_mask,
-        .irq_unmask             = tegra_unmask,
-        .irq_retrigger          = tegra_retrigger,
-};
-
 void __init tegra_init_irq(void)
 {
-        struct irq_chip *gic;
-        unsigned int i;
-        int irq;
+        int i;
 
-        tegra_init_legacy_irq();
+        for (i = 0; i < NUM_ICTLRS; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                writel(~0, ictlr + ICTLR_CPU_IER_CLR);
+                writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
+        }
+
+        gic_arch_extn.irq_ack = tegra_ack;
+        gic_arch_extn.irq_eoi = tegra_eoi;
+        gic_arch_extn.irq_mask = tegra_mask;
+        gic_arch_extn.irq_unmask = tegra_unmask;
+        gic_arch_extn.irq_retrigger = tegra_retrigger;
 
         gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
                  IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
-
-        gic = irq_get_chip(29);
-        tegra_gic_unmask_irq = gic->irq_unmask;
-        tegra_gic_mask_irq = gic->irq_mask;
-        tegra_gic_ack_irq = gic->irq_ack;
-#ifdef CONFIG_SMP
-        tegra_irq.irq_set_affinity = gic->irq_set_affinity;
-#endif
-
-        for (i = 0; i < INT_MAIN_NR; i++) {
-                irq = INT_PRI_BASE + i;
-                irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
 }
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
deleted file mode 100644
index 38eb719a4f5..00000000000
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-tegra/legacy_irq.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/legacy_irq.h>
-
-#define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
-#define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
-#define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-
-#define ICTLR_CPU_IEP_VFIQ      0x08
-#define ICTLR_CPU_IEP_FIR       0x14
-#define ICTLR_CPU_IEP_FIR_SET   0x18
-#define ICTLR_CPU_IEP_FIR_CLR   0x1c
-
-#define ICTLR_CPU_IER           0x20
-#define ICTLR_CPU_IER_SET       0x24
-#define ICTLR_CPU_IER_CLR       0x28
-#define ICTLR_CPU_IEP_CLASS     0x2C
-
-#define ICTLR_COP_IER           0x30
-#define ICTLR_COP_IER_SET       0x34
-#define ICTLR_COP_IER_CLR       0x38
-#define ICTLR_COP_IEP_CLASS     0x3c
-
-#define NUM_ICTLRS 4
-
-static void __iomem *ictlr_reg_base[] = {
-        IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-        IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-        IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-        IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-};
-
-static u32 tegra_legacy_wake_mask[4];
-static u32 tegra_legacy_saved_mask[4];
-
-/* When going into deep sleep, the CPU is powered down, taking the GIC with it
-   In order to wake, the wake interrupts need to be enabled in the legacy
-   interrupt controller. */
-void tegra_legacy_unmask_irq(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
-}
-
-void tegra_legacy_mask_irq(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
-}
-
-void tegra_legacy_force_irq_set(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
-}
-
-void tegra_legacy_force_irq_clr(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
-}
-
-int tegra_legacy_force_irq_status(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
-}
-
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
-}
-
-unsigned long tegra_legacy_vfiq(int nr)
-{
-        void __iomem *base;
-        base = ictlr_reg_base[nr];
-        return readl(base + ICTLR_CPU_IEP_VFIQ);
-}
-
-unsigned long tegra_legacy_class(int nr)
-{
-        void __iomem *base;
-        base = ictlr_reg_base[nr];
-        return readl(base + ICTLR_CPU_IEP_CLASS);
-}
-
-int tegra_legacy_irq_set_wake(int irq, int enable)
-{
-        irq -= 32;
-        if (enable)
-                tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31);
-        else
-                tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31));
-
-        return 0;
-}
-
-void tegra_legacy_irq_set_lp1_wake_mask(void)
-{
-        void __iomem *base;
-        int i;
-
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                base = ictlr_reg_base[i];
-                tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER);
-                writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER);
-        }
-}
-
-void tegra_legacy_irq_restore_mask(void)
-{
-        void __iomem *base;
-        int i;
-
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                base = ictlr_reg_base[i];
-                writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER);
-        }
-}
-
-void tegra_init_legacy_irq(void)
-{
-        int i;
-
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                void __iomem *ictlr = ictlr_reg_base[i];
-                writel(~0, ictlr + ICTLR_CPU_IER_CLR);
-                writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
-        }
-}
-
-#ifdef CONFIG_PM
-static u32 cop_ier[NUM_ICTLRS];
-static u32 cpu_ier[NUM_ICTLRS];
-static u32 cpu_iep[NUM_ICTLRS];
-
-void tegra_irq_suspend(void)
-{
-        unsigned long flags;
-        int i;
-
-        local_irq_save(flags);
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                void __iomem *ictlr = ictlr_reg_base[i];
-                cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
-                cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
-                cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
-                writel(~0, ictlr + ICTLR_COP_IER_CLR);
-        }
-        local_irq_restore(flags);
-}
-
-void tegra_irq_resume(void)
-{
-        unsigned long flags;
-        int i;
-
-        local_irq_save(flags);
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                void __iomem *ictlr = ictlr_reg_base[i];
-                writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
-                writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
-                writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
-                writel(0, ictlr + ICTLR_COP_IEP_CLASS);
-                writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
-                writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
-        }
-        local_irq_restore(flags);
-}
-#endif
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 6d7c4eea4dc..4459470c052 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1362,14 +1362,15 @@ static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
 {
         unsigned long flags;
         int ret;
+        long new_rate = rate;
 
-        rate = clk_round_rate(c->parent, rate);
-        if (rate < 0)
-                return rate;
+        new_rate = clk_round_rate(c->parent, new_rate);
+        if (new_rate < 0)
+                return new_rate;
 
         spin_lock_irqsave(&c->parent->spinlock, flags);
 
-        c->u.shared_bus_user.rate = rate;
+        c->u.shared_bus_user.rate = new_rate;
         ret = tegra_clk_shared_bus_update(c->parent);
 
         spin_unlock_irqrestore(&c->parent->spinlock, flags);
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index fabcc49abe8..5535dd0a78c 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -263,7 +263,7 @@ static void disable_i2s0_vcxo(void)
         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
         val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        /* Deactivate VCXO if noone else is using VCXO */
+        /* Deactivate VCXO if no one else is using VCXO */
         if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
                 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
@@ -283,7 +283,7 @@ static void disable_i2s1_vcxo(void)
         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
         val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        /* Deactivate VCXO if noone else is using VCXO */
+        /* Deactivate VCXO if no one else is using VCXO */
         if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
                 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
@@ -649,7 +649,7 @@ static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
  */
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */
+        /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
         /* Else default to fixed value */
 
         if (clk->round_rate) {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index dc8746d7826..6e1907fa94f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -52,7 +52,7 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
          * on value present in GpioSel1 to GpioSel6 and AlternatFunction
          * register. This is the array of 7 configuration settings.
          * One has to compile time decide these settings. Below is the
-         * explaination of these setting
+         * explanation of these setting
          * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
          * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
          * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
@@ -178,16 +178,15 @@ static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
                 .irq            = NOMADIK_GPIO_TO_IRQ(217),
                 .platform_data  = &mop500_tc35892_data,
         },
-};
-
-/* I2C0 devices only available prior to HREFv60 */
-static struct i2c_board_info __initdata mop500_i2c0_old_devices[] = {
+        /* I2C0 devices only available prior to HREFv60 */
         {
                 I2C_BOARD_INFO("tps61052", 0x33),
                 .platform_data  = &mop500_tps61052_data,
         },
 };
 
+#define NUM_PRE_V60_I2C0_DEVICES 1
+
 static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
         {
                 /* lp5521 LED driver, 1st device */
@@ -425,6 +424,8 @@ static void __init mop500_uart_init(void)
 
 static void __init mop500_init_machine(void)
 {
+        int i2c0_devs;
+
         /*
          * The HREFv60 board removed a GPIO expander and routed
          * all these GPIO pins to the internal GPIO controller
@@ -448,11 +449,11 @@ static void __init mop500_init_machine(void)
 
         platform_device_register(&ab8500_device);
 
-        i2c_register_board_info(0, mop500_i2c0_devices,
-                                ARRAY_SIZE(mop500_i2c0_devices));
-        if (!machine_is_hrefv60())
-                i2c_register_board_info(0, mop500_i2c0_old_devices,
-                                        ARRAY_SIZE(mop500_i2c0_old_devices));
+        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+        if (machine_is_hrefv60())
+                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+
+        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
         i2c_register_board_info(2, mop500_i2c2_devices,
                                 ARRAY_SIZE(mop500_i2c2_devices));
 }
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 0fefb34c11e..16647b25537 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -58,7 +58,7 @@
 #define U8500_GPIO2_BASE        (U8500_PER2_BASE + 0xE000)
 #define U8500_GPIO3_BASE        (U8500_PER5_BASE + 0x1E000)
 
-/* per7 base addressess */
+/* per7 base addresses */
 #define U8500_CR_BASE_ED        (U8500_PER7_BASE_ED + 0x8000)
 #define U8500_MTU0_BASE_ED      (U8500_PER7_BASE_ED + 0xa000)
 #define U8500_MTU1_BASE_ED      (U8500_PER7_BASE_ED + 0xb000)
@@ -68,7 +68,7 @@
 #define U8500_UART0_BASE        (U8500_PER1_BASE + 0x0000)
 #define U8500_UART1_BASE        (U8500_PER1_BASE + 0x1000)
 
-/* per6 base addressess */
+/* per6 base addresses */
 #define U8500_RNG_BASE          (U8500_PER6_BASE + 0x0000)
 #define U8500_PKA_BASE          (U8500_PER6_BASE + 0x1000)
 #define U8500_PKAM_BASE         (U8500_PER6_BASE + 0x2000)
@@ -79,11 +79,11 @@
 #define U8500_CRYPTO1_BASE      (U8500_PER6_BASE + 0xb000)
 #define U8500_CLKRST6_BASE      (U8500_PER6_BASE + 0xf000)
 
-/* per5 base addressess */
+/* per5 base addresses */
 #define U8500_USBOTG_BASE       (U8500_PER5_BASE + 0x00000)
 #define U8500_CLKRST5_BASE      (U8500_PER5_BASE + 0x1f000)
 
-/* per4 base addressess */
+/* per4 base addresses */
 #define U8500_BACKUPRAM0_BASE   (U8500_PER4_BASE + 0x00000)
 #define U8500_BACKUPRAM1_BASE   (U8500_PER4_BASE + 0x01000)
 #define U8500_RTT0_BASE         (U8500_PER4_BASE + 0x02000)
@@ -106,7 +106,7 @@
 #define U8500_SDI5_BASE         (U8500_PER3_BASE + 0x8000)
 #define U8500_CLKRST3_BASE      (U8500_PER3_BASE + 0xf000)
 
-/* per2 base addressess */
+/* per2 base addresses */
 #define U8500_I2C3_BASE         (U8500_PER2_BASE + 0x0000)
 #define U8500_SPI2_BASE         (U8500_PER2_BASE + 0x1000)
 #define U8500_SPI1_BASE         (U8500_PER2_BASE + 0x2000)
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index ab0fe1432fa..088b550c40d 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -24,7 +24,7 @@
 #include <linux/amba/serial.h>
 #include <mach/hardware.h>
 
-static u32 ux500_uart_base;
+u32 ux500_uart_base;
 
 static void putc(const char c)
 {
diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h
index 56f1a74d701..03130212ace 100644
--- a/arch/arm/mach-w90x900/include/mach/uncompress.h
+++ b/arch/arm/mach-w90x900/include/mach/uncompress.h
@@ -27,7 +27,7 @@
 #define arch_decomp_wdog()
 
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-static volatile u32 * uart_base = (u32 *)UART0_PA;
+static volatile u32 * const uart_base = (u32 *)UART0_PA;
 
 static void putc(int ch)
 {
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index d3644db467b..f40c69656d8 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -32,7 +32,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  *
  *  Size  Clean (ticks) Dirty (ticks)
  *   4096   21  20  21    53  55  54
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 49c2b66cf3d..a7b276dbda1 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -34,7 +34,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  *
  * *** This needs benchmarking
  */
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 6136e68ce95..dc18d81ef8c 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all)
  *      Flush the entire cache system.
  *  The data cache flush is now achieved using atomic clean / invalidates
  *  working outwards from L1 cache. This is done using Set/Way based cache
- *  maintainance instructions.
+ *  maintenance instructions.
  *  The instruction cache can still be invalidated back to the point of
  *  unification in a single instruction.
  *
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index afe209e1e1f..74be05f3e03 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -7,6 +7,7 @@
 #include <linux/shm.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/personality.h>
 #include <linux/random.h>
 #include <asm/cputype.h>
 #include <asm/system.h>
@@ -82,7 +83,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
                 mm->cached_hole_size = 0;
         }
         /* 8 bits of randomness in 20 address space bits */
-        if (current->flags & PF_RANDOMIZE)
+        if ((current->flags & PF_RANDOMIZE) &&
+            !(current->personality & ADDR_NO_RANDOMIZE))
                 addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
 
 full_search:
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 226e3d8351c..6c4e7fd6c8a 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -64,7 +64,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  */
 #define CACHE_DLIMIT    32768
 
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 86d9c2cf0bc..4ce947c1962 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -64,7 +64,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  */
 #define CACHE_DLIMIT    32768
 
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 83d3dd34f84..c8884c5413a 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -53,7 +53,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  */
 #define CACHE_DLIMIT    32768
 
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 686043ee728..413684660aa 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -53,7 +53,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  */
 #define CACHE_DLIMIT    32768
 
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 665266da143..7a06e5964f5 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -63,7 +63,7 @@ ENTRY(cpu_arm720_proc_fin)
 /*
  * Function: arm720_proc_do_idle(void)
  * Params  : r0 = unused
- * Purpose : put the processer in proper idle mode
+ * Purpose : put the processor in proper idle mode
  */
 ENTRY(cpu_arm720_do_idle)
                 mov     pc, lr
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 219980ec8b6..bf8a1d1cccb 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -53,7 +53,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  */
 #define CACHE_DLIMIT    65536
 
@@ -390,7 +390,7 @@ ENTRY(cpu_arm920_set_pte_ext)
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl  cpu_arm920_suspend_size
 .equ    cpu_arm920_suspend_size, 4 * 3
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_arm920_do_suspend)
         stmfd   sp!, {r4 - r7, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ PID
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 36154b1e792..95ba1fc56e4 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -54,7 +54,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.  (I think this should
+ * cache line maintenance instructions.  (I think this should
  * be 32768).
  */
 #define CACHE_DLIMIT    8192
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 89c5e0009c4..541e4774eea 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -77,7 +77,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  */
 #define CACHE_DLIMIT    8192
 
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 6a4bdb2c94a..0ed85d930c0 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -404,7 +404,7 @@ ENTRY(cpu_arm926_set_pte_ext)
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl  cpu_arm926_suspend_size
 .equ    cpu_arm926_suspend_size, 4 * 3
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_arm926_do_suspend)
         stmfd   sp!, {r4 - r7, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ PID
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e32fa499194..34261f9486b 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -85,7 +85,7 @@
 
 /*
  * Sanity check the PTE configuration for the code below - which makes
- * certain assumptions about how these bits are layed out.
+ * certain assumptions about how these bits are laid out.
  */
 #ifdef CONFIG_MMU
 #if L_PTE_SHARED != PTE_EXT_SHARED
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 74483d1977f..184a9c997e3 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -171,7 +171,7 @@ ENTRY(cpu_sa1100_set_pte_ext)
 
 .globl  cpu_sa1100_suspend_size
 .equ    cpu_sa1100_suspend_size, 4*4
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_sa1100_do_suspend)
         stmfd   sp!, {r4 - r7, lr}
         mrc     p15, 0, r4, c3, c0, 0           @ domain ID
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 832b6bdc192..ab17cc0d3fa 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -124,7 +124,7 @@ ENTRY(cpu_v6_set_pte_ext)
 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
 .globl  cpu_v6_suspend_size
 .equ    cpu_v6_suspend_size, 4 * 8
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v6_do_suspend)
         stmfd   sp!, {r4 - r11, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
@@ -132,7 +132,7 @@ ENTRY(cpu_v6_do_suspend)
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r7, c2, c0, 0   @ Translation table base 0
         mrc     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-        mrc     p15, 0, r9, c1, c0, 1   @ auxillary control register
+        mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control register
         mrc     p15, 0, r10, c1, c0, 2  @ co-processor access control
         mrc     p15, 0, r11, c1, c0, 0  @ control register
         stmia   r0, {r4 - r11}
@@ -151,7 +151,7 @@ ENTRY(cpu_v6_do_resume)
         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
         mcr     p15, 0, r7, c2, c0, 0   @ Translation table base 0
         mcr     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-        mcr     p15, 0, r9, c1, c0, 1   @ auxillary control register
+        mcr     p15, 0, r9, c1, c0, 1   @ auxiliary control register
         mcr     p15, 0, r10, c1, c0, 2  @ co-processor access control
         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
         mcr     p15, 0, ip, c7, c5, 4   @ ISB
@@ -175,11 +175,6 @@ cpu_v6_name:
         .asciz  "ARMv6-compatible processor"
         .size   cpu_v6_name, . - cpu_v6_name
 
-        .type   cpu_pj4_name, #object
-cpu_pj4_name:
-        .asciz  "Marvell PJ4 processor"
-        .size   cpu_pj4_name, . - cpu_pj4_name
-
         .align
 
         __CPUINIT
@@ -305,32 +300,3 @@ __v6_proc_info:
         .long   v6_user_fns
         .long   v6_cache_fns
         .size   __v6_proc_info, . - __v6_proc_info
-
-        .type   __pj4_v6_proc_info, #object
-__pj4_v6_proc_info:
-        .long   0x560f5810
-        .long   0xff0ffff0
-        ALT_SMP(.long \
-                PMD_TYPE_SECT | \
-                PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ | \
-                PMD_FLAGS_SMP)
-        ALT_UP(.long \
-                PMD_TYPE_SECT | \
-                PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ | \
-                PMD_FLAGS_UP)
-        .long   PMD_TYPE_SECT | \
-                PMD_SECT_XN | \
-                PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ
-        b       __v6_setup
-        .long   cpu_arch_name
-        .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
-        .long   cpu_pj4_name
-        .long   v6_processor_functions
-        .long   v6wbi_tlb_fns
-        .long   v6_user_fns
-        .long   v6_cache_fns
-        .size   __pj4_v6_proc_info, . - __pj4_v6_proc_info
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 262fa88a743..babfba09c89 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -211,7 +211,7 @@ cpu_v7_name:
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl  cpu_v7_suspend_size
 .equ    cpu_v7_suspend_size, 4 * 8
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v7_do_suspend)
         stmfd   sp!, {r4 - r11, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
@@ -237,7 +237,7 @@ ENTRY(cpu_v7_do_resume)
         mcr     p15, 0, r7, c2, c0, 0   @ TTB 0
         mcr     p15, 0, r8, c2, c0, 1   @ TTB 1
         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
-        mcr     p15, 0, r10, c1, c0, 1  @ Auxillary control register
+        mcr     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
         mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access control
         ldr     r4, =PRRR               @ PRRR
         ldr     r5, =NMRR               @ NMRR
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 63d8b2044e8..596213699f3 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -417,7 +417,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
 
 .globl  cpu_xsc3_suspend_size
 .equ    cpu_xsc3_suspend_size, 4 * 8
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_xsc3_do_suspend)
         stmfd   sp!, {r4 - r10, lr}
         mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 086038cd86a..42af97664c9 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -395,7 +395,7 @@ ENTRY(xscale_dma_a0_map_area)
         teq     r2, #DMA_TO_DEVICE
         beq     xscale_dma_clean_range
         b       xscale_dma_flush_range
-ENDPROC(xscsale_dma_a0_map_area)
+ENDPROC(xscale_dma_a0_map_area)
 
 /*
  *      dma_unmap_area(start, size, dir)
@@ -518,7 +518,7 @@ ENTRY(cpu_xscale_set_pte_ext)
 
 .globl  cpu_xscale_suspend_size
 .equ    cpu_xscale_suspend_size, 4 * 7
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_xscale_do_suspend)
         stmfd   sp!, {r4 - r10, lr}
         mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index ce81481becf..4268a2bdf14 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -13,7 +13,7 @@
 
 /*
  * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
- * The CPUFREQ driver is for controling CPU frequency. It allows you to change
+ * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
  * the CPU clock speed on the fly.
  */
 
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 7a107246fd9..6cd6d7f686f 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -295,6 +295,12 @@ static int mxc_gpio_direction_output(struct gpio_chip *chip,
         return 0;
 }
 
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
 int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 {
         int i, j;
@@ -311,6 +317,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 __raw_writel(~0, port[i].base + GPIO_ISR);
                 for (j = port[i].virtual_irq_start;
                         j < port[i].virtual_irq_start + 32; j++) {
+                        irq_set_lockdep_class(j, &gpio_lock_class);
                         irq_set_chip_and_handler(j, &gpio_irq_chip,
                                                  handle_level_irq);
                         set_irq_flags(j, IRQF_VALID);
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index bd9bb979914..2e49e71b1b9 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -33,9 +33,9 @@
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
 
-        @ this macro checks which interrupt occured
+        @ this macro checks which interrupt occurred
         @ and returns its number in irqnr
-        @ and returns if an interrupt occured in irqstat
+        @ and returns if an interrupt occurred in irqstat
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 #ifndef CONFIG_MXC_TZIC
         @ Load offset & priority of the highest priority
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 04c0d060d81..6bb96ef1600 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -24,7 +24,7 @@
 
 struct mxc_nand_platform_data {
         unsigned int width;     /* data bus width in bytes */
-        unsigned int hw_ecc:1;  /* 0 if supress hardware ECC */
+        unsigned int hw_ecc:1;  /* 0 if suppress hardware ECC */
         unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
         struct mtd_partition *parts;    /* partition table */
         int nr_parts;                   /* size of parts */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 4864b0afd44..d85e2d1c032 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -21,7 +21,7 @@
 
 #include <asm/mach-types.h>
 
-static unsigned long uart_base;
+unsigned long uart_base;
 
 #define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
 
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index f49748eca1a..307b8131aa8 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,8 @@
 #include <linux/irq.h>
 #include <linux/slab.h>
 
+#include <asm/mach/irq.h>
+
 #include <plat/pincfg.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
@@ -681,13 +683,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
         struct irq_chip *host_chip = irq_get_chip(irq);
         unsigned int first_irq;
 
-        if (host_chip->irq_mask_ack)
-                host_chip->irq_mask_ack(&desc->irq_data);
-        else {
-                host_chip->irq_mask(&desc->irq_data);
-                if (host_chip->irq_ack)
-                        host_chip->irq_ack(&desc->irq_data);
-        }
+        chained_irq_enter(host_chip, desc);
 
         nmk_chip = irq_get_handler_data(irq);
         first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
@@ -698,7 +694,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
                 status &= ~BIT(bit);
         }
 
-        host_chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(host_chip, desc);
 }
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 7d9f815cede..ea28f98d5d6 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -280,7 +280,7 @@ EXPORT_SYMBOL(omap_dsp_get_mempool_base);
  * Claiming GPIOs, and setting their direction and initial values, is the
  * responsibility of the device drivers.  So is responding to probe().
  *
- * Board-specific knowlege like creating devices or pin setup is to be
+ * Board-specific knowledge like creating devices or pin setup is to be
  * kept out of drivers as much as possible.  In particular, pin setup
  * may be handled by the boot loader, and drivers should expect it will
  * normally have been done by the time they're probed.
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 2ec3b5d9f21..c22217c2ee5 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1019,7 +1019,7 @@ EXPORT_SYMBOL(omap_set_dma_callback);
  * If the channel is running the caller must disable interrupts prior calling
  * this function and process the returned value before re-enabling interrupt to
  * prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CSSA_L register overflow inbetween the two reads resulting
+ * is a chance for CSSA_L register overflow between the two reads resulting
  * in incorrect return value.
  */
 dma_addr_t omap_get_dma_src_pos(int lch)
@@ -1046,7 +1046,7 @@ EXPORT_SYMBOL(omap_get_dma_src_pos);
  * If the channel is running the caller must disable interrupts prior calling
  * this function and process the returned value before re-enabling interrupt to
  * prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CDSA_L register overflow inbetween the two reads resulting
+ * is a chance for CDSA_L register overflow between the two reads resulting
  * in incorrect return value.
  */
 dma_addr_t omap_get_dma_dst_pos(int lch)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index d2adcdda23c..a2478ebb53f 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1137,8 +1137,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         struct gpio_bank *bank;
         u32 retrigger = 0;
         int unmasked = 0;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
 
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         bank = irq_get_handler_data(irq);
 #ifdef CONFIG_ARCH_OMAP1
@@ -1195,7 +1196,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 configured, we could unmask GPIO bank interrupt immediately */
                 if (!level_mask && !unmasked) {
                         unmasked = 1;
-                        desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                        chained_irq_exit(chip, desc);
                 }
 
                 isr |= retrigger;
@@ -1231,7 +1232,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         interrupt */
 exit:
         if (!unmasked)
-                desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                chained_irq_exit(chip, desc);
 }
 
 static void gpio_irq_shutdown(struct irq_data *d)
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index d6f9fa0f62a..cac2e8ac696 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -93,7 +93,7 @@ extern void omap_gpio_restore_context(void);
 /* Wrappers for "new style" GPIO calls, using the new infrastructure
  * which lets us plug in FPGA, I2C, and other implementations.
  * *
- * The original OMAP-specfic calls should eventually be removed.
+ * The original OMAP-specific calls should eventually be removed.
  */
 
 #include <linux/errno.h>
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 12b31616503..1527929b445 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -90,7 +90,7 @@ enum omap_ecc {
                 /* 1-bit ecc: stored at end of spare area */
         OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
         OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
-                /* 1-bit ecc: stored at begining of spare area as romcode */
+                /* 1-bit ecc: stored at beginning of spare area as romcode */
         OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
 };
 
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 30b891c4a93..565d2664f5a 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -27,8 +27,8 @@
 
 #define MDR1_MODE_MASK                  0x07
 
-static volatile u8 *uart_base;
-static int uart_shift;
+volatile u8 *uart_base;
+int uart_shift;
 
 /*
  * Store the DEBUG_LL uart number into memory.
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index d598d9fd65a..5587acf0eb2 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -1103,7 +1103,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
                 /* resend */
                 return -1;
         } else {
-                /* wait for recieve confirmation */
+                /* wait for receive confirmation */
                 int attemps = 0;
                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
                         if (attemps++ > 1000) {
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 56021a72e10..95a5fc53b6d 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y   := irq.o pcie.o time.o
+obj-y   := irq.o pcie.o time.o common.o mpp.o
 obj-m   :=
 obj-n   :=
 obj-    :=
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
new file mode 100644
index 00000000000..9e5451b3c8e
--- /dev/null
+++ b/arch/arm/plat-orion/common.c
@@ -0,0 +1,957 @@
+/*
+ * arch/arm/plat-orion/common.c
+ *
+ * Marvell Orion SoC common setup code used by multiple mach-/common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/mv643xx_i2c.h>
+#include <net/dsa.h>
+#include <linux/spi/orion_spi.h>
+#include <plat/orion_wdt.h>
+#include <plat/mv_xor.h>
+#include <plat/ehci-orion.h>
+
+/* Fill in the resources structure and link it into the platform
+   device structure. There is always a memory region, and nearly
+   always an interrupt.*/
+static void fill_resources(struct platform_device *device,
+                           struct resource *resources,
+                           resource_size_t mapbase,
+                           resource_size_t size,
+                           unsigned int irq)
+{
+        device->resource = resources;
+        device->num_resources = 1;
+        resources[0].flags = IORESOURCE_MEM;
+        resources[0].start = mapbase;
+        resources[0].end = mapbase + size;
+
+        if (irq != NO_IRQ) {
+                device->num_resources++;
+                resources[1].flags = IORESOURCE_IRQ;
+                resources[1].start = irq;
+                resources[1].end = irq;
+        }
+}
+
+/*****************************************************************************
+ * UART
+ ****************************************************************************/
+static void __init uart_complete(
+        struct platform_device *orion_uart,
+        struct plat_serial8250_port *data,
+        struct resource *resources,
+        unsigned int membase,
+        resource_size_t mapbase,
+        unsigned int irq,
+        unsigned int uartclk)
+{
+        data->mapbase = mapbase;
+        data->membase = (void __iomem *)membase;
+        data->irq = irq;
+        data->uartclk = uartclk;
+        orion_uart->dev.platform_data = data;
+
+        fill_resources(orion_uart, resources, mapbase, 0xff, irq);
+        platform_device_register(orion_uart);
+}
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart0_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart0_resources[2];
+
+static struct platform_device orion_uart0 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+};
+
+void __init orion_uart0_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart1_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart1_resources[2];
+
+static struct platform_device orion_uart1 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM1,
+};
+
+void __init orion_uart1_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART2
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart2_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart2_resources[2];
+
+static struct platform_device orion_uart2 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM2,
+};
+
+void __init orion_uart2_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART3
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart3_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart3_resources[2];
+
+static struct platform_device orion_uart3 = {
+        .name                   = "serial8250",
+        .id                     = 3,
+};
+
+void __init orion_uart3_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * SoC RTC
+ ****************************************************************************/
+static struct resource orion_rtc_resource[2];
+
+void __init orion_rtc_init(unsigned long mapbase,
+                           unsigned long irq)
+{
+        orion_rtc_resource[0].start = mapbase;
+        orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
+        orion_rtc_resource[0].flags = IORESOURCE_MEM;
+        orion_rtc_resource[1].start = irq;
+        orion_rtc_resource[1].end = irq;
+        orion_rtc_resource[1].flags = IORESOURCE_IRQ;
+
+        platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
+}
+
+/*****************************************************************************
+ * GE
+ ****************************************************************************/
+static __init void ge_complete(
+        struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
+        struct mbus_dram_target_info *mbus_dram_info, int tclk,
+        struct resource *orion_ge_resource, unsigned long irq,
+        struct platform_device *orion_ge_shared,
+        struct mv643xx_eth_platform_data *eth_data,
+        struct platform_device *orion_ge)
+{
+        orion_ge_shared_data->dram = mbus_dram_info;
+        orion_ge_shared_data->t_clk = tclk;
+        orion_ge_resource->start = irq;
+        orion_ge_resource->end = irq;
+        eth_data->shared = orion_ge_shared;
+        orion_ge->dev.platform_data = eth_data;
+
+        platform_device_register(orion_ge_shared);
+        platform_device_register(orion_ge);
+}
+
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
+
+static struct resource orion_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+        }, {
+                .name   = "ge00 err irq",
+        },
+};
+
+static struct platform_device orion_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &orion_ge00_shared_data,
+        },
+};
+
+static struct resource orion_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = orion_ge00_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk,
+                    orion_ge00_resources, irq, &orion_ge00_shared,
+                    eth_data, &orion_ge00);
+}
+
+/*****************************************************************************
+ * GE01
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = {
+        .shared_smi     = &orion_ge00_shared,
+};
+
+static struct resource orion_ge01_shared_resources[] = {
+        {
+                .name   = "ge01 base",
+        }, {
+                .name   = "ge01 err irq",
+        },
+};
+
+static struct platform_device orion_ge01_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_ge01_shared_data,
+        },
+};
+
+static struct resource orion_ge01_resources[] = {
+        {
+                .name   = "ge01 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge01 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = orion_ge01_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk,
+                    orion_ge01_resources, irq, &orion_ge01_shared,
+                    eth_data, &orion_ge01);
+}
+
+/*****************************************************************************
+ * GE10
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = {
+        .shared_smi     = &orion_ge00_shared,
+};
+
+static struct resource orion_ge10_shared_resources[] = {
+        {
+                .name   = "ge10 base",
+        }, {
+                .name   = "ge10 err irq",
+        },
+};
+
+static struct platform_device orion_ge10_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_ge10_shared_data,
+        },
+};
+
+static struct resource orion_ge10_resources[] = {
+        {
+                .name   = "ge10 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge10 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 2,
+        .resource       = orion_ge10_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk,
+                    orion_ge10_resources, irq, &orion_ge10_shared,
+                    eth_data, &orion_ge10);
+}
+
+/*****************************************************************************
+ * GE11
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = {
+        .shared_smi     = &orion_ge00_shared,
+};
+
+static struct resource orion_ge11_shared_resources[] = {
+        {
+                .name   = "ge11 base",
+        }, {
+                .name   = "ge11 err irq",
+        },
+};
+
+static struct platform_device orion_ge11_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_ge11_shared_data,
+        },
+};
+
+static struct resource orion_ge11_resources[] = {
+        {
+                .name   = "ge11 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge11 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 2,
+        .resource       = orion_ge11_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk,
+                    orion_ge11_resources, irq, &orion_ge11_shared,
+                    eth_data, &orion_ge11);
+}
+
+/*****************************************************************************
+ * Ethernet switch
+ ****************************************************************************/
+static struct resource orion_switch_resources[] = {
+        {
+                .start  = 0,
+                .end    = 0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_switch_device = {
+        .name           = "dsa",
+        .id             = 0,
+        .num_resources  = 0,
+        .resource       = orion_switch_resources,
+};
+
+void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
+{
+        int i;
+
+        if (irq != NO_IRQ) {
+                orion_switch_resources[0].start = irq;
+                orion_switch_resources[0].end = irq;
+                orion_switch_device.num_resources = 1;
+        }
+
+        d->netdev = &orion_ge00.dev;
+        for (i = 0; i < d->nr_chips; i++)
+                d->chip[i].mii_bus = &orion_ge00_shared.dev;
+        orion_switch_device.dev.platform_data = d;
+
+        platform_device_register(&orion_switch_device);
+}
+
+/*****************************************************************************
+ * I2C
+ ****************************************************************************/
+static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource orion_i2c_resources[2];
+
+static struct platform_device orion_i2c = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &orion_i2c_pdata,
+        },
+};
+
+static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource orion_i2c_1_resources[2];
+
+static struct platform_device orion_i2c_1 = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_i2c_1_pdata,
+        },
+};
+
+void __init orion_i2c_init(unsigned long mapbase,
+                           unsigned long irq,
+                           unsigned long freq_m)
+{
+        orion_i2c_pdata.freq_m = freq_m;
+        fill_resources(&orion_i2c, orion_i2c_resources, mapbase,
+                       SZ_32 - 1, irq);
+        platform_device_register(&orion_i2c);
+}
+
+void __init orion_i2c_1_init(unsigned long mapbase,
+                             unsigned long irq,
+                             unsigned long freq_m)
+{
+        orion_i2c_1_pdata.freq_m = freq_m;
+        fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase,
+                       SZ_32 - 1, irq);
+        platform_device_register(&orion_i2c_1);
+}
+
+/*****************************************************************************
+ * SPI
+ ****************************************************************************/
+static struct orion_spi_info orion_spi_plat_data;
+static struct resource orion_spi_resources;
+
+static struct platform_device orion_spi = {
+        .name           = "orion_spi",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &orion_spi_plat_data,
+        },
+};
+
+static struct orion_spi_info orion_spi_1_plat_data;
+static struct resource orion_spi_1_resources;
+
+static struct platform_device orion_spi_1 = {
+        .name           = "orion_spi",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_spi_1_plat_data,
+        },
+};
+
+/* Note: The SPI silicon core does have interrupts. However the
+ * current Linux software driver does not use interrupts. */
+
+void __init orion_spi_init(unsigned long mapbase,
+                           unsigned long tclk)
+{
+        orion_spi_plat_data.tclk = tclk;
+        fill_resources(&orion_spi, &orion_spi_resources,
+                       mapbase, SZ_512 - 1, NO_IRQ);
+        platform_device_register(&orion_spi);
+}
+
+void __init orion_spi_1_init(unsigned long mapbase,
+                             unsigned long tclk)
+{
+        orion_spi_1_plat_data.tclk = tclk;
+        fill_resources(&orion_spi_1, &orion_spi_1_resources,
+                       mapbase, SZ_512 - 1, NO_IRQ);
+        platform_device_register(&orion_spi_1);
+}
+
+/*****************************************************************************
+ * Watchdog
+ ****************************************************************************/
+static struct orion_wdt_platform_data orion_wdt_data;
+
+static struct platform_device orion_wdt_device = {
+        .name           = "orion_wdt",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &orion_wdt_data,
+        },
+        .num_resources  = 0,
+};
+
+void __init orion_wdt_init(unsigned long tclk)
+{
+        orion_wdt_data.tclk = tclk;
+        platform_device_register(&orion_wdt_device);
+}
+
+/*****************************************************************************
+ * XOR
+ ****************************************************************************/
+static struct mv_xor_platform_shared_data orion_xor_shared_data;
+
+static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
+
+void __init orion_xor_init_channels(
+        struct mv_xor_platform_data *orion_xor0_data,
+        struct platform_device *orion_xor0_channel,
+        struct mv_xor_platform_data *orion_xor1_data,
+        struct platform_device *orion_xor1_channel)
+{
+        /*
+         * two engines can't do memset simultaneously, this limitation
+         * satisfied by removing memset support from one of the engines.
+         */
+        dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);
+        dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);
+        platform_device_register(orion_xor0_channel);
+
+        dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);
+        dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);
+        dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);
+        platform_device_register(orion_xor1_channel);
+}
+
+/*****************************************************************************
+ * XOR0
+ ****************************************************************************/
+static struct resource orion_xor0_shared_resources[] = {
+        {
+                .name   = "xor 0 low",
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 0 high",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device orion_xor0_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data = &orion_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(orion_xor0_shared_resources),
+        .resource       = orion_xor0_shared_resources,
+};
+
+static struct resource orion_xor00_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor00_data = {
+        .shared         = &orion_xor0_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor00_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(orion_xor00_resources),
+        .resource       = orion_xor00_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor00_data,
+        },
+};
+
+static struct resource orion_xor01_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor01_data = {
+        .shared         = &orion_xor0_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor01_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(orion_xor01_resources),
+        .resource       = orion_xor01_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor01_data,
+        },
+};
+
+void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1)
+{
+        orion_xor_shared_data.dram = mbus_dram_info;
+
+        orion_xor0_shared_resources[0].start = mapbase_low;
+        orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
+        orion_xor0_shared_resources[1].start = mapbase_high;
+        orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
+
+        orion_xor00_resources[0].start = irq_0;
+        orion_xor00_resources[0].end = irq_0;
+        orion_xor01_resources[0].start = irq_1;
+        orion_xor01_resources[0].end = irq_1;
+
+        platform_device_register(&orion_xor0_shared);
+
+        orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,
+                                &orion_xor01_data, &orion_xor01_channel);
+}
+
+/*****************************************************************************
+ * XOR1
+ ****************************************************************************/
+static struct resource orion_xor1_shared_resources[] = {
+        {
+                .name   = "xor 1 low",
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 1 high",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device orion_xor1_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data = &orion_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(orion_xor1_shared_resources),
+        .resource       = orion_xor1_shared_resources,
+};
+
+static struct resource orion_xor10_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor10_data = {
+        .shared         = &orion_xor1_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor10_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(orion_xor10_resources),
+        .resource       = orion_xor10_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor10_data,
+        },
+};
+
+static struct resource orion_xor11_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor11_data = {
+        .shared         = &orion_xor1_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor11_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(orion_xor11_resources),
+        .resource       = orion_xor11_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor11_data,
+        },
+};
+
+void __init orion_xor1_init(unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1)
+{
+        orion_xor1_shared_resources[0].start = mapbase_low;
+        orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
+        orion_xor1_shared_resources[1].start = mapbase_high;
+        orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
+
+        orion_xor10_resources[0].start = irq_0;
+        orion_xor10_resources[0].end = irq_0;
+        orion_xor11_resources[0].start = irq_1;
+        orion_xor11_resources[0].end = irq_1;
+
+        platform_device_register(&orion_xor1_shared);
+
+        orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,
+                                &orion_xor11_data, &orion_xor11_channel);
+}
+
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data orion_ehci_data = {
+        .phy_version    = EHCI_PHY_NA,
+};
+
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+
+
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource orion_ehci_resources[2];
+
+static struct platform_device orion_ehci = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &orion_ehci_data,
+        },
+};
+
+void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq)
+{
+        orion_ehci_data.dram = mbus_dram_info;
+        fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
+                       irq);
+
+        platform_device_register(&orion_ehci);
+}
+
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource orion_ehci_1_resources[2];
+
+static struct platform_device orion_ehci_1 = {
+        .name           = "orion-ehci",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &orion_ehci_data,
+        },
+};
+
+void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq)
+{
+        orion_ehci_data.dram = mbus_dram_info;
+        fill_resources(&orion_ehci_1, orion_ehci_1_resources,
+                       mapbase, SZ_4K - 1, irq);
+
+        platform_device_register(&orion_ehci_1);
+}
+
+/*****************************************************************************
+ * EHCI2
+ ****************************************************************************/
+static struct resource orion_ehci_2_resources[2];
+
+static struct platform_device orion_ehci_2 = {
+        .name           = "orion-ehci",
+        .id             = 2,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &orion_ehci_data,
+        },
+};
+
+void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq)
+{
+        orion_ehci_data.dram = mbus_dram_info;
+        fill_resources(&orion_ehci_2, orion_ehci_2_resources,
+                       mapbase, SZ_4K - 1, irq);
+
+        platform_device_register(&orion_ehci_2);
+}
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource orion_sata_resources[2] = {
+        {
+                .name   = "sata base",
+        }, {
+                .name   = "sata irq",
+        },
+};
+
+static struct platform_device orion_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq)
+{
+        sata_data->dram = mbus_dram_info;
+        orion_sata.dev.platform_data = sata_data;
+        fill_resources(&orion_sata, orion_sata_resources,
+                       mapbase, 0x5000 - 1, irq);
+
+        platform_device_register(&orion_sata);
+}
+
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+static struct resource orion_crypto_resources[] = {
+        {
+                .name   = "regs",
+        }, {
+                .name   = "crypto interrupt",
+        }, {
+                .name   = "sram",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device orion_crypto = {
+        .name           = "mv_crypto",
+        .id             = -1,
+};
+
+void __init orion_crypto_init(unsigned long mapbase,
+                              unsigned long srambase,
+                              unsigned long sram_size,
+                              unsigned long irq)
+{
+        fill_resources(&orion_crypto, orion_crypto_resources,
+                       mapbase, 0xffff, irq);
+        orion_crypto.num_resources = 3;
+        orion_crypto_resources[2].start = srambase;
+        orion_crypto_resources[2].end = srambase + sram_size - 1;
+
+        platform_device_register(&orion_crypto);
+}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index a431a138f40..5b4fffab1eb 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -321,59 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
  *        polarity    LEVEL          mask
  *
  ****************************************************************************/
-static void gpio_irq_ack(struct irq_data *d)
-{
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irqd_get_trigger_type(d);
-
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                int pin = d->irq - ochip->secondary_irq_base;
-
-                writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
-        }
-}
-
-static void gpio_irq_mask(struct irq_data *d)
-{
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irqd_get_trigger_type(d);
-        void __iomem *reg;
-        int pin;
-
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
-                reg = GPIO_EDGE_MASK(ochip);
-        else
-                reg = GPIO_LEVEL_MASK(ochip);
-
-        pin = d->irq - ochip->secondary_irq_base;
-
-        writel(readl(reg) & ~(1 << pin), reg);
-}
-
-static void gpio_irq_unmask(struct irq_data *d)
-{
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irqd_get_trigger_type(d);
-        void __iomem *reg;
-        int pin;
-
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
-                reg = GPIO_EDGE_MASK(ochip);
-        else
-                reg = GPIO_LEVEL_MASK(ochip);
-
-        pin = d->irq - ochip->secondary_irq_base;
-
-        writel(readl(reg) | (1 << pin), reg);
-}
 
 static int gpio_irq_set_type(struct irq_data *d, u32 type)
 {
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+        struct orion_gpio_chip *ochip = gc->private;
         int pin;
         u32 u;
 
-        pin = d->irq - ochip->secondary_irq_base;
+        pin = d->irq - gc->irq_base;
 
         u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
         if (!u) {
@@ -382,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
                 return -EINVAL;
         }
 
-        /*
-         * Set edge/level type.
-         */
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-        } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        } else {
-                printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
-                       d->irq, type);
+        type &= IRQ_TYPE_SENSE_MASK;
+        if (type == IRQ_TYPE_NONE)
                 return -EINVAL;
-        }
+
+        /* Check if we need to change chip and handler */
+        if (!(ct->type & type))
+                if (irq_setup_alt_chip(d, type))
+                        return -EINVAL;
 
         /*
          * Configure interrupt polarity.
@@ -425,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
         return 0;
 }
 
-struct irq_chip orion_gpio_irq_chip = {
-        .name           = "orion_gpio_irq",
-        .irq_ack        = gpio_irq_ack,
-        .irq_mask       = gpio_irq_mask,
-        .irq_unmask     = gpio_irq_unmask,
-        .irq_set_type   = gpio_irq_set_type,
-};
-
 void __init orion_gpio_init(int gpio_base, int ngpio,
                             u32 base, int mask_offset, int secondary_irq_base)
 {
         struct orion_gpio_chip *ochip;
-        int i;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
                 return;
@@ -471,15 +417,29 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
         writel(0, GPIO_EDGE_MASK(ochip));
         writel(0, GPIO_LEVEL_MASK(ochip));
 
-        for (i = 0; i < ngpio; i++) {
-                unsigned int irq = secondary_irq_base + i;
-
-                irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
-                                         handle_level_irq);
-                irq_set_chip_data(irq, ochip);
-                irq_set_status_flags(irq, IRQ_LEVEL);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
+                                    ochip->base, handle_level_irq);
+        gc->private = ochip;
+
+        ct = gc->chip_types;
+        ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_set_type = gpio_irq_set_type;
+
+        ct++;
+        ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+        ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
+        ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_set_type = gpio_irq_set_type;
+        ct->handler = handle_edge_irq;
+
+        irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 }
 
 void orion_gpio_irq_handler(int pinoff)
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
new file mode 100644
index 00000000000..a63c357e2ab
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/plat-orion/include/plat/common.h
+ *
+ * Marvell Orion SoC common setup code used by different mach-/common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_COMMON_H
+#include <linux/mv643xx_eth.h>
+
+struct dsa_platform_data;
+
+void __init orion_uart0_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_uart1_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_uart2_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_uart3_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_rtc_init(unsigned long mapbase,
+                           unsigned long irq);
+
+void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge00_switch_init(struct dsa_platform_data *d,
+                                   int irq);
+void __init orion_i2c_init(unsigned long mapbase,
+                           unsigned long irq,
+                           unsigned long freq_m);
+
+void __init orion_i2c_1_init(unsigned long mapbase,
+                             unsigned long irq,
+                             unsigned long freq_m);
+
+void __init orion_spi_init(unsigned long mapbase,
+                           unsigned long tclk);
+
+void __init orion_spi_1_init(unsigned long mapbase,
+                             unsigned long tclk);
+
+void __init orion_wdt_init(unsigned long tclk);
+
+void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1);
+
+void __init orion_xor1_init(unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1);
+
+void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq);
+
+void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq);
+
+void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq);
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq);
+
+void __init orion_crypto_init(unsigned long mapbase,
+                              unsigned long srambase,
+                              unsigned long sram_size,
+                              unsigned long irq);
+#endif
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 5578b9803fc..3075b9fdde8 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
 /*
  * GPIO interrupt handling.
  */
-extern struct irq_chip orion_gpio_irq_chip;
 void orion_gpio_irq_handler(int irqoff);
 
 
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
new file mode 100644
index 00000000000..723adce99f4
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/plat-orion/include/plat/mpp.h
+ *
+ * Marvell Orion SoC MPP handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_MPP_H
+#define __PLAT_MPP_H
+
+#define MPP_NUM(x)      ((x) & 0xff)
+#define MPP_SEL(x)      (((x) >> 8) & 0xf)
+
+/* This is the generic MPP macro, without any variant information.
+   Each machine architecture is expected to extend this with further
+   bit fields indicating which MPP configurations are valid for a
+   specific variant. */
+
+#define GENERIC_MPP(_num, _sel, _in, _out) ( \
+        /* MPP number */                ((_num) & 0xff) | \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
+        /* may be input signal */       ((!!(_in)) << 12) | \
+        /* may be output signal */      ((!!(_out)) << 13))
+
+#define MPP_INPUT_MASK          GENERIC_MPP(0, 0x0, 1, 0)
+#define MPP_OUTPUT_MASK         GENERIC_MPP(0, 0x0, 0, 1)
+
+void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
+                           unsigned int mpp_max, unsigned int dev_bus);
+
+#endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index d8d638e09f8..2d5b9c1ef38 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -14,52 +14,21 @@
 #include <linux/io.h>
 #include <plat/irq.h>
 
-static void orion_irq_mask(struct irq_data *d)
-{
-        void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
-        u32 mask;
-
-        mask = readl(maskaddr);
-        mask &= ~(1 << (d->irq & 31));
-        writel(mask, maskaddr);
-}
-
-static void orion_irq_unmask(struct irq_data *d)
-{
-        void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
-        u32 mask;
-
-        mask = readl(maskaddr);
-        mask |= 1 << (d->irq & 31);
-        writel(mask, maskaddr);
-}
-
-static struct irq_chip orion_irq_chip = {
-        .name           = "orion_irq",
-        .irq_mask       = orion_irq_mask,
-        .irq_mask_ack   = orion_irq_mask,
-        .irq_unmask     = orion_irq_unmask,
-};
-
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
-        unsigned int i;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         /*
          * Mask all interrupts initially.
          */
         writel(0, maskaddr);
 
-        /*
-         * Register IRQ sources.
-         */
-        for (i = 0; i < 32; i++) {
-                unsigned int irq = irq_start + i;
-
-                irq_set_chip_and_handler(irq, &orion_irq_chip,
-                                         handle_level_irq);
-                irq_set_chip_data(irq, maskaddr);
-                irq_set_status_flags(irq, IRQ_LEVEL);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
+                                    handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 }
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
new file mode 100644
index 00000000000..91553432711
--- /dev/null
+++ b/arch/arm/plat-orion/mpp.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/plat-orion/mpp.c
+ *
+ * MPP functions for Marvell orion SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <plat/mpp.h>
+
+/* Address of the ith MPP control register */
+static __init unsigned long mpp_ctrl_addr(unsigned int i,
+                                          unsigned long dev_bus)
+{
+        return dev_bus + (i) * 4;
+}
+
+
+void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
+                           unsigned int mpp_max, unsigned int dev_bus)
+{
+        unsigned int mpp_nr_regs = (1 + mpp_max/8);
+        u32 mpp_ctrl[mpp_nr_regs];
+        int i;
+
+        printk(KERN_DEBUG "initial MPP regs:");
+        for (i = 0; i < mpp_nr_regs; i++) {
+                mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
+                printk(" %08x", mpp_ctrl[i]);
+        }
+        printk("\n");
+
+        for ( ; *mpp_list; mpp_list++) {
+                unsigned int num = MPP_NUM(*mpp_list);
+                unsigned int sel = MPP_SEL(*mpp_list);
+                int shift, gpio_mode;
+
+                if (num > mpp_max) {
+                        printk(KERN_ERR "orion_mpp_conf: invalid MPP "
+                                        "number (%u)\n", num);
+                        continue;
+                }
+                if (variant_mask & !(*mpp_list & variant_mask)) {
+                        printk(KERN_WARNING
+                               "orion_mpp_conf: requested MPP%u config "
+                               "unavailable on this hardware\n", num);
+                        continue;
+                }
+
+                shift = (num & 7) << 2;
+                mpp_ctrl[num / 8] &= ~(0xf << shift);
+                mpp_ctrl[num / 8] |= sel << shift;
+
+                gpio_mode = 0;
+                if (*mpp_list & MPP_INPUT_MASK)
+                        gpio_mode |= GPIO_INPUT_OK;
+                if (*mpp_list & MPP_OUTPUT_MASK)
+                        gpio_mode |= GPIO_OUTPUT_OK;
+                if (sel != 0)
+                        gpio_mode = 0;
+                orion_gpio_set_valid(num, gpio_mode);
+        }
+
+        printk(KERN_DEBUG "  final MPP regs:");
+        for (i = 0; i < mpp_nr_regs; i++) {
+                writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
+                printk(" %08x", mpp_ctrl[i]);
+        }
+        printk("\n");
+}
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 75f65647124..89e68e07b0a 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -434,7 +434,7 @@ typedef unsigned long mfp_cfg_t;
  *
  * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
  * represents a range of MFP pins from "start" to "end", with the offset
- * begining at "offset", to define a single pin, let "end" = -1.
+ * beginning at "offset", to define a single pin, let "end" = -1.
  *
  * use
  *
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index c2064c30871..0291bd6e236 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_S3C24XX_DCLK)	+= clock-dclk.o
 obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpu-freq.o
 obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
 
-# Architecture dependant builds
+# Architecture dependent builds
 
 obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
index eea75ff81d1..b3d3d027899 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -455,7 +455,7 @@ static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
 
         /* whilst we will be called later on, we try and re-set the
          * cpu frequencies as soon as possible so that we do not end
-         * up resuming devices and then immediatley having to re-set
+         * up resuming devices and then immediately having to re-set
          * a number of settings once these devices have restarted.
          *
          * as a note, it is expected devices are not used until they
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 6ad274e7593..27ea852e337 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -557,7 +557,7 @@ s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
                 break;
 
         case S3C2410_DMALOAD_1LOADED_1RUNNING:
-                /* I belive in this case we do not have anything to do
+                /* I believe in this case we do not have anything to do
                  * until the next buffer comes along, and we turn off the
                  * reload */
                 return;
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 46dd078147d..135abda31c9 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -41,72 +41,11 @@ struct s5p_gpioint_bank {
 
 LIST_HEAD(banks);
 
-static int s5p_gpioint_get_offset(struct irq_data *data)
+static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
 {
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        return data->irq - chip->irq_base;
-}
-
-static void s5p_gpioint_ack(struct irq_data *data)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, pend_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        pend_offset = REG_OFFSET(group);
-
-        value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
-        value |= BIT(offset);
-        __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
-}
-
-static void s5p_gpioint_mask(struct irq_data *data)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, mask_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        mask_offset = REG_OFFSET(group);
-
-        value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-        value |= BIT(offset);
-        __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-}
-
-static void s5p_gpioint_unmask(struct irq_data *data)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, mask_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        mask_offset = REG_OFFSET(group);
-
-        value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-        value &= ~BIT(offset);
-        __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-}
-
-static void s5p_gpioint_mask_ack(struct irq_data *data)
-{
-        s5p_gpioint_mask(data);
-        s5p_gpioint_ack(data);
-}
-
-static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, con_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        con_offset = REG_OFFSET(group);
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = gc->chip_types;
+        unsigned int shift = (d->irq - gc->irq_base) << 2;
 
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
@@ -130,23 +69,12 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
                 return -EINVAL;
         }
 
-        value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
-        value &= ~(0x7 << (offset * 0x4));
-        value |= (type << (offset * 0x4));
-        __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
-
+        gc->type_cache &= ~(0x7 << shift);
+        gc->type_cache |= type << shift;
+        writel(gc->type_cache, gc->reg_base + ct->regs.type);
         return 0;
 }
 
-static struct irq_chip s5p_gpioint = {
-        .name           = "s5p_gpioint",
-        .irq_ack        = s5p_gpioint_ack,
-        .irq_mask       = s5p_gpioint_mask,
-        .irq_mask_ack   = s5p_gpioint_mask_ack,
-        .irq_unmask     = s5p_gpioint_unmask,
-        .irq_set_type   = s5p_gpioint_set_type,
-};
-
 static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 {
         struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
@@ -179,9 +107,10 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
 {
         static int used_gpioint_groups = 0;
-        int irq, group = chip->group;
-        int i;
+        int group = chip->group;
         struct s5p_gpioint_bank *bank = NULL;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
                 return -ENOMEM;
@@ -208,22 +137,31 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
         }
 
         /*
-         * chained GPIO irq has been sucessfully registered, allocate new gpio
+         * chained GPIO irq has been successfully registered, allocate new gpio
          * int group and assign irq nubmers
          */
-
         chip->irq_base = S5P_GPIOINT_BASE +
                          used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
         used_gpioint_groups++;
 
         bank->chips[group - bank->start] = chip;
-        for (i = 0; i < chip->chip.ngpio; i++) {
-                irq = chip->irq_base + i;
-                irq_set_chip(irq, &s5p_gpioint);
-                irq_set_handler_data(irq, chip);
-                irq_set_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+
+        gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
+                                    (void __iomem *)GPIO_BASE(chip),
+                                    handle_level_irq);
+        if (!gc)
+                return -ENOMEM;
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+        ct->chip.irq_set_type = s5p_gpioint_set_type,
+        ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
+        ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
+        ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
+        irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
+                               IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
         return 0;
 }
 
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index 5560b12035d..a97c08957f4 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -64,11 +64,7 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
                 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
 #endif
 
-        s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
-        s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
-        s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
-        s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
-        s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
+        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 
         s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
 }
diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
index d592b6304b4..d15dc47b0e3 100644
--- a/arch/arm/plat-s5p/pm.c
+++ b/arch/arm/plat-s5p/pm.c
@@ -19,17 +19,6 @@
 
 #define PFX "s5p pm: "
 
-/* s3c_pm_check_resume_pin
- *
- * check to see if the pin is configured correctly for sleep mode, and
- * make any necessary adjustments if it is not
-*/
-
-static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
-{
-        /* nothing here yet */
-}
-
 /* s3c_pm_configure_extint
  *
  * configure all external interrupt pins
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 9a82b887491..983c578b827 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -21,7 +21,7 @@ struct clk;
  * @set_parent: set the clock's parent, see clk_set_parent().
  *
  * Group the common clock implementations together so that we
- * don't have to keep setting the same fiels again. We leave
+ * don't have to keep setting the same fields again. We leave
  * enable in struct clk.
  *
  * Adding an extra layer of indirection into the process should
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 5603db0b79b..3ad8386599c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -114,7 +114,7 @@ extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
  * of control per GPIO, generally in the form of:
  *      0000 = Input
  *      0001 = Output
- *      others = Special functions (dependant on bank)
+ *      others = Special functions (dependent on bank)
  *
  * Note, since the code to deal with the case where there are two control
  * registers instead of one, we do not have a separate set of functions for
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 5e04fa6eda7..1762dcb4cb9 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -125,7 +125,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
  *
  * These values control the state of the weak pull-{up,down} resistors
  * available on most pins on the S3C series. Not all chips support both
- * up or down settings, and it may be dependant on the chip that is being
+ * up or down settings, and it may be dependent on the chip that is being
  * used to whether the particular mode is available.
  */
 #define S3C_GPIO_PULL_NONE      ((__force s3c_gpio_pull_t)0x00)
@@ -138,7 +138,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
  * @pull: The configuration for the pull resistor.
  *
  * This function sets the state of the pull-{up,down} resistor for the
- * specified pin. It will return 0 if successfull, or a negative error
+ * specified pin. It will return 0 if successful, or a negative error
  * code if the pin cannot support the requested pull setting.
  *
  * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP.
@@ -202,7 +202,7 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
  * @drvstr: The new value of the driver strength
  *
  * This function sets the driver strength value for the specified pin.
- * It will return 0 if successfull, or a negative error code if the pin
+ * It will return 0 if successful, or a negative error code if the pin
  * cannot support the requested setting.
 */
 extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index dac35d0a711..8cad4cf19c3 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -108,7 +108,7 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
  * of control per GPIO, generally in the form of:
  * 0000 = Input
  * 0001 = Output
- * others = Special functions (dependant on bank)
+ * others = Special functions (dependent on bank)
  *
  * Note, since the code to deal with the case where there are two control
  * registers instead of one, we do not have a separate set of function
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
index a90b53431b5..5b9c42fd32d 100644
--- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
@@ -10,4 +10,4 @@
  * published by the Free Software Foundation.
 */
 
-extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer);
+extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq);
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index b0bdf16549d..058e09654fe 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -57,7 +57,7 @@ enum clk_types {
  * @cfg_gpio: Configure the GPIO for a specific card bit-width
  * @cfg_card: Configure the interface for a specific card and speed. This
  *            is necessary the controllers and/or GPIO blocks require the
- *            changing of driver-strength and other controls dependant on
+ *            changing of driver-strength and other controls dependent on
  *            the card and speed of operation.
  *
  * Initialisation data specific to either the machine or the platform
@@ -108,7 +108,7 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
 extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
 extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata;
 
-/* Helper function availablity */
+/* Helper function availability */
 
 extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 7d6ed7263d5..ee48e12a1e7 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -18,8 +18,8 @@ typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 
 /* uart setup */
 
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
+unsigned int fifo_mask;
+unsigned int fifo_max;
 
 /* forward declerations */
 
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 4d4e571af55..32582c0958e 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -27,60 +27,6 @@
 /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
  * are consecutive when looking up the interrupt in the demux routines.
  */
-
-static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
-{
-        struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
-        return uirq->regs;
-}
-
-static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
-{
-        return irq & 3;
-}
-
-static void s3c_irq_uart_mask(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-        u32 reg;
-
-        reg = __raw_readl(regs + S3C64XX_UINTM);
-        reg |= (1 << bit);
-        __raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_maskack(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-        u32 reg;
-
-        reg = __raw_readl(regs + S3C64XX_UINTM);
-        reg |= (1 << bit);
-        __raw_writel(reg, regs + S3C64XX_UINTM);
-        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
-static void s3c_irq_uart_unmask(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-        u32 reg;
-
-        reg = __raw_readl(regs + S3C64XX_UINTM);
-        reg &= ~(1 << bit);
-        __raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_ack(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-
-        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
 static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
 {
         struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
@@ -97,30 +43,25 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(base + 3);
 }
 
-static struct irq_chip s3c_irq_uart = {
-        .name           = "s3c-uart",
-        .irq_mask       = s3c_irq_uart_mask,
-        .irq_unmask     = s3c_irq_uart_unmask,
-        .irq_mask_ack   = s3c_irq_uart_maskack,
-        .irq_ack        = s3c_irq_uart_ack,
-};
-
 static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
 {
         void __iomem *reg_base = uirq->regs;
-        unsigned int irq;
-        int offs;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         /* mask all interrupts at the start. */
         __raw_writel(0xf, reg_base + S3C64XX_UINTM);
 
-        for (offs = 0; offs < 3; offs++) {
-                irq = uirq->base_irq + offs;
-
-                irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
-                irq_set_chip_data(irq, uirq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
+                                    handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+        ct->regs.ack = S3C64XX_UINTP;
+        ct->regs.mask = S3C64XX_UINTM;
+        irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 
         irq_set_handler_data(uirq->parent_irq, uirq);
         irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index d6ad66ab929..a607546ddbd 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -28,60 +28,43 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 }
 
 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
-
-static void s3c_irq_timer_mask(struct irq_data *data)
-{
-        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        u32 mask = (u32)data->chip_data;
-
-        reg &= 0x1f;  /* mask out pending interrupts */
-        reg &= ~mask;
-        __raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static void s3c_irq_timer_unmask(struct irq_data *data)
+static void s3c_irq_timer_ack(struct irq_data *d)
 {
-        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        u32 mask = (u32)data->chip_data;
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        u32 mask = (1 << 5) << (d->irq - gc->irq_base);
 
-        reg &= 0x1f;  /* mask out pending interrupts */
-        reg |= mask;
-        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+        irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
 }
 
-static void s3c_irq_timer_ack(struct irq_data *data)
-{
-        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        u32 mask = (u32)data->chip_data;
-
-        reg &= 0x1f;
-        reg |= mask << 5;
-        __raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static struct irq_chip s3c_irq_timer = {
-        .name           = "s3c-timer",
-        .irq_mask       = s3c_irq_timer_mask,
-        .irq_unmask     = s3c_irq_timer_unmask,
-        .irq_ack        = s3c_irq_timer_ack,
-};
-
 /**
  * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
- * @parent_irq: The parent IRQ on the VIC for the timer.
- * @timer_irq: The IRQ to be used for the timer.
+ * @num: Number of timers to initialize
+ * @timer_irq: Base IRQ number to be used for the timers.
  *
  * Register the necessary IRQ chaining and support for the timer IRQs
  * chained of the VIC.
  */
-void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
-                                   unsigned int timer_irq)
+void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
 {
+        unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+                                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
+        struct irq_chip_generic *s3c_tgc;
+        struct irq_chip_type *ct;
+        unsigned int i;
 
-        irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
-        irq_set_handler_data(parent_irq, (void *)timer_irq);
+        s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
+                                         S3C64XX_TINT_CSTAT, handle_level_irq);
+        ct = s3c_tgc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_ack = s3c_irq_timer_ack;
+        irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+        /* Clear the upper bits of the mask_cache*/
+        s3c_tgc->mask_cache &= 0x1f;
 
-        irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq);
-        irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
-        set_irq_flags(timer_irq, IRQF_VALID);
+        for (i = 0; i < num; i++, timer_irq++) {
+                irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
+                irq_set_handler_data(pirq[i], (void *)timer_irq);
+        }
 }
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c
index e4baf76f374..6b733fafe7c 100644
--- a/arch/arm/plat-samsung/pm-check.c
+++ b/arch/arm/plat-samsung/pm-check.c
@@ -164,7 +164,6 @@ static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
  */
 static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
 {
-        void *save_at = phys_to_virt(s3c_sleep_save_phys);
         unsigned long addr;
         unsigned long left;
         void *stkpage;
@@ -192,11 +191,6 @@ static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
                         goto skip_check;
                 }
 
-                if (in_region(ptr, left, save_at, 32*4 )) {
-                        S3C_PMDBG("skipping %08lx, has save block in\n", addr);
-                        goto skip_check;
-                }
-
                 /* calculate and check the checksum */
 
                 calc = crc32_le(~0, ptr, left);
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index d5b58d31903..5c0a440d6e1 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -214,8 +214,9 @@ void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
  *
  * print any IRQs asserted at resume time (ie, we woke from)
 */
-static void s3c_pm_show_resume_irqs(int start, unsigned long which,
-                                    unsigned long mask)
+static void __maybe_unused s3c_pm_show_resume_irqs(int start,
+                                                   unsigned long which,
+                                                   unsigned long mask)
 {
         int i;
 
diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c
index b4ff8d74ac4..f85638c6f5a 100644
--- a/arch/arm/plat-samsung/s3c-pl330.c
+++ b/arch/arm/plat-samsung/s3c-pl330.c
@@ -68,7 +68,7 @@ struct s3c_pl330_xfer {
  * @req: Two requests to communicate with the PL330 engine.
  * @callback_fn: Callback function to the client.
  * @rqcfg: Channel configuration for the xfers.
- * @xfer_head: Pointer to the xfer to be next excecuted.
+ * @xfer_head: Pointer to the xfer to be next executed.
  * @dmac: Pointer to the DMAC that manages this channel, NULL if the
  *      channel is available to be acquired.
  * @client: Client of this channel. NULL if the
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index 2ae6606930a..fcc0d0ad4a1 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -89,7 +89,7 @@ struct rate_config {
  * @sibling: node for list of clocks having same parents
  * @private_data: clock specific private data
  * @node: list to maintain clocks linearly
- * @cl: clocklook up assoicated with this clock
+ * @cl: clocklook up associated with this clock
  * @dent: object for debugfs
  */
 struct clk {
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index bbf3da012af..f74695075e6 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -78,6 +78,14 @@ static void vfp_thread_exit(struct thread_info *thread)
         put_cpu();
 }
 
+static void vfp_thread_copy(struct thread_info *thread)
+{
+        struct thread_info *parent = current_thread_info();
+
+        vfp_sync_hwstate(parent);
+        thread->vfpstate = parent->vfpstate;
+}
+
 /*
  * When this function is called with the following 'cmd's, the following
  * is true while this function is being run:
@@ -104,12 +112,17 @@ static void vfp_thread_exit(struct thread_info *thread)
 static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 {
         struct thread_info *thread = v;
+        u32 fpexc;
+#ifdef CONFIG_SMP
+        unsigned int cpu;
+#endif
 
-        if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
-                u32 fpexc = fmrx(FPEXC);
+        switch (cmd) {
+        case THREAD_NOTIFY_SWITCH:
+                fpexc = fmrx(FPEXC);
 
 #ifdef CONFIG_SMP
-                unsigned int cpu = thread->cpu;
+                cpu = thread->cpu;
 
                 /*
                  * On SMP, if VFP is enabled, save the old state in
@@ -134,13 +147,20 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
                  * old state.
                  */
                 fmxr(FPEXC, fpexc & ~FPEXC_EN);
-                return NOTIFY_DONE;
-        }
+                break;
 
-        if (cmd == THREAD_NOTIFY_FLUSH)
+        case THREAD_NOTIFY_FLUSH:
                 vfp_thread_flush(thread);
-        else
+                break;
+
+        case THREAD_NOTIFY_EXIT:
                 vfp_thread_exit(thread);
+                break;
+
+        case THREAD_NOTIFY_COPY:
+                vfp_thread_copy(thread);
+                break;
+        }
 
         return NOTIFY_DONE;
 }