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-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index e9de5dfd94e..c2102a312bc 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1913,9 +1913,7 @@ struct clk_ops tegra30_periph_clk_ops = {
1913static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) 1913static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
1914{ 1914{
1915 struct clk *d = clk_get_sys(NULL, "pll_d"); 1915 struct clk *d = clk_get_sys(NULL, "pll_d");
1916 /* The DSIB parent selection bit is in PLLD base 1916 /* The DSIB parent selection bit is in PLLD base register */
1917 register - can not do direct r-m-w, must be
1918 protected by PLLD lock */
1919 tegra_clk_cfg_ex( 1917 tegra_clk_cfg_ex(
1920 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); 1918 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
1921 1919