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-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/configs/ag5evm_defconfig83
-rw-r--r--arch/arm/configs/mackerel_defconfig138
-rw-r--r--arch/arm/mach-shmobile/Kconfig35
-rw-r--r--arch/arm/mach-shmobile/Makefile15
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c314
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c23
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c1199
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c356
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro-gic.S89
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro-intc.S61
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro.S52
-rw-r--r--arch/arm/mach-shmobile/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h2
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h467
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c267
-rw-r--r--arch/arm/mach-shmobile/pfc-sh73a0.c2746
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c10
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c412
-rw-r--r--arch/arm/mm/Kconfig2
21 files changed, 6222 insertions, 71 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a3fb23be87f..3b7be793d96 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -632,9 +632,14 @@ config ARCH_MSM
632 (clock and power control, etc). 632 (clock and power control, etc).
633 633
634config ARCH_SHMOBILE 634config ARCH_SHMOBILE
635 bool "Renesas SH-Mobile" 635 bool "Renesas SH-Mobile / R-Mobile"
636 select HAVE_CLK
637 select CLKDEV_LOOKUP
638 select GENERIC_CLOCKEVENTS
639 select NO_IOPORT
640 select SPARSE_IRQ
636 help 641 help
637 Support for Renesas's SH-Mobile ARM platforms 642 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
638 643
639config ARCH_RPC 644config ARCH_RPC
640 bool "RiscPC" 645 bool "RiscPC"
diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig
new file mode 100644
index 00000000000..2b9cf56db36
--- /dev/null
+++ b/arch/arm/configs/ag5evm_defconfig
@@ -0,0 +1,83 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_NAMESPACES=y
7# CONFIG_UTS_NS is not set
8# CONFIG_IPC_NS is not set
9# CONFIG_USER_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_INITRAMFS_SOURCE=""
13CONFIG_EMBEDDED=y
14CONFIG_SLAB=y
15# CONFIG_BLK_DEV_BSG is not set
16# CONFIG_IOSCHED_DEADLINE is not set
17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_SHMOBILE=y
19CONFIG_ARCH_SH73A0=y
20CONFIG_MACH_AG5EVM=y
21CONFIG_MEMORY_SIZE=0x10000000
22CONFIG_CPU_BPREDICT_DISABLE=y
23CONFIG_ARM_ERRATA_430973=y
24CONFIG_ARM_ERRATA_458693=y
25CONFIG_NO_HZ=y
26CONFIG_AEABI=y
27# CONFIG_OABI_COMPAT is not set
28CONFIG_HIGHMEM=y
29CONFIG_ZBOOT_ROM_TEXT=0x0
30CONFIG_ZBOOT_ROM_BSS=0x0
31CONFIG_CMDLINE="console=tty0 console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
32CONFIG_CMDLINE_FORCE=y
33CONFIG_KEXEC=y
34# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
35CONFIG_PM=y
36# CONFIG_SUSPEND is not set
37CONFIG_PM_RUNTIME=y
38CONFIG_NET=y
39CONFIG_PACKET=y
40CONFIG_UNIX=y
41CONFIG_INET=y
42# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET_XFRM_MODE_BEET is not set
45# CONFIG_INET_LRO is not set
46# CONFIG_INET_DIAG is not set
47# CONFIG_IPV6 is not set
48# CONFIG_WIRELESS is not set
49CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
50# CONFIG_BLK_DEV is not set
51CONFIG_NETDEVICES=y
52CONFIG_NET_ETHERNET=y
53CONFIG_SMSC911X=y
54# CONFIG_NETDEV_1000 is not set
55# CONFIG_NETDEV_10000 is not set
56# CONFIG_WLAN is not set
57CONFIG_INPUT_SPARSEKMAP=y
58# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
59CONFIG_INPUT_EVDEV=y
60# CONFIG_INPUT_KEYBOARD is not set
61# CONFIG_INPUT_MOUSE is not set
62CONFIG_SERIAL_SH_SCI=y
63CONFIG_SERIAL_SH_SCI_NR_UARTS=9
64CONFIG_SERIAL_SH_SCI_CONSOLE=y
65# CONFIG_LEGACY_PTYS is not set
66# CONFIG_HW_RANDOM is not set
67CONFIG_I2C=y
68CONFIG_I2C_SH_MOBILE=y
69# CONFIG_HWMON is not set
70# CONFIG_MFD_SUPPORT is not set
71CONFIG_FB=y
72CONFIG_FB_SH_MOBILE_LCDC=y
73CONFIG_FRAMEBUFFER_CONSOLE=y
74CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
75# CONFIG_HID_SUPPORT is not set
76# CONFIG_USB_SUPPORT is not set
77# CONFIG_DNOTIFY is not set
78# CONFIG_INOTIFY_USER is not set
79CONFIG_TMPFS=y
80# CONFIG_MISC_FILESYSTEMS is not set
81CONFIG_MAGIC_SYSRQ=y
82CONFIG_DEBUG_KERNEL=y
83# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
new file mode 100644
index 00000000000..306a2e2d362
--- /dev/null
+++ b/arch/arm/configs/mackerel_defconfig
@@ -0,0 +1,138 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6# CONFIG_UTS_NS is not set
7# CONFIG_IPC_NS is not set
8# CONFIG_USER_NS is not set
9# CONFIG_PID_NS is not set
10# CONFIG_NET_NS is not set
11CONFIG_SLAB=y
12CONFIG_MODULES=y
13CONFIG_MODULE_UNLOAD=y
14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set
16# CONFIG_IOSCHED_CFQ is not set
17CONFIG_ARCH_SHMOBILE=y
18CONFIG_ARCH_SH7372=y
19CONFIG_MACH_MACKEREL=y
20CONFIG_MEMORY_SIZE=0x10000000
21CONFIG_AEABI=y
22# CONFIG_OABI_COMPAT is not set
23CONFIG_FORCE_MAX_ZONEORDER=15
24CONFIG_ZBOOT_ROM_TEXT=0x0
25CONFIG_ZBOOT_ROM_BSS=0x0
26CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp memchunk.vpu=64m memchunk.veu0=8m memchunk.spu0=2m mem=240m"
27CONFIG_KEXEC=y
28# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
29CONFIG_PM=y
30CONFIG_PM_RUNTIME=y
31CONFIG_NET=y
32CONFIG_PACKET=y
33CONFIG_UNIX=y
34CONFIG_INET=y
35CONFIG_IP_MULTICAST=y
36CONFIG_IP_PNP=y
37CONFIG_IP_PNP_DHCP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_IPV6 is not set
42# CONFIG_WIRELESS is not set
43CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
44# CONFIG_FIRMWARE_IN_KERNEL is not set
45CONFIG_MTD=y
46CONFIG_MTD_CONCAT=y
47CONFIG_MTD_PARTITIONS=y
48CONFIG_MTD_CHAR=y
49CONFIG_MTD_BLOCK=y
50CONFIG_MTD_CFI=y
51CONFIG_MTD_CFI_ADV_OPTIONS=y
52CONFIG_MTD_CFI_INTELEXT=y
53CONFIG_MTD_PHYSMAP=y
54CONFIG_MTD_ARM_INTEGRATOR=y
55CONFIG_MTD_BLOCK2MTD=y
56CONFIG_SCSI=y
57CONFIG_BLK_DEV_SD=y
58# CONFIG_SCSI_LOWLEVEL is not set
59CONFIG_NETDEVICES=y
60CONFIG_NET_ETHERNET=y
61CONFIG_SMSC911X=y
62# CONFIG_NETDEV_1000 is not set
63# CONFIG_NETDEV_10000 is not set
64# CONFIG_WLAN is not set
65# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
66# CONFIG_INPUT_KEYBOARD is not set
67# CONFIG_INPUT_MOUSE is not set
68CONFIG_SERIAL_SH_SCI=y
69CONFIG_SERIAL_SH_SCI_NR_UARTS=8
70CONFIG_SERIAL_SH_SCI_CONSOLE=y
71# CONFIG_LEGACY_PTYS is not set
72# CONFIG_HW_RANDOM is not set
73# CONFIG_HWMON is not set
74# CONFIG_MFD_SUPPORT is not set
75CONFIG_FB=y
76CONFIG_FB_MODE_HELPERS=y
77CONFIG_FB_SH_MOBILE_LCDC=y
78CONFIG_FRAMEBUFFER_CONSOLE=y
79CONFIG_LOGO=y
80# CONFIG_LOGO_LINUX_MONO is not set
81# CONFIG_LOGO_LINUX_CLUT224 is not set
82# CONFIG_HID_SUPPORT is not set
83# CONFIG_USB_SUPPORT is not set
84CONFIG_EXT2_FS=y
85CONFIG_EXT2_FS_XATTR=y
86CONFIG_EXT2_FS_POSIX_ACL=y
87CONFIG_EXT2_FS_SECURITY=y
88CONFIG_EXT2_FS_XIP=y
89CONFIG_EXT3_FS=y
90# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
91CONFIG_EXT3_FS_POSIX_ACL=y
92CONFIG_EXT3_FS_SECURITY=y
93# CONFIG_DNOTIFY is not set
94# CONFIG_INOTIFY_USER is not set
95CONFIG_MSDOS_FS=y
96CONFIG_VFAT_FS=y
97CONFIG_TMPFS=y
98# CONFIG_MISC_FILESYSTEMS is not set
99CONFIG_NFS_FS=y
100CONFIG_NFS_V3=y
101CONFIG_NFS_V3_ACL=y
102CONFIG_NFS_V4=y
103CONFIG_NFS_V4_1=y
104CONFIG_ROOT_NFS=y
105CONFIG_NLS_CODEPAGE_437=y
106CONFIG_NLS_CODEPAGE_737=y
107CONFIG_NLS_CODEPAGE_775=y
108CONFIG_NLS_CODEPAGE_850=y
109CONFIG_NLS_CODEPAGE_852=y
110CONFIG_NLS_CODEPAGE_855=y
111CONFIG_NLS_CODEPAGE_857=y
112CONFIG_NLS_CODEPAGE_860=y
113CONFIG_NLS_CODEPAGE_861=y
114CONFIG_NLS_CODEPAGE_862=y
115CONFIG_NLS_CODEPAGE_863=y
116CONFIG_NLS_CODEPAGE_864=y
117CONFIG_NLS_CODEPAGE_865=y
118CONFIG_NLS_CODEPAGE_866=y
119CONFIG_NLS_CODEPAGE_869=y
120CONFIG_NLS_ISO8859_1=y
121CONFIG_NLS_ISO8859_2=y
122CONFIG_NLS_ISO8859_3=y
123CONFIG_NLS_ISO8859_4=y
124CONFIG_NLS_ISO8859_5=y
125CONFIG_NLS_ISO8859_6=y
126CONFIG_NLS_ISO8859_7=y
127CONFIG_NLS_ISO8859_9=y
128CONFIG_NLS_ISO8859_13=y
129CONFIG_NLS_ISO8859_14=y
130CONFIG_NLS_ISO8859_15=y
131CONFIG_NLS_KOI8_R=y
132CONFIG_NLS_KOI8_U=y
133CONFIG_NLS_UTF8=y
134# CONFIG_ENABLE_WARN_DEPRECATED is not set
135# CONFIG_ENABLE_MUST_CHECK is not set
136# CONFIG_ARM_UNWIND is not set
137CONFIG_CRYPTO=y
138CONFIG_CRYPTO_ANSI_CPRNG=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 63293335724..4d1b4c5c938 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -5,26 +5,27 @@ comment "SH-Mobile System Type"
5config ARCH_SH7367 5config ARCH_SH7367
6 bool "SH-Mobile G3 (SH7367)" 6 bool "SH-Mobile G3 (SH7367)"
7 select CPU_V6 7 select CPU_V6
8 select HAVE_CLK
9 select CLKDEV_LOOKUP
10 select SH_CLK_CPG 8 select SH_CLK_CPG
11 select GENERIC_CLOCKEVENTS 9 select ARCH_WANT_OPTIONAL_GPIOLIB
12 10
13config ARCH_SH7377 11config ARCH_SH7377
14 bool "SH-Mobile G4 (SH7377)" 12 bool "SH-Mobile G4 (SH7377)"
15 select CPU_V7 13 select CPU_V7
16 select HAVE_CLK
17 select CLKDEV_LOOKUP
18 select SH_CLK_CPG 14 select SH_CLK_CPG
19 select GENERIC_CLOCKEVENTS 15 select ARCH_WANT_OPTIONAL_GPIOLIB
20 16
21config ARCH_SH7372 17config ARCH_SH7372
22 bool "SH-Mobile AP4 (SH7372)" 18 bool "SH-Mobile AP4 (SH7372)"
23 select CPU_V7 19 select CPU_V7
24 select HAVE_CLK
25 select CLKDEV_LOOKUP
26 select SH_CLK_CPG 20 select SH_CLK_CPG
27 select GENERIC_CLOCKEVENTS 21 select ARCH_WANT_OPTIONAL_GPIOLIB
22
23config ARCH_SH73A0
24 bool "SH-Mobile AG5 (R8A73A00)"
25 select CPU_V7
26 select SH_CLK_CPG
27 select ARCH_WANT_OPTIONAL_GPIOLIB
28 select ARM_GIC
28 29
29comment "SH-Mobile Board Type" 30comment "SH-Mobile Board Type"
30 31
@@ -57,6 +58,15 @@ config AP4EVB_WVGA
57 58
58endchoice 59endchoice
59 60
61config MACH_AG5EVM
62 bool "AG5EVM board"
63 depends on ARCH_SH73A0
64
65config MACH_MACKEREL
66 bool "mackerel board"
67 depends on ARCH_SH7372
68 select ARCH_REQUIRE_GPIOLIB
69
60comment "SH-Mobile System Configuration" 70comment "SH-Mobile System Configuration"
61 71
62menu "Memory configuration" 72menu "Memory configuration"
@@ -64,8 +74,8 @@ menu "Memory configuration"
64config MEMORY_START 74config MEMORY_START
65 hex "Physical memory start address" 75 hex "Physical memory start address"
66 default "0x50000000" if MACH_G3EVM 76 default "0x50000000" if MACH_G3EVM
67 default "0x40000000" if MACH_G4EVM 77 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
68 default "0x40000000" if MACH_AP4EVB 78 MACH_MACKEREL
69 default "0x00000000" 79 default "0x00000000"
70 ---help--- 80 ---help---
71 Tweak this only when porting to a new machine which does not 81 Tweak this only when porting to a new machine which does not
@@ -76,7 +86,8 @@ config MEMORY_SIZE
76 hex "Physical memory size" 86 hex "Physical memory size"
77 default "0x08000000" if MACH_G3EVM 87 default "0x08000000" if MACH_G3EVM
78 default "0x08000000" if MACH_G4EVM 88 default "0x08000000" if MACH_G4EVM
79 default "0x10000000" if MACH_AP4EVB 89 default "0x20000000" if MACH_AG5EVM
90 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
80 default "0x04000000" 91 default "0x04000000"
81 help 92 help
82 This sets the default memory size assumed by your kernel. It can 93 This sets the default memory size assumed by your kernel. It can
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index ae416fe7daf..ab100e4bddd 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -9,14 +9,21 @@ obj-y := timer.o console.o clock.o pm_runtime.o
9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o 9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o 10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
12 13
13# Pinmux setup 14# Pinmux setup
14pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o 15pfc-y :=
15pfc-$(CONFIG_ARCH_SH7377) := pfc-sh7377.o 16pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
16pfc-$(CONFIG_ARCH_SH7372) := pfc-sh7372.o 17pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
17obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) 18pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
19pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
18 20
19# Board objects 21# Board objects
20obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o 22obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
21obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o 23obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o
22obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o 24obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
25obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
26obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
27
28# Framework support
29obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
new file mode 100644
index 00000000000..2f135923e2b
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -0,0 +1,314 @@
1/*
2 * arch/arm/mach-shmobile/board-ag5evm.c
3 *
4 * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com>
5 * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/io.h>
29#include <linux/dma-mapping.h>
30#include <linux/serial_sci.h>
31#include <linux/smsc911x.h>
32#include <linux/gpio.h>
33#include <linux/input.h>
34#include <linux/input/sh_keysc.h>
35#include <linux/mmc/host.h>
36#include <linux/mmc/sh_mmcif.h>
37
38#include <sound/sh_fsi.h>
39
40#include <mach/hardware.h>
41#include <mach/sh73a0.h>
42#include <mach/common.h>
43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/map.h>
46#include <asm/mach/time.h>
47#include <asm/hardware/gic.h>
48#include <asm/hardware/cache-l2x0.h>
49#include <asm/traps.h>
50
51static struct resource smsc9220_resources[] = {
52 [0] = {
53 .start = 0x14000000,
54 .end = 0x14000000 + SZ_64K - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = gic_spi(33), /* PINT1 */
59 .flags = IORESOURCE_IRQ,
60 },
61};
62
63static struct smsc911x_platform_config smsc9220_platdata = {
64 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
65 .phy_interface = PHY_INTERFACE_MODE_MII,
66 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
67 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
68};
69
70static struct platform_device eth_device = {
71 .name = "smsc911x",
72 .id = 0,
73 .dev = {
74 .platform_data = &smsc9220_platdata,
75 },
76 .resource = smsc9220_resources,
77 .num_resources = ARRAY_SIZE(smsc9220_resources),
78};
79
80static struct sh_keysc_info keysc_platdata = {
81 .mode = SH_KEYSC_MODE_6,
82 .scan_timing = 3,
83 .delay = 100,
84 .keycodes = {
85 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
86 KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
87 KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
88 KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
89 KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \
90 KEY_COFFEE,
91 KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP,
92 KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \
93 KEY_COMPUTER,
94 },
95};
96
97static struct resource keysc_resources[] = {
98 [0] = {
99 .name = "KEYSC",
100 .start = 0xe61b0000,
101 .end = 0xe61b0098 - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = gic_spi(71),
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110static struct platform_device keysc_device = {
111 .name = "sh_keysc",
112 .id = 0,
113 .num_resources = ARRAY_SIZE(keysc_resources),
114 .resource = keysc_resources,
115 .dev = {
116 .platform_data = &keysc_platdata,
117 },
118};
119
120/* FSI A */
121static struct sh_fsi_platform_info fsi_info = {
122 .porta_flags = SH_FSI_OUT_SLAVE_MODE |
123 SH_FSI_IN_SLAVE_MODE |
124 SH_FSI_OFMT(I2S) |
125 SH_FSI_IFMT(I2S),
126};
127
128static struct resource fsi_resources[] = {
129 [0] = {
130 .name = "FSI",
131 .start = 0xEC230000,
132 .end = 0xEC230400 - 1,
133 .flags = IORESOURCE_MEM,
134 },
135 [1] = {
136 .start = gic_spi(146),
137 .flags = IORESOURCE_IRQ,
138 },
139};
140
141static struct platform_device fsi_device = {
142 .name = "sh_fsi2",
143 .id = -1,
144 .num_resources = ARRAY_SIZE(fsi_resources),
145 .resource = fsi_resources,
146 .dev = {
147 .platform_data = &fsi_info,
148 },
149};
150
151static struct resource sh_mmcif_resources[] = {
152 [0] = {
153 .name = "MMCIF",
154 .start = 0xe6bd0000,
155 .end = 0xe6bd00ff,
156 .flags = IORESOURCE_MEM,
157 },
158 [1] = {
159 .start = gic_spi(141),
160 .flags = IORESOURCE_IRQ,
161 },
162 [2] = {
163 .start = gic_spi(140),
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct sh_mmcif_plat_data sh_mmcif_platdata = {
169 .sup_pclk = 0,
170 .ocr = MMC_VDD_165_195,
171 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
172};
173
174static struct platform_device mmc_device = {
175 .name = "sh_mmcif",
176 .id = 0,
177 .dev = {
178 .dma_mask = NULL,
179 .coherent_dma_mask = 0xffffffff,
180 .platform_data = &sh_mmcif_platdata,
181 },
182 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
183 .resource = sh_mmcif_resources,
184};
185
186static struct platform_device *ag5evm_devices[] __initdata = {
187 &eth_device,
188 &keysc_device,
189 &fsi_device,
190 &mmc_device,
191};
192
193static struct map_desc ag5evm_io_desc[] __initdata = {
194 /* create a 1:1 entity map for 0xe6xxxxxx
195 * used by CPGA, INTC and PFC.
196 */
197 {
198 .virtual = 0xe6000000,
199 .pfn = __phys_to_pfn(0xe6000000),
200 .length = 256 << 20,
201 .type = MT_DEVICE_NONSHARED
202 },
203};
204
205static void __init ag5evm_map_io(void)
206{
207 iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
208
209 /* setup early devices and console here as well */
210 sh73a0_add_early_devices();
211 shmobile_setup_console();
212}
213
214#define PINTC_ADDR 0xe6900000
215#define PINTER0A (PINTC_ADDR + 0xa0)
216#define PINTCR0A (PINTC_ADDR + 0xb0)
217
218void __init ag5evm_init_irq(void)
219{
220 sh73a0_init_irq();
221
222 /* setup PINT: enable PINTA2 as active low */
223 __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
224 __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
225}
226
227static void __init ag5evm_init(void)
228{
229 sh73a0_pinmux_init();
230
231 /* enable SCIFA2 */
232 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
233 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
234 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
235 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
236
237 /* enable KEYSC */
238 gpio_request(GPIO_FN_KEYIN0_PU, NULL);
239 gpio_request(GPIO_FN_KEYIN1_PU, NULL);
240 gpio_request(GPIO_FN_KEYIN2_PU, NULL);
241 gpio_request(GPIO_FN_KEYIN3_PU, NULL);
242 gpio_request(GPIO_FN_KEYIN4_PU, NULL);
243 gpio_request(GPIO_FN_KEYIN5_PU, NULL);
244 gpio_request(GPIO_FN_KEYIN6_PU, NULL);
245 gpio_request(GPIO_FN_KEYIN7_PU, NULL);
246 gpio_request(GPIO_FN_KEYOUT0, NULL);
247 gpio_request(GPIO_FN_KEYOUT1, NULL);
248 gpio_request(GPIO_FN_KEYOUT2, NULL);
249 gpio_request(GPIO_FN_KEYOUT3, NULL);
250 gpio_request(GPIO_FN_KEYOUT4, NULL);
251 gpio_request(GPIO_FN_KEYOUT5, NULL);
252 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
253 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
254 gpio_request(GPIO_FN_KEYOUT8, NULL);
255 gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
256
257 /* enable I2C channel 2 and 3 */
258 gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
259 gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
260 gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
261 gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
262
263 /* enable MMCIF */
264 gpio_request(GPIO_FN_MMCCLK0, NULL);
265 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
266 gpio_request(GPIO_FN_MMCD0_0, NULL);
267 gpio_request(GPIO_FN_MMCD0_1, NULL);
268 gpio_request(GPIO_FN_MMCD0_2, NULL);
269 gpio_request(GPIO_FN_MMCD0_3, NULL);
270 gpio_request(GPIO_FN_MMCD0_4, NULL);
271 gpio_request(GPIO_FN_MMCD0_5, NULL);
272 gpio_request(GPIO_FN_MMCD0_6, NULL);
273 gpio_request(GPIO_FN_MMCD0_7, NULL);
274 gpio_request(GPIO_PORT208, NULL); /* Reset */
275 gpio_direction_output(GPIO_PORT208, 1);
276
277 /* enable SMSC911X */
278 gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
279 gpio_direction_input(GPIO_PORT144);
280 gpio_request(GPIO_PORT145, NULL); /* RESET */
281 gpio_direction_output(GPIO_PORT145, 1);
282
283 /* FSI A */
284 gpio_request(GPIO_FN_FSIACK, NULL);
285 gpio_request(GPIO_FN_FSIAILR, NULL);
286 gpio_request(GPIO_FN_FSIAIBT, NULL);
287 gpio_request(GPIO_FN_FSIAISLD, NULL);
288 gpio_request(GPIO_FN_FSIAOSLD, NULL);
289
290#ifdef CONFIG_CACHE_L2X0
291 /* Shared attribute override enable, 64K*8way */
292 l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
293#endif
294 sh73a0_add_standard_devices();
295 platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
296}
297
298static void __init ag5evm_timer_init(void)
299{
300 sh73a0_clock_init();
301 shmobile_timer.init();
302 return;
303}
304
305struct sys_timer ag5evm_timer = {
306 .init = ag5evm_timer_init,
307};
308
309MACHINE_START(AG5EVM, "ag5evm")
310 .map_io = ag5evm_map_io,
311 .init_irq = ag5evm_init_irq,
312 .init_machine = ag5evm_init,
313 .timer = &ag5evm_timer,
314MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f92dbd0c06d..86edc772f82 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -273,6 +273,15 @@ static struct resource sh_mmcif_resources[] = {
273 }, 273 },
274}; 274};
275 275
276static struct sh_mmcif_dma sh_mmcif_dma = {
277 .chan_priv_rx = {
278 .slave_id = SHDMA_SLAVE_MMCIF_RX,
279 },
280 .chan_priv_tx = {
281 .slave_id = SHDMA_SLAVE_MMCIF_TX,
282 },
283};
284
276static struct sh_mmcif_plat_data sh_mmcif_plat = { 285static struct sh_mmcif_plat_data sh_mmcif_plat = {
277 .sup_pclk = 0, 286 .sup_pclk = 0,
278 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 287 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -280,6 +289,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
280 MMC_CAP_8_BIT_DATA | 289 MMC_CAP_8_BIT_DATA |
281 MMC_CAP_NEEDS_POLL, 290 MMC_CAP_NEEDS_POLL,
282 .get_cd = slot_cn7_get_cd, 291 .get_cd = slot_cn7_get_cd,
292 .dma = &sh_mmcif_dma,
283}; 293};
284 294
285static struct platform_device sh_mmcif_device = { 295static struct platform_device sh_mmcif_device = {
@@ -633,9 +643,8 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
633 return -EIO; 643 return -EIO;
634 644
635 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); 645 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
636 clk_put(fsib_clk);
637 if (ret < 0) 646 if (ret < 0)
638 return ret; 647 goto fsi_set_rate_end;
639 648
640 /* FSI DIV setting */ 649 /* FSI DIV setting */
641 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); 650 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
@@ -643,10 +652,14 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
643 /* disable FSI B */ 652 /* disable FSI B */
644 if (enable) 653 if (enable)
645 __fsi_set_round_rate(fsib_clk, fsib_rate, 0); 654 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
646 return ret; 655 goto fsi_set_rate_end;
647 } 656 }
648 657
649 return ackmd_bpfmd; 658 ret = ackmd_bpfmd;
659
660fsi_set_rate_end:
661 clk_put(fsib_clk);
662 return ret;
650} 663}
651 664
652static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) 665static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
@@ -1174,7 +1187,7 @@ static void __init ap4evb_init(void)
1174 gpio_request(GPIO_FN_OVCN2_1, NULL); 1187 gpio_request(GPIO_FN_OVCN2_1, NULL);
1175 1188
1176 /* setup USB phy */ 1189 /* setup USB phy */
1177 __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */ 1190 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
1178 1191
1179 /* enable FSI2 port A (ak4643) */ 1192 /* enable FSI2 port A (ak4643) */
1180 gpio_request(GPIO_FN_FSIAIBT, NULL); 1193 gpio_request(GPIO_FN_FSIAIBT, NULL);
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
new file mode 100644
index 00000000000..6a5ce9a0dcf
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -0,0 +1,1199 @@
1/*
2 * mackerel board support
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on ap4evb
8 * Copyright (C) 2010 Magnus Damm
9 * Copyright (C) 2008 Yoshihiro Shimoda
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/platform_device.h>
30#include <linux/gpio.h>
31#include <linux/input.h>
32#include <linux/io.h>
33#include <linux/i2c.h>
34#include <linux/leds.h>
35#include <linux/mfd/sh_mobile_sdhi.h>
36#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h>
38#include <linux/mmc/sh_mmcif.h>
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/partitions.h>
41#include <linux/mtd/physmap.h>
42#include <linux/smsc911x.h>
43#include <linux/sh_intc.h>
44#include <linux/tca6416_keypad.h>
45#include <linux/usb/r8a66597.h>
46
47#include <video/sh_mobile_hdmi.h>
48#include <video/sh_mobile_lcdc.h>
49#include <media/sh_mobile_ceu.h>
50#include <media/soc_camera.h>
51#include <media/soc_camera_platform.h>
52#include <sound/sh_fsi.h>
53
54#include <mach/common.h>
55#include <mach/sh7372.h>
56
57#include <asm/mach/arch.h>
58#include <asm/mach/time.h>
59#include <asm/mach/map.h>
60#include <asm/mach-types.h>
61
62/*
63 * Address Interface BusWidth note
64 * ------------------------------------------------------------------
65 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
66 * 0x0800_0000 user area -
67 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
68 * 0x1400_0000 Ether (LAN9220) 16bit
69 * 0x1600_0000 user area - cannot use with NAND
70 * 0x1800_0000 user area -
71 * 0x1A00_0000 -
72 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
73 */
74
75/*
76 * CPU mode
77 *
78 * SW4 | Boot Area| Master | Remarks
79 * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor|
80 * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
81 * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM
82 * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug
83 * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug
84 * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM
85 * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM
86 * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM
87 * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone
88 * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone
89*/
90
91/*
92 * NOR Flash ROM
93 *
94 * SW1 | SW2 | SW7 | NOR Flash ROM
95 * bit1 | bit1 bit2 | bit1 | Memory allocation
96 * ------+------------+------+------------------
97 * OFF | ON OFF | ON | Area 0
98 * OFF | ON OFF | OFF | Area 4
99 */
100
101/*
102 * SMSC 9220
103 *
104 * SW1 SMSC 9220
105 * -----------------------
106 * ON access disable
107 * OFF access enable
108 */
109
110/*
111 * NAND Flash ROM
112 *
113 * SW1 | SW2 | SW7 | NAND Flash ROM
114 * bit1 | bit1 bit2 | bit2 | Memory allocation
115 * ------+------------+------+------------------
116 * OFF | ON OFF | ON | FCE 0
117 * OFF | ON OFF | OFF | FCE 1
118 */
119
120/*
121 * External interrupt pin settings
122 *
123 * IRQX | pin setting | device | level
124 * ------+--------------------+--------------------+-------
125 * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low
126 * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High
127 * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Tuch Panel | Low
128 * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low
129 * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low
130 * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High
131 * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High
132 */
133
134/*
135 * USB
136 *
137 * USB0 : CN22 : Function
138 * USB1 : CN31 : Function/Host *1
139 *
140 * J30 (for CN31) *1
141 * ----------+---------------+-------------
142 * 1-2 short | VBUS 5V | Host
143 * open | external VBUS | Function
144 *
145 * *1
146 * CN31 is used as Host in Linux.
147 */
148
149/*
150 * SDHI0 (CN12)
151 *
152 * SW56 : OFF
153 *
154 */
155
156/* MMC /SDHI1 (CN7)
157 *
158 * I/O voltage : 1.8v
159 *
160 * Power voltage : 1.8v or 3.3v
161 * J22 : select power voltage *1
162 * 1-2 pin : 1.8v
163 * 2-3 pin : 3.3v
164 *
165 * *1
166 * Please change J22 depends the card to be used.
167 * MMC's OCR field set to support either voltage for the card inserted.
168 *
169 * SW1 | SW33
170 * | bit1 | bit2 | bit3 | bit4
171 * -------------+------+------+------+-------
172 * MMC0 OFF | OFF | ON | ON | X
173 * MMC1 ON | OFF | ON | X | ON
174 * SDHI1 OFF | ON | X | OFF | ON
175 *
176 */
177
178/*
179 * SDHI2 (CN23)
180 *
181 * microSD card sloct
182 *
183 */
184
185/*
186 * FIXME !!
187 *
188 * gpio_no_direction
189 * are quick_hack.
190 *
191 * current gpio frame work doesn't have
192 * the method to control only pull up/down/free.
193 * this function should be replaced by correct gpio function
194 */
195static void __init gpio_no_direction(u32 addr)
196{
197 __raw_writeb(0x00, addr);
198}
199
200/* MTD */
201static struct mtd_partition nor_flash_partitions[] = {
202 {
203 .name = "loader",
204 .offset = 0x00000000,
205 .size = 512 * 1024,
206 .mask_flags = MTD_WRITEABLE,
207 },
208 {
209 .name = "bootenv",
210 .offset = MTDPART_OFS_APPEND,
211 .size = 512 * 1024,
212 .mask_flags = MTD_WRITEABLE,
213 },
214 {
215 .name = "kernel_ro",
216 .offset = MTDPART_OFS_APPEND,
217 .size = 8 * 1024 * 1024,
218 .mask_flags = MTD_WRITEABLE,
219 },
220 {
221 .name = "kernel",
222 .offset = MTDPART_OFS_APPEND,
223 .size = 8 * 1024 * 1024,
224 },
225 {
226 .name = "data",
227 .offset = MTDPART_OFS_APPEND,
228 .size = MTDPART_SIZ_FULL,
229 },
230};
231
232static struct physmap_flash_data nor_flash_data = {
233 .width = 2,
234 .parts = nor_flash_partitions,
235 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
236};
237
238static struct resource nor_flash_resources[] = {
239 [0] = {
240 .start = 0x00000000,
241 .end = 0x08000000 - 1,
242 .flags = IORESOURCE_MEM,
243 }
244};
245
246static struct platform_device nor_flash_device = {
247 .name = "physmap-flash",
248 .dev = {
249 .platform_data = &nor_flash_data,
250 },
251 .num_resources = ARRAY_SIZE(nor_flash_resources),
252 .resource = nor_flash_resources,
253};
254
255/* SMSC */
256static struct resource smc911x_resources[] = {
257 {
258 .start = 0x14000000,
259 .end = 0x16000000 - 1,
260 .flags = IORESOURCE_MEM,
261 }, {
262 .start = evt2irq(0x02c0) /* IRQ6A */,
263 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
264 },
265};
266
267static struct smsc911x_platform_config smsc911x_info = {
268 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
269 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
270 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
271};
272
273static struct platform_device smc911x_device = {
274 .name = "smsc911x",
275 .id = -1,
276 .num_resources = ARRAY_SIZE(smc911x_resources),
277 .resource = smc911x_resources,
278 .dev = {
279 .platform_data = &smsc911x_info,
280 },
281};
282
283/* LCDC */
284static struct fb_videomode mackerel_lcdc_modes[] = {
285 {
286 .name = "WVGA Panel",
287 .xres = 800,
288 .yres = 480,
289 .left_margin = 220,
290 .right_margin = 110,
291 .hsync_len = 70,
292 .upper_margin = 20,
293 .lower_margin = 5,
294 .vsync_len = 5,
295 .sync = 0,
296 },
297};
298
299static struct sh_mobile_lcdc_info lcdc_info = {
300 .clock_source = LCDC_CLK_BUS,
301 .ch[0] = {
302 .chan = LCDC_CHAN_MAINLCD,
303 .bpp = 16,
304 .lcd_cfg = mackerel_lcdc_modes,
305 .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
306 .interface_type = RGB24,
307 .clock_divider = 2,
308 .flags = 0,
309 .lcd_size_cfg.width = 152,
310 .lcd_size_cfg.height = 91,
311 }
312};
313
314static struct resource lcdc_resources[] = {
315 [0] = {
316 .name = "LCDC",
317 .start = 0xfe940000,
318 .end = 0xfe943fff,
319 .flags = IORESOURCE_MEM,
320 },
321 [1] = {
322 .start = intcs_evt2irq(0x580),
323 .flags = IORESOURCE_IRQ,
324 },
325};
326
327static struct platform_device lcdc_device = {
328 .name = "sh_mobile_lcdc_fb",
329 .num_resources = ARRAY_SIZE(lcdc_resources),
330 .resource = lcdc_resources,
331 .dev = {
332 .platform_data = &lcdc_info,
333 .coherent_dma_mask = ~0,
334 },
335};
336
337/* HDMI */
338static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
339 .clock_source = LCDC_CLK_EXTERNAL,
340 .ch[0] = {
341 .chan = LCDC_CHAN_MAINLCD,
342 .bpp = 16,
343 .interface_type = RGB24,
344 .clock_divider = 1,
345 .flags = LCDC_FLAGS_DWPOL,
346 }
347};
348
349static struct resource hdmi_lcdc_resources[] = {
350 [0] = {
351 .name = "LCDC1",
352 .start = 0xfe944000,
353 .end = 0xfe947fff,
354 .flags = IORESOURCE_MEM,
355 },
356 [1] = {
357 .start = intcs_evt2irq(0x1780),
358 .flags = IORESOURCE_IRQ,
359 },
360};
361
362static struct platform_device hdmi_lcdc_device = {
363 .name = "sh_mobile_lcdc_fb",
364 .num_resources = ARRAY_SIZE(hdmi_lcdc_resources),
365 .resource = hdmi_lcdc_resources,
366 .id = 1,
367 .dev = {
368 .platform_data = &hdmi_lcdc_info,
369 .coherent_dma_mask = ~0,
370 },
371};
372
373static struct sh_mobile_hdmi_info hdmi_info = {
374 .lcd_chan = &hdmi_lcdc_info.ch[0],
375 .lcd_dev = &hdmi_lcdc_device.dev,
376 .flags = HDMI_SND_SRC_SPDIF,
377};
378
379static struct resource hdmi_resources[] = {
380 [0] = {
381 .name = "HDMI",
382 .start = 0xe6be0000,
383 .end = 0xe6be00ff,
384 .flags = IORESOURCE_MEM,
385 },
386 [1] = {
387 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
388 .start = evt2irq(0x17e0),
389 .flags = IORESOURCE_IRQ,
390 },
391};
392
393static struct platform_device hdmi_device = {
394 .name = "sh-mobile-hdmi",
395 .num_resources = ARRAY_SIZE(hdmi_resources),
396 .resource = hdmi_resources,
397 .id = -1,
398 .dev = {
399 .platform_data = &hdmi_info,
400 },
401};
402
403static int __init hdmi_init_pm_clock(void)
404{
405 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
406 int ret;
407 long rate;
408
409 if (IS_ERR(hdmi_ick)) {
410 ret = PTR_ERR(hdmi_ick);
411 pr_err("Cannot get HDMI ICK: %d\n", ret);
412 goto out;
413 }
414
415 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
416 if (ret < 0) {
417 pr_err("Cannot set PLLC2 parent: %d, %d users\n",
418 ret, sh7372_pllc2_clk.usecount);
419 goto out;
420 }
421
422 pr_debug("PLLC2 initial frequency %lu\n",
423 clk_get_rate(&sh7372_pllc2_clk));
424
425 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
426 if (rate < 0) {
427 pr_err("Cannot get suitable rate: %ld\n", rate);
428 ret = rate;
429 goto out;
430 }
431
432 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
433 if (ret < 0) {
434 pr_err("Cannot set rate %ld: %d\n", rate, ret);
435 goto out;
436 }
437
438 ret = clk_enable(&sh7372_pllc2_clk);
439 if (ret < 0) {
440 pr_err("Cannot enable pllc2 clock\n");
441 goto out;
442 }
443
444 pr_debug("PLLC2 set frequency %lu\n", rate);
445
446 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
447 if (ret < 0) {
448 pr_err("Cannot set HDMI parent: %d\n", ret);
449 goto out;
450 }
451
452out:
453 if (!IS_ERR(hdmi_ick))
454 clk_put(hdmi_ick);
455 return ret;
456}
457device_initcall(hdmi_init_pm_clock);
458
459/* USB1 (Host) */
460static void usb1_host_port_power(int port, int power)
461{
462 if (!power) /* only power-on is supported for now */
463 return;
464
465 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
466 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
467}
468
469static struct r8a66597_platdata usb1_host_data = {
470 .on_chip = 1,
471 .port_power = usb1_host_port_power,
472};
473
474static struct resource usb1_host_resources[] = {
475 [0] = {
476 .name = "USBHS",
477 .start = 0xE68B0000,
478 .end = 0xE68B00E6 - 1,
479 .flags = IORESOURCE_MEM,
480 },
481 [1] = {
482 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
483 .flags = IORESOURCE_IRQ,
484 },
485};
486
487static struct platform_device usb1_host_device = {
488 .name = "r8a66597_hcd",
489 .id = 1,
490 .dev = {
491 .dma_mask = NULL, /* not use dma */
492 .coherent_dma_mask = 0xffffffff,
493 .platform_data = &usb1_host_data,
494 },
495 .num_resources = ARRAY_SIZE(usb1_host_resources),
496 .resource = usb1_host_resources,
497};
498
499/* LED */
500static struct gpio_led mackerel_leds[] = {
501 {
502 .name = "led0",
503 .gpio = GPIO_PORT0,
504 .default_state = LEDS_GPIO_DEFSTATE_ON,
505 },
506 {
507 .name = "led1",
508 .gpio = GPIO_PORT1,
509 .default_state = LEDS_GPIO_DEFSTATE_ON,
510 },
511 {
512 .name = "led2",
513 .gpio = GPIO_PORT2,
514 .default_state = LEDS_GPIO_DEFSTATE_ON,
515 },
516 {
517 .name = "led3",
518 .gpio = GPIO_PORT159,
519 .default_state = LEDS_GPIO_DEFSTATE_ON,
520 }
521};
522
523static struct gpio_led_platform_data mackerel_leds_pdata = {
524 .leds = mackerel_leds,
525 .num_leds = ARRAY_SIZE(mackerel_leds),
526};
527
528static struct platform_device leds_device = {
529 .name = "leds-gpio",
530 .id = 0,
531 .dev = {
532 .platform_data = &mackerel_leds_pdata,
533 },
534};
535
536/* FSI */
537#define IRQ_FSI evt2irq(0x1840)
538static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
539{
540 int ret;
541
542 if (rate <= 0)
543 return 0;
544
545 if (!enable) {
546 clk_disable(clk);
547 return 0;
548 }
549
550 ret = clk_set_rate(clk, clk_round_rate(clk, rate));
551 if (ret < 0)
552 return ret;
553
554 return clk_enable(clk);
555}
556
557static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
558{
559 struct clk *fsib_clk;
560 struct clk *fdiv_clk = &sh7372_fsidivb_clk;
561 long fsib_rate = 0;
562 long fdiv_rate = 0;
563 int ackmd_bpfmd;
564 int ret;
565
566 /* FSIA is slave mode. nothing to do here */
567 if (is_porta)
568 return 0;
569
570 /* clock start */
571 switch (rate) {
572 case 44100:
573 fsib_rate = rate * 256;
574 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
575 break;
576 case 48000:
577 fsib_rate = 85428000; /* around 48kHz x 256 x 7 */
578 fdiv_rate = rate * 256;
579 ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
580 break;
581 default:
582 pr_err("unsupported rate in FSI2 port B\n");
583 return -EINVAL;
584 }
585
586 /* FSI B setting */
587 fsib_clk = clk_get(dev, "ickb");
588 if (IS_ERR(fsib_clk))
589 return -EIO;
590
591 /* fsib */
592 ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
593 if (ret < 0)
594 goto fsi_set_rate_end;
595
596 /* FSI DIV */
597 ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
598 if (ret < 0) {
599 /* disable FSI B */
600 if (enable)
601 __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
602 goto fsi_set_rate_end;
603 }
604
605 ret = ackmd_bpfmd;
606
607fsi_set_rate_end:
608 clk_put(fsib_clk);
609 return ret;
610}
611
612static struct sh_fsi_platform_info fsi_info = {
613 .porta_flags = SH_FSI_BRS_INV |
614 SH_FSI_OUT_SLAVE_MODE |
615 SH_FSI_IN_SLAVE_MODE |
616 SH_FSI_OFMT(PCM) |
617 SH_FSI_IFMT(PCM),
618
619 .portb_flags = SH_FSI_BRS_INV |
620 SH_FSI_BRM_INV |
621 SH_FSI_LRS_INV |
622 SH_FSI_OFMT(SPDIF),
623
624 .set_rate = fsi_set_rate,
625};
626
627static struct resource fsi_resources[] = {
628 [0] = {
629 .name = "FSI",
630 .start = 0xFE3C0000,
631 .end = 0xFE3C0400 - 1,
632 .flags = IORESOURCE_MEM,
633 },
634 [1] = {
635 .start = IRQ_FSI,
636 .flags = IORESOURCE_IRQ,
637 },
638};
639
640static struct platform_device fsi_device = {
641 .name = "sh_fsi2",
642 .id = -1,
643 .num_resources = ARRAY_SIZE(fsi_resources),
644 .resource = fsi_resources,
645 .dev = {
646 .platform_data = &fsi_info,
647 },
648};
649
650static struct platform_device fsi_ak4643_device = {
651 .name = "sh_fsi2_a_ak4643",
652};
653
654/*
655 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
656 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
657 */
658static int slot_cn7_get_cd(struct platform_device *pdev)
659{
660 if (gpio_is_valid(GPIO_PORT41))
661 return !gpio_get_value(GPIO_PORT41);
662 else
663 return -ENXIO;
664}
665
666/* SDHI0 */
667static struct sh_mobile_sdhi_info sdhi0_info = {
668 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
669 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
670 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
671};
672
673static struct resource sdhi0_resources[] = {
674 [0] = {
675 .name = "SDHI0",
676 .start = 0xe6850000,
677 .end = 0xe68501ff,
678 .flags = IORESOURCE_MEM,
679 },
680 [1] = {
681 .start = evt2irq(0x0e00) /* SDHI0 */,
682 .flags = IORESOURCE_IRQ,
683 },
684};
685
686static struct platform_device sdhi0_device = {
687 .name = "sh_mobile_sdhi",
688 .num_resources = ARRAY_SIZE(sdhi0_resources),
689 .resource = sdhi0_resources,
690 .id = 0,
691 .dev = {
692 .platform_data = &sdhi0_info,
693 },
694};
695
696#if !defined(CONFIG_MMC_SH_MMCIF)
697/* SDHI1 */
698static struct sh_mobile_sdhi_info sdhi1_info = {
699 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
700 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
701 .tmio_ocr_mask = MMC_VDD_165_195,
702 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
703 .tmio_caps = MMC_CAP_SD_HIGHSPEED |
704 MMC_CAP_NEEDS_POLL,
705 .get_cd = slot_cn7_get_cd,
706};
707
708static struct resource sdhi1_resources[] = {
709 [0] = {
710 .name = "SDHI1",
711 .start = 0xe6860000,
712 .end = 0xe68601ff,
713 .flags = IORESOURCE_MEM,
714 },
715 [1] = {
716 .start = evt2irq(0x0e80),
717 .flags = IORESOURCE_IRQ,
718 },
719};
720
721static struct platform_device sdhi1_device = {
722 .name = "sh_mobile_sdhi",
723 .num_resources = ARRAY_SIZE(sdhi1_resources),
724 .resource = sdhi1_resources,
725 .id = 1,
726 .dev = {
727 .platform_data = &sdhi1_info,
728 },
729};
730#endif
731
732/* SDHI2 */
733static struct sh_mobile_sdhi_info sdhi2_info = {
734 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
735 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
736 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
737 .tmio_caps = MMC_CAP_SD_HIGHSPEED |
738 MMC_CAP_NEEDS_POLL,
739};
740
741static struct resource sdhi2_resources[] = {
742 [0] = {
743 .name = "SDHI2",
744 .start = 0xe6870000,
745 .end = 0xe68701ff,
746 .flags = IORESOURCE_MEM,
747 },
748 [1] = {
749 .start = evt2irq(0x1200),
750 .flags = IORESOURCE_IRQ,
751 },
752};
753
754static struct platform_device sdhi2_device = {
755 .name = "sh_mobile_sdhi",
756 .num_resources = ARRAY_SIZE(sdhi2_resources),
757 .resource = sdhi2_resources,
758 .id = 2,
759 .dev = {
760 .platform_data = &sdhi2_info,
761 },
762};
763
764/* SH_MMCIF */
765static struct resource sh_mmcif_resources[] = {
766 [0] = {
767 .name = "MMCIF",
768 .start = 0xE6BD0000,
769 .end = 0xE6BD00FF,
770 .flags = IORESOURCE_MEM,
771 },
772 [1] = {
773 /* MMC ERR */
774 .start = evt2irq(0x1ac0),
775 .flags = IORESOURCE_IRQ,
776 },
777 [2] = {
778 /* MMC NOR */
779 .start = evt2irq(0x1ae0),
780 .flags = IORESOURCE_IRQ,
781 },
782};
783
784static struct sh_mmcif_plat_data sh_mmcif_plat = {
785 .sup_pclk = 0,
786 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
787 .caps = MMC_CAP_4_BIT_DATA |
788 MMC_CAP_8_BIT_DATA |
789 MMC_CAP_NEEDS_POLL,
790 .get_cd = slot_cn7_get_cd,
791};
792
793static struct platform_device sh_mmcif_device = {
794 .name = "sh_mmcif",
795 .id = 0,
796 .dev = {
797 .dma_mask = NULL,
798 .coherent_dma_mask = 0xffffffff,
799 .platform_data = &sh_mmcif_plat,
800 },
801 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
802 .resource = sh_mmcif_resources,
803};
804
805
806static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev);
807static void mackerel_camera_del(struct soc_camera_link *icl);
808
809static int camera_set_capture(struct soc_camera_platform_info *info,
810 int enable)
811{
812 return 0; /* camera sensor always enabled */
813}
814
815static struct soc_camera_platform_info camera_info = {
816 .format_name = "UYVY",
817 .format_depth = 16,
818 .format = {
819 .code = V4L2_MBUS_FMT_UYVY8_2X8,
820 .colorspace = V4L2_COLORSPACE_SMPTE170M,
821 .field = V4L2_FIELD_NONE,
822 .width = 640,
823 .height = 480,
824 },
825 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
826 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
827 SOCAM_DATA_ACTIVE_HIGH,
828 .set_capture = camera_set_capture,
829};
830
831static struct soc_camera_link camera_link = {
832 .bus_id = 0,
833 .add_device = mackerel_camera_add,
834 .del_device = mackerel_camera_del,
835 .module_name = "soc_camera_platform",
836 .priv = &camera_info,
837};
838
839static void dummy_release(struct device *dev)
840{
841}
842
843static struct platform_device camera_device = {
844 .name = "soc_camera_platform",
845 .dev = {
846 .platform_data = &camera_info,
847 .release = dummy_release,
848 },
849};
850
851static int mackerel_camera_add(struct soc_camera_link *icl,
852 struct device *dev)
853{
854 if (icl != &camera_link)
855 return -ENODEV;
856
857 camera_info.dev = dev;
858
859 return platform_device_register(&camera_device);
860}
861
862static void mackerel_camera_del(struct soc_camera_link *icl)
863{
864 if (icl != &camera_link)
865 return;
866
867 platform_device_unregister(&camera_device);
868 memset(&camera_device.dev.kobj, 0,
869 sizeof(camera_device.dev.kobj));
870}
871
872static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
873 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
874};
875
876static struct resource ceu_resources[] = {
877 [0] = {
878 .name = "CEU",
879 .start = 0xfe910000,
880 .end = 0xfe91009f,
881 .flags = IORESOURCE_MEM,
882 },
883 [1] = {
884 .start = intcs_evt2irq(0x880),
885 .flags = IORESOURCE_IRQ,
886 },
887 [2] = {
888 /* place holder for contiguous memory */
889 },
890};
891
892static struct platform_device ceu_device = {
893 .name = "sh_mobile_ceu",
894 .id = 0, /* "ceu0" clock */
895 .num_resources = ARRAY_SIZE(ceu_resources),
896 .resource = ceu_resources,
897 .dev = {
898 .platform_data = &sh_mobile_ceu_info,
899 },
900};
901
902static struct platform_device mackerel_camera = {
903 .name = "soc-camera-pdrv",
904 .id = 0,
905 .dev = {
906 .platform_data = &camera_link,
907 },
908};
909
910static struct platform_device *mackerel_devices[] __initdata = {
911 &nor_flash_device,
912 &smc911x_device,
913 &lcdc_device,
914 &usb1_host_device,
915 &leds_device,
916 &fsi_device,
917 &fsi_ak4643_device,
918 &sdhi0_device,
919#if !defined(CONFIG_MMC_SH_MMCIF)
920 &sdhi1_device,
921#endif
922 &sdhi2_device,
923 &sh_mmcif_device,
924 &ceu_device,
925 &mackerel_camera,
926 &hdmi_lcdc_device,
927 &hdmi_device,
928};
929
930/* Keypad Initialization */
931#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
932{ \
933 .type = ev_type, \
934 .code = ev_code, \
935 .active_low = act_low, \
936}
937
938#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
939
940static struct tca6416_button mackerel_gpio_keys[] = {
941 KEYPAD_BUTTON_LOW(KEY_HOME),
942 KEYPAD_BUTTON_LOW(KEY_MENU),
943 KEYPAD_BUTTON_LOW(KEY_BACK),
944 KEYPAD_BUTTON_LOW(KEY_POWER),
945};
946
947static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
948 .buttons = mackerel_gpio_keys,
949 .nbuttons = ARRAY_SIZE(mackerel_gpio_keys),
950 .rep = 1,
951 .use_polling = 0,
952 .pinmask = 0x000F,
953};
954
955/* I2C */
956#define IRQ9 evt2irq(0x0320)
957
958static struct i2c_board_info i2c0_devices[] = {
959 {
960 I2C_BOARD_INFO("ak4643", 0x13),
961 },
962 /* Keypad */
963 {
964 I2C_BOARD_INFO("tca6408-keys", 0x20),
965 .platform_data = &mackerel_tca6416_keys_info,
966 .irq = IRQ9,
967 },
968};
969
970#define IRQ21 evt2irq(0x32a0)
971
972static struct i2c_board_info i2c1_devices[] = {
973 /* Accelerometer */
974 {
975 I2C_BOARD_INFO("adxl34x", 0x53),
976 .irq = IRQ21,
977 },
978};
979
980static struct map_desc mackerel_io_desc[] __initdata = {
981 /* create a 1:1 entity map for 0xe6xxxxxx
982 * used by CPGA, INTC and PFC.
983 */
984 {
985 .virtual = 0xe6000000,
986 .pfn = __phys_to_pfn(0xe6000000),
987 .length = 256 << 20,
988 .type = MT_DEVICE_NONSHARED
989 },
990};
991
992static void __init mackerel_map_io(void)
993{
994 iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
995
996 /* setup early devices and console here as well */
997 sh7372_add_early_devices();
998 shmobile_setup_console();
999}
1000
1001#define GPIO_PORT9CR 0xE6051009
1002#define GPIO_PORT10CR 0xE605100A
1003#define SRCR4 0xe61580bc
1004#define USCCR1 0xE6058144
1005static void __init mackerel_init(void)
1006{
1007 u32 srcr4;
1008 struct clk *clk;
1009
1010 sh7372_pinmux_init();
1011
1012 /* enable SCIFA0 */
1013 gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
1014 gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
1015
1016 /* enable SMSC911X */
1017 gpio_request(GPIO_FN_CS5A, NULL);
1018 gpio_request(GPIO_FN_IRQ6_39, NULL);
1019
1020 /* LCDC */
1021 gpio_request(GPIO_FN_LCDD23, NULL);
1022 gpio_request(GPIO_FN_LCDD22, NULL);
1023 gpio_request(GPIO_FN_LCDD21, NULL);
1024 gpio_request(GPIO_FN_LCDD20, NULL);
1025 gpio_request(GPIO_FN_LCDD19, NULL);
1026 gpio_request(GPIO_FN_LCDD18, NULL);
1027 gpio_request(GPIO_FN_LCDD17, NULL);
1028 gpio_request(GPIO_FN_LCDD16, NULL);
1029 gpio_request(GPIO_FN_LCDD15, NULL);
1030 gpio_request(GPIO_FN_LCDD14, NULL);
1031 gpio_request(GPIO_FN_LCDD13, NULL);
1032 gpio_request(GPIO_FN_LCDD12, NULL);
1033 gpio_request(GPIO_FN_LCDD11, NULL);
1034 gpio_request(GPIO_FN_LCDD10, NULL);
1035 gpio_request(GPIO_FN_LCDD9, NULL);
1036 gpio_request(GPIO_FN_LCDD8, NULL);
1037 gpio_request(GPIO_FN_LCDD7, NULL);
1038 gpio_request(GPIO_FN_LCDD6, NULL);
1039 gpio_request(GPIO_FN_LCDD5, NULL);
1040 gpio_request(GPIO_FN_LCDD4, NULL);
1041 gpio_request(GPIO_FN_LCDD3, NULL);
1042 gpio_request(GPIO_FN_LCDD2, NULL);
1043 gpio_request(GPIO_FN_LCDD1, NULL);
1044 gpio_request(GPIO_FN_LCDD0, NULL);
1045 gpio_request(GPIO_FN_LCDDISP, NULL);
1046 gpio_request(GPIO_FN_LCDDCK, NULL);
1047
1048 gpio_request(GPIO_PORT31, NULL); /* backlight */
1049 gpio_direction_output(GPIO_PORT31, 1);
1050
1051 gpio_request(GPIO_PORT151, NULL); /* LCDDON */
1052 gpio_direction_output(GPIO_PORT151, 1);
1053
1054 /* USB enable */
1055 gpio_request(GPIO_FN_VBUS0_1, NULL);
1056 gpio_request(GPIO_FN_IDIN_1_18, NULL);
1057 gpio_request(GPIO_FN_PWEN_1_115, NULL);
1058 gpio_request(GPIO_FN_OVCN_1_114, NULL);
1059 gpio_request(GPIO_FN_EXTLP_1, NULL);
1060 gpio_request(GPIO_FN_OVCN2_1, NULL);
1061
1062 /* setup USB phy */
1063 __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
1064
1065 /* enable FSI2 port A (ak4643) */
1066 gpio_request(GPIO_FN_FSIAIBT, NULL);
1067 gpio_request(GPIO_FN_FSIAILR, NULL);
1068 gpio_request(GPIO_FN_FSIAISLD, NULL);
1069 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1070 gpio_request(GPIO_PORT161, NULL);
1071 gpio_direction_output(GPIO_PORT161, 0); /* slave */
1072
1073 gpio_request(GPIO_PORT9, NULL);
1074 gpio_request(GPIO_PORT10, NULL);
1075 gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1076 gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1077
1078 intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
1079
1080 /* setup FSI2 port B (HDMI) */
1081 gpio_request(GPIO_FN_FSIBCK, NULL);
1082 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1083
1084 /* set SPU2 clock to 119.6 MHz */
1085 clk = clk_get(NULL, "spu_clk");
1086 if (!IS_ERR(clk)) {
1087 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1088 clk_put(clk);
1089 }
1090
1091 /* enable Keypad */
1092 gpio_request(GPIO_FN_IRQ9_42, NULL);
1093 set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
1094
1095 /* enable Accelerometer */
1096 gpio_request(GPIO_FN_IRQ21, NULL);
1097 set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1098
1099 /* enable SDHI0 */
1100 gpio_request(GPIO_FN_SDHICD0, NULL);
1101 gpio_request(GPIO_FN_SDHIWP0, NULL);
1102 gpio_request(GPIO_FN_SDHICMD0, NULL);
1103 gpio_request(GPIO_FN_SDHICLK0, NULL);
1104 gpio_request(GPIO_FN_SDHID0_3, NULL);
1105 gpio_request(GPIO_FN_SDHID0_2, NULL);
1106 gpio_request(GPIO_FN_SDHID0_1, NULL);
1107 gpio_request(GPIO_FN_SDHID0_0, NULL);
1108
1109#if !defined(CONFIG_MMC_SH_MMCIF)
1110 /* enable SDHI1 */
1111 gpio_request(GPIO_FN_SDHICMD1, NULL);
1112 gpio_request(GPIO_FN_SDHICLK1, NULL);
1113 gpio_request(GPIO_FN_SDHID1_3, NULL);
1114 gpio_request(GPIO_FN_SDHID1_2, NULL);
1115 gpio_request(GPIO_FN_SDHID1_1, NULL);
1116 gpio_request(GPIO_FN_SDHID1_0, NULL);
1117#endif
1118 /* card detect pin for MMC slot (CN7) */
1119 gpio_request(GPIO_PORT41, NULL);
1120 gpio_direction_input(GPIO_PORT41);
1121
1122 /* enable SDHI2 */
1123 gpio_request(GPIO_FN_SDHICMD2, NULL);
1124 gpio_request(GPIO_FN_SDHICLK2, NULL);
1125 gpio_request(GPIO_FN_SDHID2_3, NULL);
1126 gpio_request(GPIO_FN_SDHID2_2, NULL);
1127 gpio_request(GPIO_FN_SDHID2_1, NULL);
1128 gpio_request(GPIO_FN_SDHID2_0, NULL);
1129
1130 /* MMCIF */
1131 gpio_request(GPIO_FN_MMCD0_0, NULL);
1132 gpio_request(GPIO_FN_MMCD0_1, NULL);
1133 gpio_request(GPIO_FN_MMCD0_2, NULL);
1134 gpio_request(GPIO_FN_MMCD0_3, NULL);
1135 gpio_request(GPIO_FN_MMCD0_4, NULL);
1136 gpio_request(GPIO_FN_MMCD0_5, NULL);
1137 gpio_request(GPIO_FN_MMCD0_6, NULL);
1138 gpio_request(GPIO_FN_MMCD0_7, NULL);
1139 gpio_request(GPIO_FN_MMCCMD0, NULL);
1140 gpio_request(GPIO_FN_MMCCLK0, NULL);
1141
1142 /* enable GPS module (GT-720F) */
1143 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
1144 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
1145
1146 /* CEU */
1147 gpio_request(GPIO_FN_VIO_CLK, NULL);
1148 gpio_request(GPIO_FN_VIO_VD, NULL);
1149 gpio_request(GPIO_FN_VIO_HD, NULL);
1150 gpio_request(GPIO_FN_VIO_FIELD, NULL);
1151 gpio_request(GPIO_FN_VIO_CKO, NULL);
1152 gpio_request(GPIO_FN_VIO_D7, NULL);
1153 gpio_request(GPIO_FN_VIO_D6, NULL);
1154 gpio_request(GPIO_FN_VIO_D5, NULL);
1155 gpio_request(GPIO_FN_VIO_D4, NULL);
1156 gpio_request(GPIO_FN_VIO_D3, NULL);
1157 gpio_request(GPIO_FN_VIO_D2, NULL);
1158 gpio_request(GPIO_FN_VIO_D1, NULL);
1159 gpio_request(GPIO_FN_VIO_D0, NULL);
1160
1161 /* HDMI */
1162 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1163 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1164
1165 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1166 srcr4 = __raw_readl(SRCR4);
1167 __raw_writel(srcr4 | (1 << 13), SRCR4);
1168 udelay(50);
1169 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1170
1171 i2c_register_board_info(0, i2c0_devices,
1172 ARRAY_SIZE(i2c0_devices));
1173 i2c_register_board_info(1, i2c1_devices,
1174 ARRAY_SIZE(i2c1_devices));
1175
1176 sh7372_add_standard_devices();
1177
1178 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
1179}
1180
1181static void __init mackerel_timer_init(void)
1182{
1183 sh7372_clock_init();
1184 shmobile_timer.init();
1185
1186 /* External clock source */
1187 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1188}
1189
1190static struct sys_timer mackerel_timer = {
1191 .init = mackerel_timer_init,
1192};
1193
1194MACHINE_START(MACKEREL, "mackerel")
1195 .map_io = mackerel_map_io,
1196 .init_irq = sh7372_init_irq,
1197 .init_machine = mackerel_init,
1198 .timer = &mackerel_timer,
1199MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
new file mode 100644
index 00000000000..c196a288f22
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -0,0 +1,356 @@
1/*
2 * sh73a0 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <mach/common.h>
24#include <asm/clkdev.h>
25
26#define FRQCRA 0xe6150000
27#define FRQCRB 0xe6150004
28#define FRQCRD 0xe61500e4
29#define VCLKCR1 0xe6150008
30#define VCLKCR2 0xe615000C
31#define VCLKCR3 0xe615001C
32#define ZBCKCR 0xe6150010
33#define FLCKCR 0xe6150014
34#define SD0CKCR 0xe6150074
35#define SD1CKCR 0xe6150078
36#define SD2CKCR 0xe615007C
37#define FSIACKCR 0xe6150018
38#define FSIBCKCR 0xe6150090
39#define SUBCKCR 0xe6150080
40#define SPUACKCR 0xe6150084
41#define SPUVCKCR 0xe6150094
42#define MSUCKCR 0xe6150088
43#define HSICKCR 0xe615008C
44#define MFCK1CR 0xe6150098
45#define MFCK2CR 0xe615009C
46#define DSITCKCR 0xe6150060
47#define DSI0PCKCR 0xe6150064
48#define DSI1PCKCR 0xe6150068
49#define DSI0PHYCR 0xe615006C
50#define DSI1PHYCR 0xe6150070
51#define PLLECR 0xe61500d0
52#define PLL0CR 0xe61500d8
53#define PLL1CR 0xe6150028
54#define PLL2CR 0xe615002c
55#define PLL3CR 0xe61500dc
56#define SMSTPCR0 0xe6150130
57#define SMSTPCR1 0xe6150134
58#define SMSTPCR2 0xe6150138
59#define SMSTPCR3 0xe615013c
60#define SMSTPCR4 0xe6150140
61#define SMSTPCR5 0xe6150144
62#define CKSCR 0xe61500c0
63
64/* Fixed 32 KHz root clock from EXTALR pin */
65static struct clk r_clk = {
66 .rate = 32768,
67};
68
69/*
70 * 26MHz default rate for the EXTAL1 root input clock.
71 * If needed, reset this with clk_set_rate() from the platform code.
72 */
73struct clk sh73a0_extal1_clk = {
74 .rate = 26000000,
75};
76
77/*
78 * 48MHz default rate for the EXTAL2 root input clock.
79 * If needed, reset this with clk_set_rate() from the platform code.
80 */
81struct clk sh73a0_extal2_clk = {
82 .rate = 48000000,
83};
84
85/* A fixed divide-by-2 block */
86static unsigned long div2_recalc(struct clk *clk)
87{
88 return clk->parent->rate / 2;
89}
90
91static struct clk_ops div2_clk_ops = {
92 .recalc = div2_recalc,
93};
94
95/* Divide extal1 by two */
96static struct clk extal1_div2_clk = {
97 .ops = &div2_clk_ops,
98 .parent = &sh73a0_extal1_clk,
99};
100
101/* Divide extal2 by two */
102static struct clk extal2_div2_clk = {
103 .ops = &div2_clk_ops,
104 .parent = &sh73a0_extal2_clk,
105};
106
107static struct clk_ops main_clk_ops = {
108 .recalc = followparent_recalc,
109};
110
111/* Main clock */
112static struct clk main_clk = {
113 .ops = &main_clk_ops,
114};
115
116/* PLL0, PLL1, PLL2, PLL3 */
117static unsigned long pll_recalc(struct clk *clk)
118{
119 unsigned long mult = 1;
120
121 if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
122 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
123
124 return clk->parent->rate * mult;
125}
126
127static struct clk_ops pll_clk_ops = {
128 .recalc = pll_recalc,
129};
130
131static struct clk pll0_clk = {
132 .ops = &pll_clk_ops,
133 .flags = CLK_ENABLE_ON_INIT,
134 .parent = &main_clk,
135 .enable_reg = (void __iomem *)PLL0CR,
136 .enable_bit = 0,
137};
138
139static struct clk pll1_clk = {
140 .ops = &pll_clk_ops,
141 .flags = CLK_ENABLE_ON_INIT,
142 .parent = &main_clk,
143 .enable_reg = (void __iomem *)PLL1CR,
144 .enable_bit = 1,
145};
146
147static struct clk pll2_clk = {
148 .ops = &pll_clk_ops,
149 .flags = CLK_ENABLE_ON_INIT,
150 .parent = &main_clk,
151 .enable_reg = (void __iomem *)PLL2CR,
152 .enable_bit = 2,
153};
154
155static struct clk pll3_clk = {
156 .ops = &pll_clk_ops,
157 .flags = CLK_ENABLE_ON_INIT,
158 .parent = &main_clk,
159 .enable_reg = (void __iomem *)PLL3CR,
160 .enable_bit = 3,
161};
162
163/* Divide PLL1 by two */
164static struct clk pll1_div2_clk = {
165 .ops = &div2_clk_ops,
166 .parent = &pll1_clk,
167};
168
169static struct clk *main_clks[] = {
170 &r_clk,
171 &sh73a0_extal1_clk,
172 &sh73a0_extal2_clk,
173 &extal1_div2_clk,
174 &extal2_div2_clk,
175 &main_clk,
176 &pll0_clk,
177 &pll1_clk,
178 &pll2_clk,
179 &pll3_clk,
180 &pll1_div2_clk,
181};
182
183static void div4_kick(struct clk *clk)
184{
185 unsigned long value;
186
187 /* set KICK bit in FRQCRB to update hardware setting */
188 value = __raw_readl(FRQCRB);
189 value |= (1 << 31);
190 __raw_writel(value, FRQCRB);
191}
192
193static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
194 24, 0, 36, 48, 7 };
195
196static struct clk_div_mult_table div4_div_mult_table = {
197 .divisors = divisors,
198 .nr_divisors = ARRAY_SIZE(divisors),
199};
200
201static struct clk_div4_table div4_table = {
202 .div_mult_table = &div4_div_mult_table,
203 .kick = div4_kick,
204};
205
206enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
207 DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
208
209#define DIV4(_reg, _bit, _mask, _flags) \
210 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
211
212static struct clk div4_clks[DIV4_NR] = {
213 [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
214 [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
215 [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
216 [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
217 [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
218 [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
219 [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
220 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
221 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
222 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
223 [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
224};
225
226enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
227 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
228 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
229 DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
230 DIV6_HSI, DIV6_MFG1, DIV6_MFG2,
231 DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
232 DIV6_NR };
233
234static struct clk div6_clks[DIV6_NR] = {
235 [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
236 [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
237 [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
238 [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
239 [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
240 [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
241 [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
242 [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
243 [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
244 [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
245 [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
246 [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
247 [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
248 [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
249 [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
250 [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
251 [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
252 [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
253 [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
254 [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
255};
256
257enum { MSTP001,
258 MSTP125, MSTP116,
259 MSTP219,
260 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
261 MSTP331, MSTP329, MSTP323, MSTP312,
262 MSTP411, MSTP410, MSTP403,
263 MSTP_NR };
264
265#define MSTP(_parent, _reg, _bit, _flags) \
266 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
267
268static struct clk mstp_clks[MSTP_NR] = {
269 [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
270 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
271 [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
272 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
273 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
274 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
275 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
276 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
277 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
278 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
279 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
280 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
281 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
282 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
283 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
284 [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
285 [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
286 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
287};
288
289#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
290#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
291
292static struct clk_lookup lookups[] = {
293 /* main clocks */
294 CLKDEV_CON_ID("r_clk", &r_clk),
295
296 /* MSTP32 clocks */
297 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
298 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
299 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
300 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
301 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
302 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
303 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
304 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
305 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
306 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
307 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
308 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
309 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
310 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
311 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
312 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
313 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
314 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
315 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
316};
317
318void __init sh73a0_clock_init(void)
319{
320 int k, ret = 0;
321
322 /* detect main clock parent */
323 switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
324 case 0:
325 main_clk.parent = &sh73a0_extal1_clk;
326 break;
327 case 1:
328 main_clk.parent = &extal1_div2_clk;
329 break;
330 case 2:
331 main_clk.parent = &sh73a0_extal2_clk;
332 break;
333 case 3:
334 main_clk.parent = &extal2_div2_clk;
335 break;
336 }
337
338 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
339 ret = clk_register(main_clks[k]);
340
341 if (!ret)
342 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
343
344 if (!ret)
345 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
346
347 if (!ret)
348 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
349
350 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
351
352 if (!ret)
353 clk_init();
354 else
355 panic("failed to setup sh73a0 clocks\n");
356}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index efeef778a87..49ac8ebdc18 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -30,4 +30,12 @@ extern void sh7372_pinmux_init(void);
30extern struct clk sh7372_extal1_clk; 30extern struct clk sh7372_extal1_clk;
31extern struct clk sh7372_extal2_clk; 31extern struct clk sh7372_extal2_clk;
32 32
33extern void sh73a0_init_irq(void);
34extern void sh73a0_add_early_devices(void);
35extern void sh73a0_add_standard_devices(void);
36extern void sh73a0_clock_init(void);
37extern void sh73a0_pinmux_init(void);
38extern struct clk sh73a0_extal1_clk;
39extern struct clk sh73a0_extal2_clk;
40
33#endif /* __ARCH_MACH_COMMON_H */ 41#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro-gic.S b/arch/arm/mach-shmobile/include/mach/entry-macro-gic.S
new file mode 100644
index 00000000000..50b1f16d54a
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro-gic.S
@@ -0,0 +1,89 @@
1/*
2 * Copyright (C) 2010 Renesas Solutions Corp.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */
17#include <mach/hardware.h>
18#include <asm/hardware/gic.h>
19
20 .macro disable_fiq
21 .endm
22
23 .macro get_irqnr_preamble, base, tmp
24 ldr \base, =(0xf0000100)
25 .endm
26
27 .macro arch_ret_to_user, tmp1, tmp2
28 .endm
29
30 /*
31 * The interrupt numbering scheme is defined in the
32 * interrupt controller spec. To wit:
33 *
34 * Interrupts 0-15 are IPI
35 * 16-28 are reserved
36 * 29-31 are local. We allow 30 to be used for the watchdog.
37 * 32-1020 are global
38 * 1021-1022 are reserved
39 * 1023 is "spurious" (no interrupt)
40 *
41 * For now, we ignore all local interrupts so only return an
42 * interrupt if it's between 30 and 1020. The test_for_ipi
43 * routine below will pick up on IPIs.
44 *
45 * A simple read from the controller will tell us the number of
46 * the highest priority enabled interrupt. We then just need to
47 * check whether it is in the valid range for an IRQ (30-1020
48 * inclusive).
49 */
50
51 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
52
53 ldr \irqstat, [\base, #GIC_CPU_INTACK]
54 /* bits 12-10 = src CPU, 9-0 = int # */
55
56 ldr \tmp, =1021
57 bic \irqnr, \irqstat, #0x1c00
58 cmp \irqnr, #29
59 cmpcc \irqnr, \irqnr
60 cmpne \irqnr, \tmp
61 cmpcs \irqnr, \irqnr
62
63 .endm
64
65 /*
66 * We assume that irqstat (the raw value of the IRQ acknowledge
67 * register) is preserved from the macro above.
68 * If there is an IPI, we immediately signal end of interrupt on the
69 * controller, since this requires the original irqstat value which
70 * we won't easily be able to recreate later.
71 */
72
73 .macro test_for_ipi, irqnr, irqstat, base, tmp
74 bic \irqnr, \irqstat, #0x1c00
75 cmp \irqnr, #16
76 strcc \irqstat, [\base, #GIC_CPU_EOI]
77 cmpcs \irqnr, \irqnr
78 .endm
79
80 /* As above, this assumes that irqstat and base are preserved.. */
81
82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
83 bic \irqnr, \irqstat, #0x1c00
84 mov \tmp, #0
85 cmp \irqnr, #29
86 moveq \tmp, #1
87 streq \irqstat, [\base, #GIC_CPU_EOI]
88 cmp \tmp, #0
89 .endm
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro-intc.S b/arch/arm/mach-shmobile/include/mach/entry-macro-intc.S
new file mode 100644
index 00000000000..f428c4db2b6
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro-intc.S
@@ -0,0 +1,61 @@
1/*
2 * Copyright (C) 2010 Magnus Damm
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#include <mach/irqs.h>
19
20#define INTCA_BASE 0xe6980000
21#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
22#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
23#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
24#define INTLVLB_OFFS 0x00000034 /* previous priority level */
25
26 .macro disable_fiq
27 .endm
28
29 .macro get_irqnr_preamble, base, tmp
30 ldr \base, =INTCA_BASE
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
35
36 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
37 /* The single INTFLGA read access below results in the following:
38 *
39 * 1. INTLVLB is updated with old priority value from INTLVLA
40 * 2. Highest priority interrupt is accepted
41 * 3. INTLVLA is updated to contain priority of accepted interrupt
42 * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
43 */
44 ldr \irqnr, [\base, #INTFLGA_OFFS]
45
46 /* Restore INTLVLA with the value saved in INTLVLB.
47 * This is required to support interrupt priorities properly.
48 */
49 ldrb \tmp, [\base, #INTLVLB_OFFS]
50 strb \tmp, [\base, #INTLVLA_OFFS]
51
52 /* Handle invalid vector number case */
53 cmp \irqnr, #0
54 beq 1000f
55
56 /* Convert vector to irq number, same as the evt2irq() macro */
57 lsr \irqnr, \irqnr, #0x5
58 subs \irqnr, \irqnr, #16
59
601000:
61 .endm
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index f428c4db2b6..26e40116760 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,6 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Magnus Damm 2 * Copyright (C) 2010 Paul Mundt
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License as published by
@@ -15,47 +14,8 @@
15 * along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */ 16 */
18#include <mach/irqs.h> 17#if defined(CONFIG_ARM_GIC)
19 18#include <mach/entry-macro-gic.S>
20#define INTCA_BASE 0xe6980000 19#else
21#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */ 20#include <mach/entry-macro-intc.S>
22#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */ 21#endif
23#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
24#define INTLVLB_OFFS 0x00000034 /* previous priority level */
25
26 .macro disable_fiq
27 .endm
28
29 .macro get_irqnr_preamble, base, tmp
30 ldr \base, =INTCA_BASE
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
35
36 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
37 /* The single INTFLGA read access below results in the following:
38 *
39 * 1. INTLVLB is updated with old priority value from INTLVLA
40 * 2. Highest priority interrupt is accepted
41 * 3. INTLVLA is updated to contain priority of accepted interrupt
42 * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
43 */
44 ldr \irqnr, [\base, #INTFLGA_OFFS]
45
46 /* Restore INTLVLA with the value saved in INTLVLB.
47 * This is required to support interrupt priorities properly.
48 */
49 ldrb \tmp, [\base, #INTLVLB_OFFS]
50 strb \tmp, [\base, #INTLVLA_OFFS]
51
52 /* Handle invalid vector number case */
53 cmp \irqnr, #0
54 beq 1000f
55
56 /* Convert vector to irq number, same as the evt2irq() macro */
57 lsr \irqnr, \irqnr, #0x5
58 subs \irqnr, \irqnr, #16
59
601000:
61 .endm
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index fa15b5f8a00..dcb714f4d75 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -1,7 +1,10 @@
1#ifndef __ASM_MACH_IRQS_H 1#ifndef __ASM_MACH_IRQS_H
2#define __ASM_MACH_IRQS_H 2#define __ASM_MACH_IRQS_H
3 3
4#define NR_IRQS 512 4#define NR_IRQS 1024
5
6/* GIC */
7#define gic_spi(nr) ((nr) + 32)
5 8
6/* INTCA */ 9/* INTCA */
7#define evt2irq(evt) (((evt) >> 5) - 16) 10#define evt2irq(evt) (((evt) >> 5) - 16)
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index e4f9004e710..5736efcca60 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -455,6 +455,8 @@ enum {
455 SHDMA_SLAVE_SDHI1_TX, 455 SHDMA_SLAVE_SDHI1_TX,
456 SHDMA_SLAVE_SDHI2_RX, 456 SHDMA_SLAVE_SDHI2_RX,
457 SHDMA_SLAVE_SDHI2_TX, 457 SHDMA_SLAVE_SDHI2_TX,
458 SHDMA_SLAVE_MMCIF_RX,
459 SHDMA_SLAVE_MMCIF_TX,
458}; 460};
459 461
460extern struct clk sh7372_extal1_clk; 462extern struct clk sh7372_extal1_clk;
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
new file mode 100644
index 00000000000..ceb2cdc92bf
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -0,0 +1,467 @@
1#ifndef __ASM_SH73A0_H__
2#define __ASM_SH73A0_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
6 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 /* Hardware manual Table 25-1 (GPIO) */
10 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
11 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
12
13 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
14 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
15
16 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
17 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
18
19 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
20 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
21
22 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
23 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
24
25 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
26 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
27
28 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
29 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
30
31 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
32 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
33
34 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
35 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
36
37 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
38 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
39
40 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
41 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
42
43 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
44 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
45
46 GPIO_PORT128, GPIO_PORT129,
47
48 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
49 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
50
51 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
52 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
53
54 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
55 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
56
57 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
58
59 GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
60 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
61
62 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
63 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
64
65 GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
66 GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
67
68 GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
69 GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
70
71 GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
72 GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
73
74 GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
75 GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
76
77 GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
78 GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
79
80 GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
81 GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
82
83 GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
84 GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
85
86 GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
87
88 GPIO_PORT288, GPIO_PORT289,
89
90 GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
91 GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
92
93 GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
94 GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
95
96 /* Table 25-1 (Function 0-7) */
97 GPIO_FN_VBUS_0,
98 GPIO_FN_GPI0,
99 GPIO_FN_GPI1,
100 GPIO_FN_GPI2,
101 GPIO_FN_GPI3,
102 GPIO_FN_GPI4,
103 GPIO_FN_GPI5,
104 GPIO_FN_GPI6,
105 GPIO_FN_GPI7,
106 GPIO_FN_SCIFA7_RXD,
107 GPIO_FN_SCIFA7_CTS_,
108 GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
109 GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
110 GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
111 GPIO_FN_PORT16_VIO_CKOR,
112 GPIO_FN_SCIFA0_TXD,
113 GPIO_FN_SCIFA7_TXD,
114 GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
115 GPIO_FN_GPO0,
116 GPIO_FN_GPO1,
117 GPIO_FN_GPO2, GPIO_FN_STATUS0,
118 GPIO_FN_GPO3, GPIO_FN_STATUS1,
119 GPIO_FN_GPO4, GPIO_FN_STATUS2,
120 GPIO_FN_VINT,
121 GPIO_FN_TCKON,
122 GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
123 GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
124 GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
125 GPIO_FN_PORT28_TPU1TO1,
126 GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
127 GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
128 GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
129 GPIO_FN_SCIFA4_TXD,
130 GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
131 GPIO_FN_SCIFA4_RTS_,
132 GPIO_FN_SCIFA4_CTS_,
133 GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
134 GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
135 GPIO_FN_FSIBOSLD,
136 GPIO_FN_FSIBISLD,
137 GPIO_FN_VACK,
138 GPIO_FN_XTAL1L,
139 GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
140 GPIO_FN_SCIFA0_RXD,
141 GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
142 GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
143 GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
144 GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
145 GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
146 GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
147 GPIO_FN_FSIAOMC,
148 GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
149
150 GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
151 GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
152 GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
153 GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
154 GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
155 GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
156 GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
157 GPIO_FN_A0, GPIO_FN_BS_,
158 GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
159 GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
160 GPIO_FN_A14, GPIO_FN_KEYOUT5,
161 GPIO_FN_A15, GPIO_FN_KEYOUT4,
162 GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
163 GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
164 GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
165 GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
166 GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
167 GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
168 GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
169 GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
170 GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
171 GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
172 GPIO_FN_A26, GPIO_FN_KEYIN6,
173 GPIO_FN_KEYIN7,
174 GPIO_FN_D0_NAF0,
175 GPIO_FN_D1_NAF1,
176 GPIO_FN_D2_NAF2,
177 GPIO_FN_D3_NAF3,
178 GPIO_FN_D4_NAF4,
179 GPIO_FN_D5_NAF5,
180 GPIO_FN_D6_NAF6,
181 GPIO_FN_D7_NAF7,
182 GPIO_FN_D8_NAF8,
183 GPIO_FN_D9_NAF9,
184 GPIO_FN_D10_NAF10,
185 GPIO_FN_D11_NAF11,
186 GPIO_FN_D12_NAF12,
187 GPIO_FN_D13_NAF13,
188 GPIO_FN_D14_NAF14,
189 GPIO_FN_D15_NAF15,
190 GPIO_FN_CS4_,
191 GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
192 GPIO_FN_CS5B_, GPIO_FN_FCE1_,
193 GPIO_FN_CS6B_, GPIO_FN_DACK0,
194 GPIO_FN_FCE0_, GPIO_FN_CS6A_,
195 GPIO_FN_WAIT_, GPIO_FN_DREQ0,
196 GPIO_FN_RD__FSC,
197 GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
198 GPIO_FN_WE1_,
199 GPIO_FN_FRB,
200 GPIO_FN_CKO,
201 GPIO_FN_NBRSTOUT_,
202 GPIO_FN_NBRST_,
203 GPIO_FN_BBIF2_TXD,
204 GPIO_FN_BBIF2_RXD,
205 GPIO_FN_BBIF2_SYNC,
206 GPIO_FN_BBIF2_SCK,
207 GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
208 GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
209 GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
210 GPIO_FN_SCIFA3_TXD,
211 GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
212 GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
213 GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
214 GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
215 GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
216 GPIO_FN_PORT115_I2C_SCL3,
217 GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
218 GPIO_FN_PORT116_I2C_SDA3,
219 GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
220 GPIO_FN_HSI_TX_FLAG,
221 GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
222 GPIO_FN_LCD2D0,
223
224 GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
225 GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
226 GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
227 GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
228 GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
229 GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
230 GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
231 GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
232 GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
233 GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
234 GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
235 GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
236 GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
237 GPIO_FN_LCD2D6,
238 GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
239 GPIO_FN_LCD2D7,
240 GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
241 GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
242 GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
243 GPIO_FN_LCD2D2,
244 GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
245 GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
246 GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
247 GPIO_FN_LCD2D4,
248 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
249 GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
250 GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
251 GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
252 GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
253 GPIO_FN_VIO_CKO,
254 GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
255 GPIO_FN_PORT149_KEYOUT9,
256 GPIO_FN_MFG0_IN2,
257 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
258 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
259 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
260 GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
261 GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
262 GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
263 GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
264 GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
265 GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
266 GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
267 GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
268 GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
269 GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
270 GPIO_FN_TPU3TO0,
271 GPIO_FN_LCDD0,
272 GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
273 GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
274 GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
275 GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
276 GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
277 GPIO_FN_TPU2TO1,
278 GPIO_FN_LCDD6,
279 GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
280 GPIO_FN_LCDD8, GPIO_FN_D16,
281 GPIO_FN_LCDD9, GPIO_FN_D17,
282 GPIO_FN_LCDD10, GPIO_FN_D18,
283 GPIO_FN_LCDD11, GPIO_FN_D19,
284 GPIO_FN_LCDD12, GPIO_FN_D20,
285 GPIO_FN_LCDD13, GPIO_FN_D21,
286 GPIO_FN_LCDD14, GPIO_FN_D22,
287 GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
288 GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
289 GPIO_FN_LCDD17, GPIO_FN_D25,
290 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
291 GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
292 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
293 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
294 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
295 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
296 GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
297 GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
298 GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
299 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
300 GPIO_FN_PORT218_VIO_CKOR,
301 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
302 GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
303 GPIO_FN_LCD2DCK_2,
304 GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
305 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
306 GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
307 GPIO_FN_PORT221_LCD2HSYN,
308 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
309 GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
310
311 GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
312 GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
313 GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
314 GPIO_FN_SCIFA1_RXD,
315 GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
316 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
317 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
318 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
319 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
320 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
321 GPIO_FN_LCD2D20,
322 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
323 GPIO_FN_LCD2D21,
324 GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
325 GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
326 GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
327 GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
328 GPIO_FN_SCIFA6_TXD,
329 GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
330 GPIO_FN_TPU4TO0,
331 GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
332 GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
333 GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
334 GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
335 GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
336 GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
337 GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
338 GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
339 GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
340 GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
341 GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
342 GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
343 GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
344 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
345 GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
346 GPIO_FN_SDHICLK0,
347 GPIO_FN_SDHICD0,
348 GPIO_FN_SDHID0_0,
349 GPIO_FN_SDHID0_1,
350 GPIO_FN_SDHID0_2,
351 GPIO_FN_SDHID0_3,
352 GPIO_FN_SDHICMD0,
353 GPIO_FN_SDHIWP0,
354 GPIO_FN_SDHICLK1,
355 GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
356 GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
357 GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
358 GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
359 GPIO_FN_SDHICMD1,
360 GPIO_FN_SDHICLK2,
361 GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
362 GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
363 GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
364 GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
365 GPIO_FN_SDHICMD2,
366 GPIO_FN_MMCCLK0,
367 GPIO_FN_MMCD0_0,
368 GPIO_FN_MMCD0_1,
369 GPIO_FN_MMCD0_2,
370 GPIO_FN_MMCD0_3,
371 GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
372 GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
373 GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
374 GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
375 GPIO_FN_MMCCMD0,
376 GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
377 GPIO_FN_MCP_WAIT__MCP_FRB,
378 GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
379 GPIO_FN_MCP_D15_MCP_NAF15,
380 GPIO_FN_MCP_D14_MCP_NAF14,
381 GPIO_FN_MCP_D13_MCP_NAF13,
382 GPIO_FN_MCP_D12_MCP_NAF12,
383 GPIO_FN_MCP_D11_MCP_NAF11,
384 GPIO_FN_MCP_D10_MCP_NAF10,
385 GPIO_FN_MCP_D9_MCP_NAF9,
386 GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
387 GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
388
389 GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
390 GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
391 GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
392 GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
393 GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
394 GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
395 GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
396 GPIO_FN_MCP_NBRSTOUT_,
397 GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
398
399 /* MSEL2 special case */
400 GPIO_FN_TSIF2_TS_XX1,
401 GPIO_FN_TSIF2_TS_XX2,
402 GPIO_FN_TSIF2_TS_XX3,
403 GPIO_FN_TSIF2_TS_XX4,
404 GPIO_FN_TSIF2_TS_XX5,
405 GPIO_FN_TSIF1_TS_XX1,
406 GPIO_FN_TSIF1_TS_XX2,
407 GPIO_FN_TSIF1_TS_XX3,
408 GPIO_FN_TSIF1_TS_XX4,
409 GPIO_FN_TSIF1_TS_XX5,
410 GPIO_FN_TSIF0_TS_XX1,
411 GPIO_FN_TSIF0_TS_XX2,
412 GPIO_FN_TSIF0_TS_XX3,
413 GPIO_FN_TSIF0_TS_XX4,
414 GPIO_FN_TSIF0_TS_XX5,
415 GPIO_FN_MST1_TS_XX1,
416 GPIO_FN_MST1_TS_XX2,
417 GPIO_FN_MST1_TS_XX3,
418 GPIO_FN_MST1_TS_XX4,
419 GPIO_FN_MST1_TS_XX5,
420 GPIO_FN_MST0_TS_XX1,
421 GPIO_FN_MST0_TS_XX2,
422 GPIO_FN_MST0_TS_XX3,
423 GPIO_FN_MST0_TS_XX4,
424 GPIO_FN_MST0_TS_XX5,
425
426 /* MSEL3 special cases */
427 GPIO_FN_SDHI0_VCCQ_MC0_ON,
428 GPIO_FN_SDHI0_VCCQ_MC0_OFF,
429 GPIO_FN_DEBUG_MON_VIO,
430 GPIO_FN_DEBUG_MON_LCDD,
431 GPIO_FN_LCDC_LCDC0,
432 GPIO_FN_LCDC_LCDC1,
433
434 /* MSEL4 special cases */
435 GPIO_FN_IRQ9_MEM_INT,
436 GPIO_FN_IRQ9_MCP_INT,
437 GPIO_FN_A11,
438 GPIO_FN_KEYOUT8,
439 GPIO_FN_TPU4TO3,
440 GPIO_FN_RESETA_N_PU_ON,
441 GPIO_FN_RESETA_N_PU_OFF,
442 GPIO_FN_EDBGREQ_PD,
443 GPIO_FN_EDBGREQ_PU,
444
445 /* Functions with pull-ups */
446 GPIO_FN_KEYIN0_PU,
447 GPIO_FN_KEYIN1_PU,
448 GPIO_FN_KEYIN2_PU,
449 GPIO_FN_KEYIN3_PU,
450 GPIO_FN_KEYIN4_PU,
451 GPIO_FN_KEYIN5_PU,
452 GPIO_FN_KEYIN6_PU,
453 GPIO_FN_KEYIN7_PU,
454 GPIO_FN_SDHID1_0_PU,
455 GPIO_FN_SDHID1_1_PU,
456 GPIO_FN_SDHID1_2_PU,
457 GPIO_FN_SDHID1_3_PU,
458 GPIO_FN_SDHICMD1_PU,
459 GPIO_FN_MMCCMD0_PU,
460 GPIO_FN_MMCCMD1_PU,
461 GPIO_FN_FSIACK_PU,
462 GPIO_FN_FSIAILR_PU,
463 GPIO_FN_FSIAIBT_PU,
464 GPIO_FN_FSIAISLD_PU,
465};
466
467#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
new file mode 100644
index 00000000000..5af2be07c2b
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -0,0 +1,267 @@
1/*
2 * sh73a0 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <asm/hardware/gic.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28
29enum {
30 UNUSED = 0,
31
32 /* interrupt sources INTCS */
33 PINTCS_PINT1, PINTCS_PINT2,
34 RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
35 CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
36 RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
37 KEYSC_KEY, VINT, MSIOF,
38 TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
39 CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
40 CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
41 RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
42 RTDMAC_3_DEI10, RTDMAC_3_DEI11,
43 FRC, GCU, LCDC1, CSIRX,
44 DSITX0_DSITX00, DSITX0_DSITX01,
45 SPU2_SPU0, SPU2_SPU1, FSI,
46 TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
47 TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
48 VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
49 DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
50 MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
51 SPUV,
52
53 /* interrupt groups INTCS */
54 RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
55 DSITX0, SPU2, TMU1, MSU,
56};
57
58static struct intc_vect intcs_vectors[] = {
59 INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
60 INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
61 INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
62 INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
63 INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
64 INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
65 INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
66 INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
67 INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
68 INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
69 INTCS_VECT(MSIOF, 0x0d20),
70 INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
71 INTCS_VECT(TMU0_TUNI02, 0x0ec0),
72 INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
73 INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
74 INTCS_VECT(MSUG, 0x0f80),
75 INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
76 INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
77 INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
78 INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
79 INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
80 INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
81 INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
82 INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
83 INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
84 INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
85 INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
86 INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
87 INTCS_VECT(FSI, 0x1840),
88 INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
89 INTCS_VECT(TMU1_TUNI12, 0x1940),
90 INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
91 INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
92 INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
93 INTCS_VECT(SCUW, 0x1b40),
94 INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
95 INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
96 INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
97 INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
98 INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
99 INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
100 INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
101 INTCS_VECT(SPUV, 0x2300),
102};
103
104static struct intc_group intcs_groups[] __initdata = {
105 INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
106 RTDMAC_0_DEI2, RTDMAC_0_DEI3),
107 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
108 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
109 RTDMAC_2_DEI8, RTDMAC_2_DEI9),
110 INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
111 INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
112 INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
113 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
114 INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
115};
116
117static struct intc_mask_reg intcs_mask_registers[] = {
118 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
119 { 0, 0, 0, CEU,
120 0, 0, 0, 0 } },
121 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
122 { 0, 0, 0, VPU,
123 BBIF2, 0, 0, MFI } },
124 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
125 { 0, 0, 0, _2DDMAC_2DDM0,
126 0, ASA, PEP, ICB } },
127 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
128 { 0, 0, 0, CTI,
129 JPU_JPEG, 0, LCRC, LCDC } },
130 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
131 { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
132 RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
133 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
134 { 0, 0, MSIOF, 0,
135 _3DG_SGX543, 0, 0, 0 } },
136 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
137 { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
138 0, 0, 0, 0 } },
139 { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
140 { 0, 0, 0, 0,
141 0, MSU_MSU, MSU_MSU2, MSUG } },
142 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
143 { 0, RWDT0, CMT2, CMT0,
144 0, 0, 0, 0 } },
145 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
146 { 0, 0, 0, 0,
147 0, TSIF1, LMB, TSIF0 } },
148 { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
149 { 0, 0, 0, 0,
150 0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
151 { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
152 { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
153 RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
154 { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
155 { FRC, 0, 0, GCU,
156 LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
157 { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
158 { SPU2_SPU0, SPU2_SPU1, FSI, 0,
159 0, 0, 0, 0 } },
160 { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
161 { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
162 TSIF2, CMT4, 0, 0 } },
163 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
164 { MFIS2, CPORTS2R, 0, 0,
165 0, 0, 0, TSG } },
166 { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
167 { DMASCH1, 0, SCUW, VIO60,
168 VIO61, CEU21, 0, CSI21 } },
169 { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
170 { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
171 EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
172 { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
173 { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
174 0, 0, 0, 0 } },
175 { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
176 { SPUV, 0, 0, 0,
177 0, 0, 0, 0 } },
178};
179
180/* Priority is needed for INTCA to receive the INTCS interrupt */
181static struct intc_prio_reg intcs_prio_registers[] = {
182 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
183 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
184 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
185 { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
186 0, 0 } },
187 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
188 { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
189 CMT2, CMT0 } },
190 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
191 TMU0_TUNI02, TSIF1 } },
192 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
193 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
194 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
195 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
196 { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
197 { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
198 { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
199 { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
200 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
201 { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
202 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
203 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
204 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
205 { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
206 { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
207 { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
208 DISP, DSRV } },
209 { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
210 MSTIF0_MST00I, MSTIF0_MST01I } },
211 { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
212 0, 0 } },
213 { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
214};
215
216static struct resource intcs_resources[] __initdata = {
217 [0] = {
218 .start = 0xffd20000,
219 .end = 0xffd201ff,
220 .flags = IORESOURCE_MEM,
221 },
222 [1] = {
223 .start = 0xffd50000,
224 .end = 0xffd501ff,
225 .flags = IORESOURCE_MEM,
226 },
227 [2] = {
228 .start = 0xffd60000,
229 .end = 0xffd601ff,
230 .flags = IORESOURCE_MEM,
231 }
232};
233
234static struct intc_desc intcs_desc __initdata = {
235 .name = "sh73a0-intcs",
236 .resource = intcs_resources,
237 .num_resources = ARRAY_SIZE(intcs_resources),
238 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
239 intcs_prio_registers, NULL, NULL),
240};
241
242static struct irqaction sh73a0_intcs_cascade;
243
244static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
245{
246 unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
247
248 generic_handle_irq(intcs_evt2irq(evtcodeas));
249
250 return IRQ_HANDLED;
251}
252
253void __init sh73a0_init_irq(void)
254{
255 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
256
257 gic_dist_init(0, __io(0xf0001000), 29);
258 gic_cpu_init(0, __io(0xf0000100));
259
260 register_intc_controller(&intcs_desc);
261
262 /* demux using INTEVTSA */
263 sh73a0_intcs_cascade.name = "INTCS cascade";
264 sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
265 sh73a0_intcs_cascade.dev_id = intevtsa;
266 setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
267}
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
new file mode 100644
index 00000000000..3eed44eb98b
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -0,0 +1,2746 @@
1/*
2 * sh73a0 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Copyright (C) 2010 NISHIMOTO Hiroki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/gpio.h>
24#include <mach/sh73a0.h>
25
26#define _1(fn, pfx, sfx) fn(pfx, sfx)
27
28#define _10(fn, pfx, sfx) \
29 _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
30 _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
31 _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
32 _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
33 _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
34
35#define _310(fn, pfx, sfx) \
36 _10(fn, pfx, sfx), _10(fn, pfx##1, sfx), \
37 _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx), \
38 _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx), \
39 _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx), \
40 _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx), \
41 _10(fn, pfx##10, sfx), \
42 _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \
43 _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \
44 _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \
45 _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \
46 _1(fn, pfx##118, sfx), \
47 _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \
48 _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \
49 _10(fn, pfx##15, sfx), \
50 _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \
51 _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \
52 _1(fn, pfx##164, sfx), \
53 _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \
54 _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \
55 _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \
56 _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
57 _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
58 _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
59 _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
60 _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx), \
61 _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx), \
62 _1(fn, pfx##282, sfx), \
63 _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx), \
64 _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
65
66#define _PORT(pfx, sfx) pfx##_##sfx
67#define PORT_310(str) _310(_PORT, PORT, str)
68
69enum {
70 PINMUX_RESERVED = 0,
71
72 PINMUX_DATA_BEGIN,
73 PORT_310(DATA), /* PORT0_DATA -> PORT309_DATA */
74 PINMUX_DATA_END,
75
76 PINMUX_INPUT_BEGIN,
77 PORT_310(IN), /* PORT0_IN -> PORT309_IN */
78 PINMUX_INPUT_END,
79
80 PINMUX_INPUT_PULLUP_BEGIN,
81 PORT_310(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
82 PINMUX_INPUT_PULLUP_END,
83
84 PINMUX_INPUT_PULLDOWN_BEGIN,
85 PORT_310(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
86 PINMUX_INPUT_PULLDOWN_END,
87
88 PINMUX_OUTPUT_BEGIN,
89 PORT_310(OUT), /* PORT0_OUT -> PORT309_OUT */
90 PINMUX_OUTPUT_END,
91
92 PINMUX_FUNCTION_BEGIN,
93 PORT_310(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
94 PORT_310(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
95 PORT_310(FN0), /* PORT0_FN0 -> PORT309_FN0 */
96 PORT_310(FN1), /* PORT0_FN1 -> PORT309_FN1 */
97 PORT_310(FN2), /* PORT0_FN2 -> PORT309_FN2 */
98 PORT_310(FN3), /* PORT0_FN3 -> PORT309_FN3 */
99 PORT_310(FN4), /* PORT0_FN4 -> PORT309_FN4 */
100 PORT_310(FN5), /* PORT0_FN5 -> PORT309_FN5 */
101 PORT_310(FN6), /* PORT0_FN6 -> PORT309_FN6 */
102 PORT_310(FN7), /* PORT0_FN7 -> PORT309_FN7 */
103
104 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
105 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
106 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
107 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
108 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
109 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
110 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
111 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
112 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
113 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
114 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
115 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
116 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
117 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
118 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
119 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
120 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
121 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
122 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
123 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
124 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
125 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
126 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
127 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
128 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
129 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
130 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
131 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
132 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
133 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
134 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
135 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
136 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
137 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
138 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
139 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
140 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
141 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
142 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
143 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
144 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
145 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
146 PINMUX_FUNCTION_END,
147
148 PINMUX_MARK_BEGIN,
149 /* Hardware manual Table 25-1 (Function 0-7) */
150 VBUS_0_MARK,
151 GPI0_MARK,
152 GPI1_MARK,
153 GPI2_MARK,
154 GPI3_MARK,
155 GPI4_MARK,
156 GPI5_MARK,
157 GPI6_MARK,
158 GPI7_MARK,
159 SCIFA7_RXD_MARK,
160 SCIFA7_CTS__MARK,
161 GPO7_MARK, MFG0_OUT2_MARK,
162 GPO6_MARK, MFG1_OUT2_MARK,
163 GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
164 SCIFA0_TXD_MARK,
165 SCIFA7_TXD_MARK,
166 SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
167 GPO0_MARK,
168 GPO1_MARK,
169 GPO2_MARK, STATUS0_MARK,
170 GPO3_MARK, STATUS1_MARK,
171 GPO4_MARK, STATUS2_MARK,
172 VINT_MARK,
173 TCKON_MARK,
174 XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
175 MFG0_OUT1_MARK, PORT27_IROUT_MARK,
176 XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
177 PORT28_TPU1TO1_MARK,
178 SIM_RST_MARK, PORT29_TPU1TO1_MARK,
179 SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
180 SIM_D_MARK, PORT31_IROUT_MARK,
181 SCIFA4_TXD_MARK,
182 SCIFA4_RXD_MARK, XWUP_MARK,
183 SCIFA4_RTS__MARK,
184 SCIFA4_CTS__MARK,
185 FSIBOBT_MARK, FSIBIBT_MARK,
186 FSIBOLR_MARK, FSIBILR_MARK,
187 FSIBOSLD_MARK,
188 FSIBISLD_MARK,
189 VACK_MARK,
190 XTAL1L_MARK,
191 SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
192 SCIFA0_RXD_MARK,
193 SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
194 FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
195 FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
196 FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
197 FSICISLD_MARK, FSIDISLD_MARK,
198 FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
199 FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
200
201 FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
202 FSIAOSLD_MARK, BBIF2_TXD2_MARK,
203 FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
204 PORT53_FSICSPDIF_MARK,
205 FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
206 FSICCK_MARK, FSICOMC_MARK,
207 FSIAISLD_MARK, TPU0TO0_MARK,
208 A0_MARK, BS__MARK,
209 A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
210 A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
211 A14_MARK, KEYOUT5_MARK,
212 A15_MARK, KEYOUT4_MARK,
213 A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
214 A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
215 A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
216 A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
217 A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
218 A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
219 A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
220 A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
221 A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
222 A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
223 A26_MARK, KEYIN6_MARK,
224 KEYIN7_MARK,
225 D0_NAF0_MARK,
226 D1_NAF1_MARK,
227 D2_NAF2_MARK,
228 D3_NAF3_MARK,
229 D4_NAF4_MARK,
230 D5_NAF5_MARK,
231 D6_NAF6_MARK,
232 D7_NAF7_MARK,
233 D8_NAF8_MARK,
234 D9_NAF9_MARK,
235 D10_NAF10_MARK,
236 D11_NAF11_MARK,
237 D12_NAF12_MARK,
238 D13_NAF13_MARK,
239 D14_NAF14_MARK,
240 D15_NAF15_MARK,
241 CS4__MARK,
242 CS5A__MARK, PORT91_RDWR_MARK,
243 CS5B__MARK, FCE1__MARK,
244 CS6B__MARK, DACK0_MARK,
245 FCE0__MARK, CS6A__MARK,
246 WAIT__MARK, DREQ0_MARK,
247 RD__FSC_MARK,
248 WE0__FWE_MARK, RDWR_FWE_MARK,
249 WE1__MARK,
250 FRB_MARK,
251 CKO_MARK,
252 NBRSTOUT__MARK,
253 NBRST__MARK,
254 BBIF2_TXD_MARK,
255 BBIF2_RXD_MARK,
256 BBIF2_SYNC_MARK,
257 BBIF2_SCK_MARK,
258 SCIFA3_CTS__MARK, MFG3_IN2_MARK,
259 SCIFA3_RXD_MARK, MFG3_IN1_MARK,
260 BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
261 SCIFA3_TXD_MARK,
262 HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
263 HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
264 HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
265 HSI_TX_READY_MARK, BBIF1_TXD_MARK,
266 HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
267 PORT115_I2C_SCL3_MARK,
268 HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
269 PORT116_I2C_SDA3_MARK,
270 HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
271 HSI_TX_FLAG_MARK,
272 VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
273
274 VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
275 VIO2_HD_MARK, LCD2D1_MARK,
276 VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
277 VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
278 PORT131_KEYOUT11_MARK, LCD2D11_MARK,
279 VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
280 PORT132_KEYOUT10_MARK, LCD2D12_MARK,
281 VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
282 VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
283 VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
284 VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
285 VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
286 VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
287 VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
288 VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
289 VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
290 VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
291 VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
292 VIO2_D5_MARK, LCD2D3_MARK,
293 VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
294 VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
295 PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
296 VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
297 LCD2D18_MARK,
298 VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
299 VIO_CKO_MARK,
300 A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
301 MFG0_IN2_MARK,
302 TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
303 TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
304 TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
305 SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
306 SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
307 SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
308 SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
309 DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
310 PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
311 PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
312 PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
313 PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
314 PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
315 LCDD0_MARK,
316 LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
317 LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
318 LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
319 LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
320 LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
321 LCDD6_MARK,
322 LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
323 LCDD8_MARK, D16_MARK,
324 LCDD9_MARK, D17_MARK,
325 LCDD10_MARK, D18_MARK,
326 LCDD11_MARK, D19_MARK,
327 LCDD12_MARK, D20_MARK,
328 LCDD13_MARK, D21_MARK,
329 LCDD14_MARK, D22_MARK,
330 LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
331 LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
332 LCDD17_MARK, D25_MARK,
333 LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
334 LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
335 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
336 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
337 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
338 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
339 LCDDCK_MARK, LCDWR__MARK,
340 LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
341 VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
342 LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
343 PORT218_VIO_CKOR_MARK,
344 LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
345 MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
346 LCDVSYN_MARK, LCDVSYN2_MARK,
347 LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
348 MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
349 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
350 VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
351
352 SCIFA1_TXD_MARK, OVCN2_MARK,
353 EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
354 SCIFA1_RTS__MARK, IDIN_MARK,
355 SCIFA1_RXD_MARK,
356 SCIFA1_CTS__MARK, MFG1_IN1_MARK,
357 MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
358 MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
359 MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
360 MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
361 MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
362 MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
363 MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
364 MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
365 MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
366 MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
367 SCIFA6_TXD_MARK,
368 PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
369 PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
370 PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
371 PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
372 MSIOF2R_RXD_MARK,
373 PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
374 MSIOF2R_TXD_MARK,
375 PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
376 TPU1TO0_MARK,
377 PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
378 TPU3TO1_MARK,
379 PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
380 TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
381 PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
382 MSIOF2R_TSYNC_MARK,
383 SDHICLK0_MARK,
384 SDHICD0_MARK,
385 SDHID0_0_MARK,
386 SDHID0_1_MARK,
387 SDHID0_2_MARK,
388 SDHID0_3_MARK,
389 SDHICMD0_MARK,
390 SDHIWP0_MARK,
391 SDHICLK1_MARK,
392 SDHID1_0_MARK, TS_SPSYNC2_MARK,
393 SDHID1_1_MARK, TS_SDAT2_MARK,
394 SDHID1_2_MARK, TS_SDEN2_MARK,
395 SDHID1_3_MARK, TS_SCK2_MARK,
396 SDHICMD1_MARK,
397 SDHICLK2_MARK,
398 SDHID2_0_MARK, TS_SPSYNC4_MARK,
399 SDHID2_1_MARK, TS_SDAT4_MARK,
400 SDHID2_2_MARK, TS_SDEN4_MARK,
401 SDHID2_3_MARK, TS_SCK4_MARK,
402 SDHICMD2_MARK,
403 MMCCLK0_MARK,
404 MMCD0_0_MARK,
405 MMCD0_1_MARK,
406 MMCD0_2_MARK,
407 MMCD0_3_MARK,
408 MMCD0_4_MARK, TS_SPSYNC5_MARK,
409 MMCD0_5_MARK, TS_SDAT5_MARK,
410 MMCD0_6_MARK, TS_SDEN5_MARK,
411 MMCD0_7_MARK, TS_SCK5_MARK,
412 MMCCMD0_MARK,
413 RESETOUTS__MARK, EXTAL2OUT_MARK,
414 MCP_WAIT__MCP_FRB_MARK,
415 MCP_CKO_MARK, MMCCLK1_MARK,
416 MCP_D15_MCP_NAF15_MARK,
417 MCP_D14_MCP_NAF14_MARK,
418 MCP_D13_MCP_NAF13_MARK,
419 MCP_D12_MCP_NAF12_MARK,
420 MCP_D11_MCP_NAF11_MARK,
421 MCP_D10_MCP_NAF10_MARK,
422 MCP_D9_MCP_NAF9_MARK,
423 MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
424 MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
425
426 MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
427 MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
428 MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
429 MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
430 MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
431 MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
432 MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
433 MCP_NBRSTOUT__MARK,
434 MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
435
436 /* MSEL2 special cases */
437 TSIF2_TS_XX1_MARK,
438 TSIF2_TS_XX2_MARK,
439 TSIF2_TS_XX3_MARK,
440 TSIF2_TS_XX4_MARK,
441 TSIF2_TS_XX5_MARK,
442 TSIF1_TS_XX1_MARK,
443 TSIF1_TS_XX2_MARK,
444 TSIF1_TS_XX3_MARK,
445 TSIF1_TS_XX4_MARK,
446 TSIF1_TS_XX5_MARK,
447 TSIF0_TS_XX1_MARK,
448 TSIF0_TS_XX2_MARK,
449 TSIF0_TS_XX3_MARK,
450 TSIF0_TS_XX4_MARK,
451 TSIF0_TS_XX5_MARK,
452 MST1_TS_XX1_MARK,
453 MST1_TS_XX2_MARK,
454 MST1_TS_XX3_MARK,
455 MST1_TS_XX4_MARK,
456 MST1_TS_XX5_MARK,
457 MST0_TS_XX1_MARK,
458 MST0_TS_XX2_MARK,
459 MST0_TS_XX3_MARK,
460 MST0_TS_XX4_MARK,
461 MST0_TS_XX5_MARK,
462
463 /* MSEL3 special cases */
464 SDHI0_VCCQ_MC0_ON_MARK,
465 SDHI0_VCCQ_MC0_OFF_MARK,
466 DEBUG_MON_VIO_MARK,
467 DEBUG_MON_LCDD_MARK,
468 LCDC_LCDC0_MARK,
469 LCDC_LCDC1_MARK,
470
471 /* MSEL4 special cases */
472 IRQ9_MEM_INT_MARK,
473 IRQ9_MCP_INT_MARK,
474 A11_MARK,
475 KEYOUT8_MARK,
476 TPU4TO3_MARK,
477 RESETA_N_PU_ON_MARK,
478 RESETA_N_PU_OFF_MARK,
479 EDBGREQ_PD_MARK,
480 EDBGREQ_PU_MARK,
481
482 /* Functions with pull-ups */
483 KEYIN0_PU_MARK,
484 KEYIN1_PU_MARK,
485 KEYIN2_PU_MARK,
486 KEYIN3_PU_MARK,
487 KEYIN4_PU_MARK,
488 KEYIN5_PU_MARK,
489 KEYIN6_PU_MARK,
490 KEYIN7_PU_MARK,
491 SDHID1_0_PU_MARK,
492 SDHID1_1_PU_MARK,
493 SDHID1_2_PU_MARK,
494 SDHID1_3_PU_MARK,
495 SDHICMD1_PU_MARK,
496 MMCCMD0_PU_MARK,
497 MMCCMD1_PU_MARK,
498 FSIACK_PU_MARK,
499 FSIAILR_PU_MARK,
500 FSIAIBT_PU_MARK,
501 FSIAISLD_PU_MARK,
502
503 PINMUX_MARK_END,
504};
505
506#define PORT_DATA_I(nr) \
507 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
508
509#define PORT_DATA_I_PD(nr) \
510 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
511 PORT##nr##_IN, PORT##nr##_IN_PD)
512
513#define PORT_DATA_I_PU(nr) \
514 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
515 PORT##nr##_IN, PORT##nr##_IN_PU)
516
517#define PORT_DATA_I_PU_PD(nr) \
518 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
519 PORT##nr##_IN, PORT##nr##_IN_PD, \
520 PORT##nr##_IN_PU)
521
522#define PORT_DATA_O(nr) \
523 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
524 PORT##nr##_OUT)
525
526#define PORT_DATA_IO(nr) \
527 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
528 PORT##nr##_OUT, PORT##nr##_IN)
529
530#define PORT_DATA_IO_PD(nr) \
531 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
532 PORT##nr##_OUT, PORT##nr##_IN, \
533 PORT##nr##_IN_PD)
534
535#define PORT_DATA_IO_PU(nr) \
536 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
537 PORT##nr##_OUT, PORT##nr##_IN, \
538 PORT##nr##_IN_PU)
539
540#define PORT_DATA_IO_PU_PD(nr) \
541 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
542 PORT##nr##_OUT, PORT##nr##_IN, \
543 PORT##nr##_IN_PD, PORT##nr##_IN_PU)
544
545static pinmux_enum_t pinmux_data[] = {
546 /* specify valid pin states for each pin in GPIO mode */
547
548 /* Table 25-1 (I/O and Pull U/D) */
549 PORT_DATA_I_PD(0),
550 PORT_DATA_I_PU(1),
551 PORT_DATA_I_PU(2),
552 PORT_DATA_I_PU(3),
553 PORT_DATA_I_PU(4),
554 PORT_DATA_I_PU(5),
555 PORT_DATA_I_PU(6),
556 PORT_DATA_I_PU(7),
557 PORT_DATA_I_PU(8),
558 PORT_DATA_I_PD(9),
559 PORT_DATA_I_PD(10),
560 PORT_DATA_I_PU_PD(11),
561 PORT_DATA_IO_PU_PD(12),
562 PORT_DATA_IO_PU_PD(13),
563 PORT_DATA_IO_PU_PD(14),
564 PORT_DATA_IO_PU_PD(15),
565 PORT_DATA_IO_PD(16),
566 PORT_DATA_IO_PD(17),
567 PORT_DATA_IO_PU(18),
568 PORT_DATA_IO_PU(19),
569 PORT_DATA_O(20),
570 PORT_DATA_O(21),
571 PORT_DATA_O(22),
572 PORT_DATA_O(23),
573 PORT_DATA_O(24),
574 PORT_DATA_I_PD(25),
575 PORT_DATA_I_PD(26),
576 PORT_DATA_IO_PU(27),
577 PORT_DATA_IO_PU(28),
578 PORT_DATA_IO_PD(29),
579 PORT_DATA_IO_PD(30),
580 PORT_DATA_IO_PU(31),
581 PORT_DATA_IO_PD(32),
582 PORT_DATA_I_PU_PD(33),
583 PORT_DATA_IO_PD(34),
584 PORT_DATA_I_PU_PD(35),
585 PORT_DATA_IO_PD(36),
586 PORT_DATA_IO(37),
587 PORT_DATA_O(38),
588 PORT_DATA_I_PU(39),
589 PORT_DATA_I_PU_PD(40),
590 PORT_DATA_O(41),
591 PORT_DATA_IO_PD(42),
592 PORT_DATA_IO_PU_PD(43),
593 PORT_DATA_IO_PU_PD(44),
594 PORT_DATA_IO_PD(45),
595 PORT_DATA_IO_PD(46),
596 PORT_DATA_IO_PD(47),
597 PORT_DATA_I_PD(48),
598 PORT_DATA_IO_PU_PD(49),
599 PORT_DATA_IO_PD(50),
600
601 PORT_DATA_IO_PD(51),
602 PORT_DATA_O(52),
603 PORT_DATA_IO_PU_PD(53),
604 PORT_DATA_IO_PU_PD(54),
605 PORT_DATA_IO_PD(55),
606 PORT_DATA_I_PU_PD(56),
607 PORT_DATA_IO(57),
608 PORT_DATA_IO(58),
609 PORT_DATA_IO(59),
610 PORT_DATA_IO(60),
611 PORT_DATA_IO(61),
612 PORT_DATA_IO_PD(62),
613 PORT_DATA_IO_PD(63),
614 PORT_DATA_IO_PU_PD(64),
615 PORT_DATA_IO_PD(65),
616 PORT_DATA_IO_PU_PD(66),
617 PORT_DATA_IO_PU_PD(67),
618 PORT_DATA_IO_PU_PD(68),
619 PORT_DATA_IO_PU_PD(69),
620 PORT_DATA_IO_PU_PD(70),
621 PORT_DATA_IO_PU_PD(71),
622 PORT_DATA_IO_PU_PD(72),
623 PORT_DATA_I_PU_PD(73),
624 PORT_DATA_IO_PU(74),
625 PORT_DATA_IO_PU(75),
626 PORT_DATA_IO_PU(76),
627 PORT_DATA_IO_PU(77),
628 PORT_DATA_IO_PU(78),
629 PORT_DATA_IO_PU(79),
630 PORT_DATA_IO_PU(80),
631 PORT_DATA_IO_PU(81),
632 PORT_DATA_IO_PU(82),
633 PORT_DATA_IO_PU(83),
634 PORT_DATA_IO_PU(84),
635 PORT_DATA_IO_PU(85),
636 PORT_DATA_IO_PU(86),
637 PORT_DATA_IO_PU(87),
638 PORT_DATA_IO_PU(88),
639 PORT_DATA_IO_PU(89),
640 PORT_DATA_O(90),
641 PORT_DATA_IO_PU(91),
642 PORT_DATA_O(92),
643 PORT_DATA_IO_PU(93),
644 PORT_DATA_O(94),
645 PORT_DATA_I_PU_PD(95),
646 PORT_DATA_IO(96),
647 PORT_DATA_IO(97),
648 PORT_DATA_IO(98),
649 PORT_DATA_I_PU(99),
650 PORT_DATA_O(100),
651 PORT_DATA_O(101),
652 PORT_DATA_I_PU(102),
653 PORT_DATA_IO_PD(103),
654 PORT_DATA_I_PU_PD(104),
655 PORT_DATA_I_PD(105),
656 PORT_DATA_I_PD(106),
657 PORT_DATA_I_PU_PD(107),
658 PORT_DATA_I_PU_PD(108),
659 PORT_DATA_IO_PD(109),
660 PORT_DATA_IO_PD(110),
661 PORT_DATA_IO_PU_PD(111),
662 PORT_DATA_IO_PU_PD(112),
663 PORT_DATA_IO_PU_PD(113),
664 PORT_DATA_IO_PD(114),
665 PORT_DATA_IO_PU(115),
666 PORT_DATA_IO_PU(116),
667 PORT_DATA_IO_PU_PD(117),
668 PORT_DATA_IO_PU_PD(118),
669 PORT_DATA_IO_PD(128),
670
671 PORT_DATA_IO_PD(129),
672 PORT_DATA_IO_PU_PD(130),
673 PORT_DATA_IO_PD(131),
674 PORT_DATA_IO_PD(132),
675 PORT_DATA_IO_PD(133),
676 PORT_DATA_IO_PU_PD(134),
677 PORT_DATA_IO_PU_PD(135),
678 PORT_DATA_IO_PU_PD(136),
679 PORT_DATA_IO_PU_PD(137),
680 PORT_DATA_IO_PD(138),
681 PORT_DATA_IO_PD(139),
682 PORT_DATA_IO_PD(140),
683 PORT_DATA_IO_PD(141),
684 PORT_DATA_IO_PD(142),
685 PORT_DATA_IO_PD(143),
686 PORT_DATA_IO_PU_PD(144),
687 PORT_DATA_IO_PD(145),
688 PORT_DATA_IO_PU_PD(146),
689 PORT_DATA_IO_PU_PD(147),
690 PORT_DATA_IO_PU_PD(148),
691 PORT_DATA_IO_PU_PD(149),
692 PORT_DATA_I_PU_PD(150),
693 PORT_DATA_IO_PU_PD(151),
694 PORT_DATA_IO_PU_PD(152),
695 PORT_DATA_IO_PD(153),
696 PORT_DATA_IO_PD(154),
697 PORT_DATA_I_PU_PD(155),
698 PORT_DATA_IO_PU_PD(156),
699 PORT_DATA_I_PD(157),
700 PORT_DATA_IO_PD(158),
701 PORT_DATA_IO_PU_PD(159),
702 PORT_DATA_IO_PU_PD(160),
703 PORT_DATA_I_PU_PD(161),
704 PORT_DATA_I_PU_PD(162),
705 PORT_DATA_IO_PU_PD(163),
706 PORT_DATA_I_PU_PD(164),
707 PORT_DATA_IO_PD(192),
708 PORT_DATA_IO_PU_PD(193),
709 PORT_DATA_IO_PD(194),
710 PORT_DATA_IO_PU_PD(195),
711 PORT_DATA_IO_PD(196),
712 PORT_DATA_IO_PD(197),
713 PORT_DATA_IO_PD(198),
714 PORT_DATA_IO_PD(199),
715 PORT_DATA_IO_PU_PD(200),
716 PORT_DATA_IO_PU_PD(201),
717 PORT_DATA_IO_PU_PD(202),
718 PORT_DATA_IO_PU_PD(203),
719 PORT_DATA_IO_PU_PD(204),
720 PORT_DATA_IO_PU_PD(205),
721 PORT_DATA_IO_PU_PD(206),
722 PORT_DATA_IO_PD(207),
723 PORT_DATA_IO_PD(208),
724 PORT_DATA_IO_PD(209),
725 PORT_DATA_IO_PD(210),
726 PORT_DATA_IO_PD(211),
727 PORT_DATA_IO_PD(212),
728 PORT_DATA_IO_PD(213),
729 PORT_DATA_IO_PU_PD(214),
730 PORT_DATA_IO_PU_PD(215),
731 PORT_DATA_IO_PD(216),
732 PORT_DATA_IO_PD(217),
733 PORT_DATA_O(218),
734 PORT_DATA_IO_PD(219),
735 PORT_DATA_IO_PD(220),
736 PORT_DATA_IO_PU_PD(221),
737 PORT_DATA_IO_PU_PD(222),
738 PORT_DATA_I_PU_PD(223),
739 PORT_DATA_I_PU_PD(224),
740
741 PORT_DATA_IO_PU_PD(225),
742 PORT_DATA_O(226),
743 PORT_DATA_IO_PU_PD(227),
744 PORT_DATA_I_PU_PD(228),
745 PORT_DATA_I_PD(229),
746 PORT_DATA_IO(230),
747 PORT_DATA_IO_PU_PD(231),
748 PORT_DATA_IO_PU_PD(232),
749 PORT_DATA_I_PU_PD(233),
750 PORT_DATA_IO_PU_PD(234),
751 PORT_DATA_IO_PU_PD(235),
752 PORT_DATA_IO_PU_PD(236),
753 PORT_DATA_IO_PD(237),
754 PORT_DATA_IO_PU_PD(238),
755 PORT_DATA_IO_PU_PD(239),
756 PORT_DATA_IO_PU_PD(240),
757 PORT_DATA_O(241),
758 PORT_DATA_I_PD(242),
759 PORT_DATA_IO_PU_PD(243),
760 PORT_DATA_IO_PU_PD(244),
761 PORT_DATA_IO_PU_PD(245),
762 PORT_DATA_IO_PU_PD(246),
763 PORT_DATA_IO_PU_PD(247),
764 PORT_DATA_IO_PU_PD(248),
765 PORT_DATA_IO_PU_PD(249),
766 PORT_DATA_IO_PU_PD(250),
767 PORT_DATA_IO_PU_PD(251),
768 PORT_DATA_IO_PU_PD(252),
769 PORT_DATA_IO_PU_PD(253),
770 PORT_DATA_IO_PU_PD(254),
771 PORT_DATA_IO_PU_PD(255),
772 PORT_DATA_IO_PU_PD(256),
773 PORT_DATA_IO_PU_PD(257),
774 PORT_DATA_IO_PU_PD(258),
775 PORT_DATA_IO_PU_PD(259),
776 PORT_DATA_IO_PU_PD(260),
777 PORT_DATA_IO_PU_PD(261),
778 PORT_DATA_IO_PU_PD(262),
779 PORT_DATA_IO_PU_PD(263),
780 PORT_DATA_IO_PU_PD(264),
781 PORT_DATA_IO_PU_PD(265),
782 PORT_DATA_IO_PU_PD(266),
783 PORT_DATA_IO_PU_PD(267),
784 PORT_DATA_IO_PU_PD(268),
785 PORT_DATA_IO_PU_PD(269),
786 PORT_DATA_IO_PU_PD(270),
787 PORT_DATA_IO_PU_PD(271),
788 PORT_DATA_IO_PU_PD(272),
789 PORT_DATA_IO_PU_PD(273),
790 PORT_DATA_IO_PU_PD(274),
791 PORT_DATA_IO_PU_PD(275),
792 PORT_DATA_IO_PU_PD(276),
793 PORT_DATA_IO_PU_PD(277),
794 PORT_DATA_IO_PU_PD(278),
795 PORT_DATA_IO_PU_PD(279),
796 PORT_DATA_IO_PU_PD(280),
797 PORT_DATA_O(281),
798 PORT_DATA_O(282),
799 PORT_DATA_I_PU(288),
800 PORT_DATA_IO_PU_PD(289),
801 PORT_DATA_IO_PU_PD(290),
802 PORT_DATA_IO_PU_PD(291),
803 PORT_DATA_IO_PU_PD(292),
804 PORT_DATA_IO_PU_PD(293),
805 PORT_DATA_IO_PU_PD(294),
806 PORT_DATA_IO_PU_PD(295),
807 PORT_DATA_IO_PU_PD(296),
808 PORT_DATA_IO_PU_PD(297),
809 PORT_DATA_IO_PU_PD(298),
810
811 PORT_DATA_IO_PU_PD(299),
812 PORT_DATA_IO_PU_PD(300),
813 PORT_DATA_IO_PU_PD(301),
814 PORT_DATA_IO_PU_PD(302),
815 PORT_DATA_IO_PU_PD(303),
816 PORT_DATA_IO_PU_PD(304),
817 PORT_DATA_IO_PU_PD(305),
818 PORT_DATA_O(306),
819 PORT_DATA_O(307),
820 PORT_DATA_I_PU(308),
821 PORT_DATA_O(309),
822
823 /* Table 25-1 (Function 0-7) */
824 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
825 PINMUX_DATA(GPI0_MARK, PORT1_FN1),
826 PINMUX_DATA(GPI1_MARK, PORT2_FN1),
827 PINMUX_DATA(GPI2_MARK, PORT3_FN1),
828 PINMUX_DATA(GPI3_MARK, PORT4_FN1),
829 PINMUX_DATA(GPI4_MARK, PORT5_FN1),
830 PINMUX_DATA(GPI5_MARK, PORT6_FN1),
831 PINMUX_DATA(GPI6_MARK, PORT7_FN1),
832 PINMUX_DATA(GPI7_MARK, PORT8_FN1),
833 PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
834 PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
835 PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
836 PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
837 PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
838 PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
839 PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
840 PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
841 PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
842 PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
843 PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
844 PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
845 PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
846 PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
847 PINMUX_DATA(GPO0_MARK, PORT20_FN1),
848 PINMUX_DATA(GPO1_MARK, PORT21_FN1),
849 PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
850 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
851 PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
852 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
853 PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
854 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
855 PINMUX_DATA(VINT_MARK, PORT25_FN1),
856 PINMUX_DATA(TCKON_MARK, PORT26_FN1),
857 PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
858 PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
859 MSEL2CR_MSEL16_1), \
860 PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
861 MSEL2CR_MSEL18_0), \
862 PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
863 PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
864 PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
865 PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
866 MSEL2CR_MSEL16_1), \
867 PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
868 MSEL2CR_MSEL18_0), \
869 PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
870 PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
871 PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
872 PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
873 PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
874 PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
875 PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
876 PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
877 PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
878 PINMUX_DATA(XWUP_MARK, PORT33_FN3),
879 PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
880 PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
881 PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
882 PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
883 PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
884 PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
885 PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
886 PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
887 PINMUX_DATA(VACK_MARK, PORT40_FN1),
888 PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
889 PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
890 PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
891 PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
892 PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
893 PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
894 PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
895 PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
896 PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
897 PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
898 PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
899 PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
900 PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
901 PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
902 PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
903 PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
904 PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
905 PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
906 PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
907 PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
908 PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
909 PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
910 PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
911 PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
912 PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
913 PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
914
915 PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
916 PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
917 PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
918 PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
919 PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
920 PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
921 PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
922 PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
923 PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
924 PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
925 PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
926 PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
927 PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
928 PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
929 PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
930 PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
931 PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
932 PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
933 PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
934 PINMUX_DATA(A0_MARK, PORT57_FN1), \
935 PINMUX_DATA(BS__MARK, PORT57_FN2),
936 PINMUX_DATA(A12_MARK, PORT58_FN1), \
937 PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
938 PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
939 PINMUX_DATA(A13_MARK, PORT59_FN1), \
940 PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
941 PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
942 PINMUX_DATA(A14_MARK, PORT60_FN1), \
943 PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
944 PINMUX_DATA(A15_MARK, PORT61_FN1), \
945 PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
946 PINMUX_DATA(A16_MARK, PORT62_FN1), \
947 PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
948 PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
949 PINMUX_DATA(A17_MARK, PORT63_FN1), \
950 PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
951 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
952 PINMUX_DATA(A18_MARK, PORT64_FN1), \
953 PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
954 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
955 PINMUX_DATA(A19_MARK, PORT65_FN1), \
956 PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
957 PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
958 PINMUX_DATA(A20_MARK, PORT66_FN1), \
959 PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
960 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
961 PINMUX_DATA(A21_MARK, PORT67_FN1), \
962 PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
963 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
964 PINMUX_DATA(A22_MARK, PORT68_FN1), \
965 PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
966 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
967 PINMUX_DATA(A23_MARK, PORT69_FN1), \
968 PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
969 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
970 PINMUX_DATA(A24_MARK, PORT70_FN1), \
971 PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
972 PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
973 PINMUX_DATA(A25_MARK, PORT71_FN1), \
974 PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
975 PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
976 PINMUX_DATA(A26_MARK, PORT72_FN1), \
977 PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
978 PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
979 PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
980 PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
981 PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
982 PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
983 PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
984 PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
985 PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
986 PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
987 PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
988 PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
989 PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
990 PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
991 PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
992 PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
993 PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
994 PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
995 PINMUX_DATA(CS4__MARK, PORT90_FN1),
996 PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
997 PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
998 PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
999 PINMUX_DATA(FCE1__MARK, PORT92_FN2),
1000 PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
1001 PINMUX_DATA(DACK0_MARK, PORT93_FN4),
1002 PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
1003 PINMUX_DATA(CS6A__MARK, PORT94_FN2),
1004 PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
1005 PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
1006 PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
1007 PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
1008 PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
1009 PINMUX_DATA(WE1__MARK, PORT98_FN1),
1010 PINMUX_DATA(FRB_MARK, PORT99_FN1),
1011 PINMUX_DATA(CKO_MARK, PORT100_FN1),
1012 PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
1013 PINMUX_DATA(NBRST__MARK, PORT102_FN1),
1014 PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
1015 PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
1016 PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
1017 PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
1018 PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
1019 PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
1020 PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
1021 PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
1022 PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
1023 PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
1024 PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
1025 PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
1026 PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
1027 PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
1028 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
1029 PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
1030 PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
1031 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
1032 PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
1033 PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
1034 PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
1035 PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
1036 PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
1037 PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
1038 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
1039 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
1040 PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
1041 PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
1042 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
1043 PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
1044 PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
1045 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
1046 PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
1047 PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
1048 PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
1049 PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
1050
1051 PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
1052 PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
1053 PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
1054 PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
1055 PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
1056 PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
1057 PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
1058 MSEL4CR_MSEL10_1), \
1059 PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
1060 PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
1061 PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
1062 PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
1063 PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
1064 PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
1065 PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
1066 PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
1067 PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
1068 PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
1069 PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
1070 PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
1071 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
1072 PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
1073 PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
1074 PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
1075 PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
1076 PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
1077 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
1078 PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
1079 PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
1080 PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
1081 PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
1082 PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
1083 PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
1084 PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
1085 PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
1086 PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
1087 PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
1088 PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
1089 PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
1090 PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
1091 PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
1092 PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
1093 PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
1094 PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
1095 PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
1096 PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
1097 PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
1098 PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
1099 PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
1100 PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
1101 PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
1102 PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
1103 PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
1104 PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
1105 PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
1106 PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
1107 PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
1108 PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
1109 PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
1110 PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
1111 PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
1112 PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
1113 PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
1114 PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
1115 PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
1116 PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
1117 PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
1118 PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
1119 PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
1120 PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
1121 PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
1122 PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
1123 PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
1124 PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
1125 PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
1126 PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
1127 PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
1128 PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
1129 PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
1130 PINMUX_DATA(A27_MARK, PORT149_FN1), \
1131 PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
1132 PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
1133 PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
1134 PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
1135 PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
1136 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
1137 PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
1138 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
1139 PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
1140 PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
1141 PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
1142 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
1143 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
1144 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
1145 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
1146 PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
1147 PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
1148 PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
1149 PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
1150 MSEL4CR_MSEL10_0),
1151 PINMUX_DATA(DINT__MARK, PORT158_FN1), \
1152 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
1153 PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
1154 PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
1155 PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
1156 PINMUX_DATA(NMI_MARK, PORT159_FN3),
1157 PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
1158 PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
1159 PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
1160 PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
1161 PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
1162 PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
1163 PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
1164 PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
1165 PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
1166 PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
1167 PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
1168 PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
1169 MSEL4CR_MSEL20_1), \
1170 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
1171 PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
1172 PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
1173 MSEL4CR_MSEL20_1), \
1174 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
1175 PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
1176 PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
1177 MSEL4CR_MSEL20_1), \
1178 PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
1179 PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
1180 PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
1181 MSEL4CR_MSEL20_1),
1182 PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
1183 PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
1184 MSEL4CR_MSEL20_1), \
1185 PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
1186 PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
1187 PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
1188 PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
1189 PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
1190 PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
1191 PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
1192 PINMUX_DATA(D16_MARK, PORT200_FN6),
1193 PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
1194 PINMUX_DATA(D17_MARK, PORT201_FN6),
1195 PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
1196 PINMUX_DATA(D18_MARK, PORT202_FN6),
1197 PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
1198 PINMUX_DATA(D19_MARK, PORT203_FN6),
1199 PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
1200 PINMUX_DATA(D20_MARK, PORT204_FN6),
1201 PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
1202 PINMUX_DATA(D21_MARK, PORT205_FN6),
1203 PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
1204 PINMUX_DATA(D22_MARK, PORT206_FN6),
1205 PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
1206 PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
1207 PINMUX_DATA(D23_MARK, PORT207_FN6),
1208 PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
1209 PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
1210 PINMUX_DATA(D24_MARK, PORT208_FN6),
1211 PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
1212 PINMUX_DATA(D25_MARK, PORT209_FN6),
1213 PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
1214 PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
1215 PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
1216 PINMUX_DATA(D26_MARK, PORT210_FN6),
1217 PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
1218 PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
1219 PINMUX_DATA(D27_MARK, PORT211_FN6),
1220 PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
1221 PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
1222 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
1223 PINMUX_DATA(D28_MARK, PORT212_FN6),
1224 PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
1225 PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
1226 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
1227 PINMUX_DATA(D29_MARK, PORT213_FN6),
1228 PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
1229 PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
1230 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
1231 PINMUX_DATA(D30_MARK, PORT214_FN6),
1232 PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
1233 PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
1234 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
1235 PINMUX_DATA(D31_MARK, PORT215_FN6),
1236 PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
1237 PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
1238 PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
1239 PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
1240 PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
1241 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
1242 PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
1243 MSEL4CR_MSEL26_1), \
1244 PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
1245 PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
1246 PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
1247 PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
1248 PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
1249 PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
1250 PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
1251 PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
1252 PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
1253 PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
1254 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
1255 PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
1256 MSEL4CR_MSEL26_1), \
1257 PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
1258 PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
1259 PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
1260 PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
1261 PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
1262 PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
1263 PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
1264 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
1265 PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
1266 MSEL4CR_MSEL26_1), \
1267 PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
1268 PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
1269 PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
1270 PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
1271 PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
1272 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
1273 PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
1274 MSEL4CR_MSEL26_1), \
1275 PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
1276
1277 PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
1278 PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
1279 PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
1280 PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
1281 PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
1282 PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
1283 PINMUX_DATA(IDIN_MARK, PORT227_FN4),
1284 PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
1285 PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
1286 PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
1287 PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
1288 PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
1289 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
1290 PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
1291 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
1292 PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
1293 PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
1294 PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
1295 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
1296 PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
1297 PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
1298 MSEL4CR_MSEL26_0), \
1299 PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
1300 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
1301 PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
1302 PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
1303 MSEL4CR_MSEL26_0), \
1304 PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
1305 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
1306 PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
1307 MSEL2CR_MSEL16_0),
1308 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
1309 PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
1310 MSEL2CR_MSEL16_0),
1311 PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
1312 PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
1313 MSEL4CR_MSEL26_0), \
1314 PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
1315 PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
1316 PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
1317 MSEL4CR_MSEL26_0), \
1318 PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
1319 PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
1320 PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
1321 PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
1322 PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
1323 PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
1324 PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
1325 PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
1326 PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
1327 PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
1328 PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
1329 MSEL4CR_MSEL20_0), \
1330 PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
1331 PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
1332 PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
1333 PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
1334 MSEL4CR_MSEL20_0), \
1335 PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
1336 PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
1337 PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
1338 PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
1339 MSEL4CR_MSEL20_0), \
1340 PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
1341 PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
1342 PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
1343 PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
1344 MSEL4CR_MSEL20_0), \
1345 PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
1346 PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
1347 PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
1348 PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
1349 MSEL4CR_MSEL20_0), \
1350 PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
1351 PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1352 PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1353 PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1354 MSEL2CR_MSEL18_0), \
1355 PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1356 PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1357 PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1358 PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1359 MSEL2CR_MSEL18_0), \
1360 PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1361 PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1362 PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1363 PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1364 PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1365 PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1366 PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1367 PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1368 PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1369 PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1370 PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1371 PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1372 PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1373 PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1374 PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1375 PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1376 PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1377 PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1378 PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1379 PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1380 PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1381 PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1382 PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1383 PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1384 PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1385 PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1386 PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1387 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1388 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1389 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1390 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1391 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1392 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1393 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1394 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \
1395 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1396 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \
1397 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1398 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \
1399 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1400 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \
1401 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1402 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1403 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1404 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1405 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1406 PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1407 PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1408 PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1409 PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1410 PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1411 PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1412 PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1413 PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1414 PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1415 PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1416 PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1417 PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1418 PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1419
1420 PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1421 PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1422 PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1423 PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1424 PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1425 PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1426 PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1427 PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1428 PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1429 PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1430 PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1431 PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1432 PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1433 PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1434 PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1435 PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1436 PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1437
1438 /* MSEL2 special cases */
1439 PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1440 MSEL2CR_MSEL12_0),
1441 PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1442 MSEL2CR_MSEL12_1),
1443 PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1444 MSEL2CR_MSEL12_0),
1445 PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1446 MSEL2CR_MSEL12_1),
1447 PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1448 MSEL2CR_MSEL12_0),
1449 PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1450 MSEL2CR_MSEL9_0),
1451 PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1452 MSEL2CR_MSEL9_1),
1453 PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1454 MSEL2CR_MSEL9_0),
1455 PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1456 MSEL2CR_MSEL9_1),
1457 PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1458 MSEL2CR_MSEL9_0),
1459 PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1460 MSEL2CR_MSEL6_0),
1461 PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1462 MSEL2CR_MSEL6_1),
1463 PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1464 MSEL2CR_MSEL6_0),
1465 PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1466 MSEL2CR_MSEL6_1),
1467 PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1468 MSEL2CR_MSEL6_0),
1469 PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1470 MSEL2CR_MSEL3_0),
1471 PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1472 MSEL2CR_MSEL3_1),
1473 PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1474 MSEL2CR_MSEL3_0),
1475 PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1476 MSEL2CR_MSEL3_1),
1477 PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1478 MSEL2CR_MSEL3_0),
1479 PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1480 MSEL2CR_MSEL0_0),
1481 PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1482 MSEL2CR_MSEL0_1),
1483 PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1484 MSEL2CR_MSEL0_0),
1485 PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1486 MSEL2CR_MSEL0_1),
1487 PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1488 MSEL2CR_MSEL0_0),
1489
1490 /* MSEL3 special cases */
1491 PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1492 PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1493 PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1494 PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1495 PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1496 PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1497
1498 /* MSEL4 special cases */
1499 PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1500 PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1501 PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1502 PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1503 PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1504 PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1505 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1506 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1507 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1508
1509 /* Functions with pull-ups */
1510 PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
1511 PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
1512 PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
1513 PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
1514 PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
1515 PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
1516 PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
1517 PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
1518
1519 PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1),
1520 PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1),
1521 PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1),
1522 PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1),
1523 PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1),
1524
1525 PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
1526 MSEL4CR_MSEL15_0),
1527 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU,
1528 MSEL4CR_MSEL15_1),
1529 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
1530 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
1531 PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
1532 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
1533};
1534
1535#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1536#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
1537#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1538
1539static struct pinmux_gpio pinmux_gpios[] = {
1540 GPIO_PORT_310(),
1541
1542 /* Table 25-1 (Functions 0-7) */
1543 GPIO_FN(VBUS_0),
1544 GPIO_FN(GPI0),
1545 GPIO_FN(GPI1),
1546 GPIO_FN(GPI2),
1547 GPIO_FN(GPI3),
1548 GPIO_FN(GPI4),
1549 GPIO_FN(GPI5),
1550 GPIO_FN(GPI6),
1551 GPIO_FN(GPI7),
1552 GPIO_FN(SCIFA7_RXD),
1553 GPIO_FN(SCIFA7_CTS_),
1554 GPIO_FN(GPO7), \
1555 GPIO_FN(MFG0_OUT2),
1556 GPIO_FN(GPO6), \
1557 GPIO_FN(MFG1_OUT2),
1558 GPIO_FN(GPO5), \
1559 GPIO_FN(SCIFA0_SCK), \
1560 GPIO_FN(FSICOSLDT3), \
1561 GPIO_FN(PORT16_VIO_CKOR),
1562 GPIO_FN(SCIFA0_TXD),
1563 GPIO_FN(SCIFA7_TXD),
1564 GPIO_FN(SCIFA7_RTS_), \
1565 GPIO_FN(PORT19_VIO_CKO2),
1566 GPIO_FN(GPO0),
1567 GPIO_FN(GPO1),
1568 GPIO_FN(GPO2), \
1569 GPIO_FN(STATUS0),
1570 GPIO_FN(GPO3), \
1571 GPIO_FN(STATUS1),
1572 GPIO_FN(GPO4), \
1573 GPIO_FN(STATUS2),
1574 GPIO_FN(VINT),
1575 GPIO_FN(TCKON),
1576 GPIO_FN(XDVFS1), \
1577 GPIO_FN(PORT27_I2C_SCL2), \
1578 GPIO_FN(PORT27_I2C_SCL3), \
1579 GPIO_FN(MFG0_OUT1), \
1580 GPIO_FN(PORT27_IROUT),
1581 GPIO_FN(XDVFS2), \
1582 GPIO_FN(PORT28_I2C_SDA2), \
1583 GPIO_FN(PORT28_I2C_SDA3), \
1584 GPIO_FN(PORT28_TPU1TO1),
1585 GPIO_FN(SIM_RST), \
1586 GPIO_FN(PORT29_TPU1TO1),
1587 GPIO_FN(SIM_CLK), \
1588 GPIO_FN(PORT30_VIO_CKOR),
1589 GPIO_FN(SIM_D), \
1590 GPIO_FN(PORT31_IROUT),
1591 GPIO_FN(SCIFA4_TXD),
1592 GPIO_FN(SCIFA4_RXD), \
1593 GPIO_FN(XWUP),
1594 GPIO_FN(SCIFA4_RTS_),
1595 GPIO_FN(SCIFA4_CTS_),
1596 GPIO_FN(FSIBOBT), \
1597 GPIO_FN(FSIBIBT),
1598 GPIO_FN(FSIBOLR), \
1599 GPIO_FN(FSIBILR),
1600 GPIO_FN(FSIBOSLD),
1601 GPIO_FN(FSIBISLD),
1602 GPIO_FN(VACK),
1603 GPIO_FN(XTAL1L),
1604 GPIO_FN(SCIFA0_RTS_), \
1605 GPIO_FN(FSICOSLDT2),
1606 GPIO_FN(SCIFA0_RXD),
1607 GPIO_FN(SCIFA0_CTS_), \
1608 GPIO_FN(FSICOSLDT1),
1609 GPIO_FN(FSICOBT), \
1610 GPIO_FN(FSICIBT), \
1611 GPIO_FN(FSIDOBT), \
1612 GPIO_FN(FSIDIBT),
1613 GPIO_FN(FSICOLR), \
1614 GPIO_FN(FSICILR), \
1615 GPIO_FN(FSIDOLR), \
1616 GPIO_FN(FSIDILR),
1617 GPIO_FN(FSICOSLD), \
1618 GPIO_FN(PORT47_FSICSPDIF),
1619 GPIO_FN(FSICISLD), \
1620 GPIO_FN(FSIDISLD),
1621 GPIO_FN(FSIACK), \
1622 GPIO_FN(PORT49_IRDA_OUT), \
1623 GPIO_FN(PORT49_IROUT), \
1624 GPIO_FN(FSIAOMC),
1625 GPIO_FN(FSIAOLR), \
1626 GPIO_FN(BBIF2_TSYNC2), \
1627 GPIO_FN(TPU2TO2), \
1628 GPIO_FN(FSIAILR),
1629
1630 GPIO_FN(FSIAOBT), \
1631 GPIO_FN(BBIF2_TSCK2), \
1632 GPIO_FN(TPU2TO3), \
1633 GPIO_FN(FSIAIBT),
1634 GPIO_FN(FSIAOSLD), \
1635 GPIO_FN(BBIF2_TXD2),
1636 GPIO_FN(FSIASPDIF), \
1637 GPIO_FN(PORT53_IRDA_IN), \
1638 GPIO_FN(TPU3TO3), \
1639 GPIO_FN(FSIBSPDIF), \
1640 GPIO_FN(PORT53_FSICSPDIF),
1641 GPIO_FN(FSIBCK), \
1642 GPIO_FN(PORT54_IRDA_FIRSEL), \
1643 GPIO_FN(TPU3TO2), \
1644 GPIO_FN(FSIBOMC), \
1645 GPIO_FN(FSICCK), \
1646 GPIO_FN(FSICOMC),
1647 GPIO_FN(FSIAISLD), \
1648 GPIO_FN(TPU0TO0),
1649 GPIO_FN(A0), \
1650 GPIO_FN(BS_),
1651 GPIO_FN(A12), \
1652 GPIO_FN(PORT58_KEYOUT7), \
1653 GPIO_FN(TPU4TO2),
1654 GPIO_FN(A13), \
1655 GPIO_FN(PORT59_KEYOUT6), \
1656 GPIO_FN(TPU0TO1),
1657 GPIO_FN(A14), \
1658 GPIO_FN(KEYOUT5),
1659 GPIO_FN(A15), \
1660 GPIO_FN(KEYOUT4),
1661 GPIO_FN(A16), \
1662 GPIO_FN(KEYOUT3), \
1663 GPIO_FN(MSIOF0_SS1),
1664 GPIO_FN(A17), \
1665 GPIO_FN(KEYOUT2), \
1666 GPIO_FN(MSIOF0_TSYNC),
1667 GPIO_FN(A18), \
1668 GPIO_FN(KEYOUT1), \
1669 GPIO_FN(MSIOF0_TSCK),
1670 GPIO_FN(A19), \
1671 GPIO_FN(KEYOUT0), \
1672 GPIO_FN(MSIOF0_TXD),
1673 GPIO_FN(A20), \
1674 GPIO_FN(KEYIN0), \
1675 GPIO_FN(MSIOF0_RSCK),
1676 GPIO_FN(A21), \
1677 GPIO_FN(KEYIN1), \
1678 GPIO_FN(MSIOF0_RSYNC),
1679 GPIO_FN(A22), \
1680 GPIO_FN(KEYIN2), \
1681 GPIO_FN(MSIOF0_MCK0),
1682 GPIO_FN(A23), \
1683 GPIO_FN(KEYIN3), \
1684 GPIO_FN(MSIOF0_MCK1),
1685 GPIO_FN(A24), \
1686 GPIO_FN(KEYIN4), \
1687 GPIO_FN(MSIOF0_RXD),
1688 GPIO_FN(A25), \
1689 GPIO_FN(KEYIN5), \
1690 GPIO_FN(MSIOF0_SS2),
1691 GPIO_FN(A26), \
1692 GPIO_FN(KEYIN6),
1693 GPIO_FN(KEYIN7),
1694 GPIO_FN(D0_NAF0),
1695 GPIO_FN(D1_NAF1),
1696 GPIO_FN(D2_NAF2),
1697 GPIO_FN(D3_NAF3),
1698 GPIO_FN(D4_NAF4),
1699 GPIO_FN(D5_NAF5),
1700 GPIO_FN(D6_NAF6),
1701 GPIO_FN(D7_NAF7),
1702 GPIO_FN(D8_NAF8),
1703 GPIO_FN(D9_NAF9),
1704 GPIO_FN(D10_NAF10),
1705 GPIO_FN(D11_NAF11),
1706 GPIO_FN(D12_NAF12),
1707 GPIO_FN(D13_NAF13),
1708 GPIO_FN(D14_NAF14),
1709 GPIO_FN(D15_NAF15),
1710 GPIO_FN(CS4_),
1711 GPIO_FN(CS5A_), \
1712 GPIO_FN(PORT91_RDWR),
1713 GPIO_FN(CS5B_), \
1714 GPIO_FN(FCE1_),
1715 GPIO_FN(CS6B_), \
1716 GPIO_FN(DACK0),
1717 GPIO_FN(FCE0_), \
1718 GPIO_FN(CS6A_),
1719 GPIO_FN(WAIT_), \
1720 GPIO_FN(DREQ0),
1721 GPIO_FN(RD__FSC),
1722 GPIO_FN(WE0__FWE), \
1723 GPIO_FN(RDWR_FWE),
1724 GPIO_FN(WE1_),
1725 GPIO_FN(FRB),
1726 GPIO_FN(CKO),
1727 GPIO_FN(NBRSTOUT_),
1728 GPIO_FN(NBRST_),
1729 GPIO_FN(BBIF2_TXD),
1730 GPIO_FN(BBIF2_RXD),
1731 GPIO_FN(BBIF2_SYNC),
1732 GPIO_FN(BBIF2_SCK),
1733 GPIO_FN(SCIFA3_CTS_), \
1734 GPIO_FN(MFG3_IN2),
1735 GPIO_FN(SCIFA3_RXD), \
1736 GPIO_FN(MFG3_IN1),
1737 GPIO_FN(BBIF1_SS2), \
1738 GPIO_FN(SCIFA3_RTS_), \
1739 GPIO_FN(MFG3_OUT1),
1740 GPIO_FN(SCIFA3_TXD),
1741 GPIO_FN(HSI_RX_DATA), \
1742 GPIO_FN(BBIF1_RXD),
1743 GPIO_FN(HSI_TX_WAKE), \
1744 GPIO_FN(BBIF1_TSCK),
1745 GPIO_FN(HSI_TX_DATA), \
1746 GPIO_FN(BBIF1_TSYNC),
1747 GPIO_FN(HSI_TX_READY), \
1748 GPIO_FN(BBIF1_TXD),
1749 GPIO_FN(HSI_RX_READY), \
1750 GPIO_FN(BBIF1_RSCK), \
1751 GPIO_FN(PORT115_I2C_SCL2), \
1752 GPIO_FN(PORT115_I2C_SCL3),
1753 GPIO_FN(HSI_RX_WAKE), \
1754 GPIO_FN(BBIF1_RSYNC), \
1755 GPIO_FN(PORT116_I2C_SDA2), \
1756 GPIO_FN(PORT116_I2C_SDA3),
1757 GPIO_FN(HSI_RX_FLAG), \
1758 GPIO_FN(BBIF1_SS1), \
1759 GPIO_FN(BBIF1_FLOW),
1760 GPIO_FN(HSI_TX_FLAG),
1761 GPIO_FN(VIO_VD), \
1762 GPIO_FN(PORT128_LCD2VSYN), \
1763 GPIO_FN(VIO2_VD), \
1764 GPIO_FN(LCD2D0),
1765
1766 GPIO_FN(VIO_HD), \
1767 GPIO_FN(PORT129_LCD2HSYN), \
1768 GPIO_FN(PORT129_LCD2CS_), \
1769 GPIO_FN(VIO2_HD), \
1770 GPIO_FN(LCD2D1),
1771 GPIO_FN(VIO_D0), \
1772 GPIO_FN(PORT130_MSIOF2_RXD), \
1773 GPIO_FN(LCD2D10),
1774 GPIO_FN(VIO_D1), \
1775 GPIO_FN(PORT131_KEYOUT6), \
1776 GPIO_FN(PORT131_MSIOF2_SS1), \
1777 GPIO_FN(PORT131_KEYOUT11), \
1778 GPIO_FN(LCD2D11),
1779 GPIO_FN(VIO_D2), \
1780 GPIO_FN(PORT132_KEYOUT7), \
1781 GPIO_FN(PORT132_MSIOF2_SS2), \
1782 GPIO_FN(PORT132_KEYOUT10), \
1783 GPIO_FN(LCD2D12),
1784 GPIO_FN(VIO_D3), \
1785 GPIO_FN(MSIOF2_TSYNC), \
1786 GPIO_FN(LCD2D13),
1787 GPIO_FN(VIO_D4), \
1788 GPIO_FN(MSIOF2_TXD), \
1789 GPIO_FN(LCD2D14),
1790 GPIO_FN(VIO_D5), \
1791 GPIO_FN(MSIOF2_TSCK), \
1792 GPIO_FN(LCD2D15),
1793 GPIO_FN(VIO_D6), \
1794 GPIO_FN(PORT136_KEYOUT8), \
1795 GPIO_FN(LCD2D16),
1796 GPIO_FN(VIO_D7), \
1797 GPIO_FN(PORT137_KEYOUT9), \
1798 GPIO_FN(LCD2D17),
1799 GPIO_FN(VIO_D8), \
1800 GPIO_FN(PORT138_KEYOUT8), \
1801 GPIO_FN(VIO2_D0), \
1802 GPIO_FN(LCD2D6),
1803 GPIO_FN(VIO_D9), \
1804 GPIO_FN(PORT139_KEYOUT9), \
1805 GPIO_FN(VIO2_D1), \
1806 GPIO_FN(LCD2D7),
1807 GPIO_FN(VIO_D10), \
1808 GPIO_FN(TPU0TO2), \
1809 GPIO_FN(VIO2_D2), \
1810 GPIO_FN(LCD2D8),
1811 GPIO_FN(VIO_D11), \
1812 GPIO_FN(TPU0TO3), \
1813 GPIO_FN(VIO2_D3), \
1814 GPIO_FN(LCD2D9),
1815 GPIO_FN(VIO_D12), \
1816 GPIO_FN(PORT142_KEYOUT10), \
1817 GPIO_FN(VIO2_D4), \
1818 GPIO_FN(LCD2D2),
1819 GPIO_FN(VIO_D13), \
1820 GPIO_FN(PORT143_KEYOUT11), \
1821 GPIO_FN(PORT143_KEYOUT6), \
1822 GPIO_FN(VIO2_D5), \
1823 GPIO_FN(LCD2D3),
1824 GPIO_FN(VIO_D14), \
1825 GPIO_FN(PORT144_KEYOUT7), \
1826 GPIO_FN(VIO2_D6), \
1827 GPIO_FN(LCD2D4),
1828 GPIO_FN(VIO_D15), \
1829 GPIO_FN(TPU1TO3), \
1830 GPIO_FN(PORT145_LCD2DISP), \
1831 GPIO_FN(PORT145_LCD2RS), \
1832 GPIO_FN(VIO2_D7), \
1833 GPIO_FN(LCD2D5),
1834 GPIO_FN(VIO_CLK), \
1835 GPIO_FN(LCD2DCK), \
1836 GPIO_FN(PORT146_LCD2WR_), \
1837 GPIO_FN(VIO2_CLK), \
1838 GPIO_FN(LCD2D18),
1839 GPIO_FN(VIO_FIELD), \
1840 GPIO_FN(LCD2RD_), \
1841 GPIO_FN(VIO2_FIELD), \
1842 GPIO_FN(LCD2D19),
1843 GPIO_FN(VIO_CKO),
1844 GPIO_FN(A27), \
1845 GPIO_FN(PORT149_RDWR), \
1846 GPIO_FN(MFG0_IN1), \
1847 GPIO_FN(PORT149_KEYOUT9),
1848 GPIO_FN(MFG0_IN2),
1849 GPIO_FN(TS_SPSYNC3), \
1850 GPIO_FN(MSIOF2_RSCK),
1851 GPIO_FN(TS_SDAT3), \
1852 GPIO_FN(MSIOF2_RSYNC),
1853 GPIO_FN(TPU1TO2), \
1854 GPIO_FN(TS_SDEN3), \
1855 GPIO_FN(PORT153_MSIOF2_SS1),
1856 GPIO_FN(SCIFA2_TXD1), \
1857 GPIO_FN(MSIOF2_MCK0),
1858 GPIO_FN(SCIFA2_RXD1), \
1859 GPIO_FN(MSIOF2_MCK1),
1860 GPIO_FN(SCIFA2_RTS1_), \
1861 GPIO_FN(PORT156_MSIOF2_SS2),
1862 GPIO_FN(SCIFA2_CTS1_), \
1863 GPIO_FN(PORT157_MSIOF2_RXD),
1864 GPIO_FN(DINT_), \
1865 GPIO_FN(SCIFA2_SCK1), \
1866 GPIO_FN(TS_SCK3),
1867 GPIO_FN(PORT159_SCIFB_SCK), \
1868 GPIO_FN(PORT159_SCIFA5_SCK), \
1869 GPIO_FN(NMI),
1870 GPIO_FN(PORT160_SCIFB_TXD), \
1871 GPIO_FN(PORT160_SCIFA5_TXD),
1872 GPIO_FN(PORT161_SCIFB_CTS_), \
1873 GPIO_FN(PORT161_SCIFA5_CTS_),
1874 GPIO_FN(PORT162_SCIFB_RXD), \
1875 GPIO_FN(PORT162_SCIFA5_RXD),
1876 GPIO_FN(PORT163_SCIFB_RTS_), \
1877 GPIO_FN(PORT163_SCIFA5_RTS_), \
1878 GPIO_FN(TPU3TO0),
1879 GPIO_FN(LCDD0),
1880 GPIO_FN(LCDD1), \
1881 GPIO_FN(PORT193_SCIFA5_CTS_), \
1882 GPIO_FN(BBIF2_TSYNC1),
1883 GPIO_FN(LCDD2), \
1884 GPIO_FN(PORT194_SCIFA5_RTS_), \
1885 GPIO_FN(BBIF2_TSCK1),
1886 GPIO_FN(LCDD3), \
1887 GPIO_FN(PORT195_SCIFA5_RXD), \
1888 GPIO_FN(BBIF2_TXD1),
1889 GPIO_FN(LCDD4), \
1890 GPIO_FN(PORT196_SCIFA5_TXD),
1891 GPIO_FN(LCDD5), \
1892 GPIO_FN(PORT197_SCIFA5_SCK), \
1893 GPIO_FN(MFG2_OUT2), \
1894 GPIO_FN(TPU2TO1),
1895 GPIO_FN(LCDD6),
1896 GPIO_FN(LCDD7), \
1897 GPIO_FN(TPU4TO1), \
1898 GPIO_FN(MFG4_OUT2),
1899 GPIO_FN(LCDD8), \
1900 GPIO_FN(D16),
1901 GPIO_FN(LCDD9), \
1902 GPIO_FN(D17),
1903 GPIO_FN(LCDD10), \
1904 GPIO_FN(D18),
1905 GPIO_FN(LCDD11), \
1906 GPIO_FN(D19),
1907 GPIO_FN(LCDD12), \
1908 GPIO_FN(D20),
1909 GPIO_FN(LCDD13), \
1910 GPIO_FN(D21),
1911 GPIO_FN(LCDD14), \
1912 GPIO_FN(D22),
1913 GPIO_FN(LCDD15), \
1914 GPIO_FN(PORT207_MSIOF0L_SS1), \
1915 GPIO_FN(D23),
1916 GPIO_FN(LCDD16), \
1917 GPIO_FN(PORT208_MSIOF0L_SS2), \
1918 GPIO_FN(D24),
1919 GPIO_FN(LCDD17), \
1920 GPIO_FN(D25),
1921 GPIO_FN(LCDD18), \
1922 GPIO_FN(DREQ2), \
1923 GPIO_FN(PORT210_MSIOF0L_SS1), \
1924 GPIO_FN(D26),
1925 GPIO_FN(LCDD19), \
1926 GPIO_FN(PORT211_MSIOF0L_SS2), \
1927 GPIO_FN(D27),
1928 GPIO_FN(LCDD20), \
1929 GPIO_FN(TS_SPSYNC1), \
1930 GPIO_FN(MSIOF0L_MCK0), \
1931 GPIO_FN(D28),
1932 GPIO_FN(LCDD21), \
1933 GPIO_FN(TS_SDAT1), \
1934 GPIO_FN(MSIOF0L_MCK1), \
1935 GPIO_FN(D29),
1936 GPIO_FN(LCDD22), \
1937 GPIO_FN(TS_SDEN1), \
1938 GPIO_FN(MSIOF0L_RSCK), \
1939 GPIO_FN(D30),
1940 GPIO_FN(LCDD23), \
1941 GPIO_FN(TS_SCK1), \
1942 GPIO_FN(MSIOF0L_RSYNC), \
1943 GPIO_FN(D31),
1944 GPIO_FN(LCDDCK), \
1945 GPIO_FN(LCDWR_),
1946 GPIO_FN(LCDRD_), \
1947 GPIO_FN(DACK2), \
1948 GPIO_FN(PORT217_LCD2RS), \
1949 GPIO_FN(MSIOF0L_TSYNC), \
1950 GPIO_FN(VIO2_FIELD3), \
1951 GPIO_FN(PORT217_LCD2DISP),
1952 GPIO_FN(LCDHSYN), \
1953 GPIO_FN(LCDCS_), \
1954 GPIO_FN(LCDCS2_), \
1955 GPIO_FN(DACK3), \
1956 GPIO_FN(PORT218_VIO_CKOR),
1957 GPIO_FN(LCDDISP), \
1958 GPIO_FN(LCDRS), \
1959 GPIO_FN(PORT219_LCD2WR_), \
1960 GPIO_FN(DREQ3), \
1961 GPIO_FN(MSIOF0L_TSCK), \
1962 GPIO_FN(VIO2_CLK3), \
1963 GPIO_FN(LCD2DCK_2),
1964 GPIO_FN(LCDVSYN), \
1965 GPIO_FN(LCDVSYN2),
1966 GPIO_FN(LCDLCLK), \
1967 GPIO_FN(DREQ1), \
1968 GPIO_FN(PORT221_LCD2CS_), \
1969 GPIO_FN(PWEN), \
1970 GPIO_FN(MSIOF0L_RXD), \
1971 GPIO_FN(VIO2_HD3), \
1972 GPIO_FN(PORT221_LCD2HSYN),
1973 GPIO_FN(LCDDON), \
1974 GPIO_FN(LCDDON2), \
1975 GPIO_FN(DACK1), \
1976 GPIO_FN(OVCN), \
1977 GPIO_FN(MSIOF0L_TXD), \
1978 GPIO_FN(VIO2_VD3), \
1979 GPIO_FN(PORT222_LCD2VSYN),
1980
1981 GPIO_FN(SCIFA1_TXD), \
1982 GPIO_FN(OVCN2),
1983 GPIO_FN(EXTLP), \
1984 GPIO_FN(SCIFA1_SCK), \
1985 GPIO_FN(PORT226_VIO_CKO2),
1986 GPIO_FN(SCIFA1_RTS_), \
1987 GPIO_FN(IDIN),
1988 GPIO_FN(SCIFA1_RXD),
1989 GPIO_FN(SCIFA1_CTS_), \
1990 GPIO_FN(MFG1_IN1),
1991 GPIO_FN(MSIOF1_TXD), \
1992 GPIO_FN(SCIFA2_TXD2),
1993 GPIO_FN(MSIOF1_TSYNC), \
1994 GPIO_FN(SCIFA2_CTS2_),
1995 GPIO_FN(MSIOF1_TSCK), \
1996 GPIO_FN(SCIFA2_SCK2),
1997 GPIO_FN(MSIOF1_RXD), \
1998 GPIO_FN(SCIFA2_RXD2),
1999 GPIO_FN(MSIOF1_RSCK), \
2000 GPIO_FN(SCIFA2_RTS2_), \
2001 GPIO_FN(VIO2_CLK2), \
2002 GPIO_FN(LCD2D20),
2003 GPIO_FN(MSIOF1_RSYNC), \
2004 GPIO_FN(MFG1_IN2), \
2005 GPIO_FN(VIO2_VD2), \
2006 GPIO_FN(LCD2D21),
2007 GPIO_FN(MSIOF1_MCK0), \
2008 GPIO_FN(PORT236_I2C_SDA2),
2009 GPIO_FN(MSIOF1_MCK1), \
2010 GPIO_FN(PORT237_I2C_SCL2),
2011 GPIO_FN(MSIOF1_SS1), \
2012 GPIO_FN(VIO2_FIELD2), \
2013 GPIO_FN(LCD2D22),
2014 GPIO_FN(MSIOF1_SS2), \
2015 GPIO_FN(VIO2_HD2), \
2016 GPIO_FN(LCD2D23),
2017 GPIO_FN(SCIFA6_TXD),
2018 GPIO_FN(PORT241_IRDA_OUT), \
2019 GPIO_FN(PORT241_IROUT), \
2020 GPIO_FN(MFG4_OUT1), \
2021 GPIO_FN(TPU4TO0),
2022 GPIO_FN(PORT242_IRDA_IN), \
2023 GPIO_FN(MFG4_IN2),
2024 GPIO_FN(PORT243_IRDA_FIRSEL), \
2025 GPIO_FN(PORT243_VIO_CKO2),
2026 GPIO_FN(PORT244_SCIFA5_CTS_), \
2027 GPIO_FN(MFG2_IN1), \
2028 GPIO_FN(PORT244_SCIFB_CTS_), \
2029 GPIO_FN(MSIOF2R_RXD),
2030 GPIO_FN(PORT245_SCIFA5_RTS_), \
2031 GPIO_FN(MFG2_IN2), \
2032 GPIO_FN(PORT245_SCIFB_RTS_), \
2033 GPIO_FN(MSIOF2R_TXD),
2034 GPIO_FN(PORT246_SCIFA5_RXD), \
2035 GPIO_FN(MFG1_OUT1), \
2036 GPIO_FN(PORT246_SCIFB_RXD), \
2037 GPIO_FN(TPU1TO0),
2038 GPIO_FN(PORT247_SCIFA5_TXD), \
2039 GPIO_FN(MFG3_OUT2), \
2040 GPIO_FN(PORT247_SCIFB_TXD), \
2041 GPIO_FN(TPU3TO1),
2042 GPIO_FN(PORT248_SCIFA5_SCK), \
2043 GPIO_FN(MFG2_OUT1), \
2044 GPIO_FN(PORT248_SCIFB_SCK), \
2045 GPIO_FN(TPU2TO0), \
2046 GPIO_FN(PORT248_I2C_SCL3), \
2047 GPIO_FN(MSIOF2R_TSCK),
2048 GPIO_FN(PORT249_IROUT), \
2049 GPIO_FN(MFG4_IN1), \
2050 GPIO_FN(PORT249_I2C_SDA3), \
2051 GPIO_FN(MSIOF2R_TSYNC),
2052 GPIO_FN(SDHICLK0),
2053 GPIO_FN(SDHICD0),
2054 GPIO_FN(SDHID0_0),
2055 GPIO_FN(SDHID0_1),
2056 GPIO_FN(SDHID0_2),
2057 GPIO_FN(SDHID0_3),
2058 GPIO_FN(SDHICMD0),
2059 GPIO_FN(SDHIWP0),
2060 GPIO_FN(SDHICLK1),
2061 GPIO_FN(SDHID1_0), \
2062 GPIO_FN(TS_SPSYNC2),
2063 GPIO_FN(SDHID1_1), \
2064 GPIO_FN(TS_SDAT2),
2065 GPIO_FN(SDHID1_2), \
2066 GPIO_FN(TS_SDEN2),
2067 GPIO_FN(SDHID1_3), \
2068 GPIO_FN(TS_SCK2),
2069 GPIO_FN(SDHICMD1),
2070 GPIO_FN(SDHICLK2),
2071 GPIO_FN(SDHID2_0), \
2072 GPIO_FN(TS_SPSYNC4),
2073 GPIO_FN(SDHID2_1), \
2074 GPIO_FN(TS_SDAT4),
2075 GPIO_FN(SDHID2_2), \
2076 GPIO_FN(TS_SDEN4),
2077 GPIO_FN(SDHID2_3), \
2078 GPIO_FN(TS_SCK4),
2079 GPIO_FN(SDHICMD2),
2080 GPIO_FN(MMCCLK0),
2081 GPIO_FN(MMCD0_0),
2082 GPIO_FN(MMCD0_1),
2083 GPIO_FN(MMCD0_2),
2084 GPIO_FN(MMCD0_3),
2085 GPIO_FN(MMCD0_4), \
2086 GPIO_FN(TS_SPSYNC5),
2087 GPIO_FN(MMCD0_5), \
2088 GPIO_FN(TS_SDAT5),
2089 GPIO_FN(MMCD0_6), \
2090 GPIO_FN(TS_SDEN5),
2091 GPIO_FN(MMCD0_7), \
2092 GPIO_FN(TS_SCK5),
2093 GPIO_FN(MMCCMD0),
2094 GPIO_FN(RESETOUTS_), \
2095 GPIO_FN(EXTAL2OUT),
2096 GPIO_FN(MCP_WAIT__MCP_FRB),
2097 GPIO_FN(MCP_CKO), \
2098 GPIO_FN(MMCCLK1),
2099 GPIO_FN(MCP_D15_MCP_NAF15),
2100 GPIO_FN(MCP_D14_MCP_NAF14),
2101 GPIO_FN(MCP_D13_MCP_NAF13),
2102 GPIO_FN(MCP_D12_MCP_NAF12),
2103 GPIO_FN(MCP_D11_MCP_NAF11),
2104 GPIO_FN(MCP_D10_MCP_NAF10),
2105 GPIO_FN(MCP_D9_MCP_NAF9),
2106 GPIO_FN(MCP_D8_MCP_NAF8), \
2107 GPIO_FN(MMCCMD1),
2108 GPIO_FN(MCP_D7_MCP_NAF7), \
2109 GPIO_FN(MMCD1_7),
2110
2111 GPIO_FN(MCP_D6_MCP_NAF6), \
2112 GPIO_FN(MMCD1_6),
2113 GPIO_FN(MCP_D5_MCP_NAF5), \
2114 GPIO_FN(MMCD1_5),
2115 GPIO_FN(MCP_D4_MCP_NAF4), \
2116 GPIO_FN(MMCD1_4),
2117 GPIO_FN(MCP_D3_MCP_NAF3), \
2118 GPIO_FN(MMCD1_3),
2119 GPIO_FN(MCP_D2_MCP_NAF2), \
2120 GPIO_FN(MMCD1_2),
2121 GPIO_FN(MCP_D1_MCP_NAF1), \
2122 GPIO_FN(MMCD1_1),
2123 GPIO_FN(MCP_D0_MCP_NAF0), \
2124 GPIO_FN(MMCD1_0),
2125 GPIO_FN(MCP_NBRSTOUT_),
2126 GPIO_FN(MCP_WE0__MCP_FWE), \
2127 GPIO_FN(MCP_RDWR_MCP_FWE),
2128
2129 /* MSEL2 special cases */
2130 GPIO_FN(TSIF2_TS_XX1),
2131 GPIO_FN(TSIF2_TS_XX2),
2132 GPIO_FN(TSIF2_TS_XX3),
2133 GPIO_FN(TSIF2_TS_XX4),
2134 GPIO_FN(TSIF2_TS_XX5),
2135 GPIO_FN(TSIF1_TS_XX1),
2136 GPIO_FN(TSIF1_TS_XX2),
2137 GPIO_FN(TSIF1_TS_XX3),
2138 GPIO_FN(TSIF1_TS_XX4),
2139 GPIO_FN(TSIF1_TS_XX5),
2140 GPIO_FN(TSIF0_TS_XX1),
2141 GPIO_FN(TSIF0_TS_XX2),
2142 GPIO_FN(TSIF0_TS_XX3),
2143 GPIO_FN(TSIF0_TS_XX4),
2144 GPIO_FN(TSIF0_TS_XX5),
2145 GPIO_FN(MST1_TS_XX1),
2146 GPIO_FN(MST1_TS_XX2),
2147 GPIO_FN(MST1_TS_XX3),
2148 GPIO_FN(MST1_TS_XX4),
2149 GPIO_FN(MST1_TS_XX5),
2150 GPIO_FN(MST0_TS_XX1),
2151 GPIO_FN(MST0_TS_XX2),
2152 GPIO_FN(MST0_TS_XX3),
2153 GPIO_FN(MST0_TS_XX4),
2154 GPIO_FN(MST0_TS_XX5),
2155
2156 /* MSEL3 special cases */
2157 GPIO_FN(SDHI0_VCCQ_MC0_ON),
2158 GPIO_FN(SDHI0_VCCQ_MC0_OFF),
2159 GPIO_FN(DEBUG_MON_VIO),
2160 GPIO_FN(DEBUG_MON_LCDD),
2161 GPIO_FN(LCDC_LCDC0),
2162 GPIO_FN(LCDC_LCDC1),
2163
2164 /* MSEL4 special cases */
2165 GPIO_FN(IRQ9_MEM_INT),
2166 GPIO_FN(IRQ9_MCP_INT),
2167 GPIO_FN(A11),
2168 GPIO_FN(KEYOUT8),
2169 GPIO_FN(TPU4TO3),
2170 GPIO_FN(RESETA_N_PU_ON),
2171 GPIO_FN(RESETA_N_PU_OFF),
2172 GPIO_FN(EDBGREQ_PD),
2173 GPIO_FN(EDBGREQ_PU),
2174
2175 /* Functions with pull-ups */
2176 GPIO_FN(KEYIN0_PU),
2177 GPIO_FN(KEYIN1_PU),
2178 GPIO_FN(KEYIN2_PU),
2179 GPIO_FN(KEYIN3_PU),
2180 GPIO_FN(KEYIN4_PU),
2181 GPIO_FN(KEYIN5_PU),
2182 GPIO_FN(KEYIN6_PU),
2183 GPIO_FN(KEYIN7_PU),
2184 GPIO_FN(SDHID1_0_PU),
2185 GPIO_FN(SDHID1_1_PU),
2186 GPIO_FN(SDHID1_2_PU),
2187 GPIO_FN(SDHID1_3_PU),
2188 GPIO_FN(SDHICMD1_PU),
2189 GPIO_FN(MMCCMD0_PU),
2190 GPIO_FN(MMCCMD1_PU),
2191 GPIO_FN(FSIACK_PU),
2192 GPIO_FN(FSIAILR_PU),
2193 GPIO_FN(FSIAIBT_PU),
2194 GPIO_FN(FSIAISLD_PU),
2195};
2196
2197#define PORTCR(nr, reg) \
2198 { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2199 0, \
2200 /*0001*/ PORT##nr##_OUT , \
2201 /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
2202 /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
2203 /*1110*/ PORT##nr##_IN_PU, 0, \
2204 PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
2205 PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
2206 PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
2207 }
2208
2209static struct pinmux_cfg_reg pinmux_config_regs[] = {
2210 PORTCR(0, 0xe6050000), /* PORT0CR */
2211 PORTCR(1, 0xe6050001), /* PORT1CR */
2212 PORTCR(2, 0xe6050002), /* PORT2CR */
2213 PORTCR(3, 0xe6050003), /* PORT3CR */
2214 PORTCR(4, 0xe6050004), /* PORT4CR */
2215 PORTCR(5, 0xe6050005), /* PORT5CR */
2216 PORTCR(6, 0xe6050006), /* PORT6CR */
2217 PORTCR(7, 0xe6050007), /* PORT7CR */
2218 PORTCR(8, 0xe6050008), /* PORT8CR */
2219 PORTCR(9, 0xe6050009), /* PORT9CR */
2220
2221 PORTCR(10, 0xe605000a), /* PORT10CR */
2222 PORTCR(11, 0xe605000b), /* PORT11CR */
2223 PORTCR(12, 0xe605000c), /* PORT12CR */
2224 PORTCR(13, 0xe605000d), /* PORT13CR */
2225 PORTCR(14, 0xe605000e), /* PORT14CR */
2226 PORTCR(15, 0xe605000f), /* PORT15CR */
2227 PORTCR(16, 0xe6050010), /* PORT16CR */
2228 PORTCR(17, 0xe6050011), /* PORT17CR */
2229 PORTCR(18, 0xe6050012), /* PORT18CR */
2230 PORTCR(19, 0xe6050013), /* PORT19CR */
2231
2232 PORTCR(20, 0xe6050014), /* PORT20CR */
2233 PORTCR(21, 0xe6050015), /* PORT21CR */
2234 PORTCR(22, 0xe6050016), /* PORT22CR */
2235 PORTCR(23, 0xe6050017), /* PORT23CR */
2236 PORTCR(24, 0xe6050018), /* PORT24CR */
2237 PORTCR(25, 0xe6050019), /* PORT25CR */
2238 PORTCR(26, 0xe605001a), /* PORT26CR */
2239 PORTCR(27, 0xe605001b), /* PORT27CR */
2240 PORTCR(28, 0xe605001c), /* PORT28CR */
2241 PORTCR(29, 0xe605001d), /* PORT29CR */
2242
2243 PORTCR(30, 0xe605001e), /* PORT30CR */
2244 PORTCR(31, 0xe605001f), /* PORT31CR */
2245 PORTCR(32, 0xe6051020), /* PORT32CR */
2246 PORTCR(33, 0xe6051021), /* PORT33CR */
2247 PORTCR(34, 0xe6051022), /* PORT34CR */
2248 PORTCR(35, 0xe6051023), /* PORT35CR */
2249 PORTCR(36, 0xe6051024), /* PORT36CR */
2250 PORTCR(37, 0xe6051025), /* PORT37CR */
2251 PORTCR(38, 0xe6051026), /* PORT38CR */
2252 PORTCR(39, 0xe6051027), /* PORT39CR */
2253
2254 PORTCR(40, 0xe6051028), /* PORT40CR */
2255 PORTCR(41, 0xe6051029), /* PORT41CR */
2256 PORTCR(42, 0xe605102a), /* PORT42CR */
2257 PORTCR(43, 0xe605102b), /* PORT43CR */
2258 PORTCR(44, 0xe605102c), /* PORT44CR */
2259 PORTCR(45, 0xe605102d), /* PORT45CR */
2260 PORTCR(46, 0xe605102e), /* PORT46CR */
2261 PORTCR(47, 0xe605102f), /* PORT47CR */
2262 PORTCR(48, 0xe6051030), /* PORT48CR */
2263 PORTCR(49, 0xe6051031), /* PORT49CR */
2264
2265 PORTCR(50, 0xe6051032), /* PORT50CR */
2266 PORTCR(51, 0xe6051033), /* PORT51CR */
2267 PORTCR(52, 0xe6051034), /* PORT52CR */
2268 PORTCR(53, 0xe6051035), /* PORT53CR */
2269 PORTCR(54, 0xe6051036), /* PORT54CR */
2270 PORTCR(55, 0xe6051037), /* PORT55CR */
2271 PORTCR(56, 0xe6051038), /* PORT56CR */
2272 PORTCR(57, 0xe6051039), /* PORT57CR */
2273 PORTCR(58, 0xe605103a), /* PORT58CR */
2274 PORTCR(59, 0xe605103b), /* PORT59CR */
2275
2276 PORTCR(60, 0xe605103c), /* PORT60CR */
2277 PORTCR(61, 0xe605103d), /* PORT61CR */
2278 PORTCR(62, 0xe605103e), /* PORT62CR */
2279 PORTCR(63, 0xe605103f), /* PORT63CR */
2280 PORTCR(64, 0xe6051040), /* PORT64CR */
2281 PORTCR(65, 0xe6051041), /* PORT65CR */
2282 PORTCR(66, 0xe6051042), /* PORT66CR */
2283 PORTCR(67, 0xe6051043), /* PORT67CR */
2284 PORTCR(68, 0xe6051044), /* PORT68CR */
2285 PORTCR(69, 0xe6051045), /* PORT69CR */
2286
2287 PORTCR(70, 0xe6051046), /* PORT70CR */
2288 PORTCR(71, 0xe6051047), /* PORT71CR */
2289 PORTCR(72, 0xe6051048), /* PORT72CR */
2290 PORTCR(73, 0xe6051049), /* PORT73CR */
2291 PORTCR(74, 0xe605104a), /* PORT74CR */
2292 PORTCR(75, 0xe605104b), /* PORT75CR */
2293 PORTCR(76, 0xe605104c), /* PORT76CR */
2294 PORTCR(77, 0xe605104d), /* PORT77CR */
2295 PORTCR(78, 0xe605104e), /* PORT78CR */
2296 PORTCR(79, 0xe605104f), /* PORT79CR */
2297
2298 PORTCR(80, 0xe6051050), /* PORT80CR */
2299 PORTCR(81, 0xe6051051), /* PORT81CR */
2300 PORTCR(82, 0xe6051052), /* PORT82CR */
2301 PORTCR(83, 0xe6051053), /* PORT83CR */
2302 PORTCR(84, 0xe6051054), /* PORT84CR */
2303 PORTCR(85, 0xe6051055), /* PORT85CR */
2304 PORTCR(86, 0xe6051056), /* PORT86CR */
2305 PORTCR(87, 0xe6051057), /* PORT87CR */
2306 PORTCR(88, 0xe6051058), /* PORT88CR */
2307 PORTCR(89, 0xe6051059), /* PORT89CR */
2308
2309 PORTCR(90, 0xe605105a), /* PORT90CR */
2310 PORTCR(91, 0xe605105b), /* PORT91CR */
2311 PORTCR(92, 0xe605105c), /* PORT92CR */
2312 PORTCR(93, 0xe605105d), /* PORT93CR */
2313 PORTCR(94, 0xe605105e), /* PORT94CR */
2314 PORTCR(95, 0xe605105f), /* PORT95CR */
2315 PORTCR(96, 0xe6052060), /* PORT96CR */
2316 PORTCR(97, 0xe6052061), /* PORT97CR */
2317 PORTCR(98, 0xe6052062), /* PORT98CR */
2318 PORTCR(99, 0xe6052063), /* PORT99CR */
2319
2320 PORTCR(100, 0xe6052064), /* PORT100CR */
2321 PORTCR(101, 0xe6052065), /* PORT101CR */
2322 PORTCR(102, 0xe6052066), /* PORT102CR */
2323 PORTCR(103, 0xe6052067), /* PORT103CR */
2324 PORTCR(104, 0xe6052068), /* PORT104CR */
2325 PORTCR(105, 0xe6052069), /* PORT105CR */
2326 PORTCR(106, 0xe605206a), /* PORT106CR */
2327 PORTCR(107, 0xe605206b), /* PORT107CR */
2328 PORTCR(108, 0xe605206c), /* PORT108CR */
2329 PORTCR(109, 0xe605206d), /* PORT109CR */
2330
2331 PORTCR(110, 0xe605206e), /* PORT110CR */
2332 PORTCR(111, 0xe605206f), /* PORT111CR */
2333 PORTCR(112, 0xe6052070), /* PORT112CR */
2334 PORTCR(113, 0xe6052071), /* PORT113CR */
2335 PORTCR(114, 0xe6052072), /* PORT114CR */
2336 PORTCR(115, 0xe6052073), /* PORT115CR */
2337 PORTCR(116, 0xe6052074), /* PORT116CR */
2338 PORTCR(117, 0xe6052075), /* PORT117CR */
2339 PORTCR(118, 0xe6052076), /* PORT118CR */
2340
2341 PORTCR(128, 0xe6052080), /* PORT128CR */
2342 PORTCR(129, 0xe6052081), /* PORT129CR */
2343
2344 PORTCR(130, 0xe6052082), /* PORT130CR */
2345 PORTCR(131, 0xe6052083), /* PORT131CR */
2346 PORTCR(132, 0xe6052084), /* PORT132CR */
2347 PORTCR(133, 0xe6052085), /* PORT133CR */
2348 PORTCR(134, 0xe6052086), /* PORT134CR */
2349 PORTCR(135, 0xe6052087), /* PORT135CR */
2350 PORTCR(136, 0xe6052088), /* PORT136CR */
2351 PORTCR(137, 0xe6052089), /* PORT137CR */
2352 PORTCR(138, 0xe605208a), /* PORT138CR */
2353 PORTCR(139, 0xe605208b), /* PORT139CR */
2354
2355 PORTCR(140, 0xe605208c), /* PORT140CR */
2356 PORTCR(141, 0xe605208d), /* PORT141CR */
2357 PORTCR(142, 0xe605208e), /* PORT142CR */
2358 PORTCR(143, 0xe605208f), /* PORT143CR */
2359 PORTCR(144, 0xe6052090), /* PORT144CR */
2360 PORTCR(145, 0xe6052091), /* PORT145CR */
2361 PORTCR(146, 0xe6052092), /* PORT146CR */
2362 PORTCR(147, 0xe6052093), /* PORT147CR */
2363 PORTCR(148, 0xe6052094), /* PORT148CR */
2364 PORTCR(149, 0xe6052095), /* PORT149CR */
2365
2366 PORTCR(150, 0xe6052096), /* PORT150CR */
2367 PORTCR(151, 0xe6052097), /* PORT151CR */
2368 PORTCR(152, 0xe6052098), /* PORT152CR */
2369 PORTCR(153, 0xe6052099), /* PORT153CR */
2370 PORTCR(154, 0xe605209a), /* PORT154CR */
2371 PORTCR(155, 0xe605209b), /* PORT155CR */
2372 PORTCR(156, 0xe605209c), /* PORT156CR */
2373 PORTCR(157, 0xe605209d), /* PORT157CR */
2374 PORTCR(158, 0xe605209e), /* PORT158CR */
2375 PORTCR(159, 0xe605209f), /* PORT159CR */
2376
2377 PORTCR(160, 0xe60520a0), /* PORT160CR */
2378 PORTCR(161, 0xe60520a1), /* PORT161CR */
2379 PORTCR(162, 0xe60520a2), /* PORT162CR */
2380 PORTCR(163, 0xe60520a3), /* PORT163CR */
2381 PORTCR(164, 0xe60520a4), /* PORT164CR */
2382
2383 PORTCR(192, 0xe60520c0), /* PORT192CR */
2384 PORTCR(193, 0xe60520c1), /* PORT193CR */
2385 PORTCR(194, 0xe60520c2), /* PORT194CR */
2386 PORTCR(195, 0xe60520c3), /* PORT195CR */
2387 PORTCR(196, 0xe60520c4), /* PORT196CR */
2388 PORTCR(197, 0xe60520c5), /* PORT197CR */
2389 PORTCR(198, 0xe60520c6), /* PORT198CR */
2390 PORTCR(199, 0xe60520c7), /* PORT199CR */
2391
2392 PORTCR(200, 0xe60520c8), /* PORT200CR */
2393 PORTCR(201, 0xe60520c9), /* PORT201CR */
2394 PORTCR(202, 0xe60520ca), /* PORT202CR */
2395 PORTCR(203, 0xe60520cb), /* PORT203CR */
2396 PORTCR(204, 0xe60520cc), /* PORT204CR */
2397 PORTCR(205, 0xe60520cd), /* PORT205CR */
2398 PORTCR(206, 0xe60520ce), /* PORT206CR */
2399 PORTCR(207, 0xe60520cf), /* PORT207CR */
2400 PORTCR(208, 0xe60520d0), /* PORT208CR */
2401 PORTCR(209, 0xe60520d1), /* PORT209CR */
2402
2403 PORTCR(210, 0xe60520d2), /* PORT210CR */
2404 PORTCR(211, 0xe60520d3), /* PORT211CR */
2405 PORTCR(212, 0xe60520d4), /* PORT212CR */
2406 PORTCR(213, 0xe60520d5), /* PORT213CR */
2407 PORTCR(214, 0xe60520d6), /* PORT214CR */
2408 PORTCR(215, 0xe60520d7), /* PORT215CR */
2409 PORTCR(216, 0xe60520d8), /* PORT216CR */
2410 PORTCR(217, 0xe60520d9), /* PORT217CR */
2411 PORTCR(218, 0xe60520da), /* PORT218CR */
2412 PORTCR(219, 0xe60520db), /* PORT219CR */
2413
2414 PORTCR(220, 0xe60520dc), /* PORT220CR */
2415 PORTCR(221, 0xe60520dd), /* PORT221CR */
2416 PORTCR(222, 0xe60520de), /* PORT222CR */
2417 PORTCR(223, 0xe60520df), /* PORT223CR */
2418 PORTCR(224, 0xe60530e0), /* PORT224CR */
2419 PORTCR(225, 0xe60530e1), /* PORT225CR */
2420 PORTCR(226, 0xe60530e2), /* PORT226CR */
2421 PORTCR(227, 0xe60530e3), /* PORT227CR */
2422 PORTCR(228, 0xe60530e4), /* PORT228CR */
2423 PORTCR(229, 0xe60530e5), /* PORT229CR */
2424
2425 PORTCR(230, 0xe60530e6), /* PORT230CR */
2426 PORTCR(231, 0xe60530e7), /* PORT231CR */
2427 PORTCR(232, 0xe60530e8), /* PORT232CR */
2428 PORTCR(233, 0xe60530e9), /* PORT233CR */
2429 PORTCR(234, 0xe60530ea), /* PORT234CR */
2430 PORTCR(235, 0xe60530eb), /* PORT235CR */
2431 PORTCR(236, 0xe60530ec), /* PORT236CR */
2432 PORTCR(237, 0xe60530ed), /* PORT237CR */
2433 PORTCR(238, 0xe60530ee), /* PORT238CR */
2434 PORTCR(239, 0xe60530ef), /* PORT239CR */
2435
2436 PORTCR(240, 0xe60530f0), /* PORT240CR */
2437 PORTCR(241, 0xe60530f1), /* PORT241CR */
2438 PORTCR(242, 0xe60530f2), /* PORT242CR */
2439 PORTCR(243, 0xe60530f3), /* PORT243CR */
2440 PORTCR(244, 0xe60530f4), /* PORT244CR */
2441 PORTCR(245, 0xe60530f5), /* PORT245CR */
2442 PORTCR(246, 0xe60530f6), /* PORT246CR */
2443 PORTCR(247, 0xe60530f7), /* PORT247CR */
2444 PORTCR(248, 0xe60530f8), /* PORT248CR */
2445 PORTCR(249, 0xe60530f9), /* PORT249CR */
2446
2447 PORTCR(250, 0xe60530fa), /* PORT250CR */
2448 PORTCR(251, 0xe60530fb), /* PORT251CR */
2449 PORTCR(252, 0xe60530fc), /* PORT252CR */
2450 PORTCR(253, 0xe60530fd), /* PORT253CR */
2451 PORTCR(254, 0xe60530fe), /* PORT254CR */
2452 PORTCR(255, 0xe60530ff), /* PORT255CR */
2453 PORTCR(256, 0xe6053100), /* PORT256CR */
2454 PORTCR(257, 0xe6053101), /* PORT257CR */
2455 PORTCR(258, 0xe6053102), /* PORT258CR */
2456 PORTCR(259, 0xe6053103), /* PORT259CR */
2457
2458 PORTCR(260, 0xe6053104), /* PORT260CR */
2459 PORTCR(261, 0xe6053105), /* PORT261CR */
2460 PORTCR(262, 0xe6053106), /* PORT262CR */
2461 PORTCR(263, 0xe6053107), /* PORT263CR */
2462 PORTCR(264, 0xe6053108), /* PORT264CR */
2463 PORTCR(265, 0xe6053109), /* PORT265CR */
2464 PORTCR(266, 0xe605310a), /* PORT266CR */
2465 PORTCR(267, 0xe605310b), /* PORT267CR */
2466 PORTCR(268, 0xe605310c), /* PORT268CR */
2467 PORTCR(269, 0xe605310d), /* PORT269CR */
2468
2469 PORTCR(270, 0xe605310e), /* PORT270CR */
2470 PORTCR(271, 0xe605310f), /* PORT271CR */
2471 PORTCR(272, 0xe6053110), /* PORT272CR */
2472 PORTCR(273, 0xe6053111), /* PORT273CR */
2473 PORTCR(274, 0xe6053112), /* PORT274CR */
2474 PORTCR(275, 0xe6053113), /* PORT275CR */
2475 PORTCR(276, 0xe6053114), /* PORT276CR */
2476 PORTCR(277, 0xe6053115), /* PORT277CR */
2477 PORTCR(278, 0xe6053116), /* PORT278CR */
2478 PORTCR(279, 0xe6053117), /* PORT279CR */
2479
2480 PORTCR(280, 0xe6053118), /* PORT280CR */
2481 PORTCR(281, 0xe6053119), /* PORT281CR */
2482 PORTCR(282, 0xe605311a), /* PORT282CR */
2483
2484 PORTCR(288, 0xe6052120), /* PORT288CR */
2485 PORTCR(289, 0xe6052121), /* PORT289CR */
2486
2487 PORTCR(290, 0xe6052122), /* PORT290CR */
2488 PORTCR(291, 0xe6052123), /* PORT291CR */
2489 PORTCR(292, 0xe6052124), /* PORT292CR */
2490 PORTCR(293, 0xe6052125), /* PORT293CR */
2491 PORTCR(294, 0xe6052126), /* PORT294CR */
2492 PORTCR(295, 0xe6052127), /* PORT295CR */
2493 PORTCR(296, 0xe6052128), /* PORT296CR */
2494 PORTCR(297, 0xe6052129), /* PORT297CR */
2495 PORTCR(298, 0xe605212a), /* PORT298CR */
2496 PORTCR(299, 0xe605212b), /* PORT299CR */
2497
2498 PORTCR(300, 0xe605212c), /* PORT300CR */
2499 PORTCR(301, 0xe605212d), /* PORT301CR */
2500 PORTCR(302, 0xe605212e), /* PORT302CR */
2501 PORTCR(303, 0xe605212f), /* PORT303CR */
2502 PORTCR(304, 0xe6052130), /* PORT304CR */
2503 PORTCR(305, 0xe6052131), /* PORT305CR */
2504 PORTCR(306, 0xe6052132), /* PORT306CR */
2505 PORTCR(307, 0xe6052133), /* PORT307CR */
2506 PORTCR(308, 0xe6052134), /* PORT308CR */
2507 PORTCR(309, 0xe6052135), /* PORT309CR */
2508
2509 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
2510 0, 0,
2511 0, 0,
2512 0, 0,
2513 0, 0,
2514 0, 0,
2515 0, 0,
2516 0, 0,
2517 0, 0,
2518 0, 0,
2519 0, 0,
2520 0, 0,
2521 0, 0,
2522 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
2523 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
2524 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
2525 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
2526 0, 0,
2527 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
2528 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
2529 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
2530 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
2531 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
2532 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
2533 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
2534 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
2535 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
2536 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
2537 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
2538 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
2539 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
2540 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
2541 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
2542 }
2543 },
2544 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2545 0, 0,
2546 0, 0,
2547 0, 0,
2548 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
2549 0, 0,
2550 0, 0,
2551 0, 0,
2552 0, 0,
2553 0, 0,
2554 0, 0,
2555 0, 0,
2556 0, 0,
2557 0, 0,
2558 0, 0,
2559 0, 0,
2560 0, 0,
2561 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
2562 0, 0,
2563 0, 0,
2564 0, 0,
2565 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
2566 0, 0,
2567 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
2568 0, 0,
2569 0, 0,
2570 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
2571 0, 0,
2572 0, 0,
2573 0, 0,
2574 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
2575 0, 0,
2576 0, 0,
2577 }
2578 },
2579 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2580 0, 0,
2581 0, 0,
2582 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
2583 0, 0,
2584 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
2585 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
2586 0, 0,
2587 0, 0,
2588 0, 0,
2589 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
2590 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
2591 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
2592 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
2593 0, 0,
2594 0, 0,
2595 0, 0,
2596 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
2597 0, 0,
2598 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
2599 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
2600 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
2601 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
2602 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
2603 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
2604 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
2605 0, 0,
2606 0, 0,
2607 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
2608 0, 0,
2609 0, 0,
2610 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
2611 0, 0,
2612 }
2613 },
2614 { },
2615};
2616
2617static struct pinmux_data_reg pinmux_data_regs[] = {
2618 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2619 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2620 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2621 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2622 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2623 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2624 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2625 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2626 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
2627 },
2628 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2629 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2630 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2631 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2632 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2633 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
2634 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2635 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2636 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
2637 },
2638 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
2639 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2640 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2641 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2642 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2643 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2644 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2645 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2646 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
2647 },
2648 { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
2649 0, 0, 0, 0,
2650 0, 0, 0, 0,
2651 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2652 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2653 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2654 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2655 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2656 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
2657 },
2658 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
2659 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2660 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2661 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2662 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2663 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2664 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2665 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2666 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
2667 },
2668 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
2669 0, 0, 0, 0,
2670 0, 0, 0, 0,
2671 0, 0, 0, 0,
2672 0, 0, 0, 0,
2673 0, 0, 0, 0,
2674 0, 0, 0, 0,
2675 0, 0, 0, PORT164_DATA,
2676 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
2677 },
2678 { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
2679 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2680 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2681 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2682 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2683 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2684 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2685 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2686 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
2687 },
2688 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
2689 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
2690 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2691 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2692 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2693 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2694 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2695 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2696 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
2697 },
2698 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
2699 0, 0, 0, 0,
2700 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2701 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2702 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2703 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2704 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2705 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2706 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
2707 },
2708 { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
2709 0, 0, 0, 0,
2710 0, 0, 0, 0,
2711 0, 0, PORT309_DATA, PORT308_DATA,
2712 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2713 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2714 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2715 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2716 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
2717 },
2718 { },
2719};
2720
2721static struct pinmux_info sh73a0_pinmux_info = {
2722 .name = "sh73a0_pfc",
2723 .reserved_id = PINMUX_RESERVED,
2724 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2725 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2726 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2727 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
2728 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2729 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2730 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2731
2732 .first_gpio = GPIO_PORT0,
2733 .last_gpio = GPIO_FN_FSIAISLD_PU,
2734
2735 .gpios = pinmux_gpios,
2736 .cfg_regs = pinmux_config_regs,
2737 .data_regs = pinmux_data_regs,
2738
2739 .gpio_data = pinmux_data,
2740 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2741};
2742
2743void sh73a0_pinmux_init(void)
2744{
2745 register_pinmux(&sh73a0_pinmux_info);
2746}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 564a6d0be47..2e3e11ee7c4 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -416,6 +416,16 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
416 .addr = 0xe6870030, 416 .addr = 0xe6870030,
417 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 417 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
418 .mid_rid = 0xce, 418 .mid_rid = 0xce,
419 }, {
420 .slave_id = SHDMA_SLAVE_MMCIF_TX,
421 .addr = 0xe6bd0034,
422 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
423 .mid_rid = 0xd1,
424 }, {
425 .slave_id = SHDMA_SLAVE_MMCIF_RX,
426 .addr = 0xe6bd0034,
427 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
428 .mid_rid = 0xd2,
419 }, 429 },
420}; 430};
421 431
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
new file mode 100644
index 00000000000..f1eff8b37bd
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -0,0 +1,412 @@
1/*
2 * sh73a0 processor support
3 *
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
30#include <linux/sh_intc.h>
31#include <linux/sh_timer.h>
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35
36static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .type = PORT_SCIFA,
40 .irqs = { gic_spi(72), gic_spi(72),
41 gic_spi(72), gic_spi(72) },
42};
43
44static struct platform_device scif0_device = {
45 .name = "sh-sci",
46 .id = 0,
47 .dev = {
48 .platform_data = &scif0_platform_data,
49 },
50};
51
52static struct plat_sci_port scif1_platform_data = {
53 .mapbase = 0xe6c50000,
54 .flags = UPF_BOOT_AUTOCONF,
55 .type = PORT_SCIFA,
56 .irqs = { gic_spi(73), gic_spi(73),
57 gic_spi(73), gic_spi(73) },
58};
59
60static struct platform_device scif1_device = {
61 .name = "sh-sci",
62 .id = 1,
63 .dev = {
64 .platform_data = &scif1_platform_data,
65 },
66};
67
68static struct plat_sci_port scif2_platform_data = {
69 .mapbase = 0xe6c60000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .type = PORT_SCIFA,
72 .irqs = { gic_spi(74), gic_spi(74),
73 gic_spi(74), gic_spi(74) },
74};
75
76static struct platform_device scif2_device = {
77 .name = "sh-sci",
78 .id = 2,
79 .dev = {
80 .platform_data = &scif2_platform_data,
81 },
82};
83
84static struct plat_sci_port scif3_platform_data = {
85 .mapbase = 0xe6c70000,
86 .flags = UPF_BOOT_AUTOCONF,
87 .type = PORT_SCIFA,
88 .irqs = { gic_spi(75), gic_spi(75),
89 gic_spi(75), gic_spi(75) },
90};
91
92static struct platform_device scif3_device = {
93 .name = "sh-sci",
94 .id = 3,
95 .dev = {
96 .platform_data = &scif3_platform_data,
97 },
98};
99
100static struct plat_sci_port scif4_platform_data = {
101 .mapbase = 0xe6c80000,
102 .flags = UPF_BOOT_AUTOCONF,
103 .type = PORT_SCIFA,
104 .irqs = { gic_spi(78), gic_spi(78),
105 gic_spi(78), gic_spi(78) },
106};
107
108static struct platform_device scif4_device = {
109 .name = "sh-sci",
110 .id = 4,
111 .dev = {
112 .platform_data = &scif4_platform_data,
113 },
114};
115
116static struct plat_sci_port scif5_platform_data = {
117 .mapbase = 0xe6cb0000,
118 .flags = UPF_BOOT_AUTOCONF,
119 .type = PORT_SCIFA,
120 .irqs = { gic_spi(79), gic_spi(79),
121 gic_spi(79), gic_spi(79) },
122};
123
124static struct platform_device scif5_device = {
125 .name = "sh-sci",
126 .id = 5,
127 .dev = {
128 .platform_data = &scif5_platform_data,
129 },
130};
131
132static struct plat_sci_port scif6_platform_data = {
133 .mapbase = 0xe6cc0000,
134 .flags = UPF_BOOT_AUTOCONF,
135 .type = PORT_SCIFA,
136 .irqs = { gic_spi(156), gic_spi(156),
137 gic_spi(156), gic_spi(156) },
138};
139
140static struct platform_device scif6_device = {
141 .name = "sh-sci",
142 .id = 6,
143 .dev = {
144 .platform_data = &scif6_platform_data,
145 },
146};
147
148static struct plat_sci_port scif7_platform_data = {
149 .mapbase = 0xe6cd0000,
150 .flags = UPF_BOOT_AUTOCONF,
151 .type = PORT_SCIFA,
152 .irqs = { gic_spi(143), gic_spi(143),
153 gic_spi(143), gic_spi(143) },
154};
155
156static struct platform_device scif7_device = {
157 .name = "sh-sci",
158 .id = 7,
159 .dev = {
160 .platform_data = &scif7_platform_data,
161 },
162};
163
164static struct plat_sci_port scif8_platform_data = {
165 .mapbase = 0xe6c30000,
166 .flags = UPF_BOOT_AUTOCONF,
167 .type = PORT_SCIFB,
168 .irqs = { gic_spi(80), gic_spi(80),
169 gic_spi(80), gic_spi(80) },
170};
171
172static struct platform_device scif8_device = {
173 .name = "sh-sci",
174 .id = 8,
175 .dev = {
176 .platform_data = &scif8_platform_data,
177 },
178};
179
180static struct sh_timer_config cmt10_platform_data = {
181 .name = "CMT10",
182 .channel_offset = 0x10,
183 .timer_bit = 0,
184 .clockevent_rating = 125,
185 .clocksource_rating = 125,
186};
187
188static struct resource cmt10_resources[] = {
189 [0] = {
190 .name = "CMT10",
191 .start = 0xe6138010,
192 .end = 0xe613801b,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 .start = gic_spi(65),
197 .flags = IORESOURCE_IRQ,
198 },
199};
200
201static struct platform_device cmt10_device = {
202 .name = "sh_cmt",
203 .id = 10,
204 .dev = {
205 .platform_data = &cmt10_platform_data,
206 },
207 .resource = cmt10_resources,
208 .num_resources = ARRAY_SIZE(cmt10_resources),
209};
210
211/* TMU */
212static struct sh_timer_config tmu00_platform_data = {
213 .name = "TMU00",
214 .channel_offset = 0x4,
215 .timer_bit = 0,
216 .clockevent_rating = 200,
217};
218
219static struct resource tmu00_resources[] = {
220 [0] = {
221 .name = "TMU00",
222 .start = 0xfff60008,
223 .end = 0xfff60013,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device tmu00_device = {
233 .name = "sh_tmu",
234 .id = 0,
235 .dev = {
236 .platform_data = &tmu00_platform_data,
237 },
238 .resource = tmu00_resources,
239 .num_resources = ARRAY_SIZE(tmu00_resources),
240};
241
242static struct sh_timer_config tmu01_platform_data = {
243 .name = "TMU01",
244 .channel_offset = 0x10,
245 .timer_bit = 1,
246 .clocksource_rating = 200,
247};
248
249static struct resource tmu01_resources[] = {
250 [0] = {
251 .name = "TMU01",
252 .start = 0xfff60014,
253 .end = 0xfff6001f,
254 .flags = IORESOURCE_MEM,
255 },
256 [1] = {
257 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
258 .flags = IORESOURCE_IRQ,
259 },
260};
261
262static struct platform_device tmu01_device = {
263 .name = "sh_tmu",
264 .id = 1,
265 .dev = {
266 .platform_data = &tmu01_platform_data,
267 },
268 .resource = tmu01_resources,
269 .num_resources = ARRAY_SIZE(tmu01_resources),
270};
271
272static struct resource i2c0_resources[] = {
273 [0] = {
274 .name = "IIC0",
275 .start = 0xe6820000,
276 .end = 0xe6820425 - 1,
277 .flags = IORESOURCE_MEM,
278 },
279 [1] = {
280 .start = gic_spi(167),
281 .end = gic_spi(170),
282 .flags = IORESOURCE_IRQ,
283 },
284};
285
286static struct resource i2c1_resources[] = {
287 [0] = {
288 .name = "IIC1",
289 .start = 0xe6822000,
290 .end = 0xe6822425 - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 [1] = {
294 .start = gic_spi(51),
295 .end = gic_spi(54),
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct resource i2c2_resources[] = {
301 [0] = {
302 .name = "IIC2",
303 .start = 0xe6824000,
304 .end = 0xe6824425 - 1,
305 .flags = IORESOURCE_MEM,
306 },
307 [1] = {
308 .start = gic_spi(171),
309 .end = gic_spi(174),
310 .flags = IORESOURCE_IRQ,
311 },
312};
313
314static struct resource i2c3_resources[] = {
315 [0] = {
316 .name = "IIC3",
317 .start = 0xe6826000,
318 .end = 0xe6826425 - 1,
319 .flags = IORESOURCE_MEM,
320 },
321 [1] = {
322 .start = gic_spi(183),
323 .end = gic_spi(186),
324 .flags = IORESOURCE_IRQ,
325 },
326};
327
328static struct resource i2c4_resources[] = {
329 [0] = {
330 .name = "IIC4",
331 .start = 0xe6828000,
332 .end = 0xe6828425 - 1,
333 .flags = IORESOURCE_MEM,
334 },
335 [1] = {
336 .start = gic_spi(187),
337 .end = gic_spi(190),
338 .flags = IORESOURCE_IRQ,
339 },
340};
341
342static struct platform_device i2c0_device = {
343 .name = "i2c-sh_mobile",
344 .id = 0,
345 .resource = i2c0_resources,
346 .num_resources = ARRAY_SIZE(i2c0_resources),
347};
348
349static struct platform_device i2c1_device = {
350 .name = "i2c-sh_mobile",
351 .id = 1,
352 .resource = i2c1_resources,
353 .num_resources = ARRAY_SIZE(i2c1_resources),
354};
355
356static struct platform_device i2c2_device = {
357 .name = "i2c-sh_mobile",
358 .id = 2,
359 .resource = i2c2_resources,
360 .num_resources = ARRAY_SIZE(i2c2_resources),
361};
362
363static struct platform_device i2c3_device = {
364 .name = "i2c-sh_mobile",
365 .id = 3,
366 .resource = i2c3_resources,
367 .num_resources = ARRAY_SIZE(i2c3_resources),
368};
369
370static struct platform_device i2c4_device = {
371 .name = "i2c-sh_mobile",
372 .id = 4,
373 .resource = i2c4_resources,
374 .num_resources = ARRAY_SIZE(i2c4_resources),
375};
376
377static struct platform_device *sh73a0_early_devices[] __initdata = {
378 &scif0_device,
379 &scif1_device,
380 &scif2_device,
381 &scif3_device,
382 &scif4_device,
383 &scif5_device,
384 &scif6_device,
385 &scif7_device,
386 &scif8_device,
387 &cmt10_device,
388 &tmu00_device,
389 &tmu01_device,
390};
391
392static struct platform_device *sh73a0_late_devices[] __initdata = {
393 &i2c0_device,
394 &i2c1_device,
395 &i2c2_device,
396 &i2c3_device,
397 &i2c4_device,
398};
399
400void __init sh73a0_add_standard_devices(void)
401{
402 platform_add_devices(sh73a0_early_devices,
403 ARRAY_SIZE(sh73a0_early_devices));
404 platform_add_devices(sh73a0_late_devices,
405 ARRAY_SIZE(sh73a0_late_devices));
406}
407
408void __init sh73a0_add_early_devices(void)
409{
410 early_platform_add_devices(sh73a0_early_devices,
411 ARRAY_SIZE(sh73a0_early_devices));
412}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 49db8b3e4a4..fcc1e628e05 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,7 +813,7 @@ config CACHE_L2X0
813 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 813 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
814 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ 814 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
815 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ 815 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
816 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 816 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
817 default y 817 default y
818 select OUTER_CACHE 818 select OUTER_CACHE
819 select OUTER_CACHE_SYNC 819 select OUTER_CACHE_SYNC
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 00:21:20 -0400