102 files changed, 2723 insertions, 572 deletions

diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index f8766af1121..564cb8c19f1 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -35,20 +35,19 @@
                                 };
 
                                 esdhc@70008000 { /* ESDHC2 */
-                                        cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
-                                        wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
+                                        cd-gpios = <&gpio1 6 0>;
+                                        wp-gpios = <&gpio1 5 0>;
                                         status = "okay";
                                 };
 
-                                uart2: uart@7000c000 { /* UART3 */
+                                uart3: uart@7000c000 {
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@70010000 { /* ECSPI1 */
                                         fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
-                                                   <&gpio3 25 0>; /* GPIO4_25 */
+                                        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
                                         status = "okay";
 
                                         pmic: mc13892@0 {
@@ -57,7 +56,7 @@
                                                 compatible = "fsl,mc13892";
                                                 spi-max-frequency = <6000000>;
                                                 reg = <0>;
-                                                mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                                                mc13xxx-irq-gpios = <&gpio1 8 0>;
                                                 fsl,mc13xxx-uses-regulator;
                                         };
 
@@ -91,12 +90,12 @@
                                 reg = <0x73fa8000 0x4000>;
                         };
 
-                        uart0: uart@73fbc000 {
+                        uart1: uart@73fbc000 {
                                 fsl,uart-has-rtscts;
                                 status = "okay";
                         };
 
-                        uart1: uart@73fc0000 {
+                        uart2: uart@73fc0000 {
                                 status = "okay";
                         };
                 };
@@ -127,7 +126,7 @@
 
                 power {
                         label = "Power Button";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio2 21 0>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 327ab8e3a4c..6663986fe1c 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -14,9 +14,9 @@
 
 / {
         aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
         };
 
         tzic: tz-interrupt-controller@e0000000 {
@@ -86,7 +86,7 @@
                                         status = "disabled";
                                 };
 
-                                uart2: uart@7000c000 { /* UART3 */
+                                uart3: uart@7000c000 {
                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                         reg = <0x7000c000 0x4000>;
                                         interrupts = <33>;
@@ -117,7 +117,7 @@
                                 };
                         };
 
-                        gpio0: gpio@73f84000 { /* GPIO1 */
+                        gpio1: gpio@73f84000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f84000 0x4000>;
                                 interrupts = <50 51>;
@@ -127,7 +127,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio1: gpio@73f88000 { /* GPIO2 */
+                        gpio2: gpio@73f88000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f88000 0x4000>;
                                 interrupts = <52 53>;
@@ -137,7 +137,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio2: gpio@73f8c000 { /* GPIO3 */
+                        gpio3: gpio@73f8c000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f8c000 0x4000>;
                                 interrupts = <54 55>;
@@ -147,7 +147,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio3: gpio@73f90000 { /* GPIO4 */
+                        gpio4: gpio@73f90000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                 reg = <0x73f90000 0x4000>;
                                 interrupts = <56 57>;
@@ -171,14 +171,14 @@
                                 status = "disabled";
                         };
 
-                        uart0: uart@73fbc000 {
+                        uart1: uart@73fbc000 {
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fbc000 0x4000>;
                                 interrupts = <31>;
                                 status = "disabled";
                         };
 
-                        uart1: uart@73fc0000 {
+                        uart2: uart@73fc0000 {
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fc0000 0x4000>;
                                 interrupts = <32>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2ab7f80a0a3..2dccce46ed8 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -29,8 +29,8 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
-                                        wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
+                                        cd-gpios = <&gpio1 1 0>;
+                                        wp-gpios = <&gpio1 9 0>;
                                         status = "okay";
                                 };
                         };
@@ -44,7 +44,7 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
                 };
@@ -67,7 +67,7 @@
                         compatible = "smsc,lan9220", "smsc,lan9115";
                         reg = <0xf4000000 0x2000000>;
                         phy-mode = "mii";
-                        interrupt-parent = <&gpio1>;
+                        interrupt-parent = <&gpio2>;
                         interrupts = <31>;
                         reg-io-width = <4>;
                         smsc,irq-push-pull;
@@ -79,34 +79,34 @@
 
                 home {
                         label = "Home";
-                        gpios = <&gpio4 10 0>; /* GPIO5_10 */
+                        gpios = <&gpio5 10 0>;
                         linux,code = <102>; /* KEY_HOME */
                         gpio-key,wakeup;
                 };
 
                 back {
                         label = "Back";
-                        gpios = <&gpio4 11 0>; /* GPIO5_11 */
+                        gpios = <&gpio5 11 0>;
                         linux,code = <158>; /* KEY_BACK */
                         gpio-key,wakeup;
                 };
 
                 program {
                         label = "Program";
-                        gpios = <&gpio4 12 0>; /* GPIO5_12 */
+                        gpios = <&gpio5 12 0>;
                         linux,code = <362>; /* KEY_PROGRAM */
                         gpio-key,wakeup;
                 };
 
                 volume-up {
                         label = "Volume Up";
-                        gpios = <&gpio4 13 0>; /* GPIO5_13 */
+                        gpios = <&gpio5 13 0>;
                         linux,code = <115>; /* KEY_VOLUMEUP */
                 };
 
                 volume-down {
                         label = "Volume Down";
-                        gpios = <&gpio3 0 0>; /* GPIO4_0 */
+                        gpios = <&gpio4 0 0>;
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 3f3a88185ff..5bac4aa4800 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -29,15 +29,14 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
-                                        wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
+                                        cd-gpios = <&gpio3 13 0>;
+                                        wp-gpios = <&gpio3 14 0>;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
                                         fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
-                                                   <&gpio2 19 0>; /* GPIO3_19 */
+                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
 
                                         flash: at45db321d@1 {
@@ -61,8 +60,8 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
-                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
-                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        cd-gpios = <&gpio3 11 0>;
+                                        wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
@@ -76,7 +75,7 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
                 };
@@ -102,7 +101,7 @@
 
                         fec@63fec000 {
                                 phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
                         };
                 };
@@ -113,7 +112,7 @@
 
                 green {
                         label = "Heartbeat";
-                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        gpios = <&gpio7 7 0>;
                         linux,default-trigger = "heartbeat";
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index ae6de6d0c3f..5c57c8672c3 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -29,13 +29,13 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        cd-gpios = <&gpio3 13 0>;
                                         status = "okay";
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
-                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
-                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        cd-gpios = <&gpio3 11 0>;
+                                        wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
@@ -49,7 +49,7 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
                 };
@@ -84,7 +84,7 @@
 
                         fec@63fec000 {
                                 phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
                         };
                 };
@@ -95,20 +95,20 @@
 
                 power {
                         label = "Power Button";
-                        gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                        gpios = <&gpio1 8 0>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
 
                 volume-up {
                         label = "Volume Up";
-                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        gpios = <&gpio2 14 0>;
                         linux,code = <115>; /* KEY_VOLUMEUP */
                 };
 
                 volume-down {
                         label = "Volume Down";
-                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        gpios = <&gpio2 15 0>;
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
@@ -118,7 +118,7 @@
 
                 user {
                         label = "Heartbeat";
-                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        gpios = <&gpio7 7 0>;
                         linux,default-trigger = "heartbeat";
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index b1c062eea71..c7ee86c2dfb 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -29,8 +29,8 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
-                                        wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
+                                        cd-gpios = <&gpio3 13 0>;
+                                        wp-gpios = <&gpio4 11 0>;
                                         status = "okay";
                                 };
 
@@ -39,15 +39,14 @@
                                         status = "okay";
                                 };
 
-                                uart2: uart@5000c000 { /* UART3 */
+                                uart3: uart@5000c000 {
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
                                         fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
-                                                   <&gpio2 19 0>; /* GPIO3_19 */
+                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
 
                                         zigbee: mc1323@0 {
@@ -91,11 +90,11 @@
                                 reg = <0x53fa8000 0x4000>;
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 status = "okay";
                         };
 
-                        uart1: uart@53fc0000 { /* UART2 */
+                        uart2: uart@53fc0000 {
                                 status = "okay";
                         };
                 };
@@ -145,7 +144,7 @@
 
                         fec@63fec000 {
                                 phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
                         };
                 };
@@ -156,13 +155,13 @@
 
                 volume-up {
                         label = "Volume Up";
-                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        gpios = <&gpio2 14 0>;
                         linux,code = <115>; /* KEY_VOLUMEUP */
                 };
 
                 volume-down {
                         label = "Volume Down";
-                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        gpios = <&gpio2 15 0>;
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 099cd84ee37..5dd91b942c9 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -14,11 +14,11 @@
 
 / {
         aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
-                serial3 = &uart3;
-                serial4 = &uart4;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
         };
 
         tzic: tz-interrupt-controller@0fffc000 {
@@ -88,7 +88,7 @@
                                         status = "disabled";
                                 };
 
-                                uart2: uart@5000c000 { /* UART3 */
+                                uart3: uart@5000c000 {
                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                         reg = <0x5000c000 0x4000>;
                                         interrupts = <33>;
@@ -119,7 +119,7 @@
                                 };
                         };
 
-                        gpio0: gpio@53f84000 { /* GPIO1 */
+                        gpio1: gpio@53f84000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f84000 0x4000>;
                                 interrupts = <50 51>;
@@ -129,7 +129,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio1: gpio@53f88000 { /* GPIO2 */
+                        gpio2: gpio@53f88000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f88000 0x4000>;
                                 interrupts = <52 53>;
@@ -139,7 +139,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio2: gpio@53f8c000 { /* GPIO3 */
+                        gpio3: gpio@53f8c000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f8c000 0x4000>;
                                 interrupts = <54 55>;
@@ -149,7 +149,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio3: gpio@53f90000 { /* GPIO4 */
+                        gpio4: gpio@53f90000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53f90000 0x4000>;
                                 interrupts = <56 57>;
@@ -173,21 +173,21 @@
                                 status = "disabled";
                         };
 
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fbc000 0x4000>;
                                 interrupts = <31>;
                                 status = "disabled";
                         };
 
-                        uart1: uart@53fc0000 { /* UART2 */
+                        uart2: uart@53fc0000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fc0000 0x4000>;
                                 interrupts = <32>;
                                 status = "disabled";
                         };
 
-                        gpio4: gpio@53fdc000 { /* GPIO5 */
+                        gpio5: gpio@53fdc000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53fdc000 0x4000>;
                                 interrupts = <103 104>;
@@ -197,7 +197,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio5: gpio@53fe0000 { /* GPIO6 */
+                        gpio6: gpio@53fe0000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53fe0000 0x4000>;
                                 interrupts = <105 106>;
@@ -207,7 +207,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio6: gpio@53fe4000 { /* GPIO7 */
+                        gpio7: gpio@53fe4000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                 reg = <0x53fe4000 0x4000>;
                                 interrupts = <107 108>;
@@ -226,7 +226,7 @@
                                 status = "disabled";
                         };
 
-                        uart3: uart@53ff0000 { /* UART4 */
+                        uart4: uart@53ff0000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53ff0000 0x4000>;
                                 interrupts = <13>;
@@ -241,7 +241,7 @@
                         reg = <0x60000000 0x10000000>;
                         ranges;
 
-                        uart4: uart@63f90000 { /* UART5 */
+                        uart5: uart@63f90000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x63f90000 0x4000>;
                                 interrupts = <86>;
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 072974e443f..c3977e0478b 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -14,8 +14,8 @@
 /include/ "imx6q.dtsi"
 
 / {
-        model = "Freescale i.MX6 Quad SABRE Automotive Board";
-        compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+        model = "Freescale i.MX6 Quad Armadillo2 Board";
+        compatible = "fsl,imx6q-arm2", "fsl,imx6q";
 
         chosen {
                 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
@@ -34,8 +34,8 @@
                         };
 
                         usdhc@02198000 { /* uSDHC3 */
-                                cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
-                                wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
+                                cd-gpios = <&gpio6 11 0>;
+                                wp-gpios = <&gpio6 14 0>;
                                 status = "okay";
                         };
 
@@ -44,7 +44,7 @@
                                 status = "okay";
                         };
 
-                        uart3: uart@021f0000 { /* UART4 */
+                        uart4: uart@021f0000 {
                                 status = "okay";
                         };
                 };
@@ -55,7 +55,7 @@
 
                 debug-led {
                         label = "Heartbeat";
-                        gpios = <&gpio2 25 0>; /* GPIO3_25 */
+                        gpios = <&gpio3 25 0>;
                         linux,default-trigger = "heartbeat";
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
new file mode 100644
index 00000000000..08d920de728
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx6q.dtsi"
+
+/ {
+        model = "Freescale i.MX6 Quad SABRE Lite Board";
+        compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
+
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+
+        soc {
+                aips-bus@02100000 { /* AIPS2 */
+                        enet@02188000 {
+                                phy-mode = "rgmii";
+                                phy-reset-gpios = <&gpio3 23 0>;
+                                status = "okay";
+                        };
+
+                        usdhc@02198000 { /* uSDHC3 */
+                                cd-gpios = <&gpio7 0 0>;
+                                wp-gpios = <&gpio7 1 0>;
+                                status = "okay";
+                        };
+
+                        usdhc@0219c000 { /* uSDHC4 */
+                                cd-gpios = <&gpio2 6 0>;
+                                wp-gpios = <&gpio2 7 0>;
+                                status = "okay";
+                        };
+
+                        uart2: uart@021e8000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7dda599558c..263e8f3664b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -14,11 +14,11 @@
 
 / {
         aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
-                serial3 = &uart3;
-                serial4 = &uart4;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
         };
 
         cpus {
@@ -165,7 +165,7 @@
                                         status = "disabled";
                                 };
 
-                                uart0: uart@02020000 { /* UART1 */
+                                uart1: uart@02020000 {
                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02020000 0x4000>;
                                         interrupts = <0 26 0x04>;
@@ -247,7 +247,7 @@
                                 interrupts = <0 55 0x04>;
                         };
 
-                        gpio0: gpio@0209c000 { /* GPIO1 */
+                        gpio1: gpio@0209c000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x0209c000 0x4000>;
                                 interrupts = <0 66 0x04 0 67 0x04>;
@@ -257,7 +257,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio1: gpio@020a0000 { /* GPIO2 */
+                        gpio2: gpio@020a0000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020a0000 0x4000>;
                                 interrupts = <0 68 0x04 0 69 0x04>;
@@ -267,7 +267,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio2: gpio@020a4000 { /* GPIO3 */
+                        gpio3: gpio@020a4000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020a4000 0x4000>;
                                 interrupts = <0 70 0x04 0 71 0x04>;
@@ -277,7 +277,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio3: gpio@020a8000 { /* GPIO4 */
+                        gpio4: gpio@020a8000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020a8000 0x4000>;
                                 interrupts = <0 72 0x04 0 73 0x04>;
@@ -287,7 +287,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio4: gpio@020ac000 { /* GPIO5 */
+                        gpio5: gpio@020ac000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020ac000 0x4000>;
                                 interrupts = <0 74 0x04 0 75 0x04>;
@@ -297,7 +297,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio5: gpio@020b0000 { /* GPIO6 */
+                        gpio6: gpio@020b0000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020b0000 0x4000>;
                                 interrupts = <0 76 0x04 0 77 0x04>;
@@ -307,7 +307,7 @@
                                 #interrupt-cells = <1>;
                         };
 
-                        gpio6: gpio@020b4000 { /* GPIO7 */
+                        gpio7: gpio@020b4000 {
                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                 reg = <0x020b4000 0x4000>;
                                 interrupts = <0 78 0x04 0 79 0x04>;
@@ -543,28 +543,28 @@
                                 interrupts = <0 18 0x04>;
                         };
 
-                        uart1: uart@021e8000 { /* UART2 */
+                        uart2: uart@021e8000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021e8000 0x4000>;
                                 interrupts = <0 27 0x04>;
                                 status = "disabled";
                         };
 
-                        uart2: uart@021ec000 { /* UART3 */
+                        uart3: uart@021ec000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021ec000 0x4000>;
                                 interrupts = <0 28 0x04>;
                                 status = "disabled";
                         };
 
-                        uart3: uart@021f0000 { /* UART4 */
+                        uart4: uart@021f0000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f0000 0x4000>;
                                 interrupts = <0 29 0x04>;
                                 status = "disabled";
                         };
 
-                        uart4: uart@021f4000 { /* UART5 */
+                        uart5: uart@021f4000 {
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f4000 0x4000>;
                                 interrupts = <0 30 0x04>;
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
new file mode 100644
index 00000000000..70c41fc897d
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/include/ "tegra30.dtsi"
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu evaluation board";
+        compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+        memory {
+                reg = < 0x80000000 0x40000000 >;
+        };
+
+        serial@70006000 {
+                clock-frequency = < 408000000 >;
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c700 {
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <100000>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 0e225b86b65..80afa1b70b8 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -1,16 +1,11 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra2 Harmony evaluation board";
         compatible = "nvidia,harmony", "nvidia,tegra20";
 
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
-        };
-
         memory@0 {
                 reg = < 0x00000000 0x40000000 >;
         };
@@ -52,16 +47,40 @@
                 ext-mic-en-gpios = <&gpio 185 0>;
         };
 
+        serial@70006000 {
+                status = "disable";
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
         serial@70006300 {
                 clock-frequency = < 216000000 >;
         };
 
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
         sdhci@c8000200 {
                 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 155 0>; /* gpio PT3 */
         };
 
+        sdhci@c8000400 {
+                status = "disable";
+        };
+
         sdhci@c8000600 {
                 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
new file mode 100644
index 00000000000..1a1d7023b69
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "Toshiba AC100 / Dynabook AZ";
+        compatible = "compal,paz00", "nvidia,tegra20";
+
+        memory@0 {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                status = "disable";
+        };
+
+        nvec@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,nvec";
+                reg = <0x7000C500 0x100>;
+                interrupts = <0 92 0x04>;
+                clock-frequency = <80000>;
+                request-gpios = <&gpio 170 0>;
+                slave-addr = <138>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+
+        serial@70006000 {
+                clock-frequency = <216000000>;
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
+        serial@70006300 {
+                clock-frequency = <216000000>;
+        };
+
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+                wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
+                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
+        sdhci@c8000400 {
+                status = "disable";
+        };
+
+        sdhci@c8000600 {
+                support-8bit;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index a72299b8e66..f552bcc0441 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -1,25 +1,60 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 
 / {
         model = "NVIDIA Seaboard";
         compatible = "nvidia,seaboard", "nvidia,tegra20";
 
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
-        };
-
         memory {
                 device_type = "memory";
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+
+        serial@70006000 {
+                status = "disable";
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
         serial@70006300 {
                 clock-frequency = < 216000000 >;
         };
 
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
         sdhci@c8000400 {
                 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
@@ -29,4 +64,8 @@
         sdhci@c8000600 {
                 support-8bit;
         };
+
+        usb@c5000000 {
+                nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
new file mode 100644
index 00000000000..3b3ee7db99f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -0,0 +1,65 @@
+/dts-v1/;
+
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "Compulab TrimSlice board";
+        compatible = "compulab,trimslice", "nvidia,tegra20";
+
+        memory@0 {
+                reg = < 0x00000000 0x40000000 >;
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000d000 {
+                status = "disable";
+        };
+
+        serial@70006000 {
+                clock-frequency = < 216000000 >;
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
+        serial@70006300 {
+                status = "disable";
+        };
+
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
+        sdhci@c8000400 {
+                status = "disable";
+        };
+
+        sdhci@c8000600 {
+                cd-gpios = <&gpio 121 0>;
+                wp-gpios = <&gpio 122 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 3f9abd6b696..c7d3b87f29d 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -1,24 +1,59 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra2 Ventana evaluation board";
         compatible = "nvidia,ventana", "nvidia,tegra20";
 
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
-        };
-
         memory {
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+
+        serial@70006000 {
+                status = "disable";
+        };
+
+        serial@70006040 {
+                status = "disable";
+        };
+
+        serial@70006200 {
+                status = "disable";
+        };
+
         serial@70006300 {
                 clock-frequency = < 216000000 >;
         };
 
+        serial@70006400 {
+                status = "disable";
+        };
+
+        sdhci@c8000000 {
+                status = "disable";
+        };
+
+        sdhci@c8000200 {
+                status = "disable";
+        };
+
         sdhci@c8000400 {
                 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 65d7e6a333e..660c8ad537c 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -5,9 +5,9 @@
         interrupt-parent = <&intc>;
 
         intc: interrupt-controller@50041000 {
-                compatible = "nvidia,tegra20-gic";
+                compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
-                #interrupt-cells = <1>;
+                #interrupt-cells = <3>;
                 reg = < 0x50041000 0x1000 >,
                       < 0x50040100 0x0100 >;
         };
@@ -17,7 +17,7 @@
                 #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000C000 0x100>;
-                interrupts = < 70 >;
+                interrupts = < 0 38 0x04 >;
         };
 
         i2c@7000c400 {
@@ -25,7 +25,7 @@
                 #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000C400 0x100>;
-                interrupts = < 116 >;
+                interrupts = < 0 84 0x04 >;
         };
 
         i2c@7000c500 {
@@ -33,7 +33,7 @@
                 #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000C500 0x100>;
-                interrupts = < 124 >;
+                interrupts = < 0 92 0x04 >;
         };
 
         i2c@7000d000 {
@@ -41,30 +41,24 @@
                 #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000D000 0x200>;
-                interrupts = < 85 >;
+                interrupts = < 0 53 0x04 >;
         };
 
         i2s@70002800 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
-                interrupts = < 45 >;
+                interrupts = < 0 13 0x04 >;
                 dma-channel = < 2 >;
         };
 
         i2s@70002a00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
-                interrupts = < 35 >;
+                interrupts = < 0 3 0x04 >;
                 dma-channel = < 1 >;
         };
 
         das@70000c00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                 compatible = "nvidia,tegra20-das";
                 reg = <0x70000c00 0x80>;
         };
@@ -72,7 +66,13 @@
         gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra20-gpio";
                 reg = < 0x6000d000 0x1000 >;
-                interrupts = < 64 65 66 67 87 119 121 >;
+                interrupts = < 0 32 0x04
+                               0 33 0x04
+                               0 34 0x04
+                               0 35 0x04
+                               0 55 0x04
+                               0 87 0x04
+                               0 89 0x04 >;
                 #gpio-cells = <2>;
                 gpio-controller;
         };
@@ -89,59 +89,80 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = < 68 >;
+                interrupts = < 0 36 0x04 >;
         };
 
         serial@70006040 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = < 69 >;
+                interrupts = < 0 37 0x04 >;
         };
 
         serial@70006200 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = < 78 >;
+                interrupts = < 0 46 0x04 >;
         };
 
         serial@70006300 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = < 122 >;
+                interrupts = < 0 90 0x04 >;
         };
 
         serial@70006400 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
-                interrupts = < 123 >;
+                interrupts = < 0 91 0x04 >;
         };
 
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
-                interrupts = < 46 >;
+                interrupts = < 0 14 0x04 >;
         };
 
         sdhci@c8000200 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000200 0x200>;
-                interrupts = < 47 >;
+                interrupts = < 0 15 0x04 >;
         };
 
         sdhci@c8000400 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000400 0x200>;
-                interrupts = < 51 >;
+                interrupts = < 0 19 0x04 >;
         };
 
         sdhci@c8000600 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000600 0x200>;
-                interrupts = < 63 >;
+                interrupts = < 0 31 0x04 >;
+        };
+
+        usb@c5000000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5000000 0x4000>;
+                interrupts = < 0 20 0x04 >;
+                phy_type = "utmi";
+        };
+
+        usb@c5004000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5004000 0x4000>;
+                interrupts = < 0 21 0x04 >;
+                phy_type = "ulpi";
+        };
+
+        usb@c5008000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5008000 0x4000>;
+                interrupts = < 0 97 0x04 >;
+                phy_type = "utmi";
         };
 };
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
new file mode 100644
index 00000000000..ee7db9892e0
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -0,0 +1,127 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "nvidia,tegra30";
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller@50041000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x50041000 0x1000 >,
+                      < 0x50040100 0x0100 >;
+        };
+
+        i2c@7000c000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C000 0x100>;
+                interrupts = < 0 38 0x04 >;
+        };
+
+        i2c@7000c400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C400 0x100>;
+                interrupts = < 0 84 0x04 >;
+        };
+
+        i2c@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C500 0x100>;
+                interrupts = < 0 92 0x04 >;
+        };
+
+        i2c@7000c700 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000c700 0x100>;
+                interrupts = < 0 120 0x04 >;
+        };
+
+        i2c@7000d000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000D000 0x100>;
+                interrupts = < 0 53 0x04 >;
+        };
+
+        gpio: gpio@6000d000 {
+                compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+                reg = < 0x6000d000 0x1000 >;
+                interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
+                #gpio-cells = <2>;
+                gpio-controller;
+        };
+
+        serial@70006000 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006000 0x40>;
+                reg-shift = <2>;
+                interrupts = < 0 36 0x04 >;
+        };
+
+        serial@70006040 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006040 0x40>;
+                reg-shift = <2>;
+                interrupts = < 0 37 0x04 >;
+        };
+
+        serial@70006200 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006200 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 46 0x04 >;
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006300 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 90 0x04 >;
+        };
+
+        serial@70006400 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006400 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 91 0x04 >;
+        };
+
+        sdhci@78000000 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000000 0x200>;
+                interrupts = < 0 14 0x04 >;
+        };
+
+        sdhci@78000200 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000200 0x200>;
+                interrupts = < 0 15 0x04 >;
+        };
+
+        sdhci@78000400 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000400 0x200>;
+                interrupts = < 0 19 0x04 >;
+        };
+
+        sdhci@78000600 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000600 0x200>;
+                interrupts = < 0 31 0x04 >;
+        };
+
+        pinmux: pinmux@70000000 {
+                compatible = "nvidia,tegra30-pinmux";
+                reg = < 0x70000868 0xd0     /* Pad control registers */
+                        0x70003000 0x3e0 >; /* Mux registers */
+        };
+};
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index cf497ce41df..a22e9307906 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -68,7 +68,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 195729760ae..fd5d3041d71 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_2x_SOC=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_MACH_HARMONY=y
 CONFIG_MACH_KAEN=y
 CONFIG_MACH_PAZ00=y
@@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_R8169=y
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 35a218cb5c7..9d8598f29fd 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -98,6 +98,7 @@ config MACH_SCB9328
 config MACH_APF9328
         bool "APF9328"
         select SOC_IMX1
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         help
           Say Yes here if you are using the Armadeus APF9328 development board
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index cfede5768aa..5f4d06af491 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -25,3 +25,6 @@ initrd_phys-$(CONFIG_SOC_IMX35)	:= 0x80800000
 zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
+
+dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
+                           imx6q-sabrelite.dtb
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 146a4f07346..f4a63ee9e21 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/dm9000.h>
+#include <linux/i2c.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +42,9 @@ static const int apf9328_pins[] __initconst = {
         PB29_PF_UART2_RTS,
         PB30_PF_UART2_TXD,
         PB31_PF_UART2_RXD,
+        /* I2C */
+        PA15_PF_I2C_SDA,
+        PA16_PF_I2C_SCL,
 };
 
 /*
@@ -103,6 +107,10 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static const struct imxi2c_platform_data apf9328_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 static struct platform_device *devices[] __initdata = {
         &apf9328_flash_device,
         &dm9000x_device,
@@ -119,6 +127,8 @@ static void __init apf9328_init(void)
         imx1_add_imx_uart0(NULL);
         imx1_add_imx_uart1(&uart1_pdata);
 
+        imx1_add_imx_i2c(&apf9328_i2c_data);
+
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 05b49bb5d67..c2572810691 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -19,6 +19,8 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/micrel_phy.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
@@ -56,8 +58,27 @@ soft:
         soft_restart(0);
 }
 
+/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
+static int ksz9021rn_phy_fixup(struct phy_device *phydev)
+{
+        /* min rx data delay */
+        phy_write(phydev, 0x0b, 0x8105);
+        phy_write(phydev, 0x0c, 0x0000);
+
+        /* max rx/tx clock delay, min rx/tx control delay */
+        phy_write(phydev, 0x0b, 0x8104);
+        phy_write(phydev, 0x0c, 0xf0f0);
+        phy_write(phydev, 0x0b, 0x104);
+
+        return 0;
+}
+
 static void __init imx6q_init_machine(void)
 {
+        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                                           ksz9021rn_phy_fixup);
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         imx6q_pm_init();
@@ -105,7 +126,8 @@ static struct sys_timer imx6q_timer = {
 };
 
 static const char *imx6q_dt_compat[] __initdata = {
-        "fsl,imx6q-sabreauto",
+        "fsl,imx6q-arm2",
+        "fsl,imx6q-sabrelite",
         NULL,
 };
 
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 2b565c38134..89c33258639 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -492,7 +492,7 @@ static struct mc13xxx_platform_data mc13783_pdata = {
                 .regulators = mx31_3ds_regulators,
                 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
         },
-        .flags  = MC13XXX_USE_TOUCHSCREEN,
+        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
 };
 
 /* SPI */
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4f01533083c..b7407154c88 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -78,8 +78,13 @@ config SOC_OMAP3430
         default y
         select ARCH_OMAP_OTG
 
-config SOC_OMAPTI816X
-        bool "TI816X support"
+config SOC_OMAPTI81XX
+        bool "TI81XX support"
+        depends on ARCH_OMAP3
+        default y
+
+config SOC_OMAPAM33XX
+        bool "AM33XX support"
         depends on ARCH_OMAP3
         default y
 
@@ -316,7 +321,12 @@ config MACH_OMAP_3630SDP
 
 config MACH_TI8168EVM
         bool "TI8168 Evaluation Module"
-        depends on SOC_OMAPTI816X
+        depends on SOC_OMAPTI81XX
+        default y
+
+config MACH_TI8148EVM
+        bool "TI8148 Evaluation Module"
+        depends on SOC_OMAPTI81XX
         default y
 
 config MACH_OMAP_4430SDP
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b009f17dee5..6d226a76d05 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -232,6 +232,7 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
 
 obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
 obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
+obj-$(CONFIG_MACH_TI8148EVM)            += board-ti8168evm.o
 
 # Platform specific device init code
 
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index bad5d5a5ef7..5598e00ccf5 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -372,11 +372,17 @@ static struct platform_device sdp4430_vbat = {
         },
 };
 
+static struct platform_device sdp4430_dmic_codec = {
+        .name   = "dmic-codec",
+        .id     = -1,
+};
+
 static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
         &sdp4430_leds_pwm,
         &sdp4430_vbat,
+        &sdp4430_dmic_codec,
 };
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 1545102d1f9..e921e3be24a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -53,7 +53,8 @@
 #include "hsmmc.h"
 #include "common-board-devices.h"
 
-#define CM_T35_GPIO_PENDOWN     57
+#define CM_T35_GPIO_PENDOWN             57
+#define SB_T35_USB_HUB_RESET_GPIO       167
 
 #define CM_T35_SMSC911X_CS      5
 #define CM_T35_SMSC911X_GPIO    163
@@ -339,8 +340,10 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
         REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
 
-static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
-        REGULATOR_SUPPLY("vdvi", "omapdss"),
+static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -373,6 +376,19 @@ static struct regulator_init_data cm_t35_vsim = {
         .consumer_supplies      = cm_t35_vsim_supply,
 };
 
+static struct regulator_init_data cm_t35_vio = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(cm_t35_vio_supplies),
+        .consumer_supplies      = cm_t35_vio_supplies,
+};
+
 static uint32_t cm_t35_keymap[] = {
         KEY(0, 0, KEY_A),       KEY(0, 1, KEY_B),       KEY(0, 2, KEY_LEFT),
         KEY(1, 0, KEY_UP),      KEY(1, 1, KEY_ENTER),   KEY(1, 2, KEY_DOWN),
@@ -421,6 +437,23 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+static void cm_t35_init_usbh(void)
+{
+        int err;
+
+        err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
+                               GPIOF_OUT_INIT_LOW, "usb hub rst");
+        if (err) {
+                pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
+        } else {
+                udelay(10);
+                gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
+                msleep(1);
+        }
+
+        usbhs_init(&usbhs_bdata);
+}
+
 static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
                                  unsigned ngpio)
 {
@@ -456,17 +489,14 @@ static struct twl4030_platform_data cm_t35_twldata = {
         .gpio           = &cm_t35_gpio_data,
         .vmmc1          = &cm_t35_vmmc1,
         .vsim           = &cm_t35_vsim,
+        .vio            = &cm_t35_vio,
 };
 
 static void __init cm_t35_init_i2c(void)
 {
         omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
-                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
-
-        cm_t35_twldata.vpll2->constraints.name = "VDVI";
-        cm_t35_twldata.vpll2->num_consumer_supplies =
-                                                ARRAY_SIZE(cm_t35_vdvi_supply);
-        cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
+                              TWL_COMMON_REGULATOR_VDAC |
+                              TWL_COMMON_PDATA_AUDIO);
 
         omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
@@ -570,24 +600,28 @@ static void __init cm_t3x_common_dss_mux_init(int mux_mode)
 
 static void __init cm_t35_init_mux(void)
 {
-        omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
+
+        omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
+        omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
+        omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
+        omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
+        omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
+        omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
+        cm_t3x_common_dss_mux_init(mux_mode);
 }
 
 static void __init cm_t3730_init_mux(void)
 {
-        omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
+
+        omap_mux_init_signal("sys_boot0", mux_mode);
+        omap_mux_init_signal("sys_boot1", mux_mode);
+        omap_mux_init_signal("sys_boot3", mux_mode);
+        omap_mux_init_signal("sys_boot4", mux_mode);
+        omap_mux_init_signal("sys_boot5", mux_mode);
+        omap_mux_init_signal("sys_boot6", mux_mode);
+        cm_t3x_common_dss_mux_init(mux_mode);
 }
 #else
 static inline void cm_t35_init_mux(void) {}
@@ -612,7 +646,7 @@ static void __init cm_t3x_common_init(void)
         cm_t35_init_display();
 
         usb_musb_init(NULL);
-        usbhs_init(&usbhs_bdata);
+        cm_t35_init_usbh();
 }
 
 static void __init cm_t35_init(void)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 108fee6146f..d67bcdf724d 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -15,6 +15,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/wl12xx.h>
+#include <linux/spi/tsc2005.h>
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/clk.h>
@@ -58,6 +59,9 @@
 
 #define RX51_USB_TRANSCEIVER_RST_GPIO   67
 
+#define RX51_TSC2005_RESET_GPIO         104
+#define RX51_TSC2005_IRQ_GPIO           100
+
 /* list all spi devices here */
 enum {
         RX51_SPI_WL1251,
@@ -66,6 +70,7 @@ enum {
 };
 
 static struct wl12xx_platform_data wl1251_pdata;
+static struct tsc2005_platform_data tsc2005_pdata;
 
 #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
 static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
@@ -167,10 +172,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
                 .modalias               = "tsc2005",
                 .bus_num                = 1,
                 .chip_select            = 0,
-                /* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/
+                .irq                    = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
                 .max_speed_hz           = 6000000,
                 .controller_data        = &tsc2005_mcspi_config,
-                /* .platform_data = &tsc2005_config,*/
+                .platform_data          = &tsc2005_pdata,
         },
 };
 
@@ -1086,6 +1091,42 @@ error:
          */
 }
 
+static struct tsc2005_platform_data tsc2005_pdata = {
+        .ts_pressure_max        = 2048,
+        .ts_pressure_fudge      = 2,
+        .ts_x_max               = 4096,
+        .ts_x_fudge             = 4,
+        .ts_y_max               = 4096,
+        .ts_y_fudge             = 7,
+        .ts_x_plate_ohm         = 280,
+        .esd_timeout_ms         = 8000,
+};
+
+static void rx51_tsc2005_set_reset(bool enable)
+{
+        gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
+}
+
+static void __init rx51_init_tsc2005(void)
+{
+        int r;
+
+        r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
+        if (r < 0) {
+                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
+                rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
+        }
+
+        r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
+                "tsc2005 reset");
+        if (r >= 0) {
+                tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+        } else {
+                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
+                tsc2005_pdata.esd_timeout_ms = 0;
+        }
+}
+
 void __init rx51_peripherals_init(void)
 {
         rx51_i2c_init();
@@ -1094,6 +1135,7 @@ void __init rx51_peripherals_init(void)
         board_smc91x_init();
         rx51_add_gpio_keys();
         rx51_init_wl1251();
+        rx51_init_tsc2005();
         rx51_init_si4713();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 74713e3993e..ab9a7a9e9d6 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -1,5 +1,5 @@
 /*
- * Code for TI8168 EVM.
+ * Code for TI8168/TI8148 EVM.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
  *
@@ -23,30 +23,45 @@
 #include <plat/irqs.h>
 #include <plat/board.h>
 #include "common.h"
+#include <plat/usb.h>
 
-static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+static struct omap_musb_board_data musb_board_data = {
+        .set_phy_power  = ti81xx_musb_phy_power,
+        .interface_type = MUSB_INTERFACE_ULPI,
+        .mode           = MUSB_OTG,
+        .power          = 500,
 };
 
-static void __init ti8168_evm_init(void)
+static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
+};
+
+static void __init ti81xx_evm_init(void)
 {
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
-        omap_board_config = ti8168_evm_config;
-        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
-}
-
-static void __init ti8168_evm_map_io(void)
-{
-        omapti816x_map_common_io();
+        omap_board_config = ti81xx_evm_config;
+        omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
+        usb_musb_init(&musb_board_data);
 }
 
 MACHINE_START(TI8168EVM, "ti8168evm")
         /* Maintainer: Texas Instruments */
         .atag_offset    = 0x100,
-        .map_io         = ti8168_evm_map_io,
-        .init_early     = ti816x_init_early,
-        .init_irq       = ti816x_init_irq,
+        .map_io         = ti81xx_map_io,
+        .init_early     = ti81xx_init_early,
+        .init_irq       = ti81xx_init_irq,
+        .timer          = &omap3_timer,
+        .init_machine   = ti81xx_evm_init,
+        .restart        = omap_prcm_restart,
+MACHINE_END
+
+MACHINE_START(TI8148EVM, "ti8148evm")
+        /* Maintainer: Texas Instruments */
+        .atag_offset    = 0x100,
+        .map_io         = ti81xx_map_io,
+        .init_early     = ti81xx_init_early,
+        .init_irq       = ti81xx_init_irq,
         .timer          = &omap3_timer,
-        .init_machine   = ti8168_evm_init,
+        .init_machine   = ti81xx_evm_init,
         .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1f3481f8d69..f57ed5baecc 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,7 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-u8 cpu_mask;
+u16 cpu_mask;
 
 /*
  * clkdm_control: if true, then when a clock is enabled in the
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2311bc21722..b8c2a686481 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -132,7 +132,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                                const char *core_ck_name,
                                const char *mpu_ck_name);
 
-extern u8 cpu_mask;
+extern u16 cpu_mask;
 
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_dummy;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 5d0064a4fb5..60424f41156 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3517,6 +3517,10 @@ int __init omap3xxx_clk_init(void)
         } else if (cpu_is_ti816x()) {
                 cpu_mask = RATE_IN_TI816X;
                 cpu_clkflg = CK_TI816X;
+        } else if (cpu_is_am33xx()) {
+                cpu_mask = RATE_IN_AM33XX;
+        } else if (cpu_is_ti814x()) {
+                cpu_mask = RATE_IN_TI814X;
         } else if (cpu_is_omap34xx()) {
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
                         cpu_mask = RATE_IN_3430ES1;
@@ -3600,7 +3604,7 @@ int __init omap3xxx_clk_init(void)
          * Lock DPLL5 -- here only until other device init code can
          * handle this
          */
-        if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+        if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
                 omap3_clk_lock_dpll5();
 
         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 684b8a7cd40..aaf421178c9 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -110,23 +110,49 @@ void __init omap3_map_io(void)
 
 /*
  * Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI816X register for checking device ID (it adds 0x204 to tap base while
- * TI816X DEVICE ID register is at offset 0x600 from control base).
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
  */
-#define TI816X_TAP_BASE         (TI816X_CTRL_BASE + \
-                                TI816X_CONTROL_DEVICE_ID - 0x204)
+#define TI81XX_TAP_BASE         (TI81XX_CTRL_BASE + \
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
 
-static struct omap_globals ti816x_globals = {
+static struct omap_globals ti81xx_globals = {
         .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
 };
 
-void __init omap2_set_globals_ti816x(void)
+void __init omap2_set_globals_ti81xx(void)
 {
-        __omap2_set_globals(&ti816x_globals);
+        __omap2_set_globals(&ti81xx_globals);
+}
+
+void __init ti81xx_map_io(void)
+{
+        omapti81xx_map_common_io();
+}
+
+#define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + \
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals am33xx_globals = {
+        .class  = AM335X_CLASS,
+        .tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+        .ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        .prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+        .cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+};
+
+void __init omap2_set_globals_am33xx(void)
+{
+        __omap2_set_globals(&am33xx_globals);
+}
+
+void __init am33xx_map_io(void)
+{
+        omapam33xx_map_common_io();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index cda888a2e63..9403b2ce6c8 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -52,10 +52,18 @@ static inline void omap34xx_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI816X
-extern void omapti816x_map_common_io(void);
+#ifdef CONFIG_SOC_OMAPTI81XX
+extern void omapti81xx_map_common_io(void);
 #else
-static inline void omapti816x_map_common_io(void)
+static inline void omapti81xx_map_common_io(void)
+{
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
 {
 }
 #endif
@@ -82,7 +90,7 @@ void omap35xx_init_early(void);
 void omap3630_init_early(void);
 void omap3_init_early(void);    /* Do not use this one */
 void am35xx_init_early(void);
-void ti816x_init_early(void);
+void ti81xx_init_early(void);
 void omap4430_init_early(void);
 void omap_prcm_restart(char, const char *);
 
@@ -107,7 +115,8 @@ void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
-void omap2_set_globals_ti816x(void);
+void omap2_set_globals_ti81xx(void);
+void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
@@ -118,7 +127,9 @@ void omap2_set_globals_prcm(struct omap_globals *);
 void omap242x_map_io(void);
 void omap243x_map_io(void);
 void omap3_map_io(void);
+void am33xx_map_io(void);
 void omap4_map_io(void);
+void ti81xx_map_io(void);
 
 /**
  * omap_test_timeout - busy-loop, testing a condition
@@ -147,7 +158,7 @@ extern struct device *omap4_get_dsp_device(void);
 
 void omap2_init_irq(void);
 void omap3_init_irq(void);
-void ti816x_init_irq(void);
+void ti81xx_init_irq(void);
 extern int omap_irq_pending(void);
 void omap_intc_save_context(void);
 void omap_intc_restore_context(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d5a38..0ba68d3764b 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,8 +52,8 @@
 #define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
 #define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
 
-/* TI816X spefic control submodules */
-#define TI816X_CONTROL_DEVCONF          0x600
+/* TI81XX spefic control submodules */
+#define TI81XX_CONTROL_DEVCONF          0x600
 
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
 
@@ -244,8 +244,8 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
-/* TI816X CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID        (TI816X_CONTROL_DEVCONF + 0x000)
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_DEVICE_ID        (TI81XX_CONTROL_DEVCONF + 0x000)
 
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c15cfada5f1..35d5dffab7e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -336,6 +336,27 @@ static void omap_init_mcpdm(void)
 static inline void omap_init_mcpdm(void) {}
 #endif
 
+#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
+                defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
+
+static void omap_init_dmic(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("dmic");
+        if (!oh) {
+                printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+                return;
+        }
+
+        pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
+}
+#else
+static inline void omap_init_dmic(void) {}
+#endif
+
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
 #include <plat/mcspi.h>
@@ -681,6 +702,7 @@ static int __init omap2_init_devices(void)
          */
         omap_init_audio();
         omap_init_mcpdm();
+        omap_init_dmic();
         omap_init_camera();
         omap_init_mbox();
         omap_init_mcspi();
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 27ad722df63..6c5826605ea 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -226,7 +226,7 @@ static void __init omap4_check_features(void)
         }
 }
 
-static void __init ti816x_check_features(void)
+static void __init ti81xx_check_features(void)
 {
         omap_features = OMAP3_HAS_NEON;
 }
@@ -340,6 +340,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
                         break;
                 }
                 break;
+        case 0xb944:
+                omap_revision = AM335X_REV_ES1_0;
+                *cpu_rev = "1.0";
+        case 0xb8f2:
+                switch (rev) {
+                case 0:
+                /* FALLTHROUGH */
+                case 1:
+                        omap_revision = TI8148_REV_ES1_0;
+                        *cpu_rev = "1.0";
+                        break;
+                case 2:
+                        omap_revision = TI8148_REV_ES2_0;
+                        *cpu_rev = "2.0";
+                        break;
+                case 3:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = TI8148_REV_ES2_1;
+                        *cpu_rev = "2.1";
+                        break;
+                }
+                break;
         default:
                 /* Unknown default to latest silicon rev as default */
                 omap_revision = OMAP3630_REV_ES1_2;
@@ -367,7 +390,7 @@ static void __init omap4_check_revision(void)
          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
          * Use ARM register to detect the correct ES version
          */
-        if (!rev && (hawkeye != 0xb94e)) {
+        if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
                 idcode = read_cpuid(CPUID_ID);
                 rev = (idcode & 0xf) - 1;
         }
@@ -389,8 +412,11 @@ static void __init omap4_check_revision(void)
                         omap_revision = OMAP4430_REV_ES2_1;
                         break;
                 case 4:
-                default:
                         omap_revision = OMAP4430_REV_ES2_2;
+                        break;
+                case 6:
+                default:
+                        omap_revision = OMAP4430_REV_ES2_3;
                 }
                 break;
         case 0xb94e:
@@ -401,9 +427,17 @@ static void __init omap4_check_revision(void)
                         break;
                 }
                 break;
+        case 0xb975:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP4470_REV_ES1_0;
+                        break;
+                }
+                break;
         default:
                 /* Unknown default to latest silicon rev as default */
-                omap_revision = OMAP4430_REV_ES2_2;
+                omap_revision = OMAP4430_REV_ES2_3;
         }
 
         pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -432,6 +466,10 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
         } else if (cpu_is_ti816x()) {
                 cpu_name = "TI816X";
+        } else if (cpu_is_am335x()) {
+                cpu_name =  "AM335X";
+        } else if (cpu_is_ti814x()) {
+                cpu_name = "TI814X";
         } else if (omap3_has_iva() && omap3_has_sgx()) {
                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                 cpu_name = "OMAP3430/3530";
@@ -472,11 +510,11 @@ void __init omap2_check_revision(void)
         } else if (cpu_is_omap34xx()) {
                 omap3_check_revision(&cpu_rev);
 
-                /* TI816X doesn't have feature register */
-                if (!cpu_is_ti816x())
+                /* TI81XX doesn't have feature register */
+                if (!cpu_is_ti81xx())
                         omap3_check_features();
                 else
-                        ti816x_check_features();
+                        ti81xx_check_features();
 
                 omap3_cpuinfo(cpu_rev);
                 return;
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 13f98e59cfe..cdfc2a1f0e7 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -66,11 +66,11 @@ omap_uart_lsr:	.word	0
                 beq     34f                     @ configure OMAP3UART4
                 cmp     \rp, #OMAP4UART4        @ only on 44xx
                 beq     44f                     @ configure OMAP4UART4
-                cmp     \rp, #TI816XUART1       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
                 beq     81f                     @ configure UART1
-                cmp     \rp, #TI816XUART2       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
                 beq     82f                     @ configure UART2
-                cmp     \rp, #TI816XUART3       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
                 beq     83f                     @ configure UART3
                 cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                 beq     95f                     @ configure ZOOM_UART
@@ -94,11 +94,11 @@ omap_uart_lsr:	.word	0
                 b       98f
 44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                 b       98f
-81:             mov     \rp, #UART_OFFSET(TI816X_UART1_BASE)
+81:             mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
                 b       98f
-82:             mov     \rp, #UART_OFFSET(TI816X_UART2_BASE)
+82:             mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
                 b       98f
-83:             mov     \rp, #UART_OFFSET(TI816X_UART3_BASE)
+83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                 b       98f
 
 95:             ldr     \rp, =ZOOM_UART_BASE
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3f565dd2ea8..73d617f0dc4 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -176,14 +176,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI816X
-static struct map_desc omapti816x_io_desc[] __initdata = {
+#ifdef CONFIG_SOC_OMAPTI81XX
+static struct map_desc omapti81xx_io_desc[] __initdata = {
+        {
+                .virtual        = L4_34XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
+                .length         = L4_34XX_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
         {
                 .virtual        = L4_34XX_VIRT,
                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
                 .length         = L4_34XX_SIZE,
                 .type           = MT_DEVICE
         },
+        {
+                .virtual        = L4_WK_AM33XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
+                .length         = L4_WK_AM33XX_SIZE,
+                .type           = MT_DEVICE
+        }
 };
 #endif
 
@@ -263,10 +280,17 @@ void __init omap34xx_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI816X
-void __init omapti816x_map_common_io(void)
+#ifdef CONFIG_SOC_OMAPTI81XX
+void __init omapti81xx_map_common_io(void)
+{
+        iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
+}
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
 {
-        iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+        iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 }
 #endif
 
@@ -418,9 +442,9 @@ void __init am35xx_init_early(void)
         omap3_init_early();
 }
 
-void __init ti816x_init_early(void)
+void __init ti81xx_init_early(void)
 {
-        omap2_set_globals_ti816x();
+        omap2_set_globals_ti81xx();
         omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 42b1d659191..1fef061f792 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -193,7 +193,7 @@ void __init omap3_init_irq(void)
         omap_init_irq(OMAP34XX_IC_BASE, 96);
 }
 
-void __init ti816x_init_irq(void)
+void __init ti81xx_init_irq(void)
 {
         omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 58775e3c847..4c90477e6f8 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -260,3 +260,38 @@ void am35x_set_mode(u8 musb_mode)
 
         omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 }
+
+void ti81xx_musb_phy_power(u8 on)
+{
+        void __iomem *scm_base = NULL;
+        u32 usbphycfg;
+
+        scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
+        if (!scm_base) {
+                pr_err("system control module ioremap failed\n");
+                return;
+        }
+
+        usbphycfg = __raw_readl(scm_base + USBCTRL0);
+
+        if (on) {
+                if (cpu_is_ti816x()) {
+                        usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
+                        usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
+                } else if (cpu_is_ti814x()) {
+                        usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
+                                | USBPHY_DPINPUT | USBPHY_DMINPUT);
+                        usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
+                                | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
+                }
+        } else {
+                if (cpu_is_ti816x())
+                        usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
+                else if (cpu_is_ti814x())
+                        usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
+
+        }
+        __raw_writel(usbphycfg, scm_base + USBCTRL0);
+
+        iounmap(scm_base);
+}
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 8affc66a92c..8fae534eb15 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -51,7 +51,7 @@ struct prcm_config {
         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
+        unsigned short flags;
 };
 
 
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index ee3a8ad304c..7479d7ea137 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -1,7 +1,7 @@
 /*
  * SDRC register values for Nokia boards
  *
- * Copyright (C) 2008, 2010 Nokia Corporation
+ * Copyright (C) 2008, 2010-2011 Nokia Corporation
  *
  * Lauri Leukkunen <lauri.leukkunen@nokia.com>
  *
@@ -107,14 +107,37 @@ static const struct sdram_timings nokia_195dot2mhz_timings[] = {
         },
 };
 
+static const struct sdram_timings nokia_200mhz_timings[] = {
+        {
+                .casl = 3,
+                .tDAL = 30000,
+                .tDPL = 15000,
+                .tRRD = 10000,
+                .tRCD = 20000,
+                .tRP = 15000,
+                .tRAS = 40000,
+                .tRC = 55000,
+                .tRFC = 140000,
+                .tXSR = 200000,
+
+                .tREF = 7800,
+
+                .tXP = 2,
+                .tCKE = 4,
+                .tWTR = 2
+        },
+};
+
 static const struct {
         long rate;
         struct sdram_timings const *data;
 } nokia_timings[] = {
         { 83000000, nokia_166mhz_timings },
         { 97600000, nokia_97dot6mhz_timings },
+        { 100000000, nokia_200mhz_timings },
         { 166000000, nokia_166mhz_timings },
         { 195200000, nokia_195dot2mhz_timings },
+        { 200000000, nokia_200mhz_timings },
 };
 static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
 
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 42c326732a2..d0f009cbfb5 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -464,7 +464,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 mod_timer(&uart->timer, jiffies + uart->timeout);
         omap_uart_smart_idle_enable(uart, 0);
 
-        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+        if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) {
                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
                 u32 wk_mask = 0;
                 u32 padconf = 0;
@@ -746,7 +746,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
          */
         uart->regshift = p->regshift;
         uart->membase = p->membase;
-        if (cpu_is_omap44xx() || cpu_is_ti816x())
+        if (cpu_is_omap44xx() || cpu_is_ti81xx())
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
@@ -828,7 +828,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
         }
 
         /* Enable the MDR1 errata for OMAP3 */
-        if (cpu_is_omap34xx() && !cpu_is_ti816x())
+        if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx()))
                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 267975086a7..8d5ed775dd5 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -93,6 +93,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
         if (cpu_is_omap3517() || cpu_is_omap3505()) {
                 oh_name = "am35x_otg_hs";
                 name = "musb-am35x";
+        } else if (cpu_is_ti81xx()) {
+                oh_name = "usb_otg_hs";
+                name = "musb-ti81xx";
         } else {
                 oh_name = "usb_otg_hs";
                 name = "musb-omap2430";
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 924a3b5f8da..dce71b4a3a5 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -53,6 +53,7 @@
 #include <mach/pxa27x-udc.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
+#include <mach/smemc.h>
 #include <media/soc_camera.h>
 
 #include <mach/mioa701.h>
@@ -390,24 +391,19 @@ static struct pxamci_platform_data mioa701_mci_info = {
 };
 
 /* FlashRAM */
-static struct resource strataflash_resource = {
+static struct resource docg3_resource = {
         .start = PXA_CS0_PHYS,
-        .end   = PXA_CS0_PHYS + SZ_64M - 1,
+        .end   = PXA_CS0_PHYS + SZ_8K - 1,
         .flags = IORESOURCE_MEM,
 };
 
-static struct physmap_flash_data strataflash_data = {
-        .width = 2,
-        /* .set_vpp = mioa701_set_vpp, */
-};
-
-static struct platform_device strataflash = {
-        .name          = "physmap-flash",
+static struct platform_device docg3 = {
+        .name          = "docg3",
         .id            = -1,
-        .resource      = &strataflash_resource,
+        .resource      = &docg3_resource,
         .num_resources = 1,
         .dev = {
-                .platform_data = &strataflash_data,
+                .platform_data = NULL,
         },
 };
 
@@ -685,7 +681,7 @@ static struct platform_device *devices[] __initdata = {
         &pxa2xx_pcm,
         &mioa701_sound,
         &power_dev,
-        &strataflash,
+        &docg3,
         &gpio_vbus,
         &mioa701_camera,
         &mioa701_board,
@@ -720,6 +716,15 @@ static void __init mioa701_machine_init(void)
         RTTR = 32768 - 1; /* Reset crazy WinCE value */
         UP2OCR = UP2OCR_HXOE;
 
+        /*
+         * Set up the flash memory : DiskOnChip G3 on first static memory bank
+         */
+        __raw_writel(0x7ff02dd8, MSC0);
+        __raw_writel(0x0001c391, MCMEM0);
+        __raw_writel(0x0001c391, MCATT0);
+        __raw_writel(0x0001c391, MCIO0);
+
+
         pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 437322ffd88..adbbb85bc4c 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -169,6 +169,24 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
                                    S3C2410_LCDCON5_HWSWP),
         },
+        /* mini2440 + 3.5" TFT (LCD-W35i, LQ035Q1DG06 type) + touchscreen*/
+        [3] = {
+                _LCD_DECLARE(
+                        /* clock */
+                        7,
+                        /* xres, margin_right, margin_left, hsync */
+                        320, 68, 66, 4,
+                        /* yres, margin_top, margin_bottom, vsync */
+                        240, 4, 4, 9,
+                        /* refresh rate */
+                        60),
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVDEN |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVCLK |
+                                   S3C2410_LCDCON5_HWSWP),
+        },
 };
 
 /* todo - put into gpio header */
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 90b34ab75b5..e9dae9105df 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -193,7 +193,7 @@ config SMDK6410_WM1190_EV1
         depends on MACH_SMDK6410
         select REGULATOR
         select REGULATOR_WM8350
-        select S3C24XX_GPIO_EXTRA64
+        select SAMSUNG_GPIO_EXTRA64
         select MFD_WM8350_I2C
         select MFD_WM8350_CONFIG_MODE_0
         select MFD_WM8350_CONFIG_MODE_3
@@ -211,7 +211,7 @@ config SMDK6410_WM1192_EV1
         depends on MACH_SMDK6410
         select REGULATOR
         select REGULATOR_WM831X
-        select S3C24XX_GPIO_EXTRA64
+        select SAMSUNG_GPIO_EXTRA64
         select MFD_WM831X
         select MFD_WM831X_I2C
         help
@@ -293,7 +293,7 @@ config MACH_WLF_CRAGG_6410
         select S3C_DEV_WDT
         select S3C_DEV_RTC
         select S3C64XX_DEV_SPI0
-        select S3C24XX_GPIO_EXTRA128
+        select SAMSUNG_GPIO_EXTRA128
         select I2C
         help
           Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
index be9074e17df..5d55ab018b6 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -15,9 +15,11 @@
 
 #define BANFF_PMIC_IRQ_BASE             IRQ_BOARD_START
 #define GLENFARCLAS_PMIC_IRQ_BASE       (IRQ_BOARD_START + 64)
+#define CODEC_IRQ_BASE                  (IRQ_BOARD_START + 128)
 
 #define PCA935X_GPIO_BASE               GPIO_BOARD_START
-#define CODEC_GPIO_BASE         (GPIO_BOARD_START + 8)
-#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 16)
+#define CODEC_GPIO_BASE                 (GPIO_BOARD_START + 8)
+#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 32)
+#define BANFF_PMIC_GPIO_BASE            (GPIO_BOARD_START + 64)
 
 #endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h
index 6e34c2f6e67..8b540c42d5d 100644
--- a/arch/arm/mach-s3c64xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h
@@ -88,6 +88,6 @@ enum s3c_gpio_number {
 /* define the number of gpios we need to the one after the GPQ() range */
 #define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
 
-#define BOARD_NR_GPIOS 16
+#define BOARD_NR_GPIOS  (16 + CONFIG_SAMSUNG_GPIO_EXTRA)
 
 #define ARCH_NR_GPIOS   (GPIO_BOARD_START + BOARD_NR_GPIOS)
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 443f85b3c20..96d60e0d937 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -169,7 +169,7 @@
 #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
 
 #ifdef CONFIG_MACH_WLF_CRAGG_6410
-#define IRQ_BOARD_NR 128
+#define IRQ_BOARD_NR 160
 #elif defined(CONFIG_SMDK6410_WM1190_EV1)
 #define IRQ_BOARD_NR 64
 #elif defined(CONFIG_SMDK6410_WM1192_EV1)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index f208154b138..cd3c97e2ee7 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -14,13 +14,43 @@
 
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
+#include <linux/mfd/wm8994/pdata.h>
 
+#include <sound/wm5100.h>
 #include <sound/wm8996.h>
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
 
 #include <mach/crag6410.h>
 
+static struct wm5100_pdata wm5100_pdata = {
+        .ldo_ena = S3C64XX_GPN(7),
+        .irq_flags = IRQF_TRIGGER_HIGH,
+        .gpio_base = CODEC_GPIO_BASE,
+
+        .in_mode = {
+                WM5100_IN_DIFF,
+                WM5100_IN_DIFF,
+                WM5100_IN_DIFF,
+                WM5100_IN_SE,
+        },
+
+        .hp_pol = CODEC_GPIO_BASE + 3,
+        .jack_modes = {
+                { WM5100_MICDET_MICBIAS3, 0, 0 },
+                { WM5100_MICDET_MICBIAS2, 1, 1 },
+        },
+
+        .gpio_defaults = {
+                0,
+                0,
+                0,
+                0,
+                0x2, /* IRQ: CMOS output */
+                0x3, /* CLKOUT: CMOS output */
+        },
+};
+
 static struct wm8996_retune_mobile_config wm8996_retune[] = {
         {
                 .name = "Sub LPF",
@@ -72,7 +102,6 @@ static struct wm8962_pdata wm8962_pdata __initdata = {
                 0x8000 | WM8962_GPIO_FN_DMICDAT,
                 WM8962_GPIO_FN_IRQ,    /* Open drain mode */
         },
-        .irq_active_low = true,
 };
 
 static struct wm9081_pdata wm9081_pdata __initdata = {
@@ -91,6 +120,7 @@ static const struct i2c_board_info wm1254_devs[] = {
 
 static const struct i2c_board_info wm1255_devs[] = {
         { I2C_BOARD_INFO("wm5100", 0x1a),
+          .platform_data = &wm5100_pdata,
           .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
         },
         { I2C_BOARD_INFO("wm9081", 0x6c),
@@ -104,6 +134,24 @@ static const struct i2c_board_info wm1259_devs[] = {
         },
 };
 
+static struct wm8994_pdata wm8994_pdata = {
+        .gpio_base = CODEC_GPIO_BASE,
+        .gpio_defaults = {
+                0x3,          /* IRQ out, active high, CMOS */
+        },
+        .irq_base = CODEC_IRQ_BASE,
+        .ldo = {
+                { .supply = "WALLVDD" },
+                { .supply = "WALLVDD" },
+        },
+};
+
+static const struct i2c_board_info wm1277_devs[] = {
+        { I2C_BOARD_INFO("wm8958", 0x1a),  /* WM8958 is the superset */
+          .platform_data = &wm8994_pdata,
+          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+        },
+};
 
 static __devinitdata const struct {
         u8 id;
@@ -125,6 +173,8 @@ static __devinitdata const struct {
         { .id = 0x3b, .name = "1255-EV1 Kilchoman",
           .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
         { .id = 0x3c, .name = "1273-EV1 Longmorn" },
+        { .id = 0x3d, .name = "1277-EV1 Littlemill",
+          .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
 };
 
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
@@ -154,8 +204,8 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
                                         "Failed to register dev: %d\n", ret);
                 }
         } else {
-                dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
-                         id, rev);
+                dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
+                         id, rev + 1);
         }
 
         return 0;
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index f1c848aa4a1..25d9f0cf945 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -37,6 +37,8 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
 
+#include <sound/wm1250-ev1.h>
+
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -289,6 +291,11 @@ static struct platform_device speyside_wm8962_device = {
         .id             = -1,
 };
 
+static struct platform_device littlemill_device = {
+        .name           = "littlemill",
+        .id             = -1,
+};
+
 static struct regulator_consumer_supply wallvdd_consumers[] = {
         REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
@@ -341,6 +348,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
         &crag6410_backlight_device,
         &speyside_device,
         &speyside_wm8962_device,
+        &littlemill_device,
         &lowland_device,
         &wallvdd_device,
 };
@@ -374,6 +382,10 @@ static struct regulator_init_data vddarm __initdata = {
         .driver_data = &vddarm_pdata,
 };
 
+static struct regulator_consumer_supply vddint_consumers[] __initdata = {
+        REGULATOR_SUPPLY("vddint", NULL),
+};
+
 static struct regulator_init_data vddint __initdata = {
         .constraints = {
                 .name = "VDDINT",
@@ -382,6 +394,9 @@ static struct regulator_init_data vddint __initdata = {
                 .always_on = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
         },
+        .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
+        .consumer_supplies = vddint_consumers,
+        .supply_regulator = "WALLVDD",
 };
 
 static struct regulator_init_data vddmem __initdata = {
@@ -502,7 +517,8 @@ static struct wm831x_touch_pdata touch_pdata __initdata = {
 static struct wm831x_pdata crag_pmic_pdata __initdata = {
         .wm831x_num = 1,
         .irq_base = BANFF_PMIC_IRQ_BASE,
-        .gpio_base = GPIO_BOARD_START + 8,
+        .gpio_base = BANFF_PMIC_GPIO_BASE,
+        .soft_shutdown = true,
 
         .backup = &banff_backup_pdata,
 
@@ -607,6 +623,7 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
         .wm831x_num = 2,
         .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
         .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
+        .soft_shutdown = true,
 
         .gpio_defaults = {
                 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
@@ -624,6 +641,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
         .disable_touch = true,
 };
 
+static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
+        .gpios = {
+                [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
+                [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
+                [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
+                [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
+                [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
+        },
+};
+
 static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("wm8311", 0x34),
           .irq = S3C_EINT(0),
@@ -633,7 +660,13 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
         { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
 
-        { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
+        { I2C_BOARD_INFO("wm1250-ev1", 0x27),
+          .platform_data = &wm1250_ev1_pdata },
+};
+
+static struct s3c2410_platform_i2c i2c1_pdata = {
+        .frequency = 400000,
+        .bus_num = 1,
 };
 
 static void __init crag6410_map_io(void)
@@ -694,7 +727,7 @@ static void __init crag6410_machine_init(void)
         s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
 
         s3c_i2c0_set_platdata(&i2c0_pdata);
-        s3c_i2c1_set_platdata(NULL);
+        s3c_i2c1_set_platdata(&i2c1_pdata);
         s3c_fb_set_platdata(&crag6410_lcd_pdata);
 
         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b375cd5c47c..0868d133191 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -89,6 +89,8 @@ static struct sleep_save misc_save[] = {
 
         SAVE_ITEM(S3C64XX_SDMA_SEL),
         SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
+
+        SAVE_ITEM(S3C64XX_NORMAL_CFG),
 };
 
 void s3c_pm_configure_extint(void)
@@ -181,10 +183,23 @@ static void s3c64xx_pm_prepare(void)
 
 static int s3c64xx_pm_init(void)
 {
+        u32 val;
+
         pm_cpu_prep = s3c64xx_pm_prepare;
         pm_cpu_sleep = s3c64xx_cpu_suspend;
         pm_uart_udivslot = 1;
 
+        /*
+         * Unconditionally disable power domains that contain only
+         * blocks which have no mainline driver support.
+         */
+        val = __raw_readl(S3C64XX_NORMAL_CFG);
+        val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
+                 S3C64XX_NORMALCFG_DOMAIN_V_ON |
+                 S3C64XX_NORMALCFG_DOMAIN_I_ON |
+                 S3C64XX_NORMALCFG_DOMAIN_P_ON);
+        __raw_writel(val, S3C64XX_NORMAL_CFG);
+
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
         gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
         gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 91aff7cb828..373652d76b9 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,11 +2,8 @@ if ARCH_TEGRA
 
 comment "NVIDIA Tegra options"
 
-choice
-        prompt "Select Tegra processor family for target system"
-
 config ARCH_TEGRA_2x_SOC
-        bool "Tegra 2 family"
+        bool "Enable support for Tegra20 family"
         select CPU_V7
         select ARM_GIC
         select ARCH_REQUIRE_GPIOLIB
@@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC
           Support for NVIDIA Tegra AP20 and T20 processors, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
-endchoice
+config ARCH_TEGRA_3x_SOC
+        bool "Enable support for Tegra30 family"
+        select CPU_V7
+        select ARM_GIC
+        select ARCH_REQUIRE_GPIOLIB
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
+        select USB_ULPI if USB_SUPPORT
+        select USB_ULPI_VIEWPORT if USB_SUPPORT
+        select USE_OF
+        help
+          Support for NVIDIA Tegra T30 processor family, based on the
+          ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
 config TEGRA_PCI
         bool "PCI Express support"
+        depends on ARCH_TEGRA_2x_SOC
         select PCI
 
 comment "Tegra board type"
 
 config MACH_HARMONY
        bool "Harmony board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Harmony development platform
 
 config MACH_KAEN
        bool "Kaen board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_SEABOARD
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
@@ -40,11 +51,13 @@ config MACH_KAEN
 
 config MACH_PAZ00
        bool "Paz00 board"
+       depends on ARCH_TEGRA_2x_SOC
        help
          Support for the Toshiba AC100/Dynabook AZ netbook
 
 config MACH_SEABOARD
        bool "Seaboard board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Seaboard development platform. It will
@@ -52,25 +65,29 @@ config MACH_SEABOARD
          have large similarities with the seaboard design.
 
 config MACH_TEGRA_DT
-        bool "Generic Tegra board (FDT support)"
+        bool "Generic Tegra20 board (FDT support)"
+        depends on ARCH_TEGRA_2x_SOC
         select USE_OF
         help
-          Support for generic nVidia Tegra boards using Flattened Device Tree
+          Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
 
 config MACH_TRIMSLICE
        bool "TrimSlice board"
+       depends on ARCH_TEGRA_2x_SOC
        select TEGRA_PCI
        help
          Support for CompuLab TrimSlice platform
 
 config MACH_WARIO
        bool "Wario board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_SEABOARD
        help
          Support for the Wario version of Seaboard
 
 config MACH_VENTANA
        bool "Ventana board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_TEGRA_DT
        help
          Support for the nVidia Ventana development platform
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 5be8e9eefc9..e120ff54f66 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,4 @@
+obj-y                                   += board-pinmux.o
 obj-y                                   += common.o
 obj-y                                   += devices.o
 obj-y                                   += io.o
@@ -5,12 +6,13 @@ obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += pinmux.o
-obj-y                                   += powergate.o
 obj-y                                   += fuse.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-t2-tables.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
@@ -29,9 +31,11 @@ obj-$(CONFIG_MACH_PAZ00)		+= board-paz00-pinmux.o
 obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard.o
 obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard-pinmux.o
 
-obj-$(CONFIG_MACH_TEGRA_DT)             += board-dt.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-dt-tegra20.o
 obj-$(CONFIG_MACH_TEGRA_DT)             += board-harmony-pinmux.o
 obj-$(CONFIG_MACH_TEGRA_DT)             += board-seaboard-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-paz00-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-trimslice-pinmux.o
 
 obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
 obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index bd12c9fb81e..9a82094092d 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,5 +3,8 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
 
 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
+dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
 dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
+dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
 dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
+dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index e417a8383db..c2ff8e02010 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -37,6 +37,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
 #include <mach/irqs.h>
@@ -47,10 +48,14 @@
 #include "devices.h"
 
 void harmony_pinmux_init(void);
+void paz00_pinmux_init(void);
 void seaboard_pinmux_init(void);
+void trimslice_pinmux_init(void);
 void ventana_pinmux_init(void);
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -60,14 +65,28 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
+                       &tegra_ehci1_device.dev.platform_data),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
+                       &tegra_ehci2_device.dev.platform_data),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
+                       &tegra_ehci3_device.dev.platform_data),
         {}
 };
 
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "uartd",      "pll_p",        216000000,      true },
+        { "usbd",       "clk_m",        12000000,       false },
+        { "usb2",       "clk_m",        12000000,       false },
+        { "usb3",       "clk_m",        12000000,       false },
+        { "pll_a",      "pll_p_out1",   56448000,       true },
+        { "pll_a_out0", "pll_a",        11289600,       true },
+        { "cdev1",      NULL,           0,              true },
+        { "i2s1",       "pll_a_out0",   11289600,       false},
+        { "i2s2",       "pll_a_out0",   11289600,       false},
         { NULL,         NULL,           0,              0},
 };
 
@@ -76,39 +95,23 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
         {}
 };
 
-static struct of_device_id tegra_dt_gic_match[] __initdata = {
-        { .compatible = "nvidia,tegra20-gic", },
-        {}
-};
-
 static struct {
         char *machine;
         void (*init)(void);
 } pinmux_configs[] = {
+        { "compulab,trimslice", trimslice_pinmux_init },
         { "nvidia,harmony", harmony_pinmux_init },
+        { "compal,paz00", paz00_pinmux_init },
         { "nvidia,seaboard", seaboard_pinmux_init },
         { "nvidia,ventana", ventana_pinmux_init },
 };
 
 static void __init tegra_dt_init(void)
 {
-        struct device_node *node;
         int i;
 
-        node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
-                                                TEGRA_ARM_INT_DIST_BASE);
-        if (node)
-                irq_domain_add_simple(node, INT_GIC_BASE);
-
         tegra_clk_init_from_table(tegra_dt_clk_init_table);
 
-        /*
-         * Finished with the static registrations now; fill in the missing
-         * devices
-         */
-        of_platform_populate(NULL, tegra_dt_match_table,
-                                tegra20_auxdata_lookup, NULL);
-
         for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
                 if (of_machine_is_compatible(pinmux_configs[i].machine)) {
                         pinmux_configs[i].init();
@@ -118,22 +121,31 @@ static void __init tegra_dt_init(void)
 
         WARN(i == ARRAY_SIZE(pinmux_configs),
                 "Unknown platform! Pinmuxing not initialized\n");
+
+        /*
+         * Finished with the static registrations now; fill in the missing
+         * devices
+         */
+        of_platform_populate(NULL, tegra_dt_match_table,
+                                tegra20_auxdata_lookup, NULL);
 }
 
-static const char * tegra_dt_board_compat[] = {
+static const char *tegra20_dt_board_compat[] = {
+        "compulab,trimslice",
         "nvidia,harmony",
+        "compal,paz00",
         "nvidia,seaboard",
         "nvidia,ventana",
         NULL
 };
 
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
-        .init_irq       = tegra_init_irq,
+        .init_early     = tegra20_init_early,
+        .init_irq       = tegra_dt_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_dt_init,
         .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra_dt_board_compat,
+        .dt_compat      = tegra20_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
new file mode 100644
index 00000000000..3c197e2440b
--- /dev/null
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-tegra/board-dt-tegra30.c
+ *
+ * NVIDIA Tegra30 device tree board support
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * Derived from:
+ *
+ * arch/arm/mach-tegra/board-dt-tegra20.c
+ *
+ * Copyright (C) 2010 Secret Lab Technologies, Ltd.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include "board.h"
+
+static struct of_device_id tegra_dt_match_table[] __initdata = {
+        { .compatible = "simple-bus", },
+        {}
+};
+
+static void __init tegra30_dt_init(void)
+{
+        of_platform_populate(NULL, tegra_dt_match_table,
+                                NULL, NULL);
+}
+
+static const char *tegra30_dt_board_compat[] = {
+        "nvidia,cardhu",
+        NULL
+};
+
+DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
+        .map_io         = tegra_map_common_io,
+        .init_early     = tegra30_init_early,
+        .init_irq       = tegra_dt_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .timer          = &tegra_timer,
+        .init_machine   = tegra30_dt_init,
+        .restart        = tegra_assert_system_reset,
+        .dt_compat      = tegra30_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 6db7d699ef1..33c4fedab84 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -22,7 +22,6 @@
 
 #include <asm/mach-types.h>
 
-#include <mach/pinmux.h>
 #include "board.h"
 #include "board-harmony.h"
 
@@ -48,10 +47,6 @@ static int __init harmony_pcie_init(void)
 
         regulator_enable(regulator);
 
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
-
         err = tegra_pcie_init(true, true);
         if (err)
                 goto err_pcie;
@@ -59,10 +54,6 @@ static int __init harmony_pcie_init(void)
         return 0;
 
 err_pcie:
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
-
         regulator_disable(regulator);
         regulator_put(regulator);
 err_reg:
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 7a4a26d5174..465808c8ac0 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -19,10 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
 #include "board-harmony.h"
-#include "devices.h"
+#include "board-pinmux.h"
 
 static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -143,11 +144,6 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true  },
         { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true  },
@@ -161,13 +157,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_EXT_MIC_EN,        .enable = true  },
 };
 
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = harmony_pinmux,
+        .pg_count = ARRAY_SIZE(harmony_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
 void harmony_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-
-        tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux));
-
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 70ee674131f..a0f9634f672 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony")
         .atag_offset    = 0x100,
         .fixup          = tegra_harmony_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index be30e215f4b..c775572dcea 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -19,10 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
 #include "board-paz00.h"
-#include "devices.h"
+#include "board-pinmux.h"
 
 static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -30,7 +31,7 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_PLLC_OUT1,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
@@ -143,11 +144,6 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true },
         { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true },
@@ -158,13 +154,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_WIFI_LED,       .enable = true },
 };
 
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = paz00_pinmux,
+        .pg_count = ARRAY_SIZE(paz00_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
 void paz00_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-
-        tegra_pinmux_config_table(paz00_pinmux, ARRAY_SIZE(paz00_pinmux));
-
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 33d6205ad30..fcf4f377b1d 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -23,8 +23,10 @@
 #include <linux/serial_8250.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
+#include <linux/gpio_keys.h>
 #include <linux/pda_power.h>
 #include <linux/io.h>
+#include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
@@ -115,12 +117,37 @@ static struct platform_device leds_gpio = {
         },
 };
 
+static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = TEGRA_GPIO_POWERKEY,
+                .active_low     = 1,
+                .desc           = "Power",
+                .type           = EV_KEY,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data paz00_gpio_keys = {
+        .buttons        = paz00_gpio_keys_buttons,
+        .nbuttons       = ARRAY_SIZE(paz00_gpio_keys_buttons),
+};
+
+static struct platform_device gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &paz00_gpio_keys,
+        },
+};
+
 static struct platform_device *paz00_devices[] __initdata = {
         &debug_uart,
         &tegra_sdhci_device4,
         &tegra_sdhci_device1,
         &wifi_rfkill_device,
         &leds_gpio,
+        &gpio_keys_device,
 };
 
 static void paz00_i2c_init(void)
@@ -189,7 +216,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
         .atag_offset    = 0x100,
         .fixup          = tegra_paz00_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 8aff06eb58c..ffa83f580db 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -32,6 +32,9 @@
 #define TEGRA_WIFI_RST                  TEGRA_GPIO_PD1
 #define TEGRA_WIFI_LED                  TEGRA_GPIO_PD0
 
+/* WakeUp */
+#define TEGRA_GPIO_POWERKEY     TEGRA_GPIO_PJ7
+
 void paz00_pinmux_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
new file mode 100644
index 00000000000..adc3efe979b
--- /dev/null
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/notifier.h>
+#include <linux/of.h>
+#include <linux/string.h>
+
+#include <mach/gpio-tegra.h>
+#include <mach/pinmux.h>
+
+#include "board-pinmux.h"
+#include "devices.h"
+
+struct tegra_board_pinmux_conf *confs[2];
+
+static void tegra_board_pinmux_setup_gpios(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(confs); i++) {
+                if (!confs[i])
+                        continue;
+
+                tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
+        }
+}
+
+static void tegra_board_pinmux_setup_pinmux(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(confs); i++) {
+                if (!confs[i])
+                        continue;
+
+                tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
+
+                if (confs[i]->drives)
+                        tegra_drive_pinmux_config_table(confs[i]->drives,
+                                                        confs[i]->drive_count);
+        }
+}
+
+static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
+                                         unsigned long event, void *vdev)
+{
+        static bool had_gpio;
+        static bool had_pinmux;
+
+        struct device *dev = vdev;
+        const char *devname;
+
+        if (event != BUS_NOTIFY_BOUND_DRIVER)
+                return NOTIFY_DONE;
+
+        devname = dev_name(dev);
+
+        if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
+                tegra_board_pinmux_setup_gpios();
+                had_gpio = true;
+        } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
+                tegra_board_pinmux_setup_pinmux();
+                had_pinmux = true;
+        }
+
+        if (had_gpio && had_pinmux)
+                return NOTIFY_STOP_MASK;
+        else
+                return NOTIFY_DONE;
+}
+
+static struct notifier_block nb = {
+        .notifier_call = tegra_board_pinmux_bus_notify,
+};
+
+static struct platform_device *devices[] = {
+        &tegra_gpio_device,
+        &tegra_pinmux_device,
+};
+
+void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
+                             struct tegra_board_pinmux_conf *conf_b)
+{
+        confs[0] = conf_a;
+        confs[1] = conf_b;
+
+        bus_register_notifier(&platform_bus_type, &nb);
+
+        if (!of_machine_is_compatible("nvidia,tegra20"))
+                platform_add_devices(devices, ARRAY_SIZE(devices));
+}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
new file mode 100644
index 00000000000..4aac73546f5
--- /dev/null
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_BOARD_PINMUX_H
+#define __MACH_TEGRA_BOARD_PINMUX_H
+
+#define GPIO_DEV "tegra-gpio"
+#define PINMUX_DEV "tegra-pinmux"
+
+struct tegra_pingroup_config;
+struct tegra_gpio_table;
+
+struct tegra_board_pinmux_conf {
+        struct tegra_pingroup_config *pgs;
+        int pg_count;
+
+        struct tegra_drive_pingroup_config *drives;
+        int drive_count;
+
+        struct tegra_gpio_table *gpios;
+        int gpio_count;
+};
+
+void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
+                             struct tegra_board_pinmux_conf *conf_b);
+
+#endif
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index b1c2972f62f..55e7e43a14a 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -19,11 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
-#include <mach/pinmux-t2.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
+#include "board-pinmux.h"
 #include "board-seaboard.h"
-#include "devices.h"
 
 #define DEFAULT_DRIVE(_name)                                    \
         {                                                       \
@@ -37,11 +37,11 @@
                 .slew_falling = TEGRA_SLEW_SLOWEST,             \
         }
 
-static __initdata struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
+static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
         DEFAULT_DRIVE(SDIO1),
 };
 
-static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
+static struct tegra_pingroup_config common_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -55,7 +55,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
@@ -65,7 +64,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -108,13 +106,8 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_LM0,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LM1,   TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
@@ -122,25 +115,19 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDB,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDD,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
@@ -160,13 +147,24 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
-        {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+static struct tegra_pingroup_config seaboard_pinmux[] = {
+        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+};
+
+static struct tegra_pingroup_config ventana_pinmux[] = {
         {TEGRA_PINGROUP_DDC,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTB,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTC,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTD,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GMD,  TEGRA_MUX_SFLASH,   TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -181,65 +179,59 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
         {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table common_gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true },
         { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true },
         { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true },
+        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
+};
+
+static struct tegra_gpio_table seaboard_gpio_table[] = {
         { .gpio = TEGRA_GPIO_LIDSWITCH,         .enable = true },
         { .gpio = TEGRA_GPIO_POWERKEY,          .enable = true },
         { .gpio = TEGRA_GPIO_HP_DET,            .enable = true },
         { .gpio = TEGRA_GPIO_ISL29018_IRQ,      .enable = true },
-        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
         { .gpio = TEGRA_GPIO_USB1,              .enable = true },
 };
 
-static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
-{
-        int i, j;
-        struct tegra_pingroup_config *new_pingroup, *base_pingroup;
-
-        /* Update base seaboard pinmux table with secondary board
-         * specific pinmux table table.
-         */
-        for (i = 0; i < size; i++) {
-                new_pingroup = &newtbl[i];
-                for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
-                        base_pingroup = &seaboard_pinmux[j];
-                        if (new_pingroup->pingroup == base_pingroup->pingroup) {
-                                *base_pingroup = *new_pingroup;
-                                break;
-                        }
-                }
-        }
-}
-
-void __init seaboard_common_pinmux_init(void)
-{
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
+static struct tegra_gpio_table ventana_gpio_table[] = {
+        /* hp_det */
+        { .gpio = TEGRA_GPIO_PW2,               .enable = true },
+        /* int_mic_en */
+        { .gpio = TEGRA_GPIO_PX0,               .enable = true },
+        /* ext_mic_en */
+        { .gpio = TEGRA_GPIO_PX1,               .enable = true },
+};
 
-        tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
+static struct tegra_board_pinmux_conf common_conf = {
+        .pgs = common_pinmux,
+        .pg_count = ARRAY_SIZE(common_pinmux),
+        .gpios = common_gpio_table,
+        .gpio_count = ARRAY_SIZE(common_gpio_table),
+};
 
-        tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
-                                        ARRAY_SIZE(seaboard_drive_pinmux));
+static struct tegra_board_pinmux_conf seaboard_conf = {
+        .pgs = seaboard_pinmux,
+        .pg_count = ARRAY_SIZE(seaboard_pinmux),
+        .drives = seaboard_drive_pinmux,
+        .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
+        .gpios = seaboard_gpio_table,
+        .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
+};
 
-        tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table));
-}
+static struct tegra_board_pinmux_conf ventana_conf = {
+        .pgs = ventana_pinmux,
+        .pg_count = ARRAY_SIZE(ventana_pinmux),
+        .gpios = ventana_gpio_table,
+        .gpio_count = ARRAY_SIZE(ventana_gpio_table),
+};
 
-void __init seaboard_pinmux_init(void)
+void seaboard_pinmux_init(void)
 {
-        seaboard_common_pinmux_init();
+        tegra_board_pinmux_init(&common_conf, &seaboard_conf);
 }
 
-void __init ventana_pinmux_init(void)
+void ventana_pinmux_init(void)
 {
-        update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux));
-        seaboard_common_pinmux_init();
+        tegra_board_pinmux_init(&common_conf, &ventana_conf);
 }
-
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index c1599eb8e0c..cfc74d46a09 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -283,7 +283,7 @@ static void __init tegra_wario_init(void)
 MACHINE_START(SEABOARD, "seaboard")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
@@ -294,7 +294,7 @@ MACHINE_END
 MACHINE_START(KAEN, "kaen")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
@@ -305,7 +305,7 @@ MACHINE_END
 MACHINE_START(WARIO, "wario")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index 7ab719d46da..a21a2be57cb 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -19,12 +19,13 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
+#include "board-pinmux.h"
 #include "board-trimslice.h"
-#include "devices.h"
 
-static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
+static struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
@@ -105,7 +106,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_RSVD3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
@@ -143,11 +144,6 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
         { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
@@ -156,11 +152,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
 };
 
-void __init trimslice_pinmux_init(void)
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = trimslice_pinmux,
+        .pg_count = ARRAY_SIZE(trimslice_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
+void trimslice_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-        tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux));
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index c242314a1db..cd52820a3e3 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
         .atag_offset    = 0x100,
         .fixup          = tegra_trimslice_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1d14df7eb7d..75d1543d77c 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -25,10 +25,11 @@
 
 void tegra_assert_system_reset(char mode, const char *cmd);
 
-void __init tegra_init_early(void);
+void __init tegra20_init_early(void);
+void __init tegra30_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
-void __init tegra_init_clock(void);
+void __init tegra_dt_init_irq(void);
 int __init tegra_pcie_init(bool init_port0, bool init_port1);
 
 extern struct sys_timer tegra_timer;
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f8d41ffc0ca..8337068a4ab 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
 
 void tegra_periph_reset_deassert(struct clk *c)
 {
-        tegra2_periph_reset_deassert(c);
+        BUG_ON(!c->ops->reset);
+        c->ops->reset(c, false);
 }
 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
-        tegra2_periph_reset_assert(c);
+        BUG_ON(!c->ops->reset);
+        c->ops->reset(c, true);
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
-void __init tegra_init_clock(void)
-{
-        tegra2_init_clocks();
-}
-
-/*
- * The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB.
- */
-void tegra_sdmmc_tap_delay(struct clk *c, int delay)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-        tegra2_sdmmc_tap_delay(c, delay);
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
 #ifdef CONFIG_DEBUG_FS
 
 static int __clk_lock_all_spinlocks(void)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 688316abc64..5c44106616c 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -146,15 +146,11 @@ struct tegra_clk_init_table {
 };
 
 void tegra2_init_clocks(void);
-void tegra2_periph_reset_deassert(struct clk *c);
-void tegra2_periph_reset_assert(struct clk *c);
 void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
-unsigned long clk_measure_input_freq(void);
 int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 unsigned long clk_get_rate_locked(struct clk *c);
 int clk_set_rate_locked(struct clk *c, unsigned long rate);
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 20f396d740f..a2eb90169ae 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-tegra/board-harmony.c
+ * arch/arm/mach-tegra/common.c
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -21,8 +21,10 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/of_irq.h>
 
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
 #include <mach/system.h>
@@ -31,18 +33,31 @@
 #include "clock.h"
 #include "fuse.h"
 
+#ifdef CONFIG_OF
+static const struct of_device_id tegra_dt_irq_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
+        { }
+};
+
+void __init tegra_dt_init_irq(void)
+{
+        tegra_init_irq();
+        of_irq_init(tegra_dt_irq_match);
+}
+#endif
+
 void tegra_assert_system_reset(char mode, const char *cmd)
 {
-        void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
+        void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
         u32 reg;
 
-        /* use *_related to avoid spinlock since caches are off */
         reg = readl_relaxed(reset);
-        reg |= 0x04;
+        reg |= 0x10;
         writel_relaxed(reg, reset);
 }
 
-static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "clk_m",      NULL,           0,              true },
         { "pll_p",      "clk_m",        216000000,      true },
@@ -58,24 +73,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
         { "cpu",        NULL,           0,              true },
         { NULL,         NULL,           0,              0},
 };
+#endif
 
-static void __init tegra_init_cache(void)
+static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 {
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+        u32 aux_ctrl, cache_type;
+
+        writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
+        writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
 
-        writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
-        writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
+        cache_type = readl(p + L2X0_CACHE_TYPE);
+        aux_ctrl = (cache_type & 0x700) << (17-8);
+        aux_ctrl |= 0x6C000001;
 
-        l2x0_init(p, 0x6C080001, 0x8200c3fe);
+        l2x0_init(p, aux_ctrl, 0x8200c3fe);
 #endif
 
 }
 
-void __init tegra_init_early(void)
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void __init tegra20_init_early(void)
 {
         tegra_init_fuse();
-        tegra_init_clock();
-        tegra_clk_init_from_table(common_clk_init_table);
-        tegra_init_cache();
+        tegra2_init_clocks();
+        tegra_clk_init_from_table(tegra20_clk_init_table);
+        tegra_init_cache(0x331, 0x441);
+}
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void __init tegra30_init_early(void)
+{
+        tegra_init_cache(0x441, 0x551);
 }
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index c8baf8f80d2..fc3ecb66de0 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
 unsigned long clk_get_rate_all_locked(struct clk *c);
-void tegra_sdmmc_tap_delay(struct clk *c, int delay);
+void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index 73265af4dda..a2146cd6867 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -25,7 +25,6 @@
 
 #define IRQ_LOCALTIMER                  29
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 /* Primary Interrupt Controller */
 #define INT_PRI_BASE                    (INT_GIC_BASE + 32)
 #define INT_TMR1                        (INT_PRI_BASE + 0)
@@ -178,6 +177,5 @@
 #define NR_BOARD_IRQS                   32
 
 #define NR_IRQS                         (INT_BOARD_BASE + NR_BOARD_IRQS)
-#endif
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
index 4c262634726..6a40c1dbab1 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -14,8 +14,8 @@
  *
  */
 
-#ifndef __MACH_TEGRA_PINMUX_T2_H
-#define __MACH_TEGRA_PINMUX_T2_H
+#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
+#define __MACH_TEGRA_PINMUX_TEGRA20_H
 
 enum tegra_pingroup {
         TEGRA_PINGROUP_ATA = 0,
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
new file mode 100644
index 00000000000..c1aee3eb2df
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
@@ -0,0 +1,320 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Nvidia, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
+#define __MACH_TEGRA_PINMUX_TEGRA30_H
+
+enum tegra_pingroup {
+        TEGRA_PINGROUP_ULPI_DATA0 = 0,
+        TEGRA_PINGROUP_ULPI_DATA1,
+        TEGRA_PINGROUP_ULPI_DATA2,
+        TEGRA_PINGROUP_ULPI_DATA3,
+        TEGRA_PINGROUP_ULPI_DATA4,
+        TEGRA_PINGROUP_ULPI_DATA5,
+        TEGRA_PINGROUP_ULPI_DATA6,
+        TEGRA_PINGROUP_ULPI_DATA7,
+        TEGRA_PINGROUP_ULPI_CLK,
+        TEGRA_PINGROUP_ULPI_DIR,
+        TEGRA_PINGROUP_ULPI_NXT,
+        TEGRA_PINGROUP_ULPI_STP,
+        TEGRA_PINGROUP_DAP3_FS,
+        TEGRA_PINGROUP_DAP3_DIN,
+        TEGRA_PINGROUP_DAP3_DOUT,
+        TEGRA_PINGROUP_DAP3_SCLK,
+        TEGRA_PINGROUP_GPIO_PV0,
+        TEGRA_PINGROUP_GPIO_PV1,
+        TEGRA_PINGROUP_SDMMC1_CLK,
+        TEGRA_PINGROUP_SDMMC1_CMD,
+        TEGRA_PINGROUP_SDMMC1_DAT3,
+        TEGRA_PINGROUP_SDMMC1_DAT2,
+        TEGRA_PINGROUP_SDMMC1_DAT1,
+        TEGRA_PINGROUP_SDMMC1_DAT0,
+        TEGRA_PINGROUP_GPIO_PV2,
+        TEGRA_PINGROUP_GPIO_PV3,
+        TEGRA_PINGROUP_CLK2_OUT,
+        TEGRA_PINGROUP_CLK2_REQ,
+        TEGRA_PINGROUP_LCD_PWR1,
+        TEGRA_PINGROUP_LCD_PWR2,
+        TEGRA_PINGROUP_LCD_SDIN,
+        TEGRA_PINGROUP_LCD_SDOUT,
+        TEGRA_PINGROUP_LCD_WR_N,
+        TEGRA_PINGROUP_LCD_CS0_N,
+        TEGRA_PINGROUP_LCD_DC0,
+        TEGRA_PINGROUP_LCD_SCK,
+        TEGRA_PINGROUP_LCD_PWR0,
+        TEGRA_PINGROUP_LCD_PCLK,
+        TEGRA_PINGROUP_LCD_DE,
+        TEGRA_PINGROUP_LCD_HSYNC,
+        TEGRA_PINGROUP_LCD_VSYNC,
+        TEGRA_PINGROUP_LCD_D0,
+        TEGRA_PINGROUP_LCD_D1,
+        TEGRA_PINGROUP_LCD_D2,
+        TEGRA_PINGROUP_LCD_D3,
+        TEGRA_PINGROUP_LCD_D4,
+        TEGRA_PINGROUP_LCD_D5,
+        TEGRA_PINGROUP_LCD_D6,
+        TEGRA_PINGROUP_LCD_D7,
+        TEGRA_PINGROUP_LCD_D8,
+        TEGRA_PINGROUP_LCD_D9,
+        TEGRA_PINGROUP_LCD_D10,
+        TEGRA_PINGROUP_LCD_D11,
+        TEGRA_PINGROUP_LCD_D12,
+        TEGRA_PINGROUP_LCD_D13,
+        TEGRA_PINGROUP_LCD_D14,
+        TEGRA_PINGROUP_LCD_D15,
+        TEGRA_PINGROUP_LCD_D16,
+        TEGRA_PINGROUP_LCD_D17,
+        TEGRA_PINGROUP_LCD_D18,
+        TEGRA_PINGROUP_LCD_D19,
+        TEGRA_PINGROUP_LCD_D20,
+        TEGRA_PINGROUP_LCD_D21,
+        TEGRA_PINGROUP_LCD_D22,
+        TEGRA_PINGROUP_LCD_D23,
+        TEGRA_PINGROUP_LCD_CS1_N,
+        TEGRA_PINGROUP_LCD_M1,
+        TEGRA_PINGROUP_LCD_DC1,
+        TEGRA_PINGROUP_HDMI_INT,
+        TEGRA_PINGROUP_DDC_SCL,
+        TEGRA_PINGROUP_DDC_SDA,
+        TEGRA_PINGROUP_CRT_HSYNC,
+        TEGRA_PINGROUP_CRT_VSYNC,
+        TEGRA_PINGROUP_VI_D0,
+        TEGRA_PINGROUP_VI_D1,
+        TEGRA_PINGROUP_VI_D2,
+        TEGRA_PINGROUP_VI_D3,
+        TEGRA_PINGROUP_VI_D4,
+        TEGRA_PINGROUP_VI_D5,
+        TEGRA_PINGROUP_VI_D6,
+        TEGRA_PINGROUP_VI_D7,
+        TEGRA_PINGROUP_VI_D8,
+        TEGRA_PINGROUP_VI_D9,
+        TEGRA_PINGROUP_VI_D10,
+        TEGRA_PINGROUP_VI_D11,
+        TEGRA_PINGROUP_VI_PCLK,
+        TEGRA_PINGROUP_VI_MCLK,
+        TEGRA_PINGROUP_VI_VSYNC,
+        TEGRA_PINGROUP_VI_HSYNC,
+        TEGRA_PINGROUP_UART2_RXD,
+        TEGRA_PINGROUP_UART2_TXD,
+        TEGRA_PINGROUP_UART2_RTS_N,
+        TEGRA_PINGROUP_UART2_CTS_N,
+        TEGRA_PINGROUP_UART3_TXD,
+        TEGRA_PINGROUP_UART3_RXD,
+        TEGRA_PINGROUP_UART3_CTS_N,
+        TEGRA_PINGROUP_UART3_RTS_N,
+        TEGRA_PINGROUP_GPIO_PU0,
+        TEGRA_PINGROUP_GPIO_PU1,
+        TEGRA_PINGROUP_GPIO_PU2,
+        TEGRA_PINGROUP_GPIO_PU3,
+        TEGRA_PINGROUP_GPIO_PU4,
+        TEGRA_PINGROUP_GPIO_PU5,
+        TEGRA_PINGROUP_GPIO_PU6,
+        TEGRA_PINGROUP_GEN1_I2C_SDA,
+        TEGRA_PINGROUP_GEN1_I2C_SCL,
+        TEGRA_PINGROUP_DAP4_FS,
+        TEGRA_PINGROUP_DAP4_DIN,
+        TEGRA_PINGROUP_DAP4_DOUT,
+        TEGRA_PINGROUP_DAP4_SCLK,
+        TEGRA_PINGROUP_CLK3_OUT,
+        TEGRA_PINGROUP_CLK3_REQ,
+        TEGRA_PINGROUP_GMI_WP_N,
+        TEGRA_PINGROUP_GMI_IORDY,
+        TEGRA_PINGROUP_GMI_WAIT,
+        TEGRA_PINGROUP_GMI_ADV_N,
+        TEGRA_PINGROUP_GMI_CLK,
+        TEGRA_PINGROUP_GMI_CS0_N,
+        TEGRA_PINGROUP_GMI_CS1_N,
+        TEGRA_PINGROUP_GMI_CS2_N,
+        TEGRA_PINGROUP_GMI_CS3_N,
+        TEGRA_PINGROUP_GMI_CS4_N,
+        TEGRA_PINGROUP_GMI_CS6_N,
+        TEGRA_PINGROUP_GMI_CS7_N,
+        TEGRA_PINGROUP_GMI_AD0,
+        TEGRA_PINGROUP_GMI_AD1,
+        TEGRA_PINGROUP_GMI_AD2,
+        TEGRA_PINGROUP_GMI_AD3,
+        TEGRA_PINGROUP_GMI_AD4,
+        TEGRA_PINGROUP_GMI_AD5,
+        TEGRA_PINGROUP_GMI_AD6,
+        TEGRA_PINGROUP_GMI_AD7,
+        TEGRA_PINGROUP_GMI_AD8,
+        TEGRA_PINGROUP_GMI_AD9,
+        TEGRA_PINGROUP_GMI_AD10,
+        TEGRA_PINGROUP_GMI_AD11,
+        TEGRA_PINGROUP_GMI_AD12,
+        TEGRA_PINGROUP_GMI_AD13,
+        TEGRA_PINGROUP_GMI_AD14,
+        TEGRA_PINGROUP_GMI_AD15,
+        TEGRA_PINGROUP_GMI_A16,
+        TEGRA_PINGROUP_GMI_A17,
+        TEGRA_PINGROUP_GMI_A18,
+        TEGRA_PINGROUP_GMI_A19,
+        TEGRA_PINGROUP_GMI_WR_N,
+        TEGRA_PINGROUP_GMI_OE_N,
+        TEGRA_PINGROUP_GMI_DQS,
+        TEGRA_PINGROUP_GMI_RST_N,
+        TEGRA_PINGROUP_GEN2_I2C_SCL,
+        TEGRA_PINGROUP_GEN2_I2C_SDA,
+        TEGRA_PINGROUP_SDMMC4_CLK,
+        TEGRA_PINGROUP_SDMMC4_CMD,
+        TEGRA_PINGROUP_SDMMC4_DAT0,
+        TEGRA_PINGROUP_SDMMC4_DAT1,
+        TEGRA_PINGROUP_SDMMC4_DAT2,
+        TEGRA_PINGROUP_SDMMC4_DAT3,
+        TEGRA_PINGROUP_SDMMC4_DAT4,
+        TEGRA_PINGROUP_SDMMC4_DAT5,
+        TEGRA_PINGROUP_SDMMC4_DAT6,
+        TEGRA_PINGROUP_SDMMC4_DAT7,
+        TEGRA_PINGROUP_SDMMC4_RST_N,
+        TEGRA_PINGROUP_CAM_MCLK,
+        TEGRA_PINGROUP_GPIO_PCC1,
+        TEGRA_PINGROUP_GPIO_PBB0,
+        TEGRA_PINGROUP_CAM_I2C_SCL,
+        TEGRA_PINGROUP_CAM_I2C_SDA,
+        TEGRA_PINGROUP_GPIO_PBB3,
+        TEGRA_PINGROUP_GPIO_PBB4,
+        TEGRA_PINGROUP_GPIO_PBB5,
+        TEGRA_PINGROUP_GPIO_PBB6,
+        TEGRA_PINGROUP_GPIO_PBB7,
+        TEGRA_PINGROUP_GPIO_PCC2,
+        TEGRA_PINGROUP_JTAG_RTCK,
+        TEGRA_PINGROUP_PWR_I2C_SCL,
+        TEGRA_PINGROUP_PWR_I2C_SDA,
+        TEGRA_PINGROUP_KB_ROW0,
+        TEGRA_PINGROUP_KB_ROW1,
+        TEGRA_PINGROUP_KB_ROW2,
+        TEGRA_PINGROUP_KB_ROW3,
+        TEGRA_PINGROUP_KB_ROW4,
+        TEGRA_PINGROUP_KB_ROW5,
+        TEGRA_PINGROUP_KB_ROW6,
+        TEGRA_PINGROUP_KB_ROW7,
+        TEGRA_PINGROUP_KB_ROW8,
+        TEGRA_PINGROUP_KB_ROW9,
+        TEGRA_PINGROUP_KB_ROW10,
+        TEGRA_PINGROUP_KB_ROW11,
+        TEGRA_PINGROUP_KB_ROW12,
+        TEGRA_PINGROUP_KB_ROW13,
+        TEGRA_PINGROUP_KB_ROW14,
+        TEGRA_PINGROUP_KB_ROW15,
+        TEGRA_PINGROUP_KB_COL0,
+        TEGRA_PINGROUP_KB_COL1,
+        TEGRA_PINGROUP_KB_COL2,
+        TEGRA_PINGROUP_KB_COL3,
+        TEGRA_PINGROUP_KB_COL4,
+        TEGRA_PINGROUP_KB_COL5,
+        TEGRA_PINGROUP_KB_COL6,
+        TEGRA_PINGROUP_KB_COL7,
+        TEGRA_PINGROUP_CLK_32K_OUT,
+        TEGRA_PINGROUP_SYS_CLK_REQ,
+        TEGRA_PINGROUP_CORE_PWR_REQ,
+        TEGRA_PINGROUP_CPU_PWR_REQ,
+        TEGRA_PINGROUP_PWR_INT_N,
+        TEGRA_PINGROUP_CLK_32K_IN,
+        TEGRA_PINGROUP_OWR,
+        TEGRA_PINGROUP_DAP1_FS,
+        TEGRA_PINGROUP_DAP1_DIN,
+        TEGRA_PINGROUP_DAP1_DOUT,
+        TEGRA_PINGROUP_DAP1_SCLK,
+        TEGRA_PINGROUP_CLK1_REQ,
+        TEGRA_PINGROUP_CLK1_OUT,
+        TEGRA_PINGROUP_SPDIF_IN,
+        TEGRA_PINGROUP_SPDIF_OUT,
+        TEGRA_PINGROUP_DAP2_FS,
+        TEGRA_PINGROUP_DAP2_DIN,
+        TEGRA_PINGROUP_DAP2_DOUT,
+        TEGRA_PINGROUP_DAP2_SCLK,
+        TEGRA_PINGROUP_SPI2_MOSI,
+        TEGRA_PINGROUP_SPI2_MISO,
+        TEGRA_PINGROUP_SPI2_CS0_N,
+        TEGRA_PINGROUP_SPI2_SCK,
+        TEGRA_PINGROUP_SPI1_MOSI,
+        TEGRA_PINGROUP_SPI1_SCK,
+        TEGRA_PINGROUP_SPI1_CS0_N,
+        TEGRA_PINGROUP_SPI1_MISO,
+        TEGRA_PINGROUP_SPI2_CS1_N,
+        TEGRA_PINGROUP_SPI2_CS2_N,
+        TEGRA_PINGROUP_SDMMC3_CLK,
+        TEGRA_PINGROUP_SDMMC3_CMD,
+        TEGRA_PINGROUP_SDMMC3_DAT0,
+        TEGRA_PINGROUP_SDMMC3_DAT1,
+        TEGRA_PINGROUP_SDMMC3_DAT2,
+        TEGRA_PINGROUP_SDMMC3_DAT3,
+        TEGRA_PINGROUP_SDMMC3_DAT4,
+        TEGRA_PINGROUP_SDMMC3_DAT5,
+        TEGRA_PINGROUP_SDMMC3_DAT6,
+        TEGRA_PINGROUP_SDMMC3_DAT7,
+        TEGRA_PINGROUP_PEX_L0_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L0_RST_N,
+        TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_WAKE_N,
+        TEGRA_PINGROUP_PEX_L1_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L1_RST_N,
+        TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_L2_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L2_RST_N,
+        TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
+        TEGRA_PINGROUP_HDMI_CEC,
+        TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_drive_pingroup {
+        TEGRA_DRIVE_PINGROUP_AO1 = 0,
+        TEGRA_DRIVE_PINGROUP_AO2,
+        TEGRA_DRIVE_PINGROUP_AT1,
+        TEGRA_DRIVE_PINGROUP_AT2,
+        TEGRA_DRIVE_PINGROUP_AT3,
+        TEGRA_DRIVE_PINGROUP_AT4,
+        TEGRA_DRIVE_PINGROUP_AT5,
+        TEGRA_DRIVE_PINGROUP_CDEV1,
+        TEGRA_DRIVE_PINGROUP_CDEV2,
+        TEGRA_DRIVE_PINGROUP_CSUS,
+        TEGRA_DRIVE_PINGROUP_DAP1,
+        TEGRA_DRIVE_PINGROUP_DAP2,
+        TEGRA_DRIVE_PINGROUP_DAP3,
+        TEGRA_DRIVE_PINGROUP_DAP4,
+        TEGRA_DRIVE_PINGROUP_DBG,
+        TEGRA_DRIVE_PINGROUP_LCD1,
+        TEGRA_DRIVE_PINGROUP_LCD2,
+        TEGRA_DRIVE_PINGROUP_SDIO2,
+        TEGRA_DRIVE_PINGROUP_SDIO3,
+        TEGRA_DRIVE_PINGROUP_SPI,
+        TEGRA_DRIVE_PINGROUP_UAA,
+        TEGRA_DRIVE_PINGROUP_UAB,
+        TEGRA_DRIVE_PINGROUP_UART2,
+        TEGRA_DRIVE_PINGROUP_UART3,
+        TEGRA_DRIVE_PINGROUP_VI1,
+        TEGRA_DRIVE_PINGROUP_SDIO1,
+        TEGRA_DRIVE_PINGROUP_CRT,
+        TEGRA_DRIVE_PINGROUP_DDC,
+        TEGRA_DRIVE_PINGROUP_GMA,
+        TEGRA_DRIVE_PINGROUP_GMB,
+        TEGRA_DRIVE_PINGROUP_GMC,
+        TEGRA_DRIVE_PINGROUP_GMD,
+        TEGRA_DRIVE_PINGROUP_GME,
+        TEGRA_DRIVE_PINGROUP_GMF,
+        TEGRA_DRIVE_PINGROUP_GMG,
+        TEGRA_DRIVE_PINGROUP_GMH,
+        TEGRA_DRIVE_PINGROUP_OWR,
+        TEGRA_DRIVE_PINGROUP_UAD,
+        TEGRA_DRIVE_PINGROUP_GPV,
+        TEGRA_DRIVE_PINGROUP_DEV3,
+        TEGRA_DRIVE_PINGROUP_CEC,
+        TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index bb7dfdb6120..055f1792c8f 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -2,6 +2,7 @@
  * linux/arch/arm/mach-tegra/include/mach/pinmux.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Nvidia, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -17,18 +18,13 @@
 #ifndef __MACH_TEGRA_PINMUX_H
 #define __MACH_TEGRA_PINMUX_H
 
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
-#include "pinmux-t2.h"
-#else
-#error "Undefined Tegra architecture"
-#endif
-
 enum tegra_mux_func {
         TEGRA_MUX_RSVD = 0x8000,
         TEGRA_MUX_RSVD1 = 0x8000,
         TEGRA_MUX_RSVD2 = 0x8001,
         TEGRA_MUX_RSVD3 = 0x8002,
         TEGRA_MUX_RSVD4 = 0x8003,
+        TEGRA_MUX_INVALID = 0x4000,
         TEGRA_MUX_NONE = -1,
         TEGRA_MUX_AHB_CLK,
         TEGRA_MUX_APB_CLK,
@@ -90,6 +86,49 @@ enum tegra_mux_func {
         TEGRA_MUX_VI,
         TEGRA_MUX_VI_SENSOR_CLK,
         TEGRA_MUX_XIO,
+        TEGRA_MUX_BLINK,
+        TEGRA_MUX_CEC,
+        TEGRA_MUX_CLK12,
+        TEGRA_MUX_DAP,
+        TEGRA_MUX_DAPSDMMC2,
+        TEGRA_MUX_DDR,
+        TEGRA_MUX_DEV3,
+        TEGRA_MUX_DTV,
+        TEGRA_MUX_VI_ALT1,
+        TEGRA_MUX_VI_ALT2,
+        TEGRA_MUX_VI_ALT3,
+        TEGRA_MUX_EMC_DLL,
+        TEGRA_MUX_EXTPERIPH1,
+        TEGRA_MUX_EXTPERIPH2,
+        TEGRA_MUX_EXTPERIPH3,
+        TEGRA_MUX_GMI_ALT,
+        TEGRA_MUX_HDA,
+        TEGRA_MUX_HSI,
+        TEGRA_MUX_I2C4,
+        TEGRA_MUX_I2C5,
+        TEGRA_MUX_I2CPWR,
+        TEGRA_MUX_I2S0,
+        TEGRA_MUX_I2S1,
+        TEGRA_MUX_I2S2,
+        TEGRA_MUX_I2S3,
+        TEGRA_MUX_I2S4,
+        TEGRA_MUX_NAND_ALT,
+        TEGRA_MUX_POPSDIO4,
+        TEGRA_MUX_POPSDMMC4,
+        TEGRA_MUX_PWM0,
+        TEGRA_MUX_PWM1,
+        TEGRA_MUX_PWM2,
+        TEGRA_MUX_PWM3,
+        TEGRA_MUX_SATA,
+        TEGRA_MUX_SPI5,
+        TEGRA_MUX_SPI6,
+        TEGRA_MUX_SYSCLK,
+        TEGRA_MUX_VGP1,
+        TEGRA_MUX_VGP2,
+        TEGRA_MUX_VGP3,
+        TEGRA_MUX_VGP4,
+        TEGRA_MUX_VGP5,
+        TEGRA_MUX_VGP6,
         TEGRA_MUX_SAFE,
         TEGRA_MAX_MUX,
 };
@@ -105,6 +144,11 @@ enum tegra_tristate {
         TEGRA_TRI_TRISTATE = 1,
 };
 
+enum tegra_pin_io {
+        TEGRA_PIN_OUTPUT = 0,
+        TEGRA_PIN_INPUT = 1,
+};
+
 enum tegra_vddio {
         TEGRA_VDDIO_BB = 0,
         TEGRA_VDDIO_LCD,
@@ -115,10 +159,16 @@ enum tegra_vddio {
         TEGRA_VDDIO_SYS,
         TEGRA_VDDIO_AUDIO,
         TEGRA_VDDIO_SD,
+        TEGRA_VDDIO_CAM,
+        TEGRA_VDDIO_GMI,
+        TEGRA_VDDIO_PEXCTL,
+        TEGRA_VDDIO_SDMMC1,
+        TEGRA_VDDIO_SDMMC3,
+        TEGRA_VDDIO_SDMMC4,
 };
 
 struct tegra_pingroup_config {
-        enum tegra_pingroup     pingroup;
+        int pingroup;
         enum tegra_mux_func     func;
         enum tegra_pullupdown   pupd;
         enum tegra_tristate     tristate;
@@ -187,7 +237,7 @@ enum tegra_schmitt {
 };
 
 struct tegra_drive_pingroup_config {
-        enum tegra_drive_pingroup pingroup;
+        int pingroup;
         enum tegra_hsm hsm;
         enum tegra_schmitt schmitt;
         enum tegra_drive drive;
@@ -208,6 +258,7 @@ struct tegra_pingroup_desc {
         int funcs[4];
         int func_safe;
         int vddio;
+        enum tegra_pin_io io_default;
         s16 tri_bank;   /* Register bank the tri_reg exists within */
         s16 mux_bank;   /* Register bank the mux_reg exists within */
         s16 pupd_bank;  /* Register bank the pupd_reg exists within */
@@ -217,15 +268,23 @@ struct tegra_pingroup_desc {
         s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
         s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
         s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
+        s8 lock_bit;    /* offset of the LOCK bit into mux register bit */
+        s8 od_bit;      /* offset of the OD bit into mux register bit */
+        s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
 };
 
-extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
-extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
+typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
+        int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+        int *pgdrive_max);
 
-int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
-        enum tegra_tristate tristate);
-int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
-        enum tegra_pullupdown pupd);
+void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
+
+void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
+
+int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
+int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
 
 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
         int len);
@@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
         int len, enum tegra_pullupdown pupd);
 #endif
-
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 8ad82af6a29..4e1afcd54fa 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -21,6 +21,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 
 #include <asm/hardware/gic.h>
 
@@ -125,6 +126,11 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
 
-        gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
-                 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+        /*
+         * Check if there is a devicetree present, since the GIC will be
+         * initialized elsewhere under DT.
+         */
+        if (!of_have_populated_dt())
+                gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
+                        IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 }
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 97ef3e55dfd..ec63c6b2b6b 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -37,7 +37,6 @@
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
 
-#include <mach/pinmux.h>
 #include <mach/iomap.h>
 #include <mach/clk.h>
 #include <mach/powergate.h>
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
index a0dc2bc28ed..734add1280b 100644
--- a/arch/arm/mach-tegra/pinmux-t2-tables.c
+++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
@@ -1,7 +1,7 @@
 /*
- * linux/arch/arm/mach-tegra/pinmux-t2-tables.c
+ * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
  *
- * Common pinmux configurations for Tegra 2 SoCs
+ * Common pinmux configurations for Tegra20 SoCs
  *
  * Copyright (C) 2010 NVIDIA Corporation
  *
@@ -29,6 +29,7 @@
 
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 #include <mach/suspend.h>
 
 #define TRISTATE_REG_A          0x14
@@ -43,7 +44,7 @@
                 .reg = ((r) - PINGROUP_REG_A)                   \
         }
 
-const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
         DRIVE_PINGROUP(AO1,             0x868),
         DRIVE_PINGROUP(AO2,             0x86c),
         DRIVE_PINGROUP(AT1,             0x870),
@@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
                 .pupd_bank = 2,                         \
                 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
                 .pupd_bit = pupd_b,                             \
+                .lock_bit = -1,                                 \
+                .od_bit = -1,                                   \
+                .ioreset_bit = -1,                              \
+                .io_default = -1,                               \
         }
 
-const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
         PINGROUP(ATA,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x14, 0,  0x80, 24, 0xA0, 0),
         PINGROUP(ATB,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 1,  0x80, 16, 0xA0, 2),
         PINGROUP(ATC,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 2,  0x80, 22, 0xA0, 4),
@@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
         PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
         PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
 };
+
+void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
+                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+                int *pgdrive_max)
+{
+        *pg = tegra_soc_pingroups;
+        *pg_max = TEGRA_MAX_PINGROUP;
+        *pgdrive = tegra_soc_drive_pingroups;
+        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+}
+
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
new file mode 100644
index 00000000000..14fc0e4c1c4
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
@@ -0,0 +1,376 @@
+/*
+ * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+ *
+ * Common pinmux configurations for Tegra30 SoCs
+ *
+ * Copyright (C) 2010,2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-tegra30.h>
+#include <mach/suspend.h>
+
+#define PINGROUP_REG_A  0x868
+#define MUXCTL_REG_A    0x3000
+
+#define DRIVE_PINGROUP(pg_name, r)              \
+        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {  \
+                .name = #pg_name,               \
+                .reg_bank = 0,                  \
+                .reg = ((r) - PINGROUP_REG_A)   \
+        }
+
+static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+        DRIVE_PINGROUP(AO1,             0x868),
+        DRIVE_PINGROUP(AO2,             0x86c),
+        DRIVE_PINGROUP(AT1,             0x870),
+        DRIVE_PINGROUP(AT2,             0x874),
+        DRIVE_PINGROUP(AT3,             0x878),
+        DRIVE_PINGROUP(AT4,             0x87c),
+        DRIVE_PINGROUP(AT5,             0x880),
+        DRIVE_PINGROUP(CDEV1,           0x884),
+        DRIVE_PINGROUP(CDEV2,           0x888),
+        DRIVE_PINGROUP(CSUS,            0x88c),
+        DRIVE_PINGROUP(DAP1,            0x890),
+        DRIVE_PINGROUP(DAP2,            0x894),
+        DRIVE_PINGROUP(DAP3,            0x898),
+        DRIVE_PINGROUP(DAP4,            0x89c),
+        DRIVE_PINGROUP(DBG,             0x8a0),
+        DRIVE_PINGROUP(LCD1,            0x8a4),
+        DRIVE_PINGROUP(LCD2,            0x8a8),
+        DRIVE_PINGROUP(SDIO2,           0x8ac),
+        DRIVE_PINGROUP(SDIO3,           0x8b0),
+        DRIVE_PINGROUP(SPI,             0x8b4),
+        DRIVE_PINGROUP(UAA,             0x8b8),
+        DRIVE_PINGROUP(UAB,             0x8bc),
+        DRIVE_PINGROUP(UART2,           0x8c0),
+        DRIVE_PINGROUP(UART3,           0x8c4),
+        DRIVE_PINGROUP(VI1,             0x8c8),
+        DRIVE_PINGROUP(SDIO1,           0x8ec),
+        DRIVE_PINGROUP(CRT,             0x8f8),
+        DRIVE_PINGROUP(DDC,             0x8fc),
+        DRIVE_PINGROUP(GMA,             0x900),
+        DRIVE_PINGROUP(GMB,             0x904),
+        DRIVE_PINGROUP(GMC,             0x908),
+        DRIVE_PINGROUP(GMD,             0x90c),
+        DRIVE_PINGROUP(GME,             0x910),
+        DRIVE_PINGROUP(GMF,             0x914),
+        DRIVE_PINGROUP(GMG,             0x918),
+        DRIVE_PINGROUP(GMH,             0x91c),
+        DRIVE_PINGROUP(OWR,             0x920),
+        DRIVE_PINGROUP(UAD,             0x924),
+        DRIVE_PINGROUP(GPV,             0x928),
+        DRIVE_PINGROUP(DEV3,            0x92c),
+        DRIVE_PINGROUP(CEC,             0x938),
+};
+
+#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg)    \
+        [TEGRA_PINGROUP_ ## pg_name] = {                        \
+                .name = #pg_name,                               \
+                .vddio = TEGRA_VDDIO_ ## vdd,                   \
+                .funcs = {                                      \
+                        TEGRA_MUX_ ## f0,                       \
+                        TEGRA_MUX_ ## f1,                       \
+                        TEGRA_MUX_ ## f2,                       \
+                        TEGRA_MUX_ ## f3,                       \
+                },                                              \
+                .func_safe = TEGRA_MUX_ ## fs,                  \
+                .tri_bank = 1,                                  \
+                .tri_reg = ((reg) - MUXCTL_REG_A),              \
+                .tri_bit = 4,                                   \
+                .mux_bank = 1,                                  \
+                .mux_reg = ((reg) - MUXCTL_REG_A),              \
+                .mux_bit = 0,                                   \
+                .pupd_bank = 1,                                 \
+                .pupd_reg = ((reg) - MUXCTL_REG_A),             \
+                .pupd_bit = 2,                                  \
+                .io_default = TEGRA_PIN_ ## iod,                \
+                .od_bit = 6,                                    \
+                .lock_bit = 7,                                  \
+                .ioreset_bit = 8,                               \
+        }
+
+static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+        /*       NAME             VDD       f0          f1          f2          f3          fSafe       io      reg */
+        PINGROUP(ULPI_DATA0,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3000),
+        PINGROUP(ULPI_DATA1,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3004),
+        PINGROUP(ULPI_DATA2,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3008),
+        PINGROUP(ULPI_DATA3,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x300c),
+        PINGROUP(ULPI_DATA4,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3010),
+        PINGROUP(ULPI_DATA5,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3014),
+        PINGROUP(ULPI_DATA6,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3018),
+        PINGROUP(ULPI_DATA7,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x301c),
+        PINGROUP(ULPI_CLK,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3020),
+        PINGROUP(ULPI_DIR,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3024),
+        PINGROUP(ULPI_NXT,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3028),
+        PINGROUP(ULPI_STP,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x302c),
+        PINGROUP(DAP3_FS,         BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3030),
+        PINGROUP(DAP3_DIN,        BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3034),
+        PINGROUP(DAP3_DOUT,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3038),
+        PINGROUP(DAP3_SCLK,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x303c),
+        PINGROUP(GPIO_PV0,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3040),
+        PINGROUP(GPIO_PV1,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3044),
+        PINGROUP(SDMMC1_CLK,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x3048),
+        PINGROUP(SDMMC1_CMD,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x304c),
+        PINGROUP(SDMMC1_DAT3,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3050),
+        PINGROUP(SDMMC1_DAT2,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3054),
+        PINGROUP(SDMMC1_DAT1,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3058),
+        PINGROUP(SDMMC1_DAT0,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x305c),
+        PINGROUP(GPIO_PV2,        SDMMC1,   OWR,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3060),
+        PINGROUP(GPIO_PV3,        SDMMC1,   INVALID,    RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3064),
+        PINGROUP(CLK2_OUT,        SDMMC1,   EXTPERIPH2, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3068),
+        PINGROUP(CLK2_REQ,        SDMMC1,   DAP,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x306c),
+        PINGROUP(LCD_PWR1,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3070),
+        PINGROUP(LCD_PWR2,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3074),
+        PINGROUP(LCD_SDIN,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3078),
+        PINGROUP(LCD_SDOUT,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x307c),
+        PINGROUP(LCD_WR_N,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3080),
+        PINGROUP(LCD_CS0_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3084),
+        PINGROUP(LCD_DC0,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3088),
+        PINGROUP(LCD_SCK,         LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x308c),
+        PINGROUP(LCD_PWR0,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3090),
+        PINGROUP(LCD_PCLK,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3094),
+        PINGROUP(LCD_DE,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3098),
+        PINGROUP(LCD_HSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x309c),
+        PINGROUP(LCD_VSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a0),
+        PINGROUP(LCD_D0,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a4),
+        PINGROUP(LCD_D1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a8),
+        PINGROUP(LCD_D2,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ac),
+        PINGROUP(LCD_D3,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b0),
+        PINGROUP(LCD_D4,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b4),
+        PINGROUP(LCD_D5,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b8),
+        PINGROUP(LCD_D6,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30bc),
+        PINGROUP(LCD_D7,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c0),
+        PINGROUP(LCD_D8,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c4),
+        PINGROUP(LCD_D9,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c8),
+        PINGROUP(LCD_D10,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30cc),
+        PINGROUP(LCD_D11,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d0),
+        PINGROUP(LCD_D12,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d4),
+        PINGROUP(LCD_D13,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d8),
+        PINGROUP(LCD_D14,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30dc),
+        PINGROUP(LCD_D15,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e0),
+        PINGROUP(LCD_D16,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e4),
+        PINGROUP(LCD_D17,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e8),
+        PINGROUP(LCD_D18,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ec),
+        PINGROUP(LCD_D19,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f0),
+        PINGROUP(LCD_D20,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f4),
+        PINGROUP(LCD_D21,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f8),
+        PINGROUP(LCD_D22,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30fc),
+        PINGROUP(LCD_D23,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3100),
+        PINGROUP(LCD_CS1_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD2,      RSVD,       OUTPUT, 0x3104),
+        PINGROUP(LCD_M1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3108),
+        PINGROUP(LCD_DC1,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x310c),
+        PINGROUP(HDMI_INT,        LCD,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3110),
+        PINGROUP(DDC_SCL,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3114),
+        PINGROUP(DDC_SDA,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3118),
+        PINGROUP(CRT_HSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x311c),
+        PINGROUP(CRT_VSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3120),
+        PINGROUP(VI_D0,           VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3124),
+        PINGROUP(VI_D1,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3128),
+        PINGROUP(VI_D2,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x312c),
+        PINGROUP(VI_D3,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3130),
+        PINGROUP(VI_D4,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3134),
+        PINGROUP(VI_D5,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3138),
+        PINGROUP(VI_D6,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x313c),
+        PINGROUP(VI_D7,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3140),
+        PINGROUP(VI_D8,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3144),
+        PINGROUP(VI_D9,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3148),
+        PINGROUP(VI_D10,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x314c),
+        PINGROUP(VI_D11,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3150),
+        PINGROUP(VI_PCLK,         VI,       RSVD1,      SDIO2,      VI,         RSVD2,      RSVD,       INPUT,  0x3154),
+        PINGROUP(VI_MCLK,         VI,       VI,         INVALID,    INVALID,    INVALID,    RSVD,       INPUT,  0x3158),
+        PINGROUP(VI_VSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x315c),
+        PINGROUP(VI_HSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3160),
+        PINGROUP(UART2_RXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3164),
+        PINGROUP(UART2_TXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3168),
+        PINGROUP(UART2_RTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x316c),
+        PINGROUP(UART2_CTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x3170),
+        PINGROUP(UART3_TXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3174),
+        PINGROUP(UART3_RXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3178),
+        PINGROUP(UART3_CTS_N,     UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x317c),
+        PINGROUP(UART3_RTS_N,     UART,     UARTC,      PWM0,       GMI,        RSVD2,      RSVD,       INPUT,  0x3180),
+        PINGROUP(GPIO_PU0,        UART,     OWR,        UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3184),
+        PINGROUP(GPIO_PU1,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x3188),
+        PINGROUP(GPIO_PU2,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x318c),
+        PINGROUP(GPIO_PU3,        UART,     PWM0,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3190),
+        PINGROUP(GPIO_PU4,        UART,     PWM1,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3194),
+        PINGROUP(GPIO_PU5,        UART,     PWM2,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3198),
+        PINGROUP(GPIO_PU6,        UART,     PWM3,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x319c),
+        PINGROUP(GEN1_I2C_SDA,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a0),
+        PINGROUP(GEN1_I2C_SCL,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a4),
+        PINGROUP(DAP4_FS,         UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31a8),
+        PINGROUP(DAP4_DIN,        UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31ac),
+        PINGROUP(DAP4_DOUT,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b0),
+        PINGROUP(DAP4_SCLK,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b4),
+        PINGROUP(CLK3_OUT,        UART,     EXTPERIPH3, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b8),
+        PINGROUP(CLK3_REQ,        UART,     DEV3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31bc),
+        PINGROUP(GMI_WP_N,        GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31c0),
+        PINGROUP(GMI_IORDY,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c4),
+        PINGROUP(GMI_WAIT,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c8),
+        PINGROUP(GMI_ADV_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31cc),
+        PINGROUP(GMI_CLK,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31d0),
+        PINGROUP(GMI_CS0_N,       GMI,      RSVD1,      NAND,       GMI,        INVALID,    RSVD,       INPUT,  0x31d4),
+        PINGROUP(GMI_CS1_N,       GMI,      RSVD1,      NAND,       GMI,        DTV,        RSVD,       INPUT,  0x31d8),
+        PINGROUP(GMI_CS2_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31dc),
+        PINGROUP(GMI_CS3_N,       GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31e0),
+        PINGROUP(GMI_CS4_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31e4),
+        PINGROUP(GMI_CS6_N,       GMI,      NAND,       NAND_ALT,   GMI,        SATA,       RSVD,       INPUT,  0x31e8),
+        PINGROUP(GMI_CS7_N,       GMI,      NAND,       NAND_ALT,   GMI,        GMI_ALT,    RSVD,       INPUT,  0x31ec),
+        PINGROUP(GMI_AD0,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f0),
+        PINGROUP(GMI_AD1,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f4),
+        PINGROUP(GMI_AD2,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f8),
+        PINGROUP(GMI_AD3,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31fc),
+        PINGROUP(GMI_AD4,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3200),
+        PINGROUP(GMI_AD5,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3204),
+        PINGROUP(GMI_AD6,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3208),
+        PINGROUP(GMI_AD7,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x320c),
+        PINGROUP(GMI_AD8,         GMI,      PWM0,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3210),
+        PINGROUP(GMI_AD9,         GMI,      PWM1,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3214),
+        PINGROUP(GMI_AD10,        GMI,      PWM2,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3218),
+        PINGROUP(GMI_AD11,        GMI,      PWM3,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x321c),
+        PINGROUP(GMI_AD12,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3220),
+        PINGROUP(GMI_AD13,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3224),
+        PINGROUP(GMI_AD14,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3228),
+        PINGROUP(GMI_AD15,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x322c),
+        PINGROUP(GMI_A16,         GMI,      UARTD,      SPI4,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x3230),
+        PINGROUP(GMI_A17,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3234),
+        PINGROUP(GMI_A18,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3238),
+        PINGROUP(GMI_A19,         GMI,      UARTD,      SPI4,       GMI,        RSVD3,      RSVD,       INPUT,  0x323c),
+        PINGROUP(GMI_WR_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3240),
+        PINGROUP(GMI_OE_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3244),
+        PINGROUP(GMI_DQS,         GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3248),
+        PINGROUP(GMI_RST_N,       GMI,      NAND,       NAND_ALT,   GMI,        RSVD3,      RSVD,       INPUT,  0x324c),
+        PINGROUP(GEN2_I2C_SCL,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3250),
+        PINGROUP(GEN2_I2C_SDA,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3254),
+        PINGROUP(SDMMC4_CLK,      SDMMC4,   INVALID,    NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x3258),
+        PINGROUP(SDMMC4_CMD,      SDMMC4,   I2C3,       NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x325c),
+        PINGROUP(SDMMC4_DAT0,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3260),
+        PINGROUP(SDMMC4_DAT1,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3264),
+        PINGROUP(SDMMC4_DAT2,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3268),
+        PINGROUP(SDMMC4_DAT3,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x326c),
+        PINGROUP(SDMMC4_DAT4,     SDMMC4,   I2C3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3270),
+        PINGROUP(SDMMC4_DAT5,     SDMMC4,   VGP3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3274),
+        PINGROUP(SDMMC4_DAT6,     SDMMC4,   VGP4,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3278),
+        PINGROUP(SDMMC4_DAT7,     SDMMC4,   VGP5,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x327c),
+        PINGROUP(SDMMC4_RST_N,    SDMMC4,   VGP6,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3280),
+        PINGROUP(CAM_MCLK,        CAM,      VI,         INVALID,    VI_ALT2,    POPSDMMC4,  RSVD,       INPUT,  0x3284),
+        PINGROUP(GPIO_PCC1,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3288),
+        PINGROUP(GPIO_PBB0,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x328c),
+        PINGROUP(CAM_I2C_SCL,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3290),
+        PINGROUP(CAM_I2C_SDA,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3294),
+        PINGROUP(GPIO_PBB3,       CAM,      VGP3,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x3298),
+        PINGROUP(GPIO_PBB4,       CAM,      VGP4,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x329c),
+        PINGROUP(GPIO_PBB5,       CAM,      VGP5,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a0),
+        PINGROUP(GPIO_PBB6,       CAM,      VGP6,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a4),
+        PINGROUP(GPIO_PBB7,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x32a8),
+        PINGROUP(GPIO_PCC2,       CAM,      I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32ac),
+        PINGROUP(JTAG_RTCK,       SYS,      RTCK,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b0),
+        PINGROUP(PWR_I2C_SCL,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b4),
+        PINGROUP(PWR_I2C_SDA,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b8),
+        PINGROUP(KB_ROW0,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32bc),
+        PINGROUP(KB_ROW1,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c0),
+        PINGROUP(KB_ROW2,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c4),
+        PINGROUP(KB_ROW3,         SYS,      KBC,        INVALID,    RSVD2,      INVALID,    RSVD,       INPUT,  0x32c8),
+        PINGROUP(KB_ROW4,         SYS,      KBC,        INVALID,    TRACE,      RSVD3,      RSVD,       INPUT,  0x32cc),
+        PINGROUP(KB_ROW5,         SYS,      KBC,        INVALID,    TRACE,      OWR,        RSVD,       INPUT,  0x32d0),
+        PINGROUP(KB_ROW6,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d4),
+        PINGROUP(KB_ROW7,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d8),
+        PINGROUP(KB_ROW8,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32dc),
+        PINGROUP(KB_ROW9,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e0),
+        PINGROUP(KB_ROW10,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e4),
+        PINGROUP(KB_ROW11,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e8),
+        PINGROUP(KB_ROW12,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32ec),
+        PINGROUP(KB_ROW13,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f0),
+        PINGROUP(KB_ROW14,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f4),
+        PINGROUP(KB_ROW15,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f8),
+        PINGROUP(KB_COL0,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x32fc),
+        PINGROUP(KB_COL1,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3300),
+        PINGROUP(KB_COL2,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3304),
+        PINGROUP(KB_COL3,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3308),
+        PINGROUP(KB_COL4,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x330c),
+        PINGROUP(KB_COL5,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3310),
+        PINGROUP(KB_COL6,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3314),
+        PINGROUP(KB_COL7,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3318),
+        PINGROUP(CLK_32K_OUT,     SYS,      BLINK,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x331c),
+        PINGROUP(SYS_CLK_REQ,     SYS,      SYSCLK,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3320),
+        PINGROUP(CORE_PWR_REQ,    SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3324),
+        PINGROUP(CPU_PWR_REQ,     SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3328),
+        PINGROUP(PWR_INT_N,       SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x332c),
+        PINGROUP(CLK_32K_IN,      SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3330),
+        PINGROUP(OWR,             SYS,      OWR,        RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3334),
+        PINGROUP(DAP1_FS,         AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3338),
+        PINGROUP(DAP1_DIN,        AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x333c),
+        PINGROUP(DAP1_DOUT,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3340),
+        PINGROUP(DAP1_SCLK,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3344),
+        PINGROUP(CLK1_REQ,        AUDIO,    DAP,        HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x3348),
+        PINGROUP(CLK1_OUT,        AUDIO,    EXTPERIPH1, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x334c),
+        PINGROUP(SPDIF_IN,        AUDIO,    SPDIF,      HDA,        INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3350),
+        PINGROUP(SPDIF_OUT,       AUDIO,    SPDIF,      RSVD1,      INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3354),
+        PINGROUP(DAP2_FS,         AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3358),
+        PINGROUP(DAP2_DIN,        AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x335c),
+        PINGROUP(DAP2_DOUT,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3360),
+        PINGROUP(DAP2_SCLK,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3364),
+        PINGROUP(SPI2_MOSI,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3368),
+        PINGROUP(SPI2_MISO,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x336c),
+        PINGROUP(SPI2_CS0_N,      AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3370),
+        PINGROUP(SPI2_SCK,        AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3374),
+        PINGROUP(SPI1_MOSI,       AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3378),
+        PINGROUP(SPI1_SCK,        AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x337c),
+        PINGROUP(SPI1_CS0_N,      AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3380),
+        PINGROUP(SPI1_MISO,       AUDIO,    INVALID,    SPI1,       INVALID,    RSVD3,      RSVD,       INPUT,  0x3384),
+        PINGROUP(SPI2_CS1_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x3388),
+        PINGROUP(SPI2_CS2_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x338c),
+        PINGROUP(SDMMC3_CLK,      SDMMC3,   UARTA,      PWM2,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3390),
+        PINGROUP(SDMMC3_CMD,      SDMMC3,   UARTA,      PWM3,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3394),
+        PINGROUP(SDMMC3_DAT0,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x3398),
+        PINGROUP(SDMMC3_DAT1,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x339c),
+        PINGROUP(SDMMC3_DAT2,     SDMMC3,   RSVD,       PWM1,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a0),
+        PINGROUP(SDMMC3_DAT3,     SDMMC3,   RSVD,       PWM0,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a4),
+        PINGROUP(SDMMC3_DAT4,     SDMMC3,   PWM1,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33a8),
+        PINGROUP(SDMMC3_DAT5,     SDMMC3,   PWM0,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33ac),
+        PINGROUP(SDMMC3_DAT6,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b0),
+        PINGROUP(SDMMC3_DAT7,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b4),
+        PINGROUP(PEX_L0_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33b8),
+        PINGROUP(PEX_L0_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33bc),
+        PINGROUP(PEX_L0_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c0),
+        PINGROUP(PEX_WAKE_N,      PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c4),
+        PINGROUP(PEX_L1_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c8),
+        PINGROUP(PEX_L1_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33cc),
+        PINGROUP(PEX_L1_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d0),
+        PINGROUP(PEX_L2_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d4),
+        PINGROUP(PEX_L2_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d8),
+        PINGROUP(PEX_L2_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33dc),
+        PINGROUP(HDMI_CEC,        SYS,      CEC,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x33e0),
+};
+
+void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
+                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+                int *pgdrive_max)
+{
+        *pg = tegra_soc_pingroups;
+        *pg_max = TEGRA_MAX_PINGROUP;
+        *pgdrive = tegra_soc_drive_pingroups;
+        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+}
+
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 1d201650d7a..ac35d2b7685 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -21,6 +21,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of_device.h>
 
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
@@ -33,8 +34,10 @@
 #define SLWR(reg)       (((reg) >> 28) & 0x3)
 #define SLWF(reg)       (((reg) >> 30) & 0x3)
 
-static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
-static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
+static const struct tegra_pingroup_desc *pingroups;
+static const struct tegra_drive_pingroup_desc *drive_pingroups;
+static int pingroup_max;
+static int drive_max;
 
 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@@ -97,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_VI] = "VI",
         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
         [TEGRA_MUX_XIO] = "XIO",
+        [TEGRA_MUX_BLINK] = "BLINK",
+        [TEGRA_MUX_CEC] = "CEC",
+        [TEGRA_MUX_CLK12] = "CLK12",
+        [TEGRA_MUX_DAP] = "DAP",
+        [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
+        [TEGRA_MUX_DDR] = "DDR",
+        [TEGRA_MUX_DEV3] = "DEV3",
+        [TEGRA_MUX_DTV] = "DTV",
+        [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
+        [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
+        [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
+        [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
+        [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
+        [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
+        [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
+        [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
+        [TEGRA_MUX_HDA] = "HDA",
+        [TEGRA_MUX_HSI] = "HSI",
+        [TEGRA_MUX_I2C4] = "I2C4",
+        [TEGRA_MUX_I2C5] = "I2C5",
+        [TEGRA_MUX_I2CPWR] = "I2CPWR",
+        [TEGRA_MUX_I2S0] = "I2S0",
+        [TEGRA_MUX_I2S1] = "I2S1",
+        [TEGRA_MUX_I2S2] = "I2S2",
+        [TEGRA_MUX_I2S3] = "I2S3",
+        [TEGRA_MUX_I2S4] = "I2S4",
+        [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
+        [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
+        [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
+        [TEGRA_MUX_PWM0] = "PWM0",
+        [TEGRA_MUX_PWM1] = "PWM2",
+        [TEGRA_MUX_PWM2] = "PWM2",
+        [TEGRA_MUX_PWM3] = "PWM3",
+        [TEGRA_MUX_SATA] = "SATA",
+        [TEGRA_MUX_SPI5] = "SPI5",
+        [TEGRA_MUX_SPI6] = "SPI6",
+        [TEGRA_MUX_SYSCLK] = "SYSCLK",
+        [TEGRA_MUX_VGP1] = "VGP1",
+        [TEGRA_MUX_VGP2] = "VGP2",
+        [TEGRA_MUX_VGP3] = "VGP3",
+        [TEGRA_MUX_VGP4] = "VGP4",
+        [TEGRA_MUX_VGP5] = "VGP5",
+        [TEGRA_MUX_VGP6] = "VGP6",
         [TEGRA_MUX_SAFE] = "<safe>",
 };
 
@@ -116,9 +162,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
 
 static DEFINE_SPINLOCK(mux_lock);
 
-static const char *pingroup_name(enum tegra_pingroup pg)
+static const char *pingroup_name(int pg)
 {
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return "<UNKNOWN>";
 
         return pingroups[pg].name;
@@ -189,10 +235,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
         int i;
         unsigned long reg;
         unsigned long flags;
-        enum tegra_pingroup pg = config->pingroup;
+        int pg = config->pingroup;
         enum tegra_mux_func func = config->func;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].mux_reg < 0)
@@ -230,13 +276,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
         return 0;
 }
 
-int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
-        enum tegra_tristate tristate)
+int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
 {
         unsigned long reg;
         unsigned long flags;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].tri_reg < 0)
@@ -255,13 +300,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
         return 0;
 }
 
-int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
-        enum tegra_pullupdown pupd)
+int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
 {
         unsigned long reg;
         unsigned long flags;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].pupd_reg < 0)
@@ -287,7 +331,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
 
 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
 {
-        enum tegra_pingroup pingroup = config->pingroup;
+        int pingroup = config->pingroup;
         enum tegra_mux_func func     = config->func;
         enum tegra_pullupdown pupd   = config->pupd;
         enum tegra_tristate tristate = config->tristate;
@@ -323,9 +367,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l
                 tegra_pinmux_config_pingroup(&config[i]);
 }
 
-static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
+static const char *drive_pinmux_name(int pg)
 {
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return "<UNKNOWN>";
 
         return drive_pingroups[pg].name;
@@ -352,12 +396,11 @@ static const char *slew_name(unsigned long val)
         return tegra_slew_names[val];
 }
 
-static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
-        enum tegra_hsm hsm)
+static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
@@ -377,12 +420,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
-        enum tegra_schmitt schmitt)
+static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
@@ -402,12 +444,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
-        enum tegra_drive drive)
+static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
@@ -425,12 +466,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_pull_down(int pg,
         enum tegra_pull_strength pull_down)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
@@ -448,12 +489,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_pull_up(int pg,
         enum tegra_pull_strength pull_up)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
@@ -471,12 +512,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_slew_rising(int pg,
         enum tegra_slew slew_rising)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
@@ -494,12 +535,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_slew_falling(int pg,
         enum tegra_slew slew_falling)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
@@ -517,7 +558,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
+static void tegra_drive_pinmux_config_pingroup(int pingroup,
                                           enum tegra_hsm hsm,
                                           enum tegra_schmitt schmitt,
                                           enum tegra_drive drive,
@@ -596,7 +637,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf
         for (i = 0; i < len; i++) {
                 int err;
                 c = config[i];
-                if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
+                if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
                         WARN_ON(1);
                         continue;
                 }
@@ -617,7 +658,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config
         for (i = 0; i < len; i++) {
                 int err;
                 if (config[i].pingroup < 0 ||
-                    config[i].pingroup >= TEGRA_MAX_PINGROUP) {
+                    config[i].pingroup >= pingroup_max) {
                         WARN_ON(1);
                         continue;
                 }
@@ -635,7 +676,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
 {
         int i;
         int err;
-        enum tegra_pingroup pingroup;
+        int pingroup;
 
         for (i = 0; i < len; i++) {
                 pingroup = config[i].pingroup;
@@ -654,7 +695,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
 {
         int i;
         int err;
-        enum tegra_pingroup pingroup;
+        int pingroup;
 
         for (i = 0; i < len; i++) {
                 pingroup = config[i].pingroup;
@@ -668,11 +709,36 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
         }
 }
 
+static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
+#endif
+        { },
+};
+
 static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
 {
         struct resource *res;
         int i;
         int config_bad = 0;
+        const struct of_device_id *match;
+
+        match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
+
+        if (match)
+                ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
+                        &drive_pingroups, &drive_max);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        else
+                /* no device tree available, so we must be on tegra20 */
+                tegra20_pinmux_init(&pingroups, &pingroup_max,
+                                        &drive_pingroups, &drive_max);
+#else
+        pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
+#endif
 
         for (i = 0; ; i++) {
                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@@ -681,7 +747,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
         }
         nbanks = i;
 
-        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+        for (i = 0; i < pingroup_max; i++) {
                 if (pingroups[i].tri_bank >= nbanks) {
                         dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
                         config_bad = 1;
@@ -698,7 +764,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
                 }
         }
 
-        for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+        for (i = 0; i < drive_max; i++) {
                 if (drive_pingroups[i].reg_bank >= nbanks) {
                         dev_err(&pdev->dev,
                                 "drive pingroup %d: bad reg_bank\n", i);
@@ -741,11 +807,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
         return 0;
 }
 
-static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
-        { .compatible = "nvidia,tegra20-pinmux", },
-        { },
-};
-
 static struct platform_driver tegra_pinmux_driver = {
         .driver         = {
                 .name   = "tegra-pinmux",
@@ -779,7 +840,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
         int i;
         int len;
 
-        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+        for (i = 0; i < pingroup_max; i++) {
                 unsigned long reg;
                 unsigned long tri;
                 unsigned long mux;
@@ -850,7 +911,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
         int i;
         int len;
 
-        for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+        for (i = 0; i < drive_max; i++) {
                 u32 reg;
 
                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 371869d8ea0..ff9e6b6c046 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32];
 #define pmc_readl(reg) \
         __raw_readl(reg_pmc_base + (reg))
 
-unsigned long clk_measure_input_freq(void)
+static unsigned long clk_measure_input_freq(void)
 {
         u32 clock_autodetect;
         clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
@@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = {
         .disable        = tegra2_clk_m_disable,
 };
 
-void tegra2_periph_reset_assert(struct clk *c)
-{
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, true);
-}
-
-void tegra2_periph_reset_deassert(struct clk *c)
-{
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, false);
-}
-
 /* super clock functions */
 /* "super clocks" on tegra have two-stage muxes and a clock skipping
  * super divider.  We will ignore the clock skipping divider, since we
@@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = {
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
 {
         u32 reg;
+        unsigned long flags;
+
+        spin_lock_irqsave(&c->spinlock, flags);
 
         delay = clamp(delay, 0, 15);
         reg = clk_readl(c->reg);
@@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
         reg |= SDMMC_CLK_INT_FB_SEL;
         reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
         clk_writel(reg, c->reg);
+
+        spin_unlock_irqrestore(&c->spinlock, flags);
 }
 
 /* External memory controller clock ops */
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 732c724008b..1d1acda4f3e 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -165,20 +165,28 @@ static struct irqaction tegra_timer_irq = {
 static void __init tegra_init_timer(void)
 {
         struct clk *clk;
-        unsigned long rate = clk_measure_input_freq();
+        unsigned long rate;
         int ret;
 
         clk = clk_get_sys("timer", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        if (IS_ERR(clk)) {
+                pr_warn("Unable to get timer clock."
+                        " Assuming 12Mhz input clock.\n");
+                rate = 12000000;
+        } else {
+                clk_enable(clk);
+                rate = clk_get_rate(clk);
+        }
 
         /*
          * rtc registers are used by read_persistent_clock, keep the rtc clock
          * enabled
          */
         clk = clk_get_sys("rtc-tegra", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        if (IS_ERR(clk))
+                pr_warn("Unable to get rtc-tegra clock\n");
+        else
+                clk_enable(clk);
 
 #ifdef CONFIG_HAVE_ARM_TWD
         twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index bf64e1e594e..f0726d48df2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -265,16 +265,20 @@
 #define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__CSPI3_MOSI     IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D3__CSPI3_MISO     IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__CSPI3_SCLK     IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D5__CSPI3_RDY      IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 3df04d944e4..9a584614e7e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
-obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
new file mode 100644
index 00000000000..06c19bb7bca
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/am33xx.h
@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+#define L4_SLOW_AM33XX_BASE     0x48000000
+
+#define AM33XX_SCM_BASE         0x44E10000
+#define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE        0x44E00000
+
+#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index eb73ab40e95..240a7b9fd94 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -59,6 +59,8 @@ struct clkops {
 #define RATE_IN_4430            (1 << 5)
 #define RATE_IN_TI816X          (1 << 6)
 #define RATE_IN_4460            (1 << 7)
+#define RATE_IN_AM33XX          (1 << 8)
+#define RATE_IN_TI814X          (1 << 9)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -84,7 +86,7 @@ struct clkops {
 struct clksel_rate {
         u32                     val;
         u8                      div;
-        u8                      flags;
+        u16                     flags;
 };
 
 /**
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 408a12f7920..6b51086fce1 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -69,6 +69,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap343x():   True for OMAP3430
  * cpu_is_omap443x():   True for OMAP4430
  * cpu_is_omap446x():   True for OMAP4460
+ * cpu_is_omap447x():   True for OMAP4470
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -78,6 +79,22 @@ static inline int is_omap ##class (void)		\
         return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
 }
 
+#define GET_AM_CLASS    ((omap_rev() >> 24) & 0xff)
+
+#define IS_AM_CLASS(class, id)                          \
+static inline int is_am ##class (void)                  \
+{                                                       \
+        return (GET_AM_CLASS == (id)) ? 1 : 0;          \
+}
+
+#define GET_TI_CLASS    ((omap_rev() >> 24) & 0xff)
+
+#define IS_TI_CLASS(class, id)                  \
+static inline int is_ti ##class (void)          \
+{                                                       \
+        return (GET_TI_CLASS == (id)) ? 1 : 0;  \
+}
+
 #define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
 
 #define IS_OMAP_SUBCLASS(subclass, id)                  \
@@ -92,12 +109,21 @@ static inline int is_ti ##subclass (void)		\
         return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
 }
 
+#define IS_AM_SUBCLASS(subclass, id)                    \
+static inline int is_am ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_CLASS(44xx, 0x44)
+IS_AM_CLASS(33xx, 0x33)
+
+IS_TI_CLASS(81xx, 0x81)
 
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
@@ -105,8 +131,11 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 IS_OMAP_SUBCLASS(446x, 0x446)
+IS_OMAP_SUBCLASS(447x, 0x447)
 
 IS_TI_SUBCLASS(816x, 0x816)
+IS_TI_SUBCLASS(814x, 0x814)
+IS_AM_SUBCLASS(335x, 0x335)
 
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -116,10 +145,15 @@ IS_TI_SUBCLASS(816x, 0x816)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_ti81xx()                 0
 #define cpu_is_ti816x()                 0
+#define cpu_is_ti814x()                 0
+#define cpu_is_am33xx()                 0
+#define cpu_is_am335x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
+#define cpu_is_omap447x()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -322,7 +356,11 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3530
 # undef cpu_is_omap3505
 # undef cpu_is_omap3517
+# undef cpu_is_ti81xx
 # undef cpu_is_ti816x
+# undef cpu_is_ti814x
+# undef cpu_is_am33xx
+# undef cpu_is_am335x
 # define cpu_is_omap3430()              is_omap3430()
 # define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
                                                 (!omap3_has_iva()) &&   \
@@ -339,16 +377,22 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                 !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti81xx()                is_ti81xx()
 # define cpu_is_ti816x()                is_ti816x()
+# define cpu_is_ti814x()                is_ti814x()
+# define cpu_is_am33xx()                is_am33xx()
+# define cpu_is_am335x()                is_am335x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
 # undef cpu_is_omap446x
+# undef cpu_is_omap447x
 # define cpu_is_omap44xx()              is_omap44xx()
 # define cpu_is_omap443x()              is_omap443x()
 # define cpu_is_omap446x()              is_omap446x()
+# define cpu_is_omap447x()              is_omap447x()
 # endif
 
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -386,15 +430,27 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define TI8168_REV_ES1_0        TI816X_CLASS
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
 
+#define TI814X_CLASS            0x81400034
+#define TI8148_REV_ES1_0        TI814X_CLASS
+#define TI8148_REV_ES2_0        (TI814X_CLASS | (0x1 << 8))
+#define TI8148_REV_ES2_1        (TI814X_CLASS | (0x2 << 8))
+
+#define AM335X_CLASS            0x33500034
+#define AM335X_REV_ES1_0        AM335X_CLASS
+
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
 #define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
 #define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
+#define OMAP4430_REV_ES2_3      (OMAP443X_CLASS | (0x23 << 8))
 
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
 
+#define OMAP447X_CLASS          0x44700044
+#define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
+
 void omap2_check_revision(void);
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e87efe1499b..e897978371c 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,6 +286,7 @@
 #include <plat/omap24xx.h>
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
-#include <plat/ti816x.h>
+#include <plat/ti81xx.h>
+#include <plat/am33xx.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 1234944a4da..0696bae1818 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -73,6 +73,9 @@
 #define OMAP4_L3_IO_OFFSET      0xb4000000
 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
 
+#define AM33XX_L4_WK_IO_OFFSET  0xb5000000
+#define AM33XX_L4_WK_IO_ADDRESS(pa)     IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
+
 #define OMAP4_L3_PER_IO_OFFSET  0xb1100000
 #define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
 
@@ -154,6 +157,15 @@
 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 
 /*
+ * ----------------------------------------------------------------------------
+ * AM33XX specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L4_WK_AM33XX_PHYS       L4_WK_AM33XX_BASE
+#define L4_WK_AM33XX_VIRT       (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
+#define L4_WK_AM33XX_SIZE       SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+
+/*
  * Need to look at the Size 4M for L4.
  * VPOM3430 was not working for Int controller
  */
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index b9e85886b9d..0d818acf391 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -35,6 +35,8 @@
 #define L4_EMU_34XX_BASE        0x54000000
 #define L3_34XX_BASE            0x68000000
 
+#define L4_WK_AM33XX_BASE       0x44C00000
+
 #define OMAP3430_32KSYNCT_BASE  0x48320000
 #define OMAP3430_CM_BASE        0x48004800
 #define OMAP3430_PRM_BASE       0x48306800
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 1ab9fd6abe6..6975ee3f521 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,10 +51,10 @@
 #define OMAP4_UART3_BASE        0x48020000
 #define OMAP4_UART4_BASE        0x4806e000
 
-/* TI816X serial ports */
-#define TI816X_UART1_BASE       0x48020000
-#define TI816X_UART2_BASE       0x48022000
-#define TI816X_UART3_BASE       0x48024000
+/* TI81XX serial ports */
+#define TI81XX_UART1_BASE       0x48020000
+#define TI81XX_UART2_BASE       0x48022000
+#define TI81XX_UART3_BASE       0x48024000
 
 /* AM3505/3517 UART4 */
 #define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
@@ -89,9 +89,9 @@
 #define OMAP4UART2              OMAP2UART2
 #define OMAP4UART3              43
 #define OMAP4UART4              44
-#define TI816XUART1             81
-#define TI816XUART2             82
-#define TI816XUART3             83
+#define TI81XXUART1             81
+#define TI81XXUART2             82
+#define TI81XXUART3             83
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti81xx.h
index 50510f5dda1..8f9843f7842 100644
--- a/arch/arm/plat-omap/include/plat/ti816x.h
+++ b/arch/arm/plat-omap/include/plat/ti81xx.h
@@ -1,5 +1,5 @@
 /*
- * This file contains the address data for various TI816X modules.
+ * This file contains the address data for various TI81XX modules.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
  *
@@ -13,15 +13,15 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __ASM_ARCH_TI816X_H
-#define __ASM_ARCH_TI816X_H
+#ifndef __ASM_ARCH_TI81XX_H
+#define __ASM_ARCH_TI81XX_H
 
-#define L4_SLOW_TI816X_BASE     0x48000000
+#define L4_SLOW_TI81XX_BASE     0x48000000
 
-#define TI816X_SCM_BASE         0x48140000
-#define TI816X_CTRL_BASE        TI816X_SCM_BASE
-#define TI816X_PRCM_BASE        0x48180000
+#define TI81XX_SCM_BASE         0x48140000
+#define TI81XX_CTRL_BASE        TI81XX_SCM_BASE
+#define TI81XX_PRCM_BASE        0x48180000
 
-#define TI816X_ARM_INTC_BASE    0x48200000
+#define TI81XX_ARM_INTC_BASE    0x48200000
 
-#endif /* __ASM_ARCH_TI816X_H */
+#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 2f472e989ec..6ee90495ca4 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -99,9 +99,9 @@ static inline void flush(void)
 #define DEBUG_LL_ZOOM(mach)                                             \
         _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
 
-#define DEBUG_LL_TI816X(p, mach)                                        \
-        _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,   \
-                TI816XUART##p)
+#define DEBUG_LL_TI81XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                TI81XXUART##p)
 
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -177,7 +177,10 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_ZOOM(omap_zoom3);
 
                 /* TI8168 base boards using UART3 */
-                DEBUG_LL_TI816X(3, ti8168evm);
+                DEBUG_LL_TI81XX(3, ti8168evm);
+
+                /* TI8148 base boards using UART1 */
+                DEBUG_LL_TI81XX(1, ti8148evm);
 
         } while (0);
 }
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 17d3c939775..c616385f27b 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -114,6 +114,7 @@ extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
 extern void am35x_musb_clear_irq(void);
 extern void am35x_set_mode(u8 musb_mode);
+extern void ti81xx_musb_phy_power(u8 on);
 
 /*
  * FIXME correct answer depends on hmc_mode,
@@ -273,6 +274,37 @@ static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
 #define CONF2_OTGPWRDN          (1 << 2)
 #define CONF2_DATPOL            (1 << 1)
 
+/* TI81XX specific definitions */
+#define USBCTRL0        0x620
+#define USBSTAT0        0x624
+
+/* TI816X PHY controls bits */
+#define TI816X_USBPHY0_NORMAL_MODE      (1 << 0)
+#define TI816X_USBPHY_REFCLK_OSC        (1 << 8)
+
+/* TI814X PHY controls bits */
+#define USBPHY_CM_PWRDN         (1 << 0)
+#define USBPHY_OTG_PWRDN        (1 << 1)
+#define USBPHY_CHGDET_DIS       (1 << 2)
+#define USBPHY_CHGDET_RSTRT     (1 << 3)
+#define USBPHY_SRCONDM          (1 << 4)
+#define USBPHY_SINKONDP         (1 << 5)
+#define USBPHY_CHGISINK_EN      (1 << 6)
+#define USBPHY_CHGVSRC_EN       (1 << 7)
+#define USBPHY_DMPULLUP         (1 << 8)
+#define USBPHY_DPPULLUP         (1 << 9)
+#define USBPHY_CDET_EXTCTL      (1 << 10)
+#define USBPHY_GPIO_MODE        (1 << 12)
+#define USBPHY_DPOPBUFCTL       (1 << 13)
+#define USBPHY_DMOPBUFCTL       (1 << 14)
+#define USBPHY_DPINPUT          (1 << 15)
+#define USBPHY_DMINPUT          (1 << 16)
+#define USBPHY_DPGPIO_PD        (1 << 17)
+#define USBPHY_DMGPIO_PD        (1 << 18)
+#define USBPHY_OTGVDET_EN       (1 << 19)
+#define USBPHY_OTGSESSEND_EN    (1 << 20)
+#define USBPHY_DATA_POLARITY    (1 << 23)
+
 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
 u32 omap1_usb1_init(unsigned nwires);
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 160eea15a6e..6a2abe67c8b 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -88,12 +88,20 @@ config S5P_GPIO_DRVSTR
 
 config SAMSUNG_GPIO_EXTRA
         int "Number of additional GPIO pins"
+        default 128 if SAMSUNG_GPIO_EXTRA128
+        default 64 if SAMSUNG_GPIO_EXTRA64
         default 0
         help
           Use additional GPIO space in addition to the GPIO's the SOC
           provides. This allows expanding the GPIO space for use with
           GPIO expanders.
 
+config SAMSUNG_GPIO_EXTRA64
+        bool
+
+config SAMSUNG_GPIO_EXTRA128
+        bool
+
 config S3C_GPIO_SPACE
         int "Space between gpio banks"
         default 0