1040 files changed, 41898 insertions, 11692 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 88c97bc7a6f..bf7273f3dc6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -19,13 +19,17 @@ config ARM
         select HAVE_KPROBES if (!XIP_KERNEL)
         select HAVE_KRETPROBES if (HAVE_KPROBES)
         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
+        select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
+        select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_LZO
         select HAVE_KERNEL_LZMA
+        select HAVE_IRQ_WORK
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
         select HAVE_REGS_AND_STACK_ACCESS_API
+        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -145,6 +149,9 @@ config ARCH_HAS_CPUFREQ
           and that the relevant menu configurations are displayed for
           it.
 
+config ARCH_HAS_CPU_IDLE_WAIT
+       def_bool y
+
 config GENERIC_HWEIGHT
         bool
         default y
@@ -510,6 +517,7 @@ config ARCH_MMP
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
         select PLAT_PXA
+        select SPARSE_IRQ
         help
           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
@@ -565,6 +573,7 @@ config ARCH_TEGRA
         select HAVE_CLK
         select COMMON_CLKDEV
         select ARCH_HAS_BARRIERS if CACHE_L2X0
+        select ARCH_HAS_CPUFREQ
         help
           This enables support for NVIDIA Tegra based systems (Tegra APX,
           Tegra 6xx and Tegra 2 series).
@@ -587,6 +596,7 @@ config ARCH_PXA
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
         select PLAT_PXA
+        select SPARSE_IRQ
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
@@ -678,8 +688,8 @@ config ARCH_S3C64XX
         help
           Samsung S3C64XX series based systems
 
-config ARCH_S5P6440
-        bool "Samsung S5P6440"
+config ARCH_S5P64X0
+        bool "Samsung S5P6440 S5P6450"
         select CPU_V6
         select GENERIC_GPIO
         select HAVE_CLK
@@ -688,7 +698,8 @@ config ARCH_S5P6440
         select HAVE_S3C2410_I2C
         select HAVE_S3C_RTC
         help
-          Samsung S5P6440 CPU based systems
+          Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
+          SMDK6450.
 
 config ARCH_S5P6442
         bool "Samsung S5P6442"
@@ -747,6 +758,15 @@ config ARCH_SHARK
           Support for the StrongARM based Digital DNARD machine, also known
           as "Shark" (<http://www.shark-linux.de/shark.html>).
 
+config ARCH_TCC_926
+        bool "Telechips TCC ARM926-based systems"
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_CLOCKEVENTS
+        help
+          Support for Telechips TCC ARM926-based systems.
+
 config ARCH_LH7A40X
         bool "Sharp LH7A40X"
         select CPU_ARM922T
@@ -812,7 +832,7 @@ config ARCH_OMAP
         select GENERIC_CLOCKEVENTS
         select ARCH_HAS_HOLES_MEMORYMODEL
         help
-          Support for TI's OMAP platform (OMAP1 and OMAP2).
+          Support for TI's OMAP platform (OMAP1/2/3/4).
 
 config PLAT_SPEAR
         bool "ST SPEAr"
@@ -915,6 +935,8 @@ source "arch/arm/plat-s5p/Kconfig"
 
 source "arch/arm/plat-spear/Kconfig"
 
+source "arch/arm/plat-tcc/Kconfig"
+
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"
@@ -928,7 +950,7 @@ if ARCH_S3C64XX
 source "arch/arm/mach-s3c64xx/Kconfig"
 endif
 
-source "arch/arm/mach-s5p6440/Kconfig"
+source "arch/arm/mach-s5p64x0/Kconfig"
 
 source "arch/arm/mach-s5p6442/Kconfig"
 
@@ -1002,7 +1024,7 @@ endif
 
 config ARM_ERRATA_411920
         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
-        depends on CPU_V6 && !SMP
+        depends on CPU_V6
         help
           Invalidation of the Instruction Cache operation can
           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
@@ -1101,6 +1123,20 @@ config ARM_ERRATA_720789
           invalidated are not, resulting in an incoherency in the system page
           tables. The workaround changes the TLB flushing routines to invalidate
           entries regardless of the ASID.
+
+config ARM_ERRATA_743622
+        bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 743622 Cortex-A9
+          (r2p0..r2p2) erratum. Under very rare conditions, a faulty
+          optimisation in the Cortex-A9 Store Buffer may lead to data
+          corruption. This workaround sets a specific bit in the diagnostic
+          register of the Cortex-A9 which disables the Store Buffer
+          optimisation, preventing the defect from occurring. This has no
+          visible impact on the overall performance or power consumption of the
+          processor.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1167,13 +1203,13 @@ source "kernel/time/Kconfig"
 
 config SMP
         bool "Symmetric Multi-Processing (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
-                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+        depends on EXPERIMENTAL
         depends on GENERIC_CLOCKEVENTS
+        depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
+                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
+                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
         select USE_GENERIC_SMP_HELPERS
-        select HAVE_ARM_SCU if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 ||\
-                 ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+        select HAVE_ARM_SCU
         help
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -1187,10 +1223,23 @@ config SMP
 
           See also <file:Documentation/i386/IO-APIC.txt>,
           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
-          <http://www.linuxdoc.org/docs.html#howto>.
+          <http://tldp.org/HOWTO/SMP-HOWTO.html>.
 
           If you don't know what to do here, say N.
 
+config SMP_ON_UP
+        bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        depends on SMP && !XIP && !THUMB2_KERNEL
+        default y
+        help
+          SMP kernels contain instructions which fail on non-SMP processors.
+          Enabling this option allows the kernel to modify itself to make
+          these instructions safe.  Disabling it allows about 1K of space
+          savings.
+
+          If you don't know what to do here, say Y.
+
 config HAVE_ARM_SCU
         bool
         depends on SMP
@@ -1241,12 +1290,9 @@ config HOTPLUG_CPU
 
 config LOCAL_TIMERS
         bool "Use local timer interrupts"
-        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
-                ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+        depends on SMP
         default y
-        select HAVE_ARM_TWD if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 || \
-                ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS
+        select HAVE_ARM_TWD
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1257,7 +1303,7 @@ source kernel/Kconfig.preempt
 
 config HZ
         int
-        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \
+        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
                 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
@@ -1463,6 +1509,20 @@ config UACCESS_WITH_MEMCPY
           However, if the CPU data cache is using a write-allocate mode,
           this option is unlikely to provide any performance gain.
 
+config SECCOMP
+        bool
+        prompt "Enable seccomp to safely compute untrusted bytecode"
+        ---help---
+          This kernel feature is useful for number crunching applications
+          that may need to compute untrusted bytecode during their
+          execution. By using pipes or other transports made available to
+          the process as file descriptors supporting the read/write
+          syscalls, it's possible to isolate those applications in
+          their own address space using seccomp. Once seccomp is
+          enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+          and the task is only allowed to execute a few safe syscalls
+          defined by each seccomp mode.
+
 config CC_STACKPROTECTOR
         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
         help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 91344af75f3..2fd0b99afc4 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -2,6 +2,20 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
+config STRICT_DEVMEM
+        bool "Filter access to /dev/mem"
+        depends on MMU
+        ---help---
+          If this option is disabled, you allow userspace (root) access to all
+          of memory, including kernel and userspace memory. Accidental
+          access to this is obviously disastrous, but specific access can
+          be used by people debugging the kernel.
+
+          If this option is switched on, the /dev/mem file only allows
+          userspace access to memory mapped peripherals.
+
+          If in doubt, say Y.
+
 # RMK wants arm kernels compiled with frame pointers or stack unwinding.
 # If you know what you are doing and are willing to live without stack
 # traces, you can get a slightly smaller kernel by setting this option to
@@ -27,6 +41,11 @@ config ARM_UNWIND
           the performance is not affected. Currently, this feature
           only works with EABI compilers. If unsure say Y.
 
+config OLD_MCOUNT
+        bool
+        depends on FUNCTION_TRACER && FRAME_POINTER
+        default y
+
 config DEBUG_USER
         bool "Verbose user fault messages"
         help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 59c1ce858fc..b87aed028ee 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_RPC)		:= rpc
 machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
-machine-$(CONFIG_ARCH_S5P6440)          := s5p6440
+machine-$(CONFIG_ARCH_S5P64X0)          := s5p64x0
 machine-$(CONFIG_ARCH_S5P6442)          := s5p6442
 machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
@@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
 machine-$(CONFIG_ARCH_STMP378X)         := stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)         := stmp37xx
+machine-$(CONFIG_ARCH_TCC8K)            := tcc8k
 machine-$(CONFIG_ARCH_TEGRA)            := tegra
 machine-$(CONFIG_ARCH_U300)             := u300
 machine-$(CONFIG_ARCH_U8500)            := ux500
@@ -202,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC)		:= mxc
 plat-$(CONFIG_ARCH_OMAP)        := omap
 plat-$(CONFIG_ARCH_S3C64XX)     := samsung
 plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
+plat-$(CONFIG_ARCH_TCC_926)     := tcc
 plat-$(CONFIG_PLAT_IOP)         := iop
 plat-$(CONFIG_PLAT_NOMADIK)     := nomadik
 plat-$(CONFIG_PLAT_ORION)       := orion
@@ -245,13 +247,14 @@ ifeq ($(FASTFPE),$(wildcard $(FASTFPE)))
 FASTFPE_OBJ     :=$(FASTFPE)/
 endif
 
-# If we have a machine-specific directory, then include it in the build.
-core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
-core-y                          += $(machdirs) $(platdirs)
 core-$(CONFIG_FPE_NWFPE)        += arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)      += $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)              += arch/arm/vfp/
 
+# If we have a machine-specific directory, then include it in the build.
+core-y                          += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
+core-y                          += $(machdirs) $(platdirs)
+
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
 
 libs-y                          := arch/arm/lib/ $(libs-y)
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 7dfa9a85bc0..ada6359160e 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq)
 
 /*
  * Routines to acknowledge, disable and enable interrupts
- *
- * Linux assumes that when we're done with an interrupt we need to
- * unmask it, in the same way we need to unmask an interrupt when
- * we first enable it.
- *
- * The GIC has a separate notion of "end of interrupt" to re-enable
- * an interrupt after handling, in order to support hardware
- * prioritisation.
- *
- * We can make the GIC behave in the way that Linux expects by making
- * our "acknowledge" routine disable the interrupt, then mark it as
- * complete.
  */
 static void gic_ack_irq(unsigned int irq)
 {
-        u32 mask = 1 << (irq % 32);
 
         spin_lock(&irq_controller_lock);
-        writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
         writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
         spin_unlock(&irq_controller_lock);
 }
diff --git a/arch/arm/common/icst.c b/arch/arm/common/icst.c
index 9a7f09cff30..2dc6da70ae5 100644
--- a/arch/arm/common/icst.c
+++ b/arch/arm/common/icst.c
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  *
  *  Support functions for calculating clocks/divisors for the ICST307
- *  clock generators.  See http://www.icst.com/ for more information
+ *  clock generators.  See http://www.idt.com/ for more information
  *  on these devices.
  *
  *  This is an almost identical implementation to the ICST525 clock generator.
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index 5ebbab6242a..8f0f86db360 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -146,8 +146,7 @@
 #define DESIGNER        0x41
 #define REVISION        0x0
 #define INTEG_CFG       0x0
-#define PERIPH_ID_VAL   ((PART << 0) | (DESIGNER << 12) \
-                          | (REVISION << 20) | (INTEG_CFG << 24))
+#define PERIPH_ID_VAL   ((PART << 0) | (DESIGNER << 12))
 
 #define PCELL_ID_VAL    0xb105f00d
 
@@ -1859,10 +1858,10 @@ int pl330_add(struct pl330_info *pi)
         regs = pi->base;
 
         /* Check if we can handle this DMAC */
-        if (get_id(pi, PERIPH_ID) != PERIPH_ID_VAL
+        if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL
            || get_id(pi, PCELL_ID) != PCELL_ID_VAL) {
                 dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n",
-                        readl(regs + PERIPH_ID), readl(regs + PCELL_ID));
+                        get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID));
                 return -EINVAL;
         }
 
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 517d50ddbeb..c0258a8c103 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -678,7 +678,7 @@ out:
  *      %-EBUSY         physical address already marked in-use.
  *      %0              successful.
  */
-static int
+static int __devinit
 __sa1111_probe(struct device *me, struct resource *mem, int irq)
 {
         struct sa1111 *sachip;
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index 9012004321d..c11af1e4bad 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -44,12 +44,12 @@ void reset_scoop(struct device *dev)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
 
-        iowrite16(0x0100, sdev->base + SCOOP_MCR);  // 00
-        iowrite16(0x0000, sdev->base + SCOOP_CDR);  // 04
-        iowrite16(0x0000, sdev->base + SCOOP_CCR);  // 10
-        iowrite16(0x0000, sdev->base + SCOOP_IMR);  // 18
-        iowrite16(0x00FF, sdev->base + SCOOP_IRM);  // 14
-        iowrite16(0x0000, sdev->base + SCOOP_ISR);  // 1C
+        iowrite16(0x0100, sdev->base + SCOOP_MCR);  /* 00 */
+        iowrite16(0x0000, sdev->base + SCOOP_CDR);  /* 04 */
+        iowrite16(0x0000, sdev->base + SCOOP_CCR);  /* 10 */
+        iowrite16(0x0000, sdev->base + SCOOP_IMR);  /* 18 */
+        iowrite16(0x00FF, sdev->base + SCOOP_IRM);  /* 14 */
+        iowrite16(0x0000, sdev->base + SCOOP_ISR);  /* 1C */
         iowrite16(0x0000, sdev->base + SCOOP_IRM);
 }
 
diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c
index b520e56216a..bef408f3d76 100644
--- a/arch/arm/common/uengine.c
+++ b/arch/arm/common/uengine.c
@@ -312,16 +312,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
                 b1 = (gpr_a[i] >> 8) & 0xff;
                 b0 = gpr_a[i] & 0xff;
 
-                // immed[@ai, (b1 << 8) | b0]
-                // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
+                /* immed[@ai, (b1 << 8) | b0] */
+                /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */
                 ucode[offset++] = 0xf0;
                 ucode[offset++] = (b1 >> 4);
                 ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
                 ucode[offset++] = (b0 << 2);
                 ucode[offset++] = 0x80 | i;
 
-                // immed_w1[@ai, (b3 << 8) | b2]
-                // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
+                /* immed_w1[@ai, (b3 << 8) | b2] */
+                /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */
                 ucode[offset++] = 0xf4;
                 ucode[offset++] = 0x40 | (b3 >> 4);
                 ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
@@ -340,16 +340,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
                 b1 = (gpr_b[i] >> 8) & 0xff;
                 b0 = gpr_b[i] & 0xff;
 
-                // immed[@bi, (b1 << 8) | b0]
-                // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
+                /* immed[@bi, (b1 << 8) | b0] */
+                /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */
                 ucode[offset++] = 0xf0;
                 ucode[offset++] = (b1 >> 4);
                 ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
                 ucode[offset++] = (i << 2) | 0x03;
                 ucode[offset++] = b0;
 
-                // immed_w1[@bi, (b3 << 8) | b2]
-                // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
+                /* immed_w1[@bi, (b3 << 8) | b2] */
+                /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */
                 ucode[offset++] = 0xf4;
                 ucode[offset++] = 0x40 | (b3 >> 4);
                 ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
@@ -357,7 +357,7 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
                 ucode[offset++] = b2;
         }
 
-        // ctx_arb[kill]
+        /* ctx_arb[kill] */
         ucode[offset++] = 0xe0;
         ucode[offset++] = 0x00;
         ucode[offset++] = 0x01;
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index f1bac70d6ce..9e90e6d7929 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -13,6 +13,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_AT91SAM9G20EK=y
+CONFIG_MACH_AT91SAM9G20EK_2MMC=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index ba6670556f7..cdc40c4b8c4 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -17,6 +17,8 @@ CONFIG_MODVERSIONS=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_ARCH_DAVINCI_DA830=y
 CONFIG_ARCH_DAVINCI_DA850=y
+CONFIG_MACH_MITYOMAPL138=y
+CONFIG_MACH_OMAPL138_HAWKBOARD=y
 CONFIG_DAVINCI_RESET_CLOCKS=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -79,6 +81,7 @@ CONFIG_I2C_DAVINCI=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DUMMY=y
 CONFIG_REGULATOR_TPS6507X=y
 CONFIG_FB=y
 CONFIG_FB_DA8XX=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index ccc9c9959b8..2f704281376 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -15,6 +15,7 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_OPENRD_BASE=y
diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig
index b2038b0e266..813cfb366c1 100644
--- a/arch/arm/configs/mx27_defconfig
+++ b/arch/arm/configs/mx27_defconfig
@@ -21,8 +21,14 @@ CONFIG_ARCH_MX2=y
 CONFIG_MACH_MX27=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_PCM038=y
+CONFIG_MACH_CPUIMX27=y
+CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
+CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
 CONFIG_MACH_MX27_3DS=y
+CONFIG_MACH_IMX27_VISSTRIM_M10=y
 CONFIG_MACH_IMX27LITE=y
+CONFIG_MACH_PCA100=y
+CONFIG_MACH_MXT_TD60=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 CONFIG_NO_HZ=y
@@ -76,7 +82,9 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=m
 # CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=m
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
@@ -85,19 +93,20 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_IMX=y
 CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
+CONFIG_SPI_IMX=y
 CONFIG_W1=y
 CONFIG_W1_MASTER_MXC=y
 CONFIG_W1_SLAVE_THERM=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_IMX=y
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
 CONFIG_FONT_8x8=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=m
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_ULPI=y
 CONFIG_MMC=y
 CONFIG_MMC_MXC=y
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/mx31pdk_defconfig b/arch/arm/configs/mx31pdk_defconfig
deleted file mode 100644
index 2d29329749e..00000000000
--- a/arch/arm/configs/mx31pdk_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_MXC=y
-# CONFIG_MACH_MX31ADS is not set
-CONFIG_MACH_MX31_3DS=y
-CONFIG_AEABI=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_LRO is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index 161f907b611..f0c339fd5d2 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -24,6 +24,7 @@ CONFIG_MACH_PCM043=y
 CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_KZM_ARM11_01=y
+CONFIG_MACH_EUKREA_CPUIMX35=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 CONFIG_NO_HZ=y
@@ -108,7 +109,6 @@ CONFIG_MMC=y
 CONFIG_MMC_MXC=y
 CONFIG_DMADEVICES=y
 # CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index a665ecbbe2b..163cfee7644 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -15,6 +15,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_ARCH_MXC=y
 CONFIG_ARCH_MX5=y
 CONFIG_MACH_MX51_BABBAGE=y
+CONFIG_MACH_MX51_3DS=y
+CONFIG_MACH_EUKREA_CPUIMX51=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -69,7 +71,6 @@ CONFIG_REALTEK_PHY=y
 CONFIG_NATIONAL_PHY=y
 CONFIG_STE10XP=y
 CONFIG_LSI_ET1011C_PHY=y
-CONFIG_FIXED_PHY=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_GPIO=y
 CONFIG_NET_ETHERNET=y
@@ -100,7 +101,6 @@ CONFIG_I2C_ALGOPCF=m
 CONFIG_I2C_ALGOPCA=m
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -117,13 +117,11 @@ CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
 CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
-CONFIG_INOTIFY=y
 CONFIG_QUOTA=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
@@ -136,6 +134,7 @@ CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
 CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
 CONFIG_CONFIGFS_FS=m
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -151,7 +150,6 @@ CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -159,7 +157,6 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_ARM_UNWIND is not set
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_KEYS=y
 CONFIG_SECURITYFS=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_LZO=y
diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig
deleted file mode 100644
index 56aebb69411..00000000000
--- a/arch/arm/configs/n8x0_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
-# CONFIG_OMAP_MCBSP is not set
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_MACH_NOKIA_N8X0=y
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x10C08000
-CONFIG_ZBOOT_ROM_BSS=0x10200000
-CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait"
-CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_OMAP2=y
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-# CONFIG_HWMON is not set
-CONFIG_MENELAUS=y
-CONFIG_REGULATOR=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_USB_MUSB_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DEBUG=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_EEM=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap2plus_defconfig
index 5db9a6be205..ccedde1371c 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -53,18 +53,18 @@ CONFIG_MACH_SBC3530=y
 CONFIG_MACH_OMAP_3630SDP=y
 CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+# CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200"
+CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
 CONFIG_KEXEC=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 CONFIG_FPE_NWFPE=y
 CONFIG_VFP=y
 CONFIG_NEON=y
@@ -87,23 +87,23 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
 CONFIG_BT_RFCOMM=y
 CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP=m
 CONFIG_BT_BNEP_MC_FILTER=y
 CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIUART=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIUART=m
 CONFIG_BT_HCIUART_H4=y
 CONFIG_BT_HCIUART_BCSP=y
 CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIBCM203X=y
-CONFIG_BT_HCIBPA10X=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
 CONFIG_MAC80211_RC_PID=y
 CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_MAC80211_LEDS=y
@@ -137,9 +137,11 @@ CONFIG_SMSC_PHY=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
-CONFIG_LIBERTAS=y
-CONFIG_LIBERTAS_USB=y
-CONFIG_LIBERTAS_SDIO=y
+CONFIG_KS8851=y
+CONFIG_KS8851_MLL=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
 CONFIG_LIBERTAS_DEBUG=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_ALI_M5632=y
@@ -201,8 +203,8 @@ CONFIG_FONTS=y
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
 CONFIG_LOGO=y
-CONFIG_SOUND=y
-CONFIG_SND=y
+CONFIG_SOUND=m
+CONFIG_SND=m
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 CONFIG_SND_VERBOSE_PRINTK=y
@@ -218,9 +220,9 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_OTG=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 CONFIG_USB_MUSB_DEBUG=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
@@ -276,12 +278,11 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-CONFIG_LOCK_STAT=y
+# CONFIG_LOCK_STAT is not set
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_LL=y
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_MICHAEL_MIC=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
deleted file mode 100644
index 14c1e18c648..00000000000
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ /dev/null
@@ -1,125 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP4=y
-# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
-# CONFIG_ARCH_OMAP2 is not set
-# CONFIG_ARCH_OMAP3 is not set
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_MACH_OMAP_4430SDP=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-# CONFIG_LOCAL_TIMERS is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_KS8851=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP24XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_TWL4030_CORE=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_TWL4030=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TWL4030=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V2=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_ARM_UNWIND is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/omap_generic_2420_defconfig b/arch/arm/configs/omap_generic_2420_defconfig
deleted file mode 100644
index ac08e51180d..00000000000
--- a/arch/arm/configs/omap_generic_2420_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x10C08000
-CONFIG_ZBOOT_ROM_BSS=0x10200000
-CONFIG_FPE_NWFPE=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_INOTIFY=y
-CONFIG_ROMFS_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index 9312ef9f9bf..5ca7a61f7c0 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -39,6 +39,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_ARM_CHARLCD=y
 CONFIG_NETDEVICES=y
 CONFIG_SMSC_PHY=y
 CONFIG_NET_ETHERNET=y
@@ -52,10 +53,13 @@ CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_VERSATILE=y
+CONFIG_SPI=y
+CONFIG_GPIOLIB=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
@@ -70,7 +74,13 @@ CONFIG_SND_ARMAACI=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
-CONFIG_INOTIFY=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_PL031=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_CRAMFS=y
@@ -80,6 +90,7 @@ CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index fb75192ee7e..fcaa6032805 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -38,6 +38,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_ARM_CHARLCD=y
 CONFIG_NETDEVICES=y
 CONFIG_SMSC_PHY=y
 CONFIG_NET_ETHERNET=y
@@ -51,10 +52,13 @@ CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_VERSATILE=y
+CONFIG_SPI=y
+CONFIG_GPIOLIB=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
@@ -69,7 +73,13 @@ CONFIG_SND_ARMAACI=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
-CONFIG_INOTIFY=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_PL031=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_CRAMFS=y
@@ -79,6 +89,7 @@ CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p64x0_defconfig
index 0b0266c6d32..2993ecd3514 100644
--- a/arch/arm/configs/s5p6440_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -5,10 +5,11 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5P6440=y
+CONFIG_ARCH_S5P64X0=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDK6440=y
+CONFIG_MACH_SMDK6450=y
 CONFIG_CPU_32v6K=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 46e5e074726..c1c252cdca6 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -28,26 +28,9 @@ CONFIG_CPU_IDLE=y
 CONFIG_FPE_NWFPE=y
 CONFIG_PM=y
 # CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MISC_DEVICES is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
@@ -58,7 +41,6 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
-CONFIG_POWER_SUPPLY=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
@@ -66,24 +48,10 @@ CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_SOC=y
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
 CONFIG_MMC_ARMMMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
 CONFIG_RTC_DRV_COH901331=y
@@ -93,12 +61,11 @@ CONFIG_COH901318=y
 CONFIG_FUSE_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c8a1c..062b58c029a 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,39 @@
         .long   9999b,9001f;                    \
         .popsection
 
+#ifdef CONFIG_SMP
+#define ALT_SMP(instr...)                                       \
+9998:   instr
+#define ALT_UP(instr...)                                        \
+        .pushsection ".alt.smp.init", "a"                       ;\
+        .long   9998b                                           ;\
+        instr                                                   ;\
+        .popsection
+#define ALT_UP_B(label)                                 \
+        .equ    up_b_offset, label - 9998b                      ;\
+        .pushsection ".alt.smp.init", "a"                       ;\
+        .long   9998b                                           ;\
+        b       . + up_b_offset                                 ;\
+        .popsection
+#else
+#define ALT_SMP(instr...)
+#define ALT_UP(instr...) instr
+#define ALT_UP_B(label) b label
+#endif
+
 /*
  * SMP data memory barrier
  */
         .macro  smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-        dmb
+        ALT_SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-        mcr     p15, 0, r0, c7, c10, 5  @ dmb
+        ALT_SMP(mcr     p15, 0, r0, c7, c10, 5) @ dmb
+#else
+#error Incompatible SMP platform
 #endif
+        ALT_UP(nop)
 #endif
         .endm
 
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24058d..3acd8fa25e3 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *      MM Cache Management
@@ -156,6 +156,12 @@
  *      Please note that the implementation of these, and the required
  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
  *
+ *      flush_icache_all()
+ *
+ *              Unconditionally clean and invalidate the entire icache.
+ *              Currently only needed for cache-v6.S and cache-v7.S, see
+ *              __flush_icache_all for the generic implementation.
+ *
  *      flush_kern_all()
  *
  *              Unconditionally clean and invalidate the entire cache.
@@ -206,6 +212,7 @@
  */
 
 struct cpu_cache_fns {
+        void (*flush_icache_all)(void);
         void (*flush_kern_all)(void);
         void (*flush_user_all)(void);
         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -227,6 +234,7 @@ struct cpu_cache_fns {
 
 extern struct cpu_cache_fns cpu_cache;
 
+#define __cpuc_flush_icache_all         cpu_cache.flush_icache_all
 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
@@ -246,6 +254,7 @@ extern struct cpu_cache_fns cpu_cache;
 
 #else
 
+#define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
@@ -253,6 +262,7 @@ extern struct cpu_cache_fns cpu_cache;
 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 #define __cpuc_flush_dcache_area        __glue(_CACHE,_flush_kern_dcache_area)
 
+extern void __cpuc_flush_icache_all(void);
 extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
@@ -291,6 +301,37 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 /*
  * Convert calls to our calling convention.
  */
+
+/* Invalidate I-cache */
+#define __flush_icache_all_generic()                                    \
+        asm("mcr        p15, 0, %0, c7, c5, 0"                          \
+            : : "r" (0));
+
+/* Invalidate I-cache inner shareable */
+#define __flush_icache_all_v7_smp()                                     \
+        asm("mcr        p15, 0, %0, c7, c1, 0"                          \
+            : : "r" (0));
+
+/*
+ * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
+ * will fall through to use __flush_icache_all_generic.
+ */
+#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) ||               \
+        defined(CONFIG_SMP_ON_UP)
+#define __flush_icache_preferred        __cpuc_flush_icache_all
+#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
+#define __flush_icache_preferred        __flush_icache_all_v7_smp
+#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
+#define __flush_icache_preferred        __cpuc_flush_icache_all
+#else
+#define __flush_icache_preferred        __flush_icache_all_generic
+#endif
+
+static inline void __flush_icache_all(void)
+{
+        __flush_icache_preferred();
+}
+
 #define flush_cache_all()               __cpuc_flush_kern_all()
 
 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
@@ -366,21 +407,6 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 extern void flush_dcache_page(struct page *);
 
-static inline void __flush_icache_all(void)
-{
-#ifdef CONFIG_ARM_ERRATA_411920
-        extern void v6_icache_inval_all(void);
-        v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-        asm("mcr        p15, 0, %0, c7, c1, 0   @ invalidate I-cache inner shareable\n"
-            :
-            : "r" (0));
-#else
-        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
-            :
-            : "r" (0));
-#endif
-}
 static inline void flush_kernel_vmap_range(void *addr, int size)
 {
         if ((cache_is_vivt() || cache_is_vipt_aliasing()))
@@ -405,9 +431,6 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
 static inline void flush_kernel_dcache_page(struct page *page)
 {
-        /* highmem pages are always flushed upon kunmap already */
-        if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
-                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
 
 #define flush_dcache_mmap_lock(mapping) \
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
index d3a4c2cb9f2..c023db09fcc 100644
--- a/arch/arm/include/asm/cachetype.h
+++ b/arch/arm/include/asm/cachetype.h
@@ -6,6 +6,7 @@
 #define CACHEID_VIPT_ALIASING           (1 << 2)
 #define CACHEID_VIPT                    (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
 #define CACHEID_ASID_TAGGED             (1 << 3)
+#define CACHEID_VIPT_I_ALIASING         (1 << 4)
 
 extern unsigned int cacheid;
 
@@ -14,15 +15,18 @@ extern unsigned int cacheid;
 #define cache_is_vipt_nonaliasing()     cacheid_is(CACHEID_VIPT_NONALIASING)
 #define cache_is_vipt_aliasing()        cacheid_is(CACHEID_VIPT_ALIASING)
 #define icache_is_vivt_asid_tagged()    cacheid_is(CACHEID_ASID_TAGGED)
+#define icache_is_vipt_aliasing()       cacheid_is(CACHEID_VIPT_I_ALIASING)
 
 /*
  * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
  * Mask out support which will never be present on newer CPUs.
  * - v6+ is never VIVT
- * - v7+ VIPT never aliases
+ * - v7+ VIPT never aliases on D-side
  */
 #if __LINUX_ARM_ARCH__ >= 7
-#define __CACHEID_ARCH_MIN      (CACHEID_VIPT_NONALIASING | CACHEID_ASID_TAGGED)
+#define __CACHEID_ARCH_MIN      (CACHEID_VIPT_NONALIASING |\
+                                 CACHEID_ASID_TAGGED |\
+                                 CACHEID_VIPT_I_ALIASING)
 #elif __LINUX_ARM_ARCH__ >= 6
 #define __CACHEID_ARCH_MIN      (~CACHEID_VIVT)
 #else
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 5747a8baa41..8bb66bca2e3 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -127,4 +127,8 @@ struct mm_struct;
 extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
 
+extern int vectors_user_mapping(void);
+#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping()
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+
 #endif
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index 103f7ee9731..f89515adac6 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -2,12 +2,30 @@
 #define _ASM_ARM_FTRACE
 
 #ifdef CONFIG_FUNCTION_TRACER
-#define MCOUNT_ADDR             ((long)(mcount))
+#define MCOUNT_ADDR             ((unsigned long)(__gnu_mcount_nc))
 #define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
 
 #ifndef __ASSEMBLY__
 extern void mcount(void);
 extern void __gnu_mcount_nc(void);
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+struct dyn_arch_ftrace {
+#ifdef CONFIG_OLD_MCOUNT
+        bool    old_mcount;
+#endif
+};
+
+static inline unsigned long ftrace_call_adjust(unsigned long addr)
+{
+        /* With Thumb-2, the recorded addresses have the lsb set */
+        return addr & ~1;
+}
+
+extern void ftrace_caller_old(void);
+extern void ftrace_call_old(void);
+#endif
+
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 212e47828c7..7ecd793b8f5 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -21,18 +21,6 @@
 #define TRACER_RUNNING          BIT(TRACER_RUNNING_BIT)
 #define TRACER_CYCLE_ACC        BIT(TRACER_CYCLE_ACC_BIT)
 
-struct tracectx {
-        unsigned int    etb_bufsz;
-        void __iomem    *etb_regs;
-        void __iomem    *etm_regs;
-        unsigned long   flags;
-        int             ncmppairs;
-        int             etm_portsz;
-        struct device   *dev;
-        struct clk      *emu_clk;
-        struct mutex    mutex;
-};
-
 #define TRACER_TIMEOUT 10000
 
 #define etm_writel(t, v, x) \
@@ -112,10 +100,10 @@ struct tracectx {
 
 /* ETM status register, "ETM Architecture", 3.3.2 */
 #define ETMR_STATUS             (0x10)
-#define ETMST_OVERFLOW          (1 << 0)
-#define ETMST_PROGBIT           (1 << 1)
-#define ETMST_STARTSTOP         (1 << 2)
-#define ETMST_TRIGGER           (1 << 3)
+#define ETMST_OVERFLOW          BIT(0)
+#define ETMST_PROGBIT           BIT(1)
+#define ETMST_STARTSTOP         BIT(2)
+#define ETMST_TRIGGER           BIT(3)
 
 #define etm_progbit(t)          (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)
 #define etm_started(t)          (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)
@@ -123,7 +111,7 @@ struct tracectx {
 
 #define ETMR_TRACEENCTRL2       0x1c
 #define ETMR_TRACEENCTRL        0x24
-#define ETMTE_INCLEXCL          (1 << 24)
+#define ETMTE_INCLEXCL          BIT(24)
 #define ETMR_TRACEENEVT         0x20
 #define ETMCTRL_OPTS            (ETMCTRL_DO_CPRT | \
                                 ETMCTRL_DATA_DO_ADDR | \
@@ -146,12 +134,12 @@ struct tracectx {
 #define ETBR_CTRL               0x20
 #define ETBR_FORMATTERCTRL      0x304
 #define ETBFF_ENFTC             1
-#define ETBFF_ENFCONT           (1 << 1)
-#define ETBFF_FONFLIN           (1 << 4)
-#define ETBFF_MANUAL_FLUSH      (1 << 6)
-#define ETBFF_TRIGIN            (1 << 8)
-#define ETBFF_TRIGEVT           (1 << 9)
-#define ETBFF_TRIGFL            (1 << 10)
+#define ETBFF_ENFCONT           BIT(1)
+#define ETBFF_FONFLIN           BIT(4)
+#define ETBFF_MANUAL_FLUSH      BIT(6)
+#define ETBFF_TRIGIN            BIT(8)
+#define ETBFF_TRIGEVT           BIT(9)
+#define ETBFF_TRIGFL            BIT(10)
 
 #define etb_writel(t, v, x) \
         (__raw_writel((v), (t)->etb_regs + (x)))
diff --git a/arch/arm/include/asm/hardware/icst.h b/arch/arm/include/asm/hardware/icst.h
index 10382a3dcec..794220b087d 100644
--- a/arch/arm/include/asm/hardware/icst.h
+++ b/arch/arm/include/asm/hardware/icst.h
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  *
  *  Support functions for calculating clocks/divisors for the ICST
- *  clock generators.  See http://www.icst.com/ for more information
+ *  clock generators.  See http://www.idt.com/ for more information
  *  on these devices.
  */
 #ifndef ASMARM_HARDWARE_ICST_H
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
new file mode 100644
index 00000000000..4d8ae9d67ab
--- /dev/null
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -0,0 +1,133 @@
+#ifndef _ARM_HW_BREAKPOINT_H
+#define _ARM_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+
+struct task_struct;
+
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+
+struct arch_hw_breakpoint_ctrl {
+                u32 __reserved  : 9,
+                mismatch        : 1,
+                                : 9,
+                len             : 8,
+                type            : 2,
+                privilege       : 2,
+                enabled         : 1;
+};
+
+struct arch_hw_breakpoint {
+        u32     address;
+        u32     trigger;
+        struct perf_event *suspended_wp;
+        struct arch_hw_breakpoint_ctrl ctrl;
+};
+
+static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
+{
+        return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
+                (ctrl.privilege << 1) | ctrl.enabled;
+}
+
+static inline void decode_ctrl_reg(u32 reg,
+                                   struct arch_hw_breakpoint_ctrl *ctrl)
+{
+        ctrl->enabled   = reg & 0x1;
+        reg >>= 1;
+        ctrl->privilege = reg & 0x3;
+        reg >>= 2;
+        ctrl->type      = reg & 0x3;
+        reg >>= 2;
+        ctrl->len       = reg & 0xff;
+        reg >>= 17;
+        ctrl->mismatch  = reg & 0x1;
+}
+
+/* Debug architecture numbers. */
+#define ARM_DEBUG_ARCH_RESERVED 0       /* In case of ptrace ABI updates. */
+#define ARM_DEBUG_ARCH_V6       1
+#define ARM_DEBUG_ARCH_V6_1     2
+#define ARM_DEBUG_ARCH_V7_ECP14 3
+#define ARM_DEBUG_ARCH_V7_MM    4
+
+/* Breakpoint */
+#define ARM_BREAKPOINT_EXECUTE  0
+
+/* Watchpoints */
+#define ARM_BREAKPOINT_LOAD     1
+#define ARM_BREAKPOINT_STORE    2
+
+/* Privilege Levels */
+#define ARM_BREAKPOINT_PRIV     1
+#define ARM_BREAKPOINT_USER     2
+
+/* Lengths */
+#define ARM_BREAKPOINT_LEN_1    0x1
+#define ARM_BREAKPOINT_LEN_2    0x3
+#define ARM_BREAKPOINT_LEN_4    0xf
+#define ARM_BREAKPOINT_LEN_8    0xff
+
+/* Limits */
+#define ARM_MAX_BRP             16
+#define ARM_MAX_WRP             16
+#define ARM_MAX_HBP_SLOTS       (ARM_MAX_BRP + ARM_MAX_WRP)
+
+/* DSCR method of entry bits. */
+#define ARM_DSCR_MOE(x)                 ((x >> 2) & 0xf)
+#define ARM_ENTRY_BREAKPOINT            0x1
+#define ARM_ENTRY_ASYNC_WATCHPOINT      0x2
+#define ARM_ENTRY_SYNC_WATCHPOINT       0xa
+
+/* DSCR monitor/halting bits. */
+#define ARM_DSCR_HDBGEN         (1 << 14)
+#define ARM_DSCR_MDBGEN         (1 << 15)
+
+/* opcode2 numbers for the co-processor instructions. */
+#define ARM_OP2_BVR             4
+#define ARM_OP2_BCR             5
+#define ARM_OP2_WVR             6
+#define ARM_OP2_WCR             7
+
+/* Base register numbers for the debug registers. */
+#define ARM_BASE_BVR            64
+#define ARM_BASE_BCR            80
+#define ARM_BASE_WVR            96
+#define ARM_BASE_WCR            112
+
+/* Accessor macros for the debug registers. */
+#define ARM_DBG_READ(M, OP2, VAL) do {\
+        asm volatile("mrc p14, 0, %0, c0," #M ", " #OP2 : "=r" (VAL));\
+} while (0)
+
+#define ARM_DBG_WRITE(M, OP2, VAL) do {\
+        asm volatile("mcr p14, 0, %0, c0," #M ", " #OP2 : : "r" (VAL));\
+} while (0)
+
+struct notifier_block;
+struct perf_event;
+struct pmu;
+
+extern struct pmu perf_ops_bp;
+extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
+                                  int *gen_len, int *gen_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+                                           unsigned long val, void *data);
+
+extern u8 arch_get_debug_arch(void);
+extern u8 arch_get_max_wp_len(void);
+extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
+
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+int hw_breakpoint_slots(int type);
+
+#else
+static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
+
+#endif  /* CONFIG_HAVE_HW_BREAKPOINT */
+#endif  /* __KERNEL__ */
+#endif  /* _ARM_HW_BREAKPOINT_H */
diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h
index 90831f6f5f5..5586b7c8ef6 100644
--- a/arch/arm/include/asm/hw_irq.h
+++ b/arch/arm/include/asm/hw_irq.h
@@ -24,4 +24,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags);
 #define IRQF_PROBE      (1 << 1)
 #define IRQF_NOAUTOEN   (1 << 2)
 
+#define ARCH_IRQ_INIT_FLAGS     (IRQ_NOREQUEST | IRQ_NOPROBE)
+
 #endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1261b1f928d..815efa2d4e0 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -294,6 +294,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+extern int devmem_is_allowed(unsigned long pfn);
 #endif
 
 /*
diff --git a/arch/arm/include/asm/ioctls.h b/arch/arm/include/asm/ioctls.h
index 0b30894b548..9c962981612 100644
--- a/arch/arm/include/asm/ioctls.h
+++ b/arch/arm/include/asm/ioctls.h
@@ -1,89 +1,8 @@
 #ifndef __ASM_ARM_IOCTLS_H
 #define __ASM_ARM_IOCTLS_H
 
-#include <asm/ioctl.h>
-
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-
-#define TCGETS          0x5401
-#define TCSETS          0x5402
-#define TCSETSW         0x5403
-#define TCSETSF         0x5404
-#define TCGETA          0x5405
-#define TCSETA          0x5406
-#define TCSETAW         0x5407
-#define TCSETAF         0x5408
-#define TCSBRK          0x5409
-#define TCXONC          0x540A
-#define TCFLSH          0x540B
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-#define TIOCGPGRP       0x540F
-#define TIOCSPGRP       0x5410
-#define TIOCOUTQ        0x5411
-#define TIOCSTI         0x5412
-#define TIOCGWINSZ      0x5413
-#define TIOCSWINSZ      0x5414
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define FIONREAD        0x541B
-#define TIOCINQ         FIONREAD
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-#define FIONBIO         0x5421
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TCGETS2         _IOR('T',0x2A, struct termios2)
-#define TCSETS2         _IOW('T',0x2B, struct termios2)
-#define TCSETSW2        _IOW('T',0x2C, struct termios2)
-#define TCSETSF2        _IOW('T',0x2D, struct termios2)
-#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
-#define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
-
-#define TIOCGRS485      0x542E
-#define TIOCSRS485      0x542F
-
-#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
-#define FIOCLEX         0x5451
-#define FIOASYNC        0x5452
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
 #define FIOQSIZE        0x545E
 
-/* Used for packet mode */
-#define TIOCPKT_DATA             0
-#define TIOCPKT_FLUSHREAD        1
-#define TIOCPKT_FLUSHWRITE       2
-#define TIOCPKT_STOP             4
-#define TIOCPKT_START            8
-#define TIOCPKT_NOSTOP          16
-#define TIOCPKT_DOSTOP          32
-#define TIOCPKT_IOCTL           64
-
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+#include <asm-generic/ioctls.h>
 
 #endif
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 6d09974e664..1e6cca55c75 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -10,66 +10,85 @@
  */
 #if __LINUX_ARM_ARCH__ >= 6
 
-#define raw_local_irq_save(x)                                   \
-        ({                                                      \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_save\n"     \
-        "cpsid  i"                                              \
-        : "=r" (x) : : "memory", "cc");                         \
-        })
+static inline unsigned long arch_local_irq_save(void)
+{
+        unsigned long flags;
+
+        asm volatile(
+                "       mrs     %0, cpsr        @ arch_local_irq_save\n"
+                "       cpsid   i"
+                : "=r" (flags) : : "memory", "cc");
+        return flags;
+}
+
+static inline void arch_local_irq_enable(void)
+{
+        asm volatile(
+                "       cpsie i                 @ arch_local_irq_enable"
+                :
+                :
+                : "memory", "cc");
+}
+
+static inline void arch_local_irq_disable(void)
+{
+        asm volatile(
+                "       cpsid i                 @ arch_local_irq_disable"
+                :
+                :
+                : "memory", "cc");
+}
 
-#define raw_local_irq_enable()  __asm__("cpsie i        @ __sti" : : : "memory", "cc")
-#define raw_local_irq_disable() __asm__("cpsid i        @ __cli" : : : "memory", "cc")
 #define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
 #define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
-
 #else
 
 /*
  * Save the current interrupt enable state & disable IRQs
  */
-#define raw_local_irq_save(x)                                   \
-        ({                                                      \
-                unsigned long temp;                             \
-                (void) (&temp == &x);                           \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_save\n"     \
-"       orr     %1, %0, #128\n"                                 \
-"       msr     cpsr_c, %1"                                     \
-        : "=r" (x), "=r" (temp)                                 \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
-        
+static inline unsigned long arch_local_irq_save(void)
+{
+        unsigned long flags, temp;
+
+        asm volatile(
+                "       mrs     %0, cpsr        @ arch_local_irq_save\n"
+                "       orr     %1, %0, #128\n"
+                "       msr     cpsr_c, %1"
+                : "=r" (flags), "=r" (temp)
+                :
+                : "memory", "cc");
+        return flags;
+}
+
 /*
  * Enable IRQs
  */
-#define raw_local_irq_enable()                                  \
-        ({                                                      \
-                unsigned long temp;                             \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_enable\n"   \
-"       bic     %0, %0, #128\n"                                 \
-"       msr     cpsr_c, %0"                                     \
-        : "=r" (temp)                                           \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
+static inline void arch_local_irq_enable(void)
+{
+        unsigned long temp;
+        asm volatile(
+                "       mrs     %0, cpsr        @ arch_local_irq_enable\n"
+                "       bic     %0, %0, #128\n"
+                "       msr     cpsr_c, %0"
+                : "=r" (temp)
+                :
+                : "memory", "cc");
+}
 
 /*
  * Disable IRQs
  */
-#define raw_local_irq_disable()                                 \
-        ({                                                      \
-                unsigned long temp;                             \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_irq_disable\n"  \
-"       orr     %0, %0, #128\n"                                 \
-"       msr     cpsr_c, %0"                                     \
-        : "=r" (temp)                                           \
-        :                                                       \
-        : "memory", "cc");                                      \
-        })
+static inline void arch_local_irq_disable(void)
+{
+        unsigned long temp;
+        asm volatile(
+                "       mrs     %0, cpsr        @ arch_local_irq_disable\n"
+                "       orr     %0, %0, #128\n"
+                "       msr     cpsr_c, %0"
+                : "=r" (temp)
+                :
+                : "memory", "cc");
+}
 
 /*
  * Enable FIQs
@@ -106,27 +125,31 @@
 /*
  * Save the current interrupt enable state.
  */
-#define raw_local_save_flags(x)                                 \
-        ({                                                      \
-        __asm__ __volatile__(                                   \
-        "mrs    %0, cpsr                @ local_save_flags"     \
-        : "=r" (x) : : "memory", "cc");                         \
-        })
+static inline unsigned long arch_local_save_flags(void)
+{
+        unsigned long flags;
+        asm volatile(
+                "       mrs     %0, cpsr        @ local_save_flags"
+                : "=r" (flags) : : "memory", "cc");
+        return flags;
+}
 
 /*
  * restore saved IRQ & FIQ state
  */
-#define raw_local_irq_restore(x)                                \
-        __asm__ __volatile__(                                   \
-        "msr    cpsr_c, %0              @ local_irq_restore\n"  \
-        :                                                       \
-        : "r" (x)                                               \
-        : "memory", "cc")
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+        asm volatile(
+                "       msr     cpsr_c, %0      @ local_irq_restore"
+                :
+                : "r" (flags)
+                : "memory", "cc");
+}
 
-#define raw_irqs_disabled_flags(flags)  \
-({                                      \
-        (int)((flags) & PSR_I_BIT);     \
-})
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+        return flags & PSR_I_BIT;
+}
 
 #endif
 #endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 8a0dd18ba64..d97a964207f 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -16,18 +16,15 @@ struct sys_timer;
 
 struct machine_desc {
         /*
-         * Note! The first four elements are used
+         * Note! The first two elements are used
          * by assembler code in head.S, head-common.S
          */
         unsigned int            nr;             /* architecture number  */
-        unsigned int            nr_irqs;        /* number of IRQs */
-        unsigned int            phys_io;        /* start of physical io */
-        unsigned int            io_pg_offst;    /* byte offset for io 
-                                                 * page tabe entry      */
-
         const char              *name;          /* architecture name    */
         unsigned long           boot_params;    /* tagged list          */
 
+        unsigned int            nr_irqs;        /* number of IRQs */
+
         unsigned int            video_start;    /* start of video RAM   */
         unsigned int            video_end;      /* end of video RAM     */
 
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a0b3cac0547..71605d9f8e4 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,7 +18,6 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/proc-fns.h>
-#include <asm-generic/mm_hooks.h>
 
 void __check_kvm_seq(struct mm_struct *mm);
 
@@ -134,4 +133,32 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #define deactivate_mm(tsk,mm)   do { } while (0)
 #define activate_mm(prev,next)  switch_mm(prev, next, NULL)
 
+/*
+ * We are inserting a "fake" vma for the user-accessible vector page so
+ * gdb and friends can get to it through ptrace and /proc/<pid>/mem.
+ * But we also want to remove it before the generic code gets to see it
+ * during process exit or the unmapping of it would  cause total havoc.
+ * (the macro is used as remove_vma() is static to mm/mmap.c)
+ */
+#define arch_exit_mmap(mm) \
+do { \
+        struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \
+        if (high_vma) { \
+                BUG_ON(high_vma->vm_next);  /* it should be last */ \
+                if (high_vma->vm_prev) \
+                        high_vma->vm_prev->vm_next = NULL; \
+                else \
+                        mm->mmap = NULL; \
+                rb_erase(&high_vma->vm_rb, &mm->mm_rb); \
+                mm->mmap_cache = NULL; \
+                mm->map_count--; \
+                remove_vma(high_vma); \
+        } \
+} while (0)
+
+static inline void arch_dup_mmap(struct mm_struct *oldmm,
+                                 struct mm_struct *mm)
+{
+}
+
 #endif
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index e4dfa69abb6..cbb0bc295d2 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -7,20 +7,27 @@
 
 struct unwind_table;
 
-struct mod_arch_specific
-{
 #ifdef CONFIG_ARM_UNWIND
-        Elf_Shdr *unw_sec_init;
-        Elf_Shdr *unw_sec_devinit;
-        Elf_Shdr *unw_sec_core;
-        Elf_Shdr *sec_init_text;
-        Elf_Shdr *sec_devinit_text;
-        Elf_Shdr *sec_core_text;
-        struct unwind_table *unwind_init;
-        struct unwind_table *unwind_devinit;
-        struct unwind_table *unwind_core;
-#endif
+struct arm_unwind_mapping {
+        Elf_Shdr *unw_sec;
+        Elf_Shdr *sec_text;
+        struct unwind_table *unwind;
+};
+enum {
+        ARM_SEC_INIT,
+        ARM_SEC_DEVINIT,
+        ARM_SEC_CORE,
+        ARM_SEC_EXIT,
+        ARM_SEC_DEVEXIT,
+        ARM_SEC_MAX,
+};
+struct mod_arch_specific {
+        struct arm_unwind_mapping map[ARM_SEC_MAX];
 };
+#else
+struct mod_arch_specific {
+};
+#endif
 
 /*
  * Include the ARM architecture version.
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index b5799a3b711..c4aa4e8c6af 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,18 +12,6 @@
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
 
-/*
- * NOP: on *most* (read: all supported) ARM platforms, the performance
- * counter interrupts are regular interrupts and not an NMI. This
- * means that when we receive the interrupt we can call
- * perf_event_do_pending() that handles all of the work with
- * interrupts disabled.
- */
-static inline void
-set_perf_event_pending(void)
-{
-}
-
 /* ARM performance counters start from 1 (in the cp15 accesses) so use the
  * same indexes here for consistency. */
 #define PERF_EVENT_INDEX_OFFSET 1
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index e90b167ea84..a9672e8406a 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -278,9 +278,24 @@ extern struct page *empty_zero_page;
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
-#define set_pte_at(mm,addr,ptep,pteval) do { \
-        set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
- } while (0)
+#if __LINUX_ARM_ARCH__ < 6
+static inline void __sync_icache_dcache(pte_t pteval)
+{
+}
+#else
+extern void __sync_icache_dcache(pte_t pteval);
+#endif
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pteval)
+{
+        if (addr >= TASK_SIZE)
+                set_pte_ext(ptep, pteval, 0);
+        else {
+                __sync_icache_dcache(pteval);
+                set_pte_ext(ptep, pteval, PTE_EXT_NG);
+        }
+}
 
 /*
  * The following only work if pte_present() is true.
@@ -290,8 +305,13 @@ extern struct page *empty_zero_page;
 #define pte_write(pte)          (pte_val(pte) & L_PTE_WRITE)
 #define pte_dirty(pte)          (pte_val(pte) & L_PTE_DIRTY)
 #define pte_young(pte)          (pte_val(pte) & L_PTE_YOUNG)
+#define pte_exec(pte)           (pte_val(pte) & L_PTE_EXEC)
 #define pte_special(pte)        (0)
 
+#define pte_present_user(pte) \
+        ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \
+         (L_PTE_PRESENT | L_PTE_USER))
+
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 7bed3daf83b..67357baaeee 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -19,6 +19,7 @@
 
 #ifdef __KERNEL__
 
+#include <asm/hw_breakpoint.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
 
@@ -41,6 +42,9 @@ struct debug_entry {
 struct debug_info {
         int                     nsaved;
         struct debug_entry      bp[2];
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        struct perf_event       *hbp[ARM_MAX_HBP_SLOTS];
+#endif
 };
 
 struct thread_struct {
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 7ce15eb15f7..783d50f3261 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -29,6 +29,8 @@
 #define PTRACE_SETCRUNCHREGS    26
 #define PTRACE_GETVFPREGS       27
 #define PTRACE_SETVFPREGS       28
+#define PTRACE_GETHBPREGS       29
+#define PTRACE_SETHBPREGS       30
 
 /*
  * PSR bits
diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h
new file mode 100644
index 00000000000..52b156b341f
--- /dev/null
+++ b/arch/arm/include/asm/seccomp.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_ARM_SECCOMP_H
+#define _ASM_ARM_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#endif /* _ASM_ARM_SECCOMP_H */
diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h
new file mode 100644
index 00000000000..6a9307d6490
--- /dev/null
+++ b/arch/arm/include/asm/smp_mpidr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()                                         \
+        ({                                                              \
+                unsigned int cpunum;                                    \
+                __asm__("\n"                                            \
+                        "1:     mrc p15, 0, %0, c0, c0, 5\n"            \
+                        "       .pushsection \".alt.smp.init\", \"a\"\n"\
+                        "       .long   1b\n"                           \
+                        "       mov     %0, #0\n"                       \
+                        "       .popsection"                            \
+                        : "=r" (cpunum));                               \
+                cpunum &= 0x0F;                                         \
+        })
+
+#endif
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e6215305544..f24c1b9e211 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -7,15 +7,40 @@
 
 #include <asm/cputype.h>
 
+/*
+ * Return true if we are running on a SMP platform
+ */
+static inline bool is_smp(void)
+{
+#ifndef CONFIG_SMP
+        return false;
+#elif defined(CONFIG_SMP_ON_UP)
+        extern unsigned int smp_on_up;
+        return !!smp_on_up;
+#else
+        return true;
+#endif
+}
+
 /* all SMP configurations have the extended CPUID registers */
 static inline int tlb_ops_need_broadcast(void)
 {
+        if (!is_smp())
+                return 0;
+
         return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
+#define cache_ops_need_broadcast()      0
+#else
 static inline int cache_ops_need_broadcast(void)
 {
+        if (!is_smp())
+                return 0;
+
         return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 8ba1ccf82a0..1120f18a6b1 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -85,6 +85,10 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                        struct pt_regs *),
                      int sig, int code, const char *name);
 
+void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
+                                       struct pt_regs *),
+                     int sig, int code, const char *name);
+
 #define xchg(ptr,x) \
         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
@@ -325,6 +329,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 extern void disable_hlt(void);
 extern void enable_hlt(void);
 
+void cpu_idle_wait(void);
+
 #include <asm-generic/cmpxchg-local.h>
 
 #if __LINUX_ARM_ARCH__ < 6
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 763e29fa853..7b5cc8dae06 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -144,6 +144,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_FREEZE              19
 #define TIF_RESTORE_SIGMASK     20
+#define TIF_SECCOMP             21
 
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
@@ -153,6 +154,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
+#define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546ae72d..ce7378ea15a 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags    (TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
 # define v6wbi_always_flags     (-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp     (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
                          TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up      (TLB_WB | TLB_DCLEAN | TLB_BTB | \
                          TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
-#endif
 
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags   v7wbi_tlb_flags
-# define v7wbi_always_flags     v7wbi_tlb_flags
+
+# ifdef CONFIG_SMP_ON_UP
+#  define v7wbi_possible_flags  (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
+#  define v7wbi_always_flags    (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
+# elif defined(CONFIG_SMP)
+#  define v7wbi_possible_flags  v7wbi_tlb_flags_smp
+#  define v7wbi_always_flags    v7wbi_tlb_flags_smp
+# else
+#  define v7wbi_possible_flags  v7wbi_tlb_flags_up
+#  define v7wbi_always_flags    v7wbi_tlb_flags_up
+# endif
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
@@ -560,12 +570,20 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
- * back to the page.
+ * back to the page. On ARMv6 and later, the cache coherency is handled via
+ * the set_pte_at() function.
  */
+#if __LINUX_ARM_ARCH__ < 6
 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
         pte_t *ptep);
+#else
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+                                    unsigned long addr, pte_t *ptep)
+{
+}
+#endif
 
 #endif
 
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 980b78e3132..5b9b268f4fb 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_KGDB)		+= kgdb.o
 obj-$(CONFIG_ARM_UNWIND)        += unwind.o
 obj-$(CONFIG_HAVE_TCM)          += tcm.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += hw_breakpoint.o
 
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 8214bfebfac..e5e1e538767 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -165,6 +165,8 @@ EXPORT_SYMBOL(_find_next_bit_be);
 #endif
 
 #ifdef CONFIG_FUNCTION_TRACER
+#ifdef CONFIG_OLD_MCOUNT
 EXPORT_SYMBOL(mcount);
+#endif
 EXPORT_SYMBOL(__gnu_mcount_nc);
 #endif
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 85f2a019f77..82da6617213 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -102,8 +102,6 @@ int main(void)
   DEFINE(SIZEOF_MACHINE_DESC,   sizeof(struct machine_desc));
   DEFINE(MACHINFO_TYPE,         offsetof(struct machine_desc, nr));
   DEFINE(MACHINFO_NAME,         offsetof(struct machine_desc, name));
-  DEFINE(MACHINFO_PHYSIO,       offsetof(struct machine_desc, phys_io));
-  DEFINE(MACHINFO_PGOFFIO,      offsetof(struct machine_desc, io_pg_offst));
   BLANK();
   DEFINE(PROC_INFO_SZ,          sizeof(struct proc_info_list));
   DEFINE(PROCINFO_INITFUNC,     offsetof(struct proc_info_list, __cpu_flush));
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index a38b4879441..a0f07521ca8 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -22,11 +22,11 @@
 #if defined(CONFIG_DEBUG_ICEDCC)
                 @@ debug using ARM EmbeddedICE DCC channel
 
-#if defined(CONFIG_CPU_V6)
-
-                .macro  addruart, rx, tmp
+                .macro  addruart, rp, rv
                 .endm
 
+#if defined(CONFIG_CPU_V6)
+
                 .macro  senduart, rd, rx
                 mcr     p14, 0, \rd, c0, c5, 0
                 .endm
@@ -51,9 +51,6 @@
 
 #elif defined(CONFIG_CPU_V7)
 
-                .macro  addruart, rx, tmp
-                .endm
-
                 .macro  senduart, rd, rx
                 mcr     p14, 0, \rd, c0, c5, 0
                 .endm
@@ -71,9 +68,6 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 
 #elif defined(CONFIG_CPU_XSCALE)
 
-                .macro  addruart, rx, tmp
-                .endm
-
                 .macro  senduart, rd, rx
                 mcr     p14, 0, \rd, c8, c0, 0
                 .endm
@@ -98,9 +92,6 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 
 #else
 
-                .macro  addruart, rx, tmp
-                .endm
-
                 .macro  senduart, rd, rx
                 mcr     p14, 0, \rd, c1, c0, 0
                 .endm
@@ -130,6 +121,22 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 #include <mach/debug-macro.S>
 #endif  /* CONFIG_DEBUG_ICEDCC */
 
+#ifdef CONFIG_MMU
+                .macro  addruart_current, rx, tmp1, tmp2
+                addruart        \tmp1, \tmp2
+                mrc             p15, 0, \rx, c1, c0
+                tst             \rx, #1
+                moveq           \rx, \tmp1
+                movne           \rx, \tmp2
+                .endm
+
+#else /* !CONFIG_MMU */
+                .macro  addruart_current, rx, tmp1, tmp2
+                addruart        \rx, \tmp1
+                .endm
+
+#endif /* CONFIG_MMU */
+
 /*
  * Useful debugging routines
  */
@@ -164,7 +171,7 @@ ENDPROC(printhex2)
                 .ltorg
 
 ENTRY(printascii)
-                addruart r3, r1
+                addruart_current r3, r1, r2
                 b       2f
 1:              waituart r2, r3
                 senduart r1, r3
@@ -180,7 +187,7 @@ ENTRY(printascii)
 ENDPROC(printascii)
 
 ENTRY(printch)
-                addruart r3, r1
+                addruart_current r3, r1, r2
                 mov     r1, r0
                 mov     r0, #0
                 b       1b
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a7640..c09e3573c5d 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -46,7 +46,8 @@
          * this macro assumes that irqstat (r6) and base (r5) are
          * preserved from get_irqnr_and_base above
          */
-        test_for_ipi r0, r6, r5, lr
+        ALT_SMP(test_for_ipi r0, r6, r5, lr)
+        ALT_UP_B(9997f)
         movne   r0, sp
         adrne   lr, BSYM(1b)
         bne     do_IPI
@@ -57,6 +58,7 @@
         adrne   lr, BSYM(1b)
         bne     do_local_timer
 #endif
+9997:
 #endif
 
         .endm
@@ -965,11 +967,8 @@ kuser_cmpxchg_fixup:
         beq     1b
         rsbs    r0, r3, #0
         /* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-        b       __kuser_memory_barrier
-#else
-        usr_ret lr
-#endif
+        ALT_SMP(b       __kuser_memory_barrier)
+        ALT_UP(usr_ret  lr)
 
 #endif
 
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 7885722bdf4..8bfa98757cd 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -129,30 +129,58 @@ ENDPROC(ret_from_fork)
  * clobber the ip register.  This is OK because the ARM calling convention
  * allows it to be clobbered in subroutines and doesn't use it to hold
  * parameters.)
+ *
+ * When using dynamic ftrace, we patch out the mcount call by a "mov r0, r0"
+ * for the mcount case, and a "pop {lr}" for the __gnu_mcount_nc case (see
+ * arch/arm/kernel/ftrace.c).
  */
+
+#ifndef CONFIG_OLD_MCOUNT
+#if (__GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))
+#error Ftrace requires CONFIG_FRAME_POINTER=y with GCC older than 4.4.0.
+#endif
+#endif
+
 #ifdef CONFIG_DYNAMIC_FTRACE
-ENTRY(mcount)
+ENTRY(__gnu_mcount_nc)
+        mov     ip, lr
+        ldmia   sp!, {lr}
+        mov     pc, ip
+ENDPROC(__gnu_mcount_nc)
+
+ENTRY(ftrace_caller)
         stmdb   sp!, {r0-r3, lr}
         mov     r0, lr
         sub     r0, r0, #MCOUNT_INSN_SIZE
+        ldr     r1, [sp, #20]
 
-        .globl mcount_call
-mcount_call:
+        .global ftrace_call
+ftrace_call:
         bl      ftrace_stub
-        ldr     lr, [fp, #-4]                   @ restore lr
-        ldmia   sp!, {r0-r3, pc}
+        ldmia   sp!, {r0-r3, ip, lr}
+        mov     pc, ip
+ENDPROC(ftrace_caller)
 
-ENTRY(ftrace_caller)
+#ifdef CONFIG_OLD_MCOUNT
+ENTRY(mcount)
+        stmdb   sp!, {lr}
+        ldr     lr, [fp, #-4]
+        ldmia   sp!, {pc}
+ENDPROC(mcount)
+
+ENTRY(ftrace_caller_old)
         stmdb   sp!, {r0-r3, lr}
         ldr     r1, [fp, #-4]
         mov     r0, lr
         sub     r0, r0, #MCOUNT_INSN_SIZE
 
-        .globl ftrace_call
-ftrace_call:
+        .globl ftrace_call_old
+ftrace_call_old:
         bl      ftrace_stub
         ldr     lr, [fp, #-4]                   @ restore lr
         ldmia   sp!, {r0-r3, pc}
+ENDPROC(ftrace_caller_old)
+#endif
 
 #else
 
@@ -160,7 +188,7 @@ ENTRY(__gnu_mcount_nc)
         stmdb   sp!, {r0-r3, lr}
         ldr     r0, =ftrace_trace_function
         ldr     r2, [r0]
-        adr     r0, ftrace_stub
+        adr     r0, .Lftrace_stub
         cmp     r0, r2
         bne     gnu_trace
         ldmia   sp!, {r0-r3, ip, lr}
@@ -170,11 +198,19 @@ gnu_trace:
         ldr     r1, [sp, #20]                   @ lr of instrumented routine
         mov     r0, lr
         sub     r0, r0, #MCOUNT_INSN_SIZE
-        mov     lr, pc
+        adr     lr, BSYM(1f)
         mov     pc, r2
+1:
         ldmia   sp!, {r0-r3, ip, lr}
         mov     pc, ip
+ENDPROC(__gnu_mcount_nc)
 
+#ifdef CONFIG_OLD_MCOUNT
+/*
+ * This is under an ifdef in order to force link-time errors for people trying
+ * to build with !FRAME_POINTER with a GCC which doesn't use the new-style
+ * mcount.
+ */
 ENTRY(mcount)
         stmdb   sp!, {r0-r3, lr}
         ldr     r0, =ftrace_trace_function
@@ -193,12 +229,15 @@ trace:
         mov     pc, r2
         ldr     lr, [fp, #-4]                   @ restore lr
         ldmia   sp!, {r0-r3, pc}
+ENDPROC(mcount)
+#endif
 
 #endif /* CONFIG_DYNAMIC_FTRACE */
 
-        .globl ftrace_stub
-ftrace_stub:
+ENTRY(ftrace_stub)
+.Lftrace_stub:
         mov     pc, lr
+ENDPROC(ftrace_stub)
 
 #endif /* CONFIG_FUNCTION_TRACER */
 
@@ -295,7 +334,6 @@ ENTRY(vector_swi)
 
         get_thread_info tsk
         adr     tbl, sys_call_table             @ load syscall table pointer
-        ldr     ip, [tsk, #TI_FLAGS]            @ check for syscall tracing
 
 #if defined(CONFIG_OABI_COMPAT)
         /*
@@ -312,8 +350,20 @@ ENTRY(vector_swi)
         eor     scno, scno, #__NR_SYSCALL_BASE  @ check OS number
 #endif
 
+        ldr     r10, [tsk, #TI_FLAGS]           @ check for syscall tracing
         stmdb   sp!, {r4, r5}                   @ push fifth and sixth args
-        tst     ip, #_TIF_SYSCALL_TRACE         @ are we tracing syscalls?
+
+#ifdef CONFIG_SECCOMP
+        tst     r10, #_TIF_SECCOMP
+        beq     1f
+        mov     r0, scno
+        bl      __secure_computing      
+        add     r0, sp, #S_R0 + S_OFF           @ pointer to regs
+        ldmia   r0, {r0 - r3}                   @ have to reload r0 - r3
+1:
+#endif
+
+        tst     r10, #_TIF_SYSCALL_TRACE                @ are we tracing syscalls?
         bne     __sys_trace
 
         cmp     scno, #NR_syscalls              @ check upper syscall limit
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 33c7077174d..11db62806a1 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -30,6 +30,21 @@
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Alexander Shishkin");
 
+/*
+ * ETM tracer state
+ */
+struct tracectx {
+        unsigned int    etb_bufsz;
+        void __iomem    *etb_regs;
+        void __iomem    *etm_regs;
+        unsigned long   flags;
+        int             ncmppairs;
+        int             etm_portsz;
+        struct device   *dev;
+        struct clk      *emu_clk;
+        struct mutex    mutex;
+};
+
 static struct tracectx tracer;
 
 static inline bool trace_isrunning(struct tracectx *t)
@@ -314,6 +329,7 @@ static const struct file_operations etb_fops = {
         .read = etb_read,
         .open = etb_open,
         .release = etb_release,
+        .llseek = no_llseek,
 };
 
 static struct miscdevice etb_miscdev = {
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index 0298286ad4a..971ac8c36ea 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -2,102 +2,194 @@
  * Dynamic function tracing support.
  *
  * Copyright (C) 2008 Abhishek Sagar <sagar.abhishek@gmail.com>
+ * Copyright (C) 2010 Rabin Vincent <rabin@rab.in>
  *
  * For licencing details, see COPYING.
  *
  * Defines low-level handling of mcount calls when the kernel
  * is compiled with the -pg flag. When using dynamic ftrace, the
- * mcount call-sites get patched lazily with NOP till they are
- * enabled. All code mutation routines here take effect atomically.
+ * mcount call-sites get patched with NOP till they are enabled.
+ * All code mutation routines here are called under stop_machine().
  */
 
 #include <linux/ftrace.h>
+#include <linux/uaccess.h>
 
 #include <asm/cacheflush.h>
 #include <asm/ftrace.h>
 
-#define PC_OFFSET      8
-#define BL_OPCODE      0xeb000000
-#define BL_OFFSET_MASK 0x00ffffff
+#ifdef CONFIG_THUMB2_KERNEL
+#define NOP             0xeb04f85d      /* pop.w {lr} */
+#else
+#define NOP             0xe8bd4000      /* pop {lr} */
+#endif
 
-static unsigned long bl_insn;
-static const unsigned long NOP = 0xe1a00000; /* mov r0, r0 */
+#ifdef CONFIG_OLD_MCOUNT
+#define OLD_MCOUNT_ADDR ((unsigned long) mcount)
+#define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old)
 
-unsigned char *ftrace_nop_replace(void)
+#define OLD_NOP         0xe1a00000      /* mov r0, r0 */
+
+static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec)
 {
-        return (char *)&NOP;
+        return rec->arch.old_mcount ? OLD_NOP : NOP;
 }
 
+static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
+{
+        if (!rec->arch.old_mcount)
+                return addr;
+
+        if (addr == MCOUNT_ADDR)
+                addr = OLD_MCOUNT_ADDR;
+        else if (addr == FTRACE_ADDR)
+                addr = OLD_FTRACE_ADDR;
+
+        return addr;
+}
+#else
+static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec)
+{
+        return NOP;
+}
+
+static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
+{
+        return addr;
+}
+#endif
+
 /* construct a branch (BL) instruction to addr */
-unsigned char *ftrace_call_replace(unsigned long pc, unsigned long addr)
+#ifdef CONFIG_THUMB2_KERNEL
+static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
 {
+        unsigned long s, j1, j2, i1, i2, imm10, imm11;
+        unsigned long first, second;
         long offset;
 
-        offset = (long)addr - (long)(pc + PC_OFFSET);
+        offset = (long)addr - (long)(pc + 4);
+        if (offset < -16777216 || offset > 16777214) {
+                WARN_ON_ONCE(1);
+                return 0;
+        }
+
+        s       = (offset >> 24) & 0x1;
+        i1      = (offset >> 23) & 0x1;
+        i2      = (offset >> 22) & 0x1;
+        imm10   = (offset >> 12) & 0x3ff;
+        imm11   = (offset >>  1) & 0x7ff;
+
+        j1 = (!i1) ^ s;
+        j2 = (!i2) ^ s;
+
+        first = 0xf000 | (s << 10) | imm10;
+        second = 0xd000 | (j1 << 13) | (j2 << 11) | imm11;
+
+        return (second << 16) | first;
+}
+#else
+static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+{
+        long offset;
+
+        offset = (long)addr - (long)(pc + 8);
         if (unlikely(offset < -33554432 || offset > 33554428)) {
                 /* Can't generate branches that far (from ARM ARM). Ftrace
                  * doesn't generate branches outside of kernel text.
                  */
                 WARN_ON_ONCE(1);
-                return NULL;
+                return 0;
         }
-        offset = (offset >> 2) & BL_OFFSET_MASK;
-        bl_insn = BL_OPCODE | offset;
-        return (unsigned char *)&bl_insn;
-}
 
-int ftrace_modify_code(unsigned long pc, unsigned char *old_code,
-                       unsigned char *new_code)
-{
-        unsigned long err = 0, replaced = 0, old, new;
+        offset = (offset >> 2) & 0x00ffffff;
 
-        old = *(unsigned long *)old_code;
-        new = *(unsigned long *)new_code;
+        return 0xeb000000 | offset;
+}
+#endif
 
-        __asm__ __volatile__ (
-                "1:  ldr    %1, [%2]  \n"
-                "    cmp    %1, %4    \n"
-                "2:  streq  %3, [%2]  \n"
-                "    cmpne  %1, %3    \n"
-                "    movne  %0, #2    \n"
-                "3:\n"
+static int ftrace_modify_code(unsigned long pc, unsigned long old,
+                              unsigned long new)
+{
+        unsigned long replaced;
 
-                ".pushsection .fixup, \"ax\"\n"
-                "4:  mov  %0, #1  \n"
-                "    b    3b      \n"
-                ".popsection\n"
+        if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE))
+                return -EFAULT;
 
-                ".pushsection __ex_table, \"a\"\n"
-                "    .long 1b, 4b \n"
-                "    .long 2b, 4b \n"
-                ".popsection\n"
+        if (replaced != old)
+                return -EINVAL;
 
-                : "=r"(err), "=r"(replaced)
-                : "r"(pc), "r"(new), "r"(old), "0"(err), "1"(replaced)
-                : "memory");
+        if (probe_kernel_write((void *)pc, &new, MCOUNT_INSN_SIZE))
+                return -EPERM;
 
-        if (!err && (replaced == old))
-                flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
+        flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
 
-        return err;
+        return 0;
 }
 
 int ftrace_update_ftrace_func(ftrace_func_t func)
 {
-        int ret;
         unsigned long pc, old;
-        unsigned char *new;
+        unsigned long new;
+        int ret;
 
         pc = (unsigned long)&ftrace_call;
         memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE);
         new = ftrace_call_replace(pc, (unsigned long)func);
-        ret = ftrace_modify_code(pc, (unsigned char *)&old, new);
+
+        ret = ftrace_modify_code(pc, old, new);
+
+#ifdef CONFIG_OLD_MCOUNT
+        if (!ret) {
+                pc = (unsigned long)&ftrace_call_old;
+                memcpy(&old, &ftrace_call_old, MCOUNT_INSN_SIZE);
+                new = ftrace_call_replace(pc, (unsigned long)func);
+
+                ret = ftrace_modify_code(pc, old, new);
+        }
+#endif
+
+        return ret;
+}
+
+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned long new, old;
+        unsigned long ip = rec->ip;
+
+        old = ftrace_nop_replace(rec);
+        new = ftrace_call_replace(ip, adjust_address(rec, addr));
+
+        return ftrace_modify_code(rec->ip, old, new);
+}
+
+int ftrace_make_nop(struct module *mod,
+                    struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned long ip = rec->ip;
+        unsigned long old;
+        unsigned long new;
+        int ret;
+
+        old = ftrace_call_replace(ip, adjust_address(rec, addr));
+        new = ftrace_nop_replace(rec);
+        ret = ftrace_modify_code(ip, old, new);
+
+#ifdef CONFIG_OLD_MCOUNT
+        if (ret == -EINVAL && addr == MCOUNT_ADDR) {
+                rec->arch.old_mcount = true;
+
+                old = ftrace_call_replace(ip, adjust_address(rec, addr));
+                new = ftrace_nop_replace(rec);
+                ret = ftrace_modify_code(ip, old, new);
+        }
+#endif
+
         return ret;
 }
 
-/* run from ftrace_init with irqs disabled */
 int __init ftrace_dyn_arch_init(void *data)
 {
-        ftrace_mcount_set(data);
+        *(unsigned long *)data = 0;
+
         return 0;
 }
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index b9505aa267c..bbecaac1e01 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -15,55 +15,6 @@
 #define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
 #define ATAG_CORE_SIZE_EMPTY ((2*4) >> 2)
 
-        .align  2
-        .type   __switch_data, %object
-__switch_data:
-        .long   __mmap_switched
-        .long   __data_loc                      @ r4
-        .long   _data                           @ r5
-        .long   __bss_start                     @ r6
-        .long   _end                            @ r7
-        .long   processor_id                    @ r4
-        .long   __machine_arch_type             @ r5
-        .long   __atags_pointer                 @ r6
-        .long   cr_alignment                    @ r7
-        .long   init_thread_union + THREAD_START_SP @ sp
-
-/*
- * The following fragment of code is executed with the MMU on in MMU mode,
- * and uses absolute addresses; this is not position independent.
- *
- *  r0  = cp#15 control register
- *  r1  = machine ID
- *  r2  = atags pointer
- *  r9  = processor ID
- */
-__mmap_switched:
-        adr     r3, __switch_data + 4
-
-        ldmia   r3!, {r4, r5, r6, r7}
-        cmp     r4, r5                          @ Copy data segment if needed
-1:      cmpne   r5, r6
-        ldrne   fp, [r4], #4
-        strne   fp, [r5], #4
-        bne     1b
-
-        mov     fp, #0                          @ Clear BSS (and zero fp)
-1:      cmp     r6, r7
-        strcc   fp, [r6],#4
-        bcc     1b
-
- ARM(   ldmia   r3, {r4, r5, r6, r7, sp})
- THUMB( ldmia   r3, {r4, r5, r6, r7}    )
- THUMB( ldr     sp, [r3, #16]           )
-        str     r9, [r4]                        @ Save processor ID
-        str     r1, [r5]                        @ Save machine type
-        str     r2, [r6]                        @ Save atags pointer
-        bic     r4, r0, #CR_A                   @ Clear 'A' bit
-        stmia   r7, {r0, r4}                    @ Save control register values
-        b       start_kernel
-ENDPROC(__mmap_switched)
-
 /*
  * Exception handling.  Something went wrong and we can't proceed.  We
  * ought to tell the user, but since we don't have any guarantee that
@@ -73,21 +24,7 @@ ENDPROC(__mmap_switched)
  * and hope for the best (useful if bootloader fails to pass a proper
  * machine ID for example).
  */
-__error_p:
-#ifdef CONFIG_DEBUG_LL
-        adr     r0, str_p1
-        bl      printascii
-        mov     r0, r9
-        bl      printhex8
-        adr     r0, str_p2
-        bl      printascii
-        b       __error
-str_p1: .asciz  "\nError: unrecognized/unsupported processor variant (0x"
-str_p2: .asciz  ").\n"
-        .align
-#endif
-ENDPROC(__error_p)
-
+        __HEAD
 __error_a:
 #ifdef CONFIG_DEBUG_LL
         mov     r4, r1                          @ preserve machine ID
@@ -97,7 +34,7 @@ __error_a:
         bl      printhex8
         adr     r0, str_a2
         bl      printascii
-        adr     r3, 4f
+        adr     r3, __lookup_machine_type_data
         ldmia   r3, {r4, r5, r6}                @ get machine desc list
         sub     r4, r3, r4                      @ get offset between virt&phys
         add     r5, r5, r4                      @ convert virt addresses to
@@ -125,78 +62,6 @@ str_a3:	.asciz	"\nPlease check your kernel config and/or bootloader.\n"
         .align
 #endif
 
-__error:
-#ifdef CONFIG_ARCH_RPC
-/*
- * Turn the screen red on a error - RiscPC only.
- */
-        mov     r0, #0x02000000
-        mov     r3, #0x11
-        orr     r3, r3, r3, lsl #8
-        orr     r3, r3, r3, lsl #16
-        str     r3, [r0], #4
-        str     r3, [r0], #4
-        str     r3, [r0], #4
-        str     r3, [r0], #4
-#endif
-1:      mov     r0, r0
-        b       1b
-ENDPROC(__error)
-
-
-/*
- * Read processor ID register (CP#15, CR0), and look up in the linker-built
- * supported processor list.  Note that we can't use the absolute addresses
- * for the __proc_info lists since we aren't running with the MMU on
- * (and therefore, we are not in the correct address space).  We have to
- * calculate the offset.
- *
- *      r9 = cpuid
- * Returns:
- *      r3, r4, r6 corrupted
- *      r5 = proc_info pointer in physical address space
- *      r9 = cpuid (preserved)
- */
-__lookup_processor_type:
-        adr     r3, 3f
-        ldmia   r3, {r5 - r7}
-        add     r3, r3, #8
-        sub     r3, r3, r7                      @ get offset between virt&phys
-        add     r5, r5, r3                      @ convert virt addresses to
-        add     r6, r6, r3                      @ physical address space
-1:      ldmia   r5, {r3, r4}                    @ value, mask
-        and     r4, r4, r9                      @ mask wanted bits
-        teq     r3, r4
-        beq     2f
-        add     r5, r5, #PROC_INFO_SZ           @ sizeof(proc_info_list)
-        cmp     r5, r6
-        blo     1b
-        mov     r5, #0                          @ unknown processor
-2:      mov     pc, lr
-ENDPROC(__lookup_processor_type)
-
-/*
- * This provides a C-API version of the above function.
- */
-ENTRY(lookup_processor_type)
-        stmfd   sp!, {r4 - r7, r9, lr}
-        mov     r9, r0
-        bl      __lookup_processor_type
-        mov     r0, r5
-        ldmfd   sp!, {r4 - r7, r9, pc}
-ENDPROC(lookup_processor_type)
-
-/*
- * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for
- * more information about the __proc_info and __arch_info structures.
- */
-        .align  2
-3:      .long   __proc_info_begin
-        .long   __proc_info_end
-4:      .long   .
-        .long   __arch_info_begin
-        .long   __arch_info_end
-
 /*
  * Lookup machine architecture in the linker-build list of architectures.
  * Note that we can't use the absolute addresses for the __arch_info
@@ -209,7 +74,7 @@ ENDPROC(lookup_processor_type)
  *  r5 = mach_info pointer in physical address space
  */
 __lookup_machine_type:
-        adr     r3, 4b
+        adr     r3, __lookup_machine_type_data
         ldmia   r3, {r4, r5, r6}
         sub     r3, r3, r4                      @ get offset between virt&phys
         add     r5, r5, r3                      @ convert virt addresses to
@@ -225,15 +90,16 @@ __lookup_machine_type:
 ENDPROC(__lookup_machine_type)
 
 /*
- * This provides a C-API version of the above function.
+ * Look in arch/arm/kernel/arch.[ch] for information about the
+ * __arch_info structures.
  */
-ENTRY(lookup_machine_type)
-        stmfd   sp!, {r4 - r6, lr}
-        mov     r1, r0
-        bl      __lookup_machine_type
-        mov     r0, r5
-        ldmfd   sp!, {r4 - r6, pc}
-ENDPROC(lookup_machine_type)
+        .align  2
+        .type   __lookup_machine_type_data, %object
+__lookup_machine_type_data:
+        .long   .
+        .long   __arch_info_begin
+        .long   __arch_info_end
+        .size   __lookup_machine_type_data, . - __lookup_machine_type_data
 
 /* Determine validity of the r2 atags pointer.  The heuristic requires
  * that the pointer be aligned, in the first 16k of physical RAM and
@@ -265,3 +131,150 @@ __vet_atags:
 1:      mov     r2, #0
         mov     pc, lr
 ENDPROC(__vet_atags)
+
+/*
+ * The following fragment of code is executed with the MMU on in MMU mode,
+ * and uses absolute addresses; this is not position independent.
+ *
+ *  r0  = cp#15 control register
+ *  r1  = machine ID
+ *  r2  = atags pointer
+ *  r9  = processor ID
+ */
+        __INIT
+__mmap_switched:
+        adr     r3, __mmap_switched_data
+
+        ldmia   r3!, {r4, r5, r6, r7}
+        cmp     r4, r5                          @ Copy data segment if needed
+1:      cmpne   r5, r6
+        ldrne   fp, [r4], #4
+        strne   fp, [r5], #4
+        bne     1b
+
+        mov     fp, #0                          @ Clear BSS (and zero fp)
+1:      cmp     r6, r7
+        strcc   fp, [r6],#4
+        bcc     1b
+
+ ARM(   ldmia   r3, {r4, r5, r6, r7, sp})
+ THUMB( ldmia   r3, {r4, r5, r6, r7}    )
+ THUMB( ldr     sp, [r3, #16]           )
+        str     r9, [r4]                        @ Save processor ID
+        str     r1, [r5]                        @ Save machine type
+        str     r2, [r6]                        @ Save atags pointer
+        bic     r4, r0, #CR_A                   @ Clear 'A' bit
+        stmia   r7, {r0, r4}                    @ Save control register values
+        b       start_kernel
+ENDPROC(__mmap_switched)
+
+        .align  2
+        .type   __mmap_switched_data, %object
+__mmap_switched_data:
+        .long   __data_loc                      @ r4
+        .long   _sdata                          @ r5
+        .long   __bss_start                     @ r6
+        .long   _end                            @ r7
+        .long   processor_id                    @ r4
+        .long   __machine_arch_type             @ r5
+        .long   __atags_pointer                 @ r6
+        .long   cr_alignment                    @ r7
+        .long   init_thread_union + THREAD_START_SP @ sp
+        .size   __mmap_switched_data, . - __mmap_switched_data
+
+/*
+ * This provides a C-API version of __lookup_machine_type
+ */
+ENTRY(lookup_machine_type)
+        stmfd   sp!, {r4 - r6, lr}
+        mov     r1, r0
+        bl      __lookup_machine_type
+        mov     r0, r5
+        ldmfd   sp!, {r4 - r6, pc}
+ENDPROC(lookup_machine_type)
+
+/*
+ * This provides a C-API version of __lookup_processor_type
+ */
+ENTRY(lookup_processor_type)
+        stmfd   sp!, {r4 - r6, r9, lr}
+        mov     r9, r0
+        bl      __lookup_processor_type
+        mov     r0, r5
+        ldmfd   sp!, {r4 - r6, r9, pc}
+ENDPROC(lookup_processor_type)
+
+/*
+ * Read processor ID register (CP#15, CR0), and look up in the linker-built
+ * supported processor list.  Note that we can't use the absolute addresses
+ * for the __proc_info lists since we aren't running with the MMU on
+ * (and therefore, we are not in the correct address space).  We have to
+ * calculate the offset.
+ *
+ *      r9 = cpuid
+ * Returns:
+ *      r3, r4, r6 corrupted
+ *      r5 = proc_info pointer in physical address space
+ *      r9 = cpuid (preserved)
+ */
+        __CPUINIT
+__lookup_processor_type:
+        adr     r3, __lookup_processor_type_data
+        ldmia   r3, {r4 - r6}
+        sub     r3, r3, r4                      @ get offset between virt&phys
+        add     r5, r5, r3                      @ convert virt addresses to
+        add     r6, r6, r3                      @ physical address space
+1:      ldmia   r5, {r3, r4}                    @ value, mask
+        and     r4, r4, r9                      @ mask wanted bits
+        teq     r3, r4
+        beq     2f
+        add     r5, r5, #PROC_INFO_SZ           @ sizeof(proc_info_list)
+        cmp     r5, r6
+        blo     1b
+        mov     r5, #0                          @ unknown processor
+2:      mov     pc, lr
+ENDPROC(__lookup_processor_type)
+
+/*
+ * Look in <asm/procinfo.h> for information about the __proc_info structure.
+ */
+        .align  2
+        .type   __lookup_processor_type_data, %object
+__lookup_processor_type_data:
+        .long   .
+        .long   __proc_info_begin
+        .long   __proc_info_end
+        .size   __lookup_processor_type_data, . - __lookup_processor_type_data
+
+__error_p:
+#ifdef CONFIG_DEBUG_LL
+        adr     r0, str_p1
+        bl      printascii
+        mov     r0, r9
+        bl      printhex8
+        adr     r0, str_p2
+        bl      printascii
+        b       __error
+str_p1: .asciz  "\nError: unrecognized/unsupported processor variant (0x"
+str_p2: .asciz  ").\n"
+        .align
+#endif
+ENDPROC(__error_p)
+
+__error:
+#ifdef CONFIG_ARCH_RPC
+/*
+ * Turn the screen red on a error - RiscPC only.
+ */
+        mov     r0, #0x02000000
+        mov     r3, #0x11
+        orr     r3, r3, r3, lsl #8
+        orr     r3, r3, r3, lsl #16
+        str     r3, [r0], #4
+        str     r3, [r0], #4
+        str     r3, [r0], #4
+        str     r3, [r0], #4
+#endif
+1:      mov     r0, r0
+        b       1b
+ENDPROC(__error)
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 573b803dc6b..814ce1a7327 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -48,8 +48,6 @@ ENTRY(stext)
         movs    r8, r5                          @ invalid machine (r5=0)?
         beq     __error_a                       @ yes, error 'a'
 
-        ldr     r13, __switch_data              @ address to jump to after
-                                                @ the initialization is done
         adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
@@ -87,8 +85,7 @@ __after_proc_init:
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
 
-        mov     r3, r13
-        mov     pc, r3                          @ clear the BSS and jump
+        b       __mmap_switched                 @ clear the BSS and jump
                                                 @ to start_kernel
 ENDPROC(__after_proc_init)
         .ltorg
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf94721..dd6b369ac69 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -22,6 +22,10 @@
 #include <asm/thread_info.h>
 #include <asm/system.h>
 
+#ifdef CONFIG_DEBUG_LL
+#include <mach/debug-macro.S>
+#endif
+
 #if (PHYS_OFFSET & 0x001fffff)
 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
 #endif
@@ -86,6 +90,9 @@ ENTRY(stext)
         movs    r8, r5                          @ invalid machine (r5=0)?
         beq     __error_a                       @ yes, error 'a'
         bl      __vet_atags
+#ifdef CONFIG_SMP_ON_UP
+        bl      __fixup_smp
+#endif
         bl      __create_page_tables
 
         /*
@@ -95,113 +102,15 @@ ENTRY(stext)
          * above.  On return, the CPU will be ready for the MMU to be
          * turned on, and r0 will hold the CPU control register value.
          */
-        ldr     r13, __switch_data              @ address to jump to after
+        ldr     r13, =__mmap_switched           @ address to jump to after
                                                 @ mmu has been enabled
-        adr     lr, BSYM(__enable_mmu)          @ return (PIC) address
+        adr     lr, BSYM(1f)                    @ return (PIC) address
  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
  THUMB( mov     pc, r12                         )
+1:      b       __enable_mmu
 ENDPROC(stext)
-
-#if defined(CONFIG_SMP)
-ENTRY(secondary_startup)
-        /*
-         * Common entry point for secondary CPUs.
-         *
-         * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
-         * the processor type - there is no need to check the machine type
-         * as it has already been validated by the primary processor.
-         */
-        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
-        mrc     p15, 0, r9, c0, c0              @ get processor id
-        bl      __lookup_processor_type
-        movs    r10, r5                         @ invalid processor?
-        moveq   r0, #'p'                        @ yes, error 'p'
-        beq     __error
-
-        /*
-         * Use the page tables supplied from  __cpu_up.
-         */
-        adr     r4, __secondary_data
-        ldmia   r4, {r5, r7, r12}               @ address to jump to after
-        sub     r4, r4, r5                      @ mmu has been enabled
-        ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
-        adr     lr, BSYM(__enable_mmu)          @ return address
-        mov     r13, r12                        @ __secondary_switched address
- ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
-                                                  @ (return control reg)
- THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
- THUMB( mov     pc, r12                         )
-ENDPROC(secondary_startup)
-
-        /*
-         * r6  = &secondary_data
-         */
-ENTRY(__secondary_switched)
-        ldr     sp, [r7, #4]                    @ get secondary_data.stack
-        mov     fp, #0
-        b       secondary_start_kernel
-ENDPROC(__secondary_switched)
-
-        .type   __secondary_data, %object
-__secondary_data:
-        .long   .
-        .long   secondary_data
-        .long   __secondary_switched
-#endif /* defined(CONFIG_SMP) */
-
-
-
-/*
- * Setup common bits before finally enabling the MMU.  Essentially
- * this is just loading the page table pointer and domain access
- * registers.
- */
-__enable_mmu:
-#ifdef CONFIG_ALIGNMENT_TRAP
-        orr     r0, r0, #CR_A
-#else
-        bic     r0, r0, #CR_A
-#endif
-#ifdef CONFIG_CPU_DCACHE_DISABLE
-        bic     r0, r0, #CR_C
-#endif
-#ifdef CONFIG_CPU_BPREDICT_DISABLE
-        bic     r0, r0, #CR_Z
-#endif
-#ifdef CONFIG_CPU_ICACHE_DISABLE
-        bic     r0, r0, #CR_I
-#endif
-        mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
-                      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
-                      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
-                      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
-        mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
-        mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
-        b       __turn_mmu_on
-ENDPROC(__enable_mmu)
-
-/*
- * Enable the MMU.  This completely changes the structure of the visible
- * memory space.  You will not be able to trace execution through this.
- * If you have an enquiry about this, *please* check the linux-arm-kernel
- * mailing list archives BEFORE sending another post to the list.
- *
- *  r0  = cp#15 control register
- *  r13 = *virtual* address to jump to upon completion
- *
- * other registers depend on the function called upon completion
- */
-        .align  5
-__turn_mmu_on:
-        mov     r0, r0
-        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
-        mrc     p15, 0, r3, c0, c0, 0           @ read id reg
-        mov     r3, r3
-        mov     r3, r13
-        mov     pc, r3
-ENDPROC(__turn_mmu_on)
-
+        .ltorg
 
 /*
  * Setup the initial page tables.  We only setup the barest
@@ -213,7 +122,7 @@ ENDPROC(__turn_mmu_on)
  * r10 = procinfo
  *
  * Returns:
- *  r0, r3, r6, r7 corrupted
+ *  r0, r3, r5-r7 corrupted
  *  r4 = physical page table address
  */
 __create_page_tables:
@@ -235,20 +144,30 @@ __create_page_tables:
         ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 
         /*
-         * Create identity mapping for first MB of kernel to
-         * cater for the MMU enable.  This identity mapping
-         * will be removed by paging_init().  We use our current program
-         * counter to determine corresponding section base address.
+         * Create identity mapping to cater for __enable_mmu.
+         * This identity mapping will be removed by paging_init().
          */
-        mov     r6, pc
-        mov     r6, r6, lsr #20                 @ start of kernel section
-        orr     r3, r7, r6, lsl #20             @ flags + kernel base
-        str     r3, [r4, r6, lsl #2]            @ identity mapping
+        adr     r0, __enable_mmu_loc
+        ldmia   r0, {r3, r5, r6}
+        sub     r0, r0, r3                      @ virt->phys offset
+        add     r5, r5, r0                      @ phys __enable_mmu
+        add     r6, r6, r0                      @ phys __enable_mmu_end
+        mov     r5, r5, lsr #20
+        mov     r6, r6, lsr #20
+
+1:      orr     r3, r7, r5, lsl #20             @ flags + kernel base
+        str     r3, [r4, r5, lsl #2]            @ identity mapping
+        teq     r5, r6
+        addne   r5, r5, #1                      @ next section
+        bne     1b
 
         /*
          * Now setup the pagetables for our kernel direct
          * mapped region.
          */
+        mov     r3, pc
+        mov     r3, r3, lsr #20
+        orr     r3, r7, r3, lsl #20
         add     r0, r4,  #(KERNEL_START & 0xff000000) >> 18
         str     r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
         ldr     r6, =(KERNEL_END - 1)
@@ -289,24 +208,35 @@ __create_page_tables:
         str     r6, [r0]
 
 #ifdef CONFIG_DEBUG_LL
-        ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
+#ifndef CONFIG_DEBUG_ICEDCC
         /*
          * Map in IO space for serial debugging.
          * This allows debug messages to be output
          * via a serial console before paging_init.
          */
-        ldr     r3, [r8, #MACHINFO_PGOFFIO]
+        addruart r7, r3
+
+        mov     r3, r3, lsr #20
+        mov     r3, r3, lsl #2
+
         add     r0, r4, r3
         rsb     r3, r3, #0x4000                 @ PTRS_PER_PGD*sizeof(long)
         cmp     r3, #0x0800                     @ limit to 512MB
         movhi   r3, #0x0800
         add     r6, r0, r3
-        ldr     r3, [r8, #MACHINFO_PHYSIO]
-        orr     r3, r3, r7
+        mov     r3, r7, lsr #20
+        ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
+        orr     r3, r7, r3, lsl #20
 1:      str     r3, [r0], #4
         add     r3, r3, #1 << 20
         teq     r0, r6
         bne     1b
+
+#else /* CONFIG_DEBUG_ICEDCC */
+        /* we don't need any serial debugging mappings for ICEDCC */
+        ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
+#endif /* !CONFIG_DEBUG_ICEDCC */
+
 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
         /*
          * If we're using the NetWinder or CATS, we also need to map
@@ -332,5 +262,168 @@ __create_page_tables:
         mov     pc, lr
 ENDPROC(__create_page_tables)
         .ltorg
+__enable_mmu_loc:
+        .long   .
+        .long   __enable_mmu
+        .long   __enable_mmu_end
+
+#if defined(CONFIG_SMP)
+        __CPUINIT
+ENTRY(secondary_startup)
+        /*
+         * Common entry point for secondary CPUs.
+         *
+         * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
+         * the processor type - there is no need to check the machine type
+         * as it has already been validated by the primary processor.
+         */
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+        mrc     p15, 0, r9, c0, c0              @ get processor id
+        bl      __lookup_processor_type
+        movs    r10, r5                         @ invalid processor?
+        moveq   r0, #'p'                        @ yes, error 'p'
+        beq     __error_p
+
+        /*
+         * Use the page tables supplied from  __cpu_up.
+         */
+        adr     r4, __secondary_data
+        ldmia   r4, {r5, r7, r12}               @ address to jump to after
+        sub     r4, r4, r5                      @ mmu has been enabled
+        ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
+        adr     lr, BSYM(__enable_mmu)          @ return address
+        mov     r13, r12                        @ __secondary_switched address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
+                                                  @ (return control reg)
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
+ENDPROC(secondary_startup)
+
+        /*
+         * r6  = &secondary_data
+         */
+ENTRY(__secondary_switched)
+        ldr     sp, [r7, #4]                    @ get secondary_data.stack
+        mov     fp, #0
+        b       secondary_start_kernel
+ENDPROC(__secondary_switched)
+
+        .type   __secondary_data, %object
+__secondary_data:
+        .long   .
+        .long   secondary_data
+        .long   __secondary_switched
+#endif /* defined(CONFIG_SMP) */
+
+
+
+/*
+ * Setup common bits before finally enabling the MMU.  Essentially
+ * this is just loading the page table pointer and domain access
+ * registers.
+ *
+ *  r0  = cp#15 control register
+ *  r1  = machine ID
+ *  r2  = atags pointer
+ *  r4  = page table pointer
+ *  r9  = processor ID
+ *  r13 = *virtual* address to jump to upon completion
+ */
+__enable_mmu:
+#ifdef CONFIG_ALIGNMENT_TRAP
+        orr     r0, r0, #CR_A
+#else
+        bic     r0, r0, #CR_A
+#endif
+#ifdef CONFIG_CPU_DCACHE_DISABLE
+        bic     r0, r0, #CR_C
+#endif
+#ifdef CONFIG_CPU_BPREDICT_DISABLE
+        bic     r0, r0, #CR_Z
+#endif
+#ifdef CONFIG_CPU_ICACHE_DISABLE
+        bic     r0, r0, #CR_I
+#endif
+        mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
+                      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
+                      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
+                      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
+        mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
+        mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
+        b       __turn_mmu_on
+ENDPROC(__enable_mmu)
+
+/*
+ * Enable the MMU.  This completely changes the structure of the visible
+ * memory space.  You will not be able to trace execution through this.
+ * If you have an enquiry about this, *please* check the linux-arm-kernel
+ * mailing list archives BEFORE sending another post to the list.
+ *
+ *  r0  = cp#15 control register
+ *  r1  = machine ID
+ *  r2  = atags pointer
+ *  r9  = processor ID
+ *  r13 = *virtual* address to jump to upon completion
+ *
+ * other registers depend on the function called upon completion
+ */
+        .align  5
+__turn_mmu_on:
+        mov     r0, r0
+        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
+        mrc     p15, 0, r3, c0, c0, 0           @ read id reg
+        mov     r3, r3
+        mov     r3, r13
+        mov     pc, r3
+__enable_mmu_end:
+ENDPROC(__turn_mmu_on)
+
+
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+        mov     r7, #0x00070000
+        orr     r6, r7, #0xff000000     @ mask 0xff070000
+        orr     r7, r7, #0x41000000     @ val 0x41070000
+        and     r0, r9, r6
+        teq     r0, r7                  @ ARM CPU and ARMv6/v7?
+        bne     __fixup_smp_on_up       @ no, assume UP
+
+        orr     r6, r6, #0x0000ff00
+        orr     r6, r6, #0x000000f0     @ mask 0xff07fff0
+        orr     r7, r7, #0x0000b000
+        orr     r7, r7, #0x00000020     @ val 0x4107b020
+        and     r0, r9, r6
+        teq     r0, r7                  @ ARM 11MPCore?
+        moveq   pc, lr                  @ yes, assume SMP
+
+        mrc     p15, 0, r0, c0, c0, 5   @ read MPIDR
+        tst     r0, #1 << 31
+        movne   pc, lr                  @ bit 31 => SMP
+
+__fixup_smp_on_up:
+        adr     r0, 1f
+        ldmia   r0, {r3, r6, r7}
+        sub     r3, r0, r3
+        add     r6, r6, r3
+        add     r7, r7, r3
+2:      cmp     r6, r7
+        ldmia   r6!, {r0, r4}
+        strlo   r4, [r0, r3]
+        blo     2b
+        mov     pc, lr
+ENDPROC(__fixup_smp)
+
+1:      .word   .
+        .word   __smpalt_begin
+        .word   __smpalt_end
+
+        .pushsection .data
+        .globl  smp_on_up
+smp_on_up:
+        ALT_SMP(.long   1)
+        ALT_UP(.long    0)
+        .popsection
+
+#endif
 
 #include "head-common.S"
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
new file mode 100644
index 00000000000..54593b0c241
--- /dev/null
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -0,0 +1,849 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2009, 2010 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers.
+ */
+#define pr_fmt(fmt) "hw-breakpoint: " fmt
+
+#include <linux/errno.h>
+#include <linux/perf_event.h>
+#include <linux/hw_breakpoint.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/current.h>
+#include <asm/hw_breakpoint.h>
+#include <asm/kdebug.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+
+/* Breakpoint currently in use for each BRP. */
+static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
+
+/* Watchpoint currently in use for each WRP. */
+static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
+
+/* Number of BRP/WRP registers on this CPU. */
+static int core_num_brps;
+static int core_num_wrps;
+
+/* Debug architecture version. */
+static u8 debug_arch;
+
+/* Maximum supported watchpoint length. */
+static u8 max_watchpoint_len;
+
+/* Determine number of BRP registers available. */
+static int get_num_brps(void)
+{
+        u32 didr;
+        ARM_DBG_READ(c0, 0, didr);
+        return ((didr >> 24) & 0xf) + 1;
+}
+
+/* Determine number of WRP registers available. */
+static int get_num_wrps(void)
+{
+        /*
+         * FIXME: When a watchpoint fires, the only way to work out which
+         * watchpoint it was is by disassembling the faulting instruction
+         * and working out the address of the memory access.
+         *
+         * Furthermore, we can only do this if the watchpoint was precise
+         * since imprecise watchpoints prevent us from calculating register
+         * based addresses.
+         *
+         * For the time being, we only report 1 watchpoint register so we
+         * always know which watchpoint fired. In the future we can either
+         * add a disassembler and address generation emulator, or we can
+         * insert a check to see if the DFAR is set on watchpoint exception
+         * entry [the ARM ARM states that the DFAR is UNKNOWN, but
+         * experience shows that it is set on some implementations].
+         */
+
+#if 0
+        u32 didr, wrps;
+        ARM_DBG_READ(c0, 0, didr);
+        return ((didr >> 28) & 0xf) + 1;
+#endif
+
+        return 1;
+}
+
+int hw_breakpoint_slots(int type)
+{
+        /*
+         * We can be called early, so don't rely on
+         * our static variables being initialised.
+         */
+        switch (type) {
+        case TYPE_INST:
+                return get_num_brps();
+        case TYPE_DATA:
+                return get_num_wrps();
+        default:
+                pr_warning("unknown slot type: %d\n", type);
+                return 0;
+        }
+}
+
+/* Determine debug architecture. */
+static u8 get_debug_arch(void)
+{
+        u32 didr;
+
+        /* Do we implement the extended CPUID interface? */
+        if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
+                pr_warning("CPUID feature registers not supported. "
+                                "Assuming v6 debug is present.\n");
+                return ARM_DEBUG_ARCH_V6;
+        }
+
+        ARM_DBG_READ(c0, 0, didr);
+        return (didr >> 16) & 0xf;
+}
+
+/* Does this core support mismatch breakpoints? */
+static int core_has_mismatch_bps(void)
+{
+        return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1;
+}
+
+u8 arch_get_debug_arch(void)
+{
+        return debug_arch;
+}
+
+#define READ_WB_REG_CASE(OP2, M, VAL)           \
+        case ((OP2 << 4) + M):                  \
+                ARM_DBG_READ(c ## M, OP2, VAL); \
+                break
+
+#define WRITE_WB_REG_CASE(OP2, M, VAL)          \
+        case ((OP2 << 4) + M):                  \
+                ARM_DBG_WRITE(c ## M, OP2, VAL);\
+                break
+
+#define GEN_READ_WB_REG_CASES(OP2, VAL)         \
+        READ_WB_REG_CASE(OP2, 0, VAL);          \
+        READ_WB_REG_CASE(OP2, 1, VAL);          \
+        READ_WB_REG_CASE(OP2, 2, VAL);          \
+        READ_WB_REG_CASE(OP2, 3, VAL);          \
+        READ_WB_REG_CASE(OP2, 4, VAL);          \
+        READ_WB_REG_CASE(OP2, 5, VAL);          \
+        READ_WB_REG_CASE(OP2, 6, VAL);          \
+        READ_WB_REG_CASE(OP2, 7, VAL);          \
+        READ_WB_REG_CASE(OP2, 8, VAL);          \
+        READ_WB_REG_CASE(OP2, 9, VAL);          \
+        READ_WB_REG_CASE(OP2, 10, VAL);         \
+        READ_WB_REG_CASE(OP2, 11, VAL);         \
+        READ_WB_REG_CASE(OP2, 12, VAL);         \
+        READ_WB_REG_CASE(OP2, 13, VAL);         \
+        READ_WB_REG_CASE(OP2, 14, VAL);         \
+        READ_WB_REG_CASE(OP2, 15, VAL)
+
+#define GEN_WRITE_WB_REG_CASES(OP2, VAL)        \
+        WRITE_WB_REG_CASE(OP2, 0, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 1, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 2, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 3, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 4, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 5, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 6, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 7, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 8, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 9, VAL);         \
+        WRITE_WB_REG_CASE(OP2, 10, VAL);        \
+        WRITE_WB_REG_CASE(OP2, 11, VAL);        \
+        WRITE_WB_REG_CASE(OP2, 12, VAL);        \
+        WRITE_WB_REG_CASE(OP2, 13, VAL);        \
+        WRITE_WB_REG_CASE(OP2, 14, VAL);        \
+        WRITE_WB_REG_CASE(OP2, 15, VAL)
+
+static u32 read_wb_reg(int n)
+{
+        u32 val = 0;
+
+        switch (n) {
+        GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
+        GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
+        GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
+        GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
+        default:
+                pr_warning("attempt to read from unknown breakpoint "
+                                "register %d\n", n);
+        }
+
+        return val;
+}
+
+static void write_wb_reg(int n, u32 val)
+{
+        switch (n) {
+        GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
+        GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
+        GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
+        GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
+        default:
+                pr_warning("attempt to write to unknown breakpoint "
+                                "register %d\n", n);
+        }
+        isb();
+}
+
+/*
+ * In order to access the breakpoint/watchpoint control registers,
+ * we must be running in debug monitor mode. Unfortunately, we can
+ * be put into halting debug mode at any time by an external debugger
+ * but there is nothing we can do to prevent that.
+ */
+static int enable_monitor_mode(void)
+{
+        u32 dscr;
+        int ret = 0;
+
+        ARM_DBG_READ(c1, 0, dscr);
+
+        /* Ensure that halting mode is disabled. */
+        if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled."
+                                "Unable to access hardware resources.")) {
+                ret = -EPERM;
+                goto out;
+        }
+
+        /* Write to the corresponding DSCR. */
+        switch (debug_arch) {
+        case ARM_DEBUG_ARCH_V6:
+        case ARM_DEBUG_ARCH_V6_1:
+                ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
+                break;
+        case ARM_DEBUG_ARCH_V7_ECP14:
+                ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
+                break;
+        default:
+                ret = -ENODEV;
+                goto out;
+        }
+
+        /* Check that the write made it through. */
+        ARM_DBG_READ(c1, 0, dscr);
+        if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN),
+                                "failed to enable monitor mode.")) {
+                ret = -EPERM;
+        }
+
+out:
+        return ret;
+}
+
+/*
+ * Check if 8-bit byte-address select is available.
+ * This clobbers WRP 0.
+ */
+static u8 get_max_wp_len(void)
+{
+        u32 ctrl_reg;
+        struct arch_hw_breakpoint_ctrl ctrl;
+        u8 size = 4;
+
+        if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
+                goto out;
+
+        if (enable_monitor_mode())
+                goto out;
+
+        memset(&ctrl, 0, sizeof(ctrl));
+        ctrl.len = ARM_BREAKPOINT_LEN_8;
+        ctrl_reg = encode_ctrl_reg(ctrl);
+
+        write_wb_reg(ARM_BASE_WVR, 0);
+        write_wb_reg(ARM_BASE_WCR, ctrl_reg);
+        if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
+                size = 8;
+
+out:
+        return size;
+}
+
+u8 arch_get_max_wp_len(void)
+{
+        return max_watchpoint_len;
+}
+
+/*
+ * Handler for reactivating a suspended watchpoint when the single
+ * step `mismatch' breakpoint is triggered.
+ */
+static void wp_single_step_handler(struct perf_event *bp, int unused,
+                                   struct perf_sample_data *data,
+                                   struct pt_regs *regs)
+{
+        perf_event_enable(counter_arch_bp(bp)->suspended_wp);
+        unregister_hw_breakpoint(bp);
+}
+
+static int bp_is_single_step(struct perf_event *bp)
+{
+        return bp->overflow_handler == wp_single_step_handler;
+}
+
+/*
+ * Install a perf counter breakpoint.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        struct perf_event **slot, **slots;
+        int i, max_slots, ctrl_base, val_base, ret = 0;
+
+        /* Ensure that we are in monitor mode and halting mode is disabled. */
+        ret = enable_monitor_mode();
+        if (ret)
+                goto out;
+
+        if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
+                /* Breakpoint */
+                ctrl_base = ARM_BASE_BCR;
+                val_base = ARM_BASE_BVR;
+                slots = __get_cpu_var(bp_on_reg);
+                max_slots = core_num_brps - 1;
+
+                if (bp_is_single_step(bp)) {
+                        info->ctrl.mismatch = 1;
+                        i = max_slots;
+                        slots[i] = bp;
+                        goto setup;
+                }
+        } else {
+                /* Watchpoint */
+                ctrl_base = ARM_BASE_WCR;
+                val_base = ARM_BASE_WVR;
+                slots = __get_cpu_var(wp_on_reg);
+                max_slots = core_num_wrps;
+        }
+
+        for (i = 0; i < max_slots; ++i) {
+                slot = &slots[i];
+
+                if (!*slot) {
+                        *slot = bp;
+                        break;
+                }
+        }
+
+        if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) {
+                ret = -EBUSY;
+                goto out;
+        }
+
+setup:
+        /* Setup the address register. */
+        write_wb_reg(val_base + i, info->address);
+
+        /* Setup the control register. */
+        write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1);
+
+out:
+        return ret;
+}
+
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        struct perf_event **slot, **slots;
+        int i, max_slots, base;
+
+        if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
+                /* Breakpoint */
+                base = ARM_BASE_BCR;
+                slots = __get_cpu_var(bp_on_reg);
+                max_slots = core_num_brps - 1;
+
+                if (bp_is_single_step(bp)) {
+                        i = max_slots;
+                        slots[i] = NULL;
+                        goto reset;
+                }
+        } else {
+                /* Watchpoint */
+                base = ARM_BASE_WCR;
+                slots = __get_cpu_var(wp_on_reg);
+                max_slots = core_num_wrps;
+        }
+
+        /* Remove the breakpoint. */
+        for (i = 0; i < max_slots; ++i) {
+                slot = &slots[i];
+
+                if (*slot == bp) {
+                        *slot = NULL;
+                        break;
+                }
+        }
+
+        if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
+                return;
+
+reset:
+        /* Reset the control register. */
+        write_wb_reg(base + i, 0);
+}
+
+static int get_hbp_len(u8 hbp_len)
+{
+        unsigned int len_in_bytes = 0;
+
+        switch (hbp_len) {
+        case ARM_BREAKPOINT_LEN_1:
+                len_in_bytes = 1;
+                break;
+        case ARM_BREAKPOINT_LEN_2:
+                len_in_bytes = 2;
+                break;
+        case ARM_BREAKPOINT_LEN_4:
+                len_in_bytes = 4;
+                break;
+        case ARM_BREAKPOINT_LEN_8:
+                len_in_bytes = 8;
+                break;
+        }
+
+        return len_in_bytes;
+}
+
+/*
+ * Check whether bp virtual address is in kernel space.
+ */
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
+{
+        unsigned int len;
+        unsigned long va;
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        va = info->address;
+        len = get_hbp_len(info->ctrl.len);
+
+        return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
+}
+
+/*
+ * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
+ * Hopefully this will disappear when ptrace can bypass the conversion
+ * to generic breakpoint descriptions.
+ */
+int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
+                           int *gen_len, int *gen_type)
+{
+        /* Type */
+        switch (ctrl.type) {
+        case ARM_BREAKPOINT_EXECUTE:
+                *gen_type = HW_BREAKPOINT_X;
+                break;
+        case ARM_BREAKPOINT_LOAD:
+                *gen_type = HW_BREAKPOINT_R;
+                break;
+        case ARM_BREAKPOINT_STORE:
+                *gen_type = HW_BREAKPOINT_W;
+                break;
+        case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
+                *gen_type = HW_BREAKPOINT_RW;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Len */
+        switch (ctrl.len) {
+        case ARM_BREAKPOINT_LEN_1:
+                *gen_len = HW_BREAKPOINT_LEN_1;
+                break;
+        case ARM_BREAKPOINT_LEN_2:
+                *gen_len = HW_BREAKPOINT_LEN_2;
+                break;
+        case ARM_BREAKPOINT_LEN_4:
+                *gen_len = HW_BREAKPOINT_LEN_4;
+                break;
+        case ARM_BREAKPOINT_LEN_8:
+                *gen_len = HW_BREAKPOINT_LEN_8;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/*
+ * Construct an arch_hw_breakpoint from a perf_event.
+ */
+static int arch_build_bp_info(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        /* Type */
+        switch (bp->attr.bp_type) {
+        case HW_BREAKPOINT_X:
+                info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
+                break;
+        case HW_BREAKPOINT_R:
+                info->ctrl.type = ARM_BREAKPOINT_LOAD;
+                break;
+        case HW_BREAKPOINT_W:
+                info->ctrl.type = ARM_BREAKPOINT_STORE;
+                break;
+        case HW_BREAKPOINT_RW:
+                info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Len */
+        switch (bp->attr.bp_len) {
+        case HW_BREAKPOINT_LEN_1:
+                info->ctrl.len = ARM_BREAKPOINT_LEN_1;
+                break;
+        case HW_BREAKPOINT_LEN_2:
+                info->ctrl.len = ARM_BREAKPOINT_LEN_2;
+                break;
+        case HW_BREAKPOINT_LEN_4:
+                info->ctrl.len = ARM_BREAKPOINT_LEN_4;
+                break;
+        case HW_BREAKPOINT_LEN_8:
+                info->ctrl.len = ARM_BREAKPOINT_LEN_8;
+                if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
+                        && max_watchpoint_len >= 8)
+                        break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Address */
+        info->address = bp->attr.bp_addr;
+
+        /* Privilege */
+        info->ctrl.privilege = ARM_BREAKPOINT_USER;
+        if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp))
+                info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
+
+        /* Enabled? */
+        info->ctrl.enabled = !bp->attr.disabled;
+
+        /* Mismatch */
+        info->ctrl.mismatch = 0;
+
+        return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings.
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        int ret = 0;
+        u32 bytelen, max_len, offset, alignment_mask = 0x3;
+
+        /* Build the arch_hw_breakpoint. */
+        ret = arch_build_bp_info(bp);
+        if (ret)
+                goto out;
+
+        /* Check address alignment. */
+        if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
+                alignment_mask = 0x7;
+        if (info->address & alignment_mask) {
+                /*
+                 * Try to fix the alignment. This may result in a length
+                 * that is too large, so we must check for that.
+                 */
+                bytelen = get_hbp_len(info->ctrl.len);
+                max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 :
+                                max_watchpoint_len;
+
+                if (max_len >= 8)
+                        offset = info->address & 0x7;
+                else
+                        offset = info->address & 0x3;
+
+                if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) {
+                        ret = -EFBIG;
+                        goto out;
+                }
+
+                info->ctrl.len <<= offset;
+                info->address &= ~offset;
+
+                pr_debug("breakpoint alignment fixup: length = 0x%x, "
+                        "address = 0x%x\n", info->ctrl.len, info->address);
+        }
+
+        /*
+         * Currently we rely on an overflow handler to take
+         * care of single-stepping the breakpoint when it fires.
+         * In the case of userspace breakpoints on a core with V7 debug,
+         * we can use the mismatch feature as a poor-man's hardware single-step.
+         */
+        if (WARN_ONCE(!bp->overflow_handler &&
+                (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()),
+                        "overflow handler required but none found")) {
+                ret = -EINVAL;
+                goto out;
+        }
+out:
+        return ret;
+}
+
+static void update_mismatch_flag(int idx, int flag)
+{
+        struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]);
+        struct arch_hw_breakpoint *info;
+
+        if (bp == NULL)
+                return;
+
+        info = counter_arch_bp(bp);
+
+        /* Update the mismatch field to enter/exit `single-step' mode */
+        if (!bp->overflow_handler && info->ctrl.mismatch != flag) {
+                info->ctrl.mismatch = flag;
+                write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1);
+        }
+}
+
+static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
+{
+        int i;
+        struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg);
+        struct arch_hw_breakpoint *info;
+        struct perf_event_attr attr;
+
+        /* Without a disassembler, we can only handle 1 watchpoint. */
+        BUG_ON(core_num_wrps > 1);
+
+        hw_breakpoint_init(&attr);
+        attr.bp_addr    = regs->ARM_pc & ~0x3;
+        attr.bp_len     = HW_BREAKPOINT_LEN_4;
+        attr.bp_type    = HW_BREAKPOINT_X;
+
+        for (i = 0; i < core_num_wrps; ++i) {
+                rcu_read_lock();
+
+                if (slots[i] == NULL) {
+                        rcu_read_unlock();
+                        continue;
+                }
+
+                /*
+                 * The DFAR is an unknown value. Since we only allow a
+                 * single watchpoint, we can set the trigger to the lowest
+                 * possible faulting address.
+                 */
+                info = counter_arch_bp(slots[i]);
+                info->trigger = slots[i]->attr.bp_addr;
+                pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
+                perf_bp_event(slots[i], regs);
+
+                /*
+                 * If no overflow handler is present, insert a temporary
+                 * mismatch breakpoint so we can single-step over the
+                 * watchpoint trigger.
+                 */
+                if (!slots[i]->overflow_handler) {
+                        bp = register_user_hw_breakpoint(&attr,
+                                                         wp_single_step_handler,
+                                                         current);
+                        counter_arch_bp(bp)->suspended_wp = slots[i];
+                        perf_event_disable(slots[i]);
+                }
+
+                rcu_read_unlock();
+        }
+}
+
+static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
+{
+        int i;
+        int mismatch;
+        u32 ctrl_reg, val, addr;
+        struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg);
+        struct arch_hw_breakpoint *info;
+        struct arch_hw_breakpoint_ctrl ctrl;
+
+        /* The exception entry code places the amended lr in the PC. */
+        addr = regs->ARM_pc;
+
+        for (i = 0; i < core_num_brps; ++i) {
+                rcu_read_lock();
+
+                bp = slots[i];
+
+                if (bp == NULL) {
+                        rcu_read_unlock();
+                        continue;
+                }
+
+                mismatch = 0;
+
+                /* Check if the breakpoint value matches. */
+                val = read_wb_reg(ARM_BASE_BVR + i);
+                if (val != (addr & ~0x3))
+                        goto unlock;
+
+                /* Possible match, check the byte address select to confirm. */
+                ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
+                decode_ctrl_reg(ctrl_reg, &ctrl);
+                if ((1 << (addr & 0x3)) & ctrl.len) {
+                        mismatch = 1;
+                        info = counter_arch_bp(bp);
+                        info->trigger = addr;
+                }
+
+unlock:
+                if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) {
+                        pr_debug("breakpoint fired: address = 0x%x\n", addr);
+                        perf_bp_event(bp, regs);
+                }
+
+                update_mismatch_flag(i, mismatch);
+                rcu_read_unlock();
+        }
+}
+
+/*
+ * Called from either the Data Abort Handler [watchpoint] or the
+ * Prefetch Abort Handler [breakpoint].
+ */
+static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
+                                 struct pt_regs *regs)
+{
+        int ret = 1; /* Unhandled fault. */
+        u32 dscr;
+
+        /* We only handle watchpoints and hardware breakpoints. */
+        ARM_DBG_READ(c1, 0, dscr);
+
+        /* Perform perf callbacks. */
+        switch (ARM_DSCR_MOE(dscr)) {
+        case ARM_ENTRY_BREAKPOINT:
+                breakpoint_handler(addr, regs);
+                break;
+        case ARM_ENTRY_ASYNC_WATCHPOINT:
+                WARN_ON("Asynchronous watchpoint exception taken. "
+                        "Debugging results may be unreliable");
+        case ARM_ENTRY_SYNC_WATCHPOINT:
+                watchpoint_handler(addr, regs);
+                break;
+        default:
+                goto out;
+        }
+
+        ret = 0;
+out:
+        return ret;
+}
+
+/*
+ * One-time initialisation.
+ */
+static void __init reset_ctrl_regs(void *unused)
+{
+        int i;
+
+        if (enable_monitor_mode())
+                return;
+
+        for (i = 0; i < core_num_brps; ++i) {
+                write_wb_reg(ARM_BASE_BCR + i, 0UL);
+                write_wb_reg(ARM_BASE_BVR + i, 0UL);
+        }
+
+        for (i = 0; i < core_num_wrps; ++i) {
+                write_wb_reg(ARM_BASE_WCR + i, 0UL);
+                write_wb_reg(ARM_BASE_WVR + i, 0UL);
+        }
+}
+
+static int __init arch_hw_breakpoint_init(void)
+{
+        int ret = 0;
+        u32 dscr;
+
+        debug_arch = get_debug_arch();
+
+        if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
+                pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
+                ret = -ENODEV;
+                goto out;
+        }
+
+        /* Determine how many BRPs/WRPs are available. */
+        core_num_brps = get_num_brps();
+        core_num_wrps = get_num_wrps();
+
+        pr_info("found %d breakpoint and %d watchpoint registers.\n",
+                        core_num_brps, core_num_wrps);
+
+        if (core_has_mismatch_bps())
+                pr_info("1 breakpoint reserved for watchpoint single-step.\n");
+
+        ARM_DBG_READ(c1, 0, dscr);
+        if (dscr & ARM_DSCR_HDBGEN) {
+                pr_warning("halting debug mode enabled. Assuming maximum "
+                                "watchpoint size of 4 bytes.");
+        } else {
+                /* Work out the maximum supported watchpoint length. */
+                max_watchpoint_len = get_max_wp_len();
+                pr_info("maximum watchpoint size is %u bytes.\n",
+                                max_watchpoint_len);
+
+                /*
+                 * Reset the breakpoint resources. We assume that a halting
+                 * debugger will leave the world in a nice state for us.
+                 */
+                smp_call_function(reset_ctrl_regs, NULL, 1);
+                reset_ctrl_regs(NULL);
+        }
+
+        /* Register debug fault handler. */
+        hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
+                        "watchpoint debug exception");
+        hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
+                        "breakpoint debug exception");
+
+out:
+        return ret;
+}
+arch_initcall(arch_hw_breakpoint_init);
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+}
+
+/*
+ * Dummy function to register with die_notifier.
+ */
+int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+                                        unsigned long val, void *data)
+{
+        return NOTIFY_DONE;
+}
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index c0d5c3b3a76..36ad3be4692 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -154,14 +154,6 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
 
 void __init init_IRQ(void)
 {
-        struct irq_desc *desc;
-        int irq;
-
-        for (irq = 0; irq < nr_irqs; irq++) {
-                desc = irq_to_desc_alloc_node(irq, 0);
-                desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
-        }
-
         init_arch_irq();
 }
 
@@ -169,7 +161,7 @@ void __init init_IRQ(void)
 int __init arch_probe_nr_irqs(void)
 {
         nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
-        return 0;
+        return nr_irqs;
 }
 #endif
 
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 8bccbfa693f..2c1f0050c9c 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 {
         /*
          * MSR   : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
-         * Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx
+         * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
          * ALU op with S bit and Rd == 15 :
          *         cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
          */
-        if ((insn & 0x0f900000) == 0x03200000 ||        /* MSR & Undef */
+        if ((insn & 0x0fb00000) == 0x03200000 ||        /* MSR */
+            (insn & 0x0ff00000) == 0x03400000 ||        /* Undef */
             (insn & 0x0e10f000) == 0x0210f000)          /* ALU s-bit, R15  */
                 return INSN_REJECTED;
 
@@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
          * *S (bit 20) updates condition codes
          * ADC/SBC/RSC reads the C flag
          */
-        insn &= 0xfff00fff;     /* Rn = r0, Rd = r0 */
+        insn &= 0xffff0fff;     /* Rd = r0 */
         asi->insn[0] = insn;
         asi->insn_handler = (insn & (1 << 20)) ?  /* S-bit */
                         emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 6b4605893f1..d9bd786ce23 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -69,20 +69,31 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
 {
 #ifdef CONFIG_ARM_UNWIND
         Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
+        struct arm_unwind_mapping *maps = mod->arch.map;
 
         for (s = sechdrs; s < sechdrs_end; s++) {
-                if (strcmp(".ARM.exidx.init.text", secstrings + s->sh_name) == 0)
-                        mod->arch.unw_sec_init = s;
-                else if (strcmp(".ARM.exidx.devinit.text", secstrings + s->sh_name) == 0)
-                        mod->arch.unw_sec_devinit = s;
-                else if (strcmp(".ARM.exidx", secstrings + s->sh_name) == 0)
-                        mod->arch.unw_sec_core = s;
-                else if (strcmp(".init.text", secstrings + s->sh_name) == 0)
-                        mod->arch.sec_init_text = s;
-                else if (strcmp(".devinit.text", secstrings + s->sh_name) == 0)
-                        mod->arch.sec_devinit_text = s;
-                else if (strcmp(".text", secstrings + s->sh_name) == 0)
-                        mod->arch.sec_core_text = s;
+                char const *secname = secstrings + s->sh_name;
+
+                if (strcmp(".ARM.exidx.init.text", secname) == 0)
+                        maps[ARM_SEC_INIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
+                        maps[ARM_SEC_DEVINIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx", secname) == 0)
+                        maps[ARM_SEC_CORE].unw_sec = s;
+                else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
+                        maps[ARM_SEC_EXIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
+                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
+                else if (strcmp(".init.text", secname) == 0)
+                        maps[ARM_SEC_INIT].sec_text = s;
+                else if (strcmp(".devinit.text", secname) == 0)
+                        maps[ARM_SEC_DEVINIT].sec_text = s;
+                else if (strcmp(".text", secname) == 0)
+                        maps[ARM_SEC_CORE].sec_text = s;
+                else if (strcmp(".exit.text", secname) == 0)
+                        maps[ARM_SEC_EXIT].sec_text = s;
+                else if (strcmp(".devexit.text", secname) == 0)
+                        maps[ARM_SEC_DEVEXIT].sec_text = s;
         }
 #endif
         return 0;
@@ -292,31 +303,22 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
 #ifdef CONFIG_ARM_UNWIND
 static void register_unwind_tables(struct module *mod)
 {
-        if (mod->arch.unw_sec_init && mod->arch.sec_init_text)
-                mod->arch.unwind_init =
-                        unwind_table_add(mod->arch.unw_sec_init->sh_addr,
-                                         mod->arch.unw_sec_init->sh_size,
-                                         mod->arch.sec_init_text->sh_addr,
-                                         mod->arch.sec_init_text->sh_size);
-        if (mod->arch.unw_sec_devinit && mod->arch.sec_devinit_text)
-                mod->arch.unwind_devinit =
-                        unwind_table_add(mod->arch.unw_sec_devinit->sh_addr,
-                                         mod->arch.unw_sec_devinit->sh_size,
-                                         mod->arch.sec_devinit_text->sh_addr,
-                                         mod->arch.sec_devinit_text->sh_size);
-        if (mod->arch.unw_sec_core && mod->arch.sec_core_text)
-                mod->arch.unwind_core =
-                        unwind_table_add(mod->arch.unw_sec_core->sh_addr,
-                                         mod->arch.unw_sec_core->sh_size,
-                                         mod->arch.sec_core_text->sh_addr,
-                                         mod->arch.sec_core_text->sh_size);
+        int i;
+        for (i = 0; i < ARM_SEC_MAX; ++i) {
+                struct arm_unwind_mapping *map = &mod->arch.map[i];
+                if (map->unw_sec && map->sec_text)
+                        map->unwind = unwind_table_add(map->unw_sec->sh_addr,
+                                                       map->unw_sec->sh_size,
+                                                       map->sec_text->sh_addr,
+                                                       map->sec_text->sh_size);
+        }
 }
 
 static void unregister_unwind_tables(struct module *mod)
 {
-        unwind_table_del(mod->arch.unwind_init);
-        unwind_table_del(mod->arch.unwind_devinit);
-        unwind_table_del(mod->arch.unwind_core);
+        int i = ARM_SEC_MAX;
+        while (--i >= 0)
+                unwind_table_del(mod->arch.map[i].unwind);
 }
 #else
 static inline void register_unwind_tables(struct module *mod) { }
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ecbb0288e5d..49643b1467e 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -123,6 +123,12 @@ armpmu_get_max_events(void)
 }
 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
 
+int perf_num_counters(void)
+{
+        return armpmu_get_max_events();
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
 #define HW_OP_UNSUPPORTED               0xFFFF
 
 #define C(_x) \
@@ -221,46 +227,56 @@ again:
 }
 
 static void
-armpmu_disable(struct perf_event *event)
+armpmu_read(struct perf_event *event)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
-        int idx = hwc->idx;
-
-        WARN_ON(idx < 0);
-
-        clear_bit(idx, cpuc->active_mask);
-        armpmu->disable(hwc, idx);
-
-        barrier();
 
-        armpmu_event_update(event, hwc, idx);
-        cpuc->events[idx] = NULL;
-        clear_bit(idx, cpuc->used_mask);
+        /* Don't read disabled counters! */
+        if (hwc->idx < 0)
+                return;
 
-        perf_event_update_userpage(event);
+        armpmu_event_update(event, hwc, hwc->idx);
 }
 
 static void
-armpmu_read(struct perf_event *event)
+armpmu_stop(struct perf_event *event, int flags)
 {
         struct hw_perf_event *hwc = &event->hw;
 
-        /* Don't read disabled counters! */
-        if (hwc->idx < 0)
+        if (!armpmu)
                 return;
 
-        armpmu_event_update(event, hwc, hwc->idx);
+        /*
+         * ARM pmu always has to update the counter, so ignore
+         * PERF_EF_UPDATE, see comments in armpmu_start().
+         */
+        if (!(hwc->state & PERF_HES_STOPPED)) {
+                armpmu->disable(hwc, hwc->idx);
+                barrier(); /* why? */
+                armpmu_event_update(event, hwc, hwc->idx);
+                hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
+        }
 }
 
 static void
-armpmu_unthrottle(struct perf_event *event)
+armpmu_start(struct perf_event *event, int flags)
 {
         struct hw_perf_event *hwc = &event->hw;
 
+        if (!armpmu)
+                return;
+
+        /*
+         * ARM pmu always has to reprogram the period, so ignore
+         * PERF_EF_RELOAD, see the comment below.
+         */
+        if (flags & PERF_EF_RELOAD)
+                WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+
+        hwc->state = 0;
         /*
          * Set the period again. Some counters can't be stopped, so when we
-         * were throttled we simply disabled the IRQ source and the counter
+         * were stopped we simply disabled the IRQ source and the counter
          * may have been left counting. If we don't do this step then we may
          * get an interrupt too soon or *way* too late if the overflow has
          * happened since disabling.
@@ -269,14 +285,33 @@ armpmu_unthrottle(struct perf_event *event)
         armpmu->enable(hwc, hwc->idx);
 }
 
+static void
+armpmu_del(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        WARN_ON(idx < 0);
+
+        clear_bit(idx, cpuc->active_mask);
+        armpmu_stop(event, PERF_EF_UPDATE);
+        cpuc->events[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
 static int
-armpmu_enable(struct perf_event *event)
+armpmu_add(struct perf_event *event, int flags)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
         int idx;
         int err = 0;
 
+        perf_pmu_disable(event->pmu);
+
         /* If we don't have a space for the counter then finish early. */
         idx = armpmu->get_event_idx(cpuc, hwc);
         if (idx < 0) {
@@ -293,25 +328,19 @@ armpmu_enable(struct perf_event *event)
         cpuc->events[idx] = event;
         set_bit(idx, cpuc->active_mask);
 
-        /* Set the period for the event. */
-        armpmu_event_set_period(event, hwc, idx);
-
-        /* Enable the event. */
-        armpmu->enable(hwc, idx);
+        hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+        if (flags & PERF_EF_START)
+                armpmu_start(event, PERF_EF_RELOAD);
 
         /* Propagate our changes to the userspace mapping. */
         perf_event_update_userpage(event);
 
 out:
+        perf_pmu_enable(event->pmu);
         return err;
 }
 
-static struct pmu pmu = {
-        .enable     = armpmu_enable,
-        .disable    = armpmu_disable,
-        .unthrottle = armpmu_unthrottle,
-        .read       = armpmu_read,
-};
+static struct pmu pmu;
 
 static int
 validate_event(struct cpu_hw_events *cpuc,
@@ -491,20 +520,29 @@ __hw_perf_event_init(struct perf_event *event)
         return err;
 }
 
-const struct pmu *
-hw_perf_event_init(struct perf_event *event)
+static int armpmu_event_init(struct perf_event *event)
 {
         int err = 0;
 
+        switch (event->attr.type) {
+        case PERF_TYPE_RAW:
+        case PERF_TYPE_HARDWARE:
+        case PERF_TYPE_HW_CACHE:
+                break;
+
+        default:
+                return -ENOENT;
+        }
+
         if (!armpmu)
-                return ERR_PTR(-ENODEV);
+                return -ENODEV;
 
         event->destroy = hw_perf_event_destroy;
 
         if (!atomic_inc_not_zero(&active_events)) {
-                if (atomic_read(&active_events) > perf_max_events) {
+                if (atomic_read(&active_events) > armpmu->num_events) {
                         atomic_dec(&active_events);
-                        return ERR_PTR(-ENOSPC);
+                        return -ENOSPC;
                 }
 
                 mutex_lock(&pmu_reserve_mutex);
@@ -518,17 +556,16 @@ hw_perf_event_init(struct perf_event *event)
         }
 
         if (err)
-                return ERR_PTR(err);
+                return err;
 
         err = __hw_perf_event_init(event);
         if (err)
                 hw_perf_event_destroy(event);
 
-        return err ? ERR_PTR(err) : &pmu;
+        return err;
 }
 
-void
-hw_perf_enable(void)
+static void armpmu_enable(struct pmu *pmu)
 {
         /* Enable all of the perf events on hardware. */
         int idx;
@@ -549,13 +586,23 @@ hw_perf_enable(void)
         armpmu->start();
 }
 
-void
-hw_perf_disable(void)
+static void armpmu_disable(struct pmu *pmu)
 {
         if (armpmu)
                 armpmu->stop();
 }
 
+static struct pmu pmu = {
+        .pmu_enable     = armpmu_enable,
+        .pmu_disable    = armpmu_disable,
+        .event_init     = armpmu_event_init,
+        .add            = armpmu_add,
+        .del            = armpmu_del,
+        .start          = armpmu_start,
+        .stop           = armpmu_stop,
+        .read           = armpmu_read,
+};
+
 /*
  * ARMv6 Performance counter handling code.
  *
@@ -1045,7 +1092,7 @@ armv6pmu_handle_irq(int irq_num,
          * platforms that can have the PMU interrupts raised as an NMI, this
          * will not work.
          */
-        perf_event_do_pending();
+        irq_work_run();
 
         return IRQ_HANDLED;
 }
@@ -2021,7 +2068,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
          * platforms that can have the PMU interrupts raised as an NMI, this
          * will not work.
          */
-        perf_event_do_pending();
+        irq_work_run();
 
         return IRQ_HANDLED;
 }
@@ -2389,7 +2436,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
                         armpmu->disable(hwc, idx);
         }
 
-        perf_event_do_pending();
+        irq_work_run();
 
         /*
          * Re-enable the PMU.
@@ -2716,7 +2763,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
                         armpmu->disable(hwc, idx);
         }
 
-        perf_event_do_pending();
+        irq_work_run();
 
         /*
          * Re-enable the PMU.
@@ -2933,14 +2980,12 @@ init_hw_perf_events(void)
                         armpmu = &armv6pmu;
                         memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
                                         sizeof(armv6_perf_cache_map));
-                        perf_max_events = armv6pmu.num_events;
                         break;
                 case 0xB020:    /* ARM11mpcore */
                         armpmu = &armv6mpcore_pmu;
                         memcpy(armpmu_perf_cache_map,
                                armv6mpcore_perf_cache_map,
                                sizeof(armv6mpcore_perf_cache_map));
-                        perf_max_events = armv6mpcore_pmu.num_events;
                         break;
                 case 0xC080:    /* Cortex-A8 */
                         armv7pmu.id = ARM_PERF_PMU_ID_CA8;
@@ -2952,7 +2997,6 @@ init_hw_perf_events(void)
                         /* Reset PMNC and read the nb of CNTx counters
                             supported */
                         armv7pmu.num_events = armv7_reset_read_pmnc();
-                        perf_max_events = armv7pmu.num_events;
                         break;
                 case 0xC090:    /* Cortex-A9 */
                         armv7pmu.id = ARM_PERF_PMU_ID_CA9;
@@ -2964,7 +3008,6 @@ init_hw_perf_events(void)
                         /* Reset PMNC and read the nb of CNTx counters
                             supported */
                         armv7pmu.num_events = armv7_reset_read_pmnc();
-                        perf_max_events = armv7pmu.num_events;
                         break;
                 }
         /* Intel CPUs [xscale]. */
@@ -2975,13 +3018,11 @@ init_hw_perf_events(void)
                         armpmu = &xscale1pmu;
                         memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
                                         sizeof(xscale_perf_cache_map));
-                        perf_max_events = xscale1pmu.num_events;
                         break;
                 case 2:
                         armpmu = &xscale2pmu;
                         memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
                                         sizeof(xscale_perf_cache_map));
-                        perf_max_events = xscale2pmu.num_events;
                         break;
                 }
         }
@@ -2991,9 +3032,10 @@ init_hw_perf_events(void)
                                 arm_pmu_names[armpmu->id], armpmu->num_events);
         } else {
                 pr_info("no hardware support available\n");
-                perf_max_events = -1;
         }
 
+        perf_pmu_register(&pmu);
+
         return 0;
 }
 arch_initcall(init_hw_perf_events);
@@ -3001,13 +3043,6 @@ arch_initcall(init_hw_perf_events);
 /*
  * Callchain handling code.
  */
-static inline void
-callchain_store(struct perf_callchain_entry *entry,
-                u64 ip)
-{
-        if (entry->nr < PERF_MAX_STACK_DEPTH)
-                entry->ip[entry->nr++] = ip;
-}
 
 /*
  * The registers we're interested in are at the end of the variable
@@ -3039,7 +3074,7 @@ user_backtrace(struct frame_tail *tail,
         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
                 return NULL;
 
-        callchain_store(entry, buftail.lr);
+        perf_callchain_store(entry, buftail.lr);
 
         /*
          * Frame pointers should strictly progress back up the stack
@@ -3051,16 +3086,11 @@ user_backtrace(struct frame_tail *tail,
         return buftail.fp - 1;
 }
 
-static void
-perf_callchain_user(struct pt_regs *regs,
-                    struct perf_callchain_entry *entry)
+void
+perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
         struct frame_tail *tail;
 
-        callchain_store(entry, PERF_CONTEXT_USER);
-
-        if (!user_mode(regs))
-                regs = task_pt_regs(current);
 
         tail = (struct frame_tail *)regs->ARM_fp - 1;
 
@@ -3078,56 +3108,18 @@ callchain_trace(struct stackframe *fr,
                 void *data)
 {
         struct perf_callchain_entry *entry = data;
-        callchain_store(entry, fr->pc);
+        perf_callchain_store(entry, fr->pc);
         return 0;
 }
 
-static void
-perf_callchain_kernel(struct pt_regs *regs,
-                      struct perf_callchain_entry *entry)
+void
+perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
         struct stackframe fr;
 
-        callchain_store(entry, PERF_CONTEXT_KERNEL);
         fr.fp = regs->ARM_fp;
         fr.sp = regs->ARM_sp;
         fr.lr = regs->ARM_lr;
         fr.pc = regs->ARM_pc;
         walk_stackframe(&fr, callchain_trace, entry);
 }
-
-static void
-perf_do_callchain(struct pt_regs *regs,
-                  struct perf_callchain_entry *entry)
-{
-        int is_user;
-
-        if (!regs)
-                return;
-
-        is_user = user_mode(regs);
-
-        if (!current || !current->pid)
-                return;
-
-        if (is_user && current->state != TASK_RUNNING)
-                return;
-
-        if (!is_user)
-                perf_callchain_kernel(regs, entry);
-
-        if (current->mm)
-                perf_callchain_user(regs, entry);
-}
-
-static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
-
-struct perf_callchain_entry *
-perf_callchain(struct pt_regs *regs)
-{
-        struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
-
-        entry->nr = 0;
-        perf_do_callchain(regs, entry);
-        return entry;
-}
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 401e38be1f7..e76fcaadce0 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -29,6 +29,7 @@
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
 #include <linux/random.h>
+#include <linux/hw_breakpoint.h>
 
 #include <asm/cacheflush.h>
 #include <asm/leds.h>
@@ -135,6 +136,25 @@ EXPORT_SYMBOL(pm_power_off);
 void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 
+static void do_nothing(void *unused)
+{
+}
+
+/*
+ * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
+ * pm_idle and update to new pm_idle value. Required while changing pm_idle
+ * handler on SMP systems.
+ *
+ * Caller must have changed pm_idle to the new value before the call. Old
+ * pm_idle value will not be used by any CPU after the return of this function.
+ */
+void cpu_idle_wait(void)
+{
+        smp_mb();
+        /* kick all the CPUs so that they exit out of pm_idle */
+        smp_call_function(do_nothing, NULL, 1);
+}
+EXPORT_SYMBOL_GPL(cpu_idle_wait);
 
 /*
  * This is our default idle handler.  We need to disable
@@ -317,6 +337,8 @@ void flush_thread(void)
         struct thread_info *thread = current_thread_info();
         struct task_struct *tsk = current;
 
+        flush_ptrace_hw_breakpoint(tsk);
+
         memset(thread->used_cp, 0, sizeof(thread->used_cp));
         memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
         memset(&thread->fpstate, 0, sizeof(union fp_state));
@@ -345,6 +367,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
         thread->cpu_context.sp = (unsigned long)childregs;
         thread->cpu_context.pc = (unsigned long)ret_from_fork;
 
+        clear_ptrace_hw_breakpoint(p);
+
         if (clone_flags & CLONE_SETTLS)
                 thread->tp_value = regs->ARM_r3;
 
@@ -458,3 +482,24 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
         unsigned long range_end = mm->brk + 0x02000000;
         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 }
+
+/*
+ * The vectors page is always readable from user space for the
+ * atomic helpers and the signal restart code.  Let's declare a mapping
+ * for it so it is visible through ptrace and /proc/<pid>/mem.
+ */
+
+int vectors_user_mapping(void)
+{
+        struct mm_struct *mm = current->mm;
+        return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
+                                       VM_READ | VM_EXEC |
+                                       VM_MAYREAD | VM_MAYEXEC |
+                                       VM_ALWAYSDUMP | VM_RESERVED,
+                                       NULL);
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+        return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL;
+}
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index f99d489822d..e0cb6370ed1 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -19,6 +19,8 @@
 #include <linux/init.h>
 #include <linux/signal.h>
 #include <linux/uaccess.h>
+#include <linux/perf_event.h>
+#include <linux/hw_breakpoint.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -847,6 +849,232 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
 }
 #endif
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+/*
+ * Convert a virtual register number into an index for a thread_info
+ * breakpoint array. Breakpoints are identified using positive numbers
+ * whilst watchpoints are negative. The registers are laid out as pairs
+ * of (address, control), each pair mapping to a unique hw_breakpoint struct.
+ * Register 0 is reserved for describing resource information.
+ */
+static int ptrace_hbp_num_to_idx(long num)
+{
+        if (num < 0)
+                num = (ARM_MAX_BRP << 1) - num;
+        return (num - 1) >> 1;
+}
+
+/*
+ * Returns the virtual register number for the address of the
+ * breakpoint at index idx.
+ */
+static long ptrace_hbp_idx_to_num(int idx)
+{
+        long mid = ARM_MAX_BRP << 1;
+        long num = (idx << 1) + 1;
+        return num > mid ? mid - num : num;
+}
+
+/*
+ * Handle hitting a HW-breakpoint.
+ */
+static void ptrace_hbptriggered(struct perf_event *bp, int unused,
+                                     struct perf_sample_data *data,
+                                     struct pt_regs *regs)
+{
+        struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
+        long num;
+        int i;
+        siginfo_t info;
+
+        for (i = 0; i < ARM_MAX_HBP_SLOTS; ++i)
+                if (current->thread.debug.hbp[i] == bp)
+                        break;
+
+        num = (i == ARM_MAX_HBP_SLOTS) ? 0 : ptrace_hbp_idx_to_num(i);
+
+        info.si_signo   = SIGTRAP;
+        info.si_errno   = (int)num;
+        info.si_code    = TRAP_HWBKPT;
+        info.si_addr    = (void __user *)(bkpt->trigger);
+
+        force_sig_info(SIGTRAP, &info, current);
+}
+
+/*
+ * Set ptrace breakpoint pointers to zero for this task.
+ * This is required in order to prevent child processes from unregistering
+ * breakpoints held by their parent.
+ */
+void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+        memset(tsk->thread.debug.hbp, 0, sizeof(tsk->thread.debug.hbp));
+}
+
+/*
+ * Unregister breakpoints from this task and reset the pointers in
+ * the thread_struct.
+ */
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+        int i;
+        struct thread_struct *t = &tsk->thread;
+
+        for (i = 0; i < ARM_MAX_HBP_SLOTS; i++) {
+                if (t->debug.hbp[i]) {
+                        unregister_hw_breakpoint(t->debug.hbp[i]);
+                        t->debug.hbp[i] = NULL;
+                }
+        }
+}
+
+static u32 ptrace_get_hbp_resource_info(void)
+{
+        u8 num_brps, num_wrps, debug_arch, wp_len;
+        u32 reg = 0;
+
+        num_brps        = hw_breakpoint_slots(TYPE_INST);
+        num_wrps        = hw_breakpoint_slots(TYPE_DATA);
+        debug_arch      = arch_get_debug_arch();
+        wp_len          = arch_get_max_wp_len();
+
+        reg             |= debug_arch;
+        reg             <<= 8;
+        reg             |= wp_len;
+        reg             <<= 8;
+        reg             |= num_wrps;
+        reg             <<= 8;
+        reg             |= num_brps;
+
+        return reg;
+}
+
+static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
+{
+        struct perf_event_attr attr;
+
+        ptrace_breakpoint_init(&attr);
+
+        /* Initialise fields to sane defaults. */
+        attr.bp_addr    = 0;
+        attr.bp_len     = HW_BREAKPOINT_LEN_4;
+        attr.bp_type    = type;
+        attr.disabled   = 1;
+
+        return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, tsk);
+}
+
+static int ptrace_gethbpregs(struct task_struct *tsk, long num,
+                             unsigned long  __user *data)
+{
+        u32 reg;
+        int idx, ret = 0;
+        struct perf_event *bp;
+        struct arch_hw_breakpoint_ctrl arch_ctrl;
+
+        if (num == 0) {
+                reg = ptrace_get_hbp_resource_info();
+        } else {
+                idx = ptrace_hbp_num_to_idx(num);
+                if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) {
+                        ret = -EINVAL;
+                        goto out;
+                }
+
+                bp = tsk->thread.debug.hbp[idx];
+                if (!bp) {
+                        reg = 0;
+                        goto put;
+                }
+
+                arch_ctrl = counter_arch_bp(bp)->ctrl;
+
+                /*
+                 * Fix up the len because we may have adjusted it
+                 * to compensate for an unaligned address.
+                 */
+                while (!(arch_ctrl.len & 0x1))
+                        arch_ctrl.len >>= 1;
+
+                if (idx & 0x1)
+                        reg = encode_ctrl_reg(arch_ctrl);
+                else
+                        reg = bp->attr.bp_addr;
+        }
+
+put:
+        if (put_user(reg, data))
+                ret = -EFAULT;
+
+out:
+        return ret;
+}
+
+static int ptrace_sethbpregs(struct task_struct *tsk, long num,
+                             unsigned long __user *data)
+{
+        int idx, gen_len, gen_type, implied_type, ret = 0;
+        u32 user_val;
+        struct perf_event *bp;
+        struct arch_hw_breakpoint_ctrl ctrl;
+        struct perf_event_attr attr;
+
+        if (num == 0)
+                goto out;
+        else if (num < 0)
+                implied_type = HW_BREAKPOINT_RW;
+        else
+                implied_type = HW_BREAKPOINT_X;
+
+        idx = ptrace_hbp_num_to_idx(num);
+        if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) {
+                ret = -EINVAL;
+                goto out;
+        }
+
+        if (get_user(user_val, data)) {
+                ret = -EFAULT;
+                goto out;
+        }
+
+        bp = tsk->thread.debug.hbp[idx];
+        if (!bp) {
+                bp = ptrace_hbp_create(tsk, implied_type);
+                if (IS_ERR(bp)) {
+                        ret = PTR_ERR(bp);
+                        goto out;
+                }
+                tsk->thread.debug.hbp[idx] = bp;
+        }
+
+        attr = bp->attr;
+
+        if (num & 0x1) {
+                /* Address */
+                attr.bp_addr    = user_val;
+        } else {
+                /* Control */
+                decode_ctrl_reg(user_val, &ctrl);
+                ret = arch_bp_generic_fields(ctrl, &gen_len, &gen_type);
+                if (ret)
+                        goto out;
+
+                if ((gen_type & implied_type) != gen_type) {
+                                ret = -EINVAL;
+                                goto out;
+                }
+
+                attr.bp_len     = gen_len;
+                attr.bp_type    = gen_type;
+                attr.disabled   = !ctrl.enabled;
+        }
+
+        ret = modify_user_hw_breakpoint(bp, &attr);
+out:
+        return ret;
+}
+#endif
+
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
         int ret;
@@ -916,6 +1144,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         break;
 #endif
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+                case PTRACE_GETHBPREGS:
+                        ret = ptrace_gethbpregs(child, addr,
+                                                (unsigned long __user *)data);
+                        break;
+                case PTRACE_SETHBPREGS:
+                        ret = ptrace_sethbpregs(child, addr,
+                                                (unsigned long __user *)data);
+                        break;
+#endif
+
                 default:
                         ret = ptrace_request(child, request, addr, data);
                         break;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae7355..336f14e0e5c 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -36,6 +36,7 @@
 #include <asm/procinfo.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
+#include <asm/smp_plat.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
@@ -238,6 +239,35 @@ int cpu_architecture(void)
         return cpu_arch;
 }
 
+static int cpu_has_aliasing_icache(unsigned int arch)
+{
+        int aliasing_icache;
+        unsigned int id_reg, num_sets, line_size;
+
+        /* arch specifies the register format */
+        switch (arch) {
+        case CPU_ARCH_ARMv7:
+                asm("mcr        p15, 2, %0, c0, c0, 0 @ set CSSELR"
+                    : /* No output operands */
+                    : "r" (1));
+                isb();
+                asm("mrc        p15, 1, %0, c0, c0, 0 @ read CCSIDR"
+                    : "=r" (id_reg));
+                line_size = 4 << ((id_reg & 0x7) + 2);
+                num_sets = ((id_reg >> 13) & 0x7fff) + 1;
+                aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
+                break;
+        case CPU_ARCH_ARMv6:
+                aliasing_icache = read_cpuid_cachetype() & (1 << 11);
+                break;
+        default:
+                /* I-cache aliases will be handled by D-cache aliasing code */
+                aliasing_icache = 0;
+        }
+
+        return aliasing_icache;
+}
+
 static void __init cacheid_init(void)
 {
         unsigned int cachetype = read_cpuid_cachetype();
@@ -249,10 +279,15 @@ static void __init cacheid_init(void)
                         cacheid = CACHEID_VIPT_NONALIASING;
                         if ((cachetype & (3 << 14)) == 1 << 14)
                                 cacheid |= CACHEID_ASID_TAGGED;
-                } else if (cachetype & (1 << 23))
+                        else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))
+                                cacheid |= CACHEID_VIPT_I_ALIASING;
+                } else if (cachetype & (1 << 23)) {
                         cacheid = CACHEID_VIPT_ALIASING;
-                else
+                } else {
                         cacheid = CACHEID_VIPT_NONALIASING;
+                        if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6))
+                                cacheid |= CACHEID_VIPT_I_ALIASING;
+                }
         } else {
                 cacheid = CACHEID_VIVT;
         }
@@ -263,7 +298,7 @@ static void __init cacheid_init(void)
                 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown",
                 cache_is_vivt() ? "VIVT" :
                 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
-                cache_is_vipt_aliasing() ? "VIPT aliasing" :
+                icache_is_vipt_aliasing() ? "VIPT aliasing" :
                 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
 }
 
@@ -490,7 +525,7 @@ request_standard_resources(struct meminfo *mi, struct machine_desc *mdesc)
 
         kernel_code.start   = virt_to_phys(_text);
         kernel_code.end     = virt_to_phys(_etext - 1);
-        kernel_data.start   = virt_to_phys(_data);
+        kernel_data.start   = virt_to_phys(_sdata);
         kernel_data.end     = virt_to_phys(_end - 1);
 
         for (i = 0; i < mi->nr_banks; i++) {
@@ -825,7 +860,8 @@ void __init setup_arch(char **cmdline_p)
         request_standard_resources(&meminfo, mdesc);
 
 #ifdef CONFIG_SMP
-        smp_init_cpus();
+        if (is_smp())
+                smp_init_cpus();
 #endif
         reserve_crashkernel();
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 40dc74f2b27..8c195959025 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -33,6 +33,7 @@
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
+#include <asm/sections.h>
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
 #include <asm/localtimer.h>
@@ -67,12 +68,47 @@ enum ipi_msg_type {
         IPI_CPU_STOP,
 };
 
+static inline void identity_mapping_add(pgd_t *pgd, unsigned long start,
+        unsigned long end)
+{
+        unsigned long addr, prot;
+        pmd_t *pmd;
+
+        prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE;
+        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
+                prot |= PMD_BIT4;
+
+        for (addr = start & PGDIR_MASK; addr < end;) {
+                pmd = pmd_offset(pgd + pgd_index(addr), addr);
+                pmd[0] = __pmd(addr | prot);
+                addr += SECTION_SIZE;
+                pmd[1] = __pmd(addr | prot);
+                addr += SECTION_SIZE;
+                flush_pmd_entry(pmd);
+                outer_clean_range(__pa(pmd), __pa(pmd + 1));
+        }
+}
+
+static inline void identity_mapping_del(pgd_t *pgd, unsigned long start,
+        unsigned long end)
+{
+        unsigned long addr;
+        pmd_t *pmd;
+
+        for (addr = start & PGDIR_MASK; addr < end; addr += PGDIR_SIZE) {
+                pmd = pmd_offset(pgd + pgd_index(addr), addr);
+                pmd[0] = __pmd(0);
+                pmd[1] = __pmd(0);
+                clean_pmd_entry(pmd);
+                outer_clean_range(__pa(pmd), __pa(pmd + 1));
+        }
+}
+
 int __cpuinit __cpu_up(unsigned int cpu)
 {
         struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
         struct task_struct *idle = ci->idle;
         pgd_t *pgd;
-        pmd_t *pmd;
         int ret;
 
         /*
@@ -101,11 +137,16 @@ int __cpuinit __cpu_up(unsigned int cpu)
          * a 1:1 mapping for the physical address of the kernel.
          */
         pgd = pgd_alloc(&init_mm);
-        pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET);
-        *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) |
-                     PMD_TYPE_SECT | PMD_SECT_AP_WRITE);
-        flush_pmd_entry(pmd);
-        outer_clean_range(__pa(pmd), __pa(pmd + 1));
+        if (!pgd)
+                return -ENOMEM;
+
+        if (PHYS_OFFSET != PAGE_OFFSET) {
+#ifndef CONFIG_HOTPLUG_CPU
+                identity_mapping_add(pgd, __pa(__init_begin), __pa(__init_end));
+#endif
+                identity_mapping_add(pgd, __pa(_stext), __pa(_etext));
+                identity_mapping_add(pgd, __pa(_sdata), __pa(_edata));
+        }
 
         /*
          * We need to tell the secondary core where to find
@@ -143,8 +184,14 @@ int __cpuinit __cpu_up(unsigned int cpu)
         secondary_data.stack = NULL;
         secondary_data.pgdir = 0;
 
-        *pmd = __pmd(0);
-        clean_pmd_entry(pmd);
+        if (PHYS_OFFSET != PAGE_OFFSET) {
+#ifndef CONFIG_HOTPLUG_CPU
+                identity_mapping_del(pgd, __pa(__init_begin), __pa(__init_end));
+#endif
+                identity_mapping_del(pgd, __pa(_stext), __pa(_etext));
+                identity_mapping_del(pgd, __pa(_sdata), __pa(_edata));
+        }
+
         pgd_free(&init_mm, pgd);
 
         if (ret) {
@@ -567,7 +614,8 @@ void smp_send_stop(void)
 {
         cpumask_t mask = cpu_online_map;
         cpu_clear(smp_processor_id(), mask);
-        send_ipi_message(&mask, IPI_CPU_STOP);
+        if (!cpus_empty(mask))
+                send_ipi_message(&mask, IPI_CPU_STOP);
 }
 
 /*
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index dd81a918c10..2a161765f6d 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -146,6 +146,8 @@ static struct unwind_idx *unwind_find_idx(unsigned long addr)
                             addr < table->end_addr) {
                                 idx = search_index(addr, table->start,
                                                    table->stop - 1);
+                                /* Move-to-front to exploit common traces */
+                                list_move(&table->list, &unwind_tables);
                                 break;
                         }
                 }
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c07914b5..1953e3d21ab 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -8,6 +8,19 @@
 #include <asm/memory.h>
 #include <asm/page.h>
         
+#define PROC_INFO                                                       \
+        VMLINUX_SYMBOL(__proc_info_begin) = .;                          \
+        *(.proc.info.init)                                              \
+        VMLINUX_SYMBOL(__proc_info_end) = .;
+
+#ifdef CONFIG_HOTPLUG_CPU
+#define ARM_CPU_DISCARD(x)
+#define ARM_CPU_KEEP(x)         x
+#else
+#define ARM_CPU_DISCARD(x)      x
+#define ARM_CPU_KEEP(x)
+#endif
+
 OUTPUT_ARCH(arm)
 ENTRY(stext)
 
@@ -31,15 +44,18 @@ SECTIONS
                         HEAD_TEXT
                         INIT_TEXT
                 _einittext = .;
-                __proc_info_begin = .;
-                        *(.proc.info.init)
-                __proc_info_end = .;
+                ARM_CPU_DISCARD(PROC_INFO)
                 __arch_info_begin = .;
                         *(.arch.info.init)
                 __arch_info_end = .;
                 __tagtable_begin = .;
                         *(.taglist.init)
                 __tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+                __smpalt_begin = .;
+                        *(.alt.smp.init)
+                __smpalt_end = .;
+#endif
 
                 INIT_SETUP(16)
 
@@ -68,10 +84,8 @@ SECTIONS
         /DISCARD/ : {
                 *(.ARM.exidx.exit.text)
                 *(.ARM.extab.exit.text)
-#ifndef CONFIG_HOTPLUG_CPU
-                *(.ARM.exidx.cpuexit.text)
-                *(.ARM.extab.cpuexit.text)
-#endif
+                ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
+                ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
 #ifndef CONFIG_HOTPLUG
                 *(.ARM.exidx.devexit.text)
                 *(.ARM.extab.devexit.text)
@@ -100,12 +114,11 @@ SECTIONS
                         *(.glue_7)
                         *(.glue_7t)
                 *(.got)                 /* Global offset table          */
+                        ARM_CPU_KEEP(PROC_INFO)
         }
 
         RO_DATA(PAGE_SIZE)
 
-        _etext = .;                     /* End of text and rodata section */
-
 #ifdef CONFIG_ARM_UNWIND
         /*
          * Stack unwinding tables
@@ -123,6 +136,8 @@ SECTIONS
         }
 #endif
 
+        _etext = .;                     /* End of text and rodata section */
+
 #ifdef CONFIG_XIP_KERNEL
         __data_loc = ALIGN(4);          /* location in binary */
         . = PAGE_OFFSET + TEXT_OFFSET;
@@ -237,6 +252,12 @@ SECTIONS
 
         /* Default discards */
         DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+        /DISCARD/ : {
+                *(.alt.smp.init)
+        }
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c
index 81a3ecc0d10..0eb3e3e5b2d 100644
--- a/arch/arm/mach-aaec2000/aaed2000.c
+++ b/arch/arm/mach-aaec2000/aaed2000.c
@@ -95,8 +95,6 @@ static void __init aaed2000_map_io(void)
 
 MACHINE_START(AAED2000, "Agilent AAED-2000 Development Platform")
         /* Maintainer: Nicolas Bellido Y Ortega */
-        .phys_io        = PIO_BASE,
-        .io_pg_offst    = ((VIO_BASE) >> 18) & 0xfffc,
         .map_io         = aaed2000_map_io,
         .init_irq       = aaed2000_init_irq,
         .timer          = &aaec2000_timer,
diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
index a9cac368bfe..bc7ad5561c4 100644
--- a/arch/arm/mach-aaec2000/include/mach/debug-macro.S
+++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
@@ -10,12 +10,10 @@
  */
 
 #include "hardware.h"
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x80000000                @ physical
-                movne   \rx, #io_p2v(0x80000000)        @ virtual
-                orr     \rx, \rx, #0x00000800
+                .macro  addruart, rp, rv
+                mov     \rp, 0x00000800
+                orr     \rv, \rp, #io_p2v(0x80000000)   @ virtual
+                orr     \rp, \rp, #0x80000000           @ physical
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
index 551f68f666b..cff4e0a996c 100644
--- a/arch/arm/mach-aaec2000/include/mach/vmalloc.h
+++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
@@ -11,6 +11,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END             (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END             0xd0000000
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 939bccd7056..abed4d15a7f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -33,6 +33,7 @@ config ARCH_AT91SAM9260
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261"
@@ -51,6 +52,7 @@ config ARCH_AT91SAM9263
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
@@ -66,6 +68,7 @@ config ARCH_AT91SAM9G20
         select HAVE_AT91_USART3
         select HAVE_AT91_USART4
         select HAVE_AT91_USART5
+        select HAVE_NET_MACB
 
 config ARCH_AT91SAM9G45
         bool "AT91SAM9G45"
@@ -73,6 +76,7 @@ config ARCH_AT91SAM9G45
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_USART3
         select HAVE_FB_ATMEL
+        select HAVE_NET_MACB
 
 config ARCH_AT91CAP9
         bool "AT91CAP9"
@@ -105,7 +109,7 @@ config MACH_ONEARM
         bool "Ajeco 1ARM Single Board Computer"
         help
           Select this if you are using Ajeco's 1ARM Single Board Computer.
-          <http://www.ajeco.fi/products.htm>
+          <http://www.ajeco.fi/>
 
 config ARCH_AT91RM9200DK
         bool "Atmel AT91RM9200-DK Development board"
@@ -137,7 +141,7 @@ config MACH_CARMEVA
         bool "Conitec ARM&EVA"
         help
           Select this if you are using Conitec's AT91RM9200-MCU-Module.
-          <http://www.conitec.net/english/linuxboard.htm>
+          <http://www.conitec.net/english/linuxboard.php>
 
 config MACH_ATEB9200
         bool "Embest ATEB9200"
@@ -149,7 +153,7 @@ config MACH_KB9200
         bool "KwikByte KB920x"
         help
           Select this if you are using KwikByte's KB920x board.
-          <http://kwikbyte.com/KB9202_description_new.htm>
+          <http://www.kwikbyte.com/KB9202.html>
 
 config MACH_PICOTUX2XX
         bool "picotux 200"
@@ -248,6 +252,12 @@ config MACH_CPU9260
           Select this if you are using a Eukrea Electromatique's
           CPU9260 Board <http://www.eukrea.com/>
 
+config MACH_FLEXIBITY
+        bool "Flexibity Connect board"
+        help
+          Select this if you are using Flexibity Connect board
+          <http://www.flexibity.com>
+
 endif
 
 # ----------------------------------------------------------
@@ -338,6 +348,7 @@ config MACH_AT91SAM9G20EK
           that embeds only one SD/MMC slot.
 
 config MACH_AT91SAM9G20EK_2MMC
+        depends on MACH_AT91SAM9G20EK
         bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
         select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
@@ -383,8 +394,8 @@ if ARCH_AT91SAM9G45
 
 comment "AT91SAM9G45 Board Type"
 
-config MACH_AT91SAM9G45EKES
-        bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
+config MACH_AT91SAM9M10G45EK
+        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
         select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ca2ac003f41..412b3a471a4 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_USB_A9260)	+= board-usb-a9260.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
+obj-$(CONFIG_MACH_FLEXIBITY)    += board-flexibity.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
@@ -61,7 +62,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
 
 # AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
-obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
@@ -70,7 +70,7 @@ obj-$(CONFIG_MACH_PORTUXG20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
 
 # AT91SAM9G45 board-specific support
-obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
+obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 9b27d167bff..46bdc82d3fb 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -92,8 +92,6 @@ static void __init onearm_board_init(void)
 
 MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = onearm_map_io,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 50667bed7cc..cba7f7771fe 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -218,8 +218,6 @@ static void __init afeb9260_board_init(void)
 
 MACHINE_START(AFEB9260, "Custom afeb9260 board")
         /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = afeb9260_map_io,
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
index 5daff277f53..3929f1c9e4e 100644
--- a/arch/arm/mach-at91/board-at572d940hf_ek.c
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -216,7 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = {
 /*      .rdy_pin        = AT91_PIN_PC16, */
         .enable_pin     = AT91_PIN_PA15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
@@ -318,8 +318,6 @@ static void __init eb_board_init(void)
 
 MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
         /* Maintainer: Atmel <costa.antonior@gmail.com> */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = eb_map_io,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 44eb9f76493..b54e3e6fceb 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -198,8 +198,6 @@ static void __init cam60_board_init(void)
 
 MACHINE_START(CAM60, "KwikByte CAM60")
         /* Maintainer: KwikByte */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = cam60_map_io,
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index d6940870e40..e7274440ead 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -399,8 +399,6 @@ static void __init cap9adk_board_init(void)
 
 MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
         /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = cap9adk_map_io,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index db1f9544d2e..2e74a19874d 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -162,8 +162,6 @@ static void __init carmeva_board_init(void)
 
 MACHINE_START(CARMEVA, "Carmeva")
         /* Maintainer: Conitec Datasystems */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = carmeva_map_io,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 4bc2e9f6ebb..3838594578f 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -375,8 +375,6 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
 MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
 #endif
         /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = cpu9krea_map_io,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index a28d9965619..2f4dd8cdd48 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -175,8 +175,6 @@ static void __init cpuat91_board_init(void)
 
 MACHINE_START(CPUAT91, "Eukrea")
         /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = cpuat91_map_io,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index fea2529ebcf..464839dc39b 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -257,8 +257,6 @@ static void __init csb337_board_init(void)
 
 MACHINE_START(CSB337, "Cogent CSB337")
         /* Maintainer: Bill Gatliff */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = csb337_map_io,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index cfa3f04b220..431688c6141 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -138,8 +138,6 @@ static void __init csb637_board_init(void)
 
 MACHINE_START(CSB637, "Cogent CSB637")
         /* Maintainer: Bill Gatliff */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = csb637_map_io,
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c
index 0fd0f5bc77e..e14f0e16568 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-dk.c
@@ -225,8 +225,6 @@ static void __init dk_board_init(void)
 
 MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
         /* Maintainer: SAN People/Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = dk_map_io,
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 528656761ff..6cf6566ae34 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -120,8 +120,6 @@ static void __init eb9200_board_init(void)
 }
 
 MACHINE_START(ATEB9200, "Embest ATEB9200")
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = eb9200_map_io,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 1d69908617f..7b58c948a95 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -168,8 +168,6 @@ static void __init ecb_at91board_init(void)
 
 MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
         /* Maintainer: emQbit.com */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = ecb_at91map_io,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 295a96609e7..a158a0ce458 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -148,8 +148,6 @@ static void __init eco920_board_init(void)
 
 MACHINE_START(ECO920, "eco920")
         /* Maintainer: Sascha Hauer */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = eco920_map_io,
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c
index 4cdfaac8e59..56e92c4bbc2 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-ek.c
@@ -191,8 +191,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
         /* Maintainer: SAN People/Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
new file mode 100644
index 00000000000..c8a62dc8fa6
--- /dev/null
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -0,0 +1,162 @@
+/*
+ * linux/arch/arm/mach-at91/board-flexibity.c
+ *
+ *  Copyright (C) 2010 Flexibity
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+
+#include "generic.h"
+
+static void __init flexibity_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init flexibity_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+/* USB Host port */
+static struct at91_usbh_data __initdata flexibity_usbh_data = {
+        .ports          = 2,
+};
+
+/* USB Device port */
+static struct at91_udc_data __initdata flexibity_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/* SPI devices */
+static struct spi_board_info flexibity_spi_devices[] = {
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+};
+
+/* MCI (SD/MMC) */
+static struct at91_mmc_data __initdata flexibity_mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 1,
+        .det_pin        = AT91_PIN_PC9,
+        .wp_pin         = AT91_PIN_PC4,
+};
+
+/* LEDs */
+static struct gpio_led flexibity_leds[] = {
+        {
+                .name                   = "usb1:green",
+                .gpio                   = AT91_PIN_PA12,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "usb1:red",
+                .gpio                   = AT91_PIN_PA13,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "usb2:green",
+                .gpio                   = AT91_PIN_PB26,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "usb2:red",
+                .gpio                   = AT91_PIN_PB27,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "usb3:green",
+                .gpio                   = AT91_PIN_PC8,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "usb3:red",
+                .gpio                   = AT91_PIN_PC6,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "usb4:green",
+                .gpio                   = AT91_PIN_PB4,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "usb4:red",
+                .gpio                   = AT91_PIN_PB5,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        }
+};
+
+static void __init flexibity_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&flexibity_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&flexibity_udc_data);
+        /* SPI */
+        at91_add_device_spi(flexibity_spi_devices,
+                ARRAY_SIZE(flexibity_spi_devices));
+        /* MMC */
+        at91_add_device_mmc(0, &flexibity_mmc_data);
+        /* LEDs */
+        at91_gpio_leds(flexibity_leds, ARRAY_SIZE(flexibity_leds));
+}
+
+MACHINE_START(FLEXIBITY, "Flexibity Connect")
+        /* Maintainer: Maxim Osipov */
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = flexibity_map_io,
+        .init_irq       = flexibity_init_irq,
+        .init_machine   = flexibity_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index a87956c0a74..c0ce79d431a 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -99,8 +99,6 @@ static void __init kafa_board_init(void)
 
 MACHINE_START(KAFA, "Sperry-Sun KAFA")
         /* Maintainer: Sergei Sharonov */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = kafa_map_io,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index fe9b9913fa3..a13d2063faf 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -136,8 +136,6 @@ static void __init kb9202_board_init(void)
 
 MACHINE_START(KB9200, "KB920x")
         /* Maintainer: KwikByte, Inc. */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = kb9202_map_io,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 7c1e382330f..fe5f1d47e6e 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -387,8 +387,6 @@ static void __init neocore926_board_init(void)
 
 MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
         /* Maintainer: ADENEO */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = neocore926_map_io,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 859727e7ea3..9d833bbc592 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -156,8 +156,6 @@ static void __init picotux200_board_init(void)
 
 MACHINE_START(PICOTUX2XX, "picotux 200")
         /* Maintainer: Kleinhenz Elektronik GmbH */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = picotux200_map_io,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 664938e8f66..69d15a875b6 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -268,8 +268,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
         /* Maintainer: calao-systems */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index b4834697753..25a26beaa72 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -212,8 +212,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
         /* Maintainer: Olimex */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index ba9d501b5c5..de1816e0e1d 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -356,8 +356,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
         /* Maintainer: Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 65eb0943194..14acc901e24 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -623,8 +623,6 @@ MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
 #endif
         /* Maintainer: Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 2d867fb0630..bfe490df58b 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -454,8 +454,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
         /* Maintainer: Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
deleted file mode 100644
index c49f5c003ee..00000000000
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2008 Atmel
- *  Copyright (C) 2009 Rob Emanuele
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/at73c213.h>
-#include <linux/clk.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/at91sam9_smc.h>
-
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init ek_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91sam9260_initialize(18432000);
-
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-
-static void __init ek_init_irq(void)
-{
-        at91sam9260_init_interrupts(NULL);
-}
-
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
-};
-
-
-/*
- * SPI devices.
- */
-static struct spi_board_info ek_spi_devices[] = {
-#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 1,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#endif
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct at91_eth_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PB0,
-        .is_rmii        = 1,
-};
-
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "Bootstrap",
-                .offset = 0,
-                .size   = 4 * SZ_1M,
-        },
-        {
-                .name   = "Partition 1",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 60 * SZ_1M,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
-{
-        *num_partitions = ARRAY_SIZE(ek_nand_partition);
-        return ek_nand_partition;
-}
-
-/* det_pin is not connected */
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-        .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
-};
-
-static struct sam9_smc_config __initdata ek_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 3,
-};
-
-static void __init ek_add_device_nand(void)
-{
-        /* setup bus-width (8 or 16) */
-        if (ek_nand_data.bus_width_16)
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
-
-        at91_add_device_nand(&ek_nand_data);
-}
-
-
-/*
- * MCI (SD/MMC)
- * wp_pin is not connected
- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-static struct mci_platform_data __initdata ek_mmc_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC2,
-                .wp_pin         = -ENODEV,
-        },
-        .slot[1] = {
-                .bus_width      = 4,
-                .detect_pin     = AT91_PIN_PC9,
-                .wp_pin         = -ENODEV,
-        },
-
-};
-#else
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,    /* Only one slot so use slot B */
-        .wire4          = 1,
-        .det_pin        = AT91_PIN_PC9,
-};
-#endif
-
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* "bottom" led, green, userled1 to be defined */
-                .name                   = "ds5",
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-                .default_trigger        = "none",
-        },
-        {       /* "power" led, yellow */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PB9,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("AVDD", "0-001b"),
-        REGULATOR_SUPPLY("HPVDD", "0-001b"),
-        REGULATOR_SUPPLY("DBVDD", "0-001b"),
-        REGULATOR_SUPPLY("DCVDD", "0-001b"),
-};
-
-static struct regulator_init_data ek_avdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .consumer_supplies = ek_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config ek_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 0,
-        .init_data      = &ek_avdd_reg_init_data,
-};
-static struct platform_device ek_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_vdd_pdata,
-        },
-};
-static void __init ek_add_regulators(void)
-{
-        platform_device_register(&ek_voltage_regulator);
-}
-#else
-static void __init ek_add_regulators(void) {}
-#endif
-
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("24c512", 0x50),
-        },
-};
-
-
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&ek_udc_data);
-        /* SPI */
-        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
-        /* NAND */
-        ek_add_device_nand();
-        /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
-        /* Regulators */
-        ek_add_regulators();
-        /* MMC */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-        at91_add_device_mci(0, &ek_mmc_data);
-#else
-        at91_add_device_mmc(0, &ek_mmc_data);
-#endif
-        /* I2C */
-        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-        /* PCK0 provides MCLK to the WM8731 */
-        at91_set_B_periph(AT91_PIN_PC1, 0);
-        /* SSC (for WM8731) */
-        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
-}
-
-MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
-        /* Maintainer: Rob Emanuele */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
-        .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
-        .init_irq       = ek_init_irq,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 6ea9808b886..ca8198b3c16 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -47,6 +47,18 @@
 #include "sam9_smc.h"
 #include "generic.h"
 
+/*
+ * board revision encoding
+ * bit 0:
+ *      0 => 1 sd/mmc slot
+ *      1 => 2 sd/mmc slots connectors (board from revision C)
+ */
+#define HAVE_2MMC       (1 << 0)
+static int inline ek_have_2mmc(void)
+{
+        return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
+}
+
 
 static void __init ek_map_io(void)
 {
@@ -94,7 +106,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
-#if !defined(CONFIG_MMC_AT91)
+#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
         {       /* DataFlash chip */
                 .modalias       = "mtd_dataflash",
                 .chip_select    = 1,
@@ -121,6 +133,13 @@ static struct at91_eth_data __initdata ek_macb_data = {
         .is_rmii        = 1,
 };
 
+static void __init ek_add_device_macb(void)
+{
+        if (ek_have_2mmc())
+                ek_macb_data.phy_irq_pin = AT91_PIN_PB0;
+
+        at91_add_device_eth(&ek_macb_data);
+}
 
 /*
  * NAND flash
@@ -198,13 +217,36 @@ static void __init ek_add_device_nand(void)
 
 /*
  * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
+ * wp_pin and vcc_pin are not connected
  */
+#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+static struct mci_platform_data __initdata ek_mmc_data = {
+        .slot[1] = {
+                .bus_width      = 4,
+                .detect_pin     = AT91_PIN_PC9,
+        },
+
+};
+#else
 static struct at91_mmc_data __initdata ek_mmc_data = {
-        .slot_b         = 1,
+        .slot_b         = 1,    /* Only one slot so use slot B */
         .wire4          = 1,
+        .det_pin        = AT91_PIN_PC9,
 };
+#endif
 
+static void __init ek_add_device_mmc(void)
+{
+#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
+        if (ek_have_2mmc()) {
+                ek_mmc_data.slot[0].bus_width = 4;
+                ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
+        }
+        at91_add_device_mci(0, &ek_mmc_data);
+#else
+        at91_add_device_mmc(0, &ek_mmc_data);
+#endif
+}
 
 /*
  * LEDs
@@ -223,6 +265,15 @@ static struct gpio_led ek_leds[] = {
         }
 };
 
+static void __init ek_add_device_gpio_leds(void)
+{
+        if (ek_have_2mmc()) {
+                ek_leds[0].gpio = AT91_PIN_PB8;
+                ek_leds[1].gpio = AT91_PIN_PB9;
+        }
+
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+}
 
 /*
  * GPIO Buttons
@@ -336,15 +387,15 @@ static void __init ek_board_init(void)
         /* NAND */
         ek_add_device_nand();
         /* Ethernet */
-        at91_add_device_eth(&ek_macb_data);
+        ek_add_device_macb();
         /* Regulators */
         ek_add_regulators();
         /* MMC */
-        at91_add_device_mmc(0, &ek_mmc_data);
+        ek_add_device_mmc();
         /* I2C */
         at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
         /* LEDs */
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        ek_add_device_gpio_leds();
         /* Push Buttons */
         ek_add_device_buttons();
         /* PCK0 provides MCLK to the WM8731 */
@@ -355,8 +406,15 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
         /* Maintainer: Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
+
+MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
+        /* Maintainer: Atmel */
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ee800595594..7913984f6de 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -135,7 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC8,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
@@ -399,10 +399,8 @@ static void __init ek_board_init(void)
         at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
 }
 
-MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
+MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
         /* Maintainer: Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 7ac20f3a206..3bf3408e94c 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -329,8 +329,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
         /* Maintainer: Atmel */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 2c08ae4ad3a..0a99b3cedd7 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -177,8 +177,6 @@ static void __init snapper9260_board_init(void)
 }
 
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = snapper9260_map_io,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 87958274290..5206eef4a67 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -294,8 +294,6 @@ static void __init stamp9g20_board_init(void)
 
 MACHINE_START(PORTUXG20, "taskit PortuxG20")
         /* Maintainer: taskit GmbH */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = portuxg20_map_io,
@@ -305,8 +303,6 @@ MACHINE_END
 
 MACHINE_START(STAMP9G20, "taskit Stamp9G20")
         /* Maintainer: taskit GmbH */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = stamp9g20_map_io,
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
index 905d6ef7680..07784baeae8 100644
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -228,8 +228,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(USB_A9260, "CALAO USB_A9260")
         /* Maintainer: calao-systems */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
index b6a3480383e..b614508931f 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -244,8 +244,6 @@ static void __init ek_board_init(void)
 
 MACHINE_START(USB_A9263, "CALAO USB_A9263")
         /* Maintainer: calao-systems */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
         .map_io         = ek_map_io,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index e22bf051f83..89df00a9d2f 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -594,8 +594,6 @@ static void __init yl9200_board_init(void)
 
 MACHINE_START(YL9200, "uCdragon YL-9200")
         /* Maintainer: S.Birtles */
-        .phys_io        = AT91_BASE_SYS,
-        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
         .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
         .map_io         = yl9200_map_io,
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index d34cdb8abdc..063ac44a020 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -52,4 +52,10 @@
 #define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
 #define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
 
+/*
+ * Support defines for the simple Power Controller module.
+ */
+#define AT91_PS_CR      (AT91_PS + 0)   /* PS Control register */
+#define AT91_PS_CR_CPU  (1 << 0)        /* CPU clock disable bit */
+
 #endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index 9e750a1c1b5..0f959faf74a 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -14,11 +14,9 @@
 #include <mach/hardware.h>
 #include <mach/at91_dbgu.h>
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                         @ MMU enabled?
-        ldreq   \rx, =(AT91_BASE_SYS + AT91_DBGU)               @ System peripherals (phys address)
-        ldrne   \rx, =(AT91_VA_BASE_SYS + AT91_DBGU)            @ System peripherals (virt address)
+        .macro  addruart, rp, rv
+        ldr     \rp, =(AT91_BASE_SYS + AT91_DBGU)               @ System peripherals (phys address)
+        ldr     \rv, =(AT91_VA_BASE_SYS + AT91_DBGU)            @ System peripherals (virt address)
         .endm
 
         .macro  senduart,rd,rx
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index c80e090b367..36af14bc13b 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -28,17 +28,20 @@
 
 static inline void arch_idle(void)
 {
-#ifndef CONFIG_DEBUG_KERNEL
         /*
          * Disable the processor clock.  The processor will be automatically
          * re-enabled by an interrupt or by a reset.
          */
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+#ifdef AT91_PS
+        at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
 #else
+        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+#endif
+#ifndef CONFIG_CPU_ARM920T
         /*
          * Set the processor (CP15) into 'Wait for Interrupt' mode.
-         * Unlike disabling the processor clock via the PMC (above)
-         *  this allows the processor to be woken via JTAG.
+         * Post-RM9200 processors need this in conjunction with the above
+         * to save power when idle.
          */
         cpu_do_idle();
 #endif
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 2f139196d63..73eb066d232 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -167,8 +167,6 @@ static void __init bcmring_fixup(struct machine_desc *desc,
 
 MACHINE_START(BCMRING, "BCMRING")
         /* Maintainer: Broadcom Corporation */
-        .phys_io = MM_IO_START,
-        .io_pg_offst = (MM_IO_BASE >> 18) & 0xfffc,
         .fixup = bcmring_fixup,
         .map_io = bcmring_map_io,
         .init_irq = bcmring_init_irq,
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index 29c0a911df2..77eb35c89cd 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -691,7 +691,7 @@ int dma_init(void)
 
         memset(&gDMA, 0, sizeof(gDMA));
 
-        init_MUTEX_LOCKED(&gDMA.lock);
+        sema_init(&gDMA.lock, 0);
         init_waitqueue_head(&gDMA.freeChannelQ);
 
         /* Initialize the Hardware */
@@ -1574,7 +1574,7 @@ int dma_init_mem_map(DMA_MemMap_t *memMap)
 {
         memset(memMap, 0, sizeof(*memMap));
 
-        init_MUTEX(&memMap->lock);
+        sema_init(&memMap->lock, 1);
 
         return 0;
 }
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
index 35e2ead8395..3db3a09fd39 100644
--- a/arch/arm/mach-bcmring/include/mach/vmalloc.h
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -22,4 +22,4 @@
  * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
  * larger physical memory designs better.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#define VMALLOC_END       0xf0000000
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index dc1c4939b0c..e3152631eb3 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -67,21 +67,21 @@ static void bcmring_unmask_irq2(unsigned int irq)
 }
 
 static struct irq_chip bcmring_irq0_chip = {
-        .typename = "ARM-INTC0",
+        .name = "ARM-INTC0",
         .ack = bcmring_mask_irq0,
         .mask = bcmring_mask_irq0,      /* mask a specific interrupt, blocking its delivery. */
         .unmask = bcmring_unmask_irq0,  /* unmaks an interrupt */
 };
 
 static struct irq_chip bcmring_irq1_chip = {
-        .typename = "ARM-INTC1",
+        .name = "ARM-INTC1",
         .ack = bcmring_mask_irq1,
         .mask = bcmring_mask_irq1,
         .unmask = bcmring_unmask_irq1,
 };
 
 static struct irq_chip bcmring_irq2_chip = {
-        .typename = "ARM-SINTC",
+        .name = "ARM-SINTC",
         .ack = bcmring_mask_irq2,
         .mask = bcmring_mask_irq2,
         .unmask = bcmring_unmask_irq2,
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 5f18eccdc72..4a74b2c959b 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -64,8 +64,6 @@ void __init autcpu12_map_io(void)
 
 MACHINE_START(AUTCPU12, "autronix autcpu12")
         /* Maintainer: Thomas Gleixner */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xff000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0020000,
         .map_io         = autcpu12_map_io,
         .init_irq       = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index 71a80b5b8ad..5a1689d4879 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -55,8 +55,6 @@ static void __init cdb89712_map_io(void)
 
 MACHINE_START(CDB89712, "Cirrus-CDB89712")
         /* Maintainer: Ray Lehtiniemi */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xff000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = cdb89712_map_io,
         .init_irq       = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index 8ada2018497..16481cf3e93 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -56,8 +56,6 @@ static void __init ceiva_map_io(void)
 
 MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
         /* Maintainer: Rob Scott */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xff000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = ceiva_map_io,
         .init_irq       = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 3c3bf45039f..67b5abb4a60 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -37,8 +37,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
         /* Maintainer: Nobody */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xff000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .fixup          = fixup_clep7312,
         .map_io         = clps711x_map_io,
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index 4a7a2322979..98ca5b2e940 100644
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -57,8 +57,6 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         /* Maintainer: Jon McClintock */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xff000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0020100,   /* 0xc0000000 - 0xc001ffff can be video RAM */
         .fixup          = fixup_edb7211,
         .map_io         = edb7211_map_io,
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index a696099aa4f..b1cb479e71e 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -75,8 +75,6 @@ fortunet_fixup(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(FORTUNET, "ARM-FortuNet")
         /* Maintainer: FortuNet Inc. */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf0000000) >> 18) & 0xfffc,
         .boot_params    = 0x00000000,
         .fixup          = fortunet_fixup,
         .map_io         = clps711x_map_io,
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 072cc6b61ba..507c6873b7e 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -14,16 +14,14 @@
 #include <mach/hardware.h>
 #include <asm/hardware/clps7111.h>
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #CLPS7111_PHYS_BASE
-                movne   \rx, #CLPS7111_VIRT_BASE
+                .macro  addruart, rp, rv
 #ifndef CONFIG_DEBUG_CLPS711X_UART2
-                add     \rx, \rx, #0x0000       @ UART1
+                mov     \rp, #0x0000    @ UART1
 #else
-                add     \rx, \rx, #0x1000       @ UART2
+                mov     \rp, #0x1000    @ UART2
 #endif
+                orr     \rv, \rp, #CLPS7111_VIRT_BASE
+                orr     \rp, \rp, #CLPS7111_PHYS_BASE
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
index ea6cc7beff2..30b3a287ed8 100644
--- a/arch/arm/mach-clps711x/include/mach/vmalloc.h
+++ b/arch/arm/mach-clps711x/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 0d94a30fd6f..cefbce0480b 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -89,8 +89,6 @@ static void __init p720t_map_io(void)
 
 MACHINE_START(P720T, "ARM-Prospector720T")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xff000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .fixup          = fixup_p720t,
         .map_io         = p720t_map_io,
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 9df8391fd78..90fe9ab8591 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -142,8 +142,6 @@ static void __init cns3420_map_io(void)
 }
 
 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
-        .phys_io        = CNS3XXX_UART0_BASE,
-        .io_pg_offst    = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = cns3420_map_io,
         .init_irq       = cns3xxx_init_irq,
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
index d16ce7eb00e..56d828634db 100644
--- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
@@ -10,12 +10,10 @@
  * published by the Free Software Foundation.
  */
 
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xf0000000   @ virtual base
-                orr     \rx, \rx, #0x00009000
+                .macro  addruart,rp,rv
+                mov     \rp, #0x00009000
+                orr     \rv, \rp, #0xf0000000   @ virtual base
+                orr     \rp, \rp, #0x10000000
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 71f90f86474..b77b860b36d 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -20,23 +20,23 @@ config ARCH_DAVINCI_DM644x
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM355
-        bool "DaVinci 355 based system"
+        bool "DaVinci 355 based system"
         select AINTC
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM646x
-        bool "DaVinci 646x based system"
+        bool "DaVinci 646x based system"
         select AINTC
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DA830
-        bool "DA830/OMAP-L137 based system"
+        bool "DA830/OMAP-L137/AM17x based system"
         select CP_INTC
         select ARCH_DAVINCI_DA8XX
         select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
 
 config ARCH_DAVINCI_DA850
-        bool "DA850/OMAP-L138 based system"
+        bool "DA850/OMAP-L138/AM18x based system"
         select CP_INTC
         select ARCH_DAVINCI_DA8XX
         select ARCH_HAS_CPUFREQ
@@ -115,21 +115,21 @@ config MACH_DAVINCI_DM365_EVM
           for development is a DM365 EVM
 
 config MACH_DAVINCI_DA830_EVM
-        bool "TI DA830/OMAP-L137 Reference Platform"
+        bool "TI DA830/OMAP-L137/AM17x Reference Platform"
         default ARCH_DAVINCI_DA830
         depends on ARCH_DAVINCI_DA830
         select GPIO_PCF857X
         help
-          Say Y here to select the TI DA830/OMAP-L137 Evaluation Module.
+          Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
 
 choice
-        prompt "Select DA830/OMAP-L137 UI board peripheral"
+        prompt "Select DA830/OMAP-L137/AM17x UI board peripheral"
         depends on MACH_DAVINCI_DA830_EVM
         help
-          The presence of UI card on the DA830/OMAP-L137 EVM is detected
-          automatically based on successful probe of the I2C based GPIO
-          expander on that board. This option selected in this menu has
-          an effect only in case of a successful UI card detection.
+          The presence of UI card on the DA830/OMAP-L137/AM17x EVM is
+          detected automatically based on successful probe of the I2C
+          based GPIO expander on that board. This option selected in this
+          menu has an effect only in case of a successful UI card detection.
 
 config DA830_UI_LCD
         bool "LCD"
@@ -140,23 +140,23 @@ config DA830_UI_LCD
 config DA830_UI_NAND
         bool "NAND flash"
         help
-          Say Y here to use the NAND flash.  Do not forget to setup
+          Say Y here to use the NAND flash. Do not forget to setup
           the switch correctly.
 endchoice
 
 config MACH_DAVINCI_DA850_EVM
-        bool "TI DA850/OMAP-L138 Reference Platform"
+        bool "TI DA850/OMAP-L138/AM18x Reference Platform"
         default ARCH_DAVINCI_DA850
         depends on ARCH_DAVINCI_DA850
         select GPIO_PCA953X
         help
-          Say Y here to select the TI DA850/OMAP-L138 Evaluation Module.
+          Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.
 
 choice
         prompt "Select peripherals connected to expander on UI board"
         depends on MACH_DAVINCI_DA850_EVM
         help
-          The presence of User Interface (UI) card on the DA850/OMAP-L138
+          The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x
           EVM is detected automatically based on successful probe of the I2C
           based GPIO expander on that card. This option selected in this
           menu has an effect only in case of a successful UI card detection.
@@ -165,13 +165,13 @@ config DA850_UI_NONE
         bool "No peripheral is enabled"
         help
           Say Y if you do not want to enable any of the peripherals connected
-          to TCA6416 expander on DA850/OMAP-L138 EVM UI card
+          to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card
 
 config DA850_UI_RMII
         bool "RMII Ethernet PHY"
         help
-          Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM.
-          This PHY is found on the UI daughter card that is supplied with
+          Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x
+          EVM. This PHY is found on the UI daughter card that is supplied with
           the EVM.
           NOTE: Please take care while choosing this option, MII PHY will
           not be functional if RMII mode is selected.
@@ -185,6 +185,22 @@ config MACH_TNETV107X
         help
           Say Y here to select the TI TNETV107X Evaluation Module.
 
+config MACH_MITYOMAPL138
+        bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
+        depends on ARCH_DAVINCI_DA850
+        help
+          Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
+          System on Module.  Information on this SoM may be found at
+          http://www.mitydsp.com
+
+config MACH_OMAPL138_HAWKBOARD
+        bool "TI AM1808 / OMAPL-138 Hawkboard platform"
+        depends on ARCH_DAVINCI_DA850
+        help
+          Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform .
+          Information of this board may be found at
+          http://www.hawkboard.org/
+
 config DAVINCI_MUX
         bool "DAVINCI multiplexing support"
         depends on ARCH_DAVINCI
@@ -195,20 +211,20 @@ config DAVINCI_MUX
           say Y.
 
 config DAVINCI_MUX_DEBUG
-        bool "Multiplexing debug output"
-        depends on DAVINCI_MUX
-        help
-          Makes the multiplexing functions print out a lot of debug info.
-          This is useful if you want to find out the correct values of the
-          multiplexing registers.
+        bool "Multiplexing debug output"
+        depends on DAVINCI_MUX
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
 
 config DAVINCI_MUX_WARNINGS
-        bool "Warn about pins the bootloader didn't set up"
-        depends on DAVINCI_MUX
-        help
-          Choose Y here to warn whenever driver initialization logic needs
-          to change the pin multiplexing setup.  When there are no warnings
-          printed, it's safe to deselect DAVINCI_MUX for your product.
+        bool "Warn about pins the bootloader didn't set up"
+        depends on DAVINCI_MUX
+        help
+          Choose Y here to warn whenever driver initialization logic needs
+          to change the pin multiplexing setup. When there are no warnings
+          printed, it's safe to deselect DAVINCI_MUX for your product.
 
 config DAVINCI_RESET_CLOCKS
         bool "Reset unused clocks during boot"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index eab4c0fd667..0b87a1ca2bb 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
 
 # Common objects
 obj-y                   := time.o clock.o serial.o io.o psc.o \
-                           gpio.o dma.o usb.o common.o sram.o
+                           gpio.o dma.o usb.o common.o sram.o aemif.o
 
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
 
@@ -33,6 +33,8 @@ obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)    += board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)    += board-da850-evm.o
 obj-$(CONFIG_MACH_TNETV107X)            += board-tnetv107x-evm.o
+obj-$(CONFIG_MACH_MITYOMAPL138)         += board-mityomapl138.o
+obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)   += board-omapl138-hawk.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)                  += cpufreq.o
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
new file mode 100644
index 00000000000..9c3f500fc12
--- /dev/null
+++ b/arch/arm/mach-davinci/aemif.c
@@ -0,0 +1,133 @@
+/*
+ * AEMIF support for DaVinci SoCs
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/time.h>
+
+#include <mach/aemif.h>
+
+/* Timing value configuration */
+
+#define TA(x)           ((x) << 2)
+#define RHOLD(x)        ((x) << 4)
+#define RSTROBE(x)      ((x) << 7)
+#define RSETUP(x)       ((x) << 13)
+#define WHOLD(x)        ((x) << 17)
+#define WSTROBE(x)      ((x) << 20)
+#define WSETUP(x)       ((x) << 26)
+
+#define TA_MAX          0x3
+#define RHOLD_MAX       0x7
+#define RSTROBE_MAX     0x3f
+#define RSETUP_MAX      0xf
+#define WHOLD_MAX       0x7
+#define WSTROBE_MAX     0x3f
+#define WSETUP_MAX      0xf
+
+#define TIMING_MASK     (TA(TA_MAX) | \
+                                RHOLD(RHOLD_MAX) | \
+                                RSTROBE(RSTROBE_MAX) |  \
+                                RSETUP(RSETUP_MAX) | \
+                                WHOLD(WHOLD_MAX) | \
+                                WSTROBE(WSTROBE_MAX) | \
+                                WSETUP(WSETUP_MAX))
+
+/*
+ * aemif_calc_rate - calculate timing data.
+ * @wanted: The cycle time needed in nanoseconds.
+ * @clk: The input clock rate in kHz.
+ * @max: The maximum divider value that can be programmed.
+ *
+ * On success, returns the calculated timing value minus 1 for easy
+ * programming into AEMIF timing registers, else negative errno.
+ */
+static int aemif_calc_rate(int wanted, unsigned long clk, int max)
+{
+        int result;
+
+        result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
+
+        pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted);
+
+        /* It is generally OK to have a more relaxed timing than requested... */
+        if (result < 0)
+                result = 0;
+
+        /* ... But configuring tighter timings is not an option. */
+        else if (result > max)
+                result = -EINVAL;
+
+        return result;
+}
+
+/**
+ * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface
+ * @t: timing values to be progammed
+ * @base: The virtual base address of the AEMIF interface
+ * @cs: chip-select to program the timing values for
+ *
+ * This function programs the given timing values (in real clock) into the
+ * AEMIF registers taking the AEMIF clock into account.
+ *
+ * This function does not use any locking while programming the AEMIF
+ * because it is expected that there is only one user of a given
+ * chip-select.
+ *
+ * Returns 0 on success, else negative errno.
+ */
+int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+                                        void __iomem *base, unsigned cs)
+{
+        unsigned set, val;
+        unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
+        unsigned offset = A1CR_OFFSET + cs * 4;
+        struct clk *aemif_clk;
+        unsigned long clkrate;
+
+        if (!t)
+                return 0;       /* Nothing to do */
+
+        aemif_clk = clk_get(NULL, "aemif");
+        if (IS_ERR(aemif_clk))
+                return PTR_ERR(aemif_clk);
+
+        clkrate = clk_get_rate(aemif_clk);
+
+        clkrate /= 1000;        /* turn clock into kHz for ease of use */
+
+        ta      = aemif_calc_rate(t->ta, clkrate, TA_MAX);
+        rhold   = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX);
+        rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX);
+        rsetup  = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX);
+        whold   = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX);
+        wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX);
+        wsetup  = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX);
+
+        if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
+                        whold < 0 || wstrobe < 0 || wsetup < 0) {
+                pr_err("%s: cannot get suitable timings\n", __func__);
+                return -EINVAL;
+        }
+
+        set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
+                WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
+
+        val = __raw_readl(base + offset);
+        val &= ~TIMING_MASK;
+        val |= set;
+        __raw_writel(val, base + offset);
+
+        return 0;
+}
+EXPORT_SYMBOL(davinci_aemif_setup_timing);
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index c3994f341e4..b52a3a1abd9 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -29,10 +29,9 @@
 #include <mach/nand.h>
 #include <mach/da8xx.h>
 #include <mach/usb.h>
+#include <mach/aemif.h>
 
-#define DA830_EVM_PHY_MASK              0x0
-#define DA830_EVM_MDIO_FREQUENCY        2200000 /* PHY bus frequency */
-
+#define DA830_EVM_PHY_ID                ""
 /*
  * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
  */
@@ -360,6 +359,16 @@ static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
         .pattern        = da830_evm_nand_mirror_pattern
 };
 
+static struct davinci_aemif_timing da830_evm_nandflash_timing = {
+        .wsetup         = 24,
+        .wstrobe        = 21,
+        .whold          = 14,
+        .rsetup         = 19,
+        .rstrobe        = 50,
+        .rhold          = 0,
+        .ta             = 20,
+};
+
 static struct davinci_nand_pdata da830_evm_nand_pdata = {
         .parts          = da830_evm_nand_partitions,
         .nr_parts       = ARRAY_SIZE(da830_evm_nand_partitions),
@@ -368,6 +377,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
         .options        = NAND_USE_FLASH_BBT,
         .bbt_td         = &da830_evm_nand_bbt_main_descr,
         .bbt_md         = &da830_evm_nand_bbt_mirror_descr,
+        .timing         = &da830_evm_nandflash_timing,
 };
 
 static struct resource da830_evm_nand_resources[] = {
@@ -546,9 +556,8 @@ static __init void da830_evm_init(void)
 
         da830_evm_usb_init();
 
-        soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
         soc_info->emac_pdata->rmii_en = 1;
+        soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID;
 
         ret = davinci_cfg_reg_list(da830_cpgmac_pins);
         if (ret)
@@ -586,6 +595,9 @@ static __init void da830_evm_init(void)
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 static int __init da830_evm_console_init(void)
 {
+        if (!machine_is_davinci_da830_evm())
+                return 0;
+
         return add_preferred_console("ttyS", 2, "115200");
 }
 console_initcall(da830_evm_console_init);
@@ -596,9 +608,7 @@ static void __init da830_evm_map_io(void)
         da830_init();
 }
 
-MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
         .boot_params    = (DA8XX_DDR_BASE + 0x100),
         .map_io         = da830_evm_map_io,
         .init_irq       = cp_intc_init,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index fdc2cc500fc..c6e11c682e4 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -26,7 +26,6 @@
 #include <linux/mtd/physmap.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/tps6507x.h>
-#include <linux/mfd/tps6507x.h>
 #include <linux/input/tps6507x-ts.h>
 
 #include <asm/mach-types.h>
@@ -36,10 +35,9 @@
 #include <mach/da8xx.h>
 #include <mach/nand.h>
 #include <mach/mux.h>
+#include <mach/aemif.h>
 
-#define DA850_EVM_PHY_MASK              0x1
-#define DA850_EVM_MDIO_FREQUENCY        2200000 /* PHY bus frequency */
-
+#define DA850_EVM_PHY_ID                "0:00"
 #define DA850_LCD_PWR_PIN               GPIO_TO_PIN(2, 8)
 #define DA850_LCD_BL_PIN                GPIO_TO_PIN(2, 15)
 
@@ -110,7 +108,7 @@ static struct platform_device da850_pm_device = {
  * to boot, using TI's tools to install the secondary boot loader
  * (UBL) and U-Boot.
  */
-struct mtd_partition da850_evm_nandflash_partition[] = {
+static struct mtd_partition da850_evm_nandflash_partition[] = {
         {
                 .name           = "u-boot env",
                 .offset         = 0,
@@ -143,12 +141,23 @@ struct mtd_partition da850_evm_nandflash_partition[] = {
         },
 };
 
+static struct davinci_aemif_timing da850_evm_nandflash_timing = {
+        .wsetup         = 24,
+        .wstrobe        = 21,
+        .whold          = 14,
+        .rsetup         = 19,
+        .rstrobe        = 50,
+        .rhold          = 0,
+        .ta             = 20,
+};
+
 static struct davinci_nand_pdata da850_evm_nandflash_data = {
         .parts          = da850_evm_nandflash_partition,
         .nr_parts       = ARRAY_SIZE(da850_evm_nandflash_partition),
         .ecc_mode       = NAND_ECC_HW,
         .ecc_bits       = 4,
         .options        = NAND_USE_FLASH_BBT,
+        .timing         = &da850_evm_nandflash_timing,
 };
 
 static struct resource da850_evm_nandflash_resource[] = {
@@ -196,6 +205,30 @@ static void __init da850_evm_init_nor(void)
         iounmap(aemif_addr);
 }
 
+static const short da850_evm_nand_pins[] = {
+        DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
+        DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
+        DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
+        DA850_NEMA_WE, DA850_NEMA_OE,
+        -1
+};
+
+static const short da850_evm_nor_pins[] = {
+        DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
+        DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
+        DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
+        DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
+        DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
+        DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
+        DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
+        DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
+        DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
+        DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
+        DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
+        DA850_EMA_A_22, DA850_EMA_A_23,
+        -1
+};
+
 static u32 ui_card_detected;
 
 #if defined(CONFIG_MMC_DAVINCI) || \
@@ -205,17 +238,17 @@ static u32 ui_card_detected;
 #define HAS_MMC 0
 #endif
 
-static __init void da850_evm_setup_nor_nand(void)
+static inline void da850_evm_setup_nor_nand(void)
 {
         int ret = 0;
 
         if (ui_card_detected & !HAS_MMC) {
-                ret = davinci_cfg_reg_list(da850_nand_pins);
+                ret = davinci_cfg_reg_list(da850_evm_nand_pins);
                 if (ret)
                         pr_warning("da850_evm_init: nand mux setup failed: "
                                         "%d\n", ret);
 
-                ret = davinci_cfg_reg_list(da850_nor_pins);
+                ret = davinci_cfg_reg_list(da850_evm_nor_pins);
                 if (ret)
                         pr_warning("da850_evm_init: nor mux setup failed: %d\n",
                                 ret);
@@ -406,7 +439,7 @@ static int da850_lcd_hw_init(void)
 /* TPS65070 voltage regulator support */
 
 /* 3.3V */
-struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
+static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
         {
                 .supply = "usb0_vdda33",
         },
@@ -416,7 +449,7 @@ struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
 };
 
 /* 3.3V or 1.8V */
-struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
+static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
         {
                 .supply = "dvdd3318_a",
         },
@@ -429,14 +462,14 @@ struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
 };
 
 /* 1.2V */
-struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
+static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
         {
                 .supply = "cvdd",
         },
 };
 
 /* 1.8V LDO */
-struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
+static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
         {
                 .supply = "sata_vddr",
         },
@@ -452,7 +485,7 @@ struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
 };
 
 /* 1.2V LDO */
-struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
+static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
         {
                 .supply = "sata_vdd",
         },
@@ -475,7 +508,7 @@ static struct tps6507x_reg_platform_data tps6507x_platform_data = {
         .defdcdc_default = true,
 };
 
-struct regulator_init_data tps65070_regulator_data[] = {
+static struct regulator_init_data tps65070_regulator_data[] = {
         /* dcdc1 */
         {
                 .constraints = {
@@ -576,6 +609,23 @@ static const short da850_evm_lcdc_pins[] = {
         -1
 };
 
+static const short da850_evm_mii_pins[] = {
+        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static const short da850_evm_rmii_pins[] = {
+        DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
+        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
+        DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
 static int __init da850_evm_config_emac(void)
 {
         void __iomem *cfg_chip3_base;
@@ -593,12 +643,12 @@ static int __init da850_evm_config_emac(void)
 
         if (rmii_en) {
                 val |= BIT(8);
-                ret = davinci_cfg_reg_list(da850_rmii_pins);
+                ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
                 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
                                                         " functional\n");
         } else {
                 val &= ~BIT(8);
-                ret = davinci_cfg_reg_list(da850_cpgmac_pins);
+                ret = davinci_cfg_reg_list(da850_evm_mii_pins);
                 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
                                                         " functional\n");
         }
@@ -625,8 +675,7 @@ static int __init da850_evm_config_emac(void)
         /* Enable/Disable MII MDIO clock */
         gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
 
-        soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
 
         ret = da8xx_register_emac();
         if (ret)
@@ -787,7 +836,7 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
 
-        ret = da850_register_cpufreq();
+        ret = da850_register_cpufreq("pll0_sysclk3");
         if (ret)
                 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
                                 ret);
@@ -806,6 +855,9 @@ static __init void da850_evm_init(void)
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 static int __init da850_evm_console_init(void)
 {
+        if (!machine_is_davinci_da850_evm())
+                return 0;
+
         return add_preferred_console("ttyS", 2, "115200");
 }
 console_initcall(da850_evm_console_init);
@@ -816,9 +868,7 @@ static void __init da850_evm_map_io(void)
         da850_init();
 }
 
-MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
         .boot_params    = (DA8XX_DDR_BASE + 0x100),
         .map_io         = da850_evm_map_io,
         .init_irq       = cp_intc_init,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index a3191015efe..6e7cad13352 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -351,8 +351,6 @@ static __init void dm355_evm_init(void)
 }
 
 MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = dm355_evm_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index f1d8132cf0c..543f9911b28 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -270,8 +270,6 @@ static __init void dm355_leopard_init(void)
 }
 
 MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = dm355_leopard_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 84acef1d0b3..c67f684ee3e 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,9 +54,7 @@ static inline int have_tvp7002(void)
         return 0;
 }
 
-#define DM365_EVM_PHY_MASK              (0x2)
-#define DM365_EVM_MDIO_FREQUENCY        (2200000) /* PHY bus frequency */
-
+#define DM365_EVM_PHY_ID                "0:01"
 /*
  * A MAX-II CPLD is used for various board control functions.
  */
@@ -175,7 +173,9 @@ static struct at24_platform_data eeprom_info = {
         .context        = (void *)0x7f00,
 };
 
-static struct snd_platform_data dm365_evm_snd_data;
+static struct snd_platform_data dm365_evm_snd_data = {
+        .asp_chan_q = EVENTQ_3,
+};
 
 static struct i2c_board_info i2c_info[] = {
         {
@@ -533,8 +533,7 @@ fail:
 
                 /* ... and ENET ... */
                 dm365evm_emac_configure();
-                soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
-                soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
+                soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
                 resets &= ~BIT(3);
 
                 /* ... and AIC33 */
@@ -613,8 +612,6 @@ static __init void dm365_evm_init(void)
 }
 
 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params    = (0x80000100),
         .map_io         = dm365_evm_map_io,
         .init_irq       = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 34c8b418cd7..0ca90b83458 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -37,10 +37,9 @@
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
+#include <mach/aemif.h>
 
-#define DM644X_EVM_PHY_MASK             (0x2)
-#define DM644X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
-
+#define DM644X_EVM_PHY_ID               "0:01"
 #define LXT971_PHY_ID   (0x001378e2)
 #define LXT971_PHY_MASK (0xfffffff0)
 
@@ -137,11 +136,22 @@ static struct mtd_partition davinci_evm_nandflash_partition[] = {
          */
 };
 
+static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
+        .wsetup         = 20,
+        .wstrobe        = 40,
+        .whold          = 20,
+        .rsetup         = 10,
+        .rstrobe        = 40,
+        .rhold          = 10,
+        .ta             = 40,
+};
+
 static struct davinci_nand_pdata davinci_evm_nandflash_data = {
         .parts          = davinci_evm_nandflash_partition,
         .nr_parts       = ARRAY_SIZE(davinci_evm_nandflash_partition),
         .ecc_mode       = NAND_ECC_HW,
         .options        = NAND_USE_FLASH_BBT,
+        .timing         = &davinci_evm_nandflash_timing,
 };
 
 static struct resource davinci_evm_nandflash_resource[] = {
@@ -695,9 +705,7 @@ static __init void davinci_evm_init(void)
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_evm_snd_data);
 
-        soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
-
+        soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
         /* Register the fixup for PHY on DaVinci */
         phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
                                         davinci_phy_fixup);
@@ -706,8 +714,6 @@ static __init void davinci_evm_init(void)
 
 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
         /* Maintainer: MontaVista Software <source@mvista.com> */
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (DAVINCI_DDR_BASE + 0x100),
         .map_io       = davinci_evm_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 4502f346b2b..f6ac9ba7487 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -42,6 +42,7 @@
 #include <mach/nand.h>
 #include <mach/clock.h>
 #include <mach/cdce949.h>
+#include <mach/aemif.h>
 
 #include "clock.h"
 
@@ -71,6 +72,16 @@ static struct mtd_partition davinci_nand_partitions[] = {
         }
 };
 
+static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
+        .wsetup         = 29,
+        .wstrobe        = 24,
+        .whold          = 14,
+        .rsetup         = 19,
+        .rstrobe        = 33,
+        .rhold          = 0,
+        .ta             = 29,
+};
+
 static struct davinci_nand_pdata davinci_nand_data = {
         .mask_cle               = 0x80000,
         .mask_ale               = 0x40000,
@@ -718,9 +729,7 @@ static struct davinci_uart_config uart_config __initdata = {
         .enabled_uarts = (1 << 0),
 };
 
-#define DM646X_EVM_PHY_MASK             (0x2)
-#define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
-
+#define DM646X_EVM_PHY_ID               "0:01"
 /*
  * The following EDMA channels/slots are not being used by drivers (for
  * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
@@ -763,6 +772,9 @@ static __init void evm_init(void)
         dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
         dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
 
+        if (machine_is_davinci_dm6467tevm())
+                davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
+
         platform_device_register(&davinci_nand_device);
 
         dm646x_init_edma(dm646x_edma_rsv);
@@ -770,8 +782,7 @@ static __init void evm_init(void)
         if (HAS_ATA)
                 davinci_init_ide();
 
-        soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
 }
 
 #define DM646X_EVM_REF_FREQ             27000000
@@ -786,8 +797,6 @@ void __init dm646x_board_setup_refclk(struct clk *clk)
 }
 
 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = davinci_map_io,
         .init_irq     = davinci_irq_init,
@@ -796,8 +805,6 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
 MACHINE_END
 
 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (0x80000100),
         .map_io       = davinci_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
new file mode 100644
index 00000000000..0bb5f0ce4fd
--- /dev/null
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -0,0 +1,422 @@
+/*
+ * Critical Link MityOMAP-L138 SoM
+ *
+ * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of
+ * any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/regulator/machine.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/etherdevice.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/common.h>
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+#include <mach/nand.h>
+#include <mach/mux.h>
+
+#define MITYOMAPL138_PHY_ID             "0:03"
+
+#define FACTORY_CONFIG_MAGIC    0x012C0138
+#define FACTORY_CONFIG_VERSION  0x00010001
+
+/* Data Held in On-Board I2C device */
+struct factory_config {
+        u32     magic;
+        u32     version;
+        u8      mac[6];
+        u32     fpga_type;
+        u32     spare;
+        u32     serialnumber;
+        char    partnum[32];
+};
+
+static struct factory_config factory_config;
+
+static void read_factory_config(struct memory_accessor *a, void *context)
+{
+        int ret;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
+        if (ret != sizeof(struct factory_config)) {
+                pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
+                                ret);
+                return;
+        }
+
+        if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
+                pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
+                                factory_config.magic);
+                return;
+        }
+
+        if (factory_config.version != FACTORY_CONFIG_VERSION) {
+                pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
+                                factory_config.version);
+                return;
+        }
+
+        pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
+        pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
+        if (is_valid_ether_addr(factory_config.mac))
+                memcpy(soc_info->emac_pdata->mac_addr,
+                        factory_config.mac, ETH_ALEN);
+        else
+                pr_warning("MityOMAPL138: Invalid MAC found "
+                                "in factory config block\n");
+}
+
+static struct at24_platform_data mityomapl138_fd_chip = {
+        .byte_len       = 256,
+        .page_size      = 8,
+        .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
+        .setup          = read_factory_config,
+        .context        = NULL,
+};
+
+static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
+        .bus_freq       = 100,  /* kHz */
+        .bus_delay      = 0,    /* usec */
+};
+
+/* TPS65023 voltage regulator support */
+/* 1.2V Core */
+static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
+        {
+                .supply = "cvdd",
+        },
+};
+
+/* 1.8V */
+static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
+        {
+                .supply = "usb0_vdda18",
+        },
+        {
+                .supply = "usb1_vdda18",
+        },
+        {
+                .supply = "ddr_dvdd18",
+        },
+        {
+                .supply = "sata_vddr",
+        },
+};
+
+/* 1.2V */
+static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
+        {
+                .supply = "sata_vdd",
+        },
+        {
+                .supply = "usb_cvdd",
+        },
+        {
+                .supply = "pll0_vdda",
+        },
+        {
+                .supply = "pll1_vdda",
+        },
+};
+
+/* 1.8V Aux LDO, not used */
+static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
+        {
+                .supply = "1.8v_aux",
+        },
+};
+
+/* FPGA VCC Aux (2.5 or 3.3) LDO */
+static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
+        {
+                .supply = "vccaux",
+        },
+};
+
+static struct regulator_init_data tps65023_regulator_data[] = {
+        /* dcdc1 */
+        {
+                .constraints = {
+                        .min_uV = 1150000,
+                        .max_uV = 1350000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
+                .consumer_supplies = tps65023_dcdc1_consumers,
+        },
+        /* dcdc2 */
+        {
+                .constraints = {
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
+                .consumer_supplies = tps65023_dcdc2_consumers,
+        },
+        /* dcdc3 */
+        {
+                .constraints = {
+                        .min_uV = 1200000,
+                        .max_uV = 1200000,
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
+                .consumer_supplies = tps65023_dcdc3_consumers,
+        },
+        /* ldo1 */
+        {
+                .constraints = {
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
+                .consumer_supplies = tps65023_ldo1_consumers,
+        },
+        /* ldo2 */
+        {
+                .constraints = {
+                        .min_uV = 2500000,
+                        .max_uV = 3300000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
+                .consumer_supplies = tps65023_ldo2_consumers,
+        },
+};
+
+static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
+        {
+                I2C_BOARD_INFO("tps65023", 0x48),
+                .platform_data = &tps65023_regulator_data[0],
+        },
+        {
+                I2C_BOARD_INFO("24c02", 0x50),
+                .platform_data = &mityomapl138_fd_chip,
+        },
+};
+
+static int __init pmic_tps65023_init(void)
+{
+        return i2c_register_board_info(1, mityomap_tps65023_info,
+                                        ARRAY_SIZE(mityomap_tps65023_info));
+}
+
+/*
+ * MityDSP-L138 includes a 256 MByte large-page NAND flash
+ * (128K blocks).
+ */
+static struct mtd_partition mityomapl138_nandflash_partition[] = {
+        {
+                .name           = "rootfs",
+                .offset         = 0,
+                .size           = SZ_128M,
+                .mask_flags     = 0, /* MTD_WRITEABLE, */
+        },
+        {
+                .name           = "homefs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        },
+};
+
+static struct davinci_nand_pdata mityomapl138_nandflash_data = {
+        .parts          = mityomapl138_nandflash_partition,
+        .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
+        .ecc_mode       = NAND_ECC_HW,
+        .options        = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
+        .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
+};
+
+static struct resource mityomapl138_nandflash_resource[] = {
+        {
+                .start  = DA8XX_AEMIF_CS3_BASE,
+                .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = DA8XX_AEMIF_CTL_BASE,
+                .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device mityomapl138_nandflash_device = {
+        .name           = "davinci_nand",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &mityomapl138_nandflash_data,
+        },
+        .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
+        .resource       = mityomapl138_nandflash_resource,
+};
+
+static struct platform_device *mityomapl138_devices[] __initdata = {
+        &mityomapl138_nandflash_device,
+};
+
+static void __init mityomapl138_setup_nand(void)
+{
+        platform_add_devices(mityomapl138_devices,
+                                 ARRAY_SIZE(mityomapl138_devices));
+}
+
+static struct davinci_uart_config mityomapl138_uart_config __initdata = {
+        .enabled_uarts = 0x7,
+};
+
+static const short mityomap_mii_pins[] = {
+        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static const short mityomap_rmii_pins[] = {
+        DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
+        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
+        DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+static void __init mityomapl138_config_emac(void)
+{
+        void __iomem *cfg_chip3_base;
+        int ret;
+        u32 val;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
+
+        cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
+        val = __raw_readl(cfg_chip3_base);
+
+        if (soc_info->emac_pdata->rmii_en) {
+                val |= BIT(8);
+                ret = davinci_cfg_reg_list(mityomap_rmii_pins);
+                pr_info("RMII PHY configured\n");
+        } else {
+                val &= ~BIT(8);
+                ret = davinci_cfg_reg_list(mityomap_mii_pins);
+                pr_info("MII PHY configured\n");
+        }
+
+        if (ret) {
+                pr_warning("mii/rmii mux setup failed: %d\n", ret);
+                return;
+        }
+
+        /* configure the CFGCHIP3 register for RMII or MII */
+        __raw_writel(val, cfg_chip3_base);
+
+        soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
+
+        ret = da8xx_register_emac();
+        if (ret)
+                pr_warning("emac registration failed: %d\n", ret);
+}
+
+static struct davinci_pm_config da850_pm_pdata = {
+        .sleepcount = 128,
+};
+
+static struct platform_device da850_pm_device = {
+        .name   = "pm-davinci",
+        .dev = {
+                .platform_data  = &da850_pm_pdata,
+        },
+        .id     = -1,
+};
+
+static void __init mityomapl138_init(void)
+{
+        int ret;
+
+        /* for now, no special EDMA channels are reserved */
+        ret = da850_register_edma(NULL);
+        if (ret)
+                pr_warning("edma registration failed: %d\n", ret);
+
+        ret = da8xx_register_watchdog();
+        if (ret)
+                pr_warning("watchdog registration failed: %d\n", ret);
+
+        davinci_serial_init(&mityomapl138_uart_config);
+
+        ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
+        if (ret)
+                pr_warning("i2c0 registration failed: %d\n", ret);
+
+        ret = pmic_tps65023_init();
+        if (ret)
+                pr_warning("TPS65023 PMIC init failed: %d\n", ret);
+
+        mityomapl138_setup_nand();
+
+        mityomapl138_config_emac();
+
+        ret = da8xx_register_rtc();
+        if (ret)
+                pr_warning("rtc setup failed: %d\n", ret);
+
+        ret = da850_register_cpufreq("pll0_sysclk3");
+        if (ret)
+                pr_warning("cpufreq registration failed: %d\n", ret);
+
+        ret = da8xx_register_cpuidle();
+        if (ret)
+                pr_warning("cpuidle registration failed: %d\n", ret);
+
+        ret = da850_register_pm(&da850_pm_device);
+        if (ret)
+                pr_warning("da850_evm_init: suspend registration failed: %d\n",
+                                ret);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init mityomapl138_console_init(void)
+{
+        if (!machine_is_mityomapl138())
+                return 0;
+
+        return add_preferred_console("ttyS", 1, "115200");
+}
+console_initcall(mityomapl138_console_init);
+#endif
+
+static void __init mityomapl138_map_io(void)
+{
+        da850_init();
+}
+
+MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
+        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .map_io         = mityomapl138_map_io,
+        .init_irq       = cp_intc_init,
+        .timer          = &davinci_timer,
+        .init_machine   = mityomapl138_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 4c30e929bbf..6c389ff1020 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -39,9 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
-#define NEUROS_OSD2_PHY_MASK            0x2
-#define NEUROS_OSD2_MDIO_FREQUENCY      2200000 /* PHY bus frequency */
-
+#define NEUROS_OSD2_PHY_ID              "0:01"
 #define LXT971_PHY_ID                   0x001378e2
 #define LXT971_PHY_MASK                 0xfffffff0
 
@@ -252,8 +250,7 @@ static __init void davinci_ntosd2_init(void)
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_ntosd2_snd_data);
 
-        soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
 
         davinci_setup_usb(1000, 8);
         /*
@@ -275,8 +272,6 @@ static __init void davinci_ntosd2_init(void)
 
 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
         /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
-        .phys_io        = IO_PHYS,
-        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params    = (DAVINCI_DDR_BASE + 0x100),
         .map_io          = davinci_ntosd2_map_io,
         .init_irq       = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
new file mode 100644
index 00000000000..0b8dbdb79fe
--- /dev/null
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -0,0 +1,62 @@
+/*
+ * Hawkboard.org based on TI's OMAP-L138 Platform
+ *
+ * Initial code: Syed Mohammed Khasim
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of
+ * any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+
+static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
+        .enabled_uarts = 0x7,
+};
+
+static __init void omapl138_hawk_init(void)
+{
+        int ret;
+
+        davinci_serial_init(&omapl138_hawk_uart_config);
+
+        ret = da8xx_register_watchdog();
+        if (ret)
+                pr_warning("omapl138_hawk_init: "
+                        "watchdog registration failed: %d\n",
+                        ret);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init omapl138_hawk_console_init(void)
+{
+        if (!machine_is_omapl138_hawkboard())
+                return 0;
+
+        return add_preferred_console("ttyS", 2, "115200");
+}
+console_initcall(omapl138_hawk_console_init);
+#endif
+
+static void __init omapl138_hawk_map_io(void)
+{
+        da850_init();
+}
+
+MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
+        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .map_io         = omapl138_hawk_map_io,
+        .init_irq       = cp_intc_init,
+        .timer          = &davinci_timer,
+        .init_machine   = omapl138_hawk_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 23e664a1a80..61ac96d8f00 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -42,9 +42,7 @@
 #include <mach/mux.h>
 #include <mach/usb.h>
 
-#define SFFSDR_PHY_MASK         (0x2)
-#define SFFSDR_MDIO_FREQUENCY   (2200000) /* PHY bus frequency */
-
+#define SFFSDR_PHY_ID           "0:01"
 static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
         /* U-Boot Environment: Block 0
          * UBL:                Block 1
@@ -143,8 +141,7 @@ static __init void davinci_sffsdr_init(void)
                              ARRAY_SIZE(davinci_sffsdr_devices));
         sffsdr_init_i2c();
         davinci_serial_init(&uart_config);
-        soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK;
-        soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
+        soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
         davinci_setup_usb(0, 0); /* We support only peripheral mode. */
 
         /* mux VLYNQ pins */
@@ -154,8 +151,6 @@ static __init void davinci_sffsdr_init(void)
 
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
         /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
-        .phys_io      = IO_PHYS,
-        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (DAVINCI_DDR_BASE + 0x100),
         .map_io       = davinci_sffsdr_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index fe2a9d9c8bb..a6db8546022 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -23,6 +23,9 @@
 #include <linux/ratelimit.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -141,10 +144,63 @@ static struct davinci_uart_config serial_config __initconst = {
         .enabled_uarts  = BIT(1),
 };
 
+static const uint32_t keymap[] = {
+        KEY(0, 0, KEY_NUMERIC_1),
+        KEY(0, 1, KEY_NUMERIC_2),
+        KEY(0, 2, KEY_NUMERIC_3),
+        KEY(0, 3, KEY_FN_F1),
+        KEY(0, 4, KEY_MENU),
+
+        KEY(1, 0, KEY_NUMERIC_4),
+        KEY(1, 1, KEY_NUMERIC_5),
+        KEY(1, 2, KEY_NUMERIC_6),
+        KEY(1, 3, KEY_UP),
+        KEY(1, 4, KEY_FN_F2),
+
+        KEY(2, 0, KEY_NUMERIC_7),
+        KEY(2, 1, KEY_NUMERIC_8),
+        KEY(2, 2, KEY_NUMERIC_9),
+        KEY(2, 3, KEY_LEFT),
+        KEY(2, 4, KEY_ENTER),
+
+        KEY(3, 0, KEY_NUMERIC_STAR),
+        KEY(3, 1, KEY_NUMERIC_0),
+        KEY(3, 2, KEY_NUMERIC_POUND),
+        KEY(3, 3, KEY_DOWN),
+        KEY(3, 4, KEY_RIGHT),
+
+        KEY(4, 0, KEY_FN_F3),
+        KEY(4, 1, KEY_FN_F4),
+        KEY(4, 2, KEY_MUTE),
+        KEY(4, 3, KEY_HOME),
+        KEY(4, 4, KEY_BACK),
+
+        KEY(5, 0, KEY_VOLUMEDOWN),
+        KEY(5, 1, KEY_VOLUMEUP),
+        KEY(5, 2, KEY_F1),
+        KEY(5, 3, KEY_F2),
+        KEY(5, 4, KEY_F3),
+};
+
+static const struct matrix_keymap_data keymap_data = {
+        .keymap         = keymap,
+        .keymap_size    = ARRAY_SIZE(keymap),
+};
+
+static struct matrix_keypad_platform_data keypad_config = {
+        .keymap_data    = &keymap_data,
+        .num_row_gpios  = 6,
+        .num_col_gpios  = 5,
+        .debounce_ms    = 0, /* minimum */
+        .active_low     = 0, /* pull up realization */
+        .no_autorepeat  = 0,
+};
+
 static struct tnetv107x_device_info evm_device_info __initconst = {
         .serial_config          = &serial_config,
         .mmc_config[1]          = &mmc_config,  /* controller 1 */
         .nand_config[0]         = &nand_config, /* chip select 0 */
+        .keypad_config          = &keypad_config,
 };
 
 static __init void tnetv107x_evm_board_init(void)
@@ -164,8 +220,6 @@ console_initcall(tnetv107x_evm_console_init);
 #endif
 
 MACHINE_START(TNETV107X, "TNETV107X EVM")
-        .phys_io        = TNETV107X_IO_BASE,
-        .io_pg_offst    = (TNETV107X_IO_VIRT >> 18) & 0xfffc,
         .boot_params    = (TNETV107X_DDR_BASE + 0x100),
         .map_io         = tnetv107x_init,
         .init_irq       = cp_intc_init,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 054c303caea..01ba080433d 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -236,7 +236,7 @@ static int __init clk_disable_unused(void)
                 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
                         continue;
 
-                pr_info("Clocks: disable unused %s\n", ck->name);
+                pr_debug("Clocks: disable unused %s\n", ck->name);
 
                 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
                                 (ck->flags & PSC_SWRSTDISABLE) ?
@@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
         return rate;
 }
 
+int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned v;
+        struct pll_data *pll;
+        unsigned long input;
+        unsigned ratio = 0;
+
+        /* If this is the PLL base clock, wrong function to call */
+        if (clk->pll_data)
+                return -EINVAL;
+
+        /* There must be a parent... */
+        if (WARN_ON(!clk->parent))
+                return -EINVAL;
+
+        /* ... the parent must be a PLL... */
+        if (WARN_ON(!clk->parent->pll_data))
+                return -EINVAL;
+
+        /* ... and this clock must have a divider. */
+        if (WARN_ON(!clk->div_reg))
+                return -EINVAL;
+
+        pll = clk->parent->pll_data;
+
+        input = clk->parent->rate;
+
+        /* If pre-PLL, source clock is before the multiplier and divider(s) */
+        if (clk->flags & PRE_PLL)
+                input = pll->input_rate;
+
+        if (input > rate) {
+                /*
+                 * Can afford to provide an output little higher than requested
+                 * only if maximum rate supported by hardware on this sysclk
+                 * is known.
+                 */
+                if (clk->maxrate) {
+                        ratio = DIV_ROUND_CLOSEST(input, rate);
+                        if (input / ratio > clk->maxrate)
+                                ratio = 0;
+                }
+
+                if (ratio == 0)
+                        ratio = DIV_ROUND_UP(input, rate);
+
+                ratio--;
+        }
+
+        if (ratio > PLLDIV_RATIO_MASK)
+                return -EINVAL;
+
+        do {
+                v = __raw_readl(pll->base + PLLSTAT);
+        } while (v & PLLSTAT_GOSTAT);
+
+        v = __raw_readl(pll->base + clk->div_reg);
+        v &= ~PLLDIV_RATIO_MASK;
+        v |= ratio | PLLDIV_EN;
+        __raw_writel(v, pll->base + clk->div_reg);
+
+        v = __raw_readl(pll->base + PLLCMD);
+        v |= PLLCMD_GOSET;
+        __raw_writel(v, pll->base + PLLCMD);
+
+        do {
+                v = __raw_readl(pll->base + PLLSTAT);
+        } while (v & PLLSTAT_GOSTAT);
+
+        return 0;
+}
+EXPORT_SYMBOL(davinci_set_sysclk_rate);
+
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
         if (WARN_ON(!clk->parent))
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 01e36483ac3..11099980b58 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -70,6 +70,9 @@
 #include <linux/list.h>
 #include <asm/clkdev.h>
 
+#define PLLSTAT_GOSTAT  BIT(0)
+#define PLLCMD_GOSET    BIT(0)
+
 struct pll_data {
         u32 phys_base;
         void __iomem *base;
@@ -86,6 +89,7 @@ struct clk {
         struct module           *owner;
         const char              *name;
         unsigned long           rate;
+        unsigned long           maxrate;        /* H/W supported max rate */
         u8                      usecount;
         u8                      lpsc;
         u8                      gpsc;
@@ -118,6 +122,7 @@ struct clk {
 int davinci_clk_init(struct clk_lookup *clocks);
 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
                                 unsigned int mult, unsigned int postdiv);
+int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
 
 extern struct platform_device davinci_wdt_device;
 extern void davinci_watchdog_reset(struct platform_device *);
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index d3fa6de1e20..343de73161f 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -34,6 +34,8 @@
 struct davinci_cpufreq {
         struct device *dev;
         struct clk *armclk;
+        struct clk *asyncclk;
+        unsigned long asyncrate;
 };
 static struct davinci_cpufreq cpufreq;
 
@@ -104,15 +106,27 @@ static int davinci_target(struct cpufreq_policy *policy,
         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 
         /* if moving to higher frequency, up the voltage beforehand */
-        if (pdata->set_voltage && freqs.new > freqs.old)
-                pdata->set_voltage(idx);
+        if (pdata->set_voltage && freqs.new > freqs.old) {
+                ret = pdata->set_voltage(idx);
+                if (ret)
+                        goto out;
+        }
 
         ret = clk_set_rate(armclk, idx);
+        if (ret)
+                goto out;
+
+        if (cpufreq.asyncclk) {
+                ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate);
+                if (ret)
+                        goto out;
+        }
 
         /* if moving to lower freq, lower the voltage after lowering freq */
         if (pdata->set_voltage && freqs.new < freqs.old)
                 pdata->set_voltage(idx);
 
+out:
         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 
         return ret;
@@ -185,6 +199,7 @@ static struct cpufreq_driver davinci_driver = {
 static int __init davinci_cpufreq_probe(struct platform_device *pdev)
 {
         struct davinci_cpufreq_config *pdata = pdev->dev.platform_data;
+        struct clk *asyncclk;
 
         if (!pdata)
                 return -EINVAL;
@@ -199,6 +214,12 @@ static int __init davinci_cpufreq_probe(struct platform_device *pdev)
                 return PTR_ERR(cpufreq.armclk);
         }
 
+        asyncclk = clk_get(cpufreq.dev, "async");
+        if (!IS_ERR(asyncclk)) {
+                cpufreq.asyncclk = asyncclk;
+                cpufreq.asyncrate = clk_get_rate(asyncclk);
+        }
+
         return cpufreq_register_driver(&davinci_driver);
 }
 
@@ -206,6 +227,9 @@ static int __exit davinci_cpufreq_remove(struct platform_device *pdev)
 {
         clk_put(cpufreq.armclk);
 
+        if (cpufreq.asyncclk)
+                clk_put(cpufreq.asyncclk);
+
         return cpufreq_unregister_driver(&davinci_driver);
 }
 
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 68ed58a4825..63916b90276 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = {
         .parent         = &pll0_clk,
         .flags          = CLK_PLL,
         .div_reg        = PLLDIV3,
+        .set_rate       = davinci_set_sysclk_rate,
+        .maxrate        = 100000000,
 };
 
 static struct clk pll0_sysclk4 = {
@@ -323,12 +325,19 @@ static struct clk lcdc_clk = {
         .gpsc           = 1,
 };
 
-static struct clk mmcsd_clk = {
-        .name           = "mmcsd",
+static struct clk mmcsd0_clk = {
+        .name           = "mmcsd0",
         .parent         = &pll0_sysclk2,
         .lpsc           = DA8XX_LPSC0_MMC_SD,
 };
 
+static struct clk mmcsd1_clk = {
+        .name           = "mmcsd1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA850_LPSC1_MMC_SD1,
+        .gpsc           = 1,
+};
+
 static struct clk aemif_clk = {
         .name           = "aemif",
         .parent         = &pll0_sysclk3,
@@ -375,7 +384,8 @@ static struct clk_lookup da850_clks[] = {
         CLK("davinci_emac.1",   NULL,           &emac_clk),
         CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
         CLK("da8xx_lcdc.0",     NULL,           &lcdc_clk),
-        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+        CLK("davinci_mmc.0",    NULL,           &mmcsd0_clk),
+        CLK("davinci_mmc.1",    NULL,           &mmcsd1_clk),
         CLK(NULL,               "aemif",        &aemif_clk),
         CLK(NULL,               NULL,           NULL),
 };
@@ -572,15 +582,9 @@ const short da850_cpgmac_pins[] __initdata = {
         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
-        DA850_MDIO_D,
-        -1
-};
-
-const short da850_rmii_pins[] __initdata = {
-        DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
-        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
-        DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
-        DA850_MDIO_D,
+        DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
+        DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER,
+        DA850_RMII_MHZ_50_CLK,
         -1
 };
 
@@ -607,27 +611,19 @@ const short da850_mmcsd0_pins[] __initdata = {
         -1
 };
 
-const short da850_nand_pins[] __initdata = {
-        DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
-        DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
-        DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
-        DA850_NEMA_WE, DA850_NEMA_OE,
-        -1
-};
-
-const short da850_nor_pins[] __initdata = {
+const short da850_emif25_pins[] __initdata = {
         DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
-        DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
-        DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
-        DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
-        DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
-        DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
-        DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
-        DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
-        DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
-        DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
-        DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
-        DA850_EMA_A_22, DA850_EMA_A_23,
+        DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE,
+        DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
+        DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
+        DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
+        DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
+        DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3,
+        DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7,
+        DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11,
+        DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15,
+        DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19,
+        DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23,
         -1
 };
 
@@ -851,7 +847,7 @@ static const struct da850_opp da850_opp_300 = {
         .prediv         = 1,
         .mult           = 25,
         .postdiv        = 2,
-        .cvdd_min       = 1140000,
+        .cvdd_min       = 1200000,
         .cvdd_max       = 1320000,
 };
 
@@ -860,7 +856,7 @@ static const struct da850_opp da850_opp_200 = {
         .prediv         = 1,
         .mult           = 25,
         .postdiv        = 3,
-        .cvdd_min       = 1050000,
+        .cvdd_min       = 1100000,
         .cvdd_max       = 1160000,
 };
 
@@ -869,7 +865,7 @@ static const struct da850_opp da850_opp_96 = {
         .prediv         = 1,
         .mult           = 20,
         .postdiv        = 5,
-        .cvdd_min       = 950000,
+        .cvdd_min       = 1000000,
         .cvdd_max       = 1050000,
 };
 
@@ -929,10 +925,16 @@ static struct platform_device da850_cpufreq_device = {
         .dev = {
                 .platform_data  = &cpufreq_info,
         },
+        .id = -1,
 };
 
-int __init da850_register_cpufreq(void)
+int __init da850_register_cpufreq(char *async_clk)
 {
+        /* cpufreq driver can help keep an "async" clock constant */
+        if (async_clk)
+                clk_add_alias("async", da850_cpufreq_device.name,
+                                                        async_clk, NULL);
+
         return platform_device_register(&da850_cpufreq_device);
 }
 
@@ -983,7 +985,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         return 0;
 }
 #else
-int __init da850_register_cpufreq(void)
+int __init da850_register_cpufreq(char *async_clk)
 {
         return 0;
 }
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 52bc7b1c6ca..9eec63070e0 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,6 +24,7 @@
 #include "clock.h"
 
 #define DA8XX_TPCC_BASE                 0x01c00000
+#define DA850_MMCSD1_BASE               0x01e1b000
 #define DA850_TPCC1_BASE                0x01e30000
 #define DA8XX_TPTC0_BASE                0x01c08000
 #define DA8XX_TPTC1_BASE                0x01c08400
@@ -41,7 +42,6 @@
 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
 #define DA8XX_EMAC_RAM_OFFSET           0x0000
-#define DA8XX_MDIO_REG_OFFSET           0x4000
 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
 
 void __iomem *da8xx_syscfg0_base;
@@ -351,7 +351,7 @@ int __init da8xx_register_watchdog(void)
 static struct resource da8xx_emac_resources[] = {
         {
                 .start  = DA8XX_EMAC_CPPI_PORT_BASE,
-                .end    = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
+                .end    = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -380,7 +380,6 @@ struct emac_platform_data da8xx_emac_pdata = {
         .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
         .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
         .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
-        .mdio_reg_offset        = DA8XX_MDIO_REG_OFFSET,
         .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
         .version                = EMAC_VERSION_2,
 };
@@ -395,9 +394,34 @@ static struct platform_device da8xx_emac_device = {
         .resource       = da8xx_emac_resources,
 };
 
+static struct resource da8xx_mdio_resources[] = {
+        {
+                .start  = DA8XX_EMAC_MDIO_BASE,
+                .end    = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device da8xx_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(da8xx_mdio_resources),
+        .resource       = da8xx_mdio_resources,
+};
+
 int __init da8xx_register_emac(void)
 {
-        return platform_device_register(&da8xx_emac_device);
+        int ret;
+
+        ret = platform_device_register(&da8xx_mdio_device);
+        if (ret < 0)
+                return ret;
+        ret = platform_device_register(&da8xx_emac_device);
+        if (ret < 0)
+                return ret;
+        ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
+                            NULL, &da8xx_emac_device.dev);
+        return ret;
 }
 
 static struct resource da830_mcasp1_resources[] = {
@@ -566,6 +590,44 @@ int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
         return platform_device_register(&da8xx_mmcsd0_device);
 }
 
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+static struct resource da850_mmcsd1_resources[] = {
+        {               /* registers */
+                .start  = DA850_MMCSD1_BASE,
+                .end    = DA850_MMCSD1_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {               /* interrupt */
+                .start  = IRQ_DA850_MMCSDINT0_1,
+                .end    = IRQ_DA850_MMCSDINT0_1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {               /* DMA RX */
+                .start  = EDMA_CTLR_CHAN(1, 28),
+                .end    = EDMA_CTLR_CHAN(1, 28),
+                .flags  = IORESOURCE_DMA,
+        },
+        {               /* DMA TX */
+                .start  = EDMA_CTLR_CHAN(1, 29),
+                .end    = EDMA_CTLR_CHAN(1, 29),
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device da850_mmcsd1_device = {
+        .name           = "davinci_mmc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
+        .resource       = da850_mmcsd1_resources,
+};
+
+int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
+{
+        da850_mmcsd1_device.dev.platform_data = config;
+        return platform_device_register(&da850_mmcsd1_device);
+}
+#endif
+
 static struct resource da8xx_rtc_resources[] = {
         {
                 .start          = DA8XX_RTC_BASE,
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 2718a3a90df..c9a86d8130d 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -31,8 +31,10 @@
 #define TNETV107X_TPTC0_BASE                    0x01c10000
 #define TNETV107X_TPTC1_BASE                    0x01c10400
 #define TNETV107X_WDOG_BASE                     0x08086700
+#define TNETV107X_TSC_BASE                      0x08088500
 #define TNETV107X_SDIO0_BASE                    0x08088700
 #define TNETV107X_SDIO1_BASE                    0x08088800
+#define TNETV107X_KEYPAD_BASE                   0x08088a00
 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE         0x08200000
 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE      0x30000000
 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE      0x40000000
@@ -298,12 +300,55 @@ static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
         return platform_device_register(pdev);
 }
 
+static struct resource keypad_resources[] = {
+        {
+                .start  = TNETV107X_KEYPAD_BASE,
+                .end    = TNETV107X_KEYPAD_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_TNETV107X_KEYPAD,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "press",
+        },
+        {
+                .start  = IRQ_TNETV107X_KEYPAD_FREE,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "release",
+        },
+};
+
+static struct platform_device keypad_device = {
+        .name           = "tnetv107x-keypad",
+        .num_resources  = ARRAY_SIZE(keypad_resources),
+        .resource       = keypad_resources,
+};
+
+static struct resource tsc_resources[] = {
+        {
+                .start  = TNETV107X_TSC_BASE,
+                .end    = TNETV107X_TSC_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_TNETV107X_TSC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tsc_device = {
+        .name           = "tnetv107x-ts",
+        .num_resources  = ARRAY_SIZE(tsc_resources),
+        .resource       = tsc_resources,
+};
+
 void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
 {
         int i;
 
         platform_device_register(&edma_device);
         platform_device_register(&tnetv107x_wdt_device);
+        platform_device_register(&tsc_device);
 
         if (info->serial_config)
                 davinci_serial_init(info->serial_config);
@@ -317,4 +362,9 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
         for (i = 0; i < 4; i++)
                 if (info->nand_config[i])
                         nand_init(i, info->nand_config[i]);
+
+        if (info->keypad_config) {
+                keypad_device.dev.platform_data = info->keypad_config;
+                platform_device_register(&keypad_device);
+        }
 }
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 8b7201e4c79..22ebc64bc9d 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -213,7 +213,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                                 IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
 
                         /* Configure pull down control */
-                        __raw_writel((__raw_readl(pupdctl1) & ~0x400),
+                        __raw_writel((__raw_readl(pupdctl1) & ~0xfc0),
                                         pupdctl1);
 
                         mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
@@ -295,6 +295,18 @@ static void davinci_init_wdt(void)
 
 /*-------------------------------------------------------------------------*/
 
+struct platform_device davinci_pcm_device = {
+        .name           = "davinci-pcm-audio",
+        .id             = -1,
+};
+
+static void davinci_init_pcm(void)
+{
+        platform_device_register(&davinci_pcm_device);
+}
+
+/*-------------------------------------------------------------------------*/
+
 struct davinci_timer_instance davinci_timer_instance[2] = {
         {
                 .base           = DAVINCI_TIMER0_BASE,
@@ -315,6 +327,7 @@ static int __init davinci_init_devices(void)
         /* please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
+        davinci_init_pcm();
         davinci_init_wdt();
 
         return 0;
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 7781e35daec..a12065e8726 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -691,7 +691,6 @@ static struct emac_platform_data dm365_emac_pdata = {
         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
-        .mdio_reg_offset        = DM365_EMAC_MDIO_OFFSET,
         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
         .version                = EMAC_VERSION_2,
 };
@@ -699,7 +698,7 @@ static struct emac_platform_data dm365_emac_pdata = {
 static struct resource dm365_emac_resources[] = {
         {
                 .start  = DM365_EMAC_BASE,
-                .end    = DM365_EMAC_BASE + 0x47ff,
+                .end    = DM365_EMAC_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -734,6 +733,21 @@ static struct platform_device dm365_emac_device = {
         .resource       = dm365_emac_resources,
 };
 
+static struct resource dm365_mdio_resources[] = {
+        {
+                .start  = DM365_EMAC_MDIO_BASE,
+                .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm365_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
+        .resource       = dm365_mdio_resources,
+};
+
 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
         [IRQ_VDINT0]                    = 2,
         [IRQ_VDINT1]                    = 6,
@@ -1219,7 +1233,12 @@ static int __init dm365_init_devices(void)
 
         davinci_cfg_reg(DM365_INT_EDMA_CC);
         platform_device_register(&dm365_edma_device);
+
+        platform_device_register(&dm365_mdio_device);
         platform_device_register(&dm365_emac_device);
+        clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
+                      NULL, &dm365_emac_device.dev);
+
         /* Add isif clock alias */
         clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
         platform_device_register(&dm365_vpss_device);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 5e5b0a7831f..0608dd776a1 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -322,7 +322,6 @@ static struct emac_platform_data dm644x_emac_pdata = {
         .ctrl_reg_offset        = DM644X_EMAC_CNTRL_OFFSET,
         .ctrl_mod_reg_offset    = DM644X_EMAC_CNTRL_MOD_OFFSET,
         .ctrl_ram_offset        = DM644X_EMAC_CNTRL_RAM_OFFSET,
-        .mdio_reg_offset        = DM644X_EMAC_MDIO_OFFSET,
         .ctrl_ram_size          = DM644X_EMAC_CNTRL_RAM_SIZE,
         .version                = EMAC_VERSION_1,
 };
@@ -330,7 +329,7 @@ static struct emac_platform_data dm644x_emac_pdata = {
 static struct resource dm644x_emac_resources[] = {
         {
                 .start  = DM644X_EMAC_BASE,
-                .end    = DM644X_EMAC_BASE + 0x47ff,
+                .end    = DM644X_EMAC_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -350,6 +349,21 @@ static struct platform_device dm644x_emac_device = {
        .resource        = dm644x_emac_resources,
 };
 
+static struct resource dm644x_mdio_resources[] = {
+        {
+                .start  = DM644X_EMAC_MDIO_BASE,
+                .end    = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm644x_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm644x_mdio_resources),
+        .resource       = dm644x_mdio_resources,
+};
+
 /*
  * Device specific mux setup
  *
@@ -776,7 +790,12 @@ static int __init dm644x_init_devices(void)
         clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
         clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
         platform_device_register(&dm644x_edma_device);
+
+        platform_device_register(&dm644x_mdio_device);
         platform_device_register(&dm644x_emac_device);
+        clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
+                      NULL, &dm644x_emac_device.dev);
+
         platform_device_register(&dm644x_vpss_device);
         platform_device_register(&dm644x_ccdc_dev);
         platform_device_register(&vpfe_capture_dev);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 26e8a9c7f50..1e0f809644b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -358,7 +358,6 @@ static struct emac_platform_data dm646x_emac_pdata = {
         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
-        .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
         .version                = EMAC_VERSION_2,
 };
@@ -366,7 +365,7 @@ static struct emac_platform_data dm646x_emac_pdata = {
 static struct resource dm646x_emac_resources[] = {
         {
                 .start  = DM646X_EMAC_BASE,
-                .end    = DM646X_EMAC_BASE + 0x47ff,
+                .end    = DM646X_EMAC_BASE + SZ_16K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -401,6 +400,21 @@ static struct platform_device dm646x_emac_device = {
         .resource       = dm646x_emac_resources,
 };
 
+static struct resource dm646x_mdio_resources[] = {
+        {
+                .start  = DM646X_EMAC_MDIO_BASE,
+                .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm646x_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
+        .resource       = dm646x_mdio_resources,
+};
+
 /*
  * Device specific mux setup
  *
@@ -896,7 +910,11 @@ static int __init dm646x_init_devices(void)
         if (!cpu_is_davinci_dm646x())
                 return 0;
 
+        platform_device_register(&dm646x_mdio_device);
         platform_device_register(&dm646x_emac_device);
+        clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
+                      NULL, &dm646x_emac_device.dev);
+
         return 0;
 }
 postcore_initcall(dm646x_init_devices);
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 2ede598b77d..6b9669869c4 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -354,10 +354,12 @@ static int irq2ctlr(int irq)
 static irqreturn_t dma_irq_handler(int irq, void *data)
 {
         int i;
-        unsigned ctlr;
+        int ctlr;
         unsigned int cnt = 0;
 
         ctlr = irq2ctlr(irq);
+        if (ctlr < 0)
+                return IRQ_NONE;
 
         dev_dbg(data, "dma_irq_handler\n");
 
@@ -408,10 +410,12 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 static irqreturn_t dma_ccerr_handler(int irq, void *data)
 {
         int i;
-        unsigned ctlr;
+        int ctlr;
         unsigned int cnt = 0;
 
         ctlr = irq2ctlr(irq);
+        if (ctlr < 0)
+                return IRQ_NONE;
 
         dev_dbg(data, "dma_ccerr_handler\n");
 
diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h
new file mode 100644
index 00000000000..05b29344309
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/aemif.h
@@ -0,0 +1,36 @@
+/*
+ * TI DaVinci AEMIF support
+ *
+ * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef _MACH_DAVINCI_AEMIF_H
+#define _MACH_DAVINCI_AEMIF_H
+
+#define NRCSR_OFFSET            0x00
+#define AWCCR_OFFSET            0x04
+#define A1CR_OFFSET             0x10
+
+#define ACR_ASIZE_MASK          0x3
+#define ACR_EW_MASK             BIT(30)
+#define ACR_SS_MASK             BIT(31)
+
+/* All timings in nanoseconds */
+struct davinci_aemif_timing {
+        u8      wsetup;
+        u8      wstrobe;
+        u8      whold;
+
+        u8      rsetup;
+        u8      rstrobe;
+        u8      rhold;
+
+        u8      ta;
+};
+
+int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+                                        void __iomem *base, unsigned cs);
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 3c07059f526..4247b3f53b3 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -76,9 +76,10 @@ int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
 int da8xx_register_emac(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
+int da850_register_mmcsd1(struct davinci_mmc_config *config);
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
-int da850_register_cpufreq(void);
+int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
@@ -121,11 +122,9 @@ extern const short da850_uart2_pins[];
 extern const short da850_i2c0_pins[];
 extern const short da850_i2c1_pins[];
 extern const short da850_cpgmac_pins[];
-extern const short da850_rmii_pins[];
 extern const short da850_mcasp_pins[];
 extern const short da850_lcdcntl_pins[];
 extern const short da850_mmcsd0_pins[];
-extern const short da850_nand_pins[];
-extern const short da850_nor_pins[];
+extern const short da850_emif25_pins[];
 
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index f761dfdb868..9f1befc5ac3 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -29,35 +29,39 @@ davinci_uart_phys:	.word	0
 davinci_uart_virt:      .word   0
                 .popsection
 
-                .macro addruart, rx, tmp
+                .macro addruart, rp, rv
 
                 /* Use davinci_uart_phys/virt if already configured */
-10:             mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =__virt_to_phys(davinci_uart_phys)
-                ldrne   \rx, =davinci_uart_virt
-                ldr     \rx, [\rx]
-                cmp     \rx, #0                 @ is port configured?
+10:             mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =__virt_to_phys(davinci_uart_phys)
+                ldrne   \rp, =davinci_uart_phys
+                add     \rv, \rp, #4            @ davinci_uart_virt
+                ldr     \rp, [\rp, #0]
+                ldr     \rv, [\rv, #0]
+                cmp     \rp, #0                 @ is port configured?
+                cmpne   \rv, #0
                 bne     99f                     @ already configured
 
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
+                /* Check the debug UART address set in uncompress.h */
+                mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
 
                 /* Copy uart phys address from decompressor uart info */
-                ldreq   \tmp, =__virt_to_phys(davinci_uart_phys)
-                ldrne   \tmp, =davinci_uart_phys
-                ldreq   \rx, =DAVINCI_UART_INFO
-                ldrne   \rx, =__phys_to_virt(DAVINCI_UART_INFO)
-                ldr     \rx, [\rx, #0]
-                str     \rx, [\tmp]
+                ldreq   \rv, =__virt_to_phys(davinci_uart_phys)
+                ldrne   \rv, =davinci_uart_phys
+                ldreq   \rp, =DAVINCI_UART_INFO
+                ldrne   \rp, =__phys_to_virt(DAVINCI_UART_INFO)
+                ldr     \rp, [\rp, #0]
+                str     \rp, [\rv]
 
                 /* Copy uart virt address from decompressor uart info */
-                ldreq   \tmp, =__virt_to_phys(davinci_uart_virt)
-                ldrne   \tmp, =davinci_uart_virt
-                ldreq   \rx, =DAVINCI_UART_INFO
-                ldrne   \rx, =__phys_to_virt(DAVINCI_UART_INFO)
-                ldr     \rx, [\rx, #4]
-                str     \rx, [\tmp]
+                ldreq   \rv, =__virt_to_phys(davinci_uart_virt)
+                ldrne   \rv, =davinci_uart_virt
+                ldreq   \rp, =DAVINCI_UART_INFO
+                ldrne   \rp, =__phys_to_virt(DAVINCI_UART_INFO)
+                ldr     \rp, [\rp, #4]
+                str     \rp, [\rv]
 
                 b       10b
 99:
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index ea5df3b49ec..2563bf4e93a 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -21,10 +21,10 @@
 #include <media/davinci/vpfe_capture.h>
 
 #define DM365_EMAC_BASE                 (0x01D07000)
+#define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
 #define DM365_EMAC_CNTRL_OFFSET         (0x0000)
 #define DM365_EMAC_CNTRL_MOD_OFFSET     (0x3000)
 #define DM365_EMAC_CNTRL_RAM_OFFSET     (0x1000)
-#define DM365_EMAC_MDIO_OFFSET          (0x4000)
 #define DM365_EMAC_CNTRL_RAM_SIZE       (0x2000)
 
 /* Base of key scan register bank */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 6fca568a0fd..5a1b26d4e68 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -28,10 +28,10 @@
 #include <media/davinci/vpfe_capture.h>
 
 #define DM644X_EMAC_BASE                (0x01C80000)
+#define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
 #define DM644X_EMAC_CNTRL_OFFSET        (0x0000)
 #define DM644X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
 #define DM644X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM644X_EMAC_MDIO_OFFSET         (0x4000)
 #define DM644X_EMAC_CNTRL_RAM_SIZE      (0x2000)
 
 #define DM644X_ASYNC_EMIF_CONTROL_BASE  0x01E00000
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 0a27ee9a70e..7a27f3f1391 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -19,10 +19,10 @@
 #include <linux/davinci_emac.h>
 
 #define DM646X_EMAC_BASE                (0x01C80000)
+#define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
 #define DM646X_EMAC_CNTRL_OFFSET        (0x0000)
 #define DM646X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
 #define DM646X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM646X_EMAC_MDIO_OFFSET         (0x4000)
 #define DM646X_EMAC_CNTRL_RAM_SIZE      (0x2000)
 
 #define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
index b2ad8090bd1..025151049f0 100644
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -30,9 +30,6 @@
 
 #include <linux/mtd/nand.h>
 
-#define NRCSR_OFFSET            0x00
-#define AWCCR_OFFSET            0x04
-#define A1CR_OFFSET             0x10
 #define NANDFCR_OFFSET          0x60
 #define NANDFSR_OFFSET          0x64
 #define NANDF1ECC_OFFSET        0x70
@@ -83,6 +80,9 @@ struct davinci_nand_pdata {		/* platform_data */
         /* Main and mirror bbt descriptor overrides */
         struct nand_bbt_descr   *bbt_td;
         struct nand_bbt_descr   *bbt_md;
+
+        /* Access timings */
+        struct davinci_aemif_timing     *timing;
 };
 
 #endif  /* __ARCH_ARM_DAVINCI_NAND_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 983da6e4554..62b0858f68c 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -172,6 +172,7 @@
 #define DA8XX_LPSC1_UART2               13
 #define DA8XX_LPSC1_LCDC                16
 #define DA8XX_LPSC1_PWM                 17
+#define DA850_LPSC1_MMC_SD1             18
 #define DA8XX_LPSC1_ECAP                20
 #define DA830_LPSC1_EQEP                21
 #define DA850_LPSC1_TPTC2               21
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index c7206473312..5a681d880dc 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -33,6 +33,8 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/serial_8250.h>
+#include <linux/input/matrix_keypad.h>
+
 #include <mach/mmc.h>
 #include <mach/nand.h>
 #include <mach/serial.h>
@@ -41,6 +43,7 @@ struct tnetv107x_device_info {
         struct davinci_uart_config      *serial_config;
         struct davinci_mmc_config       *mmc_config[2];  /* 2 controllers */
         struct davinci_nand_pdata       *nand_config[4]; /* 4 chipsels */
+        struct matrix_keypad_platform_data *keypad_config;
 };
 
 extern struct platform_device tnetv107x_wdt_device;
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 15a6192ad6e..47723e8d75a 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -88,6 +88,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 /* DA8xx boards */
                 DEBUG_LL_DA8XX(davinci_da830_evm,       2);
                 DEBUG_LL_DA8XX(davinci_da850_evm,       2);
+                DEBUG_LL_DA8XX(mityomapl138,            1);
+                DEBUG_LL_DA8XX(omapl138_hawkboard,      2);
 
                 /* TNETV107x boards */
                 DEBUG_LL_TNETV107X(tnetv107x,           1);
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 864e60482c5..daeae06430b 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -104,7 +104,7 @@ static u32 pll_ext_freq[] = {
 };
 
 /* PSC control registers */
-static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE };
+static u32 psc_regs[] = { TNETV107X_PSC_BASE };
 
 /* Host map for interrupt controller */
 static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
@@ -581,7 +581,14 @@ static struct davinci_id ids[] = {
                 .part_no        = 0xb8a1,
                 .manufacturer   = 0x017,
                 .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
-                .name           = "tnetv107x rev1.0",
+                .name           = "tnetv107x rev 1.0",
+        },
+        {
+                .variant        = 0x1,
+                .part_no        = 0xb8a1,
+                .manufacturer   = 0x017,
+                .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
+                .name           = "tnetv107x rev 1.1/1.2",
         },
 };
 
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index bef70460fbc..95925aa76dd 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -94,8 +94,6 @@ static void __init dove_db_init(void)
 }
 
 MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
-        .phys_io        = DOVE_SB_REGS_PHYS_BASE,
-        .io_pg_offst    = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = dove_db_init,
         .map_io         = dove_map_io,
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
index 1521d13f1d1..da8bf2bad3b 100644
--- a/arch/arm/mach-dove/include/mach/debug-macro.S
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =DOVE_SB_REGS_PHYS_BASE
-        ldrne   \rx, =DOVE_SB_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
+        .macro  addruart, rp, rv
+        ldr     \rp, =DOVE_SB_REGS_PHYS_BASE
+        ldr     \rv, =DOVE_SB_REGS_VIRT_BASE
+        orr     \rp, \rp, #0x00012000
+        orr     \rv, \rv, #0x00012000
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index c7bc7fbb11a..5df4099fc14 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -280,8 +280,6 @@ arch_initcall(ebsa110_init);
 
 MACHINE_START(EBSA110, "EBSA110")
         /* Maintainer: Russell King */
-        .phys_io        = 0xe0000000,
-        .io_pg_offst    = ((0xe0000000) >> 18) & 0xfffc,
         .boot_params    = 0x00000400,
         .reserve_lp0    = 1,
         .reserve_lp2    = 1,
diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
index ebbd89f0e6c..7ef5690fd08 100644
--- a/arch/arm/mach-ebsa110/include/mach/debug-macro.S
+++ b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
@@ -11,9 +11,10 @@
  *
 **/
 
-                .macro  addruart, rx, tmp
-                mov     \rx, #0xf0000000
-                orr     \rx, \rx, #0x00000be0
+                .macro  addruart, rp, rv
+                mov     \rp, #0xf0000000
+                orr     \rp, \rp, #0x00000be0
+                mov     \rp, \rv
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
index 9b44c19e95e..60bde56fba4 100644
--- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h
+++ b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
+#define VMALLOC_END       0xdf000000
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index f744f676783..61b98ce4b67 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -33,8 +33,6 @@ static void __init adssphere_init_machine(void)
 
 MACHINE_START(ADSSPHERE, "ADS Sphere board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 4cb55d3902f..ffdf87be295 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -776,9 +776,15 @@ static struct platform_device ep93xx_i2s_device = {
         .resource       = ep93xx_i2s_resource,
 };
 
+static struct platform_device ep93xx_pcm_device = {
+        .name           = "ep93xx-pcm-audio",
+        .id             = -1,
+};
+
 void __init ep93xx_register_i2s(void)
 {
         platform_device_register(&ep93xx_i2s_device);
+        platform_device_register(&ep93xx_pcm_device);
 }
 
 #define EP93XX_SYSCON_DEVCFG_I2S_MASK   (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
@@ -826,6 +832,40 @@ void ep93xx_i2s_release(void)
 }
 EXPORT_SYMBOL(ep93xx_i2s_release);
 
+/*************************************************************************
+ * EP93xx AC97 audio peripheral handling
+ *************************************************************************/
+static struct resource ep93xx_ac97_resources[] = {
+        {
+                .start  = EP93XX_AAC_PHYS_BASE,
+                .end    = EP93XX_AAC_PHYS_BASE + 0xb0 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_EP93XX_AACINTR,
+                .end    = IRQ_EP93XX_AACINTR,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ep93xx_ac97_device = {
+        .name           = "ep93xx-ac97",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ep93xx_ac97_resources),
+        .resource       = ep93xx_ac97_resources,
+};
+
+void __init ep93xx_register_ac97(void)
+{
+        /*
+         * Make sure that the AC97 pins are not used by I2S.
+         */
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
+
+        platform_device_register(&ep93xx_ac97_device);
+        platform_device_register(&ep93xx_pcm_device);
+}
+
 extern void ep93xx_gpio_init(void);
 
 void __init ep93xx_init_devices(void)
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
index 8904ca4e2e2..a696d354b1f 100644
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -276,7 +276,7 @@ static void channel_disable(struct m2p_channel *ch)
         v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
         m2p_set_control(ch, v);
 
-        while (m2p_channel_state(ch) == STATE_ON)
+        while (m2p_channel_state(ch) >= STATE_ON)
                 cpu_relax();
 
         m2p_set_control(ch, 0x0);
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index c2ce9034ba8..4b043165213 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -124,8 +124,6 @@ static void __init edb93xx_init_machine(void)
 #ifdef CONFIG_MACH_EDB9301
 MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
         /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -137,8 +135,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9302
 MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
         /* Maintainer: George Kashperko <george@chas.com.ua> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -150,8 +146,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9302A
 MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -163,8 +157,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9307
 MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
         /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -176,8 +168,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9307A
 MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
         /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -189,8 +179,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9312
 MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
         /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -202,8 +190,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9315
 MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -215,8 +201,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_EDB9315A
 MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index d97168c0ba3..9bd3152bff9 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -33,8 +33,6 @@ static void __init gesbc9312_init_machine(void)
 
 MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
index 5cd22444e22..b25bc907636 100644
--- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
@@ -11,12 +11,11 @@
  */
 #include <mach/ep93xx-regs.h>
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                         @ MMU enabled?
-                ldreq   \rx, =EP93XX_APB_PHYS_BASE      @ Physical base
-                ldrne   \rx, =EP93XX_APB_VIRT_BASE      @ virtual base
-                orr     \rx, \rx, #0x000c0000
+                .macro  addruart, rp, rv
+                ldr     \rp, =EP93XX_APB_PHYS_BASE      @ Physical base
+                ldr     \rv, =EP93XX_APB_VIRT_BASE      @ virtual base
+                orr     \rp, \rp, #0x000c0000
+                orr     \rv, \rv, #0x000c0000
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index c54b3e56ba6..9ac4d105509 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -105,6 +105,7 @@
 #define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
 #define EP93XX_GPIO_EEDRIVE             EP93XX_GPIO_REG(0xc8)
 
+#define EP93XX_AAC_PHYS_BASE            EP93XX_APB_PHYS(0x00080000)
 #define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
 
 #define EP93XX_SPI_PHYS_BASE            EP93XX_APB_PHYS(0x000a0000)
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 3330b36d79e..50660455b1d 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -61,6 +61,7 @@ void ep93xx_keypad_release_gpio(struct platform_device *pdev);
 void ep93xx_register_i2s(void);
 int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config);
 void ep93xx_i2s_release(void);
+void ep93xx_register_ac97(void);
 
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 2ba776320a8..7adea6258ef 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -77,8 +77,6 @@ static void __init micro9_init_machine(void)
 #ifdef CONFIG_MACH_MICRO9H
 MACHINE_START(MICRO9, "Contec Micro9-High")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -90,8 +88,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_MICRO9M
 MACHINE_START(MICRO9M, "Contec Micro9-Mid")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -103,8 +99,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_MICRO9L
 MACHINE_START(MICRO9L, "Contec Micro9-Lite")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
@@ -116,8 +110,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_MICRO9S
 MACHINE_START(MICRO9S, "Contec Micro9-Slim")
         /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 5dded588413..d96dc1c5da2 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -61,12 +61,11 @@ static void __init simone_init_machine(void)
         ep93xx_register_fb(&simone_fb_info);
         ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
                             ARRAY_SIZE(simone_i2c_board_info));
+        ep93xx_register_ac97();
 }
 
 MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
 /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index a12c8930129..ac601fe2b44 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -163,8 +163,6 @@ static void __init snappercl15_init_machine(void)
 
 MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
         /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
         .map_io         = ep93xx_map_io,
         .init_irq       = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 93aeab8af70..c2d2cf40ead 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -257,8 +257,6 @@ static void __init ts72xx_init_machine(void)
 
 MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
         .map_io         = ts72xx_map_io,
         .init_irq       = ep93xx_init_irq,
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 1b996b26d2e..5b1a8db779b 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,8 +86,6 @@ fixup_cats(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(CATS, "Chalice-CATS")
         /* Maintainer: Philip Blundell */
-        .phys_io        = DC21285_ARMCSR_BASE,
-        .io_pg_offst    = ((0xfe000000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .soft_reboot    = 1,
         .fixup          = fixup_cats,
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 30040fd588c..2ef69ff44ba 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -15,8 +15,6 @@
 
 MACHINE_START(EBSA285, "EBSA285")
         /* Maintainer: Russell King */
-        .phys_io        = DC21285_ARMCSR_BASE,
-        .io_pg_offst    = ((0xfe000000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .video_start    = 0x000a0000,
         .video_end      = 0x000bffff,
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index 60dda1318f2..3c9e0c40c67 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -15,12 +15,10 @@
 
 #ifndef CONFIG_DEBUG_DC21285_PORT
         /* For NetWinder debugging */
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x7c000000        @ physical
-                movne   \rx, #0xff000000        @ virtual
-                orr     \rx, \rx, #0x000003f8
+                .macro  addruart, rp, rv
+                mov     \rp, #0x000003f8
+                orr     \rv, \rp, #0x7c000000   @ physical
+                orr     \rp, \rp, #0xff000000   @ virtual
                 .endm
 
 #define UART_SHIFT      0
@@ -32,14 +30,14 @@
                 .equ    dc21285_high, ARMCSR_BASE & 0xff000000
                 .equ    dc21285_low,  ARMCSR_BASE & 0x00ffffff
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x42000000
-                movne   \rx, #dc21285_high
+                .macro  addruart, rp, rv
                 .if     dc21285_low
-                orrne   \rx, \rx, #dc21285_low
+                mov     \rp, #dc21285_low
+                .else
+                mov     \rp, #0
                 .endif
+                orr     \rv, \rp, #0x42000000
+                orr     \rp, \rp, #dc21285_high
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
index d0958d860a3..0ffbb7c85e5 100644
--- a/arch/arm/mach-footbridge/include/mach/vmalloc.h
+++ b/arch/arm/mach-footbridge/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  */
 
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#define VMALLOC_END       0xf0000000
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index ac7ffa6fc41..06e514f372d 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -648,8 +648,6 @@ fixup_netwinder(struct machine_desc *desc, struct tag *tags,
 
 MACHINE_START(NETWINDER, "Rebel-NetWinder")
         /* Maintainer: Russell King/Rebel.com */
-        .phys_io        = DC21285_ARMCSR_BASE,
-        .io_pg_offst    = ((0xfe000000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .video_start    = 0x000a0000,
         .video_end      = 0x000bffff,
diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c
index e2c9f0690b1..3285e91ca8c 100644
--- a/arch/arm/mach-footbridge/personal.c
+++ b/arch/arm/mach-footbridge/personal.c
@@ -15,8 +15,6 @@
 
 MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer")
         /* Maintainer: Jamey Hicks / George France */
-        .phys_io        = DC21285_ARMCSR_BASE,
-        .io_pg_offst    = ((0xfe000000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = footbridge_map_io,
         .init_irq       = footbridge_init_irq,
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 01f1d6daab4..2ba096de003 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -101,8 +101,6 @@ static void __init ib4220b_init(void)
 }
 
 MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
-        .phys_io        = 0x7fffc000,
-        .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
         .boot_params    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
index e0de968e32a..a9a0d8b0194 100644
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -85,8 +85,6 @@ static void __init rut1xx_init(void)
 }
 
 MACHINE_START(RUT100, "Teltonika RUT100")
-        .phys_io        = 0x7fffc000,
-        .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
         .boot_params    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index 36538c15b3c..8b88d50d433 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -133,8 +133,6 @@ static void __init wbd111_init(void)
 }
 
 MACHINE_START(WBD111, "Wiliboard WBD-111")
-        .phys_io        = 0x7fffc000,
-        .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
         .boot_params    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index ece8b4c6511..1eebcecd1c3 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -133,8 +133,6 @@ static void __init wbd222_init(void)
 }
 
 MACHINE_START(WBD222, "Wiliboard WBD-222")
-        .phys_io        = 0x7fffc000,
-        .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
         .boot_params    = 0x100,
         .map_io         = gemini_map_io,
         .init_irq       = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S
index ad477047069..f40e006d296 100644
--- a/arch/arm/mach-gemini/include/mach/debug-macro.S
+++ b/arch/arm/mach-gemini/include/mach/debug-macro.S
@@ -11,11 +11,9 @@
  */
 #include <mach/hardware.h>
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =GEMINI_UART_BASE                  @ physical
-        ldrne   \rx, =IO_ADDRESS(GEMINI_UART_BASE)      @ virtual
+        .macro  addruart, rp, rv
+        ldr     \rp, =GEMINI_UART_BASE                  @ physical
+        ldr     \rv, =IO_ADDRESS(GEMINI_UART_BASE)      @ virtual
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 78be457dc32..79f0b896e44 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -30,8 +30,6 @@
 
 MACHINE_START(H7201, "Hynix GMS30C7201")
         /* Maintainer: Robert Schwebel, Pengutronix */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf0000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0001000,
         .map_io         = h720x_map_io,
         .init_irq       = h720x_init_irq,
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 8c0ba99d683..cc28b1efe04 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -72,8 +72,6 @@ static void __init init_eval_h7202(void)
 
 MACHINE_START(H7202, "Hynix HMS30C7202")
         /* Maintainer: Robert Schwebel, Pengutronix */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf0000000) >> 18) & 0xfffc,
         .boot_params    = 0x40000100,
         .map_io         = h720x_map_io,
         .init_irq       = h7202_init_irq,
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
index 27cafd12f03..c2093e83572 100644
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -16,12 +16,10 @@
                 .equ    io_virt, IO_VIRT
                 .equ    io_phys, IO_PHYS
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                @ MMU enabled?
-                moveq   \rx, #io_phys          @ physical base address
-                movne   \rx, #io_virt          @ virtual address
-                add     \rx, \rx, #0x00020000   @ UART1
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00020000        @ UART1
+                add     \rv, \rp, #io_virt      @ virtual address
+                add     \rp, \rp, #io_phys      @ physical base address
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
index ff1460d6841..a45915b8875 100644
--- a/arch/arm/mach-h720x/include/mach/vmalloc.h
+++ b/arch/arm/mach-h720x/include/mach/vmalloc.h
@@ -5,6 +5,6 @@
 #ifndef __ARCH_ARM_VMALLOC_H
 #define __ARCH_ARM_VMALLOC_H
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
 
 #endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c5c0369bb48..197f9e241cf 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -122,6 +122,7 @@ config MACH_CPUIMX27
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select MXC_ULPI if USB_ULPI
         help
           Include support for Eukrea CPUIMX27 platform. This includes
           specific configurations for the module and its peripherals.
@@ -146,8 +147,8 @@ choice
         default MACH_EUKREA_MBIMX27_BASEBOARD
 
 config MACH_EUKREA_MBIMX27_BASEBOARD
-        prompt "Eukrea MBIMX27 development board"
-        bool
+        bool "Eukrea MBIMX27 development board"
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SPI_IMX
         help
@@ -163,6 +164,15 @@ config MACH_MX27_3DS
           Include support for MX27PDK platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_IMX27_VISSTRIM_M10
+        bool "Vista Silicon i.MX27 Visstrim_m10"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for Visstrim_m10 platform and its different variants.
+          This includes specific configurations for the board and its
+          peripherals.
+
 config MACH_IMX27LITE
         bool "LogicPD MX27 LITEKIT platform"
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -173,6 +183,7 @@ config MACH_IMX27LITE
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 46a9fdfbbd1..5582692bb17 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
 obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
+obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
 obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index c05096c3830..daca30b2d5b 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
+        _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
         _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
         _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bb419ef4d13..cf15ea516a7 100644
--- a/arch/arm/mach-imx/clock-imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
         _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
         _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
-        _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
-        _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
-        _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
+        _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
+        _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
+        _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
         _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
         _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 5a1aa15c8a1..98a25bada78 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
 
 /* Clocks we cannot directly gate, but drivers need their rates */
-DEFINE_CLOCK(cspi1_clk,    0, 0,      0, NULL, &cspi1_clk1, &per2_clk);
-DEFINE_CLOCK(cspi2_clk,    1, 0,      0, NULL, &cspi2_clk1, &per2_clk);
-DEFINE_CLOCK(cspi3_clk,    2, 0,      0, NULL, &cspi13_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc1_clk,    0, 0,      0, NULL, &sdhc1_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc2_clk,    1, 0,      0, NULL, &sdhc2_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc3_clk,    2, 0,      0, NULL, &sdhc3_clk1, &per2_clk);
-DEFINE_CLOCK(pwm_clk,      0, 0,      0, NULL, &pwm_clk1, &per1_clk);
-DEFINE_CLOCK(gpt1_clk,     0, 0,      0, NULL, &gpt1_clk1, &per1_clk);
-DEFINE_CLOCK(gpt2_clk,     1, 0,      0, NULL, &gpt2_clk1, &per1_clk);
-DEFINE_CLOCK(gpt3_clk,     2, 0,      0, NULL, &gpt3_clk1, &per1_clk);
-DEFINE_CLOCK(gpt4_clk,     3, 0,      0, NULL, &gpt4_clk1, &per1_clk);
-DEFINE_CLOCK(gpt5_clk,     4, 0,      0, NULL, &gpt5_clk1, &per1_clk);
-DEFINE_CLOCK(gpt6_clk,     5, 0,      0, NULL, &gpt6_clk1, &per1_clk);
-DEFINE_CLOCK(uart1_clk,    0, 0,      0, NULL, &uart1_clk1, &per1_clk);
-DEFINE_CLOCK(uart2_clk,    1, 0,      0, NULL, &uart2_clk1, &per1_clk);
-DEFINE_CLOCK(uart3_clk,    2, 0,      0, NULL, &uart3_clk1, &per1_clk);
-DEFINE_CLOCK(uart4_clk,    3, 0,      0, NULL, &uart4_clk1, &per1_clk);
-DEFINE_CLOCK(uart5_clk,    4, 0,      0, NULL, &uart5_clk1, &per1_clk);
-DEFINE_CLOCK(uart6_clk,    5, 0,      0, NULL, &uart6_clk1, &per1_clk);
-DEFINE_CLOCK1(lcdc_clk,    0, 0,      0, parent, &lcdc_clk1, &per3_clk);
-DEFINE_CLOCK1(csi_clk,     0, 0,      0, parent, &csi_clk1, &per4_clk);
+DEFINE_CLOCK(cspi1_clk,    0, NULL,   0, NULL, &cspi1_clk1, &per2_clk);
+DEFINE_CLOCK(cspi2_clk,    1, NULL,   0, NULL, &cspi2_clk1, &per2_clk);
+DEFINE_CLOCK(cspi3_clk,    2, NULL,   0, NULL, &cspi13_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc1_clk,    0, NULL,   0, NULL, &sdhc1_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc2_clk,    1, NULL,   0, NULL, &sdhc2_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc3_clk,    2, NULL,   0, NULL, &sdhc3_clk1, &per2_clk);
+DEFINE_CLOCK(pwm_clk,      0, NULL,   0, NULL, &pwm_clk1, &per1_clk);
+DEFINE_CLOCK(gpt1_clk,     0, NULL,   0, NULL, &gpt1_clk1, &per1_clk);
+DEFINE_CLOCK(gpt2_clk,     1, NULL,   0, NULL, &gpt2_clk1, &per1_clk);
+DEFINE_CLOCK(gpt3_clk,     2, NULL,   0, NULL, &gpt3_clk1, &per1_clk);
+DEFINE_CLOCK(gpt4_clk,     3, NULL,   0, NULL, &gpt4_clk1, &per1_clk);
+DEFINE_CLOCK(gpt5_clk,     4, NULL,   0, NULL, &gpt5_clk1, &per1_clk);
+DEFINE_CLOCK(gpt6_clk,     5, NULL,   0, NULL, &gpt6_clk1, &per1_clk);
+DEFINE_CLOCK(uart1_clk,    0, NULL,   0, NULL, &uart1_clk1, &per1_clk);
+DEFINE_CLOCK(uart2_clk,    1, NULL,   0, NULL, &uart2_clk1, &per1_clk);
+DEFINE_CLOCK(uart3_clk,    2, NULL,   0, NULL, &uart3_clk1, &per1_clk);
+DEFINE_CLOCK(uart4_clk,    3, NULL,   0, NULL, &uart4_clk1, &per1_clk);
+DEFINE_CLOCK(uart5_clk,    4, NULL,   0, NULL, &uart5_clk1, &per1_clk);
+DEFINE_CLOCK(uart6_clk,    5, NULL,   0, NULL, &uart6_clk1, &per1_clk);
+DEFINE_CLOCK1(lcdc_clk,    0, NULL,   0, parent, &lcdc_clk1, &per3_clk);
+DEFINE_CLOCK1(csi_clk,     0, NULL,   0, parent, &csi_clk1, &per4_clk);
 
 #define _REGISTER_CLOCK(d, n, c) \
         { \
@@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
         _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
         _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
         _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index a8d94f07819..81979486218 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,10 +9,12 @@
 #include <mach/mx1.h>
 #include <mach/devices-common.h>
 
-#define imx1_add_i2c_imx(pdata)         \
-        imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
+extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
+#define imx1_add_imx_i2c(pdata)         \
+        imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
 
-#define imx1_add_imx_uart0(pdata)       \
-        imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
-#define imx1_add_imx_uart1(pdata)       \
-        imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
+extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
+#define imx1_add_imx_uart(id, pdata)    \
+        imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
+#define imx1_add_imx_uart0(pdata)       imx1_add_imx_uart(0, pdata)
+#define imx1_add_imx_uart1(pdata)       imx1_add_imx_uart(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 42788e99d12..d189039749b 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,22 +9,28 @@
 #include <mach/mx21.h>
 #include <mach/devices-common.h>
 
-#define imx21_add_i2c_imx(pdata)        \
-        imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
+extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
+#define imx21_add_imx_i2c(pdata)        \
+        imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
 
-#define imx21_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
-#define imx21_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
-#define imx21_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
-#define imx21_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
+extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
+#define imx21_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
 
+extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
+#define imx21_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
+#define imx21_add_imx_uart0(pdata)      imx21_add_imx_uart(0, pdata)
+#define imx21_add_imx_uart1(pdata)      imx21_add_imx_uart(1, pdata)
+#define imx21_add_imx_uart2(pdata)      imx21_add_imx_uart(2, pdata)
+#define imx21_add_imx_uart3(pdata)      imx21_add_imx_uart(3, pdata)
+
+extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
 #define imx21_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
 
-#define imx21_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
-#define imx21_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
+extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
+#define imx21_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx21_cspi_data[id], pdata)
+#define imx21_add_spi_imx0(pdata)       imx21_add_cspi(0, pdata)
+#define imx21_add_spi_imx1(pdata)       imx21_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 65e7bb7ec2e..7011690364f 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -9,30 +9,35 @@
 #include <mach/mx27.h>
 #include <mach/devices-common.h>
 
-#define imx27_add_i2c_imx0(pdata)       \
-        imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
-#define imx27_add_i2c_imx1(pdata)       \
-        imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
+extern const struct imx_fec_data imx27_fec_data __initconst;
+#define imx27_add_fec(pdata)    \
+        imx_add_fec(&imx27_fec_data, pdata)
 
-#define imx27_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
-#define imx27_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
-#define imx27_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
-#define imx27_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
-#define imx27_add_imx_uart4(pdata)      \
-        imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
-#define imx27_add_imx_uart5(pdata)      \
-        imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
+extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
+#define imx27_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
 
+extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
+#define imx27_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
+#define imx27_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
+#define imx27_add_imx_uart0(pdata)      imx27_add_imx_uart(0, pdata)
+#define imx27_add_imx_uart1(pdata)      imx27_add_imx_uart(1, pdata)
+#define imx27_add_imx_uart2(pdata)      imx27_add_imx_uart(2, pdata)
+#define imx27_add_imx_uart3(pdata)      imx27_add_imx_uart(3, pdata)
+#define imx27_add_imx_uart4(pdata)      imx27_add_imx_uart(4, pdata)
+#define imx27_add_imx_uart5(pdata)      imx27_add_imx_uart(5, pdata)
+
+extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
 #define imx27_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
 
-#define imx27_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
-#define imx27_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
-#define imx27_add_spi_imx2(pdata)       \
-        imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
+#define imx27_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx27_cspi_data[id], pdata)
+#define imx27_add_spi_imx0(pdata)       imx27_add_cspi(0, pdata)
+#define imx27_add_spi_imx1(pdata)       imx27_add_cspi(1, pdata)
+#define imx27_add_spi_imx2(pdata)       imx27_add_cspi(2, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 9c271a752b8..fba5047de8b 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -314,27 +314,6 @@ struct platform_device mxc_fb_device = {
         },
 };
 
-#ifdef CONFIG_MACH_MX27
-static struct resource mxc_fec_resources[] = {
-        {
-                .start = MX27_FEC_BASE_ADDR,
-                .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_FEC,
-                .end = MX27_INT_FEC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_fec_device = {
-        .name = "fec",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fec_resources),
-        .resource = mxc_fec_resources,
-};
-#endif
-
 static struct resource mxc_pwm_resources[] = {
         {
                 .start = MX2x_PWM_BASE_ADDR,
@@ -480,41 +459,6 @@ struct platform_device mxc_usbh2 = {
 };
 #endif
 
-#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix)                      \
-        {                                                               \
-                .name = _name,                                          \
-                .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,       \
-                .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,         \
-                .flags = IORESOURCE_DMA,                                \
-        }
-
-#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq)                   \
-        static struct resource imx_ssi_resources ## n[] = {             \
-                {                                                       \
-                        .start = MX2x_SSI ## ssin ## _BASE_ADDR,        \
-                        .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f,   \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = MX2x_INT_SSI1,                         \
-                        .end = MX2x_INT_SSI1,                           \
-                        .flags = IORESOURCE_IRQ,                        \
-                },                                                      \
-                DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0),                \
-                DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0),                \
-                DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1),                \
-                DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1),                \
-        };                                                              \
-                                                                        \
-        struct platform_device imx_ssi_device ## n = {                  \
-                .name = "imx-ssi",                                      \
-                .id = n,                                                \
-                .num_resources = ARRAY_SIZE(imx_ssi_resources ## n),    \
-                .resource = imx_ssi_resources ## n,                     \
-        }
-
-DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
-DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
-
 /* GPIO port description */
 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)                          \
         {                                                               \
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index efd4527506a..807f02a031c 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -16,7 +16,6 @@ extern struct platform_device mxc_gpt5;
 extern struct platform_device mxc_wdt;
 extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mxc_fb_device;
-extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
@@ -26,7 +25,5 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mx21_usbhc_device;
-extern struct platform_device imx_ssi_device0;
-extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_kpp_device;
 #endif
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 4edc5f43920..026263c665c 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -36,13 +36,12 @@
 #include <mach/hardware.h>
 #include <mach/mmc.h>
 #include <mach/spi.h>
-#include <mach/ssi.h>
 #include <mach/audmux.h>
 
 #include "devices-imx27.h"
 #include "devices.h"
 
-static int eukrea_mbimx27_pins[] = {
+static const int eukrea_mbimx27_pins[] __initconst = {
         /* UART2 */
         PE3_PF_UART2_CTS,
         PE4_PF_UART2_RTS,
@@ -311,7 +310,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
         .dat3_card_detect = 1,
 };
 
-struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
+static const
+struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
         .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
 };
 
@@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
         i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
 
-        mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
+        imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
 
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) \
         || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 339150ab0ea..745ee60fb06 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -46,7 +46,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static int eukrea_cpuimx27_pins[] = {
+static const int eukrea_cpuimx27_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -157,7 +157,6 @@ cpuimx27_nand_board_info __initconst = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_cpuimx27_nor_mtd_device,
-        &mxc_fec_device,
         &mxc_wdt,
         &mxc_w1_master_device,
 };
@@ -259,8 +258,9 @@ static void __init eukrea_cpuimx27_init(void)
         i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
 
-        imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
+        imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
@@ -307,8 +307,6 @@ static struct sys_timer eukrea_cpuimx27_timer = {
 };
 
 MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
-        .phys_io        = MX27_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX27_PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
         .init_irq       = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
new file mode 100644
index 00000000000..59716fab586
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -0,0 +1,261 @@
+/*
+ * mach-imx27_visstrim_m10.c
+ *
+ * Copyright 2010  Javier Martin <javier.martin@vista-silicon.com>
+ *
+ * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mmc.h>
+#include <mach/iomux.h>
+#include <mach/mxc_ehci.h>
+
+#include "devices-imx27.h"
+#include "devices.h"
+
+#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
+#define SDHC1_IRQ IRQ_GPIOB(25)
+
+static const int visstrim_m10_pins[] __initconst = {
+        /* UART1 (console) */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* SDHC1 */
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        /* Both I2Cs */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* USB OTG */
+        OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+        PC9_PF_USBOTG_DATA0,
+        PC11_PF_USBOTG_DATA1,
+        PC10_PF_USBOTG_DATA2,
+        PC13_PF_USBOTG_DATA3,
+        PC12_PF_USBOTG_DATA4,
+        PC7_PF_USBOTG_DATA5,
+        PC8_PF_USBOTG_DATA6,
+        PE25_PF_USBOTG_DATA7,
+        PE24_PF_USBOTG_CLK,
+        PE2_PF_USBOTG_DIR,
+        PE0_PF_USBOTG_NXT,
+        PE1_PF_USBOTG_STP,
+        PB23_PF_USB_PWR,
+        PB24_PF_USB_OC,
+};
+
+/* GPIOs used as events for applications */
+static struct gpio_keys_button visstrim_gpio_keys[] = {
+        {
+                .type   = EV_KEY,
+                .code   = KEY_RESTART,
+                .gpio   = (GPIO_PORTC + 15),
+                .desc   = "Default config",
+                .active_low = 0,
+                .wakeup = 1,
+        },
+        {
+                .type   = EV_KEY,
+                .code   = KEY_RECORD,
+                .gpio   = (GPIO_PORTF + 14),
+                .desc   = "Record",
+                .active_low = 0,
+                .wakeup = 1,
+        },
+        {
+                .type   = EV_KEY,
+                .code   = KEY_STOP,
+                .gpio   = (GPIO_PORTF + 13),
+                .desc   = "Stop",
+                .active_low = 0,
+                .wakeup = 1,
+        }
+};
+
+static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
+        .buttons        = visstrim_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(visstrim_gpio_keys),
+};
+
+static struct platform_device visstrim_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &visstrim_gpio_keys_platform_data,
+        },
+};
+
+/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
+static int visstrim_m10_sdhc1_init(struct device *dev,
+                irq_handler_t detect_irq, void *data)
+{
+        int ret;
+
+        ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
+                                "mmc-detect", data);
+        return ret;
+}
+
+static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(SDHC1_IRQ, data);
+}
+
+static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
+        .init = visstrim_m10_sdhc1_init,
+        .exit = visstrim_m10_sdhc1_exit,
+};
+
+/* Visstrim_SM10 NOR flash */
+static struct physmap_flash_data visstrim_m10_flash_data = {
+        .width = 2,
+};
+
+static struct resource visstrim_m10_flash_resource = {
+        .start = 0xc0000000,
+        .end = 0xc0000000 + SZ_64M - 1,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device visstrim_m10_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &visstrim_m10_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &visstrim_m10_flash_resource,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &visstrim_gpio_keys_device,
+        &visstrim_m10_nor_mtd_device,
+};
+
+/* Visstrim_M10 uses UART0 as console */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/* I2C */
+static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
+static struct pca953x_platform_data visstrim_m10_pca9555_pdata = {
+        .gpio_base = 240, /* After MX27 internal GPIOs */
+        .invert = 0,
+};
+
+static struct i2c_board_info visstrim_m10_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pca9555", 0x20),
+                .platform_data = &visstrim_m10_pca9555_pdata,
+        },
+};
+
+/* USB OTG */
+static int otg_phy_init(struct platform_device *pdev)
+{
+        gpio_set_value(OTG_PHY_CS_GPIO, 0);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
+        .init = otg_phy_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+static void __init visstrim_m10_board_init(void)
+{
+        int ret;
+
+        ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
+                        ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
+        if (ret)
+                pr_err("Failed to setup pins (%d)\n", ret);
+
+        imx27_add_imx_uart0(&uart_pdata);
+
+        i2c_register_board_info(0, visstrim_m10_i2c_devices,
+                                ARRAY_SIZE(visstrim_m10_i2c_devices));
+        imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
+        imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
+        mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
+        mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
+        imx27_add_fec(NULL);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init visstrim_m10_timer_init(void)
+{
+        mx27_clocks_init((unsigned long)25000000);
+}
+
+static struct sys_timer visstrim_m10_timer = {
+        .init   = visstrim_m10_timer_init,
+};
+
+MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
+        .boot_params    = MX27_PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mx27_init_irq,
+        .init_machine   = visstrim_m10_board_init,
+        .timer          = &visstrim_m10_timer,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 22a2b5d9121..bbdbc75127d 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -27,7 +27,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static unsigned int mx27lite_pins[] = {
+static const int mx27lite_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -58,16 +58,12 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct platform_device *platform_devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 static void __init mx27lite_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
                 "imx27lite");
         imx27_add_imx_uart0(&uart_pdata);
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_fec(NULL);
 }
 
 static void __init mx27lite_timer_init(void)
@@ -80,8 +76,6 @@ static struct sys_timer mx27lite_timer = {
 };
 
 MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
-        .phys_io        = MX27_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX27_PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
         .init_irq       = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 77a760cfadc..6187ce9ba7d 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -32,7 +32,7 @@
 #include "devices-imx1.h"
 #include "devices.h"
 
-static int mx1ads_pins[] = {
+static const int mx1ads_pins[] __initconst = {
         /* UART1 */
         PC9_PF_UART1_CTS,
         PC10_PF_UART1_RTS,
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
         i2c_register_board_info(0, mx1ads_i2c_devices,
                                 ARRAY_SIZE(mx1ads_i2c_devices));
 
-        imx1_add_i2c_imx(&mx1ads_i2c_data);
+        imx1_add_imx_i2c(&mx1ads_i2c_data);
 }
 
 static void __init mx1ads_timer_init(void)
@@ -145,8 +145,6 @@ struct sys_timer mx1ads_timer = {
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
         /* Maintainer: Sascha Hauer, Pengutronix */
-        .phys_io        = MX1_IO_BASE_ADDR,
-        .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX1_PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
         .init_irq       = mx1_init_irq,
@@ -155,8 +153,6 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-        .phys_io        = MX1_IO_BASE_ADDR,
-        .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX1_PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
         .init_irq       = mx1_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 96d7f8189f3..e1282e9f50f 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -67,7 +67,7 @@
 #define MX21ADS_IO_LED4_ON      0x4000
 #define MX21ADS_IO_LED3_ON      0x8000
 
-static unsigned int mx21ads_pins[] = {
+static const int mx21ads_pins[] __initconst = {
 
         /* CS8900A */
         (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
@@ -314,8 +314,6 @@ static struct sys_timer mx21ads_timer = {
 
 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .phys_io        = MX21_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX21_PHYS_OFFSET + 0x100,
         .map_io         = mx21ads_map_io,
         .init_irq       = mx21_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index e66ffaa1c26..b8bbd31aa85 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -33,7 +33,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static unsigned int mx27pdk_pins[] = {
+static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -64,10 +64,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct platform_device *platform_devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 /*
  * Matrix keyboard
  */
@@ -94,7 +90,7 @@ static void __init mx27pdk_init(void)
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
                 "mx27pdk");
         imx27_add_imx_uart0(&uart_pdata);
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_fec(NULL);
         mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
 }
 
@@ -109,8 +105,6 @@ static struct sys_timer mx27pdk_timer = {
 
 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .phys_io        = MX27_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX27_PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
         .init_irq       = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 9c77da98a10..a1e4bc573af 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -66,7 +66,7 @@
 /* to determine the correct external crystal reference */
 #define CKIH_27MHZ_BIT_SET      (1 << 3)
 
-static unsigned int mx27ads_pins[] = {
+static const int mx27ads_pins[] __initconst = {
         /* UART0 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -284,7 +284,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &mx27ads_nor_mtd_device,
-        &mxc_fec_device,
         &mxc_w1_master_device,
 };
 
@@ -308,11 +307,12 @@ static void __init mx27ads_board_init(void)
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, mx27ads_i2c_devices,
                                 ARRAY_SIZE(mx27ads_i2c_devices));
-        imx27_add_i2c_imx1(&mx27ads_i2c1_data);
+        imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
         mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
@@ -347,8 +347,6 @@ static void __init mx27ads_map_io(void)
 
 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         /* maintainer: Freescale Semiconductor, Inc. */
-        .phys_io        = MX27_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX27_PHYS_OFFSET + 0x100,
         .map_io         = mx27ads_map_io,
         .init_irq       = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index a3a1e452d4c..38d3a4ae17c 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -37,7 +37,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static unsigned int mxt_td60_pins[] __initdata = {
+static const int mxt_td60_pins[] __initconst = {
         /* UART0 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -231,10 +231,6 @@ static struct imxmmc_platform_data sdhc1_pdata = {
         .exit = mxt_td60_sdhc1_exit,
 };
 
-static struct platform_device *platform_devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -255,12 +251,11 @@ static void __init mxt_td60_board_init(void)
         i2c_register_board_info(1, mxt_td60_i2c2_devices,
                                 ARRAY_SIZE(mxt_td60_i2c2_devices));
 
-        imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
-        imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
+        imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
+        imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
-
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_fec(NULL);
 }
 
 static void __init mxt_td60_timer_init(void)
@@ -274,8 +269,6 @@ static struct sys_timer mxt_td60_timer = {
 
 MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
         /* maintainer: Maxtrack Industrial */
-        .phys_io        = MX27_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX27_PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
         .init_irq       = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 23c9e1f37b9..8c720d44602 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -38,7 +38,6 @@
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
 #include <mach/audmux.h>
-#include <mach/ssi.h>
 #include <mach/mxc_nand.h>
 #include <mach/irqs.h>
 #include <mach/mmc.h>
@@ -55,7 +54,7 @@
 #define SPI1_SS1 (GPIO_PORTD + 27)
 #define SD2_CD (GPIO_PORTC + 29)
 
-static int pca100_pins[] = {
+static const int pca100_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -174,7 +173,6 @@ pca100_nand_board_info __initconst = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &mxc_w1_master_device,
-        &mxc_fec_device,
         &mxc_wdt,
 };
 
@@ -193,11 +191,9 @@ static struct i2c_board_info pca100_i2c_devices[] = {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563"
+                I2C_BOARD_INFO("pcf8563", 0x51),
         }, {
                 I2C_BOARD_INFO("lm75", 0x4a),
-                .type = "lm75"
         }
 };
 
@@ -252,7 +248,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
         msleep(2);
 }
 
-static struct imx_ssi_platform_data pca100_ssi_pdata = {
+static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
         .ac97_reset             = pca100_ac97_cold_reset,
         .ac97_warm_reset        = pca100_ac97_warm_reset,
         .flags                  = IMX_SSI_USE_AC97,
@@ -389,7 +385,7 @@ static void __init pca100_init(void)
         if (ret)
                 printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
 
-        mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
+        imx27_add_imx_ssi(0, &pca100_ssi_pdata);
 
         imx27_add_imx_uart0(&uart_pdata);
 
@@ -401,7 +397,7 @@ static void __init pca100_init(void)
         i2c_register_board_info(1, pca100_i2c_devices,
                                 ARRAY_SIZE(pca100_i2c_devices));
 
-        imx27_add_i2c_imx1(&pca100_i2c1_data);
+        imx27_add_imx_i2c(1, &pca100_i2c1_data);
 
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
         mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
@@ -436,6 +432,7 @@ static void __init pca100_init(void)
 
         mxc_register_device(&mxc_fb_device, &pca100_fb_data);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
@@ -449,8 +446,6 @@ static struct sys_timer pca100_timer = {
 };
 
 MACHINE_START(PCA100, "phyCARD-i.MX27")
-        .phys_io        = MX27_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX27_PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
         .init_irq       = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 9212e8f3700..49a97ce0742 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -43,7 +43,7 @@
 #include "devices-imx27.h"
 #include "devices.h"
 
-static int pcm038_pins[] = {
+static const int pcm038_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
         PE13_PF_UART1_RXD,
@@ -173,7 +173,6 @@ pcm038_nand_board_info __initconst = {
 static struct platform_device *platform_devices[] __initdata = {
         &pcm038_nor_mtd_device,
         &mxc_w1_master_device,
-        &mxc_fec_device,
         &pcm038_sram_mtd_device,
         &mxc_wdt,
 };
@@ -257,7 +256,7 @@ static struct regulator_init_data cam_data = {
         .consumer_supplies = cam_consumers,
 };
 
-struct mc13783_regulator_init_data pcm038_regulators[] = {
+static struct mc13783_regulator_init_data pcm038_regulators[] = {
         {
                 .id = MC13783_REGU_VCAM,
                 .init_data = &cam_data,
@@ -309,7 +308,7 @@ static void __init pcm038_init(void)
         i2c_register_board_info(1, pcm038_i2c_devices,
                                 ARRAY_SIZE(pcm038_i2c_devices));
 
-        imx27_add_i2c_imx1(&pcm038_i2c1_data);
+        imx27_add_imx_i2c(1, &pcm038_i2c1_data);
 
         /* PE18 for user-LED D40 */
         mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@@ -325,6 +324,7 @@ static void __init pcm038_init(void)
 
         mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 
+        imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -342,8 +342,6 @@ static struct sys_timer pcm038_timer = {
 };
 
 MACHINE_START(PCM038, "phyCORE-i.MX27")
-        .phys_io        = MX27_AIPI_BASE_ADDR,
-        .io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX27_PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
         .init_irq       = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 88bf0d1e26e..1fbdd3faa7a 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = {
         }
 };
 
-static int mxc_uart1_pins[] = {
+static const int mxc_uart1_pins[] = {
         PC9_PF_UART1_CTS,
         PC10_PF_UART1_RTS,
         PC11_PF_UART1_TXD,
@@ -147,8 +147,6 @@ static struct sys_timer scb9328_timer = {
 
 MACHINE_START(SCB9328, "Synertronixx scb9328")
     /* Sascha Hauer */
-        .phys_io        = 0x00200000,
-        .io_pg_offst    = ((0xe0200000) >> 18) & 0xfffc,
         .boot_params    = 0x08000100,
         .map_io         = mx1_map_io,
         .init_irq       = mx1_init_irq,
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index f490a406d57..9110d9cca7a 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -31,7 +31,7 @@
 
 #include "devices.h"
 
-static int pcm970_pins[] = {
+static const int pcm970_pins[] __initconst = {
         /* SDHC */
         PB4_PF_SD2_D0,
         PB5_PF_SD2_D1,
@@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = {
         },
 };
 
-struct sja1000_platform_data pcm970_sja1000_platform_data = {
+static struct sja1000_platform_data pcm970_sja1000_platform_data = {
         .osc_freq       = 16000000,
         .ocr            = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
         .cdr            = CDR_CBP,
diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S
index 87a6888ae01..a1f598fd3a5 100644
--- a/arch/arm/mach-integrator/include/mach/debug-macro.S
+++ b/arch/arm/mach-integrator/include/mach/debug-macro.S
@@ -11,12 +11,10 @@
  *
 */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x16000000        @ physical base address
-                movne   \rx, #0xf0000000        @ virtual base
-                addne   \rx, \rx, #0x16000000 >> 4
+                .macro  addruart, rp, rv
+                mov     \rp, #0x16000000        @ physical base address
+                mov     \rv, #0xf0000000        @ virtual base
+                add     \rv, \rv, #0x16000000 >> 4
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
index e87ab0b37bd..e056e7cf564 100644
--- a/arch/arm/mach-integrator/include/mach/vmalloc.h
+++ b/arch/arm/mach-integrator/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 6ab5a03ab9d..548208f1117 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -500,8 +500,6 @@ static struct sys_timer ap_timer = {
 
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = 0x16000000,
-        .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = ap_map_io,
         .reserve        = integrator_reserve,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 05db40e3c4f..6258c90d020 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -599,8 +599,6 @@ static struct sys_timer cp_timer = {
 
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = 0x16000000,
-        .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = intcp_map_io,
         .reserve        = integrator_reserve,
diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
index c9d6ba46963..e664466d51b 100644
--- a/arch/arm/mach-iop13xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
@@ -11,15 +11,13 @@
  * published by the Free Software Foundation.
  */
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                 @ mmu enabled?
-        moveq   \rx, #0xff000000        @ physical
-        orreq   \rx, \rx, #0x00d80000
-        movne   \rx, #0xfe000000        @ virtual
-        orrne   \rx, \rx, #0x00e80000
-        orr     \rx, \rx, #0x00002300
-        orr     \rx, \rx, #0x00000040
+        .macro  addruart, rp, rv
+        mov     \rp, #0x00002300
+        orr     \rp, \rp, #0x00000040
+        orr     \rv, \rp, #0xfe000000   @ virtual
+        orr     \rv, \rv, #0x00e80000
+        orr     \rp, \rp, #0xff000000   @ physical
+        orr     \rp, \rp, #0x00d80000
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index f91f3154577..9b5a63f5d07 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -91,8 +91,6 @@ static struct sys_timer iq81340mc_timer = {
 
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
         /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
-        .phys_io        = IOP13XX_PMMR_PHYS_MEM_BASE,
-        .io_pg_offst    = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = iop13xx_map_io,
         .init_irq       = iop13xx_init_irq,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index ddb7a3435de..df3492a9c28 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -93,8 +93,6 @@ static struct sys_timer iq81340sc_timer = {
 
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
         /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
-        .phys_io        = IOP13XX_PMMR_PHYS_MEM_BASE,
-        .io_pg_offst    = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = iop13xx_map_io,
         .init_irq       = iop13xx_init_irq,
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index f34b0ed8063..7149fcc16c8 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -164,10 +164,10 @@ static void iop13xx_msi_nop(unsigned int irq)
 static struct irq_chip iop13xx_msi_chip = {
         .name = "PCI-MSI",
         .ack = iop13xx_msi_nop,
-        .enable = unmask_msi_irq,
-        .disable = mask_msi_irq,
-        .mask = mask_msi_irq,
-        .unmask = unmask_msi_irq,
+        .irq_enable = unmask_msi_irq,
+        .irq_disable = mask_msi_irq,
+        .irq_mask = mask_msi_irq,
+        .irq_unmask = unmask_msi_irq,
 };
 
 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 2bef9b6e1cc..779f924af30 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -203,8 +203,6 @@ static void __init em7210_init_machine(void)
 }
 
 MACHINE_START(EM7210, "Lanner EM7210")
-        .phys_io        = IQ31244_UART,
-        .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = em7210_map_io,
         .init_irq       = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 10384fc37cb..c6b6f9c5650 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -207,8 +207,6 @@ static void __init glantank_init_machine(void)
 
 MACHINE_START(GLANTANK, "GLAN Tank")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = GLANTANK_UART,
-        .io_pg_offst    = ((GLANTANK_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = glantank_map_io,
         .init_irq       = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S
index 736afe1edd1..ff9e76c09f3 100644
--- a/arch/arm/mach-iop32x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S
@@ -11,9 +11,10 @@
  * published by the Free Software Foundation.
  */
 
-                .macro  addruart, rx, tmp
-                mov     \rx, #0xfe000000        @ physical as well as virtual
-                orr     \rx, \rx, #0x00800000   @ location of the UART
+                .macro  addruart, rp, rv
+                mov     \rp, #0xfe000000        @ physical as well as virtual
+                orr     \rp, \rp, #0x00800000   @ location of the UART
+                mov     \rv, \rp
                 .endm
 
 #define UART_SHIFT      0
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index d6ac85ff109..fde962c057f 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -313,8 +313,6 @@ __setup("force_ep80219", force_ep80219_setup);
 
 MACHINE_START(IQ31244, "Intel IQ31244")
         /* Maintainer: Intel Corp. */
-        .phys_io        = IQ31244_UART,
-        .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = iq31244_map_io,
         .init_irq       = iop32x_init_irq,
@@ -329,8 +327,6 @@ MACHINE_END
  */
 MACHINE_START(EP80219, "Intel EP80219")
         /* Maintainer: Intel Corp. */
-        .phys_io        = IQ31244_UART,
-        .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = iq31244_map_io,
         .init_irq       = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index c6a0e4ee9d9..3a95950e873 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -186,8 +186,6 @@ static void __init iq80321_init_machine(void)
 
 MACHINE_START(IQ80321, "Intel IQ80321")
         /* Maintainer: Intel Corp. */
-        .phys_io        = IQ80321_UART,
-        .io_pg_offst    = ((IQ80321_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = iq80321_map_io,
         .init_irq       = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index f108a31afc2..626aa375915 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -327,8 +327,6 @@ static void __init n2100_init_machine(void)
 
 MACHINE_START(N2100, "Thecus N2100")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = N2100_UART,
-        .io_pg_offst    = ((N2100_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = n2100_map_io,
         .init_irq       = iop32x_init_irq,
diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S
index addb2da7842..40c500dd1fa 100644
--- a/arch/arm/mach-iop33x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S
@@ -11,13 +11,11 @@
  * published by the Free Software Foundation.
  */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ mmu enabled?
-                moveq   \rx, #0xff000000        @ physical
-                movne   \rx, #0xfe000000        @ virtual
-                orr     \rx, \rx, #0x00ff0000
-                orr     \rx, \rx, #0x0000f700
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00ff0000
+                orr     \rp, \rp, #0x0000f700
+                orr     \rv, #0xfe000000        @ virtual
+                orr     \rp, #0xff000000        @ physical
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index c6ff5523b38..c565f8d1e3a 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -141,8 +141,6 @@ static void __init iq80331_init_machine(void)
 
 MACHINE_START(IQ80331, "Intel IQ80331")
         /* Maintainer: Intel Corp. */
-        .phys_io        = 0xfefff000,
-        .io_pg_offst    = ((0xfffff000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = iop3xx_map_io,
         .init_irq       = iop33x_init_irq,
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index fbf55140939..36a9efb254c 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -141,8 +141,6 @@ static void __init iq80332_init_machine(void)
 
 MACHINE_START(IQ80332, "Intel IQ80332")
         /* Maintainer: Intel Corp. */
-        .phys_io        = 0xfefff000,
-        .io_pg_offst    = ((0xfffff000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = iop3xx_map_io,
         .init_irq       = iop33x_init_irq,
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 1a557e0d055..88663ab1d2a 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -253,8 +253,6 @@ static void __init enp2611_init_machine(void)
 
 MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = IXP2000_UART_PHYS_BASE,
-        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = enp2611_map_io,
         .init_irq       = ixp2000_init_irq,
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
index 6a827681680..0ef533b2097 100644
--- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -11,16 +11,14 @@
  *
 */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0xc0000000        @ Physical base
-                movne   \rx, #0xfe000000        @ virtual base
-                orrne   \rx, \rx, #0x00f00000
-                orr     \rx, \rx, #0x00030000
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00030000
 #ifdef  __ARMEB__
-                orr     \rx, \rx, #0x00000003
+                orr     \rp, \rp, #0x00000003
 #endif
+                orr     \rv, \rp, #0xfe000000   @ virtual base
+                orr     \rv, \rv, #0x00f00000
+                orr     \rp, \rp, #0xc0000000   @ Physical base
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index 55e5c69352a..dfffc1e817f 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -170,8 +170,6 @@ void __init ixdp2400_init_irq(void)
 
 MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP2000_UART_PHYS_BASE,
-        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = ixdp2x00_map_io,
         .init_irq       = ixdp2400_init_irq,
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 237b61a85e9..cd4c9bcff2b 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -285,8 +285,6 @@ void __init ixdp2800_init_irq(void)
 
 MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP2000_UART_PHYS_BASE,
-        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = ixdp2x00_map_io,
         .init_irq       = ixdp2800_init_irq,
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 0369ec4242a..6c121bdbe31 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -416,8 +416,6 @@ static void __init ixdp2x01_init_machine(void)
 #ifdef CONFIG_ARCH_IXDP2401
 MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP2000_UART_PHYS_BASE,
-        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = ixdp2x01_map_io,
         .init_irq       = ixdp2x01_init_irq,
@@ -429,8 +427,6 @@ MACHINE_END
 #ifdef CONFIG_ARCH_IXDP2801
 MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP2000_UART_PHYS_BASE,
-        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = ixdp2x01_map_io,
         .init_irq       = ixdp2x01_init_irq,
@@ -444,8 +440,6 @@ MACHINE_END
  */
 MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP2000_UART_PHYS_BASE,
-        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = ixdp2x01_map_io,
         .init_irq       = ixdp2x01_init_irq,
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index 1c06bfc5a7e..e25e5fe183b 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -85,8 +85,6 @@ static void __init espresso_init(void)
 
 MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
         /* Maintainer: Lennert Buytenhek */
-        .phys_io        = IXP23XX_PERIPHERAL_PHYS,
-        .io_pg_offst    = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
         .map_io         = ixp23xx_map_io,
         .init_irq       = ixp23xx_init_irq,
         .timer          = &ixp23xx_timer,
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
index a82e375465e..f7c6eef7fa2 100644
--- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
@@ -12,13 +12,12 @@
  */
 #include <mach/ixp23xx.h>
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                         @ mmu enabled?
-                ldreq   \rx, =IXP23XX_PERIPHERAL_PHYS   @ physical
-                ldrne   \rx, =IXP23XX_PERIPHERAL_VIRT   @ virtual
+                .macro  addruart, rp, rv
+                ldr     \rp, =IXP23XX_PERIPHERAL_PHYS   @ physical
+                ldr     \rv, =IXP23XX_PERIPHERAL_VIRT   @ virtual
 #ifdef __ARMEB__
-                orr     \rx, \rx, #0x00000003
+                orr     \rp, \rp, #0x00000003
+                orr     \rv, \rv, #0x00000003
 #endif
                 .endm
 
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index f1b124a709a..664e39c2a90 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -328,8 +328,6 @@ static void __init ixdp2351_init(void)
 
 MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP23XX_PERIPHERAL_PHYS,
-        .io_pg_offst    = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
         .map_io         = ixdp2351_map_io,
         .init_irq       = ixdp2351_init_irq,
         .timer          = &ixp23xx_timer,
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 6d38d769761..76c61ba7321 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -171,8 +171,6 @@ static void __init roadrunner_init(void)
 
 MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
         /* Maintainer: Deepak Saxena */
-        .phys_io        = IXP23XX_PERIPHERAL_PHYS,
-        .io_pg_offst    = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
         .map_io         = ixp23xx_map_io,
         .init_irq       = ixp23xx_init_irq,
         .timer          = &ixp23xx_timer,
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index d8bc86d76f1..73745ff102d 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -164,8 +164,6 @@ static void __init avila_init(void)
 
 MACHINE_START(AVILA, "Gateworks Avila Network Platform")
         /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
@@ -181,8 +179,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_LOFT
 MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
         /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 31a47f6a893..355e3de3873 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -109,8 +109,6 @@ static void __init coyote_init(void)
 #ifdef CONFIG_ARCH_ADI_COYOTE
 MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
@@ -126,8 +124,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_IXDPG425
 MACHINE_START(IXDPG425, "Intel IXDPG425")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 7c1fa54a614..d398229cfaa 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -279,8 +279,6 @@ static void __init dsmg600_init(void)
 
 MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
         /* Maintainer: www.nslu2-linux.org */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index e7f4befba42..727ee39ce11 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -270,8 +270,6 @@ static void __init fsg_init(void)
 
 MACHINE_START(FSG, "Freecom FSG-3")
         /* Maintainer: www.nslu2-linux.org */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 2583b2a1317..9dc0b4eaa65 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -96,8 +96,6 @@ static void __init gateway7001_init(void)
 #ifdef CONFIG_MACH_GATEWAY7001
 MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
         /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 1c28048209c..d0e4861ac03 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -496,8 +496,6 @@ subsys_initcall(gmlr_pci_init);
 
 MACHINE_START(GORAMO_MLR, "MultiLink")
         /* Maintainer: Krzysztof Halasa */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index c67586b7940..77abead3622 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -164,8 +164,6 @@ static void __init gtwx5715_init(void)
 
 MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
         /* Maintainer: George Joseph */
-        .phys_io        = IXP4XX_UART2_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
index 3fc66d6d00a..b974a49c0af 100644
--- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -10,16 +10,16 @@
  * published by the Free Software Foundation.
 */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0xc8000000
-                movne   \rx, #0xff000000
-                orrne   \rx, \rx, #0x00b00000
+                .macro  addruart, rp, rv
 #ifdef __ARMEB__
-                add     \rx,\rx,#3              @ Uart regs are at off set of 3 if
-                                                @ byte writes used - Big Endian.
+                mov     \rp, #3         @ Uart regs are at off set of 3 if
+                                        @ byte writes used - Big Endian.
+#else
+                mov     \rp, #0
 #endif
+                orr     \rv, \rp, #0xff000000   @ virtual
+                orr     \rv, \rv, #0x00b00000
+                orr     \rp, \rp, #0xc8000000   @ physical
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index ea9ee4ed0a3..14078338678 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -257,8 +257,6 @@ static void __init ixdp425_init(void)
 #ifdef CONFIG_ARCH_IXDP425
 MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
@@ -270,8 +268,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_IXDP465
 MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
@@ -283,8 +279,6 @@ MACHINE_END
 #ifdef CONFIG_ARCH_PRPMC1100
 MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
@@ -296,8 +290,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_KIXRP435
 MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index e3ee880aa1e..f18fee74887 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -314,8 +314,6 @@ static void __init nas100d_init(void)
 
 MACHINE_START(NAS100D, "Iomega NAS 100d")
         /* Maintainer: www.nslu2-linux.org */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index c14e0034be4..f79b62eb761 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -300,8 +300,6 @@ static void __init nslu2_init(void)
 
 MACHINE_START(NSLU2, "Linksys NSLU2")
         /* Maintainer: www.nslu2-linux.org */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 465cc5cce68..4e72cfdd3c4 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -236,8 +236,6 @@ static void __init vulcan_init(void)
 
 MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 4dd74863daa..5d148c7bc4f 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -97,8 +97,6 @@ static void __init wg302v2_init(void)
 #ifdef CONFIG_MACH_WG302V2
 MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
         /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
-        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
         .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index cc25501b57f..34106335c72 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,12 @@ config MACH_TS41X
           QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
           devices.
 
+config MACH_DOCKSTAR
+        bool "Seagate FreeAgent DockStar"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent DockStar.
+
 config MACH_OPENRD
         bool
 
@@ -100,6 +106,12 @@ config MACH_NETSPACE_MAX_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Network Space Max v2 NAS.
 
+config MACH_D2NET_V2
+        bool "LaCie d2 Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network v2 NAS.
+
 config MACH_NET2BIG_V2
         bool "LaCie 2Big Network v2 NAS Board"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 295d7baa6ae..5dcaa81a2ec 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -7,14 +7,16 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE)	+= mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
+obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
-obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
-obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o
-obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o
-obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o
+obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 1c82d4290da..51ff23b72d3 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -903,10 +903,16 @@ static struct platform_device kirkwood_i2s_device = {
         },
 };
 
+static struct platform_device kirkwood_pcm_device = {
+        .name           = "kirkwood-pcm-audio",
+        .id             = -1,
+};
+
 void __init kirkwood_audio_init(void)
 {
         kirkwood_clk_ctrl |= CGC_AUDIO;
         platform_device_register(&kirkwood_i2s_device);
+        platform_device_register(&kirkwood_pcm_device);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
new file mode 100644
index 00000000000..4aa86e4a152
--- /dev/null
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -0,0 +1,229 @@
+/*
+ * arch/arm/mach-kirkwood/d2net_v2-setup.c
+ *
+ * LaCie d2 Network Space v2 Board Setup
+ *
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <mach/leds-ns2.h>
+#include "common.h"
+#include "mpp.h"
+#include "lacie_v2-common.h"
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data d2net_v2_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data d2net_v2_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_PUSH_BUTTON          34
+#define D2NET_V2_GPIO_POWER_SWITCH_ON      13
+#define D2NET_V2_GPIO_POWER_SWITCH_OFF     15
+
+#define D2NET_V2_SWITCH_POWER_ON           0x1
+#define D2NET_V2_SWITCH_POWER_OFF          0x2
+
+static struct gpio_keys_button d2net_v2_buttons[] = {
+        [0] = {
+                .type           = EV_SW,
+                .code           = D2NET_V2_SWITCH_POWER_ON,
+                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_ON,
+                .desc           = "Back power switch (on|auto)",
+                .active_low     = 0,
+        },
+        [1] = {
+                .type           = EV_SW,
+                .code           = D2NET_V2_SWITCH_POWER_OFF,
+                .gpio           = D2NET_V2_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Back power switch (auto|off)",
+                .active_low     = 0,
+        },
+        [2] = {
+                .code           = KEY_POWER,
+                .gpio           = D2NET_V2_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data d2net_v2_button_data = {
+        .buttons        = d2net_v2_buttons,
+        .nbuttons       = ARRAY_SIZE(d2net_v2_buttons),
+};
+
+static struct platform_device d2net_v2_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_RED_LED           12
+
+static struct gpio_led d2net_v2_gpio_led_pins[] = {
+        {
+                .name   = "d2net_v2:red:fail",
+                .gpio   = D2NET_V2_GPIO_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data d2net_v2_gpio_leds_data = {
+        .num_leds       = ARRAY_SIZE(d2net_v2_gpio_led_pins),
+        .leds           = d2net_v2_gpio_led_pins,
+};
+
+static struct platform_device d2net_v2_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_gpio_leds_data,
+        },
+};
+
+/*****************************************************************************
+ * Dual-GPIO CPLD LEDs
+ ****************************************************************************/
+
+#define D2NET_V2_GPIO_BLUE_LED_SLOW     29
+#define D2NET_V2_GPIO_BLUE_LED_CMD      30
+
+static struct ns2_led d2net_v2_led_pins[] = {
+        {
+                .name   = "d2net_v2:blue:sata",
+                .cmd    = D2NET_V2_GPIO_BLUE_LED_CMD,
+                .slow   = D2NET_V2_GPIO_BLUE_LED_SLOW,
+        },
+};
+
+static struct ns2_led_platform_data d2net_v2_leds_data = {
+        .num_leds       = ARRAY_SIZE(d2net_v2_led_pins),
+        .leds           = d2net_v2_led_pins,
+};
+
+static struct platform_device d2net_v2_leds = {
+        .name           = "leds-ns2",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_v2_leds_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static unsigned int d2net_v2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP6_SYSRST_OUTn,
+        MPP7_GPO,               /* Request power-off */
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_GPO,              /* Red led */
+        MPP13_GPIO,             /* Rear power switch (on|auto) */
+        MPP14_GPIO,             /* USB fuse */
+        MPP15_GPIO,             /* Rear power switch (auto|off) */
+        MPP16_GPIO,             /* SATA 0 power */
+        MPP21_SATA0_ACTn,
+        MPP24_GPIO,             /* USB mode select */
+        MPP26_GPIO,             /* USB device vbus */
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* Blue led (slow register) */
+        MPP30_GPIO,             /* Blue led (command register) */
+        MPP34_GPIO,             /* Power button (1 = Released, 0 = Pushed) */
+        MPP35_GPIO,             /* Inhibit power-off */
+        0
+};
+
+#define D2NET_V2_GPIO_POWER_OFF         7
+
+static void d2net_v2_power_off(void)
+{
+        gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1);
+}
+
+static void __init d2net_v2_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(d2net_v2_mpp_config);
+
+        lacie_v2_hdd_power_init(1);
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&d2net_v2_ge00_data);
+        kirkwood_sata_init(&d2net_v2_sata_data);
+        kirkwood_uart0_init();
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
+
+        platform_device_register(&d2net_v2_leds);
+        platform_device_register(&d2net_v2_gpio_leds);
+        platform_device_register(&d2net_v2_gpio_buttons);
+
+        if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = d2net_v2_power_off;
+        else
+                pr_err("d2net_v2: failed to configure power-off GPIO\n");
+}
+
+MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &lacie_v2_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 16f6691e7c6..9ea71182d31 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -97,8 +97,6 @@ subsys_initcall(db88f6281_pci_init);
 
 MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
         /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = db88f6281_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
new file mode 100644
index 00000000000..433ea368c06
--- /dev/null
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -0,0 +1,110 @@
+/*
+ * arch/arm/mach-kirkwood/dockstar-setup.c
+ *
+ * Seagate FreeAgent DockStar Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition dockstar_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct gpio_led dockstar_led_pins[] = {
+        {
+                .name                   = "dockstar:green:health",
+                .default_trigger        = "default-on",
+                .gpio                   = 46,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "dockstar:orange:misc",
+                .default_trigger        = "none",
+                .gpio                   = 47,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data dockstar_led_data = {
+        .leds           = dockstar_led_pins,
+        .num_leds       = ARRAY_SIZE(dockstar_led_pins),
+};
+
+static struct platform_device dockstar_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &dockstar_led_data,
+        }
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP46_GPIO,     /* LED green */
+        MPP47_GPIO,     /* LED orange */
+        0
+};
+
+static void __init dockstar_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+
+        /* setup gpio pin select */
+        kirkwood_mpp_conf(dockstar_mpp_config);
+
+        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25);
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&dockstar_ge00_data);
+
+        platform_device_register(&dockstar_leds);
+}
+
+MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
+        .boot_params    = 0x00000100,
+        .init_machine   = dockstar_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 54d07c89d4f..8f47dc0a2fe 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -121,8 +121,6 @@ static void __init guruplug_init(void)
 
 MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
         /* Maintainer: Siddarth Gore <gores@marvell.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = guruplug_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
index d0606774dea..db06ae437d0 100644
--- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S
+++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
-        ldrne   \rx, =KIRKWOOD_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
+        .macro  addruart, rp, rv
+        ldr     \rp, =KIRKWOOD_REGS_PHYS_BASE
+        ldr     \rv, =KIRKWOOD_REGS_VIRT_BASE
+        orr     \rp, \rp, #0x00012000
+        orr     \rv, \rv, #0x00012000
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
new file mode 100644
index 00000000000..24b536ebdf1
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
+ *
+ * Platform data structure for netxbig LED driver
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_LEDS_NETXBIG_H
+#define __MACH_LEDS_NETXBIG_H
+
+struct netxbig_gpio_ext {
+        unsigned        *addr;
+        int             num_addr;
+        unsigned        *data;
+        int             num_data;
+        unsigned        enable;
+};
+
+enum netxbig_led_mode {
+        NETXBIG_LED_OFF,
+        NETXBIG_LED_ON,
+        NETXBIG_LED_SATA,
+        NETXBIG_LED_TIMER1,
+        NETXBIG_LED_TIMER2,
+        NETXBIG_LED_MODE_NUM,
+};
+
+#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM
+
+struct netxbig_led_timer {
+        unsigned long           delay_on;
+        unsigned long           delay_off;
+        enum netxbig_led_mode   mode;
+};
+
+struct netxbig_led {
+        const char      *name;
+        const char      *default_trigger;
+        int             mode_addr;
+        int             *mode_val;
+        int             bright_addr;
+};
+
+struct netxbig_led_platform_data {
+        struct netxbig_gpio_ext *gpio_ext;
+        struct netxbig_led_timer *timer;
+        int                     num_timer;
+        struct netxbig_led      *leds;
+        int                     num_leds;
+};
+
+#endif /* __MACH_LEDS_NETXBIG_H */
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c
new file mode 100644
index 00000000000..d3ea1b6c8a0
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.c
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-kirkwood/lacie_v2-common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/gpio.h>
+#include <asm/mach/time.h>
+#include <mach/kirkwood.h>
+#include <mach/irqs.h>
+#include <plat/time.h>
+#include "common.h"
+
+/*****************************************************************************
+ * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
+ ****************************************************************************/
+
+static struct mtd_partition lacie_v2_flash_parts[] = {
+        {
+                .name = "u-boot",
+                .size = MTDPART_SIZ_FULL,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE, /* force read-only */
+        },
+};
+
+static const struct flash_platform_data lacie_v2_flash = {
+        .type           = "mx25l4005a",
+        .name           = "spi_flash",
+        .parts          = lacie_v2_flash_parts,
+        .nr_parts       = ARRAY_SIZE(lacie_v2_flash_parts),
+};
+
+static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &lacie_v2_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+void __init lacie_v2_register_flash(void)
+{
+        spi_register_board_info(lacie_v2_spi_slave_info,
+                                ARRAY_SIZE(lacie_v2_spi_slave_info));
+        kirkwood_spi_init();
+}
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+static struct at24_platform_data at24c04 = {
+        .byte_len       = SZ_4K / 8,
+        .page_size      = 16,
+};
+
+/*
+ * i2c addr | chip         | description
+ * 0x50     | HT24LC04     | eeprom (512B)
+ */
+
+static struct i2c_board_info __initdata lacie_v2_i2c_info[] = {
+        {
+                I2C_BOARD_INFO("24c04", 0x50),
+                .platform_data  = &at24c04,
+        }
+};
+
+void __init lacie_v2_register_i2c_devices(void)
+{
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, lacie_v2_i2c_info,
+                                ARRAY_SIZE(lacie_v2_i2c_info));
+}
+
+/*****************************************************************************
+ * Hard Disk power
+ ****************************************************************************/
+
+static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
+
+void __init lacie_v2_hdd_power_init(int hdd_num)
+{
+        int i;
+        int err;
+
+        /* Power up all hard disks. */
+        for (i = 0; i < hdd_num; i++) {
+                err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL);
+                if (err == 0) {
+                        err = gpio_direction_output(
+                                        lacie_v2_gpio_hdd_power[i], 1);
+                        /* Free the HDD power GPIOs. This allow user-space to
+                         * configure them via the gpiolib sysfs interface. */
+                        gpio_free(lacie_v2_gpio_hdd_power[i]);
+                }
+                if (err)
+                        pr_err("Failed to power up HDD%d\n", i + 1);
+        }
+}
+
+/*****************************************************************************
+ * Timer
+ ****************************************************************************/
+
+static void lacie_v2_timer_init(void)
+{
+        kirkwood_tclk = 166666667;
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+}
+
+struct sys_timer lacie_v2_timer = {
+        .init = lacie_v2_timer_init,
+};
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.h b/arch/arm/mach-kirkwood/lacie_v2-common.h
new file mode 100644
index 00000000000..af521315b87
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.h
@@ -0,0 +1,18 @@
+/*
+ * arch/arm/mach-kirkwood/lacie_v2-common.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
+#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
+
+void lacie_v2_register_flash(void);
+void lacie_v2_register_i2c_devices(void);
+void lacie_v2_hdd_power_init(int hdd_num);
+
+extern struct sys_timer lacie_v2_timer;
+
+#endif
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index c6b92b42eb4..1e5266f57e2 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -163,8 +163,6 @@ subsys_initcall(mv88f6281gtw_ge_pci_init);
 
 MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = mv88f6281gtw_ge_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index d26bf324738..5ea66f1f417 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -24,56 +24,20 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/leds.h>
+#include <linux/gpio-fan.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 #include <mach/kirkwood.h>
 #include <mach/leds-ns2.h>
-#include <plat/time.h>
 #include "common.h"
 #include "mpp.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition netspace_v2_flash_parts[] = {
-        {
-                .name = "u-boot",
-                .size = MTDPART_SIZ_FULL,
-                .offset = 0,
-                .mask_flags = MTD_WRITEABLE, /* force read-only */
-        },
-};
-
-static const struct flash_platform_data netspace_v2_flash = {
-        .type           = "mx25l4005a",
-        .name           = "spi_flash",
-        .parts          = netspace_v2_flash_parts,
-        .nr_parts       = ARRAY_SIZE(netspace_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &netspace_v2_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
+#include "lacie_v2-common.h"
 
 /*****************************************************************************
  * Ethernet
@@ -84,27 +48,6 @@ static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
 };
 
 /*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
-        .byte_len       = SZ_4K / 8,
-        .page_size      = 16,
-};
-
-/*
- * i2c addr | chip         | description
- * 0x50     | HT24LC04     | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata netspace_v2_i2c_info[] = {
-        {
-                I2C_BOARD_INFO("24c04", 0x50),
-                .platform_data  = &at24c04,
-        }
-};
-
-/*****************************************************************************
  * SATA
  ****************************************************************************/
 
@@ -112,35 +55,6 @@ static struct mv_sata_platform_data netspace_v2_sata_data = {
         .n_ports        = 2,
 };
 
-#define NETSPACE_V2_GPIO_SATA0_POWER    16
-#define NETSPACE_V2_GPIO_SATA1_POWER    17
-
-static void __init netspace_v2_sata_power_init(void)
-{
-        int err;
-
-        err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power");
-        if (err == 0) {
-                err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1);
-                if (err)
-                        gpio_free(NETSPACE_V2_GPIO_SATA0_POWER);
-        }
-        if (err)
-                pr_err("netspace_v2: failed to setup SATA0 power\n");
-
-        if (machine_is_netspace_max_v2()) {
-                err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
-                if (err == 0) {
-                        err = gpio_direction_output(
-                                        NETSPACE_V2_GPIO_SATA1_POWER, 1);
-                        if (err)
-                                gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
-                }
-                if (err)
-                        pr_err("netspace_v2: failed to setup SATA1 power\n");
-        }
-}
-
 /*****************************************************************************
  * GPIO keys
  ****************************************************************************/
@@ -224,17 +138,43 @@ static struct platform_device netspace_v2_leds = {
 };
 
 /*****************************************************************************
- * Timer
+ * GPIO fan
  ****************************************************************************/
 
-static void netspace_v2_timer_init(void)
-{
-        kirkwood_tclk = 166666667;
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
+/* Designed for fan 40x40x16: ADDA AD0412LB-D50 6000rpm@12v */
+static struct gpio_fan_speed netspace_max_v2_fan_speed[] = {
+        {    0,  0 },
+        { 1500, 15 },
+        { 1700, 14 },
+        { 1800, 13 },
+        { 2100, 12 },
+        { 3100, 11 },
+        { 3300, 10 },
+        { 4300,  9 },
+        { 5500,  8 },
+};
+
+static unsigned netspace_max_v2_fan_ctrl[] = { 22, 7, 33, 23 };
+
+static struct gpio_fan_alarm netspace_max_v2_fan_alarm = {
+        .gpio           = 25,
+        .active_low     = 1,
+};
 
-struct sys_timer netspace_v2_timer = {
-        .init = netspace_v2_timer_init,
+static struct gpio_fan_platform_data netspace_max_v2_fan_data = {
+        .num_ctrl       = ARRAY_SIZE(netspace_max_v2_fan_ctrl),
+        .ctrl           = netspace_max_v2_fan_ctrl,
+        .alarm          = &netspace_max_v2_fan_alarm,
+        .num_speed      = ARRAY_SIZE(netspace_max_v2_fan_speed),
+        .speed          = netspace_max_v2_fan_speed,
+};
+
+static struct platform_device netspace_max_v2_gpio_fan = {
+        .name   = "gpio-fan",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &netspace_max_v2_fan_data,
+        },
 };
 
 /*****************************************************************************
@@ -291,22 +231,23 @@ static void __init netspace_v2_init(void)
         kirkwood_init();
         kirkwood_mpp_conf(netspace_v2_mpp_config);
 
-        netspace_v2_sata_power_init();
+        if (machine_is_netspace_max_v2())
+                lacie_v2_hdd_power_init(2);
+        else
+                lacie_v2_hdd_power_init(1);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&netspace_v2_ge00_data);
         kirkwood_sata_init(&netspace_v2_sata_data);
         kirkwood_uart0_init();
-        spi_register_board_info(netspace_v2_spi_slave_info,
-                                ARRAY_SIZE(netspace_v2_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, netspace_v2_i2c_info,
-                                ARRAY_SIZE(netspace_v2_i2c_info));
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
 
         platform_device_register(&netspace_v2_leds);
         platform_device_register(&netspace_v2_gpio_leds);
         platform_device_register(&netspace_v2_gpio_buttons);
+        if (machine_is_netspace_max_v2())
+                platform_device_register(&netspace_max_v2_gpio_fan);
 
         if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
             gpio_direction_output(NETSPACE_V2_GPIO_POWER_OFF, 0) == 0)
@@ -317,36 +258,30 @@ static void __init netspace_v2_init(void)
 
 #ifdef CONFIG_MACH_NETSPACE_V2
 MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
 #ifdef CONFIG_MACH_INETSPACE_V2
 MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
 #ifdef CONFIG_MACH_NETSPACE_MAX_V2
 MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netspace_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 2bd14c5079d..a1b45d501ae 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -23,55 +23,19 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
 #include <mach/kirkwood.h>
-#include <plat/time.h>
+#include <mach/leds-netxbig.h>
 #include "common.h"
 #include "mpp.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition netxbig_v2_flash_parts[] = {
-        {
-                .name = "u-boot",
-                .size = MTDPART_SIZ_FULL,
-                .offset = 0,
-                .mask_flags = MTD_WRITEABLE, /* force read-only */
-        },
-};
-
-static const struct flash_platform_data netxbig_v2_flash = {
-        .type           = "mx25l4005a",
-        .name           = "spi_flash",
-        .parts          = netxbig_v2_flash_parts,
-        .nr_parts       = ARRAY_SIZE(netxbig_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &netxbig_v2_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
+#include "lacie_v2-common.h"
 
 /*****************************************************************************
  * Ethernet
@@ -86,27 +50,6 @@ static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
 };
 
 /*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
-        .byte_len       = SZ_4K / 8,
-        .page_size      = 16,
-};
-
-/*
- * i2c addr | chip         | description
- * 0x50     | HT24LC04     | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = {
-        {
-                I2C_BOARD_INFO("24c04", 0x50),
-                .platform_data  = &at24c04,
-        }
-};
-
-/*****************************************************************************
  * SATA
  ****************************************************************************/
 
@@ -114,34 +57,6 @@ static struct mv_sata_platform_data netxbig_v2_sata_data = {
         .n_ports        = 2,
 };
 
-static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
-
-static void __init netxbig_v2_sata_power_init(void)
-{
-        int i;
-        int err;
-        int hdd_nb;
-
-        if (machine_is_net2big_v2())
-                hdd_nb = 2;
-        else
-                hdd_nb = 5;
-
-        /* Power up all hard disks. */
-        for (i = 0; i < hdd_nb; i++) {
-                err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL);
-                if (err == 0) {
-                        err = gpio_direction_output(
-                                        netxbig_v2_gpio_hdd_power[i], 1);
-                        /* Free the HDD power GPIOs. This allow user-space to
-                         * configure them via the gpiolib sysfs interface. */
-                        gpio_free(netxbig_v2_gpio_hdd_power[i]);
-                }
-                if (err)
-                        pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1);
-        }
-}
-
 /*****************************************************************************
  * GPIO keys
  ****************************************************************************/
@@ -190,7 +105,7 @@ static struct platform_device netxbig_v2_gpio_buttons = {
 };
 
 /*****************************************************************************
- * GPIO LEDs
+ * GPIO extension LEDs
  ****************************************************************************/
 
 /*
@@ -200,19 +115,32 @@ static struct platform_device netxbig_v2_gpio_buttons = {
  * - address register : bit [0-2] -> GPIO [47-49]
  * - data register    : bit [0-2] -> GPIO [44-46]
  * - enable register  : GPIO 29
- *
+ */
+
+static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
+static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
+
+static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
+        .addr           = netxbig_v2_gpio_ext_addr,
+        .num_addr       = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
+        .data           = netxbig_v2_gpio_ext_data,
+        .num_data       = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
+        .enable         = 29,
+};
+
+/*
  * Address register selection:
  *
  * addr | register
  * ----------------------------
  *   0  | front LED
  *   1  | front LED brightness
- *   2  | HDD LED brightness
- *   3  | HDD1 LED
- *   4  | HDD2 LED
- *   5  | HDD3 LED
- *   6  | HDD4 LED
- *   7  | HDD5 LED
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
  *
  * Data register configuration:
  *
@@ -233,30 +161,107 @@ static struct platform_device netxbig_v2_gpio_buttons = {
  *   6  | blink blue on=1 sec and red on=1 sec
  *   7  | blink blue on=0.5 sec and blue off=2.5 sec
  *
- * data | HDD LED mode
+ * data | SATA LED mode
  * -------------------------------------------------
- *   0  | fix blue on
+ *   0  | fix off
  *   1  | SATA activity blink
  *   2  | fix red on
  *   3  | blink blue on=1 sec and blue off=1 sec
  *   4  | blink red on=1 sec and red off=1 sec
  *   5  | blink blue on=2.5 sec and red on=0.5 sec
  *   6  | blink blue on=1 sec and red on=1 sec
- *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *   7  | fix blue on
  */
 
-/*****************************************************************************
- * Timer
- ****************************************************************************/
+static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 2,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 4,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
 
-static void netxbig_v2_timer_init(void)
-{
-        kirkwood_tclk = 166666667;
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
+static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 1,
+        [NETXBIG_LED_SATA]      = NETXBIG_LED_INVALID_MODE,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = 7,
+};
+
+static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
+        [NETXBIG_LED_OFF]       = 0,
+        [NETXBIG_LED_ON]        = 7,
+        [NETXBIG_LED_SATA]      = 1,
+        [NETXBIG_LED_TIMER1]    = 3,
+        [NETXBIG_LED_TIMER2]    = NETXBIG_LED_INVALID_MODE,
+};
+
+static struct netxbig_led_timer netxbig_v2_led_timer[] = {
+        [0] = {
+                .delay_on       = 500,
+                .delay_off      = 500,
+                .mode           = NETXBIG_LED_TIMER1,
+        },
+        [1] = {
+                .delay_on       = 500,
+                .delay_off      = 1000,
+                .mode           = NETXBIG_LED_TIMER2,
+        },
+};
+
+#define NETXBIG_LED(_name, maddr, mval, baddr)                  \
+        { .name         = _name,                                \
+          .mode_addr    = maddr,                                \
+          .mode_val     = mval,                                 \
+          .bright_addr  = baddr }
+
+static struct netxbig_led net2big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net2big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net2big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+};
+
+static struct netxbig_led_platform_data net2big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net2big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net2big_v2_leds_ctrl),
+};
+
+static struct netxbig_led net5big_v2_leds_ctrl[] = {
+        NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled,  1),
+        NETXBIG_LED("net5big-v2:red:power",  0, netxbig_v2_red_mled,       1),
+        NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata0",  3, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata1",  4, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata2",  5, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata3",  6, netxbig_v2_red_mled,       2),
+        NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
+        NETXBIG_LED("net5big-v2:red:sata5",  7, netxbig_v2_red_mled,       2),
+};
 
-struct sys_timer netxbig_v2_timer = {
-        .init = netxbig_v2_timer_init,
+static struct netxbig_led_platform_data net5big_v2_leds_data = {
+        .gpio_ext       = &netxbig_v2_gpio_ext,
+        .timer          = netxbig_v2_led_timer,
+        .num_timer      = ARRAY_SIZE(netxbig_v2_led_timer),
+        .leds           = net5big_v2_leds_ctrl,
+        .num_leds       = ARRAY_SIZE(net5big_v2_leds_ctrl),
+};
+
+static struct platform_device netxbig_v2_leds = {
+        .name           = "leds-netxbig",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_v2_leds_data,
+        },
 };
 
 /*****************************************************************************
@@ -284,18 +289,18 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
         MPP24_GPIO,             /* USB mode select */
         MPP26_GPIO,             /* USB device vbus */
         MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP29_GPIO,             /* GPIO extension ALE */
         MPP34_GPIO,             /* Rear Push button */
         MPP35_GPIO,             /* Inhibit switch power-off */
         MPP36_GPIO,             /* SATA HDD1 presence */
         MPP37_GPIO,             /* SATA HDD2 presence */
         MPP40_GPIO,             /* eSATA presence */
-        MPP44_GPIO,             /* CPLD extension (data 0) */
-        MPP45_GPIO,             /* CPLD extension (data 1) */
-        MPP46_GPIO,             /* CPLD extension (data 2) */
-        MPP47_GPIO,             /* CPLD extension (addr 0) */
-        MPP48_GPIO,             /* CPLD extension (addr 1) */
-        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        MPP44_GPIO,             /* GPIO extension (data 0) */
+        MPP45_GPIO,             /* GPIO extension (data 1) */
+        MPP46_GPIO,             /* GPIO extension (data 2) */
+        MPP47_GPIO,             /* GPIO extension (addr 0) */
+        MPP48_GPIO,             /* GPIO extension (addr 1) */
+        MPP49_GPIO,             /* GPIO extension (addr 2) */
         0
 };
 
@@ -324,7 +329,7 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP26_GE1_RXD2,
         MPP27_GE1_RXD3,
         MPP28_GPIO,             /* USB enable host vbus */
-        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP29_GPIO,             /* GPIO extension ALE */
         MPP30_GE1_RXCTL,
         MPP31_GE1_RXCLK,
         MPP32_GE1_TCLKOUT,
@@ -339,12 +344,12 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP41_GPIO,             /* SATA HDD3 power */
         MPP42_GPIO,             /* SATA HDD4 power */
         MPP43_GPIO,             /* SATA HDD5 power */
-        MPP44_GPIO,             /* CPLD extension (data 0) */
-        MPP45_GPIO,             /* CPLD extension (data 1) */
-        MPP46_GPIO,             /* CPLD extension (data 2) */
-        MPP47_GPIO,             /* CPLD extension (addr 0) */
-        MPP48_GPIO,             /* CPLD extension (addr 1) */
-        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        MPP44_GPIO,             /* GPIO extension (data 0) */
+        MPP45_GPIO,             /* GPIO extension (data 1) */
+        MPP46_GPIO,             /* GPIO extension (data 2) */
+        MPP47_GPIO,             /* GPIO extension (addr 0) */
+        MPP48_GPIO,             /* GPIO extension (addr 1) */
+        MPP49_GPIO,             /* GPIO extension (addr 2) */
         0
 };
 
@@ -366,7 +371,10 @@ static void __init netxbig_v2_init(void)
         else
                 kirkwood_mpp_conf(net5big_v2_mpp_config);
 
-        netxbig_v2_sata_power_init();
+        if (machine_is_net2big_v2())
+                lacie_v2_hdd_power_init(2);
+        else
+                lacie_v2_hdd_power_init(5);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&netxbig_v2_ge00_data);
@@ -374,13 +382,12 @@ static void __init netxbig_v2_init(void)
                 kirkwood_ge01_init(&netxbig_v2_ge01_data);
         kirkwood_sata_init(&netxbig_v2_sata_data);
         kirkwood_uart0_init();
-        spi_register_board_info(netxbig_v2_spi_slave_info,
-                                ARRAY_SIZE(netxbig_v2_spi_slave_info));
-        kirkwood_spi_init();
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, netxbig_v2_i2c_info,
-                                ARRAY_SIZE(netxbig_v2_i2c_info));
+        lacie_v2_register_flash();
+        lacie_v2_register_i2c_devices();
 
+        if (machine_is_net5big_v2())
+                netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
+        platform_device_register(&netxbig_v2_leds);
         platform_device_register(&netxbig_v2_gpio_buttons);
 
         if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -392,24 +399,20 @@ static void __init netxbig_v2_init(void)
 
 #ifdef CONFIG_MACH_NET2BIG_V2
 MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netxbig_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
 
 #ifdef CONFIG_MACH_NET5BIG_V2
 MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &netxbig_v2_timer,
+        .timer          = &lacie_v2_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index fd06be61881..c9d77fad10a 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -16,6 +16,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/i2c.h>
+#include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -57,7 +58,22 @@ static struct mvsdio_platform_data openrd_mvsdio_data = {
 };
 
 static unsigned int openrd_mpp_config[] __initdata = {
+        MPP12_SD_CLK,
+        MPP13_SD_CMD,
+        MPP14_SD_D0,
+        MPP15_SD_D1,
+        MPP16_SD_D2,
+        MPP17_SD_D3,
+        MPP28_GPIO,
         MPP29_GPIO,
+        MPP34_GPIO,
+        0
+};
+
+/* Configure MPP for UART1 */
+static unsigned int openrd_uart1_mpp_config[] __initdata = {
+        MPP13_UART1_TXD,
+        MPP14_UART1_RXD,
         0
 };
 
@@ -67,6 +83,68 @@ static struct i2c_board_info i2c_board_info[] __initdata = {
         },
 };
 
+static int __initdata uart1;
+
+static int __init sd_uart_selection(char *str)
+{
+        uart1 = -EINVAL;
+
+        /* Default is SD. Change if required, for UART */
+        if (!str)
+                return 0;
+
+        if (!strncmp(str, "232", 3)) {
+                uart1 = 232;
+        } else if (!strncmp(str, "485", 3)) {
+                /* OpenRD-Base doesn't have RS485. Treat is as an
+                 * unknown argument & just have default setting -
+                 * which is SD */
+                if (machine_is_openrd_base()) {
+                        uart1 = -ENODEV;
+                        return 1;
+                }
+
+                uart1 = 485;
+        }
+        return 1;
+}
+/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */
+__setup("kw_openrd_init_uart1=", sd_uart_selection);
+
+static int __init uart1_mpp_config(void)
+{
+        kirkwood_mpp_conf(openrd_uart1_mpp_config);
+
+        if (gpio_request(34, "SD_UART1_SEL")) {
+                printk(KERN_ERR "GPIO request failed for SD/UART1 selection"
+                                ", gpio: 34\n");
+                return -EIO;
+        }
+
+        if (gpio_request(28, "RS232_RS485_SEL")) {
+                printk(KERN_ERR "GPIO request failed for RS232/RS485 selection"
+                                ", gpio# 28\n");
+                gpio_free(34);
+                return -EIO;
+        }
+
+        /* Select UART1
+         * Pin # 34: 0 => UART1, 1 => SD */
+        gpio_direction_output(34, 0);
+
+        /* Select RS232 OR RS485
+         * Pin # 28: 0 => RS232, 1 => RS485 */
+        if (uart1 == 232)
+                gpio_direction_output(28, 0);
+        else
+                gpio_direction_output(28, 1);
+
+        gpio_free(34);
+        gpio_free(28);
+
+        return 0;
+}
+
 static void __init openrd_init(void)
 {
         /*
@@ -90,7 +168,6 @@ static void __init openrd_init(void)
                 kirkwood_ge01_init(&openrd_ge01_data);
 
         kirkwood_sata_init(&openrd_sata_data);
-        kirkwood_sdio_init(&openrd_mvsdio_data);
 
         kirkwood_i2c_init();
 
@@ -99,6 +176,28 @@ static void __init openrd_init(void)
                         ARRAY_SIZE(i2c_board_info));
                 kirkwood_audio_init();
         }
+
+        if (uart1 <= 0) {
+                if (uart1 < 0)
+                        printk(KERN_ERR "Invalid kernel parameter to select "
+                                "UART1. Defaulting to SD. ERROR CODE: %d\n",
+                                uart1);
+
+                /* Select SD
+                 * Pin # 34: 0 => UART1, 1 => SD */
+                if (gpio_request(34, "SD_UART1_SEL")) {
+                        printk(KERN_ERR "GPIO request failed for SD/UART1 "
+                                        "selection, gpio: 34\n");
+                } else {
+
+                        gpio_direction_output(34, 1);
+                        gpio_free(34);
+                        kirkwood_sdio_init(&openrd_mvsdio_data);
+                }
+        } else {
+                if (!uart1_mpp_config())
+                        kirkwood_uart1_init();
+        }
 }
 
 static int __init openrd_pci_init(void)
@@ -115,8 +214,6 @@ subsys_initcall(openrd_pci_init);
 #ifdef CONFIG_MACH_OPENRD_BASE
 MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
         /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
@@ -128,8 +225,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_OPENRD_CLIENT
 MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
         /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
@@ -141,8 +236,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_OPENRD_ULTIMATE
 MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
         /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index c34718c2cfe..0049614cd32 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -79,8 +79,6 @@ subsys_initcall(rd88f6192_pci_init);
 
 MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
         /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6192_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 3d1477135e1..0998a08cf42 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -115,8 +115,6 @@ subsys_initcall(rd88f6281_pci_init);
 
 MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
         /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6281_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index a00879d34d5..d2eec35dfe0 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -131,8 +131,6 @@ static void __init sheevaplug_init(void)
 #ifdef CONFIG_MACH_SHEEVAPLUG
 MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
         /* Maintainer: shadi Ammouri <shadi@marvell.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
@@ -143,8 +141,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
 MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index d01bf89cedb..ce50e61aac9 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -184,8 +184,6 @@ subsys_initcall(hp_t5325_pci_init);
 
 MACHINE_START(T5325, "HP t5325 Thin Client")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = hp_t5325_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index a5bd7fde04a..6710bd7773b 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -120,8 +120,6 @@ subsys_initcall(ts219_pci_init);
 
 MACHINE_START(TS219, "QNAP TS-119/TS-219")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts219_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 2e14afef07a..8be09a0ce4a 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -149,8 +149,6 @@ subsys_initcall(ts41x_pci_init);
 
 MACHINE_START(TS41X, "QNAP TS-41x")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
-        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts41x_init,
         .map_io         = kirkwood_map_io,
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index 9e3e5a640ad..3ca4f8e6f54 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -223,8 +223,6 @@ static void __init acs5k_init(void)
 
 MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board")
         /* Maintainer: Simtec Electronics. */
-        .phys_io        = KS8695_IO_PA,
-        .io_pg_offst    = (KS8695_IO_VA >> 18) & 0xfffc,
         .boot_params    = KS8695_SDRAM_PA + 0x100,
         .map_io         = ks8695_map_io,
         .init_irq       = ks8695_init_irq,
diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c
index 521ff0789f3..ada92b6bed2 100644
--- a/arch/arm/mach-ks8695/board-dsm320.c
+++ b/arch/arm/mach-ks8695/board-dsm320.c
@@ -121,8 +121,6 @@ static void __init dsm320_init(void)
 
 MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player")
         /* Maintainer: Simtec Electronics. */
-        .phys_io        = KS8695_IO_PA,
-        .io_pg_offst    = (KS8695_IO_VA >> 18) & 0xfffc,
         .boot_params    = KS8695_SDRAM_PA + 0x100,
         .map_io         = ks8695_map_io,
         .init_irq       = ks8695_init_irq,
diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c
index 8ceaf5ac6e2..c7ad09bd6ea 100644
--- a/arch/arm/mach-ks8695/board-micrel.c
+++ b/arch/arm/mach-ks8695/board-micrel.c
@@ -53,8 +53,6 @@ static void __init micrel_init(void)
 
 MACHINE_START(KS8695, "KS8695 Centaur Development Board")
         /* Maintainer: Micrel Semiconductor Inc. */
-        .phys_io        = KS8695_IO_PA,
-        .io_pg_offst    = (KS8695_IO_VA >> 18) & 0xfffc,
         .boot_params    = KS8695_SDRAM_PA + 0x100,
         .map_io         = ks8695_map_io,
         .init_irq       = ks8695_init_irq,
diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/mach-ks8695/include/mach/debug-macro.S
index cf2095da237..bf516adf192 100644
--- a/arch/arm/mach-ks8695/include/mach/debug-macro.S
+++ b/arch/arm/mach-ks8695/include/mach/debug-macro.S
@@ -14,11 +14,9 @@
 #include <mach/hardware.h>
 #include <mach/regs-uart.h>
 
-        .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                         @ MMU enabled?
-                ldreq   \rx, =KS8695_UART_PA            @ physical base address
-                ldrne   \rx, =KS8695_UART_VA            @ virtual base address
+        .macro  addruart, rp, rv
+                ldr     \rp, =KS8695_UART_PA            @ physical base address
+                ldr     \rv, =KS8695_UART_VA            @ virtual base address
         .endm
 
         .macro  senduart, rd, rx
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
new file mode 100644
index 00000000000..b0a2db77d39
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
+/* arch/arm/mach-l7200/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .equ    io_virt, IO_BASE
+                .equ    io_phys, IO_START
+
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00044000        @ UART1
+@               mov     \rp, #0x00045000        @ UART2
+                add     \rv, \rp, #io_virt      @ virtual address
+                add     \rp, \rp, #io_phys      @ physical base address
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x0]        @ UARTDR
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 3d7bd50b909..9088c16662e 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -111,8 +111,6 @@ void __init lh7a40x_init_board_irq (void)
 
 MACHINE_START (KEV7A400, "Sharp KEV7a400")
         /* Maintainer: Marc Singer */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((io_p2v (0x80000000))>>18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = kev7a400_map_io,
         .init_irq       = lh7a400_init_irq,
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index cb15e5d3212..7315a569aea 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -398,8 +398,6 @@ lpd7a40x_map_io(void)
 
 MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
         /* Maintainer: Marc Singer */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((io_p2v (0x80000000))>>18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = lpd7a40x_map_io,
         .init_irq       = lh7a400_init_irq,
@@ -413,8 +411,6 @@ MACHINE_END
 
 MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
         /* Maintainer: Marc Singer */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((io_p2v (0x80000000))>>18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = lpd7a40x_map_io,
         .init_irq       = lh7a404_init_irq,
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
index c0dcbbba22b..cff33625276 100644
--- a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
+++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
@@ -14,12 +14,10 @@
         @ It is not known if this will be appropriate for every 40x
         @ board.
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                mov     \rx, #0x00000700        @ offset from base
-                orreq   \rx, \rx, #0x80000000   @ physical base
-                orrne   \rx, \rx, #0xf8000000   @ virtual base
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00000700        @ offset from base
+                orr     \rv, \rp, #0xf8000000   @ virtual base
+                orr     \rp, \rp, #0x80000000   @ physical base
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S
index 3136c913a92..cc90d99ac76 100644
--- a/arch/arm/mach-loki/include/mach/debug-macro.S
+++ b/arch/arm/mach-loki/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
 
 #include <mach/loki.h>
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =LOKI_REGS_PHYS_BASE
-        ldrne   \rx, =LOKI_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
+        .macro  addruart, rp, rv
+        ldr     \rp, =LOKI_REGS_PHYS_BASE
+        ldr     \rv, =LOKI_REGS_VIRT_BASE
+        orr     \rp, \rp, #0x00012000
+        orr     \rv, \rv, #0x00012000
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index 85f9c1296aa..a1e75e7fc50 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -90,8 +90,6 @@ static void __init lb88rc8480_init(void)
 
 MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
         /* Maintainer: Ke Wei <kewei@marvell.com> */
-        .phys_io        = LOKI_REGS_PHYS_BASE,
-        .io_pg_offst    = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = lb88rc8480_init,
         .map_io         = loki_map_io,
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 621744d6b15..629e744aeb9 100644
--- a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -20,11 +20,9 @@
  * Debug output is hardcoded to standard UART 5
 */
 
-        .macro  addruart,rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                         @ MMU enabled?
-        ldreq   \rx, =0x40090000
-        ldrne   \rx, =0xF4090000
+        .macro  addruart, rp, rv
+        ldreq   \rp, =0x40090000
+        ldrne   \rv, =0xF4090000
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bc9a42da214..7993b096778 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -172,18 +172,12 @@ static void phy3250_spi_cs_set(u32 control)
 }
 
 static struct pl022_config_chip spi0_chip_info = {
-        .lbm                    = LOOPBACK_DISABLED,
         .com_mode               = INTERRUPT_TRANSFER,
         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
         .hierarchy              = SSP_MASTER,
         .slave_tx_disable       = 0,
-        .endian_tx              = SSP_TX_LSB,
-        .endian_rx              = SSP_RX_LSB,
-        .data_size              = SSP_DATA_BITS_8,
         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
-        .clk_phase              = SSP_CLK_FIRST_EDGE,
-        .clk_pol                = SSP_CLK_POL_IDLE_LOW,
         .ctrl_len               = SSP_BITS_8,
         .wait_state             = SSP_MWIRE_WAIT_ZERO,
         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -239,6 +233,7 @@ static int __init phy3250_spi_board_register(void)
                         .max_speed_hz = 5000000,
                         .bus_num = 0,
                         .chip_select = 0,
+                        .mode = SPI_MODE_0,
                         .platform_data = &eeprom,
                         .controller_data = &spi0_chip_info,
                 },
@@ -387,8 +382,6 @@ arch_initcall(lpc32xx_display_uid);
 
 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
         /* Maintainer: Kevin Wells, NXP Semiconductors */
-        .phys_io        = LPC32XX_UART5_BASE,
-        .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = lpc32xx_map_io,
         .init_irq       = lpc32xx_init_irq,
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 6ab843eaa35..0711d3b620a 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -57,6 +57,13 @@ config MACH_MARVELL_JASPER
           PXA910-based development board. Since MMP2 is compatible to
           ARMv6 architecture.
 
+config MACH_TETON_BGA
+        bool "Marvell's PXA168 Teton BGA Development Board"
+        select CPU_PXA168
+        help
+          Say 'Y' here if you want to support the Marvell PXA168-based
+          Teton BGA Development Board.
+
 endmenu
 
 config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 8b66d06739c..751cdbf733c 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_MACH_TAVOREVB)	+= tavorevb.o
 obj-$(CONFIG_MACH_TTC_DKB)      += ttc_dkb.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
+obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 0629394a5fb..06b5fa853c9 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -16,6 +16,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -23,6 +24,9 @@
 #include <mach/mfp-pxa168.h>
 #include <mach/pxa168.h>
 #include <mach/gpio.h>
+#include <video/pxa168fb.h>
+#include <linux/input.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "common.h"
 
@@ -66,6 +70,43 @@ static unsigned long common_pin_config[] __initdata = {
         GPIO115_I2S_BCLK,
         GPIO116_I2S_RXD,
         GPIO117_I2S_TXD,
+
+        /* LCD */
+        GPIO56_LCD_FCLK_RD,
+        GPIO57_LCD_LCLK_A0,
+        GPIO58_LCD_PCLK_WR,
+        GPIO59_LCD_DENA_BIAS,
+        GPIO60_LCD_DD0,
+        GPIO61_LCD_DD1,
+        GPIO62_LCD_DD2,
+        GPIO63_LCD_DD3,
+        GPIO64_LCD_DD4,
+        GPIO65_LCD_DD5,
+        GPIO66_LCD_DD6,
+        GPIO67_LCD_DD7,
+        GPIO68_LCD_DD8,
+        GPIO69_LCD_DD9,
+        GPIO70_LCD_DD10,
+        GPIO71_LCD_DD11,
+        GPIO72_LCD_DD12,
+        GPIO73_LCD_DD13,
+        GPIO74_LCD_DD14,
+        GPIO75_LCD_DD15,
+        GPIO76_LCD_DD16,
+        GPIO77_LCD_DD17,
+        GPIO78_LCD_DD18,
+        GPIO79_LCD_DD19,
+        GPIO80_LCD_DD20,
+        GPIO81_LCD_DD21,
+        GPIO82_LCD_DD22,
+        GPIO83_LCD_DD23,
+
+        /* Keypad */
+        GPIO109_KP_MKIN1,
+        GPIO110_KP_MKIN0,
+        GPIO111_KP_MKOUT7,
+        GPIO112_KP_MKOUT6,
+        GPIO121_KP_MKIN4,
 };
 
 static struct smc91x_platdata smc91x_info = {
@@ -134,6 +175,51 @@ static struct i2c_board_info aspenite_i2c_info[] __initdata = {
         { I2C_BOARD_INFO("wm8753", 0x1b), },
 };
 
+static struct fb_videomode video_modes[] = {
+        [0] = {
+                .pixclock       = 30120,
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .hsync_len      = 1,
+                .left_margin    = 215,
+                .right_margin   = 40,
+                .vsync_len      = 1,
+                .upper_margin   = 34,
+                .lower_margin   = 10,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+        },
+};
+
+struct pxa168fb_mach_info aspenite_lcd_info = {
+        .id                     = "Graphic Frame",
+        .modes                  = video_modes,
+        .num_modes              = ARRAY_SIZE(video_modes),
+        .pix_fmt                = PIX_FMT_RGB565,
+        .io_pin_allocation_mode = PIN_MODE_DUMB_24,
+        .dumb_mode              = DUMB_MODE_RGB888,
+        .active                 = 1,
+        .panel_rbswap           = 0,
+        .invert_pixclock        = 0,
+};
+
+static unsigned int aspenite_matrix_key_map[] = {
+        KEY(0, 6, KEY_UP),      /* SW 4 */
+        KEY(0, 7, KEY_DOWN),    /* SW 5 */
+        KEY(1, 6, KEY_LEFT),    /* SW 6 */
+        KEY(1, 7, KEY_RIGHT),   /* SW 7 */
+        KEY(4, 6, KEY_ENTER),   /* SW 8 */
+        KEY(4, 7, KEY_ESC),     /* SW 9 */
+};
+
+static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
+        .matrix_key_rows        = 5,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = aspenite_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(aspenite_matrix_key_map),
+        .debounce_interval      = 30,
+};
+
 static void __init common_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(common_pin_config));
@@ -143,24 +229,24 @@ static void __init common_init(void)
         pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
         pxa168_add_ssp(1);
         pxa168_add_nand(&aspenite_nand_info);
+        pxa168_add_fb(&aspenite_lcd_info);
+        pxa168_add_keypad(&aspenite_keypad_info);
 
         /* off-chip devices */
         platform_device_register(&smc91x_device);
 }
 
 MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
-        .phys_io        = APB_PHYS_BASE,
-        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
         .init_irq       = pxa168_init_irq,
         .timer          = &pxa168_timer,
         .init_machine   = common_init,
 MACHINE_END
 
 MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
-        .phys_io        = APB_PHYS_BASE,
-        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
         .init_irq       = pxa168_init_irq,
         .timer          = &pxa168_timer,
         .init_machine   = common_init,
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 69bcba11f53..39f0878d64a 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -41,8 +41,6 @@ static void __init avengers_lite_init(void)
 }
 
 MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
-        .phys_io        = APB_PHYS_BASE,
-        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
         .init_irq       = pxa168_init_irq,
         .timer          = &pxa168_timer,
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 3b29fa7e9b0..0ec0ca80bb3 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -10,13 +10,20 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <mach/addr-map.h>
+#include <mach/cputype.h>
 
 #include "common.h"
 
+#define MMP_CHIPID      (AXI_VIRT_BASE + 0x82c00)
+
+unsigned int mmp_chip_id;
+EXPORT_SYMBOL(mmp_chip_id);
+
 static struct map_desc standard_io_desc[] __initdata = {
         {
                 .pfn            = __phys_to_pfn(APB_PHYS_BASE),
@@ -34,4 +41,7 @@ static struct map_desc standard_io_desc[] __initdata = {
 void __init mmp_map_io(void)
 {
         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
+
+        /* this is early, initialize mmp_chip_id here */
+        mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index e4312d238ea..bdeb6db4d49 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -16,6 +16,7 @@
 #include <linux/smc91x.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,6 +26,8 @@
 
 #include "common.h"
 
+#define FLINT_NR_IRQS   (IRQ_BOARD_START + 48)
+
 static unsigned long flint_pin_config[] __initdata = {
         /* UART1 */
         GPIO45_UART1_RXD,
@@ -113,9 +116,8 @@ static void __init flint_init(void)
 }
 
 MACHINE_START(FLINT, "Flint Development Platform")
-        .phys_io        = APB_PHYS_BASE,
-        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = FLINT_NR_IRQS,
         .init_irq       = mmp2_init_irq,
         .timer          = &mmp2_timer,
         .init_machine   = flint_init,
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
index 83b18721d93..f43a68b213f 100644
--- a/arch/arm/mach-mmp/include/mach/cputype.h
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -4,36 +4,51 @@
 #include <asm/cputype.h>
 
 /*
- *  CPU   Stepping   OLD_ID       CPU_ID      CHIP_ID
+ *  CPU   Stepping   CPU_ID      CHIP_ID
  *
- * PXA168    A0    0x41159263   0x56158400   0x00A0A333
- * PXA910    Y0    0x41159262   0x56158000   0x00F0C910
- * MMP2      Z0                 0x560f5811
+ * PXA168    S0    0x56158400   0x0000C910
+ * PXA168    A0    0x56158400   0x00A0A168
+ * PXA910    Y1    0x56158400   0x00F2C920
+ * PXA910    A0    0x56158400   0x00F2C910
+ * PXA910    A1    0x56158400   0x00A0C910
+ * PXA920    Y0    0x56158400   0x00F2C920
+ * PXA920    A0    0x56158400   0x00A0C920
+ * PXA920    A1    0x56158400   0x00A1C920
+ * MMP2      Z0    0x560f5811   0x00F00410
+ * MMP2      Z1    0x560f5811   0x00E00410
+ * MMP2      A0    0x560f5811   0x00A0A610
  */
 
+extern unsigned int mmp_chip_id;
+
 #ifdef CONFIG_CPU_PXA168
-#  define __cpu_is_pxa168(id)   \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
+static inline int cpu_is_pxa168(void)
+{
+        return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+                ((mmp_chip_id & 0xfff) == 0x168);
+}
 #else
-#  define __cpu_is_pxa168(id)   (0)
+#define cpu_is_pxa168() (0)
 #endif
 
+/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
 #ifdef CONFIG_CPU_PXA910
-#  define __cpu_is_pxa910(id)   \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
+static inline int cpu_is_pxa910(void)
+{
+        return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
+                (((mmp_chip_id & 0xfff) == 0x910) ||
+                 ((mmp_chip_id & 0xfff) == 0x920));
+}
 #else
-#  define __cpu_is_pxa910(id)   (0)
+#define cpu_is_pxa910() (0)
 #endif
 
 #ifdef CONFIG_CPU_MMP2
-#  define __cpu_is_mmp2(id)     \
-        ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; })
+static inline int cpu_is_mmp2(void)
+{
+        return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
 #else
-#  define __cpu_is_mmp2(id)     (0)
+#define cpu_is_mmp2()   (0)
 #endif
 
-#define cpu_is_pxa168()         ({ __cpu_is_pxa168(read_cpuid_id()); })
-#define cpu_is_pxa910()         ({ __cpu_is_pxa910(read_cpuid_id()); })
-#define cpu_is_mmp2()           ({ __cpu_is_mmp2(read_cpuid_id()); })
-
 #endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index 76deff238e1..7e2ebd3efc7 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -11,12 +11,11 @@
 
 #include <mach/addr-map.h>
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                         @ MMU enabled?
-                ldreq   \rx, =APB_PHYS_BASE             @ physical
-                ldrne   \rx, =APB_VIRT_BASE             @ virtual
-                orr     \rx, \rx, #0x00017000
+                .macro  addruart, rp, rv
+                ldr     \rp, =APB_PHYS_BASE             @ physical
+                ldr     \rv, =APB_VIRT_BASE             @ virtual
+                orr     \rp, \rp, #0x00017000
+                orr     \rv, \rv, #0x00017000
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index b379cdec4d3..a09d328e2dd 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -222,10 +222,8 @@
 #define IRQ_GPIO_NUM                    192
 #define IRQ_GPIO(x)                     (IRQ_GPIO_START + (x))
 
-/* Board IRQ - 64 by default, increase if not enough */
 #define IRQ_BOARD_START                 (IRQ_GPIO_START + IRQ_GPIO_NUM)
-#define IRQ_BOARD_END                   (IRQ_BOARD_START + 64)
 
-#define NR_IRQS                         (IRQ_BOARD_END)
+#define NR_IRQS                         (IRQ_BOARD_START)
 
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index ded43c455ec..4621067c772 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -289,4 +289,11 @@
 #define GPIO86_PWM1_OUT         MFP_CFG(GPIO86, AF2)
 #define GPIO86_PWM2_OUT         MFP_CFG(GPIO86, AF3)
 
+/* Keypad */
+#define GPIO109_KP_MKIN1        MFP_CFG(GPIO109, AF7)
+#define GPIO110_KP_MKIN0        MFP_CFG(GPIO110, AF7)
+#define GPIO111_KP_MKOUT7       MFP_CFG(GPIO111, AF7)
+#define GPIO112_KP_MKOUT6       MFP_CFG(GPIO112, AF7)
+#define GPIO121_KP_MKIN4        MFP_CFG(GPIO121, AF7)
+
 #endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 27e1bc75862..1801e420623 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -5,11 +5,15 @@ struct sys_timer;
 
 extern struct sys_timer pxa168_timer;
 extern void __init pxa168_init_irq(void);
+extern void pxa168_clear_keypad_wakeup(void);
 
 #include <linux/i2c.h>
 #include <mach/devices.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
+#include <video/pxa168fb.h>
+#include <plat/pxa27x_keypad.h>
+#include <mach/cputype.h>
 
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
@@ -25,6 +29,8 @@ extern struct pxa_device_desc pxa168_device_ssp3;
 extern struct pxa_device_desc pxa168_device_ssp4;
 extern struct pxa_device_desc pxa168_device_ssp5;
 extern struct pxa_device_desc pxa168_device_nand;
+extern struct pxa_device_desc pxa168_device_fb;
+extern struct pxa_device_desc pxa168_device_keypad;
 
 static inline int pxa168_add_uart(int id)
 {
@@ -97,4 +103,18 @@ static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
 {
         return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
 }
+
+static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
+{
+        return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
+}
+
+static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
+{
+        if (cpu_is_pxa168())
+                data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
+
+        return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
+}
+
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 91903051412..ac4702357a6 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -33,4 +33,16 @@
 #define APMU_FNRST_DIS  (1 << 1)
 #define APMU_AXIRST_DIS (1 << 0)
 
+/* Wake Clear Register */
+#define APMU_WAKE_CLR   APMU_REG(0x07c)
+
+#define APMU_PXA168_KP_WAKE_CLR         (1 << 7)
+#define APMU_PXA168_CFI_WAKE_CLR        (1 << 6)
+#define APMU_PXA168_XD_WAKE_CLR         (1 << 5)
+#define APMU_PXA168_MSP_WAKE_CLR        (1 << 4)
+#define APMU_PXA168_SD4_WAKE_CLR        (1 << 3)
+#define APMU_PXA168_SD3_WAKE_CLR        (1 << 2)
+#define APMU_PXA168_SD2_WAKE_CLR        (1 << 1)
+#define APMU_PXA168_SD1_WAKE_CLR        (1 << 0)
+
 #endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/teton_bga.h b/arch/arm/mach-mmp/include/mach/teton_bga.h
new file mode 100644
index 00000000000..61a539b2cc9
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/teton_bga.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/arch/arm/mach-mmp/include/mach/teton_bga.h
+ *
+ *  Support for the Marvell PXA168 Teton BGA Development Platform.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_TETON_BGA_H
+#define __ASM_MACH_TETON_BGA_H
+
+/* GPIOs */
+#define MMC_PWENA_GPIO          27
+#define USBHPENB_GPIO           55
+#define RTC_INT_GPIO            78
+#define LCD_VBLK_EN_GPIO        79
+#define LCD_DVDD_EN_GPIO        80
+#define RST_WIFI_GPIO           81
+#define CF_PWEN_GPIO            82
+#define USB_OC_GPIO             83
+#define PWM_GPIO                84
+#define USBHPENA_GPIO           85
+#define TS_INT_GPIO             86
+#define CIR_GPIO                108
+
+#endif /* __ASM_MACH_TETON_BGA_H */
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 80c3e7ab1e1..2a684fa5077 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -18,16 +18,18 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max8649.h>
 #include <linux/mfd/max8925.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/addr-map.h>
 #include <mach/mfp-mmp2.h>
 #include <mach/mmp2.h>
-#include <mach/irqs.h>
 
 #include "common.h"
 
+#define JASPER_NR_IRQS          (IRQ_BOARD_START + 48)
+
 static unsigned long jasper_pin_config[] __initdata = {
         /* UART1 */
         GPIO29_UART1_RXD,
@@ -134,9 +136,8 @@ static void __init jasper_init(void)
 }
 
 MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
-        .phys_io        = APB_PHYS_BASE,
-        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = JASPER_NR_IRQS,
         .init_irq       = mmp2_init_irq,
         .timer          = &mmp2_timer,
         .init_machine   = jasper_init,
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae660634..72b4e763158 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -77,8 +77,10 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
 static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
+static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 
 static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
 
 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
@@ -96,6 +98,8 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
         INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
 };
 
 static int __init pxa168_init(void)
@@ -132,6 +136,16 @@ struct sys_timer pxa168_timer = {
         .init   = pxa168_timer_init,
 };
 
+void pxa168_clear_keypad_wakeup(void)
+{
+        uint32_t val;
+        uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
+
+        /* wake event clear is needed in order to clear keypad interrupt */
+        val = __raw_readl(APMU_WAKE_CLR);
+        __raw_writel(val |  mask, APMU_WAKE_CLR);
+}
+
 /* on-chip devices */
 PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
 PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
@@ -147,3 +161,5 @@ PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
 PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
 PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
 PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
+PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
+PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index e81db742821..c296b75c445 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -99,8 +99,6 @@ static void __init tavorevb_init(void)
 }
 
 MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
-        .phys_io        = APB_PHYS_BASE,
-        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
         .init_irq       = pxa910_init_irq,
         .timer          = &pxa910_timer,
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
new file mode 100644
index 00000000000..bbe4727b96c
--- /dev/null
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -0,0 +1,89 @@
+/*
+ *  linux/arch/arm/mach-mmp/teton_bga.c
+ *
+ *  Support for the Marvell PXA168 Teton BGA Development Platform.
+ *
+ *  Author: Mark F. Brown <mark.brown314@gmail.com>
+ *
+ *  This code is based on aspenite.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <plat/pxa27x_keypad.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-pxa168.h>
+#include <mach/pxa168.h>
+#include <mach/teton_bga.h>
+
+#include "common.h"
+
+static unsigned long teton_bga_pin_config[] __initdata = {
+        /* UART1 */
+        GPIO107_UART1_TXD,
+        GPIO108_UART1_RXD,
+
+        /* Keypad */
+        GPIO109_KP_MKIN1,
+        GPIO110_KP_MKIN0,
+        GPIO111_KP_MKOUT7,
+        GPIO112_KP_MKOUT6,
+
+        /* I2C Bus */
+        GPIO105_CI2C_SDA,
+        GPIO106_CI2C_SCL,
+
+        /* RTC */
+        GPIO78_GPIO,
+};
+
+static unsigned int teton_bga_matrix_key_map[] = {
+        KEY(0, 6, KEY_ESC),
+        KEY(0, 7, KEY_ENTER),
+        KEY(1, 6, KEY_LEFT),
+        KEY(1, 7, KEY_RIGHT),
+};
+
+static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
+        .matrix_key_rows        = 2,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = teton_bga_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(teton_bga_matrix_key_map),
+        .debounce_interval      = 30,
+};
+
+static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+                .irq = gpio_to_irq(RTC_INT_GPIO)
+        },
+};
+
+static void __init teton_bga_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
+
+        /* on-chip devices */
+        pxa168_add_uart(1);
+        pxa168_add_keypad(&teton_bga_keypad_info);
+        pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
+}
+
+MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
+        .map_io         = mmp_map_io,
+        .nr_irqs        = IRQ_BOARD_START,
+        .init_irq       = pxa168_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = teton_bga_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index ee65e05f0cf..e411039ea59 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -14,6 +14,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/onenand.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -24,6 +25,8 @@
 
 #include "common.h"
 
+#define TTCDKB_NR_IRQS          (IRQ_BOARD_START + 24)
+
 static unsigned long ttc_dkb_pin_config[] __initdata = {
         /* UART2 */
         GPIO47_UART2_RXD,
@@ -122,9 +125,8 @@ static void __init ttc_dkb_init(void)
 }
 
 MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
-        .phys_io        = APB_PHYS_BASE,
-        .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
         .map_io         = mmp_map_io,
+        .nr_irqs        = TTCDKB_NR_IRQS,
         .init_irq       = pxa910_init_irq,
         .timer          = &pxa910_timer,
         .init_machine   = ttc_dkb_init,
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 47264a76eeb..3115a29dec4 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -10,6 +10,8 @@ config ARCH_MSM7X00A
         select MSM_SMD
         select MSM_SMD_PKG3
         select CPU_V6
+        select MSM_PROC_COMM
+        select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_MSM7X30
         bool "MSM7x30"
@@ -18,6 +20,9 @@ config ARCH_MSM7X30
         select MSM_VIC
         select CPU_V7
         select MSM_REMOTE_SPINLOCK_DEKKERS
+        select MSM_GPIOMUX
+        select MSM_PROC_COMM
+        select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_QSD8X50
         bool "QSD8X50"
@@ -26,6 +31,19 @@ config ARCH_QSD8X50
         select MSM_VIC
         select CPU_V7
         select MSM_REMOTE_SPINLOCK_LDREX
+        select MSM_GPIOMUX
+        select MSM_PROC_COMM
+        select HAS_MSM_DEBUG_UART_PHYS
+
+config ARCH_MSM8X60
+        bool "MSM8X60"
+        select ARM_GIC
+        select CPU_V7
+        select MSM_V2_TLMM
+        select MSM_GPIOMUX
+        select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
+                                  && !MACH_MSM8X60_FFA)
+
 endchoice
 
 config MSM_SOC_REV_A
@@ -36,6 +54,9 @@ config  ARCH_MSM_ARM11
 config  ARCH_MSM_SCORPION
         bool
 
+config HAS_MSM_DEBUG_UART_PHYS
+        bool
+
 config  MSM_VIC
         bool
 
@@ -74,6 +95,30 @@ config MACH_QSD8X50A_ST1_5
         help
           Support for the Qualcomm ST1.5.
 
+config MACH_MSM8X60_RUMI3
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 RUMI3"
+        help
+          Support for the Qualcomm MSM8x60 RUMI3 emulator.
+
+config MACH_MSM8X60_SURF
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 SURF"
+        help
+          Support for the Qualcomm MSM8x60 SURF eval board.
+
+config MACH_MSM8X60_SIM
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 Simulator"
+        help
+          Support for the Qualcomm MSM8x60 simulator.
+
+config MACH_MSM8X60_FFA
+        depends on ARCH_MSM8X60
+        bool "MSM8x60 FFA"
+        help
+          Support for the Qualcomm MSM8x60 FFA eval board.
+
 endmenu
 
 config MSM_DEBUG_UART
@@ -82,6 +127,7 @@ config MSM_DEBUG_UART
         default 2 if MSM_DEBUG_UART2
         default 3 if MSM_DEBUG_UART3
 
+if HAS_MSM_DEBUG_UART_PHYS
 choice
         prompt "Debug UART"
 
@@ -99,11 +145,20 @@ choice
         config MSM_DEBUG_UART3
                 bool "UART3"
 endchoice
+endif
 
 config MSM_SMD_PKG3
         bool
 
+config MSM_PROC_COMM
+        bool
+
 config MSM_SMD
         bool
 
+config MSM_GPIOMUX
+        bool
+
+config MSM_V2_TLMM
+        bool
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 704610648a2..b5a7b07a44f 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,16 +1,20 @@
-obj-y += proc_comm.o
-obj-y += io.o idle.o timer.o dma.o
-obj-y += vreg.o
+obj-y += io.o idle.o timer.o
+ifndef CONFIG_ARCH_MSM8X60
 obj-y += acpuclock-arm11.o
-obj-y += clock.o clock-pcom.o
-obj-y += gpio.o
+obj-y += dma.o
+endif
 
 ifdef CONFIG_MSM_VIC
 obj-y += irq-vic.o
 else
+ifndef CONFIG_ARCH_MSM8X60
 obj-y += irq.o
 endif
+endif
 
+obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
+obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
+obj-$(CONFIG_MSM_PROC_COMM) += clock.o
 obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
@@ -19,4 +23,11 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o d
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
+obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
 
+obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
+obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
+obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
+ifndef CONFIG_MSM_V2_TLMM
+obj-y   += gpio.o
+endif
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 7bd72e8f127..59edecbe126 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -95,8 +95,6 @@ static void __init halibut_map_io(void)
 
 MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = 0x10000100,
         .fixup          = halibut_fixup,
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index bcbefdfe7b5..ef3ebf2f763 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -75,8 +75,6 @@ extern struct sys_timer msm_timer;
 
 MACHINE_START(MAHIMAHI, "mahimahi")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = 0x20000100,
         .fixup          = mahimahi_fixup,
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index db9381b85bf..e7a76eff57d 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -131,8 +131,6 @@ static void __init msm7x2x_map_io(void)
 
 MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
@@ -143,8 +141,6 @@ MACHINE_END
 
 MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
@@ -155,8 +151,6 @@ MACHINE_END
 
 MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
@@ -167,8 +161,6 @@ MACHINE_END
 
 MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = msm7x2x_map_io,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index e32981928c7..05241df3f9b 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -39,27 +39,11 @@
 
 extern struct sys_timer msm_timer;
 
-#ifdef CONFIG_SERIAL_MSM_CONSOLE
-static struct msm_gpio uart2_config_data[] = {
-        { GPIO_CFG(49, 2, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_RFR"},
-        { GPIO_CFG(50, 2, GPIO_INPUT,   GPIO_PULL_DOWN, GPIO_2MA), "UART2_CTS"},
-        { GPIO_CFG(51, 2, GPIO_INPUT,   GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
-        { GPIO_CFG(52, 2, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
-};
-
-static void msm7x30_init_uart2(void)
-{
-        msm_gpios_request_enable(uart2_config_data,
-                        ARRAY_SIZE(uart2_config_data));
-
-}
-#endif
-
 static struct platform_device *devices[] __initdata = {
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
 #endif
-
+        &msm_device_smd,
 };
 
 static void __init msm7x30_init_irq(void)
@@ -70,10 +54,6 @@ static void __init msm7x30_init_irq(void)
 static void __init msm7x30_init(void)
 {
         platform_add_devices(devices, ARRAY_SIZE(devices));
-#ifdef CONFIG_SERIAL_MSM_CONSOLE
-        msm7x30_init_uart2();
-#endif
-
 }
 
 static void __init msm7x30_map_io(void)
@@ -84,8 +64,6 @@ static void __init msm7x30_map_io(void)
 
 MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io  = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params = PHYS_OFFSET + 0x100,
         .map_io = msm7x30_map_io,
@@ -96,8 +74,6 @@ MACHINE_END
 
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io  = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params = PHYS_OFFSET + 0x100,
         .map_io = msm7x30_map_io,
@@ -108,8 +84,6 @@ MACHINE_END
 
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io  = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params = PHYS_OFFSET + 0x100,
         .map_io = msm7x30_map_io,
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
new file mode 100644
index 00000000000..7486a681cc7
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -0,0 +1,100 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/msm_iomap.h>
+
+void __iomem *gic_cpu_base_addr;
+
+unsigned long clk_get_max_axi_khz(void)
+{
+        return 0;
+}
+
+static void __init msm8x60_map_io(void)
+{
+        msm_map_msm8x60_io();
+}
+
+static void __init msm8x60_init_irq(void)
+{
+        unsigned int i;
+
+        gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
+        gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
+        gic_cpu_init(0, MSM_QGIC_CPU_BASE);
+
+        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+        /* RUMI does not adhere to GIC spec by enabling STIs by default.
+         * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
+         */
+        if (!machine_is_msm8x60_sim())
+                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+
+        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+         * as they are configured as level, which does not play nice with
+         * handle_percpu_irq.
+         */
+        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+                        set_irq_handler(i, handle_percpu_irq);
+        }
+}
+
+static void __init msm8x60_init(void)
+{
+}
+
+MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
+
+MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
+        .map_io = msm8x60_map_io,
+        .init_irq = msm8x60_init_irq,
+        .init_machine = msm8x60_init,
+        .timer = &msm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index e3cc80792d6..ed2af4ad97e 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -35,20 +35,49 @@
 
 extern struct sys_timer msm_timer;
 
-static struct msm_gpio uart3_config_data[] = {
-        { GPIO_CFG(86, 1, GPIO_INPUT,   GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
-        { GPIO_CFG(87, 1, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
+static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
+static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
+
+/* Leave smc91x resources empty here, as we'll fill them in
+ * at run-time: they vary from board to board, and the true
+ * configuration won't be known until boot.
+ */
+static struct resource smc91x_resources[] __initdata = {
+        [0] = {
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags = IORESOURCE_IRQ,
+        },
 };
 
-static struct platform_device *devices[] __initdata = {
-        &msm_device_uart3,
+static struct platform_device smc91x_device __initdata = {
+        .name           = "smc91x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
 };
 
-static void msm8x50_init_uart3(void)
+static int __init msm_init_smc91x(void)
 {
-        msm_gpios_request_enable(uart3_config_data,
-                                ARRAY_SIZE(uart3_config_data));
+        if (machine_is_qsd8x50_surf()) {
+                smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
+                smc91x_resources[0].end   = qsd8x50_surf_smc91x_base + 0xff;
+                smc91x_resources[1].start =
+                        gpio_to_irq(qsd8x50_surf_smc91x_gpio);
+                smc91x_resources[1].end   =
+                        gpio_to_irq(qsd8x50_surf_smc91x_gpio);
+                platform_device_register(&smc91x_device);
+        }
+
+        return 0;
 }
+module_init(msm_init_smc91x);
+
+static struct platform_device *devices[] __initdata = {
+        &msm_device_uart3,
+        &msm_device_smd,
+};
 
 static void __init qsd8x50_map_io(void)
 {
@@ -64,14 +93,11 @@ static void __init qsd8x50_init_irq(void)
 
 static void __init qsd8x50_init(void)
 {
-        msm8x50_init_uart3();
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
 MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io  = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params = PHYS_OFFSET + 0x100,
         .map_io = qsd8x50_map_io,
@@ -82,8 +108,6 @@ MACHINE_END
 
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io  = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params = PHYS_OFFSET + 0x100,
         .map_io = qsd8x50_map_io,
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2bc1b9d5623..8919ffb1719 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -106,8 +106,6 @@ static void __init sapphire_map_io(void)
 MACHINE_START(SAPPHIRE, "sapphire")
 /* Maintainer: Brian Swetland <swetland@google.com> */
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = PHYS_OFFSET + 0x100,
         .fixup          = sapphire_fixup,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 469e0be3499..73f14606654 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -93,8 +93,6 @@ static void __init trout_map_io(void)
 
 MACHINE_START(TROUT, "HTC Dream")
 #ifdef CONFIG_MSM_DEBUG_UART
-        .phys_io        = MSM_DEBUG_UART_PHYS,
-        .io_pg_offst    = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
 #endif
         .boot_params    = 0x10000100,
         .fixup          = trout_fixup,
diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c
new file mode 100644
index 00000000000..1250d22082e
--- /dev/null
+++ b/arch/arm/mach-msm/clock-dummy.c
@@ -0,0 +1,54 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/module.h>
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+        return -ENOENT;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        return -ENOENT;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index b449e8ad290..7fcf2e3b769 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -51,6 +51,11 @@ struct platform_device msm_device_uart2 = {
         .resource       = resources_uart2,
 };
 
+struct platform_device msm_device_smd = {
+        .name   = "msm_smd",
+        .id     = -1,
+};
+
 struct clk msm_clocks_7x30[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c
new file mode 100644
index 00000000000..89b9d4437e9
--- /dev/null
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -0,0 +1,883 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/bootmem.h>
+
+#include <mach/msm_iomap-8x60.h>
+#include <mach/irqs-8x60.h>
+#include <mach/iommu.h>
+
+static struct resource msm_iommu_jpegd_resources[] = {
+        {
+                .start = MSM_IOMMU_JPEGD_PHYS,
+                .end   = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
+                .end   = SMMU_JPEGD_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vpe_resources[] = {
+        {
+                .start = MSM_IOMMU_VPE_PHYS,
+                .end   = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VPE_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VPE_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_mdp0_resources[] = {
+        {
+                .start = MSM_IOMMU_MDP0_PHYS,
+                .end   = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
+                .end   = SMMU_MDP0_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_mdp1_resources[] = {
+        {
+                .start = MSM_IOMMU_MDP1_PHYS,
+                .end   = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
+                .end   = SMMU_MDP1_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_rot_resources[] = {
+        {
+                .start = MSM_IOMMU_ROT_PHYS,
+                .end   = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_ROT_CB_SC_SECURE_IRQ,
+                .end   = SMMU_ROT_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_ijpeg_resources[] = {
+        {
+                .start = MSM_IOMMU_IJPEG_PHYS,
+                .end   = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
+                .end   = SMMU_IJPEG_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vfe_resources[] = {
+        {
+                .start = MSM_IOMMU_VFE_PHYS,
+                .end   = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VFE_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VFE_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vcodec_a_resources[] = {
+        {
+                .start = MSM_IOMMU_VCODEC_A_PHYS,
+                .end   = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_vcodec_b_resources[] = {
+        {
+                .start = MSM_IOMMU_VCODEC_B_PHYS,
+                .end   = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
+                .end   = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_gfx3d_resources[] = {
+        {
+                .start = MSM_IOMMU_GFX3D_PHYS,
+                .end   = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
+                .end   = SMMU_GFX3D_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource msm_iommu_gfx2d0_resources[] = {
+        {
+                .start = MSM_IOMMU_GFX2D0_PHYS,
+                .end   = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
+                .end   = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device msm_root_iommu_dev = {
+        .name = "msm_iommu",
+        .id = -1,
+};
+
+static struct msm_iommu_dev jpegd_smmu = {
+        .name = "jpegd",
+        .clk_rate = -1
+};
+
+static struct msm_iommu_dev vpe_smmu = {
+        .name = "vpe"
+};
+
+static struct msm_iommu_dev mdp0_smmu = {
+        .name = "mdp0"
+};
+
+static struct msm_iommu_dev mdp1_smmu = {
+        .name = "mdp1"
+};
+
+static struct msm_iommu_dev rot_smmu = {
+        .name = "rot"
+};
+
+static struct msm_iommu_dev ijpeg_smmu = {
+        .name = "ijpeg"
+};
+
+static struct msm_iommu_dev vfe_smmu = {
+        .name = "vfe",
+        .clk_rate = -1
+};
+
+static struct msm_iommu_dev vcodec_a_smmu = {
+        .name = "vcodec_a"
+};
+
+static struct msm_iommu_dev vcodec_b_smmu = {
+        .name = "vcodec_b"
+};
+
+static struct msm_iommu_dev gfx3d_smmu = {
+        .name = "gfx3d",
+        .clk_rate = 27000000
+};
+
+static struct msm_iommu_dev gfx2d0_smmu = {
+        .name = "gfx2d0",
+        .clk_rate = 27000000
+};
+
+static struct platform_device msm_device_smmu_jpegd = {
+        .name = "msm_iommu",
+        .id = 0,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
+        .resource = msm_iommu_jpegd_resources,
+};
+
+static struct platform_device msm_device_smmu_vpe = {
+        .name = "msm_iommu",
+        .id = 1,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
+        .resource = msm_iommu_vpe_resources,
+};
+
+static struct platform_device msm_device_smmu_mdp0 = {
+        .name = "msm_iommu",
+        .id = 2,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
+        .resource = msm_iommu_mdp0_resources,
+};
+
+static struct platform_device msm_device_smmu_mdp1 = {
+        .name = "msm_iommu",
+        .id = 3,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
+        .resource = msm_iommu_mdp1_resources,
+};
+
+static struct platform_device msm_device_smmu_rot = {
+        .name = "msm_iommu",
+        .id = 4,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
+        .resource = msm_iommu_rot_resources,
+};
+
+static struct platform_device msm_device_smmu_ijpeg = {
+        .name = "msm_iommu",
+        .id = 5,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
+        .resource = msm_iommu_ijpeg_resources,
+};
+
+static struct platform_device msm_device_smmu_vfe = {
+        .name = "msm_iommu",
+        .id = 6,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
+        .resource = msm_iommu_vfe_resources,
+};
+
+static struct platform_device msm_device_smmu_vcodec_a = {
+        .name = "msm_iommu",
+        .id = 7,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
+        .resource = msm_iommu_vcodec_a_resources,
+};
+
+static struct platform_device msm_device_smmu_vcodec_b = {
+        .name = "msm_iommu",
+        .id = 8,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
+        .resource = msm_iommu_vcodec_b_resources,
+};
+
+static struct platform_device msm_device_smmu_gfx3d = {
+        .name = "msm_iommu",
+        .id = 9,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
+        .resource = msm_iommu_gfx3d_resources,
+};
+
+static struct platform_device msm_device_smmu_gfx2d0 = {
+        .name = "msm_iommu",
+        .id = 10,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
+        .resource = msm_iommu_gfx2d0_resources,
+};
+
+static struct msm_iommu_ctx_dev jpegd_src_ctx = {
+        .name = "jpegd_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
+        .name = "jpegd_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev vpe_src_ctx = {
+        .name = "vpe_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev vpe_dst_ctx = {
+        .name = "vpe_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
+        .name = "mdp_vg1",
+        .num = 0,
+        .mids = {0, 2, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
+        .name = "mdp_rgb1",
+        .num = 1,
+        .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
+        .name = "mdp_vg2",
+        .num = 0,
+        .mids = {0, 2, -1}
+};
+
+static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
+        .name = "mdp_rgb2",
+        .num = 1,
+        .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
+};
+
+static struct msm_iommu_ctx_dev rot_src_ctx = {
+        .name = "rot_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev rot_dst_ctx = {
+        .name = "rot_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
+        .name = "ijpeg_src",
+        .num = 0,
+        .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
+        .name = "ijpeg_dst",
+        .num = 1,
+        .mids = {1, -1}
+};
+
+static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
+        .name = "vfe_imgwr",
+        .num = 0,
+        .mids = {2, 3, 4, 5, 6, 7, 8, -1}
+};
+
+static struct msm_iommu_ctx_dev vfe_misc_ctx = {
+        .name = "vfe_misc",
+        .num = 1,
+        .mids = {0, 1, 9, -1}
+};
+
+static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
+        .name = "vcodec_a_stream",
+        .num = 0,
+        .mids = {2, 5, -1}
+};
+
+static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
+        .name = "vcodec_a_mm1",
+        .num = 1,
+        .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
+};
+
+static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
+        .name = "vcodec_b_mm2",
+        .num = 0,
+        .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
+        .name = "gfx3d_rbpa",
+        .num = 0,
+        .mids = {-1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
+        .name = "gfx3d_cpvgttc",
+        .num = 1,
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
+        .name = "gfx3d_smmu",
+        .num = 2,
+        .mids = {8, 9, 10, 11, 12, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
+        .name = "gfx2d0_pixv1_smmu",
+        .num = 0,
+        .mids = {0, 3, 4, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
+        .name = "gfx2d0_texv3_smmu",
+        .num = 1,
+        .mids = {1, 6, 7, -1}
+};
+
+static struct platform_device msm_device_jpegd_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 0,
+        .dev = {
+                .parent = &msm_device_smmu_jpegd.dev,
+        },
+};
+
+static struct platform_device msm_device_jpegd_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 1,
+        .dev = {
+                .parent = &msm_device_smmu_jpegd.dev,
+        },
+};
+
+static struct platform_device msm_device_vpe_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 2,
+        .dev = {
+                .parent = &msm_device_smmu_vpe.dev,
+        },
+};
+
+static struct platform_device msm_device_vpe_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 3,
+        .dev = {
+                .parent = &msm_device_smmu_vpe.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_vg1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 4,
+        .dev = {
+                .parent = &msm_device_smmu_mdp0.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_rgb1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 5,
+        .dev = {
+                .parent = &msm_device_smmu_mdp0.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_vg2_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 6,
+        .dev = {
+                .parent = &msm_device_smmu_mdp1.dev,
+        },
+};
+
+static struct platform_device msm_device_mdp_rgb2_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 7,
+        .dev = {
+                .parent = &msm_device_smmu_mdp1.dev,
+        },
+};
+
+static struct platform_device msm_device_rot_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 8,
+        .dev = {
+                .parent = &msm_device_smmu_rot.dev,
+        },
+};
+
+static struct platform_device msm_device_rot_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 9,
+        .dev = {
+                .parent = &msm_device_smmu_rot.dev,
+        },
+};
+
+static struct platform_device msm_device_ijpeg_src_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 10,
+        .dev = {
+                .parent = &msm_device_smmu_ijpeg.dev,
+        },
+};
+
+static struct platform_device msm_device_ijpeg_dst_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 11,
+        .dev = {
+                .parent = &msm_device_smmu_ijpeg.dev,
+        },
+};
+
+static struct platform_device msm_device_vfe_imgwr_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 12,
+        .dev = {
+                .parent = &msm_device_smmu_vfe.dev,
+        },
+};
+
+static struct platform_device msm_device_vfe_misc_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 13,
+        .dev = {
+                .parent = &msm_device_smmu_vfe.dev,
+        },
+};
+
+static struct platform_device msm_device_vcodec_a_stream_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 14,
+        .dev = {
+                .parent = &msm_device_smmu_vcodec_a.dev,
+        },
+};
+
+static struct platform_device msm_device_vcodec_a_mm1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 15,
+        .dev = {
+                .parent = &msm_device_smmu_vcodec_a.dev,
+        },
+};
+
+static struct platform_device msm_device_vcodec_b_mm2_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 16,
+        .dev = {
+                .parent = &msm_device_smmu_vcodec_b.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx3d_rbpa_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 17,
+        .dev = {
+                .parent = &msm_device_smmu_gfx3d.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 18,
+        .dev = {
+                .parent = &msm_device_smmu_gfx3d.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx3d_smmu_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 19,
+        .dev = {
+                .parent = &msm_device_smmu_gfx3d.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 20,
+        .dev = {
+                .parent = &msm_device_smmu_gfx2d0.dev,
+        },
+};
+
+static struct platform_device msm_device_gfx2d0_texv3_ctx = {
+        .name = "msm_iommu_ctx",
+        .id = 21,
+        .dev = {
+                .parent = &msm_device_smmu_gfx2d0.dev,
+        },
+};
+
+static struct platform_device *msm_iommu_devs[] = {
+        &msm_device_smmu_jpegd,
+        &msm_device_smmu_vpe,
+        &msm_device_smmu_mdp0,
+        &msm_device_smmu_mdp1,
+        &msm_device_smmu_rot,
+        &msm_device_smmu_ijpeg,
+        &msm_device_smmu_vfe,
+        &msm_device_smmu_vcodec_a,
+        &msm_device_smmu_vcodec_b,
+        &msm_device_smmu_gfx3d,
+        &msm_device_smmu_gfx2d0,
+};
+
+static struct msm_iommu_dev *msm_iommu_data[] = {
+        &jpegd_smmu,
+        &vpe_smmu,
+        &mdp0_smmu,
+        &mdp1_smmu,
+        &rot_smmu,
+        &ijpeg_smmu,
+        &vfe_smmu,
+        &vcodec_a_smmu,
+        &vcodec_b_smmu,
+        &gfx3d_smmu,
+        &gfx2d0_smmu,
+};
+
+static struct platform_device *msm_iommu_ctx_devs[] = {
+        &msm_device_jpegd_src_ctx,
+        &msm_device_jpegd_dst_ctx,
+        &msm_device_vpe_src_ctx,
+        &msm_device_vpe_dst_ctx,
+        &msm_device_mdp_vg1_ctx,
+        &msm_device_mdp_rgb1_ctx,
+        &msm_device_mdp_vg2_ctx,
+        &msm_device_mdp_rgb2_ctx,
+        &msm_device_rot_src_ctx,
+        &msm_device_rot_dst_ctx,
+        &msm_device_ijpeg_src_ctx,
+        &msm_device_ijpeg_dst_ctx,
+        &msm_device_vfe_imgwr_ctx,
+        &msm_device_vfe_misc_ctx,
+        &msm_device_vcodec_a_stream_ctx,
+        &msm_device_vcodec_a_mm1_ctx,
+        &msm_device_vcodec_b_mm2_ctx,
+        &msm_device_gfx3d_rbpa_ctx,
+        &msm_device_gfx3d_cpvgttc_ctx,
+        &msm_device_gfx3d_smmu_ctx,
+        &msm_device_gfx2d0_pixv1_ctx,
+        &msm_device_gfx2d0_texv3_ctx,
+};
+
+static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
+        &jpegd_src_ctx,
+        &jpegd_dst_ctx,
+        &vpe_src_ctx,
+        &vpe_dst_ctx,
+        &mdp_vg1_ctx,
+        &mdp_rgb1_ctx,
+        &mdp_vg2_ctx,
+        &mdp_rgb2_ctx,
+        &rot_src_ctx,
+        &rot_dst_ctx,
+        &ijpeg_src_ctx,
+        &ijpeg_dst_ctx,
+        &vfe_imgwr_ctx,
+        &vfe_misc_ctx,
+        &vcodec_a_stream_ctx,
+        &vcodec_a_mm1_ctx,
+        &vcodec_b_mm2_ctx,
+        &gfx3d_rbpa_ctx,
+        &gfx3d_cpvgttc_ctx,
+        &gfx3d_smmu_ctx,
+        &gfx2d0_pixv1_ctx,
+        &gfx2d0_texv3_ctx,
+};
+
+static int msm8x60_iommu_init(void)
+{
+        int ret, i;
+
+        ret = platform_device_register(&msm_root_iommu_dev);
+        if (ret != 0) {
+                pr_err("Failed to register root IOMMU device!\n");
+                goto failure;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
+                ret = platform_device_add_data(msm_iommu_devs[i],
+                                               msm_iommu_data[i],
+                                               sizeof(struct msm_iommu_dev));
+                if (ret != 0) {
+                        pr_err("platform_device_add_data failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind;
+                }
+
+                ret = platform_device_register(msm_iommu_devs[i]);
+
+                if (ret != 0) {
+                        pr_err("platform_device_register smmu failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind;
+                }
+        }
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
+                ret = platform_device_add_data(msm_iommu_ctx_devs[i],
+                                               msm_iommu_ctx_data[i],
+                                               sizeof(*msm_iommu_ctx_devs[i]));
+                if (ret != 0) {
+                        pr_err("platform_device_add_data smmu failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind2;
+                }
+
+                ret = platform_device_register(msm_iommu_ctx_devs[i]);
+                if (ret != 0) {
+                        pr_err("platform_device_register ctx failed, "
+                               "i = %d\n", i);
+                        goto failure_unwind2;
+                }
+        }
+        return 0;
+
+failure_unwind2:
+        while (--i >= 0)
+                platform_device_unregister(msm_iommu_ctx_devs[i]);
+failure_unwind:
+        while (--i >= 0)
+                platform_device_unregister(msm_iommu_devs[i]);
+
+        platform_device_unregister(&msm_root_iommu_dev);
+failure:
+        return ret;
+}
+
+static void msm8x60_iommu_exit(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
+                platform_device_unregister(msm_iommu_ctx_devs[i]);
+
+        for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
+                platform_device_unregister(msm_iommu_devs[i]);
+
+        platform_device_unregister(&msm_root_iommu_dev);
+}
+
+subsys_initcall(msm8x60_iommu_init);
+module_exit(msm8x60_iommu_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 4d4a50785e3..6fe67c5d1ae 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -48,6 +48,11 @@ struct platform_device msm_device_uart3 = {
         .resource       = resources_uart3,
 };
 
+struct platform_device msm_device_smd = {
+        .name   = "msm_smd",
+        .id     = -1,
+};
+
 struct clk msm_clocks_8x50[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index bc32c845c7b..33051b509e8 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-msm/gpio.c
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -14,72 +14,363 @@
  *
  */
 
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/module.h>
-#include <mach/gpio.h>
-#include "proc_comm.h"
-
-int gpio_tlmm_config(unsigned config, unsigned disable)
-{
-        return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
-}
-EXPORT_SYMBOL(gpio_tlmm_config);
-
-int msm_gpios_enable(const struct msm_gpio *table, int size)
-{
-        int rc;
-        int i;
-        const struct msm_gpio *g;
-        for (i = 0; i < size; i++) {
-                g = table + i;
-                rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
-                if (rc) {
-                        pr_err("gpio_tlmm_config(0x%08x, GPIO_ENABLE)"
-                               " <%s> failed: %d\n",
-                               g->gpio_cfg, g->label ?: "?", rc);
-                        pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
-                               GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
-                               GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
-                               GPIO_DRVSTR(g->gpio_cfg));
-                        goto err;
-                }
+#include "gpio_hw.h"
+#include "gpiomux.h"
+
+#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
+
+#define MSM_GPIO_BANK(bank, first, last)                                \
+        {                                                               \
+                .regs = {                                               \
+                        .out =         MSM_GPIO_OUT_##bank,             \
+                        .in =          MSM_GPIO_IN_##bank,              \
+                        .int_status =  MSM_GPIO_INT_STATUS_##bank,      \
+                        .int_clear =   MSM_GPIO_INT_CLEAR_##bank,       \
+                        .int_en =      MSM_GPIO_INT_EN_##bank,          \
+                        .int_edge =    MSM_GPIO_INT_EDGE_##bank,        \
+                        .int_pos =     MSM_GPIO_INT_POS_##bank,         \
+                        .oe =          MSM_GPIO_OE_##bank,              \
+                },                                                      \
+                .chip = {                                               \
+                        .base = (first),                                \
+                        .ngpio = (last) - (first) + 1,                  \
+                        .get = msm_gpio_get,                            \
+                        .set = msm_gpio_set,                            \
+                        .direction_input = msm_gpio_direction_input,    \
+                        .direction_output = msm_gpio_direction_output,  \
+                        .to_irq = msm_gpio_to_irq,                      \
+                        .request = msm_gpio_request,                    \
+                        .free = msm_gpio_free,                          \
+                }                                                       \
         }
+
+#define MSM_GPIO_BROKEN_INT_CLEAR 1
+
+struct msm_gpio_regs {
+        void __iomem *out;
+        void __iomem *in;
+        void __iomem *int_status;
+        void __iomem *int_clear;
+        void __iomem *int_en;
+        void __iomem *int_edge;
+        void __iomem *int_pos;
+        void __iomem *oe;
+};
+
+struct msm_gpio_chip {
+        spinlock_t              lock;
+        struct gpio_chip        chip;
+        struct msm_gpio_regs    regs;
+#if MSM_GPIO_BROKEN_INT_CLEAR
+        unsigned                int_status_copy;
+#endif
+        unsigned int            both_edge_detect;
+        unsigned int            int_enable[2]; /* 0: awake, 1: sleep */
+};
+
+static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
+                          unsigned offset, unsigned on)
+{
+        unsigned mask = BIT(offset);
+        unsigned val;
+
+        val = readl(msm_chip->regs.out);
+        if (on)
+                writel(val | mask, msm_chip->regs.out);
+        else
+                writel(val & ~mask, msm_chip->regs.out);
         return 0;
-err:
-        msm_gpios_disable(table, i);
-        return rc;
-}
-EXPORT_SYMBOL(msm_gpios_enable);
-
-void msm_gpios_disable(const struct msm_gpio *table, int size)
-{
-        int rc;
-        int i;
-        const struct msm_gpio *g;
-        for (i = size-1; i >= 0; i--) {
-                g = table + i;
-                rc = gpio_tlmm_config(g->gpio_cfg, GPIO_DISABLE);
-                if (rc) {
-                        pr_err("gpio_tlmm_config(0x%08x, GPIO_DISABLE)"
-                               " <%s> failed: %d\n",
-                               g->gpio_cfg, g->label ?: "?", rc);
-                        pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
-                               GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
-                               GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
-                               GPIO_DRVSTR(g->gpio_cfg));
-                }
+}
+
+static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
+{
+        int loop_limit = 100;
+        unsigned pol, val, val2, intstat;
+        do {
+                val = readl(msm_chip->regs.in);
+                pol = readl(msm_chip->regs.int_pos);
+                pol = (pol & ~msm_chip->both_edge_detect) |
+                      (~val & msm_chip->both_edge_detect);
+                writel(pol, msm_chip->regs.int_pos);
+                intstat = readl(msm_chip->regs.int_status);
+                val2 = readl(msm_chip->regs.in);
+                if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
+                        return;
+        } while (loop_limit-- > 0);
+        printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
+               "failed to reach stable state %x != %x\n", val, val2);
+}
+
+static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
+                                        unsigned offset)
+{
+        unsigned bit = BIT(offset);
+
+#if MSM_GPIO_BROKEN_INT_CLEAR
+        /* Save interrupts that already triggered before we loose them. */
+        /* Any interrupt that triggers between the read of int_status */
+        /* and the write to int_clear will still be lost though. */
+        msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
+        msm_chip->int_status_copy &= ~bit;
+#endif
+        writel(bit, msm_chip->regs.int_clear);
+        msm_gpio_update_both_edge_detect(msm_chip);
+        return 0;
+}
+
+static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_chip;
+        unsigned long irq_flags;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
+}
+
+static int
+msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct msm_gpio_chip *msm_chip;
+        unsigned long irq_flags;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        msm_gpio_write(msm_chip, offset, value);
+        writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
+}
+
+static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_chip;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
+}
+
+static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct msm_gpio_chip *msm_chip;
+        unsigned long irq_flags;
+
+        msm_chip = container_of(chip, struct msm_gpio_chip, chip);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        msm_gpio_write(msm_chip, offset, value);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return MSM_GPIO_TO_INT(chip->base + offset);
+}
+
+#ifdef CONFIG_MSM_GPIOMUX
+static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return msm_gpiomux_get(chip->base + offset);
+}
+
+static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        msm_gpiomux_put(chip->base + offset);
+}
+#else
+#define msm_gpio_request NULL
+#define msm_gpio_free NULL
+#endif
+
+struct msm_gpio_chip msm_gpio_chips[] = {
+#if defined(CONFIG_ARCH_MSM7X00A)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(5, 107, 121),
+#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(5, 107, 132),
+#elif defined(CONFIG_ARCH_MSM7X30)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  43),
+        MSM_GPIO_BANK(2,  44,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 106),
+        MSM_GPIO_BANK(5, 107, 133),
+        MSM_GPIO_BANK(6, 134, 150),
+        MSM_GPIO_BANK(7, 151, 181),
+#elif defined(CONFIG_ARCH_QSD8X50)
+        MSM_GPIO_BANK(0,   0,  15),
+        MSM_GPIO_BANK(1,  16,  42),
+        MSM_GPIO_BANK(2,  43,  67),
+        MSM_GPIO_BANK(3,  68,  94),
+        MSM_GPIO_BANK(4,  95, 103),
+        MSM_GPIO_BANK(5, 104, 121),
+        MSM_GPIO_BANK(6, 122, 152),
+        MSM_GPIO_BANK(7, 153, 164),
+#endif
+};
+
+static void msm_gpio_irq_ack(unsigned int irq)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        msm_gpio_clear_detect_status(msm_chip,
+                                     irq - gpio_to_irq(msm_chip->chip.base));
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static void msm_gpio_irq_mask(unsigned int irq)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        /* level triggered interrupts are also latched */
+        if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
+                msm_gpio_clear_detect_status(msm_chip, offset);
+        msm_chip->int_enable[0] &= ~BIT(offset);
+        writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static void msm_gpio_irq_unmask(unsigned int irq)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        /* level triggered interrupts are also latched */
+        if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
+                msm_gpio_clear_detect_status(msm_chip, offset);
+        msm_chip->int_enable[0] |= BIT(offset);
+        writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+}
+
+static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+
+        if (on)
+                msm_chip->int_enable[1] |= BIT(offset);
+        else
+                msm_chip->int_enable[1] &= ~BIT(offset);
+
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
+}
+
+static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+        unsigned long irq_flags;
+        struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
+        unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
+        unsigned val, mask = BIT(offset);
+
+        spin_lock_irqsave(&msm_chip->lock, irq_flags);
+        val = readl(msm_chip->regs.int_edge);
+        if (flow_type & IRQ_TYPE_EDGE_BOTH) {
+                writel(val | mask, msm_chip->regs.int_edge);
+                irq_desc[irq].handle_irq = handle_edge_irq;
+        } else {
+                writel(val & ~mask, msm_chip->regs.int_edge);
+                irq_desc[irq].handle_irq = handle_level_irq;
+        }
+        if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+                msm_chip->both_edge_detect |= mask;
+                msm_gpio_update_both_edge_detect(msm_chip);
+        } else {
+                msm_chip->both_edge_detect &= ~mask;
+                val = readl(msm_chip->regs.int_pos);
+                if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
+                        writel(val | mask, msm_chip->regs.int_pos);
+                else
+                        writel(val & ~mask, msm_chip->regs.int_pos);
         }
+        spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
+        return 0;
 }
-EXPORT_SYMBOL(msm_gpios_disable);
 
-int msm_gpios_request_enable(const struct msm_gpio *table, int size)
+static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        int rc = msm_gpios_enable(table, size);
-        return rc;
+        int i, j, mask;
+        unsigned val;
+
+        for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
+                struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
+                val = readl(msm_chip->regs.int_status);
+                val &= msm_chip->int_enable[0];
+                while (val) {
+                        mask = val & -val;
+                        j = fls(mask) - 1;
+                        /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
+                                __func__, v, m, j, msm_chip->chip.start + j,
+                                FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
+                        val &= ~mask;
+                        generic_handle_irq(FIRST_GPIO_IRQ +
+                                           msm_chip->chip.base + j);
+                }
+        }
+        desc->chip->ack(irq);
 }
-EXPORT_SYMBOL(msm_gpios_request_enable);
 
-void msm_gpios_disable_free(const struct msm_gpio *table, int size)
+static struct irq_chip msm_gpio_irq_chip = {
+        .name      = "msmgpio",
+        .ack       = msm_gpio_irq_ack,
+        .mask      = msm_gpio_irq_mask,
+        .unmask    = msm_gpio_irq_unmask,
+        .set_wake  = msm_gpio_irq_set_wake,
+        .set_type  = msm_gpio_irq_set_type,
+};
+
+static int __init msm_init_gpio(void)
 {
-        msm_gpios_disable(table, size);
+        int i, j = 0;
+
+        for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
+                if (i - FIRST_GPIO_IRQ >=
+                        msm_gpio_chips[j].chip.base +
+                        msm_gpio_chips[j].chip.ngpio)
+                        j++;
+                set_irq_chip_data(i, &msm_gpio_chips[j]);
+                set_irq_chip(i, &msm_gpio_irq_chip);
+                set_irq_handler(i, handle_edge_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+
+        for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
+                spin_lock_init(&msm_gpio_chips[i].lock);
+                writel(0, msm_gpio_chips[i].regs.int_en);
+                gpiochip_add(&msm_gpio_chips[i].chip);
+        }
+
+        set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
+        set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
+        set_irq_wake(INT_GPIO_GROUP1, 1);
+        set_irq_wake(INT_GPIO_GROUP2, 2);
+        return 0;
 }
-EXPORT_SYMBOL(msm_gpios_disable_free);
+
+postcore_initcall(msm_init_gpio);
diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h
new file mode 100644
index 00000000000..6b5066038ba
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw.h
@@ -0,0 +1,278 @@
+/* arch/arm/mach-msm/gpio_hw.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
+
+#include <mach/msm_iomap.h>
+
+/* see 80-VA736-2 Rev C pp 695-751
+**
+** These are actually the *shadow* gpio registers, since the
+** real ones (which allow full access) are only available to the
+** ARM9 side of the world.
+**
+** Since the _BASE need to be page-aligned when we're mapping them
+** to virtual addresses, adjust for the additional offset in these
+** macros.
+*/
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
+#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
+#else
+#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+#endif
+
+#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
+    defined(CONFIG_ARCH_MSM7X27)
+
+/* output value */
+#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)  /* gpio  15-0  */
+#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)  /* gpio  42-16 */
+#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)  /* gpio  67-43 */
+#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)  /* gpio  94-68 */
+#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)  /* gpio 106-95 */
+#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x50)  /* gpio 107-121 */
+
+/* same pin map as above, output enable */
+#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x10)
+#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)
+#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x14)
+#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x18)
+#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x1C)
+#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x54)
+
+/* same pin map as above, input read */
+#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x34)
+#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)
+#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x38)
+#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x3C)
+#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x40)
+#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x44)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x60)
+#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)
+#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x64)
+#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x68)
+#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x6C)
+#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0xC0)
+
+/* same pin map as above, 1=positive 0=negative */
+#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x70)
+#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)
+#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x74)
+#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x78)
+#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x7C)
+#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xBC)
+
+/* same pin map as above, interrupt enable */
+#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0x80)
+#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)
+#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0x84)
+#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0x88)
+#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0x8C)
+#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xB8)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0x90)
+#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)
+#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0x94)
+#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0x98)
+#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0x9C)
+#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xB4)
+
+/* same pin map as above, 1=interrupt pending */
+#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xA0)
+#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)
+#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xA4)
+#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xA8)
+#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xAC)
+#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0xB0)
+
+#endif
+
+#if defined(CONFIG_ARCH_QSD8X50)
+/* output value */
+#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)  /* gpio  15-0   */
+#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)  /* gpio  42-16  */
+#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)  /* gpio  67-43  */
+#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)  /* gpio  94-68  */
+#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)  /* gpio 103-95  */
+#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x10)  /* gpio 121-104 */
+#define MSM_GPIO_OUT_6         MSM_GPIO1_REG(0x14)  /* gpio 152-122 */
+#define MSM_GPIO_OUT_7         MSM_GPIO1_REG(0x18)  /* gpio 164-153 */
+
+/* same pin map as above, output enable */
+#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x20)
+#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)
+#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x24)
+#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x28)
+#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x2C)
+#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x30)
+#define MSM_GPIO_OE_6          MSM_GPIO1_REG(0x34)
+#define MSM_GPIO_OE_7          MSM_GPIO1_REG(0x38)
+
+/* same pin map as above, input read */
+#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x50)
+#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)
+#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x54)
+#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x58)
+#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x5C)
+#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x60)
+#define MSM_GPIO_IN_6          MSM_GPIO1_REG(0x64)
+#define MSM_GPIO_IN_7          MSM_GPIO1_REG(0x68)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x70)
+#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)
+#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x74)
+#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x78)
+#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x7C)
+#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0x80)
+#define MSM_GPIO_INT_EDGE_6    MSM_GPIO1_REG(0x84)
+#define MSM_GPIO_INT_EDGE_7    MSM_GPIO1_REG(0x88)
+
+/* same pin map as above, 1=positive 0=negative */
+#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x90)
+#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)
+#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x94)
+#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x98)
+#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x9C)
+#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xA0)
+#define MSM_GPIO_INT_POS_6     MSM_GPIO1_REG(0xA4)
+#define MSM_GPIO_INT_POS_7     MSM_GPIO1_REG(0xA8)
+
+/* same pin map as above, interrupt enable */
+#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0xB0)
+#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)
+#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0xB4)
+#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0xB8)
+#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0xBC)
+#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xC0)
+#define MSM_GPIO_INT_EN_6      MSM_GPIO1_REG(0xC4)
+#define MSM_GPIO_INT_EN_7      MSM_GPIO1_REG(0xC8)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0xD0)
+#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)
+#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0xD4)
+#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0xD8)
+#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0xDC)
+#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xE0)
+#define MSM_GPIO_INT_CLEAR_6   MSM_GPIO1_REG(0xE4)
+#define MSM_GPIO_INT_CLEAR_7   MSM_GPIO1_REG(0xE8)
+
+/* same pin map as above, 1=interrupt pending */
+#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xF0)
+#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)
+#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xF4)
+#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xF8)
+#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xFC)
+#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0x100)
+#define MSM_GPIO_INT_STATUS_6  MSM_GPIO1_REG(0x104)
+#define MSM_GPIO_INT_STATUS_7  MSM_GPIO1_REG(0x108)
+
+#endif
+
+#if defined(CONFIG_ARCH_MSM7X30)
+
+/* output value */
+#define MSM_GPIO_OUT_0         MSM_GPIO1_REG(0x00)   /* gpio  15-0   */
+#define MSM_GPIO_OUT_1         MSM_GPIO2_REG(0x00)   /* gpio  43-16  */
+#define MSM_GPIO_OUT_2         MSM_GPIO1_REG(0x04)   /* gpio  67-44  */
+#define MSM_GPIO_OUT_3         MSM_GPIO1_REG(0x08)   /* gpio  94-68  */
+#define MSM_GPIO_OUT_4         MSM_GPIO1_REG(0x0C)   /* gpio 106-95  */
+#define MSM_GPIO_OUT_5         MSM_GPIO1_REG(0x50)   /* gpio 133-107 */
+#define MSM_GPIO_OUT_6         MSM_GPIO1_REG(0xC4)   /* gpio 150-134 */
+#define MSM_GPIO_OUT_7         MSM_GPIO1_REG(0x214)  /* gpio 181-151 */
+
+/* same pin map as above, output enable */
+#define MSM_GPIO_OE_0          MSM_GPIO1_REG(0x10)
+#define MSM_GPIO_OE_1          MSM_GPIO2_REG(0x08)
+#define MSM_GPIO_OE_2          MSM_GPIO1_REG(0x14)
+#define MSM_GPIO_OE_3          MSM_GPIO1_REG(0x18)
+#define MSM_GPIO_OE_4          MSM_GPIO1_REG(0x1C)
+#define MSM_GPIO_OE_5          MSM_GPIO1_REG(0x54)
+#define MSM_GPIO_OE_6          MSM_GPIO1_REG(0xC8)
+#define MSM_GPIO_OE_7          MSM_GPIO1_REG(0x218)
+
+/* same pin map as above, input read */
+#define MSM_GPIO_IN_0          MSM_GPIO1_REG(0x34)
+#define MSM_GPIO_IN_1          MSM_GPIO2_REG(0x20)
+#define MSM_GPIO_IN_2          MSM_GPIO1_REG(0x38)
+#define MSM_GPIO_IN_3          MSM_GPIO1_REG(0x3C)
+#define MSM_GPIO_IN_4          MSM_GPIO1_REG(0x40)
+#define MSM_GPIO_IN_5          MSM_GPIO1_REG(0x44)
+#define MSM_GPIO_IN_6          MSM_GPIO1_REG(0xCC)
+#define MSM_GPIO_IN_7          MSM_GPIO1_REG(0x21C)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define MSM_GPIO_INT_EDGE_0    MSM_GPIO1_REG(0x60)
+#define MSM_GPIO_INT_EDGE_1    MSM_GPIO2_REG(0x50)
+#define MSM_GPIO_INT_EDGE_2    MSM_GPIO1_REG(0x64)
+#define MSM_GPIO_INT_EDGE_3    MSM_GPIO1_REG(0x68)
+#define MSM_GPIO_INT_EDGE_4    MSM_GPIO1_REG(0x6C)
+#define MSM_GPIO_INT_EDGE_5    MSM_GPIO1_REG(0xC0)
+#define MSM_GPIO_INT_EDGE_6    MSM_GPIO1_REG(0xD0)
+#define MSM_GPIO_INT_EDGE_7    MSM_GPIO1_REG(0x240)
+
+/* same pin map as above, 1=positive 0=negative */
+#define MSM_GPIO_INT_POS_0     MSM_GPIO1_REG(0x70)
+#define MSM_GPIO_INT_POS_1     MSM_GPIO2_REG(0x58)
+#define MSM_GPIO_INT_POS_2     MSM_GPIO1_REG(0x74)
+#define MSM_GPIO_INT_POS_3     MSM_GPIO1_REG(0x78)
+#define MSM_GPIO_INT_POS_4     MSM_GPIO1_REG(0x7C)
+#define MSM_GPIO_INT_POS_5     MSM_GPIO1_REG(0xBC)
+#define MSM_GPIO_INT_POS_6     MSM_GPIO1_REG(0xD4)
+#define MSM_GPIO_INT_POS_7     MSM_GPIO1_REG(0x228)
+
+/* same pin map as above, interrupt enable */
+#define MSM_GPIO_INT_EN_0      MSM_GPIO1_REG(0x80)
+#define MSM_GPIO_INT_EN_1      MSM_GPIO2_REG(0x60)
+#define MSM_GPIO_INT_EN_2      MSM_GPIO1_REG(0x84)
+#define MSM_GPIO_INT_EN_3      MSM_GPIO1_REG(0x88)
+#define MSM_GPIO_INT_EN_4      MSM_GPIO1_REG(0x8C)
+#define MSM_GPIO_INT_EN_5      MSM_GPIO1_REG(0xB8)
+#define MSM_GPIO_INT_EN_6      MSM_GPIO1_REG(0xD8)
+#define MSM_GPIO_INT_EN_7      MSM_GPIO1_REG(0x22C)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define MSM_GPIO_INT_CLEAR_0   MSM_GPIO1_REG(0x90)
+#define MSM_GPIO_INT_CLEAR_1   MSM_GPIO2_REG(0x68)
+#define MSM_GPIO_INT_CLEAR_2   MSM_GPIO1_REG(0x94)
+#define MSM_GPIO_INT_CLEAR_3   MSM_GPIO1_REG(0x98)
+#define MSM_GPIO_INT_CLEAR_4   MSM_GPIO1_REG(0x9C)
+#define MSM_GPIO_INT_CLEAR_5   MSM_GPIO1_REG(0xB4)
+#define MSM_GPIO_INT_CLEAR_6   MSM_GPIO1_REG(0xDC)
+#define MSM_GPIO_INT_CLEAR_7   MSM_GPIO1_REG(0x230)
+
+/* same pin map as above, 1=interrupt pending */
+#define MSM_GPIO_INT_STATUS_0  MSM_GPIO1_REG(0xA0)
+#define MSM_GPIO_INT_STATUS_1  MSM_GPIO2_REG(0x70)
+#define MSM_GPIO_INT_STATUS_2  MSM_GPIO1_REG(0xA4)
+#define MSM_GPIO_INT_STATUS_3  MSM_GPIO1_REG(0xA8)
+#define MSM_GPIO_INT_STATUS_4  MSM_GPIO1_REG(0xAC)
+#define MSM_GPIO_INT_STATUS_5  MSM_GPIO1_REG(0xB0)
+#define MSM_GPIO_INT_STATUS_6  MSM_GPIO1_REG(0xE0)
+#define MSM_GPIO_INT_STATUS_7  MSM_GPIO1_REG(0x234)
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c
new file mode 100644
index 00000000000..6ce41c5241a
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-7x30.c
@@ -0,0 +1,38 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include "gpiomux.h"
+
+struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
+#ifdef CONFIG_SERIAL_MSM_CONSOLE
+        [49] = { /* UART2 RFR */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [50] = { /* UART2 CTS */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [51] = { /* UART2 RX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+        [52] = { /* UART2 TX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_2 | GPIOMUX_VALID,
+        },
+#endif
+};
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
new file mode 100644
index 00000000000..4406e0f4ae9
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-8x50.c
@@ -0,0 +1,28 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include "gpiomux.h"
+
+struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
+        [86] = { /* UART3 RX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_1 | GPIOMUX_VALID,
+        },
+        [87] = { /* UART3 TX */
+                .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
+                             GPIOMUX_FUNC_1 | GPIOMUX_VALID,
+        },
+};
diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm/mach-msm/gpiomux-8x60.c
new file mode 100644
index 00000000000..7b380b31bd0
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-8x60.c
@@ -0,0 +1,19 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include "gpiomux.h"
+
+struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
diff --git a/arch/arm/mach-msm/gpiomux-v1.c b/arch/arm/mach-msm/gpiomux-v1.c
new file mode 100644
index 00000000000..27de2abd714
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v1.c
@@ -0,0 +1,33 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/kernel.h>
+#include "gpiomux.h"
+#include "proc_comm.h"
+
+void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
+{
+        unsigned tlmm_config  = (val & ~GPIOMUX_CTL_MASK) |
+                                ((gpio & 0x3ff) << 4);
+        unsigned tlmm_disable = 0;
+        int rc;
+
+        rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
+                           &tlmm_config, &tlmm_disable);
+        if (rc)
+                pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
+                       __func__, rc, tlmm_config, tlmm_disable);
+}
diff --git a/arch/arm/mach-msm/gpiomux-v1.h b/arch/arm/mach-msm/gpiomux-v1.h
new file mode 100644
index 00000000000..71d86feba45
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v1.h
@@ -0,0 +1,67 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
+#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define GPIOMUX_NGPIOS 182
+#elif defined(CONFIG_ARCH_QSD8X50)
+#define GPIOMUX_NGPIOS 165
+#else
+#define GPIOMUX_NGPIOS 133
+#endif
+
+typedef u32 gpiomux_config_t;
+
+enum {
+        GPIOMUX_DRV_2MA  = 0UL << 17,
+        GPIOMUX_DRV_4MA  = 1UL << 17,
+        GPIOMUX_DRV_6MA  = 2UL << 17,
+        GPIOMUX_DRV_8MA  = 3UL << 17,
+        GPIOMUX_DRV_10MA = 4UL << 17,
+        GPIOMUX_DRV_12MA = 5UL << 17,
+        GPIOMUX_DRV_14MA = 6UL << 17,
+        GPIOMUX_DRV_16MA = 7UL << 17,
+};
+
+enum {
+        GPIOMUX_FUNC_GPIO = 0UL,
+        GPIOMUX_FUNC_1    = 1UL,
+        GPIOMUX_FUNC_2    = 2UL,
+        GPIOMUX_FUNC_3    = 3UL,
+        GPIOMUX_FUNC_4    = 4UL,
+        GPIOMUX_FUNC_5    = 5UL,
+        GPIOMUX_FUNC_6    = 6UL,
+        GPIOMUX_FUNC_7    = 7UL,
+        GPIOMUX_FUNC_8    = 8UL,
+        GPIOMUX_FUNC_9    = 9UL,
+        GPIOMUX_FUNC_A    = 10UL,
+        GPIOMUX_FUNC_B    = 11UL,
+        GPIOMUX_FUNC_C    = 12UL,
+        GPIOMUX_FUNC_D    = 13UL,
+        GPIOMUX_FUNC_E    = 14UL,
+        GPIOMUX_FUNC_F    = 15UL,
+};
+
+enum {
+        GPIOMUX_PULL_NONE   = 0UL << 15,
+        GPIOMUX_PULL_DOWN   = 1UL << 15,
+        GPIOMUX_PULL_KEEPER = 2UL << 15,
+        GPIOMUX_PULL_UP     = 3UL << 15,
+};
+
+#endif
diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c
new file mode 100644
index 00000000000..273396d2b12
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v2.c
@@ -0,0 +1,25 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/io.h>
+#include <mach/msm_iomap.h>
+#include "gpiomux.h"
+
+void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
+{
+        writel(val & ~GPIOMUX_CTL_MASK,
+               MSM_TLMM_BASE + 0x1000 + (0x10 * gpio));
+}
diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h
new file mode 100644
index 00000000000..3bf10e7f038
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v2.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
+#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
+
+#define GPIOMUX_NGPIOS 173
+
+typedef u16 gpiomux_config_t;
+
+enum {
+        GPIOMUX_DRV_2MA  = 0UL << 6,
+        GPIOMUX_DRV_4MA  = 1UL << 6,
+        GPIOMUX_DRV_6MA  = 2UL << 6,
+        GPIOMUX_DRV_8MA  = 3UL << 6,
+        GPIOMUX_DRV_10MA = 4UL << 6,
+        GPIOMUX_DRV_12MA = 5UL << 6,
+        GPIOMUX_DRV_14MA = 6UL << 6,
+        GPIOMUX_DRV_16MA = 7UL << 6,
+};
+
+enum {
+        GPIOMUX_FUNC_GPIO = 0UL  << 2,
+        GPIOMUX_FUNC_1    = 1UL  << 2,
+        GPIOMUX_FUNC_2    = 2UL  << 2,
+        GPIOMUX_FUNC_3    = 3UL  << 2,
+        GPIOMUX_FUNC_4    = 4UL  << 2,
+        GPIOMUX_FUNC_5    = 5UL  << 2,
+        GPIOMUX_FUNC_6    = 6UL  << 2,
+        GPIOMUX_FUNC_7    = 7UL  << 2,
+        GPIOMUX_FUNC_8    = 8UL  << 2,
+        GPIOMUX_FUNC_9    = 9UL  << 2,
+        GPIOMUX_FUNC_A    = 10UL << 2,
+        GPIOMUX_FUNC_B    = 11UL << 2,
+        GPIOMUX_FUNC_C    = 12UL << 2,
+        GPIOMUX_FUNC_D    = 13UL << 2,
+        GPIOMUX_FUNC_E    = 14UL << 2,
+        GPIOMUX_FUNC_F    = 15UL << 2,
+};
+
+enum {
+        GPIOMUX_PULL_NONE   = 0UL,
+        GPIOMUX_PULL_DOWN   = 1UL,
+        GPIOMUX_PULL_KEEPER = 2UL,
+        GPIOMUX_PULL_UP     = 3UL,
+};
+
+#endif
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c
new file mode 100644
index 00000000000..53af21abd15
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux.c
@@ -0,0 +1,96 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include "gpiomux.h"
+
+static DEFINE_SPINLOCK(gpiomux_lock);
+
+int msm_gpiomux_write(unsigned gpio,
+                      gpiomux_config_t active,
+                      gpiomux_config_t suspended)
+{
+        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
+        unsigned long irq_flags;
+        gpiomux_config_t setting;
+
+        if (gpio >= GPIOMUX_NGPIOS)
+                return -EINVAL;
+
+        spin_lock_irqsave(&gpiomux_lock, irq_flags);
+
+        if (active & GPIOMUX_VALID)
+                cfg->active = active;
+
+        if (suspended & GPIOMUX_VALID)
+                cfg->suspended = suspended;
+
+        setting = cfg->ref ? active : suspended;
+        if (setting & GPIOMUX_VALID)
+                __msm_gpiomux_write(gpio, setting);
+
+        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
+        return 0;
+}
+EXPORT_SYMBOL(msm_gpiomux_write);
+
+int msm_gpiomux_get(unsigned gpio)
+{
+        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
+        unsigned long irq_flags;
+
+        if (gpio >= GPIOMUX_NGPIOS)
+                return -EINVAL;
+
+        spin_lock_irqsave(&gpiomux_lock, irq_flags);
+        if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID)
+                __msm_gpiomux_write(gpio, cfg->active);
+        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
+        return 0;
+}
+EXPORT_SYMBOL(msm_gpiomux_get);
+
+int msm_gpiomux_put(unsigned gpio)
+{
+        struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
+        unsigned long irq_flags;
+
+        if (gpio >= GPIOMUX_NGPIOS)
+                return -EINVAL;
+
+        spin_lock_irqsave(&gpiomux_lock, irq_flags);
+        BUG_ON(cfg->ref == 0);
+        if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID)
+                __msm_gpiomux_write(gpio, cfg->suspended);
+        spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
+        return 0;
+}
+EXPORT_SYMBOL(msm_gpiomux_put);
+
+static int __init gpiomux_init(void)
+{
+        unsigned n;
+
+        for (n = 0; n < GPIOMUX_NGPIOS; ++n) {
+                msm_gpiomux_configs[n].ref = 0;
+                if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID))
+                        continue;
+                __msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended);
+        }
+        return 0;
+}
+postcore_initcall(gpiomux_init);
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
new file mode 100644
index 00000000000..b178d9cb742
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux.h
@@ -0,0 +1,114 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H
+#define __ARCH_ARM_MACH_MSM_GPIOMUX_H
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+
+#if defined(CONFIG_MSM_V2_TLMM)
+#include "gpiomux-v2.h"
+#else
+#include "gpiomux-v1.h"
+#endif
+
+/**
+ * struct msm_gpiomux_config: gpiomux settings for one gpio line.
+ *
+ * A complete gpiomux config is the bitwise-or of a drive-strength,
+ * function, and pull.  For functions other than GPIO, the OE
+ * is hard-wired according to the function.  For GPIO mode,
+ * OE is controlled by gpiolib.
+ *
+ * Available settings differ by target; see the gpiomux header
+ * specific to your target arch for available configurations.
+ *
+ * @active: The configuration to be installed when the line is
+ * active, or its reference count is > 0.
+ * @suspended: The configuration to be installed when the line
+ * is suspended, or its reference count is 0.
+ * @ref: The reference count of the line.  For internal use of
+ * the gpiomux framework only.
+ */
+struct msm_gpiomux_config {
+        gpiomux_config_t active;
+        gpiomux_config_t suspended;
+        unsigned         ref;
+};
+
+/**
+ * @GPIOMUX_VALID:      If set, the config field contains 'good data'.
+ *                      The absence of this bit will prevent the gpiomux
+ *                      system from applying the configuration under all
+ *                      circumstances.
+ */
+enum {
+        GPIOMUX_VALID    = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1),
+        GPIOMUX_CTL_MASK = GPIOMUX_VALID,
+};
+
+#ifdef CONFIG_MSM_GPIOMUX
+
+/* Each architecture must provide its own instance of this table.
+ * To avoid having gpiomux manage any given gpio, one or both of
+ * the entries can avoid setting GPIOMUX_VALID - the absence
+ * of that flag will prevent the configuration from being applied
+ * during state transitions.
+ */
+extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
+
+/* Increment a gpio's reference count, possibly activating the line. */
+int __must_check msm_gpiomux_get(unsigned gpio);
+
+/* Decrement a gpio's reference count, possibly suspending the line. */
+int msm_gpiomux_put(unsigned gpio);
+
+/* Install a new configuration to the gpio line.  To avoid overwriting
+ * a configuration, leave the VALID bit out.
+ */
+int msm_gpiomux_write(unsigned gpio,
+                      gpiomux_config_t active,
+                      gpiomux_config_t suspended);
+
+/* Architecture-internal function for use by the framework only.
+ * This function can assume the following:
+ * - the gpio value has passed a bounds-check
+ * - the gpiomux spinlock has been obtained
+ *
+ * This function is not for public consumption.  External users
+ * should use msm_gpiomux_write.
+ */
+void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val);
+#else
+static inline int __must_check msm_gpiomux_get(unsigned gpio)
+{
+        return -ENOSYS;
+}
+
+static inline int msm_gpiomux_put(unsigned gpio)
+{
+        return -ENOSYS;
+}
+
+static inline int msm_gpiomux_write(unsigned gpio,
+                                    gpiomux_config_t active,
+                                    gpiomux_config_t suspended)
+{
+        return -ENOSYS;
+}
+#endif
+#endif
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 5a79bcf5041..6abf4a6eadc 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -33,6 +33,8 @@ struct msm_acpu_clock_platform_data
 
 struct clk;
 
+extern struct sys_timer msm_timer;
+
 /* common init routines for use by arch/arm/mach-msm/board-*.c */
 
 void __init msm_add_devices(void);
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 528750f307e..fbd5d90dcc8 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -19,13 +19,10 @@
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
 
-#ifdef CONFIG_MSM_DEBUG_UART
-        .macro  addruart, rx, tmp
-        @ see if the MMU is enabled and select appropriate base address
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1
-        ldreq   \rx, =MSM_DEBUG_UART_PHYS
-        ldrne   \rx, =MSM_DEBUG_UART_BASE
+#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS
+        .macro  addruart, rp, rv
+        ldr     \rp, =MSM_DEBUG_UART_PHYS
+        ldr     \rv, =MSM_DEBUG_UART_BASE
         .endm
 
         .macro  senduart,rd,rx
@@ -39,16 +36,7 @@
         tst     \rd, #0x04
         beq     1001b
         .endm
-#else
-        .macro  addruart, rx, tmp
-        .endm
-
-        .macro  senduart,rd,rx
-        .endm
-
-        .macro  waituart,rd,rx
-        .endm
-#endif
 
         .macro  busyuart,rd,rx
         .endm
+#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 00f9bbfadbe..05583f56952 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -32,10 +32,18 @@ struct msm_dmov_cmd {
         void *data;
 };
 
+#ifndef CONFIG_ARCH_MSM8X60
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
 void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
 int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
-
+#else
+static inline
+void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
+static inline
+void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
+static inline
+int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
+#endif
 
 
 #define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
new file mode 100644
index 00000000000..4dc99aa65d0
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -0,0 +1,88 @@
+/*
+ * Low-level IRQ helper macros
+ *
+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =gic_cpu_base_addr
+        ldr     \base, [\base]
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        /*
+         * The interrupt numbering scheme is defined in the
+         * interrupt controller spec.  To wit:
+         *
+         * Migrated the code from ARM MP port to be more consistant
+         * with interrupt processing , the following still holds true
+         * however, all interrupts are treated the same regardless of
+         * if they are local IPI or PPI
+         *
+         * Interrupts 0-15 are IPI
+         * 16-31 are PPI
+         *   (16-18 are the timers)
+         * 32-1020 are global
+         * 1021-1022 are reserved
+         * 1023 is "spurious" (no interrupt)
+         *
+         * A simple read from the controller will tell us the number of the
+         * highest priority enabled interrupt.  We then just need to check
+         * whether it is in the valid range for an IRQ (0-1020 inclusive).
+         *
+         * Base ARM code assumes that the local (private) peripheral interrupts
+         * are not valid, we treat them differently, in that the privates are
+         * handled like normal shared interrupts with the exception that only
+         * one processor can register the interrupt and the handler must be
+         * the same for all processors.
+         */
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+        ldr  \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
+                                                   9-0 =int # */
+
+        bic     \irqnr, \irqstat, #0x1c00       @mask src
+        cmp     \irqnr, #15
+        ldr             \tmp, =1021
+        cmpcc   \irqnr, \irqnr
+        cmpne   \irqnr, \tmp
+        cmpcs   \irqnr, \irqnr
+
+        .endm
+
+        /* We assume that irqstat (the raw value of the IRQ acknowledge
+         * register) is preserved from the macro above.
+         * If there is an IPI, we immediately signal end of interrupt on the
+         * controller, since this requires the original irqstat value which
+         * we won't easily be able to recreate later.
+         */
+        .macro test_for_ipi, irqnr, irqstat, base, tmp
+    bic \irqnr, \irqstat, #0x1c00
+    cmp \irqnr, #16
+    strcc   \irqstat, [\base, #GIC_CPU_EOI]
+    cmpcs   \irqnr, \irqnr
+        .endm
+
+        /* As above, this assumes that irqstat and base are preserved.. */
+
+        .macro test_for_ltirq, irqnr, irqstat, base, tmp
+    bic \irqnr, \irqstat, #0x1c00
+    mov     \tmp, #0
+    cmp \irqnr, #16
+    moveq   \tmp, #1
+    streq   \irqstat, [\base, #GIC_CPU_EOI]
+    cmp \tmp, #0
+        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
new file mode 100644
index 00000000000..70563ed11b3
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/msm_iomap.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        @ enable imprecise aborts
+        cpsie   a
+        mov     \base, #MSM_VIC_BASE
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ 0xD0 has irq# or old irq# if the irq has been handled
+        @ 0xD4 has irq# or -1 if none pending *but* if you just
+        @ read 0xD4 you never get the first irq for some reason
+        ldr     \irqnr, [\base, #0xD0]
+        ldr     \irqnr, [\base, #0xD4]
+        cmp     \irqnr, #0xffffffff
+        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index d2259486bcb..b16f082eeb6 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -1,38 +1,23 @@
-/* arch/arm/mach-msm7200/include/mach/entry-macro.S
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
  */
 
-#include <mach/msm_iomap.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        mov     \base, #MSM_VIC_BASE
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ 0xD0 has irq# or old irq# if the irq has been handled
-        @ 0xD4 has irq# or -1 if none pending *but* if you just
-        @ read 0xD4 you never get the first irq for some reason
-        ldr     \irqnr, [\base, #0xD0]
-        ldr     \irqnr, [\base, #0xD4]
-        cmp     \irqnr, #0xffffffff
-        .endm
+#if defined(CONFIG_ARM_GIC)
+#include <mach/entry-macro-qgic.S>
+#else
+#include <mach/entry-macro-vic.S>
+#endif
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 83e47c0d5c2..36ad50d3bfa 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -23,127 +23,4 @@
 #define gpio_cansleep   __gpio_cansleep
 #define gpio_to_irq     __gpio_to_irq
 
-/**
- * struct msm_gpio - GPIO pin description
- * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
- * @label - textual label
- *
- * Usually, GPIO's are operated by sets.
- * This struct accumulate all GPIO information in single source
- * and facilitete group operations provided by msm_gpios_xxx()
- */
-struct msm_gpio {
-        u32 gpio_cfg;
-        const char *label;
-};
-
-/**
- * msm_gpios_request_enable() - request and enable set of GPIOs
- *
- * Request and configure set of GPIO's
- * In case of error, all operations rolled back.
- * Return error code.
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-int msm_gpios_request_enable(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_disable_free() - disable and free set of GPIOs
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-void msm_gpios_disable_free(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_request() - request set of GPIOs
- * In case of error, all operations rolled back.
- * Return error code.
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-int msm_gpios_request(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_free() - free set of GPIOs
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-void msm_gpios_free(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_enable() - enable set of GPIOs
- * In case of error, all operations rolled back.
- * Return error code.
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-int msm_gpios_enable(const struct msm_gpio *table, int size);
-
-/**
- * msm_gpios_disable() - disable set of GPIOs
- *
- * @table: GPIO table
- * @size:  number of entries in @table
- */
-void msm_gpios_disable(const struct msm_gpio *table, int size);
-
-/* GPIO TLMM (Top Level Multiplexing) Definitions */
-
-/* GPIO TLMM: Function -- GPIO specific */
-
-/* GPIO TLMM: Direction */
-enum {
-        GPIO_INPUT,
-        GPIO_OUTPUT,
-};
-
-/* GPIO TLMM: Pullup/Pulldown */
-enum {
-        GPIO_NO_PULL,
-        GPIO_PULL_DOWN,
-        GPIO_KEEPER,
-        GPIO_PULL_UP,
-};
-
-/* GPIO TLMM: Drive Strength */
-enum {
-        GPIO_2MA,
-        GPIO_4MA,
-        GPIO_6MA,
-        GPIO_8MA,
-        GPIO_10MA,
-        GPIO_12MA,
-        GPIO_14MA,
-        GPIO_16MA,
-};
-
-enum {
-        GPIO_ENABLE,
-        GPIO_DISABLE,
-};
-
-#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
-        ((((gpio) & 0x3FF) << 4)        |         \
-         ((func) & 0xf)                  |        \
-         (((dir) & 0x1) << 14)           |        \
-         (((pull) & 0x3) << 15)          |        \
-         (((drvstr) & 0xF) << 17))
-
-/**
- * extract GPIO pin from bit-field used for gpio_tlmm_config
- */
-#define GPIO_PIN(gpio_cfg)    (((gpio_cfg) >>  4) & 0x3ff)
-#define GPIO_FUNC(gpio_cfg)   (((gpio_cfg) >>  0) & 0xf)
-#define GPIO_DIR(gpio_cfg)    (((gpio_cfg) >> 14) & 0x1)
-#define GPIO_PULL(gpio_cfg)   (((gpio_cfg) >> 15) & 0x3)
-#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf)
-
-int gpio_tlmm_config(unsigned config, unsigned disable);
-
 #endif /* __ASM_ARCH_MSM_GPIO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index c35b29f9ac0..7386e732baa 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -28,6 +28,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
 
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
+void msm_map_msm8x60_io(void);
 
 extern unsigned int msm_shared_ram_phys;
 
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
new file mode 100644
index 00000000000..218ef5732a2
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -0,0 +1,103 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef MSM_IOMMU_H
+#define MSM_IOMMU_H
+
+#include <linux/interrupt.h>
+
+/* Maximum number of Machine IDs that we are allowing to be mapped to the same
+ * context bank. The number of MIDs mapped to the same CB does not affect
+ * performance, but there is a practical limit on how many distinct MIDs may
+ * be present. These mappings are typically determined at design time and are
+ * not expected to change at run time.
+ */
+#define MAX_NUM_MIDS    16
+
+/**
+ * struct msm_iommu_dev - a single IOMMU hardware instance
+ * name         Human-readable name given to this IOMMU HW instance
+ * clk_rate     Rate to set for this IOMMU's clock, if applicable to this
+ *              particular IOMMU. 0 means don't set a rate.
+ *              -1 means it is an AXI clock with no valid rate
+ *
+ */
+struct msm_iommu_dev {
+        const char *name;
+        int clk_rate;
+};
+
+/**
+ * struct msm_iommu_ctx_dev - an IOMMU context bank instance
+ * name         Human-readable name given to this context bank
+ * num          Index of this context bank within the hardware
+ * mids         List of Machine IDs that are to be mapped into this context
+ *              bank, terminated by -1. The MID is a set of signals on the
+ *              AXI bus that identifies the function associated with a specific
+ *              memory request. (See ARM spec).
+ */
+struct msm_iommu_ctx_dev {
+        const char *name;
+        int num;
+        int mids[MAX_NUM_MIDS];
+};
+
+
+/**
+ * struct msm_iommu_drvdata - A single IOMMU hardware instance
+ * @base:       IOMMU config port base address (VA)
+ * @irq:        Interrupt number
+  *
+ * A msm_iommu_drvdata holds the global driver data about a single piece
+ * of an IOMMU hardware instance.
+ */
+struct msm_iommu_drvdata {
+        void __iomem *base;
+        int irq;
+};
+
+/**
+ * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
+ * @num:                Hardware context number of this context
+ * @pdev:               Platform device associated wit this HW instance
+ * @attached_elm:       List element for domains to track which devices are
+ *                      attached to them
+ *
+ * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
+ * within each IOMMU hardware instance
+ */
+struct msm_iommu_ctx_drvdata {
+        int num;
+        struct platform_device *pdev;
+        struct list_head attached_elm;
+};
+
+/*
+ * Look up an IOMMU context device by its context name. NULL if none found.
+ * Useful for testing and drivers that do not yet fully have IOMMU stuff in
+ * their platform devices.
+ */
+struct device *msm_iommu_get_ctx(const char *ctx_name);
+
+/*
+ * Interrupt handler for the IOMMU context fault interrupt. Hooking the
+ * interrupt is not supported in the API yet, but this will print an error
+ * message and dump useful IOMMU registers.
+ */
+irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
new file mode 100644
index 00000000000..f9386d3a2f7
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -0,0 +1,1871 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
+#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
+
+#define CTX_SHIFT 12
+
+#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
+#define GET_CTX_REG(reg, base, ctx) \
+                                (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
+
+#define SET_GLOBAL_REG(reg, base, val)  writel((val), ((base) + (reg)))
+
+#define SET_CTX_REG(reg, base, ctx, val) \
+                        writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
+
+/* Wrappers for numbered registers */
+#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
+#define GET_GLOBAL_REG_N(b, n, r)    GET_GLOBAL_REG(b, ((r) + (n << 2)))
+
+/* Field wrappers */
+#define GET_GLOBAL_FIELD(b, r, F)    GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
+#define GET_CONTEXT_FIELD(b, c, r, F)   \
+        GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
+
+#define SET_GLOBAL_FIELD(b, r, F, v) \
+        SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
+#define SET_CONTEXT_FIELD(b, c, r, F, v)        \
+        SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
+
+#define GET_FIELD(addr, mask, shift)  ((readl(addr) >> (shift)) & (mask))
+
+#define SET_FIELD(addr, mask, shift, v) \
+do { \
+        int t = readl(addr); \
+        writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
+} while (0)
+
+
+#define NUM_FL_PTE      4096
+#define NUM_SL_PTE      256
+
+/* First-level page table bits */
+#define FL_BASE_MASK            0xFFFFFC00
+#define FL_TYPE_TABLE           (1 << 0)
+#define FL_TYPE_SECT            (2 << 0)
+#define FL_SUPERSECTION         (1 << 18)
+#define FL_AP_WRITE             (1 << 10)
+#define FL_AP_READ              (1 << 11)
+#define FL_SHARED               (1 << 16)
+#define FL_OFFSET(va)           (((va) & 0xFFF00000) >> 20)
+
+/* Second-level page table bits */
+#define SL_BASE_MASK_LARGE      0xFFFF0000
+#define SL_BASE_MASK_SMALL      0xFFFFF000
+#define SL_TYPE_LARGE           (1 << 0)
+#define SL_TYPE_SMALL           (2 << 0)
+#define SL_AP0                  (1 << 4)
+#define SL_AP1                  (2 << 4)
+#define SL_SHARED               (1 << 10)
+#define SL_OFFSET(va)           (((va) & 0xFF000) >> 12)
+
+/* Global register setters / getters */
+#define SET_M2VCBR_N(b, N, v)    SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
+#define SET_CBACR_N(b, N, v)     SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
+#define SET_TLBRSW(b, v)         SET_GLOBAL_REG(TLBRSW, (b), (v))
+#define SET_TLBTR0(b, v)         SET_GLOBAL_REG(TLBTR0, (b), (v))
+#define SET_TLBTR1(b, v)         SET_GLOBAL_REG(TLBTR1, (b), (v))
+#define SET_TLBTR2(b, v)         SET_GLOBAL_REG(TLBTR2, (b), (v))
+#define SET_TESTBUSCR(b, v)      SET_GLOBAL_REG(TESTBUSCR, (b), (v))
+#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
+#define SET_TLBIVMID(b, v)       SET_GLOBAL_REG(TLBIVMID, (b), (v))
+#define SET_CR(b, v)             SET_GLOBAL_REG(CR, (b), (v))
+#define SET_EAR(b, v)            SET_GLOBAL_REG(EAR, (b), (v))
+#define SET_ESR(b, v)            SET_GLOBAL_REG(ESR, (b), (v))
+#define SET_ESRRESTORE(b, v)     SET_GLOBAL_REG(ESRRESTORE, (b), (v))
+#define SET_ESYNR0(b, v)         SET_GLOBAL_REG(ESYNR0, (b), (v))
+#define SET_ESYNR1(b, v)         SET_GLOBAL_REG(ESYNR1, (b), (v))
+#define SET_RPU_ACR(b, v)        SET_GLOBAL_REG(RPU_ACR, (b), (v))
+
+#define GET_M2VCBR_N(b, N)       GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
+#define GET_CBACR_N(b, N)        GET_GLOBAL_REG_N(CBACR_N, N, (b))
+#define GET_TLBTR0(b)            GET_GLOBAL_REG(TLBTR0, (b))
+#define GET_TLBTR1(b)            GET_GLOBAL_REG(TLBTR1, (b))
+#define GET_TLBTR2(b)            GET_GLOBAL_REG(TLBTR2, (b))
+#define GET_TESTBUSCR(b)         GET_GLOBAL_REG(TESTBUSCR, (b))
+#define GET_GLOBAL_TLBIALL(b)    GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
+#define GET_TLBIVMID(b)          GET_GLOBAL_REG(TLBIVMID, (b))
+#define GET_CR(b)                GET_GLOBAL_REG(CR, (b))
+#define GET_EAR(b)               GET_GLOBAL_REG(EAR, (b))
+#define GET_ESR(b)               GET_GLOBAL_REG(ESR, (b))
+#define GET_ESRRESTORE(b)        GET_GLOBAL_REG(ESRRESTORE, (b))
+#define GET_ESYNR0(b)            GET_GLOBAL_REG(ESYNR0, (b))
+#define GET_ESYNR1(b)            GET_GLOBAL_REG(ESYNR1, (b))
+#define GET_REV(b)               GET_GLOBAL_REG(REV, (b))
+#define GET_IDR(b)               GET_GLOBAL_REG(IDR, (b))
+#define GET_RPU_ACR(b)           GET_GLOBAL_REG(RPU_ACR, (b))
+
+
+/* Context register setters/getters */
+#define SET_SCTLR(b, c, v)       SET_CTX_REG(SCTLR, (b), (c), (v))
+#define SET_ACTLR(b, c, v)       SET_CTX_REG(ACTLR, (b), (c), (v))
+#define SET_CONTEXTIDR(b, c, v)  SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
+#define SET_TTBR0(b, c, v)       SET_CTX_REG(TTBR0, (b), (c), (v))
+#define SET_TTBR1(b, c, v)       SET_CTX_REG(TTBR1, (b), (c), (v))
+#define SET_TTBCR(b, c, v)       SET_CTX_REG(TTBCR, (b), (c), (v))
+#define SET_PAR(b, c, v)         SET_CTX_REG(PAR, (b), (c), (v))
+#define SET_FSR(b, c, v)         SET_CTX_REG(FSR, (b), (c), (v))
+#define SET_FSRRESTORE(b, c, v)  SET_CTX_REG(FSRRESTORE, (b), (c), (v))
+#define SET_FAR(b, c, v)         SET_CTX_REG(FAR, (b), (c), (v))
+#define SET_FSYNR0(b, c, v)      SET_CTX_REG(FSYNR0, (b), (c), (v))
+#define SET_FSYNR1(b, c, v)      SET_CTX_REG(FSYNR1, (b), (c), (v))
+#define SET_PRRR(b, c, v)        SET_CTX_REG(PRRR, (b), (c), (v))
+#define SET_NMRR(b, c, v)        SET_CTX_REG(NMRR, (b), (c), (v))
+#define SET_TLBLKCR(b, c, v)     SET_CTX_REG(TLBLCKR, (b), (c), (v))
+#define SET_V2PSR(b, c, v)       SET_CTX_REG(V2PSR, (b), (c), (v))
+#define SET_TLBFLPTER(b, c, v)   SET_CTX_REG(TLBFLPTER, (b), (c), (v))
+#define SET_TLBSLPTER(b, c, v)   SET_CTX_REG(TLBSLPTER, (b), (c), (v))
+#define SET_BFBCR(b, c, v)       SET_CTX_REG(BFBCR, (b), (c), (v))
+#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
+#define SET_TLBIASID(b, c, v)    SET_CTX_REG(TLBIASID, (b), (c), (v))
+#define SET_TLBIVA(b, c, v)      SET_CTX_REG(TLBIVA, (b), (c), (v))
+#define SET_TLBIVAA(b, c, v)     SET_CTX_REG(TLBIVAA, (b), (c), (v))
+#define SET_V2PPR(b, c, v)       SET_CTX_REG(V2PPR, (b), (c), (v))
+#define SET_V2PPW(b, c, v)       SET_CTX_REG(V2PPW, (b), (c), (v))
+#define SET_V2PUR(b, c, v)       SET_CTX_REG(V2PUR, (b), (c), (v))
+#define SET_V2PUW(b, c, v)       SET_CTX_REG(V2PUW, (b), (c), (v))
+#define SET_RESUME(b, c, v)      SET_CTX_REG(RESUME, (b), (c), (v))
+
+#define GET_SCTLR(b, c)          GET_CTX_REG(SCTLR, (b), (c))
+#define GET_ACTLR(b, c)          GET_CTX_REG(ACTLR, (b), (c))
+#define GET_CONTEXTIDR(b, c)     GET_CTX_REG(CONTEXTIDR, (b), (c))
+#define GET_TTBR0(b, c)          GET_CTX_REG(TTBR0, (b), (c))
+#define GET_TTBR1(b, c)          GET_CTX_REG(TTBR1, (b), (c))
+#define GET_TTBCR(b, c)          GET_CTX_REG(TTBCR, (b), (c))
+#define GET_PAR(b, c)            GET_CTX_REG(PAR, (b), (c))
+#define GET_FSR(b, c)            GET_CTX_REG(FSR, (b), (c))
+#define GET_FSRRESTORE(b, c)     GET_CTX_REG(FSRRESTORE, (b), (c))
+#define GET_FAR(b, c)            GET_CTX_REG(FAR, (b), (c))
+#define GET_FSYNR0(b, c)         GET_CTX_REG(FSYNR0, (b), (c))
+#define GET_FSYNR1(b, c)         GET_CTX_REG(FSYNR1, (b), (c))
+#define GET_PRRR(b, c)           GET_CTX_REG(PRRR, (b), (c))
+#define GET_NMRR(b, c)           GET_CTX_REG(NMRR, (b), (c))
+#define GET_TLBLCKR(b, c)        GET_CTX_REG(TLBLCKR, (b), (c))
+#define GET_V2PSR(b, c)          GET_CTX_REG(V2PSR, (b), (c))
+#define GET_TLBFLPTER(b, c)      GET_CTX_REG(TLBFLPTER, (b), (c))
+#define GET_TLBSLPTER(b, c)      GET_CTX_REG(TLBSLPTER, (b), (c))
+#define GET_BFBCR(b, c)          GET_CTX_REG(BFBCR, (b), (c))
+#define GET_CTX_TLBIALL(b, c)    GET_CTX_REG(CTX_TLBIALL, (b), (c))
+#define GET_TLBIASID(b, c)       GET_CTX_REG(TLBIASID, (b), (c))
+#define GET_TLBIVA(b, c)         GET_CTX_REG(TLBIVA, (b), (c))
+#define GET_TLBIVAA(b, c)        GET_CTX_REG(TLBIVAA, (b), (c))
+#define GET_V2PPR(b, c)          GET_CTX_REG(V2PPR, (b), (c))
+#define GET_V2PPW(b, c)          GET_CTX_REG(V2PPW, (b), (c))
+#define GET_V2PUR(b, c)          GET_CTX_REG(V2PUR, (b), (c))
+#define GET_V2PUW(b, c)          GET_CTX_REG(V2PUW, (b), (c))
+#define GET_RESUME(b, c)         GET_CTX_REG(RESUME, (b), (c))
+
+
+/* Global field setters / getters */
+/* Global Field Setters: */
+/* CBACR_N */
+#define SET_RWVMID(b, n, v)   SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
+#define SET_RWE(b, n, v)      SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
+#define SET_RWGE(b, n, v)     SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
+#define SET_CBVMID(b, n, v)   SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
+#define SET_IRPTNDX(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
+
+
+/* M2VCBR_N */
+#define SET_VMID(b, n, v)     SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
+#define SET_CBNDX(b, n, v)    SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
+#define SET_BYPASSD(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
+#define SET_BPRCOSH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
+#define SET_BPRCISH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
+#define SET_BPRCNSH(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
+#define SET_BPSHCFG(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
+#define SET_NSCFG(b, n, v)    SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
+#define SET_BPMTCFG(b, n, v)  SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
+#define SET_BPMEMTYPE(b, n, v) \
+        SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
+
+
+/* CR */
+#define SET_RPUE(b, v)           SET_GLOBAL_FIELD(b, CR, RPUE, v)
+#define SET_RPUERE(b, v)         SET_GLOBAL_FIELD(b, CR, RPUERE, v)
+#define SET_RPUEIE(b, v)         SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
+#define SET_DCDEE(b, v)          SET_GLOBAL_FIELD(b, CR, DCDEE, v)
+#define SET_CLIENTPD(b, v)       SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
+#define SET_STALLD(b, v)         SET_GLOBAL_FIELD(b, CR, STALLD, v)
+#define SET_TLBLKCRWE(b, v)      SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
+#define SET_CR_TLBIALLCFG(b, v)  SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
+#define SET_TLBIVMIDCFG(b, v)    SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
+#define SET_CR_HUME(b, v)        SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
+
+
+/* ESR */
+#define SET_CFG(b, v)            SET_GLOBAL_FIELD(b, ESR, CFG, v)
+#define SET_BYPASS(b, v)         SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
+#define SET_ESR_MULTI(b, v)      SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
+
+
+/* ESYNR0 */
+#define SET_ESYNR0_AMID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
+#define SET_ESYNR0_APID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
+#define SET_ESYNR0_ABID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
+#define SET_ESYNR0_AVMID(b, v)   SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
+#define SET_ESYNR0_ATID(b, v)    SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
+
+
+/* ESYNR1 */
+#define SET_ESYNR1_AMEMTYPE(b, v) \
+                        SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
+#define SET_ESYNR1_ASHARED(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
+#define SET_ESYNR1_AINNERSHARED(b, v) \
+                        SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
+#define SET_ESYNR1_APRIV(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
+#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
+#define SET_ESYNR1_AINST(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
+#define SET_ESYNR1_AWRITE(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
+#define SET_ESYNR1_ABURST(b, v)  SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
+#define SET_ESYNR1_ALEN(b, v)    SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
+#define SET_ESYNR1_ASIZE(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
+#define SET_ESYNR1_ALOCK(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
+#define SET_ESYNR1_AOOO(b, v)    SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
+#define SET_ESYNR1_AFULL(b, v)   SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
+#define SET_ESYNR1_AC(b, v)      SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
+#define SET_ESYNR1_DCD(b, v)     SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
+
+
+/* TESTBUSCR */
+#define SET_TBE(b, v)            SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
+#define SET_SPDMBE(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
+#define SET_WGSEL(b, v)          SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
+#define SET_TBLSEL(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
+#define SET_TBHSEL(b, v)         SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
+#define SET_SPDM0SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
+#define SET_SPDM1SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
+#define SET_SPDM2SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
+#define SET_SPDM3SEL(b, v)       SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
+
+
+/* TLBIVMID */
+#define SET_TLBIVMID_VMID(b, v)  SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
+
+
+/* TLBRSW */
+#define SET_TLBRSW_INDEX(b, v)   SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
+#define SET_TLBBFBS(b, v)        SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
+
+
+/* TLBTR0 */
+#define SET_PR(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
+#define SET_PW(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
+#define SET_UR(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
+#define SET_UW(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
+#define SET_XN(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
+#define SET_NSDESC(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
+#define SET_ISH(b, v)            SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
+#define SET_SH(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
+#define SET_MT(b, v)             SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
+#define SET_DPSIZR(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
+#define SET_DPSIZC(b, v)         SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
+
+
+/* TLBTR1 */
+#define SET_TLBTR1_VMID(b, v)    SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
+#define SET_TLBTR1_PA(b, v)      SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
+
+
+/* TLBTR2 */
+#define SET_TLBTR2_ASID(b, v)    SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
+#define SET_TLBTR2_V(b, v)       SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
+#define SET_TLBTR2_NSTID(b, v)   SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
+#define SET_TLBTR2_NV(b, v)      SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
+#define SET_TLBTR2_VA(b, v)      SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
+
+
+/* Global Field Getters */
+/* CBACR_N */
+#define GET_RWVMID(b, n)         GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
+#define GET_RWE(b, n)            GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
+#define GET_RWGE(b, n)           GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
+#define GET_CBVMID(b, n)         GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
+#define GET_IRPTNDX(b, n)        GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
+
+
+/* M2VCBR_N */
+#define GET_VMID(b, n)       GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
+#define GET_CBNDX(b, n)      GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
+#define GET_BYPASSD(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
+#define GET_BPRCOSH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
+#define GET_BPRCISH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
+#define GET_BPRCNSH(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
+#define GET_BPSHCFG(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
+#define GET_NSCFG(b, n)      GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
+#define GET_BPMTCFG(b, n)    GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
+#define GET_BPMEMTYPE(b, n)  GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
+
+
+/* CR */
+#define GET_RPUE(b)              GET_GLOBAL_FIELD(b, CR, RPUE)
+#define GET_RPUERE(b)            GET_GLOBAL_FIELD(b, CR, RPUERE)
+#define GET_RPUEIE(b)            GET_GLOBAL_FIELD(b, CR, RPUEIE)
+#define GET_DCDEE(b)             GET_GLOBAL_FIELD(b, CR, DCDEE)
+#define GET_CLIENTPD(b)          GET_GLOBAL_FIELD(b, CR, CLIENTPD)
+#define GET_STALLD(b)            GET_GLOBAL_FIELD(b, CR, STALLD)
+#define GET_TLBLKCRWE(b)         GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
+#define GET_CR_TLBIALLCFG(b)     GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
+#define GET_TLBIVMIDCFG(b)       GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
+#define GET_CR_HUME(b)           GET_GLOBAL_FIELD(b, CR, CR_HUME)
+
+
+/* ESR */
+#define GET_CFG(b)               GET_GLOBAL_FIELD(b, ESR, CFG)
+#define GET_BYPASS(b)            GET_GLOBAL_FIELD(b, ESR, BYPASS)
+#define GET_ESR_MULTI(b)         GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
+
+
+/* ESYNR0 */
+#define GET_ESYNR0_AMID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
+#define GET_ESYNR0_APID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
+#define GET_ESYNR0_ABID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
+#define GET_ESYNR0_AVMID(b)      GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
+#define GET_ESYNR0_ATID(b)       GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
+
+
+/* ESYNR1 */
+#define GET_ESYNR1_AMEMTYPE(b)   GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
+#define GET_ESYNR1_ASHARED(b)    GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
+#define GET_ESYNR1_AINNERSHARED(b) \
+                        GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
+#define GET_ESYNR1_APRIV(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
+#define GET_ESYNR1_APROTNS(b)    GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
+#define GET_ESYNR1_AINST(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
+#define GET_ESYNR1_AWRITE(b)     GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
+#define GET_ESYNR1_ABURST(b)     GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
+#define GET_ESYNR1_ALEN(b)       GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
+#define GET_ESYNR1_ASIZE(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
+#define GET_ESYNR1_ALOCK(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
+#define GET_ESYNR1_AOOO(b)       GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
+#define GET_ESYNR1_AFULL(b)      GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
+#define GET_ESYNR1_AC(b)         GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
+#define GET_ESYNR1_DCD(b)        GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
+
+
+/* IDR */
+#define GET_NM2VCBMT(b)          GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
+#define GET_HTW(b)               GET_GLOBAL_FIELD(b, IDR, HTW)
+#define GET_HUM(b)               GET_GLOBAL_FIELD(b, IDR, HUM)
+#define GET_TLBSIZE(b)           GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
+#define GET_NCB(b)               GET_GLOBAL_FIELD(b, IDR, NCB)
+#define GET_NIRPT(b)             GET_GLOBAL_FIELD(b, IDR, NIRPT)
+
+
+/* REV */
+#define GET_MAJOR(b)             GET_GLOBAL_FIELD(b, REV, MAJOR)
+#define GET_MINOR(b)             GET_GLOBAL_FIELD(b, REV, MINOR)
+
+
+/* TESTBUSCR */
+#define GET_TBE(b)               GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
+#define GET_SPDMBE(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
+#define GET_WGSEL(b)             GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
+#define GET_TBLSEL(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
+#define GET_TBHSEL(b)            GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
+#define GET_SPDM0SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
+#define GET_SPDM1SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
+#define GET_SPDM2SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
+#define GET_SPDM3SEL(b)          GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
+
+
+/* TLBIVMID */
+#define GET_TLBIVMID_VMID(b)     GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
+
+
+/* TLBTR0 */
+#define GET_PR(b)                GET_GLOBAL_FIELD(b, TLBTR0, PR)
+#define GET_PW(b)                GET_GLOBAL_FIELD(b, TLBTR0, PW)
+#define GET_UR(b)                GET_GLOBAL_FIELD(b, TLBTR0, UR)
+#define GET_UW(b)                GET_GLOBAL_FIELD(b, TLBTR0, UW)
+#define GET_XN(b)                GET_GLOBAL_FIELD(b, TLBTR0, XN)
+#define GET_NSDESC(b)            GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
+#define GET_ISH(b)               GET_GLOBAL_FIELD(b, TLBTR0, ISH)
+#define GET_SH(b)                GET_GLOBAL_FIELD(b, TLBTR0, SH)
+#define GET_MT(b)                GET_GLOBAL_FIELD(b, TLBTR0, MT)
+#define GET_DPSIZR(b)            GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
+#define GET_DPSIZC(b)            GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
+
+
+/* TLBTR1 */
+#define GET_TLBTR1_VMID(b)       GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
+#define GET_TLBTR1_PA(b)         GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
+
+
+/* TLBTR2 */
+#define GET_TLBTR2_ASID(b)       GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
+#define GET_TLBTR2_V(b)          GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
+#define GET_TLBTR2_NSTID(b)      GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
+#define GET_TLBTR2_NV(b)         GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
+#define GET_TLBTR2_VA(b)         GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
+
+
+/* Context Register setters / getters */
+/* Context Register setters */
+/* ACTLR */
+#define SET_CFERE(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
+#define SET_CFEIE(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
+#define SET_PTSHCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
+#define SET_RCOSH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
+#define SET_RCISH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
+#define SET_RCNSH(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
+#define SET_PRIVCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
+#define SET_DNA(b, c, v)         SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
+#define SET_DNLV2PA(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
+#define SET_TLBMCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
+#define SET_CFCFG(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
+#define SET_TIPCF(b, c, v)       SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
+#define SET_V2PCFG(b, c, v)      SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
+#define SET_HUME(b, c, v)        SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
+#define SET_PTMTCFG(b, c, v)     SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
+#define SET_PTMEMTYPE(b, c, v)   SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
+
+
+/* BFBCR */
+#define SET_BFBDFE(b, c, v)      SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
+#define SET_BFBSFE(b, c, v)      SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
+#define SET_SFVS(b, c, v)        SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
+#define SET_FLVIC(b, c, v)       SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
+#define SET_SLVIC(b, c, v)       SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
+
+
+/* CONTEXTIDR */
+#define SET_CONTEXTIDR_ASID(b, c, v)   \
+                SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
+#define SET_CONTEXTIDR_PROCID(b, c, v) \
+                SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
+
+
+/* FSR */
+#define SET_TF(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, TF, v)
+#define SET_AFF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
+#define SET_APF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, APF, v)
+#define SET_TLBMF(b, c, v)       SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
+#define SET_HTWDEEF(b, c, v)     SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
+#define SET_HTWSEEF(b, c, v)     SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
+#define SET_MHF(b, c, v)         SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
+#define SET_SL(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, SL, v)
+#define SET_SS(b, c, v)          SET_CONTEXT_FIELD(b, c, FSR, SS, v)
+#define SET_MULTI(b, c, v)       SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
+
+
+/* FSYNR0 */
+#define SET_AMID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
+#define SET_APID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
+#define SET_ABID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
+#define SET_ATID(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
+
+
+/* FSYNR1 */
+#define SET_AMEMTYPE(b, c, v)    SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
+#define SET_ASHARED(b, c, v)     SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
+#define SET_AINNERSHARED(b, c, v)  \
+                                SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
+#define SET_APRIV(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
+#define SET_APROTNS(b, c, v)     SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
+#define SET_AINST(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
+#define SET_AWRITE(b, c, v)      SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
+#define SET_ABURST(b, c, v)      SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
+#define SET_ALEN(b, c, v)        SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
+#define SET_FSYNR1_ASIZE(b, c, v) \
+                                SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
+#define SET_ALOCK(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
+#define SET_AFULL(b, c, v)       SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
+
+
+/* NMRR */
+#define SET_ICPC0(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
+#define SET_ICPC1(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
+#define SET_ICPC2(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
+#define SET_ICPC3(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
+#define SET_ICPC4(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
+#define SET_ICPC5(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
+#define SET_ICPC6(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
+#define SET_ICPC7(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
+#define SET_OCPC0(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
+#define SET_OCPC1(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
+#define SET_OCPC2(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
+#define SET_OCPC3(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
+#define SET_OCPC4(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
+#define SET_OCPC5(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
+#define SET_OCPC6(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
+#define SET_OCPC7(b, c, v)       SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
+
+
+/* PAR */
+#define SET_FAULT(b, c, v)       SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
+
+#define SET_FAULT_TF(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
+#define SET_FAULT_AFF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
+#define SET_FAULT_APF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
+#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
+#define SET_FAULT_HTWDEEF(b, c, v) \
+                                SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
+#define SET_FAULT_HTWSEEF(b, c, v) \
+                                SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
+#define SET_FAULT_MHF(b, c, v)   SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
+#define SET_FAULT_SL(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
+#define SET_FAULT_SS(b, c, v)    SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
+
+#define SET_NOFAULT_SS(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
+#define SET_NOFAULT_MT(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
+#define SET_NOFAULT_SH(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
+#define SET_NOFAULT_NS(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
+#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
+#define SET_NPFAULT_PA(b, c, v)  SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
+
+
+/* PRRR */
+#define SET_MTC0(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
+#define SET_MTC1(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
+#define SET_MTC2(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
+#define SET_MTC3(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
+#define SET_MTC4(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
+#define SET_MTC5(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
+#define SET_MTC6(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
+#define SET_MTC7(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
+#define SET_SHDSH0(b, c, v)      SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
+#define SET_SHDSH1(b, c, v)      SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
+#define SET_SHNMSH0(b, c, v)     SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
+#define SET_SHNMSH1(b, c, v)     SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
+#define SET_NOS0(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
+#define SET_NOS1(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
+#define SET_NOS2(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
+#define SET_NOS3(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
+#define SET_NOS4(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
+#define SET_NOS5(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
+#define SET_NOS6(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
+#define SET_NOS7(b, c, v)        SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
+
+
+/* RESUME */
+#define SET_TNR(b, c, v)         SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
+
+
+/* SCTLR */
+#define SET_M(b, c, v)           SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
+#define SET_TRE(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
+#define SET_AFE(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
+#define SET_HAF(b, c, v)         SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
+#define SET_BE(b, c, v)          SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
+#define SET_AFFD(b, c, v)        SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
+
+
+/* TLBLKCR */
+#define SET_LKE(b, c, v)           SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
+#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
+                        SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
+#define SET_TLBIASIDCFG(b, c, v) \
+                        SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
+#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
+#define SET_FLOOR(b, c, v)      SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
+#define SET_VICTIM(b, c, v)     SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
+
+
+/* TTBCR */
+#define SET_N(b, c, v)           SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
+#define SET_PD0(b, c, v)         SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
+#define SET_PD1(b, c, v)         SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
+
+
+/* TTBR0 */
+#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
+#define SET_TTBR0_SH(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
+#define SET_TTBR0_ORGN(b, c, v)  SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
+#define SET_TTBR0_NOS(b, c, v)   SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
+#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
+#define SET_TTBR0_PA(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
+
+
+/* TTBR1 */
+#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
+#define SET_TTBR1_SH(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
+#define SET_TTBR1_ORGN(b, c, v)  SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
+#define SET_TTBR1_NOS(b, c, v)   SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
+#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
+#define SET_TTBR1_PA(b, c, v)    SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
+
+
+/* V2PSR */
+#define SET_HIT(b, c, v)         SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
+#define SET_INDEX(b, c, v)       SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
+
+
+/* V2Pxx UW UR PW PR */
+#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v)
+#define SET_V2PUW_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v)
+
+#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v)
+#define SET_V2PUR_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v)
+
+#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v)
+#define SET_V2PPW_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v)
+
+#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v)
+#define SET_V2PPR_VA(b, c, v)    SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v)
+
+
+/* Context Register getters */
+/* ACTLR */
+#define GET_CFERE(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
+#define GET_CFEIE(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
+#define GET_PTSHCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
+#define GET_RCOSH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
+#define GET_RCISH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
+#define GET_RCNSH(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
+#define GET_PRIVCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
+#define GET_DNA(b, c)           GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
+#define GET_DNLV2PA(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
+#define GET_TLBMCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
+#define GET_CFCFG(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
+#define GET_TIPCF(b, c)         GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
+#define GET_V2PCFG(b, c)        GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
+#define GET_HUME(b, c)          GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
+#define GET_PTMTCFG(b, c)       GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
+#define GET_PTMEMTYPE(b, c)     GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
+
+/* BFBCR */
+#define GET_BFBDFE(b, c)        GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
+#define GET_BFBSFE(b, c)        GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
+#define GET_SFVS(b, c)          GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
+#define GET_FLVIC(b, c)         GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
+#define GET_SLVIC(b, c)         GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
+
+
+/* CONTEXTIDR */
+#define GET_CONTEXTIDR_ASID(b, c) \
+                        GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
+#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
+
+
+/* FSR */
+#define GET_TF(b, c)            GET_CONTEXT_FIELD(b, c, FSR, TF)
+#define GET_AFF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, AFF)
+#define GET_APF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, APF)
+#define GET_TLBMF(b, c)         GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
+#define GET_HTWDEEF(b, c)       GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
+#define GET_HTWSEEF(b, c)       GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
+#define GET_MHF(b, c)           GET_CONTEXT_FIELD(b, c, FSR, MHF)
+#define GET_SL(b, c)            GET_CONTEXT_FIELD(b, c, FSR, SL)
+#define GET_SS(b, c)            GET_CONTEXT_FIELD(b, c, FSR, SS)
+#define GET_MULTI(b, c)         GET_CONTEXT_FIELD(b, c, FSR, MULTI)
+
+
+/* FSYNR0 */
+#define GET_AMID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
+#define GET_APID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
+#define GET_ABID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
+#define GET_ATID(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
+
+
+/* FSYNR1 */
+#define GET_AMEMTYPE(b, c)      GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
+#define GET_ASHARED(b, c)       GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
+#define GET_AINNERSHARED(b, c)  GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
+#define GET_APRIV(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
+#define GET_APROTNS(b, c)       GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
+#define GET_AINST(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
+#define GET_AWRITE(b, c)        GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
+#define GET_ABURST(b, c)        GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
+#define GET_ALEN(b, c)          GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
+#define GET_FSYNR1_ASIZE(b, c)  GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
+#define GET_ALOCK(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
+#define GET_AFULL(b, c)         GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
+
+
+/* NMRR */
+#define GET_ICPC0(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
+#define GET_ICPC1(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
+#define GET_ICPC2(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
+#define GET_ICPC3(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
+#define GET_ICPC4(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
+#define GET_ICPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
+#define GET_ICPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
+#define GET_ICPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
+#define GET_OCPC0(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
+#define GET_OCPC1(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
+#define GET_OCPC2(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
+#define GET_OCPC3(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
+#define GET_OCPC4(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
+#define GET_OCPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
+#define GET_OCPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
+#define GET_OCPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
+
+
+/* PAR */
+#define GET_FAULT(b, c)         GET_CONTEXT_FIELD(b, c, PAR, FAULT)
+
+#define GET_FAULT_TF(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
+#define GET_FAULT_AFF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
+#define GET_FAULT_APF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
+#define GET_FAULT_TLBMF(b, c)   GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
+#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
+#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
+#define GET_FAULT_MHF(b, c)     GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
+#define GET_FAULT_SL(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
+#define GET_FAULT_SS(b, c)      GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
+
+#define GET_NOFAULT_SS(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
+#define GET_NOFAULT_MT(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
+#define GET_NOFAULT_SH(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
+#define GET_NOFAULT_NS(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
+#define GET_NOFAULT_NOS(b, c)   GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
+#define GET_NPFAULT_PA(b, c)    GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
+
+
+/* PRRR */
+#define GET_MTC0(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
+#define GET_MTC1(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
+#define GET_MTC2(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
+#define GET_MTC3(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
+#define GET_MTC4(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
+#define GET_MTC5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
+#define GET_MTC6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
+#define GET_MTC7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
+#define GET_SHDSH0(b, c)        GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
+#define GET_SHDSH1(b, c)        GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
+#define GET_SHNMSH0(b, c)       GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
+#define GET_SHNMSH1(b, c)       GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
+#define GET_NOS0(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
+#define GET_NOS1(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
+#define GET_NOS2(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
+#define GET_NOS3(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
+#define GET_NOS4(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
+#define GET_NOS5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
+#define GET_NOS6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
+#define GET_NOS7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
+
+
+/* RESUME */
+#define GET_TNR(b, c)           GET_CONTEXT_FIELD(b, c, RESUME, TNR)
+
+
+/* SCTLR */
+#define GET_M(b, c)             GET_CONTEXT_FIELD(b, c, SCTLR, M)
+#define GET_TRE(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
+#define GET_AFE(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
+#define GET_HAF(b, c)           GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
+#define GET_BE(b, c)            GET_CONTEXT_FIELD(b, c, SCTLR, BE)
+#define GET_AFFD(b, c)          GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
+
+
+/* TLBLKCR */
+#define GET_LKE(b, c)           GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
+#define GET_TLBLCKR_TLBIALLCFG(b, c) \
+                        GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
+#define GET_TLBIASIDCFG(b, c)   GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
+#define GET_TLBIVAACFG(b, c)    GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
+#define GET_FLOOR(b, c)         GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
+#define GET_VICTIM(b, c)        GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
+
+
+/* TTBCR */
+#define GET_N(b, c)             GET_CONTEXT_FIELD(b, c, TTBCR, N)
+#define GET_PD0(b, c)           GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
+#define GET_PD1(b, c)           GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
+
+
+/* TTBR0 */
+#define GET_TTBR0_IRGNH(b, c)   GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
+#define GET_TTBR0_SH(b, c)      GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
+#define GET_TTBR0_ORGN(b, c)    GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
+#define GET_TTBR0_NOS(b, c)     GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
+#define GET_TTBR0_IRGNL(b, c)   GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
+#define GET_TTBR0_PA(b, c)      GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
+
+
+/* TTBR1 */
+#define GET_TTBR1_IRGNH(b, c)   GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
+#define GET_TTBR1_SH(b, c)      GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
+#define GET_TTBR1_ORGN(b, c)    GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
+#define GET_TTBR1_NOS(b, c)     GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
+#define GET_TTBR1_IRGNL(b, c)   GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
+#define GET_TTBR1_PA(b, c)      GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
+
+
+/* V2PSR */
+#define GET_HIT(b, c)           GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
+#define GET_INDEX(b, c)         GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
+
+
+/* V2Pxx UW UR PW PR */
+#define GET_V2PUW_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX)
+#define GET_V2PUW_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA)
+
+#define GET_V2PUR_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX)
+#define GET_V2PUR_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA)
+
+#define GET_V2PPW_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX)
+#define GET_V2PPW_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA)
+
+#define GET_V2PPR_INDEX(b, c)   GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX)
+#define GET_V2PPR_VA(b, c)      GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA)
+
+
+/* Global Registers */
+#define M2VCBR_N        (0xFF000)
+#define CBACR_N         (0xFF800)
+#define TLBRSW          (0xFFE00)
+#define TLBTR0          (0xFFE80)
+#define TLBTR1          (0xFFE84)
+#define TLBTR2          (0xFFE88)
+#define TESTBUSCR       (0xFFE8C)
+#define GLOBAL_TLBIALL  (0xFFF00)
+#define TLBIVMID        (0xFFF04)
+#define CR              (0xFFF80)
+#define EAR             (0xFFF84)
+#define ESR             (0xFFF88)
+#define ESRRESTORE      (0xFFF8C)
+#define ESYNR0          (0xFFF90)
+#define ESYNR1          (0xFFF94)
+#define REV             (0xFFFF4)
+#define IDR             (0xFFFF8)
+#define RPU_ACR         (0xFFFFC)
+
+
+/* Context Bank Registers */
+#define SCTLR           (0x000)
+#define ACTLR           (0x004)
+#define CONTEXTIDR      (0x008)
+#define TTBR0           (0x010)
+#define TTBR1           (0x014)
+#define TTBCR           (0x018)
+#define PAR             (0x01C)
+#define FSR             (0x020)
+#define FSRRESTORE      (0x024)
+#define FAR             (0x028)
+#define FSYNR0          (0x02C)
+#define FSYNR1          (0x030)
+#define PRRR            (0x034)
+#define NMRR            (0x038)
+#define TLBLCKR         (0x03C)
+#define V2PSR           (0x040)
+#define TLBFLPTER       (0x044)
+#define TLBSLPTER       (0x048)
+#define BFBCR           (0x04C)
+#define CTX_TLBIALL     (0x800)
+#define TLBIASID        (0x804)
+#define TLBIVA          (0x808)
+#define TLBIVAA         (0x80C)
+#define V2PPR           (0x810)
+#define V2PPW           (0x814)
+#define V2PUR           (0x818)
+#define V2PUW           (0x81C)
+#define RESUME          (0x820)
+
+
+/* Global Register Fields */
+/* CBACRn */
+#define RWVMID        (RWVMID_MASK       << RWVMID_SHIFT)
+#define RWE           (RWE_MASK          << RWE_SHIFT)
+#define RWGE          (RWGE_MASK         << RWGE_SHIFT)
+#define CBVMID        (CBVMID_MASK       << CBVMID_SHIFT)
+#define IRPTNDX       (IRPTNDX_MASK      << IRPTNDX_SHIFT)
+
+
+/* CR */
+#define RPUE          (RPUE_MASK          << RPUE_SHIFT)
+#define RPUERE        (RPUERE_MASK        << RPUERE_SHIFT)
+#define RPUEIE        (RPUEIE_MASK        << RPUEIE_SHIFT)
+#define DCDEE         (DCDEE_MASK         << DCDEE_SHIFT)
+#define CLIENTPD      (CLIENTPD_MASK      << CLIENTPD_SHIFT)
+#define STALLD        (STALLD_MASK        << STALLD_SHIFT)
+#define TLBLKCRWE     (TLBLKCRWE_MASK     << TLBLKCRWE_SHIFT)
+#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
+#define TLBIVMIDCFG   (TLBIVMIDCFG_MASK   << TLBIVMIDCFG_SHIFT)
+#define CR_HUME       (CR_HUME_MASK       << CR_HUME_SHIFT)
+
+
+/* ESR */
+#define CFG           (CFG_MASK          << CFG_SHIFT)
+#define BYPASS        (BYPASS_MASK       << BYPASS_SHIFT)
+#define ESR_MULTI     (ESR_MULTI_MASK    << ESR_MULTI_SHIFT)
+
+
+/* ESYNR0 */
+#define ESYNR0_AMID   (ESYNR0_AMID_MASK  << ESYNR0_AMID_SHIFT)
+#define ESYNR0_APID   (ESYNR0_APID_MASK  << ESYNR0_APID_SHIFT)
+#define ESYNR0_ABID   (ESYNR0_ABID_MASK  << ESYNR0_ABID_SHIFT)
+#define ESYNR0_AVMID  (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
+#define ESYNR0_ATID   (ESYNR0_ATID_MASK  << ESYNR0_ATID_SHIFT)
+
+
+/* ESYNR1 */
+#define ESYNR1_AMEMTYPE      (ESYNR1_AMEMTYPE_MASK    << ESYNR1_AMEMTYPE_SHIFT)
+#define ESYNR1_ASHARED       (ESYNR1_ASHARED_MASK     << ESYNR1_ASHARED_SHIFT)
+#define ESYNR1_AINNERSHARED  (ESYNR1_AINNERSHARED_MASK<< \
+                                                ESYNR1_AINNERSHARED_SHIFT)
+#define ESYNR1_APRIV         (ESYNR1_APRIV_MASK       << ESYNR1_APRIV_SHIFT)
+#define ESYNR1_APROTNS       (ESYNR1_APROTNS_MASK     << ESYNR1_APROTNS_SHIFT)
+#define ESYNR1_AINST         (ESYNR1_AINST_MASK       << ESYNR1_AINST_SHIFT)
+#define ESYNR1_AWRITE        (ESYNR1_AWRITE_MASK      << ESYNR1_AWRITE_SHIFT)
+#define ESYNR1_ABURST        (ESYNR1_ABURST_MASK      << ESYNR1_ABURST_SHIFT)
+#define ESYNR1_ALEN          (ESYNR1_ALEN_MASK        << ESYNR1_ALEN_SHIFT)
+#define ESYNR1_ASIZE         (ESYNR1_ASIZE_MASK       << ESYNR1_ASIZE_SHIFT)
+#define ESYNR1_ALOCK         (ESYNR1_ALOCK_MASK       << ESYNR1_ALOCK_SHIFT)
+#define ESYNR1_AOOO          (ESYNR1_AOOO_MASK        << ESYNR1_AOOO_SHIFT)
+#define ESYNR1_AFULL         (ESYNR1_AFULL_MASK       << ESYNR1_AFULL_SHIFT)
+#define ESYNR1_AC            (ESYNR1_AC_MASK          << ESYNR1_AC_SHIFT)
+#define ESYNR1_DCD           (ESYNR1_DCD_MASK         << ESYNR1_DCD_SHIFT)
+
+
+/* IDR */
+#define NM2VCBMT      (NM2VCBMT_MASK     << NM2VCBMT_SHIFT)
+#define HTW           (HTW_MASK          << HTW_SHIFT)
+#define HUM           (HUM_MASK          << HUM_SHIFT)
+#define TLBSIZE       (TLBSIZE_MASK      << TLBSIZE_SHIFT)
+#define NCB           (NCB_MASK          << NCB_SHIFT)
+#define NIRPT         (NIRPT_MASK        << NIRPT_SHIFT)
+
+
+/* M2VCBRn */
+#define VMID          (VMID_MASK         << VMID_SHIFT)
+#define CBNDX         (CBNDX_MASK        << CBNDX_SHIFT)
+#define BYPASSD       (BYPASSD_MASK      << BYPASSD_SHIFT)
+#define BPRCOSH       (BPRCOSH_MASK      << BPRCOSH_SHIFT)
+#define BPRCISH       (BPRCISH_MASK      << BPRCISH_SHIFT)
+#define BPRCNSH       (BPRCNSH_MASK      << BPRCNSH_SHIFT)
+#define BPSHCFG       (BPSHCFG_MASK      << BPSHCFG_SHIFT)
+#define NSCFG         (NSCFG_MASK        << NSCFG_SHIFT)
+#define BPMTCFG       (BPMTCFG_MASK      << BPMTCFG_SHIFT)
+#define BPMEMTYPE     (BPMEMTYPE_MASK    << BPMEMTYPE_SHIFT)
+
+
+/* REV */
+#define IDR_MINOR     (MINOR_MASK        << MINOR_SHIFT)
+#define IDR_MAJOR     (MAJOR_MASK        << MAJOR_SHIFT)
+
+
+/* TESTBUSCR */
+#define TBE           (TBE_MASK          << TBE_SHIFT)
+#define SPDMBE        (SPDMBE_MASK       << SPDMBE_SHIFT)
+#define WGSEL         (WGSEL_MASK        << WGSEL_SHIFT)
+#define TBLSEL        (TBLSEL_MASK       << TBLSEL_SHIFT)
+#define TBHSEL        (TBHSEL_MASK       << TBHSEL_SHIFT)
+#define SPDM0SEL      (SPDM0SEL_MASK     << SPDM0SEL_SHIFT)
+#define SPDM1SEL      (SPDM1SEL_MASK     << SPDM1SEL_SHIFT)
+#define SPDM2SEL      (SPDM2SEL_MASK     << SPDM2SEL_SHIFT)
+#define SPDM3SEL      (SPDM3SEL_MASK     << SPDM3SEL_SHIFT)
+
+
+/* TLBIVMID */
+#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
+
+
+/* TLBRSW */
+#define TLBRSW_INDEX  (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
+#define TLBBFBS       (TLBBFBS_MASK      << TLBBFBS_SHIFT)
+
+
+/* TLBTR0 */
+#define PR            (PR_MASK           << PR_SHIFT)
+#define PW            (PW_MASK           << PW_SHIFT)
+#define UR            (UR_MASK           << UR_SHIFT)
+#define UW            (UW_MASK           << UW_SHIFT)
+#define XN            (XN_MASK           << XN_SHIFT)
+#define NSDESC        (NSDESC_MASK       << NSDESC_SHIFT)
+#define ISH           (ISH_MASK          << ISH_SHIFT)
+#define SH            (SH_MASK           << SH_SHIFT)
+#define MT            (MT_MASK           << MT_SHIFT)
+#define DPSIZR        (DPSIZR_MASK       << DPSIZR_SHIFT)
+#define DPSIZC        (DPSIZC_MASK       << DPSIZC_SHIFT)
+
+
+/* TLBTR1 */
+#define TLBTR1_VMID   (TLBTR1_VMID_MASK  << TLBTR1_VMID_SHIFT)
+#define TLBTR1_PA     (TLBTR1_PA_MASK    << TLBTR1_PA_SHIFT)
+
+
+/* TLBTR2 */
+#define TLBTR2_ASID   (TLBTR2_ASID_MASK  << TLBTR2_ASID_SHIFT)
+#define TLBTR2_V      (TLBTR2_V_MASK     << TLBTR2_V_SHIFT)
+#define TLBTR2_NSTID  (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
+#define TLBTR2_NV     (TLBTR2_NV_MASK    << TLBTR2_NV_SHIFT)
+#define TLBTR2_VA     (TLBTR2_VA_MASK    << TLBTR2_VA_SHIFT)
+
+
+/* Context Register Fields */
+/* ACTLR */
+#define CFERE              (CFERE_MASK              << CFERE_SHIFT)
+#define CFEIE              (CFEIE_MASK              << CFEIE_SHIFT)
+#define PTSHCFG            (PTSHCFG_MASK            << PTSHCFG_SHIFT)
+#define RCOSH              (RCOSH_MASK              << RCOSH_SHIFT)
+#define RCISH              (RCISH_MASK              << RCISH_SHIFT)
+#define RCNSH              (RCNSH_MASK              << RCNSH_SHIFT)
+#define PRIVCFG            (PRIVCFG_MASK            << PRIVCFG_SHIFT)
+#define DNA                (DNA_MASK                << DNA_SHIFT)
+#define DNLV2PA            (DNLV2PA_MASK            << DNLV2PA_SHIFT)
+#define TLBMCFG            (TLBMCFG_MASK            << TLBMCFG_SHIFT)
+#define CFCFG              (CFCFG_MASK              << CFCFG_SHIFT)
+#define TIPCF              (TIPCF_MASK              << TIPCF_SHIFT)
+#define V2PCFG             (V2PCFG_MASK             << V2PCFG_SHIFT)
+#define HUME               (HUME_MASK               << HUME_SHIFT)
+#define PTMTCFG            (PTMTCFG_MASK            << PTMTCFG_SHIFT)
+#define PTMEMTYPE          (PTMEMTYPE_MASK          << PTMEMTYPE_SHIFT)
+
+
+/* BFBCR */
+#define BFBDFE             (BFBDFE_MASK             << BFBDFE_SHIFT)
+#define BFBSFE             (BFBSFE_MASK             << BFBSFE_SHIFT)
+#define SFVS               (SFVS_MASK               << SFVS_SHIFT)
+#define FLVIC              (FLVIC_MASK              << FLVIC_SHIFT)
+#define SLVIC              (SLVIC_MASK              << SLVIC_SHIFT)
+
+
+/* CONTEXTIDR */
+#define CONTEXTIDR_ASID    (CONTEXTIDR_ASID_MASK    << CONTEXTIDR_ASID_SHIFT)
+#define PROCID             (PROCID_MASK             << PROCID_SHIFT)
+
+
+/* FSR */
+#define TF                 (TF_MASK                 << TF_SHIFT)
+#define AFF                (AFF_MASK                << AFF_SHIFT)
+#define APF                (APF_MASK                << APF_SHIFT)
+#define TLBMF              (TLBMF_MASK              << TLBMF_SHIFT)
+#define HTWDEEF            (HTWDEEF_MASK            << HTWDEEF_SHIFT)
+#define HTWSEEF            (HTWSEEF_MASK            << HTWSEEF_SHIFT)
+#define MHF                (MHF_MASK                << MHF_SHIFT)
+#define SL                 (SL_MASK                 << SL_SHIFT)
+#define SS                 (SS_MASK                 << SS_SHIFT)
+#define MULTI              (MULTI_MASK              << MULTI_SHIFT)
+
+
+/* FSYNR0 */
+#define AMID               (AMID_MASK               << AMID_SHIFT)
+#define APID               (APID_MASK               << APID_SHIFT)
+#define ABID               (ABID_MASK               << ABID_SHIFT)
+#define ATID               (ATID_MASK               << ATID_SHIFT)
+
+
+/* FSYNR1 */
+#define AMEMTYPE           (AMEMTYPE_MASK           << AMEMTYPE_SHIFT)
+#define ASHARED            (ASHARED_MASK            << ASHARED_SHIFT)
+#define AINNERSHARED       (AINNERSHARED_MASK       << AINNERSHARED_SHIFT)
+#define APRIV              (APRIV_MASK              << APRIV_SHIFT)
+#define APROTNS            (APROTNS_MASK            << APROTNS_SHIFT)
+#define AINST              (AINST_MASK              << AINST_SHIFT)
+#define AWRITE             (AWRITE_MASK             << AWRITE_SHIFT)
+#define ABURST             (ABURST_MASK             << ABURST_SHIFT)
+#define ALEN               (ALEN_MASK               << ALEN_SHIFT)
+#define FSYNR1_ASIZE       (FSYNR1_ASIZE_MASK       << FSYNR1_ASIZE_SHIFT)
+#define ALOCK              (ALOCK_MASK              << ALOCK_SHIFT)
+#define AFULL              (AFULL_MASK              << AFULL_SHIFT)
+
+
+/* NMRR */
+#define ICPC0              (ICPC0_MASK              << ICPC0_SHIFT)
+#define ICPC1              (ICPC1_MASK              << ICPC1_SHIFT)
+#define ICPC2              (ICPC2_MASK              << ICPC2_SHIFT)
+#define ICPC3              (ICPC3_MASK              << ICPC3_SHIFT)
+#define ICPC4              (ICPC4_MASK              << ICPC4_SHIFT)
+#define ICPC5              (ICPC5_MASK              << ICPC5_SHIFT)
+#define ICPC6              (ICPC6_MASK              << ICPC6_SHIFT)
+#define ICPC7              (ICPC7_MASK              << ICPC7_SHIFT)
+#define OCPC0              (OCPC0_MASK              << OCPC0_SHIFT)
+#define OCPC1              (OCPC1_MASK              << OCPC1_SHIFT)
+#define OCPC2              (OCPC2_MASK              << OCPC2_SHIFT)
+#define OCPC3              (OCPC3_MASK              << OCPC3_SHIFT)
+#define OCPC4              (OCPC4_MASK              << OCPC4_SHIFT)
+#define OCPC5              (OCPC5_MASK              << OCPC5_SHIFT)
+#define OCPC6              (OCPC6_MASK              << OCPC6_SHIFT)
+#define OCPC7              (OCPC7_MASK              << OCPC7_SHIFT)
+
+
+/* PAR */
+#define FAULT              (FAULT_MASK              << FAULT_SHIFT)
+/* If a fault is present, these are the
+same as the fault fields in the FAR */
+#define FAULT_TF           (FAULT_TF_MASK           << FAULT_TF_SHIFT)
+#define FAULT_AFF          (FAULT_AFF_MASK          << FAULT_AFF_SHIFT)
+#define FAULT_APF          (FAULT_APF_MASK          << FAULT_APF_SHIFT)
+#define FAULT_TLBMF        (FAULT_TLBMF_MASK        << FAULT_TLBMF_SHIFT)
+#define FAULT_HTWDEEF      (FAULT_HTWDEEF_MASK      << FAULT_HTWDEEF_SHIFT)
+#define FAULT_HTWSEEF      (FAULT_HTWSEEF_MASK      << FAULT_HTWSEEF_SHIFT)
+#define FAULT_MHF          (FAULT_MHF_MASK          << FAULT_MHF_SHIFT)
+#define FAULT_SL           (FAULT_SL_MASK           << FAULT_SL_SHIFT)
+#define FAULT_SS           (FAULT_SS_MASK           << FAULT_SS_SHIFT)
+
+/* If NO fault is present, the following fields are in effect */
+/* (FAULT remains as before) */
+#define PAR_NOFAULT_SS     (PAR_NOFAULT_SS_MASK     << PAR_NOFAULT_SS_SHIFT)
+#define PAR_NOFAULT_MT     (PAR_NOFAULT_MT_MASK     << PAR_NOFAULT_MT_SHIFT)
+#define PAR_NOFAULT_SH     (PAR_NOFAULT_SH_MASK     << PAR_NOFAULT_SH_SHIFT)
+#define PAR_NOFAULT_NS     (PAR_NOFAULT_NS_MASK     << PAR_NOFAULT_NS_SHIFT)
+#define PAR_NOFAULT_NOS    (PAR_NOFAULT_NOS_MASK    << PAR_NOFAULT_NOS_SHIFT)
+#define PAR_NPFAULT_PA     (PAR_NPFAULT_PA_MASK     << PAR_NPFAULT_PA_SHIFT)
+
+
+/* PRRR */
+#define MTC0               (MTC0_MASK               << MTC0_SHIFT)
+#define MTC1               (MTC1_MASK               << MTC1_SHIFT)
+#define MTC2               (MTC2_MASK               << MTC2_SHIFT)
+#define MTC3               (MTC3_MASK               << MTC3_SHIFT)
+#define MTC4               (MTC4_MASK               << MTC4_SHIFT)
+#define MTC5               (MTC5_MASK               << MTC5_SHIFT)
+#define MTC6               (MTC6_MASK               << MTC6_SHIFT)
+#define MTC7               (MTC7_MASK               << MTC7_SHIFT)
+#define SHDSH0             (SHDSH0_MASK             << SHDSH0_SHIFT)
+#define SHDSH1             (SHDSH1_MASK             << SHDSH1_SHIFT)
+#define SHNMSH0            (SHNMSH0_MASK            << SHNMSH0_SHIFT)
+#define SHNMSH1            (SHNMSH1_MASK            << SHNMSH1_SHIFT)
+#define NOS0               (NOS0_MASK               << NOS0_SHIFT)
+#define NOS1               (NOS1_MASK               << NOS1_SHIFT)
+#define NOS2               (NOS2_MASK               << NOS2_SHIFT)
+#define NOS3               (NOS3_MASK               << NOS3_SHIFT)
+#define NOS4               (NOS4_MASK               << NOS4_SHIFT)
+#define NOS5               (NOS5_MASK               << NOS5_SHIFT)
+#define NOS6               (NOS6_MASK               << NOS6_SHIFT)
+#define NOS7               (NOS7_MASK               << NOS7_SHIFT)
+
+
+/* RESUME */
+#define TNR                (TNR_MASK                << TNR_SHIFT)
+
+
+/* SCTLR */
+#define M                  (M_MASK                  << M_SHIFT)
+#define TRE                (TRE_MASK                << TRE_SHIFT)
+#define AFE                (AFE_MASK                << AFE_SHIFT)
+#define HAF                (HAF_MASK                << HAF_SHIFT)
+#define BE                 (BE_MASK                 << BE_SHIFT)
+#define AFFD               (AFFD_MASK               << AFFD_SHIFT)
+
+
+/* TLBIASID */
+#define TLBIASID_ASID      (TLBIASID_ASID_MASK      << TLBIASID_ASID_SHIFT)
+
+
+/* TLBIVA */
+#define TLBIVA_ASID        (TLBIVA_ASID_MASK        << TLBIVA_ASID_SHIFT)
+#define TLBIVA_VA          (TLBIVA_VA_MASK          << TLBIVA_VA_SHIFT)
+
+
+/* TLBIVAA */
+#define TLBIVAA_VA         (TLBIVAA_VA_MASK         << TLBIVAA_VA_SHIFT)
+
+
+/* TLBLCKR */
+#define LKE                (LKE_MASK                << LKE_SHIFT)
+#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
+#define TLBIASIDCFG        (TLBIASIDCFG_MASK        << TLBIASIDCFG_SHIFT)
+#define TLBIVAACFG         (TLBIVAACFG_MASK         << TLBIVAACFG_SHIFT)
+#define FLOOR              (FLOOR_MASK              << FLOOR_SHIFT)
+#define VICTIM             (VICTIM_MASK             << VICTIM_SHIFT)
+
+
+/* TTBCR */
+#define N                  (N_MASK                  << N_SHIFT)
+#define PD0                (PD0_MASK                << PD0_SHIFT)
+#define PD1                (PD1_MASK                << PD1_SHIFT)
+
+
+/* TTBR0 */
+#define TTBR0_IRGNH        (TTBR0_IRGNH_MASK        << TTBR0_IRGNH_SHIFT)
+#define TTBR0_SH           (TTBR0_SH_MASK           << TTBR0_SH_SHIFT)
+#define TTBR0_ORGN         (TTBR0_ORGN_MASK         << TTBR0_ORGN_SHIFT)
+#define TTBR0_NOS          (TTBR0_NOS_MASK          << TTBR0_NOS_SHIFT)
+#define TTBR0_IRGNL        (TTBR0_IRGNL_MASK        << TTBR0_IRGNL_SHIFT)
+#define TTBR0_PA           (TTBR0_PA_MASK           << TTBR0_PA_SHIFT)
+
+
+/* TTBR1 */
+#define TTBR1_IRGNH        (TTBR1_IRGNH_MASK        << TTBR1_IRGNH_SHIFT)
+#define TTBR1_SH           (TTBR1_SH_MASK           << TTBR1_SH_SHIFT)
+#define TTBR1_ORGN         (TTBR1_ORGN_MASK         << TTBR1_ORGN_SHIFT)
+#define TTBR1_NOS          (TTBR1_NOS_MASK          << TTBR1_NOS_SHIFT)
+#define TTBR1_IRGNL        (TTBR1_IRGNL_MASK        << TTBR1_IRGNL_SHIFT)
+#define TTBR1_PA           (TTBR1_PA_MASK           << TTBR1_PA_SHIFT)
+
+
+/* V2PSR */
+#define HIT                (HIT_MASK                << HIT_SHIFT)
+#define INDEX              (INDEX_MASK              << INDEX_SHIFT)
+
+
+/* V2Pxx */
+#define V2Pxx_INDEX        (V2Pxx_INDEX_MASK        << V2Pxx_INDEX_SHIFT)
+#define V2Pxx_VA           (V2Pxx_VA_MASK           << V2Pxx_VA_SHIFT)
+
+
+/* Global Register Masks */
+/* CBACRn */
+#define RWVMID_MASK               0x1F
+#define RWE_MASK                  0x01
+#define RWGE_MASK                 0x01
+#define CBVMID_MASK               0x1F
+#define IRPTNDX_MASK              0xFF
+
+
+/* CR */
+#define RPUE_MASK                 0x01
+#define RPUERE_MASK               0x01
+#define RPUEIE_MASK               0x01
+#define DCDEE_MASK                0x01
+#define CLIENTPD_MASK             0x01
+#define STALLD_MASK               0x01
+#define TLBLKCRWE_MASK            0x01
+#define CR_TLBIALLCFG_MASK        0x01
+#define TLBIVMIDCFG_MASK          0x01
+#define CR_HUME_MASK              0x01
+
+
+/* ESR */
+#define CFG_MASK                  0x01
+#define BYPASS_MASK               0x01
+#define ESR_MULTI_MASK            0x01
+
+
+/* ESYNR0 */
+#define ESYNR0_AMID_MASK          0xFF
+#define ESYNR0_APID_MASK          0x1F
+#define ESYNR0_ABID_MASK          0x07
+#define ESYNR0_AVMID_MASK         0x1F
+#define ESYNR0_ATID_MASK          0xFF
+
+
+/* ESYNR1 */
+#define ESYNR1_AMEMTYPE_MASK             0x07
+#define ESYNR1_ASHARED_MASK              0x01
+#define ESYNR1_AINNERSHARED_MASK         0x01
+#define ESYNR1_APRIV_MASK                0x01
+#define ESYNR1_APROTNS_MASK              0x01
+#define ESYNR1_AINST_MASK                0x01
+#define ESYNR1_AWRITE_MASK               0x01
+#define ESYNR1_ABURST_MASK               0x01
+#define ESYNR1_ALEN_MASK                 0x0F
+#define ESYNR1_ASIZE_MASK                0x01
+#define ESYNR1_ALOCK_MASK                0x03
+#define ESYNR1_AOOO_MASK                 0x01
+#define ESYNR1_AFULL_MASK                0x01
+#define ESYNR1_AC_MASK                   0x01
+#define ESYNR1_DCD_MASK                  0x01
+
+
+/* IDR */
+#define NM2VCBMT_MASK             0x1FF
+#define HTW_MASK                  0x01
+#define HUM_MASK                  0x01
+#define TLBSIZE_MASK              0x0F
+#define NCB_MASK                  0xFF
+#define NIRPT_MASK                0xFF
+
+
+/* M2VCBRn */
+#define VMID_MASK                 0x1F
+#define CBNDX_MASK                0xFF
+#define BYPASSD_MASK              0x01
+#define BPRCOSH_MASK              0x01
+#define BPRCISH_MASK              0x01
+#define BPRCNSH_MASK              0x01
+#define BPSHCFG_MASK              0x03
+#define NSCFG_MASK                0x03
+#define BPMTCFG_MASK              0x01
+#define BPMEMTYPE_MASK            0x07
+
+
+/* REV */
+#define MINOR_MASK                0x0F
+#define MAJOR_MASK                0x0F
+
+
+/* TESTBUSCR */
+#define TBE_MASK                  0x01
+#define SPDMBE_MASK               0x01
+#define WGSEL_MASK                0x03
+#define TBLSEL_MASK               0x03
+#define TBHSEL_MASK               0x03
+#define SPDM0SEL_MASK             0x0F
+#define SPDM1SEL_MASK             0x0F
+#define SPDM2SEL_MASK             0x0F
+#define SPDM3SEL_MASK             0x0F
+
+
+/* TLBIMID */
+#define TLBIVMID_VMID_MASK        0x1F
+
+
+/* TLBRSW */
+#define TLBRSW_INDEX_MASK         0xFF
+#define TLBBFBS_MASK              0x03
+
+
+/* TLBTR0 */
+#define PR_MASK                   0x01
+#define PW_MASK                   0x01
+#define UR_MASK                   0x01
+#define UW_MASK                   0x01
+#define XN_MASK                   0x01
+#define NSDESC_MASK               0x01
+#define ISH_MASK                  0x01
+#define SH_MASK                   0x01
+#define MT_MASK                   0x07
+#define DPSIZR_MASK               0x07
+#define DPSIZC_MASK               0x07
+
+
+/* TLBTR1 */
+#define TLBTR1_VMID_MASK          0x1F
+#define TLBTR1_PA_MASK            0x000FFFFF
+
+
+/* TLBTR2 */
+#define TLBTR2_ASID_MASK          0xFF
+#define TLBTR2_V_MASK             0x01
+#define TLBTR2_NSTID_MASK         0x01
+#define TLBTR2_NV_MASK            0x01
+#define TLBTR2_VA_MASK            0x000FFFFF
+
+
+/* Global Register Shifts */
+/* CBACRn */
+#define RWVMID_SHIFT             0
+#define RWE_SHIFT                8
+#define RWGE_SHIFT               9
+#define CBVMID_SHIFT             16
+#define IRPTNDX_SHIFT            24
+
+
+/* CR */
+#define RPUE_SHIFT               0
+#define RPUERE_SHIFT             1
+#define RPUEIE_SHIFT             2
+#define DCDEE_SHIFT              3
+#define CLIENTPD_SHIFT           4
+#define STALLD_SHIFT             5
+#define TLBLKCRWE_SHIFT          6
+#define CR_TLBIALLCFG_SHIFT      7
+#define TLBIVMIDCFG_SHIFT        8
+#define CR_HUME_SHIFT            9
+
+
+/* ESR */
+#define CFG_SHIFT                0
+#define BYPASS_SHIFT             1
+#define ESR_MULTI_SHIFT          31
+
+
+/* ESYNR0 */
+#define ESYNR0_AMID_SHIFT        0
+#define ESYNR0_APID_SHIFT        8
+#define ESYNR0_ABID_SHIFT        13
+#define ESYNR0_AVMID_SHIFT       16
+#define ESYNR0_ATID_SHIFT        24
+
+
+/* ESYNR1 */
+#define ESYNR1_AMEMTYPE_SHIFT           0
+#define ESYNR1_ASHARED_SHIFT            3
+#define ESYNR1_AINNERSHARED_SHIFT       4
+#define ESYNR1_APRIV_SHIFT              5
+#define ESYNR1_APROTNS_SHIFT            6
+#define ESYNR1_AINST_SHIFT              7
+#define ESYNR1_AWRITE_SHIFT             8
+#define ESYNR1_ABURST_SHIFT             10
+#define ESYNR1_ALEN_SHIFT               12
+#define ESYNR1_ASIZE_SHIFT              16
+#define ESYNR1_ALOCK_SHIFT              20
+#define ESYNR1_AOOO_SHIFT               22
+#define ESYNR1_AFULL_SHIFT              24
+#define ESYNR1_AC_SHIFT                 30
+#define ESYNR1_DCD_SHIFT                31
+
+
+/* IDR */
+#define NM2VCBMT_SHIFT           0
+#define HTW_SHIFT                9
+#define HUM_SHIFT                10
+#define TLBSIZE_SHIFT            12
+#define NCB_SHIFT                16
+#define NIRPT_SHIFT              24
+
+
+/* M2VCBRn */
+#define VMID_SHIFT               0
+#define CBNDX_SHIFT              8
+#define BYPASSD_SHIFT            16
+#define BPRCOSH_SHIFT            17
+#define BPRCISH_SHIFT            18
+#define BPRCNSH_SHIFT            19
+#define BPSHCFG_SHIFT            20
+#define NSCFG_SHIFT              22
+#define BPMTCFG_SHIFT            24
+#define BPMEMTYPE_SHIFT          25
+
+
+/* REV */
+#define MINOR_SHIFT              0
+#define MAJOR_SHIFT              4
+
+
+/* TESTBUSCR */
+#define TBE_SHIFT                0
+#define SPDMBE_SHIFT             1
+#define WGSEL_SHIFT              8
+#define TBLSEL_SHIFT             12
+#define TBHSEL_SHIFT             14
+#define SPDM0SEL_SHIFT           16
+#define SPDM1SEL_SHIFT           20
+#define SPDM2SEL_SHIFT           24
+#define SPDM3SEL_SHIFT           28
+
+
+/* TLBIMID */
+#define TLBIVMID_VMID_SHIFT      0
+
+
+/* TLBRSW */
+#define TLBRSW_INDEX_SHIFT       0
+#define TLBBFBS_SHIFT            8
+
+
+/* TLBTR0 */
+#define PR_SHIFT                 0
+#define PW_SHIFT                 1
+#define UR_SHIFT                 2
+#define UW_SHIFT                 3
+#define XN_SHIFT                 4
+#define NSDESC_SHIFT             6
+#define ISH_SHIFT                7
+#define SH_SHIFT                 8
+#define MT_SHIFT                 9
+#define DPSIZR_SHIFT             16
+#define DPSIZC_SHIFT             20
+
+
+/* TLBTR1 */
+#define TLBTR1_VMID_SHIFT        0
+#define TLBTR1_PA_SHIFT          12
+
+
+/* TLBTR2 */
+#define TLBTR2_ASID_SHIFT        0
+#define TLBTR2_V_SHIFT           8
+#define TLBTR2_NSTID_SHIFT       9
+#define TLBTR2_NV_SHIFT          10
+#define TLBTR2_VA_SHIFT          12
+
+
+/* Context Register Masks */
+/* ACTLR */
+#define CFERE_MASK                       0x01
+#define CFEIE_MASK                       0x01
+#define PTSHCFG_MASK                     0x03
+#define RCOSH_MASK                       0x01
+#define RCISH_MASK                       0x01
+#define RCNSH_MASK                       0x01
+#define PRIVCFG_MASK                     0x03
+#define DNA_MASK                         0x01
+#define DNLV2PA_MASK                     0x01
+#define TLBMCFG_MASK                     0x03
+#define CFCFG_MASK                       0x01
+#define TIPCF_MASK                       0x01
+#define V2PCFG_MASK                      0x03
+#define HUME_MASK                        0x01
+#define PTMTCFG_MASK                     0x01
+#define PTMEMTYPE_MASK                   0x07
+
+
+/* BFBCR */
+#define BFBDFE_MASK                      0x01
+#define BFBSFE_MASK                      0x01
+#define SFVS_MASK                        0x01
+#define FLVIC_MASK                       0x0F
+#define SLVIC_MASK                       0x0F
+
+
+/* CONTEXTIDR */
+#define CONTEXTIDR_ASID_MASK             0xFF
+#define PROCID_MASK                      0x00FFFFFF
+
+
+/* FSR */
+#define TF_MASK                          0x01
+#define AFF_MASK                         0x01
+#define APF_MASK                         0x01
+#define TLBMF_MASK                       0x01
+#define HTWDEEF_MASK                     0x01
+#define HTWSEEF_MASK                     0x01
+#define MHF_MASK                         0x01
+#define SL_MASK                          0x01
+#define SS_MASK                          0x01
+#define MULTI_MASK                       0x01
+
+
+/* FSYNR0 */
+#define AMID_MASK                        0xFF
+#define APID_MASK                        0x1F
+#define ABID_MASK                        0x07
+#define ATID_MASK                        0xFF
+
+
+/* FSYNR1 */
+#define AMEMTYPE_MASK                    0x07
+#define ASHARED_MASK                     0x01
+#define AINNERSHARED_MASK                0x01
+#define APRIV_MASK                       0x01
+#define APROTNS_MASK                     0x01
+#define AINST_MASK                       0x01
+#define AWRITE_MASK                      0x01
+#define ABURST_MASK                      0x01
+#define ALEN_MASK                        0x0F
+#define FSYNR1_ASIZE_MASK                0x07
+#define ALOCK_MASK                       0x03
+#define AFULL_MASK                       0x01
+
+
+/* NMRR */
+#define ICPC0_MASK                       0x03
+#define ICPC1_MASK                       0x03
+#define ICPC2_MASK                       0x03
+#define ICPC3_MASK                       0x03
+#define ICPC4_MASK                       0x03
+#define ICPC5_MASK                       0x03
+#define ICPC6_MASK                       0x03
+#define ICPC7_MASK                       0x03
+#define OCPC0_MASK                       0x03
+#define OCPC1_MASK                       0x03
+#define OCPC2_MASK                       0x03
+#define OCPC3_MASK                       0x03
+#define OCPC4_MASK                       0x03
+#define OCPC5_MASK                       0x03
+#define OCPC6_MASK                       0x03
+#define OCPC7_MASK                       0x03
+
+
+/* PAR */
+#define FAULT_MASK                       0x01
+/* If a fault is present, these are the
+same as the fault fields in the FAR */
+#define FAULT_TF_MASK                    0x01
+#define FAULT_AFF_MASK                   0x01
+#define FAULT_APF_MASK                   0x01
+#define FAULT_TLBMF_MASK                 0x01
+#define FAULT_HTWDEEF_MASK               0x01
+#define FAULT_HTWSEEF_MASK               0x01
+#define FAULT_MHF_MASK                   0x01
+#define FAULT_SL_MASK                    0x01
+#define FAULT_SS_MASK                    0x01
+
+/* If NO fault is present, the following
+ * fields are in effect
+ * (FAULT remains as before) */
+#define PAR_NOFAULT_SS_MASK              0x01
+#define PAR_NOFAULT_MT_MASK              0x07
+#define PAR_NOFAULT_SH_MASK              0x01
+#define PAR_NOFAULT_NS_MASK              0x01
+#define PAR_NOFAULT_NOS_MASK             0x01
+#define PAR_NPFAULT_PA_MASK              0x000FFFFF
+
+
+/* PRRR */
+#define MTC0_MASK                        0x03
+#define MTC1_MASK                        0x03
+#define MTC2_MASK                        0x03
+#define MTC3_MASK                        0x03
+#define MTC4_MASK                        0x03
+#define MTC5_MASK                        0x03
+#define MTC6_MASK                        0x03
+#define MTC7_MASK                        0x03
+#define SHDSH0_MASK                      0x01
+#define SHDSH1_MASK                      0x01
+#define SHNMSH0_MASK                     0x01
+#define SHNMSH1_MASK                     0x01
+#define NOS0_MASK                        0x01
+#define NOS1_MASK                        0x01
+#define NOS2_MASK                        0x01
+#define NOS3_MASK                        0x01
+#define NOS4_MASK                        0x01
+#define NOS5_MASK                        0x01
+#define NOS6_MASK                        0x01
+#define NOS7_MASK                        0x01
+
+
+/* RESUME */
+#define TNR_MASK                         0x01
+
+
+/* SCTLR */
+#define M_MASK                           0x01
+#define TRE_MASK                         0x01
+#define AFE_MASK                         0x01
+#define HAF_MASK                         0x01
+#define BE_MASK                          0x01
+#define AFFD_MASK                        0x01
+
+
+/* TLBIASID */
+#define TLBIASID_ASID_MASK               0xFF
+
+
+/* TLBIVA */
+#define TLBIVA_ASID_MASK                 0xFF
+#define TLBIVA_VA_MASK                   0x000FFFFF
+
+
+/* TLBIVAA */
+#define TLBIVAA_VA_MASK                  0x000FFFFF
+
+
+/* TLBLCKR */
+#define LKE_MASK                         0x01
+#define TLBLCKR_TLBIALLCFG_MASK          0x01
+#define TLBIASIDCFG_MASK                 0x01
+#define TLBIVAACFG_MASK                  0x01
+#define FLOOR_MASK                       0xFF
+#define VICTIM_MASK                      0xFF
+
+
+/* TTBCR */
+#define N_MASK                           0x07
+#define PD0_MASK                         0x01
+#define PD1_MASK                         0x01
+
+
+/* TTBR0 */
+#define TTBR0_IRGNH_MASK                 0x01
+#define TTBR0_SH_MASK                    0x01
+#define TTBR0_ORGN_MASK                  0x03
+#define TTBR0_NOS_MASK                   0x01
+#define TTBR0_IRGNL_MASK                 0x01
+#define TTBR0_PA_MASK                    0x0003FFFF
+
+
+/* TTBR1 */
+#define TTBR1_IRGNH_MASK                 0x01
+#define TTBR1_SH_MASK                    0x01
+#define TTBR1_ORGN_MASK                  0x03
+#define TTBR1_NOS_MASK                   0x01
+#define TTBR1_IRGNL_MASK                 0x01
+#define TTBR1_PA_MASK                    0x0003FFFF
+
+
+/* V2PSR */
+#define HIT_MASK                         0x01
+#define INDEX_MASK                       0xFF
+
+
+/* V2Pxx */
+#define V2Pxx_INDEX_MASK                 0xFF
+#define V2Pxx_VA_MASK                    0x000FFFFF
+
+
+/* Context Register Shifts */
+/* ACTLR */
+#define CFERE_SHIFT                    0
+#define CFEIE_SHIFT                    1
+#define PTSHCFG_SHIFT                  2
+#define RCOSH_SHIFT                    4
+#define RCISH_SHIFT                    5
+#define RCNSH_SHIFT                    6
+#define PRIVCFG_SHIFT                  8
+#define DNA_SHIFT                      10
+#define DNLV2PA_SHIFT                  11
+#define TLBMCFG_SHIFT                  12
+#define CFCFG_SHIFT                    14
+#define TIPCF_SHIFT                    15
+#define V2PCFG_SHIFT                   16
+#define HUME_SHIFT                     18
+#define PTMTCFG_SHIFT                  20
+#define PTMEMTYPE_SHIFT                21
+
+
+/* BFBCR */
+#define BFBDFE_SHIFT                   0
+#define BFBSFE_SHIFT                   1
+#define SFVS_SHIFT                     2
+#define FLVIC_SHIFT                    4
+#define SLVIC_SHIFT                    8
+
+
+/* CONTEXTIDR */
+#define CONTEXTIDR_ASID_SHIFT          0
+#define PROCID_SHIFT                   8
+
+
+/* FSR */
+#define TF_SHIFT                       1
+#define AFF_SHIFT                      2
+#define APF_SHIFT                      3
+#define TLBMF_SHIFT                    4
+#define HTWDEEF_SHIFT                  5
+#define HTWSEEF_SHIFT                  6
+#define MHF_SHIFT                      7
+#define SL_SHIFT                       16
+#define SS_SHIFT                       30
+#define MULTI_SHIFT                    31
+
+
+/* FSYNR0 */
+#define AMID_SHIFT                     0
+#define APID_SHIFT                     8
+#define ABID_SHIFT                     13
+#define ATID_SHIFT                     24
+
+
+/* FSYNR1 */
+#define AMEMTYPE_SHIFT                 0
+#define ASHARED_SHIFT                  3
+#define AINNERSHARED_SHIFT             4
+#define APRIV_SHIFT                    5
+#define APROTNS_SHIFT                  6
+#define AINST_SHIFT                    7
+#define AWRITE_SHIFT                   8
+#define ABURST_SHIFT                   10
+#define ALEN_SHIFT                     12
+#define FSYNR1_ASIZE_SHIFT             16
+#define ALOCK_SHIFT                    20
+#define AFULL_SHIFT                    24
+
+
+/* NMRR */
+#define ICPC0_SHIFT                    0
+#define ICPC1_SHIFT                    2
+#define ICPC2_SHIFT                    4
+#define ICPC3_SHIFT                    6
+#define ICPC4_SHIFT                    8
+#define ICPC5_SHIFT                    10
+#define ICPC6_SHIFT                    12
+#define ICPC7_SHIFT                    14
+#define OCPC0_SHIFT                    16
+#define OCPC1_SHIFT                    18
+#define OCPC2_SHIFT                    20
+#define OCPC3_SHIFT                    22
+#define OCPC4_SHIFT                    24
+#define OCPC5_SHIFT                    26
+#define OCPC6_SHIFT                    28
+#define OCPC7_SHIFT                    30
+
+
+/* PAR */
+#define FAULT_SHIFT                    0
+/* If a fault is present, these are the
+same as the fault fields in the FAR */
+#define FAULT_TF_SHIFT                 1
+#define FAULT_AFF_SHIFT                2
+#define FAULT_APF_SHIFT                3
+#define FAULT_TLBMF_SHIFT              4
+#define FAULT_HTWDEEF_SHIFT            5
+#define FAULT_HTWSEEF_SHIFT            6
+#define FAULT_MHF_SHIFT                7
+#define FAULT_SL_SHIFT                 16
+#define FAULT_SS_SHIFT                 30
+
+/* If NO fault is present, the following
+ * fields are in effect
+ * (FAULT remains as before) */
+#define PAR_NOFAULT_SS_SHIFT           1
+#define PAR_NOFAULT_MT_SHIFT           4
+#define PAR_NOFAULT_SH_SHIFT           7
+#define PAR_NOFAULT_NS_SHIFT           9
+#define PAR_NOFAULT_NOS_SHIFT          10
+#define PAR_NPFAULT_PA_SHIFT           12
+
+
+/* PRRR */
+#define MTC0_SHIFT                     0
+#define MTC1_SHIFT                     2
+#define MTC2_SHIFT                     4
+#define MTC3_SHIFT                     6
+#define MTC4_SHIFT                     8
+#define MTC5_SHIFT                     10
+#define MTC6_SHIFT                     12
+#define MTC7_SHIFT                     14
+#define SHDSH0_SHIFT                   16
+#define SHDSH1_SHIFT                   17
+#define SHNMSH0_SHIFT                  18
+#define SHNMSH1_SHIFT                  19
+#define NOS0_SHIFT                     24
+#define NOS1_SHIFT                     25
+#define NOS2_SHIFT                     26
+#define NOS3_SHIFT                     27
+#define NOS4_SHIFT                     28
+#define NOS5_SHIFT                     29
+#define NOS6_SHIFT                     30
+#define NOS7_SHIFT                     31
+
+
+/* RESUME */
+#define TNR_SHIFT                      0
+
+
+/* SCTLR */
+#define M_SHIFT                        0
+#define TRE_SHIFT                      1
+#define AFE_SHIFT                      2
+#define HAF_SHIFT                      3
+#define BE_SHIFT                       4
+#define AFFD_SHIFT                     5
+
+
+/* TLBIASID */
+#define TLBIASID_ASID_SHIFT            0
+
+
+/* TLBIVA */
+#define TLBIVA_ASID_SHIFT              0
+#define TLBIVA_VA_SHIFT                12
+
+
+/* TLBIVAA */
+#define TLBIVAA_VA_SHIFT               12
+
+
+/* TLBLCKR */
+#define LKE_SHIFT                      0
+#define TLBLCKR_TLBIALLCFG_SHIFT       1
+#define TLBIASIDCFG_SHIFT              2
+#define TLBIVAACFG_SHIFT               3
+#define FLOOR_SHIFT                    8
+#define VICTIM_SHIFT                   8
+
+
+/* TTBCR */
+#define N_SHIFT                        3
+#define PD0_SHIFT                      4
+#define PD1_SHIFT                      5
+
+
+/* TTBR0 */
+#define TTBR0_IRGNH_SHIFT              0
+#define TTBR0_SH_SHIFT                 1
+#define TTBR0_ORGN_SHIFT               3
+#define TTBR0_NOS_SHIFT                5
+#define TTBR0_IRGNL_SHIFT              6
+#define TTBR0_PA_SHIFT                 14
+
+
+/* TTBR1 */
+#define TTBR1_IRGNH_SHIFT              0
+#define TTBR1_SH_SHIFT                 1
+#define TTBR1_ORGN_SHIFT               3
+#define TTBR1_NOS_SHIFT                5
+#define TTBR1_IRGNL_SHIFT              6
+#define TTBR1_PA_SHIFT                 14
+
+
+/* V2PSR */
+#define HIT_SHIFT                      0
+#define INDEX_SHIFT                    8
+
+
+/* V2Pxx */
+#define V2Pxx_INDEX_SHIFT              0
+#define V2Pxx_VA_SHIFT                 12
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
new file mode 100644
index 00000000000..36074cfc9ad
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -0,0 +1,253 @@
+/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8X60_H
+#define __ASM_ARCH_MSM_IRQS_8X60_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_DEBUG_TIMER_EXP                     (GIC_PPI_START + 0)
+#define INT_GP_TIMER_EXP                        (GIC_PPI_START + 1)
+#define INT_GP_TIMER2_EXP                       (GIC_PPI_START + 2)
+#define WDT0_ACCSCSSNBARK_INT                   (GIC_PPI_START + 3)
+#define WDT1_ACCSCSSNBARK_INT                   (GIC_PPI_START + 4)
+#define AVS_SVICINT                             (GIC_PPI_START + 5)
+#define AVS_SVICINTSWDONE                       (GIC_PPI_START + 6)
+#define CPU_DBGCPUXCOMMRXFULL                   (GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMTXEMPTY                  (GIC_PPI_START + 8)
+#define CPU_SICCPUXPERFMONIRPTREQ               (GIC_PPI_START + 9)
+#define SC_AVSCPUXDOWN                          (GIC_PPI_START + 10)
+#define SC_AVSCPUXUP                            (GIC_PPI_START + 11)
+#define SC_SICCPUXACGIRPTREQ                    (GIC_PPI_START + 12)
+/* PPI 13 to 15 are unused */
+
+
+#define SC_SICMPUIRPTREQ                        (GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ                         (GIC_SPI_START + 1)
+#define SC_SICL2ACGIRPTREQ                      (GIC_SPI_START + 2)
+#define NC                                      (GIC_SPI_START + 3)
+#define TLMM_SCSS_DIR_CONN_IRQ_0                (GIC_SPI_START + 4)
+#define TLMM_SCSS_DIR_CONN_IRQ_1                (GIC_SPI_START + 5)
+#define TLMM_SCSS_DIR_CONN_IRQ_2                (GIC_SPI_START + 6)
+#define TLMM_SCSS_DIR_CONN_IRQ_3                (GIC_SPI_START + 7)
+#define TLMM_SCSS_DIR_CONN_IRQ_4                (GIC_SPI_START + 8)
+#define TLMM_SCSS_DIR_CONN_IRQ_5                (GIC_SPI_START + 9)
+#define TLMM_SCSS_DIR_CONN_IRQ_6                (GIC_SPI_START + 10)
+#define TLMM_SCSS_DIR_CONN_IRQ_7                (GIC_SPI_START + 11)
+#define TLMM_SCSS_DIR_CONN_IRQ_8                (GIC_SPI_START + 12)
+#define TLMM_SCSS_DIR_CONN_IRQ_9                (GIC_SPI_START + 13)
+#define PM8058_SEC_IRQ_N                        (GIC_SPI_START + 14)
+#define PM8901_SEC_IRQ_N                        (GIC_SPI_START + 15)
+#define TLMM_SCSS_SUMMARY_IRQ                   (GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ                           (GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ                           (GIC_SPI_START + 18)
+#define RPM_SCSS_CPU0_GP_HIGH_IRQ               (GIC_SPI_START + 19)
+#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ             (GIC_SPI_START + 20)
+#define RPM_SCSS_CPU0_GP_LOW_IRQ                (GIC_SPI_START + 21)
+#define RPM_SCSS_CPU0_WAKE_UP_IRQ               (GIC_SPI_START + 22)
+#define RPM_SCSS_CPU1_GP_HIGH_IRQ               (GIC_SPI_START + 23)
+#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ             (GIC_SPI_START + 24)
+#define RPM_SCSS_CPU1_GP_LOW_IRQ                (GIC_SPI_START + 25)
+#define RPM_SCSS_CPU1_WAKE_UP_IRQ               (GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_INT              (GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_INT          (GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_INT              (GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_INT          (GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ                      (GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ                      (GIC_SPI_START + 32)
+#define MARM_FIQ                                (GIC_SPI_START + 33)
+#define MARM_IRQ                                (GIC_SPI_START + 34)
+#define MARM_L2CC_IRQ                           (GIC_SPI_START + 35)
+#define MARM_WDOG_EXPIRED                       (GIC_SPI_START + 36)
+#define MARM_SCSS_GP_IRQ_0                      (GIC_SPI_START + 37)
+#define MARM_SCSS_GP_IRQ_1                      (GIC_SPI_START + 38)
+#define MARM_SCSS_GP_IRQ_2                      (GIC_SPI_START + 39)
+#define MARM_SCSS_GP_IRQ_3                      (GIC_SPI_START + 40)
+#define MARM_SCSS_GP_IRQ_4                      (GIC_SPI_START + 41)
+#define MARM_SCSS_GP_IRQ_5                      (GIC_SPI_START + 42)
+#define MARM_SCSS_GP_IRQ_6                      (GIC_SPI_START + 43)
+#define MARM_SCSS_GP_IRQ_7                      (GIC_SPI_START + 44)
+#define MARM_SCSS_GP_IRQ_8                      (GIC_SPI_START + 45)
+#define MARM_SCSS_GP_IRQ_9                      (GIC_SPI_START + 46)
+#define VPE_IRQ                                 (GIC_SPI_START + 47)
+#define VFE_IRQ                                 (GIC_SPI_START + 48)
+#define VCODEC_IRQ                              (GIC_SPI_START + 49)
+#define TV_ENC_IRQ                              (GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ          (GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ          (GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ               (GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ              (GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ              (GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ             (GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ             (GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ             (GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ            (GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 72)
+#define ROT_IRQ                                 (GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ                         (GIC_SPI_START + 74)
+#define MDP_IRQ                                 (GIC_SPI_START + 75)
+#define JPEGD_IRQ                               (GIC_SPI_START + 76)
+#define JPEG_IRQ                                (GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ                           (GIC_SPI_START + 78)
+#define HDMI_IRQ                                (GIC_SPI_START + 79)
+#define GFX3D_IRQ                               (GIC_SPI_START + 80)
+#define GFX2D0_IRQ                              (GIC_SPI_START + 81)
+#define DSI_IRQ                                 (GIC_SPI_START + 82)
+#define CSI_1_IRQ                               (GIC_SPI_START + 83)
+#define CSI_0_IRQ                               (GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ            (GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ                     (GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED                 (GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ                   (GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ                (GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ                  (GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ                            (GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ                          (GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ                         (GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ                         (GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ                            (GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ                            (GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ                            (GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ                            (GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ                          (GIC_SPI_START + 99)
+#define USB1_HS_IRQ                             (GIC_SPI_START + 100)
+#define SDC4_IRQ_0                              (GIC_SPI_START + 101)
+#define SDC3_IRQ_0                              (GIC_SPI_START + 102)
+#define SDC2_IRQ_0                              (GIC_SPI_START + 103)
+#define SDC1_IRQ_0                              (GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ                         (GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ                        (GIC_SPI_START + 106)
+#define SPS_MTI_0                               (GIC_SPI_START + 107)
+#define SPS_MTI_1                               (GIC_SPI_START + 108)
+#define SPS_MTI_2                               (GIC_SPI_START + 109)
+#define SPS_MTI_3                               (GIC_SPI_START + 110)
+#define SPS_MTI_4                               (GIC_SPI_START + 111)
+#define SPS_MTI_5                               (GIC_SPI_START + 112)
+#define SPS_MTI_6                               (GIC_SPI_START + 113)
+#define SPS_MTI_7                               (GIC_SPI_START + 114)
+#define SPS_MTI_8                               (GIC_SPI_START + 115)
+#define SPS_MTI_9                               (GIC_SPI_START + 116)
+#define SPS_MTI_10                              (GIC_SPI_START + 117)
+#define SPS_MTI_11                              (GIC_SPI_START + 118)
+#define SPS_MTI_12                              (GIC_SPI_START + 119)
+#define SPS_MTI_13                              (GIC_SPI_START + 120)
+#define SPS_MTI_14                              (GIC_SPI_START + 121)
+#define SPS_MTI_15                              (GIC_SPI_START + 122)
+#define SPS_MTI_16                              (GIC_SPI_START + 123)
+#define SPS_MTI_17                              (GIC_SPI_START + 124)
+#define SPS_MTI_18                              (GIC_SPI_START + 125)
+#define SPS_MTI_19                              (GIC_SPI_START + 126)
+#define SPS_MTI_20                              (GIC_SPI_START + 127)
+#define SPS_MTI_21                              (GIC_SPI_START + 128)
+#define SPS_MTI_22                              (GIC_SPI_START + 129)
+#define SPS_MTI_23                              (GIC_SPI_START + 130)
+#define SPS_MTI_24                              (GIC_SPI_START + 131)
+#define SPS_MTI_25                              (GIC_SPI_START + 132)
+#define SPS_MTI_26                              (GIC_SPI_START + 133)
+#define SPS_MTI_27                              (GIC_SPI_START + 134)
+#define SPS_MTI_28                              (GIC_SPI_START + 135)
+#define SPS_MTI_29                              (GIC_SPI_START + 136)
+#define SPS_MTI_30                              (GIC_SPI_START + 137)
+#define SPS_MTI_31                              (GIC_SPI_START + 138)
+#define UXMC_EBI2_WR_ER_DONE_IRQ                (GIC_SPI_START + 139)
+#define UXMC_EBI2_OP_DONE_IRQ                   (GIC_SPI_START + 140)
+#define USB2_IRQ                                (GIC_SPI_START + 141)
+#define USB1_IRQ                                (GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ                           (GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ                         (GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ                          (GIC_SPI_START + 145)
+#define INT_UART1DM_IRQ                         (GIC_SPI_START + 146)
+#define GSBI1_QUP_IRQ                           (GIC_SPI_START + 147)
+#define INT_UART2DM_IRQ                         (GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ                           (GIC_SPI_START + 149)
+#define INT_UART3DM_IRQ                         (GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ                           (GIC_SPI_START + 151)
+#define INT_UART4DM_IRQ                         (GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ                           (GIC_SPI_START + 153)
+#define INT_UART5DM_IRQ                         (GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ                           (GIC_SPI_START + 155)
+#define INT_UART6DM_IRQ                         (GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ                           (GIC_SPI_START + 157)
+#define INT_UART7DM_IRQ                         (GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ                           (GIC_SPI_START + 159)
+#define INT_UART8DM_IRQ                         (GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ                           (GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ                           (GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ                            (GIC_SPI_START + 163)
+#define TSIF2_IRQ                               (GIC_SPI_START + 164)
+#define TSIF1_IRQ                               (GIC_SPI_START + 165)
+#define INT_ADM1_MASTER                         (GIC_SPI_START + 166)
+#define INT_ADM1_AARM                           (GIC_SPI_START + 167)
+#define INT_ADM1_SD2                            (GIC_SPI_START + 168)
+#define INT_ADM1_SD3                            (GIC_SPI_START + 169)
+#define INT_ADM0_MASTER                         (GIC_SPI_START + 170)
+#define INT_ADM0_AARM                           (GIC_SPI_START + 171)
+#define INT_ADM0_SD2                            (GIC_SPI_START + 172)
+#define INT_ADM0_SD3                            (GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED             (GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED             (GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED             (GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED             (GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT                   (GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT              (GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT              (GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ                         (GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ               (GIC_SPI_START + 184)
+#define HSDDRX_SMICH0_IRQ                       (GIC_SPI_START + 185)
+#define HSDDRX_EBI1_IRQ                         (GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ                            (GIC_SPI_START + 187)
+#define SDC5_IRQ_0                              (GIC_SPI_START + 188)
+#define INT_UART9DM_IRQ                         (GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ                           (GIC_SPI_START + 190)
+#define INT_UART10DM_IRQ                        (GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ                          (GIC_SPI_START + 192)
+#define INT_UART11DM_IRQ                        (GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ                          (GIC_SPI_START + 194)
+#define INT_UART12DM_IRQ                        (GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ                          (GIC_SPI_START + 196)
+/*SPI 197 to 216 arent used in 8x60*/
+#define SMPSS_SPARE_1                           (GIC_SPI_START + 217)
+#define SMPSS_SPARE_2                           (GIC_SPI_START + 218)
+#define SMPSS_SPARE_3                           (GIC_SPI_START + 219)
+#define SMPSS_SPARE_4                           (GIC_SPI_START + 220)
+#define SMPSS_SPARE_5                           (GIC_SPI_START + 221)
+#define SMPSS_SPARE_6                           (GIC_SPI_START + 222)
+#define SMPSS_SPARE_7                           (GIC_SPI_START + 223)
+
+#define NR_GPIO_IRQS 173
+#define NR_MSM_IRQS 256
+#define NR_BOARD_IRQS 0
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 164d355c96e..8679a456474 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -24,6 +24,8 @@
 #elif defined(CONFIG_ARCH_QSD8X50)
 #include "irqs-8x50.h"
 #include "sirc.h"
+#elif defined(CONFIG_ARCH_MSM8X60)
+#include "irqs-8x60.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 50c7847e600..070e17d237f 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -23,6 +23,8 @@
 #define PHYS_OFFSET             UL(0x20000000)
 #elif defined(CONFIG_ARCH_MSM7X30)
 #define PHYS_OFFSET             UL(0x00200000)
+#elif defined(CONFIG_ARCH_MSM8X60)
+#define PHYS_OFFSET             UL(0x40200000)
 #else
 #define PHYS_OFFSET             UL(0x10000000)
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
new file mode 100644
index 00000000000..45bab50e3ee
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
+#define __ASM_ARCH_MSM_IOMAP_8X60_H
+
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * MSM_VIC_BASE must be an value that can be loaded via a "mov"
+ * instruction, otherwise entry-macro.S will not compile.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+
+#define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
+#define MSM_QGIC_DIST_PHYS      0x02080000
+#define MSM_QGIC_DIST_SIZE      SZ_4K
+
+#define MSM_QGIC_CPU_BASE       IOMEM(0xF0001000)
+#define MSM_QGIC_CPU_PHYS       0x02081000
+#define MSM_QGIC_CPU_SIZE       SZ_4K
+
+#define MSM_ACC_BASE            IOMEM(0xF0002000)
+#define MSM_ACC_PHYS            0x02001000
+#define MSM_ACC_SIZE            SZ_4K
+
+#define MSM_GCC_BASE            IOMEM(0xF0003000)
+#define MSM_GCC_PHYS            0x02082000
+#define MSM_GCC_SIZE            SZ_4K
+
+#define MSM_TLMM_BASE           IOMEM(0xF0004000)
+#define MSM_TLMM_PHYS           0x00800000
+#define MSM_TLMM_SIZE           SZ_16K
+
+#define MSM_SHARED_RAM_BASE     IOMEM(0xF0100000)
+#define MSM_SHARED_RAM_SIZE     SZ_1M
+
+#define MSM_TMR_BASE            IOMEM(0xF0200000)
+#define MSM_TMR_PHYS            0x02000000
+#define MSM_TMR_SIZE            (SZ_1M)
+
+#define MSM_GPT_BASE            (MSM_TMR_BASE + 0x4)
+#define MSM_DGT_BASE            (MSM_TMR_BASE + 0x24)
+
+#define MSM_IOMMU_JPEGD_PHYS    0x07300000
+#define MSM_IOMMU_JPEGD_SIZE    SZ_1M
+
+#define MSM_IOMMU_VPE_PHYS      0x07400000
+#define MSM_IOMMU_VPE_SIZE      SZ_1M
+
+#define MSM_IOMMU_MDP0_PHYS     0x07500000
+#define MSM_IOMMU_MDP0_SIZE     SZ_1M
+
+#define MSM_IOMMU_MDP1_PHYS     0x07600000
+#define MSM_IOMMU_MDP1_SIZE     SZ_1M
+
+#define MSM_IOMMU_ROT_PHYS      0x07700000
+#define MSM_IOMMU_ROT_SIZE      SZ_1M
+
+#define MSM_IOMMU_IJPEG_PHYS    0x07800000
+#define MSM_IOMMU_IJPEG_SIZE    SZ_1M
+
+#define MSM_IOMMU_VFE_PHYS      0x07900000
+#define MSM_IOMMU_VFE_SIZE      SZ_1M
+
+#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000
+#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M
+
+#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000
+#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M
+
+#define MSM_IOMMU_GFX3D_PHYS    0x07C00000
+#define MSM_IOMMU_GFX3D_SIZE    SZ_1M
+
+#define MSM_IOMMU_GFX2D0_PHYS   0x07D00000
+#define MSM_IOMMU_GFX2D0_SIZE   SZ_1M
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index e6b1821cc4e..8e24dd81213 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -47,8 +47,12 @@
 #include "msm_iomap-7x30.h"
 #elif defined(CONFIG_ARCH_QSD8X50)
 #include "msm_iomap-8x50.h"
+#elif defined(CONFIG_ARCH_MSM8X60)
+#include "msm_iomap-8x60.h"
 #else
 #include "msm_iomap-7x00.h"
 #endif
 
+
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
new file mode 100644
index 00000000000..3ff7bf5e679
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/smp.h
@@ -0,0 +1,39 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_SMP_H
+#define __ASM_ARCH_MSM_SMP_H
+
+#include <asm/hardware/gic.h>
+
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+        gic_raise_softirq(mask, 1);
+}
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
index 05f81fd8623..31a32ad062d 100644
--- a/arch/arm/mach-msm/include/mach/vmalloc.h
+++ b/arch/arm/mach-msm/include/mach/vmalloc.h
@@ -16,7 +16,7 @@
 #ifndef __ASM_ARCH_MSM_VMALLOC_H
 #define __ASM_ARCH_MSM_VMALLOC_H
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
 
 #endif
 
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 1c05060b5f3..d36b6107414 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -100,6 +100,21 @@ void __init msm_map_qsd8x50_io(void)
 }
 #endif /* CONFIG_ARCH_QSD8X50 */
 
+#ifdef CONFIG_ARCH_MSM8X60
+static struct map_desc msm8x60_io_desc[] __initdata = {
+        MSM_DEVICE(QGIC_DIST),
+        MSM_DEVICE(QGIC_CPU),
+        MSM_DEVICE(TMR),
+        MSM_DEVICE(ACC),
+        MSM_DEVICE(GCC),
+};
+
+void __init msm_map_msm8x60_io(void)
+{
+        iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
+}
+#endif /* CONFIG_ARCH_MSM8X60 */
+
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
         MSM_DEVICE(VIC),
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
new file mode 100644
index 00000000000..f71747db3be
--- /dev/null
+++ b/arch/arm/mach-msm/iommu.c
@@ -0,0 +1,597 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/iommu.h>
+
+#include <asm/cacheflush.h>
+#include <asm/sizes.h>
+
+#include <mach/iommu_hw-8xxx.h>
+#include <mach/iommu.h>
+
+DEFINE_SPINLOCK(msm_iommu_lock);
+
+struct msm_priv {
+        unsigned long *pgtable;
+        struct list_head list_attached;
+};
+
+static void __flush_iotlb(struct iommu_domain *domain)
+{
+        struct msm_priv *priv = domain->priv;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+
+#ifndef CONFIG_IOMMU_PGTABLES_L2
+        unsigned long *fl_table = priv->pgtable;
+        int i;
+
+        dmac_flush_range(fl_table, fl_table + SZ_16K);
+
+        for (i = 0; i < NUM_FL_PTE; i++)
+                if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
+                        void *sl_table = __va(fl_table[i] & FL_BASE_MASK);
+                        dmac_flush_range(sl_table, sl_table + SZ_4K);
+                }
+#endif
+
+        list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
+                if (!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent)
+                        BUG();
+
+                iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
+                SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
+        }
+}
+
+static void __reset_context(void __iomem *base, int ctx)
+{
+        SET_BPRCOSH(base, ctx, 0);
+        SET_BPRCISH(base, ctx, 0);
+        SET_BPRCNSH(base, ctx, 0);
+        SET_BPSHCFG(base, ctx, 0);
+        SET_BPMTCFG(base, ctx, 0);
+        SET_ACTLR(base, ctx, 0);
+        SET_SCTLR(base, ctx, 0);
+        SET_FSRRESTORE(base, ctx, 0);
+        SET_TTBR0(base, ctx, 0);
+        SET_TTBR1(base, ctx, 0);
+        SET_TTBCR(base, ctx, 0);
+        SET_BFBCR(base, ctx, 0);
+        SET_PAR(base, ctx, 0);
+        SET_FAR(base, ctx, 0);
+        SET_CTX_TLBIALL(base, ctx, 0);
+        SET_TLBFLPTER(base, ctx, 0);
+        SET_TLBSLPTER(base, ctx, 0);
+        SET_TLBLKCR(base, ctx, 0);
+        SET_PRRR(base, ctx, 0);
+        SET_NMRR(base, ctx, 0);
+        SET_CONTEXTIDR(base, ctx, 0);
+}
+
+static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
+{
+        __reset_context(base, ctx);
+
+        /* Set up HTW mode */
+        /* TLB miss configuration: perform HTW on miss */
+        SET_TLBMCFG(base, ctx, 0x3);
+
+        /* V2P configuration: HTW for access */
+        SET_V2PCFG(base, ctx, 0x3);
+
+        SET_TTBCR(base, ctx, 0);
+        SET_TTBR0_PA(base, ctx, (pgtable >> 14));
+
+        /* Invalidate the TLB for this context */
+        SET_CTX_TLBIALL(base, ctx, 0);
+
+        /* Set interrupt number to "secure" interrupt */
+        SET_IRPTNDX(base, ctx, 0);
+
+        /* Enable context fault interrupt */
+        SET_CFEIE(base, ctx, 1);
+
+        /* Stall access on a context fault and let the handler deal with it */
+        SET_CFCFG(base, ctx, 1);
+
+        /* Redirect all cacheable requests to L2 slave port. */
+        SET_RCISH(base, ctx, 1);
+        SET_RCOSH(base, ctx, 1);
+        SET_RCNSH(base, ctx, 1);
+
+        /* Turn on TEX Remap */
+        SET_TRE(base, ctx, 1);
+
+        /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
+         * TEX class 0 for everything until attributes are properly worked out
+         */
+        SET_PRRR(base, ctx, 0);
+        SET_NMRR(base, ctx, 0);
+
+        /* Turn on BFB prefetch */
+        SET_BFBDFE(base, ctx, 1);
+
+#ifdef CONFIG_IOMMU_PGTABLES_L2
+        /* Configure page tables as inner-cacheable and shareable to reduce
+         * the TLB miss penalty.
+         */
+        SET_TTBR0_SH(base, ctx, 1);
+        SET_TTBR1_SH(base, ctx, 1);
+
+        SET_TTBR0_NOS(base, ctx, 1);
+        SET_TTBR1_NOS(base, ctx, 1);
+
+        SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
+        SET_TTBR0_IRGNL(base, ctx, 1);
+
+        SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
+        SET_TTBR1_IRGNL(base, ctx, 1);
+
+        SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
+        SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
+#endif
+
+        /* Enable the MMU */
+        SET_M(base, ctx, 1);
+}
+
+static int msm_iommu_domain_init(struct iommu_domain *domain)
+{
+        struct msm_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+
+        if (!priv)
+                goto fail_nomem;
+
+        INIT_LIST_HEAD(&priv->list_attached);
+        priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
+                                                          get_order(SZ_16K));
+
+        if (!priv->pgtable)
+                goto fail_nomem;
+
+        memset(priv->pgtable, 0, SZ_16K);
+        domain->priv = priv;
+        return 0;
+
+fail_nomem:
+        kfree(priv);
+        return -ENOMEM;
+}
+
+static void msm_iommu_domain_destroy(struct iommu_domain *domain)
+{
+        struct msm_priv *priv;
+        unsigned long flags;
+        unsigned long *fl_table;
+        int i;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+        priv = domain->priv;
+        domain->priv = NULL;
+
+        if (priv) {
+                fl_table = priv->pgtable;
+
+                for (i = 0; i < NUM_FL_PTE; i++)
+                        if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
+                                free_page((unsigned long) __va(((fl_table[i]) &
+                                                                FL_BASE_MASK)));
+
+                free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
+                priv->pgtable = NULL;
+        }
+
+        kfree(priv);
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+}
+
+static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
+{
+        struct msm_priv *priv;
+        struct msm_iommu_ctx_dev *ctx_dev;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+        struct msm_iommu_ctx_drvdata *tmp_drvdata;
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+
+        priv = domain->priv;
+
+        if (!priv || !dev) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        iommu_drvdata = dev_get_drvdata(dev->parent);
+        ctx_drvdata = dev_get_drvdata(dev);
+        ctx_dev = dev->platform_data;
+
+        if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
+                if (tmp_drvdata == ctx_drvdata) {
+                        ret = -EBUSY;
+                        goto fail;
+                }
+
+        __program_context(iommu_drvdata->base, ctx_dev->num,
+                          __pa(priv->pgtable));
+
+        list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
+        __flush_iotlb(domain);
+
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static void msm_iommu_detach_dev(struct iommu_domain *domain,
+                                 struct device *dev)
+{
+        struct msm_priv *priv;
+        struct msm_iommu_ctx_dev *ctx_dev;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+        unsigned long flags;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+        priv = domain->priv;
+
+        if (!priv || !dev)
+                goto fail;
+
+        iommu_drvdata = dev_get_drvdata(dev->parent);
+        ctx_drvdata = dev_get_drvdata(dev);
+        ctx_dev = dev->platform_data;
+
+        if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
+                goto fail;
+
+        __flush_iotlb(domain);
+        __reset_context(iommu_drvdata->base, ctx_dev->num);
+        list_del_init(&ctx_drvdata->attached_elm);
+
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+}
+
+static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
+                         phys_addr_t pa, int order, int prot)
+{
+        struct msm_priv *priv;
+        unsigned long flags;
+        unsigned long *fl_table;
+        unsigned long *fl_pte;
+        unsigned long fl_offset;
+        unsigned long *sl_table;
+        unsigned long *sl_pte;
+        unsigned long sl_offset;
+        size_t len = 0x1000UL << order;
+        int ret = 0;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+        priv = domain->priv;
+
+        if (!priv) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        fl_table = priv->pgtable;
+
+        if (len != SZ_16M && len != SZ_1M &&
+            len != SZ_64K && len != SZ_4K) {
+                pr_debug("Bad size: %d\n", len);
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        if (!fl_table) {
+                pr_debug("Null page table\n");
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
+        fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
+
+        if (len == SZ_16M) {
+                int i = 0;
+                for (i = 0; i < 16; i++)
+                        *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
+                                  FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
+                                  FL_SHARED;
+        }
+
+        if (len == SZ_1M)
+                *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
+                                                FL_TYPE_SECT | FL_SHARED;
+
+        /* Need a 2nd level table */
+        if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
+                unsigned long *sl;
+                sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
+                                                        get_order(SZ_4K));
+
+                if (!sl) {
+                        pr_debug("Could not allocate second level table\n");
+                        ret = -ENOMEM;
+                        goto fail;
+                }
+
+                memset(sl, 0, SZ_4K);
+                *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
+        }
+
+        sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
+        sl_offset = SL_OFFSET(va);
+        sl_pte = sl_table + sl_offset;
+
+
+        if (len == SZ_4K)
+                *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
+                                          SL_SHARED | SL_TYPE_SMALL;
+
+        if (len == SZ_64K) {
+                int i;
+
+                for (i = 0; i < 16; i++)
+                        *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
+                                            SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
+        }
+
+        __flush_iotlb(domain);
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
+                            int order)
+{
+        struct msm_priv *priv;
+        unsigned long flags;
+        unsigned long *fl_table;
+        unsigned long *fl_pte;
+        unsigned long fl_offset;
+        unsigned long *sl_table;
+        unsigned long *sl_pte;
+        unsigned long sl_offset;
+        size_t len = 0x1000UL << order;
+        int i, ret = 0;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+
+        priv = domain->priv;
+
+        if (!priv) {
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        fl_table = priv->pgtable;
+
+        if (len != SZ_16M && len != SZ_1M &&
+            len != SZ_64K && len != SZ_4K) {
+                pr_debug("Bad length: %d\n", len);
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        if (!fl_table) {
+                pr_debug("Null page table\n");
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
+        fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
+
+        if (*fl_pte == 0) {
+                pr_debug("First level PTE is 0\n");
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        /* Unmap supersection */
+        if (len == SZ_16M)
+                for (i = 0; i < 16; i++)
+                        *(fl_pte+i) = 0;
+
+        if (len == SZ_1M)
+                *fl_pte = 0;
+
+        sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
+        sl_offset = SL_OFFSET(va);
+        sl_pte = sl_table + sl_offset;
+
+        if (len == SZ_64K) {
+                for (i = 0; i < 16; i++)
+                        *(sl_pte+i) = 0;
+        }
+
+        if (len == SZ_4K)
+                *sl_pte = 0;
+
+        if (len == SZ_4K || len == SZ_64K) {
+                int used = 0;
+
+                for (i = 0; i < NUM_SL_PTE; i++)
+                        if (sl_table[i])
+                                used = 1;
+                if (!used) {
+                        free_page((unsigned long)sl_table);
+                        *fl_pte = 0;
+                }
+        }
+
+        __flush_iotlb(domain);
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
+                                          unsigned long va)
+{
+        struct msm_priv *priv;
+        struct msm_iommu_drvdata *iommu_drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata;
+        unsigned int par;
+        unsigned long flags;
+        void __iomem *base;
+        phys_addr_t ret = 0;
+        int ctx;
+
+        spin_lock_irqsave(&msm_iommu_lock, flags);
+
+        priv = domain->priv;
+        if (list_empty(&priv->list_attached))
+                goto fail;
+
+        ctx_drvdata = list_entry(priv->list_attached.next,
+                                 struct msm_iommu_ctx_drvdata, attached_elm);
+        iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
+
+        base = iommu_drvdata->base;
+        ctx = ctx_drvdata->num;
+
+        /* Invalidate context TLB */
+        SET_CTX_TLBIALL(base, ctx, 0);
+        SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
+
+        if (GET_FAULT(base, ctx))
+                goto fail;
+
+        par = GET_PAR(base, ctx);
+
+        /* We are dealing with a supersection */
+        if (GET_NOFAULT_SS(base, ctx))
+                ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
+        else    /* Upper 20 bits from PAR, lower 12 from VA */
+                ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
+
+fail:
+        spin_unlock_irqrestore(&msm_iommu_lock, flags);
+        return ret;
+}
+
+static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
+                                    unsigned long cap)
+{
+        return 0;
+}
+
+static void print_ctx_regs(void __iomem *base, int ctx)
+{
+        unsigned int fsr = GET_FSR(base, ctx);
+        pr_err("FAR    = %08x    PAR    = %08x\n",
+               GET_FAR(base, ctx), GET_PAR(base, ctx));
+        pr_err("FSR    = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
+                        (fsr & 0x02) ? "TF " : "",
+                        (fsr & 0x04) ? "AFF " : "",
+                        (fsr & 0x08) ? "APF " : "",
+                        (fsr & 0x10) ? "TLBMF " : "",
+                        (fsr & 0x20) ? "HTWDEEF " : "",
+                        (fsr & 0x40) ? "HTWSEEF " : "",
+                        (fsr & 0x80) ? "MHF " : "",
+                        (fsr & 0x10000) ? "SL " : "",
+                        (fsr & 0x40000000) ? "SS " : "",
+                        (fsr & 0x80000000) ? "MULTI " : "");
+
+        pr_err("FSYNR0 = %08x    FSYNR1 = %08x\n",
+               GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
+        pr_err("TTBR0  = %08x    TTBR1  = %08x\n",
+               GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
+        pr_err("SCTLR  = %08x    ACTLR  = %08x\n",
+               GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
+        pr_err("PRRR   = %08x    NMRR   = %08x\n",
+               GET_PRRR(base, ctx), GET_NMRR(base, ctx));
+}
+
+irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
+{
+        struct msm_iommu_drvdata *drvdata = dev_id;
+        void __iomem *base;
+        unsigned int fsr = 0;
+        int ncb = 0, i = 0;
+
+        spin_lock(&msm_iommu_lock);
+
+        if (!drvdata) {
+                pr_err("Invalid device ID in context interrupt handler\n");
+                goto fail;
+        }
+
+        base = drvdata->base;
+
+        pr_err("===== WOAH! =====\n");
+        pr_err("Unexpected IOMMU page fault!\n");
+        pr_err("base = %08x\n", (unsigned int) base);
+
+        ncb = GET_NCB(base)+1;
+        for (i = 0; i < ncb; i++) {
+                fsr = GET_FSR(base, i);
+                if (fsr) {
+                        pr_err("Fault occurred in context %d.\n", i);
+                        pr_err("Interesting registers:\n");
+                        print_ctx_regs(base, i);
+                        SET_FSR(base, i, 0x4000000F);
+                }
+        }
+fail:
+        spin_unlock(&msm_iommu_lock);
+        return 0;
+}
+
+static struct iommu_ops msm_iommu_ops = {
+        .domain_init = msm_iommu_domain_init,
+        .domain_destroy = msm_iommu_domain_destroy,
+        .attach_dev = msm_iommu_attach_dev,
+        .detach_dev = msm_iommu_detach_dev,
+        .map = msm_iommu_map,
+        .unmap = msm_iommu_unmap,
+        .iova_to_phys = msm_iommu_iova_to_phys,
+        .domain_has_cap = msm_iommu_domain_has_cap
+};
+
+static int msm_iommu_init(void)
+{
+        register_iommu(&msm_iommu_ops);
+        return 0;
+}
+
+subsys_initcall(msm_iommu_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
new file mode 100644
index 00000000000..c33ae786c41
--- /dev/null
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -0,0 +1,374 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/iommu.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include <mach/iommu_hw-8xxx.h>
+#include <mach/iommu.h>
+
+struct iommu_ctx_iter_data {
+        /* input */
+        const char *name;
+
+        /* output */
+        struct device *dev;
+};
+
+static struct platform_device *msm_iommu_root_dev;
+
+static int each_iommu_ctx(struct device *dev, void *data)
+{
+        struct iommu_ctx_iter_data *res = data;
+        struct msm_iommu_ctx_dev *c = dev->platform_data;
+
+        if (!res || !c || !c->name || !res->name)
+                return -EINVAL;
+
+        if (!strcmp(res->name, c->name)) {
+                res->dev = dev;
+                return 1;
+        }
+        return 0;
+}
+
+static int each_iommu(struct device *dev, void *data)
+{
+        return device_for_each_child(dev, data, each_iommu_ctx);
+}
+
+struct device *msm_iommu_get_ctx(const char *ctx_name)
+{
+        struct iommu_ctx_iter_data r;
+        int found;
+
+        if (!msm_iommu_root_dev) {
+                pr_err("No root IOMMU device.\n");
+                goto fail;
+        }
+
+        r.name = ctx_name;
+        found = device_for_each_child(&msm_iommu_root_dev->dev, &r, each_iommu);
+
+        if (!found) {
+                pr_err("Could not find context <%s>\n", ctx_name);
+                goto fail;
+        }
+
+        return r.dev;
+fail:
+        return NULL;
+}
+EXPORT_SYMBOL(msm_iommu_get_ctx);
+
+static void msm_iommu_reset(void __iomem *base)
+{
+        int ctx, ncb;
+
+        SET_RPUE(base, 0);
+        SET_RPUEIE(base, 0);
+        SET_ESRRESTORE(base, 0);
+        SET_TBE(base, 0);
+        SET_CR(base, 0);
+        SET_SPDMBE(base, 0);
+        SET_TESTBUSCR(base, 0);
+        SET_TLBRSW(base, 0);
+        SET_GLOBAL_TLBIALL(base, 0);
+        SET_RPU_ACR(base, 0);
+        SET_TLBLKCRWE(base, 1);
+        ncb = GET_NCB(base)+1;
+
+        for (ctx = 0; ctx < ncb; ctx++) {
+                SET_BPRCOSH(base, ctx, 0);
+                SET_BPRCISH(base, ctx, 0);
+                SET_BPRCNSH(base, ctx, 0);
+                SET_BPSHCFG(base, ctx, 0);
+                SET_BPMTCFG(base, ctx, 0);
+                SET_ACTLR(base, ctx, 0);
+                SET_SCTLR(base, ctx, 0);
+                SET_FSRRESTORE(base, ctx, 0);
+                SET_TTBR0(base, ctx, 0);
+                SET_TTBR1(base, ctx, 0);
+                SET_TTBCR(base, ctx, 0);
+                SET_BFBCR(base, ctx, 0);
+                SET_PAR(base, ctx, 0);
+                SET_FAR(base, ctx, 0);
+                SET_CTX_TLBIALL(base, ctx, 0);
+                SET_TLBFLPTER(base, ctx, 0);
+                SET_TLBSLPTER(base, ctx, 0);
+                SET_TLBLKCR(base, ctx, 0);
+                SET_PRRR(base, ctx, 0);
+                SET_NMRR(base, ctx, 0);
+                SET_CONTEXTIDR(base, ctx, 0);
+        }
+}
+
+static int msm_iommu_probe(struct platform_device *pdev)
+{
+        struct resource *r;
+        struct clk *iommu_clk;
+        struct msm_iommu_drvdata *drvdata;
+        struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
+        void __iomem *regs_base;
+        resource_size_t len;
+        int ret = 0, ncb, nm2v, irq;
+
+        if (pdev->id != -1) {
+                drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
+
+                if (!drvdata) {
+                        ret = -ENOMEM;
+                        goto fail;
+                }
+
+                if (!iommu_dev) {
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                if (iommu_dev->clk_rate != 0) {
+                        iommu_clk = clk_get(&pdev->dev, "iommu_clk");
+
+                        if (IS_ERR(iommu_clk)) {
+                                ret = -ENODEV;
+                                goto fail;
+                        }
+
+                        if (iommu_dev->clk_rate > 0) {
+                                ret = clk_set_rate(iommu_clk,
+                                                        iommu_dev->clk_rate);
+                                if (ret) {
+                                        clk_put(iommu_clk);
+                                        goto fail;
+                                }
+                        }
+
+                        ret = clk_enable(iommu_clk);
+                        if (ret) {
+                                clk_put(iommu_clk);
+                                goto fail;
+                        }
+                        clk_put(iommu_clk);
+                }
+
+                r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                                 "physbase");
+                if (!r) {
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                len = r->end - r->start + 1;
+
+                r = request_mem_region(r->start, len, r->name);
+                if (!r) {
+                        pr_err("Could not request memory region: "
+                        "start=%p, len=%d\n", (void *) r->start, len);
+                        ret = -EBUSY;
+                        goto fail;
+                }
+
+                regs_base = ioremap(r->start, len);
+
+                if (!regs_base) {
+                        pr_err("Could not ioremap: start=%p, len=%d\n",
+                                 (void *) r->start, len);
+                        ret = -EBUSY;
+                        goto fail;
+                }
+
+                irq = platform_get_irq_byname(pdev, "secure_irq");
+                if (irq < 0) {
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                mb();
+
+                if (GET_IDR(regs_base) == 0) {
+                        pr_err("Invalid IDR value detected\n");
+                        ret = -ENODEV;
+                        goto fail;
+                }
+
+                ret = request_irq(irq, msm_iommu_fault_handler, 0,
+                                "msm_iommu_secure_irpt_handler", drvdata);
+                if (ret) {
+                        pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
+                        goto fail;
+                }
+
+                msm_iommu_reset(regs_base);
+                drvdata->base = regs_base;
+                drvdata->irq = irq;
+
+                nm2v = GET_NM2VCBMT((unsigned long) regs_base);
+                ncb = GET_NCB((unsigned long) regs_base);
+
+                pr_info("device %s mapped at %p, irq %d with %d ctx banks\n",
+                        iommu_dev->name, regs_base, irq, ncb+1);
+
+                platform_set_drvdata(pdev, drvdata);
+        } else
+                msm_iommu_root_dev = pdev;
+
+        return 0;
+
+fail:
+        kfree(drvdata);
+        return ret;
+}
+
+static int msm_iommu_remove(struct platform_device *pdev)
+{
+        struct msm_iommu_drvdata *drv = NULL;
+
+        drv = platform_get_drvdata(pdev);
+        if (drv) {
+                memset(drv, 0, sizeof(struct msm_iommu_drvdata));
+                kfree(drv);
+                platform_set_drvdata(pdev, NULL);
+        }
+        return 0;
+}
+
+static int msm_iommu_ctx_probe(struct platform_device *pdev)
+{
+        struct msm_iommu_ctx_dev *c = pdev->dev.platform_data;
+        struct msm_iommu_drvdata *drvdata;
+        struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL;
+        int i, ret = 0;
+        if (!c || !pdev->dev.parent) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        drvdata = dev_get_drvdata(pdev->dev.parent);
+
+        if (!drvdata) {
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        ctx_drvdata = kzalloc(sizeof(*ctx_drvdata), GFP_KERNEL);
+        if (!ctx_drvdata) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+        ctx_drvdata->num = c->num;
+        ctx_drvdata->pdev = pdev;
+
+        INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
+        platform_set_drvdata(pdev, ctx_drvdata);
+
+        /* Program the M2V tables for this context */
+        for (i = 0; i < MAX_NUM_MIDS; i++) {
+                int mid = c->mids[i];
+                if (mid == -1)
+                        break;
+
+                SET_M2VCBR_N(drvdata->base, mid, 0);
+                SET_CBACR_N(drvdata->base, c->num, 0);
+
+                /* Set VMID = MID */
+                SET_VMID(drvdata->base, mid, mid);
+
+                /* Set the context number for that MID to this context */
+                SET_CBNDX(drvdata->base, mid, c->num);
+
+                /* Set MID associated with this context bank */
+                SET_CBVMID(drvdata->base, c->num, mid);
+
+                /* Set security bit override to be Non-secure */
+                SET_NSCFG(drvdata->base, mid, 3);
+        }
+
+        pr_info("context device %s with bank index %d\n", c->name, c->num);
+
+        return 0;
+fail:
+        kfree(ctx_drvdata);
+        return ret;
+}
+
+static int msm_iommu_ctx_remove(struct platform_device *pdev)
+{
+        struct msm_iommu_ctx_drvdata *drv = NULL;
+        drv = platform_get_drvdata(pdev);
+        if (drv) {
+                memset(drv, 0, sizeof(struct msm_iommu_ctx_drvdata));
+                kfree(drv);
+                platform_set_drvdata(pdev, NULL);
+        }
+        return 0;
+}
+
+static struct platform_driver msm_iommu_driver = {
+        .driver = {
+                .name   = "msm_iommu",
+        },
+        .probe          = msm_iommu_probe,
+        .remove         = msm_iommu_remove,
+};
+
+static struct platform_driver msm_iommu_ctx_driver = {
+        .driver = {
+                .name   = "msm_iommu_ctx",
+        },
+        .probe          = msm_iommu_ctx_probe,
+        .remove         = msm_iommu_ctx_remove,
+};
+
+static int msm_iommu_driver_init(void)
+{
+        int ret;
+        ret = platform_driver_register(&msm_iommu_driver);
+        if (ret != 0) {
+                pr_err("Failed to register IOMMU driver\n");
+                goto error;
+        }
+
+        ret = platform_driver_register(&msm_iommu_ctx_driver);
+        if (ret != 0) {
+                pr_err("Failed to register IOMMU context driver\n");
+                goto error;
+        }
+
+error:
+        return ret;
+}
+
+static void msm_iommu_driver_exit(void)
+{
+        platform_driver_unregister(&msm_iommu_ctx_driver);
+        platform_driver_unregister(&msm_iommu_driver);
+}
+
+subsys_initcall(msm_iommu_driver_init);
+module_exit(msm_iommu_driver_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c
index b64ba5a9868..1e243f46a96 100644
--- a/arch/arm/mach-msm/last_radio_log.c
+++ b/arch/arm/mach-msm/last_radio_log.c
@@ -48,7 +48,8 @@ static ssize_t last_radio_log_read(struct file *file, char __user *buf,
 }
 
 static struct file_operations last_radio_log_fops = {
-        .read = last_radio_log_read
+        .read = last_radio_log_read,
+        .llseek = default_llseek,
 };
 
 void msm_init_last_radio_log(struct module *owner)
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
index 3b2dd717b78..f91c3b7bc65 100644
--- a/arch/arm/mach-msm/smd_debug.c
+++ b/arch/arm/mach-msm/smd_debug.c
@@ -212,6 +212,7 @@ static int debug_open(struct inode *inode, struct file *file)
 static const struct file_operations debug_ops = {
         .read = debug_read,
         .open = debug_open,
+        .llseek = default_llseek,
 };
 
 static void debug_create(const char *name, mode_t mode,
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index dec5ca622d7..7689848ec68 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -28,7 +28,6 @@
 #ifndef MSM_DGT_BASE
 #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
 #endif
-#define MSM_DGT_SHIFT (5)
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -36,12 +35,28 @@
 #define TIMER_ENABLE_CLR_ON_MATCH_EN    2
 #define TIMER_ENABLE_EN                 1
 #define TIMER_CLEAR             0x000C
-
+#define DGT_CLK_CTL             0x0034
+enum {
+        DGT_CLK_CTL_DIV_1 = 0,
+        DGT_CLK_CTL_DIV_2 = 1,
+        DGT_CLK_CTL_DIV_3 = 2,
+        DGT_CLK_CTL_DIV_4 = 3,
+};
 #define CSR_PROTECTION          0x0020
 #define CSR_PROTECTION_EN               1
 
 #define GPT_HZ 32768
+
+#if defined(CONFIG_ARCH_QSD8X50)
+#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
+#define MSM_DGT_SHIFT (0)
+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
+#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
+#define MSM_DGT_SHIFT (0)
+#else
 #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
+#define MSM_DGT_SHIFT (5)
+#endif
 
 struct msm_clock {
         struct clock_event_device   clockevent;
@@ -170,6 +185,10 @@ static void __init msm_timer_init(void)
         int i;
         int res;
 
+#ifdef CONFIG_ARCH_MSM8X60
+        writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+#endif
+
         for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
                 struct msm_clock *clock = &msm_clocks[i];
                 struct clock_event_device *ce = &clock->clockevent;
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 61e5e583603..29e390e89ff 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -145,8 +145,6 @@ subsys_initcall(wxl_pci_init);
 
 MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
         /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */
-        .phys_io        = MV78XX0_REGS_PHYS_BASE,
-        .io_pg_offst    = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = wxl_init,
         .map_io         = mv78xx0_map_io,
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index efdabe04c69..207c95e403b 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -93,8 +93,6 @@ subsys_initcall(db78x00_pci_init);
 
 MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .phys_io        = MV78XX0_REGS_PHYS_BASE,
-        .io_pg_offst    = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = db78x00_init,
         .map_io         = mv78xx0_map_io,
diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
index cd81689c462..04891428e48 100644
--- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
+++ b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
 
 #include <mach/mv78xx0.h>
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
-        ldrne   \rx, =MV78XX0_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
+        .macro  addruart, rp, rv
+        ldr     \rp, =MV78XX0_REGS_PHYS_BASE
+        ldr     \rv, =MV78XX0_REGS_VIRT_BASE
+        orr     \rp, \rp, #0x00012000
+        orr     \rv, \rv, #0x00012000
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index e136b7a0335..3511ad4d973 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -78,8 +78,6 @@ subsys_initcall(rd78x00_pci_init);
 
 MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .phys_io        = MV78XX0_REGS_PHYS_BASE,
-        .io_pg_offst    = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = rd78x00_masa_init,
         .map_io         = mv78xx0_map_io,
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index c71a7bc1928..aa57e35ce3c 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -12,6 +12,8 @@ config MACH_EUKREA_CPUIMX25
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_ESDHC
         select MXC_ULPI if USB_ULPI
 
 choice
@@ -20,8 +22,8 @@ choice
         default MACH_EUKREA_MBIMXSD25_BASEBOARD
 
 config MACH_EUKREA_MBIMXSD25_BASEBOARD
-        prompt "Eukrea MBIMXSD development board"
-        bool
+        bool "Eukrea MBIMXSD development board"
+        select IMX_HAVE_PLATFORM_IMX_SSI
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMXSD evaluation board.
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 40c7cc41cee..9e4a5578c2f 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -72,7 +72,7 @@ unsigned long get_rate_arm(struct clk *clk)
         unsigned long rate = get_rate_mpll();
 
         if (cctl & (1 << 14))
-                rate = (rate * 3) >> 1;
+                rate = (rate * 3) >> 2;
 
         return rate / ((cctl >> 30) + 1);
 }
@@ -99,7 +99,7 @@ static unsigned long get_rate_per(int per)
         if (readl(CRM_BASE + 0x64) & (1 << per))
                 fref = get_rate_upll();
         else
-                fref = get_rate_ipg(NULL);
+                fref = get_rate_ahb(NULL);
 
         return fref / (val + 1);
 }
@@ -139,6 +139,16 @@ static unsigned long get_rate_lcdc(struct clk *clk)
         return get_rate_per(7);
 }
 
+static unsigned long get_rate_esdhc1(struct clk *clk)
+{
+        return get_rate_per(3);
+}
+
+static unsigned long get_rate_esdhc2(struct clk *clk)
+{
+        return get_rate_per(4);
+}
+
 static unsigned long get_rate_csi(struct clk *clk)
 {
         return get_rate_per(0);
@@ -213,6 +223,12 @@ DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1,  NULL, NULL);
+DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,  NULL,
+                &esdhc1_ahb_clk);
+DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,  NULL, NULL);
+DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,  NULL,
+                &esdhc2_ahb_clk);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
@@ -238,10 +254,14 @@ DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
 DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
 DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
 DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
+                &esdhc1_per_clk);
+DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
+                &esdhc2_per_clk);
 DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
 DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
 DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(can2_clk,   0, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(can2_clk,   1, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c)        \
         {                               \
@@ -261,9 +281,9 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("imx25-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx25-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx25-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
@@ -279,6 +299,8 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
         _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
         _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
         _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index d86a7c3ca8b..93afa10b13c 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -9,35 +9,46 @@
 #include <mach/mx25.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_fec_data imx25_fec_data __initconst;
+#define imx25_add_fec(pdata)    \
+        imx_add_fec(&imx25_fec_data, pdata)
+
 #define imx25_add_flexcan0(pdata)       \
         imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
 #define imx25_add_flexcan1(pdata)       \
         imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
 
-#define imx25_add_imx_i2c0(pdata)       \
-        imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
-#define imx25_add_imx_i2c1(pdata)       \
-        imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
-#define imx25_add_imx_i2c2(pdata)       \
-        imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
-
-#define imx25_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
-#define imx25_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
-#define imx25_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
-#define imx25_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
-#define imx25_add_imx_uart4(pdata)      \
-        imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
+extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
+#define imx25_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
+#define imx25_add_imx_i2c0(pdata)       imx25_add_imx_i2c(0, pdata)
+#define imx25_add_imx_i2c1(pdata)       imx25_add_imx_i2c(1, pdata)
+#define imx25_add_imx_i2c2(pdata)       imx25_add_imx_i2c(2, pdata)
+
+extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
+#define imx25_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
+#define imx25_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
+#define imx25_add_imx_uart0(pdata)      imx25_add_imx_uart(0, pdata)
+#define imx25_add_imx_uart1(pdata)      imx25_add_imx_uart(1, pdata)
+#define imx25_add_imx_uart2(pdata)      imx25_add_imx_uart(2, pdata)
+#define imx25_add_imx_uart3(pdata)      imx25_add_imx_uart(3, pdata)
+#define imx25_add_imx_uart4(pdata)      imx25_add_imx_uart(4, pdata)
 
+extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
 #define imx25_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
-
-#define imx25_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
-#define imx25_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
-#define imx25_add_spi_imx2(pdata)       \
-        imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
+        imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
+
+extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
+#define imx25_add_spi_imx(id, pdata)    \
+        imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
+#define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
+#define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
+#define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
+
+extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
+#define imx25_add_esdhc(id, pdata)      \
+        imx_add_esdhc(&imx25_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3468eb15b23..1d0eb3e8594 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -208,26 +208,6 @@ int __init imx25_register_gpios(void)
         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
 
-static struct resource mx25_fec_resources[] = {
-        {
-                .start  = MX25_FEC_BASE_ADDR,
-                .end    = MX25_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_FEC,
-                .end    = MX25_INT_FEC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mx25_fec_device = {
-        .name   = "fec",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(mx25_fec_resources),
-        .resource       = mx25_fec_resources,
-};
-
 static struct resource mx25_rtc_resources[] = {
         {
                 .start  = MX25_DRYICE_BASE_ADDR,
@@ -305,44 +285,6 @@ struct platform_device mx25_kpp_device = {
         .resource       = mx25_kpp_resources,
 };
 
-static struct resource imx_ssi_resources0[] = {
-        {
-                .start  = MX25_SSI1_BASE_ADDR,
-                .end    = MX25_SSI1_BASE_ADDR + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX25_INT_SSI1,
-                .end    = MX25_INT_SSI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource imx_ssi_resources1[] = {
-        {
-                .start  = MX25_SSI2_BASE_ADDR,
-                .end    = MX25_SSI2_BASE_ADDR + 0x3fff,
-                .flags  = IORESOURCE_MEM
-        }, {
-                .start  = MX25_INT_SSI2,
-                .end    = MX25_INT_SSI2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_ssi_device0 = {
-        .name = "imx-ssi",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
-        .resource = imx_ssi_resources0,
-};
-
-struct platform_device imx_ssi_device1 = {
-        .name = "imx-ssi",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
-        .resource = imx_ssi_resources1,
-};
-
 static struct resource mx25_csi_resources[] = {
         {
                 .start  = MX25_CSI_BASE_ADDR,
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 4aceb68e35a..7b70a43c3a4 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -6,11 +6,8 @@ extern struct platform_device mxc_pwm_device1;
 extern struct platform_device mxc_pwm_device2;
 extern struct platform_device mxc_pwm_device3;
 extern struct platform_device mxc_keypad_device;
-extern struct platform_device mx25_fec_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
 extern struct platform_device mx25_kpp_device;
-extern struct platform_device imx_ssi_device0;
-extern struct platform_device imx_ssi_device1;
 extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
index 4aaadc753d3..e765ac5d9a0 100644
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -34,7 +34,6 @@
 #include <mach/mx25.h>
 #include <mach/imx-uart.h>
 #include <mach/imxfb.h>
-#include <mach/ssi.h>
 #include <mach/audmux.h>
 
 #include "devices-imx25.h"
@@ -90,6 +89,9 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
         MX25_PAD_KPP_COL2__AUD5_TXC,
         MX25_PAD_KPP_COL1__AUD5_RXD,
         MX25_PAD_KPP_COL0__AUD5_TXD,
+        /* CAN */
+        MX25_PAD_GPIO_D__CAN2_RX,
+        MX25_PAD_GPIO_C__CAN2_TX,
 };
 
 #define GPIO_LED1       83
@@ -114,6 +116,38 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
                 },
                 .bpp    = 16,
                 .pcr    = 0xCAD08B80,
+        }, {
+                .mode = {
+                        .name           = "DVI-VGA",
+                        .refresh        = 60,
+                        .xres           = 640,
+                        .yres           = 480,
+                        .pixclock       = 32000,
+                        .hsync_len      = 7,
+                        .left_margin    = 100,
+                        .right_margin   = 100,
+                        .vsync_len      = 7,
+                        .upper_margin   = 7,
+                        .lower_margin   = 100,
+                },
+                .pcr            = 0xFA208B80,
+                .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "DVI-SVGA",
+                        .refresh        = 60,
+                        .xres           = 800,
+                        .yres           = 600,
+                        .pixclock       = 25000,
+                        .hsync_len      = 7,
+                        .left_margin    = 75,
+                        .right_margin   = 75,
+                        .vsync_len      = 7,
+                        .upper_margin   = 7,
+                        .lower_margin   = 75,
+                },
+                .pcr            = 0xFA208B80,
+                .bpp            = 16,
         },
 };
 
@@ -205,7 +239,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
         },
 };
 
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+static const
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
         .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
 };
 
@@ -239,7 +274,10 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
 
         imx25_add_imx_uart1(&uart_pdata);
         mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
-        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+        imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
+
+        imx25_add_flexcan1(NULL);
+        imx25_add_esdhc(0, NULL);
 
         gpio_request(GPIO_LED1, "LED1");
         gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
index e064bb3d691..f6f9ad60c25 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -23,7 +23,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/fec.h>
 #include <linux/platform_device.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -41,7 +40,6 @@
 #include <mach/mxc_nand.h>
 #include <mach/imxfb.h>
 #include <mach/mxc_ehci.h>
-#include <mach/ulpi.h>
 #include <mach/iomux-mx25.h>
 
 #include "devices-imx25.h"
@@ -67,7 +65,7 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
         MX25_PAD_I2C1_DAT__I2C1_DAT,
 };
 
-static struct fec_platform_data mx25_fec_pdata = {
+static const struct fec_platform_data mx25_fec_pdata __initconst = {
         .phy    = PHY_INTERFACE_MODE_RMII,
 };
 
@@ -129,24 +127,19 @@ static void __init eukrea_cpuimx25_init(void)
         imx25_add_imx_uart0(&uart_pdata);
         imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
         mxc_register_device(&mx25_rtc_device, NULL);
-        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+        imx25_add_fec(&mx25_fec_pdata);
 
         i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
         imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
 
-#if defined(CONFIG_USB_ULPI)
-        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
+        if (otg_mode_host)
                 mxc_register_device(&mxc_otg, &otg_pdata);
-        }
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
-#endif
-        if (!otg_mode_host)
+        else
                 mxc_register_device(&otg_udc_device, &otg_device_pdata);
 
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+
 #ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
         eukrea_mbimxsd25_baseboard_init();
 #endif
@@ -163,8 +156,6 @@ static struct sys_timer eukrea_cpuimx25_timer = {
 
 MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
         /* Maintainer: Eukrea Electromatique */
-        .phys_io        = MX25_AIPS1_BASE_ADDR,
-        .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX25_PHYS_OFFSET + 0x100,
         .map_io         = mx25_map_io,
         .init_irq       = mx25_init_irq,
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 62bc21f11a7..80805107a73 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/fec.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
 
@@ -99,7 +98,7 @@ static struct pad_desc mx25pdk_pads[] = {
         MX25_PAD_KPP_COL3__KPP_COL3,
 };
 
-static struct fec_platform_data mx25_fec_pdata = {
+static const struct fec_platform_data mx25_fec_pdata __initconst = {
         .phy    = PHY_INTERFACE_MODE_RMII,
 };
 
@@ -192,7 +191,7 @@ static void __init mx25pdk_init(void)
         mxc_register_device(&mxc_wdt, NULL);
 
         mx25pdk_fec_reset();
-        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+        imx25_add_fec(&mx25_fec_pdata);
         mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
 }
 
@@ -207,8 +206,6 @@ static struct sys_timer mx25pdk_timer = {
 
 MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .phys_io        = MX25_AIPS1_BASE_ADDR,
-        .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX25_PHYS_OFFSET + 0x100,
         .map_io         = mx25_map_io,
         .init_irq       = mx25_init_irq,
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 85beece802a..096fd33f8ab 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -9,6 +9,7 @@ config ARCH_MX35
         bool
         select ARCH_MXC_IOMUX_V3
         select ARCH_MXC_AUDMUX_V2
+        select HAVE_EPIT
 
 comment "MX3 platforms:"
 
@@ -16,6 +17,7 @@ config MACH_MX31ADS
         bool "Support MX31ADS platforms"
         select ARCH_MX31
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         default y
         help
@@ -117,9 +119,11 @@ config MACH_PCM043
         bool "Support Phytec pcm043 (i.MX35) platforms"
         select ARCH_MX35
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_ESDHC
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm043 platform. This includes
@@ -140,6 +144,7 @@ config MACH_MX35_3DS
         bool "Support MX35PDK platform"
         select ARCH_MX35
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         default n
         help
           Include support for MX35PDK platform. This includes specific
@@ -159,6 +164,8 @@ config MACH_EUKREA_CPUIMX35
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_ESDHC
         select MXC_ULPI if USB_ULPI
         help
           Include support for Eukrea CPUIMX35 platform. This includes
@@ -170,8 +177,8 @@ choice
         default MACH_EUKREA_MBIMXSD35_BASEBOARD
 
 config MACH_EUKREA_MBIMXSD35_BASEBOARD
-        prompt "Eukrea MBIMXSD development board"
-        bool
+        bool "Eukrea MBIMXSD development board"
+        select IMX_HAVE_PLATFORM_IMX_SSI
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMXSD evaluation board.
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 2bd7beceb99..8a182d0a3fc 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -7,7 +7,6 @@
 obj-y                           := mm.o devices.o cpu.o
 CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
 CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
-CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
 obj-$(CONFIG_ARCH_MX31)         += clock-imx31.o iomux-imx31.o
 obj-$(CONFIG_ARCH_MX35)         += clock-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mach-mx31ads.o
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 9a9eb6de612..109e98f323e 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -477,7 +477,7 @@ DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(ata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk);
+DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
@@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
 
 static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
         _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
@@ -564,7 +564,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "ata", ata_clk)
         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
         _REGISTER_CLOCK(NULL, "rng", rng_clk)
-        _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
         _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
         _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
         _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 7a62e744a8b..61e4a318980 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -364,8 +364,8 @@ DEFINE_CLOCK(cspi2_clk,  1, CCM_CGR0, 12, get_rate_ipg, NULL);
 DEFINE_CLOCK(ect_clk,    0, CCM_CGR0, 14, get_rate_ipg, NULL);
 DEFINE_CLOCK(edio_clk,   0, CCM_CGR0, 16, NULL, NULL);
 DEFINE_CLOCK(emi_clk,    0, CCM_CGR0, 18, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg, NULL);
 DEFINE_CLOCK(esai_clk,   0, CCM_CGR0, 24, NULL, NULL);
 DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
 DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
@@ -451,17 +451,17 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "ata", ata_clk)
         _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
         _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
         _REGISTER_CLOCK(NULL, "ect", ect_clk)
         _REGISTER_CLOCK(NULL, "edio", edio_clk)
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK(NULL, "epit", epit1_clk)
-        _REGISTER_CLOCK(NULL, "epit", epit2_clk)
+        _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
+        _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
         _REGISTER_CLOCK(NULL, "esai", esai_clk)
-        _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk)
-        _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk)
-        _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
         _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
@@ -482,7 +482,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
         _REGISTER_CLOCK(NULL, "scc", scc_clk)
-        _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
         _REGISTER_CLOCK(NULL, "spba", spba_clk)
         _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
@@ -535,8 +535,16 @@ int __init mx35_clocks_init()
         __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
         __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
 
+        clk_enable(&iim_clk);
+        mx35_read_cpu_rev();
+
+#ifdef CONFIG_MXC_USE_EPIT
+        epit_timer_init(&epit1_clk,
+                        MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
+#else
         mxc_timer_init(&gpt_clk,
                         MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
+#endif
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
index 861afe0fe3a..d00a7545781 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-mx3/cpu.c
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
 };
 
 static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
-        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = CHIP_REV_1_0   },
-        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = CHIP_REV_1_1   },
-        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = CHIP_REV_1_1   },
-        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = CHIP_REV_1_1   },
-        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = CHIP_REV_1_1   },
-        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = CHIP_REV_1_2   },
-        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = CHIP_REV_1_2   },
-        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = CHIP_REV_2_0   },
-        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = CHIP_REV_2_0   },
+        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = MX3x_CHIP_REV_1_0 },
+        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
+        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
+        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
+        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
+        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
 };
 
 void __init mx31_read_cpu_rev(void)
@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void)
         u32 i, srev;
 
         /* read SREV register from IIM module */
-        srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV));
+        srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
 
         for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
                 if (srev == mx31_cpu_type[i].srev) {
@@ -55,3 +55,30 @@ void __init mx31_read_cpu_rev(void)
 
         printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
 }
+
+unsigned int mx35_cpu_rev;
+EXPORT_SYMBOL(mx35_cpu_rev);
+
+void __init mx35_read_cpu_rev(void)
+{
+        u32 rev;
+        char *srev = "unknown";
+
+        rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
+        switch (rev) {
+        case 0x00:
+                mx35_cpu_rev = MX3x_CHIP_REV_1_0;
+                srev = "1.0";
+                break;
+        case 0x10:
+                mx35_cpu_rev = MX3x_CHIP_REV_2_0;
+                srev = "2.0";
+                break;
+        case 0x11:
+                mx35_cpu_rev = MX3x_CHIP_REV_2_1;
+                srev = "2.1";
+                break;
+        }
+
+        printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
+}
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 3b1a44a2058..de9598590eb 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -9,30 +9,33 @@
 #include <mach/mx31.h>
 #include <mach/devices-common.h>
 
-#define imx31_add_imx_i2c0(pdata)       \
-        imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
-#define imx31_add_imx_i2c1(pdata)       \
-        imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata)
-#define imx31_add_imx_i2c2(pdata)       \
-        imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
+extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
+#define imx31_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
+#define imx31_add_imx_i2c0(pdata)       imx31_add_imx_i2c(0, pdata)
+#define imx31_add_imx_i2c1(pdata)       imx31_add_imx_i2c(1, pdata)
+#define imx31_add_imx_i2c2(pdata)       imx31_add_imx_i2c(2, pdata)
 
-#define imx31_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
-#define imx31_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
-#define imx31_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
-#define imx31_add_imx_uart3(pdata)      \
-        imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
-#define imx31_add_imx_uart4(pdata)      \
-        imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
+extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
+#define imx31_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
 
+extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
+#define imx31_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
+#define imx31_add_imx_uart0(pdata)      imx31_add_imx_uart(0, pdata)
+#define imx31_add_imx_uart1(pdata)      imx31_add_imx_uart(1, pdata)
+#define imx31_add_imx_uart2(pdata)      imx31_add_imx_uart(2, pdata)
+#define imx31_add_imx_uart3(pdata)      imx31_add_imx_uart(3, pdata)
+#define imx31_add_imx_uart4(pdata)      imx31_add_imx_uart(4, pdata)
+
+extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
 #define imx31_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
 
-#define imx31_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
-#define imx31_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
-#define imx31_add_spi_imx2(pdata)       \
-        imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
+#define imx31_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx31_cspi_data[id], pdata)
+#define imx31_add_spi_imx0(pdata)       imx31_add_cspi(0, pdata)
+#define imx31_add_spi_imx1(pdata)       imx31_add_cspi(1, pdata)
+#define imx31_add_spi_imx2(pdata)       imx31_add_cspi(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index f6a431a4c3d..5eb917b638d 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -9,29 +9,43 @@
 #include <mach/mx35.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_fec_data imx35_fec_data __initconst;
+#define imx35_add_fec(pdata)    \
+        imx_add_fec(&imx35_fec_data, pdata)
+
 #define imx35_add_flexcan0(pdata)       \
         imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
 #define imx35_add_flexcan1(pdata)       \
         imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
 
-#define imx35_add_imx_i2c0(pdata)       \
-        imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
-#define imx35_add_imx_i2c1(pdata)       \
-        imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
-#define imx35_add_imx_i2c2(pdata)       \
-        imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
+extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
+#define imx35_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
+#define imx35_add_imx_i2c0(pdata)       imx35_add_imx_i2c(0, pdata)
+#define imx35_add_imx_i2c1(pdata)       imx35_add_imx_i2c(1, pdata)
+#define imx35_add_imx_i2c2(pdata)       imx35_add_imx_i2c(2, pdata)
+
+extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
+#define imx35_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
 
-#define imx35_add_imx_uart0(pdata)      \
-        imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
-#define imx35_add_imx_uart1(pdata)      \
-        imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata)
-#define imx35_add_imx_uart2(pdata)      \
-        imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata)
+extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
+#define imx35_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
+#define imx35_add_imx_uart0(pdata)      imx35_add_imx_uart(0, pdata)
+#define imx35_add_imx_uart1(pdata)      imx35_add_imx_uart(1, pdata)
+#define imx35_add_imx_uart2(pdata)      imx35_add_imx_uart(2, pdata)
 
+extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
 #define imx35_add_mxc_nand(pdata)       \
-        imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
+        imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
+
+extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
+#define imx35_add_cspi(id, pdata)       \
+        imx_add_spi_imx(&imx35_cspi_data[id], pdata)
+#define imx35_add_spi_imx0(pdata)       imx35_add_cspi(0, pdata)
+#define imx35_add_spi_imx1(pdata)       imx35_add_cspi(1, pdata)
 
-#define imx35_add_spi_imx0(pdata)       \
-        imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
-#define imx35_add_spi_imx1(pdata)       \
-        imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
+extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
+#define imx35_add_esdhc(id, pdata)      \
+        imx_add_esdhc(&imx35_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index a4fd1a26fc9..f4dff11aaee 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -281,65 +281,6 @@ struct platform_device mxc_usbh2 = {
         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-#if defined(CONFIG_ARCH_MX35)
-static struct resource mxc_fec_resources[] = {
-        {
-                .start  = MXC_FEC_BASE_ADDR,
-                .end    = MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MXC_INT_FEC,
-                .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_fec_device = {
-        .name = "fec",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fec_resources),
-        .resource = mxc_fec_resources,
-};
-#endif
-
-static struct resource imx_ssi_resources0[] = {
-        {
-                .start  = SSI1_BASE_ADDR,
-                .end    = SSI1_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX31_INT_SSI1,
-                .end    = MX31_INT_SSI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource imx_ssi_resources1[] = {
-        {
-                .start  = SSI2_BASE_ADDR,
-                .end    = SSI2_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
-        }, {
-                .start  = MX31_INT_SSI2,
-                .end    = MX31_INT_SSI2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_ssi_device0 = {
-        .name = "imx-ssi",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
-        .resource = imx_ssi_resources0,
-};
-
-struct platform_device imx_ssi_device1 = {
-        .name = "imx-ssi",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
-        .resource = imx_ssi_resources1,
-};
-
 static struct resource imx_wdt_resources[] = {
         {
                 .flags = IORESOURCE_MEM,
@@ -410,10 +351,6 @@ static int __init mx3_devices_init(void)
                 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
                 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
                 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
-                imx_ssi_resources0[1].start = MX35_INT_SSI1;
-                imx_ssi_resources0[1].end = MX35_INT_SSI1;
-                imx_ssi_resources1[1].start = MX35_INT_SSI2;
-                imx_ssi_resources1[1].end = MX35_INT_SSI2;
                 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
                 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
         }
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index e5535234839..585f814473d 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -2,7 +2,6 @@ extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
-extern struct platform_device mxc_fec_device;
 extern struct platform_device mxcsdhc_device0;
 extern struct platform_device mxcsdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
@@ -10,9 +9,6 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
-extern struct platform_device imx_ssi_device0;
-extern struct platform_device imx_ssi_device1;
-extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_wdt_device0;
 extern struct platform_device imx_rtc_device0;
 extern struct platform_device imx_kpp_device;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index f8f15e3ac7a..1abc10d5292 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -43,14 +43,13 @@
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
 #include <mach/audmux.h>
-#include <mach/ssi.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
 
 static const struct fb_videomode fb_modedb[] = {
         {
-                .name           = "CMO_QVGA",
+                .name           = "CMO-QVGA",
                 .refresh        = 60,
                 .xres           = 320,
                 .yres           = 240,
@@ -65,6 +64,40 @@ static const struct fb_videomode fb_modedb[] = {
                 .vmode          = FB_VMODE_NONINTERLACED,
                 .flag           = 0,
         },
+        {
+                .name           = "DVI-VGA",
+                .refresh        = 60,
+                .xres           = 640,
+                .yres           = 480,
+                .pixclock       = 32000,
+                .left_margin    = 100,
+                .right_margin   = 100,
+                .upper_margin   = 7,
+                .lower_margin   = 100,
+                .hsync_len      = 7,
+                .vsync_len      = 7,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
+                                  FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+        {
+                .name           = "DVI-SVGA",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 600,
+                .pixclock       = 25000,
+                .left_margin    = 75,
+                .right_margin   = 75,
+                .upper_margin   = 7,
+                .lower_margin   = 75,
+                .hsync_len      = 7,
+                .vsync_len      = 7,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
+                                  FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
 };
 
 static struct ipu_platform_data mx3_ipu_data = {
@@ -73,7 +106,7 @@ static struct ipu_platform_data mx3_ipu_data = {
 
 static struct mx3fb_platform_data mx3fb_pdata = {
         .dma_dev        = &mx3_ipu.dev,
-        .name           = "CMO_QVGA",
+        .name           = "CMO-QVGA",
         .mode           = fb_modedb,
         .num_modes      = ARRAY_SIZE(fb_modedb),
 };
@@ -120,6 +153,16 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
         MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
         MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
         MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+        /* CAN2 */
+        MX35_PAD_TX5_RX0__CAN2_TXCAN,
+        MX35_PAD_TX4_RX1__CAN2_RXCAN,
+        /* SDCARD */
+        MX35_PAD_SD1_CMD__ESDHC1_CMD,
+        MX35_PAD_SD1_CLK__ESDHC1_CLK,
+        MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
 #define GPIO_LED1       (2 * 32 + 29)
@@ -206,7 +249,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
         },
 };
 
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+static const
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
         .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
 };
 
@@ -242,7 +286,10 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
 
-        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+        imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
+
+        imx35_add_flexcan1(NULL);
+        imx35_add_esdhc(0, NULL);
 
         gpio_request(GPIO_LED1, "LED1");
         gpio_direction_output(GPIO_LED1, 1);
@@ -254,7 +301,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
 
         gpio_request(GPIO_LCDPWR, "LCDPWR");
         gpio_direction_output(GPIO_LCDPWR, 1);
-        gpio_free(GPIO_SWITCH1);
+        gpio_free(GPIO_LCDPWR);
 
         i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
                                 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 68879c996a5..aaa30fe18f8 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -571,8 +571,6 @@ static struct sys_timer armadillo5x0_timer = {
 
 MACHINE_START(ARMADILLO5X0, "Armadillo-500")
         /* Maintainer: Alberto Panizzo  */
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 2a4f8b781ba..9fde873f588 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -31,6 +31,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/fsl_devices.h>
+#include <linux/i2c-gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -43,7 +44,6 @@
 #include <mach/iomux-mx35.h>
 #include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
-#include <mach/ulpi.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -53,39 +53,16 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 };
 
 static const struct imxi2c_platform_data
-eukrea_cpuimx35_i2c0_data __initconst = {
-        .bitrate = 50000,
+                eukrea_cpuimx35_i2c0_data __initconst = {
+        .bitrate =              100000,
 };
 
-#define TSC2007_IRQGPIO         (2 * 32 + 2)
-static int ts_get_pendown_state(void)
-{
-        int val = 0;
-        gpio_free(TSC2007_IRQGPIO);
-        gpio_request(TSC2007_IRQGPIO, NULL);
-        gpio_direction_input(TSC2007_IRQGPIO);
-
-        val = gpio_get_value(TSC2007_IRQGPIO);
-
-        gpio_free(TSC2007_IRQGPIO);
-        gpio_request(TSC2007_IRQGPIO, NULL);
-
-        return val ? 0 : 1;
-}
-
-static int ts_init(void)
-{
-        gpio_request(TSC2007_IRQGPIO, NULL);
-        return 0;
-}
-
 static struct tsc2007_platform_data tsc2007_info = {
         .model                  = 2007,
         .x_plate_ohms           = 180,
-        .get_pendown_state      = ts_get_pendown_state,
-        .init_platform_hw       = ts_init,
 };
 
+#define TSC2007_IRQGPIO         (2 * 32 + 2)
 static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8563", 0x51),
@@ -98,7 +75,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
 };
 
 static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
         &imx_wdt_device0,
 };
 
@@ -135,18 +111,18 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
 };
 
 static const struct mxc_nand_platform_data
-eukrea_cpuimx35_nand_board_info __initconst = {
+                eukrea_cpuimx35_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
         .flash_bbt      = 1,
 };
 
-static struct mxc_usbh_platform_data otg_pdata = {
+static struct mxc_usbh_platform_data __maybe_unused otg_pdata = {
         .portsc = MXC_EHCI_MODE_UTMI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh1_pdata = {
+static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = {
         .portsc = MXC_EHCI_MODE_SERIAL,
         .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                   MXC_EHCI_IPPUE_DOWN,
@@ -155,6 +131,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
 static struct fsl_usb2_platform_data otg_device_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI,
+        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
 static int otg_mode_host;
@@ -180,6 +157,7 @@ static void __init mxc_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
 
+        imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
@@ -189,18 +167,13 @@ static void __init mxc_board_init(void)
                         ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
         imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
 
-#if defined(CONFIG_USB_ULPI)
-        if (otg_mode_host) {
-                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
+        if (otg_mode_host)
                 mxc_register_device(&mxc_otg_host, &otg_pdata);
-        }
-        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
-#endif
-        if (!otg_mode_host)
+        else
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 
+        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+
 #ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
         eukrea_mbimxsd35_baseboard_init();
 #endif
@@ -217,8 +190,6 @@ struct sys_timer eukrea_cpuimx35_timer = {
 
 MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
         /* Maintainer: Eukrea Electromatique */
-        .phys_io        = MX35_AIPS1_BASE_ADDR,
-        .io_pg_offst    = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx35_map_io,
         .init_irq       = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index 5b23e416d6c..042cd5655e1 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -274,8 +274,6 @@ static struct sys_timer kzm_timer = {
  * initialize __mach_desc_KZM_ARM11_01 data structure.
  */
 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = kzm_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 6fe69e124d3..5c1d0e86c91 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -301,8 +301,6 @@ static struct sys_timer mx31_3ds_timer = {
  */
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31_3ds_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 94b3e7c4240..b993b9bf617 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -22,13 +22,13 @@
 #include <linux/i2c.h>
 #include <linux/irq.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
+#include <mach/board-mx31ads.h>
 #include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -40,10 +40,6 @@
 #include "devices-imx31.h"
 #include "devices.h"
 
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
-/* Offsets for the PBC Controller register */
-
 /* PBC Board interrupt status register */
 #define PBC_INTSTATUS           0x000016
 
@@ -67,7 +63,6 @@
 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
 
 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
@@ -517,7 +512,7 @@ static unsigned int ssi_pins[] = {
 
 static void mxc_init_audio(void)
 {
-        mxc_register_device(&imx_ssi_device0, NULL);
+        imx31_add_imx_ssi(0, NULL);
         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
 
@@ -574,8 +569,6 @@ static struct sys_timer mx31ads_timer = {
  */
 MACHINE_START(MX31ADS, "Freescale MX31ADS")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31ads_map_io,
         .init_irq       = mx31ads_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 7c37daabb75..42f47faa6fd 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -348,8 +348,6 @@ static struct sys_timer mx31lilly_timer = {
 };
 
 MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index f66a9576d8c..b93895814cd 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -282,8 +282,6 @@ struct sys_timer mx31lite_timer = {
 
 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31lite_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 7a075e8bf2d..eb5f426df22 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -560,8 +560,6 @@ struct sys_timer mx31moboard_timer = {
 
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
         /* Maintainer: Valentin Longchamp, EPFL Mobots group */
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index 1c30d7212f1..05f628d9072 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
@@ -27,6 +28,8 @@
 #include <linux/gpio.h>
 #include <linux/fsl_devices.h>
 
+#include <linux/mtd/physmap.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -35,6 +38,7 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
+#include <mach/mxc_ehci.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -43,8 +47,34 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static struct physmap_flash_data mx35pdk_flash_data = {
+        .width  = 2,
+};
+
+static struct resource mx35pdk_flash_resource = {
+        .start  = MX35_CS0_BASE_ADDR,
+        .end    = MX35_CS0_BASE_ADDR + SZ_64M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device mx35pdk_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &mx35pdk_flash_data,
+        },
+        .resource = &mx35pdk_flash_resource,
+        .num_resources = 1,
+};
+
+static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = {
+        .width = 1,
+        .hw_ecc = 1,
+        .flash_bbt = 1,
+};
+
 static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
+        &mx35pdk_flash,
 };
 
 static struct pad_desc mx35pdk_pads[] = {
@@ -75,14 +105,24 @@ static struct pad_desc mx35pdk_pads[] = {
         /* USBOTG */
         MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
         MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+        /* USBH1 */
+        MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
+        MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
 };
 
 /* OTG config */
-static struct fsl_usb2_platform_data usb_pdata = {
+static struct fsl_usb2_platform_data usb_otg_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
 
+/* USB HOST config */
+static struct mxc_usbh_platform_data usb_host_pdata = {
+        .portsc         = MXC_EHCI_MODE_SERIAL,
+        .flags          = MXC_EHCI_INTERFACE_SINGLE_UNI |
+                          MXC_EHCI_INTERNAL_PHY,
+};
+
 /*
  * Board specific initialization.
  */
@@ -90,11 +130,16 @@ static void __init mxc_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
+        imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
 
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata);
+
+        mxc_register_device(&mxc_usbh1, &usb_host_pdata);
+
+        imx35_add_mxc_nand(&mx35pdk_nand_board_info);
 }
 
 static void __init mx35pdk_timer_init(void)
@@ -108,8 +153,6 @@ struct sys_timer mx35pdk_timer = {
 
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         /* Maintainer: Freescale Semiconductor, Inc */
-        .phys_io        = MX35_AIPS1_BASE_ADDR,
-        .io_pg_offst    = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx35_map_io,
         .init_irq       = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 214de11b20b..86e86c1300d 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -680,8 +680,6 @@ struct sys_timer pcm037_timer = {
 
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
         /* Maintainer: Pengutronix */
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index c8b98218efe..99e0894e07d 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -19,6 +19,7 @@
 
 #include "pcm037.h"
 #include "devices.h"
+#include "devices-imx31.h"
 
 static unsigned int pcm037_eet_pins[] = {
         /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
@@ -181,7 +182,7 @@ static int eet_init_devices(void)
         /* SPI */
         spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-        imx35_add_spi_imx0(&pcm037_spi1_pdata);
+        imx31_add_spi_imx0(&pcm037_spi1_pdata);
 #endif
 
         platform_device_register(&pcm037_gpio_keys_device);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 28886f0e62f..4e1de87995d 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -42,7 +42,6 @@
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
-#include <mach/ssi.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -141,7 +140,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
 
 static struct platform_device *devices[] __initdata = {
         &pcm043_flash,
-        &mxc_fec_device,
         &imx_wdt_device0,
 };
 
@@ -217,6 +215,13 @@ static struct pad_desc pcm043_pads[] = {
         /* CAN2 */
         MX35_PAD_TX5_RX0__CAN2_TXCAN,
         MX35_PAD_TX4_RX1__CAN2_RXCAN,
+        /* esdhc */
+        MX35_PAD_SD1_CMD__ESDHC1_CMD,
+        MX35_PAD_SD1_CLK__ESDHC1_CLK,
+        MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
 #define AC97_GPIO_TXFS  (1 * 32 + 31)
@@ -293,7 +298,7 @@ err1:
         mdelay(1);
 }
 
-static struct imx_ssi_platform_data pcm043_ssi_pdata = {
+static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
         .ac97_reset = pcm043_ac97_cold_reset,
         .ac97_warm_reset = pcm043_ac97_warm_reset,
         .flags = IMX_SSI_USE_AC97,
@@ -357,11 +362,12 @@ static void __init mxc_board_init(void)
                         MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
                         MXC_AUDMUX_V2_PDCR_RXDSEL(3));
 
+        imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&pcm037_nand_board_info);
-        mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
+        imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
 
         imx35_add_imx_uart1(&uart_pdata);
 
@@ -389,6 +395,7 @@ static void __init mxc_board_init(void)
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 
         imx35_add_flexcan1(NULL);
+        imx35_add_esdhc(0, NULL);
 }
 
 static void __init pcm043_timer_init(void)
@@ -402,8 +409,6 @@ struct sys_timer pcm043_timer = {
 
 MACHINE_START(PCM043, "Phytec Phycore pcm043")
         /* Maintainer: Pengutronix */
-        .phys_io        = MX35_AIPS1_BASE_ADDR,
-        .io_pg_offst    = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx35_map_io,
         .init_irq       = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index c8c380eef74..fd1050c4096 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -270,8 +270,6 @@ static struct sys_timer qong_timer = {
 
 MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
         /* Maintainer: DENX Software Engineering GmbH */
-        .phys_io        = MX31_AIPS1_BASE_ADDR,
-        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
         .init_irq       = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 20e48c0195c..b4ffc531a82 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -110,6 +110,24 @@ void __init mx35_init_irq(void)
 static int mxc_init_l2x0(void)
 {
         void __iomem *l2x0_base;
+        void __iomem *clkctl_base;
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value
+ */
+#define L2_MEM_VAL 0x10
+
+        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+        if (clkctl_base != NULL) {
+                writel(0x00000515, clkctl_base + L2_MEM_VAL);
+                iounmap(clkctl_base);
+        } else {
+                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+        }
 
         l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
         if (IS_ERR(l2x0_base)) {
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5dd36..a2df9ac3799 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -5,11 +5,14 @@ config ARCH_MX51
         default y
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
+        select ARCH_MXC_AUDMUX_V2
 
 comment "MX5 platforms:"
 
 config MACH_MX51_BABBAGE
         bool "Support MX51 BABBAGE platforms"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX51 Babbage platform, also known as MX51EVK in
           u-boot. This includes specific configurations for the board and its
@@ -17,6 +20,8 @@ config MACH_MX51_BABBAGE
 
 config MACH_MX51_3DS
         bool "Support MX51PDK (3DS)"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
         help
           Include support for MX51PDK (3DS) platform. This includes specific
@@ -24,6 +29,10 @@ config MACH_MX51_3DS
 
 config MACH_EUKREA_CPUIMX51
         bool "Support Eukrea CPUIMX51 module"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for Eukrea CPUIMX51 platform. This includes
           specific configurations for the module and its peripherals.
@@ -36,10 +45,43 @@ choice
 config MACH_EUKREA_MBIMX51_BASEBOARD
         prompt "Eukrea MBIMX51 development board"
         bool
+        select IMX_HAVE_PLATFORM_ESDHC
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMX51 evaluation board.
 
 endchoice
 
+config MACH_EUKREA_CPUIMX51SD
+        bool "Support Eukrea CPUIMX51SD module"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        help
+          Include support for Eukrea CPUIMX51SD platform. This includes
+          specific configurations for the module and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX51SD
+        default MACH_EUKREA_MBIMXSD51_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD51_BASEBOARD
+        prompt "Eukrea MBIMXSD development board"
+        bool
+        select IMX_HAVE_PLATFORM_ESDHC
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMXSD evaluation board.
+
+endchoice
+
+config MACH_MX51_EFIKAMX
+        bool "Support MX51 Genesi Efika MX nettop"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for Genesi Efika MX nettop. This includes specific
+          configurations for the board and its peripherals.
+
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 86c66e7f52f..1769c161a60 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 623607a20f5..6a9792fd0a7 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -28,9 +28,7 @@
 #include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -39,6 +37,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define CPUIMX51_USBH1_STP      (0*32 + 27)
@@ -109,7 +108,6 @@ static struct platform_device serial_device = {
 #endif
 
 static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         &serial_device,
 #endif
@@ -148,11 +146,19 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
         MX51_PAD_USBH1_STP__USBH1_STP,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct mxc_nand_platform_data
+                eukrea_cpuimx51_nand_board_info __initconst = {
+        .width          = 1,
+        .hw_ecc         = 1,
+        .flash_bbt      = 1,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
+static const
+struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -239,7 +245,9 @@ static void __init eukrea_cpuimx51_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
+
         gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
         gpio_direction_input(CPUIMX51_QUARTA_GPIO);
         gpio_free(CPUIMX51_QUARTA_GPIO);
@@ -253,9 +261,10 @@ static void __init eukrea_cpuimx51_init(void)
         gpio_direction_input(CPUIMX51_QUARTD_GPIO);
         gpio_free(CPUIMX51_QUARTD_GPIO);
 
+        imx51_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
+        imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
         i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 
@@ -283,8 +292,6 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .phys_io = MX51_AIPS1_BASE_ADDR,
-        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params = PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
new file mode 100644
index 00000000000..4b3a6119c5f
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -0,0 +1,331 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * based on board-mx51_babbage.c which is
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
+#include <linux/i2c-gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/can/platform/mcp251x.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+
+#define USBH1_RST               (1*32 + 28)
+#define ETH_RST                 (1*32 + 31)
+#define TSC2007_IRQGPIO         (2*32 + 12)
+#define CAN_IRQGPIO             (0*32 + 1)
+#define CAN_RST                 (3*32 + 15)
+#define CAN_NCS                 (3*32 + 24)
+#define CAN_RXOBF               (0*32 + 4)
+#define CAN_RX1BF               (0*32 + 6)
+#define CAN_TXORTS              (0*32 + 7)
+#define CAN_TX1RTS              (0*32 + 8)
+#define CAN_TX2RTS              (0*32 + 9)
+#define I2C_SCL                 (3*32 + 16)
+#define I2C_SDA                 (3*32 + 17)
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET          0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
+
+#define MX51_USB_PLLDIV_12_MHZ          0x00
+#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define MX51_USB_PLL_DIV_24_MHZ         0x02
+
+#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
+                                MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
+
+static struct pad_desc eukrea_cpuimx51sd_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+
+        /* USB HOST1 */
+        MX51_PAD_USBH1_CLK__USBH1_CLK,
+        MX51_PAD_USBH1_DIR__USBH1_DIR,
+        MX51_PAD_USBH1_NXT__USBH1_NXT,
+        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+        MX51_PAD_USBH1_STP__USBH1_STP,
+        MX51_PAD_EIM_CS3__GPIO_2_28,            /* PHY nRESET */
+
+        /* FEC */
+        MX51_PAD_EIM_DTACK__GPIO_2_31,          /* PHY nRESET */
+
+        /* HSI2C */
+        MX51_PAD_I2C1_CLK__GPIO_4_16,
+        MX51_PAD_I2C1_DAT__GPIO_4_17,
+
+        /* CAN */
+        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+        MX51_PAD_CSPI1_SS0__GPIO_4_24,          /* nCS */
+        MX51_PAD_CSI2_PIXCLK__GPIO_4_15,        /* nReset */
+        MX51_PAD_GPIO_1_1__GPIO_1_1,            /* IRQ */
+        MX51_PAD_GPIO_1_4__GPIO_1_4,            /* Control signals */
+        MX51_PAD_GPIO_1_6__GPIO_1_6,
+        MX51_PAD_GPIO_1_7__GPIO_1_7,
+        MX51_PAD_GPIO_1_8__GPIO_1_8,
+        MX51_PAD_GPIO_1_9__GPIO_1_9,
+
+        /* Touchscreen */
+        CPUIMX51SD_GPIO_3_12,                   /* IRQ */
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int ts_get_pendown_state(void)
+{
+        return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+        .model                  = 2007,
+        .x_plate_ohms           = 180,
+        .get_pendown_state      = ts_get_pendown_state,
+};
+
+static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        }, {
+                I2C_BOARD_INFO("tsc2007", 0x49),
+                .type           = "tsc2007",
+                .platform_data  = &tsc2007_info,
+                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+        },
+};
+
+static const struct mxc_nand_platform_data
+                eukrea_cpuimx51sd_nand_board_info __initconst = {
+        .width          = 1,
+        .hw_ecc         = 1,
+        .flash_bbt      = 1,
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_19_2_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* The clock for the USBH1 ULPI port will come from the PHY. */
+        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
+                        usbother_base + MX51_USB_CTRL_1_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init           = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static struct mxc_usbh_platform_data usbh1_config = {
+        .init           = initialize_usbh1_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx51sd_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
+
+static struct i2c_gpio_platform_data pdata = {
+        .sda_pin                = I2C_SDA,
+        .sda_is_open_drain      = 0,
+        .scl_pin                = I2C_SCL,
+        .scl_is_open_drain      = 0,
+        .udelay                 = 2,
+};
+
+static struct platform_device hsi2c_gpio_device = {
+        .name                   = "i2c-gpio",
+        .id                     = 0,
+        .dev.platform_data      = &pdata,
+};
+
+static struct mcp251x_platform_data mcp251x_info = {
+        .oscillator_frequency = 24E6,
+};
+
+static struct spi_board_info cpuimx51sd_spi_device[] = {
+        {
+                .modalias        = "mcp2515",
+                .max_speed_hz    = 6500000,
+                .bus_num         = 0,
+                .mode           = SPI_MODE_0,
+                .chip_select     = 0,
+                .platform_data   = &mcp251x_info,
+                .irq             = gpio_to_irq(0 * 32 + 1)
+        },
+};
+
+static int cpuimx51sd_spi1_cs[] = {
+        CAN_NCS,
+};
+
+static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
+        .chipselect     = cpuimx51sd_spi1_cs,
+        .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &hsi2c_gpio_device,
+};
+
+static void __init eukrea_cpuimx51sd_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
+                                        ARRAY_SIZE(eukrea_cpuimx51sd_pads));
+
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
+
+        gpio_request(ETH_RST, "eth_rst");
+        gpio_set_value(ETH_RST, 1);
+        imx51_add_fec(NULL);
+
+        gpio_request(CAN_IRQGPIO, "can_irq");
+        gpio_direction_input(CAN_IRQGPIO);
+        gpio_free(CAN_IRQGPIO);
+        gpio_request(CAN_NCS, "can_ncs");
+        gpio_direction_output(CAN_NCS, 1);
+        gpio_free(CAN_NCS);
+        gpio_request(CAN_RST, "can_rst");
+        gpio_direction_output(CAN_RST, 0);
+        msleep(20);
+        gpio_set_value(CAN_RST, 1);
+        imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
+        spi_register_board_info(cpuimx51sd_spi_device,
+                                ARRAY_SIZE(cpuimx51sd_spi_device));
+
+        gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
+        gpio_direction_input(TSC2007_IRQGPIO);
+        gpio_free(TSC2007_IRQGPIO);
+
+        i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
+                        ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+        if (otg_mode_host)
+                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        else {
+                initialize_otg_port(NULL);
+                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+        }
+
+        gpio_request(USBH1_RST, "usb_rst");
+        gpio_direction_output(USBH1_RST, 0);
+        msleep(20);
+        gpio_set_value(USBH1_RST, 1);
+        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
+        eukrea_mbimxsd51_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx51sd_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = eukrea_cpuimx51sd_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
+        /* Maintainer: Eric Bénard <eric@eukrea.com> */
+        .boot_params = PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine = eukrea_cpuimx51sd_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index f95c2fd9466..79ce8dcf3cd 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -21,12 +22,13 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx51.h>
-#include <mach/imx-uart.h>
 #include <mach/3ds_debugboard.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+#define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
 
 static struct pad_desc mx51_3ds_pads[] = {
         /* UART1 */
@@ -61,19 +63,25 @@ static struct pad_desc mx51_3ds_pads[] = {
         MX51_PAD_KEY_COL3__KEY_COL3,
         MX51_PAD_KEY_COL4__KEY_COL4,
         MX51_PAD_KEY_COL5__KEY_COL5,
+
+        /* eCSPI2 */
+        MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
+        MX51_PAD_NANDF_RB3__ECSPI2_MISO,
+        MX51_PAD_NANDF_D15__ECSPI2_MOSI,
+        MX51_PAD_NANDF_D12__GPIO_3_28,
 };
 
 /* Serial ports */
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static inline void mxc_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -127,6 +135,26 @@ static inline void mxc_init_keypad(void)
 }
 #endif
 
+static int mx51_3ds_spi2_cs[] = {
+        MXC_SPI_CS(0),
+        MX51_3DS_ECSPI2_CS,
+};
+
+static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
+        .chipselect     = mx51_3ds_spi2_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
+};
+
+static struct spi_board_info mx51_3ds_spi_nor_device[] = {
+        {
+         .modalias = "m25p80",
+         .max_speed_hz = 25000000,      /* max spi clock (SCK) speed in HZ */
+         .bus_num = 1,
+         .chip_select = 1,
+         .mode = SPI_MODE_0,
+         .platform_data = NULL,},
+};
+
 /*
  * Board specific initialization.
  */
@@ -136,6 +164,10 @@ static void __init mxc_board_init(void)
                                         ARRAY_SIZE(mx51_3ds_pads));
         mxc_init_imx_uart();
 
+        imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
+        spi_register_board_info(mx51_3ds_spi_nor_device,
+                                ARRAY_SIZE(mx51_3ds_spi_nor_device));
+
         if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 printk(KERN_WARNING "Init of the debugboard failed, all "
                                     "devices on the board are unusable.\n");
@@ -154,8 +186,6 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .phys_io = MX51_AIPS1_BASE_ADDR,
-        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params = PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 6e384d92e62..0821fe9b3b2 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -17,12 +17,11 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/fsl_devices.h>
+#include <linux/fec.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -31,11 +30,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
 #define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
-#define BABBAGE_PHY_RESET (1*32 +5)     /* GPIO_2_5 */
+#define BABBAGE_PHY_RESET       (1*32 + 5)      /* GPIO_2_5 */
+#define BABBAGE_FEC_PHY_RESET   (1*32 + 14)     /* GPIO_2_14 */
 
 /* USB_CTRL_1 */
 #define MX51_USB_CTRL_1_OFFSET                  0x10
@@ -45,10 +46,6 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ 0x02
 
-static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 static struct pad_desc mx51babbage_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
@@ -93,19 +90,41 @@ static struct pad_desc mx51babbage_pads[] = {
 
         /* USB HUB reset line*/
         MX51_PAD_GPIO_1_7__GPIO_1_7,
+
+        /* FEC */
+        MX51_PAD_EIM_EB2__FEC_MDIO,
+        MX51_PAD_EIM_EB3__FEC_RDAT1,
+        MX51_PAD_EIM_CS2__FEC_RDAT2,
+        MX51_PAD_EIM_CS3__FEC_RDAT3,
+        MX51_PAD_EIM_CS4__FEC_RX_ER,
+        MX51_PAD_EIM_CS5__FEC_CRS,
+        MX51_PAD_NANDF_RB2__FEC_COL,
+        MX51_PAD_NANDF_RB3__FEC_RXCLK,
+        MX51_PAD_NANDF_RB6__FEC_RDAT0,
+        MX51_PAD_NANDF_RB7__FEC_TDAT0,
+        MX51_PAD_NANDF_CS2__FEC_TX_ER,
+        MX51_PAD_NANDF_CS3__FEC_MDC,
+        MX51_PAD_NANDF_CS4__FEC_TDAT1,
+        MX51_PAD_NANDF_CS5__FEC_TDAT2,
+        MX51_PAD_NANDF_CS6__FEC_TDAT3,
+        MX51_PAD_NANDF_CS7__FEC_TX_EN,
+        MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+
+        /* FEC PHY reset line */
+        MX51_PAD_EIM_A20__GPIO_2_14,
 };
 
 /* Serial ports */
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static inline void mxc_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -113,7 +132,7 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
-static struct imxi2c_platform_data babbage_i2c_data = {
+static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -171,6 +190,22 @@ static inline void babbage_usbhub_reset(void)
         gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
 }
 
+static inline void babbage_fec_reset(void)
+{
+        int ret;
+
+        /* reset FEC PHY */
+        ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
+        gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
+        msleep(1);
+        gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
+}
+
 /* This function is board specific as the bit mask for the plldiv will also
 be different for other Freescale SoCs, thus a common bitmask is not
 possible and cannot get place in /plat-mxc/ehci.c.*/
@@ -178,7 +213,7 @@ static int initialize_otg_port(struct platform_device *pdev)
 {
         u32 v;
         void __iomem *usb_base;
-        u32 usbother_base;
+        void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -196,7 +231,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
 {
         u32 v;
         void __iomem *usb_base;
-        u32 usbother_base;
+        void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -250,10 +285,11 @@ static void __init mxc_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                         ARRAY_SIZE(mx51babbage_pads));
         mxc_init_imx_uart();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        babbage_fec_reset();
+        imx51_add_fec(NULL);
 
-        mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
-        mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
+        imx51_add_imx_i2c(0, &babbage_i2c_data);
+        imx51_add_imx_i2c(1, &babbage_i2c_data);
         mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
 
         if (otg_mode_host)
@@ -281,9 +317,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
-        .phys_io = MX51_AIPS1_BASE_ADDR,
-        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
-        .boot_params = PHYS_OFFSET + 0x100,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
         .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
new file mode 100644
index 00000000000..6e623bda3ee
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2010 Linaro Limited
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+
+#define MX51_USB_PLL_DIV_24_MHZ 0x01
+
+static struct pad_desc mx51efikamx_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static const struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/* This function is board specific as the bit mask for the plldiv will also
+ * be different for other Freescale SoCs, thus a common bitmask is not
+ * possible and cannot get place in /plat-mxc/ehci.c.
+ */
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_24_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init   = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
+                                        ARRAY_SIZE(mx51efikamx_pads));
+        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        mxc_init_imx_uart();
+}
+
+static void __init mx51_efikamx_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = mx51_efikamx_timer_init,
+};
+
+MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
+        /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine =  mxc_board_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 57c10a9926c..f2aae92cf0e 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -41,34 +41,66 @@ static struct clk usboh3_clk;
 
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
 
-static int _clk_ccgr_enable(struct clk *clk)
+/* calculate best pre and post dividers to get the required divider */
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
+        u32 max_pre, u32 max_post)
 {
-        u32 reg;
+        if (div >= max_pre * max_post) {
+                *pre = max_pre;
+                *post = max_post;
+        } else if (div >= max_pre) {
+                u32 min_pre, temp_pre, old_err, err;
+                min_pre = DIV_ROUND_UP(div, max_post);
+                old_err = max_pre;
+                for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
+                        err = div % temp_pre;
+                        if (err == 0) {
+                                *pre = temp_pre;
+                                break;
+                        }
+                        err = temp_pre - err;
+                        if (err < old_err) {
+                                old_err = err;
+                                *pre = temp_pre;
+                        }
+                }
+                *post = DIV_ROUND_UP(div, *pre);
+        } else {
+                *pre = div;
+                *post = 1;
+        }
+}
+
+static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
+{
+        u32 reg = __raw_readl(clk->enable_reg);
+
+        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+        reg |= mode << clk->enable_shift;
 
-        reg = __raw_readl(clk->enable_reg);
-        reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
         __raw_writel(reg, clk->enable_reg);
+}
 
+static int _clk_ccgr_enable(struct clk *clk)
+{
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
         return 0;
 }
 
 static void _clk_ccgr_disable(struct clk *clk)
 {
-        u32 reg;
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
+}
 
+static int _clk_ccgr_enable_inrun(struct clk *clk)
+{
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+        return 0;
 }
 
 static void _clk_ccgr_disable_inwait(struct clk *clk)
 {
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-        reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
 }
 
 /*
@@ -542,60 +574,60 @@ static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
-static unsigned long clk_uart_get_rate(struct clk *clk)
-{
-        u32 reg, prediv, podf;
-        unsigned long parent_rate;
+#define clk_nfc_set_parent      NULL
 
-        parent_rate = clk_get_rate(clk->parent);
-
-        reg = __raw_readl(MXC_CCM_CSCDR1);
-        prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-                  MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
-        podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-                MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+        u32 reg, div;
 
-        return parent_rate / (prediv * podf);
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
+               MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
+        rate = clk_get_rate(clk->parent) / div;
+        WARN_ON(rate == 0);
+        return rate;
 }
 
-static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
+static unsigned long clk_nfc_round_rate(struct clk *clk,
+                                                unsigned long rate)
 {
-        u32 reg, mux;
+        u32 div;
+        unsigned long parent_rate = clk_get_rate(clk->parent);
 
-        mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-                       &lp_apm_clk);
-        reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
-        reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
-        __raw_writel(reg, MXC_CCM_CSCMR1);
+        if (!rate)
+                return -EINVAL;
 
-        return 0;
-}
+        div = parent_rate / rate;
 
-static unsigned long clk_usboh3_get_rate(struct clk *clk)
-{
-        u32 reg, prediv, podf;
-        unsigned long parent_rate;
+        if (parent_rate % rate)
+                div++;
 
-        parent_rate = clk_get_rate(clk->parent);
+        if (div > 8)
+                return -EINVAL;
 
-        reg = __raw_readl(MXC_CCM_CSCDR1);
-        prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
-                  MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
-        podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
-                MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
+        return parent_rate / div;
 
-        return parent_rate / (prediv * podf);
 }
 
-static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
+static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
 {
-        u32 reg, mux;
+        u32 reg, div;
+
+        div = clk_get_rate(clk->parent) / rate;
+        if (div == 0)
+                div++;
+        if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
+                return -EINVAL;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+        reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+        __raw_writel(reg, MXC_CCM_CBCDR);
 
-        mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
-                       &lp_apm_clk);
-        reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
-        reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
-        __raw_writel(reg, MXC_CCM_CSCMR1);
+        while (__raw_readl(MXC_CCM_CDHIPR) &
+                        MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
+        }
 
         return 0;
 }
@@ -620,6 +652,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
         return ckih2_reference;
 }
 
+static unsigned long clk_emi_slow_get_rate(struct clk *clk)
+{
+        u32 reg, div;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+               MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
 /* External high frequency clock */
 static struct clk ckih_clk = {
         .get_rate = get_high_reference_clock_rate,
@@ -715,18 +758,6 @@ static struct clk ipg_perclk = {
         .set_parent = _clk_ipg_per_set_parent,
 };
 
-static struct clk uart_root_clk = {
-        .parent = &pll2_sw_clk,
-        .get_rate = clk_uart_get_rate,
-        .set_parent = _clk_uart_set_parent,
-};
-
-static struct clk usboh3_clk = {
-        .parent = &pll2_sw_clk,
-        .get_rate = clk_usboh3_get_rate,
-        .set_parent = _clk_usboh3_set_parent,
-};
-
 static struct clk ahb_max_clk = {
         .parent = &ahb_clk,
         .enable_reg = MXC_CCM_CCGR0,
@@ -762,45 +793,183 @@ static struct clk kpp_clk = {
         .id = 0,
 };
 
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)     \
+static struct clk emi_slow_clk = {
+        .parent = &pll2_sw_clk,
+        .enable_reg = MXC_CCM_CCGR5,
+        .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+        .enable = _clk_ccgr_enable,
+        .disable = _clk_ccgr_disable_inwait,
+        .get_rate = clk_emi_slow_get_rate,
+};
+
+#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)   \
         static struct clk name = {                      \
                 .id             = i,                    \
                 .enable_reg     = er,                   \
                 .enable_shift   = es,                   \
-                .get_rate       = gr,                   \
-                .set_rate       = sr,                   \
+                .get_rate       = pfx##_get_rate,       \
+                .set_rate       = pfx##_set_rate,       \
+                .round_rate     = pfx##_round_rate,     \
+                .set_parent     = pfx##_set_parent,     \
                 .enable         = _clk_ccgr_enable,     \
                 .disable        = _clk_ccgr_disable,    \
                 .parent         = p,                    \
                 .secondary      = s,                    \
         }
 
-/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
-   get_rate, set_rate, parent, secondary); */
+#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)    \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .get_rate       = pfx##_get_rate,       \
+                .set_rate       = pfx##_set_rate,       \
+                .set_parent     = pfx##_set_parent,     \
+                .enable         = _clk_max_enable,      \
+                .disable        = _clk_max_disable,     \
+                .parent         = p,                    \
+                .secondary      = s,                    \
+        }
+
+#define CLK_GET_RATE(name, nr, bitsname)                                \
+static unsigned long clk_##name##_get_rate(struct clk *clk)             \
+{                                                                       \
+        u32 reg, pred, podf;                                            \
+                                                                        \
+        reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
+        pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
+                >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
+        podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
+                >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
+                                                                        \
+        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
+                        (pred + 1) * (podf + 1));                       \
+}
+
+#define CLK_SET_PARENT(name, nr, bitsname)                              \
+static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
+{                                                                       \
+        u32 reg, mux;                                                   \
+                                                                        \
+        mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
+                        &pll3_sw_clk, &lp_apm_clk);                     \
+        reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
+                ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
+        reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
+        __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
+                                                                        \
+        return 0;                                                       \
+}
+
+#define CLK_SET_RATE(name, nr, bitsname)                                \
+static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)   \
+{                                                                       \
+        u32 reg, div, parent_rate;                                      \
+        u32 pre = 0, post = 0;                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        div = parent_rate / rate;                                       \
+                                                                        \
+        if ((parent_rate / div) != rate)                                \
+                return -EINVAL;                                         \
+                                                                        \
+        __calc_pre_post_dividers(div, &pre, &post,                      \
+                (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
+                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
+                (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
+                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
+                                                                        \
+        /* Set sdhc1 clock divider */                                   \
+        reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
+                ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
+                | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
+        reg |= (post - 1) <<                                            \
+                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
+        reg |= (pre - 1) <<                                             \
+                MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
+        __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
+                                                                        \
+        return 0;                                                       \
+}
+
+/* UART */
+CLK_GET_RATE(uart, 1, UART)
+CLK_SET_PARENT(uart, 1, UART)
+
+static struct clk uart_root_clk = {
+        .parent = &pll2_sw_clk,
+        .get_rate = clk_uart_get_rate,
+        .set_parent = clk_uart_set_parent,
+};
+
+/* USBOH3 */
+CLK_GET_RATE(usboh3, 1, USBOH3)
+CLK_SET_PARENT(usboh3, 1, USBOH3)
+
+static struct clk usboh3_clk = {
+        .parent = &pll2_sw_clk,
+        .get_rate = clk_usboh3_get_rate,
+        .set_parent = clk_usboh3_set_parent,
+};
+
+/* eCSPI */
+CLK_GET_RATE(ecspi, 2, CSPI)
+CLK_SET_PARENT(ecspi, 1, CSPI)
+
+static struct clk ecspi_main_clk = {
+        .parent = &pll3_sw_clk,
+        .get_rate = clk_ecspi_get_rate,
+        .set_parent = clk_ecspi_set_parent,
+};
+
+/* eSDHC */
+CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
+CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+
+CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
+CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+
+#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
+        static struct clk name = {                                      \
+                .id             = i,                                    \
+                .enable_reg     = er,                                   \
+                .enable_shift   = es,                                   \
+                .get_rate       = gr,                                   \
+                .set_rate       = sr,                                   \
+                .enable         = e,                                    \
+                .disable        = d,                                    \
+                .parent         = p,                                    \
+                .secondary      = s,                                    \
+        }
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                     \
+        DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
 
 /* Shared peripheral bus arbiter */
 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
 /* UART */
-DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
-DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
-DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
         NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
+DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
+DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
 
 /* GPT */
-DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-        NULL,  NULL, &ipg_clk, NULL);
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
 
 /* I2C */
 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -814,6 +983,52 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
+/* NFC */
+DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
+        clk_nfc, &emi_slow_clk, NULL);
+
+/* SSI */
+DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
+DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
+        NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
+
+/* eCSPI */
+DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+                &ipg_clk, &spba_clk);
+DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+                NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
+DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
+                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+                &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+                NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
+
+/* CSPI */
+DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+                NULL, NULL, &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+                NULL, NULL, &ipg_clk, &cspi_ipg_clk);
+
+/* SDMA */
+DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
+                NULL, NULL, &ahb_clk, NULL);
+
+/* eSDHC */
+DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
+        clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
+DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
+        clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
+
 #define _REGISTER_CLOCK(d, n, c) \
        { \
                 .dev_id = d, \
@@ -837,6 +1052,18 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
+        _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+        _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+        _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
+        _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
+        _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+        _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+        _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
 };
 
 static void clk_tree_init(void)
@@ -880,6 +1107,14 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
         /* set the usboh3_clk parent to pll2_sw_clk */
         clk_set_parent(&usboh3_clk, &pll2_sw_clk);
 
+        /* Set SDHC parents to be PLL2 */
+        clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+        clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
+
+        /* set SDHC root clock as 166.25MHZ*/
+        clk_set_rate(&esdhc1_clk, 166250000);
+        clk_set_rate(&esdhc2_clk, 166250000);
+
         /* System timer */
         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
                 MX51_MXC_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 2d37785e385..eaacb6e9b5d 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -70,6 +70,25 @@ int mx51_revision(void)
 }
 EXPORT_SYMBOL(mx51_revision);
 
+#ifdef CONFIG_NEON
+
+/*
+ * All versions of the silicon before Rev. 3 have broken NEON implementations.
+ * Dependent on link order - so the assumption is that vfp_init is called
+ * before us.
+ */
+static int __init mx51_neon_fixup(void)
+{
+        if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
+                elf_hwcap &= ~HWCAP_NEON;
+                pr_info("Turning off NEON support, detected broken NEON implementation\n");
+        }
+        return 0;
+}
+
+late_initcall(mx51_neon_fixup);
+#endif
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 00000000000..5cc910e6053
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx51.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_fec_data imx51_fec_data __initconst;
+#define imx51_add_fec(pdata)    \
+        imx_add_fec(&imx51_fec_data, pdata)
+
+extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
+#define imx51_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
+
+extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
+#define imx51_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
+#define imx51_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
+
+extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
+#define imx51_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
+
+extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
+#define imx51_add_cspi(pdata)   \
+        imx_add_spi_imx(&imx51_cspi_data, pdata)
+
+extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
+#define imx51_add_ecspi(id, pdata)      \
+        imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
+
+extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
+#define imx51_add_esdhc(id, pdata)      \
+        imx_add_esdhc(&imx51_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 1920ff4963b..4c7be87a7c9 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -17,120 +17,6 @@
 #include <mach/imx-uart.h>
 #include <mach/irqs.h>
 
-static struct resource uart0[] = {
-        {
-                .start = MX51_UART1_BASE_ADDR,
-                .end = MX51_UART1_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART1,
-                .end = MX51_MXC_INT_UART1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = MX51_UART2_BASE_ADDR,
-                .end = MX51_UART2_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART2,
-                .end = MX51_MXC_INT_UART2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = MX51_UART3_BASE_ADDR,
-                .end = MX51_UART3_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART3,
-                .end = MX51_MXC_INT_UART3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource mxc_fec_resources[] = {
-        {
-                .start  = MX51_MXC_FEC_BASE_ADDR,
-                .end    = MX51_MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX51_MXC_INT_FEC,
-                .end    = MX51_MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_fec_device = {
-        .name = "fec",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fec_resources),
-        .resource = mxc_fec_resources,
-};
-
-static struct resource mxc_i2c0_resources[] = {
-        {
-                .start = MX51_I2C1_BASE_ADDR,
-                .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_I2C1,
-                .end = MX51_MXC_INT_I2C1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device0 = {
-        .name = "imx-i2c",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
-        .resource = mxc_i2c0_resources,
-};
-
-static struct resource mxc_i2c1_resources[] = {
-        {
-                .start = MX51_I2C2_BASE_ADDR,
-                .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_I2C2,
-                .end = MX51_MXC_INT_I2C2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device1 = {
-        .name = "imx-i2c",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
-        .resource = mxc_i2c1_resources,
-};
-
 static struct resource mxc_hsi2c_resources[] = {
         {
                 .start = MX51_HSI2C_DMA_BASE_ADDR,
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index e509cfaad1d..af1d07c0bbc 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -1,12 +1,6 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_hsi2c_device;
 extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index ffa93d1d6ef..a2e6e8c39d2 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -30,6 +30,7 @@
 
 #include <asm/mach/arch.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define MBIMX51_TSC2007_GPIO    (2*32 + 30)
@@ -112,9 +113,25 @@ static struct pad_desc mbimx51_pads[] = {
         MX51_PAD_KEY_COL1__KEY_COL1,
         MX51_PAD_KEY_COL2__KEY_COL2,
         MX51_PAD_KEY_COL3__KEY_COL3,
+
+        /* SD 1 */
+        MX51_PAD_SD1_CMD__SD1_CMD,
+        MX51_PAD_SD1_CLK__SD1_CLK,
+        MX51_PAD_SD1_DATA0__SD1_DATA0,
+        MX51_PAD_SD1_DATA1__SD1_DATA1,
+        MX51_PAD_SD1_DATA2__SD1_DATA2,
+        MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+        /* SD 2 */
+        MX51_PAD_SD2_CMD__SD2_CMD,
+        MX51_PAD_SD2_CLK__SD2_CLK,
+        MX51_PAD_SD2_DATA0__SD2_DATA0,
+        MX51_PAD_SD2_DATA1__SD2_DATA1,
+        MX51_PAD_SD2_DATA2__SD2_DATA2,
+        MX51_PAD_SD2_DATA3__SD2_DATA3,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -158,9 +175,11 @@ struct tsc2007_platform_data tsc2007_data = {
 
 static struct i2c_board_info mbimx51_i2c_devices[] = {
         {
-                I2C_BOARD_INFO("tsc2007", 0x48),
+                I2C_BOARD_INFO("tsc2007", 0x49),
                 .irq  = MBIMX51_TSC2007_IRQ,
                 .platform_data = &tsc2007_data,
+        }, {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
         },
 };
 
@@ -172,8 +191,8 @@ void __init eukrea_mbimx51_baseboard_init(void)
         mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
                                         ARRAY_SIZE(mbimx51_pads));
 
-        mxc_register_device(&mxc_uart_device1, NULL);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(1, NULL);
+        imx51_add_imx_uart(2, &uart_pdata);
 
         gpio_request(MBIMX51_LED0, "LED0");
         gpio_direction_output(MBIMX51_LED0, 1);
@@ -197,4 +216,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
         set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
         i2c_register_board_info(1, mbimx51_i2c_devices,
                                 ARRAY_SIZE(mbimx51_i2c_devices));
+
+        imx51_add_esdhc(0, NULL);
+        imx51_add_esdhc(1, NULL);
 }
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 00000000000..2b48f519083
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx51.h>
+#include <mach/audmux.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+
+#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
+                                MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+        /* LED */
+        MX51_PAD_NANDF_D10__GPIO_3_30,
+        /* SWITCH */
+        MBIMXSD_GPIO_3_31,
+        /* UART2 */
+        MX51_PAD_UART2_RXD__UART2_RXD,
+        MX51_PAD_UART2_TXD__UART2_TXD,
+        /* UART 3 */
+        MX51_PAD_UART3_RXD__UART3_RXD,
+        MX51_PAD_UART3_TXD__UART3_TXD,
+        MX51_PAD_KEY_COL4__UART3_RTS,
+        MX51_PAD_KEY_COL5__UART3_CTS,
+        /* SD */
+        MX51_PAD_SD1_CMD__SD1_CMD,
+        MX51_PAD_SD1_CLK__SD1_CLK,
+        MX51_PAD_SD1_DATA0__SD1_DATA0,
+        MX51_PAD_SD1_DATA1__SD1_DATA1,
+        MX51_PAD_SD1_DATA2__SD1_DATA2,
+        MX51_PAD_SD1_DATA3__SD1_DATA3,
+};
+
+#define GPIO_LED1       (2 * 32 + 30)
+#define GPIO_SWITCH1    (2 * 32 + 31)
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_LED1,
+        },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+        .leds           = eukrea_mbimxsd_leds,
+        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &eukrea_mbimxsd_led_info,
+        },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+        {
+                .gpio           = GPIO_SWITCH1,
+                .code           = BTN_0,
+                .desc           = "BP1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+        .buttons        = eukrea_mbimxsd_gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &eukrea_mbimxsd_button_data,
+        }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_mbimxsd_leds_gpio,
+        &eukrea_mbimxsd_button_device,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx51sd init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd51_baseboard_init(void)
+{
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
+                printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+        imx51_add_imx_uart(1, NULL);
+        imx51_add_imx_uart(2, &uart_pdata);
+
+        imx51_add_esdhc(0, NULL);
+
+        gpio_request(GPIO_LED1, "LED1");
+        gpio_direction_output(GPIO_LED1, 1);
+        gpio_free(GPIO_LED1);
+
+        gpio_request(GPIO_SWITCH1, "SWITCH1");
+        gpio_direction_input(GPIO_SWITCH1);
+        gpio_free(GPIO_SWITCH1);
+
+        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 69816ba8293..395d83be8c9 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -53,8 +53,6 @@ struct sys_timer zn5_timer = {
 };
 
 MACHINE_START(MAGX_ZN5, "Motorola Zn5")
-        .phys_io        = MXC91231_AIPS1_BASE_ADDR,
-        .io_pg_offst    = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = MXC91231_PHYS_OFFSET + 0x100,
         .map_io         = mxc91231_map_io,
         .init_irq       = mxc91231_init_irq,
diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/mach-netx/include/mach/debug-macro.S
index e96339e71d8..56a91522818 100644
--- a/arch/arm/mach-netx/include/mach/debug-macro.S
+++ b/arch/arm/mach-netx/include/mach/debug-macro.S
@@ -13,12 +13,10 @@
 
 #include "hardware.h"
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x00100000                @ physical
-                movne   \rx, #io_p2v(0x00100000)        @ virtual
-                orr     \rx, \rx, #0x00000a00
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00000a00
+                orr     \rv, \rp, #io_p2v(0x00100000)   @ virtual
+                orr     \rp, \rp, #0x00100000           @ physical
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h
index 25d5cc676e0..7cca3574308 100644
--- a/arch/arm/mach-netx/include/mach/vmalloc.h
+++ b/arch/arm/mach-netx/include/mach/vmalloc.h
@@ -16,4 +16,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index c9b174bc8cc..ca8b203a3c9 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -200,8 +200,6 @@ static void __init nxdb500_init(void)
 }
 
 MACHINE_START(NXDB500, "Hilscher nxdb500")
-        .phys_io        = 0x00100000,
-        .io_pg_offst    = (io_p2v(0x00100000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = netx_map_io,
         .init_irq       = netx_init_irq,
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index 15b54c62d60..d775cbe0727 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -93,8 +93,6 @@ static void __init nxdkn_init(void)
 }
 
 MACHINE_START(NXDKN, "Hilscher nxdkn")
-        .phys_io        = 0x00100000,
-        .io_pg_offst    = (io_p2v(0x00100000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = netx_map_io,
         .init_irq       = netx_init_irq,
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index 1061c01ff67..de369cd1dcb 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -177,8 +177,6 @@ static void __init nxeb500hmi_init(void)
 }
 
 MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
-        .phys_io        = 0x00100000,
-        .io_pg_offst    = (io_p2v(0x00100000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = netx_map_io,
         .init_irq       = netx_init_irq,
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 841d459ad59..139930350d9 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -276,8 +276,6 @@ static void __init nhk8815_platform_init(void)
 
 MACHINE_START(NOMADIK, "NHK8815")
         /* Maintainer: ST MicroElectronics */
-        .phys_io        = NOMADIK_UART0_BASE,
-        .io_pg_offst    = (IO_ADDRESS(NOMADIK_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x100,
         .map_io         = cpu8815_map_io,
         .init_irq       = cpu8815_init_irq,
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S
index 4f92acfba95..e7151b4b888 100644
--- a/arch/arm/mach-nomadik/include/mach/debug-macro.S
+++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S
@@ -10,13 +10,11 @@
  *
 */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x10000000        @ physical base address
-                movne   \rx, #0xf0000000        @ virtual base
-                add     \rx, \rx, #0x00100000
-                add     \rx, \rx, #0x000fb000
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00100000
+                add     \rp, \rp, #0x000fb000
+                add     \rv, \rp, #0xf0000000   @ virtual base
+                add     \rp, \rp, #0x10000000   @ physical base address
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
index 5c934bdb715..5a2acbdc3d6 100644
--- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
@@ -12,11 +12,9 @@
 
 #include <mach/regs-board-a9m9750dev.h>
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, =NS9XXX_CSxSTAT_PHYS(0)
-                ldrne   \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
+                .macro  addruart, rp, rv
+                ldr     \rp, =NS9XXX_CSxSTAT_PHYS(0)
+                ldr     \rv, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
index 9f79266f08e..d7025704248 100644
--- a/arch/arm/mach-nuc93x/mach-nuc932evb.c
+++ b/arch/arm/mach-nuc93x/mach-nuc932evb.c
@@ -35,8 +35,6 @@ static void __init nuc932evb_init(void)
 
 MACHINE_START(NUC932EVB, "NUC932EVB")
         /* Maintainer: Wan ZongShun */
-        .phys_io        = NUC93X_PA_UART,
-        .io_pg_offst    = (((u32)NUC93X_VA_UART) >> 18) & 0xfffc,
         .boot_params    = 0,
         .map_io         = nuc932evb_map_io,
         .init_irq       = nuc93x_init_irq,
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 3b02d3b944a..5f649637540 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -128,7 +128,7 @@ config MACH_OMAP_PALMTT
         help
           Support for the Palm Tungsten|T PDA. To boot the kernel, you'll
           need a PalmOS compatible bootloader (Garux); check out
-          http://www.hackndev.com/palm/tt/ for more information.
+          http://garux.sourceforge.net/ for more information.
           Say Y here if you have this PDA model, say N otherwise.
 
 config MACH_SX1
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index facfaeb1ae5..9a304d854e3 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER)	+= time.o
 obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
 
 # Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o
 
 # DSP
 obj-$(CONFIG_OMAP_MBOX_FWK)     += mailbox_mach.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 41992ab7196..1d4163b9f0b 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -16,9 +16,12 @@
 #include <linux/init.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
+#include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 
+#include <media/soc_camera.h>
+
 #include <asm/serial.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -32,6 +35,7 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
+#include <mach/camera.h>
 
 #include <mach/ams-delta-fiq.h>
 
@@ -213,10 +217,56 @@ static struct platform_device ams_delta_led_device = {
         .id     = -1
 };
 
+static struct i2c_board_info ams_delta_camera_board_info[] = {
+        {
+                I2C_BOARD_INFO("ov6650", 0x60),
+        },
+};
+
+#ifdef CONFIG_LEDS_TRIGGERS
+DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger);
+
+static int ams_delta_camera_power(struct device *dev, int power)
+{
+        /*
+         * turn on camera LED
+         */
+        if (power)
+                led_trigger_event(ams_delta_camera_led_trigger, LED_FULL);
+        else
+                led_trigger_event(ams_delta_camera_led_trigger, LED_OFF);
+        return 0;
+}
+#else
+#define ams_delta_camera_power  NULL
+#endif
+
+static struct soc_camera_link __initdata ams_delta_iclink = {
+        .bus_id         = 0,    /* OMAP1 SoC camera bus */
+        .i2c_adapter_id = 1,
+        .board_info     = &ams_delta_camera_board_info[0],
+        .module_name    = "ov6650",
+        .power          = ams_delta_camera_power,
+};
+
+static struct platform_device ams_delta_camera_device = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &ams_delta_iclink,
+        },
+};
+
+static struct omap1_cam_platform_data ams_delta_camera_platform_data = {
+        .camexclk_khz   = 12000,        /* default 12MHz clock, no extra DPLL */
+        .lclk_khz_max   = 1334,         /* results in 5fps CIF, 10fps QCIF */
+};
+
 static struct platform_device *ams_delta_devices[] __initdata = {
         &ams_delta_kp_device,
         &ams_delta_lcd_device,
         &ams_delta_led_device,
+        &ams_delta_camera_device,
 };
 
 static void __init ams_delta_init(void)
@@ -225,6 +275,20 @@ static void __init ams_delta_init(void)
         omap_cfg_reg(UART1_TX);
         omap_cfg_reg(UART1_RTS);
 
+        /* parallel camera interface */
+        omap_cfg_reg(H19_1610_CAM_EXCLK);
+        omap_cfg_reg(J15_1610_CAM_LCLK);
+        omap_cfg_reg(L18_1610_CAM_VS);
+        omap_cfg_reg(L15_1610_CAM_HS);
+        omap_cfg_reg(L19_1610_CAM_D0);
+        omap_cfg_reg(K14_1610_CAM_D1);
+        omap_cfg_reg(K15_1610_CAM_D2);
+        omap_cfg_reg(K19_1610_CAM_D3);
+        omap_cfg_reg(K18_1610_CAM_D4);
+        omap_cfg_reg(J14_1610_CAM_D5);
+        omap_cfg_reg(J19_1610_CAM_D6);
+        omap_cfg_reg(J18_1610_CAM_D7);
+
         iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
 
         omap_board_config = ams_delta_config;
@@ -236,6 +300,11 @@ static void __init ams_delta_init(void)
         ams_delta_latch2_write(~0, 0);
 
         omap1_usb_init(&ams_delta_usb_config);
+        omap1_set_camera_info(&ams_delta_camera_platform_data);
+#ifdef CONFIG_LEDS_TRIGGERS
+        led_trigger_register_simple("ams_delta_camera",
+                        &ams_delta_camera_led_trigger);
+#endif
         platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 
 #ifdef CONFIG_AMS_DELTA_FIQ
@@ -297,8 +366,6 @@ static void __init ams_delta_map_io(void)
 
 MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
         /* Maintainer: Jonathan McDowell <noodles@earth.li> */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = ams_delta_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 180ce79e5ea..149fdd32e12 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -386,8 +386,6 @@ static void __init omap_fsample_map_io(void)
 
 MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
 /* Maintainer: Brian Swetland <swetland@google.com> */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_fsample_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 93b9ab8fc3b..23f4ab9e265 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -94,8 +94,6 @@ static void __init omap_generic_map_io(void)
 
 MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
         /* Maintainer: Tony Lindgren <tony@atomide.com> */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_generic_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index b30c4990744..f2fc43d8382 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -58,8 +58,7 @@ static struct omap_mmc_platform_data mmc1_data = {
         .dma_mask                       = 0xffffffff,
         .slots[0]       = {
                 .set_power              = mmc_set_power,
-                .ocr_mask               = MMC_VDD_28_29 | MMC_VDD_30_31 |
-                                          MMC_VDD_32_33 | MMC_VDD_33_34,
+                .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
                 .name                   = "mmcblk",
         },
 };
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index d2cda58bcc4..197adb49dc5 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -458,8 +458,6 @@ static void __init h2_map_io(void)
 
 MACHINE_START(OMAP_H2, "TI-H2")
         /* Maintainer: Imre Deak <imre.deak@nokia.com> */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = h2_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index 54b0f063e26..2098525e7cc 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -40,8 +40,7 @@ static struct omap_mmc_platform_data mmc1_data = {
         .dma_mask                       = 0xffffffff,
         .slots[0]       = {
                 .set_power              = mmc_set_power,
-                .ocr_mask               = MMC_VDD_28_29 | MMC_VDD_30_31 |
-                                          MMC_VDD_32_33 | MMC_VDD_33_34,
+                .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
                 .name                   = "mmcblk",
         },
 };
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index c2ef4ff846c..9126e3e37b4 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -446,8 +446,6 @@ static void __init h3_map_io(void)
 
 MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
         /* Maintainer: Texas Instruments, Inc. */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = h3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 311899ff5ff..071af3e4778 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -30,6 +30,13 @@
 #include <linux/input.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/htcpld.h>
+#include <linux/leds.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,6 +46,7 @@
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/usb.h>
+#include <plat/mmc.h>
 
 #include <mach/irqs.h>
 
@@ -52,13 +60,123 @@
 #define       OMAP_LCDC_CTRL_LCD_EN           (1 << 0)
 #define       OMAP_LCDC_STAT_DONE             (1 << 0)
 
-static struct omap_lcd_config htcherald_lcd_config __initdata = {
-        .ctrl_name      = "internal",
-};
+/* GPIO definitions for the power button and keyboard slide switch */
+#define HTCHERALD_GPIO_POWER 139
+#define HTCHERALD_GPIO_SLIDE 174
+#define HTCHERALD_GIRQ_BTNS 141
 
-static struct omap_board_config_kernel htcherald_config[] __initdata = {
-        { OMAP_TAG_LCD, &htcherald_lcd_config },
-};
+/* GPIO definitions for the touchscreen */
+#define HTCHERALD_GPIO_TS 76
+
+/* HTCPLD definitions */
+
+/*
+ * CPLD Logic
+ *
+ * Chip 3 - 0x03
+ *
+ * Function            7 6 5 4  3 2 1 0
+ * ------------------------------------
+ * DPAD light          x x x x  x x x 1
+ * SoundDev            x x x x  1 x x x
+ * Screen white        1 x x x  x x x x
+ * MMC power on        x x x x  x 1 x x
+ * Happy times (n)     0 x x x  x 1 x x
+ *
+ * Chip 4 - 0x04
+ *
+ * Function            7 6 5 4  3 2 1 0
+ * ------------------------------------
+ * Keyboard light      x x x x  x x x 1
+ * LCD Bright (4)      x x x x  x 1 1 x
+ * LCD Bright (3)      x x x x  x 0 1 x
+ * LCD Bright (2)      x x x x  x 1 0 x
+ * LCD Bright (1)      x x x x  x 0 0 x
+ * LCD Off             x x x x  0 x x x
+ * LCD image (fb)      1 x x x  x x x x
+ * LCD image (white)   0 x x x  x x x x
+ * Caps lock LED       x x 1 x  x x x x
+ *
+ * Chip 5 - 0x05
+ *
+ * Function            7 6 5 4  3 2 1 0
+ * ------------------------------------
+ * Red (solid)         x x x x  x 1 x x
+ * Red (flash)         x x x x  x x 1 x
+ * Green (GSM flash)   x x x x  1 x x x
+ * Green (GSM solid)   x x x 1  x x x x
+ * Green (wifi flash)  x x 1 x  x x x x
+ * Blue (bt flash)     x 1 x x  x x x x
+ * DPAD Int Enable     1 x x x  x x x 0
+ *
+ * (Combinations of the above can be made for different colors.)
+ * The direction pad interrupt enable must be set each time the
+ * interrupt is handled.
+ *
+ * Chip 6 - 0x06
+ *
+ * Function            7 6 5 4  3 2 1 0
+ * ------------------------------------
+ * Vibrator            x x x x  1 x x x
+ * Alt LED             x x x 1  x x x x
+ * Screen white        1 x x x  x x x x
+ * Screen white        x x 1 x  x x x x
+ * Screen white        x 0 x x  x x x x
+ * Enable kbd dpad     x x x x  x x 0 x
+ * Happy Times         0 1 0 x  x x 0 x
+ */
+
+/*
+ * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account
+ * for the 16 MPUIO lines.
+ */
+#define HTCPLD_GPIO_START_OFFSET        (OMAP_MAX_GPIO_LINES + 16)
+#define HTCPLD_IRQ(chip, offset)        (OMAP_IRQ_END + 8 * (chip) + (offset))
+#define HTCPLD_BASE(chip, offset)       \
+        (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset))
+
+#define HTCPLD_GPIO_LED_DPAD            HTCPLD_BASE(0, 0)
+#define HTCPLD_GPIO_LED_KBD             HTCPLD_BASE(1, 0)
+#define HTCPLD_GPIO_LED_CAPS            HTCPLD_BASE(1, 5)
+#define HTCPLD_GPIO_LED_RED_FLASH       HTCPLD_BASE(2, 1)
+#define HTCPLD_GPIO_LED_RED_SOLID       HTCPLD_BASE(2, 2)
+#define HTCPLD_GPIO_LED_GREEN_FLASH     HTCPLD_BASE(2, 3)
+#define HTCPLD_GPIO_LED_GREEN_SOLID     HTCPLD_BASE(2, 4)
+#define HTCPLD_GPIO_LED_WIFI            HTCPLD_BASE(2, 5)
+#define HTCPLD_GPIO_LED_BT              HTCPLD_BASE(2, 6)
+#define HTCPLD_GPIO_LED_VIBRATE         HTCPLD_BASE(3, 3)
+#define HTCPLD_GPIO_LED_ALT             HTCPLD_BASE(3, 4)
+
+#define HTCPLD_GPIO_RIGHT_KBD           HTCPLD_BASE(6, 7)
+#define HTCPLD_GPIO_UP_KBD              HTCPLD_BASE(6, 6)
+#define HTCPLD_GPIO_LEFT_KBD            HTCPLD_BASE(6, 5)
+#define HTCPLD_GPIO_DOWN_KBD            HTCPLD_BASE(6, 4)
+
+#define HTCPLD_GPIO_RIGHT_DPAD          HTCPLD_BASE(7, 7)
+#define HTCPLD_GPIO_UP_DPAD             HTCPLD_BASE(7, 6)
+#define HTCPLD_GPIO_LEFT_DPAD           HTCPLD_BASE(7, 5)
+#define HTCPLD_GPIO_DOWN_DPAD           HTCPLD_BASE(7, 4)
+#define HTCPLD_GPIO_ENTER_DPAD          HTCPLD_BASE(7, 3)
+
+/*
+ * The htcpld chip requires a gpio write to a specific line
+ * to re-enable interrupts after one has occurred.
+ */
+#define HTCPLD_GPIO_INT_RESET_HI        HTCPLD_BASE(2, 7)
+#define HTCPLD_GPIO_INT_RESET_LO        HTCPLD_BASE(2, 0)
+
+/* Chip 5 */
+#define HTCPLD_IRQ_RIGHT_KBD            HTCPLD_IRQ(0, 7)
+#define HTCPLD_IRQ_UP_KBD               HTCPLD_IRQ(0, 6)
+#define HTCPLD_IRQ_LEFT_KBD             HTCPLD_IRQ(0, 5)
+#define HTCPLD_IRQ_DOWN_KBD             HTCPLD_IRQ(0, 4)
+
+/* Chip 6 */
+#define HTCPLD_IRQ_RIGHT_DPAD           HTCPLD_IRQ(1, 7)
+#define HTCPLD_IRQ_UP_DPAD              HTCPLD_IRQ(1, 6)
+#define HTCPLD_IRQ_LEFT_DPAD            HTCPLD_IRQ(1, 5)
+#define HTCPLD_IRQ_DOWN_DPAD            HTCPLD_IRQ(1, 4)
+#define HTCPLD_IRQ_ENTER_DPAD           HTCPLD_IRQ(1, 3)
 
 /* Keyboard definition */
 
@@ -140,6 +258,129 @@ static struct platform_device kp_device = {
         .resource       = kp_resources,
 };
 
+/* GPIO buttons for keyboard slide and power button */
+static struct gpio_keys_button herald_gpio_keys_table[] = {
+        {BTN_0,  HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20},
+        {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW,  1, 20},
+
+        {KEY_LEFT,  HTCPLD_GPIO_LEFT_KBD,  1, "LEFT",  EV_KEY, 1, 20},
+        {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20},
+        {KEY_UP,    HTCPLD_GPIO_UP_KBD,    1, "UP",    EV_KEY, 1, 20},
+        {KEY_DOWN,  HTCPLD_GPIO_DOWN_KBD,  1, "DOWN",  EV_KEY, 1, 20},
+
+        {KEY_LEFT,  HTCPLD_GPIO_LEFT_DPAD,   1, "DLEFT",  EV_KEY, 1, 20},
+        {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD,  1, "DRIGHT", EV_KEY, 1, 20},
+        {KEY_UP,    HTCPLD_GPIO_UP_DPAD,     1, "DUP",    EV_KEY, 1, 20},
+        {KEY_DOWN,  HTCPLD_GPIO_DOWN_DPAD,   1, "DDOWN",  EV_KEY, 1, 20},
+        {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD,  1, "DENTER", EV_KEY, 1, 20},
+};
+
+static struct gpio_keys_platform_data herald_gpio_keys_data = {
+        .buttons        = herald_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(herald_gpio_keys_table),
+        .rep            = 1,
+};
+
+static struct platform_device herald_gpiokeys_device = {
+        .name      = "gpio-keys",
+        .id             = -1,
+        .dev = {
+                .platform_data = &herald_gpio_keys_data,
+        },
+};
+
+/* LEDs for the Herald.  These connect to the HTCPLD GPIO device. */
+static struct gpio_led gpio_leds[] = {
+        {"dpad",        NULL, HTCPLD_GPIO_LED_DPAD,        0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"kbd",         NULL, HTCPLD_GPIO_LED_KBD,         0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"vibrate",     NULL, HTCPLD_GPIO_LED_VIBRATE,     0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"red_solid",   "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"red_flash",   NULL, HTCPLD_GPIO_LED_RED_FLASH,   0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"wifi",        NULL, HTCPLD_GPIO_LED_WIFI,        0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"bt",          NULL, HTCPLD_GPIO_LED_BT,          0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"caps",        NULL, HTCPLD_GPIO_LED_CAPS,        0, 0, LEDS_GPIO_DEFSTATE_OFF},
+        {"alt",         NULL, HTCPLD_GPIO_LED_ALT,         0, 0, LEDS_GPIO_DEFSTATE_OFF},
+};
+
+static struct gpio_led_platform_data gpio_leds_data = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device gpio_leds_device = {
+        .name           = "leds-gpio",
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &gpio_leds_data,
+        },
+};
+
+/* HTC PLD chips */
+
+static struct resource htcpld_resources[] = {
+        [0] = {
+                .start  = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
+                .end    = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct htcpld_chip_platform_data htcpld_chips[] = {
+        [0] = {
+                .addr           = 0x03,
+                .reset          = 0x04,
+                .num_gpios      = 8,
+                .gpio_out_base  = HTCPLD_BASE(0, 0),
+                .gpio_in_base   = HTCPLD_BASE(4, 0),
+        },
+        [1] = {
+                .addr           = 0x04,
+                .reset          = 0x8e,
+                .num_gpios      = 8,
+                .gpio_out_base  = HTCPLD_BASE(1, 0),
+                .gpio_in_base   = HTCPLD_BASE(5, 0),
+        },
+        [2] = {
+                .addr           = 0x05,
+                .reset          = 0x80,
+                .num_gpios      = 8,
+                .gpio_out_base  = HTCPLD_BASE(2, 0),
+                .gpio_in_base   = HTCPLD_BASE(6, 0),
+                .irq_base       = HTCPLD_IRQ(0, 0),
+                .num_irqs       = 8,
+        },
+        [3] = {
+                .addr           = 0x06,
+                .reset          = 0x40,
+                .num_gpios      = 8,
+                .gpio_out_base  = HTCPLD_BASE(3, 0),
+                .gpio_in_base   = HTCPLD_BASE(7, 0),
+                .irq_base       = HTCPLD_IRQ(1, 0),
+                .num_irqs       = 8,
+        },
+};
+
+struct htcpld_core_platform_data htcpld_pfdata = {
+        .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI,
+        .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO,
+        .i2c_adapter_id    = 1,
+
+        .chip              = htcpld_chips,
+        .num_chip          = ARRAY_SIZE(htcpld_chips),
+};
+
+static struct platform_device htcpld_device = {
+        .name           = "i2c-htcpld",
+        .id             = -1,
+        .resource       = htcpld_resources,
+        .num_resources  = ARRAY_SIZE(htcpld_resources),
+        .dev    = {
+                .platform_data  = &htcpld_pfdata,
+        },
+};
+
 /* USB Device */
 static struct omap_usb_config htcherald_usb_config __initdata = {
         .otg = 0,
@@ -150,14 +391,71 @@ static struct omap_usb_config htcherald_usb_config __initdata = {
 };
 
 /* LCD Device resources */
+static struct omap_lcd_config htcherald_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
+
+static struct omap_board_config_kernel htcherald_config[] __initdata = {
+        { OMAP_TAG_LCD, &htcherald_lcd_config },
+};
+
 static struct platform_device lcd_device = {
         .name           = "lcd_htcherald",
         .id             = -1,
 };
 
+/* MMC Card */
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+static struct omap_mmc_platform_data htc_mmc1_data = {
+        .nr_slots                       = 1,
+        .switch_slot                    = NULL,
+        .slots[0]       = {
+                .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
+                .name                   = "mmcblk",
+                .nomux                  = 1,
+                .wires                  = 4,
+                .switch_pin             = -1,
+        },
+};
+
+static struct omap_mmc_platform_data *htc_mmc_data[1];
+#endif
+
+
+/* Platform devices for the Herald */
 static struct platform_device *devices[] __initdata = {
         &kp_device,
         &lcd_device,
+        &htcpld_device,
+        &gpio_leds_device,
+        &herald_gpiokeys_device,
+};
+
+/*
+ * Touchscreen
+ */
+static const struct ads7846_platform_data htcherald_ts_platform_data = {
+        .model                  = 7846,
+        .keep_vref_on           = 1,
+        .x_plate_ohms           = 496,
+        .gpio_pendown           = HTCHERALD_GPIO_TS,
+        .pressure_max           = 100000,
+        .pressure_min           = 5000,
+        .x_min                  = 528,
+        .x_max                  = 3760,
+        .y_min                  = 624,
+        .y_max                  = 3760,
+};
+
+static struct spi_board_info __initdata htcherald_spi_board_info[] = {
+        {
+                .modalias               = "ads7846",
+                .platform_data          = &htcherald_ts_platform_data,
+                .irq                    = OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS),
+                .max_speed_hz           = 2500000,
+                .bus_num                = 2,
+                .chip_select            = 1,
+        }
 };
 
 /*
@@ -278,6 +576,7 @@ static void __init htcherald_init(void)
 {
         printk(KERN_INFO "HTC Herald init.\n");
 
+        /* Do board initialization before we register all the devices */
         omap_gpio_init();
 
         omap_board_config = htcherald_config;
@@ -288,6 +587,16 @@ static void __init htcherald_init(void)
 
         htcherald_usb_enable();
         omap1_usb_init(&htcherald_usb_config);
+
+        spi_register_board_info(htcherald_spi_board_info,
+                ARRAY_SIZE(htcherald_spi_board_info));
+
+        omap_register_i2c_bus(1, 100, NULL, 0);
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+        htc_mmc_data[0] = &htc_mmc1_data;
+        omap1_init_mmc(htc_mmc_data, 1);
+#endif
 }
 
 static void __init htcherald_init_irq(void)
@@ -300,8 +609,6 @@ static void __init htcherald_init_irq(void)
 MACHINE_START(HERALD, "HTC Herald")
         /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */
         /* Maintainer: wing-linux.sourceforge.net */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = htcherald_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 3daf87ad257..dc2b86fd66c 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -459,8 +459,6 @@ static void __init innovator_map_io(void)
 
 MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
         /* Maintainer: MontaVista Software, Inc. */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = innovator_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 51a4539aecf..aa8375b2a0a 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -262,8 +262,6 @@ static void __init omap_nokia770_map_io(void)
 }
 
 MACHINE_START(NOKIA770, "Nokia 770")
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_nokia770_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 679740cc1e9..e9dd79149a8 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -580,8 +580,6 @@ static void __init osk_map_io(void)
 
 MACHINE_START(OMAP_OSK, "TI-OSK")
         /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = osk_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 782bb257a85..f32738b1eb6 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -285,8 +285,6 @@ static void __init omap_palmte_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_palmte_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 0b35ef54a64..ed1400a67f7 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -317,8 +317,6 @@ static void __init omap_palmtt_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_palmtt_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 66362903b6e..d7a245cef9a 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -338,8 +338,6 @@ omap_palmz71_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_palmz71_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 34ab354758b..a8d16a255c1 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -347,8 +347,6 @@ static void __init omap_perseus2_map_io(void)
 
 MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
         /* Maintainer: Kevin Hilman <kjh@hilman.org> */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_perseus2_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c
index 5b33ae8141b..e8ddd86e3fd 100644
--- a/arch/arm/mach-omap1/board-sx1-mmc.c
+++ b/arch/arm/mach-omap1/board-sx1-mmc.c
@@ -44,8 +44,7 @@ static struct omap_mmc_platform_data mmc1_data = {
         .nr_slots                       = 1,
         .slots[0]       = {
                 .set_power              = mmc_set_power,
-                .ocr_mask               = MMC_VDD_28_29 | MMC_VDD_30_31 |
-                                          MMC_VDD_32_33 | MMC_VDD_33_34,
+                .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
                 .name                   = "mmcblk",
         },
 };
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2eb148b8de9..d25f59e5a77 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -419,8 +419,6 @@ static void __init omap_sx1_map_io(void)
 }
 
 MACHINE_START(SX1, "OMAP310 based Siemens SX1")
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_sx1_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6b3cf14bc75..f5992c239bc 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -283,8 +283,6 @@ EXPORT_SYMBOL(voiceblue_wdt_ping);
 
 MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
         /* Maintainer: Ladislav Michl <michl@2n.cz> */
-        .phys_io        = 0xfff00000,
-        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = voiceblue_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index aa0725608fb..ea0d80a89da 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -9,6 +9,7 @@
  * (at your option) any later version.
  */
 
+#include <linux/dma-mapping.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -25,6 +26,7 @@
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 #include <plat/omap7xx.h>
+#include <plat/mcbsp.h>
 
 /*-------------------------------------------------------------------------*/
 
@@ -191,10 +193,76 @@ static inline void omap_init_spi100k(void)
 }
 #endif
 
+
+#define OMAP1_CAMERA_BASE       0xfffb6800
+#define OMAP1_CAMERA_IOSIZE     0x1c
+
+static struct resource omap1_camera_resources[] = {
+        [0] = {
+                .start  = OMAP1_CAMERA_BASE,
+                .end    = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = INT_CAMERA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device omap1_camera_device = {
+        .name           = "omap1-camera",
+        .id             = 0, /* This is used to put cameras on this interface */
+        .dev            = {
+                .dma_mask               = &omap1_camera_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(omap1_camera_resources),
+        .resource       = omap1_camera_resources,
+};
+
+void __init omap1_camera_init(void *info)
+{
+        struct platform_device *dev = &omap1_camera_device;
+        int ret;
+
+        dev->dev.platform_data = info;
+
+        ret = platform_device_register(dev);
+        if (ret)
+                dev_err(&dev->dev, "unable to register device: %d\n", ret);
+}
+
+
 /*-------------------------------------------------------------------------*/
 
 static inline void omap_init_sti(void) {}
 
+#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
+
+static struct platform_device omap_pcm = {
+        .name   = "omap-pcm-audio",
+        .id     = -1,
+};
+
+OMAP_MCBSP_PLATFORM_DEVICE(1);
+OMAP_MCBSP_PLATFORM_DEVICE(2);
+OMAP_MCBSP_PLATFORM_DEVICE(3);
+
+static void omap_init_audio(void)
+{
+        platform_device_register(&omap_mcbsp1);
+        platform_device_register(&omap_mcbsp2);
+        if (!cpu_is_omap7xx())
+                platform_device_register(&omap_mcbsp3);
+        platform_device_register(&omap_pcm);
+}
+
+#else
+static inline void omap_init_audio(void) {}
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 /*
@@ -227,8 +295,36 @@ static int __init omap1_init_devices(void)
         omap_init_rtc();
         omap_init_spi100k();
         omap_init_sti();
+        omap_init_audio();
 
         return 0;
 }
 arch_initcall(omap1_init_devices);
 
+#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+
+static struct resource wdt_resources[] = {
+        {
+                .start          = 0xfffeb000,
+                .end            = 0xfffeb07F,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap_wdt_device = {
+        .name      = "omap_wdt",
+        .id          = -1,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
+        .resource       = wdt_resources,
+};
+
+static int __init omap_init_wdt(void)
+{
+        if (!cpu_is_omap16xx())
+                return;
+
+        platform_device_register(&omap_wdt_device);
+        return 0;
+}
+subsys_initcall(omap_init_wdt);
+#endif
diff --git a/arch/arm/mach-omap1/include/mach/camera.h b/arch/arm/mach-omap1/include/mach/camera.h
new file mode 100644
index 00000000000..fd54b452eb2
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/camera.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_ARCH_CAMERA_H_
+#define __ASM_ARCH_CAMERA_H_
+
+void omap1_camera_init(void *);
+
+static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info)
+{
+        omap1_camera_init(info);
+}
+
+#endif /* __ASM_ARCH_CAMERA_H_ */
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index 671408eb4ab..6a0fa046236 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -28,56 +28,58 @@ omap_uart_virt:	.word	0x0
                  * the desired UART phys and virt addresses temporarily into
                  * the omap_uart_phys and omap_uart_virt above.
                  */
-                .macro  addruart, rx, tmp
+                .macro  addruart, rp, rv
 
                 /* Use omap_uart_phys/virt if already configured */
-9:              mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =__virt_to_phys(omap_uart_phys)    @ physical base address
-                ldrne   \rx, =omap_uart_virt    @ virtual base
-                ldr     \rx, [\rx, #0]
-                cmp     \rx, #0                 @ is port configured?
+9:              mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =__virt_to_phys(omap_uart_phys)    @ MMU not enabled
+                ldrne   \rp, =omap_uart_phys    @ MMU enabled
+                add     \rv, \rp, #4            @ omap_uart_virt
+                ldr     \rp, [\rp, #0]
+                ldr     \rv, [\rv, #0]
+                cmp     \rp, #0                 @ is port configured?
+                cmpne   \rv, #0
                 bne     99f                     @ already configured
 
                 /* Check the debug UART configuration set in uncompress.h */
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =OMAP_UART_INFO
-                ldrne   \rx, =__phys_to_virt(OMAP_UART_INFO)
-                ldr     \rx, [\rx, #0]
+                mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =OMAP_UART_INFO    @ MMU not enabled
+                ldrne   \rp, =__phys_to_virt(OMAP_UART_INFO)    @ MMU enabled
+                ldr     \rp, [\rp, #0]
 
                 /* Select the UART to use based on the UART1 scratchpad value */
-10:             cmp     \rx, #0                 @ no port configured?
+10:             cmp     \rp, #0                 @ no port configured?
                 beq     11f                     @ if none, try to use UART1
-                cmp     \rx, #OMAP1UART1
+                cmp     \rp, #OMAP1UART1
                 beq     11f                     @ configure OMAP1UART1
-                cmp     \rx, #OMAP1UART2
+                cmp     \rp, #OMAP1UART2
                 beq     12f                     @ configure OMAP1UART2
-                cmp     \rx, #OMAP1UART3
+                cmp     \rp, #OMAP1UART3
                 beq     13f                     @ configure OMAP2UART3
 
                 /* Configure the UART offset from the phys/virt base */
-11:             mov     \rx, #0x00fb0000        @ OMAP1UART1
+11:             mov     \rp, #0x00fb0000        @ OMAP1UART1
                 b       98f
-12:             mov     \rx, #0x00fb0000        @ OMAP1UART1
-                orr     \rx, \rx, #0x00000800   @ OMAP1UART2
+12:             mov     \rp, #0x00fb0000        @ OMAP1UART1
+                orr     \rp, \rp, #0x00000800   @ OMAP1UART2
                 b       98f
-13:             mov     \rx, #0x00fb0000        @ OMAP1UART1
-                orr     \rx, \rx, #0x00000800   @ OMAP1UART2
-                orr     \rx, \rx, #0x00009000   @ OMAP1UART3
+13:             mov     \rp, #0x00fb0000        @ OMAP1UART1
+                orr     \rp, \rp, #0x00000800   @ OMAP1UART2
+                orr     \rp, \rp, #0x00009000   @ OMAP1UART3
 
                 /* Store both phys and virt address for the uart */
-98:             add     \rx, \rx, #0xff000000   @ phys base
-                mrc     p15, 0, \tmp, c1, c0
-                tst     \tmp, #1                @ MMU enabled?
-                ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
-                ldrne   \tmp, =omap_uart_phys
-                str     \rx, [\tmp, #0]
-                sub     \rx, \rx, #0xff000000   @ phys base
-                add     \rx, \rx, #0xfe000000   @ virt base
-                ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
-                ldrne   \tmp, =omap_uart_virt
-                str     \rx, [\tmp, #0]
+98:             add     \rp, \rp, #0xff000000   @ phys base
+                mrc     p15, 0, \rv, c1, c0
+                tst     \rv, #1                 @ MMU enabled?
+                ldreq   \rv, =__virt_to_phys(omap_uart_phys)    @ MMU not enabled
+                ldrne   \rv, =omap_uart_phys    @ MMU enabled
+                str     \rp, [\rv, #0]
+                sub     \rp, \rp, #0xff000000   @ phys base
+                add     \rp, \rp, #0xfe000000   @ virt base
+                add     \rv, \rv, #4            @ omap_uart_lsr
+                str     \rp, [\rv, #0]
                 b       9b
 99:
                 .endm
diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h
index 1b2af14df15..b001f67d695 100644
--- a/arch/arm/mach-omap1/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap1/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
-#define VMALLOC_END     (PAGE_OFFSET + 0x18000000)
+#define VMALLOC_END     0xd8000000
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
new file mode 100644
index 00000000000..8b66392be74
--- /dev/null
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -0,0 +1,98 @@
+/*
+ * Runtime PM support code for OMAP1
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+
+#ifdef CONFIG_PM_RUNTIME
+static int omap1_pm_runtime_suspend(struct device *dev)
+{
+        struct clk *iclk, *fclk;
+        int ret = 0;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        ret = pm_generic_runtime_suspend(dev);
+
+        fclk = clk_get(dev, "fck");
+        if (!IS_ERR(fclk)) {
+                clk_disable(fclk);
+                clk_put(fclk);
+        }
+
+        iclk = clk_get(dev, "ick");
+        if (!IS_ERR(iclk)) {
+                clk_disable(iclk);
+                clk_put(iclk);
+        }
+
+        return 0;
+};
+
+static int omap1_pm_runtime_resume(struct device *dev)
+{
+        int ret = 0;
+        struct clk *iclk, *fclk;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        iclk = clk_get(dev, "ick");
+        if (!IS_ERR(iclk)) {
+                clk_enable(iclk);
+                clk_put(iclk);
+        }
+
+        fclk = clk_get(dev, "fck");
+        if (!IS_ERR(fclk)) {
+                clk_enable(fclk);
+                clk_put(fclk);
+        }
+
+        return pm_generic_runtime_resume(dev);
+};
+
+static int __init omap1_pm_runtime_init(void)
+{
+        const struct dev_pm_ops *pm;
+        struct dev_pm_ops *omap_pm;
+
+        pm = platform_bus_get_pm_ops();
+        if (!pm) {
+                pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
+                        __func__);
+                return -ENODEV;
+        }
+
+        omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL);
+        if (!omap_pm) {
+                pr_err("%s: unable to alloc memory for new dev_pm_ops\n",
+                        __func__);
+                return -ENOMEM;
+        }
+
+        omap_pm->runtime_suspend = omap1_pm_runtime_suspend;
+        omap_pm->runtime_resume = omap1_pm_runtime_resume;
+
+        platform_bus_set_pm_ops(omap_pm);
+
+        return 0;
+}
+core_initcall(omap1_pm_runtime_init);
+#endif /* CONFIG_PM_RUNTIME */
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf0a7a..ab784bfde90 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -11,9 +11,8 @@ config ARCH_OMAP2PLUS_TYPICAL
         select PM_RUNTIME
         select VFP
         select NEON if ARCH_OMAP3 || ARCH_OMAP4
-        select SERIAL_8250
-        select SERIAL_CORE_CONSOLE
-        select SERIAL_8250_CONSOLE
+        select SERIAL_OMAP
+        select SERIAL_OMAP_CONSOLE
         select I2C
         select I2C_OMAP
         select MFD
@@ -35,7 +34,7 @@ config ARCH_OMAP3
         default y
         select CPU_V7
         select USB_ARCH_HAS_EHCI
-        select ARM_L1_CACHE_SHIFT_6
+        select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 
 config ARCH_OMAP4
         bool "TI OMAP4"
@@ -43,6 +42,8 @@ config ARCH_OMAP4
         depends on ARCH_OMAP2PLUS
         select CPU_V7
         select ARM_GIC
+        select PL310_ERRATA_588369
+        select ARM_ERRATA_720789
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
@@ -99,20 +100,20 @@ config MACH_OMAP2_TUSB6010
 
 config MACH_OMAP_H4
         bool "OMAP 2420 H4 board"
-        depends on ARCH_OMAP2
+        depends on ARCH_OMAP2420
         default y
         select OMAP_PACKAGE_ZAF
         select OMAP_DEBUG_DEVICES
 
 config MACH_OMAP_APOLLON
         bool "OMAP 2420 Apollon board"
-        depends on ARCH_OMAP2
+        depends on ARCH_OMAP2420
         default y
         select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP_2430SDP
         bool "OMAP 2430 SDP board"
-        depends on ARCH_OMAP2
+        depends on ARCH_OMAP2430
         default y
         select OMAP_PACKAGE_ZAC
 
@@ -135,6 +136,26 @@ config MACH_OMAP_LDP
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_OMAP3530_LV_SOM
+        bool "OMAP3 Logic 3530 LV SOM board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+        default y
+        help
+         Support for the LogicPD OMAP3530 SOM Development kit
+         for full description please see the products webpage at
+         http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
+
+config MACH_OMAP3_TORPEDO
+        bool "OMAP3 Logic 35x Torpedo board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+        default y
+        help
+         Support for the LogicPD OMAP35x Torpedo Development kit
+         for full description please see the products webpage at
+         http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
+
 config MACH_OVERO
         bool "Gumstix Overo board"
         depends on ARCH_OMAP3
@@ -200,12 +221,18 @@ config MACH_OMAP_ZOOM2
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select SERIAL_8250
+        select SERIAL_CORE_CONSOLE
+        select SERIAL_8250_CONSOLE
 
 config MACH_OMAP_ZOOM3
         bool "OMAP3630 Zoom3 board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBP
+        select SERIAL_8250
+        select SERIAL_CORE_CONSOLE
+        select SERIAL_8250_CONSOLE
 
 config MACH_CM_T35
         bool "CompuLab CM-T35 module"
@@ -214,12 +241,25 @@ config MACH_CM_T35
         select OMAP_PACKAGE_CUS
         select OMAP_MUX
 
+config MACH_CM_T3517
+        bool "CompuLab CM-T3517 module"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
+        select OMAP_MUX
+
 config MACH_IGEP0020
         bool "IGEP v2 board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_IGEP0030
+        bool "IGEP OMAP3 module"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
+
 config MACH_SBC3530
         bool "OMAP3 SBC STALKER board"
         depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 88d3a1e920f..7352412e491 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,9 +3,10 @@
 #
 
 # Common support
-obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o
+obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
+         common.o
 
-omap-2-3-common                         = irq.o sdrc.o
+omap-2-3-common                         = irq.o sdrc.o prm2xxx_3xxx.o
 hwmod-common                            = omap_hwmod.o \
                                           omap_hwmod_common_data.o
 prcm-common                             = prcm.o powerdomain.o
@@ -15,7 +16,7 @@ clock-common				= clock.o clock_common_data.o \
 
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common)
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
@@ -49,14 +50,18 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sdrc2xxx.o
 # Power Management
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o pm_bus.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a
 
+ifeq ($(CONFIG_PM_VERBOSE),y)
+CFLAGS_pm_bus.o                         += -DDEBUG
+endif
+
 endif
 
 # PRCM
@@ -87,6 +92,7 @@ obj-$(CONFIG_ARCH_OMAP2430)		+= opp2430_data.o
 obj-$(CONFIG_ARCH_OMAP2420)             += omap_hwmod_2420_data.o
 obj-$(CONFIG_ARCH_OMAP2430)             += omap_hwmod_2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
@@ -115,6 +121,10 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o \
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o \
                                            board-flash.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
+                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o \
@@ -146,8 +156,11 @@ obj-$(CONFIG_MACH_OMAP_3630SDP)		+= board-3630sdp.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_IGEP0030)             += board-igep0030.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
@@ -174,3 +187,6 @@ obj-y					+= $(nand-m) $(nand-y)
 
 smc91x-$(CONFIG_SMC91X)                 := gpmc-smc91x.o
 obj-y                                   += $(smc91x-m) $(smc91x-y)
+
+smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
+obj-y                                   += $(smsc911x-m) $(smsc911x-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 8538e4131d2..b527f8d187a 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -19,6 +19,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/mmc/host.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
 #include <linux/err.h>
@@ -190,7 +191,7 @@ static int __init omap2430_i2c_init(void)
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .ext_clock      = 1,
@@ -253,8 +254,6 @@ static void __init omap_2430sdp_map_io(void)
 
 MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_2430sdp_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 67b95b5f1a2..4e3742c512b 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -24,6 +24,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -38,15 +39,14 @@
 #include <plat/gpmc.h>
 #include <plat/display.h>
 
-#include <plat/control.h>
 #include <plat/gpmc-smc91x.h>
 
-#include <mach/board-flash.h>
-
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "control.h"
 
 #define CONFIG_DISABLE_HFCLK 1
 
@@ -76,7 +76,7 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = {
         {1, 10000, 30000, 300000},
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_A),
@@ -353,12 +353,12 @@ static struct omap2_hsmmc_info mmc[] = {
                 /* 8 bits (default) requires S6.3 == ON,
                  * so the SIM card isn't used; else 4 bits.
                  */
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 4,
         },
         {
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 7,
         },
         {}      /* Terminator */
@@ -817,8 +817,6 @@ static void __init omap_3430sdp_init(void)
 
 MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
         /* Maintainer: Syed Khasim - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index b359c3f7bb3..bbcf580fa09 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -21,8 +21,8 @@
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
-#include <mach/board-flash.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
@@ -208,7 +208,6 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-        omap_serial_init();
         zoom_peripherals_init();
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_sdp);
@@ -217,8 +216,6 @@ static void __init omap_sdp_init(void)
 }
 
 MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 9447644774c..69a4ae971e4 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,6 +20,7 @@
 #include <linux/usb/otg.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/twl.h>
+#include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/leds.h>
 
@@ -31,15 +32,18 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
-#include <plat/timer-gp.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+
 #include "hsmmc.h"
+#include "timer-gp.h"
+#include "control.h"
 
 #define ETH_KS8851_IRQ                  34
 #define ETH_KS8851_POWER_ON             48
 #define ETH_KS8851_QUART                138
+#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
+#define OMAP4_SFH7741_ENABLE_GPIO               188
 
 static struct gpio_led sdp4430_gpio_leds[] = {
         {
@@ -77,11 +81,47 @@ static struct gpio_led sdp4430_gpio_leds[] = {
 
 };
 
+static struct gpio_keys_button sdp4430_gpio_keys[] = {
+        {
+                .desc                   = "Proximity Sensor",
+                .type                   = EV_SW,
+                .code                   = SW_FRONT_PROXIMITY,
+                .gpio                   = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
+                .active_low             = 0,
+        }
+};
+
 static struct gpio_led_platform_data sdp4430_led_data = {
         .leds   = sdp4430_gpio_leds,
         .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
 };
 
+static int omap_prox_activate(struct device *dev)
+{
+        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
+        return 0;
+}
+
+static void omap_prox_deactivate(struct device *dev)
+{
+        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
+}
+
+static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
+        .buttons        = sdp4430_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(sdp4430_gpio_keys),
+        .enable         = omap_prox_activate,
+        .disable        = omap_prox_deactivate,
+};
+
+static struct platform_device sdp4430_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &sdp4430_gpio_keys_data,
+        },
+};
+
 static struct platform_device sdp4430_leds_gpio = {
         .name   = "leds-gpio",
         .id     = -1,
@@ -161,6 +201,7 @@ static struct platform_device sdp4430_lcd_device = {
 
 static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_lcd_device,
+        &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
 };
 
@@ -193,15 +234,16 @@ static struct omap_musb_board_data musb_board_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
         },
         {
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           =  MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
+                .ocr_mask       = MMC_VDD_29_30,
         },
         {}      /* Terminator */
 };
@@ -235,8 +277,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
 {
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
+        struct omap_mmc_platform_data *pdata;
 
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed %s\n", __func__);
+                return;
+        }
+        pdata = dev->platform_data;
         pdata->init =   omap4_twl6030_hsmmc_late_init;
 }
 
@@ -412,6 +460,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
                 I2C_BOARD_INFO("tmp105", 0x48),
         },
 };
+static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("hmc5843", 0x1e),
+        },
+};
 static int __init omap4_i2c_init(void)
 {
         /*
@@ -423,14 +476,36 @@ static int __init omap4_i2c_init(void)
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
-        omap_register_i2c_bus(4, 400, NULL, 0);
+        omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
+                                ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
         return 0;
 }
+
+static void __init omap_sfh7741prox_init(void)
+{
+        int  error;
+
+        error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741");
+        if (error < 0) {
+                pr_err("%s:failed to request GPIO %d, error %d\n",
+                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
+                return;
+        }
+
+        error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0);
+        if (error < 0) {
+                pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n",
+                         __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
+                gpio_free(OMAP4_SFH7741_ENABLE_GPIO);
+        }
+}
+
 static void __init omap_4430sdp_init(void)
 {
         int status;
 
         omap4_i2c_init();
+        omap_sfh7741prox_init();
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
@@ -458,8 +533,6 @@ static void __init omap_4430sdp_map_io(void)
 
 MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_4430sdp_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4d0f5859286..07399505312 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/i2c/pca953x.h>
@@ -32,25 +33,43 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/usb.h>
 #include <plat/display.h>
 
 #include "mux.h"
+#include "control.h"
 
-#define AM35XX_EVM_PHY_MASK             (0xF)
 #define AM35XX_EVM_MDIO_FREQUENCY       (1000000)
 
+static struct mdio_platform_data am3517_evm_mdio_pdata = {
+        .bus_freq       = AM35XX_EVM_MDIO_FREQUENCY,
+};
+
+static struct resource am3517_mdio_resources[] = {
+        {
+                .start  = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET,
+                .end    = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET +
+                          SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device am3517_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(am3517_mdio_resources),
+        .resource       = am3517_mdio_resources,
+        .dev.platform_data = &am3517_evm_mdio_pdata,
+};
+
 static struct emac_platform_data am3517_evm_emac_pdata = {
-        .phy_mask       = AM35XX_EVM_PHY_MASK,
-        .mdio_max_freq  = AM35XX_EVM_MDIO_FREQUENCY,
         .rmii_en        = 1,
 };
 
 static struct resource am3517_emac_resources[] = {
         {
                 .start  = AM35XX_IPSS_EMAC_BASE,
-                .end    = AM35XX_IPSS_EMAC_BASE + 0x3FFFF,
+                .end    = AM35XX_IPSS_EMAC_BASE + 0x2FFFF,
                 .flags  = IORESOURCE_MEM,
         },
         {
@@ -106,14 +125,13 @@ static void am3517_disable_ethernet_int(void)
         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 }
 
-void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
+static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 {
         unsigned int regval;
 
         pdata->ctrl_reg_offset          = AM35XX_EMAC_CNTRL_OFFSET;
         pdata->ctrl_mod_reg_offset      = AM35XX_EMAC_CNTRL_MOD_OFFSET;
         pdata->ctrl_ram_offset          = AM35XX_EMAC_CNTRL_RAM_OFFSET;
-        pdata->mdio_reg_offset          = AM35XX_EMAC_MDIO_OFFSET;
         pdata->ctrl_ram_size            = AM35XX_EMAC_CNTRL_RAM_SIZE;
         pdata->version                  = EMAC_VERSION_2;
         pdata->hw_ram_addr              = AM35XX_EMAC_HW_RAM_ADDR;
@@ -121,6 +139,9 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
         pdata->interrupt_disable        = am3517_disable_ethernet_int;
         am3517_emac_device.dev.platform_data    = pdata;
         platform_device_register(&am3517_emac_device);
+        platform_device_register(&am3517_mdio_device);
+        clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev),
+                      NULL, &am3517_emac_device.dev);
 
         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
         regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
@@ -139,7 +160,6 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = {
         {
                 I2C_BOARD_INFO("s35390a", 0x30),
-                .type           = "s35390a",
         },
 };
 
@@ -347,7 +367,7 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
         .default_device = &am3517_evm_lcd_device,
 };
 
-struct platform_device am3517_evm_dss_device = {
+static struct platform_device am3517_evm_dss_device = {
         .name           = "omapdss",
         .id             = -1,
         .dev            = {
@@ -375,6 +395,31 @@ static void __init am3517_evm_init_irq(void)
         omap_gpio_init();
 }
 
+static struct omap_musb_board_data musb_board_data = {
+        .interface_type         = MUSB_INTERFACE_ULPI,
+        .mode                   = MUSB_OTG,
+        .power                  = 500,
+};
+
+static __init void am3517_evm_musb_init(void)
+{
+        u32 devconf2;
+
+        /*
+         * Set up USB clock/mode in the DEVCONF2 register.
+         */
+        devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+        /* USB2.0 PHY reference clock is 13 MHz */
+        devconf2 &= ~(CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE);
+        devconf2 |=  CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | CONF2_VBDTCTEN
+                        | CONF2_DATPOL;
+
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+
+        usb_musb_init(&musb_board_data);
+}
+
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -393,6 +438,8 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* USB OTG DRVVBUS offset = 0x212 */
+        OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
@@ -459,11 +506,12 @@ static void __init am3517_evm_init(void)
                                 ARRAY_SIZE(am3517evm_i2c1_boardinfo));
         /*Ethernet*/
         am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
+
+        /* MUSB */
+        am3517_evm_musb_init();
 }
 
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index c6421a72514..2c6db1aaeb2 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -39,9 +39,9 @@
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
-#include <plat/control.h>
 
 #include "mux.h"
+#include "control.h"
 
 /* LED & Switch macros */
 #define LED0_GPIO13             13
@@ -356,8 +356,6 @@ static void __init omap_apollon_map_io(void)
 
 MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_apollon_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e10bc109415..63f764e2af3 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/mmc/host.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/tdo24m.h>
@@ -237,8 +238,6 @@ static inline void cm_t35_init_nand(void) {}
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 #include <linux/spi/ads7846.h>
 
-#include <plat/mcspi.h>
-
 static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .turbo_mode     = 0,
         .single_channel = 1,    /* 0: slave, 1: master */
@@ -558,7 +557,7 @@ static struct twl4030_usb_data cm_t35_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int cm_t35_keymap[] = {
+static uint32_t cm_t35_keymap[] = {
         KEY(0, 0, KEY_A),       KEY(0, 1, KEY_B),       KEY(0, 2, KEY_LEFT),
         KEY(1, 0, KEY_UP),      KEY(1, 1, KEY_ENTER),   KEY(1, 2, KEY_DOWN),
         KEY(2, 0, KEY_RIGHT),   KEY(2, 1, KEY_C),       KEY(2, 2, KEY_D),
@@ -579,14 +578,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
 
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .transceiver    = 1,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
@@ -809,8 +808,6 @@ static void __init cm_t35_init(void)
 }
 
 MACHINE_START(CM_T35, "Compulab CM-T35")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
new file mode 100644
index 00000000000..1dd303e9a26
--- /dev/null
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -0,0 +1,292 @@
+/*
+ * linux/arch/arm/mach-omap2/board-cm-t3517.c
+ *
+ * Support for the CompuLab CM-T3517 modules
+ *
+ * Copyright (C) 2010 CompuLab, Ltd.
+ * Author: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/rtc-v3020.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/can/platform/ti_hecc.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/usb.h>
+#include <plat/nand.h>
+#include <plat/gpmc.h>
+
+#include <mach/am35xx.h>
+
+#include "mux.h"
+#include "control.h"
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led cm_t3517_leds[] = {
+        [0] = {
+                .gpio                   = 186,
+                .name                   = "cm-t3517:green",
+                .default_trigger        = "heartbeat",
+                .active_low             = 0,
+        },
+};
+
+static struct gpio_led_platform_data cm_t3517_led_pdata = {
+        .num_leds       = ARRAY_SIZE(cm_t3517_leds),
+        .leds           = cm_t3517_leds,
+};
+
+static struct platform_device cm_t3517_led_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &cm_t3517_led_pdata,
+        },
+};
+
+static void __init cm_t3517_init_leds(void)
+{
+        platform_device_register(&cm_t3517_led_device);
+}
+#else
+static inline void cm_t3517_init_leds(void) {}
+#endif
+
+#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE)
+static struct resource cm_t3517_hecc_resources[] = {
+        {
+                .start  = AM35XX_IPSS_HECC_BASE,
+                .end    = AM35XX_IPSS_HECC_BASE + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_35XX_HECC0_IRQ,
+                .end    = INT_35XX_HECC0_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct ti_hecc_platform_data cm_t3517_hecc_pdata = {
+        .scc_hecc_offset        = AM35XX_HECC_SCC_HECC_OFFSET,
+        .scc_ram_offset         = AM35XX_HECC_SCC_RAM_OFFSET,
+        .hecc_ram_offset        = AM35XX_HECC_RAM_OFFSET,
+        .mbx_offset             = AM35XX_HECC_MBOX_OFFSET,
+        .int_line               = AM35XX_HECC_INT_LINE,
+        .version                = AM35XX_HECC_VERSION,
+};
+
+static struct platform_device cm_t3517_hecc_device = {
+        .name           = "ti_hecc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(cm_t3517_hecc_resources),
+        .resource       = cm_t3517_hecc_resources,
+        .dev            = {
+                .platform_data  = &cm_t3517_hecc_pdata,
+        },
+};
+
+static void cm_t3517_init_hecc(void)
+{
+        platform_device_register(&cm_t3517_hecc_device);
+}
+#else
+static inline void cm_t3517_init_hecc(void) {}
+#endif
+
+#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
+#define RTC_IO_GPIO             (153)
+#define RTC_WR_GPIO             (154)
+#define RTC_RD_GPIO             (160)
+#define RTC_CS_GPIO             (163)
+
+struct v3020_platform_data cm_t3517_v3020_pdata = {
+        .use_gpio       = 1,
+        .gpio_cs        = RTC_CS_GPIO,
+        .gpio_wr        = RTC_WR_GPIO,
+        .gpio_rd        = RTC_RD_GPIO,
+        .gpio_io        = RTC_IO_GPIO,
+};
+
+static struct platform_device cm_t3517_rtc_device = {
+        .name           = "v3020",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cm_t3517_v3020_pdata,
+        }
+};
+
+static void __init cm_t3517_init_rtc(void)
+{
+        platform_device_register(&cm_t3517_rtc_device);
+}
+#else
+static inline void cm_t3517_init_rtc(void) {}
+#endif
+
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+#define HSUSB1_RESET_GPIO       (146)
+#define HSUSB2_RESET_GPIO       (147)
+#define USB_HUB_RESET_GPIO      (152)
+
+static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = {
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+        .phy_reset  = true,
+        .reset_gpio_port[0]  = HSUSB1_RESET_GPIO,
+        .reset_gpio_port[1]  = HSUSB2_RESET_GPIO,
+        .reset_gpio_port[2]  = -EINVAL,
+};
+
+static int cm_t3517_init_usbh(void)
+{
+        int err;
+
+        err = gpio_request(USB_HUB_RESET_GPIO, "usb hub rst");
+        if (err) {
+                pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err);
+        } else {
+                gpio_direction_output(USB_HUB_RESET_GPIO, 0);
+                udelay(10);
+                gpio_set_value(USB_HUB_RESET_GPIO, 1);
+                msleep(1);
+        }
+
+        usb_ehci_init(&cm_t3517_ehci_pdata);
+
+        return 0;
+}
+#else
+static inline int cm_t3517_init_usbh(void)
+{
+        return 0;
+}
+#endif
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+#define NAND_BLOCK_SIZE         SZ_128K
+
+static struct mtd_partition cm_t3517_nand_partitions[] = {
+        {
+                .name           = "xloader",
+                .offset         = 0,                    /* Offset = 0x00000 */
+                .size           = 4 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE
+        },
+        {
+                .name           = "uboot",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+                .size           = 15 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "uboot environment",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
+                .size           = 2 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "linux",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
+                .size           = 32 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "rootfs",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x680000 */
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_nand_platform_data cm_t3517_nand_data = {
+        .parts                  = cm_t3517_nand_partitions,
+        .nr_parts               = ARRAY_SIZE(cm_t3517_nand_partitions),
+        .dma_channel            = -1,   /* disable DMA in OMAP NAND driver */
+        .cs                     = 0,
+};
+
+static void __init cm_t3517_init_nand(void)
+{
+        if (gpmc_nand_init(&cm_t3517_nand_data) < 0)
+                pr_err("CM-T3517: NAND initialization failed\n");
+}
+#else
+static inline void cm_t3517_init_nand(void) {}
+#endif
+
+static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
+};
+
+static void __init cm_t3517_init_irq(void)
+{
+        omap_board_config = cm_t3517_config;
+        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
+
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+static struct omap_board_mux board_mux[] __initdata = {
+        /* GPIO186 - Green LED */
+        OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* RTC GPIOs: IO, WR#, RD#, CS# */
+        OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        /* HSUSB1 RESET */
+        OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* HSUSB2 RESET */
+        OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* CM-T3517 USB HUB nRESET */
+        OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+static void __init cm_t3517_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_serial_init();
+        cm_t3517_init_leds();
+        cm_t3517_init_nand();
+        cm_t3517_init_rtc();
+        cm_t3517_init_usbh();
+        cm_t3517_init_hecc();
+}
+
+MACHINE_START(CM_T3517, "Compulab CM-T3517")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .reserve        = omap_reserve,
+        .init_irq       = cm_t3517_init_irq,
+        .init_machine   = cm_t3517_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a07086d6a0b..067f4379c87 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -44,7 +45,6 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 #include <plat/display.h>
 
 #include <plat/mcspi.h>
@@ -58,6 +58,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
@@ -105,7 +106,7 @@ static struct omap_nand_platform_data devkit8000_nand_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -198,7 +199,7 @@ static struct platform_device devkit8000_dss_device = {
 static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
         KEY(2, 0, KEY_3),
@@ -800,8 +801,6 @@ static void __init devkit8000_init(void)
 }
 
 MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index ac834aa7abf..fd38c05bb47 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -21,7 +21,8 @@
 #include <plat/nand.h>
 #include <plat/onenand.h>
 #include <plat/tc.h>
-#include <mach/board-flash.h>
+
+#include "board-flash.h"
 
 #define REG_FPGA_REV                    0x10
 #define REG_FPGA_DIP_SWITCH_INPUT2      0x60
diff --git a/arch/arm/mach-omap2/include/mach/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index b2242ae2bb6..69befe00dd2 100644
--- a/arch/arm/mach-omap2/include/mach/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -26,3 +26,5 @@ struct flash_partitions {
 
 extern void board_flash_init(struct flash_partitions [],
                                 char chip_sel[][GPMC_CS_NUM]);
+extern void board_nand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3482b99e8c8..b1c2c9a11c3 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -48,14 +48,24 @@ static void __init omap_generic_init(void)
 
 static void __init omap_generic_map_io(void)
 {
-        omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */
-        omap242x_map_common_io();
+        if (cpu_is_omap242x()) {
+                omap2_set_globals_242x();
+                omap242x_map_common_io();
+        } else if (cpu_is_omap243x()) {
+                omap2_set_globals_243x();
+                omap243x_map_common_io();
+        } else if (cpu_is_omap34xx()) {
+                omap2_set_globals_3xxx();
+                omap34xx_map_common_io();
+        } else if (cpu_is_omap44xx()) {
+                omap2_set_globals_443x();
+                omap44xx_map_common_io();
+        }
 }
 
+/* XXX This machine entry name should be updated */
 MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_generic_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e09bd686389..929993b4bf2 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -31,7 +31,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/control.h>
 #include <mach/gpio.h>
 #include <plat/usb.h>
 #include <plat/board.h>
@@ -42,6 +41,7 @@
 #include <plat/gpmc.h>
 
 #include "mux.h"
+#include "control.h"
 
 #define H4_FLASH_CS     0
 #define H4_SMC91X_CS    1
@@ -376,8 +376,6 @@ static void __init omap_h4_map_io(void)
 
 MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_h4_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 175f0433976..5e035a58b80 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -20,6 +20,7 @@
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -38,12 +39,61 @@
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
 #define IGEP2_GPIO_USBH_NRESET  24
-#define IGEP2_GPIO_LED0_GREEN   26
-#define IGEP2_GPIO_LED0_RED     27
-#define IGEP2_GPIO_LED1_RED     28
-#define IGEP2_GPIO_DVI_PUP      170
-#define IGEP2_GPIO_WIFI_NPD     94
-#define IGEP2_GPIO_WIFI_NRESET  95
+#define IGEP2_GPIO_LED0_GREEN   26
+#define IGEP2_GPIO_LED0_RED     27
+#define IGEP2_GPIO_LED1_RED     28
+#define IGEP2_GPIO_DVI_PUP      170
+
+#define IGEP2_RB_GPIO_WIFI_NPD     94
+#define IGEP2_RB_GPIO_WIFI_NRESET  95
+#define IGEP2_RB_GPIO_BT_NRESET    137
+#define IGEP2_RC_GPIO_WIFI_NPD     138
+#define IGEP2_RC_GPIO_WIFI_NRESET  139
+#define IGEP2_RC_GPIO_BT_NRESET    137
+
+/*
+ * IGEP2 Hardware Revision Table
+ *
+ *  --------------------------------------------------------------------------
+ * | Id. | Hw Rev.            | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET |
+ *  --------------------------------------------------------------------------
+ * |  0  | B                  |   high   |  gpio94  |   gpio95    |     -     |
+ * |  0  | B/C (B-compatible) |   high   |  gpio94  |   gpio95    |  gpio137  |
+ * |  1  | C                  |   low    |  gpio138 |   gpio139   |  gpio137  |
+ *  --------------------------------------------------------------------------
+ */
+
+#define IGEP2_BOARD_HWREV_B     0
+#define IGEP2_BOARD_HWREV_C     1
+
+static u8 hwrev;
+
+static void __init igep2_get_revision(void)
+{
+        u8 ret;
+
+        omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT);
+
+        if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_HW0_REV") == 0) &&
+            (gpio_direction_input(IGEP2_GPIO_LED1_RED) == 0)) {
+                ret = gpio_get_value(IGEP2_GPIO_LED1_RED);
+                if (ret == 0) {
+                        pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n");
+                        hwrev = IGEP2_BOARD_HWREV_C;
+                } else if (ret ==  1) {
+                        pr_info("IGEP2: Hardware Revision B/C (B compatible)\n");
+                        hwrev = IGEP2_BOARD_HWREV_B;
+                } else {
+                        pr_err("IGEP2: Unknown Hardware Revision\n");
+                        hwrev = -1;
+                }
+        } else {
+                pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n");
+                pr_err("IGEP2: Unknown Hardware Revision\n");
+        }
+
+        gpio_free(IGEP2_GPIO_LED1_RED);
+}
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
         defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
@@ -107,7 +157,7 @@ static struct platform_device igep2_onenand_device = {
         },
 };
 
-void __init igep2_flash_init(void)
+static void __init igep2_flash_init(void)
 {
         u8              cs = 0;
         u8              onenandcs = GPMC_CS_NUM + 1;
@@ -141,7 +191,7 @@ void __init igep2_flash_init(void)
 }
 
 #else
-void __init igep2_flash_init(void) {}
+static void __init igep2_flash_init(void) {}
 #endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@@ -211,10 +261,6 @@ static struct regulator_consumer_supply igep2_vmmc1_supply = {
         .supply         = "vmmc",
 };
 
-static struct regulator_consumer_supply igep2_vmmc2_supply = {
-        .supply         = "vmmc",
-};
-
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data igep2_vmmc1 = {
         .constraints = {
@@ -230,37 +276,95 @@ static struct regulator_init_data igep2_vmmc1 = {
         .consumer_supplies      = &igep2_vmmc1_supply,
 };
 
-/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */
-static struct regulator_init_data igep2_vmmc2 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vmmc2_supply,
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
+#endif
         {}      /* Terminator */
 };
 
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#include <linux/leds.h>
+
+static struct gpio_led igep2_gpio_leds[] = {
+        [0] = {
+                .name                   = "gpio-led:red:d0",
+                .gpio                   = IGEP2_GPIO_LED0_RED,
+                .default_trigger        = "default-off"
+        },
+        [1] = {
+                .name                   = "gpio-led:green:d0",
+                .gpio                   = IGEP2_GPIO_LED0_GREEN,
+                .default_trigger        = "default-off",
+        },
+        [2] = {
+                .name                   = "gpio-led:red:d1",
+                .gpio                   = IGEP2_GPIO_LED1_RED,
+                .default_trigger        = "default-off",
+        },
+        [3] = {
+                .name                   = "gpio-led:green:d1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = -EINVAL, /* gets replaced */
+        },
+};
+
+static struct gpio_led_platform_data igep2_led_pdata = {
+        .leds           = igep2_gpio_leds,
+        .num_leds       = ARRAY_SIZE(igep2_gpio_leds),
+};
+
+static struct platform_device igep2_led_device = {
+         .name   = "leds-gpio",
+         .id     = -1,
+         .dev    = {
+                 .platform_data  =  &igep2_led_pdata,
+        },
+};
+
+static void __init igep2_leds_init(void)
+{
+        platform_device_register(&igep2_led_device);
+}
+
+#else
+static inline void igep2_leds_init(void)
+{
+        if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
+            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
+                gpio_export(IGEP2_GPIO_LED0_RED, 0);
+                gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
+
+        if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
+            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
+                gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
+                gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
+
+        if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
+            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
+                gpio_export(IGEP2_GPIO_LED1_RED, 0);
+                gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
+
+}
+#endif
+
 static int igep2_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -268,20 +372,48 @@ static int igep2_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters ... we "know" the
+        /*
+         * link regulators to MMC adapters ... we "know" the
          * regulators will be set up only *after* we return.
-        */
+         */
         igep2_vmmc1_supply.dev = mmc[0].dev;
-        igep2_vmmc2_supply.dev = mmc[1].dev;
+
+        /*
+         * REVISIT: need ehci-omap hooks for external VBUS
+         * power switch and overcurrent detect
+         */
+        if ((gpio_request(gpio + 1, "GPIO_EHCI_NOC") < 0) ||
+            (gpio_direction_input(gpio + 1) < 0))
+                pr_err("IGEP2: Could not obtain gpio for EHCI NOC");
+
+        /*
+         * TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN
+         * (out, active low)
+         */
+        if ((gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USBH_CPEN") < 0) ||
+            (gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0) < 0))
+                pr_err("IGEP2: Could not obtain gpio for USBH_CPEN");
+
+        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
+#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
+        if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
+            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) {
+                gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
+                gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n");
+#else
+        igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
+#endif
 
         return 0;
 };
 
-static struct twl4030_gpio_platform_data igep2_gpio_data = {
+static struct twl4030_gpio_platform_data igep2_twl4030_gpio_pdata = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
-        .use_leds       = false,
+        .use_leds       = true,
         .setup          = igep2_twl_gpio_setup,
 };
 
@@ -355,47 +487,6 @@ static void __init igep2_display_init(void)
                 pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
 }
 
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-#include <linux/leds.h>
-
-static struct gpio_led igep2_gpio_leds[] = {
-        {
-                .name = "led0:red",
-                .gpio = IGEP2_GPIO_LED0_RED,
-        },
-        {
-                .name = "led0:green",
-                .default_trigger = "heartbeat",
-                .gpio = IGEP2_GPIO_LED0_GREEN,
-        },
-        {
-                .name = "led1:red",
-                .gpio = IGEP2_GPIO_LED1_RED,
-        },
-};
-
-static struct gpio_led_platform_data igep2_led_pdata = {
-        .leds           = igep2_gpio_leds,
-        .num_leds       = ARRAY_SIZE(igep2_gpio_leds),
-};
-
-static struct platform_device igep2_led_device = {
-         .name   = "leds-gpio",
-         .id     = -1,
-         .dev    = {
-                 .platform_data  =  &igep2_led_pdata,
-        },
-};
-
-static void __init igep2_init_led(void)
-{
-        platform_device_register(&igep2_led_device);
-}
-
-#else
-static inline void igep2_init_led(void) {}
-#endif
-
 static struct platform_device *igep2_devices[] __initdata = {
         &igep2_dss_device,
 };
@@ -425,14 +516,13 @@ static struct twl4030_platform_data igep2_twldata = {
         /* platform_data for children goes here */
         .usb            = &igep2_usb_data,
         .codec          = &igep2_codec_data,
-        .gpio           = &igep2_gpio_data,
+        .gpio           = &igep2_twl4030_gpio_pdata,
         .vmmc1          = &igep2_vmmc1,
-        .vmmc2          = &igep2_vmmc2,
         .vpll2          = &igep2_vpll2,
 
 };
 
-static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = {
+static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = {
         {
                 I2C_BOARD_INFO("twl4030", 0x48),
                 .flags          = I2C_CLIENT_WAKE,
@@ -441,14 +531,29 @@ static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = {
         },
 };
 
-static int __init igep2_i2c_init(void)
+static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("eeprom", 0x50),
+        },
+};
+
+static void __init igep2_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, igep2_i2c_boardinfo,
-                        ARRAY_SIZE(igep2_i2c_boardinfo));
-        /* Bus 3 is attached to the DVI port where devices like the pico DLP
-         * projector don't work reliably with 400kHz */
-        omap_register_i2c_bus(3, 100, NULL, 0);
-        return 0;
+        int ret;
+
+        ret = omap_register_i2c_bus(1, 2600, igep2_i2c1_boardinfo,
+                ARRAY_SIZE(igep2_i2c1_boardinfo));
+        if (ret)
+                pr_warning("IGEP2: Could not register I2C1 bus (%d)\n", ret);
+
+        /*
+         * Bus 3 is attached to the DVI port where devices like the pico DLP
+         * projector don't work reliably with 400kHz
+         */
+        ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo,
+                ARRAY_SIZE(igep2_i2c3_boardinfo));
+        if (ret)
+                pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
 }
 
 static struct omap_musb_board_data musb_board_data = {
@@ -476,9 +581,57 @@ static struct omap_board_mux board_mux[] __initdata = {
 #define board_mux       NULL
 #endif
 
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+
+static void __init igep2_wlan_bt_init(void)
+{
+        unsigned npd, wreset, btreset;
+
+        /* GPIO's for WLAN-BT combo depends on hardware revision */
+        if (hwrev == IGEP2_BOARD_HWREV_B) {
+                npd = IGEP2_RB_GPIO_WIFI_NPD;
+                wreset = IGEP2_RB_GPIO_WIFI_NRESET;
+                btreset = IGEP2_RB_GPIO_BT_NRESET;
+        } else if (hwrev == IGEP2_BOARD_HWREV_C) {
+                npd = IGEP2_RC_GPIO_WIFI_NPD;
+                wreset = IGEP2_RC_GPIO_WIFI_NRESET;
+                btreset = IGEP2_RC_GPIO_BT_NRESET;
+        } else
+                return;
+
+        /* Set GPIO's for  WLAN-BT combo module */
+        if ((gpio_request(npd, "GPIO_WIFI_NPD") == 0) &&
+            (gpio_direction_output(npd, 1) == 0)) {
+                gpio_export(npd, 0);
+        } else
+                pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NPD\n");
+
+        if ((gpio_request(wreset, "GPIO_WIFI_NRESET") == 0) &&
+            (gpio_direction_output(wreset, 1) == 0)) {
+                gpio_export(wreset, 0);
+                gpio_set_value(wreset, 0);
+                udelay(10);
+                gpio_set_value(wreset, 1);
+        } else
+                pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NRESET\n");
+
+        if ((gpio_request(btreset, "GPIO_BT_NRESET") == 0) &&
+            (gpio_direction_output(btreset, 1) == 0)) {
+                gpio_export(btreset, 0);
+        } else
+                pr_warning("IGEP2: Could not obtain gpio GPIO_BT_NRESET\n");
+}
+#else
+static inline void __init igep2_wlan_bt_init(void) { }
+#endif
+
 static void __init igep2_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        /* Get IGEP2 hardware revision */
+        igep2_get_revision();
+        /* Register I2C busses and drivers */
         igep2_i2c_init();
         platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
         omap_serial_init();
@@ -486,55 +639,19 @@ static void __init igep2_init(void)
         usb_ehci_init(&ehci_pdata);
 
         igep2_flash_init();
-        igep2_init_led();
+        igep2_leds_init();
         igep2_display_init();
         igep2_init_smsc911x();
 
-        /* GPIO userspace leds */
-#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
-        if ((gpio_request(IGEP2_GPIO_LED0_RED, "led0:red") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED0_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
-
-        if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "led0:green") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
-
-        if ((gpio_request(IGEP2_GPIO_LED1_RED, "led1:red") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED1_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
-#endif
-
-        /* GPIO W-LAN + Bluetooth combo module */
-        if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_WIFI_NPD, 0);
-/*              gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n");
+        /*
+         * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+         * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
+         */
+        igep2_wlan_bt_init();
 
-        if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_WIFI_NRESET, 0);
-                gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0);
-                udelay(10);
-                gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n");
 }
 
 MACHINE_START(IGEP0020, "IGEP v2 board")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
new file mode 100644
index 00000000000..22b0b253e16
--- /dev/null
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -0,0 +1,400 @@
+/*
+ * Copyright (C) 2010 - ISEE 2007 SL
+ *
+ * Modified from mach-omap2/board-generic.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+
+#include <linux/regulator/machine.h>
+#include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc.h>
+#include <plat/usb.h>
+#include <plat/onenand.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "sdram-numonyx-m65kxxxxam.h"
+
+#define IGEP3_GPIO_LED0_GREEN   54
+#define IGEP3_GPIO_LED0_RED     53
+#define IGEP3_GPIO_LED1_RED     16
+
+#define IGEP3_GPIO_WIFI_NPD     138
+#define IGEP3_GPIO_WIFI_NRESET  139
+#define IGEP3_GPIO_BT_NRESET    137
+
+#define IGEP3_GPIO_USBH_NRESET  115
+
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+
+#define ONENAND_MAP             0x20000000
+
+/*
+ * x2 Flash built-in COMBO POP MEMORY
+ * Since the device is equipped with two DataRAMs, and two-plane NAND
+ * Flash memory array, these two component enables simultaneous program
+ * of 4KiB. Plane1 has only even blocks such as block0, block2, block4
+ * while Plane2 has only odd blocks such as block1, block3, block5.
+ * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
+ */
+
+static struct mtd_partition igep3_onenand_partitions[] = {
+        {
+                .name           = "X-Loader",
+                .offset         = 0,
+                .size           = 2 * (64*(2*2048))
+        },
+        {
+                .name           = "U-Boot",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 6 * (64*(2*2048)),
+        },
+        {
+                .name           = "Environment",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 2 * (64*(2*2048)),
+        },
+        {
+                .name           = "Kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 12 * (64*(2*2048)),
+        },
+        {
+                .name           = "File System",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_onenand_platform_data igep3_onenand_pdata = {
+        .parts = igep3_onenand_partitions,
+        .nr_parts = ARRAY_SIZE(igep3_onenand_partitions),
+        .onenand_setup = NULL,
+        .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
+};
+
+static struct platform_device igep3_onenand_device = {
+        .name           = "omap2-onenand",
+        .id             = -1,
+        .dev = {
+                .platform_data = &igep3_onenand_pdata,
+        },
+};
+
+void __init igep3_flash_init(void)
+{
+        u8 cs = 0;
+        u8 onenandcs = GPMC_CS_NUM + 1;
+
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                u32 ret;
+                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+                /* Check if NAND/oneNAND is configured */
+                if ((ret & 0xC00) == 0x800)
+                        /* NAND found */
+                        pr_err("IGEP3: Unsupported NAND found\n");
+                else {
+                        ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+
+                        if ((ret & 0x3F) == (ONENAND_MAP >> 24))
+                                /* OneNAND found */
+                                onenandcs = cs;
+                }
+        }
+
+        if (onenandcs > GPMC_CS_NUM) {
+                pr_err("IGEP3: Unable to find configuration in GPMC\n");
+                return;
+        }
+
+        igep3_onenand_pdata.cs = onenandcs;
+
+        if (platform_device_register(&igep3_onenand_device) < 0)
+                pr_err("IGEP3: Unable to register OneNAND device\n");
+}
+
+#else
+void __init igep3_flash_init(void) {}
+#endif
+
+static struct regulator_consumer_supply igep3_vmmc1_supply = {
+        .supply         = "vmmc",
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data igep3_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &igep3_vmmc1_supply,
+};
+
+static struct omap2_hsmmc_info mmc[] = {
+        [0] = {
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+        [1] = {
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+#endif
+        {}      /* Terminator */
+};
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#include <linux/leds.h>
+
+static struct gpio_led igep3_gpio_leds[] = {
+        [0] = {
+                .name                   = "gpio-led:red:d0",
+                .gpio                   = IGEP3_GPIO_LED0_RED,
+                .default_trigger        = "default-off"
+        },
+        [1] = {
+                .name                   = "gpio-led:green:d0",
+                .gpio                   = IGEP3_GPIO_LED0_GREEN,
+                .default_trigger        = "default-off",
+        },
+        [2] = {
+                .name                   = "gpio-led:red:d1",
+                .gpio                   = IGEP3_GPIO_LED1_RED,
+                .default_trigger        = "default-off",
+        },
+        [3] = {
+                .name                   = "gpio-led:green:d1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = -EINVAL, /* gets replaced */
+        },
+};
+
+static struct gpio_led_platform_data igep3_led_pdata = {
+        .leds           = igep3_gpio_leds,
+        .num_leds       = ARRAY_SIZE(igep3_gpio_leds),
+};
+
+static struct platform_device igep3_led_device = {
+         .name   = "leds-gpio",
+         .id     = -1,
+         .dev    = {
+                 .platform_data = &igep3_led_pdata,
+        },
+};
+
+static void __init igep3_leds_init(void)
+{
+        platform_device_register(&igep3_led_device);
+}
+
+#else
+static inline void igep3_leds_init(void)
+{
+        if ((gpio_request(IGEP3_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_LED0_RED, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_LED0_RED, 0);
+                gpio_set_value(IGEP3_GPIO_LED0_RED, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_RED\n");
+
+        if ((gpio_request(IGEP3_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_LED0_GREEN, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_LED0_GREEN, 0);
+                gpio_set_value(IGEP3_GPIO_LED0_GREEN, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_GREEN\n");
+
+        if ((gpio_request(IGEP3_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
+                (gpio_direction_output(IGEP3_GPIO_LED1_RED, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_LED1_RED, 0);
+                gpio_set_value(IGEP3_GPIO_LED1_RED, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_RED\n");
+}
+#endif
+
+static int igep3_twl4030_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
+{
+        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+        mmc[0].gpio_cd = gpio + 0;
+        omap2_hsmmc_init(mmc);
+
+        /*
+         * link regulators to MMC adapters ... we "know" the
+         * regulators will be set up only *after* we return.
+         */
+        igep3_vmmc1_supply.dev = mmc[0].dev;
+
+        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
+#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
+        if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
+            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) {
+                gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
+                gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_GREEN\n");
+#else
+        igep3_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
+#endif
+
+        return 0;
+};
+
+static struct twl4030_gpio_platform_data igep3_twl4030_gpio_pdata = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .setup          = igep3_twl4030_gpio_setup,
+};
+
+static struct twl4030_usb_data igep3_twl4030_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+static void __init igep3_init_irq(void)
+{
+        omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+static struct twl4030_platform_data igep3_twl4030_pdata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .usb            = &igep3_twl4030_usb_data,
+        .gpio           = &igep3_twl4030_gpio_pdata,
+        .vmmc1          = &igep3_vmmc1,
+};
+
+static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags          = I2C_CLIENT_WAKE,
+                .irq            = INT_34XX_SYS_NIRQ,
+                .platform_data  = &igep3_twl4030_pdata,
+        },
+};
+
+static int __init igep3_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, igep3_i2c_boardinfo,
+                        ARRAY_SIZE(igep3_i2c_boardinfo));
+
+        return 0;
+}
+
+static struct omap_musb_board_data musb_board_data = {
+        .interface_type = MUSB_INTERFACE_ULPI,
+        .mode           = MUSB_OTG,
+        .power          = 100,
+};
+
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+
+static void __init igep3_wifi_bt_init(void)
+{
+        /* Configure MUX values for W-LAN + Bluetooth GPIO's */
+        omap_mux_init_gpio(IGEP3_GPIO_WIFI_NPD, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(IGEP3_GPIO_WIFI_NRESET, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(IGEP3_GPIO_BT_NRESET, OMAP_PIN_OUTPUT);
+
+        /* Set GPIO's for  W-LAN + Bluetooth combo module */
+        if ((gpio_request(IGEP3_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_WIFI_NPD, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_WIFI_NPD, 0);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NPD\n");
+
+        if ((gpio_request(IGEP3_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_WIFI_NRESET, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_WIFI_NRESET, 0);
+                gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 0);
+                udelay(10);
+                gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NRESET\n");
+
+        if ((gpio_request(IGEP3_GPIO_BT_NRESET, "GPIO_BT_NRESET") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_BT_NRESET, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_BT_NRESET, 0);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_BT_NRESET\n");
+}
+#else
+void __init igep3_wifi_bt_init(void) {}
+#endif
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init igep3_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        /* Register I2C busses and drivers */
+        igep3_i2c_init();
+
+        omap_serial_init();
+        usb_musb_init(&musb_board_data);
+
+        igep3_flash_init();
+        igep3_leds_init();
+
+        /*
+         * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+         * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
+         */
+        igep3_wifi_bt_init();
+
+}
+
+MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_irq       = igep3_init_irq,
+        .init_machine   = igep3_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 00d9b13b01c..001fd9713f3 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -27,6 +27,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -41,11 +42,12 @@
 #include <mach/board-zoom.h>
 
 #include <asm/delay.h>
-#include <plat/control.h>
 #include <plat/usb.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "control.h"
 
 #define LDP_SMSC911X_CS         1
 #define LDP_SMSC911X_GPIO       152
@@ -82,7 +84,7 @@ static struct platform_device ldp_smsc911x_device = {
         },
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
         KEY(2, 0, KEY_3),
@@ -362,7 +364,7 @@ static int __init omap_i2c_init(void)
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
@@ -442,8 +444,6 @@ static void __init omap_ldp_init(void)
 }
 
 MACHINE_START(OMAP_LDP, "OMAP LDP board")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index a3e2b49aa39..e823c7042ab 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,6 +20,7 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <sound/tlv320aic3x.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -383,15 +384,6 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
         omap_mmc_notify_cover_event(mmc_device, index, *openp);
 }
 
-void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state)
-{
-        if (mmc_device == NULL)
-                return;
-
-        slot1_cover_open = !closed_state;
-        omap_mmc_notify_cover_event(mmc_device, 0, closed_state);
-}
-
 static int n8x0_mmc_late_init(struct device *dev)
 {
         int r, bit, *openp;
@@ -511,7 +503,7 @@ static struct omap_mmc_platform_data mmc1_data = {
 
 static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
 
-void __init n8x0_mmc_init(void)
+static void __init n8x0_mmc_init(void)
 
 {
         int err;
@@ -560,11 +552,6 @@ void __init n8x0_mmc_init(void)
 void __init n8x0_mmc_init(void)
 {
 }
-
-void n8x0_mmc_slot1_cover_handler(void *arg, int state)
-{
-}
-
 #endif  /* CONFIG_MMC_OMAP */
 
 #ifdef CONFIG_MENELAUS
@@ -614,29 +601,35 @@ static int n8x0_menelaus_late_init(struct device *dev)
         return 0;
 }
 
-static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = {
+#else
+static int n8x0_menelaus_late_init(struct device *dev)
+{
+        return 0;
+}
+#endif
+
+static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
+        .late_init = n8x0_menelaus_late_init,
+};
+
+static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
         {
                 I2C_BOARD_INFO("menelaus", 0x72),
                 .irq = INT_24XX_SYS_NIRQ,
+                .platform_data = &n8x0_menelaus_platform_data,
         },
 };
 
-static struct menelaus_platform_data n8x0_menelaus_platform_data = {
-        .late_init = n8x0_menelaus_late_init,
+static struct aic3x_pdata n810_aic33_data __initdata = {
+        .gpio_reset = 118,
 };
 
-static void __init n8x0_menelaus_init(void)
-{
-        n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data;
-        omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
-                              ARRAY_SIZE(n8x0_i2c_board_info_1));
-}
-
-#else
-static inline void __init n8x0_menelaus_init(void)
-{
-}
-#endif
+static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
+        {
+                I2C_BOARD_INFO("tlv320aic3x", 0x18),
+                .platform_data = &n810_aic33_data,
+        },
+};
 
 static void __init n8x0_map_io(void)
 {
@@ -653,6 +646,11 @@ static void __init n8x0_init_irq(void)
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* I2S codec port pins for McBSP block */
+        OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
@@ -665,17 +663,20 @@ static void __init n8x0_init_machine(void)
         /* FIXME: add n810 spi devices */
         spi_register_board_info(n800_spi_board_info,
                                 ARRAY_SIZE(n800_spi_board_info));
+        omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
+                              ARRAY_SIZE(n8x0_i2c_board_info_1));
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        if (machine_is_nokia_n810())
+                i2c_register_board_info(2, n810_i2c_board_info_2,
+                                        ARRAY_SIZE(n810_i2c_board_info_2));
 
         omap_serial_init();
-        n8x0_menelaus_init();
         n8x0_onenand_init();
         n8x0_mmc_init();
         n8x0_usb_init();
 }
 
 MACHINE_START(NOKIA_N800, "Nokia N800")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
@@ -685,8 +686,6 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
 MACHINE_END
 
 MACHINE_START(NOKIA_N810, "Nokia N810")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
@@ -696,8 +695,6 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
 MACHINE_END
 
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = n8x0_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 87969c7df65..14f42240ae7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -43,13 +44,100 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
+/*
+ * OMAP3 Beagle revision
+ * Run time detection of Beagle revision is done by reading GPIO.
+ * GPIO ID -
+ *      AXBX    = GPIO173, GPIO172, GPIO171: 1 1 1
+ *      C1_3    = GPIO173, GPIO172, GPIO171: 1 1 0
+ *      C4      = GPIO173, GPIO172, GPIO171: 1 0 1
+ *      XM      = GPIO173, GPIO172, GPIO171: 0 0 0
+ */
+enum {
+        OMAP3BEAGLE_BOARD_UNKN = 0,
+        OMAP3BEAGLE_BOARD_AXBX,
+        OMAP3BEAGLE_BOARD_C1_3,
+        OMAP3BEAGLE_BOARD_C4,
+        OMAP3BEAGLE_BOARD_XM,
+};
+
+static u8 omap3_beagle_version;
+
+static u8 omap3_beagle_get_rev(void)
+{
+        return omap3_beagle_version;
+}
+
+static void __init omap3_beagle_init_rev(void)
+{
+        int ret;
+        u16 beagle_rev = 0;
+
+        omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP);
+
+        ret = gpio_request(171, "rev_id_0");
+        if (ret < 0)
+                goto fail0;
+
+        ret = gpio_request(172, "rev_id_1");
+        if (ret < 0)
+                goto fail1;
+
+        ret = gpio_request(173, "rev_id_2");
+        if (ret < 0)
+                goto fail2;
+
+        gpio_direction_input(171);
+        gpio_direction_input(172);
+        gpio_direction_input(173);
+
+        beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1)
+                        | (gpio_get_value(173) << 2);
+
+        switch (beagle_rev) {
+        case 7:
+                printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
+                break;
+        case 6:
+                printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
+                break;
+        case 5:
+                printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
+                break;
+        case 0:
+                printk(KERN_INFO "OMAP3 Beagle Rev: xM\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
+                break;
+        default:
+                printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
+        }
+
+        return;
+
+fail2:
+        gpio_free(172);
+fail1:
+        gpio_free(171);
+fail0:
+        printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
+        omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
+
+        return;
+}
+
 static struct mtd_partition omap3beagle_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
         {
@@ -166,7 +254,7 @@ static void __init beagle_display_init(void)
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -185,7 +273,10 @@ static struct gpio_led gpio_leds[];
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
+        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+                mmc[0].gpio_wp = -EINVAL;
+        } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) ||
+                (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) {
                 omap_mux_init_gpio(23, OMAP_PIN_INPUT);
                 mmc[0].gpio_wp = 23;
         } else {
@@ -322,13 +413,19 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = {
         },
 };
 
+static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+       {
+               I2C_BOARD_INFO("eeprom", 0x50),
+       },
+};
+
 static int __init omap3_beagle_i2c_init(void)
 {
         omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo,
                         ARRAY_SIZE(beagle_i2c_boardinfo));
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
-        omap_register_i2c_bus(3, 100, NULL, 0);
+        omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
         return 0;
 }
 
@@ -464,6 +561,7 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init omap3_beagle_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap3_beagle_init_rev();
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
@@ -487,8 +585,6 @@ static void __init omap3_beagle_init(void)
 
 MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
         /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d9c0a47a..b04365c6bb1 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -31,6 +31,7 @@
 #include <linux/smsc911x.h>
 
 #include <linux/regulator/machine.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -370,7 +371,7 @@ static struct regulator_init_data omap3evm_vsim = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 63,
         },
@@ -446,7 +447,7 @@ static struct twl4030_usb_data omap3evm_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
         KEY(0, 2, KEY_ENTER),
@@ -584,7 +585,7 @@ static int ads7846_get_pendown_state(void)
         return !gpio_get_value(OMAP3_EVM_TS_GPIO);
 }
 
-struct ads7846_platform_data ads7846_config = {
+static struct ads7846_platform_data ads7846_config = {
         .x_max                  = 0x0fff,
         .y_max                  = 0x0fff,
         .x_plate_ohms           = 180,
@@ -603,7 +604,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .single_channel = 1,    /* 0: slave, 1: master */
 };
 
-struct spi_board_info omap3evm_spi_board_info[] = {
+static struct spi_board_info omap3evm_spi_board_info[] = {
         [0] = {
                 .modalias               = "ads7846",
                 .bus_num                = 1,
@@ -714,8 +715,6 @@ static void __init omap3_evm_init(void)
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
         /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
new file mode 100644
index 00000000000..5f7d2c1e7ef
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -0,0 +1,241 @@
+/*
+ * linux/arch/arm/mach-omap2/board-omap3logic.c
+ *
+ * Copyright (C) 2010 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Copyright (C) 2010 Logic Product Development, Inc.
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Modified from Beagle, EVM, and RX51
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <linux/regulator/machine.h>
+
+#include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "timer-gp.h"
+#include "control.h"
+
+#include <plat/mux.h>
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc-smsc911x.h>
+#include <plat/gpmc.h>
+#include <plat/sdrc.h>
+
+#define OMAP3LOGIC_SMSC911X_CS                  1
+
+#define OMAP3530_LV_SOM_MMC_GPIO_CD             110
+#define OMAP3530_LV_SOM_MMC_GPIO_WP             126
+#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ       152
+
+#define OMAP3_TORPEDO_MMC_GPIO_CD               127
+#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ         129
+
+static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data omap3logic_vmmc1 = {
+        .constraints = {
+                .name                   = "VMMC1",
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &omap3logic_vmmc1_supply,
+};
+
+static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .pullups        = BIT(1),
+        .pulldowns      = BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
+                        | BIT(13) | BIT(15) | BIT(16) | BIT(17),
+};
+
+static struct twl4030_platform_data omap3logic_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .gpio           = &omap3logic_gpio_data,
+        .vmmc1          = &omap3logic_vmmc1,
+};
+
+static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags = I2C_CLIENT_WAKE,
+                .irq = INT_34XX_SYS_NIRQ,
+                .platform_data = &omap3logic_twldata,
+        },
+};
+
+static int __init omap3logic_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo,
+                                ARRAY_SIZE(omap3logic_i2c_boardinfo));
+        return 0;
+}
+
+static struct omap2_hsmmc_info __initdata board_mmc_info[] = {
+        {
+                .name           = "external",
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        {}      /* Terminator */
+};
+
+static void __init board_mmc_init(void)
+{
+        if (machine_is_omap3530_lv_som()) {
+                /* OMAP3530 LV SOM board */
+                board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD;
+                board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP;
+                omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT);
+        } else if (machine_is_omap3_torpedo()) {
+                /* OMAP3 Torpedo board */
+                board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD;
+                omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT);
+        } else {
+                /* unsupported board */
+                printk(KERN_ERR "%s(): unknown machine type\n", __func__);
+                return;
+        }
+
+        omap2_hsmmc_init(board_mmc_info);
+        /* link regulators to MMC adapters */
+        omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
+}
+
+static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
+        .cs             = OMAP3LOGIC_SMSC911X_CS,
+        .gpio_irq       = -EINVAL,
+        .gpio_reset     = -EINVAL,
+        .flags          = IORESOURCE_IRQ_LOWLEVEL,
+};
+
+/* TODO/FIXME (comment by Peter Barada, LogicPD):
+ * Fix the PBIAS voltage for Torpedo MMC1 pins that
+ * are used for other needs (IRQs, etc).            */
+static void omap3torpedo_fix_pbias_voltage(void)
+{
+        u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+        u32 reg;
+
+        if (machine_is_omap3_torpedo())
+        {
+                /* Set the bias for the pin */
+                reg = omap_ctrl_readl(control_pbias_offset);
+
+                reg &= ~OMAP343X_PBIASLITEPWRDNZ1;
+                omap_ctrl_writel(reg, control_pbias_offset);
+
+                /* 100ms delay required for PBIAS configuration */
+                msleep(100);
+
+                reg |= OMAP343X_PBIASLITEVMODE1;
+                reg |= OMAP343X_PBIASLITEPWRDNZ1;
+                omap_ctrl_writel(reg | 0x300, control_pbias_offset);
+        }
+}
+
+static inline void __init board_smsc911x_init(void)
+{
+        if (machine_is_omap3530_lv_som()) {
+                /* OMAP3530 LV SOM board */
+                board_smsc911x_data.gpio_irq =
+                                        OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ;
+                omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT);
+        } else if (machine_is_omap3_torpedo()) {
+                /* OMAP3 Torpedo board */
+                board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ;
+                omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT);
+        } else {
+                /* unsupported board */
+                printk(KERN_ERR "%s(): unknown machine type\n", __func__);
+                return;
+        }
+
+        gpmc_smsc911x_init(&board_smsc911x_data);
+}
+
+static void __init omap3logic_init_irq(void)
+{
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init omap3logic_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap3torpedo_fix_pbias_voltage();
+        omap3logic_i2c_init();
+        omap_serial_init();
+        board_mmc_init();
+        board_smsc911x_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+}
+
+MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_irq       = omap3logic_init_irq,
+        .init_machine   = omap3logic_init,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_irq       = omap3logic_init_irq,
+        .init_machine   = omap3logic_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index dd3af2be13b..89ed1be2d62 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -25,14 +25,16 @@
 #include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
-#include <linux/spi/wl12xx.h>
+#include <linux/wl12xx.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/leds.h>
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/gpio_keys.h>
+#include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
+#include <linux/regulator/fixed.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -276,14 +278,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card)
 static struct omap2_hsmmc_info omap3pandora_mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 126,
                 .ext_clock      = 0,
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 127,
                 .ext_clock      = 1,
@@ -291,7 +293,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
         },
         {
                 .mmc            = 3,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .init_card      = pandora_wl1251_init_card,
@@ -344,6 +346,9 @@ static struct regulator_consumer_supply pandora_vmmc1_supply =
 static struct regulator_consumer_supply pandora_vmmc2_supply =
         REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
 
+static struct regulator_consumer_supply pandora_vmmc3_supply =
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2");
+
 static struct regulator_consumer_supply pandora_vdda_dac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
@@ -488,6 +493,33 @@ static struct regulator_init_data pandora_vsim = {
         .consumer_supplies      = &pandora_adac_supply,
 };
 
+/* Fixed regulator internal to Wifi module */
+static struct regulator_init_data pandora_vmmc3 = {
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &pandora_vmmc3_supply,
+};
+
+static struct fixed_voltage_config pandora_vwlan = {
+        .supply_name            = "vwlan",
+        .microvolts             = 1800000, /* 1.8V */
+        .gpio                   = PANDORA_WIFI_NRESET_GPIO,
+        .startup_delay          = 50000, /* 50ms */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &pandora_vmmc3,
+};
+
+static struct platform_device pandora_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &pandora_vwlan,
+        },
+};
+
 static struct twl4030_usb_data omap3pandora_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
@@ -501,6 +533,8 @@ static struct twl4030_codec_data omap3pandora_codec_data = {
         .audio = &omap3pandora_audio_data,
 };
 
+static struct twl4030_bci_platform_data pandora_bci_data;
+
 static struct twl4030_platform_data omap3pandora_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -516,6 +550,7 @@ static struct twl4030_platform_data omap3pandora_twldata = {
         .vaux4          = &pandora_vaux4,
         .vsim           = &pandora_vsim,
         .keypad         = &pandora_kp_data,
+        .bci            = &pandora_bci_data,
 };
 
 static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
@@ -644,19 +679,8 @@ static void pandora_wl1251_init(void)
         if (pandora_wl1251_pdata.irq < 0)
                 goto fail_irq;
 
-        ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset");
-        if (ret < 0)
-                goto fail_irq;
-
-        /* start powered so that it probes with MMC subsystem */
-        ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1);
-        if (ret < 0)
-                goto fail_nreset;
-
         return;
 
-fail_nreset:
-        gpio_free(PANDORA_WIFI_NRESET_GPIO);
 fail_irq:
         gpio_free(PANDORA_WIFI_IRQ_GPIO);
 fail:
@@ -668,6 +692,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_keys_gpio,
         &pandora_dss_device,
         &pandora_wl1251_data,
+        &pandora_vwlan_device,
 };
 
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -717,8 +742,6 @@ static void __init omap3pandora_init(void)
 }
 
 MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index bcd01d278c6..f2527212541 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -26,6 +26,7 @@
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -38,7 +39,6 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 #include <plat/display.h>
 
 #include <plat/mcspi.h>
@@ -52,6 +52,7 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #define OMAP3STALKER_ETHR_START 0x2c000000
@@ -275,7 +276,7 @@ static struct regulator_init_data omap3stalker_vsim = {
 static struct omap2_hsmmc_info mmc[] = {
         {
          .mmc           = 1,
-         .wires         = 4,
+         .caps          = MMC_CAP_4_BIT_DATA,
          .gpio_cd       = -EINVAL,
          .gpio_wp       = 23,
          },
@@ -389,7 +390,7 @@ static struct twl4030_usb_data omap3stalker_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
         KEY(0, 2, KEY_ENTER),
@@ -564,7 +565,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .single_channel         = 1,    /* 0: slave, 1: master */
 };
 
-struct spi_board_info omap3stalker_spi_board_info[] = {
+static struct spi_board_info omap3stalker_spi_board_info[] = {
         [0] = {
                .modalias        = "ads7846",
                .bus_num         = 1,
@@ -654,8 +655,6 @@ static void __init omap3_stalker_init(void)
 
 MACHINE_START(SBC3530, "OMAP3 STALKER")
         /* Maintainer: Jason Lam -lzg@ema-tech.com */
-        .phys_io                = 0x48000000,
-        .io_pg_offst            = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params            = 0x80000100,
         .map_io                 = omap3_map_io,
         .init_irq               = omap3_stalker_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 663c62d271e..41104bb8774 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <plat/mcspi.h>
 #include <linux/spi/spi.h>
@@ -47,10 +48,10 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #include <asm/setup.h>
 
@@ -61,7 +62,7 @@
 #define TB_BL_PWM_TIMER         9
 #define TB_KILL_POWER_GPIO      168
 
-unsigned long touchbook_revision;
+static unsigned long touchbook_revision;
 
 static struct mtd_partition omap3touchbook_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
@@ -108,7 +109,7 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -538,8 +539,6 @@ static void __init omap3_touchbook_init(void)
 
 MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
         /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index c03d1d56db5..702f2a63f2c 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/leds.h>
 #include <linux/gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
@@ -33,12 +34,45 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
-#include <plat/timer-gp.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+#include "timer-gp.h"
+
 #include "hsmmc.h"
+#include "control.h"
+
+#define GPIO_HUB_POWER          1
+#define GPIO_HUB_NRESET         62
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "pandaboard::status1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 7,
+        },
+        {
+                .name                   = "pandaboard::status2",
+                .default_trigger        = "mmc0",
+                .gpio                   = 8,
+        },
+};
 
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+
+static struct platform_device *panda_devices[] __initdata = {
+        &leds_gpio,
+};
 
 static void __init omap4_panda_init_irq(void)
 {
@@ -47,6 +81,56 @@ static void __init omap4_panda_init_irq(void)
         omap_gpio_init();
 }
 
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .phy_reset  = false,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[2]  = -EINVAL
+};
+
+static void __init omap4_ehci_init(void)
+{
+        int ret;
+
+
+        /* disable the power to the usb hub prior to init */
+        ret = gpio_request(GPIO_HUB_POWER, "hub_power");
+        if (ret) {
+                pr_err("Cannot request GPIO %d\n", GPIO_HUB_POWER);
+                goto error1;
+        }
+        gpio_export(GPIO_HUB_POWER, 0);
+        gpio_direction_output(GPIO_HUB_POWER, 0);
+        gpio_set_value(GPIO_HUB_POWER, 0);
+
+        /* reset phy+hub */
+        ret = gpio_request(GPIO_HUB_NRESET, "hub_nreset");
+        if (ret) {
+                pr_err("Cannot request GPIO %d\n", GPIO_HUB_NRESET);
+                goto error2;
+        }
+        gpio_export(GPIO_HUB_NRESET, 0);
+        gpio_direction_output(GPIO_HUB_NRESET, 0);
+        gpio_set_value(GPIO_HUB_NRESET, 0);
+        gpio_set_value(GPIO_HUB_NRESET, 1);
+
+        usb_ehci_init(&ehci_pdata);
+
+        /* enable power to hub */
+        gpio_set_value(GPIO_HUB_POWER, 1);
+        return;
+
+error2:
+        gpio_free(GPIO_HUB_POWER);
+error1:
+        pr_err("Unable to initialize EHCI power/reset\n");
+        return;
+
+}
+
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
         .mode                   = MUSB_PERIPHERAL,
@@ -56,7 +140,7 @@ static struct omap_musb_board_data musb_board_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
         },
         {}      /* Terminator */
@@ -67,10 +151,6 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
                 .supply = "vmmc",
                 .dev_name = "mmci-omap-hs.0",
         },
-        {
-                .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.1",
-        },
 };
 
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
@@ -89,7 +169,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
 {
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
+        struct omap_mmc_platform_data *pdata;
+
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
+                return;
+        }
+        pdata = dev->platform_data;
 
         pdata->init =   omap4_twl6030_hsmmc_late_init;
 }
@@ -156,7 +243,7 @@ static struct regulator_init_data omap4_panda_vmmc = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 2,
+        .num_consumer_supplies  = 1,
         .consumer_supplies      = omap4_panda_vmmc_supply,
 };
 
@@ -274,13 +361,13 @@ static int __init omap4_panda_i2c_init(void)
 }
 static void __init omap4_panda_init(void)
 {
-        int status;
-
         omap4_panda_i2c_init();
+        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
         /* OMAP4 Panda uses internal transceiver so register nop transceiver */
         usb_nop_xceiv_register();
+        omap4_ehci_init();
         /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
         if (!cpu_is_omap44xx())
                 usb_musb_init(&musb_board_data);
@@ -294,8 +381,6 @@ static void __init omap4_panda_map_io(void)
 
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         /* Maintainer: David Anders - Texas Instruments Inc */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap4_panda_map_io,
         .init_irq       = omap4_panda_init_irq,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4c484361835..7053bc0b46d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -32,6 +32,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -303,13 +304,13 @@ static void __init overo_flash_init(void)
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .transceiver    = true,
@@ -501,8 +502,6 @@ static void __init overo_init(void)
 }
 
 MACHINE_START(OVERO, "Gumstix Overo")
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 9a5eb87425f..41285297eaf 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -14,7 +14,7 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/wl12xx.h>
+#include <linux/wl12xx.h>
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/clk.h>
@@ -23,6 +23,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
+#include <sound/tlv320aic3x.h>
 
 #include <plat/mcspi.h>
 #include <plat/board.h>
@@ -32,6 +33,8 @@
 #include <plat/onenand.h>
 #include <plat/gpmc-smc91x.h>
 
+#include <mach/board-rx51.h>
+
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
 
@@ -184,7 +187,7 @@ static void __init rx51_add_gpio_keys(void)
 }
 #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         /*
          * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
          * connected to the ground" matrix state.
@@ -302,7 +305,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "external",
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .cover_only     = true,
                 .gpio_cd        = 160,
                 .gpio_wp        = -EINVAL,
@@ -311,7 +314,8 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "internal",
                 .mmc            = 2,
-                .wires          = 8, /* See also rx51_mmc2_remux */
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+                                                /* See also rx51_mmc2_remux */
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
@@ -689,7 +693,6 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
 };
 
 
-
 static struct twl4030_platform_data rx51_twldata __initdata = {
         .irq_base               = TWL4030_IRQ_BASE,
         .irq_end                = TWL4030_IRQ_END,
@@ -710,10 +713,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
         .vio                    = &rx51_vio,
 };
 
-static struct aic3x_pdata rx51_aic3x_data __initdata = {
-        .gpio_reset             = 60,
-};
-
 static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = {
         .id                     = TPA6130A2,
         .power_gpio             = 98,
@@ -728,6 +727,17 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
         },
 };
 
+/* Audio setup data */
+static struct aic3x_setup_data rx51_aic34_setup = {
+        .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
+        .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
+};
+
+static struct aic3x_pdata rx51_aic3x_data = {
+        .setup = &rx51_aic34_setup,
+        .gpio_reset = 60,
+};
+
 static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
         {
                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c
index f392844195d..a43b2c5c838 100644
--- a/arch/arm/mach-omap2/board-rx51-sdram.c
+++ b/arch/arm/mach-omap2/board-rx51-sdram.c
@@ -43,7 +43,7 @@ struct sdram_timings {
         u32 tWTR;
 };
 
-struct omap_sdrc_params rx51_sdrc_params[4];
+static struct omap_sdrc_params rx51_sdrc_params[4];
 
 static const struct sdram_timings rx51_timings[] = {
         {
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 5a1005ba981..85503fed4e1 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -20,6 +20,8 @@
 #include <plat/vram.h>
 #include <plat/mcspi.h>
 
+#include <mach/board-rx51.h>
+
 #include "mux.h"
 
 #define RX51_LCD_RESET_GPIO     90
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index a58e8cb1a7f..36f2cf4efd5 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -150,8 +150,6 @@ static void __init rx51_map_io(void)
 
 MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
-        .phys_io        = 0x48000000,
-        .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = rx51_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 1d7f827b040..007ebdc6c99 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -16,6 +16,8 @@
 
 #include <plat/gpmc.h>
 
+#include <mach/board-zoom.h>
+
 #define ZOOM_SMSC911X_CS        7
 #define ZOOM_SMSC911X_GPIO      158
 #define ZOOM_QUADUART_CS        3
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 6b3984964cc..86c9b210295 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -16,6 +16,9 @@
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/wl12xx.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -24,11 +27,16 @@
 #include <plat/common.h>
 #include <plat/usb.h>
 
+#include <mach/board-zoom.h>
+
 #include "mux.h"
 #include "hsmmc.h"
 
+#define OMAP_ZOOM_WLAN_PMENA_GPIO       (101)
+#define OMAP_ZOOM_WLAN_IRQ_GPIO         (162)
+
 /* Zoom2 has Qwerty keyboard*/
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_E),
         KEY(0, 1, KEY_R),
         KEY(0, 2, KEY_T),
@@ -106,6 +114,11 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
         .supply         = "vmmc",
 };
 
+static struct regulator_consumer_supply zoom_vmmc3_supply = {
+        .supply         = "vmmc",
+        .dev_name       = "mmci-omap-hs.2",
+};
+
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data zoom_vmmc1 = {
         .constraints = {
@@ -151,23 +164,63 @@ static struct regulator_init_data zoom_vsim = {
         .consumer_supplies      = &zoom_vsim_supply,
 };
 
+static struct regulator_init_data zoom_vmmc3 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies = &zoom_vmmc3_supply,
+};
+
+static struct fixed_voltage_config zoom_vwlan = {
+        .supply_name            = "vwl1271",
+        .microvolts             = 1800000, /* 1.8V */
+        .gpio                   = OMAP_ZOOM_WLAN_PMENA_GPIO,
+        .startup_delay          = 70000, /* 70msec */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &zoom_vmmc3,
+};
+
+static struct platform_device omap_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &zoom_vwlan,
+        },
+};
+
+struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
+        .irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO),
+        /* ZOOM ref clock is 26 MHz */
+        .board_ref_clock = 1,
+};
+
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "external",
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_wp        = -EINVAL,
                 .power_saving   = true,
         },
         {
                 .name           = "internal",
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
                 .power_saving   = true,
         },
+        {
+                .name           = "wl1271",
+                .mmc            = 3,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .nonremovable   = true,
+        },
         {}      /* Terminator */
 };
 
@@ -188,6 +241,11 @@ static int zoom_twl_gpio_setup(struct device *dev,
         return 0;
 }
 
+/* EXTMUTE callback function */
+void zoom2_set_hs_extmute(int mute)
+{
+        gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
+}
 
 static int zoom_batt_table[] = {
 /* 0 C*/
@@ -257,6 +315,11 @@ static struct i2c_board_info __initdata zoom_i2c_boardinfo[] = {
 
 static int __init omap_i2c_init(void)
 {
+        if (machine_is_omap_zoom2()) {
+                zoom_audio_data.ramp_delay_value = 3;   /* 161 ms */
+                zoom_audio_data.hs_extmute = 1;
+                zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
+        }
         omap_register_i2c_bus(1, 2400, zoom_i2c_boardinfo,
                         ARRAY_SIZE(zoom_i2c_boardinfo));
         omap_register_i2c_bus(2, 400, NULL, 0);
@@ -279,7 +342,12 @@ static void enable_board_wakeup_source(void)
 
 void __init zoom_peripherals_init(void)
 {
+        if (wl12xx_set_platform_data(&omap_zoom_wlan_data))
+                pr_err("error setting wl12xx data\n");
+
         omap_i2c_init();
+        platform_device_register(&omap_vwlan_device);
         usb_musb_init(&musb_board_data);
         enable_board_wakeup_source();
+        omap_serial_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 3ad9ecf7f5e..2992a9f3a58 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/i2c/twl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -23,6 +24,7 @@
 
 #include <mach/board-zoom.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 
@@ -34,41 +36,6 @@ static void __init omap_zoom2_init_irq(void)
         omap_gpio_init();
 }
 
-/* REVISIT: These audio entries can be removed once MFD code is merged */
-#if 0
-
-static struct twl4030_madc_platform_data zoom2_madc_data = {
-        .irq_line       = 1,
-};
-
-static struct twl4030_codec_audio_data zoom2_audio_data = {
-        .audio_mclk = 26000000,
-};
-
-static struct twl4030_codec_data zoom2_codec_data = {
-        .audio_mclk = 26000000,
-        .audio = &zoom2_audio_data,
-};
-
-static struct twl4030_platform_data zoom2_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
-        /* platform_data for children goes here */
-        .bci            = &zoom2_bci_data,
-        .madc           = &zoom2_madc_data,
-        .usb            = &zoom2_usb_data,
-        .gpio           = &zoom2_gpio_data,
-        .keypad         = &zoom2_kp_twl4030_data,
-        .codec          = &zoom2_codec_data,
-        .vmmc1          = &zoom2_vmmc1,
-        .vmmc2          = &zoom2_vmmc2,
-        .vsim           = &zoom2_vsim,
-
-};
-
-#endif
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         /* WLAN IRQ - GPIO 162 */
@@ -141,8 +108,6 @@ static void __init omap_zoom2_init(void)
 }
 
 MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
-        .phys_io        = ZOOM_UART_BASE,
-        .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index 6ca0b834161..5adde12c039 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -22,6 +22,7 @@
 #include <plat/board.h>
 #include <plat/usb.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
@@ -123,8 +124,6 @@ static void __init omap_zoom_init(void)
 }
 
 MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
-        .phys_io        = ZOOM_UART_BASE,
-        .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
         .reserve        = omap_reserve,
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 605f531783a..b5babf5440e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -395,7 +395,7 @@ void omap2_clk_disable_unused(struct clk *clk)
         if ((regval32 & (1 << clk->enable_bit)) == v)
                 return;
 
-        printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
+        pr_debug("Disabling unused clock \"%s\"\n", clk->name);
         if (cpu_is_omap34xx()) {
                 omap2_clk_enable(clk);
                 omap2_clk_disable(clk);
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 37d65d62ed8..21f856252ad 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -27,6 +27,7 @@
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
 
@@ -89,6 +90,12 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
         .clkdm_name     = "wkup_clkdm",
 };
 
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
 /*
  * Analog domain root source clocks
  */
@@ -1135,14 +1142,34 @@ static struct clk mcbsp1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp2_ick = {
@@ -1159,10 +1186,14 @@ static struct clk mcbsp2_fck = {
         .name           = "mcbsp2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcspi1_ick = {
@@ -1721,6 +1752,9 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
@@ -1728,6 +1762,8 @@ static struct omap_clk omap2420_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
@@ -1838,7 +1874,7 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
         CLK("musb_hdrc",        "fck",  &osc_ck,        CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index b33118fb6a8..e32afcbdfb8 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -27,6 +27,7 @@
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
 
@@ -89,6 +90,12 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
         .clkdm_name     = "wkup_clkdm",
 };
 
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
 /*
  * Analog domain root source clocks
  */
@@ -1123,14 +1130,34 @@ static struct clk mcbsp1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp2_ick = {
@@ -1147,10 +1174,14 @@ static struct clk mcbsp2_fck = {
         .name           = "mcbsp2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp3_ick = {
@@ -1167,10 +1198,14 @@ static struct clk mcbsp3_fck = {
         .name           = "mcbsp3_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp4_ick = {
@@ -1187,10 +1222,14 @@ static struct clk mcbsp4_fck = {
         .name           = "mcbsp4_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp5_ick = {
@@ -1207,10 +1246,14 @@ static struct clk mcbsp5_fck = {
         .name           = "mcbsp5_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcspi1_ick = {
@@ -1808,6 +1851,12 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
@@ -1815,6 +1864,11 @@ static struct omap_clk omap2430_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
@@ -1926,7 +1980,7 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X),
+        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
         CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index dfdce2d8277..d85ecd5aebf 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -20,7 +20,6 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/control.h>
 #include <plat/clkdev_omap.h>
 
 #include "clock.h"
@@ -33,6 +32,7 @@
 #include "cm-regbits-34xx.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
+#include "control.h"
 
 /*
  * clocks
@@ -2465,6 +2465,16 @@ static struct clk uart3_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk uart4_fck = {
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpt2_fck = {
         .name           = "gpt2_fck",
         .ops            = &clkops_omap2_dflt_wait,
@@ -2715,6 +2725,16 @@ static struct clk uart3_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk uart4_ick = {
+        .name           = "uart4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
         .ops            = &clkops_omap2_dflt_wait,
@@ -3188,6 +3208,11 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
@@ -3253,6 +3278,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2 | CK_AM35XX),
         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
@@ -3288,7 +3315,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2 | CK_AM35XX),
         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
-        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
+        CLK("omap-aes", "ick",  &aes2_ick,      CK_343X),
         CLK("omap-sham",        "ick",  &sha12_ick,     CK_343X),
         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
@@ -3346,9 +3373,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3372,6 +3403,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
+        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index e10db7a90cb..1599836ba3d 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -17,13 +17,15 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
  */
 
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/clk.h>
-
-#include <plat/control.h>
 #include <plat/clkdev_omap.h>
 
 #include "clock.h"
@@ -32,6 +34,7 @@
 #include "cm-regbits-44xx.h"
 #include "prm.h"
 #include "prm-regbits-44xx.h"
+#include "control.h"
 
 /* Root clocks */
 
@@ -175,21 +178,27 @@ static struct clk sys_clkin_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+static struct clk tie_low_clock_ck = {
+        .name           = "tie_low_clock_ck",
+        .rate           = 0,
+        .ops            = &clkops_null,
+};
+
 static struct clk utmi_phy_clkout_ck = {
         .name           = "utmi_phy_clkout_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
 static struct clk xclk60mhsp1_ck = {
         .name           = "xclk60mhsp1_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
 static struct clk xclk60mhsp2_ck = {
         .name           = "xclk60mhsp2_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
@@ -201,39 +210,23 @@ static struct clk xclk60motg_ck = {
 
 /* Module clocks and DPLL outputs */
 
-static const struct clksel_rate div2_1to2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel dpll_sys_ref_clk_div[] = {
-        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-static struct clk dpll_sys_ref_clk = {
-        .name           = "dpll_sys_ref_clk",
+static struct clk abe_dpll_bypass_clk_mux_ck = {
+        .name           = "abe_dpll_bypass_clk_mux_ck",
         .parent         = &sys_clkin_ck,
-        .clksel         = dpll_sys_ref_clk_div,
-        .clksel_reg     = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
         .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
-static const struct clksel abe_dpll_refclk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk abe_dpll_refclk_mux_ck = {
         .name           = "abe_dpll_refclk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
-        .clksel         = abe_dpll_refclk_mux_sel,
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
@@ -244,7 +237,7 @@ static struct clk abe_dpll_refclk_mux_ck = {
 /* DPLL_ABE */
 static struct dpll_data dpll_abe_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
-        .clk_bypass     = &sys_clkin_ck,
+        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
         .clk_ref        = &abe_dpll_refclk_mux_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -310,6 +303,12 @@ static struct clk abe_clk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
+static const struct clksel_rate div2_1to2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
 static const struct clksel aess_fclk_div[] = {
         { .parent = &abe_clk, .rates = div2_1to2_rates },
         { .parent = NULL },
@@ -380,14 +379,14 @@ static struct clk dpll_abe_m3_ck = {
 };
 
 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk core_hsd_byp_clk_mux_ck = {
         .name           = "core_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .clksel         = core_hsd_byp_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
@@ -400,7 +399,7 @@ static struct clk core_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_core_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
@@ -418,7 +417,7 @@ static struct dpll_data dpll_core_dd = {
 
 static struct clk dpll_core_ck = {
         .name           = "dpll_core_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_core_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_null,
@@ -596,14 +595,14 @@ static struct clk dpll_core_m7_ck = {
 };
 
 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk iva_hsd_byp_clk_mux_ck = {
         .name           = "iva_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .ops            = &clkops_null,
         .recalc         = &followparent_recalc,
 };
@@ -612,7 +611,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_iva_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
@@ -630,7 +629,7 @@ static struct dpll_data dpll_iva_dd = {
 
 static struct clk dpll_iva_ck = {
         .name           = "dpll_iva_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_iva_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -672,7 +671,7 @@ static struct clk dpll_iva_m5_ck = {
 static struct dpll_data dpll_mpu_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
         .clk_bypass     = &div_mpu_hs_clk,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
@@ -690,7 +689,7 @@ static struct dpll_data dpll_mpu_dd = {
 
 static struct clk dpll_mpu_ck = {
         .name           = "dpll_mpu_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_mpu_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -724,14 +723,14 @@ static struct clk per_hs_clk_div_ck = {
 };
 
 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk per_hsd_byp_clk_mux_ck = {
         .name           = "per_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .clksel         = per_hsd_byp_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
@@ -744,7 +743,7 @@ static struct clk per_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_per_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
@@ -762,7 +761,7 @@ static struct dpll_data dpll_per_dd = {
 
 static struct clk dpll_per_ck = {
         .name           = "dpll_per_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_per_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -858,8 +857,8 @@ static struct clk dpll_per_m7_ck = {
 /* DPLL_UNIPRO */
 static struct dpll_data dpll_unipro_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
-        .clk_bypass     = &dpll_sys_ref_clk,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
@@ -877,7 +876,7 @@ static struct dpll_data dpll_unipro_dd = {
 
 static struct clk dpll_unipro_ck = {
         .name           = "dpll_unipro_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_unipro_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -914,7 +913,8 @@ static struct clk usb_hs_clk_div_ck = {
 static struct dpll_data dpll_usb_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
         .clk_bypass     = &usb_hs_clk_div_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .flags          = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
@@ -927,13 +927,12 @@ static struct dpll_data dpll_usb_dd = {
         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
         .max_divider    = OMAP4430_MAX_DPLL_DIV,
         .min_divider    = 1,
-        .flags          = DPLL_J_TYPE | DPLL_NO_DCO_SEL
 };
 
 
 static struct clk dpll_usb_ck = {
         .name           = "dpll_usb_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_usb_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -1222,7 +1221,7 @@ static struct clk per_abe_24m_fclk = {
 static const struct clksel pmd_stm_clock_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
+        { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
         { .parent = NULL },
 };
 
@@ -1240,10 +1239,15 @@ static struct clk pmd_trace_clk_mux_ck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel syc_clk_div_div[] = {
+        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
 static struct clk syc_clk_div_ck = {
         .name           = "syc_clk_div_ck",
         .parent         = &sys_clkin_ck,
-        .clksel         = dpll_sys_ref_clk_div,
+        .clksel         = syc_clk_div_div,
         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
         .ops            = &clkops_null,
@@ -1284,13 +1288,13 @@ static struct clk aess_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk cust_efuse_fck = {
-        .name           = "cust_efuse_fck",
+static struct clk bandgap_fclk = {
+        .name           = "bandgap_fclk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_cefuse_clkdm",
-        .parent         = &sys_clkin_ck,
+        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -1344,6 +1348,56 @@ static struct clk dmic_fck = {
         .clkdm_name     = "abe_clkdm",
 };
 
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "tesla_clkdm",
+        .parent         = &dpll_iva_m4_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_sys_clk = {
+        .name           = "dss_sys_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &syc_clk_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_tv_clk = {
+        .name           = "dss_tv_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &extalt_clkin_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_dss_clk = {
+        .name           = "dss_dss_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &dpll_per_m5_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_48mhz_clk = {
+        .name           = "dss_48mhz_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_fck = {
         .name           = "dss_fck",
         .ops            = &clkops_omap2_dflt,
@@ -1354,18 +1408,18 @@ static struct clk dss_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ducati_ick = {
-        .name           = "ducati_ick",
+static struct clk efuse_ctrl_cust_fck = {
+        .name           = "efuse_ctrl_cust_fck",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "ducati_clkdm",
-        .parent         = &ducati_clk_mux_ck,
+        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .parent         = &sys_clkin_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk emif1_ick = {
-        .name           = "emif1_ick",
+static struct clk emif1_fck = {
+        .name           = "emif1_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1375,8 +1429,8 @@ static struct clk emif1_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk emif2_ick = {
-        .name           = "emif2_ick",
+static struct clk emif2_fck = {
+        .name           = "emif2_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1407,42 +1461,24 @@ static struct clk fdif_fck = {
         .clkdm_name     = "iss_clkdm",
 };
 
-static const struct clksel per_sgx_fclk_div[] = {
-        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-
-static struct clk per_sgx_fclk = {
-        .name           = "per_sgx_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .clksel         = per_sgx_fclk_div,
-        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PER_192M_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
-static const struct clksel sgx_clk_mux_sel[] = {
-        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
-        { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
+static struct clk fpka_fck = {
+        .name           = "fpka_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
 };
 
-/* Merged sgx_clk_mux into gfx */
-static struct clk gfx_fck = {
-        .name           = "gfx_fck",
-        .parent         = &dpll_core_m7_ck,
-        .clksel         = sgx_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
+static struct clk gpio1_dbclk = {
+        .name           = "gpio1_dbclk",
         .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_gfx_clkdm",
+        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio1_ick = {
@@ -1455,6 +1491,16 @@ static struct clk gpio1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio2_dbclk = {
+        .name           = "gpio2_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio2_ick = {
         .name           = "gpio2_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1465,6 +1511,16 @@ static struct clk gpio2_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio3_dbclk = {
+        .name           = "gpio3_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio3_ick = {
         .name           = "gpio3_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1475,6 +1531,16 @@ static struct clk gpio3_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio4_dbclk = {
+        .name           = "gpio4_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio4_ick = {
         .name           = "gpio4_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1485,6 +1551,16 @@ static struct clk gpio4_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio5_dbclk = {
+        .name           = "gpio5_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1495,6 +1571,16 @@ static struct clk gpio5_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio6_dbclk = {
+        .name           = "gpio6_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio6_ick = {
         .name           = "gpio6_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1515,214 +1601,25 @@ static struct clk gpmc_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static const struct clksel dmt1_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-/*
- * Merged dmt1_clk_mux into gptimer1
- * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
- */
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-};
-
-/*
- * Merged cm2_dm10_mux into gptimer10
- * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
- */
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm11_mux into gptimer11
- * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
- */
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm2_mux into gptimer2
- * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
- */
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm3_mux into gptimer3
- * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
- */
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm4_mux into gptimer4
- * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
- */
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-static const struct clksel timer5_sync_mux_sel[] = {
-        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+static const struct clksel sgx_clk_mux_sel[] = {
+        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-/*
- * Merged timer5_sync_mux into gptimer5
- * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
- */
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer6_sync_mux into gptimer6
- * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
- */
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer7_sync_mux into gptimer7
- * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
- */
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer8_sync_mux into gptimer8
- * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
- */
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged cm2_dm9_mux into gptimer9
- * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
- */
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
+/* Merged sgx_clk_mux into gpu */
+static struct clk gpu_fck = {
+        .name           = "gpu_fck",
+        .parent         = &dpll_core_m7_ck,
+        .clksel         = sgx_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
         .ops            = &clkops_omap2_dflt,
         .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
+        .clkdm_name     = "l3_gfx_clkdm",
 };
 
 static struct clk hdq1w_fck = {
@@ -1735,11 +1632,16 @@ static struct clk hdq1w_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel hsi_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
 /* Merged hsi_fclk into hsi */
-static struct clk hsi_ick = {
-        .name           = "hsi_ick",
+static struct clk hsi_fck = {
+        .name           = "hsi_fck",
         .parent         = &dpll_per_m2x2_ck,
-        .clksel         = per_sgx_fclk_div,
+        .clksel         = hsi_fclk_div,
         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
         .ops            = &clkops_omap2_dflt,
@@ -1791,6 +1693,26 @@ static struct clk i2c4_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk ipu_fck = {
+        .name           = "ipu_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ducati_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk iss_ctrlclk = {
+        .name           = "iss_ctrlclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
+        .clkdm_name     = "iss_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk iss_fck = {
         .name           = "iss_fck",
         .ops            = &clkops_omap2_dflt,
@@ -1801,8 +1723,8 @@ static struct clk iss_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ivahd_ick = {
-        .name           = "ivahd_ick",
+static struct clk iva_fck = {
+        .name           = "iva_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1811,8 +1733,8 @@ static struct clk ivahd_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk keyboard_fck = {
-        .name           = "keyboard_fck",
+static struct clk kbd_fck = {
+        .name           = "kbd_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -1821,8 +1743,8 @@ static struct clk keyboard_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk l3_instr_interconnect_ick = {
-        .name           = "l3_instr_interconnect_ick",
+static struct clk l3_instr_ick = {
+        .name           = "l3_instr_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1831,8 +1753,8 @@ static struct clk l3_instr_interconnect_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk l3_interconnect_3_ick = {
-        .name           = "l3_interconnect_3_ick",
+static struct clk l3_main_3_ick = {
+        .name           = "l3_main_3_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -2005,6 +1927,16 @@ static struct clk mcbsp4_fck = {
         .clkdm_name     = "l4_per_clkdm",
 };
 
+static struct clk mcpdm_fck = {
+        .name           = "mcpdm_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk mcspi1_fck = {
         .name           = "mcspi1_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2105,33 +2037,33 @@ static struct clk mmc5_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ocp_wp1_ick = {
-        .name           = "ocp_wp1_ick",
+static struct clk ocp2scp_usb_phy_phy_48m = {
+        .name           = "ocp2scp_usb_phy_phy_48m",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
-        .parent         = &l3_div_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk pdm_fck = {
-        .name           = "pdm_fck",
+static struct clk ocp2scp_usb_phy_ick = {
+        .name           = "ocp2scp_usb_phy_ick",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &pad_clks_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk pkaeip29_fck = {
-        .name           = "pkaeip29_fck",
+static struct clk ocp_wp_noc_ick = {
+        .name           = "ocp_wp_noc_ick",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l4_div_ck,
+        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -2145,8 +2077,8 @@ static struct clk rng_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sha2md51_fck = {
-        .name           = "sha2md51_fck",
+static struct clk sha2md5_fck = {
+        .name           = "sha2md5_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2155,8 +2087,8 @@ static struct clk sha2md51_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sl2_ick = {
-        .name           = "sl2_ick",
+static struct clk sl2if_ick = {
+        .name           = "sl2if_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -2165,6 +2097,46 @@ static struct clk sl2_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk slimbus1_fclk_1 = {
+        .name           = "slimbus1_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &func_24m_clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_fclk_0 = {
+        .name           = "slimbus1_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_fclk_2 = {
+        .name           = "slimbus1_fclk_2",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_slimbus_clk = {
+        .name           = "slimbus1_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &slimbus_clk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk slimbus1_fck = {
         .name           = "slimbus1_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2175,6 +2147,36 @@ static struct clk slimbus1_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk slimbus2_fclk_1 = {
+        .name           = "slimbus2_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &per_abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_fclk_0 = {
+        .name           = "slimbus2_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_24mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_slimbus_clk = {
+        .name           = "slimbus2_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &pad_slimbus_core_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk slimbus2_fck = {
         .name           = "slimbus2_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2185,8 +2187,8 @@ static struct clk slimbus2_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_core_fck = {
-        .name           = "sr_core_fck",
+static struct clk smartreflex_core_fck = {
+        .name           = "smartreflex_core_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2195,8 +2197,8 @@ static struct clk sr_core_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_iva_fck = {
-        .name           = "sr_iva_fck",
+static struct clk smartreflex_iva_fck = {
+        .name           = "smartreflex_iva_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2205,8 +2207,8 @@ static struct clk sr_iva_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_mpu_fck = {
-        .name           = "sr_mpu_fck",
+static struct clk smartreflex_mpu_fck = {
+        .name           = "smartreflex_mpu_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2215,14 +2217,175 @@ static struct clk sr_mpu_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk tesla_ick = {
-        .name           = "tesla_ick",
+/* Merged dmt1_clk_mux into timer1 */
+static struct clk timer1_fck = {
+        .name           = "timer1_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "tesla_clkdm",
-        .parent         = &dpll_iva_m4_ck,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/* Merged cm2_dm10_mux into timer10 */
+static struct clk timer10_fck = {
+        .name           = "timer10_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm11_mux into timer11 */
+static struct clk timer11_fck = {
+        .name           = "timer11_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm2_mux into timer2 */
+static struct clk timer2_fck = {
+        .name           = "timer2_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm3_mux into timer3 */
+static struct clk timer3_fck = {
+        .name           = "timer3_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm4_mux into timer4 */
+static struct clk timer4_fck = {
+        .name           = "timer4_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static const struct clksel timer5_sync_mux_sel[] = {
+        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged timer5_sync_mux into timer5 */
+static struct clk timer5_fck = {
+        .name           = "timer5_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer6_sync_mux into timer6 */
+static struct clk timer6_fck = {
+        .name           = "timer6_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer7_sync_mux into timer7 */
+static struct clk timer7_fck = {
+        .name           = "timer7_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer8_sync_mux into timer8 */
+static struct clk timer8_fck = {
+        .name           = "timer8_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged cm2_dm9_mux into timer9 */
+static struct clk timer9_fck = {
+        .name           = "timer9_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
 };
 
 static struct clk uart1_fck = {
@@ -2265,105 +2428,148 @@ static struct clk uart4_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk unipro1_fck = {
-        .name           = "unipro1_fck",
+static struct clk usb_host_fs_fck = {
+        .name           = "usb_host_fs_fck",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_96m_fclk,
+        .parent         = &func_48mc_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_host_fck = {
-        .name           = "usb_host_fck",
+static struct clk usb_host_hs_utmi_p3_clk = {
+        .name           = "usb_host_hs_utmi_p3_clk",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
         .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_host_fs_fck = {
-        .name           = "usb_host_fs_fck",
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+        .name           = "usb_host_hs_hsic60m_p1_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_48mc_fclk,
+        .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_otg_ick = {
-        .name           = "usb_otg_ick",
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+        .name           = "usb_host_hs_hsic60m_p2_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l3_div_ck,
+        .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_tll_ick = {
-        .name           = "usb_tll_ick",
+static const struct clksel utmi_p1_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p1_gfclk = {
+        .name           = "utmi_p1_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk usb_host_hs_utmi_p1_clk = {
+        .name           = "usb_host_hs_utmi_p1_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l4_div_ck,
+        .parent         = &utmi_p1_gfclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usbphyocp2scp_ick = {
-        .name           = "usbphyocp2scp_ick",
+static const struct clksel utmi_p2_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p2_gfclk = {
+        .name           = "utmi_p2_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk usb_host_hs_utmi_p2_clk = {
+        .name           = "usb_host_hs_utmi_p2_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l4_div_ck,
+        .parent         = &utmi_p2_gfclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usim_fck = {
-        .name           = "usim_fck",
+static struct clk usb_host_hs_hsic480m_p1_clk = {
+        .name           = "usb_host_hs_hsic480m_p1_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk wdt2_fck = {
-        .name           = "wdt2_fck",
+static struct clk usb_host_hs_hsic480m_p2_clk = {
+        .name           = "usb_host_hs_hsic480m_p2_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
+static struct clk usb_host_hs_func48mclk = {
+        .name           = "usb_host_hs_func48mclk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_fck = {
+        .name           = "usb_host_hs_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &sys_32k_ck,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-/* Remaining optional clocks */
 static const struct clksel otg_60m_gfclk_sel[] = {
         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-static struct clk otg_60m_gfclk_ck = {
-        .name           = "otg_60m_gfclk_ck",
+static struct clk otg_60m_gfclk = {
+        .name           = "otg_60m_gfclk",
         .parent         = &utmi_phy_clkout_ck,
         .clksel         = otg_60m_gfclk_sel,
         .init           = &omap2_init_clksel_parent,
@@ -2373,38 +2579,74 @@ static struct clk otg_60m_gfclk_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-static const struct clksel stm_clk_div_div[] = {
-        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
+static struct clk usb_otg_hs_xclk = {
+        .name           = "usb_otg_hs_xclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &otg_60m_gfclk,
+        .recalc         = &followparent_recalc,
 };
 
-static struct clk stm_clk_div_ck = {
-        .name           = "stm_clk_div_ck",
-        .parent         = &pmd_stm_clock_mux_ck,
-        .clksel         = stm_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
+static struct clk usb_otg_hs_ick = {
+        .name           = "usb_otg_hs_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
 };
 
-static const struct clksel trace_clk_div_div[] = {
-        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
+static struct clk usb_phy_cm_clk32k = {
+        .name           = "usb_phy_cm_clk32k",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
 };
 
-static struct clk trace_clk_div_ck = {
-        .name           = "trace_clk_div_ck",
-        .parent         = &pmd_trace_clk_mux_ck,
-        .clksel         = trace_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
+static struct clk usb_tll_hs_usb_ch2_clk = {
+        .name           = "usb_tll_hs_usb_ch2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_usb_ch0_clk = {
+        .name           = "usb_tll_hs_usb_ch0_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_usb_ch1_clk = {
+        .name           = "usb_tll_hs_usb_ch1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_ick = {
+        .name           = "usb_tll_hs_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
 };
 
 static const struct clksel_rate div2_14to18_rates[] = {
@@ -2418,8 +2660,8 @@ static const struct clksel usim_fclk_div[] = {
         { .parent = NULL },
 };
 
-static struct clk usim_fclk = {
-        .name           = "usim_fclk",
+static struct clk usim_ck = {
+        .name           = "usim_ck",
         .parent         = &dpll_per_m4_ck,
         .clksel         = usim_fclk_div,
         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
@@ -2430,38 +2672,79 @@ static struct clk usim_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel utmi_p1_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+static struct clk usim_fclk = {
+        .name           = "usim_fclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &usim_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wd_timer2_fck = {
+        .name           = "wd_timer2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wd_timer3_fck = {
+        .name           = "wd_timer3_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+/* Remaining optional clocks */
+static const struct clksel stm_clk_div_div[] = {
+        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
         { .parent = NULL },
 };
 
-static struct clk utmi_p1_gfclk_ck = {
-        .name           = "utmi_p1_gfclk_ck",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p1_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+static struct clk stm_clk_div_ck = {
+        .name           = "stm_clk_div_ck",
+        .parent         = &pmd_stm_clock_mux_ck,
+        .clksel         = stm_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
         .ops            = &clkops_null,
         .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel utmi_p2_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+static const struct clksel trace_clk_div_div[] = {
+        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
         { .parent = NULL },
 };
 
-static struct clk utmi_p2_gfclk_ck = {
-        .name           = "utmi_p2_gfclk_ck",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p2_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+static struct clk trace_clk_div_ck = {
+        .name           = "trace_clk_div_ck",
+        .parent         = &pmd_trace_clk_mux_ck,
+        .clksel         = trace_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
         .ops            = &clkops_null,
         .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
 /*
@@ -2483,11 +2766,12 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
+        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
-        CLK(NULL,       "dpll_sys_ref_clk",             &dpll_sys_ref_clk,      CK_443X),
+        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
@@ -2557,46 +2841,48 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
-        CLK(NULL,       "cust_efuse_fck",               &cust_efuse_fck,        CK_443X),
+        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
+        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
-        CLK(NULL,       "ducati_ick",                   &ducati_ick,    CK_443X),
-        CLK(NULL,       "emif1_ick",                    &emif1_ick,     CK_443X),
-        CLK(NULL,       "emif2_ick",                    &emif2_ick,     CK_443X),
+        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
+        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
+        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "per_sgx_fclk",                 &per_sgx_fclk,  CK_443X),
-        CLK(NULL,       "gfx_fck",                      &gfx_fck,       CK_443X),
+        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
+        CLK(NULL,       "gpio1_dbck",                   &gpio1_dbclk,   CK_443X),
         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
+        CLK(NULL,       "gpio2_dbck",                   &gpio2_dbclk,   CK_443X),
         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
+        CLK(NULL,       "gpio3_dbck",                   &gpio3_dbclk,   CK_443X),
         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
+        CLK(NULL,       "gpio4_dbck",                   &gpio4_dbclk,   CK_443X),
         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
+        CLK(NULL,       "gpio5_dbck",                   &gpio5_dbclk,   CK_443X),
         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
+        CLK(NULL,       "gpio6_dbck",                   &gpio6_dbclk,   CK_443X),
         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
-        CLK(NULL,       "gpt1_fck",                     &gpt1_fck,      CK_443X),
-        CLK(NULL,       "gpt10_fck",                    &gpt10_fck,     CK_443X),
-        CLK(NULL,       "gpt11_fck",                    &gpt11_fck,     CK_443X),
-        CLK(NULL,       "gpt2_fck",                     &gpt2_fck,      CK_443X),
-        CLK(NULL,       "gpt3_fck",                     &gpt3_fck,      CK_443X),
-        CLK(NULL,       "gpt4_fck",                     &gpt4_fck,      CK_443X),
-        CLK(NULL,       "gpt5_fck",                     &gpt5_fck,      CK_443X),
-        CLK(NULL,       "gpt6_fck",                     &gpt6_fck,      CK_443X),
-        CLK(NULL,       "gpt7_fck",                     &gpt7_fck,      CK_443X),
-        CLK(NULL,       "gpt8_fck",                     &gpt8_fck,      CK_443X),
-        CLK(NULL,       "gpt9_fck",                     &gpt9_fck,      CK_443X),
+        CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
-        CLK(NULL,       "hsi_ick",                      &hsi_ick,       CK_443X),
+        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
         CLK("i2c_omap.1",       "fck",                          &i2c1_fck,      CK_443X),
         CLK("i2c_omap.2",       "fck",                          &i2c2_fck,      CK_443X),
         CLK("i2c_omap.3",       "fck",                          &i2c3_fck,      CK_443X),
         CLK("i2c_omap.4",       "fck",                          &i2c4_fck,      CK_443X),
+        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
+        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
-        CLK(NULL,       "ivahd_ick",                    &ivahd_ick,     CK_443X),
-        CLK(NULL,       "keyboard_fck",                 &keyboard_fck,  CK_443X),
-        CLK(NULL,       "l3_instr_interconnect_ick",    &l3_instr_interconnect_ick,     CK_443X),
-        CLK(NULL,       "l3_interconnect_3_ick",        &l3_interconnect_3_ick, CK_443X),
+        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
+        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
+        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
+        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
@@ -2607,6 +2893,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
@@ -2616,43 +2903,66 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
         CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
         CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
-        CLK(NULL,       "ocp_wp1_ick",                  &ocp_wp1_ick,   CK_443X),
-        CLK(NULL,       "pdm_fck",                      &pdm_fck,       CK_443X),
-        CLK(NULL,       "pkaeip29_fck",                 &pkaeip29_fck,  CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
+        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
-        CLK(NULL,       "sha2md51_fck",                 &sha2md51_fck,  CK_443X),
-        CLK(NULL,       "sl2_ick",                      &sl2_ick,       CK_443X),
+        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
+        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
+        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
+        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
+        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
-        CLK(NULL,       "sr_core_fck",                  &sr_core_fck,   CK_443X),
-        CLK(NULL,       "sr_iva_fck",                   &sr_iva_fck,    CK_443X),
-        CLK(NULL,       "sr_mpu_fck",                   &sr_mpu_fck,    CK_443X),
-        CLK(NULL,       "tesla_ick",                    &tesla_ick,     CK_443X),
+        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
+        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
+        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
+        CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
+        CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
+        CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
+        CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
+        CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
+        CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
+        CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
+        CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
+        CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
+        CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
+        CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK(NULL,       "unipro1_fck",                  &unipro1_fck,   CK_443X),
-        CLK(NULL,       "usb_host_fck",                 &usb_host_fck,  CK_443X),
         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
-        CLK("musb_hdrc",        "ick",                          &usb_otg_ick,   CK_443X),
-        CLK(NULL,       "usb_tll_ick",                  &usb_tll_ick,   CK_443X),
-        CLK(NULL,       "usbphyocp2scp_ick",            &usbphyocp2scp_ick,     CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
+        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
+        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
+        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
+        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK("musb_hdrc",        "ick",                          &usb_otg_hs_ick,        CK_443X),
+        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
+        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK("omap_wdt", "fck",                          &wdt2_fck,      CK_443X),
-        CLK(NULL,       "wdt3_fck",                     &wdt3_fck,      CK_443X),
-        CLK(NULL,       "otg_60m_gfclk_ck",             &otg_60m_gfclk_ck,      CK_443X),
+        CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
+        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "utmi_p1_gfclk_ck",             &utmi_p1_gfclk_ck,      CK_443X),
-        CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
-        CLK(NULL,       "gpio1_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio2_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio3_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio4_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio5_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio6_dbck",                   &dummy_ck,      CK_443X),
         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
@@ -2669,19 +2979,19 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("i2c_omap.2",       "ick",                          &dummy_ck,      CK_443X),
         CLK("i2c_omap.3",       "ick",                          &dummy_ck,      CK_443X),
         CLK("i2c_omap.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.3",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.4",   "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.0",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.1",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.2",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.3",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.4",   "ick",          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 5d80cb89748..6fb61b1a0d4 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -258,97 +258,6 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
 
 }
 
-/**
- * _init_wkdep_usecount - initialize wkdep usecounts to match hardware
- * @clkdm: clockdomain to initialize wkdep usecounts
- *
- * Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
- * If a wakeup dependency is present in the hardware, the usecount will be
- * set to 1; otherwise, it will be set to 0.  Software should clear all
- * software wakeup dependencies prior to calling this function if it wishes
- * to ensure that all usecounts start at 0.  No return value.
- */
-static void _init_wkdep_usecount(struct clockdomain *clkdm)
-{
-        u32 v;
-        struct clkdm_dep *cd;
-
-        if (!clkdm->wkdep_srcs)
-                return;
-
-        for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
-                if (!cd->clkdm && cd->clkdm_name)
-                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
-
-                if (!cd->clkdm) {
-                        WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
-                             "found\n", clkdm->name, cd->clkdm_name);
-                        continue;
-                }
-
-                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
-                                            PM_WKDEP,
-                                            (1 << cd->clkdm->dep_bit));
-
-                if (v)
-                        pr_debug("clockdomain: %s: wakeup dependency already "
-                                 "set to wake up when %s wakes\n",
-                                 clkdm->name, cd->clkdm->name);
-
-                atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
-        }
-}
-
-/**
- * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
- * @clkdm: clockdomain to initialize sleepdep usecounts
- *
- * Initialize the sleep dependency usecount variables for clockdomain @clkdm.
- * If a sleep dependency is present in the hardware, the usecount will be
- * set to 1; otherwise, it will be set to 0.  Software should clear all
- * software sleep dependencies prior to calling this function if it wishes
- * to ensure that all usecounts start at 0.  No return value.
- */
-static void _init_sleepdep_usecount(struct clockdomain *clkdm)
-{
-        u32 v;
-        struct clkdm_dep *cd;
-
-        if (!cpu_is_omap34xx())
-                return;
-
-        if (!clkdm->sleepdep_srcs)
-                return;
-
-        for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
-                if (!cd->clkdm && cd->clkdm_name)
-                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
-
-                if (!cd->clkdm) {
-                        WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
-                             "not found\n", clkdm->name, cd->clkdm_name);
-                        continue;
-                }
-
-                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
-                                            OMAP3430_CM_SLEEPDEP,
-                                            (1 << cd->clkdm->dep_bit));
-
-                if (v)
-                        pr_debug("clockdomain: %s: sleep dependency already "
-                                 "set to prevent from idling until %s "
-                                 "idles\n", clkdm->name, cd->clkdm->name);
-
-                atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
-        }
-};
-
 /* Public functions */
 
 /**
@@ -379,12 +288,17 @@ void clkdm_init(struct clockdomain **clkdms,
                         _autodep_lookup(autodep);
 
         /*
-         * Ensure that the *dep_usecount registers reflect the current
-         * state of the PRCM.
+         * Put all clockdomains into software-supervised mode; PM code
+         * should later enable hardware-supervised mode as appropriate
          */
         list_for_each_entry(clkdm, &clkdm_list, node) {
-                _init_wkdep_usecount(clkdm);
-                _init_sleepdep_usecount(clkdm);
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap2_clkdm_wakeup(clkdm);
+                else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
+                        omap2_clkdm_deny_idle(clkdm);
+
+                clkdm_clear_all_wkdeps(clkdm);
+                clkdm_clear_all_sleepdeps(clkdm);
         }
 }
 
@@ -592,6 +506,9 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
                 if (!omap_chip_is(cd->omap_chip))
                         continue;
 
+                if (!cd->clkdm && cd->clkdm_name)
+                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
                 /* PRM accesses are slow, so minimize them */
                 mask |= 1 << cd->clkdm->dep_bit;
                 atomic_set(&cd->wkdep_usecount, 0);
@@ -752,6 +669,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
                 if (!omap_chip_is(cd->omap_chip))
                         continue;
 
+                if (!cd->clkdm && cd->clkdm_name)
+                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
                 /* PRM accesses are slow, so minimize them */
                 mask |= 1 << cd->clkdm->dep_bit;
                 atomic_set(&cd->sleepdep_usecount, 0);
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index fe82b79d5f3..4f959a7d881 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -649,6 +649,8 @@
 #define OMAP3430_ST_MCBSP2_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE_PER */
+#define OMAP3630_AUTO_UART4_MASK                        (1 << 18)
+#define OMAP3630_AUTO_UART4_SHIFT                       18
 #define OMAP3430_AUTO_GPIO6_MASK                        (1 << 17)
 #define OMAP3430_AUTO_GPIO6_SHIFT                       17
 #define OMAP3430_AUTO_GPIO5_MASK                        (1 << 16)
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index ac8458e4325..0b72be43377 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx Clock Management register bits
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -25,453 +25,459 @@
 #include "cm.h"
 
 
-/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+/*
+ * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
+ * CM_TESLA_DYNAMICDEP
+ */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
-#define OMAP4430_ABE_DYNDEP_MASK                                BITFIELD(3, 3)
+#define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
-#define OMAP4430_ABE_STATDEP_MASK                               BITFIELD(3, 3)
+#define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
-#define OMAP4430_ALWONCORE_DYNDEP_MASK                          BITFIELD(16, 16)
+#define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
-#define OMAP4430_ALWONCORE_STATDEP_MASK                         BITFIELD(16, 16)
+#define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
 
 /*
- * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB,
- * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
- * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
+ * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
+ * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
+ * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
-#define OMAP4430_AUTO_DPLL_MODE_MASK                            BITFIELD(0, 2)
+#define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
-#define OMAP4430_CEFUSE_DYNDEP_MASK                             BITFIELD(17, 17)
+#define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
-#define OMAP4430_CEFUSE_STATDEP_MASK                            BITFIELD(17, 17)
+#define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
-#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    BITFIELD(14, 14)
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 
 /* Used by CM_DUCATI_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   BITFIELD(8, 8)
-
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK                BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                BITFIELD(15, 15)
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            BITFIELD(20, 20)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 BITFIELD(26, 26)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            BITFIELD(21, 21)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 BITFIELD(27, 27)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT               31
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK                BITFIELD(31, 31)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             BITFIELD(28, 28)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             BITFIELD(29, 29)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                BITFIELD(16, 16)
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             BITFIELD(17, 17)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             BITFIELD(18, 18)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             BITFIELD(19, 19)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 
 /* Used by CM_IVAHD_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT        14
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK         BITFIELD(14, 14)
+/* Used by CM_D2D_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 
 /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_SDMA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_L3INSTR_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 
 /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                BITFIELD(16, 16)
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 BITFIELD(17, 17)
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 BITFIELD(18, 18)
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 BITFIELD(19, 19)
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             BITFIELD(25, 25)
-
-/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT             10
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK              BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              BITFIELD(20, 20)
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
-#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              BITFIELD(21, 21)
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              BITFIELD(22, 22)
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 BITFIELD(24, 24)
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
-#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 
 /* Used by CM_TESLA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 BITFIELD(22, 22)
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 BITFIELD(23, 23)
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 BITFIELD(24, 24)
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               BITFIELD(15, 15)
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 BITFIELD(30, 30)
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               BITFIELD(25, 25)
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 
 /*
- * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
+ * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL,
- * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL
+ * CM_WKUP_TIMER1_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SHIFT                                   24
-#define OMAP4430_CLKSEL_MASK                                    BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 
 /*
  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
- * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
- * CM_CLKSEL_USB_60MHZ
+ * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
  */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
-#define OMAP4430_CLKSEL_0_0_MASK                                BITFIELD(0, 0)
+#define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
-#define OMAP4430_CLKSEL_0_1_MASK                                BITFIELD(0, 1)
+#define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
-#define OMAP4430_CLKSEL_24_25_MASK                              BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
-#define OMAP4430_CLKSEL_60M_MASK                                BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
-#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
-#define OMAP4430_CLKSEL_CORE_MASK                               BITFIELD(0, 0)
+#define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 
-/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
+/*
+ * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+ * CM_SHADOW_FREQ_CONFIG2
+ */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
-#define OMAP4430_CLKSEL_CORE_1_1_MASK                           BITFIELD(1, 1)
+#define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
-#define OMAP4430_CLKSEL_DIV_MASK                                BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
-#define OMAP4430_CLKSEL_FCLK_MASK                               BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    BITFIELD(25, 25)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 
 /*
  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
@@ -479,836 +485,869 @@
  * CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       BITFIELD(26, 27)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
-#define OMAP4430_CLKSEL_L3_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 
-/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+/*
+ * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+ * CM_SHADOW_FREQ_CONFIG2
+ */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
-#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          BITFIELD(2, 2)
+#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
-#define OMAP4430_CLKSEL_L4_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
-#define OMAP4430_CLKSEL_OPP_MASK                                BITFIELD(0, 1)
-
-/* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_PER_192M_SHIFT                          25
-#define OMAP4430_CLKSEL_PER_192M_MASK                           BITFIELD(25, 26)
+#define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
-#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        BITFIELD(27, 29)
+#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
-#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      BITFIELD(24, 26)
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
-#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 
 /*
  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
-#define OMAP4430_CLKSEL_SOURCE_MASK                             BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
-#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
-#define OMAP4430_CLKSEL_UTMI_P1_MASK                            BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
-#define OMAP4430_CLKSEL_UTMI_P2_MASK                            BITFIELD(25, 25)
+#define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 
 /*
- * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL,
- * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
- * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL,
- * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE,
- * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE,
- * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL,
- * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
- * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
+ * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
+ * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
+ * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
+ * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
+ * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
+ * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
+ * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
+ * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
+ * CM_WKUP_CLKSTCTRL
  */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
-#define OMAP4430_CLKTRCTRL_MASK                                 BITFIELD(0, 1)
+#define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
-#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         BITFIELD(0, 6)
+#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
-#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        BITFIELD(8, 18)
+#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_CUSTOM_SHIFT                                   6
+#define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
-#define OMAP4430_D2D_DYNDEP_MASK                                BITFIELD(18, 18)
+#define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 
 /* Used by CM_MPU_STATICDEP */
 #define OMAP4430_D2D_STATDEP_SHIFT                              18
-#define OMAP4430_D2D_STATDEP_MASK                               BITFIELD(18, 18)
+#define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 
 /*
- * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
- * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,
- * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
- * CM_SSC_DELTAMSTEP_DPLL_MPU
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
+ * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
+ * CM_SSC_DELTAMSTEP_DPLL_USB
  */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
-#define OMAP4430_DELTAMSTEP_MASK                                BITFIELD(0, 19)
+#define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DLL_OVERRIDE_SHIFT                             2
-#define OMAP4430_DLL_OVERRIDE_MASK                              BITFIELD(2, 2)
+#define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 2)
 
 /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         0
-#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          BITFIELD(0, 0)
+#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          (1 << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DLL_RESET_SHIFT                                3
-#define OMAP4430_DLL_RESET_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+ * CM_CLKSEL_DPLL_USB
  */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
-#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           BITFIELD(23, 23)
+#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 
-/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
+/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     BITFIELD(20, 20)
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
-#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        BITFIELD(0, 4)
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   BITFIELD(5, 5)
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 
-/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
-#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   BITFIELD(10, 10)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
-#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           BITFIELD(0, 4)
+#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
-#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       BITFIELD(0, 6)
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      BITFIELD(5, 5)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               BITFIELD(7, 7)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
- * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
-#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
-#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         BITFIELD(8, 10)
+#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
-#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          BITFIELD(11, 15)
+#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
+/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
-#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          BITFIELD(3, 7)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT                 1
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK                  BITFIELD(1, 1)
+#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
-#define OMAP4430_DPLL_DIV_MASK                                  BITFIELD(0, 6)
+#define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
-#define OMAP4430_DPLL_DIV_0_7_MASK                              BITFIELD(0, 7)
+#define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
-#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        BITFIELD(8, 8)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    BITFIELD(3, 3)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
-#define OMAP4430_DPLL_EN_MASK                                   BITFIELD(0, 2)
+#define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
-#define OMAP4430_DPLL_LPMODE_EN_MASK                            BITFIELD(10, 10)
+#define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
-#define OMAP4430_DPLL_MULT_MASK                                 BITFIELD(8, 18)
+#define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
-#define OMAP4430_DPLL_MULT_USB_MASK                             BITFIELD(8, 19)
+#define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
-#define OMAP4430_DPLL_REGM4XEN_MASK                             BITFIELD(11, 11)
+#define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
-#define OMAP4430_DPLL_SD_DIV_MASK                               BITFIELD(24, 31)
+#define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
-#define OMAP4430_DPLL_SSC_ACK_MASK                              BITFIELD(13, 13)
+#define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       BITFIELD(14, 14)
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
-#define OMAP4430_DPLL_SSC_EN_MASK                               BITFIELD(12, 12)
+#define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
-#define OMAP4430_DSS_DYNDEP_MASK                                BITFIELD(8, 8)
+#define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE
  */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
-#define OMAP4430_DSS_STATDEP_MASK                               BITFIELD(8, 8)
+#define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
-#define OMAP4430_DUCATI_DYNDEP_MASK                             BITFIELD(0, 0)
+#define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 
-/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
+/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
-#define OMAP4430_DUCATI_STATDEP_MASK                            BITFIELD(0, 0)
+#define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
-#define OMAP4430_FREQ_UPDATE_MASK                               BITFIELD(0, 0)
+#define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_FUNC_SHIFT                                     16
+#define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
-#define OMAP4430_GFX_DYNDEP_MASK                                BITFIELD(10, 10)
+#define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
-#define OMAP4430_GFX_STATDEP_MASK                               BITFIELD(10, 10)
+#define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
+/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
-#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          BITFIELD(0, 0)
+#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    BITFIELD(12, 12)
-
-/*
- * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
- * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
- * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
- * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
- * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
- * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
- * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
- * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
+
+/*
+ * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
- * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
- * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
- * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
- * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
- * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
- * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_IDLEST_SHIFT                                   16
-#define OMAP4430_IDLEST_MASK                                    BITFIELD(16, 17)
+#define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 
-/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+/*
+ * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+ * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
-#define OMAP4430_ISS_DYNDEP_MASK                                BITFIELD(9, 9)
+#define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
-#define OMAP4430_ISS_STATDEP_MASK                               BITFIELD(9, 9)
+#define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
-#define OMAP4430_IVAHD_DYNDEP_MASK                              BITFIELD(2, 2)
+#define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
-#define OMAP4430_IVAHD_STATDEP_MASK                             BITFIELD(2, 2)
+#define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
-#define OMAP4430_L3INIT_DYNDEP_MASK                             BITFIELD(7, 7)
+#define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
-#define OMAP4430_L3INIT_STATDEP_MASK                            BITFIELD(7, 7)
+#define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 
 /*
- * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
- * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+ * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
-#define OMAP4430_L3_1_DYNDEP_MASK                               BITFIELD(5, 5)
+#define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
-#define OMAP4430_L3_1_STATDEP_MASK                              BITFIELD(5, 5)
+#define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 
 /*
- * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP,
- * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
- * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
+ * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
+ * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
+ * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
  */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
-#define OMAP4430_L3_2_DYNDEP_MASK                               BITFIELD(6, 6)
+#define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
-#define OMAP4430_L3_2_STATDEP_MASK                              BITFIELD(6, 6)
+#define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 
-/* Used by CM_L3_1_DYNAMICDEP */
+/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
-#define OMAP4430_L4CFG_DYNDEP_MASK                              BITFIELD(12, 12)
+#define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
-#define OMAP4430_L4CFG_STATDEP_MASK                             BITFIELD(12, 12)
+#define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
-#define OMAP4430_L4PER_DYNDEP_MASK                              BITFIELD(13, 13)
+#define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
-#define OMAP4430_L4PER_STATDEP_MASK                             BITFIELD(13, 13)
+#define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
-#define OMAP4430_L4SEC_DYNDEP_MASK                              BITFIELD(14, 14)
+#define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
  */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
-#define OMAP4430_L4SEC_STATDEP_MASK                             BITFIELD(14, 14)
+#define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
-#define OMAP4430_L4WKUP_DYNDEP_MASK                             BITFIELD(15, 15)
+#define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
-#define OMAP4430_L4WKUP_STATDEP_MASK                            BITFIELD(15, 15)
+#define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 
 /*
- * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_MPU_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
  */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
-#define OMAP4430_MEMIF_DYNDEP_MASK                              BITFIELD(4, 4)
+#define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
-#define OMAP4430_MEMIF_STATDEP_MASK                             BITFIELD(4, 4)
+#define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 
 /*
- * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
- * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
-#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       BITFIELD(8, 10)
+#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 
 /*
- * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
- * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
-#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       BITFIELD(0, 6)
-
-/*
- * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
- * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
- * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
- * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
- * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
- * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
- * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
- * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
+
+/*
+ * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
- * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
- * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
- * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
- * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
- * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
- * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_MODULEMODE_SHIFT                               0
-#define OMAP4430_MODULEMODE_MASK                                BITFIELD(0, 1)
+#define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
-#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
 
-/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         9
-#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          BITFIELD(9, 9)
+/* Used by CM_ALWON_USBPHY_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
 
 /* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 
 /*
- * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
  */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
 
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
-#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
+
+/* Used by CM_WKUP_USIM_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
-#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
-#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
-#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      BITFIELD(15, 15)
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
-#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 BITFIELD(13, 13)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
-#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 BITFIELD(14, 14)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
-#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
-#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  BITFIELD(12, 12)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
-#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
-#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
 
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
-#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
-#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
 
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
-#define OMAP4430_OPTFCLKEN_XCLK_MASK                            BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
 
-/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
+/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
-#define OMAP4430_OVERRIDE_ENABLE_MASK                           BITFIELD(19, 19)
+#define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
-#define OMAP4430_PAD_CLKS_GATE_MASK                             BITFIELD(8, 8)
+#define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
 
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
 #define OMAP4430_PERF_CURRENT_SHIFT                             0
-#define OMAP4430_PERF_CURRENT_MASK                              BITFIELD(0, 7)
+#define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
 
 /*
  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
@@ -1316,159 +1355,173 @@
  * CM_IVA_DVFS_PERF_TESLA
  */
 #define OMAP4430_PERF_REQ_SHIFT                                 0
-#define OMAP4430_PERF_REQ_MASK                                  BITFIELD(0, 7)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT                         0
-#define OMAP4430_PER_DPLL_EMU_DIV_MASK                          BITFIELD(0, 6)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT                        8
-#define OMAP4430_PER_DPLL_EMU_MULT_MASK                         BITFIELD(8, 18)
+#define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
-#define OMAP4430_PHASE1_COMPLETED_MASK                          BITFIELD(0, 0)
+#define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
-#define OMAP4430_PHASE2A_COMPLETED_MASK                         BITFIELD(1, 1)
+#define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
-#define OMAP4430_PHASE2B_COMPLETED_MASK                         BITFIELD(2, 2)
+#define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
-#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          BITFIELD(20, 21)
+#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
-#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        BITFIELD(22, 23)
+#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 
-/* Used by CM_DYN_DEP_PRESCAL */
+/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
 #define OMAP4430_PRESCAL_SHIFT                                  0
-#define OMAP4430_PRESCAL_MASK                                   BITFIELD(0, 5)
+#define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 
-/* Used by REVISION_CM2, REVISION_CM1 */
-#define OMAP4430_REV_SHIFT                                      0
-#define OMAP4430_REV_MASK                                       BITFIELD(0, 7)
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_R_RTL_SHIFT                                    11
+#define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 
 /*
- * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
+ * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
  */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
-#define OMAP4430_SAR_MODE_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 
 /* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
-#define OMAP4430_SCALE_FCLK_MASK                                BITFIELD(0, 0)
+#define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_SCHEME_SHIFT                                   30
+#define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
-#define OMAP4430_SDMA_DYNDEP_MASK                               BITFIELD(11, 11)
+#define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
-#define OMAP4430_SDMA_STATDEP_MASK                              BITFIELD(11, 11)
+#define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
-#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          BITFIELD(10, 10)
+#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
 
 /*
- * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
- * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
- * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
  */
 #define OMAP4430_STBYST_SHIFT                                   18
-#define OMAP4430_STBYST_MASK                                    BITFIELD(18, 18)
+#define OMAP4430_STBYST_MASK                                    (1 << 18)
 
 /*
- * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB,
- * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
- * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
-#define OMAP4430_ST_DPLL_CLK_MASK                               BITFIELD(0, 0)
+#define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
- * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
-#define OMAP4430_ST_DPLL_CLKOUT_MASK                            BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 
-/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
-#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          BITFIELD(11, 11)
+#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
+ */
+#define OMAP4430_ST_MN_BYPASS_SHIFT                             8
+#define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
 
 /* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
-#define OMAP4430_SYS_CLKSEL_MASK                                BITFIELD(0, 2)
+#define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
-#define OMAP4430_TESLA_DYNDEP_MASK                              BITFIELD(1, 1)
+#define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
-#define OMAP4430_TESLA_STATDEP_MASK                             BITFIELD(1, 1)
+#define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 
 /*
- * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
+ * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
+ * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
-#define OMAP4430_WINDOWSIZE_MASK                                BITFIELD(24, 27)
+#define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_X_MAJOR_SHIFT                                  8
+#define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_Y_MINOR_SHIFT                                  0
+#define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 336d94889e5..3c35a87cb90 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -195,6 +195,42 @@
 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
 
+/* CM1.RESTORE_CM1 register offsets */
+#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET             0x0000
+#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
+#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET        0x0004
+#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
+#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET        0x0008
+#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
+#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET        0x000c
+#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
+#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET        0x0010
+#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
+#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
+#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET        0x0018
+#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
+#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET        0x0020
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET        0x0024
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
+#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET       0x0028
+#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET     0x002c
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET     0x0030
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET      0x0034
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
+#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET           0x0038
+#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET   0x003c
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
+#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET         0x0040
+#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
+
 /* CM2 */
 
 /* CM2.OCP_SOCKET_CM2 register offsets */
@@ -252,8 +288,6 @@
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET         0x006c
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
-#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET           0x0070
-#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
 #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
 #define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
 #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
@@ -296,6 +330,8 @@
 #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
 #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
+#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET            0x0040
+#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
 
 /* CM2.CORE_CM2 register offsets */
 #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
@@ -578,4 +614,54 @@
 #define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
+
+/* CM2.RESTORE_CM2 register offsets */
+#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET          0x0000
+#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
+#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET          0x0004
+#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
+#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET         0x0008
+#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
+#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET         0x000c
+#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
+#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET         0x0010
+#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
+#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
+#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET    0x0018
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
+#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
+#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
+#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET   0x0024
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
+#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET           0x0028
+#define OMAP4430_CM_D2D_STATICDEP_RESTORE               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
+#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET         0x002c
+#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
+#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET         0x0030
+#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
+#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET          0x0034
+#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
+#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET        0x0038
+#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
+#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET        0x003c
+#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
+#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET     0x0040
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
+#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET     0x0044
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
+#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET     0x0048
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
+#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET     0x004c
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
+#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET     0x0050
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
+#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
+#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET  0x0058
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
+#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET          0x005c
+#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
 #endif
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
index b101091e95d..f8a660a1a4a 100644
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ b/arch/arm/mach-omap2/cm4xxx.c
@@ -43,7 +43,6 @@
  *                 using separate functional clock
  *   0x3 disabled: Module is disabled and cannot be accessed
  *
- * TODO: Need to handle module accessible in idle state
  */
 int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
 {
@@ -52,9 +51,11 @@ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
         if (!clkctrl_reg)
                 return 0;
 
-        omap_test_timeout(((__raw_readl(clkctrl_reg) &
-                            OMAP4430_IDLEST_MASK) == 0),
-                          MAX_MODULE_READY_TIME, i);
+        omap_test_timeout((
+                ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
+                 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
+                  OMAP4430_IDLEST_SHIFT) == 0x2)),
+                MAX_MODULE_READY_TIME, i);
 
         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
new file mode 100644
index 00000000000..778929f7e92
--- /dev/null
+++ b/arch/arm/mach-omap2/common.c
@@ -0,0 +1,135 @@
+/*
+ * linux/arch/arm/mach-omap2/common.c
+ *
+ * Code common to all OMAP2+ machines.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2010 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+#include <plat/board.h>
+#include <plat/mux.h>
+
+#include <plat/clock.h>
+
+#include "sdrc.h"
+#include "control.h"
+
+/* Global address base setup code */
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
+{
+        omap2_set_globals_tap(omap2_globals);
+        omap2_set_globals_sdrc(omap2_globals);
+        omap2_set_globals_control(omap2_globals);
+        omap2_set_globals_prcm(omap2_globals);
+}
+
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2420)
+
+static struct omap_globals omap242x_globals = {
+        .class  = OMAP242X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
+        .sdrc   = OMAP2420_SDRC_BASE,
+        .sms    = OMAP2420_SMS_BASE,
+        .ctrl   = OMAP242X_CTRL_BASE,
+        .prm    = OMAP2420_PRM_BASE,
+        .cm     = OMAP2420_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
+};
+
+void __init omap2_set_globals_242x(void)
+{
+        __omap2_set_globals(&omap242x_globals);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2430)
+
+static struct omap_globals omap243x_globals = {
+        .class  = OMAP243X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
+        .sdrc   = OMAP243X_SDRC_BASE,
+        .sms    = OMAP243X_SMS_BASE,
+        .ctrl   = OMAP243X_CTRL_BASE,
+        .prm    = OMAP2430_PRM_BASE,
+        .cm     = OMAP2430_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
+};
+
+void __init omap2_set_globals_243x(void)
+{
+        __omap2_set_globals(&omap243x_globals);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3)
+
+static struct omap_globals omap3_globals = {
+        .class  = OMAP343X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
+        .sdrc   = OMAP343X_SDRC_BASE,
+        .sms    = OMAP343X_SMS_BASE,
+        .ctrl   = OMAP343X_CTRL_BASE,
+        .prm    = OMAP3430_PRM_BASE,
+        .cm     = OMAP3430_CM_BASE,
+        .uart1_phys     = OMAP3_UART1_BASE,
+        .uart2_phys     = OMAP3_UART2_BASE,
+        .uart3_phys     = OMAP3_UART3_BASE,
+        .uart4_phys     = OMAP3_UART4_BASE,     /* Only on 3630 */
+};
+
+void __init omap2_set_globals_3xxx(void)
+{
+        __omap2_set_globals(&omap3_globals);
+}
+
+void __init omap3_map_io(void)
+{
+        omap2_set_globals_3xxx();
+        omap34xx_map_common_io();
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4)
+static struct omap_globals omap4_globals = {
+        .class  = OMAP443X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
+        .ctrl   = OMAP443X_SCM_BASE,
+        .ctrl_pad       = OMAP443X_CTRL_BASE,
+        .prm    = OMAP4430_PRM_BASE,
+        .cm     = OMAP4430_CM_BASE,
+        .cm2    = OMAP4430_CM2_BASE,
+        .uart1_phys     = OMAP4_UART1_BASE,
+        .uart2_phys     = OMAP4_UART2_BASE,
+        .uart3_phys     = OMAP4_UART3_BASE,
+        .uart4_phys     = OMAP4_UART4_BASE,
+};
+
+void __init omap2_set_globals_443x(void)
+{
+        omap2_set_globals_tap(&omap4_globals);
+        omap2_set_globals_control(&omap4_globals);
+        omap2_set_globals_prcm(&omap4_globals);
+}
+#endif
+
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20eef230..1fa3294b604 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -16,15 +16,18 @@
 #include <linux/io.h>
 
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/sdrc.h>
+
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "prm.h"
 #include "sdrc.h"
+#include "pm.h"
+#include "control.h"
 
 static void __iomem *omap2_ctrl_base;
+static void __iomem *omap4_ctrl_pad_base;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 struct omap3_scratchpad {
@@ -137,6 +140,7 @@ static struct omap3_control_regs control_context;
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 
 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
+#define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 
 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
@@ -145,6 +149,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
                 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
                 WARN_ON(!omap2_ctrl_base);
         }
+
+        /* Static mapping, never released */
+        if (omap2_globals->ctrl_pad) {
+                omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
+                WARN_ON(!omap4_ctrl_pad_base);
+        }
 }
 
 void __iomem *omap_ctrl_base_get(void)
@@ -182,6 +192,23 @@ void omap_ctrl_writel(u32 val, u16 offset)
         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 }
 
+/*
+ * On OMAP4 control pad are not addressable from control
+ * core base. So the common omap_ctrl_read/write APIs breaks
+ * Hence export separate APIs to manage the omap4 pad control
+ * registers. This APIs will work only for OMAP4
+ */
+
+u32 omap4_ctrl_pad_readl(u16 offset)
+{
+        return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
+}
+
+void omap4_ctrl_pad_writel(u32 val, u16 offset)
+{
+        __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
+}
+
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 /*
  * Clears the scratchpad contents in case of cold boot-
@@ -190,7 +217,7 @@ void omap_ctrl_writel(u32 val, u16 offset)
 void omap3_clear_scratchpad_contents(void)
 {
         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
-        u32 *v_addr;
+        void __iomem *v_addr;
         u32 offset = 0;
         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
         if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
@@ -206,7 +233,7 @@ void omap3_clear_scratchpad_contents(void)
 /* Populate the scratchpad structure with restore structure */
 void omap3_save_scratchpad_contents(void)
 {
-        void * __iomem scratchpad_address;
+        void  __iomem *scratchpad_address;
         u32 arm_context_addr;
         struct omap3_scratchpad scratchpad_contents;
         struct omap3_scratchpad_prcm_block prcm_block_contents;
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/mach-omap2/control.h
index 131bf405c2f..b6c6b7c450b 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -1,10 +1,10 @@
 /*
- * arch/arm/plat-omap/include/mach/control.h
+ * arch/arm/mach-omap2/control.h
  *
  * OMAP2/3/4 System Control Module definitions
  *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2010 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -13,10 +13,14 @@
  * the Free Software Foundation.
  */
 
-#ifndef __ASM_ARCH_CONTROL_H
-#define __ASM_ARCH_CONTROL_H
+#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
+#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 
 #include <mach/io.h>
+#include <mach/ctrl_module_core_44xx.h>
+#include <mach/ctrl_module_wkup_44xx.h>
+#include <mach/ctrl_module_pad_core_44xx.h>
+#include <mach/ctrl_module_pad_wkup_44xx.h>
 
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
@@ -204,12 +208,6 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
-/* 44xx control status register offset */
-#define OMAP44XX_CONTROL_STATUS         0x2c4
-
-/* 44xx-only CONTROL_GENERAL register offsets */
-#define OMAP44XX_CONTROL_MMC1                   0x628
-#define OMAP44XX_CONTROL_PBIAS_LITE             0x600
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
@@ -225,6 +223,8 @@
 #define OMAP2_MMCSDIO1ADPCLKISEL        (1 << 24) /* MMC1 loop back clock */
 #define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
 #define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
+#define OMAP2_MCBSP1_FSR_MASK           (1 << 4)
+#define OMAP2_MCBSP1_CLKR_MASK          (1 << 3)
 #define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
 
 /* CONTROL_DEVCONF1 bits */
@@ -255,23 +255,6 @@
 #define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
 #define OMAP2_PBIASLITEVMODE0           (1 << 0)
 
-/* CONTROL_PBIAS_LITE bits for OMAP4 */
-#define OMAP4_MMC1_PWRDNZ                       (1 << 26)
-#define OMAP4_MMC1_PBIASLITE_HIZ_MODE           (1 << 25)
-#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT      (1 << 24)
-#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR        (1 << 23)
-#define OMAP4_MMC1_PBIASLITE_PWRDNZ             (1 << 22)
-#define OMAP4_MMC1_PBIASLITE_VMODE              (1 << 21)
-#define OMAP4_USBC1_ICUSB_PWRDNZ                (1 << 20)
-
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0     (1 << 31)
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1     (1 << 30)
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2     (1 << 29)
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3     (1 << 28)
-#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL      (1 << 27)
-#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL      (1 << 26)
-#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL      (1 << 25)
-
 /* CONTROL_PROG_IO1 bits */
 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
 
@@ -338,12 +321,12 @@
 #define         FEAT_L2CACHE_256KB      3
 
 #define OMAP3_ISP_SHIFT                 5
-#define OMAP3_ISP_MASK                  (1<< OMAP3_ISP_SHIFT)
+#define OMAP3_ISP_MASK                  (1 << OMAP3_ISP_SHIFT)
 #define         FEAT_ISP                0
 #define         FEAT_ISP_NONE           1
 
 #define OMAP3_NEON_SHIFT                4
-#define OMAP3_NEON_MASK                 (1<< OMAP3_NEON_SHIFT)
+#define OMAP3_NEON_MASK                 (1 << OMAP3_NEON_SHIFT)
 #define         FEAT_NEON               0
 #define         FEAT_NEON_NONE          1
 
@@ -354,9 +337,11 @@ extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
+extern u32 omap4_ctrl_pad_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
+extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
 
 extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
@@ -371,11 +356,13 @@ extern void omap3_control_restore_context(void);
 #define omap_ctrl_readb(x)              0
 #define omap_ctrl_readw(x)              0
 #define omap_ctrl_readl(x)              0
+#define omap4_ctrl_pad_readl(x)         0
 #define omap_ctrl_writeb(x, y)          WARN_ON(1)
 #define omap_ctrl_writew(x, y)          WARN_ON(1)
 #define omap_ctrl_writel(x, y)          WARN_ON(1)
+#define omap4_ctrl_pad_writel(x, y)     WARN_ON(1)
 #endif
 #endif  /* __ASSEMBLY__ */
 
-#endif /* __ASM_ARCH_CONTROL_H */
+#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
 
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 3d3d035db9a..0d50b45d041 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -29,10 +29,10 @@
 #include <plat/irqs.h>
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
-#include <plat/control.h>
 #include <plat/serial.h>
 
 #include "pm.h"
+#include "control.h"
 
 #ifdef CONFIG_CPU_IDLE
 
@@ -60,7 +60,8 @@ struct omap3_processor_cx {
 
 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
 struct omap3_processor_cx current_cx_state;
-struct powerdomain *mpu_pd, *core_pd;
+struct powerdomain *mpu_pd, *core_pd, *per_pd;
+struct powerdomain *cam_pd;
 
 /*
  * The latencies/thresholds for various C states have
@@ -233,14 +234,60 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
                                struct cpuidle_state *state)
 {
         struct cpuidle_state *new_state = next_valid_state(dev, state);
+        u32 core_next_state, per_next_state = 0, per_saved_state = 0;
+        u32 cam_state;
+        struct omap3_processor_cx *cx;
+        int ret;
 
         if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
                 BUG_ON(!dev->safe_state);
                 new_state = dev->safe_state;
+                goto select_state;
         }
 
+        cx = cpuidle_get_statedata(state);
+        core_next_state = cx->core_state;
+
+        /*
+         * FIXME: we currently manage device-specific idle states
+         *        for PER and CORE in combination with CPU-specific
+         *        idle states.  This is wrong, and device-specific
+         *        idle managment needs to be separated out into 
+         *        its own code.
+         */
+
+        /*
+         * Prevent idle completely if CAM is active.
+         * CAM does not have wakeup capability in OMAP3.
+         */
+        cam_state = pwrdm_read_pwrst(cam_pd);
+        if (cam_state == PWRDM_POWER_ON) {
+                new_state = dev->safe_state;
+                goto select_state;
+        }
+
+        /*
+         * Prevent PER off if CORE is not in retention or off as this
+         * would disable PER wakeups completely.
+         */
+        per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
+        if ((per_next_state == PWRDM_POWER_OFF) &&
+            (core_next_state > PWRDM_POWER_RET))
+                per_next_state = PWRDM_POWER_RET;
+
+        /* Are we changing PER target state? */
+        if (per_next_state != per_saved_state)
+                pwrdm_set_next_pwrst(per_pd, per_next_state);
+
+select_state:
         dev->last_state = new_state;
-        return omap3_enter_idle(dev, new_state);
+        ret = omap3_enter_idle(dev, new_state);
+
+        /* Restore original PER state if it was modified */
+        if (per_next_state != per_saved_state)
+                pwrdm_set_next_pwrst(per_pd, per_saved_state);
+
+        return ret;
 }
 
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
@@ -328,7 +375,8 @@ void omap_init_power_states(void)
                         cpuidle_params_table[OMAP3_STATE_C2].threshold;
         omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
         omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
+        omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
+                                CPUIDLE_FLAG_CHECK_BM;
 
         /* C3 . MPU CSWR + Core inactive */
         omap3_power_states[OMAP3_STATE_C3].valid =
@@ -426,6 +474,8 @@ int __init omap3_idle_init(void)
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
         core_pd = pwrdm_lookup("core_pwrdm");
+        per_pd = pwrdm_lookup("per_pwrdm");
+        cam_pd = pwrdm_lookup("cam_pwrdm");
 
         omap_init_power_states();
         cpuidle_register_driver(&omap3_idle_driver);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2dbb265bedd..5a0c148e23b 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -9,12 +9,12 @@
  * (at your option) any later version.
  */
 
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/err.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -22,14 +22,17 @@
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
 
-#include <plat/control.h>
 #include <plat/tc.h>
 #include <plat/board.h>
+#include <plat/mcbsp.h>
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 #include <plat/dma.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 
 #include "mux.h"
+#include "control.h"
 
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
@@ -235,6 +238,43 @@ static inline void omap_init_mbox(void) { }
 
 static inline void omap_init_sti(void) {}
 
+#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
+
+static struct platform_device omap_pcm = {
+        .name   = "omap-pcm-audio",
+        .id     = -1,
+};
+
+/*
+ * OMAP2420 has 2 McBSP ports
+ * OMAP2430 has 5 McBSP ports
+ * OMAP3 has 5 McBSP ports
+ * OMAP4 has 4 McBSP ports
+ */
+OMAP_MCBSP_PLATFORM_DEVICE(1);
+OMAP_MCBSP_PLATFORM_DEVICE(2);
+OMAP_MCBSP_PLATFORM_DEVICE(3);
+OMAP_MCBSP_PLATFORM_DEVICE(4);
+OMAP_MCBSP_PLATFORM_DEVICE(5);
+
+static void omap_init_audio(void)
+{
+        platform_device_register(&omap_mcbsp1);
+        platform_device_register(&omap_mcbsp2);
+        if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                platform_device_register(&omap_mcbsp3);
+                platform_device_register(&omap_mcbsp4);
+        }
+        if (cpu_is_omap243x() || cpu_is_omap34xx())
+                platform_device_register(&omap_mcbsp5);
+
+        platform_device_register(&omap_pcm);
+}
+
+#else
+static inline void omap_init_audio(void) {}
+#endif
+
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
 #include <plat/mcspi.h>
@@ -498,6 +538,76 @@ static void omap_init_sham(void)
 static inline void omap_init_sham(void) { }
 #endif
 
+#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
+
+#ifdef CONFIG_ARCH_OMAP2
+static struct resource omap2_aes_resources[] = {
+        {
+                .start  = OMAP24XX_SEC_AES_BASE,
+                .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = OMAP24XX_DMA_AES_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = OMAP24XX_DMA_AES_RX,
+                .flags  = IORESOURCE_DMA,
+        }
+};
+static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
+#else
+#define omap2_aes_resources             NULL
+#define omap2_aes_resources_sz          0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static struct resource omap3_aes_resources[] = {
+        {
+                .start  = OMAP34XX_SEC_AES_BASE,
+                .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = OMAP34XX_DMA_AES2_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = OMAP34XX_DMA_AES2_RX,
+                .flags  = IORESOURCE_DMA,
+        }
+};
+static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
+#else
+#define omap3_aes_resources             NULL
+#define omap3_aes_resources_sz          0
+#endif
+
+static struct platform_device aes_device = {
+        .name           = "omap-aes",
+        .id             = -1,
+};
+
+static void omap_init_aes(void)
+{
+        if (cpu_is_omap24xx()) {
+                aes_device.resource = omap2_aes_resources;
+                aes_device.num_resources = omap2_aes_resources_sz;
+        } else if (cpu_is_omap34xx()) {
+                aes_device.resource = omap3_aes_resources;
+                aes_device.num_resources = omap3_aes_resources_sz;
+        } else {
+                pr_err("%s: platform not supported\n", __func__);
+                return;
+        }
+        platform_device_register(&aes_device);
+}
+
+#else
+static inline void omap_init_aes(void) { }
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
@@ -624,7 +734,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                 omap_mux_init_signal("sdmmc_dat0", 0);
                 omap_mux_init_signal("sdmmc_dat_dir0", 0);
                 omap_mux_init_signal("sdmmc_cmd_dir", 0);
-                if (mmc_controller->slots[0].wires == 4) {
+                if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
                         omap_mux_init_signal("sdmmc_dat1", 0);
                         omap_mux_init_signal("sdmmc_dat2", 0);
                         omap_mux_init_signal("sdmmc_dat3", 0);
@@ -652,8 +762,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                 OMAP_PIN_INPUT_PULLUP);
                         omap_mux_init_signal("sdmmc1_dat0",
                                 OMAP_PIN_INPUT_PULLUP);
-                        if (mmc_controller->slots[0].wires == 4 ||
-                                mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
                                 omap_mux_init_signal("sdmmc1_dat1",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc1_dat2",
@@ -661,7 +771,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                 omap_mux_init_signal("sdmmc1_dat3",
                                         OMAP_PIN_INPUT_PULLUP);
                         }
-                        if (mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                                MMC_CAP_8_BIT_DATA) {
                                 omap_mux_init_signal("sdmmc1_dat4",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc1_dat5",
@@ -685,8 +796,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
                          * in the board-*.c files
                          */
-                        if (mmc_controller->slots[0].wires == 4 ||
-                                mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
                                 omap_mux_init_signal("sdmmc2_dat1",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc2_dat2",
@@ -694,7 +805,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                 omap_mux_init_signal("sdmmc2_dat3",
                                         OMAP_PIN_INPUT_PULLUP);
                         }
-                        if (mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                                        MMC_CAP_8_BIT_DATA) {
                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
@@ -745,13 +857,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
                 case 3:
                         if (!cpu_is_omap44xx())
                                 return;
-                        base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
+                        base = OMAP4_MMC4_BASE;
                         irq = OMAP44XX_IRQ_MMC4;
                         break;
                 case 4:
                         if (!cpu_is_omap44xx())
                                 return;
-                        base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
+                        base = OMAP4_MMC5_BASE;
                         irq = OMAP44XX_IRQ_MMC5;
                         break;
                 default:
@@ -762,10 +874,8 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
                         size = OMAP2420_MMC_SIZE;
                         name = "mmci-omap";
                 } else if (cpu_is_omap44xx()) {
-                        if (i < 3) {
-                                base += OMAP4_MMC_REG_OFFSET;
+                        if (i < 3)
                                 irq += OMAP44XX_IRQ_GIC_START;
-                        }
                         size = OMAP4_HSMMC_SIZE;
                         name = "mmci-omap-hs";
                 } else {
@@ -841,12 +951,74 @@ static inline void omap_init_vout(void) {}
 
 /*-------------------------------------------------------------------------*/
 
+/*
+ * Inorder to avoid any assumptions from bootloader regarding WDT
+ * settings, WDT module is reset during init. This enables the watchdog
+ * timer. Hence it is required to disable the watchdog after the WDT reset
+ * during init. Otherwise the system would reboot as per the default
+ * watchdog timer registers settings.
+ */
+#define OMAP_WDT_WPS    (0x34)
+#define OMAP_WDT_SPR    (0x48)
+
+static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
+{
+        void __iomem *base;
+        int ret;
+
+        if (!oh) {
+                pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
+                return -EINVAL;
+        }
+
+        base = omap_hwmod_get_mpu_rt_va(oh);
+        if (!base) {
+                pr_err("%s: Could not get the base address for %s\n",
+                                oh->name, __func__);
+                return -EINVAL;
+        }
+
+        /* Enable the clocks before accessing the WDT registers */
+        ret = omap_hwmod_enable(oh);
+        if (ret) {
+                pr_err("%s: Could not enable clocks for %s\n",
+                                oh->name, __func__);
+                return ret;
+        }
+
+        /* sequence required to disable watchdog */
+        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        __raw_writel(0x5555, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        ret = omap_hwmod_idle(oh);
+        if (ret)
+                pr_err("%s: Could not disable clocks for %s\n",
+                                oh->name, __func__);
+
+        return ret;
+}
+
+static void __init omap_disable_wdt(void)
+{
+        if (cpu_class_is_omap2())
+                omap_hwmod_for_each_by_class("wd_timer",
+                                                omap2_disable_wdt, NULL);
+        return;
+}
+
 static int __init omap2_init_devices(void)
 {
         /* please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
+        omap_disable_wdt();
         omap_hsmmc_reset();
+        omap_init_audio();
         omap_init_camera();
         omap_init_mbox();
         omap_init_mcspi();
@@ -854,8 +1026,45 @@ static int __init omap2_init_devices(void)
         omap_hdq_init();
         omap_init_sti();
         omap_init_sham();
+        omap_init_aes();
         omap_init_vout();
 
         return 0;
 }
 arch_initcall(omap2_init_devices);
+
+#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+struct omap_device_pm_latency omap_wdt_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+static int __init omap_init_wdt(void)
+{
+        int id = -1;
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+        char *oh_name = "wd_timer2";
+        char *dev_name = "omap_wdt";
+
+        if (!cpu_class_is_omap2())
+                return 0;
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up wd_timer%d hwmod\n", id);
+                return -EINVAL;
+        }
+
+        od = omap_device_build(dev_name, id, oh, NULL, 0,
+                                omap_wdt_latency,
+                                ARRAY_SIZE(omap_wdt_latency), 0);
+        WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
+                                dev_name, oh->name);
+        return 0;
+}
+subsys_initcall(omap_init_wdt);
+#endif
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
new file mode 100644
index 00000000000..703f150dd01
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -0,0 +1,113 @@
+/*
+ * linux/arch/arm/mach-omap2/gpmc-smsc911x.c
+ *
+ * Copyright (C) 2009 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/smsc911x.h>
+
+#include <plat/board.h>
+#include <plat/gpmc.h>
+#include <plat/gpmc-smsc911x.h>
+
+static struct omap_smsc911x_platform_data *gpmc_cfg;
+
+static struct resource gpmc_smsc911x_resources[] = {
+        [0] = {
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config gpmc_smsc911x_config = {
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_16BIT,
+};
+
+static struct platform_device gpmc_smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(gpmc_smsc911x_resources),
+        .resource       = gpmc_smsc911x_resources,
+        .dev            = {
+                .platform_data = &gpmc_smsc911x_config,
+        },
+};
+
+/*
+ * Initialize smsc911x device connected to the GPMC. Note that we
+ * assume that pin multiplexing is done in the board-*.c file,
+ * or in the bootloader.
+ */
+void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
+{
+        unsigned long cs_mem_base;
+        int ret;
+
+        gpmc_cfg = board_data;
+
+        if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
+                return;
+        }
+
+        gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
+        gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
+
+        if (gpio_request(gpmc_cfg->gpio_irq, "smsc911x irq") < 0) {
+                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
+                                gpmc_cfg->gpio_irq);
+                goto free1;
+        }
+
+        gpio_direction_input(gpmc_cfg->gpio_irq);
+        gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
+        gpmc_smsc911x_resources[1].flags |=
+                                        (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
+
+        if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
+                ret = gpio_request(gpmc_cfg->gpio_reset, "smsc911x reset");
+                if (ret) {
+                        printk(KERN_ERR "Failed to request GPIO%d for smsc911x reset\n",
+                                        gpmc_cfg->gpio_reset);
+                        goto free2;
+                }
+
+                gpio_direction_output(gpmc_cfg->gpio_reset, 1);
+                gpio_set_value(gpmc_cfg->gpio_reset, 0);
+                msleep(100);
+                gpio_set_value(gpmc_cfg->gpio_reset, 1);
+        }
+
+        if (platform_device_register(&gpmc_smsc911x_device) < 0) {
+                printk(KERN_ERR "Unable to register smsc911x device\n");
+                gpio_free(gpmc_cfg->gpio_reset);
+                goto free2;
+        }
+
+        return;
+
+free2:
+        gpio_free(gpmc_cfg->gpio_irq);
+free1:
+        gpmc_cs_free(gpmc_cfg->cs);
+
+        printk(KERN_ERR "Could not initialize smsc911x\n");
+}
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index c8f647b6205..34272e4863f 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,11 +14,11 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <mach/hardware.h>
-#include <plat/control.h>
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
 
 #include "hsmmc.h"
+#include "control.h"
 
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
@@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
          *
          * FIXME handle VMMC1A as needed ...
          */
-        reg = omap_ctrl_readl(control_pbias_offset);
-        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
-                                        OMAP4_USBC1_ICUSB_PWRDNZ);
-        omap_ctrl_writel(reg, control_pbias_offset);
+        reg = omap4_ctrl_pad_readl(control_pbias_offset);
+        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                OMAP4_MMC1_PWRDNZ_MASK |
+                OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+        omap4_ctrl_pad_writel(reg, control_pbias_offset);
 }
 
 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
@@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
         u32 reg;
 
         if (power_on) {
-                reg = omap_ctrl_readl(control_pbias_offset);
-                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
                 if ((1 << vdd) <= MMC_VDD_165_195)
-                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;
+                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
                 else
-                        reg |= OMAP4_MMC1_PBIASLITE_VMODE;
-                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
-                                                OMAP4_USBC1_ICUSB_PWRDNZ);
-                omap_ctrl_writel(reg, control_pbias_offset);
+                        reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
+                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                        OMAP4_MMC1_PWRDNZ_MASK |
+                        OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                omap4_ctrl_pad_writel(reg, control_pbias_offset);
                 /* 4 microsec delay for comparator to generate an error*/
                 udelay(4);
-                reg = omap_ctrl_readl(control_pbias_offset);
-                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
                         pr_err("Pbias Voltage is not same as LDO\n");
                         /* Caution : On VMODE_ERROR Power Down MMC IO */
-                        reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);
-                        omap_ctrl_writel(reg, control_pbias_offset);
+                        reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
+                                OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                        omap4_ctrl_pad_writel(reg, control_pbias_offset);
                 }
         } else {
-                reg = omap_ctrl_readl(control_pbias_offset);
-                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |
-                        OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |
-                        OMAP4_USBC1_ICUSB_PWRDNZ);
-                omap_ctrl_writel(reg, control_pbias_offset);
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                        OMAP4_MMC1_PWRDNZ_MASK |
+                        OMAP4_MMC1_PBIASLITE_VMODE_MASK |
+                        OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                omap4_ctrl_pad_writel(reg, control_pbias_offset);
         }
 }
 
@@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
                 }
         } else {
-                control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;
-                control_mmc1 = OMAP44XX_CONTROL_MMC1;
-                reg = omap_ctrl_readl(control_mmc1);
-                reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |
-                        OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);
-                reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |
-                        OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);
-                reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |
-                        OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |
-                        OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);
-                omap_ctrl_writel(reg, control_mmc1);
+                control_pbias_offset =
+                        OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
+                control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
+                reg = omap4_ctrl_pad_readl(control_mmc1);
+                reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
+                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
+                reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
+                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
+                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
+                omap4_ctrl_pad_writel(reg, control_mmc1);
         }
 
         for (c = controllers; c->mmc; c++) {
@@ -258,9 +263,13 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                                 "mmc%islot%i", c->mmc, 1);
                 mmc->slots[0].name = hc->name;
                 mmc->nr_slots = 1;
-                mmc->slots[0].wires = c->wires;
+                mmc->slots[0].caps = c->caps;
                 mmc->slots[0].internal_clock = !c->ext_clock;
                 mmc->dma_mask = 0xffffffff;
+                if (cpu_is_omap44xx())
+                        mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
+                else
+                        mmc->reg_offset = 0;
 
                 mmc->get_context_loss_count = hsmmc_get_context_loss;
 
@@ -298,6 +307,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                 else
                         mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 
+                if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
+                        mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+
                 switch (c->mmc) {
                 case 1:
                         if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
@@ -316,16 +328,20 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                         }
 
                         /* Omap3630 HSMMC1 supports only 4-bit */
-                        if (cpu_is_omap3630() && c->wires > 4) {
-                                c->wires = 4;
-                                mmc->slots[0].wires = c->wires;
+                        if (cpu_is_omap3630() &&
+                                        (c->caps & MMC_CAP_8_BIT_DATA)) {
+                                c->caps &= ~MMC_CAP_8_BIT_DATA;
+                                c->caps |= MMC_CAP_4_BIT_DATA;
+                                mmc->slots[0].caps = c->caps;
                         }
                         break;
                 case 2:
                         if (c->ext_clock)
                                 c->transceiver = 1;
-                        if (c->transceiver && c->wires > 4)
-                                c->wires = 4;
+                        if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
+                                c->caps &= ~MMC_CAP_8_BIT_DATA;
+                                c->caps |= MMC_CAP_4_BIT_DATA;
+                        }
                         /* FALLTHROUGH */
                 case 3:
                         if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 1fe6f018717..f119348827d 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -10,7 +10,8 @@ struct mmc_card;
 
 struct omap2_hsmmc_info {
         u8      mmc;            /* controller 1/2/3 */
-        u8      wires;          /* 1/4/8 wires */
+        u32     caps;           /* 4/8 wires and any additional host
+                                 * capabilities OR'd (ref. linux/mmc/host.h) */
         bool    transceiver;    /* MMC-2 option */
         bool    ext_clock;      /* use external pin for input clock */
         bool    cover_only;     /* No card detect - just cover switch */
@@ -23,7 +24,7 @@ struct omap2_hsmmc_info {
         char    *name;          /* or NULL for default */
         struct device *dev;     /* returned: pointer to mmc adapter */
         int     ocr_mask;       /* temporary HACK */
-        /* Remux (pad configuation) when powering on/off */
+        /* Remux (pad configuration) when powering on/off */
         void (*remux)(struct device *dev, int slot, int power_on);
         /* init some special card */
         void (*init_card)(struct mmc_card *card);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9a879f95950..5f9086c65e4 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,11 +22,12 @@
 #include <asm/cputype.h>
 
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/cpu.h>
 
 #include <mach/id.h>
 
+#include "control.h"
+
 static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 
@@ -60,7 +61,7 @@ int omap_type(void)
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
-                val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
+                val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
         } else {
                 pr_err("Cannot detect omap type!\n");
                 goto out;
@@ -298,7 +299,6 @@ static void __init omap4_check_revision(void)
         u32 idcode;
         u16 hawkeye;
         u8 rev;
-        char *rev_name = "ES1.0";
 
         /*
          * The IC rev detection is done with hawkeye and rev.
@@ -309,14 +309,39 @@ static void __init omap4_check_revision(void)
         hawkeye = (idcode >> 12) & 0xffff;
         rev = (idcode >> 28) & 0xff;
 
-        if ((hawkeye == 0xb852) && (rev == 0x0)) {
-                omap_revision = OMAP4430_REV_ES1_0;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES1;
-                pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
-                return;
+        /*
+         * Few initial ES2.0 samples IDCODE is same as ES1.0
+         * Use ARM register to detect the correct ES version
+         */
+        if (!rev) {
+                idcode = read_cpuid(CPUID_ID);
+                rev = (idcode & 0xf) - 1;
+        }
+
+        switch (hawkeye) {
+        case 0xb852:
+                switch (rev) {
+                case 0:
+                        omap_revision = OMAP4430_REV_ES1_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES1;
+                        break;
+                case 1:
+                        omap_revision = OMAP4430_REV_ES2_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                        break;
+                default:
+                        omap_revision = OMAP4430_REV_ES2_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+        }
+        break;
+        default:
+                /* Unknown default to latest silicon rev as default*/
+                omap_revision = OMAP4430_REV_ES2_0;
+                omap_chip.oc |= CHIP_IS_OMAP4430ES2;
         }
 
-        pr_err("Unknown OMAP4 CPU id\n");
+        pr_info("OMAP%04x ES%d.0\n",
+                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
 }
 
 #define OMAP3_SHOW_FEATURE(feat)                \
@@ -361,30 +386,54 @@ static void __init omap3_cpuinfo(void)
                 strcpy(cpu_name, "OMAP3503");
         }
 
-        switch (rev) {
-        case OMAP_REVBITS_00:
-                strcpy(cpu_rev, "1.0");
-                break;
-        case OMAP_REVBITS_01:
-                strcpy(cpu_rev, "1.1");
-                break;
-        case OMAP_REVBITS_02:
-                strcpy(cpu_rev, "1.2");
-                break;
-        case OMAP_REVBITS_10:
-                strcpy(cpu_rev, "2.0");
-                break;
-        case OMAP_REVBITS_20:
-                strcpy(cpu_rev, "2.1");
-                break;
-        case OMAP_REVBITS_30:
-                strcpy(cpu_rev, "3.0");
-                break;
-        case OMAP_REVBITS_40:
-        /* FALLTHROUGH */
-        default:
-                /* Use the latest known revision as default */
-                strcpy(cpu_rev, "3.1");
+        if (cpu_is_omap3630()) {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        strcpy(cpu_rev, "1.1");
+                        break;
+                case OMAP_REVBITS_02:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "1.2");
+                }
+        } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "1.1");
+                }
+        } else {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        strcpy(cpu_rev, "2.0");
+                        break;
+                case OMAP_REVBITS_02:
+                        strcpy(cpu_rev, "2.1");
+                        break;
+                case OMAP_REVBITS_03:
+                        strcpy(cpu_rev, "3.0");
+                        break;
+                case OMAP_REVBITS_04:
+                        strcpy(cpu_rev, "3.1");
+                        break;
+                case OMAP_REVBITS_05:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "3.1.2");
+                }
         }
 
         /* Print verbose information */
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/include/mach/board-rx51.h
new file mode 100644
index 00000000000..b76f49e7eed
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-rx51.h
@@ -0,0 +1,11 @@
+/*
+ * Defines for rx51 boards
+ */
+
+#ifndef _OMAP_BOARD_RX51_H
+#define _OMAP_BOARD_RX51_H
+
+extern void __init rx51_peripherals_init(void);
+extern void __init rx51_video_mem_init(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index 3af69d2c3dc..f93ca3928c3 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -1,11 +1,9 @@
 /*
  * Defines for zoom boards
  */
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
 #define ZOOM_NAND_CS    0
 
-extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs);
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);
+
+#define ZOOM2_HEADSET_EXTMUTE_GPIO      153
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
new file mode 100644
index 00000000000..2f7ac70a20d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -0,0 +1,391 @@
+/*
+ * OMAP44xx CTRL_MODULE_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_CORE                                  0x4a002000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_CORE_IP_REVISION                      0x0000
+#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO                        0x0004
+#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG                     0x0010
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0                0x0200
+#define OMAP4_CTRL_MODULE_CORE_ID_CODE                          0x0204
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1                0x0208
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2                0x020c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3                0x0210
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0               0x0214
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1               0x0218
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF                0x021c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP            0x0228
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP                0x0260
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0              0x0264
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1              0x0268
+#define OMAP4_CTRL_MODULE_CORE_STATUS                           0x02c4
+#define OMAP4_CTRL_MODULE_CORE_DEV_CONF                         0x0300
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL          0x0314
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL          0x0318
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL         0x0320
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL         0x0324
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL        0x0328
+#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR                      0x032c
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0                0x0330
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1                0x0334
+#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL                 0x033c
+#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL                      0x0340
+#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL                    0x0350
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL             0x0400
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU                   0x0408
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0               0x042c
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1               0x0430
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2               0x0434
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3               0x0438
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0                    0x0440
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1                    0x0444
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2                    0x0448
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL           0x044c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL             0x0450
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL          0x0454
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0             0x0480
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1             0x0484
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2             0x0488
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3             0x048c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4             0x0490
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5             0x0494
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6             0x0498
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7             0x049c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8             0x04a0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9             0x04a4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10            0x04a8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11            0x04ac
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12            0x04b0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13            0x04b4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14            0x04b8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15            0x04bc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16            0x04c0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17            0x04c4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18            0x04c8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19            0x04cc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20            0x04d0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21            0x04d4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22            0x04d8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23            0x04dc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24            0x04e0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25            0x04e4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26            0x04e8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27            0x04ec
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28            0x04f0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29            0x04f4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30            0x04f8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31            0x04fc
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                       30
+#define OMAP4_IP_REV_SCHEME_MASK                        (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                         16
+#define OMAP4_IP_REV_FUNC_MASK                          (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                          11
+#define OMAP4_IP_REV_RTL_MASK                           (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                        8
+#define OMAP4_IP_REV_MAJOR_MASK                         (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                       6
+#define OMAP4_IP_REV_CUSTOM_MASK                        (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                        0
+#define OMAP4_IP_REV_MINOR_MASK                         (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                           0
+#define OMAP4_IP_HWINFO_MASK                            (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT               2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                (0x3 << 2)
+
+/* STD_FUSE_DIE_ID_0 */
+#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_0_MASK                    (0xffffffff << 0)
+
+/* ID_CODE */
+#define OMAP4_STD_FUSE_IDCODE_SHIFT                     0
+#define OMAP4_STD_FUSE_IDCODE_MASK                      (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_1 */
+#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_1_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_2 */
+#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_2_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_3 */
+#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_3_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_0 */
+#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_0_MASK                   (0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_1 */
+#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_1_MASK                   (0xffffffff << 0)
+
+/* STD_FUSE_USB_CONF */
+#define OMAP4_USB_PROD_ID_SHIFT                         16
+#define OMAP4_USB_PROD_ID_MASK                          (0xffff << 16)
+#define OMAP4_USB_VENDOR_ID_SHIFT                       0
+#define OMAP4_USB_VENDOR_ID_MASK                        (0xffff << 0)
+
+/* STD_FUSE_OPP_VDD_WKUP */
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT               0
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK                (0xffffffff << 0)
+
+/* STD_FUSE_OPP_BGAP */
+#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT                   0
+#define OMAP4_STD_FUSE_OPP_BGAP_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_0 */
+#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK                  (0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_1 */
+#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK                  (0xffffffff << 0)
+
+/* STATUS */
+#define OMAP4_ATTILA_CONF_SHIFT                         11
+#define OMAP4_ATTILA_CONF_MASK                          (0x3 << 11)
+#define OMAP4_DEVICE_TYPE_SHIFT                         8
+#define OMAP4_DEVICE_TYPE_MASK                          (0x7 << 8)
+#define OMAP4_SYS_BOOT_SHIFT                            0
+#define OMAP4_SYS_BOOT_MASK                             (0xff << 0)
+
+/* DEV_CONF */
+#define OMAP4_DEV_CONF_SHIFT                            1
+#define OMAP4_DEV_CONF_MASK                             (0x7fffffff << 1)
+#define OMAP4_USBPHY_PD_SHIFT                           0
+#define OMAP4_USBPHY_PD_MASK                            (1 << 0)
+
+/* LDOVBB_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK               (0x1f << 0)
+
+/* LDOVBB_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK               (0x1f << 0)
+
+/* LDOSRAM_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+
+/* LDOSRAM_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+
+/* LDOSRAM_CORE_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT        26
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK         (1 << 26)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT         21
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK          (0x1f << 21)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT        16
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK         (0x1f << 16)
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT        10
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK         (1 << 10)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT         5
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK          (0x1f << 5)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT        0
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK         (0x1f << 0)
+
+/* TEMP_SENSOR */
+#define OMAP4_BGAP_TEMPSOFF_SHIFT                       12
+#define OMAP4_BGAP_TEMPSOFF_MASK                        (1 << 12)
+#define OMAP4_BGAP_TSHUT_SHIFT                          11
+#define OMAP4_BGAP_TSHUT_MASK                           (1 << 11)
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT           10
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK            (1 << 10)
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT                9
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK                 (1 << 9)
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT               8
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK                (1 << 8)
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT              0
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK               (0xff << 0)
+
+/* DPLL_NWELL_TRIM_0 */
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT        29
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK         (1 << 29)
+#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT                 24
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK                  (0x1f << 24)
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_PER_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT        11
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK         (1 << 11)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT                 6
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK                  (0x1f << 6)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT        5
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK         (1 << 5)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT                 0
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK                  (0x1f << 0)
+
+/* DPLL_NWELL_TRIM_1 */
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT     29
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK      (1 << 29)
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT              24
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK               (0x1f << 24)
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_USB_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT       11
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK        (1 << 11)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT                6
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK                 (0x1f << 6)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT       5
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK        (1 << 5)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT                0
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK                 (0x1f << 0)
+
+/* USBOTGHS_CONTROL */
+#define OMAP4_DISCHRGVBUS_SHIFT                         8
+#define OMAP4_DISCHRGVBUS_MASK                          (1 << 8)
+#define OMAP4_CHRGVBUS_SHIFT                            7
+#define OMAP4_CHRGVBUS_MASK                             (1 << 7)
+#define OMAP4_DRVVBUS_SHIFT                             6
+#define OMAP4_DRVVBUS_MASK                              (1 << 6)
+#define OMAP4_IDPULLUP_SHIFT                            5
+#define OMAP4_IDPULLUP_MASK                             (1 << 5)
+#define OMAP4_IDDIG_SHIFT                               4
+#define OMAP4_IDDIG_MASK                                (1 << 4)
+#define OMAP4_SESSEND_SHIFT                             3
+#define OMAP4_SESSEND_MASK                              (1 << 3)
+#define OMAP4_VBUSVALID_SHIFT                           2
+#define OMAP4_VBUSVALID_MASK                            (1 << 2)
+#define OMAP4_BVALID_SHIFT                              1
+#define OMAP4_BVALID_MASK                               (1 << 1)
+#define OMAP4_AVALID_SHIFT                              0
+#define OMAP4_AVALID_MASK                               (1 << 0)
+
+/* DSS_CONTROL */
+#define OMAP4_DSS_MUX6_SELECT_SHIFT                     0
+#define OMAP4_DSS_MUX6_SELECT_MASK                      (1 << 0)
+
+/* HWOBS_CONTROL */
+#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT                    3
+#define OMAP4_HWOBS_CLKDIV_SEL_MASK                     (0x1f << 3)
+#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT                 2
+#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK                  (1 << 2)
+#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT                  1
+#define OMAP4_HWOBS_ALL_ONE_MODE_MASK                   (1 << 1)
+#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT                  0
+#define OMAP4_HWOBS_MACRO_ENABLE_MASK                   (1 << 0)
+
+/* DEBOBS_FINAL_MUX_SEL */
+#define OMAP4_SELECT_SHIFT                              0
+#define OMAP4_SELECT_MASK                               (0xffffffff << 0)
+
+/* DEBOBS_MMR_MPU */
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT               0
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK                (0xf << 0)
+
+/* CONF_SDMA_REQ_SEL0 */
+#define OMAP4_MULT_SHIFT                                0
+#define OMAP4_MULT_MASK                                 (0x7f << 0)
+
+/* CONF_CLK_SEL0 */
+#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL0_MASK                   (0x7 << 0)
+
+/* CONF_CLK_SEL1 */
+#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL1_MASK                   (0x7 << 0)
+
+/* CONF_CLK_SEL2 */
+#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL2_MASK                   (0x7 << 0)
+
+/* CONF_DPLL_FREQLOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT         0
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK          (0x7 << 0)
+
+/* CONF_DPLL_TINITZ_SEL */
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT           0
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK            (0x7 << 0)
+
+/* CONF_DPLL_PHASELOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT        0
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK         (0x7 << 0)
+
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_MODE_SHIFT                                0
+#define OMAP4_MODE_MASK                                 (0xf << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
new file mode 100644
index 00000000000..c88420de115
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -0,0 +1,1409 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE                              0x4a100000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION                  0x0000
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO                    0x0004
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG                 0x0010
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0        0x01d8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1        0x01dc
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2        0x01e0
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3        0x01e4
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4        0x01e8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5        0x01ec
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6        0x01f0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE         0x05a4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0   0x05a8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1   0x05ac
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0   0x05b0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1   0x05b4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0   0x05b8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1   0x05bc
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2   0x05c0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC            0x05c4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS              0x05c8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE            0x0600
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0                0x0604
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX            0x0608
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC                0x060c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY          0x0610
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2                 0x0614
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY               0x0618
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP              0x061c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE          0x0620
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1                0x0624
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1                 0x0628
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI                  0x062c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB                  0x0630
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ                  0x0634
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0          0x0638
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1          0x063c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2          0x0640
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3          0x0644
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0          0x0648
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1          0x064c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2          0x0650
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3          0x0654
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD             0x0658
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C                  0x065c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW        0x0660
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R         0x0664
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0      0x0668
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1              0x0700
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2              0x0704
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3              0x0708
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4              0x070c
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT               31
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK                (1 << 31)
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT               30
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK                (1 << 30)
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT               16
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK                (1 << 16)
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT              11
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK               (1 << 11)
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT              10
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK               (1 << 10)
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT               9
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK                (1 << 9)
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT               8
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK                (1 << 8)
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT               6
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK                (1 << 6)
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT               5
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK                (1 << 5)
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT               4
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK                (1 << 4)
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT               3
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK                (1 << 3)
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT               0
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK                (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_1 */
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT            30
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK             (1 << 30)
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT              25
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK               (1 << 25)
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT              24
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK               (1 << 24)
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT              23
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK               (1 << 23)
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT              22
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK               (1 << 22)
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT              20
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK               (1 << 20)
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT           15
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK            (1 << 15)
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT               13
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK                (1 << 13)
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT               12
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK                (1 << 12)
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT             11
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK              (1 << 11)
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_2 */
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        31
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 31)
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT         30
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 30)
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT          29
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 29)
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT          28
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 28)
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        27
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 27)
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT            25
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK             (1 << 25)
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT            24
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK             (1 << 24)
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT            23
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK             (1 << 23)
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            22
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 22)
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            21
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 21)
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            20
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 20)
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            19
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 19)
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT             18
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 18)
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             17
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 17)
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT         16
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK          (1 << 16)
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT         15
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK          (1 << 15)
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      14
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 14)
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        13
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 13)
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     12
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 12)
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     11
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 11)
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     10
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 10)
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     9
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 9)
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     8
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 8)
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     7
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 7)
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     6
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     5
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      4
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 4)
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      3
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      2
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 2)
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      1
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 1)
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT        0
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK         (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_3 */
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT             29
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK              (1 << 29)
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT             28
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 28)
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            27
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 27)
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             25
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 25)
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT                16
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK                 (1 << 16)
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT         6
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK          (1 << 6)
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT          5
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK           (1 << 5)
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        4
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 4)
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        3
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 3)
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT         2
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 2)
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT          1
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 1)
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_4 */
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      29
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        28
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 28)
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     27
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 27)
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     26
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 26)
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     25
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 25)
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     24
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 24)
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     23
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 23)
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     22
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 22)
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     21
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 21)
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     20
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 20)
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      19
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 19)
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      18
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 18)
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      17
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 17)
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      16
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 16)
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT             13
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 13)
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            12
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 12)
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            11
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 11)
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            9
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 9)
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            8
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 8)
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            7
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 7)
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            6
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 6)
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT          2
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK           (1 << 2)
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT           1
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK            (1 << 1)
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT         0
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK          (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_5 */
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT              31
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK               (1 << 31)
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT              30
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK               (1 << 30)
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT               29
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK                (1 << 29)
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT               28
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK                (1 << 28)
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT               27
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK                (1 << 27)
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT               26
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK                (1 << 26)
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT             3
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 3)
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT             2
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 2)
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT             1
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 1)
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT             0
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_6 */
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT              7
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK               (1 << 7)
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT              6
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK               (1 << 6)
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT              5
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK               (1 << 5)
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT              3
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK               (1 << 3)
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT              1
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK               (1 << 1)
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT              0
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK               (1 << 0)
+
+/* CONTROL_PADCONF_GLOBAL */
+#define OMAP4_FORCE_OFFMODE_EN_SHIFT                            31
+#define OMAP4_FORCE_OFFMODE_EN_MASK                             (1 << 31)
+
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_BANK0_SHIFT                               31
+#define OMAP4_VDDS_DV_BANK0_MASK                                (1 << 31)
+#define OMAP4_VDDS_DV_BANK1_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK1_MASK                                (1 << 30)
+#define OMAP4_VDDS_DV_BANK3_SHIFT                               29
+#define OMAP4_VDDS_DV_BANK3_MASK                                (1 << 29)
+#define OMAP4_VDDS_DV_BANK4_SHIFT                               28
+#define OMAP4_VDDS_DV_BANK4_MASK                                (1 << 28)
+#define OMAP4_VDDS_DV_BANK5_SHIFT                               27
+#define OMAP4_VDDS_DV_BANK5_MASK                                (1 << 27)
+#define OMAP4_VDDS_DV_BANK6_SHIFT                               26
+#define OMAP4_VDDS_DV_BANK6_MASK                                (1 << 26)
+#define OMAP4_VDDS_DV_C2C_SHIFT                                 25
+#define OMAP4_VDDS_DV_C2C_MASK                                  (1 << 25)
+#define OMAP4_VDDS_DV_CAM_SHIFT                                 24
+#define OMAP4_VDDS_DV_CAM_MASK                                  (1 << 24)
+#define OMAP4_VDDS_DV_GPMC_SHIFT                                23
+#define OMAP4_VDDS_DV_GPMC_MASK                                 (1 << 23)
+#define OMAP4_VDDS_DV_SDMMC2_SHIFT                              22
+#define OMAP4_VDDS_DV_SDMMC2_MASK                               (1 << 22)
+
+/* CONTROL_SMART1IO_PADCONF_0 */
+#define OMAP4_ABE_DR0_SC_SHIFT                                  30
+#define OMAP4_ABE_DR0_SC_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_SC_SHIFT                                  28
+#define OMAP4_CAM_DR0_SC_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_SC_SHIFT                                 26
+#define OMAP4_FREF_DR2_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_SC_SHIFT                                 24
+#define OMAP4_FREF_DR3_SC_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_SC_SHIFT                                 22
+#define OMAP4_GPIO_DR8_SC_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_SC_SHIFT                                 20
+#define OMAP4_GPIO_DR9_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_SC_SHIFT                                 18
+#define OMAP4_GPMC_DR2_SC_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_SC_SHIFT                                 16
+#define OMAP4_GPMC_DR3_SC_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_SC_SHIFT                                 14
+#define OMAP4_GPMC_DR6_SC_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_SC_SHIFT                                 12
+#define OMAP4_HDMI_DR0_SC_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_SC_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_SC_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_SC_SHIFT                                8
+#define OMAP4_UART1_DR0_SC_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_SC_SHIFT                                6
+#define OMAP4_UART3_DR0_SC_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_SC_SHIFT                                4
+#define OMAP4_UART3_DR1_SC_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_SC_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_SC_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_SC_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_SC_MASK                                (0x3 << 0)
+
+/* CONTROL_SMART1IO_PADCONF_1 */
+#define OMAP4_ABE_DR0_LB_SHIFT                                  30
+#define OMAP4_ABE_DR0_LB_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_LB_SHIFT                                  28
+#define OMAP4_CAM_DR0_LB_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_LB_SHIFT                                 26
+#define OMAP4_FREF_DR2_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_LB_SHIFT                                 24
+#define OMAP4_FREF_DR3_LB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_LB_SHIFT                                 22
+#define OMAP4_GPIO_DR8_LB_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_LB_SHIFT                                 20
+#define OMAP4_GPIO_DR9_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_LB_SHIFT                                 18
+#define OMAP4_GPMC_DR2_LB_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_LB_SHIFT                                 16
+#define OMAP4_GPMC_DR3_LB_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_LB_SHIFT                                 14
+#define OMAP4_GPMC_DR6_LB_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_LB_SHIFT                                 12
+#define OMAP4_HDMI_DR0_LB_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_LB_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_LB_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_LB_SHIFT                                8
+#define OMAP4_UART1_DR0_LB_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_LB_SHIFT                                6
+#define OMAP4_UART3_DR0_LB_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_LB_SHIFT                                4
+#define OMAP4_UART3_DR1_LB_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_LB_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_LB_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_LB_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_LB_MASK                                (0x3 << 0)
+
+/* CONTROL_SMART2IO_PADCONF_0 */
+#define OMAP4_C2C_DR0_LB_SHIFT                                  31
+#define OMAP4_C2C_DR0_LB_MASK                                   (1 << 31)
+#define OMAP4_DPM_DR1_LB_SHIFT                                  30
+#define OMAP4_DPM_DR1_LB_MASK                                   (1 << 30)
+#define OMAP4_DPM_DR2_LB_SHIFT                                  29
+#define OMAP4_DPM_DR2_LB_MASK                                   (1 << 29)
+#define OMAP4_DPM_DR3_LB_SHIFT                                  28
+#define OMAP4_DPM_DR3_LB_MASK                                   (1 << 28)
+#define OMAP4_GPIO_DR0_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR0_LB_MASK                                  (1 << 27)
+#define OMAP4_GPIO_DR1_LB_SHIFT                                 26
+#define OMAP4_GPIO_DR1_LB_MASK                                  (1 << 26)
+#define OMAP4_GPIO_DR10_LB_SHIFT                                25
+#define OMAP4_GPIO_DR10_LB_MASK                                 (1 << 25)
+#define OMAP4_GPIO_DR2_LB_SHIFT                                 24
+#define OMAP4_GPIO_DR2_LB_MASK                                  (1 << 24)
+#define OMAP4_GPMC_DR0_LB_SHIFT                                 23
+#define OMAP4_GPMC_DR0_LB_MASK                                  (1 << 23)
+#define OMAP4_GPMC_DR1_LB_SHIFT                                 22
+#define OMAP4_GPMC_DR1_LB_MASK                                  (1 << 22)
+#define OMAP4_GPMC_DR4_LB_SHIFT                                 21
+#define OMAP4_GPMC_DR4_LB_MASK                                  (1 << 21)
+#define OMAP4_GPMC_DR5_LB_SHIFT                                 20
+#define OMAP4_GPMC_DR5_LB_MASK                                  (1 << 20)
+#define OMAP4_GPMC_DR7_LB_SHIFT                                 19
+#define OMAP4_GPMC_DR7_LB_MASK                                  (1 << 19)
+#define OMAP4_HSI2_DR0_LB_SHIFT                                 18
+#define OMAP4_HSI2_DR0_LB_MASK                                  (1 << 18)
+#define OMAP4_HSI2_DR1_LB_SHIFT                                 17
+#define OMAP4_HSI2_DR1_LB_MASK                                  (1 << 17)
+#define OMAP4_HSI2_DR2_LB_SHIFT                                 16
+#define OMAP4_HSI2_DR2_LB_MASK                                  (1 << 16)
+#define OMAP4_KPD_DR0_LB_SHIFT                                  15
+#define OMAP4_KPD_DR0_LB_MASK                                   (1 << 15)
+#define OMAP4_KPD_DR1_LB_SHIFT                                  14
+#define OMAP4_KPD_DR1_LB_MASK                                   (1 << 14)
+#define OMAP4_PDM_DR0_LB_SHIFT                                  13
+#define OMAP4_PDM_DR0_LB_MASK                                   (1 << 13)
+#define OMAP4_SDMMC2_DR0_LB_SHIFT                               12
+#define OMAP4_SDMMC2_DR0_LB_MASK                                (1 << 12)
+#define OMAP4_SDMMC3_DR0_LB_SHIFT                               11
+#define OMAP4_SDMMC3_DR0_LB_MASK                                (1 << 11)
+#define OMAP4_SDMMC4_DR0_LB_SHIFT                               10
+#define OMAP4_SDMMC4_DR0_LB_MASK                                (1 << 10)
+#define OMAP4_SDMMC4_DR1_LB_SHIFT                               9
+#define OMAP4_SDMMC4_DR1_LB_MASK                                (1 << 9)
+#define OMAP4_SPI3_DR0_LB_SHIFT                                 8
+#define OMAP4_SPI3_DR0_LB_MASK                                  (1 << 8)
+#define OMAP4_SPI3_DR1_LB_SHIFT                                 7
+#define OMAP4_SPI3_DR1_LB_MASK                                  (1 << 7)
+#define OMAP4_UART3_DR2_LB_SHIFT                                6
+#define OMAP4_UART3_DR2_LB_MASK                                 (1 << 6)
+#define OMAP4_UART3_DR3_LB_SHIFT                                5
+#define OMAP4_UART3_DR3_LB_MASK                                 (1 << 5)
+#define OMAP4_UART3_DR4_LB_SHIFT                                4
+#define OMAP4_UART3_DR4_LB_MASK                                 (1 << 4)
+#define OMAP4_UART3_DR5_LB_SHIFT                                3
+#define OMAP4_UART3_DR5_LB_MASK                                 (1 << 3)
+#define OMAP4_USBA0_DR1_LB_SHIFT                                2
+#define OMAP4_USBA0_DR1_LB_MASK                                 (1 << 2)
+#define OMAP4_USBA_DR2_LB_SHIFT                                 1
+#define OMAP4_USBA_DR2_LB_MASK                                  (1 << 1)
+
+/* CONTROL_SMART2IO_PADCONF_1 */
+#define OMAP4_USBB1_DR0_LB_SHIFT                                31
+#define OMAP4_USBB1_DR0_LB_MASK                                 (1 << 31)
+#define OMAP4_USBB2_DR0_LB_SHIFT                                30
+#define OMAP4_USBB2_DR0_LB_MASK                                 (1 << 30)
+#define OMAP4_USBA0_DR0_LB_SHIFT                                29
+#define OMAP4_USBA0_DR0_LB_MASK                                 (1 << 29)
+
+/* CONTROL_SMART3IO_PADCONF_0 */
+#define OMAP4_DMIC_DR0_MB_SHIFT                                 30
+#define OMAP4_DMIC_DR0_MB_MASK                                  (0x3 << 30)
+#define OMAP4_GPIO_DR3_MB_SHIFT                                 28
+#define OMAP4_GPIO_DR3_MB_MASK                                  (0x3 << 28)
+#define OMAP4_GPIO_DR4_MB_SHIFT                                 26
+#define OMAP4_GPIO_DR4_MB_MASK                                  (0x3 << 26)
+#define OMAP4_GPIO_DR5_MB_SHIFT                                 24
+#define OMAP4_GPIO_DR5_MB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR6_MB_SHIFT                                 22
+#define OMAP4_GPIO_DR6_MB_MASK                                  (0x3 << 22)
+#define OMAP4_HSI_DR1_MB_SHIFT                                  20
+#define OMAP4_HSI_DR1_MB_MASK                                   (0x3 << 20)
+#define OMAP4_HSI_DR2_MB_SHIFT                                  18
+#define OMAP4_HSI_DR2_MB_MASK                                   (0x3 << 18)
+#define OMAP4_HSI_DR3_MB_SHIFT                                  16
+#define OMAP4_HSI_DR3_MB_MASK                                   (0x3 << 16)
+#define OMAP4_MCBSP2_DR0_MB_SHIFT                               14
+#define OMAP4_MCBSP2_DR0_MB_MASK                                (0x3 << 14)
+#define OMAP4_MCSPI4_DR0_MB_SHIFT                               12
+#define OMAP4_MCSPI4_DR0_MB_MASK                                (0x3 << 12)
+#define OMAP4_MCSPI4_DR1_MB_SHIFT                               10
+#define OMAP4_MCSPI4_DR1_MB_MASK                                (0x3 << 10)
+#define OMAP4_SDMMC3_DR0_MB_SHIFT                               8
+#define OMAP4_SDMMC3_DR0_MB_MASK                                (0x3 << 8)
+#define OMAP4_SPI2_DR0_MB_SHIFT                                 0
+#define OMAP4_SPI2_DR0_MB_MASK                                  (0x3 << 0)
+
+/* CONTROL_SMART3IO_PADCONF_1 */
+#define OMAP4_SPI2_DR1_MB_SHIFT                                 30
+#define OMAP4_SPI2_DR1_MB_MASK                                  (0x3 << 30)
+#define OMAP4_SPI2_DR2_MB_SHIFT                                 28
+#define OMAP4_SPI2_DR2_MB_MASK                                  (0x3 << 28)
+#define OMAP4_UART2_DR0_MB_SHIFT                                26
+#define OMAP4_UART2_DR0_MB_MASK                                 (0x3 << 26)
+#define OMAP4_UART2_DR1_MB_SHIFT                                24
+#define OMAP4_UART2_DR1_MB_MASK                                 (0x3 << 24)
+#define OMAP4_UART4_DR0_MB_SHIFT                                22
+#define OMAP4_UART4_DR0_MB_MASK                                 (0x3 << 22)
+#define OMAP4_HSI_DR0_MB_SHIFT                                  20
+#define OMAP4_HSI_DR0_MB_MASK                                   (0x3 << 20)
+
+/* CONTROL_SMART3IO_PADCONF_2 */
+#define OMAP4_DMIC_DR0_LB_SHIFT                                 31
+#define OMAP4_DMIC_DR0_LB_MASK                                  (1 << 31)
+#define OMAP4_GPIO_DR3_LB_SHIFT                                 30
+#define OMAP4_GPIO_DR3_LB_MASK                                  (1 << 30)
+#define OMAP4_GPIO_DR4_LB_SHIFT                                 29
+#define OMAP4_GPIO_DR4_LB_MASK                                  (1 << 29)
+#define OMAP4_GPIO_DR5_LB_SHIFT                                 28
+#define OMAP4_GPIO_DR5_LB_MASK                                  (1 << 28)
+#define OMAP4_GPIO_DR6_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR6_LB_MASK                                  (1 << 27)
+#define OMAP4_HSI_DR1_LB_SHIFT                                  26
+#define OMAP4_HSI_DR1_LB_MASK                                   (1 << 26)
+#define OMAP4_HSI_DR2_LB_SHIFT                                  25
+#define OMAP4_HSI_DR2_LB_MASK                                   (1 << 25)
+#define OMAP4_HSI_DR3_LB_SHIFT                                  24
+#define OMAP4_HSI_DR3_LB_MASK                                   (1 << 24)
+#define OMAP4_MCBSP2_DR0_LB_SHIFT                               23
+#define OMAP4_MCBSP2_DR0_LB_MASK                                (1 << 23)
+#define OMAP4_MCSPI4_DR0_LB_SHIFT                               22
+#define OMAP4_MCSPI4_DR0_LB_MASK                                (1 << 22)
+#define OMAP4_MCSPI4_DR1_LB_SHIFT                               21
+#define OMAP4_MCSPI4_DR1_LB_MASK                                (1 << 21)
+#define OMAP4_SLIMBUS2_DR0_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR0_LB_MASK                              (1 << 18)
+#define OMAP4_SPI2_DR0_LB_SHIFT                                 16
+#define OMAP4_SPI2_DR0_LB_MASK                                  (1 << 16)
+#define OMAP4_SPI2_DR1_LB_SHIFT                                 15
+#define OMAP4_SPI2_DR1_LB_MASK                                  (1 << 15)
+#define OMAP4_SPI2_DR2_LB_SHIFT                                 14
+#define OMAP4_SPI2_DR2_LB_MASK                                  (1 << 14)
+#define OMAP4_UART2_DR0_LB_SHIFT                                13
+#define OMAP4_UART2_DR0_LB_MASK                                 (1 << 13)
+#define OMAP4_UART2_DR1_LB_SHIFT                                12
+#define OMAP4_UART2_DR1_LB_MASK                                 (1 << 12)
+#define OMAP4_UART4_DR0_LB_SHIFT                                11
+#define OMAP4_UART4_DR0_LB_MASK                                 (1 << 11)
+#define OMAP4_HSI_DR0_LB_SHIFT                                  10
+#define OMAP4_HSI_DR0_LB_MASK                                   (1 << 10)
+
+/* CONTROL_USBB_HSIC */
+#define OMAP4_USBB2_DR1_SR_SHIFT                                30
+#define OMAP4_USBB2_DR1_SR_MASK                                 (0x3 << 30)
+#define OMAP4_USBB2_DR1_I_SHIFT                                 27
+#define OMAP4_USBB2_DR1_I_MASK                                  (0x7 << 27)
+#define OMAP4_USBB1_DR1_SR_SHIFT                                25
+#define OMAP4_USBB1_DR1_SR_MASK                                 (0x3 << 25)
+#define OMAP4_USBB1_DR1_I_SHIFT                                 22
+#define OMAP4_USBB1_DR1_I_MASK                                  (0x7 << 22)
+#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT                          20
+#define OMAP4_USBB1_HSIC_DATA_WD_MASK                           (0x3 << 20)
+#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT                        18
+#define OMAP4_USBB1_HSIC_STROBE_WD_MASK                         (0x3 << 18)
+#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT                          16
+#define OMAP4_USBB2_HSIC_DATA_WD_MASK                           (0x3 << 16)
+#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT                        14
+#define OMAP4_USBB2_HSIC_STROBE_WD_MASK                         (0x3 << 14)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           13
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 13)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT                  11
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 11)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         10
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 10)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT                8
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 8)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           7
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 7)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT                  5
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 5)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         4
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 4)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT                2
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 2)
+
+/* CONTROL_SLIMBUS */
+#define OMAP4_SLIMBUS1_DR0_MB_SHIFT                             30
+#define OMAP4_SLIMBUS1_DR0_MB_MASK                              (0x3 << 30)
+#define OMAP4_SLIMBUS1_DR1_MB_SHIFT                             28
+#define OMAP4_SLIMBUS1_DR1_MB_MASK                              (0x3 << 28)
+#define OMAP4_SLIMBUS2_DR0_MB_SHIFT                             26
+#define OMAP4_SLIMBUS2_DR0_MB_MASK                              (0x3 << 26)
+#define OMAP4_SLIMBUS2_DR1_MB_SHIFT                             24
+#define OMAP4_SLIMBUS2_DR1_MB_MASK                              (0x3 << 24)
+#define OMAP4_SLIMBUS2_DR2_MB_SHIFT                             22
+#define OMAP4_SLIMBUS2_DR2_MB_MASK                              (0x3 << 22)
+#define OMAP4_SLIMBUS2_DR3_MB_SHIFT                             20
+#define OMAP4_SLIMBUS2_DR3_MB_MASK                              (0x3 << 20)
+#define OMAP4_SLIMBUS1_DR0_LB_SHIFT                             19
+#define OMAP4_SLIMBUS1_DR0_LB_MASK                              (1 << 19)
+#define OMAP4_SLIMBUS2_DR1_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR1_LB_MASK                              (1 << 18)
+
+/* CONTROL_PBIASLITE */
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT                     31
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK                      (1 << 31)
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT                30
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 30)
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT                  29
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK                   (1 << 29)
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT                       28
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK                        (1 << 28)
+#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT                        27
+#define OMAP4_USIM_PBIASLITE_VMODE_MASK                         (1 << 27)
+#define OMAP4_MMC1_PWRDNZ_SHIFT                                 26
+#define OMAP4_MMC1_PWRDNZ_MASK                                  (1 << 26)
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT                     25
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK                      (1 << 25)
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT                24
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 24)
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT                  23
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK                   (1 << 23)
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT                       22
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK                        (1 << 22)
+#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT                        21
+#define OMAP4_MMC1_PBIASLITE_VMODE_MASK                         (1 << 21)
+#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT                          20
+#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK                           (1 << 20)
+
+/* CONTROL_I2C_0 */
+#define OMAP4_I2C4_SDA_GLFENB_SHIFT                             31
+#define OMAP4_I2C4_SDA_GLFENB_MASK                              (1 << 31)
+#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT                          29
+#define OMAP4_I2C4_SDA_LOAD_BITS_MASK                           (0x3 << 29)
+#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT                         28
+#define OMAP4_I2C4_SDA_PULLUPRESX_MASK                          (1 << 28)
+#define OMAP4_I2C3_SDA_GLFENB_SHIFT                             27
+#define OMAP4_I2C3_SDA_GLFENB_MASK                              (1 << 27)
+#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT                          25
+#define OMAP4_I2C3_SDA_LOAD_BITS_MASK                           (0x3 << 25)
+#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT                         24
+#define OMAP4_I2C3_SDA_PULLUPRESX_MASK                          (1 << 24)
+#define OMAP4_I2C2_SDA_GLFENB_SHIFT                             23
+#define OMAP4_I2C2_SDA_GLFENB_MASK                              (1 << 23)
+#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT                          21
+#define OMAP4_I2C2_SDA_LOAD_BITS_MASK                           (0x3 << 21)
+#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT                         20
+#define OMAP4_I2C2_SDA_PULLUPRESX_MASK                          (1 << 20)
+#define OMAP4_I2C1_SDA_GLFENB_SHIFT                             19
+#define OMAP4_I2C1_SDA_GLFENB_MASK                              (1 << 19)
+#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT                          17
+#define OMAP4_I2C1_SDA_LOAD_BITS_MASK                           (0x3 << 17)
+#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT                         16
+#define OMAP4_I2C1_SDA_PULLUPRESX_MASK                          (1 << 16)
+#define OMAP4_I2C4_SCL_GLFENB_SHIFT                             15
+#define OMAP4_I2C4_SCL_GLFENB_MASK                              (1 << 15)
+#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT                          13
+#define OMAP4_I2C4_SCL_LOAD_BITS_MASK                           (0x3 << 13)
+#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT                         12
+#define OMAP4_I2C4_SCL_PULLUPRESX_MASK                          (1 << 12)
+#define OMAP4_I2C3_SCL_GLFENB_SHIFT                             11
+#define OMAP4_I2C3_SCL_GLFENB_MASK                              (1 << 11)
+#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT                          9
+#define OMAP4_I2C3_SCL_LOAD_BITS_MASK                           (0x3 << 9)
+#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT                         8
+#define OMAP4_I2C3_SCL_PULLUPRESX_MASK                          (1 << 8)
+#define OMAP4_I2C2_SCL_GLFENB_SHIFT                             7
+#define OMAP4_I2C2_SCL_GLFENB_MASK                              (1 << 7)
+#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT                          5
+#define OMAP4_I2C2_SCL_LOAD_BITS_MASK                           (0x3 << 5)
+#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT                         4
+#define OMAP4_I2C2_SCL_PULLUPRESX_MASK                          (1 << 4)
+#define OMAP4_I2C1_SCL_GLFENB_SHIFT                             3
+#define OMAP4_I2C1_SCL_GLFENB_MASK                              (1 << 3)
+#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT                          1
+#define OMAP4_I2C1_SCL_LOAD_BITS_MASK                           (0x3 << 1)
+#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT                         0
+#define OMAP4_I2C1_SCL_PULLUPRESX_MASK                          (1 << 0)
+
+/* CONTROL_CAMERA_RX */
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT                   31
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK                    (1 << 31)
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT                   29
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK                    (0x3 << 29)
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT                   24
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK                    (0x1f << 24)
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT                     22
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK                      (0x3 << 22)
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT                    21
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK                     (1 << 21)
+#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT                      19
+#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK                       (0x3 << 19)
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT                    18
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK                     (1 << 18)
+#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT                      16
+#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK                       (0x3 << 16)
+
+/* CONTROL_AVDAC */
+#define OMAP4_AVDAC_ACEN_SHIFT                                  31
+#define OMAP4_AVDAC_ACEN_MASK                                   (1 << 31)
+#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT                           30
+#define OMAP4_AVDAC_TVOUTBYPASS_MASK                            (1 << 30)
+#define OMAP4_AVDAC_INPUTINV_SHIFT                              29
+#define OMAP4_AVDAC_INPUTINV_MASK                               (1 << 29)
+#define OMAP4_AVDAC_CTL_SHIFT                                   13
+#define OMAP4_AVDAC_CTL_MASK                                    (0xffff << 13)
+#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT                            12
+#define OMAP4_AVDAC_CTL_WR_ACK_MASK                             (1 << 12)
+
+/* CONTROL_HDMI_TX_PHY */
+#define OMAP4_HDMITXPHY_PADORDER_SHIFT                          31
+#define OMAP4_HDMITXPHY_PADORDER_MASK                           (1 << 31)
+#define OMAP4_HDMITXPHY_TXVALID_SHIFT                           30
+#define OMAP4_HDMITXPHY_TXVALID_MASK                            (1 << 30)
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT                       29
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK                        (1 << 29)
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT                      28
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK                       (1 << 28)
+
+/* CONTROL_MMC2 */
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT                       31
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK                        (1 << 31)
+
+/* CONTROL_DSIPHY */
+#define OMAP4_DSI2_LANEENABLE_SHIFT                             29
+#define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
+#define OMAP4_DSI1_LANEENABLE_SHIFT                             24
+#define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
+#define OMAP4_DSI1_PIPD_SHIFT                                   19
+#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                                   14
+#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
+
+/* CONTROL_MCBSPLP */
+#define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
+#define OMAP4_ALBCTRLRX_FSX_MASK                                (1 << 31)
+#define OMAP4_ALBCTRLRX_CLKX_SHIFT                              30
+#define OMAP4_ALBCTRLRX_CLKX_MASK                               (1 << 30)
+#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT                            29
+#define OMAP4_ABE_MCBSP1_DR_EN_MASK                             (1 << 29)
+
+/* CONTROL_USB2PHYCORE */
+#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT                       31
+#define OMAP4_USB2PHY_AUTORESUME_EN_MASK                        (1 << 31)
+#define OMAP4_USB2PHY_DISCHGDET_SHIFT                           30
+#define OMAP4_USB2PHY_DISCHGDET_MASK                            (1 << 30)
+#define OMAP4_USB2PHY_GPIOMODE_SHIFT                            29
+#define OMAP4_USB2PHY_GPIOMODE_MASK                             (1 << 29)
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT                     28
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK                      (1 << 28)
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT                    27
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK                     (1 << 27)
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT                    26
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK                     (1 << 26)
+#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT                         25
+#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK                          (1 << 25)
+#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT                        24
+#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK                         (1 << 24)
+#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT                      21
+#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK                       (0x7 << 21)
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT                     20
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK                      (1 << 20)
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT                     19
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK                      (1 << 19)
+#define OMAP4_USB2PHY_DATADET_SHIFT                             18
+#define OMAP4_USB2PHY_DATADET_MASK                              (1 << 18)
+#define OMAP4_USB2PHY_SINKONDP_SHIFT                            17
+#define OMAP4_USB2PHY_SINKONDP_MASK                             (1 << 17)
+#define OMAP4_USB2PHY_SRCONDM_SHIFT                             16
+#define OMAP4_USB2PHY_SRCONDM_MASK                              (1 << 16)
+#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT                       15
+#define OMAP4_USB2PHY_RESTARTCHGDET_MASK                        (1 << 15)
+#define OMAP4_USB2PHY_CHGDETDONE_SHIFT                          14
+#define OMAP4_USB2PHY_CHGDETDONE_MASK                           (1 << 14)
+#define OMAP4_USB2PHY_CHGDETECTED_SHIFT                         13
+#define OMAP4_USB2PHY_CHGDETECTED_MASK                          (1 << 13)
+#define OMAP4_USB2PHY_MCPCPUEN_SHIFT                            12
+#define OMAP4_USB2PHY_MCPCPUEN_MASK                             (1 << 12)
+#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT                          11
+#define OMAP4_USB2PHY_MCPCMODEEN_MASK                           (1 << 11)
+#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT                       10
+#define OMAP4_USB2PHY_RESETDONEMCLK_MASK                        (1 << 10)
+#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT                       9
+#define OMAP4_USB2PHY_UTMIRESETDONE_MASK                        (1 << 9)
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT                    8
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK                     (1 << 8)
+#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT                       7
+#define OMAP4_USB2PHY_DATAPOLARITYN_MASK                        (1 << 7)
+#define OMAP4_USBDPLL_FREQLOCK_SHIFT                            6
+#define OMAP4_USBDPLL_FREQLOCK_MASK                             (1 << 6)
+#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT                       5
+#define OMAP4_USB2PHY_RESETDONETCLK_MASK                        (1 << 5)
+
+/* CONTROL_I2C_1 */
+#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT                         31
+#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK                          (1 << 31)
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT                      29
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK                       (0x3 << 29)
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT                     28
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK                      (1 << 28)
+#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT                         27
+#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK                          (1 << 27)
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT                      25
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK                       (0x3 << 25)
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT                     24
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK                      (1 << 24)
+#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT                         23
+#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK                          (1 << 23)
+#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT                          22
+#define OMAP4_HDMI_DDC_SDA_NMODE_MASK                           (1 << 22)
+#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT                         21
+#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK                          (1 << 21)
+#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT                          20
+#define OMAP4_HDMI_DDC_SCL_NMODE_MASK                           (1 << 20)
+
+/* CONTROL_MMC1 */
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT                      31
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK                       (1 << 31)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT                      30
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK                       (1 << 30)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT                      29
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK                       (1 << 29)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT                      28
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK                       (1 << 28)
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT                        27
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK                         (1 << 27)
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT                        26
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK                         (1 << 26)
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT                        25
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK                         (1 << 25)
+#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT                         24
+#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK                          (1 << 24)
+#define OMAP4_USB_FD_CDEN_SHIFT                                 23
+#define OMAP4_USB_FD_CDEN_MASK                                  (1 << 23)
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT                        22
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK                         (1 << 22)
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT                        21
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK                         (1 << 21)
+
+/* CONTROL_HSI */
+#define OMAP4_HSI1_CALLOOP_SEL_SHIFT                            31
+#define OMAP4_HSI1_CALLOOP_SEL_MASK                             (1 << 31)
+#define OMAP4_HSI1_CALMUX_SEL_SHIFT                             30
+#define OMAP4_HSI1_CALMUX_SEL_MASK                              (1 << 30)
+#define OMAP4_HSI2_CALLOOP_SEL_SHIFT                            29
+#define OMAP4_HSI2_CALLOOP_SEL_MASK                             (1 << 29)
+#define OMAP4_HSI2_CALMUX_SEL_SHIFT                             28
+#define OMAP4_HSI2_CALMUX_SEL_MASK                              (1 << 28)
+
+/* CONTROL_USB */
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT           31
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK            (1 << 31)
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT           30
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK            (1 << 30)
+
+/* CONTROL_HDQ */
+#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT                              31
+#define OMAP4_HDQ_SIO_PWRDNZ_MASK                               (1 << 31)
+
+/* CONTROL_LPDDR2IO1_0 */
+#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR1_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO1_1 */
+#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR5_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO1_2 */
+#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO1_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO1_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO1_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO1_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO1_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO1_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR9_WD_MASK                             (0x3 << 9)
+
+/* CONTROL_LPDDR2IO1_3 */
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK                         (1 << 12)
+
+/* CONTROL_LPDDR2IO2_0 */
+#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR1_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO2_1 */
+#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR5_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO2_2 */
+#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO2_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO2_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO2_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO2_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO2_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO2_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR9_WD_MASK                             (0x3 << 9)
+
+/* CONTROL_LPDDR2IO2_3 */
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK                         (1 << 12)
+
+/* CONTROL_BUS_HOLD */
+#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT                            31
+#define OMAP4_ABE_DMIC_DIN3_EN_MASK                             (1 << 31)
+#define OMAP4_MCSPI1_CS3_EN_SHIFT                               30
+#define OMAP4_MCSPI1_CS3_EN_MASK                                (1 << 30)
+
+/* CONTROL_C2C */
+#define OMAP4_MIRROR_MODE_EN_SHIFT                              31
+#define OMAP4_MIRROR_MODE_EN_MASK                               (1 << 31)
+#define OMAP4_C2C_SPARE_SHIFT                                   24
+#define OMAP4_C2C_SPARE_MASK                                    (0x7f << 24)
+
+/* CORE_CONTROL_SPARE_RW */
+#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_CORE_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+
+/* CORE_CONTROL_SPARE_R */
+#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_CORE_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+
+/* CORE_CONTROL_SPARE_R_C0 */
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+
+/* CONTROL_EFUSE_1 */
+#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT                            24
+#define OMAP4_AVDAC_TRIM_BYTE3_MASK                             (0x7f << 24)
+#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT                            16
+#define OMAP4_AVDAC_TRIM_BYTE2_MASK                             (0xff << 16)
+#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT                            8
+#define OMAP4_AVDAC_TRIM_BYTE1_MASK                             (0xff << 8)
+#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT                            0
+#define OMAP4_AVDAC_TRIM_BYTE0_MASK                             (0xff << 0)
+
+/* CONTROL_EFUSE_2 */
+#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT                         31
+#define OMAP4_EFUSE_SMART2TEST_P0_MASK                          (1 << 31)
+#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT                         30
+#define OMAP4_EFUSE_SMART2TEST_P1_MASK                          (1 << 30)
+#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT                         29
+#define OMAP4_EFUSE_SMART2TEST_P2_MASK                          (1 << 29)
+#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT                         28
+#define OMAP4_EFUSE_SMART2TEST_P3_MASK                          (1 << 28)
+#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT                         27
+#define OMAP4_EFUSE_SMART2TEST_N0_MASK                          (1 << 27)
+#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT                         26
+#define OMAP4_EFUSE_SMART2TEST_N1_MASK                          (1 << 26)
+#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT                         25
+#define OMAP4_EFUSE_SMART2TEST_N2_MASK                          (1 << 25)
+#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT                         24
+#define OMAP4_EFUSE_SMART2TEST_N3_MASK                          (1 << 24)
+#define OMAP4_LPDDR2_PTV_N1_SHIFT                               23
+#define OMAP4_LPDDR2_PTV_N1_MASK                                (1 << 23)
+#define OMAP4_LPDDR2_PTV_N2_SHIFT                               22
+#define OMAP4_LPDDR2_PTV_N2_MASK                                (1 << 22)
+#define OMAP4_LPDDR2_PTV_N3_SHIFT                               21
+#define OMAP4_LPDDR2_PTV_N3_MASK                                (1 << 21)
+#define OMAP4_LPDDR2_PTV_N4_SHIFT                               20
+#define OMAP4_LPDDR2_PTV_N4_MASK                                (1 << 20)
+#define OMAP4_LPDDR2_PTV_N5_SHIFT                               19
+#define OMAP4_LPDDR2_PTV_N5_MASK                                (1 << 19)
+#define OMAP4_LPDDR2_PTV_P1_SHIFT                               18
+#define OMAP4_LPDDR2_PTV_P1_MASK                                (1 << 18)
+#define OMAP4_LPDDR2_PTV_P2_SHIFT                               17
+#define OMAP4_LPDDR2_PTV_P2_MASK                                (1 << 17)
+#define OMAP4_LPDDR2_PTV_P3_SHIFT                               16
+#define OMAP4_LPDDR2_PTV_P3_MASK                                (1 << 16)
+#define OMAP4_LPDDR2_PTV_P4_SHIFT                               15
+#define OMAP4_LPDDR2_PTV_P4_MASK                                (1 << 15)
+#define OMAP4_LPDDR2_PTV_P5_SHIFT                               14
+#define OMAP4_LPDDR2_PTV_P5_MASK                                (1 << 14)
+
+/* CONTROL_EFUSE_3 */
+#define OMAP4_STD_FUSE_SPARE_1_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_1_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_2_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_2_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_3_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_3_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_4_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_4_MASK                             (0xff << 0)
+
+/* CONTROL_EFUSE_4 */
+#define OMAP4_STD_FUSE_SPARE_5_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_5_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_6_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_6_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_7_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_7_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_8_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_8_MASK                             (0xff << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
new file mode 100644
index 00000000000..17c9b37042c
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
@@ -0,0 +1,236 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP                                      0x4a31e000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION                          0x0000
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO                            0x0004
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG                         0x0010
+#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0                0x007c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1       0x05a4
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE                 0x05a8
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR              0x05ac
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO                       0x0600
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2                        0x0604
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG                         0x0608
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS                          0x060c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW                0x0614
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R                 0x0618
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0              0x061c
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT          22
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK           (1 << 22)
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT             19
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK              (1 << 19)
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT    16
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK     (1 << 16)
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT            15
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK             (1 << 15)
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT                13
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK                 (1 << 13)
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT          12
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 12)
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT         7
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK          (1 << 7)
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT                 6
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK                  (1 << 6)
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT                 5
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK                  (1 << 5)
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT            4
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK             (1 << 4)
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT                 3
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK                  (1 << 3)
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT                1
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK                 (1 << 1)
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT                 0
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK                  (1 << 0)
+
+/* CONTROL_SMART1NOPMIO_PADCONF_0 */
+#define OMAP4_FREF_DR0_SC_SHIFT                                 30
+#define OMAP4_FREF_DR0_SC_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_SC_SHIFT                                 28
+#define OMAP4_FREF_DR1_SC_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_SC_SHIFT                                 26
+#define OMAP4_FREF_DR4_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_SC_SHIFT                                 24
+#define OMAP4_FREF_DR5_SC_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_SC_SHIFT                                 22
+#define OMAP4_FREF_DR6_SC_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_SC_SHIFT                                 20
+#define OMAP4_FREF_DR7_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_SC_SHIFT                                 18
+#define OMAP4_GPIO_DR7_SC_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_SC_SHIFT                                  14
+#define OMAP4_DPM_DR0_SC_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_SC_SHIFT                                  12
+#define OMAP4_SIM_DR0_SC_MASK                                   (0x3 << 12)
+
+/* CONTROL_SMART1NOPMIO_PADCONF_1 */
+#define OMAP4_FREF_DR0_LB_SHIFT                                 30
+#define OMAP4_FREF_DR0_LB_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_LB_SHIFT                                 28
+#define OMAP4_FREF_DR1_LB_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_LB_SHIFT                                 26
+#define OMAP4_FREF_DR4_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_LB_SHIFT                                 24
+#define OMAP4_FREF_DR5_LB_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_LB_SHIFT                                 22
+#define OMAP4_FREF_DR6_LB_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_LB_SHIFT                                 20
+#define OMAP4_FREF_DR7_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_LB_SHIFT                                 18
+#define OMAP4_GPIO_DR7_LB_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_LB_SHIFT                                  14
+#define OMAP4_DPM_DR0_LB_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_LB_SHIFT                                  12
+#define OMAP4_SIM_DR0_LB_MASK                                   (0x3 << 12)
+
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_FREF_SHIFT                                31
+#define OMAP4_VDDS_DV_FREF_MASK                                 (1 << 31)
+#define OMAP4_VDDS_DV_BANK2_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK2_MASK                                (1 << 30)
+
+/* CONTROL_XTAL_OSCILLATOR */
+#define OMAP4_OSCILLATOR_BOOST_SHIFT                            31
+#define OMAP4_OSCILLATOR_BOOST_MASK                             (1 << 31)
+#define OMAP4_OSCILLATOR_OS_OUT_SHIFT                           30
+#define OMAP4_OSCILLATOR_OS_OUT_MASK                            (1 << 30)
+
+/* CONTROL_USIMIO */
+#define OMAP4_PAD_USIM_CLK_LOW_SHIFT                            31
+#define OMAP4_PAD_USIM_CLK_LOW_MASK                             (1 << 31)
+#define OMAP4_PAD_USIM_RST_LOW_SHIFT                            29
+#define OMAP4_PAD_USIM_RST_LOW_MASK                             (1 << 29)
+#define OMAP4_USIM_PWRDNZ_SHIFT                                 28
+#define OMAP4_USIM_PWRDNZ_MASK                                  (1 << 28)
+
+/* CONTROL_I2C_2 */
+#define OMAP4_SR_SDA_GLFENB_SHIFT                               31
+#define OMAP4_SR_SDA_GLFENB_MASK                                (1 << 31)
+#define OMAP4_SR_SDA_LOAD_BITS_SHIFT                            29
+#define OMAP4_SR_SDA_LOAD_BITS_MASK                             (0x3 << 29)
+#define OMAP4_SR_SDA_PULLUPRESX_SHIFT                           28
+#define OMAP4_SR_SDA_PULLUPRESX_MASK                            (1 << 28)
+#define OMAP4_SR_SCL_GLFENB_SHIFT                               27
+#define OMAP4_SR_SCL_GLFENB_MASK                                (1 << 27)
+#define OMAP4_SR_SCL_LOAD_BITS_SHIFT                            25
+#define OMAP4_SR_SCL_LOAD_BITS_MASK                             (0x3 << 25)
+#define OMAP4_SR_SCL_PULLUPRESX_SHIFT                           24
+#define OMAP4_SR_SCL_PULLUPRESX_MASK                            (1 << 24)
+
+/* CONTROL_JTAG */
+#define OMAP4_JTAG_NTRST_EN_SHIFT                               31
+#define OMAP4_JTAG_NTRST_EN_MASK                                (1 << 31)
+#define OMAP4_JTAG_TCK_EN_SHIFT                                 30
+#define OMAP4_JTAG_TCK_EN_MASK                                  (1 << 30)
+#define OMAP4_JTAG_RTCK_EN_SHIFT                                29
+#define OMAP4_JTAG_RTCK_EN_MASK                                 (1 << 29)
+#define OMAP4_JTAG_TDI_EN_SHIFT                                 28
+#define OMAP4_JTAG_TDI_EN_MASK                                  (1 << 28)
+#define OMAP4_JTAG_TDO_EN_SHIFT                                 27
+#define OMAP4_JTAG_TDO_EN_MASK                                  (1 << 27)
+
+/* CONTROL_SYS */
+#define OMAP4_SYS_NRESWARM_PIPU_SHIFT                           31
+#define OMAP4_SYS_NRESWARM_PIPU_MASK                            (1 << 31)
+
+/* WKUP_CONTROL_SPARE_RW */
+#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+
+/* WKUP_CONTROL_SPARE_R */
+#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_WKUP_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+
+/* WKUP_CONTROL_SPARE_R_C0 */
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
new file mode 100644
index 00000000000..a0af9baec3f
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
@@ -0,0 +1,92 @@
+/*
+ * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_WKUP                          0x4a30c000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION              0x0000
+#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO                0x0004
+#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG             0x0010
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0     0x0460
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1     0x0464
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2     0x0468
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3     0x046c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4     0x0470
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5     0x0474
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6     0x0478
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7     0x047c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8     0x0480
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9     0x0484
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10    0x0488
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11    0x048c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12    0x0490
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13    0x0494
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14    0x0498
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15    0x049c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16    0x04a0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17    0x04a4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18    0x04a8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19    0x04ac
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20    0x04b0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21    0x04b4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22    0x04b8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23    0x04bc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24    0x04c0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25    0x04c4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26    0x04c8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27    0x04cc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28    0x04d0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29    0x04d4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30    0x04d8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31    0x04dc
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT               30
+#define OMAP4_IP_REV_SCHEME_MASK                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                 16
+#define OMAP4_IP_REV_FUNC_MASK                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                  11
+#define OMAP4_IP_REV_RTL_MASK                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                8
+#define OMAP4_IP_REV_MAJOR_MASK                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT               6
+#define OMAP4_IP_REV_CUSTOM_MASK                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                0
+#define OMAP4_IP_REV_MINOR_MASK                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                   0
+#define OMAP4_IP_HWINFO_MASK                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK        (0x3 << 2)
+
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_WKUP_MODE_SHIFT                   0
+#define OMAP4_WKUP_MODE_MASK                            (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 09331bbbda5..6a4d4136002 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -31,95 +31,94 @@ omap_uart_lsr:	.word	0
                  * the desired UART phys and virt addresses temporarily into
                  * the omap_uart_phys and omap_uart_virt above.
                  */
-                .macro  addruart, rx, tmp
+                .macro  addruart, rp, rv
 
                 /* Use omap_uart_phys/virt if already configured */
-10:             mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =__virt_to_phys(omap_uart_phys)    @ physical base address
-                ldrne   \rx, =omap_uart_virt    @ virtual base address
-                ldr     \rx, [\rx, #0]
-                cmp     \rx, #0                 @ is port configured?
+10:             mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =__virt_to_phys(omap_uart_phys)    @ MMU not enabled
+                ldrne   \rp, =omap_uart_phys    @ MMU enabled
+                add     \rv, \rp, #4            @ omap_uart_virt
+                ldr     \rp, [\rp, #0]
+                ldr     \rv, [\rv, #0]
+                cmp     \rp, #0                 @ is port configured?
+                cmpne   \rv, #0
                 bne     99f                     @ already configured
 
                 /* Check the debug UART configuration set in uncompress.h */
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =OMAP_UART_INFO
-                ldrne   \rx, =__phys_to_virt(OMAP_UART_INFO)
-                ldr     \rx, [\rx, #0]
+                mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                ldreq   \rp, =OMAP_UART_INFO    @ MMU not enabled
+                ldrne   \rp, =__phys_to_virt(OMAP_UART_INFO)    @ MMU enabled
+                ldr     \rp, [\rp, #0]
 
                 /* Select the UART to use based on the UART1 scratchpad value */
-                cmp     \rx, #0                 @ no port configured?
+                cmp     \rp, #0                 @ no port configured?
                 beq     21f                     @ if none, try to use UART1
-                cmp     \rx, #OMAP2UART1        @ OMAP2/3/4UART1
+                cmp     \rp, #OMAP2UART1        @ OMAP2/3/4UART1
                 beq     21f                     @ configure OMAP2/3/4UART1
-                cmp     \rx, #OMAP2UART2        @ OMAP2/3/4UART2
+                cmp     \rp, #OMAP2UART2        @ OMAP2/3/4UART2
                 beq     22f                     @ configure OMAP2/3/4UART2
-                cmp     \rx, #OMAP2UART3        @ only on 24xx
+                cmp     \rp, #OMAP2UART3        @ only on 24xx
                 beq     23f                     @ configure OMAP2UART3
-                cmp     \rx, #OMAP3UART3        @ only on 34xx
+                cmp     \rp, #OMAP3UART3        @ only on 34xx
                 beq     33f                     @ configure OMAP3UART3
-                cmp     \rx, #OMAP4UART3        @ only on 44xx
+                cmp     \rp, #OMAP4UART3        @ only on 44xx
                 beq     43f                     @ configure OMAP4UART3
-                cmp     \rx, #OMAP3UART4        @ only on 36xx
+                cmp     \rp, #OMAP3UART4        @ only on 36xx
                 beq     34f                     @ configure OMAP3UART4
-                cmp     \rx, #OMAP4UART4        @ only on 44xx
+                cmp     \rp, #OMAP4UART4        @ only on 44xx
                 beq     44f                     @ configure OMAP4UART4
-                cmp     \rx, #ZOOM_UART         @ only on zoom2/3
+                cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                 beq     95f                     @ configure ZOOM_UART
 
                 /* Configure the UART offset from the phys/virt base */
-21:             mov     \rx, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
+21:             mov     \rp, #UART_OFFSET(OMAP2_UART1_BASE)     @ omap2/3/4
                 b       98f
-22:             mov     \rx, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
+22:             mov     \rp, #UART_OFFSET(OMAP2_UART2_BASE)     @ omap2/3/4
                 b       98f
-23:             mov     \rx, #UART_OFFSET(OMAP2_UART3_BASE)
+23:             mov     \rp, #UART_OFFSET(OMAP2_UART3_BASE)
                 b       98f
-33:             mov     \rx, #UART_OFFSET(OMAP3_UART1_BASE)
-                add     \rx, \rx, #0x00fb0000
-                add     \rx, \rx, #0x00006000           @ OMAP3_UART3_BASE
+33:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+                add     \rp, \rp, #0x00fb0000
+                add     \rp, \rp, #0x00006000           @ OMAP3_UART3_BASE
                 b       98f
-34:             mov     \rx, #UART_OFFSET(OMAP3_UART1_BASE)
-                add     \rx, \rx, #0x00fb0000
-                add     \rx, \rx, #0x00028000           @ OMAP3_UART4_BASE
+34:             mov     \rp, #UART_OFFSET(OMAP3_UART1_BASE)
+                add     \rp, \rp, #0x00fb0000
+                add     \rp, \rp, #0x00028000           @ OMAP3_UART4_BASE
                 b       98f
-43:             mov     \rx, #UART_OFFSET(OMAP4_UART3_BASE)
+43:             mov     \rp, #UART_OFFSET(OMAP4_UART3_BASE)
                 b       98f
-44:             mov     \rx, #UART_OFFSET(OMAP4_UART4_BASE)
+44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                 b       98f
-95:             ldr     \rx, =ZOOM_UART_BASE
-                mrc     p15, 0, \tmp, c1, c0
-                tst     \tmp, #1                @ MMU enabled?
-                ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
-                ldrne   \tmp, =omap_uart_phys
-                str     \rx, [\tmp, #0]
-                ldr     \rx, =ZOOM_UART_VIRT
-                ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
-                ldrne   \tmp, =omap_uart_virt
-                str     \rx, [\tmp, #0]
-                mov     \rx, #(UART_LSR << ZOOM_PORT_SHIFT)
-                ldreq   \tmp, =__virt_to_phys(omap_uart_lsr)
-                ldrne   \tmp, =omap_uart_lsr
-                str     \rx, [\tmp, #0]
+95:             ldr     \rp, =ZOOM_UART_BASE
+                mrc     p15, 0, \rv, c1, c0
+                tst     \rv, #1                 @ MMU enabled?
+                ldreq   \rv, =__virt_to_phys(omap_uart_phys)    @ MMU not enabled
+                ldrne   \rv, =omap_uart_phys    @ MMU enabled
+                str     \rp, [\rv, #0]
+                ldr     \rp, =ZOOM_UART_VIRT
+                add     \rv, \rv, #4            @ omap_uart_virt
+                str     \rp, [\rv, #0]
+                mov     \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
+                add     \rv, \rv, #4            @ omap_uart_lsr
+                str     \rp, [\rv, #0]
                 b       10b
 
                 /* Store both phys and virt address for the uart */
-98:             add     \rx, \rx, #0x48000000   @ phys base
-                mrc     p15, 0, \tmp, c1, c0
-                tst     \tmp, #1                @ MMU enabled?
-                ldreq   \tmp, =__virt_to_phys(omap_uart_phys)
-                ldrne   \tmp, =omap_uart_phys
-                str     \rx, [\tmp, #0]
-                sub     \rx, \rx, #0x48000000   @ phys base
-                add     \rx, \rx, #0xfa000000   @ virt base
-                ldreq   \tmp, =__virt_to_phys(omap_uart_virt)
-                ldrne   \tmp, =omap_uart_virt
-                str     \rx, [\tmp, #0]
-                mov     \rx, #(UART_LSR << OMAP_PORT_SHIFT)
-                ldreq   \tmp, =__virt_to_phys(omap_uart_lsr)
-                ldrne   \tmp, =omap_uart_lsr
-                str     \rx, [\tmp, #0]
+98:             add     \rp, \rp, #0x48000000   @ phys base
+                mrc     p15, 0, \rv, c1, c0
+                tst     \rv, #1                 @ MMU enabled?
+                ldreq   \rv, =__virt_to_phys(omap_uart_phys)    @ MMU not enabled
+                ldrne   \rv, =omap_uart_phys    @ MMU enabled
+                str     \rp, [\rv, #0]
+                sub     \rp, \rp, #0x48000000   @ phys base
+                add     \rp, \rp, #0xfa000000   @ virt base
+                add     \rv, \rv, #4            @ omap_uart_virt
+                str     \rp, [\rv, #0]
+                mov     \rp, #(UART_LSR << OMAP_PORT_SHIFT)
+                add     \rv, \rv, #4            @ omap_uart_lsr
+                str     \rp, [\rv, #0]
 
                 b       10b
 99:
@@ -131,9 +130,9 @@ omap_uart_lsr:	.word	0
 
                 .macro  busyuart,rd,rx
 1001:           mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1         @ MMU enabled?
-                ldreq   \rd, =__virt_to_phys(omap_uart_lsr)
-                ldrne   \rd, =omap_uart_lsr
+                tst     \rd, #1                 @ MMU enabled?
+                ldreq   \rd, =__virt_to_phys(omap_uart_lsr)     @ MMU not enabled
+                ldrne   \rd, =omap_uart_lsr     @ MMU enabled
                 ldr     \rd, [\rd, #0]
                 ldrb    \rd, [\rx, \rd]
                 and     \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
index 9ce9b6e8ad2..4da31e997ef 100644
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x38000000)
+#define VMALLOC_END       0xf8000000
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b9ea70bce56..40562ddd3ee 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -36,6 +36,7 @@
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
+#include "io.h"
 
 #include <plat/omap-pm.h>
 #include <plat/powerdomain.h>
@@ -323,6 +324,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                 omap2430_hwmod_init();
         else if (cpu_is_omap34xx())
                 omap3xxx_hwmod_init();
+        else if (cpu_is_omap44xx())
+                omap44xx_hwmod_init();
+
         /* The OPP tables have to be registered before a clk init */
         omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
 
@@ -342,9 +346,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 #ifndef CONFIG_PM_RUNTIME
         skip_setup_idle = 1;
 #endif
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())   /* FIXME: OMAP4 */
-                omap_hwmod_late_init(skip_setup_idle);
-
+        omap_hwmod_late_init(skip_setup_idle);
         if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                 _omap2_init_reprogram_sdrc();
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
new file mode 100644
index 00000000000..fd230c6cded
--- /dev/null
+++ b/arch/arm/mach-omap2/io.h
@@ -0,0 +1,7 @@
+
+#ifndef __MACH_OMAP2_IO_H__
+#define __MACH_OMAP2_IO_H__
+
+extern int __init omap_sram_init(void);
+
+#endif /*  __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 26aeef560aa..32eeabe9d2a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -47,7 +47,6 @@ static struct omap_irq_bank {
 } __attribute__ ((aligned(4))) irq_banks[] = {
         {
                 /* MPU INTC */
-                .base_reg       = 0,
                 .nr_irqs        = 96,
         },
 };
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 42dbfa46e65..40ddecab93a 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -181,7 +181,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 
         l = mbox_read_reg(p->irqenable);
@@ -192,7 +192,7 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
         l = mbox_read_reg(p->irqdisable);
         l &= ~bit;
@@ -202,7 +202,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 
         mbox_write_reg(bit, p->irqstatus);
@@ -214,7 +214,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
         u32 enable = mbox_read_reg(p->irqenable);
         u32 status = mbox_read_reg(p->irqstatus);
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 467aae24578..f9c9df5b5ff 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -23,29 +23,86 @@
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
 
-#include "mux.h"
+#include "control.h"
 
-static void omap2_mcbsp2_mux_setup(void)
+
+/* McBSP internal signal muxing functions */
+
+void omap2_mcbsp1_mux_clkr_src(u8 mux)
 {
-        omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA);
-        omap_mux_init_gpio(117, OMAP_PULL_ENA);
-        /*
-         * TODO: Need to add MUX settings for OMAP 2430 SDP
-         */
+        u32 v;
+
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        if (mux == CLKR_SRC_CLKR)
+                v &= ~OMAP2_MCBSP1_CLKR_MASK;
+        else if (mux == CLKR_SRC_CLKX)
+                v |= OMAP2_MCBSP1_CLKR_MASK;
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
 
-static void omap2_mcbsp_request(unsigned int id)
+void omap2_mcbsp1_mux_fsr_src(u8 mux)
 {
-        if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
-                omap2_mcbsp2_mux_setup();
+        u32 v;
+
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        if (mux == FSR_SRC_FSR)
+                v &= ~OMAP2_MCBSP1_FSR_MASK;
+        else if (mux == FSR_SRC_FSX)
+                v |= OMAP2_MCBSP1_FSR_MASK;
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
 
-static struct omap_mcbsp_ops omap2_mcbsp_ops = {
-        .request        = omap2_mcbsp_request,
-};
+/* McBSP CLKS source switching function */
+
+int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct clk *fck_src;
+        char *fck_src_name;
+        int r;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
+                return -EINVAL;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
+                fck_src_name = "pad_fck";
+        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
+                fck_src_name = "prcm_fck";
+        else
+                return -EINVAL;
+
+        fck_src = clk_get(mcbsp->dev, fck_src_name);
+        if (IS_ERR_OR_NULL(fck_src)) {
+                pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
+                       fck_src_name);
+                return -EINVAL;
+        }
+
+        clk_disable(mcbsp->fclk);
+
+        r = clk_set_parent(mcbsp->fclk, fck_src);
+        if (IS_ERR_VALUE(r)) {
+                pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
+                       "clks", fck_src_name);
+                clk_put(fck_src);
+                return -EINVAL;
+        }
+
+        clk_enable(mcbsp->fclk);
+
+        clk_put(fck_src);
+
+        return 0;
+}
+EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
+
+
+/* Platform data */
 
 #ifdef CONFIG_ARCH_OMAP2420
 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
@@ -55,7 +112,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP24XX_MCBSP2_BASE,
@@ -63,7 +119,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
 };
 #define OMAP2420_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2420_mcbsp_pdata)
@@ -82,7 +137,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP24XX_MCBSP2_BASE,
@@ -90,7 +144,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP2430_MCBSP3_BASE,
@@ -98,7 +151,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP2430_MCBSP4_BASE,
@@ -106,7 +158,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP2430_MCBSP5_BASE,
@@ -114,7 +165,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
 };
 #define OMAP2430_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2430_mcbsp_pdata)
@@ -133,7 +183,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
         {
@@ -143,7 +192,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x500, /* The FIFO has 1024 + 256 locations */
         },
         {
@@ -153,7 +201,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
         {
@@ -162,7 +209,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
         {
@@ -171,7 +217,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
 };
@@ -189,28 +234,24 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP1,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP2_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP2,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP3_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP3,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP4_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP4,
-                .ops            = &omap2_mcbsp_ops,
         },
 };
 #define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ab403b2ed26..074536ae401 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -23,12 +23,11 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  *
  */
-#include <linux/module.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
 #include <linux/list.h>
+#include <linux/slab.h>
 #include <linux/ctype.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -36,8 +35,7 @@
 
 #include <asm/system.h>
 
-#include <plat/control.h>
-
+#include "control.h"
 #include "mux.h"
 
 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
@@ -87,7 +85,7 @@ static char *omap_mux_options;
 int __init omap_mux_init_gpio(int gpio, int val)
 {
         struct omap_mux_entry *e;
-        struct omap_mux *gpio_mux;
+        struct omap_mux *gpio_mux = NULL;
         u16 old_mode;
         u16 mux_mode;
         int found = 0;
@@ -127,17 +125,16 @@ int __init omap_mux_init_gpio(int gpio, int val)
         return 0;
 }
 
-int __init omap_mux_init_signal(char *muxname, int val)
+int __init omap_mux_init_signal(const char *muxname, int val)
 {
         struct omap_mux_entry *e;
-        char *m0_name = NULL, *mode_name = NULL;
-        int found = 0;
+        const char *mode_name;
+        int found = 0, mode0_len = 0;
 
         mode_name = strchr(muxname, '.');
         if (mode_name) {
-                *mode_name = '\0';
+                mode0_len = strlen(muxname) - strlen(mode_name);
                 mode_name++;
-                m0_name = muxname;
         } else {
                 mode_name = muxname;
         }
@@ -147,9 +144,11 @@ int __init omap_mux_init_signal(char *muxname, int val)
                 char *m0_entry = m->muxnames[0];
                 int i;
 
-                if (m0_name && strcmp(m0_name, m0_entry))
+                /* First check for full name in mode0.muxmode format */
+                if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
                         continue;
 
+                /* Then check for muxmode only */
                 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
                         char *mode_cur = m->muxnames[i];
 
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index a8e040c2c7e..350c04f2738 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -120,7 +120,7 @@ int omap_mux_init_gpio(int gpio, int val);
  * @muxname:            Mux name in mode0_name.signal_name format
  * @val:                Options for the mux register value
  */
-int omap_mux_init_signal(char *muxname, int val);
+int omap_mux_init_signal(const char *muxname, int val);
 
 #else
 
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
index fdb04a7eb8a..414af543445 100644
--- a/arch/arm/mach-omap2/mux2420.c
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -507,7 +507,7 @@ static struct omap_mux __initdata omap2420_muxmodes[] = {
  * Balls for 447-pin POP package
  */
 #ifdef CONFIG_DEBUG_FS
-struct omap_ball __initdata omap2420_pop_ball[] = {
+static struct omap_ball __initdata omap2420_pop_ball[] = {
         _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
         _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
         _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
index 7dcaaa8af32..84d2c5a7ecd 100644
--- a/arch/arm/mach-omap2/mux2430.c
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -586,7 +586,7 @@ static struct omap_mux __initdata omap2430_muxmodes[] = {
  * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
  */
 #ifdef CONFIG_DEBUG_FS
-struct omap_ball __initdata omap2430_pop_ball[] = {
+static struct omap_ball __initdata omap2430_pop_ball[] = {
         _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
         _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
         _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index f64d7eea345..574e54ea3ab 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -931,7 +931,7 @@ struct omap_ball __initdata omap3_cbc_ball[] = {
  * Signals different on CUS package compared to superset
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
-struct omap_mux __initdata omap3_cus_subset[] = {
+static struct omap_mux __initdata omap3_cus_subset[] = {
         _OMAP3_MUXENTRY(CAM_D10, 109,
                 "cam_d10", NULL, NULL, NULL,
                 "gpio_109", NULL, NULL, "safe_mode"),
@@ -1077,7 +1077,7 @@ struct omap_mux __initdata omap3_cus_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined(CONFIG_OMAP_PACKAGE_CUS)
-struct omap_ball __initdata omap3_cus_ball[] = {
+static struct omap_ball __initdata omap3_cus_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
@@ -1269,7 +1269,7 @@ struct omap_ball __initdata omap3_cus_ball[] = {
  * Signals different on CBB package comapared to superset
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
-struct omap_mux __initdata omap3_cbb_subset[] = {
+static struct omap_mux __initdata omap3_cbb_subset[] = {
         _OMAP3_MUXENTRY(CAM_D10, 109,
                 "cam_d10", NULL, NULL, NULL,
                 "gpio_109", NULL, NULL, "safe_mode"),
@@ -1390,7 +1390,7 @@ struct omap_mux __initdata omap3_cbb_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined(CONFIG_OMAP_PACKAGE_CBB)
-struct omap_ball __initdata omap3_cbb_ball[] = {
+static struct omap_ball __initdata omap3_cbb_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
@@ -1600,7 +1600,7 @@ struct omap_ball __initdata omap3_cbb_ball[] = {
  * Signals different on 36XX CBP package comapared to 34XX CBC package
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
-struct omap_mux __initdata omap36xx_cbp_subset[] = {
+static struct omap_mux __initdata omap36xx_cbp_subset[] = {
         _OMAP3_MUXENTRY(CAM_D0, 99,
                 "cam_d0", NULL, "csi2_dx2", NULL,
                 "gpio_99", NULL, NULL, "safe_mode"),
@@ -1818,7 +1818,7 @@ struct omap_mux __initdata omap36xx_cbp_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined (CONFIG_OMAP_PACKAGE_CBP)
-struct omap_ball __initdata omap36xx_cbp_ball[] = {
+static struct omap_ball __initdata omap36xx_cbp_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13dc9794dcc..923f9f5f91c 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -61,10 +61,14 @@ static int __init omap_l2_cache_init(void)
         omap_smc1(0x102, 0x1);
 
         /*
-         * 32KB way size, 16-way associativity,
-         * parity disabled
+         * 16-way associativity, parity disabled
+         * Way size - 32KB (es1.0)
+         * Way size - 64KB (es2.0 +)
          */
-        l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+        else
+                l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cb911d7d1a3..5a30658444d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -13,10 +13,102 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * This code manages "OMAP modules" (on-chip devices) and their
- * integration with Linux device driver and bus code.
- *
- * References:
+ * Introduction
+ * ------------
+ * One way to view an OMAP SoC is as a collection of largely unrelated
+ * IP blocks connected by interconnects.  The IP blocks include
+ * devices such as ARM processors, audio serial interfaces, UARTs,
+ * etc.  Some of these devices, like the DSP, are created by TI;
+ * others, like the SGX, largely originate from external vendors.  In
+ * TI's documentation, on-chip devices are referred to as "OMAP
+ * modules."  Some of these IP blocks are identical across several
+ * OMAP versions.  Others are revised frequently.
+ *
+ * These OMAP modules are tied together by various interconnects.
+ * Most of the address and data flow between modules is via OCP-based
+ * interconnects such as the L3 and L4 buses; but there are other
+ * interconnects that distribute the hardware clock tree, handle idle
+ * and reset signaling, supply power, and connect the modules to
+ * various pads or balls on the OMAP package.
+ *
+ * OMAP hwmod provides a consistent way to describe the on-chip
+ * hardware blocks and their integration into the rest of the chip.
+ * This description can be automatically generated from the TI
+ * hardware database.  OMAP hwmod provides a standard, consistent API
+ * to reset, enable, idle, and disable these hardware blocks.  And
+ * hwmod provides a way for other core code, such as the Linux device
+ * code or the OMAP power management and address space mapping code,
+ * to query the hardware database.
+ *
+ * Using hwmod
+ * -----------
+ * Drivers won't call hwmod functions directly.  That is done by the
+ * omap_device code, and in rare occasions, by custom integration code
+ * in arch/arm/ *omap*.  The omap_device code includes functions to
+ * build a struct platform_device using omap_hwmod data, and that is
+ * currently how hwmod data is communicated to drivers and to the
+ * Linux driver model.  Most drivers will call omap_hwmod functions only
+ * indirectly, via pm_runtime*() functions.
+ *
+ * From a layering perspective, here is where the OMAP hwmod code
+ * fits into the kernel software stack:
+ *
+ *            +-------------------------------+
+ *            |      Device driver code       |
+ *            |      (e.g., drivers/)         |
+ *            +-------------------------------+
+ *            |      Linux driver model       |
+ *            |     (platform_device /        |
+ *            |  platform_driver data/code)   |
+ *            +-------------------------------+
+ *            | OMAP core-driver integration  |
+ *            |(arch/arm/mach-omap2/devices.c)|
+ *            +-------------------------------+
+ *            |      omap_device code         |
+ *            | (../plat-omap/omap_device.c)  |
+ *            +-------------------------------+
+ *   ---->    |    omap_hwmod code/data       |    <-----
+ *            | (../mach-omap2/omap_hwmod*)   |
+ *            +-------------------------------+
+ *            | OMAP clock/PRCM/register fns  |
+ *            | (__raw_{read,write}l, clk*)   |
+ *            +-------------------------------+
+ *
+ * Device drivers should not contain any OMAP-specific code or data in
+ * them.  They should only contain code to operate the IP block that
+ * the driver is responsible for.  This is because these IP blocks can
+ * also appear in other SoCs, either from TI (such as DaVinci) or from
+ * other manufacturers; and drivers should be reusable across other
+ * platforms.
+ *
+ * The OMAP hwmod code also will attempt to reset and idle all on-chip
+ * devices upon boot.  The goal here is for the kernel to be
+ * completely self-reliant and independent from bootloaders.  This is
+ * to ensure a repeatable configuration, both to ensure consistent
+ * runtime behavior, and to make it easier for others to reproduce
+ * bugs.
+ *
+ * OMAP module activity states
+ * ---------------------------
+ * The hwmod code considers modules to be in one of several activity
+ * states.  IP blocks start out in an UNKNOWN state, then once they
+ * are registered via the hwmod code, proceed to the REGISTERED state.
+ * Once their clock names are resolved to clock pointers, the module
+ * enters the CLKS_INITED state; and finally, once the module has been
+ * reset and the integration registers programmed, the INITIALIZED state
+ * is entered.  The hwmod code will then place the module into either
+ * the IDLE state to save power, or in the case of a critical system
+ * module, the ENABLED state.
+ *
+ * OMAP core integration code can then call omap_hwmod*() functions
+ * directly to move the module between the IDLE, ENABLED, and DISABLED
+ * states, as needed.  This is done during both the PM idle loop, and
+ * in the OMAP core integration code's implementation of the PM runtime
+ * functions.
+ *
+ * References
+ * ----------
+ * This is a partial list.
  * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
  * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
  * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
@@ -50,11 +142,13 @@
 #include <plat/powerdomain.h>
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
+#include <plat/prcm.h>
 
 #include "cm.h"
+#include "prm.h"
 
-/* Maximum microseconds to wait for OMAP module to reset */
-#define MAX_MODULE_RESET_WAIT           10000
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
 
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME              "mpu"
@@ -90,7 +184,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
 
         /* XXX ensure module interface clock is up */
 
-        oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
+        oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
 
         if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
                 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
@@ -117,7 +211,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
 
         if (oh->_sysc_cache != v) {
                 oh->_sysc_cache = v;
-                omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs);
+                omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
         }
 }
 
@@ -544,6 +638,36 @@ static int _disable_clocks(struct omap_hwmod *oh)
         return 0;
 }
 
+static void _enable_optional_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        int i;
+
+        pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk) {
+                        pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
+                                 oc->_clk->name);
+                        clk_enable(oc->_clk);
+                }
+}
+
+static void _disable_optional_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        int i;
+
+        pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk) {
+                        pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
+                                 oc->_clk->name);
+                        clk_disable(oc->_clk);
+                }
+}
+
 /**
  * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
  * @oh: struct omap_hwmod *
@@ -622,7 +746,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 }
 
 /**
- * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG
+ * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * If module is marked as SWSUP_SIDLE, force the module out of slave
@@ -630,7 +754,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
  * as SWSUP_MSUSPEND, force the module out of master standby;
  * otherwise, configure it for smart-standby.  No return value.
  */
-static void _sysc_enable(struct omap_hwmod *oh)
+static void _enable_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
@@ -653,14 +777,6 @@ static void _sysc_enable(struct omap_hwmod *oh)
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
-        if (sf & SYSC_HAS_AUTOIDLE) {
-                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
-                        0 : 1;
-                _set_module_autoidle(oh, idlemode, &v);
-        }
-
-        /* XXX OCP ENAWAKEUP bit? */
-
         /*
          * XXX The clock framework should handle this, by
          * calling into this code.  But this must wait until the
@@ -671,10 +787,25 @@ static void _sysc_enable(struct omap_hwmod *oh)
                 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
 
         _write_sysconfig(v, oh);
+
+        /* If slave is in SMARTIDLE, also enable wakeup */
+        if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
+                _enable_wakeup(oh);
+
+        /*
+         * Set the autoidle bit only after setting the smartidle bit
+         * Setting this will not have any impact on the other modules.
+         */
+        if (sf & SYSC_HAS_AUTOIDLE) {
+                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
+                        0 : 1;
+                _set_module_autoidle(oh, idlemode, &v);
+                _write_sysconfig(v, oh);
+        }
 }
 
 /**
- * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG
+ * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * If module is marked as SWSUP_SIDLE, force the module into slave
@@ -682,7 +813,7 @@ static void _sysc_enable(struct omap_hwmod *oh)
  * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
  * configure it for smart-standby.  No return value.
  */
-static void _sysc_idle(struct omap_hwmod *oh)
+static void _idle_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
@@ -709,13 +840,13 @@ static void _sysc_idle(struct omap_hwmod *oh)
 }
 
 /**
- * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG
+ * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * Force the module into slave idle and master suspend. No return
  * value.
  */
-static void _sysc_shutdown(struct omap_hwmod *oh)
+static void _shutdown_sysc(struct omap_hwmod *oh)
 {
         u32 v;
         u8 sf;
@@ -767,10 +898,10 @@ static struct omap_hwmod *_lookup(const char *name)
  * @data: not used; pass NULL
  *
  * Called by omap_hwmod_late_init() (after omap2_clk_init()).
- * Resolves all clock names embedded in the hwmod.  Must be called
- * with omap_hwmod_mutex held.  Returns -EINVAL if the omap_hwmod
- * has not yet been registered or if the clocks have already been
- * initialized, 0 on success, or a non-zero error on failure.
+ * Resolves all clock names embedded in the hwmod.  Returns -EINVAL if
+ * the omap_hwmod has not yet been registered or if the clocks have
+ * already been initialized, 0 on success, or a non-zero error on
+ * failure.
  */
 static int _init_clocks(struct omap_hwmod *oh, void *data)
 {
@@ -834,56 +965,202 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 }
 
 /**
+ * _lookup_hardreset - return the register bit shift for this hwmod/reset line
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line in the context of this hwmod
+ *
+ * Return the bit position of the reset line that match the
+ * input name. Return -ENOENT if not found.
+ */
+static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int i;
+
+        for (i = 0; i < oh->rst_lines_cnt; i++) {
+                const char *rst_line = oh->rst_lines[i].name;
+                if (!strcmp(rst_line, name)) {
+                        u8 shift = oh->rst_lines[i].rst_shift;
+                        pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n",
+                                 oh->name, rst_line, shift);
+
+                        return shift;
+                }
+        }
+
+        return -ENOENT;
+}
+
+/**
+ * _assert_hardreset - assert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to lookup and assert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.
+ */
+static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        u8 shift;
+
+        if (!oh)
+                return -EINVAL;
+
+        shift = _lookup_hardreset(oh, name);
+        if (IS_ERR_VALUE(shift))
+                return shift;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+                                                  shift);
+        else if (cpu_is_omap44xx())
+                return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
+                                                  shift);
+        else
+                return -EINVAL;
+}
+
+/**
+ * _deassert_hardreset - deassert the HW reset line of submodules contained
+ * in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and deassert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.
+ */
+static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        u8 shift;
+        int r;
+
+        if (!oh)
+                return -EINVAL;
+
+        shift = _lookup_hardreset(oh, name);
+        if (IS_ERR_VALUE(shift))
+                return shift;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
+                                                 shift);
+        else if (cpu_is_omap44xx())
+                r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
+                                                 shift);
+        else
+                return -EINVAL;
+
+        if (r == -EBUSY)
+                pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
+
+        return r;
+}
+
+/**
+ * _read_hardreset - read the HW reset line state of submodules
+ * contained in the hwmod module
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and read
+ *
+ * Return the state of the reset line.
+ */
+static int _read_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        u8 shift;
+
+        if (!oh)
+                return -EINVAL;
+
+        shift = _lookup_hardreset(oh, name);
+        if (IS_ERR_VALUE(shift))
+                return shift;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+                                                       shift);
+        } else if (cpu_is_omap44xx()) {
+                return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
+                                                       shift);
+        } else {
+                return -EINVAL;
+        }
+}
+
+/**
  * _reset - reset an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
- * enabled for this to work.  Must be called with omap_hwmod_mutex
- * held.  Returns -EINVAL if the hwmod cannot be reset this way or if
- * the hwmod is in the wrong state, -ETIMEDOUT if the module did not
- * reset in time, or 0 upon success.
+ * enabled for this to work.  Returns -EINVAL if the hwmod cannot be
+ * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ * the module did not reset in time, or 0 upon success.
+ *
+ * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
+ * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead
+ * use the SYSCONFIG softreset bit to provide the status.
+ *
+ * Note that some IP like McBSP does have a reset control but no reset status.
  */
 static int _reset(struct omap_hwmod *oh)
 {
-        u32 r, v;
+        u32 v;
         int c = 0;
+        int ret = 0;
 
         if (!oh->class->sysc ||
-            !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) ||
-            (oh->class->sysc->sysc_flags & SYSS_MISSING))
+            !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
                 return -EINVAL;
 
         /* clocks must be on for this operation */
         if (oh->_state != _HWMOD_STATE_ENABLED) {
-                WARN(1, "omap_hwmod: %s: reset can only be entered from "
-                     "enabled state\n", oh->name);
+                pr_warning("omap_hwmod: %s: reset can only be entered from "
+                           "enabled state\n", oh->name);
                 return -EINVAL;
         }
 
+        /* For some modules, all optionnal clocks need to be enabled as well */
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _enable_optional_clocks(oh);
+
         pr_debug("omap_hwmod: %s: resetting\n", oh->name);
 
         v = oh->_sysc_cache;
-        r = _set_softreset(oh, &v);
-        if (r)
-                return r;
+        ret = _set_softreset(oh, &v);
+        if (ret)
+                goto dis_opt_clks;
         _write_sysconfig(v, oh);
 
-        omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) &
-                           SYSS_RESETDONE_MASK),
-                          MAX_MODULE_RESET_WAIT, c);
-
-        if (c == MAX_MODULE_RESET_WAIT)
-                WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
-                     oh->name, MAX_MODULE_RESET_WAIT);
+        if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
+                omap_test_timeout((omap_hwmod_read(oh,
+                                                    oh->class->sysc->syss_offs)
+                                   & SYSS_RESETDONE_MASK),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+        else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
+                omap_test_timeout(!(omap_hwmod_read(oh,
+                                                     oh->class->sysc->sysc_offs)
+                                   & SYSC_TYPE2_SOFTRESET_MASK),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
+                           oh->name, MAX_MODULE_SOFTRESET_WAIT);
         else
-                pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c);
+                pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
 
         /*
          * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
          * _wait_target_ready() or _reset()
          */
 
-        return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0;
+        ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
+
+dis_opt_clks:
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _disable_optional_clocks(oh);
+
+        return ret;
 }
 
 /**
@@ -891,9 +1168,11 @@ static int _reset(struct omap_hwmod *oh)
  * @oh: struct omap_hwmod *
  *
  * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
- * register target.  Must be called with omap_hwmod_mutex held.
- * Returns -EINVAL if the hwmod is in the wrong state or passes along
- * the return value of _wait_target_ready().
+ * register target.  (This function has a full name --
+ * _omap_hwmod_enable() rather than simply _enable() -- because it is
+ * currently required by the pm34xx.c idle loop.)  Returns -EINVAL if
+ * the hwmod is in the wrong state or passes along the return value of
+ * _wait_target_ready().
  */
 int _omap_hwmod_enable(struct omap_hwmod *oh)
 {
@@ -909,6 +1188,15 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
 
         pr_debug("omap_hwmod: %s: enabling\n", oh->name);
 
+        /*
+         * If an IP contains only one HW reset line, then de-assert it in order
+         * to allow to enable the clocks. Otherwise the PRCM will return
+         * Intransition status, and the init will failed.
+         */
+        if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+             oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+                _deassert_hardreset(oh, oh->rst_lines[0].name);
+
         /* XXX mux balls */
 
         _add_initiator_dep(oh, mpu_oh);
@@ -922,7 +1210,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
                 if (oh->class->sysc) {
                         if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
                                 _update_sysc_cache(oh);
-                        _sysc_enable(oh);
+                        _enable_sysc(oh);
                 }
         } else {
                 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
@@ -933,12 +1221,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
 }
 
 /**
- * _idle - idle an omap_hwmod
+ * _omap_hwmod_idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Idles an omap_hwmod @oh.  This should be called once the hwmod has
- * no further work.  Returns -EINVAL if the hwmod is in the wrong
- * state or returns 0.
+ * no further work.  (This function has a full name --
+ * _omap_hwmod_idle() rather than simply _idle() -- because it is
+ * currently required by the pm34xx.c idle loop.)  Returns -EINVAL if
+ * the hwmod is in the wrong state or returns 0.
  */
 int _omap_hwmod_idle(struct omap_hwmod *oh)
 {
@@ -951,7 +1241,7 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
         pr_debug("omap_hwmod: %s: idling\n", oh->name);
 
         if (oh->class->sysc)
-                _sysc_idle(oh);
+                _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
         _disable_clocks(oh);
 
@@ -981,10 +1271,21 @@ static int _shutdown(struct omap_hwmod *oh)
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
 
         if (oh->class->sysc)
-                _sysc_shutdown(oh);
-        _del_initiator_dep(oh, mpu_oh);
-        /* XXX what about the other system initiators here? DMA, tesla, d2d */
-        _disable_clocks(oh);
+                _shutdown_sysc(oh);
+
+        /*
+         * If an IP contains only one HW reset line, then assert it
+         * before disabling the clocks and shutting down the IP.
+         */
+        if (oh->rst_lines_cnt == 1)
+                _assert_hardreset(oh, oh->rst_lines[0].name);
+
+        /* clocks and deps are already disabled in idle */
+        if (oh->_state == _HWMOD_STATE_ENABLED) {
+                _del_initiator_dep(oh, mpu_oh);
+                /* XXX what about the other system initiators here? dma, dsp */
+                _disable_clocks(oh);
+        }
         /* XXX Should this code also force-disable the optional clocks? */
 
         /* XXX mux any associated balls to safe mode */
@@ -1000,11 +1301,10 @@ static int _shutdown(struct omap_hwmod *oh)
  * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1
  *
  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Must be called with omap_hwmod_mutex held.
- * @skip_setup_idle is intended to be used on a system that will not
- * call omap_hwmod_enable() to enable devices (e.g., a system without
- * PM runtime).  Returns -EINVAL if the hwmod is in the wrong state or
- * returns 0.
+ * OCP_SYSCONFIG register.  @skip_setup_idle is intended to be used on
+ * a system that will not call omap_hwmod_enable() to enable devices
+ * (e.g., a system without PM runtime).  Returns -EINVAL if the hwmod
+ * is in the wrong state or returns 0.
  */
 static int _setup(struct omap_hwmod *oh, void *data)
 {
@@ -1034,8 +1334,19 @@ static int _setup(struct omap_hwmod *oh, void *data)
                 }
         }
 
+        mutex_init(&oh->_mutex);
         oh->_state = _HWMOD_STATE_INITIALIZED;
 
+        /*
+         * In the case of hwmod with hardreset that should not be
+         * de-assert at boot time, we have to keep the module
+         * initialized, because we cannot enable it properly with the
+         * reset asserted. Exit without warning because that behavior is
+         * expected.
+         */
+        if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
+                return 0;
+
         r = _omap_hwmod_enable(oh);
         if (r) {
                 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
@@ -1044,16 +1355,16 @@ static int _setup(struct omap_hwmod *oh, void *data)
         }
 
         if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
+                _reset(oh);
+
                 /*
-                 * XXX Do the OCP_SYSCONFIG bits need to be
-                 * reprogrammed after a reset?  If not, then this can
-                 * be removed.  If they do, then probably the
-                 * _omap_hwmod_enable() function should be split to avoid the
-                 * rewrite of the OCP_SYSCONFIG register.
+                 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
+                 * The _omap_hwmod_enable() function should be split to
+                 * avoid the rewrite of the OCP_SYSCONFIG register.
                  */
                 if (oh->class->sysc) {
                         _update_sysc_cache(oh);
-                        _sysc_enable(oh);
+                        _enable_sysc(oh);
                 }
         }
 
@@ -1067,14 +1378,20 @@ static int _setup(struct omap_hwmod *oh, void *data)
 
 /* Public functions */
 
-u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs)
+u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
 {
-        return __raw_readl(oh->_mpu_rt_va + reg_offs);
+        if (oh->flags & HWMOD_16BIT_REG)
+                return __raw_readw(oh->_mpu_rt_va + reg_offs);
+        else
+                return __raw_readl(oh->_mpu_rt_va + reg_offs);
 }
 
-void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs)
+void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 {
-        __raw_writel(v, oh->_mpu_rt_va + reg_offs);
+        if (oh->flags & HWMOD_16BIT_REG)
+                __raw_writew(v, oh->_mpu_rt_va + reg_offs);
+        else
+                __raw_writel(v, oh->_mpu_rt_va + reg_offs);
 }
 
 /**
@@ -1309,7 +1626,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh)
  * omap_hwmod_enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Enable an omap_hwomd @oh.  Intended to be called by omap_device_enable().
+ * Enable an omap_hwmod @oh.  Intended to be called by omap_device_enable().
  * Returns -EINVAL on error or passes along the return value from _enable().
  */
 int omap_hwmod_enable(struct omap_hwmod *oh)
@@ -1319,9 +1636,9 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         r = _omap_hwmod_enable(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return r;
 }
@@ -1331,7 +1648,7 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
  * omap_hwmod_idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Idle an omap_hwomd @oh.  Intended to be called by omap_device_idle().
+ * Idle an omap_hwmod @oh.  Intended to be called by omap_device_idle().
  * Returns -EINVAL on error or passes along the return value from _idle().
  */
 int omap_hwmod_idle(struct omap_hwmod *oh)
@@ -1339,9 +1656,9 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _omap_hwmod_idle(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1350,7 +1667,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
  * omap_hwmod_shutdown - shutdown an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Shutdown an omap_hwomd @oh.  Intended to be called by
+ * Shutdown an omap_hwmod @oh.  Intended to be called by
  * omap_device_shutdown().  Returns -EINVAL on error or passes along
  * the return value from _shutdown().
  */
@@ -1359,9 +1676,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _shutdown(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1374,9 +1691,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
  */
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _enable_clocks(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1389,9 +1706,9 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
  */
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _disable_clocks(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1421,7 +1738,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
          * Forces posted writes to complete on the OCP thread handling
          * register writes
          */
-        omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
+        omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
 }
 
 /**
@@ -1430,20 +1747,18 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
  *
  * Under some conditions, a driver may wish to reset the entire device.
  * Called from omap_device code.  Returns -EINVAL on error or passes along
- * the return value from _reset()/_enable().
+ * the return value from _reset().
  */
 int omap_hwmod_reset(struct omap_hwmod *oh)
 {
         int r;
 
-        if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED))
+        if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         r = _reset(oh);
-        if (!r)
-                r = _omap_hwmod_enable(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return r;
 }
@@ -1468,7 +1783,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
         int ret, i;
 
-        ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt;
+        ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
 
         for (i = 0; i < oh->slaves_cnt; i++)
                 ret += oh->slaves[i]->addr_cnt;
@@ -1501,10 +1816,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                 r++;
         }
 
-        for (i = 0; i < oh->sdma_chs_cnt; i++) {
-                (res + r)->name = (oh->sdma_chs + i)->name;
-                (res + r)->start = (oh->sdma_chs + i)->dma_ch;
-                (res + r)->end = (oh->sdma_chs + i)->dma_ch;
+        for (i = 0; i < oh->sdma_reqs_cnt; i++) {
+                (res + r)->name = (oh->sdma_reqs + i)->name;
+                (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->end = (oh->sdma_reqs + i)->dma_req;
                 (res + r)->flags = IORESOURCE_DMA;
                 r++;
         }
@@ -1644,9 +1959,9 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _enable_wakeup(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1669,14 +1984,92 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _disable_wakeup(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
 
 /**
+ * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to lookup and assert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ * yet supported on this OMAP; otherwise, passes along the return value
+ * from _assert_hardreset().
+ */
+int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&oh->_mutex);
+        ret = _assert_hardreset(oh, name);
+        mutex_unlock(&oh->_mutex);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and deassert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ * yet supported on this OMAP; otherwise, passes along the return value
+ * from _deassert_hardreset().
+ */
+int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&oh->_mutex);
+        ret = _deassert_hardreset(oh, name);
+        mutex_unlock(&oh->_mutex);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_read_hardreset - read the HW reset line state of submodules
+ * contained in the hwmod module
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and read
+ *
+ * Return the current state of the hwmod @oh's reset line named @name:
+ * returns -EINVAL upon parameter error or if this operation
+ * is unsupported on the current OMAP; otherwise, passes along the return
+ * value from _read_hardreset().
+ */
+int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&oh->_mutex);
+        ret = _read_hardreset(oh, name);
+        mutex_unlock(&oh->_mutex);
+
+        return ret;
+}
+
+
+/**
  * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
  * @classname: struct omap_hwmod_class name to search for
  * @fn: callback function pointer to call for each hwmod in class @classname
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 3cc768e8bc0..adf6e3632a2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,10 +15,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
 
 /*
  * OMAP2420 hardware module integration data
@@ -33,6 +35,7 @@ static struct omap_hwmod omap2420_mpu_hwmod;
 static struct omap_hwmod omap2420_iva_hwmod;
 static struct omap_hwmod omap2420_l3_main_hwmod;
 static struct omap_hwmod omap2420_l4_core_hwmod;
+static struct omap_hwmod omap2420_wd_timer2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -71,6 +74,9 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2420_l4_wkup_hwmod;
+static struct omap_hwmod omap2420_uart1_hwmod;
+static struct omap_hwmod omap2420_uart2_hwmod;
+static struct omap_hwmod omap2420_uart3_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -79,6 +85,60 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART1_BASE,
+                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2420_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART2_BASE,
+                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2420_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART3_BASE,
+                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2420_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
         &omap2420_l3_main__l4_core,
@@ -87,6 +147,9 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
         &omap2420_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
 };
 
 /* L4 CORE */
@@ -165,12 +228,206 @@ static struct omap_hwmod omap2420_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48022000,
+                .pa_end         = 0x4802207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2420_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap2420_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
+        &omap2420_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap2420_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2420_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+        .slaves         = omap2420_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+        &omap2_l4_core__uart1,
+};
+
+static struct omap_hwmod omap2420_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+        &omap2_l4_core__uart2,
+};
+
+static struct omap_hwmod omap2420_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+        &omap2_l4_core__uart3,
+};
+
+static struct omap_hwmod omap2420_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         &omap2420_l3_main_hwmod,
         &omap2420_l4_core_hwmod,
         &omap2420_l4_wkup_hwmod,
         &omap2420_mpu_hwmod,
         &omap2420_iva_hwmod,
+        &omap2420_wd_timer2_hwmod,
+        &omap2420_uart1_hwmod,
+        &omap2420_uart2_hwmod,
+        &omap2420_uart3_hwmod,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4526628ed28..12d939e456c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,10 +15,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
 
 /*
  * OMAP2430 hardware module integration data
@@ -33,6 +35,7 @@ static struct omap_hwmod omap2430_mpu_hwmod;
 static struct omap_hwmod omap2430_iva_hwmod;
 static struct omap_hwmod omap2430_l3_main_hwmod;
 static struct omap_hwmod omap2430_l4_core_hwmod;
+static struct omap_hwmod omap2430_wd_timer2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -71,6 +74,9 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2430_l4_wkup_hwmod;
+static struct omap_hwmod omap2430_uart1_hwmod;
+static struct omap_hwmod omap2430_uart2_hwmod;
+static struct omap_hwmod omap2430_uart3_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -79,6 +85,60 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART1_BASE,
+                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2430_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART2_BASE,
+                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2430_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART3_BASE,
+                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2430_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
         &omap2430_l3_main__l4_core,
@@ -104,6 +164,9 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
 /* Slave interfaces on the L4_WKUP interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
         &omap2430_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
 };
 
 /* Master interfaces on the L4_WKUP interconnect */
@@ -165,12 +228,206 @@ static struct omap_hwmod omap2430_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49016000,
+                .pa_end         = 0x4901607f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2430_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap2430_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
+        &omap2430_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap2430_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2430_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+        .slaves         = omap2430_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+        &omap2_l4_core__uart1,
+};
+
+static struct omap_hwmod omap2430_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+        &omap2_l4_core__uart2,
+};
+
+static struct omap_hwmod omap2430_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+        &omap2_l4_core__uart3,
+};
+
+static struct omap_hwmod omap2430_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l3_main_hwmod,
         &omap2430_l4_core_hwmod,
         &omap2430_l4_wkup_hwmod,
         &omap2430_mpu_hwmod,
         &omap2430_iva_hwmod,
+        &omap2430_wd_timer2_hwmod,
+        &omap2430_uart1_hwmod,
+        &omap2430_uart2_hwmod,
+        &omap2430_uart3_hwmod,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58ba5e..cb97ecf0a3f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,10 +17,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-34xx.h"
+#include "cm-regbits-34xx.h"
 
 /*
  * OMAP3xxx hardware module integration data
@@ -36,6 +38,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod;
 static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
+static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -82,6 +85,10 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
+static struct omap_hwmod omap3xxx_uart1_hwmod;
+static struct omap_hwmod omap3xxx_uart2_hwmod;
+static struct omap_hwmod omap3xxx_uart3_hwmod;
+static struct omap_hwmod omap3xxx_uart4_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
@@ -90,6 +97,78 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART1_BASE,
+                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap3xxx_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART2_BASE,
+                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap3xxx_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART3_BASE,
+                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap3xxx_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART4 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_BASE,
+                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = omap3xxx_uart4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
         &omap3xxx_l3_main__l4_core,
@@ -98,6 +177,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
         &omap3xxx_l4_core__l4_wkup,
+        &omap3_l4_core__uart1,
+        &omap3_l4_core__uart2,
 };
 
 /* L4 CORE */
@@ -119,6 +200,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 
 /* Master interfaces on the L4_PER interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
+        &omap3_l4_per__uart3,
+        &omap3_l4_per__uart4,
 };
 
 /* L4 PER */
@@ -197,6 +280,235 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48314000,
+                .pa_end         = 0x4831407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_wd_timer2_hwmod,
+        .clk            = "wdt2_ick",
+        .addr           = omap3xxx_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap3xxx_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
+        &omap3xxx_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap3xxx_wd_timer_hwmod_class,
+        .main_clk       = "wdt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_WDT2_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART common */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+        &omap3_l4_core__uart1,
+};
+
+static struct omap_hwmod omap3xxx_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+        &omap3_l4_core__uart2,
+};
+
+static struct omap_hwmod omap3xxx_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+        &omap3_l4_per__uart3,
+};
+
+static struct omap_hwmod omap3xxx_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART4 */
+
+static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+        { .irq = INT_36XX_UART4_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
+        { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+        &omap3_l4_per__uart4,
+};
+
+static struct omap_hwmod omap3xxx_uart4_hwmod = {
+        .name           = "uart4",
+        .mpu_irqs       = uart4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
+        .sdma_reqs      = uart4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
+        .main_clk       = "uart4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3630_EN_UART4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
@@ -204,6 +516,11 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l4_wkup_hwmod,
         &omap3xxx_mpu_hwmod,
         &omap3xxx_iva_hwmod,
+        &omap3xxx_wd_timer2_hwmod,
+        &omap3xxx_uart1_hwmod,
+        &omap3xxx_uart2_hwmod,
+        &omap3xxx_uart3_hwmod,
+        &omap3xxx_uart4_hwmod,
         NULL,
 };
 
@@ -211,5 +528,3 @@ int __init omap3xxx_hwmod_init(void)
 {
         return omap_hwmod_init(omap3xxx_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
new file mode 100644
index 00000000000..7274db4de48
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -0,0 +1,850 @@
+/*
+ * Hardware modules present on the OMAP44xx chips
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "cm.h"
+#include "prm-regbits-44xx.h"
+
+/* Base offset for all OMAP4 interrupts external to MPUSS */
+#define OMAP44XX_IRQ_GIC_START  32
+
+/* Base offset for all OMAP4 dma requests */
+#define OMAP44XX_DMA_REQ_START  1
+
+/* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod omap44xx_dmm_hwmod;
+static struct omap_hwmod omap44xx_emif_fw_hwmod;
+static struct omap_hwmod omap44xx_l3_instr_hwmod;
+static struct omap_hwmod omap44xx_l3_main_1_hwmod;
+static struct omap_hwmod omap44xx_l3_main_2_hwmod;
+static struct omap_hwmod omap44xx_l3_main_3_hwmod;
+static struct omap_hwmod omap44xx_l4_abe_hwmod;
+static struct omap_hwmod omap44xx_l4_cfg_hwmod;
+static struct omap_hwmod omap44xx_l4_per_hwmod;
+static struct omap_hwmod omap44xx_l4_wkup_hwmod;
+static struct omap_hwmod omap44xx_mpu_hwmod;
+static struct omap_hwmod omap44xx_mpu_private_hwmod;
+
+/*
+ * Interconnects omap_hwmod structures
+ * hwmods that compose the global OMAP interconnect
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
+        .name = "dmm",
+};
+
+/* dmm interface data */
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dmm slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
+        &omap44xx_l3_main_1__dmm,
+        &omap44xx_mpu__dmm,
+};
+
+static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
+        { .irq = 113 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod omap44xx_dmm_hwmod = {
+        .name           = "dmm",
+        .class          = &omap44xx_dmm_hwmod_class,
+        .slaves         = omap44xx_dmm_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
+        .mpu_irqs       = omap44xx_dmm_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
+        .name = "emif_fw",
+};
+
+/* emif_fw interface data */
+/* dmm -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
+        .master         = &omap44xx_dmm_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* emif_fw slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
+        &omap44xx_dmm__emif_fw,
+        &omap44xx_l4_cfg__emif_fw,
+};
+
+static struct omap_hwmod omap44xx_emif_fw_hwmod = {
+        .name           = "emif_fw",
+        .class          = &omap44xx_emif_fw_hwmod_class,
+        .slaves         = omap44xx_emif_fw_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
+        .name = "l3",
+};
+
+/* l3_instr interface data */
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
+        .master         = &omap44xx_l3_main_3_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_instr slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
+        &omap44xx_l3_main_3__l3_instr,
+};
+
+static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_instr_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+        &omap44xx_l3_main_2__l3_main_1,
+        &omap44xx_l4_cfg__l3_main_1,
+        &omap44xx_mpu__l3_main_1,
+};
+
+static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+        .name           = "l3_main_1",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_2 interface data */
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+        &omap44xx_l3_main_1__l3_main_2,
+        &omap44xx_l4_cfg__l3_main_2,
+};
+
+static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+        .name           = "l3_main_2",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_3 interface data */
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
+        &omap44xx_l3_main_1__l3_main_3,
+        &omap44xx_l3_main_2__l3_main_3,
+        &omap44xx_l4_cfg__l3_main_3,
+};
+
+static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
+        .name           = "l3_main_3",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
+        .name = "l4",
+};
+
+/* l4_abe interface data */
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
+        &omap44xx_l3_main_1__l4_abe,
+        &omap44xx_mpu__l4_abe,
+};
+
+static struct omap_hwmod omap44xx_l4_abe_hwmod = {
+        .name           = "l4_abe",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_abe_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_cfg interface data */
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_cfg_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
+        &omap44xx_l3_main_1__l4_cfg,
+};
+
+static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
+        .name           = "l4_cfg",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_cfg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_per interface data */
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l4_per_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
+        &omap44xx_l3_main_2__l4_per,
+};
+
+static struct omap_hwmod omap44xx_l4_per_hwmod = {
+        .name           = "l4_per",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_per_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_wkup interface data */
+/* l4_cfg -> l4_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l4_wkup_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
+        &omap44xx_l4_cfg__l4_wkup,
+};
+
+static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_wkup_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
+        .name = "mpu_bus",
+};
+
+/* mpu_private interface data */
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_mpu_private_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu_private slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
+        &omap44xx_mpu__mpu_private,
+};
+
+static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+        .name           = "mpu_private",
+        .class          = &omap44xx_mpu_bus_hwmod_class,
+        .slaves         = omap44xx_mpu_private_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+
+static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
+        .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+        { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
+        { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
+        { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* mpu master ports */
+static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
+        &omap44xx_mpu__l3_main_1,
+        &omap44xx_mpu__l4_abe,
+        &omap44xx_mpu__dmm,
+};
+
+static struct omap_hwmod omap44xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &omap44xx_mpu_hwmod_class,
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = omap44xx_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
+                },
+        },
+        .masters        = omap44xx_mpu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap44xx_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap44xx_wd_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
+        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4a314000,
+                .pa_end         = 0x4a31407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
+        .name = "uart",
+        .sysc = &omap44xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod omap44xx_uart1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
+        { .irq = 72 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+        {
+                .pa_start       = 0x4806a000,
+                .pa_end         = 0x4806a0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
+        &omap44xx_l4_per__uart1,
+};
+
+static struct omap_hwmod omap44xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
+        .sdma_reqs      = omap44xx_uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart2 */
+static struct omap_hwmod omap44xx_uart2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
+        { .irq = 73 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+        {
+                .pa_start       = 0x4806c000,
+                .pa_end         = 0x4806c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_wd_timer2_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wd_timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
+        &omap44xx_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
+        .main_clk       = "wd_timer2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* wd_timer3 */
+static struct omap_hwmod omap44xx_wd_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
+        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+        {
+                .pa_start       = 0x40130000,
+                .pa_end         = 0x4013007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
+        &omap44xx_l4_per__uart2,
+};
+
+static struct omap_hwmod omap44xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
+        .sdma_reqs      = omap44xx_uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart3 */
+static struct omap_hwmod omap44xx_uart3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
+        { .irq = 74 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+        {
+                .pa_start       = 0x48020000,
+                .pa_end         = 0x480200ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> wd_timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> wd_timer3 (dma) */
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+        {
+                .pa_start       = 0x49030000,
+                .pa_end         = 0x4903007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
+        &omap44xx_l4_per__uart3,
+};
+
+static struct omap_hwmod omap44xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &omap44xx_uart_hwmod_class,
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = omap44xx_uart3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
+        .sdma_reqs      = omap44xx_uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart4 */
+static struct omap_hwmod omap44xx_uart4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
+        { .irq = 70 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+        {
+                .pa_start       = 0x4806e000,
+                .pa_end         = 0x4806e0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* wd_timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
+        &omap44xx_l4_abe__wd_timer3,
+        &omap44xx_l4_abe__wd_timer3_dma,
+};
+
+static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+        .name           = "wd_timer3",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
+        .main_clk       = "wd_timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
+        &omap44xx_l4_per__uart4,
+};
+
+static struct omap_hwmod omap44xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
+        .sdma_reqs      = omap44xx_uart4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
+        .main_clk       = "uart4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+        /* dmm class */
+        &omap44xx_dmm_hwmod,
+        /* emif_fw class */
+        &omap44xx_emif_fw_hwmod,
+        /* l3 class */
+        &omap44xx_l3_instr_hwmod,
+        &omap44xx_l3_main_1_hwmod,
+        &omap44xx_l3_main_2_hwmod,
+        &omap44xx_l3_main_3_hwmod,
+        /* l4 class */
+        &omap44xx_l4_abe_hwmod,
+        &omap44xx_l4_cfg_hwmod,
+        &omap44xx_l4_per_hwmod,
+        &omap44xx_l4_wkup_hwmod,
+        /* mpu_bus class */
+        &omap44xx_mpu_private_hwmod,
+
+        /* mpu class */
+        &omap44xx_mpu_hwmod,
+        /* wd_timer class */
+        &omap44xx_wd_timer2_hwmod,
+        &omap44xx_wd_timer3_hwmod,
+
+        /* uart class */
+        &omap44xx_uart1_hwmod,
+        &omap44xx_uart2_hwmod,
+        &omap44xx_uart3_hwmod,
+        &omap44xx_uart4_hwmod,
+        NULL,
+};
+
+int __init omap44xx_hwmod_init(void)
+{
+        return omap_hwmod_init(omap44xx_hwmods);
+}
+
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 723b44e252f..5e81517a7af 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -31,12 +31,17 @@
 #include <plat/board.h>
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
+#include <plat/dmtimer.h>
 
 #include "prm.h"
 #include "cm.h"
 #include "pm.h"
 
 int omap2_pm_debug;
+u32 enable_off_mode;
+u32 sleep_while_idle;
+u32 wakeup_timer_seconds;
+u32 wakeup_timer_milliseconds;
 
 #define DUMP_PRM_MOD_REG(mod, reg)    \
         regs[reg_count].name = #mod "." #reg; \
@@ -162,7 +167,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
 
 static void pm_dbg_regset_store(u32 *ptr);
 
-struct dentry *pm_dbg_dir;
+static struct dentry *pm_dbg_dir;
 
 static int pm_dbg_init_done;
 
@@ -349,6 +354,23 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
         pwrdm->timer = t;
 }
 
+void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
+{
+        u32 tick_rate, cycles;
+
+        if (!seconds && !milliseconds)
+                return;
+
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
+        omap_dm_timer_stop(gptimer_wakeup);
+        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
+
+        pr_info("PM: Resume timer in %u.%03u secs"
+                " (%d ticks at %d ticks/sec.)\n",
+                seconds, milliseconds, cycles, tick_rate);
+}
+
 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
 {
         struct seq_file *s = (struct seq_file *)user;
@@ -494,8 +516,10 @@ int pm_dbg_regset_init(int reg_set)
 
 static int pwrdm_suspend_get(void *data, u64 *val)
 {
-        int ret;
-        ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
+        int ret = -EINVAL;
+
+        if (cpu_is_omap34xx())
+                ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
         *val = ret;
 
         if (ret >= 0)
@@ -505,7 +529,10 @@ static int pwrdm_suspend_get(void *data, u64 *val)
 
 static int pwrdm_suspend_set(void *data, u64 val)
 {
-        return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
+        if (cpu_is_omap34xx())
+                return omap3_pm_set_suspend_state(
+                        (struct powerdomain *)data, (int)val);
+        return -EINVAL;
 }
 
 DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
@@ -553,8 +580,10 @@ static int option_set(void *data, u64 val)
 
         *option = val;
 
-        if (option == &enable_off_mode)
-                omap3_pm_off_mode_enable(val);
+        if (option == &enable_off_mode) {
+                if (cpu_is_omap34xx())
+                        omap3_pm_off_mode_enable(val);
+        }
 
         return 0;
 }
@@ -609,6 +638,9 @@ static int __init pm_dbg_init(void)
                                    &sleep_while_idle, &pm_dbg_option_fops);
         (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
                                    &wakeup_timer_seconds, &pm_dbg_option_fops);
+        (void) debugfs_create_file("wakeup_timer_milliseconds",
+                        S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
+                        &pm_dbg_option_fops);
         pm_dbg_init_done = 1;
 
         return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 68f9f2e9589..59ca03b0e69 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -18,11 +18,15 @@
 #include <plat/omap_device.h>
 #include <plat/common.h>
 
+#include <plat/powerdomain.h>
+#include <plat/clockdomain.h>
+
 static struct omap_device_pm_latency *pm_lats;
 
 static struct device *mpu_dev;
-static struct device *dsp_dev;
+static struct device *iva_dev;
 static struct device *l3_dev;
+static struct device *dsp_dev;
 
 struct device *omap2_get_mpuss_device(void)
 {
@@ -30,10 +34,10 @@ struct device *omap2_get_mpuss_device(void)
         return mpu_dev;
 }
 
-struct device *omap2_get_dsp_device(void)
+struct device *omap2_get_iva_device(void)
 {
-        WARN_ON_ONCE(!dsp_dev);
-        return dsp_dev;
+        WARN_ON_ONCE(!iva_dev);
+        return iva_dev;
 }
 
 struct device *omap2_get_l3_device(void)
@@ -42,6 +46,13 @@ struct device *omap2_get_l3_device(void)
         return l3_dev;
 }
 
+struct device *omap4_get_dsp_device(void)
+{
+        WARN_ON_ONCE(!dsp_dev);
+        return dsp_dev;
+}
+EXPORT_SYMBOL(omap4_get_dsp_device);
+
 /* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
 static int _init_omap_device(char *name, struct device **new_dev)
 {
@@ -69,8 +80,60 @@ static int _init_omap_device(char *name, struct device **new_dev)
 static void omap2_init_processor_devices(void)
 {
         _init_omap_device("mpu", &mpu_dev);
-        _init_omap_device("iva", &dsp_dev);
-        _init_omap_device("l3_main", &l3_dev);
+        _init_omap_device("iva", &iva_dev);
+        if (cpu_is_omap44xx()) {
+                _init_omap_device("l3_main_1", &l3_dev);
+                _init_omap_device("dsp", &dsp_dev);
+        } else {
+                _init_omap_device("l3_main", &l3_dev);
+        }
+}
+
+/*
+ * This sets pwrdm state (other than mpu & core. Currently only ON &
+ * RET are supported. Function is assuming that clkdm doesn't have
+ * hw_sup mode enabled.
+ */
+int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+{
+        u32 cur_state;
+        int sleep_switch = 0;
+        int ret = 0;
+
+        if (pwrdm == NULL || IS_ERR(pwrdm))
+                return -EINVAL;
+
+        while (!(pwrdm->pwrsts & (1 << state))) {
+                if (state == PWRDM_POWER_OFF)
+                        return ret;
+                state--;
+        }
+
+        cur_state = pwrdm_read_next_pwrst(pwrdm);
+        if (cur_state == state)
+                return ret;
+
+        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
+                omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+                sleep_switch = 1;
+                pwrdm_wait_transition(pwrdm);
+        }
+
+        ret = pwrdm_set_next_pwrst(pwrdm, state);
+        if (ret) {
+                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
+                       pwrdm->name);
+                goto err;
+        }
+
+        if (sleep_switch) {
+                omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+                pwrdm_wait_transition(pwrdm);
+                pwrdm_state_switch(pwrdm);
+        }
+
+err:
+        return ret;
 }
 
 static int __init omap2_common_pm_init(void)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 3de6ece23fc..0d75bfd1fdb 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -13,14 +13,11 @@
 
 #include <plat/powerdomain.h>
 
-extern u32 enable_off_mode;
-extern u32 sleep_while_idle;
-
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
-extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 
 struct cpuidle_params {
@@ -48,10 +45,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
 
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
+extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
 extern int omap2_pm_debug;
+extern u32 enable_off_mode;
+extern u32 sleep_while_idle;
 #else
 #define omap2_pm_dump(mode, resume, us)         do {} while (0);
+#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
 #define omap2_pm_debug                          0
+#define enable_off_mode 0
+#define sleep_while_idle 0
 #endif
 
 #if defined(CONFIG_CPU_IDLE)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 6aeedeacdad..a40457d8192 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -38,7 +38,6 @@
 #include <mach/irqs.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
-#include <plat/control.h>
 #include <plat/dma.h>
 #include <plat/board.h>
 
@@ -48,6 +47,7 @@
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 #include "pm.h"
+#include "control.h"
 
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
@@ -245,6 +245,8 @@ static int omap2_can_sleep(void)
 {
         if (omap2_fclks_active())
                 return 0;
+        if (!omap_uart_can_sleep())
+                return 0;
         if (osc_ck->usecount > 1)
                 return 0;
         if (omap_dma_running())
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7b03426c72a..75c0cd13ad8 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -32,13 +32,11 @@
 #include <plat/sram.h>
 #include <plat/clockdomain.h>
 #include <plat/powerdomain.h>
-#include <plat/control.h>
 #include <plat/serial.h>
 #include <plat/sdrc.h>
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
-#include <plat/dmtimer.h>
 
 #include <asm/tlbflush.h>
 
@@ -49,16 +47,12 @@
 #include "prm.h"
 #include "pm.h"
 #include "sdrc.h"
+#include "control.h"
 
 /* Scratchpad offsets */
-#define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
-#define OMAP343X_TABLE_VALUE_OFFSET        0x30
-#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
-
-u32 enable_off_mode;
-u32 sleep_while_idle;
-u32 wakeup_timer_seconds;
-u32 wakeup_timer_milliseconds;
+#define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
+#define OMAP343X_TABLE_VALUE_OFFSET        0xc0
+#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
 struct power_state {
         struct powerdomain *pwrdm;
@@ -316,7 +310,7 @@ static void restore_control_register(u32 val)
 /* Function to restore the table entry that was modified for enabling MMU */
 static void restore_table_entry(void)
 {
-        u32 *scratchpad_address;
+        void __iomem *scratchpad_address;
         u32 previous_value, control_reg_value;
         u32 *address;
 
@@ -351,7 +345,6 @@ void omap_sram_idle(void)
         int core_next_state = PWRDM_POWER_ON;
         int core_prev_state, per_prev_state;
         u32 sdrc_pwr = 0;
-        int per_state_modified = 0;
 
         if (!_omap_sram_idle)
                 return;
@@ -385,9 +378,9 @@ void omap_sram_idle(void)
         /* Enable IO-PAD and IO-CHAIN wakeups */
         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-        if (omap3_has_io_wakeup() && \
-                        (per_next_state < PWRDM_POWER_ON ||
-                        core_next_state < PWRDM_POWER_ON)) {
+        if (omap3_has_io_wakeup() &&
+            (per_next_state < PWRDM_POWER_ON ||
+             core_next_state < PWRDM_POWER_ON)) {
                 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_enable_io_chain();
         }
@@ -395,20 +388,12 @@ void omap_sram_idle(void)
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
                 omap_uart_prepare_idle(2);
+                omap_uart_prepare_idle(3);
                 omap2_gpio_prepare_for_idle(per_next_state);
-                if (per_next_state == PWRDM_POWER_OFF) {
-                        if (core_next_state == PWRDM_POWER_ON) {
-                                per_next_state = PWRDM_POWER_RET;
-                                pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
-                                per_state_modified = 1;
-                        } else
+                if (per_next_state == PWRDM_POWER_OFF)
                                 omap3_per_save_context();
-                }
         }
 
-        if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
-                omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
-
         /* CORE */
         if (core_next_state < PWRDM_POWER_ON) {
                 omap_uart_prepare_idle(0);
@@ -475,8 +460,7 @@ void omap_sram_idle(void)
                 if (per_prev_state == PWRDM_POWER_OFF)
                         omap3_per_restore_context();
                 omap_uart_resume_idle(2);
-                if (per_state_modified)
-                        pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
+                omap_uart_resume_idle(3);
         }
 
         /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -501,51 +485,6 @@ int omap3_can_sleep(void)
         return 1;
 }
 
-/* This sets pwrdm state (other than mpu & core. Currently only ON &
- * RET are supported. Function is assuming that clkdm doesn't have
- * hw_sup mode enabled. */
-int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
-{
-        u32 cur_state;
-        int sleep_switch = 0;
-        int ret = 0;
-
-        if (pwrdm == NULL || IS_ERR(pwrdm))
-                return -EINVAL;
-
-        while (!(pwrdm->pwrsts & (1 << state))) {
-                if (state == PWRDM_POWER_OFF)
-                        return ret;
-                state--;
-        }
-
-        cur_state = pwrdm_read_next_pwrst(pwrdm);
-        if (cur_state == state)
-                return ret;
-
-        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
-                omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
-                sleep_switch = 1;
-                pwrdm_wait_transition(pwrdm);
-        }
-
-        ret = pwrdm_set_next_pwrst(pwrdm, state);
-        if (ret) {
-                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
-                       pwrdm->name);
-                goto err;
-        }
-
-        if (sleep_switch) {
-                omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
-                pwrdm_wait_transition(pwrdm);
-                pwrdm_state_switch(pwrdm);
-        }
-
-err:
-        return ret;
-}
-
 static void omap3_pm_idle(void)
 {
         local_irq_disable();
@@ -567,23 +506,6 @@ out:
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state;
 
-static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
-        u32 tick_rate, cycles;
-
-        if (!seconds && !milliseconds)
-                return;
-
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
-        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
-        omap_dm_timer_stop(gptimer_wakeup);
-        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-
-        pr_info("PM: Resume timer in %u.%03u secs"
-                " (%d ticks at %d ticks/sec.)\n",
-                seconds, milliseconds, cycles, tick_rate);
-}
-
 static int omap3_pm_prepare(void)
 {
         disable_hlt();
@@ -604,7 +526,7 @@ static int omap3_pm_suspend(void)
                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
         /* Set ones wanted by suspend */
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
+                if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
                         goto restore;
                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
                         goto restore;
@@ -625,7 +547,7 @@ restore:
                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
-                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
         }
         if (ret)
                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -756,6 +678,14 @@ static void __init omap3_d2d_idle(void)
 
 static void __init prcm_setup_regs(void)
 {
+        u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_AUTO_UART4_MASK : 0;
+        u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_EN_UART4_MASK : 0;
+        u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_GRPSEL_UART4_MASK : 0;
+
+
         /* XXX Reset all wkdeps. This should be done when initializing
          * powerdomains */
         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
@@ -842,6 +772,7 @@ static void __init prcm_setup_regs(void)
                 CM_AUTOIDLE);
 
         cm_write_mod_reg(
+                omap3630_auto_uart4_mask |
                 OMAP3430_AUTO_GPIO6_MASK |
                 OMAP3430_AUTO_GPIO5_MASK |
                 OMAP3430_AUTO_GPIO4_MASK |
@@ -918,14 +849,16 @@ static void __init prcm_setup_regs(void)
                                 OMAP3430_DSS_MOD, PM_WKEN);
 
         /* Enable wakeups in PER */
-        prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
+        prm_write_mod_reg(omap3630_en_uart4_mask |
+                          OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
                           OMAP3430_EN_MCBSP4_MASK,
                           OMAP3430_PER_MOD, PM_WKEN);
         /* and allow them to wake up MPU */
-        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
+        prm_write_mod_reg(omap3630_grpsel_uart4_mask |
+                          OMAP3430_GRPSEL_GPIO2_MASK |
                           OMAP3430_GRPSEL_GPIO3_MASK |
                           OMAP3430_GRPSEL_GPIO4_MASK |
                           OMAP3430_GRPSEL_GPIO5_MASK |
@@ -974,7 +907,7 @@ void omap3_pm_off_mode_enable(int enable)
 
         list_for_each_entry(pwrst, &pwrst_list, node) {
                 pwrst->next_state = state;
-                set_pwrdm_state(pwrst->pwrdm, state);
+                omap_set_pwrdm_state(pwrst->pwrdm, state);
         }
 }
 
@@ -1019,7 +952,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
         if (pwrdm_has_hdwr_sar(pwrdm))
                 pwrdm_enable_hdwr_sar(pwrdm);
 
-        return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+        return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 }
 
 /*
@@ -1029,9 +962,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  */
 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        clkdm_clear_all_wkdeps(clkdm);
-        clkdm_clear_all_sleepdeps(clkdm);
-
         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
                 omap2_clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
new file mode 100644
index 00000000000..784989f8f2f
--- /dev/null
+++ b/arch/arm/mach-omap2/pm_bus.c
@@ -0,0 +1,85 @@
+/*
+ * Runtime PM support code for OMAP
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+
+#ifdef CONFIG_PM_RUNTIME
+int omap_pm_runtime_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int r, ret = 0;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        ret = pm_generic_runtime_suspend(dev);
+
+        if (!ret && dev->parent == &omap_device_parent) {
+                r = omap_device_idle(pdev);
+                WARN_ON(r);
+        }
+
+        return ret;
+};
+
+int omap_pm_runtime_resume(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int r;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        if (dev->parent == &omap_device_parent) {
+                r = omap_device_enable(pdev);
+                WARN_ON(r);
+        }
+
+        return pm_generic_runtime_resume(dev);
+};
+#else
+#define omap_pm_runtime_suspend NULL
+#define omap_pm_runtime_resume NULL
+#endif /* CONFIG_PM_RUNTIME */
+
+static int __init omap_pm_runtime_init(void)
+{
+        const struct dev_pm_ops *pm;
+        struct dev_pm_ops *omap_pm;
+
+        pm = platform_bus_get_pm_ops();
+        if (!pm) {
+                pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
+                        __func__);
+                return -ENODEV;
+        }
+
+        omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL);
+        if (!omap_pm) {
+                pr_err("%s: unable to alloc memory for new dev_pm_ops\n",
+                        __func__);
+                return -ENOMEM;
+        }
+
+        omap_pm->runtime_suspend = omap_pm_runtime_suspend;
+        omap_pm->runtime_resume = omap_pm_runtime_resume;
+
+        platform_bus_set_pm_ops(omap_pm);
+
+        return 0;
+}
+core_initcall(omap_pm_runtime_init);
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
index c7219513472..9c01b55d610 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = {
         .prcm_offs        = OMAP4430_PRM_DSS_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 1,
         .pwrsts_mem_ret = {
                 [0] = PWRDM_POWER_OFF,  /* dss_mem */
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 995b7edbf18..298a22a754e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -382,6 +382,9 @@
 #define OMAP3430_EN_MPU_SHIFT                           1
 
 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+
+#define OMAP3630_EN_UART4_MASK                          (1 << 18)
+#define OMAP3630_EN_UART4_SHIFT                         18
 #define OMAP3430_EN_GPIO6_MASK                          (1 << 17)
 #define OMAP3430_EN_GPIO6_SHIFT                         17
 #define OMAP3430_EN_GPIO5_MASK                          (1 << 16)
@@ -422,6 +425,8 @@
 #define OMAP3430_EN_MCBSP2_SHIFT                        0
 
 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3630_ST_UART4_SHIFT                         18
+#define OMAP3630_ST_UART4_MASK                          (1 << 18)
 #define OMAP3430_ST_GPIO6_SHIFT                         17
 #define OMAP3430_ST_GPIO6_MASK                          (1 << 17)
 #define OMAP3430_ST_GPIO5_SHIFT                         16
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c20137497c9..a51846e3a6f 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -26,13 +26,14 @@
 #include <plat/common.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
-#include <plat/control.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
+#include "prm-regbits-44xx.h"
+#include "control.h"
 
 static void __iomem *prm_base;
 static void __iomem *cm_base;
@@ -118,7 +119,7 @@ struct omap3_prcm_regs {
         u32 wkup_pm_wken;
 };
 
-struct omap3_prcm_regs prcm_context;
+static struct omap3_prcm_regs prcm_context;
 
 u32 omap_prcm_get_reset_sources(void)
 {
@@ -161,8 +162,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
                 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
                                                  OMAP2_RM_RSTCTRL);
         if (cpu_is_omap44xx())
-                prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
-                                                 OMAP4_RM_RSTCTRL);
+                prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
+                                     prcm_offs, OMAP4_RM_RSTCTRL);
 }
 
 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
@@ -215,6 +216,30 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
         return v;
 }
 
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= ~mask;
+        v |= bits;
+        __raw_writel(v, reg);
+
+        return v;
+}
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 7fd6023edf9..9e63cb743a9 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -122,6 +122,7 @@
 #define OMAP3430_MEMRETSTATE_MASK                       (1 << 8)
 
 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3630_GRPSEL_UART4_MASK                      (1 << 18)
 #define OMAP3430_GRPSEL_GPIO6_MASK                      (1 << 17)
 #define OMAP3430_GRPSEL_GPIO5_MASK                      (1 << 16)
 #define OMAP3430_GRPSEL_GPIO4_MASK                      (1 << 15)
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 597be4a2b9f..25b19b61017 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx Power Management register bits
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -30,587 +30,611 @@
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                1
-#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 (1 << 1)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              2
-#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               BITFIELD(2, 2)
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               (1 << 2)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   BITFIELD(31, 31)
+#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   (1 << 31)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   BITFIELD(31, 31)
+#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   (1 << 31)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   BITFIELD(7, 7)
+#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   (1 << 7)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   BITFIELD(7, 7)
+#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   (1 << 7)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   2
-#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    BITFIELD(2, 2)
+#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    (1 << 2)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   1
-#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    BITFIELD(1, 1)
+#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    (1 << 1)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_AESSMEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_AESSMEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_AESSMEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_AESSMEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_ABE_PWRSTST */
 #define OMAP4430_AESSMEM_STATEST_SHIFT                                  4
-#define OMAP4430_AESSMEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_AESSMEM_STATEST_MASK                                   (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_AIPOFF_SHIFT                                           8
-#define OMAP4430_AIPOFF_MASK                                            BITFIELD(8, 8)
+#define OMAP4430_AIPOFF_MASK                                            (1 << 8)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             0
-#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              BITFIELD(0, 1)
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              (0x3 << 0)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              4
-#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               BITFIELD(4, 5)
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               (0x3 << 4)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              2
-#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               BITFIELD(2, 3)
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               (0x3 << 2)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_RA_ERR_SHIFT                                      25
+#define OMAP4430_BYPS_RA_ERR_MASK                                       (1 << 25)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_SA_ERR_SHIFT                                      24
+#define OMAP4430_BYPS_SA_ERR_MASK                                       (1 << 24)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT                                 26
+#define OMAP4430_BYPS_TIMEOUT_ERR_MASK                                  (1 << 26)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_C2C_RST_SHIFT                                          10
+#define OMAP4430_C2C_RST_MASK                                           (1 << 10)
 
 /* Used by PM_CAM_PWRSTCTRL */
 #define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_CAM_PWRSTST */
 #define OMAP4430_CAM_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_CAM_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_CAM_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PRM_CLKREQCTRL */
 #define OMAP4430_CLKREQ_COND_SHIFT                                      0
-#define OMAP4430_CLKREQ_COND_MASK                                       BITFIELD(0, 2)
+#define OMAP4430_CLKREQ_COND_MASK                                       (0x7 << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 0
-#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  (0xff << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  8
-#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   (0xff << 8)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  16
-#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   (0xff << 16)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   4
-#define OMAP4430_CMD_VDD_CORE_L_MASK                                    BITFIELD(4, 4)
+#define OMAP4430_CMD_VDD_CORE_L_MASK                                    (1 << 4)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    12
-#define OMAP4430_CMD_VDD_IVA_L_MASK                                     BITFIELD(12, 12)
+#define OMAP4430_CMD_VDD_IVA_L_MASK                                     (1 << 12)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    17
-#define OMAP4430_CMD_VDD_MPU_L_MASK                                     BITFIELD(17, 17)
+#define OMAP4430_CMD_VDD_MPU_L_MASK                                     (1 << 17)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              18
-#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               BITFIELD(18, 19)
+#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               (0x3 << 18)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             9
-#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              BITFIELD(9, 9)
+#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              (1 << 9)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              6
-#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               BITFIELD(6, 7)
+#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               (0x3 << 6)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          16
-#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           BITFIELD(16, 17)
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           (0x3 << 16)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         8
-#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          BITFIELD(8, 8)
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          (1 << 8)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          4
-#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           BITFIELD(4, 5)
+#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           (0x3 << 4)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_CUSTOM_SHIFT                                           6
+#define OMAP4430_CUSTOM_MASK                                            (0x3 << 6)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_DATA_SHIFT                                             16
-#define OMAP4430_DATA_MASK                                              BITFIELD(16, 23)
+#define OMAP4430_DATA_MASK                                              (0xff << 16)
 
 /* Used by PRM_DEVICE_OFF_CTRL */
 #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                0
-#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 (1 << 0)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_DFILTEREN_SHIFT                                        6
-#define OMAP4430_DFILTEREN_MASK                                         BITFIELD(6, 6)
+#define OMAP4430_DFILTEREN_MASK                                         (1 << 6)
 
-/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT                               0
+#define OMAP4430_DISABLE_RTA_EXPORT_MASK                                (1 << 0)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 (1 << 4)
 
-/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                BITFIELD(0, 0)
+#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                (1 << 0)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                BITFIELD(0, 0)
+#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                (1 << 0)
 
 /* Used by PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              BITFIELD(6, 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              (1 << 6)
 
 /* Used by PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              BITFIELD(6, 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              (1 << 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 (1 << 2)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 (1 << 2)
 
 /* Used by PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 (1 << 1)
 
 /* Used by PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 (1 << 1)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 (1 << 3)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 (1 << 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              BITFIELD(7, 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              (1 << 7)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              BITFIELD(7, 7)
-
-/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT                                5
-#define OMAP4430_DPLL_USB_RECAL_EN_MASK                                 BITFIELD(5, 5)
-
-/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT                                5
-#define OMAP4430_DPLL_USB_RECAL_ST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              (1 << 7)
 
 /* Used by PM_DSS_PWRSTCTRL */
 #define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_DSS_PWRSTCTRL */
 #define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_DSS_PWRSTST */
 #define OMAP4430_DSS_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_DSS_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_DSS_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             20
-#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              BITFIELD(20, 21)
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              (0x3 << 20)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            10
-#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             BITFIELD(10, 10)
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             (1 << 10)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             8
-#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              BITFIELD(8, 9)
+#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              (0x3 << 8)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          22
-#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           BITFIELD(22, 23)
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           (0x3 << 22)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         11
-#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          BITFIELD(11, 11)
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          (1 << 11)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          10
-#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           BITFIELD(10, 11)
+#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           (0x3 << 10)
 
 /* Used by RM_MPU_RSTST */
 #define OMAP4430_EMULATION_RST_SHIFT                                    0
-#define OMAP4430_EMULATION_RST_MASK                                     BITFIELD(0, 0)
+#define OMAP4430_EMULATION_RST_MASK                                     (1 << 0)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_EMULATION_RST1ST_SHIFT                                 3
-#define OMAP4430_EMULATION_RST1ST_MASK                                  BITFIELD(3, 3)
+#define OMAP4430_EMULATION_RST1ST_MASK                                  (1 << 3)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_EMULATION_RST2ST_SHIFT                                 4
-#define OMAP4430_EMULATION_RST2ST_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_EMULATION_RST2ST_MASK                                  (1 << 4)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            3
-#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             BITFIELD(3, 3)
+#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             (1 << 3)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            4
-#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             BITFIELD(4, 4)
+#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             (1 << 4)
 
 /* Used by PM_EMU_PWRSTCTRL */
 #define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 16
-#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  BITFIELD(16, 17)
+#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  (0x3 << 16)
 
 /* Used by PM_EMU_PWRSTST */
 #define OMAP4430_EMU_BANK_STATEST_SHIFT                                 4
-#define OMAP4430_EMU_BANK_STATEST_MASK                                  BITFIELD(4, 5)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
- */
-#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT                                0
-#define OMAP4430_ENABLE_RTA_EXPORT_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_EMU_BANK_STATEST_MASK                                  (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC1_SHIFT                                          3
-#define OMAP4430_ENFUNC1_MASK                                           BITFIELD(3, 3)
+#define OMAP4430_ENFUNC1_EXPORT_SHIFT                                   3
+#define OMAP4430_ENFUNC1_EXPORT_MASK                                    (1 << 3)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC3_SHIFT                                          5
-#define OMAP4430_ENFUNC3_MASK                                           BITFIELD(5, 5)
+#define OMAP4430_ENFUNC3_EXPORT_SHIFT                                   5
+#define OMAP4430_ENFUNC3_EXPORT_MASK                                    (1 << 5)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ENFUNC4_SHIFT                                          6
-#define OMAP4430_ENFUNC4_MASK                                           BITFIELD(6, 6)
+#define OMAP4430_ENFUNC4_MASK                                           (1 << 6)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ENFUNC5_SHIFT                                          7
-#define OMAP4430_ENFUNC5_MASK                                           BITFIELD(7, 7)
+#define OMAP4430_ENFUNC5_MASK                                           (1 << 7)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_ERRORGAIN_SHIFT                                        16
-#define OMAP4430_ERRORGAIN_MASK                                         BITFIELD(16, 23)
+#define OMAP4430_ERRORGAIN_MASK                                         (0xff << 16)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_ERROROFFSET_SHIFT                                      24
-#define OMAP4430_ERROROFFSET_MASK                                       BITFIELD(24, 31)
+#define OMAP4430_ERROROFFSET_MASK                                       (0xff << 24)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                5
-#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 (1 << 5)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_FORCEUPDATE_SHIFT                                      1
-#define OMAP4430_FORCEUPDATE_MASK                                       BITFIELD(1, 1)
+#define OMAP4430_FORCEUPDATE_MASK                                       (1 << 1)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
 #define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  8
-#define OMAP4430_FORCEUPDATEWAIT_MASK                                   BITFIELD(8, 31)
+#define OMAP4430_FORCEUPDATEWAIT_MASK                                   (0xffffff << 8)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
 #define OMAP4430_FORCEWKUP_EN_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_EN_MASK                                      BITFIELD(10, 10)
+#define OMAP4430_FORCEWKUP_EN_MASK                                      (1 << 10)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_FORCEWKUP_ST_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_ST_MASK                                      BITFIELD(10, 10)
+#define OMAP4430_FORCEWKUP_ST_MASK                                      (1 << 10)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_FUNC_SHIFT                                             16
+#define OMAP4430_FUNC_MASK                                              (0xfff << 16)
 
 /* Used by PM_GFX_PWRSTCTRL */
 #define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_GFX_PWRSTST */
 #define OMAP4430_GFX_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_GFX_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_GFX_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  0
-#define OMAP4430_GLOBAL_COLD_RST_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_GLOBAL_COLD_RST_MASK                                   (1 << 0)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               1
-#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                BITFIELD(1, 1)
+#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_GLOBAL_WUEN_SHIFT                                      16
-#define OMAP4430_GLOBAL_WUEN_MASK                                       BITFIELD(16, 16)
+#define OMAP4430_GLOBAL_WUEN_MASK                                       (1 << 16)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_HSMCODE_SHIFT                                          0
-#define OMAP4430_HSMCODE_MASK                                           BITFIELD(0, 2)
+#define OMAP4430_HSMCODE_MASK                                           (0x7 << 0)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_HSMODEEN_SHIFT                                         3
-#define OMAP4430_HSMODEEN_MASK                                          BITFIELD(3, 3)
+#define OMAP4430_HSMODEEN_MASK                                          (1 << 3)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_HSSCLH_SHIFT                                           16
-#define OMAP4430_HSSCLH_MASK                                            BITFIELD(16, 23)
+#define OMAP4430_HSSCLH_MASK                                            (0xff << 16)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_HSSCLL_SHIFT                                           24
-#define OMAP4430_HSSCLL_MASK                                            BITFIELD(24, 31)
+#define OMAP4430_HSSCLL_MASK                                            (0xff << 24)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_HWA_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_HWA_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_HWA_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by RM_MPU_RSTST */
 #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               1
-#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                BITFIELD(1, 1)
+#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                (1 << 1)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                5
-#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 (1 << 5)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                6
-#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 BITFIELD(6, 6)
+#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 (1 << 6)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           5
-#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            BITFIELD(5, 5)
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            (1 << 5)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           6
-#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            BITFIELD(6, 6)
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            (1 << 6)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_ICEPICK_RST_SHIFT                                      9
-#define OMAP4430_ICEPICK_RST_MASK                                       BITFIELD(9, 9)
+#define OMAP4430_ICEPICK_RST_MASK                                       (1 << 9)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_INITVDD_SHIFT                                          2
-#define OMAP4430_INITVDD_MASK                                           BITFIELD(2, 2)
+#define OMAP4430_INITVDD_MASK                                           (1 << 2)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_INITVOLTAGE_SHIFT                                      8
-#define OMAP4430_INITVOLTAGE_MASK                                       BITFIELD(8, 15)
+#define OMAP4430_INITVOLTAGE_MASK                                       (0xff << 8)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_INTRANSITION_SHIFT                                     20
-#define OMAP4430_INTRANSITION_MASK                                      BITFIELD(20, 20)
+#define OMAP4430_INTRANSITION_MASK                                      (1 << 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_IO_EN_SHIFT                                            9
-#define OMAP4430_IO_EN_MASK                                             BITFIELD(9, 9)
+#define OMAP4430_IO_EN_MASK                                             (1 << 9)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_IO_ON_STATUS_SHIFT                                     5
-#define OMAP4430_IO_ON_STATUS_MASK                                      BITFIELD(5, 5)
+#define OMAP4430_IO_ON_STATUS_MASK                                      (1 << 5)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_IO_ST_SHIFT                                            9
-#define OMAP4430_IO_ST_MASK                                             BITFIELD(9, 9)
+#define OMAP4430_IO_ST_MASK                                             (1 << 9)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  0
-#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   (1 << 0)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOCLK_STATUS_SHIFT                                    1
-#define OMAP4430_ISOCLK_STATUS_MASK                                     BITFIELD(1, 1)
+#define OMAP4430_ISOCLK_STATUS_MASK                                     (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOOVR_EXTEND_SHIFT                                    4
-#define OMAP4430_ISOOVR_EXTEND_MASK                                     BITFIELD(4, 4)
+#define OMAP4430_ISOOVR_EXTEND_MASK                                     (1 << 4)
 
 /* Used by PRM_IO_COUNT */
 #define OMAP4430_ISO_2_ON_TIME_SHIFT                                    0
-#define OMAP4430_ISO_2_ON_TIME_MASK                                     BITFIELD(0, 7)
+#define OMAP4430_ISO_2_ON_TIME_MASK                                     (0xff << 0)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
 #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             16
-#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              BITFIELD(16, 17)
+#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              (0x3 << 16)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
 #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            8
-#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             BITFIELD(8, 8)
+#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             (1 << 8)
 
 /* Used by PM_L3INIT_PWRSTST */
 #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             4
-#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              BITFIELD(4, 5)
+#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              (0x3 << 4)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
+ */
+#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT                            24
+#define OMAP4430_LASTPOWERSTATEENTERED_MASK                             (0x3 << 24)
 
 /*
- * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL,
- * PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_LOGICRETSTATE_SHIFT                                    2
-#define OMAP4430_LOGICRETSTATE_MASK                                     BITFIELD(2, 2)
+#define OMAP4430_LOGICRETSTATE_MASK                                     (1 << 2)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_LOGICSTATEST_SHIFT                                     2
-#define OMAP4430_LOGICSTATEST_MASK                                      BITFIELD(2, 2)
+#define OMAP4430_LOGICSTATEST_MASK                                      (1 << 2)
 
 /*
- * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT,
- * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT,
- * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT,
- * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT,
- * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT,
- * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
- * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT,
- * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT,
- * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT,
- * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT,
- * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
- * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
- * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
- * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
- * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
  * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
  * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
  * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
- * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT,
- * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT,
- * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT,
- * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT,
- * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT,
- * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT,
- * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT,
- * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
- * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
- * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT,
- * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
- * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
- * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
- * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT,
- * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT,
- * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT
+ * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
+ * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
+ * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
+ * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
+ * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
+ * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
+ * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
+ * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
+ * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
+ * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
+ * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
+ * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
+ * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
+ * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
+ * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
+ * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
+ * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
+ * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
+ * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
+ * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
+ * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
+ * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
+ * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
+ * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
  */
 #define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  0
-#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   (1 << 0)
 
 /*
  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
- * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
+ * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
+ * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
  * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
  * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
- * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT,
- * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
- * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT,
- * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT,
- * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT,
- * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT,
- * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT,
- * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT,
- * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
- * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT,
- * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
- * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
+ * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
+ * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
+ * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
+ * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
+ * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
  */
 #define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  1
-#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   BITFIELD(1, 1)
+#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   (1 << 1)
 
 /* Used by RM_ABE_AESS_CONTEXT */
 #define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   (1 << 8)
 
 /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
 #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           8
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            (1 << 8)
 
 /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       9
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        (1 << 9)
 
 /* Used by RM_L3_2_OCMC_RAM_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              8
-#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               (1 << 8)
 
 /*
  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
  * RM_SDMA_SDMA_CONTEXT
  */
 #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          8
-#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           (1 << 8)
 
 /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
 #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
 #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             9
-#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              (1 << 9)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
 #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          8
-#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           (1 << 8)
 
 /* Used by RM_EMU_DEBUGSS_CONTEXT */
 #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 8
-#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  (1 << 8)
 
 /* Used by RM_GFX_GFX_CONTEXT */
 #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   (1 << 10)
 
 /*
  * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
@@ -620,19 +644,19 @@
  * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
  */
 #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             8
-#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              (1 << 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   8
-#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    (1 << 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   9
-#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    (1 << 9)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   (1 << 10)
 
 /*
  * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
@@ -640,14 +664,14 @@
  * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
  */
 #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         8
-#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          (1 << 8)
 
 /*
  * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
  * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
  */
 #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                8
-#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 (1 << 8)
 
 /*
  * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
@@ -655,245 +679,237 @@
  * RM_L4SEC_CRYPTODMA_CONTEXT
  */
 #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            8
-#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             (1 << 8)
 
 /* Used by RM_IVAHD_SL2_CONTEXT */
 #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  (1 << 9)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               10
-#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                (1 << 10)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  (1 << 8)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  (1 << 9)
 
 /* Used by RM_WKUP_SARRAM_CONTEXT */
 #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                8
-#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 (1 << 8)
 
 /*
- * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
- * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
- * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
+ * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              4
-#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               BITFIELD(4, 4)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_MEMORYCHANGE_SHIFT                                     3
-#define OMAP4430_MEMORYCHANGE_MASK                                      BITFIELD(3, 3)
+#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               (1 << 4)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_READY_SHIFT                                      1
-#define OMAP4430_MODEM_READY_MASK                                       BITFIELD(1, 1)
+#define OMAP4430_MODEM_READY_MASK                                       (1 << 1)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               9
-#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                BITFIELD(9, 9)
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                (1 << 9)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   16
-#define OMAP4430_MODEM_SLEEP_ST_MASK                                    BITFIELD(16, 16)
+#define OMAP4430_MODEM_SLEEP_ST_MASK                                    (1 << 16)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   8
-#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    (1 << 8)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   16
-#define OMAP4430_MPU_L1_ONSTATE_MASK                                    BITFIELD(16, 17)
+#define OMAP4430_MPU_L1_ONSTATE_MASK                                    (0x3 << 16)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  8
-#define OMAP4430_MPU_L1_RETSTATE_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_MPU_L1_RETSTATE_MASK                                   (1 << 8)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_L1_STATEST_SHIFT                                   4
-#define OMAP4430_MPU_L1_STATEST_MASK                                    BITFIELD(4, 5)
+#define OMAP4430_MPU_L1_STATEST_MASK                                    (0x3 << 4)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   18
-#define OMAP4430_MPU_L2_ONSTATE_MASK                                    BITFIELD(18, 19)
+#define OMAP4430_MPU_L2_ONSTATE_MASK                                    (0x3 << 18)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  9
-#define OMAP4430_MPU_L2_RETSTATE_MASK                                   BITFIELD(9, 9)
+#define OMAP4430_MPU_L2_RETSTATE_MASK                                   (1 << 9)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_L2_STATEST_SHIFT                                   6
-#define OMAP4430_MPU_L2_STATEST_MASK                                    BITFIELD(6, 7)
+#define OMAP4430_MPU_L2_STATEST_MASK                                    (0x3 << 6)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  20
-#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   BITFIELD(20, 21)
+#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   (0x3 << 20)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 10
-#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  BITFIELD(10, 10)
+#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  (1 << 10)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_RAM_STATEST_SHIFT                                  8
-#define OMAP4430_MPU_RAM_STATEST_MASK                                   BITFIELD(8, 9)
+#define OMAP4430_MPU_RAM_STATEST_MASK                                   (0x3 << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            2
-#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             BITFIELD(2, 2)
+#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             (1 << 2)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_MPU_WDT_RST_SHIFT                                      3
-#define OMAP4430_MPU_WDT_RST_MASK                                       BITFIELD(3, 3)
+#define OMAP4430_MPU_WDT_RST_MASK                                       (1 << 3)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         18
-#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          BITFIELD(18, 19)
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          (0x3 << 18)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        9
-#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         BITFIELD(9, 9)
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         (1 << 9)
 
 /* Used by PM_L4PER_PWRSTST */
 #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         6
-#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          BITFIELD(6, 7)
+#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          (0x3 << 6)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            24
-#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             BITFIELD(24, 25)
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             (0x3 << 24)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           12
-#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            BITFIELD(12, 12)
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            (1 << 12)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            12
-#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             BITFIELD(12, 13)
+#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             (0x3 << 12)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_OFF_SHIFT                                              0
-#define OMAP4430_OFF_MASK                                               BITFIELD(0, 7)
-
-/* Used by PRM_LDO_BANDGAP_CTRL */
-#define OMAP4430_OFF_ENABLE_SHIFT                                       0
-#define OMAP4430_OFF_ENABLE_MASK                                        BITFIELD(0, 0)
+#define OMAP4430_OFF_MASK                                               (0xff << 0)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_ON_SHIFT                                               24
-#define OMAP4430_ON_MASK                                                BITFIELD(24, 31)
+#define OMAP4430_ON_MASK                                                (0xff << 24)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_ONLP_SHIFT                                             16
-#define OMAP4430_ONLP_MASK                                              BITFIELD(16, 23)
+#define OMAP4430_ONLP_MASK                                              (0xff << 16)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_OPP_CHANGE_SHIFT                                       2
-#define OMAP4430_OPP_CHANGE_MASK                                        BITFIELD(2, 2)
+#define OMAP4430_OPP_CHANGE_MASK                                        (1 << 2)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_OPP_SEL_SHIFT                                          0
-#define OMAP4430_OPP_SEL_MASK                                           BITFIELD(0, 1)
+#define OMAP4430_OPP_SEL_MASK                                           (0x3 << 0)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 0
-#define OMAP4430_PCHARGECNT_VALUE_MASK                                  BITFIELD(0, 5)
+#define OMAP4430_PCHARGECNT_VALUE_MASK                                  (0x3f << 0)
 
 /* Used by PRM_PSCON_COUNT */
 #define OMAP4430_PCHARGE_TIME_SHIFT                                     0
-#define OMAP4430_PCHARGE_TIME_MASK                                      BITFIELD(0, 7)
+#define OMAP4430_PCHARGE_TIME_MASK                                      (0xff << 0)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                20
-#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 BITFIELD(20, 21)
+#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 (0x3 << 20)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               10
-#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                BITFIELD(10, 10)
+#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                (1 << 10)
 
 /* Used by PM_ABE_PWRSTST */
 #define OMAP4430_PERIPHMEM_STATEST_SHIFT                                8
-#define OMAP4430_PERIPHMEM_STATEST_MASK                                 BITFIELD(8, 9)
+#define OMAP4430_PERIPHMEM_STATEST_MASK                                 (0x3 << 8)
 
 /* Used by PRM_PHASE1_CNDP */
 #define OMAP4430_PHASE1_CNDP_SHIFT                                      0
-#define OMAP4430_PHASE1_CNDP_MASK                                       BITFIELD(0, 31)
+#define OMAP4430_PHASE1_CNDP_MASK                                       (0xffffffff << 0)
 
 /* Used by PRM_PHASE2A_CNDP */
 #define OMAP4430_PHASE2A_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2A_CNDP_MASK                                      BITFIELD(0, 31)
+#define OMAP4430_PHASE2A_CNDP_MASK                                      (0xffffffff << 0)
 
 /* Used by PRM_PHASE2B_CNDP */
 #define OMAP4430_PHASE2B_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2B_CNDP_MASK                                      BITFIELD(0, 31)
+#define OMAP4430_PHASE2B_CNDP_MASK                                      (0xffffffff << 0)
 
 /* Used by PRM_PSCON_COUNT */
 #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            8
-#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             BITFIELD(8, 15)
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             (0xff << 8)
 
 /*
- * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL,
- * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL,
- * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
- * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_POWERSTATE_SHIFT                                       0
-#define OMAP4430_POWERSTATE_MASK                                        BITFIELD(0, 1)
+#define OMAP4430_POWERSTATE_MASK                                        (0x3 << 0)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_POWERSTATEST_SHIFT                                     0
-#define OMAP4430_POWERSTATEST_MASK                                      BITFIELD(0, 1)
+#define OMAP4430_POWERSTATEST_MASK                                      (0x3 << 0)
 
 /* Used by PRM_PWRREQCTRL */
 #define OMAP4430_PWRREQ_COND_SHIFT                                      0
-#define OMAP4430_PWRREQ_COND_MASK                                       BITFIELD(0, 1)
+#define OMAP4430_PWRREQ_COND_MASK                                       (0x3 << 0)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 3
-#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  BITFIELD(3, 3)
+#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  (1 << 3)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  11
-#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   BITFIELD(11, 11)
+#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   (1 << 11)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  20
-#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   BITFIELD(20, 20)
+#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   (1 << 20)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   2
-#define OMAP4430_RAC_VDD_CORE_L_MASK                                    BITFIELD(2, 2)
+#define OMAP4430_RAC_VDD_CORE_L_MASK                                    (1 << 2)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    10
-#define OMAP4430_RAC_VDD_IVA_L_MASK                                     BITFIELD(10, 10)
+#define OMAP4430_RAC_VDD_IVA_L_MASK                                     (1 << 10)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    19
-#define OMAP4430_RAC_VDD_MPU_L_MASK                                     BITFIELD(19, 19)
+#define OMAP4430_RAC_VDD_MPU_L_MASK                                     (1 << 19)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -901,7 +917,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  16
-#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   BITFIELD(16, 21)
+#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   (0x3f << 16)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -909,7 +925,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                24
-#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 BITFIELD(24, 25)
+#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 (0x3 << 24)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -917,7 +933,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_UP_COUNT_SHIFT                                    0
-#define OMAP4430_RAMP_UP_COUNT_MASK                                     BITFIELD(0, 5)
+#define OMAP4430_RAMP_UP_COUNT_MASK                                     (0x3f << 0)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -925,1281 +941,1381 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  8
-#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   BITFIELD(8, 9)
+#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   (0x3 << 8)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   1
-#define OMAP4430_RAV_VDD_CORE_L_MASK                                    BITFIELD(1, 1)
+#define OMAP4430_RAV_VDD_CORE_L_MASK                                    (1 << 1)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    9
-#define OMAP4430_RAV_VDD_IVA_L_MASK                                     BITFIELD(9, 9)
+#define OMAP4430_RAV_VDD_IVA_L_MASK                                     (1 << 9)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    18
-#define OMAP4430_RAV_VDD_MPU_L_MASK                                     BITFIELD(18, 18)
+#define OMAP4430_RAV_VDD_MPU_L_MASK                                     (1 << 18)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_REGADDR_SHIFT                                          8
-#define OMAP4430_REGADDR_MASK                                           BITFIELD(8, 15)
+#define OMAP4430_REGADDR_MASK                                           (0xff << 8)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_RET_SHIFT                                              8
-#define OMAP4430_RET_MASK                                               BITFIELD(8, 15)
+#define OMAP4430_RET_MASK                                               (0xff << 8)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            16
-#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             BITFIELD(16, 17)
+#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             (0x3 << 16)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           8
-#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            BITFIELD(8, 8)
+#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            (1 << 8)
 
 /* Used by PM_L4PER_PWRSTST */
 #define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            4
-#define OMAP4430_RETAINED_BANK_STATEST_MASK                             BITFIELD(4, 5)
+#define OMAP4430_RETAINED_BANK_STATEST_MASK                             (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_RETMODE_ENABLE_SHIFT                                   0
-#define OMAP4430_RETMODE_ENABLE_MASK                                    BITFIELD(0, 0)
+#define OMAP4430_RETMODE_ENABLE_MASK                                    (1 << 0)
 
-/* Used by REVISION_PRM */
-#define OMAP4430_REV_SHIFT                                              0
-#define OMAP4430_REV_MASK                                               BITFIELD(0, 7)
-
-/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
 #define OMAP4430_RST1_SHIFT                                             0
-#define OMAP4430_RST1_MASK                                              BITFIELD(0, 0)
+#define OMAP4430_RST1_MASK                                              (1 << 0)
 
-/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
 #define OMAP4430_RST1ST_SHIFT                                           0
-#define OMAP4430_RST1ST_MASK                                            BITFIELD(0, 0)
+#define OMAP4430_RST1ST_MASK                                            (1 << 0)
 
-/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
 #define OMAP4430_RST2_SHIFT                                             1
-#define OMAP4430_RST2_MASK                                              BITFIELD(1, 1)
+#define OMAP4430_RST2_MASK                                              (1 << 1)
 
-/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
 #define OMAP4430_RST2ST_SHIFT                                           1
-#define OMAP4430_RST2ST_MASK                                            BITFIELD(1, 1)
+#define OMAP4430_RST2ST_MASK                                            (1 << 1)
 
 /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
 #define OMAP4430_RST3_SHIFT                                             2
-#define OMAP4430_RST3_MASK                                              BITFIELD(2, 2)
+#define OMAP4430_RST3_MASK                                              (1 << 2)
 
 /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
 #define OMAP4430_RST3ST_SHIFT                                           2
-#define OMAP4430_RST3ST_MASK                                            BITFIELD(2, 2)
+#define OMAP4430_RST3ST_MASK                                            (1 << 2)
 
 /* Used by PRM_RSTTIME */
 #define OMAP4430_RSTTIME1_SHIFT                                         0
-#define OMAP4430_RSTTIME1_MASK                                          BITFIELD(0, 9)
+#define OMAP4430_RSTTIME1_MASK                                          (0x3ff << 0)
 
 /* Used by PRM_RSTTIME */
 #define OMAP4430_RSTTIME2_SHIFT                                         10
-#define OMAP4430_RSTTIME2_MASK                                          BITFIELD(10, 14)
+#define OMAP4430_RSTTIME2_MASK                                          (0x1f << 10)
 
 /* Used by PRM_RSTCTRL */
 #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               1
-#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                BITFIELD(1, 1)
+#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                (1 << 1)
 
 /* Used by PRM_RSTCTRL */
 #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               0
-#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                BITFIELD(0, 0)
+#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                (1 << 0)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_R_RTL_SHIFT                                            11
+#define OMAP4430_R_RTL_MASK                                             (0x1f << 11)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_CORE_L_SHIFT                                    0
-#define OMAP4430_SA_VDD_CORE_L_MASK                                     BITFIELD(0, 0)
+#define OMAP4430_SA_VDD_CORE_L_MASK                                     (1 << 0)
 
 /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                0
-#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 BITFIELD(0, 6)
+#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 (0x7f << 0)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_IVA_L_SHIFT                                     8
-#define OMAP4430_SA_VDD_IVA_L_MASK                                      BITFIELD(8, 8)
+#define OMAP4430_SA_VDD_IVA_L_MASK                                      (1 << 8)
 
 /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      8
-#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(8, 14)
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 8)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_MPU_L_SHIFT                                     16
-#define OMAP4430_SA_VDD_MPU_L_MASK                                      BITFIELD(16, 16)
+#define OMAP4430_SA_VDD_MPU_L_MASK                                      (1 << 16)
 
 /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      16
-#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(16, 22)
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 16)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_SCHEME_SHIFT                                           30
+#define OMAP4430_SCHEME_MASK                                            (0x3 << 30)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLH_SHIFT                                             0
-#define OMAP4430_SCLH_MASK                                              BITFIELD(0, 7)
+#define OMAP4430_SCLH_MASK                                              (0xff << 0)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLL_SHIFT                                             8
-#define OMAP4430_SCLL_MASK                                              BITFIELD(8, 15)
+#define OMAP4430_SCLL_MASK                                              (0xff << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_SECURE_WDT_RST_SHIFT                                   4
-#define OMAP4430_SECURE_WDT_RST_MASK                                    BITFIELD(4, 4)
+#define OMAP4430_SECURE_WDT_RST_MASK                                    (1 << 4)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  18
-#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   BITFIELD(18, 19)
+#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   (0x3 << 18)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 9
-#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  (1 << 9)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_SL2_MEM_STATEST_SHIFT                                  6
-#define OMAP4430_SL2_MEM_STATEST_MASK                                   BITFIELD(6, 7)
+#define OMAP4430_SL2_MEM_STATEST_MASK                                   (0x3 << 6)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_SLAVEADDR_SHIFT                                        0
-#define OMAP4430_SLAVEADDR_MASK                                         BITFIELD(0, 6)
+#define OMAP4430_SLAVEADDR_MASK                                         (0x7f << 0)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    3
-#define OMAP4430_SLEEP_RBB_SEL_MASK                                     BITFIELD(3, 3)
+#define OMAP4430_SLEEP_RBB_SEL_MASK                                     (1 << 3)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_SLPCNT_VALUE_SHIFT                                     16
-#define OMAP4430_SLPCNT_VALUE_MASK                                      BITFIELD(16, 23)
+#define OMAP4430_SLPCNT_VALUE_MASK                                      (0xff << 16)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   BITFIELD(8, 23)
+#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   (0xffff << 8)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   BITFIELD(8, 23)
+#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   (0xffff << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT                                 1
+#define OMAP4430_SMPS_RA_ERR_CORE_MASK                                  (1 << 1)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT                                  9
+#define OMAP4430_SMPS_RA_ERR_IVA_MASK                                   (1 << 9)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT                                  17
+#define OMAP4430_SMPS_RA_ERR_MPU_MASK                                   (1 << 17)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT                                 0
+#define OMAP4430_SMPS_SA_ERR_CORE_MASK                                  (1 << 0)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT                                  8
+#define OMAP4430_SMPS_SA_ERR_IVA_MASK                                   (1 << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT                                  16
+#define OMAP4430_SMPS_SA_ERR_MPU_MASK                                   (1 << 16)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT                            2
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK                             (1 << 2)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT                             10
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK                              (1 << 10)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT                             18
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK                              (1 << 18)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SR2EN_SHIFT                                            0
-#define OMAP4430_SR2EN_MASK                                             BITFIELD(0, 0)
+#define OMAP4430_SR2EN_MASK                                             (1 << 0)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_SR2_IN_TRANSITION_SHIFT                                6
-#define OMAP4430_SR2_IN_TRANSITION_MASK                                 BITFIELD(6, 6)
+#define OMAP4430_SR2_IN_TRANSITION_MASK                                 (1 << 6)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_SR2_STATUS_SHIFT                                       3
-#define OMAP4430_SR2_STATUS_MASK                                        BITFIELD(3, 4)
+#define OMAP4430_SR2_STATUS_MASK                                        (0x3 << 3)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  8
-#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   (0xff << 8)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_SRAMLDO_STATUS_SHIFT                                   8
-#define OMAP4430_SRAMLDO_STATUS_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_SRAMLDO_STATUS_MASK                                    (1 << 8)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               9
-#define OMAP4430_SRAM_IN_TRANSITION_MASK                                BITFIELD(9, 9)
+#define OMAP4430_SRAM_IN_TRANSITION_MASK                                (1 << 9)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_SRMODEEN_SHIFT                                         4
-#define OMAP4430_SRMODEEN_MASK                                          BITFIELD(4, 4)
+#define OMAP4430_SRMODEEN_MASK                                          (1 << 4)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
 #define OMAP4430_STABLE_COUNT_SHIFT                                     0
-#define OMAP4430_STABLE_COUNT_MASK                                      BITFIELD(0, 5)
+#define OMAP4430_STABLE_COUNT_MASK                                      (0x3f << 0)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
 #define OMAP4430_STABLE_PRESCAL_SHIFT                                   8
-#define OMAP4430_STABLE_PRESCAL_MASK                                    BITFIELD(8, 9)
+#define OMAP4430_STABLE_PRESCAL_MASK                                    (0x3 << 8)
+
+/* Used by PRM_LDO_BANDGAP_SETUP */
+#define OMAP4430_STARTUP_COUNT_SHIFT                                    0
+#define OMAP4430_STARTUP_COUNT_MASK                                     (0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define OMAP4430_STARTUP_COUNT_24_31_SHIFT                              24
+#define OMAP4430_STARTUP_COUNT_24_31_MASK                               (0xff << 24)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 20
-#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  BITFIELD(20, 21)
+#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  (0x3 << 20)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                10
-#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 BITFIELD(10, 10)
+#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 (1 << 10)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 8
-#define OMAP4430_TCM1_MEM_STATEST_MASK                                  BITFIELD(8, 9)
+#define OMAP4430_TCM1_MEM_STATEST_MASK                                  (0x3 << 8)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 22
-#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  BITFIELD(22, 23)
+#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  (0x3 << 22)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                11
-#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 BITFIELD(11, 11)
+#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 (1 << 11)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 10
-#define OMAP4430_TCM2_MEM_STATEST_MASK                                  BITFIELD(10, 11)
+#define OMAP4430_TCM2_MEM_STATEST_MASK                                  (0x3 << 10)
 
 /* Used by RM_TESLA_RSTST */
 #define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                2
-#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 (1 << 2)
 
 /* Used by RM_TESLA_RSTST */
 #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          3
-#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           BITFIELD(3, 3)
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           (1 << 3)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               20
-#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                BITFIELD(20, 21)
+#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                (0x3 << 20)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              10
-#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               BITFIELD(10, 10)
+#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               (1 << 10)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               8
-#define OMAP4430_TESLA_EDMA_STATEST_MASK                                BITFIELD(8, 9)
+#define OMAP4430_TESLA_EDMA_STATEST_MASK                                (0x3 << 8)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 16
-#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  BITFIELD(16, 17)
+#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  (0x3 << 16)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                8
-#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 (1 << 8)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_L1_STATEST_SHIFT                                 4
-#define OMAP4430_TESLA_L1_STATEST_MASK                                  BITFIELD(4, 5)
+#define OMAP4430_TESLA_L1_STATEST_MASK                                  (0x3 << 4)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 18
-#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  BITFIELD(18, 19)
+#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  (0x3 << 18)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                9
-#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 BITFIELD(9, 9)
+#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 (1 << 9)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_L2_STATEST_SHIFT                                 6
-#define OMAP4430_TESLA_L2_STATEST_MASK                                  BITFIELD(6, 7)
+#define OMAP4430_TESLA_L2_STATEST_MASK                                  (0x3 << 6)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_TIMEOUT_SHIFT                                          0
-#define OMAP4430_TIMEOUT_MASK                                           BITFIELD(0, 15)
+#define OMAP4430_TIMEOUT_MASK                                           (0xffff << 0)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_TIMEOUTEN_SHIFT                                        3
-#define OMAP4430_TIMEOUTEN_MASK                                         BITFIELD(3, 3)
+#define OMAP4430_TIMEOUTEN_MASK                                         (1 << 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_TRANSITION_EN_SHIFT                                    8
-#define OMAP4430_TRANSITION_EN_MASK                                     BITFIELD(8, 8)
+#define OMAP4430_TRANSITION_EN_MASK                                     (1 << 8)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_TRANSITION_ST_SHIFT                                    8
-#define OMAP4430_TRANSITION_ST_MASK                                     BITFIELD(8, 8)
+#define OMAP4430_TRANSITION_ST_MASK                                     (1 << 8)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_VALID_SHIFT                                            24
-#define OMAP4430_VALID_MASK                                             BITFIELD(24, 24)
+#define OMAP4430_VALID_MASK                                             (1 << 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_EN_MASK                                   BITFIELD(14, 14)
+#define OMAP4430_VC_BYPASSACK_EN_MASK                                   (1 << 14)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_ST_MASK                                   BITFIELD(14, 14)
+#define OMAP4430_VC_BYPASSACK_ST_MASK                                   (1 << 14)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_CORE_VPACK_EN_SHIFT                                 22
+#define OMAP4430_VC_CORE_VPACK_EN_MASK                                  (1 << 22)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_CORE_VPACK_ST_SHIFT                                 22
+#define OMAP4430_VC_CORE_VPACK_ST_MASK                                  (1 << 22)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   BITFIELD(30, 30)
+#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   (1 << 30)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   BITFIELD(30, 30)
+#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   (1 << 30)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   BITFIELD(6, 6)
+#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   (1 << 6)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   BITFIELD(6, 6)
+#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   (1 << 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_RAERR_EN_SHIFT                                      12
-#define OMAP4430_VC_RAERR_EN_MASK                                       BITFIELD(12, 12)
+#define OMAP4430_VC_RAERR_EN_MASK                                       (1 << 12)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_RAERR_ST_SHIFT                                      12
-#define OMAP4430_VC_RAERR_ST_MASK                                       BITFIELD(12, 12)
+#define OMAP4430_VC_RAERR_ST_MASK                                       (1 << 12)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_SAERR_EN_SHIFT                                      11
-#define OMAP4430_VC_SAERR_EN_MASK                                       BITFIELD(11, 11)
+#define OMAP4430_VC_SAERR_EN_MASK                                       (1 << 11)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_SAERR_ST_SHIFT                                      11
-#define OMAP4430_VC_SAERR_ST_MASK                                       BITFIELD(11, 11)
+#define OMAP4430_VC_SAERR_ST_MASK                                       (1 << 11)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_TOERR_EN_SHIFT                                      13
-#define OMAP4430_VC_TOERR_EN_MASK                                       BITFIELD(13, 13)
+#define OMAP4430_VC_TOERR_EN_MASK                                       (1 << 13)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_TOERR_ST_SHIFT                                      13
-#define OMAP4430_VC_TOERR_ST_MASK                                       BITFIELD(13, 13)
+#define OMAP4430_VC_TOERR_ST_MASK                                       (1 << 13)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMAX_SHIFT                                           24
-#define OMAP4430_VDDMAX_MASK                                            BITFIELD(24, 31)
+#define OMAP4430_VDDMAX_MASK                                            (0xff << 24)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMIN_SHIFT                                           16
-#define OMAP4430_VDDMIN_MASK                                            BITFIELD(16, 23)
+#define OMAP4430_VDDMIN_MASK                                            (0xff << 16)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             12
-#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              BITFIELD(12, 12)
+#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              (1 << 12)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            8
-#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             BITFIELD(8, 8)
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             (1 << 8)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              14
-#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               BITFIELD(14, 14)
+#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               (1 << 14)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 9
-#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  (1 << 9)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             7
-#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              BITFIELD(7, 7)
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              (1 << 7)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              13
-#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               BITFIELD(13, 13)
+#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               (1 << 13)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 8
-#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  (1 << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             6
-#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              BITFIELD(6, 6)
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              (1 << 6)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT                                 4
+#define OMAP4430_VFSM_RA_ERR_CORE_MASK                                  (1 << 4)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT                                  12
+#define OMAP4430_VFSM_RA_ERR_IVA_MASK                                   (1 << 12)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT                                  20
+#define OMAP4430_VFSM_RA_ERR_MPU_MASK                                   (1 << 20)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT                                 3
+#define OMAP4430_VFSM_SA_ERR_CORE_MASK                                  (1 << 3)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT                                  11
+#define OMAP4430_VFSM_SA_ERR_IVA_MASK                                   (1 << 11)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT                                  19
+#define OMAP4430_VFSM_SA_ERR_MPU_MASK                                   (1 << 19)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT                            5
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK                             (1 << 5)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT                             13
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK                              (1 << 13)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT                             21
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK                              (1 << 21)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 0
-#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  (0xff << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  8
-#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   (0xff << 8)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  16
-#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   (0xff << 16)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_VPENABLE_SHIFT                                         0
-#define OMAP4430_VPENABLE_MASK                                          BITFIELD(0, 0)
+#define OMAP4430_VPENABLE_MASK                                          (1 << 0)
 
 /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
 #define OMAP4430_VPINIDLE_SHIFT                                         0
-#define OMAP4430_VPINIDLE_MASK                                          BITFIELD(0, 0)
+#define OMAP4430_VPINIDLE_MASK                                          (1 << 0)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
 #define OMAP4430_VPVOLTAGE_SHIFT                                        0
-#define OMAP4430_VPVOLTAGE_MASK                                         BITFIELD(0, 7)
+#define OMAP4430_VPVOLTAGE_MASK                                         (0xff << 0)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                BITFIELD(20, 20)
+#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                (1 << 20)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                BITFIELD(20, 20)
+#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                (1 << 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 BITFIELD(18, 18)
+#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 (1 << 18)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 BITFIELD(18, 18)
+#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 (1 << 18)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 BITFIELD(17, 17)
+#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 (1 << 17)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 BITFIELD(17, 17)
+#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 (1 << 17)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              BITFIELD(19, 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              (1 << 19)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              BITFIELD(19, 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              (1 << 19)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          BITFIELD(16, 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          (1 << 16)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          BITFIELD(16, 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          (1 << 16)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             21
-#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              BITFIELD(21, 21)
+#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              (1 << 21)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             21
-#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              BITFIELD(21, 21)
+#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              (1 << 21)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 BITFIELD(28, 28)
+#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 (1 << 28)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 BITFIELD(28, 28)
+#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 (1 << 28)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  BITFIELD(26, 26)
+#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  (1 << 26)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  BITFIELD(26, 26)
+#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  (1 << 26)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  BITFIELD(25, 25)
+#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  (1 << 25)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  BITFIELD(25, 25)
+#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  (1 << 25)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               BITFIELD(27, 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               (1 << 27)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               BITFIELD(27, 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               (1 << 27)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           BITFIELD(24, 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           (1 << 24)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           BITFIELD(24, 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           (1 << 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              29
-#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               BITFIELD(29, 29)
+#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               (1 << 29)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              29
-#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               BITFIELD(29, 29)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               (1 << 29)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  BITFIELD(2, 2)
+#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  (1 << 2)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  BITFIELD(2, 2)
+#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  (1 << 2)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  BITFIELD(1, 1)
+#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  (1 << 1)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  BITFIELD(1, 1)
+#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  (1 << 1)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               BITFIELD(3, 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               (1 << 3)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               BITFIELD(3, 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               (1 << 3)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           BITFIELD(0, 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           (1 << 0)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           BITFIELD(0, 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           (1 << 0)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              5
-#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               BITFIELD(5, 5)
+#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               (1 << 5)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              5
-#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               BITFIELD(5, 5)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               (1 << 5)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  8
-#define OMAP4430_VSETUPCNT_VALUE_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_VSETUPCNT_VALUE_MASK                                   (0xff << 8)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_VSTEPMAX_SHIFT                                         0
-#define OMAP4430_VSTEPMAX_MASK                                          BITFIELD(0, 7)
+#define OMAP4430_VSTEPMAX_MASK                                          (0xff << 0)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_VSTEPMIN_SHIFT                                         0
-#define OMAP4430_VSTEPMIN_MASK                                          BITFIELD(0, 7)
+#define OMAP4430_VSTEPMIN_MASK                                          (0xff << 0)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_WAKE_MODEM_SHIFT                                       0
-#define OMAP4430_WAKE_MODEM_MASK                                        BITFIELD(0, 0)
+#define OMAP4430_WAKE_MODEM_MASK                                        (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              (1 << 1)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               (1 << 2)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           6
-#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            (1 << 6)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           2
-#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            (1 << 2)
 
 /* Used by PM_L4PER_DMTIMER10_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         1
-#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER2_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              5
-#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               BITFIELD(5, 5)
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               (1 << 5)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 4
-#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  (1 << 4)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                7
-#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 (1 << 7)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               6
-#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                (1 << 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              9
-#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               BITFIELD(9, 9)
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               (1 << 9)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 8
-#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  (1 << 8)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                11
-#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 BITFIELD(11, 11)
+#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 (1 << 11)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               10
-#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                BITFIELD(10, 10)
+#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                (1 << 10)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         (1 << 1)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         (1 << 1)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             19
-#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              BITFIELD(19, 19)
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              (1 << 19)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           13
-#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            BITFIELD(13, 13)
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            (1 << 13)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              12
-#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               BITFIELD(12, 12)
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               (1 << 12)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            14
-#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             BITFIELD(14, 14)
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             (1 << 14)
 
 /* Used by PM_L4PER_HECC1_WKDEP */
 #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_HECC2_WKDEP */
 #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             (1 << 6)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
 #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
 #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_WKUP_KEYBOARD_WKDEP */
 #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              (1 << 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
 #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
 #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             7
-#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              (1 << 7)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             (1 << 6)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               (1 << 0)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            2
-#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             (1 << 2)
 
 /* Used by PM_WKUP_RTC_WKDEP */
 #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  0
-#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   (1 << 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
 #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
 #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         (1 << 7)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        (1 << 6)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          (1 << 0)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        (1 << 2)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         (1 << 7)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        (1 << 6)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          (1 << 0)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        (1 << 2)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
 #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
 #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               (1 << 0)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
 #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
 #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ALWON_SR_MPU_WKDEP */
 #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                (1 << 0)
 
 /* Used by PM_WKUP_TIMER12_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               (1 << 0)
 
 /* Used by PM_WKUP_TIMER1_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_UART1_WKDEP */
 #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART1_WKDEP */
 #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART2_WKDEP */
 #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART2_WKDEP */
 #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              (1 << 1)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               (1 << 2)
 
 /* Used by PM_L4PER_UART4_WKDEP */
 #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART4_WKDEP */
 #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
 #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
 #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       1
-#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        (1 << 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          0
-#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           (1 << 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
 #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
 #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
 #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
 #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               (1 << 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
 #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
 #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
 #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
 #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_ABE_WDT3_WKDEP */
 #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         8
-#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          BITFIELD(8, 8)
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          (1 << 8)
 
 /* Used by PM_L3INIT_XHPI_WKDEP */
 #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_WUCLK_CTRL_SHIFT                                       8
-#define OMAP4430_WUCLK_CTRL_MASK                                        BITFIELD(8, 8)
+#define OMAP4430_WUCLK_CTRL_MASK                                        (1 << 8)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_WUCLK_STATUS_SHIFT                                     9
-#define OMAP4430_WUCLK_STATUS_MASK                                      BITFIELD(9, 9)
+#define OMAP4430_WUCLK_STATUS_MASK                                      (1 << 9)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_X_MAJOR_SHIFT                                          8
+#define OMAP4430_X_MAJOR_MASK                                           (0x7 << 8)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_Y_MINOR_SHIFT                                          0
+#define OMAP4430_Y_MINOR_MASK                                           (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 588873b9303..7be040b2fda 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -5,7 +5,7 @@
  * OMAP2/3 Power/Reset Management (PRM) register definitions
  *
  * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2010 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -246,6 +246,15 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
         return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
 
+/* These omap2_ PRM functions apply to both OMAP2 and 3 */
+int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
+
+int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
+int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+
 #endif
 
 /*
@@ -398,4 +407,11 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
 
 
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT               10000
+
+
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
new file mode 100644
index 00000000000..421771eee45
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -0,0 +1,110 @@
+/*
+ * OMAP2/3 PRM module functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+
+#include <plat/common.h>
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
+
+/**
+ * omap2_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL if called while running on a non-OMAP2/3 chip.
+ */
+int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+{
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
+                                       (1 << shift));
+}
+
+/**
+ * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+{
+        u32 mask;
+
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        mask = 1 << shift;
+        prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
+
+        return 0;
+}
+
+/**
+ * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
+{
+        u32 mask;
+        int c;
+
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        mask = 1 << shift;
+
+        /* Check the current status to avoid de-asserting the line twice */
+        if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
+        /* de-assert the reset control line */
+        prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
+        /* wait the status to be set */
+        omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
+                                                  mask),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
+
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
new file mode 100644
index 00000000000..a1ff918d9be
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -0,0 +1,116 @@
+/*
+ * OMAP4 PRM module functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+
+#include <plat/common.h>
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "prm.h"
+#include "prm-regbits-44xx.h"
+
+/*
+ * Address offset (in bytes) between the reset control and the reset
+ * status registers: 4 bytes on OMAP4
+ */
+#define OMAP4_RST_CTRL_ST_OFFSET                4
+
+/**
+ * omap4_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
+{
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
+}
+
+/**
+ * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+{
+        u32 mask;
+
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        mask = 1 << shift;
+        omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
+
+        return 0;
+}
+
+/**
+ * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+{
+        u32 mask;
+        void __iomem *rstst_reg;
+        int c;
+
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
+
+        mask = 1 << shift;
+
+        /* Check the current status to avoid de-asserting the line twice */
+        if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
+        /* de-assert the reset control line */
+        omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
+        /* wait the status to be set */
+        omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
+
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index fe8ef26431e..59839dbabd8 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -44,14 +44,12 @@
 #define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
 #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET                0x0038
 #define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
-#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET          0x0040
-#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
+#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET           0x0040
+#define OMAP4430_CM_PRM_PROFILING_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
 
 /* PRM.CKGEN_PRM register offsets */
 #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET              0x0000
 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
-#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET             0x0004
-#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
 #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET                  0x0008
 #define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
 #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET              0x000c
@@ -686,8 +684,8 @@
 #define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
 #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET               0x00dc
 #define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
-#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET               0x00e0
-#define OMAP4430_PRM_LDO_BANDGAP_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
+#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET              0x00e0
+#define OMAP4430_PRM_LDO_BANDGAP_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
 #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET                0x00e4
 #define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
 #define OMAP4_PRM_PHASE1_CNDP_OFFSET                    0x00e8
@@ -698,6 +696,8 @@
 #define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
 #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET                  0x00f4
 #define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
+#define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
+#define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
 
 /*
  * PRCM_MPU
@@ -715,6 +715,8 @@
 /* PRCM_MPU.DEVICE_PRM register offsets */
 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
 #define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
+#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
+#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
 
 /* PRCM_MPU.CPU0 register offsets */
 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 566e991ede8..becf0e38ef7 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,20 +19,31 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/serial_8250.h>
+#include <linux/pm_runtime.h>
+
+#ifdef CONFIG_SERIAL_OMAP
+#include <plat/omap-serial.h>
+#endif
 
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/clock.h>
-#include <plat/control.h>
+#include <plat/dma.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 
 #include "prm.h"
 #include "pm.h"
+#include "cm.h"
 #include "prm-regbits-34xx.h"
+#include "control.h"
 
 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
@@ -48,6 +59,8 @@
  */
 #define DEFAULT_TIMEOUT 0
 
+#define MAX_UART_HWMOD_NAME_LEN         16
+
 struct omap_uart_state {
         int num;
         int can_sleep;
@@ -58,14 +71,21 @@ struct omap_uart_state {
         void __iomem *wk_en;
         u32 wk_mask;
         u32 padconf;
+        u32 dma_enabled;
 
         struct clk *ick;
         struct clk *fck;
         int clocked;
 
-        struct plat_serial8250_port *p;
+        int irq;
+        int regshift;
+        int irqflags;
+        void __iomem *membase;
+        resource_size_t mapbase;
+
         struct list_head node;
-        struct platform_device pdev;
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
 
         u32 errata;
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
@@ -83,75 +103,47 @@ struct omap_uart_state {
 };
 
 static LIST_HEAD(uart_list);
+static u8 num_uarts;
 
-static struct plat_serial8250_port serial_platform_data0[] = {
-        {
-                .irq            = 72,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+/*
+ * Since these idle/enable hooks are used in the idle path itself
+ * which has interrupts disabled, use the non-locking versions of
+ * the hwmod enable/disable functions.
+ */
+static int uart_idle_hwmod(struct omap_device *od)
+{
+        _omap_hwmod_idle(od->hwmods[0]);
 
-static struct plat_serial8250_port serial_platform_data1[] = {
-        {
-                .irq            = 73,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+        return 0;
+}
 
-static struct plat_serial8250_port serial_platform_data2[] = {
-        {
-                .irq            = 74,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+static int uart_enable_hwmod(struct omap_device *od)
+{
+        _omap_hwmod_enable(od->hwmods[0]);
 
-static struct plat_serial8250_port serial_platform_data3[] = {
+        return 0;
+}
+
+static struct omap_device_pm_latency omap_uart_latency[] = {
         {
-                .irq            = 70,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
+                .deactivate_func = uart_idle_hwmod,
+                .activate_func   = uart_enable_hwmod,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
 };
 
-void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
-{
-        serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
-        serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
-        serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
-        serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
-}
-
 static inline unsigned int __serial_read_reg(struct uart_port *up,
-                                           int offset)
+                                             int offset)
 {
         offset <<= up->regshift;
         return (unsigned int)__raw_readb(up->membase + offset);
 }
 
-static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
+static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
                                            int offset)
 {
-        offset <<= up->regshift;
-        return (unsigned int)__raw_readb(up->membase + offset);
+        offset <<= uart->regshift;
+        return (unsigned int)__raw_readb(uart->membase + offset);
 }
 
 static inline void __serial_write_reg(struct uart_port *up, int offset,
@@ -161,11 +153,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset,
         __raw_writeb(value, up->membase + offset);
 }
 
-static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
+static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
                                     int value)
 {
-        offset <<= p->regshift;
-        __raw_writeb(value, p->membase + offset);
+        offset <<= uart->regshift;
+        __raw_writeb(value, uart->membase + offset);
 }
 
 /*
@@ -173,14 +165,12 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
  * properly. Note that the TX watermark initialization may not be needed
  * once the 8250.c watermark handling code is merged.
  */
+
 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 {
-        struct plat_serial8250_port *p = uart->p;
-
-        serial_write_reg(p, UART_OMAP_MDR1, 0x07);
-        serial_write_reg(p, UART_OMAP_SCR, 0x08);
-        serial_write_reg(p, UART_OMAP_MDR1, 0x00);
-        serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
+        serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
+        serial_write_reg(uart, UART_OMAP_SCR, 0x08);
+        serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
 }
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
@@ -197,24 +187,23 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
                 u8 fcr_val)
 {
-        struct plat_serial8250_port *p = uart->p;
         u8 timeout = 255;
 
-        serial_write_reg(p, UART_OMAP_MDR1, mdr1_val);
+        serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
         udelay(2);
-        serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
+        serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
                         UART_FCR_CLEAR_RCVR);
         /*
          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
          * TX_FIFO_E bit is 1.
          */
-        while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) &
+        while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
                                 (UART_LSR_THRE | UART_LSR_DR))) {
                 timeout--;
                 if (!timeout) {
                         /* Should *never* happen. we warn and carry on */
-                        dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n",
-                                serial_read_reg(p, UART_LSR));
+                        dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
+                        serial_read_reg(uart, UART_LSR));
                         break;
                 }
                 udelay(1);
@@ -224,23 +213,22 @@ static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 static void omap_uart_save_context(struct omap_uart_state *uart)
 {
         u16 lcr = 0;
-        struct plat_serial8250_port *p = uart->p;
 
         if (!enable_off_mode)
                 return;
 
-        lcr = serial_read_reg(p, UART_LCR);
-        serial_write_reg(p, UART_LCR, 0xBF);
-        uart->dll = serial_read_reg(p, UART_DLL);
-        uart->dlh = serial_read_reg(p, UART_DLM);
-        serial_write_reg(p, UART_LCR, lcr);
-        uart->ier = serial_read_reg(p, UART_IER);
-        uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
-        uart->scr = serial_read_reg(p, UART_OMAP_SCR);
-        uart->wer = serial_read_reg(p, UART_OMAP_WER);
-        serial_write_reg(p, UART_LCR, 0x80);
-        uart->mcr = serial_read_reg(p, UART_MCR);
-        serial_write_reg(p, UART_LCR, lcr);
+        lcr = serial_read_reg(uart, UART_LCR);
+        serial_write_reg(uart, UART_LCR, 0xBF);
+        uart->dll = serial_read_reg(uart, UART_DLL);
+        uart->dlh = serial_read_reg(uart, UART_DLM);
+        serial_write_reg(uart, UART_LCR, lcr);
+        uart->ier = serial_read_reg(uart, UART_IER);
+        uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
+        uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
+        uart->wer = serial_read_reg(uart, UART_OMAP_WER);
+        serial_write_reg(uart, UART_LCR, 0x80);
+        uart->mcr = serial_read_reg(uart, UART_MCR);
+        serial_write_reg(uart, UART_LCR, lcr);
 
         uart->context_valid = 1;
 }
@@ -248,7 +236,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
 static void omap_uart_restore_context(struct omap_uart_state *uart)
 {
         u16 efr = 0;
-        struct plat_serial8250_port *p = uart->p;
 
         if (!enable_off_mode)
                 return;
@@ -261,29 +248,30 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
                 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
         else
-                serial_write_reg(p, UART_OMAP_MDR1, 0x7);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        efr = serial_read_reg(p, UART_EFR);
-        serial_write_reg(p, UART_EFR, UART_EFR_ECB);
-        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(p, UART_IER, 0x0);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        serial_write_reg(p, UART_DLL, uart->dll);
-        serial_write_reg(p, UART_DLM, uart->dlh);
-        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(p, UART_IER, uart->ier);
-        serial_write_reg(p, UART_LCR, 0x80);
-        serial_write_reg(p, UART_MCR, uart->mcr);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        serial_write_reg(p, UART_EFR, efr);
-        serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
-        serial_write_reg(p, UART_OMAP_SCR, uart->scr);
-        serial_write_reg(p, UART_OMAP_WER, uart->wer);
-        serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
+                serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
+        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        efr = serial_read_reg(uart, UART_EFR);
+        serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
+        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(uart, UART_IER, 0x0);
+        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(uart, UART_DLL, uart->dll);
+        serial_write_reg(uart, UART_DLM, uart->dlh);
+        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(uart, UART_IER, uart->ier);
+        serial_write_reg(uart, UART_LCR, 0x80);
+        serial_write_reg(uart, UART_MCR, uart->mcr);
+        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(uart, UART_EFR, efr);
+        serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
+        serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
+        serial_write_reg(uart, UART_OMAP_WER, uart->wer);
+        serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
                 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
         else
-                serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+                /* UART 16x mode */
+                serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
 }
 #else
 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
@@ -295,8 +283,7 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
         if (uart->clocked)
                 return;
 
-        clk_enable(uart->ick);
-        clk_enable(uart->fck);
+        omap_device_enable(uart->pdev);
         uart->clocked = 1;
         omap_uart_restore_context(uart);
 }
@@ -310,8 +297,7 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 
         omap_uart_save_context(uart);
         uart->clocked = 0;
-        clk_disable(uart->ick);
-        clk_disable(uart->fck);
+        omap_device_idle(uart->pdev);
 }
 
 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
@@ -349,18 +335,24 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 }
 
 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
-                                          int enable)
+                                               int enable)
 {
-        struct plat_serial8250_port *p = uart->p;
-        u16 sysc;
+        u8 idlemode;
 
-        sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
-        if (enable)
-                sysc |= 0x2 << 3;
-        else
-                sysc |= 0x1 << 3;
+        if (enable) {
+                /**
+                 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
+                 * in Smartidle Mode When Configured for DMA Operations.
+                 */
+                if (uart->dma_enabled)
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                else
+                        idlemode = HWMOD_IDLEMODE_SMART;
+        } else {
+                idlemode = HWMOD_IDLEMODE_NO;
+        }
 
-        serial_write_reg(p, UART_OMAP_SYSC, sysc);
+        omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 }
 
 static void omap_uart_block_sleep(struct omap_uart_state *uart)
@@ -377,7 +369,7 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
 
 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 {
-        if (device_may_wakeup(&uart->pdev.dev))
+        if (device_may_wakeup(&uart->pdev->dev))
                 omap_uart_enable_wakeup(uart);
         else
                 omap_uart_disable_wakeup(uart);
@@ -472,6 +464,7 @@ int omap_uart_can_sleep(void)
  * UART will not idle or sleep for its timeout period.
  *
  **/
+/* static int first_interrupt; */
 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 {
         struct omap_uart_state *uart = dev_id;
@@ -483,7 +476,6 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 
 static void omap_uart_idle_init(struct omap_uart_state *uart)
 {
-        struct plat_serial8250_port *p = uart->p;
         int ret;
 
         uart->can_sleep = 0;
@@ -495,7 +487,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
         omap_uart_smart_idle_enable(uart, 0);
 
         if (cpu_is_omap34xx()) {
-                u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
+                u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
                 u32 wk_mask = 0;
                 u32 padconf = 0;
 
@@ -514,19 +506,17 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                         wk_mask = OMAP3430_ST_UART3_MASK;
                         padconf = 0x19e;
                         break;
+                case 3:
+                        wk_mask = OMAP3630_ST_UART4_MASK;
+                        padconf = 0x0d2;
+                        break;
                 }
                 uart->wk_mask = wk_mask;
                 uart->padconf = padconf;
         } else if (cpu_is_omap24xx()) {
                 u32 wk_mask = 0;
+                u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 
-                if (cpu_is_omap2430()) {
-                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
-                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
-                } else if (cpu_is_omap2420()) {
-                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
-                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
-                }
                 switch (uart->num) {
                 case 0:
                         wk_mask = OMAP24XX_ST_UART1_MASK;
@@ -535,10 +525,19 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                         wk_mask = OMAP24XX_ST_UART2_MASK;
                         break;
                 case 2:
+                        wk_en = OMAP24XX_PM_WKEN2;
+                        wk_st = OMAP24XX_PM_WKST2;
                         wk_mask = OMAP24XX_ST_UART3_MASK;
                         break;
                 }
                 uart->wk_mask = wk_mask;
+                if (cpu_is_omap2430()) {
+                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
+                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
+                } else if (cpu_is_omap2420()) {
+                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
+                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
+                }
         } else {
                 uart->wk_en = NULL;
                 uart->wk_st = NULL;
@@ -546,9 +545,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        p->irqflags |= IRQF_SHARED;
-        ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
-                          "serial idle", (void *)uart);
+        uart->irqflags |= IRQF_SHARED;
+        ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
+                                   IRQF_SHARED, "serial idle", (void *)uart);
         WARN_ON(ret);
 }
 
@@ -558,11 +557,17 @@ void omap_uart_enable_irqs(int enable)
         struct omap_uart_state *uart;
 
         list_for_each_entry(uart, &uart_list, node) {
-                if (enable)
-                        ret = request_irq(uart->p->irq, omap_uart_interrupt,
-                                IRQF_SHARED, "serial idle", (void *)uart);
-                else
-                        free_irq(uart->p->irq, (void *)uart);
+                if (enable) {
+                        pm_runtime_put_sync(&uart->pdev->dev);
+                        ret = request_threaded_irq(uart->irq, NULL,
+                                                   omap_uart_interrupt,
+                                                   IRQF_SHARED,
+                                                   "serial idle",
+                                                   (void *)uart);
+                } else {
+                        pm_runtime_get_noresume(&uart->pdev->dev);
+                        free_irq(uart->irq, (void *)uart);
+                }
         }
 }
 
@@ -570,10 +575,9 @@ static ssize_t sleep_timeout_show(struct device *dev,
                                   struct device_attribute *attr,
                                   char *buf)
 {
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        struct omap_uart_state *uart = container_of(pdev,
-                                        struct omap_uart_state, pdev);
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *odev = to_omap_device(pdev);
+        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 
         return sprintf(buf, "%u\n", uart->timeout / HZ);
 }
@@ -582,10 +586,9 @@ static ssize_t sleep_timeout_store(struct device *dev,
                                    struct device_attribute *attr,
                                    const char *buf, size_t n)
 {
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        struct omap_uart_state *uart = container_of(pdev,
-                                        struct omap_uart_state, pdev);
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *odev = to_omap_device(pdev);
+        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
@@ -608,48 +611,15 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+static void omap_uart_block_sleep(struct omap_uart_state *uart)
+{
+        /* Needed to enable UART clocks when built without CONFIG_PM */
+        omap_uart_enable_clocks(uart);
+}
 #define DEV_CREATE_FILE(dev, attr)
 #endif /* CONFIG_PM */
 
-static struct omap_uart_state omap_uart[] = {
-        {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data0,
-                        },
-                },
-        }, {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM1,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data1,
-                        },
-                },
-        }, {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM2,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data2,
-                        },
-                },
-        },
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = 3,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data3,
-                        },
-                },
-        },
-#endif
-};
-
+#ifndef CONFIG_SERIAL_OMAP
 /*
  * Override the default 8250 read handler: mem_serial_in()
  * Empty RX fifo read causes an abort on omap3630 and omap4
@@ -682,71 +652,44 @@ static void serial_out_override(struct uart_port *up, int offset, int value)
         }
         __serial_write_reg(up, offset, value);
 }
+#endif
+
 void __init omap_serial_early_init(void)
 {
-        int i, nr_ports;
-        char name[16];
+        int i = 0;
 
-        if (!(cpu_is_omap3630() || cpu_is_omap4430()))
-                nr_ports = 3;
-        else
-                nr_ports = ARRAY_SIZE(omap_uart);
+        do {
+                char oh_name[MAX_UART_HWMOD_NAME_LEN];
+                struct omap_hwmod *oh;
+                struct omap_uart_state *uart;
 
-        /*
-         * Make sure the serial ports are muxed on at this point.
-         * You have to mux them off in device drivers later on
-         * if not needed.
-         */
+                snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
+                         "uart%d", i + 1);
+                oh = omap_hwmod_lookup(oh_name);
+                if (!oh)
+                        break;
 
-        for (i = 0; i < nr_ports; i++) {
-                struct omap_uart_state *uart = &omap_uart[i];
-                struct platform_device *pdev = &uart->pdev;
-                struct device *dev = &pdev->dev;
-                struct plat_serial8250_port *p = dev->platform_data;
+                uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
+                if (WARN_ON(!uart))
+                        return;
+
+                uart->oh = oh;
+                uart->num = i++;
+                list_add_tail(&uart->node, &uart_list);
+                num_uarts++;
 
-                /* Don't map zero-based physical address */
-                if (p->mapbase == 0) {
-                        dev_warn(dev, "no physical address for uart#%d,"
-                                 " so skipping early_init...\n", i);
-                        continue;
-                }
                 /*
-                 * Module 4KB + L4 interconnect 4KB
-                 * Static mapping, never released
+                 * NOTE: omap_hwmod_init() has not yet been called,
+                 *       so no hwmod functions will work yet.
                  */
-                p->membase = ioremap(p->mapbase, SZ_8K);
-                if (!p->membase) {
-                        dev_err(dev, "ioremap failed for uart%i\n", i + 1);
-                        continue;
-                }
-
-                sprintf(name, "uart%d_ick", i + 1);
-                uart->ick = clk_get(NULL, name);
-                if (IS_ERR(uart->ick)) {
-                        dev_err(dev, "Could not get uart%d_ick\n", i + 1);
-                        uart->ick = NULL;
-                }
 
-                sprintf(name, "uart%d_fck", i+1);
-                uart->fck = clk_get(NULL, name);
-                if (IS_ERR(uart->fck)) {
-                        dev_err(dev, "Could not get uart%d_fck\n", i + 1);
-                        uart->fck = NULL;
-                }
-
-                /* FIXME: Remove this once the clkdev is ready */
-                if (!cpu_is_omap44xx()) {
-                        if (!uart->ick || !uart->fck)
-                                continue;
-                }
-
-                uart->num = i;
-                p->private_data = uart;
-                uart->p = p;
-
-                if (cpu_is_omap44xx())
-                        p->irq += 32;
-        }
+                /*
+                 * During UART early init, device need to be probed
+                 * to determine SoC specific init before omap_device
+                 * is ready.  Therefore, don't allow idle here
+                 */
+                uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+        } while (1);
 }
 
 /**
@@ -763,53 +706,135 @@ void __init omap_serial_early_init(void)
 void __init omap_serial_init_port(int port)
 {
         struct omap_uart_state *uart;
-        struct platform_device *pdev;
-        struct device *dev;
-
-        BUG_ON(port < 0);
-        BUG_ON(port >= ARRAY_SIZE(omap_uart));
-
-        uart = &omap_uart[port];
-        pdev = &uart->pdev;
-        dev = &pdev->dev;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        void *pdata = NULL;
+        u32 pdata_size = 0;
+        char *name;
+#ifndef CONFIG_SERIAL_OMAP
+        struct plat_serial8250_port ports[2] = {
+                {},
+                {.flags = 0},
+        };
+        struct plat_serial8250_port *p = &ports[0];
+#else
+        struct omap_uart_port_info omap_up;
+#endif
 
-        /* Don't proceed if there's no clocks available */
-        if (unlikely(!uart->ick || !uart->fck)) {
-                WARN(1, "%s: can't init uart%d, no clocks available\n",
-                     kobject_name(&dev->kobj), port);
+        if (WARN_ON(port < 0))
+                return;
+        if (WARN_ON(port >= num_uarts))
                 return;
-        }
-
-        omap_uart_enable_clocks(uart);
-
-        omap_uart_reset(uart);
-        omap_uart_idle_init(uart);
 
-        list_add_tail(&uart->node, &uart_list);
+        list_for_each_entry(uart, &uart_list, node)
+                if (port == uart->num)
+                        break;
 
-        if (WARN_ON(platform_device_register(pdev)))
-                return;
+        oh = uart->oh;
+        uart->dma_enabled = 0;
+#ifndef CONFIG_SERIAL_OMAP
+        name = "serial8250";
 
-        if ((cpu_is_omap34xx() && uart->padconf) ||
-            (uart->wk_en && uart->wk_mask)) {
-                device_init_wakeup(dev, true);
-                DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
-        }
+        /*
+         * !! 8250 driver does not use standard IORESOURCE* It
+         * has it's own custom pdata that can be taken from
+         * the hwmod resource data.  But, this needs to be
+         * done after the build.
+         *
+         * ?? does it have to be done before the register ??
+         * YES, because platform_device_data_add() copies
+         * pdata, it does not use a pointer.
+         */
+        p->flags = UPF_BOOT_AUTOCONF;
+        p->iotype = UPIO_MEM;
+        p->regshift = 2;
+        p->uartclk = OMAP24XX_BASE_BAUD * 16;
+        p->irq = oh->mpu_irqs[0].irq;
+        p->mapbase = oh->slaves[0]->addr->pa_start;
+        p->membase = omap_hwmod_get_mpu_rt_va(oh);
+        p->irqflags = IRQF_SHARED;
+        p->private_data = uart;
 
         /*
          * omap44xx: Never read empty UART fifo
          * omap3xxx: Never read empty UART fifo on UARTs
          * with IP rev >=0x52
          */
+        uart->regshift = p->regshift;
+        uart->membase = p->membase;
         if (cpu_is_omap44xx())
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+        else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 
         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
-                uart->p->serial_in = serial_in_override;
-                uart->p->serial_out = serial_out_override;
+                p->serial_in = serial_in_override;
+                p->serial_out = serial_out_override;
+        }
+
+        pdata = &ports[0];
+        pdata_size = 2 * sizeof(struct plat_serial8250_port);
+#else
+
+        name = DRIVER_NAME;
+
+        omap_up.dma_enabled = uart->dma_enabled;
+        omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
+        omap_up.mapbase = oh->slaves[0]->addr->pa_start;
+        omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
+        omap_up.irqflags = IRQF_SHARED;
+        omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+
+        pdata = &omap_up;
+        pdata_size = sizeof(struct omap_uart_port_info);
+#endif
+
+        if (WARN_ON(!oh))
+                return;
+
+        od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
+                               omap_uart_latency,
+                               ARRAY_SIZE(omap_uart_latency), false);
+        WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
+             name, oh->name);
+
+        uart->irq = oh->mpu_irqs[0].irq;
+        uart->regshift = 2;
+        uart->mapbase = oh->slaves[0]->addr->pa_start;
+        uart->membase = omap_hwmod_get_mpu_rt_va(oh);
+        uart->pdev = &od->pdev;
+
+        oh->dev_attr = uart;
+
+        /*
+         * Because of early UART probing, UART did not get idled
+         * on init.  Now that omap_device is ready, ensure full idle
+         * before doing omap_device_enable().
+         */
+        omap_hwmod_idle(uart->oh);
+
+        omap_device_enable(uart->pdev);
+        omap_uart_idle_init(uart);
+        omap_uart_reset(uart);
+        omap_hwmod_enable_wakeup(uart->oh);
+        omap_device_idle(uart->pdev);
+
+        /*
+         * Need to block sleep long enough for interrupt driven
+         * driver to start.  Console driver is in polling mode
+         * so device needs to be kept enabled while polling driver
+         * is in use.
+         */
+        if (uart->timeout)
+                uart->timeout = (30 * HZ);
+        omap_uart_block_sleep(uart);
+        uart->timeout = DEFAULT_TIMEOUT;
+
+        if ((cpu_is_omap34xx() && uart->padconf) ||
+            (uart->wk_en && uart->wk_mask)) {
+                device_init_wakeup(&od->pdev.dev, true);
+                DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
         }
 
         /* Enable the MDR1 errata for OMAP3 */
@@ -826,13 +851,8 @@ void __init omap_serial_init_port(int port)
  */
 void __init omap_serial_init(void)
 {
-        int i, nr_ports;
-
-        if (!(cpu_is_omap3630() || cpu_is_omap4430()))
-                nr_ports = 3;
-        else
-                nr_ports = ARRAY_SIZE(omap_uart);
+        struct omap_uart_state *uart;
 
-        for (i = 0; i < nr_ports; i++)
-                omap_serial_init_port(i);
+        list_for_each_entry(uart, &uart_list, node)
+                omap_serial_init_port(uart->num);
 }
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index ba53191ae4c..2fb205a7f28 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -27,11 +27,11 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
-#include <plat/control.h>
 
 #include "cm.h"
 #include "prm.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define SDRC_SCRATCHPAD_SEM_V   0xfa00291c
 
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index de99ba2a57a..3637274af5b 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll)
         ldr     r4, [sp, #80]
         str     r4, omap_sdrc_mr_1_val
 skip_cs1_params:
+        mrc     p15, 0, r8, c1, c0, 0   @ read ctrl register
+        bic     r10, r8, #0x800         @ clear Z-bit, disable branch prediction
+        mcr     p15, 0, r10, c1, c0, 0  @ write ctrl register
         dsb                             @ flush buffered writes to interconnect
-
+        isb                             @ prevent speculative exec past here
         cmp     r3, #1                  @ if increasing SDRC clk rate,
         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
         cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
@@ -148,6 +151,7 @@ skip_cs1_params:
         beq     return_to_sdram         @ return to SDRAM code, otherwise,
         bl      configure_sdrc          @ reprogram SDRC regs now
 return_to_sdram:
+        mcr     p15, 0, r8, c1, c0, 0   @ restore ctrl register
         isb                             @ prevent speculative exec past here
         mov     r0, #0                  @ return value
         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8491f..e13c29eecf2 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -40,6 +40,8 @@
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 
+#include "timer-gp.h"
+
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
 
@@ -228,8 +230,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-        BUG_ON(!twd_base);
+        if (cpu_is_omap44xx()) {
+                twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+                BUG_ON(!twd_base);
+        }
 #endif
         omap_dm_timer_init();
 
diff --git a/arch/arm/plat-omap/include/plat/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
index c88d346b59d..5c1072c6783 100644
--- a/arch/arm/plat-omap/include/plat/timer-gp.h
+++ b/arch/arm/mach-omap2/timer-gp.h
@@ -11,7 +11,6 @@
 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
 
-int __init omap2_gp_clockevent_set_gptimer(u8 id);
+extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
 
 #endif
-
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
index a216d88b04b..1481078763b 100644
--- a/arch/arm/mach-omap2/usb-fs.c
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -29,18 +29,18 @@
 
 #include <asm/irq.h>
 
-#include <plat/control.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 
+#include "control.h"
+#include "mux.h"
+
 #define INT_USB_IRQ_GEN         INT_24XX_USB_IRQ_GEN
 #define INT_USB_IRQ_NISO        INT_24XX_USB_IRQ_NISO
 #define INT_USB_IRQ_ISO         INT_24XX_USB_IRQ_ISO
 #define INT_USB_IRQ_HGEN        INT_24XX_USB_IRQ_HGEN
 #define INT_USB_IRQ_OTG         INT_24XX_USB_IRQ_OTG
 
-#include "mux.h"
-
 #if defined(CONFIG_ARCH_OMAP2)
 
 #ifdef  CONFIG_USB_GADGET_OMAP
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 33a5cde1c22..72605584bff 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -28,6 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/am35xx.h>
 #include <plat/usb.h>
 
 #ifdef CONFIG_USB_MUSB_SOC
@@ -89,6 +90,9 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
 {
         if (cpu_is_omap243x()) {
                 musb_resources[0].start = OMAP243X_HS_BASE;
+        } else if (cpu_is_omap3517() || cpu_is_omap3505()) {
+                musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;
+                musb_resources[1].start = INT_35XX_USBOTG_IRQ;
         } else if (cpu_is_omap34xx()) {
                 musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
         } else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 7130904ad99..b1c451f5ee2 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -336,8 +336,6 @@ static void __init d2net_init(void)
 
 #ifdef CONFIG_MACH_D2NET
 MACHINE_START(D2NET, "LaCie d2 Network")
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
@@ -349,8 +347,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BIGDISK
 MACHINE_START(BIGDISK, "LaCie Big Disk Network")
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index d318bea2af9..df1083f5b6e 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -358,8 +358,6 @@ static void __init db88f5281_init(void)
 
 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
         /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = db88f5281_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index a47100d46a4..3a7bc0e3698 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -730,8 +730,6 @@ static void __init dns323_init(void)
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
 MACHINE_START(DNS323, "D-Link DNS-323")
         /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = dns323_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index b24ee0c2cd6..ba98459f44b 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -251,8 +251,6 @@ static void __init edmini_v2_init(void)
 /* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
 MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
         /* Maintainer: Christopher Moore <moore@free.fr> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = edmini_v2_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S
index 91e0e39bb23..5e3bf5b68ae 100644
--- a/arch/arm/mach-orion5x/include/mach/debug-macro.S
+++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S
@@ -10,12 +10,11 @@
 
 #include <mach/orion5x.h>
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =ORION5X_REGS_PHYS_BASE
-        ldrne   \rx, =ORION5X_REGS_VIRT_BASE
-        orr     \rx, \rx, #0x00012000
+        .macro  addruart, rp, rv
+        ldr     \rp, =ORION5X_REGS_PHYS_BASE
+        ldr     \rv, =ORION5X_REGS_VIRT_BASE
+        orr     \rp, \rp, #0x00012000
+        orr     \rv, \rv, #0x00012000
         .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index dfbb68df7b0..4be9aa08de6 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -379,8 +379,6 @@ static void __init kurobox_pro_init(void)
 #ifdef CONFIG_MACH_KUROBOX_PRO
 MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
@@ -393,8 +391,6 @@ MACHINE_END
 #ifdef CONFIG_MACH_LINKSTATION_PRO
 MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
         /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 8e569be6e2c..437364b7168 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -265,8 +265,6 @@ static void __init ls_hgl_init(void)
 
 MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
         /* Maintainer: Zhu Qingsen <zhuqs@cn.fujistu.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = ls_hgl_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index c704f056de1..ab9b0cf0a90 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -267,8 +267,6 @@ static void __init lsmini_init(void)
 #ifdef CONFIG_MACH_LINKSTATION_MINI
 MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
         /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = lsmini_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 61c086b6672..2f0e16cd7e8 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -261,8 +261,6 @@ static void __init mss2_init(void)
 
 MACHINE_START(MSS2, "Maxtor Shared Storage II")
         /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = mss2_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 97c9ccb2ac6..b3d90f25de9 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -229,8 +229,6 @@ static void __init mv2120_init(void)
 /* Warning: HP uses a wrong mach-type (=526) in their bootloader */
 MACHINE_START(MV2120, "HP Media Vault mv2120")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = mv2120_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 7bd6283476f..d6665b31665 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -419,8 +419,6 @@ static void __init net2big_init(void)
 
 /* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
 MACHINE_START(NET2BIG, "LaCie 2Big Network")
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = net2big_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 9c1ca41730b..f4c26fd731f 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -169,8 +169,6 @@ subsys_initcall(rd88f5181l_fxo_pci_init);
 
 MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
         /* Maintainer: Nicolas Pitre <nico@marvell.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5181l_fxo_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index ee1399ff0ce..b5942909bab 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -181,8 +181,6 @@ subsys_initcall(rd88f5181l_ge_pci_init);
 
 MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5181l_ge_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index a04f9e4b633..165ed87029b 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -305,8 +305,6 @@ static void __init rd88f5182_init(void)
 
 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5182_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 7737cf9a8f5..02ff45f3e2e 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -123,8 +123,6 @@ subsys_initcall(rd88f6183ap_ge_pci_init);
 
 MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6183ap_ge_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 0b101d7d41c..4403fae5ab0 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -358,8 +358,6 @@ static void __init tsp2_init(void)
 
 MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
         /* Maintainer:  Sylver Bruneau <sylver.bruneau@googlemail.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = tsp2_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9d689051419..1e196129d76 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -322,8 +322,6 @@ static void __init qnap_ts209_init(void)
 
 MACHINE_START(TS209, "QNAP TS-109/TS-209")
         /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts209_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index d85588ac7ef..428af2046e3 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -311,8 +311,6 @@ static void __init qnap_ts409_init(void)
 
 MACHINE_START(TS409, "QNAP TS-409")
         /* Maintainer:  Sylver Bruneau <sylver.bruneau@gmail.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts409_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 696b1a97f9e..16f1bd5324b 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -550,8 +550,6 @@ static void __init ts78xx_init(void)
 
 MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
         /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = ts78xx_init,
         .map_io         = ts78xx_map_io,
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 69208217b22..7994d6ec08a 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -172,8 +172,6 @@ subsys_initcall(wnr854t_pci_init);
 
 MACHINE_START(WNR854T, "Netgear WNR854T")
         /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = wnr854t_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index f9f222ebb7e..a5989b7eb53 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -260,8 +260,6 @@ subsys_initcall(wrt350n_v2_pci_init);
 
 MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
-        .phys_io        = ORION5X_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = wrt350n_v2_init,
         .map_io         = orion5x_map_io,
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 45734bb880a..63399755f19 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -264,8 +264,6 @@ extern struct sys_timer pnx4008_timer;
 
 MACHINE_START(PNX4008, "Philips PNX4008")
         /* Maintainer: MontaVista Software Inc. */
-        .phys_io                = 0x40090000,
-        .io_pg_offst            = (0xf4090000 >> 18) & 0xfffc,
         .boot_params            = 0x80000100,
         .map_io                 = pnx4008_map_io,
         .init_irq               = pnx4008_init_irq,
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
index 6ca8bd30bf4..931afebaf06 100644
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
@@ -11,12 +11,10 @@
  *
 */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                mov     \rx, #0x00090000
-                addeq   \rx, \rx, #0x40000000
-                addne   \rx, \rx, #0xf4000000
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00090000
+                add     \rv, \rp, #0xf4000000   @ virtual
+                add     \rp, \rp, #0x40000000   @ physical
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
index 2ad398378ae..31b65ee07b0 100644
--- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h
+++ b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 7aefb907485..dd235ecc9d6 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -8,19 +8,16 @@ config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform (aka Lubbock)"
         select PXA25x
         select SA1111
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_MAINSTONE
         bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_ZYLONITE
         bool
         select PXA3xx
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_ZYLONITE300
         bool "PXA3xx Development Platform (aka Zylonite) PXA300/310"
@@ -44,6 +41,10 @@ config MACH_TAVOREVB
         select PXA3xx
         select CPU_PXA930
 
+config MACH_TAVOREVB3
+        bool "PXA95x Development Platform (aka TavorEVB III)"
+        select CPU_PXA950
+
 config MACH_SAAR
         bool "PXA930 Handheld Platform (aka SAAR)"
         select PXA3xx
@@ -61,7 +62,6 @@ config ARCH_VIPER
         select ISA
         select I2C_GPIO
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
         select PXA_HAVE_ISA_IRQS
         select ARCOM_PCMCIA
 
@@ -69,7 +69,6 @@ config MACH_ARCOM_ZEUS
         bool "Arcom/Eurotech ZEUS SBC"
         select PXA27x
         select ISA
-        select PXA_HAVE_BOARD_IRQS
         select PXA_HAVE_ISA_IRQS
         select ARCOM_PCMCIA
 
@@ -77,7 +76,6 @@ config MACH_BALLOON3
         bool "Balloon 3 board"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_CSB726
         bool "Enable Cogent CSB726 System On a Module"
@@ -140,13 +138,11 @@ config MACH_INTELMOTE2
         bool "Intel Mote 2 Platform"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_STARGATE2
         bool "Intel Stargate 2 Platform"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_XCEP
         bool "Iskratel Electronics XCEP"
@@ -206,13 +202,11 @@ config MACH_LOGICPD_PXA270
         bool "LogicPD PXA270 Card Engine Development Platform"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_PCM027
         bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
         select PXA27x
         select IWMMXT
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_PCM990_BASEBOARD
         bool "PHYTEC PCM-990 development board"
@@ -247,7 +241,6 @@ config MACH_COLIBRI_PXA270_INCOME
         depends on MACH_COLIBRI
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_COLIBRI300
         bool "Toradex Colibri PXA300/310"
@@ -274,7 +267,6 @@ config MACH_H4700
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_H5000
         bool "HP iPAQ h5000"
@@ -289,7 +281,6 @@ config MACH_MAGICIAN
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_MIOA701
         bool "Mitac Mio A701 Support"
@@ -307,7 +298,6 @@ config PXA_EZX
         select PXA27x
         select IWMMXT
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_EZX_A780
         bool "Motorola EZX A780"
@@ -478,7 +468,6 @@ config MACH_POODLE
         depends on PXA_SHARPSL
         select PXA25x
         select SHARP_LOCOMO
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_CORGI
         bool "Enable Sharp SL-C700 (Corgi) Support"
@@ -523,7 +512,6 @@ config MACH_TOSA
         bool "Enable Sharp SL-6000x (Tosa) Support"
         depends on PXA_SHARPSL
         select PXA25x
-        select PXA_HAVE_BOARD_IRQS
 
 config TOSA_BT
         tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
@@ -552,7 +540,6 @@ config MACH_ICONTROL
 config ARCH_PXA_ESERIES
         bool "PXA based Toshiba e-series PDAs"
         select PXA25x
-        select PXA_HAVE_BOARD_IRQS
 
 config MACH_E330
         bool "Toshiba e330"
@@ -606,7 +593,6 @@ config MACH_ZIPIT2
         bool "Zipit Z2 Handheld"
         select PXA27x
         select HAVE_PWM
-        select PXA_HAVE_BOARD_IRQS
 
 endmenu
 
@@ -643,6 +629,7 @@ config CPU_PXA300
 config CPU_PXA310
         bool
         select CPU_PXA300
+        select PXA310_ULPI if USB_ULPI
         help
           PXA310 (codename Monahans-LV)
 
@@ -692,10 +679,10 @@ config SHARPSL_PM_MAX1111
         select HWMON
         select SENSORS_MAX1111
 
-config PXA_HAVE_BOARD_IRQS
+config PXA_HAVE_ISA_IRQS
         bool
 
-config PXA_HAVE_ISA_IRQS
+config PXA310_ULPI
         bool
 
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 85c7fb324db..e2f89c2c6f4 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -18,7 +18,7 @@ endif
 # SoC-specific code
 obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
 obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa2xx.o pxa27x.o
-obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o
+obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
@@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_ZYLONITE300)	+= zylonite.o zylonite_pxa300.o
 obj-$(CONFIG_MACH_ZYLONITE320)  += zylonite.o zylonite_pxa320.o
 obj-$(CONFIG_MACH_LITTLETON)    += littleton.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
+obj-$(CONFIG_MACH_TAVOREVB3)    += tavorevb3.o
 obj-$(CONFIG_MACH_SAAR)         += saar.o
 
 # 3rd Party Dev Platforms
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 9041340fee1..21e18890193 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -68,42 +68,6 @@ static unsigned long balloon3_pin_config[] __initdata = {
 
         /* Reset, configured as GPIO wakeup source */
         GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
-
-        /* LEDs */
-        GPIO9_GPIO,     /* NAND activity LED */
-        GPIO10_GPIO,    /* Heartbeat LED */
-
-        /* AC97 */
-        GPIO28_AC97_BITCLK,
-        GPIO29_AC97_SDATA_IN_0,
-        GPIO30_AC97_SDATA_OUT,
-        GPIO31_AC97_SYNC,
-        GPIO113_AC97_nRESET,
-        GPIO95_GPIO,
-
-        /* MMC */
-        GPIO32_MMC_CLK,
-        GPIO92_MMC_DAT_0,
-        GPIO109_MMC_DAT_1,
-        GPIO110_MMC_DAT_2,
-        GPIO111_MMC_DAT_3,
-        GPIO112_MMC_CMD,
-
-        /* USB Host */
-        GPIO88_USBH1_PWR,
-        GPIO89_USBH1_PEN,
-
-        /* PC Card */
-        GPIO48_nPOE,
-        GPIO49_nPWE,
-        GPIO50_nPIOR,
-        GPIO51_nPIOW,
-        GPIO85_nPCE_1,
-        GPIO54_nPCE_2,
-        GPIO79_PSKTSEL,
-        GPIO55_nPREG,
-        GPIO56_nPWAIT,
-        GPIO57_nIOIS16,
 };
 
 /******************************************************************************
@@ -132,6 +96,34 @@ int __init parse_balloon3_features(char *arg)
 early_param("balloon3_features", parse_balloon3_features);
 
 /******************************************************************************
+ * Compact Flash slot
+ ******************************************************************************/
+#if     defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static unsigned long balloon3_cf_pin_config[] __initdata = {
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+};
+
+static void __init balloon3_cf_init(void)
+{
+        if (!balloon3_has(BALLOON3_FEATURE_CF))
+                return;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_cf_pin_config));
+}
+#else
+static inline void balloon3_cf_init(void) {}
+#endif
+
+/******************************************************************************
  * NOR Flash
  ******************************************************************************/
 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
@@ -179,6 +171,15 @@ static inline void balloon3_nor_init(void) {}
  ******************************************************************************/
 #if     defined(CONFIG_TOUCHSCREEN_UCB1400) || \
         defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
+static unsigned long balloon3_ac97_pin_config[] __initdata = {
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+        GPIO113_AC97_nRESET,
+        GPIO95_GPIO,
+};
+
 static struct ucb1400_pdata vpac270_ucb1400_pdata = {
         .irq            = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ),
 };
@@ -197,6 +198,7 @@ static void __init balloon3_ts_init(void)
         if (!balloon3_has(BALLOON3_FEATURE_AUDIO))
                 return;
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config));
         pxa_set_ac97_info(NULL);
         platform_device_register(&balloon3_ucb1400_device);
 }
@@ -208,6 +210,11 @@ static inline void balloon3_ts_init(void) {}
  * Framebuffer
  ******************************************************************************/
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static unsigned long balloon3_lcd_pin_config[] __initdata = {
+        GPIOxx_LCD_TFT_16BPP,
+        GPIO99_GPIO,
+};
+
 static struct pxafb_mode_info balloon3_lcd_modes[] = {
         {
                 .pixclock               = 38000,
@@ -242,6 +249,8 @@ static void __init balloon3_lcd_init(void)
         if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY))
                 return;
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config));
+
         ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON");
         if (ret) {
                 pr_err("Requesting BKL-ON GPIO failed!\n");
@@ -271,6 +280,15 @@ static inline void balloon3_lcd_init(void) {}
  * SD/MMC card controller
  ******************************************************************************/
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+static unsigned long balloon3_mmc_pin_config[] __initdata = {
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+};
+
 static struct pxamci_platform_data balloon3_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_card_detect       = -1,
@@ -281,6 +299,7 @@ static struct pxamci_platform_data balloon3_mci_platform_data = {
 
 static void __init balloon3_mmc_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config));
         pxa_set_mci_info(&balloon3_mci_platform_data);
 }
 #else
@@ -339,6 +358,11 @@ static inline void balloon3_irda_init(void) {}
  * USB Host
  ******************************************************************************/
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static unsigned long balloon3_uhc_pin_config[] __initdata = {
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+};
+
 static struct pxaohci_platform_data balloon3_ohci_info = {
         .port_mode      = PMM_PERPORT_MODE,
         .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
@@ -348,6 +372,7 @@ static void __init balloon3_uhc_init(void)
 {
         if (!balloon3_has(BALLOON3_FEATURE_OHCI))
                 return;
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_uhc_pin_config));
         pxa_set_ohci_info(&balloon3_ohci_info);
 }
 #else
@@ -358,6 +383,11 @@ static inline void balloon3_uhc_init(void) {}
  * LEDs
  ******************************************************************************/
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static unsigned long balloon3_led_pin_config[] __initdata = {
+        GPIO9_GPIO,     /* NAND activity LED */
+        GPIO10_GPIO,    /* Heartbeat LED */
+};
+
 struct gpio_led balloon3_gpio_leds[] = {
         {
                 .name                   = "balloon3:green:idle",
@@ -436,6 +466,7 @@ static struct platform_device balloon3_pcf_leds = {
 
 static void __init balloon3_leds_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_led_pin_config));
         platform_device_register(&balloon3_leds);
         platform_device_register(&balloon3_pcf_leds);
 }
@@ -757,6 +788,7 @@ static void __init balloon3_init(void)
         balloon3_ts_init();
         balloon3_udc_init();
         balloon3_uhc_init();
+        balloon3_cf_init();
 }
 
 static struct map_desc balloon3_io_desc[] __initdata = {
@@ -776,9 +808,8 @@ static void __init balloon3_map_io(void)
 
 MACHINE_START(BALLOON3, "Balloon3")
         /* Maintainer: Nick Bane. */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = balloon3_map_io,
+        .nr_irqs        = BALLOON3_NR_IRQS,
         .init_irq       = balloon3_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = balloon3_init,
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index aae544631a8..4bd7a3cda48 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -148,9 +148,7 @@ static void __init capc7117_init(void)
 
 MACHINE_START(CAPC7117,
               "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
-        .phys_io = 0x40000000,
         .boot_params = 0xa0000100,
-        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io = pxa_map_io,
         .init_irq = pxa3xx_init_irq,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index bff6e78f033..ac5598ce972 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -33,6 +33,9 @@
 extern void cmx255_init(void);
 extern void cmx270_init(void);
 
+/* reserve IRQs for IT8152 */
+#define CMX2XX_NR_IRQS          (IRQ_BOARD_START + 40)
+
 /* virtual addresses for statically mapped regions */
 #define CMX2XX_VIRT_BASE        (0xe8000000)
 #define CMX2XX_IT8152_VIRT      (CMX2XX_VIRT_BASE)
@@ -511,9 +514,8 @@ static void __init cmx2xx_map_io(void)
 
 MACHINE_START(ARMCORE, "Compulab CM-X2XX")
         .boot_params    = 0xa0000100,
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = cmx2xx_map_io,
+        .nr_irqs        = CMX2XX_NR_IRQS,
         .init_irq       = cmx2xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = cmx2xx_init,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index c70e6c2f4e7..922b1075b9d 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 
 #include <linux/gpio.h>
 #include <linux/dm9000.h>
@@ -50,6 +51,7 @@
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
 #include <mach/audio.h>
+#include <mach/pxa3xx-u2d.h>
 
 #include <asm/mach/map.h>
 
@@ -68,6 +70,8 @@
 #define GPIO97_RTC_RD           (97)
 #define GPIO98_RTC_IO           (98)
 
+#define GPIO_ULPI_PHY_RST       (127)
+
 static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
         /* LCD */
         GPIO54_LCD_LDD_0,
@@ -472,6 +476,78 @@ static void __init cm_x300_init_mmc(void)
 static inline void cm_x300_init_mmc(void) {}
 #endif
 
+#if defined(CONFIG_PXA310_ULPI)
+static struct clk *pout_clk;
+
+static int cm_x300_ulpi_phy_reset(void)
+{
+        int err;
+
+        /* reset the PHY */
+        err = gpio_request(GPIO_ULPI_PHY_RST, "ulpi reset");
+        if (err) {
+                pr_err("%s: failed to request ULPI reset GPIO: %d\n",
+                       __func__, err);
+                return err;
+        }
+
+        gpio_direction_output(GPIO_ULPI_PHY_RST, 0);
+        msleep(10);
+        gpio_set_value(GPIO_ULPI_PHY_RST, 1);
+        msleep(10);
+
+        gpio_free(GPIO_ULPI_PHY_RST);
+
+        return 0;
+}
+
+static inline int cm_x300_u2d_init(struct device *dev)
+{
+        int err = 0;
+
+        if (cpu_is_pxa310()) {
+                /* CLK_POUT is connected to the ULPI PHY */
+                pout_clk = clk_get(NULL, "CLK_POUT");
+                if (IS_ERR(pout_clk)) {
+                        err = PTR_ERR(pout_clk);
+                        pr_err("%s: failed to get CLK_POUT: %d\n",
+                               __func__, err);
+                        return err;
+                }
+                clk_enable(pout_clk);
+
+                err = cm_x300_ulpi_phy_reset();
+                if (err) {
+                        clk_disable(pout_clk);
+                        clk_put(pout_clk);
+                }
+        }
+
+        return err;
+}
+
+static void cm_x300_u2d_exit(struct device *dev)
+{
+        if (cpu_is_pxa310()) {
+                clk_disable(pout_clk);
+                clk_put(pout_clk);
+        }
+}
+
+static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = {
+        .ulpi_mode      = ULPI_SER_6PIN,
+        .init           = cm_x300_u2d_init,
+        .exit           = cm_x300_u2d_exit,
+};
+
+static void cm_x300_init_u2d(void)
+{
+        pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
+}
+#else
+static inline void cm_x300_init_u2d(void) {}
+#endif
+
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 static int cm_x300_ohci_init(struct device *dev)
 {
@@ -754,6 +830,7 @@ static void __init cm_x300_init(void)
         cm_x300_init_da9030();
         cm_x300_init_dm9000();
         cm_x300_init_lcd();
+        cm_x300_init_u2d();
         cm_x300_init_ohci();
         cm_x300_init_mmc();
         cm_x300_init_nand();
@@ -779,9 +856,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
 }
 
 MACHINE_START(CM_X300, "CM-X300 module")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 98673ac6efd..bc045100ec1 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -207,8 +207,6 @@ static void __init colibri_pxa270_income_init(void)
 }
 
 MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa270_init,
         .map_io         = pxa_map_io,
@@ -217,8 +215,6 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
 MACHINE_END
 
 MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .init_machine   = colibri_pxa270_income_init,
         .map_io         = pxa_map_io,
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 40b6ac2de87..a70b256591e 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -186,8 +186,6 @@ void __init colibri_pxa300_init(void)
 }
 
 MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa300_init,
         .map_io         = pxa_map_io,
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index 99e850d8471..ca5f29e2e9c 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -255,8 +255,6 @@ void __init colibri_pxa320_init(void)
 }
 
 MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa320_init,
         .map_io         = pxa_map_io,
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 3fb0fc09908..821229acabe 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -720,8 +720,6 @@ static void __init fixup_corgi(struct machine_desc *desc,
 
 #ifdef CONFIG_MACH_CORGI
 MACHINE_START(CORGI, "SHARP Corgi")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_corgi,
         .map_io         = pxa_map_io,
         .init_irq       = pxa25x_init_irq,
@@ -732,8 +730,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_SHEPHERD
 MACHINE_START(SHEPHERD, "SHARP Shepherd")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_corgi,
         .map_io         = pxa_map_io,
         .init_irq       = pxa25x_init_irq,
@@ -744,8 +740,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_HUSKY
 MACHINE_START(HUSKY, "SHARP Husky")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_corgi,
         .map_io         = pxa_map_io,
         .init_irq       = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 0a0d0fe9922..88fbec05ec5 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -159,7 +159,7 @@ static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
 
 static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
 {
-        return get_clk_frequency_khz(0);
+        return pxa3xx_get_clk_frequency_khz(0);
 }
 
 static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
@@ -212,7 +212,8 @@ static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
         policy->cpuinfo.min_freq = 104000;
         policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
         policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
-        policy->cur = policy->min = policy->max = get_clk_frequency_khz(0);
+        policy->max = pxa3xx_get_clk_frequency_khz(0);
+        policy->cur = policy->min = policy->max;
 
         if (cpu_is_pxa300() || cpu_is_pxa310())
                 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 91fd4fea6a5..57cacaff194 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -272,9 +272,7 @@ static void __init csb726_init(void)
 }
 
 MACHINE_START(CSB726, "Cogent CSB726")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = csb726_init,
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 65447dc736c..aaa1166df96 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,11 +6,12 @@
 
 #include <asm/pmu.h>
 #include <mach/udc.h>
+#include <mach/pxa3xx-u2d.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
@@ -134,6 +135,33 @@ struct platform_device pxa27x_device_udc = {
         }
 };
 
+#ifdef CONFIG_PXA3xx
+static struct resource pxa3xx_u2d_resources[] = {
+        [0] = {
+                .start  = 0x54100000,
+                .end    = 0x54100fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_USB2,
+                .end    = IRQ_USB2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa3xx_device_u2d = {
+        .name           = "pxa3xx-u2d",
+        .id             = -1,
+        .resource       = pxa3xx_u2d_resources,
+        .num_resources  = ARRAY_SIZE(pxa3xx_u2d_resources),
+};
+
+void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
+{
+        pxa_register_device(&pxa3xx_device_u2d, info);
+}
+#endif /* CONFIG_PXA3xx */
+
 static struct resource pxafb_resources[] = {
         [0] = {
                 .start  = 0x44000000,
@@ -354,6 +382,31 @@ struct platform_device pxa_device_i2s = {
         .num_resources  = ARRAY_SIZE(pxai2s_resources),
 };
 
+struct platform_device pxa_device_asoc_ssp1 = {
+        .name           = "pxa-ssp-dai",
+        .id             = 0,
+};
+
+struct platform_device pxa_device_asoc_ssp2= {
+        .name           = "pxa-ssp-dai",
+        .id             = 1,
+};
+
+struct platform_device pxa_device_asoc_ssp3 = {
+        .name           = "pxa-ssp-dai",
+        .id             = 2,
+};
+
+struct platform_device pxa_device_asoc_ssp4 = {
+        .name           = "pxa-ssp-dai",
+        .id             = 3,
+};
+
+struct platform_device pxa_device_asoc_platform = {
+        .name           = "pxa-pcm-audio",
+        .id             = -1,
+};
+
 static u64 pxaficp_dmamask = ~(u32)0;
 
 struct platform_device pxa_device_ficp = {
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 50353ea49ba..2fd5a8b3575 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -4,6 +4,7 @@ extern struct platform_device pxa3xx_device_mci2;
 extern struct platform_device pxa3xx_device_mci3;
 extern struct platform_device pxa25x_device_udc;
 extern struct platform_device pxa27x_device_udc;
+extern struct platform_device pxa3xx_device_u2d;
 extern struct platform_device pxa_device_fb;
 extern struct platform_device pxa_device_ffuart;
 extern struct platform_device pxa_device_btuart;
@@ -38,4 +39,10 @@ extern struct platform_device pxa3xx_device_i2c_power;
 
 extern struct platform_device pxa3xx_device_gcu;
 
+extern struct platform_device pxa_device_asoc_platform;
+extern struct platform_device pxa_device_asoc_ssp1;
+extern struct platform_device pxa_device_asoc_ssp2;
+extern struct platform_device pxa_device_asoc_ssp3;
+extern struct platform_device pxa_device_asoc_ssp4;
+
 void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 0517c17978f..ab48bb81b57 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -43,7 +43,7 @@
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <plat/i2c.h>
 #include <mach/camera.h>
 #include <mach/pxa2xx_spi.h>
@@ -1301,8 +1301,6 @@ static void __init em_x270_init(void)
 
 MACHINE_START(EM_X270, "Compulab EM-X270")
         .boot_params    = 0xa0000100,
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1311,8 +1309,6 @@ MACHINE_END
 
 MACHINE_START(EXEDA, "Compulab eXeda")
         .boot_params    = 0xa0000100,
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 349212a1cbd..b25690ccadc 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -29,6 +29,7 @@
 
 #include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
+#include <mach/eseries-irq.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/udc.h>
@@ -179,10 +180,9 @@ static void __init e330_init(void)
 
 MACHINE_START(E330, "Toshiba e330")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e330_init,
@@ -229,10 +229,9 @@ static void __init e350_init(void)
 
 MACHINE_START(E350, "Toshiba e350")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e350_init,
@@ -352,10 +351,9 @@ static void __init e400_init(void)
 
 MACHINE_START(E400, "Toshiba e400")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e400_init,
@@ -541,10 +539,9 @@ static void __init e740_init(void)
 
 MACHINE_START(E740, "Toshiba e740")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e740_init,
@@ -733,10 +730,9 @@ static void __init e750_init(void)
 
 MACHINE_START(E750, "Toshiba e750")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e750_init,
@@ -929,10 +925,9 @@ static void __init e800_init(void)
 
 MACHINE_START(E800, "Toshiba e800")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
         .init_machine   = e800_init,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 626c82b1397..80a9352d43f 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -32,12 +32,14 @@
 #include <mach/ohci.h>
 #include <plat/i2c.h>
 #include <mach/hardware.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/camera.h>
 
 #include "devices.h"
 #include "generic.h"
 
+#define EZX_NR_IRQS                     (IRQ_BOARD_START + 24)
+
 #define GPIO12_A780_FLIP_LID            12
 #define GPIO15_A1200_FLIP_LID           15
 #define GPIO15_A910_FLIP_LID            15
@@ -796,10 +798,9 @@ static void __init a780_init(void)
 }
 
 MACHINE_START(EZX_A780, "Motorola EZX A780")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a780_init,
@@ -862,10 +863,9 @@ static void __init e680_init(void)
 }
 
 MACHINE_START(EZX_E680, "Motorola EZX E680")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e680_init,
@@ -928,10 +928,9 @@ static void __init a1200_init(void)
 }
 
 MACHINE_START(EZX_A1200, "Motorola EZX A1200")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a1200_init,
@@ -1120,10 +1119,9 @@ static void __init a910_init(void)
 }
 
 MACHINE_START(EZX_A910, "Motorola EZX A910")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = a910_init,
@@ -1186,10 +1184,9 @@ static void __init e6_init(void)
 }
 
 MACHINE_START(EZX_E6, "Motorola EZX E6")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e6_init,
@@ -1226,10 +1223,9 @@ static void __init e2_init(void)
 }
 
 MACHINE_START(EZX_E2, "Motorola EZX E2")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = e2_init,
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index baabb3ce088..6451e9c3a93 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -66,8 +66,7 @@ unsigned int get_clk_frequency_khz(int info)
                 return pxa25x_get_clk_frequency_khz(info);
         else if (cpu_is_pxa27x())
                 return pxa27x_get_clk_frequency_khz(info);
-        else
-                return pxa3xx_get_clk_frequency_khz(info);
+        return 0;
 }
 EXPORT_SYMBOL(get_clk_frequency_khz);
 
@@ -80,8 +79,7 @@ unsigned int get_memclk_frequency_10khz(void)
                 return pxa25x_get_memclk_frequency_10khz();
         else if (cpu_is_pxa27x())
                 return pxa27x_get_memclk_frequency_10khz();
-        else
-                return pxa3xx_get_memclk_frequency_10khz();
+        return 0;
 }
 EXPORT_SYMBOL(get_memclk_frequency_10khz);
 
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index c6305c5b8a7..4b1ad2769ed 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -54,11 +54,9 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
 
 #ifdef CONFIG_PXA3xx
 extern unsigned pxa3xx_get_clk_frequency_khz(int);
-extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
 extern void pxa3xx_clear_reset_status(unsigned int);
 #else
 #define pxa3xx_get_clk_frequency_khz(x)         (0)
-#define pxa3xx_get_memclk_frequency_10khz()     (0)
 static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
 #endif
 
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 96c34512913..1e2a9a13aec 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -224,9 +224,7 @@ static void __init gumstix_init(void)
 }
 
 MACHINE_START(GUMSTIX, "Gumstix")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100, /* match u-boot bi_boot_params */
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index c1cab0871c9..7057a1f46db 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -201,8 +201,6 @@ static void __init h5000_init(void)
 }
 
 MACHINE_START(H5400, "HP iPAQ H5000")
-        .phys_io = 0x40000000,
-        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params = 0xa0000100,
         .map_io = pxa_map_io,
         .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index f9a2e4b0f09..01b7f07ebad 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -159,8 +159,6 @@ static void __init himalaya_init(void)
 
 
 MACHINE_START(HIMALAYA, "HTC Himalaya")
-        .phys_io = 0x40000000,
-        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params = 0xa0000100,
         .map_io = pxa_map_io,
         .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 848c861dd23..76d93a25bab 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -870,10 +870,9 @@ static void __init hx4700_init(void)
 }
 
 MACHINE_START(H4700, "HP iPAQ HX4700")
-        .phys_io      = 0x40000000,
-        .io_pg_offst  = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params  = 0xa0000100,
         .map_io       = pxa_map_io,
+        .nr_irqs      = HX4700_NR_IRQS,
         .init_irq     = pxa27x_init_irq,
         .init_machine = hx4700_init,
         .timer        = &pxa_timer,
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index 5ccb0ceff6c..d51ee3d25e7 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -191,9 +191,7 @@ static void __init icontrol_init(void)
 }
 
 MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index bc78c4dc0c6..e773dceeabc 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -194,8 +194,6 @@ static void __init idp_map_io(void)
 
 MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
         /* Maintainer: Vibren Technologies */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = idp_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index eec92e6fd7c..561562b4360 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -174,6 +174,8 @@ enum balloon3_features {
 #define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
 #define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
 
+#define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 4)
+
 extern int balloon3_has(enum balloon3_features feature);
 
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
index 01cf81393fe..7d5c75125d6 100644
--- a/arch/arm/mach-pxa/include/mach/debug-macro.S
+++ b/arch/arm/mach-pxa/include/mach/debug-macro.S
@@ -13,12 +13,10 @@
 
 #include "hardware.h"
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x40000000                @ physical
-                movne   \rx, #io_p2v(0x40000000)        @ virtual
-                orr     \rx, \rx, #0x00100000
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00100000
+                orr     \rv, \rp, #io_p2v(0x40000000)   @ virtual
+                orr     \rp, \rp, #0x40000000           @ physical
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-pxa/include/mach/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h
index f2a93d5e31d..de292b269c6 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-irq.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-irq.h
@@ -25,3 +25,4 @@
 #define TMIO_SD_IRQ     IRQ_TMIO(1)
 #define TMIO_USB_IRQ    IRQ_TMIO(2)
 
+#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16)
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
index 9eaeed1f87f..37408449ec2 100644
--- a/arch/arm/mach-pxa/include/mach/hx4700.h
+++ b/arch/arm/mach-pxa/include/mach/hx4700.h
@@ -17,6 +17,7 @@
 
 #define HX4700_ASIC3_GPIO_BASE  NR_BUILTIN_GPIO
 #define HX4700_EGPIO_BASE       (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
+#define HX4700_NR_IRQS          (IRQ_BOARD_START + 70)
 
 /*
  * PXA GPIOs
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index ffc8314520f..d372caa75dc 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -117,48 +117,12 @@
 /*
  * The following interrupts are for board specific purposes. Since
  * the kernel can only run on one machine at a time, we can re-use
- * these.  There will be 16 IRQs by default.  If it is not enough,
- * IRQ_BOARD_END is allowed be customized for each board, but keep
- * the numbers within sensible limits and in descending order, so
- * when multiple config options are selected, the maximum will be
- * used.
+ * these.
+ * By default, no board IRQ is reserved. It should be finished in
+ * custom board since sparse IRQ is already enabled.
  */
 #define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
 
-#if defined(CONFIG_MACH_H4700)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 70)
-#elif defined(CONFIG_MACH_ZYLONITE)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 32)
-#elif defined(CONFIG_PXA_EZX)
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 23)
-#else
-#define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
-#endif
-
-/*
- * Figure out the MAX IRQ number.
- *
- * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
- * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
- * Otherwise, we have the standard IRQs only.
- */
-#ifdef CONFIG_SA1111
-#define NR_IRQS                 (IRQ_BOARD_END + 55)
-#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
-#define NR_IRQS                 (IRQ_BOARD_END)
-#else
 #define NR_IRQS                 (IRQ_BOARD_START)
-#endif
-
-/* add IT8152 IRQs beyond BOARD_END */
-#ifdef CONFIG_PCI_HOST_ITE8152
-#define IT8152_LAST_IRQ         (IRQ_BOARD_END + 40)
-
-#if NR_IRQS < (IT8152_LAST_IRQ+1)
-#undef NR_IRQS
-#define NR_IRQS (IT8152_LAST_IRQ+1)
-#endif
-
-#endif /* CONFIG_PCI_HOST_ITE8152 */
 
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 6c9b21c5132..2a5726c15e0 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -10,4 +10,6 @@
 #define EXT0_GPIO_BASE  (NR_BUILTIN_GPIO)
 #define EXT0_GPIO(x)    (EXT0_GPIO_BASE + (x))
 
+#define LITTLETON_NR_IRQS       (IRQ_BOARD_START + 8)
+
 #endif /* __ASM_ARCH_LITTLETON_H */
diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h
index 0e6440c8168..cd070092b6e 100644
--- a/arch/arm/mach-pxa/include/mach/lpd270.h
+++ b/arch/arm/mach-pxa/include/mach/lpd270.h
@@ -38,5 +38,6 @@
 #define LPD270_USBC_IRQ         LPD270_IRQ(2)
 #define LPD270_ETHERNET_IRQ     LPD270_IRQ(3)
 #define LPD270_AC97_IRQ         LPD270_IRQ(4)
+#define LPD270_NR_IRQS          (IRQ_BOARD_START + 5)
 
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index a0d4247f08f..2a086e8373e 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -45,6 +45,9 @@
 #define LUBBOCK_USB_DISC_IRQ    LUBBOCK_IRQ(6)  /* usb disconnect */
 #define LUBBOCK_LAST_IRQ        LUBBOCK_IRQ(6)
 
+#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16)
+#define LUBBOCK_NR_IRQS         (IRQ_BOARD_START + 16 + 55)
+
 #ifndef __ASSEMBLY__
 extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 20ef37d4a9a..0a2efcf7947 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -71,6 +71,8 @@
 #define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
 #define IRQ_MAGICIAN_VBUS       (IRQ_BOARD_START + 3)
 
+#define MAGICIAN_NR_IRQS        (IRQ_BOARD_START + 8)
+
 /*
  * CPLD EGPIOs
  */
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
index 86e623abd64..4c2d11cd824 100644
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -134,4 +134,6 @@
 #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
 #define MAINSTONE_S1_IRQ        MAINSTONE_IRQ(15)
 
+#define MAINSTONE_NR_IRQS       (IRQ_BOARD_START + 16)
+
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index 0d119d3b922..04f7c97044f 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -69,6 +69,7 @@
 #define nBE0_GPIO_60            MFP_CFG(nBE0, AF0)
 #define nBE1_GPIO_61            MFP_CFG(nBE1, AF0)
 #define RDY_GPIO_62             MFP_CFG(RDY, AF0)
+#define PMIC_INT_GPIO83         MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH)
 
 /* Chip Select */
 #define DF_nCS0_nCS2            MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
@@ -92,6 +93,9 @@
 #define GPIO63_CI2C_SCL         MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
 #define GPIO64_CI2C_SDA         MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
 
+#define GPIO73_CI2C_SCL         MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH)
+#define GPIO74_CI2C_SDA         MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH)
+
 #define GPIO77_CI2C_SCL         MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
 #define GPIO78_CI2C_SDA         MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
 
@@ -345,6 +349,9 @@
 #define GPIO69_UART1_CTS        MFP_CFG(GPIO69, AF2)
 #define GPIO70_UART1_RTS        MFP_CFG(GPIO70, AF2)
 
+#define GPIO53_UART1_TXD        MFP_CFG(GPIO53, AF2)
+#define GPIO54_UART1_RXD        MFP_CFG(GPIO54, AF2)
+
 /* UART2 - BTUART */
 #define GPIO91_UART2_RXD        MFP_CFG(GPIO91, AF1)
 #define GPIO92_UART2_TXD        MFP_CFG(GPIO92, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 04083263167..4bac588478a 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -30,6 +30,8 @@
 #define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
 #define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
 
+#define PCM027_NR_IRQS          (IRQ_BOARD_START + 32)
+
 /* I2C RTC */
 #define PCM027_RTC_IRQ_GPIO     0
 #define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 0b3e6d051c6..83d1cfd00fc 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -85,6 +85,8 @@
 #define POODLE_LOCOMO_GPIO_232VCC_ON   LOCOMO_GPIO(12)
 #define POODLE_LOCOMO_GPIO_JK_B        LOCOMO_GPIO(13)
 
+#define POODLE_NR_IRQS          (IRQ_BOARD_START + 4)   /* 4 for LoCoMo */
+
 extern struct platform_device poodle_locomo_device;
 
 #endif /* __ASM_ARCH_POODLE_H  */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
new file mode 100644
index 00000000000..9d82cb65ea5
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
@@ -0,0 +1,35 @@
+/*
+ * PXA3xx U2D header
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PXA310_U2D__
+#define __PXA310_U2D__
+
+#include <linux/usb/ulpi.h>
+
+struct pxa3xx_u2d_platform_data {
+
+#define ULPI_SER_6PIN   (1 << 0)
+#define ULPI_SER_3PIN   (1 << 1)
+        unsigned int ulpi_mode;
+
+        int (*init)(struct device *);
+        void (*exit)(struct device *);
+};
+
+
+/* Start PXA3xx U2D host */
+int pxa3xx_u2d_start_hc(struct usb_bus *host);
+/* Stop PXA3xx U2D host */
+void pxa3xx_u2d_stop_hc(struct usb_bus *host);
+
+extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
+
+#endif /* __PXA310_U2D__ */
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 1bbd1f2e4be..1272c4b56ce 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -20,6 +20,7 @@
 /* Jacket Scoop */
 #define TOSA_SCOOP_PHYS         (PXA_CS5_PHYS + 0x00800000)
 
+#define TOSA_NR_IRQS            (IRQ_BOARD_START + TC6393XB_NR_IRQS)
 /*
  * SCOOP2 internal GPIOs
  */
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index 6e119976003..faa408ab7ad 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -15,6 +15,8 @@
 #ifndef _MACH_ZEUS_H
 #define _MACH_ZEUS_H
 
+#define ZEUS_NR_IRQS            (IRQ_BOARD_START + 48)
+
 /* Physical addresses */
 #define ZEUS_FLASH_PHYS         PXA_CS0_PHYS
 #define ZEUS_ETH0_PHYS          PXA_CS1_PHYS
diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h
index 9edf645368d..ea24998b923 100644
--- a/arch/arm/mach-pxa/include/mach/zylonite.h
+++ b/arch/arm/mach-pxa/include/mach/zylonite.h
@@ -5,6 +5,8 @@
 
 #define EXT_GPIO(x)             (128 + (x))
 
+#define ZYLONITE_NR_IRQS        (IRQ_BOARD_START + 32)
+
 /* the following variables are processor specific and initialized
  * by the corresponding zylonite_pxa3xx_init()
  */
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 9b9046185b0..41aa89e3577 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -43,7 +43,7 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/littleton.h>
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
@@ -437,10 +437,9 @@ static void __init littleton_init(void)
 }
 
 MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
+        .nr_irqs        = LITTLETON_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = littleton_init,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index d279507fc74..623af0232a5 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -505,10 +505,9 @@ static void __init lpd270_map_io(void)
 
 MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
         /* Maintainer: Peter Barada */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = lpd270_map_io,
+        .nr_irqs        = LPD270_NR_IRQS,
         .init_irq       = lpd270_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = lpd270_init,
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 330c3282856..1499493cd07 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -229,7 +229,7 @@ static struct resource sa1111_resources[] = {
 };
 
 static struct sa1111_platform_data sa1111_info = {
-        .irq_base       = IRQ_BOARD_END,
+        .irq_base       = LUBBOCK_SA1111_IRQ_BASE,
 };
 
 static struct platform_device sa1111_device = {
@@ -557,9 +557,8 @@ static void __init lubbock_map_io(void)
 
 MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
         /* Maintainer: MontaVista Software Inc. */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = lubbock_map_io,
+        .nr_irqs        = LUBBOCK_NR_IRQS,
         .init_irq       = lubbock_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = lubbock_init,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e81dd0c8e40..90663760307 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -764,10 +764,9 @@ static void __init magician_init(void)
 
 
 MACHINE_START(MAGICIAN, "HTC Magician")
-        .phys_io = 0x40000000,
-        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params = 0xa0000100,
         .map_io = pxa_map_io,
+        .nr_irqs = MAGICIAN_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .init_machine = magician_init,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 5543c64da9e..a980a5c93e4 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -50,7 +50,7 @@
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -624,10 +624,9 @@ static void __init mainstone_map_io(void)
 
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
         /* Maintainer: MontaVista Software Inc. */
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,   /* BLOB boot parameter setting */
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = mainstone_map_io,
+        .nr_irqs        = MAINSTONE_NR_IRQS,
         .init_irq       = mainstone_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = mainstone_init,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dc66942ef9a..0c31fabfc7f 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -45,7 +45,7 @@
 
 #include <mach/pxa27x.h>
 #include <mach/regs-rtc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
@@ -819,8 +819,6 @@ static void mioa701_machine_exit(void)
 }
 
 MACHINE_START(MIOA701, "MIO A701")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = &pxa_map_io,
         .init_irq       = &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 6d4503927a7..116167aaba6 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -92,9 +92,7 @@ static void __init mp900c_init(void)
 
 /* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
 MACHINE_START(NEC_MP900, "MobilePro900/C")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0220100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .timer          = &pxa_timer,
         .map_io         = pxa_map_io,
         .init_irq       = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 91038eeafe4..ce092c521e6 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
 
@@ -343,8 +343,6 @@ static void __init palmld_init(void)
 }
 
 MACHINE_START(PALMLD, "Palm LifeDrive")
-        .phys_io        = PALMLD_PHYS_IO_START,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = palmld_map_io,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 1c281995f65..862da812cd1 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
@@ -202,8 +202,6 @@ static void __init palmt5_init(void)
 }
 
 MACHINE_START(PALMT5, "Palm Tungsten|T5")
-        .phys_io        = PALMT5_PHYS_IO_START,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
         .reserve        = palmt5_reserve,
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index ce1104d1bc1..2131d586091 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -412,9 +412,7 @@ static void __init palmtc_init(void)
 };
 
 MACHINE_START(PALMTC, "Palm Tungsten|C")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 93c11a0438d..a9dae7bc35d 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -373,8 +373,6 @@ static void __init palmte2_init(void)
 }
 
 MACHINE_START(PALMTE2, "Palm Tungsten|E2")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
         .init_irq       = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 52defd5e42e..00e2d7ba84e 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -39,7 +39,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/ohci.h>
 #include <mach/pxa2xx-regs.h>
@@ -441,8 +441,6 @@ static void __init centro_init(void)
 }
 
 MACHINE_START(TREO680, "Palm Treo 680")
-        .phys_io        = TREO_PHYS_IO_START,
-        .io_pg_offst    = io_p2v(0x40000000),
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
         .reserve        = treo_reserve,
@@ -452,8 +450,6 @@ MACHINE_START(TREO680, "Palm Treo 680")
 MACHINE_END
 
 MACHINE_START(CENTRO, "Palm Centro 685")
-        .phys_io        = TREO_PHYS_IO_START,
-        .io_pg_offst    = io_p2v(0x40000000),
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
         .reserve        = treo_reserve,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 144dc2b6911..d2060a1d1d6 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -43,7 +43,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
@@ -363,8 +363,6 @@ static void __init palmtx_init(void)
 }
 
 MACHINE_START(PALMTX, "Palm T|X")
-        .phys_io        = PALMTX_PHYS_IO_START,
-        .io_pg_offst    = io_p2v(0x40000000),
         .boot_params    = 0xa0000100,
         .map_io         = palmtx_map_io,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 87e4b1044e0..af6203fbca9 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -41,7 +41,7 @@
 #include <mach/mmc.h>
 #include <mach/pxafb.h>
 #include <mach/irda.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/udc.h>
 #include <mach/palmasoc.h>
 #include <mach/palm27x.h>
@@ -279,8 +279,6 @@ static void __init palmz72_init(void)
 }
 
 MACHINE_START(PALMZ72, "Palm Zire72")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = io_p2v(0x40000000),
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 2190af06647..c77e8f30a43 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -259,9 +259,8 @@ static void __init pcm027_map_io(void)
 MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
         /* Maintainer: Pengutronix */
         .boot_params    = 0xa0000100,
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pcm027_map_io,
+        .nr_irqs        = PCM027_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = pcm027_init,
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 55e8fcde014..93a191c889d 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -465,10 +465,9 @@ static void __init fixup_poodle(struct machine_desc *desc,
 }
 
 MACHINE_START(POODLE, "SHARP Poodle")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_poodle,
         .map_io         = pxa_map_io,
+        .nr_irqs        = POODLE_NR_IRQS,       /* 4 for LoCoMo */
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = poodle_init,
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 12e5b9f01e6..d1fbf29d561 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -385,6 +385,10 @@ static struct platform_device *devices[] __initdata = {
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
+        &pxa_device_asoc_ssp1,
+        &pxa_device_asoc_ssp2,
+        &pxa_device_asoc_ssp3,
+        &pxa_device_asoc_platform,
         &sa1100_device_rtc,
         &pxa_device_rtc,
         &pxa27x_device_ssp1,
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
new file mode 100644
index 00000000000..ce7168b233e
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -0,0 +1,400 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
+ *
+ * code specific to pxa3xx aka Monahans
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
+ *             initial version: pxa310 USB Host mode support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/usb.h>
+#include <linux/usb/otg.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-u2d.h>
+#include <mach/pxa3xx-u2d.h>
+
+struct pxa3xx_u2d_ulpi {
+        struct clk              *clk;
+        void __iomem            *mmio_base;
+
+        struct otg_transceiver  *otg;
+        unsigned int            ulpi_mode;
+};
+
+static struct pxa3xx_u2d_ulpi *u2d;
+
+static inline u32 u2d_readl(u32 reg)
+{
+        return __raw_readl(u2d->mmio_base + reg);
+}
+
+static inline void u2d_writel(u32 reg, u32 val)
+{
+        __raw_writel(val, u2d->mmio_base + reg);
+}
+
+#if defined(CONFIG_PXA310_ULPI)
+enum u2d_ulpi_phy_mode {
+        SYNCH           = 0,
+        CARKIT          = (1 << 0),
+        SER_3PIN        = (1 << 1),
+        SER_6PIN        = (1 << 2),
+        LOWPOWER        = (1 << 3),
+};
+
+static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
+{
+        return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
+}
+
+static int pxa310_ulpi_poll(void)
+{
+        int timeout = 50000;
+
+        while (timeout--) {
+                if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
+                        return 0;
+
+                cpu_relax();
+        }
+
+        pr_warning("%s: ULPI access timed out!\n", __func__);
+
+        return -ETIMEDOUT;
+}
+
+static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg)
+{
+        int err;
+
+        if (pxa310_ulpi_get_phymode() != SYNCH) {
+                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                return -EBUSY;
+        }
+
+        u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
+        msleep(5);
+
+        err = pxa310_ulpi_poll();
+        if (err)
+                return err;
+
+        return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
+}
+
+static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+        if (pxa310_ulpi_get_phymode() != SYNCH) {
+                pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+                return -EBUSY;
+        }
+
+        u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
+        msleep(5);
+
+        return pxa310_ulpi_poll();
+}
+
+struct otg_io_access_ops pxa310_ulpi_access_ops = {
+        .read   = pxa310_ulpi_read,
+        .write  = pxa310_ulpi_write,
+};
+
+static void pxa310_otg_transceiver_rtsm(void)
+{
+        u32 u2dotgcr;
+
+        /* put PHY to sync mode */
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |=  U2DOTGCR_RTSM | U2DOTGCR_UTMID;
+        u2d_writel(U2DOTGCR, u2dotgcr);
+        msleep(10);
+
+        /* setup OTG sync mode */
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |= U2DOTGCR_ULAF;
+        u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+        u2d_writel(U2DOTGCR, u2dotgcr);
+}
+
+static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
+{
+        int err;
+
+        pxa310_otg_transceiver_rtsm();
+
+        err = otg_init(u2d->otg);
+        if (err) {
+                pr_err("OTG transceiver init failed");
+                return err;
+        }
+
+        err = otg_set_vbus(u2d->otg, 1);
+        if (err) {
+                pr_err("OTG transceiver VBUS set failed");
+                return err;
+        }
+
+        err = otg_set_host(u2d->otg, host);
+        if (err)
+                pr_err("OTG transceiver Host mode set failed");
+
+        return err;
+}
+
+static int pxa310_start_otg_hc(struct usb_bus *host)
+{
+        u32 u2dotgcr;
+        int err;
+
+        /* disable USB device controller */
+        u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
+        u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
+        u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
+
+        err = pxa310_start_otg_host_transcvr(host);
+        if (err)
+                return err;
+
+        /* set xceiver mode */
+        if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
+                u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
+        else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
+                u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
+
+        /* start OTG host controller */
+        u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
+        u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
+
+        return 0;
+}
+
+static void pxa310_stop_otg_hc(void)
+{
+        pxa310_otg_transceiver_rtsm();
+
+        otg_set_host(u2d->otg, NULL);
+        otg_set_vbus(u2d->otg, 0);
+        otg_shutdown(u2d->otg);
+}
+
+static void pxa310_u2d_setup_otg_hc(void)
+{
+        u32 u2dotgcr;
+
+        u2dotgcr = u2d_readl(U2DOTGCR);
+        u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
+        u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+        u2d_writel(U2DOTGCR, u2dotgcr);
+        msleep(5);
+        u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
+        msleep(5);
+        u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
+}
+
+static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
+{
+        unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
+
+        if (pdata) {
+                if (pdata->ulpi_mode & ULPI_SER_6PIN)
+                        ulpi_mode |= ULPI_IC_6PIN_SERIAL;
+                else if (pdata->ulpi_mode & ULPI_SER_3PIN)
+                        ulpi_mode |= ULPI_IC_3PIN_SERIAL;
+        }
+
+        u2d->ulpi_mode = ulpi_mode;
+
+        u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
+        if (!u2d->otg)
+                return -ENOMEM;
+
+        u2d->otg->io_priv = u2d->mmio_base;
+
+        return 0;
+}
+
+static void pxa310_otg_exit(void)
+{
+        kfree(u2d->otg);
+}
+#else
+static inline void pxa310_u2d_setup_otg_hc(void) {}
+static inline int pxa310_start_otg_hc(struct usb_bus *host)
+{
+        return 0;
+}
+static inline void pxa310_stop_otg_hc(void) {}
+static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
+{
+        return 0;
+}
+static inline void pxa310_otg_exit(void) {}
+#endif /* CONFIG_PXA310_ULPI */
+
+int pxa3xx_u2d_start_hc(struct usb_bus *host)
+{
+        int err = 0;
+
+        /* In case the PXA3xx ULPI isn't used, do nothing. */
+        if (!u2d)
+                return 0;
+
+        clk_enable(u2d->clk);
+
+        if (cpu_is_pxa310()) {
+                pxa310_u2d_setup_otg_hc();
+                err = pxa310_start_otg_hc(host);
+        }
+
+        return err;
+}
+
+void pxa3xx_u2d_stop_hc(struct usb_bus *host)
+{
+        /* In case the PXA3xx ULPI isn't used, do nothing. */
+        if (!u2d)
+                return;
+
+        if (cpu_is_pxa310())
+                pxa310_stop_otg_hc();
+
+        clk_disable(u2d->clk);
+}
+
+static int pxa3xx_u2d_probe(struct platform_device *pdev)
+{
+        struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *r;
+        int err;
+
+        u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL);
+        if (!u2d) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return -ENOMEM;
+        }
+
+        u2d->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(u2d->clk)) {
+                dev_err(&pdev->dev, "failed to get u2d clock\n");
+                err = PTR_ERR(u2d->clk);
+                goto err_free_mem;
+        }
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r) {
+                dev_err(&pdev->dev, "no IO memory resource defined\n");
+                err = -ENODEV;
+                goto err_put_clk;
+        }
+
+        r = request_mem_region(r->start, resource_size(r), pdev->name);
+        if (!r) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                err = -EBUSY;
+                goto err_put_clk;
+        }
+
+        u2d->mmio_base = ioremap(r->start, resource_size(r));
+        if (!u2d->mmio_base) {
+                dev_err(&pdev->dev, "ioremap() failed\n");
+                err = -ENODEV;
+                goto err_free_res;
+        }
+
+        if (pdata->init) {
+                err = pdata->init(&pdev->dev);
+                if (err)
+                        goto err_free_io;
+        }
+
+        /* Only PXA310 U2D has OTG functionality */
+        if (cpu_is_pxa310()) {
+                err = pxa310_otg_init(pdata);
+                if (err)
+                        goto err_free_plat;
+        }
+
+        platform_set_drvdata(pdev, &u2d);
+
+        return 0;
+
+err_free_plat:
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+err_free_io:
+        iounmap(u2d->mmio_base);
+err_free_res:
+        release_mem_region(r->start, resource_size(r));
+err_put_clk:
+        clk_put(u2d->clk);
+err_free_mem:
+        kfree(u2d);
+        return err;
+}
+
+static int pxa3xx_u2d_remove(struct platform_device *pdev)
+{
+        struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *r;
+
+        if (cpu_is_pxa310()) {
+                pxa310_stop_otg_hc();
+                pxa310_otg_exit();
+        }
+
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+
+        platform_set_drvdata(pdev, NULL);
+        iounmap(u2d->mmio_base);
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, resource_size(r));
+
+        clk_put(u2d->clk);
+
+        kfree(u2d);
+
+        return 0;
+}
+
+static struct platform_driver pxa3xx_u2d_ulpi_driver = {
+        .driver         = {
+                .name   = "pxa3xx-u2d",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = pxa3xx_u2d_probe,
+        .remove         = pxa3xx_u2d_remove,
+};
+
+static int pxa3xx_u2d_ulpi_init(void)
+{
+        return platform_driver_register(&pxa3xx_u2d_ulpi_driver);
+}
+module_init(pxa3xx_u2d_ulpi_init);
+
+static void __exit pxa3xx_u2d_ulpi_exit(void)
+{
+        platform_driver_unregister(&pxa3xx_u2d_ulpi_driver);
+}
+module_exit(pxa3xx_u2d_ulpi_exit);
+
+MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
+MODULE_AUTHOR("Igor Grinberg");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index fa0014847c7..d1c747cdacf 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -98,23 +98,6 @@ unsigned int pxa3xx_get_clk_frequency_khz(int info)
         return CLK / 1000;
 }
 
-/*
- * Return the current static memory controller clock frequency
- * in units of 10kHz
- */
-unsigned int pxa3xx_get_memclk_frequency_10khz(void)
-{
-        unsigned long acsr;
-        unsigned int smcfs, clk = 0;
-
-        acsr = ACSR;
-
-        smcfs = (acsr >> 23) & 0x7;
-        clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
-
-        return (clk / 10000);
-}
-
 void pxa3xx_clear_reset_status(unsigned int mask)
 {
         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
@@ -265,7 +248,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
-        INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
+        INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
@@ -610,6 +593,11 @@ static struct platform_device *devices[] __initdata = {
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
+        &pxa_device_asoc_ssp1,
+        &pxa_device_asoc_ssp2,
+        &pxa_device_asoc_ssp3,
+        &pxa_device_asoc_ssp4,
+        &pxa_device_asoc_platform,
         &sa1100_device_rtc,
         &pxa_device_rtc,
         &pxa27x_device_ssp1,
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 06429200828..7d29dd3af79 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
 
 static int __init pxa930_init(void)
 {
-        if (cpu_is_pxa930() || cpu_is_pxa935()) {
+        if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa930_mfp_addr_map);
         }
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 67e04f4e07c..4121d03ea2c 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -1083,8 +1083,6 @@ static void __init raumfeld_speaker_init(void)
 
 #ifdef CONFIG_MACH_RAUMFELD_RC
 MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_controller_init,
         .map_io         = pxa_map_io,
@@ -1095,8 +1093,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
 MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_connector_init,
         .map_io         = pxa_map_io,
@@ -1107,8 +1103,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_RAUMFELD_SPEAKER
 MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_speaker_init,
         .map_io         = pxa_map_io,
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 115b6f234bd..4b521e045d7 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -596,9 +596,7 @@ static void __init saar_init(void)
 
 MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 1cd99cb87bb..f736119f1eb 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,8 +979,6 @@ static void __init spitz_fixup(struct machine_desc *desc,
 
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = spitz_fixup,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
@@ -991,8 +989,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = spitz_fixup,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
@@ -1003,8 +999,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = spitz_fixup,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index a654d1e6b38..738adc1773f 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -56,6 +56,8 @@
 #include "devices.h"
 #include "generic.h"
 
+#define STARGATE_NR_IRQS        (IRQ_BOARD_START + 8)
+
 /* Bluetooth */
 #define SG2_BT_RESET            81
 
@@ -996,8 +998,6 @@ static void __init stargate2_init(void)
 
 #ifdef CONFIG_MACH_INTELMOTE2
 MACHINE_START(INTELMOTE2, "IMOTE 2")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1008,9 +1008,8 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_STARGATE2
 MACHINE_START(STARGATE2, "Stargate 2")
-        .phys_io = 0x40000000,
-        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io = pxa_map_io,
+        .nr_irqs = STARGATE_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .timer = &pxa_timer,
         .init_machine = stargate2_init,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index f02dcb5b4e9..2ea7545273a 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -25,7 +25,7 @@
 
 #include <mach/pxa930.h>
 #include <mach/pxafb.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 
 #include "devices.h"
 #include "generic.h"
@@ -489,9 +489,7 @@ static void __init tavorevb_init(void)
 
 MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
new file mode 100644
index 00000000000..dc3011697bb
--- /dev/null
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -0,0 +1,135 @@
+/*
+ *  linux/arch/arm/mach-pxa/tavorevb3.c
+ *
+ *  Support for the Marvell EVB3 Development Platform.
+ *
+ *  Copyright:  (C) Copyright 2008-2010 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/mfd/88pm860x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/pxa930.h>
+
+#include <plat/i2c.h>
+
+#include "devices.h"
+#include "generic.h"
+
+#define TAVOREVB3_NR_IRQS       (IRQ_BOARD_START + 24)
+
+static mfp_cfg_t evb3_mfp_cfg[] __initdata = {
+        /* UART */
+        GPIO53_UART1_TXD,
+        GPIO54_UART1_RXD,
+
+        /* PMIC */
+        PMIC_INT_GPIO83,
+};
+
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct pm860x_touch_pdata evb3_touch = {
+        .gpadc_prebias  = 1,
+        .slot_cycle     = 1,
+        .tsi_prebias    = 6,
+        .pen_prebias    = 16,
+        .pen_prechg     = 2,
+        .res_x          = 300,
+};
+
+static struct pm860x_backlight_pdata evb3_backlight[] = {
+        {
+                .id     = PM8606_ID_BACKLIGHT,
+                .iset   = PM8606_WLED_CURRENT(24),
+                .flags  = PM8606_BACKLIGHT1,
+        },
+        {},
+};
+
+static struct pm860x_led_pdata evb3_led[] = {
+        {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_BLUE,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_BLUE,
+        },
+};
+
+static struct pm860x_platform_data evb3_pm8607_info = {
+        .touch                          = &evb3_touch,
+        .backlight                      = &evb3_backlight[0],
+        .led                            = &evb3_led[0],
+        .companion_addr                 = 0x10,
+        .irq_mode                       = 0,
+        .irq_base                       = IRQ_BOARD_START,
+
+        .i2c_port                       = GI2C_PORT,
+};
+
+static struct i2c_board_info evb3_i2c_info[] = {
+        {
+                .type           = "88PM860x",
+                .addr           = 0x34,
+                .platform_data  = &evb3_pm8607_info,
+                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+        },
+};
+
+static void __init evb3_init_i2c(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(evb3_i2c_info));
+}
+#else
+static inline void evb3_init_i2c(void) {}
+#endif
+
+static void __init evb3_init(void)
+{
+        /* initialize MFP configurations */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(evb3_mfp_cfg));
+
+        pxa_set_ffuart_info(NULL);
+
+        evb3_init_i2c();
+}
+
+MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .nr_irqs        = TAVOREVB3_NR_IRQS,
+        .init_irq       = pxa3xx_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = evb3_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 83cc3a18c2e..0ee1df49606 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -952,10 +952,9 @@ static void __init fixup_tosa(struct machine_desc *desc,
 }
 
 MACHINE_START(TOSA, "SHARP Tosa")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .fixup          = fixup_tosa,
         .map_io         = pxa_map_io,
+        .nr_irqs        = TOSA_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = tosa_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 0acff172ef2..565d062f51d 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -555,8 +555,6 @@ static void __init trizeps4_map_io(void)
 
 MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
         /* MAINTAINER("Jürgen Schindele") */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = TRIZEPS4_SDRAM_BASE + 0x100,
         .init_machine   = trizeps4_init,
         .map_io         = trizeps4_map_io,
@@ -566,8 +564,6 @@ MACHINE_END
 
 MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
         /* MAINTAINER("Jürgen Schindele") */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = TRIZEPS4_SDRAM_BASE + 0x100,
         .init_machine   = trizeps4_init,
         .map_io         = trizeps4_map_io,
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index e90114a7e24..438fc9a5ed5 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -992,8 +992,6 @@ static void __init viper_map_io(void)
 
 MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = viper_map_io,
         .init_irq       = viper_init_irq,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 37d6173bbb6..f45ac096177 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -718,8 +718,6 @@ static void __init vpac270_init(void)
 }
 
 MACHINE_START(VPAC270, "Voipac PXA270")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index d3b4e3f2e03..3260ce73d32 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -181,8 +181,6 @@ static void __init xcep_init(void)
 }
 
 MACHINE_START(XCEP, "Iskratel XCEP")
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .init_machine   = xcep_init,
         .map_io         = pxa_map_io,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index f0d02288b4c..fefde9848d8 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -37,7 +37,7 @@
 #include <mach/z2.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
 
 #include <plat/i2c.h>
@@ -703,9 +703,7 @@ static void __init z2_init(void)
 }
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 03b9cb910e0..dea46a2d089 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -900,10 +900,9 @@ static void __init zeus_map_io(void)
 
 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = ((io_p2v(0x40000000) >> 18) & 0xfffc),
         .boot_params    = 0xa0000100,
         .map_io         = zeus_map_io,
+        .nr_irqs        = ZEUS_NR_IRQS,
         .init_irq       = zeus_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = zeus_init,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index c479cbecf78..702f7a68e87 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -30,7 +30,7 @@
 #include <mach/zylonite.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
-#include <mach/pxa27x_keypad.h>
+#include <plat/pxa27x_keypad.h>
 #include <plat/pxa3xx_nand.h>
 
 #include "devices.h"
@@ -45,6 +45,16 @@ int wm9713_irq;
 int lcd_id;
 int lcd_orientation;
 
+struct platform_device pxa_device_wm9713_audio = {
+        .name           = "wm9713-codec",
+        .id             = -1,
+};
+
+static void __init zylonite_init_wm9713_audio(void)
+{
+        platform_device_register(&pxa_device_wm9713_audio);
+}
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = ZYLONITE_ETH_PHYS + 0x300,
@@ -408,13 +418,13 @@ static void __init zylonite_init(void)
         zylonite_init_nand();
         zylonite_init_leds();
         zylonite_init_ohci();
+        zylonite_init_wm9713_audio();
 }
 
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
-        .phys_io        = 0x40000000,
         .boot_params    = 0xa0000100,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = pxa_map_io,
+        .nr_irqs        = ZYLONITE_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = zylonite_init,
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 2fa38df2841..07c08151dfe 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -259,6 +259,7 @@ struct mmci_platform_data realview_mmc0_plat_data = {
         .status         = realview_mmc_status,
         .gpio_wp        = 17,
         .gpio_cd        = 16,
+        .cd_invert      = true,
 };
 
 struct mmci_platform_data realview_mmc1_plat_data = {
@@ -266,6 +267,7 @@ struct mmci_platform_data realview_mmc1_plat_data = {
         .status         = realview_mmc_status,
         .gpio_wp        = 19,
         .gpio_cd        = 18,
+        .cd_invert      = true,
 };
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index 86622289b74..90b687cbe04 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -33,12 +33,10 @@
 #error "Unknown RealView platform"
 #endif
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xfb000000   @ virtual base
-                orr     \rx, \rx, #DEBUG_LL_UART_OFFSET
+                .macro  addruart, rp, rv
+                mov     \rp, #DEBUG_LL_UART_OFFSET
+                orr     \rv, \rp, #0xfb000000   @ virtual base
+                orr     \rp, \rp, #0x10000000   @ physical base
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892d44a..d3cd265cb05 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()                 \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 991c1f8390e..f2697106f80 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -486,8 +486,6 @@ static void __init realview_eb_init(void)
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_EB_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_eb_map_io,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d2be12eb829..a4125619d71 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -378,8 +378,6 @@ static void __init realview_pb1176_init(void)
 
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PB1176_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .fixup          = realview_pb1176_fixup,
         .map_io         = realview_pb1176_map_io,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index d591bc00b86..117b95b2ca1 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -381,8 +381,6 @@ static void __init realview_pb11mp_init(void)
 
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PB11MP_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_pb11mp_map_io,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 6c37621217b..929b8dc12e8 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -331,8 +331,6 @@ static void __init realview_pba8_init(void)
 
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PBA8_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .fixup          = realview_fixup,
         .map_io         = realview_pba8_map_io,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 9428eff0b11..b9f9e20031a 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -417,8 +417,6 @@ static void __init realview_pbx_init(void)
 
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_PBX_UART0_BASE & SECTION_MASK,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .fixup          = realview_pbx_fixup,
         .map_io         = realview_pbx_map_io,
diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S
index 6fc8d66395d..85effffdc2b 100644
--- a/arch/arm/mach-rpc/include/mach/debug-macro.S
+++ b/arch/arm/mach-rpc/include/mach/debug-macro.S
@@ -11,13 +11,11 @@
  *
 */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x03000000
-                movne   \rx, #0xe0000000
-                orr     \rx, \rx, #0x00010000
-                orr     \rx, \rx, #0x00000fe0
+                .macro  addruart, rp, rv
+                mov     \rp, #0x00010000
+                orr     \rp, \rp, #0x00000fe0
+                orr     \rv, \rp, #0xe0000000   @ virtual
+                orr     \rp, \rp, #0x03000000   @ physical
                 .endm
 
 #define UART_SHIFT      2
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
index 9a96fd69e70..3bcd86fadb8 100644
--- a/arch/arm/mach-rpc/include/mach/vmalloc.h
+++ b/arch/arm/mach-rpc/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
+#define VMALLOC_END       0xdc000000
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index c7fc01e9d1f..580b3c73d2c 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -218,8 +218,6 @@ extern struct sys_timer ioc_timer;
 
 MACHINE_START(RISCPC, "Acorn-RiscPC")
         /* Maintainer: Russell King */
-        .phys_io        = 0x03000000,
-        .io_pg_offst    = ((0xe0000000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .reserve_lp0    = 1,
         .reserve_lp1    = 1,
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
index 0eef78b4a6e..5882deaa56b 100644
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
@@ -19,13 +19,12 @@
 #define S3C2410_UART1_OFF (0x4000)
 #define SHIFT_2440TXF (14-9)
 
-        .macro addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C24XX_PA_UART
-                ldrne   \rx, = S3C24XX_VA_UART
+        .macro addruart, rp, rv
+                ldr     \rp, = S3C24XX_PA_UART
+                ldr     \rv, = S3C24XX_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
+                add     \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
 #endif
         .endm
 
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 34fc05a4244..44440cbd762 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -241,8 +241,6 @@ static void __init amlm5900_init(void)
 }
 
 MACHINE_START(AML_M5900, "AML_M5900")
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = amlm5900_map_io,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index c1f90f6fab4..2970ea9f7c2 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -664,8 +664,6 @@ static void __init bast_init(void)
 
 MACHINE_START(BAST, "Simtec-BAST")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = bast_map_io,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 3ba3bab139d..98c5c9e81ee 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -350,8 +350,6 @@ static void __init h1940_init(void)
 
 MACHINE_START(H1940, "IPAQ-H1940")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = h1940_map_io,
         .reserve        = h1940_reserve,
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 41f299d983e..271b9aa6d40 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -605,8 +605,6 @@ MACHINE_START(N30, "Acer-N30")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>,
                                 Ben Dooks <ben-linux@fluff.org>
         */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .timer          = &s3c24xx_timer,
         .init_machine   = n30_init,
@@ -617,8 +615,6 @@ MACHINE_END
 MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .timer          = &s3c24xx_timer,
         .init_machine   = n30_init,
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index d8c7f2efc1a..0aa16cd5acb 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -116,8 +116,6 @@ static void __init otom11_init(void)
 
 MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index d0e87b6e2e0..e8f49feef28 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -362,8 +362,6 @@ static void __init qt2410_machine_init(void)
 }
 
 MACHINE_START(QT2410, "QT2410")
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = qt2410_map_io,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 45222304220..e17f03387ab 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -111,8 +111,6 @@ static void __init smdk2410_init(void)
 MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
                                     * to SMDK2410 */
         /* Maintainer: Jonas Dietsche */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = smdk2410_map_io,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index 929164a8e9b..a15d0621c22 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -152,8 +152,6 @@ static void __init tct_hammer_init(void)
 }
 
 MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = tct_hammer_map_io,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index d540d79dd26..6ccce5a761b 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -400,8 +400,6 @@ static void __init vr1000_init(void)
 
 MACHINE_START(VR1000, "Thorcom-VR1000")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 478f4b4606c..923e01bdf01 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -675,8 +675,6 @@ static void __init jive_machine_init(void)
 
 MACHINE_START(JIVE, "JIVE")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 054c9f92232..8e5758bdd66 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -150,8 +150,6 @@ static void __init smdk2413_machine_init(void)
 
 MACHINE_START(S3C2413, "S3C2413")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .fixup          = smdk2413_fixup,
@@ -163,8 +161,6 @@ MACHINE_END
 
 MACHINE_START(SMDK2412, "SMDK2412")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .fixup          = smdk2413_fixup,
@@ -176,8 +172,6 @@ MACHINE_END
 
 MACHINE_START(SMDK2413, "SMDK2413")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .fixup          = smdk2413_fixup,
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index f291ac25d31..83544ebe20a 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -156,8 +156,6 @@ static void __init vstms_init(void)
 }
 
 MACHINE_START(VSTMS, "VSTMS")
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .fixup          = vstms_fixup,
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index 5fc3f67ef26..7fc366476d7 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -195,8 +195,6 @@ static void __init smdk2416_machine_init(void)
 
 MACHINE_START(SMDK2416, "SMDK2416")
         /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index b73f78a9da5..d7086788b1f 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -498,8 +498,6 @@ static void __init anubis_init(void)
 
 MACHINE_START(ANUBIS, "Simtec-Anubis")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 84725791e6b..6c98b789b8c 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -5,7 +5,7 @@
  *      and modifications by SBZ <sbz@spgui.org> and
  *      Weibing <http://weibing.blogbus.com>
  *
- * For product information, visit http://www.arm9e.com/
+ * For product information, visit http://www.arm.com/
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -233,8 +233,6 @@ static void __init at2440evb_init(void)
 
 
 MACHINE_START(AT2440EVB, "AT2440EVB")
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index deaabe86741..9f2c14ec718 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -572,8 +572,6 @@ static void __init gta02_machine_init(void)
 
 MACHINE_START(NEO1973_GTA02, "GTA02")
         /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = gta02_map_io,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index a76bcda210a..f62bb4c793b 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -691,8 +691,6 @@ static void __init mini2440_init(void)
 
 MACHINE_START(MINI2440, "MINI2440")
         /* Maintainer: Michel Pollet <buserror@gmail.com> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 3ff62de45fd..37dd306fb7d 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -151,8 +151,6 @@ static void __init nexcoder_init(void)
 
 MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 319458da71a..14dc6789775 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -455,8 +455,6 @@ static void __init osiris_init(void)
 
 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = osiris_map_io,
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 142d1f92117..32019bd9db3 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -580,8 +580,6 @@ static void __init rx1950_reserve(void)
 
 MACHINE_START(RX1950, "HP iPAQ RX1950")
     /* Maintainers: Vasily Khoruzhick */
-    .phys_io = S3C2410_PA_UART,
-        .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params = S3C2410_SDRAM_PA + 0x100,
         .map_io = rx1950_map_io,
         .reserve        = rx1950_reserve,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 6bb44f75a9c..1472b1a5b2f 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -218,8 +218,6 @@ static void __init rx3715_init_machine(void)
 
 MACHINE_START(RX3715, "IPAQ-RX3715")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = rx3715_map_io,
         .reserve        = rx3715_reserve,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index df83276d85a..eedfe0f1164 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -175,8 +175,6 @@ static void __init smdk2440_machine_init(void)
 
 MACHINE_START(S3C2440, "SMDK2440")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 4c863d3a52f..4337f0a9960 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -132,8 +132,6 @@ static void __init smdk2443_machine_init(void)
 
 MACHINE_START(SMDK2443, "SMDK2443")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C2410_PA_UART,
-        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 
         .init_irq       = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
index 239476b81f3..0c5a7380556 100644
--- a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
@@ -10,13 +10,12 @@
 #include <mach/map.h>
 #include <plat/regs-serial.h>
 
-        .macro addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C24XX_PA_UART
-                ldrne   \rx, = S3C24XX_VA_UART
+        .macro addruart, rp, rv
+                ldr     \rp, = S3C24XX_PA_UART
+                ldr     \rv, = S3C24XX_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
+                add     \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
 #endif
         .endm
 
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index 9648fbc36ee..3838335f125 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -43,8 +43,10 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
                 s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
                 s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
                 s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
+                break;
         default:
-                printk(KERN_DEBUG "Invalid I2S Controller number!");
+                printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
+                        pdev->id);
                 return -EINVAL;
         }
 
@@ -184,7 +186,8 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
                 s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
                 break;
         default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
+                printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
+                        pdev->id);
                 return -EINVAL;
         }
 
@@ -333,3 +336,16 @@ void __init s3c64xx_ac97_setup_gpio(int num)
         else
                 s3c_ac97_pdata.cfg_gpio = s3c64xx_ac97_cfg_gpe;
 }
+
+static u64 s3c_device_audio_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_pcm = {
+        .name             = "s3c24xx-pcm-audio",
+        .id               = -1,
+        .dev              = {
+                .dma_mask = &s3c_device_audio_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+EXPORT_SYMBOL(s3c_device_pcm);
+
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
index f9ab5d26052..a29e70550c7 100644
--- a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -21,13 +21,12 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx, rtmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+        .macro addruart, rp, rv
+                ldr     \rp, = S3C_PA_UART
+                ldr     \rv, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
 #if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
 #endif
         .endm
 
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 742dc87bd9c..a53cf149476 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -233,8 +233,6 @@ static void __init anw6410_machine_init(void)
 
 MACHINE_START(ANW6410, "A&W6410")
         /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
 
         .init_irq       = s3c6410_init_irq,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index fba90229f0d..b2639582cac 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -265,8 +265,6 @@ static void __init hmt_machine_init(void)
 
 MACHINE_START(HMT, "Airgoo-HMT")
         /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = hmt_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index bf65747ea68..c4986498cd1 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -97,8 +97,6 @@ static void __init ncp_machine_init(void)
 
 MACHINE_START(NCP, "NCP")
         /* Maintainer: Samsung Electronics */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = ncp_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index e130379ba0e..4b4475da8ec 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -141,8 +141,6 @@ static void __init real6410_machine_init(void)
 
 MACHINE_START(REAL6410, "REAL6410")
         /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
 
         .init_irq       = s3c6410_init_irq,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 3a9639bc3d9..cb1ebeb0876 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -136,7 +136,7 @@ static struct platform_device smartq_usb_otg_vbus_dev = {
         .dev.platform_data      = &smartq_usb_otg_vbus_pdata,
 };
 
-static int __init smartq_bl_init(struct device *dev)
+static int smartq_bl_init(struct device *dev)
 {
     s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
 
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index a4d59b076e3..3a3e5acde52 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -32,7 +32,7 @@
 
 #include "mach-smartq.h"
 
-static struct gpio_led smartq5_leds[] __initdata = {
+static struct gpio_led smartq5_leds[] = {
         {
                 .name                   = "smartq5:green",
                 .active_low             = 1,
@@ -146,8 +146,6 @@ static void __init smartq5_machine_init(void)
 
 MACHINE_START(SMARTQ5, "SmartQ 5")
         /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = smartq_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index e50a7d78173..e65375877d5 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -32,7 +32,7 @@
 
 #include "mach-smartq.h"
 
-static struct gpio_led smartq7_leds[] __initdata = {
+static struct gpio_led smartq7_leds[] = {
         {
                 .name                   = "smartq7:red",
                 .active_low             = 1,
@@ -162,8 +162,6 @@ static void __init smartq7_machine_init(void)
 
 MACHINE_START(SMARTQ7, "SmartQ 7")
         /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
         .init_irq       = s3c6410_init_irq,
         .map_io         = smartq_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 59916676d8d..3cca642f1e6 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -85,8 +85,6 @@ static void __init smdk6400_machine_init(void)
 
 MACHINE_START(SMDK6400, "SMDK6400")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
 
         .init_irq       = s3c6400_init_irq,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d498219fff1..77488facfe4 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -283,6 +283,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
         &s3c_device_fb,
         &s3c_device_ohci,
         &s3c_device_usb_hsotg,
+        &s3c_device_pcm,
         &s3c64xx_device_iisv4,
         &samsung_device_keypad,
 
@@ -704,8 +705,6 @@ static void __init smdk6410_machine_init(void)
 
 MACHINE_START(SMDK6410, "SMDK6410")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
 
         .init_irq       = s3c6410_init_irq,
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
deleted file mode 100644
index 6a4af7f5758..00000000000
--- a/arch/arm/mach-s5p6440/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-# arch/arm/mach-s5p6440/Kconfig
-#
-# Copyright (c) 2009 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-if ARCH_S5P6440
-
-config CPU_S5P6440
-        bool
-        select S3C_PL330_DMA
-        help
-          Enable S5P6440 CPU support
-
-config S5P6440_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config MACH_SMDK6440
-        bool "SMDK6440"
-        select CPU_S5P6440
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_TS
-        select S5P6440_SETUP_I2C1
-        help
-          Machine support for the Samsung SMDK6440
-
-endif
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
deleted file mode 100644
index c3fe4d3662a..00000000000
--- a/arch/arm/mach-s5p6440/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# arch/arm/mach-s5p6440/Makefile
-#
-# Copyright (c) 2009 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-# Core support for S5P6440 system
-
-obj-$(CONFIG_CPU_S5P6440)       += cpu.o init.o clock.o gpio.o dma.o
-obj-$(CONFIG_CPU_S5P6440)       += setup-i2c0.o
-
-# machine support
-
-obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
-
-# device support
-obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
-obj-$(CONFIG_S5P6440_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
deleted file mode 100644
index ca6e48dce77..00000000000
--- a/arch/arm/mach-s5p6440/clock.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/clock.c
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/sysdev.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/clock-clksrc.h>
-#include <plat/s5p-clock.h>
-#include <plat/pll.h>
-#include <plat/s5p6440.h>
-
-/* APLL Mux output clock */
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
-};
-
-static int s5p6440_epll_enable(struct clk *clk, int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
-
-        if (enable)
-                __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
-        else
-                __raw_writel(epll_con, S5P_EPLL_CON);
-
-        return 0;
-}
-
-static unsigned long s5p6440_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static u32 epll_div[][5] = {
-        { 36000000,     0,      48, 1, 4 },
-        { 48000000,     0,      32, 1, 3 },
-        { 60000000,     0,      40, 1, 3 },
-        { 72000000,     0,      48, 1, 3 },
-        { 84000000,     0,      28, 1, 2 },
-        { 96000000,     0,      32, 1, 2 },
-        { 32768000,     45264,  43, 1, 4 },
-        { 45158000,     6903,   30, 1, 3 },
-        { 49152000,     50332,  32, 1, 3 },
-        { 67738000,     10398,  45, 1, 3 },
-        { 73728000,     9961,   49, 1, 3 }
-};
-
-static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-
-        if (clk->rate == rate)  /* Return if nothing changed */
-                return 0;
-
-        epll_con = __raw_readl(S5P_EPLL_CON);
-        epll_con_k = __raw_readl(S5P_EPLL_CON_K);
-
-        epll_con_k &= ~(PLL90XX_KDIV_MASK);
-        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                 if (epll_div[i][0] == rate) {
-                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
-                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
-                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
-                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(epll_con, S5P_EPLL_CON);
-        __raw_writel(epll_con_k, S5P_EPLL_CON_K);
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops s5p6440_epll_ops = {
-        .get_rate = s5p6440_epll_get_rate,
-        .set_rate = s5p6440_epll_set_rate,
-};
-
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
-};
-
-enum perf_level {
-        L0 = 532*1000,
-        L1 = 266*1000,
-        L2 = 133*1000,
-};
-
-static const u32 clock_table[][3] = {
-        /*{ARM_CLK, DIVarm, DIVhclk}*/
-        {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
-        {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
-        {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
-};
-
-static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        u32 clkdiv;
-
-        /* divisor mask starts at bit0, so no need to shift */
-        clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
-
-        return rate / (clkdiv + 1);
-}
-
-static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
-                                                unsigned long rate)
-{
-        u32 iter;
-
-        for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
-                if (rate > clock_table[iter][0])
-                        return clock_table[iter-1][0];
-        }
-
-        return clock_table[ARRAY_SIZE(clock_table) - 1][0];
-}
-
-static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 round_tmp;
-        u32 iter;
-        u32 clk_div0_tmp;
-        u32 cur_rate = clk->ops->get_rate(clk);
-        unsigned long flags;
-
-        round_tmp = clk->ops->round_rate(clk, rate);
-        if (round_tmp == cur_rate)
-                return 0;
-
-
-        for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
-                if (round_tmp == clock_table[iter][0])
-                        break;
-        }
-
-        if (iter >= ARRAY_SIZE(clock_table))
-                iter = ARRAY_SIZE(clock_table) - 1;
-
-        local_irq_save(flags);
-        if (cur_rate > round_tmp) {
-                /* Frequency Down */
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
-                clk_div0_tmp |= clock_table[iter][1];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
-                                ~(S5P_CLKDIV0_HCLK_MASK);
-                clk_div0_tmp |= clock_table[iter][2];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-
-        } else {
-                /* Frequency Up */
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
-                                ~(S5P_CLKDIV0_HCLK_MASK);
-                clk_div0_tmp |= clock_table[iter][2];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-
-                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
-                clk_div0_tmp |= clock_table[iter][1];
-                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
-                }
-        local_irq_restore(flags);
-
-        clk->rate = clock_table[iter][0];
-
-        return 0;
-}
-
-static struct clk_ops s5p6440_clkarm_ops = {
-        .get_rate       = s5p6440_armclk_get_rate,
-        .set_rate       = s5p6440_armclk_set_rate,
-        .round_rate     = s5p6440_armclk_round_rate,
-};
-
-static struct clksrc_clk clk_armclk = {
-        .clk    = {
-                .name   = "armclk",
-                .id     = 1,
-                .parent = &clk_mout_apll.clk,
-                .ops    = &s5p6440_clkarm_ops,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mpll = {
-        .clk    = {
-                .name   = "dout_mpll",
-                .id     = -1,
-                .parent = &clk_mout_mpll.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_hclk = {
-        .clk    = {
-                .name   = "clk_hclk",
-                .id     = -1,
-                .parent = &clk_armclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk = {
-        .clk    = {
-                .name   = "clk_pclk",
-                .id     = -1,
-                .parent = &clk_hclk.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
-};
-
-static struct clk *clkset_hclklow_list[] = {
-        &clk_mout_apll.clk,
-        &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_hclklow = {
-        .sources        = clkset_hclklow_list,
-        .nr_sources     = ARRAY_SIZE(clkset_hclklow_list),
-};
-
-static struct clksrc_clk clk_hclk_low = {
-        .clk = {
-                .name   = "hclk_low",
-                .id     = -1,
-        },
-        .sources        = &clkset_hclklow,
-        .reg_src        = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
-        .reg_div        = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_pclk_low = {
-        .clk    = {
-                .name   = "pclk_low",
-                .id     = -1,
-                .parent = &clk_hclk_low.clk,
-        },
-        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
-};
-
-int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
-{
-        unsigned long flags;
-        u32 val;
-
-        /* can't rely on clock lock, this register has other usages */
-        local_irq_save(flags);
-
-        val = __raw_readl(S5P_OTHERS);
-        if (enable)
-                val |= S5P_OTHERS_USB_SIG_MASK;
-        else
-                val &= ~S5P_OTHERS_USB_SIG_MASK;
-
-        __raw_writel(val, S5P_OTHERS);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
-}
-
-static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
-}
-
-static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
-}
-
-static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
-}
-
-static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
-}
-
-static int s5p6440_mem_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
-}
-
-/*
- * The following clocks will be disabled during clock initialization. It is
- * recommended to keep the following clocks disabled until the driver requests
- * for enabling the clock.
- */
-static struct clk init_clocks_disable[] = {
-        {
-                .name           = "nand",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_mem_ctrl,
-                .ctrlbit        = S5P_CLKCON_MEM0_HCLK_NFCON,
-        }, {
-                .name           = "adc",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_TSADC,
-        }, {
-                .name           = "i2c",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_IIC0,
-        }, {
-                .name           = "i2s_v40",
-                .id             = 0,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_IIS2,
-        }, {
-                .name           = "spi",
-                .id             = 0,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_SPI0,
-        }, {
-                .name           = "spi",
-                .id             = 1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_SPI1,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_SPI0_48,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_SPI1_48,
-        }, {
-                .name           = "mmc_48m",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_MMC0_48,
-        }, {
-                .name           = "mmc_48m",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_MMC1_48,
-        }, {
-                .name           = "mmc_48m",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5p6440_sclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_SCLK0_MMC2_48,
-        }, {
-                .name           = "otg",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_USB
-        }, {
-                .name           = "post",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_POST0
-        }, {
-                .name           = "lcd",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk1_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK1_DISPCON,
-        }, {
-                .name           = "hsmmc",
-                .id             = 0,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .id             = 1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .id             = 2,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC2,
-        }, {
-                .name           = "rtc",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_RTC,
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_WDT,
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_PWM,
-        }, {
-                .name           = "hclk_fimgvg",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk1_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "tsi",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "pclk_fimgvg",
-                .id             = -1,
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 31),
-        }, {
-                .name           = "dmc0",
-                .id             = -1,
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 30),
-        }, {
-                .name           = "etm",
-                .id             = -1,
-                .parent         = &clk_pclk.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 29),
-        }, {
-                .name           = "dsim",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 28),
-        }, {
-                .name           = "gps",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "pcm",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "irom",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "dma",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "2d",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-};
-
-/*
- * The following clocks will be enabled during clock initialization.
- */
-static struct clk init_clocks[] = {
-        {
-                .name           = "gpio",
-                .id             = -1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_GPIO,
-        }, {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART0,
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART1,
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART2,
-        }, {
-                .name           = "uart",
-                .id             = 3,
-                .parent         = &clk_pclk_low.clk,
-                .enable         = s5p6440_pclk_ctrl,
-                .ctrlbit        = S5P_CLKCON_PCLK_UART3,
-        }, {
-                .name           = "mem",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "intc",
-                .id             = -1,
-                .parent         = &clk_hclk.clk,
-                .enable         = s5p6440_hclk0_ctrl,
-                .ctrlbit        = (1 << 1),
-        },
-};
-
-static struct clk clk_iis_cd_v40 = {
-        .name           = "iis_cdclk_v40",
-        .id             = -1,
-};
-
-static struct clk clk_pcm_cd = {
-        .name           = "pcm_cdclk",
-        .id             = -1,
-};
-
-static struct clk *clkset_group1_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_fin_epll,
-};
-
-static struct clksrc_sources clkset_group1 = {
-        .sources        = clkset_group1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
-};
-
-static struct clk *clkset_uart_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
-};
-
-static struct clk *clkset_audio_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll.clk,
-        &clk_fin_epll,
-        &clk_iis_cd_v40,
-        &clk_pcm_cd,
-};
-
-static struct clksrc_sources clkset_audio = {
-        .sources        = clkset_audio_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 0,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_MMC0,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 1,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_MMC1,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .id             = 2,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_MMC2,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .id             = -1,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_UART,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "spi_epll",
-                        .id             = 0,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_SPI0,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "spi_epll",
-                        .id             = 1,
-                        .ctrlbit        = S5P_CLKCON_SCLK0_SPI1,
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_post",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 10),
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_dispcon",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 1),
-                        .enable         = s5p6440_sclk1_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimgvg",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 2),
-                        .enable         = s5p6440_sclk1_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_audio2",
-                        .id             = -1,
-                        .ctrlbit        = (1 << 11),
-                        .enable         = s5p6440_sclk_ctrl,
-                },
-                .sources = &clkset_audio,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
-        },
-};
-
-/* Clock initialisation code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_dout_mpll,
-        &clk_armclk,
-        &clk_hclk,
-        &clk_pclk,
-        &clk_hclk_low,
-        &clk_pclk_low,
-};
-
-void __init_or_cpufreq s5p6440_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long hclk_low;
-        unsigned long pclk;
-        unsigned long pclk_low;
-        unsigned long epll;
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned int ptr;
-
-        /* Set S5P6440 functions for clk_fout_epll */
-        clk_fout_epll.enable = s5p6440_epll_enable;
-        clk_fout_epll.ops = &s5p6440_epll_ops;
-
-        clk_48m.enable = s5p6440_clk48m_ctrl;
-
-        xtal_clk = clk_get(NULL, "ext_xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
-                                __raw_readl(S5P_EPLL_CON_K));
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
-
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_apll.rate = apll;
-
-        printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
-                        " E=%ld.%ldMHz\n",
-                        print_mhz(apll), print_mhz(mpll), print_mhz(epll));
-
-        fclk = clk_get_rate(&clk_armclk.clk);
-        hclk = clk_get_rate(&clk_hclk.clk);
-        pclk = clk_get_rate(&clk_pclk.clk);
-        hclk_low = clk_get_rate(&clk_hclk_low.clk);
-        pclk_low = clk_get_rate(&clk_pclk_low.clk);
-
-        printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
-                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
-                        print_mhz(hclk), print_mhz(hclk_low),
-                        print_mhz(pclk), print_mhz(pclk_low));
-
-        clk_f.rate = fclk;
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_iis_cd_v40,
-        &clk_pcm_cd,
-};
-
-void __init s5p6440_register_clocks(void)
-{
-        struct clk *clkp;
-        int ret;
-        int ptr;
-
-        ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-        if (ret > 0)
-                printk(KERN_ERR "Failed to register %u clocks\n", ret);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
-        }
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
deleted file mode 100644
index 526f33adb31..00000000000
--- a/arch/arm/mach-s5p6440/cpu.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/cpu.c
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/proc-fns.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/irq.h>
-
-#include <plat/regs-serial.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/s5p6440.h>
-#include <plat/adc-core.h>
-
-static void s5p6440_idle(void)
-{
-        unsigned long val;
-
-        if (!need_resched()) {
-                val = __raw_readl(S5P_PWR_CFG);
-                val &= ~(0x3<<5);
-                val |= (0x1<<5);
-                __raw_writel(val, S5P_PWR_CFG);
-
-                cpu_do_idle();
-        }
-        local_irq_enable();
-}
-
-/* s5p6440_map_io
- *
- * register the standard cpu IO areas
-*/
-
-void __init s5p6440_map_io(void)
-{
-        /* initialize any device information early */
-        s3c_adc_setname("s3c64xx-adc");
-}
-
-void __init s5p6440_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5p6440_register_clocks();
-        s5p6440_setup_clocks();
-}
-
-void __init s5p6440_init_irq(void)
-{
-        /* S5P6440 supports only 2 VIC */
-        u32 vic[2];
-
-        /*
-         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
-         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
-         */
-        vic[0] = 0xff800ae7;
-        vic[1] = 0xffbf23e5;
-
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-
-struct sysdev_class s5p6440_sysclass = {
-        .name   = "s5p6440-core",
-};
-
-static struct sys_device s5p6440_sysdev = {
-        .cls    = &s5p6440_sysclass,
-};
-
-static int __init s5p6440_core_init(void)
-{
-        return sysdev_class_register(&s5p6440_sysclass);
-}
-
-core_initcall(s5p6440_core_init);
-
-int __init s5p6440_init(void)
-{
-        printk(KERN_INFO "S5P6440: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = s5p6440_idle;
-
-        return sysdev_register(&s5p6440_sysdev);
-}
diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c
deleted file mode 100644
index 3ca0d2b8275..00000000000
--- a/arch/arm/mach-s5p6440/dev-audio.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/dev-audio.c
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/audio.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-
-static int s5p6440_cfg_i2s(struct platform_device *pdev)
-{
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case -1:
-                s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
-                break;
-
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_i2s_pdata = {
-        .cfg_gpio = s5p6440_cfg_i2s,
-};
-
-static struct resource s5p6440_iis0_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_I2S,
-                .end   = S5P6440_PA_I2S + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S0_TX,
-                .end   = DMACH_I2S0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S0_RX,
-                .end   = DMACH_I2S0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6440_device_iis = {
-        .name             = "s3c64xx-iis-v4",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s5p6440_iis0_resource),
-        .resource         = s5p6440_iis0_resource,
-        .dev = {
-                .platform_data = &s3c_i2s_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
-                break;
-
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = s5p6440_pcm_cfg_gpio,
-};
-
-static struct resource s5p6440_pcm0_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_PCM,
-                .end   = S5P6440_PA_PCM + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM0_TX,
-                .end   = DMACH_PCM0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM0_RX,
-                .end   = DMACH_PCM0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6440_device_pcm = {
-        .name             = "samsung-pcm",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5p6440_pcm0_resource),
-        .resource         = s5p6440_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c
deleted file mode 100644
index 510af44d180..00000000000
--- a/arch/arm/mach-s5p6440/dev-spi.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/dev-spi.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/spi-clocks.h>
-
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-
-static char *spi_src_clks[] = {
-        [S5P6440_SPI_SRCCLK_PCLK] = "pclk",
-        [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
-                break;
-
-        case 1:
-                s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct resource s5p6440_spi0_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_SPI0,
-                .end   = S5P6440_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
-        .cfg_gpio = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x1ff,
-        .rx_lvl_offset = 15,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5p6440_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5p6440_spi0_resource),
-        .resource         = s5p6440_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5p6440_spi0_pdata,
-        },
-};
-
-static struct resource s5p6440_spi1_resource[] = {
-        [0] = {
-                .start = S5P6440_PA_SPI1,
-                .end   = S5P6440_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
-        .cfg_gpio = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 15,
-};
-
-struct platform_device s5p6440_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5p6440_spi1_resource),
-        .resource         = s5p6440_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5p6440_spi1_pdata,
-        },
-};
-
-void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                pd = &s5p6440_spi0_pdata;
-                break;
-        case 1:
-                pd = &s5p6440_spi1_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S
deleted file mode 100644
index 1347d7f9907..00000000000
--- a/arch/arm/mach-s5p6440/include/mach/debug-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <mach/map.h>
-#include <plat/regs-serial.h>
-
-        /* note, for the boot process to work we have to keep the UART
-         * virtual address aligned to an 1MiB boundary for the L1
-         * mapping the head code makes. We keep the UART virtual address
-         * aligned and add in the offset when we load the value here.
-         */
-
-        .macro addruart, rx, rtmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = S3C_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-
-/* include the reset of the code which will do the work, we're only
- * compiling for a single cpu processor type so the default of s3c2440
- * will be fine with us.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h
deleted file mode 100644
index 21783834f2a..00000000000
--- a/arch/arm/mach-s5p6440/include/mach/gpio.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-#define gpio_to_irq     __gpio_to_irq
-
-/* GPIO bank sizes */
-#define S5P6440_GPIO_A_NR       (6)
-#define S5P6440_GPIO_B_NR       (7)
-#define S5P6440_GPIO_C_NR       (8)
-#define S5P6440_GPIO_F_NR       (2)
-#define S5P6440_GPIO_G_NR       (7)
-#define S5P6440_GPIO_H_NR       (10)
-#define S5P6440_GPIO_I_NR       (16)
-#define S5P6440_GPIO_J_NR       (12)
-#define S5P6440_GPIO_N_NR       (16)
-#define S5P6440_GPIO_P_NR       (8)
-#define S5P6440_GPIO_R_NR       (15)
-
-/* GPIO bank numbers */
-
-/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
- * space for debugging purposes so that any accidental
- * change from one gpio bank to another can be caught.
-*/
-#define S5P6440_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p_gpio_number {
-        S5P6440_GPIO_A_START = 0,
-        S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A),
-        S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B),
-        S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C),
-        S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F),
-        S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G),
-        S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H),
-        S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I),
-        S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J),
-        S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N),
-        S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P),
-};
-
-/* S5P6440 GPIO number definitions. */
-#define S5P6440_GPA(_nr)        (S5P6440_GPIO_A_START + (_nr))
-#define S5P6440_GPB(_nr)        (S5P6440_GPIO_B_START + (_nr))
-#define S5P6440_GPC(_nr)        (S5P6440_GPIO_C_START + (_nr))
-#define S5P6440_GPF(_nr)        (S5P6440_GPIO_F_START + (_nr))
-#define S5P6440_GPG(_nr)        (S5P6440_GPIO_G_START + (_nr))
-#define S5P6440_GPH(_nr)        (S5P6440_GPIO_H_START + (_nr))
-#define S5P6440_GPI(_nr)        (S5P6440_GPIO_I_START + (_nr))
-#define S5P6440_GPJ(_nr)        (S5P6440_GPIO_J_START + (_nr))
-#define S5P6440_GPN(_nr)        (S5P6440_GPIO_N_START + (_nr))
-#define S5P6440_GPP(_nr)        (S5P6440_GPIO_P_START + (_nr))
-#define S5P6440_GPR(_nr)        (S5P6440_GPIO_R_START + (_nr))
-
-/* the end of the S5P6440 specific gpios */
-#define S5P6440_GPIO_END        (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
-#define S3C_GPIO_END            S5P6440_GPIO_END
-
-/* define the number of gpios we need to the one after the GPR() range */
-#define ARCH_NR_GPIOS           (S5P6440_GPR(S5P6440_GPIO_R_NR) +       \
-                                 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
-
-#include <asm-generic/gpio.h>
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
deleted file mode 100644
index fa2d69cb1ad..00000000000
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s5p6440/include/mach/io.h
- *
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben-linux@fluff.org>
- *
- * Default IO routines for S3C64XX based
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No current ISA/PCI bus support. */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
deleted file mode 100644
index 6cc5cbc88ff..00000000000
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/map.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map-s5p.h>
-
-#define S5P6440_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5P6440_PA_CHIPID
-
-#define S5P6440_PA_SYSCON       (0xE0100000)
-#define S5P6440_PA_CLK          (S5P6440_PA_SYSCON + 0x0)
-#define S5P_PA_SYSCON           S5P6440_PA_SYSCON
-
-#define S5P6440_PA_GPIO         (0xE0308000)
-#define S5P_PA_GPIO             S5P6440_PA_GPIO
-
-#define S5P6440_PA_VIC0         (0xE4000000)
-#define S5P_PA_VIC0             S5P6440_PA_VIC0
-
-#define S5P6440_PA_PDMA         0xE9000000
-
-#define S5P6440_PA_VIC1         (0xE4100000)
-#define S5P_PA_VIC1             S5P6440_PA_VIC1
-
-#define S5P6440_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5P6440_PA_TIMER
-
-#define S5P6440_PA_RTC          (0xEA100000)
-
-#define S5P6440_PA_WDT          (0xEA200000)
-#define S5P_PA_WDT              S5P6440_PA_WDT
-
-#define S5P6440_PA_UART         (0xEC000000)
-
-#define S5P_PA_UART0            (S5P6440_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5P6440_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5P6440_PA_UART + 0x800)
-#define S5P_PA_UART3            (S5P6440_PA_UART + 0xC00)
-
-#define S5P_SZ_UART             SZ_256
-
-#define S5P6440_PA_IIC0         (0xEC104000)
-#define S5P6440_PA_IIC1         (0xEC20F000)
-
-#define S5P6440_PA_SPI0         0xEC400000
-#define S5P6440_PA_SPI1         0xEC500000
-
-#define S5P6440_PA_HSOTG        (0xED100000)
-
-#define S5P6440_PA_HSMMC0       (0xED800000)
-#define S5P6440_PA_HSMMC1       (0xED900000)
-#define S5P6440_PA_HSMMC2       (0xEDA00000)
-
-#define S5P6440_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5P6440_PA_SDRAM
-
-/* I2S */
-#define S5P6440_PA_I2S          0xF2000000
-
-/* PCM */
-#define S5P6440_PA_PCM          0xF2100000
-
-#define S5P6440_PA_ADC          (0xF3000000)
-
-/* compatibiltiy defines. */
-#define S3C_PA_UART             S5P6440_PA_UART
-#define S3C_PA_IIC              S5P6440_PA_IIC0
-#define S3C_PA_RTC              S5P6440_PA_RTC
-#define S3C_PA_IIC1             S5P6440_PA_IIC1
-#define S3C_PA_WDT              S5P6440_PA_WDT
-
-#define SAMSUNG_PA_ADC          S5P6440_PA_ADC
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h
deleted file mode 100644
index c783ecc9f19..00000000000
--- a/arch/arm/mach-s5p6440/include/mach/regs-clock.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
-
-#define S5P_APLL_LOCK           S5P_CLKREG(0x00)
-#define S5P_MPLL_LOCK           S5P_CLKREG(0x04)
-#define S5P_EPLL_LOCK           S5P_CLKREG(0x08)
-#define S5P_APLL_CON            S5P_CLKREG(0x0C)
-#define S5P_MPLL_CON            S5P_CLKREG(0x10)
-#define S5P_EPLL_CON            S5P_CLKREG(0x14)
-#define S5P_EPLL_CON_K          S5P_CLKREG(0x18)
-#define S5P_CLK_SRC0            S5P_CLKREG(0x1C)
-#define S5P_CLK_DIV0            S5P_CLKREG(0x20)
-#define S5P_CLK_DIV1            S5P_CLKREG(0x24)
-#define S5P_CLK_DIV2            S5P_CLKREG(0x28)
-#define S5P_CLK_OUT             S5P_CLKREG(0x2C)
-#define S5P_CLK_GATE_HCLK0      S5P_CLKREG(0x30)
-#define S5P_CLK_GATE_PCLK       S5P_CLKREG(0x34)
-#define S5P_CLK_GATE_SCLK0      S5P_CLKREG(0x38)
-#define S5P_CLK_GATE_MEM0       S5P_CLKREG(0x3C)
-#define S5P_CLK_DIV3            S5P_CLKREG(0x40)
-#define S5P_CLK_GATE_HCLK1      S5P_CLKREG(0x44)
-#define S5P_CLK_GATE_SCLK1      S5P_CLKREG(0x48)
-#define S5P_AHB_CON0            S5P_CLKREG(0x100)
-#define S5P_CLK_SRC1            S5P_CLKREG(0x10C)
-#define S5P_SWRESET             S5P_CLKREG(0x114)
-#define S5P_SYS_ID              S5P_CLKREG(0x118)
-#define S5P_SYS_OTHERS          S5P_CLKREG(0x11C)
-#define S5P_MEM_CFG_STAT        S5P_CLKREG(0x12C)
-#define S5P_PWR_CFG             S5P_CLKREG(0x804)
-#define S5P_EINT_WAKEUP_MASK    S5P_CLKREG(0x808)
-#define S5P_NORMAL_CFG          S5P_CLKREG(0x810)
-#define S5P_STOP_CFG            S5P_CLKREG(0x814)
-#define S5P_SLEEP_CFG           S5P_CLKREG(0x818)
-#define S5P_OSC_FREQ            S5P_CLKREG(0x820)
-#define S5P_OSC_STABLE          S5P_CLKREG(0x824)
-#define S5P_PWR_STABLE          S5P_CLKREG(0x828)
-#define S5P_MTC_STABLE          S5P_CLKREG(0x830)
-#define S5P_OTHERS              S5P_CLKREG(0x900)
-#define S5P_RST_STAT            S5P_CLKREG(0x904)
-#define S5P_WAKEUP_STAT         S5P_CLKREG(0x908)
-#define S5P_SLPEN               S5P_CLKREG(0x930)
-#define S5P_INFORM0             S5P_CLKREG(0xA00)
-#define S5P_INFORM1             S5P_CLKREG(0xA04)
-#define S5P_INFORM2             S5P_CLKREG(0xA08)
-#define S5P_INFORM3             S5P_CLKREG(0xA0C)
-
-/* CLKDIV0 */
-#define S5P_CLKDIV0_PCLK_MASK           (0xf << 12)
-#define S5P_CLKDIV0_PCLK_SHIFT          (12)
-#define S5P_CLKDIV0_HCLK_MASK           (0xf << 8)
-#define S5P_CLKDIV0_HCLK_SHIFT          (8)
-#define S5P_CLKDIV0_MPLL_MASK           (0x1 << 4)
-#define S5P_CLKDIV0_ARM_MASK            (0xf << 0)
-#define S5P_CLKDIV0_ARM_SHIFT           (0)
-
-/* CLKDIV3 */
-#define S5P_CLKDIV3_PCLK_LOW_MASK       (0xf << 12)
-#define S5P_CLKDIV3_PCLK_LOW_SHIFT      (12)
-#define S5P_CLKDIV3_HCLK_LOW_MASK       (0xf << 8)
-#define S5P_CLKDIV3_HCLK_LOW_SHIFT      (8)
-
-/* HCLK0 GATE Registers */
-#define S5P_CLKCON_HCLK0_USB            (1<<20)
-#define S5P_CLKCON_HCLK0_HSMMC2         (1<<19)
-#define S5P_CLKCON_HCLK0_HSMMC1         (1<<18)
-#define S5P_CLKCON_HCLK0_HSMMC0         (1<<17)
-#define S5P_CLKCON_HCLK0_POST0          (1<<5)
-
-/* HCLK1 GATE Registers */
-#define S5P_CLKCON_HCLK1_DISPCON        (1<<1)
-
-/* PCLK GATE Registers */
-#define S5P_CLKCON_PCLK_IIS2            (1<<26)
-#define S5P_CLKCON_PCLK_SPI1            (1<<22)
-#define S5P_CLKCON_PCLK_SPI0            (1<<21)
-#define S5P_CLKCON_PCLK_GPIO            (1<<18)
-#define S5P_CLKCON_PCLK_IIC0            (1<<17)
-#define S5P_CLKCON_PCLK_TSADC           (1<<12)
-#define S5P_CLKCON_PCLK_PWM             (1<<7)
-#define S5P_CLKCON_PCLK_RTC             (1<<6)
-#define S5P_CLKCON_PCLK_WDT             (1<<5)
-#define S5P_CLKCON_PCLK_UART3           (1<<4)
-#define S5P_CLKCON_PCLK_UART2           (1<<3)
-#define S5P_CLKCON_PCLK_UART1           (1<<2)
-#define S5P_CLKCON_PCLK_UART0           (1<<1)
-
-/* SCLK0 GATE Registers */
-#define S5P_CLKCON_SCLK0_MMC2_48        (1<<29)
-#define S5P_CLKCON_SCLK0_MMC1_48        (1<<28)
-#define S5P_CLKCON_SCLK0_MMC0_48        (1<<27)
-#define S5P_CLKCON_SCLK0_MMC2           (1<<26)
-#define S5P_CLKCON_SCLK0_MMC1           (1<<25)
-#define S5P_CLKCON_SCLK0_MMC0           (1<<24)
-#define S5P_CLKCON_SCLK0_SPI1_48        (1<<23)
-#define S5P_CLKCON_SCLK0_SPI0_48        (1<<22)
-#define S5P_CLKCON_SCLK0_SPI1           (1<<21)
-#define S5P_CLKCON_SCLK0_SPI0           (1<<20)
-#define S5P_CLKCON_SCLK0_UART           (1<<5)
-
-/* SCLK1 GATE Registers */
-
-/* MEM0 GATE Registers */
-#define S5P_CLKCON_MEM0_HCLK_NFCON      (1<<2)
-
-/*OTHERS Resgister */
-#define S5P_OTHERS_USB_SIG_MASK         (1<<16)
-#define S5P_OTHERS_HCLK_LOW_SEL_MPLL    (1<<6)
-
-/* Compatibility defines */
-#define ARM_CLK_DIV                     S5P_CLK_DIV0
-#define ARM_DIV_RATIO_SHIFT             0
-#define ARM_DIV_MASK                    (0xf << ARM_DIV_RATIO_SHIFT)
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
deleted file mode 100644
index 5fbca50d1cf..00000000000
--- a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S5P6440_PLAT_SPI_CLKS_H
-#define __S5P6440_PLAT_SPI_CLKS_H __FILE__
-
-#define S5P6440_SPI_SRCCLK_PCLK         0
-#define S5P6440_SPI_SRCCLK_SCLK         1
-
-#endif /* __S5P6440_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h
deleted file mode 100644
index 7c1f600d65c..00000000000
--- a/arch/arm/mach-s5p6440/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <mach/map.h>
-#include <plat/uncompress.h>
-
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-}
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/init.c b/arch/arm/mach-s5p6440/init.c
deleted file mode 100644
index a1f3727e402..00000000000
--- a/arch/arm/mach-s5p6440/init.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/mach-s5p6440/init.c
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6440 - Init support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/s5p6440.h>
-#include <plat/regs-serial.h>
-
-static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = {
-        [0] = {
-                .name           = "pclk_low",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "uclk1",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-
-/* uart registration process */
-void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->clocks = s5p6440_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks);
-                }
-        }
-
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
index a48fb553fd0..842af86bda6 100644
--- a/arch/arm/mach-s5p6442/cpu.c
+++ b/arch/arm/mach-s5p6442/cpu.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-s5p6442/cpu.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,7 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/sched.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -47,10 +48,30 @@ static struct map_desc s5p6442_iodesc[] __initdata = {
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5P6442_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5P6442_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5P6442_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)VA_VIC2,
                 .pfn            = __phys_to_pfn(S5P6442_PA_VIC2),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
         }
 };
 
@@ -62,10 +83,11 @@ static void s5p6442_idle(void)
         local_irq_enable();
 }
 
-/* s5p6442_map_io
+/*
+ * s5p6442_map_io
  *
  * register the standard cpu IO areas
-*/
+ */
 
 void __init s5p6442_map_io(void)
 {
diff --git a/arch/arm/mach-s5p6442/include/mach/debug-macro.S b/arch/arm/mach-s5p6442/include/mach/debug-macro.S
index bb6536147ff..e2213205d78 100644
--- a/arch/arm/mach-s5p6442/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5p6442/include/mach/debug-macro.S
@@ -15,13 +15,12 @@
 #include <mach/map.h>
 #include <plat/regs-serial.h>
 
-        .macro addruart, rx, rtmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = S3C_VA_UART
+        .macro addruart, rp, rv
+                ldr     \rp, = S3C_PA_UART
+                ldr     \rv, = S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
 #endif
         .endm
 
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 281d256faaf..31fb2e68d52 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -23,16 +23,10 @@
 #define S5P_PA_SYSCON           S5P6442_PA_SYSCON
 
 #define S5P6442_PA_GPIO         (0xE0200000)
-#define S5P_PA_GPIO             S5P6442_PA_GPIO
 
 #define S5P6442_PA_VIC0         (0xE4000000)
-#define S5P_PA_VIC0             S5P6442_PA_VIC0
-
 #define S5P6442_PA_VIC1         (0xE4100000)
-#define S5P_PA_VIC1             S5P6442_PA_VIC1
-
 #define S5P6442_PA_VIC2         (0xE4200000)
-#define S5P_PA_VIC2             S5P6442_PA_VIC2
 
 #define S5P6442_PA_MDMA         0xE8000000
 #define S5P6442_PA_PDMA         0xE9000000
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
index 8d8d04272f8..819fd80d00a 100644
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ b/arch/arm/mach-s5p6442/mach-smdk6442.c
@@ -83,8 +83,6 @@ static void __init smdk6442_machine_init(void)
 
 MACHINE_START(SMDK6442, "SMDK6442")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5p6442_init_irq,
         .map_io         = smdk6442_map_io,
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
new file mode 100644
index 00000000000..fbcae935202
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -0,0 +1,57 @@
+# arch/arm/mach-s5p64x0/Kconfig
+#
+# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+if ARCH_S5P64X0
+
+config CPU_S5P6440
+        bool
+        select PLAT_S5P
+        select S3C_PL330_DMA
+        help
+          Enable S5P6440 CPU support
+
+config CPU_S5P6450
+        bool
+        select PLAT_S5P
+        select S3C_PL330_DMA
+        help
+          Enable S5P6450 CPU support
+
+config S5P64X0_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+
+# machine support
+
+config MACH_SMDK6440
+        bool "SMDK6440"
+        select CPU_S5P6440
+        select S3C_DEV_I2C1
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C64XX_DEV_SPI
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDK6440
+
+config MACH_SMDK6450
+        bool "SMDK6450"
+        select CPU_S5P6450
+        select S3C_DEV_I2C1
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C64XX_DEV_SPI
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDK6450
+
+endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
new file mode 100644
index 00000000000..2655829e6bf
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -0,0 +1,30 @@
+# arch/arm/mach-s5p64x0/Makefile
+#
+# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# Core support for S5P64X0 system
+
+obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o
+obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o
+obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o gpio.o
+obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
+obj-$(CONFIG_MACH_SMDK6450)     += mach-smdk6450.o
+
+# device support
+
+obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
+
+obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
index ff90aa13bd6..ff90aa13bd6 100644
--- a/arch/arm/mach-s5p6440/Makefile.boot
+++ b/arch/arm/mach-s5p64x0/Makefile.boot
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
new file mode 100644
index 00000000000..f93dcd8b4d6
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -0,0 +1,626 @@
+/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P6440 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/s5p64x0-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6440.h>
+
+static u32 epll_div[][5] = {
+        { 36000000,     0,      48, 1, 4 },
+        { 48000000,     0,      32, 1, 3 },
+        { 60000000,     0,      40, 1, 3 },
+        { 72000000,     0,      48, 1, 3 },
+        { 84000000,     0,      28, 1, 2 },
+        { 96000000,     0,      32, 1, 2 },
+        { 32768000,     45264,  43, 1, 4 },
+        { 45158000,     6903,   30, 1, 3 },
+        { 49152000,     50332,  32, 1, 3 },
+        { 67738000,     10398,  45, 1, 3 },
+        { 73728000,     9961,   49, 1, 3 }
+};
+
+static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+
+        if (clk->rate == rate)  /* Return if nothing changed */
+                return 0;
+
+        epll_con = __raw_readl(S5P64X0_EPLL_CON);
+        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
+
+        epll_con_k &= ~(PLL90XX_KDIV_MASK);
+        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                 if (epll_div[i][0] == rate) {
+                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
+                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
+                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
+                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P64X0_EPLL_CON);
+        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5p6440_epll_ops = {
+        .get_rate = s5p64x0_epll_get_rate,
+        .set_rate = s5p6440_epll_set_rate,
+};
+
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name           = "clk_hclk",
+                .id             = -1,
+                .parent         = &clk_armclk.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name           = "clk_pclk",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_hclk_low = {
+        .clk    = {
+                .name           = "clk_hclk_low",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name           = "clk_pclk_low",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
+};
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_mem_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "post",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 5)
+        }, {
+                .name           = "2d",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 20)
+        }, {
+                .name           = "irom",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "hclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "tsi",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "pcm",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "gps",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "i2s_v40",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
+                .name           = "dsim",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "etm",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }, {
+                .name           = "pclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 31),
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 23),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        },
+};
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 18),
+        },
+};
+
+static struct clk clk_iis_cd_v40 = {
+        .name           = "iis_cdclk_v40",
+        .id             = -1,
+};
+
+static struct clk clk_pcm_cd = {
+        .name           = "pcm_cdclk",
+        .id             = -1,
+};
+
+static struct clk *clkset_group1_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+};
+
+static struct clksrc_sources clkset_group1 = {
+        .sources        = clkset_group1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
+};
+
+static struct clk *clkset_uart_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_audio_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+static struct clksrc_sources clkset_audio = {
+        .sources        = clkset_audio_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
+};
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 24),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 25),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 26),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 5),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 20),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 21),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_post",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimgvg",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio2",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 11),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_audio,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
+        },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
+};
+
+void __init_or_cpufreq s5p6440_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+
+        unsigned long xtal;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long hclk_low;
+        unsigned long pclk;
+        unsigned long pclk_low;
+
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned int ptr;
+
+        /* Set S5P6440 functions for clk_fout_epll */
+
+        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.ops = &s5p6440_epll_ops;
+
+        clk_48m.enable = s5p64x0_clk48m_ctrl;
+
+        xtal_clk = clk_get(NULL, "ext_xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
+        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
+        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
+                                __raw_readl(S5P64X0_EPLL_CON_K));
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+
+        printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
+                        " E=%ld.%ldMHz\n",
+                        print_mhz(apll), print_mhz(mpll), print_mhz(epll));
+
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
+
+        printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
+                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
+                        print_mhz(hclk), print_mhz(hclk_low),
+                        print_mhz(pclk), print_mhz(pclk_low));
+
+        clk_f.rate = fclk;
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+void __init s5p6440_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
new file mode 100644
index 00000000000..f9afb05b217
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -0,0 +1,655 @@
+/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P6450 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/s5p64x0-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6450.h>
+
+static struct clksrc_clk clk_mout_dpll = {
+        .clk    = {
+                .name           = "mout_dpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_dpll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
+};
+
+static u32 epll_div[][5] = {
+        { 133000000,    27307,  55, 2, 2 },
+        { 100000000,    43691,  41, 2, 2 },
+        { 480000000,    0,      80, 2, 0 },
+};
+
+static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+
+        if (clk->rate == rate)  /* Return if nothing changed */
+                return 0;
+
+        epll_con = __raw_readl(S5P64X0_EPLL_CON);
+        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
+
+        epll_con_k &= ~(PLL90XX_KDIV_MASK);
+        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                 if (epll_div[i][0] == rate) {
+                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
+                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
+                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
+                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P64X0_EPLL_CON);
+        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5p6450_epll_ops = {
+        .get_rate = s5p64x0_epll_get_rate,
+        .set_rate = s5p6450_epll_set_rate,
+};
+
+static struct clksrc_clk clk_dout_epll = {
+        .clk    = {
+                .name           = "dout_epll",
+                .id             = -1,
+                .parent         = &clk_mout_epll.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
+};
+
+static struct clksrc_clk clk_mout_hclk_sel = {
+        .clk    = {
+                .name           = "mout_hclk_sel",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
+};
+
+static struct clk *clkset_hclk_list[] = {
+        &clk_mout_hclk_sel.clk,
+        &clk_armclk.clk,
+};
+
+static struct clksrc_sources clkset_hclk = {
+        .sources        = clkset_hclk_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclk_list),
+};
+
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name           = "clk_hclk",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name           = "clk_pclk",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+        },
+        .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_dout_pwm_ratio0 = {
+        .clk    = {
+                .name           = "clk_dout_pwm_ratio0",
+                .id             = -1,
+                .parent         = &clk_mout_hclk_sel.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_to_wdt_pwm = {
+        .clk    = {
+                .name           = "clk_pclk_to_wdt_pwm",
+                .id             = -1,
+                .parent         = &clk_dout_pwm_ratio0.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
+};
+
+static struct clksrc_clk clk_hclk_low = {
+        .clk    = {
+                .name           = "clk_hclk_low",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name           = "clk_pclk_low",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
+};
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "usbhost",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "usbotg",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "iis",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
+                .name           = "i2c",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }
+};
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_pclk_to_wdt_pwm.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 18),
+        },
+};
+
+static struct clk *clkset_uart_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_mali_list[] = {
+        &clk_mout_epll.clk,
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_mali = {
+        .sources        = clkset_mali_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mali_list),
+};
+
+static struct clk *clkset_group2_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+};
+
+static struct clksrc_sources clkset_group2 = {
+        .sources        = clkset_group2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group2_list),
+};
+
+static struct clk *clkset_dispcon_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+        &clk_mout_dpll.clk,
+};
+
+static struct clksrc_sources clkset_dispcon = {
+        .sources        = clkset_dispcon_list,
+        .nr_sources     = ARRAY_SIZE(clkset_dispcon_list),
+};
+
+static struct clk *clkset_hsmmc44_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+        &s5p_clk_27m,
+        &clk_48m,
+};
+
+static struct clksrc_sources clkset_hsmmc44 = {
+        .sources        = clkset_hsmmc44_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hsmmc44_list),
+};
+
+static struct clk *clkset_sclk_audio0_list[] = {
+        [0] = &clk_dout_epll.clk,
+        [1] = &clk_dout_mpll.clk,
+        [2] = &clk_ext_xtal_mux,
+        [3] = NULL,
+        [4] = NULL,
+};
+
+static struct clksrc_sources clkset_sclk_audio0 = {
+        .sources        = clkset_sclk_audio0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk clk_sclk_audio0 = {
+        .clk            = {
+                .name           = "audio-bus",
+                .id             = -1,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 8),
+                .parent         = &clk_dout_epll.clk,
+        },
+        .sources        = &clkset_sclk_audio0,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 24),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 25),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 26),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 5),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 20),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 21),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "aclk_mali",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_mali,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_2d",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 12),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_mali,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_usi",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 7),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_camif",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 6),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_dispcon,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_hsmmc44",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 30),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_hsmmc44,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
+        },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_dout_epll,
+        &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_mout_hclk_sel,
+        &clk_dout_pwm_ratio0,
+        &clk_pclk_to_wdt_pwm,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
+        &clk_sclk_audio0,
+};
+
+void __init_or_cpufreq s5p6450_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+
+        unsigned long xtal;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long hclk_low;
+        unsigned long pclk;
+        unsigned long pclk_low;
+
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned long dpll;
+        unsigned int ptr;
+
+        /* Set S5P6450 functions for clk_fout_epll */
+
+        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.ops = &s5p6450_epll_ops;
+
+        clk_48m.enable = s5p64x0_clk48m_ctrl;
+
+        xtal_clk = clk_get(NULL, "ext_xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
+        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
+        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
+                                __raw_readl(S5P64X0_EPLL_CON_K));
+        dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
+                                __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_dpll.rate = dpll;
+
+        printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
+                        " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
+                        print_mhz(apll), print_mhz(mpll), print_mhz(epll),
+                        print_mhz(dpll));
+
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
+
+        printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
+                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
+                        print_mhz(hclk), print_mhz(hclk_low),
+                        print_mhz(pclk), print_mhz(pclk_low));
+
+        clk_f.rate = fclk;
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+void __init s5p6450_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
new file mode 100644
index 00000000000..523ba8039ac
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -0,0 +1,253 @@
+/* linux/arch/arm/mach-s5p64x0/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+
+struct clksrc_clk clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_apll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
+};
+
+struct clksrc_clk clk_mout_mpll = {
+        .clk    = {
+                .name           = "mout_mpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mpll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
+};
+
+struct clksrc_clk clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_epll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
+};
+
+enum perf_level {
+        L0 = 532*1000,
+        L1 = 266*1000,
+        L2 = 133*1000,
+};
+
+static const u32 clock_table[][3] = {
+        /*{ARM_CLK, DIVarm, DIVhclk}*/
+        {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+        {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+        {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+};
+
+int s5p64x0_epll_enable(struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
+
+        if (enable)
+                __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
+        else
+                __raw_writel(epll_con, S5P64X0_EPLL_CON);
+
+        return 0;
+}
+
+unsigned long s5p64x0_epll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        u32 clkdiv;
+
+        /* divisor mask starts at bit0, so no need to shift */
+        clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
+
+        return rate / (clkdiv + 1);
+}
+
+unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 iter;
+
+        for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
+                if (rate > clock_table[iter][0])
+                        return clock_table[iter-1][0];
+        }
+
+        return clock_table[ARRAY_SIZE(clock_table) - 1][0];
+}
+
+int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 round_tmp;
+        u32 iter;
+        u32 clk_div0_tmp;
+        u32 cur_rate = clk->ops->get_rate(clk);
+        unsigned long flags;
+
+        round_tmp = clk->ops->round_rate(clk, rate);
+        if (round_tmp == cur_rate)
+                return 0;
+
+
+        for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
+                if (round_tmp == clock_table[iter][0])
+                        break;
+        }
+
+        if (iter >= ARRAY_SIZE(clock_table))
+                iter = ARRAY_SIZE(clock_table) - 1;
+
+        local_irq_save(flags);
+        if (cur_rate > round_tmp) {
+                /* Frequency Down */
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
+                clk_div0_tmp |= clock_table[iter][1];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
+                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
+                clk_div0_tmp |= clock_table[iter][2];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+
+        } else {
+                /* Frequency Up */
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
+                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
+                clk_div0_tmp |= clock_table[iter][2];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
+                clk_div0_tmp |= clock_table[iter][1];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+        }
+        local_irq_restore(flags);
+
+        clk->rate = clock_table[iter][0];
+
+        return 0;
+}
+
+struct clk_ops s5p64x0_clkarm_ops = {
+        .get_rate       = s5p64x0_armclk_get_rate,
+        .set_rate       = s5p64x0_armclk_set_rate,
+        .round_rate     = s5p64x0_armclk_round_rate,
+};
+
+struct clksrc_clk clk_armclk = {
+        .clk    = {
+                .name           = "armclk",
+                .id             = 1,
+                .parent         = &clk_mout_apll.clk,
+                .ops            = &s5p64x0_clkarm_ops,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
+};
+
+struct clksrc_clk clk_dout_mpll = {
+        .clk    = {
+                .name           = "dout_mpll",
+                .id             = -1,
+                .parent         = &clk_mout_mpll.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
+};
+
+struct clk *clkset_hclk_low_list[] = {
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+struct clksrc_sources clkset_hclk_low = {
+        .sources        = clkset_hclk_low_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclk_low_list),
+};
+
+int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
+}
+
+int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
+}
+
+int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
+}
+
+int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
+}
+
+int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
+}
+
+int s5p64x0_mem_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
+}
+
+int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
+{
+        unsigned long flags;
+        u32 val;
+
+        /* can't rely on clock lock, this register has other usages */
+        local_irq_save(flags);
+
+        val = __raw_readl(S5P64X0_OTHERS);
+        if (enable)
+                val |= S5P64X0_OTHERS_USB_SIG_MASK;
+        else
+                val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
+
+        __raw_writel(val, S5P64X0_OTHERS);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
new file mode 100644
index 00000000000..b8d02eb4cf3
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -0,0 +1,209 @@
+/* linux/arch/arm/mach-s5p64x0/cpu.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/proc-fns.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/regs-serial.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+#include <plat/adc-core.h>
+
+/* Initial IO mappings */
+
+static struct map_desc s5p64x0_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc s5p6440_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc s5p6450_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static void s5p64x0_idle(void)
+{
+        unsigned long val;
+
+        if (!need_resched()) {
+                val = __raw_readl(S5P64X0_PWR_CFG);
+                val &= ~(0x3 << 5);
+                val |= (0x1 << 5);
+                __raw_writel(val, S5P64X0_PWR_CFG);
+
+                cpu_do_idle();
+        }
+        local_irq_enable();
+}
+
+/*
+ * s5p64x0_map_io
+ *
+ * register the standard CPU IO areas
+ */
+
+void __init s5p6440_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+
+        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+}
+
+void __init s5p6450_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+
+        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+}
+
+/*
+ * s5p64x0_init_clocks
+ *
+ * register and setup the CPU clocks
+ */
+
+void __init s5p6440_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6440_register_clocks();
+        s5p6440_setup_clocks();
+}
+
+void __init s5p6450_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6450_register_clocks();
+        s5p6450_setup_clocks();
+}
+
+/*
+ * s5p64x0_init_irq
+ *
+ * register the CPU interrupts
+ */
+
+void __init s5p6440_init_irq(void)
+{
+        /* S5P6440 supports 2 VIC */
+        u32 vic[2];
+
+        /*
+         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
+         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
+         */
+        vic[0] = 0xff800ae7;
+        vic[1] = 0xffbf23e5;
+
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+
+void __init s5p6450_init_irq(void)
+{
+        /* S5P6450 supports only 2 VIC */
+        u32 vic[2];
+
+        /*
+         * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
+         * VIC1 is missing IRQ VIC1[12, 14, 23]
+         */
+        vic[0] = 0xff9f1fff;
+        vic[1] = 0xff7fafff;
+
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+
+struct sysdev_class s5p64x0_sysclass = {
+        .name   = "s5p64x0-core",
+};
+
+static struct sys_device s5p64x0_sysdev = {
+        .cls    = &s5p64x0_sysclass,
+};
+
+static int __init s5p64x0_core_init(void)
+{
+        return sysdev_class_register(&s5p64x0_sysclass);
+}
+core_initcall(s5p64x0_core_init);
+
+int __init s5p64x0_init(void)
+{
+        printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
+
+        /* set idle function */
+        pm_idle = s5p64x0_idle;
+
+        return sysdev_register(&s5p64x0_sysdev);
+}
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
new file mode 100644
index 00000000000..fa097bd68ca
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -0,0 +1,164 @@
+/* linux/arch/arm/mach-s5p64x0/dev-audio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static int s5p6440_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case -1:
+                s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int s5p6450_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case -1:
+                s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s5p6440_i2s_pdata = {
+        .cfg_gpio = s5p6440_cfg_i2s,
+};
+
+static struct s3c_audio_pdata s5p6450_i2s_pdata = {
+        .cfg_gpio = s5p6450_cfg_i2s,
+};
+
+static struct resource s5p64x0_iis0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_I2S,
+                .end    = S5P64X0_PA_I2S + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_I2S0_TX,
+                .end    = DMACH_I2S0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_I2S0_RX,
+                .end    = DMACH_I2S0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_iis = {
+        .name           = "s3c64xx-iis-v4",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
+        .resource       = s5p64x0_iis0_resource,
+        .dev = {
+                .platform_data = &s5p6440_i2s_pdata,
+        },
+};
+
+struct platform_device s5p6450_device_iis0 = {
+        .name           = "s3c64xx-iis-v4",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
+        .resource       = s5p64x0_iis0_resource,
+        .dev = {
+                .platform_data = &s5p6450_i2s_pdata,
+        },
+};
+
+/* PCM Controller platform_devices */
+
+static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
+                break;
+
+        default:
+                printk(KERN_DEBUG "Invalid PCM Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s5p6440_pcm_pdata = {
+        .cfg_gpio = s5p6440_pcm_cfg_gpio,
+};
+
+static struct resource s5p6440_pcm0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_PCM,
+                .end    = S5P64X0_PA_PCM + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_PCM0_TX,
+                .end    = DMACH_PCM0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_PCM0_RX,
+                .end    = DMACH_PCM0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_pcm = {
+        .name           = "samsung-pcm",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p6440_pcm0_resource),
+        .resource       = s5p6440_pcm0_resource,
+        .dev = {
+                .platform_data = &s5p6440_pcm_pdata,
+        },
+};
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
new file mode 100644
index 00000000000..5b69ec4c8af
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -0,0 +1,232 @@
+/* linux/arch/arm/mach-s5p64x0/dev-spi.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/regs-clock.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+
+static char *s5p64x0_spi_src_clks[] = {
+        [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
+        [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5p64x0_spi0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_SPI0,
+                .end    = S5P64X0_PA_SPI0 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPI0_TX,
+                .end    = DMACH_SPI0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_SPI0_RX,
+                .end    = DMACH_SPI0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = IRQ_SPI0,
+                .end    = IRQ_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
+        .cfg_gpio       = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+};
+
+static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
+        .cfg_gpio       = s5p6450_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p64x0_device_spi0 = {
+        .name           = "s3c64xx-spi",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p64x0_spi0_resource),
+        .resource       = s5p64x0_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource s5p64x0_spi1_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_SPI1,
+                .end    = S5P64X0_PA_SPI1 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPI1_TX,
+                .end    = DMACH_SPI1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_SPI1_RX,
+                .end    = DMACH_SPI1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = IRQ_SPI1,
+                .end    = IRQ_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
+        .cfg_gpio       = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+};
+
+static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
+        .cfg_gpio       = s5p6450_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+};
+
+struct platform_device s5p64x0_device_spi1 = {
+        .name           = "s3c64xx-spi",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_spi1_resource),
+        .resource       = s5p64x0_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        unsigned int id;
+        struct s3c64xx_spi_info *pd;
+
+        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                if (id == 0x50000)
+                        pd = &s5p6450_spi0_pdata;
+                else
+                        pd = &s5p6440_spi0_pdata;
+
+                s5p64x0_device_spi0.dev.platform_data = pd;
+                break;
+        case 1:
+                if (id == 0x50000)
+                        pd = &s5p6450_spi1_pdata;
+                else
+                        pd = &s5p6440_spi1_pdata;
+
+                s5p64x0_device_spi1.dev.platform_data = pd;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 07606ad5751..29a8c241004 100644
--- a/arch/arm/mach-s5p6440/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -1,4 +1,8 @@
-/*
+/* linux/arch/arm/mach-s5p64x0/dma.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  *      Jaswinder Singh <jassi.brar@samsung.com>
  *
@@ -15,26 +19,25 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+*/
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <plat/devs.h>
-#include <plat/irqs.h>
-
 #include <mach/map.h>
 #include <mach/irqs.h>
+#include <mach/regs-clock.h>
 
+#include <plat/devs.h>
 #include <plat/s3c-pl330-pdata.h>
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-static struct resource s5p6440_pdma_resource[] = {
+static struct resource s5p64x0_pdma_resource[] = {
         [0] = {
-                .start  = S5P6440_PA_PDMA,
-                .end    = S5P6440_PA_PDMA + SZ_4K,
-                .flags = IORESOURCE_MEM,
+                .start  = S5P64X0_PA_PDMA,
+                .end    = S5P64X0_PA_PDMA + SZ_4K,
+                .flags  = IORESOURCE_MEM,
         },
         [1] = {
                 .start  = IRQ_DMA0,
@@ -80,26 +83,67 @@ static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
         },
 };
 
-static struct platform_device s5p6440_device_pdma = {
+static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_UART4_RX,
+                [9] = DMACH_UART4_TX,
+                [10] = DMACH_PCM0_TX,
+                [11] = DMACH_PCM0_RX,
+                [12] = DMACH_I2S0_TX,
+                [13] = DMACH_I2S0_RX,
+                [14] = DMACH_SPI0_TX,
+                [15] = DMACH_SPI0_RX,
+                [16] = DMACH_PCM1_TX,
+                [17] = DMACH_PCM1_RX,
+                [18] = DMACH_PCM2_TX,
+                [19] = DMACH_PCM2_RX,
+                [20] = DMACH_SPI1_TX,
+                [21] = DMACH_SPI1_RX,
+                [22] = DMACH_USI_TX,
+                [23] = DMACH_USI_RX,
+                [24] = DMACH_MAX,
+                [25] = DMACH_I2S1_TX,
+                [26] = DMACH_I2S1_RX,
+                [27] = DMACH_I2S2_TX,
+                [28] = DMACH_I2S2_RX,
+                [29] = DMACH_PWM,
+                [30] = DMACH_UART5_RX,
+                [31] = DMACH_UART5_TX,
+        },
+};
+
+static struct platform_device s5p64x0_device_pdma = {
         .name           = "s3c-pl330",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5p6440_pdma_resource),
-        .resource       = s5p6440_pdma_resource,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p64x0_pdma_resource),
+        .resource       = s5p64x0_pdma_resource,
         .dev            = {
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5p6440_pdma_pdata,
         },
 };
 
-static struct platform_device *s5p6440_dmacs[] __initdata = {
-        &s5p6440_device_pdma,
-};
-
-static int __init s5p6440_dma_init(void)
+static int __init s5p64x0_dma_init(void)
 {
-        platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
+        unsigned int id;
+
+        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
+
+        if (id == 0x50000)
+                s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
+        else
+                s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
+
+        platform_device_register(&s5p64x0_device_pdma);
 
         return 0;
 }
-arch_initcall(s5p6440_dma_init);
+arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p64x0/gpio.c
index 8bf6e0ce51c..39159dd5a29 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpio.c
@@ -1,14 +1,14 @@
-/* arch/arm/mach-s5p6440/gpio.c
+/* linux/arch/arm/mach-s5p64x0/gpio.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - GPIOlib support
+ * S5P64X0 - GPIOlib support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- */
+*/
 
 #include <linux/kernel.h>
 #include <linux/irq.h>
@@ -22,26 +22,29 @@
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
 
-/* GPIO bank summary:
-*
-* Bank  GPIOs   Style   SlpCon  ExtInt Group
-* A     6       4Bit    Yes     1
-* B     7       4Bit    Yes     1
-* C     8       4Bit    Yes     2
-* F     2       2Bit    Yes     4 [1]
-* G     7       4Bit    Yes     5
-* H     10      4Bit[2] Yes     6
-* I     16      2Bit    Yes     None
-* J     12      2Bit    Yes     None
-* N     16      2Bit    No      IRQ_EINT
-* P     8       2Bit    Yes     8
-* R     15      4Bit[2] Yes     8
-*
-* [1] BANKF pins 14,15 do not form part of the external interrupt sources
-* [2] BANK has two control registers, GPxCON0 and GPxCON1
-*/
+/* To be implemented S5P6450 GPIO */
+
+/*
+ * S5P6440 GPIO bank summary:
+ *
+ * Bank GPIOs   Style   SlpCon  ExtInt Group
+ * A    6       4Bit    Yes     1
+ * B    7       4Bit    Yes     1
+ * C    8       4Bit    Yes     2
+ * F    2       2Bit    Yes     4 [1]
+ * G    7       4Bit    Yes     5
+ * H    10      4Bit[2] Yes     6
+ * I    16      2Bit    Yes     None
+ * J    12      2Bit    Yes     None
+ * N    16      2Bit    No      IRQ_EINT
+ * P    8       2Bit    Yes     8
+ * R    15      4Bit[2] Yes     8
+ *
+ * [1] BANKF pins 14,15 do not form part of the external interrupt sources
+ * [2] BANK has two control registers, GPxCON0 and GPxCON1
+ */
 
-static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
+static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
                                              unsigned int offset)
 {
         struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -77,7 +80,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
         return 0;
 }
 
-static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
+static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
                                               unsigned int offset, int value)
 {
         struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -124,12 +127,11 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
         return 0;
 }
 
-int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
+int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
                                    unsigned int off, unsigned int cfg)
 {
         void __iomem *reg = chip->base;
         unsigned int shift;
-        unsigned long flags;
         u32 con;
 
         switch (off) {
@@ -155,26 +157,22 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
                 cfg <<= shift;
         }
 
-        s3c_gpio_lock(chip, flags);
-
         con = __raw_readl(reg);
         con &= ~(0xf << shift);
         con |= cfg;
         __raw_writel(con, reg);
 
-        s3c_gpio_unlock(chip, flags);
-
         return 0;
 }
 
-static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
+static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
         {
                 .cfg_eint       = 0,
         }, {
                 .cfg_eint       = 7,
         }, {
                 .cfg_eint       = 3,
-                .set_config     = s5p6440_gpio_setcfg_4bit_rbank,
+                .set_config     = s5p64x0_gpio_setcfg_4bit_rbank,
         }, {
                 .cfg_eint       = 0,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
@@ -193,7 +191,7 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
         {
                 .base   = S5P6440_GPA_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPA(0),
                         .ngpio  = S5P6440_GPIO_A_NR,
@@ -201,7 +199,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPB_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPB(0),
                         .ngpio  = S5P6440_GPIO_B_NR,
@@ -209,7 +207,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPC_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPC(0),
                         .ngpio  = S5P6440_GPIO_C_NR,
@@ -217,7 +215,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPG_BASE,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPG(0),
                         .ngpio  = S5P6440_GPIO_G_NR,
@@ -229,7 +227,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
         {
                 .base   = S5P6440_GPH_BASE + 0x4,
-                .config = &s5p6440_gpio_cfgs[1],
+                .config = &s5p64x0_gpio_cfgs[1],
                 .chip   = {
                         .base   = S5P6440_GPH(0),
                         .ngpio  = S5P6440_GPIO_H_NR,
@@ -238,10 +236,10 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
         },
 };
 
-static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
+static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
         {
                 .base   = S5P6440_GPR_BASE + 0x4,
-                .config = &s5p6440_gpio_cfgs[2],
+                .config = &s5p64x0_gpio_cfgs[2],
                 .chip   = {
                         .base   = S5P6440_GPR(0),
                         .ngpio  = S5P6440_GPIO_R_NR,
@@ -253,7 +251,7 @@ static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
         {
                 .base   = S5P6440_GPF_BASE,
-                .config = &s5p6440_gpio_cfgs[5],
+                .config = &s5p64x0_gpio_cfgs[5],
                 .chip   = {
                         .base   = S5P6440_GPF(0),
                         .ngpio  = S5P6440_GPIO_F_NR,
@@ -261,7 +259,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPI_BASE,
-                .config = &s5p6440_gpio_cfgs[3],
+                .config = &s5p64x0_gpio_cfgs[3],
                 .chip   = {
                         .base   = S5P6440_GPI(0),
                         .ngpio  = S5P6440_GPIO_I_NR,
@@ -269,7 +267,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPJ_BASE,
-                .config = &s5p6440_gpio_cfgs[3],
+                .config = &s5p64x0_gpio_cfgs[3],
                 .chip   = {
                         .base   = S5P6440_GPJ(0),
                         .ngpio  = S5P6440_GPIO_J_NR,
@@ -277,7 +275,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPN_BASE,
-                .config = &s5p6440_gpio_cfgs[4],
+                .config = &s5p64x0_gpio_cfgs[4],
                 .chip   = {
                         .base   = S5P6440_GPN(0),
                         .ngpio  = S5P6440_GPIO_N_NR,
@@ -285,7 +283,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
                 },
         }, {
                 .base   = S5P6440_GPP_BASE,
-                .config = &s5p6440_gpio_cfgs[5],
+                .config = &s5p64x0_gpio_cfgs[5],
                 .chip   = {
                         .base   = S5P6440_GPP(0),
                         .ngpio  = S5P6440_GPIO_P_NR,
@@ -294,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
         },
 };
 
-void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
+void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
 {
         for (; nr_chips > 0; nr_chips--, chipcfg++) {
                 if (!chipcfg->set_config)
@@ -308,13 +306,13 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
         }
 }
 
-static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
+static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
                                                 int nr_chips)
 {
         for (; nr_chips > 0; nr_chips--, chip++) {
-                chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
+                chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
                 chip->chip.direction_output =
-                                        s5p6440_gpiolib_rbank_4bit2_output;
+                                        s5p64x0_gpiolib_rbank_4bit2_output;
                 s3c_gpiolib_add(chip);
         }
 }
@@ -324,8 +322,8 @@ static int __init s5p6440_gpiolib_init(void)
         struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
         int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
 
-        s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
-                                ARRAY_SIZE(s5p6440_gpio_cfgs));
+        s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
+                                ARRAY_SIZE(s5p64x0_gpio_cfgs));
 
         for (; nr_chips > 0; nr_chips--, chips++)
                 s3c_gpiolib_add(chips);
@@ -336,8 +334,8 @@ static int __init s5p6440_gpiolib_init(void)
         samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
                                 ARRAY_SIZE(s5p6440_gpio_4bit2));
 
-        s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
-                                ARRAY_SIZE(gpio_rbank_4bit2));
+        s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
+                                ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
 
         return 0;
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
new file mode 100644
index 00000000000..79b04e6a6f8
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -0,0 +1,33 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+#include <plat/regs-serial.h>
+
+        .macro addruart, rp, rv
+                mov     \rp, #0xE0000000
+                orr     \rp, \rp, #0x00100000
+                ldr     \rp, [\rp, #0x118 ]
+                and     \rp, \rp, #0xff000
+                teq     \rp, #0x50000           @@ S5P6450
+                ldreq   \rp, =0xEC800000
+                movne   \rp, #0xEC000000        @@ S5P6440
+                ldrne   \rv, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
+#endif
+        .endm
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
index 81209eb1409..81209eb1409 100644
--- a/arch/arm/mach-s5p6440/include/mach/dma.h
+++ b/arch/arm/mach-s5p64x0/include/mach/dma.h
diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
index e65f1b96726..10b62b4f821 100644
--- a/arch/arm/mach-s5p6440/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S
+/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * Low-level IRQ helper macros for the Samsung S5P6440
+ * Low-level IRQ helper macros for the Samsung S5P64X0
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
new file mode 100644
index 00000000000..5486c8f01f1
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -0,0 +1,139 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+/* GPIO bank sizes */
+
+#define S5P6440_GPIO_A_NR       (6)
+#define S5P6440_GPIO_B_NR       (7)
+#define S5P6440_GPIO_C_NR       (8)
+#define S5P6440_GPIO_F_NR       (2)
+#define S5P6440_GPIO_G_NR       (7)
+#define S5P6440_GPIO_H_NR       (10)
+#define S5P6440_GPIO_I_NR       (16)
+#define S5P6440_GPIO_J_NR       (12)
+#define S5P6440_GPIO_N_NR       (16)
+#define S5P6440_GPIO_P_NR       (8)
+#define S5P6440_GPIO_R_NR       (15)
+
+#define S5P6450_GPIO_A_NR       (6)
+#define S5P6450_GPIO_B_NR       (7)
+#define S5P6450_GPIO_C_NR       (8)
+#define S5P6450_GPIO_D_NR       (8)
+#define S5P6450_GPIO_F_NR       (2)
+#define S5P6450_GPIO_G_NR       (14)
+#define S5P6450_GPIO_H_NR       (10)
+#define S5P6450_GPIO_I_NR       (16)
+#define S5P6450_GPIO_J_NR       (12)
+#define S5P6450_GPIO_K_NR       (5)
+#define S5P6450_GPIO_N_NR       (16)
+#define S5P6450_GPIO_P_NR       (11)
+#define S5P6450_GPIO_Q_NR       (14)
+#define S5P6450_GPIO_R_NR       (15)
+#define S5P6450_GPIO_S_NR       (8)
+
+/* GPIO bank numbers */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S5P64X0_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5p6440_gpio_number {
+        S5P6440_GPIO_A_START    = 0,
+        S5P6440_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
+        S5P6440_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
+        S5P6440_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
+        S5P6440_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
+        S5P6440_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
+        S5P6440_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
+        S5P6440_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
+        S5P6440_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
+        S5P6440_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
+        S5P6440_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
+};
+
+enum s5p6450_gpio_number {
+        S5P6450_GPIO_A_START    = 0,
+        S5P6450_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
+        S5P6450_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
+        S5P6450_GPIO_D_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
+        S5P6450_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
+        S5P6450_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
+        S5P6450_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
+        S5P6450_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
+        S5P6450_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
+        S5P6450_GPIO_K_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
+        S5P6450_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
+        S5P6450_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
+        S5P6450_GPIO_Q_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
+        S5P6450_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
+        S5P6450_GPIO_S_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
+};
+
+/* GPIO number definitions */
+
+#define S5P6440_GPA(_nr)        (S5P6440_GPIO_A_START + (_nr))
+#define S5P6440_GPB(_nr)        (S5P6440_GPIO_B_START + (_nr))
+#define S5P6440_GPC(_nr)        (S5P6440_GPIO_C_START + (_nr))
+#define S5P6440_GPF(_nr)        (S5P6440_GPIO_F_START + (_nr))
+#define S5P6440_GPG(_nr)        (S5P6440_GPIO_G_START + (_nr))
+#define S5P6440_GPH(_nr)        (S5P6440_GPIO_H_START + (_nr))
+#define S5P6440_GPI(_nr)        (S5P6440_GPIO_I_START + (_nr))
+#define S5P6440_GPJ(_nr)        (S5P6440_GPIO_J_START + (_nr))
+#define S5P6440_GPN(_nr)        (S5P6440_GPIO_N_START + (_nr))
+#define S5P6440_GPP(_nr)        (S5P6440_GPIO_P_START + (_nr))
+#define S5P6440_GPR(_nr)        (S5P6440_GPIO_R_START + (_nr))
+
+#define S5P6450_GPA(_nr)        (S5P6450_GPIO_A_START + (_nr))
+#define S5P6450_GPB(_nr)        (S5P6450_GPIO_B_START + (_nr))
+#define S5P6450_GPC(_nr)        (S5P6450_GPIO_C_START + (_nr))
+#define S5P6450_GPD(_nr)        (S5P6450_GPIO_D_START + (_nr))
+#define S5P6450_GPF(_nr)        (S5P6450_GPIO_F_START + (_nr))
+#define S5P6450_GPG(_nr)        (S5P6450_GPIO_G_START + (_nr))
+#define S5P6450_GPH(_nr)        (S5P6450_GPIO_H_START + (_nr))
+#define S5P6450_GPI(_nr)        (S5P6450_GPIO_I_START + (_nr))
+#define S5P6450_GPJ(_nr)        (S5P6450_GPIO_J_START + (_nr))
+#define S5P6450_GPK(_nr)        (S5P6450_GPIO_K_START + (_nr))
+#define S5P6450_GPN(_nr)        (S5P6450_GPIO_N_START + (_nr))
+#define S5P6450_GPP(_nr)        (S5P6450_GPIO_P_START + (_nr))
+#define S5P6450_GPQ(_nr)        (S5P6450_GPIO_Q_START + (_nr))
+#define S5P6450_GPR(_nr)        (S5P6450_GPIO_R_START + (_nr))
+#define S5P6450_GPS(_nr)        (S5P6450_GPIO_S_START + (_nr))
+
+/* the end of the S5P64X0 specific gpios */
+
+#define S5P6440_GPIO_END        (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
+#define S5P6450_GPIO_END        (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
+
+#define S5P64X0_GPIO_END        (S5P6440_GPIO_END > S5P6450_GPIO_END ?  \
+                                 S5P6440_GPIO_END : S5P6450_GPIO_END)
+
+#define S3C_GPIO_END            S5P64X0_GPIO_END
+
+/* define the number of gpios we need to the one after the last GPIO range */
+
+#define ARCH_NR_GPIOS           (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
index be8b26e875d..d3e87996dd9 100644
--- a/arch/arm/mach-s5p6440/include/mach/hardware.h
+++ b/arch/arm/mach-s5p64x0/include/mach/hardware.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - Hardware support
+ * S5P64X0 - Hardware support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/include/mach/i2c.h
new file mode 100644
index 00000000000..887d25209e8
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/i2c.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 I2C configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
+
+extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/io.h b/arch/arm/mach-s5p64x0/include/mach/io.h
new file mode 100644
index 00000000000..a3e095c02fb
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/io.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben-linux@fluff.org>
+ *
+ * Default IO routines for S5P64X0 based
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No current ISA/PCI bus support. */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 16a761270de..513abffc760 100644
--- a/arch/arm/mach-s5p6440/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -1,17 +1,17 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
  *
- * Copyright 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - IRQ definitions
+ * S5P64X0 - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM_ARCH_S5P_IRQS_H
-#define __ASM_ARCH_S5P_IRQS_H __FILE__
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
 
 #include <plat/irqs.h>
 
@@ -20,10 +20,12 @@
 #define IRQ_EINT0_3             S5P_IRQ_VIC0(0)
 #define IRQ_EINT4_11            S5P_IRQ_VIC0(1)
 #define IRQ_RTC_TIC             S5P_IRQ_VIC0(2)
+#define IRQ_IIS1                S5P_IRQ_VIC0(3) /* for only S5P6450 */
+#define IRQ_IIS2                S5P_IRQ_VIC0(4) /* for only S5P6450 */
 #define IRQ_IIC1                S5P_IRQ_VIC0(5)
 #define IRQ_I2SV40              S5P_IRQ_VIC0(6)
-#define IRQ_GPS                 S5P_IRQ_VIC0(7)
-#define IRQ_POST0               S5P_IRQ_VIC0(9)
+#define IRQ_GPS                 S5P_IRQ_VIC0(7) /* for only S5P6450 */
+
 #define IRQ_2D                  S5P_IRQ_VIC0(11)
 #define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(23)
 #define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(24)
@@ -39,22 +41,26 @@
 
 #define IRQ_EINT12_15           S5P_IRQ_VIC1(0)
 #define IRQ_PCM0                S5P_IRQ_VIC1(2)
+#define IRQ_PCM1                S5P_IRQ_VIC1(3) /* for only S5P6450 */
+#define IRQ_PCM2                S5P_IRQ_VIC1(4) /* for only S5P6450 */
 #define IRQ_UART0               S5P_IRQ_VIC1(5)
 #define IRQ_UART1               S5P_IRQ_VIC1(6)
 #define IRQ_UART2               S5P_IRQ_VIC1(7)
 #define IRQ_UART3               S5P_IRQ_VIC1(8)
 #define IRQ_DMA0                S5P_IRQ_VIC1(9)
+#define IRQ_UART4               S5P_IRQ_VIC1(10)        /* S5P6450 */
+#define IRQ_UART5               S5P_IRQ_VIC1(11)        /* S5P6450 */
 #define IRQ_NFC                 S5P_IRQ_VIC1(13)
+#define IRQ_USI                 S5P_IRQ_VIC1(15)        /* S5P6450 */
 #define IRQ_SPI0                S5P_IRQ_VIC1(16)
 #define IRQ_SPI1                S5P_IRQ_VIC1(17)
+#define IRQ_HSMMC2              S5P_IRQ_VIC1(17)        /* Shared */
 #define IRQ_IIC                 S5P_IRQ_VIC1(18)
 #define IRQ_DISPCON3            S5P_IRQ_VIC1(19)
-#define IRQ_FIMGVG              S5P_IRQ_VIC1(20)
 #define IRQ_EINT_GROUPS         S5P_IRQ_VIC1(21)
-#define IRQ_PMU                 S5P_IRQ_VIC1(23)
+#define IRQ_PMU                 S5P_IRQ_VIC1(23)        /* S5P6440 */
 #define IRQ_HSMMC0              S5P_IRQ_VIC1(24)
 #define IRQ_HSMMC1              S5P_IRQ_VIC1(25)
-#define IRQ_HSMMC2              IRQ_SPI1        /* shared with SPI1 */
 #define IRQ_OTG                 S5P_IRQ_VIC1(26)
 #define IRQ_DSI                 S5P_IRQ_VIC1(27)
 #define IRQ_RTC_ALARM           S5P_IRQ_VIC1(28)
@@ -63,6 +69,24 @@
 #define IRQ_TC                  IRQ_PENDN
 #define IRQ_ADC                 S5P_IRQ_VIC1(31)
 
+/* UART interrupts, S5P6450 has 5 UARTs */
+#define IRQ_S5P_UART_BASE4      (96)
+#define IRQ_S5P_UART_BASE5      (100)
+
+#define IRQ_S5P_UART_RX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR4       (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
+
+#define IRQ_S5P_UART_RX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR5       (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
+
+/* S3C compatibilty defines */
+#define IRQ_S3CUART_RX4         IRQ_S5P_UART_RX4
+#define IRQ_S3CUART_RX5         IRQ_S5P_UART_RX5
+
+/* S5P6450 EINT feature will be added */
+
 /*
  * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
  * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
@@ -115,4 +139,4 @@
 
 #define NR_IRQS                 (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
-#endif /* __ASM_ARCH_S5P_IRQS_H */
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
new file mode 100644
index 00000000000..31e534156e0
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -0,0 +1,83 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+#define S5P64X0_PA_SDRAM        (0x20000000)
+
+#define S5P64X0_PA_CHIPID       (0xE0000000)
+#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
+
+#define S5P64X0_PA_SYSCON       (0xE0100000)
+#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
+
+#define S5P64X0_PA_GPIO         (0xE0308000)
+
+#define S5P64X0_PA_VIC0         (0xE4000000)
+#define S5P64X0_PA_VIC1         (0xE4100000)
+
+#define S5P64X0_PA_PDMA         (0xE9000000)
+
+#define S5P64X0_PA_TIMER        (0xEA000000)
+#define S5P_PA_TIMER            S5P64X0_PA_TIMER
+
+#define S5P64X0_PA_RTC          (0xEA100000)
+
+#define S5P64X0_PA_WDT          (0xEA200000)
+
+#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
+#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+
+#define S5P_PA_UART0            S5P6450_PA_UART(0)
+#define S5P_PA_UART1            S5P6450_PA_UART(1)
+#define S5P_PA_UART2            S5P6450_PA_UART(2)
+#define S5P_PA_UART3            S5P6450_PA_UART(3)
+#define S5P_PA_UART4            S5P6450_PA_UART(4)
+#define S5P_PA_UART5            S5P6450_PA_UART(5)
+
+#define S5P_SZ_UART             SZ_256
+
+#define S5P6440_PA_IIC0         (0xEC104000)
+#define S5P6440_PA_IIC1         (0xEC20F000)
+#define S5P6450_PA_IIC0         (0xEC100000)
+#define S5P6450_PA_IIC1         (0xEC200000)
+
+#define S5P64X0_PA_SPI0         (0xEC400000)
+#define S5P64X0_PA_SPI1         (0xEC500000)
+
+#define S5P64X0_PA_HSOTG        (0xED100000)
+
+#define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+
+#define S5P64X0_PA_I2S          (0xF2000000)
+
+#define S5P64X0_PA_PCM          (0xF2100000)
+
+#define S5P64X0_PA_ADC          (0xF3000000)
+
+/* compatibiltiy defines. */
+
+#define S3C_PA_HSMMC0           S5P64X0_PA_HSMMC(0)
+#define S3C_PA_HSMMC1           S5P64X0_PA_HSMMC(1)
+#define S3C_PA_HSMMC2           S5P64X0_PA_HSMMC(2)
+#define S3C_PA_IIC              S5P6440_PA_IIC0
+#define S3C_PA_IIC1             S5P6440_PA_IIC1
+#define S3C_PA_RTC              S5P64X0_PA_RTC
+#define S3C_PA_WDT              S5P64X0_PA_WDT
+
+#define SAMSUNG_PA_ADC          S5P64X0_PA_ADC
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
index d62910c71b5..1b036b0a24c 100644
--- a/arch/arm/mach-s5p6440/include/mach/memory.h
+++ b/arch/arm/mach-s5p64x0/include/mach/memory.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/memory.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/memory.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - Memory definitions
+ * S5P64X0 - Memory definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,9 +11,9 @@
 */
 
 #ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H __FILE__
 
-#define PHYS_OFFSET             UL(0x20000000)
+#define PHYS_OFFSET             UL(0x20000000)
 #define CONSISTENT_DMA_SIZE     SZ_8M
 
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
index 6a2a02fdf12..19fff8b701c 100644
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
@@ -1,16 +1,14 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * S5P6440 - pwm clock and timer support
+ * S5P64X0 - pwm clock and timer support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
new file mode 100644
index 00000000000..58e1bc81380
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -0,0 +1,63 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)                   (S3C_VA_SYS + (x))
+
+#define S5P64X0_APLL_CON                S5P_CLKREG(0x0C)
+#define S5P64X0_MPLL_CON                S5P_CLKREG(0x10)
+#define S5P64X0_EPLL_CON                S5P_CLKREG(0x14)
+#define S5P64X0_EPLL_CON_K              S5P_CLKREG(0x18)
+
+#define S5P64X0_CLK_SRC0                S5P_CLKREG(0x1C)
+
+#define S5P64X0_CLK_DIV0                S5P_CLKREG(0x20)
+#define S5P64X0_CLK_DIV1                S5P_CLKREG(0x24)
+#define S5P64X0_CLK_DIV2                S5P_CLKREG(0x28)
+
+#define S5P64X0_CLK_GATE_HCLK0          S5P_CLKREG(0x30)
+#define S5P64X0_CLK_GATE_PCLK           S5P_CLKREG(0x34)
+#define S5P64X0_CLK_GATE_SCLK0          S5P_CLKREG(0x38)
+#define S5P64X0_CLK_GATE_MEM0           S5P_CLKREG(0x3C)
+
+#define S5P64X0_CLK_DIV3                S5P_CLKREG(0x40)
+
+#define S5P64X0_CLK_GATE_HCLK1          S5P_CLKREG(0x44)
+#define S5P64X0_CLK_GATE_SCLK1          S5P_CLKREG(0x48)
+
+#define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
+#define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
+
+#define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
+
+#define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
+#define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
+
+#define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
+#define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
+
+#define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
+#define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
+
+#define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
+
+/* Compatibility defines */
+
+#define ARM_CLK_DIV                     S5P64X0_CLK_DIV0
+#define ARM_DIV_RATIO_SHIFT             0
+#define ARM_DIV_MASK                    (0xF << ARM_DIV_RATIO_SHIFT)
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 82ff753913d..85f448e20a8 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -1,21 +1,24 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - GPIO register definitions
+ * S5P64X0 - GPIO register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- */
+*/
 
 #ifndef __ASM_ARCH_REGS_GPIO_H
 #define __ASM_ARCH_REGS_GPIO_H __FILE__
 
 #include <mach/map.h>
 
+/* Will be implemented S5P6442 GPIOlib */
+
 /* Base addresses for each of the banks */
+
 #define S5P6440_GPA_BASE                (S5P_VA_GPIO + 0x0000)
 #define S5P6440_GPB_BASE                (S5P_VA_GPIO + 0x0020)
 #define S5P6440_GPC_BASE                (S5P_VA_GPIO + 0x0040)
@@ -27,6 +30,7 @@
 #define S5P6440_GPN_BASE                (S5P_VA_GPIO + 0x0830)
 #define S5P6440_GPP_BASE                (S5P_VA_GPIO + 0x0160)
 #define S5P6440_GPR_BASE                (S5P_VA_GPIO + 0x0290)
+
 #define S5P6440_EINT0CON0               (S5P_VA_GPIO + 0x900)
 #define S5P6440_EINT0FLTCON0            (S5P_VA_GPIO + 0x910)
 #define S5P6440_EINT0FLTCON1            (S5P_VA_GPIO + 0x914)
@@ -34,19 +38,23 @@
 #define S5P6440_EINT0PEND               (S5P_VA_GPIO + 0x924)
 
 /* for LCD */
+
 #define S5P6440_SPCON_LCD_SEL_RGB       (1 << 0)
 #define S5P6440_SPCON_LCD_SEL_MASK      (3 << 0)
 
-/* These set of macros are not really useful for the
- * GPF/GPI/GPJ/GPN/GPP,
- * useful for others set of GPIO's (4 bit)
+/*
+ * These set of macros are not really useful for the
+ * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
  */
+
 #define S5P6440_GPIO_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
 #define S5P6440_GPIO_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
 #define S5P6440_GPIO_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
 
-/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
- * */
+/*
+ * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
+ */
+
 #define S5P6440_GPIO2_CONMASK(__gpio)   (0x3 << ((__gpio) * 2))
 #define S5P6440_GPIO2_INPUT(__gpio)     (0x0 << ((__gpio) * 2))
 #define S5P6440_GPIO2_OUTPUT(__gpio)    (0x1 << ((__gpio) * 2))
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
index a961f4beeb0..4aaebdace55 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - IRQ register definitions
+ * S5P64X0 - IRQ register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
new file mode 100644
index 00000000000..ff85b4b6e8d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p64x0 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk clk_mout_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_mout_epll;
+
+extern int s5p64x0_epll_enable(struct clk *clk, int enable);
+extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
+
+extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
+extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
+extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
+
+extern struct clk_ops s5p64x0_clkarm_ops;
+
+extern struct clksrc_clk clk_armclk;
+extern struct clksrc_clk clk_dout_mpll;
+
+extern struct clk *clkset_hclk_low_list[];
+extern struct clksrc_sources clkset_hclk_low;
+
+extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
+
+extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
new file mode 100644
index 00000000000..170a20a9643
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SPI_CLKS_H
+#define __ASM_ARCH_SPI_CLKS_H __FILE__
+
+#define S5P64X0_SPI_SRCCLK_PCLK         0
+#define S5P64X0_SPI_SRCCLK_SCLK         1
+
+#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
index a359ee3fa51..60f57532c97 100644
--- a/arch/arm/mach-s5p6440/include/mach/system.h
+++ b/arch/arm/mach-s5p64x0/include/mach/system.h
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/system.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - system support header
+ * S5P64X0 - system support header
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h
index 2f25c7f0797..00aa7f1d8e5 100644
--- a/arch/arm/mach-s5p6440/include/mach/tick.h
+++ b/arch/arm/mach-s5p64x0/include/mach/tick.h
@@ -1,9 +1,14 @@
-/* linux/arch/arm/mach-s5p6440/include/mach/tick.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
- * S5P6440 - Timer tick support definitions
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S5P64X0 - Timer tick support definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/timex.h b/arch/arm/mach-s5p64x0/include/mach/timex.h
index fb2e8cd4082..4b91faa195a 100644
--- a/arch/arm/mach-s5p6440/include/mach/timex.h
+++ b/arch/arm/mach-s5p64x0/include/mach/timex.h
@@ -1,9 +1,12 @@
-/* arch/arm/mach-s3c64xx/include/mach/timex.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright (c) 2003-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * S3C6400 - time parameters
+ * S5P64X0 - time parameters
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
new file mode 100644
index 00000000000..c65b229aab2
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -0,0 +1,212 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/map.h>
+
+/*
+ * cannot use commonly <plat/uncompress.h>
+ * because uart base of S5P6440 and S5P6450 is different
+ */
+
+typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
+
+/* uart setup */
+
+static unsigned int fifo_mask;
+static unsigned int fifo_max;
+
+/* forward declerations */
+
+static void arch_detect_cpu(void);
+
+/* defines for UART registers */
+
+#include <plat/regs-serial.h>
+#include <plat/regs-watchdog.h>
+
+/* working in physical space... */
+#undef S3C2410_WDOGREG
+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX         (14)
+
+static unsigned long uart_base;
+
+static __inline__ void get_uart_base(void)
+{
+        unsigned int chipid;
+
+        chipid = *(const volatile unsigned int __force *) 0xE0100118;
+
+        uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
+
+        if ((chipid & 0xff000) == 0x50000)
+                uart_base += 0xEC800000;
+        else
+                uart_base += 0xEC000000;
+}
+
+static __inline__ void uart_wr(unsigned int reg, unsigned int val)
+{
+        volatile unsigned int *ptr;
+
+        get_uart_base();
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        *ptr = val;
+}
+
+static __inline__ unsigned int uart_rd(unsigned int reg)
+{
+        volatile unsigned int *ptr;
+
+        get_uart_base();
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        return *ptr;
+}
+
+/*
+ * we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+ */
+
+static void putc(int ch)
+{
+        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+                int level;
+
+                while (1) {
+                        level = uart_rd(S3C2410_UFSTAT);
+                        level &= fifo_mask;
+
+                        if (level < fifo_max)
+                                break;
+                }
+
+        } else {
+                /* not using fifos */
+
+                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
+                        barrier();
+        }
+
+        /* write byte to transmission register */
+        uart_wr(S3C2410_UTXH, ch);
+}
+
+static inline void flush(void)
+{
+}
+
+#define __raw_writel(d, ad)                     \
+        do {                                                    \
+                *((volatile unsigned int __force *)(ad)) = (d); \
+        } while (0)
+
+/*
+ * CONFIG_S3C_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+ */
+
+#ifdef CONFIG_S3C_BOOT_WATCHDOG
+
+#define WDOG_COUNT (0xff00)
+
+static inline void arch_decomp_wdog(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+
+static void arch_decomp_wdog_start(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+}
+
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+
+#ifdef CONFIG_S3C_BOOT_ERROR_RESET
+
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+
+        while(1);
+}
+
+#define arch_error arch_decomp_error
+#endif
+
+#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
+static inline void arch_enable_uart_fifo(void)
+{
+        u32 fifocon = uart_rd(S3C2410_UFCON);
+
+        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
+                fifocon |= S3C2410_UFCON_RESETBOTH;
+                uart_wr(S3C2410_UFCON, fifocon);
+
+                /* wait for fifo reset to complete */
+                while (1) {
+                        fifocon = uart_rd(S3C2410_UFCON);
+                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
+                                break;
+                }
+        }
+}
+#else
+#define arch_enable_uart_fifo() do { } while(0)
+#endif
+
+static void arch_decomp_setup(void)
+{
+        /*
+         * we may need to setup the uart(s) here if we are not running
+         * on an BAST... the BAST will have left the uarts configured
+         * after calling linux.
+         */
+
+        arch_detect_cpu();
+        arch_decomp_wdog_start();
+
+        /*
+         * Enable the UART FIFOs if they where not enabled and our
+         * configuration says we should turn them on.
+         */
+
+        arch_enable_uart_fifo();
+}
+
+
+
+static void arch_detect_cpu(void)
+{
+        /* we do not need to do any cpu detection here at the moment. */
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
index e3f0eebf520..97a9df38f1c 100644
--- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
@@ -1,4 +1,7 @@
-/* arch/arm/mach-s5p6440/include/mach/vmalloc.h
+/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
  *
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
new file mode 100644
index 00000000000..79833caf816
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -0,0 +1,73 @@
+/* linux/arch/arm/mach-s5p64x0/init.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Init support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+#include <plat/regs-serial.h>
+
+static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
+        [0] = {
+                .name           = "pclk_low",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+        [1] = {
+                .name           = "uclk1",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+};
+
+/* uart registration process */
+
+void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        struct s3c2410_uartcfg *tcfg = cfg;
+        u32 ucnt;
+
+        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
+                if (!tcfg->clocks) {
+                        tcfg->clocks = s5p64x0_serial_clocks;
+                        tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
+                }
+        }
+}
+
+void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        int uart;
+
+        for (uart = 0; uart < no; uart++) {
+                s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
+                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
+        }
+
+        s5p64x0_common_init_uarts(cfg, no);
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
+
+void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s5p64x0_common_init_uarts(cfg, no);
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 9202aaac3b5..87c3f03c618 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c
+/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -21,21 +21,22 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/clk.h>
+#include <linux/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
 
 #include <mach/hardware.h>
 #include <mach/map.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
+#include <mach/regs-clock.h>
+#include <mach/i2c.h>
 
 #include <plat/regs-serial.h>
-
+#include <plat/gpio-cfg.h>
 #include <plat/s5p6440.h>
 #include <plat/clock.h>
-#include <mach/regs-clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/iic.h>
@@ -58,43 +59,60 @@
 
 static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
         [0] = {
-                .hwport      = 0,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
         [1] = {
-                .hwport      = 1,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
         [2] = {
-                .hwport      = 2,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
         [3] = {
-                .hwport      = 3,
-                .flags       = 0,
-                .ucon        = SMDK6440_UCON_DEFAULT,
-                .ulcon       = SMDK6440_ULCON_DEFAULT,
-                .ufcon       = SMDK6440_UFCON_DEFAULT,
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
         },
 };
 
 static struct platform_device *smdk6440_devices[] __initdata = {
-        &s5p6440_device_iis,
         &s3c_device_adc,
         &s3c_device_rtc,
         &s3c_device_i2c0,
         &s3c_device_i2c1,
         &s3c_device_ts,
         &s3c_device_wdt,
+        &s5p6440_device_iis,
+};
+
+static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6440_i2c0_cfg_gpio,
+};
+
+static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 1,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6440_i2c1_cfg_gpio,
 };
 
 static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
@@ -113,7 +131,7 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
 
 static void __init smdk6440_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_SYS_ID);
+        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
 }
@@ -122,9 +140,8 @@ static void __init smdk6440_machine_init(void)
 {
         s3c24xx_ts_set_platdata(&s3c_ts_platform);
 
-        /* I2C */
-        s3c_i2c0_set_platdata(NULL);
-        s3c_i2c1_set_platdata(NULL);
+        s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
+        s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
         i2c_register_board_info(0, smdk6440_i2c_devs0,
                         ARRAY_SIZE(smdk6440_i2c_devs0));
         i2c_register_board_info(1, smdk6440_i2c_devs1,
@@ -135,9 +152,7 @@ static void __init smdk6440_machine_init(void)
 
 MACHINE_START(SMDK6440, "SMDK6440")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
 
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
new file mode 100644
index 00000000000..d609f5af2b9
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -0,0 +1,180 @@
+/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/i2c.h>
+
+#include <plat/regs-serial.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s5p6450.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+#include <plat/pll.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+
+#define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |         \
+                                S3C2410_UCON_TXIRQMODE |        \
+                                S3C2410_UCON_RXIRQMODE |        \
+                                S3C2410_UCON_RXFIFO_TOI |       \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK6450_ULCON_DEFAULT  S3C2410_LCON_CS8
+
+#define SMDK6450_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                S3C2440_UFCON_TXTRIG16 |        \
+                                S3C2410_UFCON_RXTRIG8)
+
+static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
+        [4] = {
+                .hwport         = 4,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#endif
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
+        [5] = {
+                .hwport         = 5,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#endif
+};
+
+static struct platform_device *smdk6450_devices[] __initdata = {
+        &s3c_device_adc,
+        &s3c_device_rtc,
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_ts,
+        &s3c_device_wdt,
+        &s5p6450_device_iis0,
+        /* s5p6450_device_spi0 will be added */
+};
+
+static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6450_i2c0_cfg_gpio,
+};
+
+static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 1,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6450_i2c1_cfg_gpio,
+};
+
+static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
+        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung KS24C080C EEPROM */
+};
+
+static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
+        { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
+static void __init smdk6450_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
+        s3c24xx_init_clocks(19200000);
+        s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
+}
+
+static void __init smdk6450_machine_init(void)
+{
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
+        s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
+        s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
+        i2c_register_board_info(0, smdk6450_i2c_devs0,
+                        ARRAY_SIZE(smdk6450_i2c_devs0));
+        i2c_register_board_info(1, smdk6450_i2c_devs1,
+                        ARRAY_SIZE(smdk6450_i2c_devs1));
+
+        platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
+}
+
+MACHINE_START(SMDK6450, "SMDK6450")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
+
+        .init_irq       = s5p6450_init_irq,
+        .map_io         = smdk6450_map_io,
+        .init_machine   = smdk6450_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5p6440/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index 2c99d14f7ac..dc4cc65a501 100644
--- a/arch/arm/mach-s5p6440/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -1,11 +1,11 @@
-/* linux/arch/arm/mach-s5p6440/setup-i2c0.c
+/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * I2C0 GPIO configuration.
  *
- * Based on plat-s3c64xx/setup-i2c0.c
+ * Based on plat-s3c64x0/setup-i2c0.c
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,17 +14,29 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/gpio.h>
 
 struct platform_device; /* don't need the contents */
 
-#include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+#include <mach/i2c.h>
+
+void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
 {
         s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
         s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
 }
+
+void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
+}
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p6440/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index 9a1537f786e..2edd7912f8e 100644
--- a/arch/arm/mach-s5p6440/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -1,7 +1,7 @@
-/* linux/arch/arm/mach-s5p6440/setup-i2c1.c
+/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
  *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * I2C1 GPIO configuration.
  *
@@ -21,10 +21,22 @@ struct platform_device; /* don't need the contents */
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+#include <mach/i2c.h>
+
+void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
 {
         s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
         s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
         s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
         s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
 }
+
+void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
+}
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 251c92ac5b2..fd2708e7d8a 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -1,5 +1,8 @@
 /* linux/arch/arm/mach-s5pc100/cpu.c
  *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
@@ -21,6 +24,7 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/sched.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -56,11 +60,31 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)VA_VIC2,
-                .pfn            = __phys_to_pfn(S5P_PA_VIC2),
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5PC100_VA_OTHERS,
                 .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index 70e02e91ee3..b2ba95ddf8e 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,13 +22,12 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx, rtmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = S3C_VA_UART
+        .macro addruart, rp, rv
+                ldr     \rp, = S3C_PA_UART
+                ldr     \rv, = S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
 #endif
         .endm
 
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 01b9134feff..8751ef4a680 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -44,19 +44,16 @@
 #define S5PC100_PA_OTHERS       (0xE0200000)
 #define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
 
-#define S5P_PA_GPIO             (0xE0300000)
+#define S5PC100_PA_GPIO         (0xE0300000)
 #define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
 
 /* Interrupt */
-#define S5PC100_PA_VIC          (0xE4000000)
+#define S5PC100_PA_VIC0         (0xE4000000)
+#define S5PC100_PA_VIC1         (0xE4100000)
+#define S5PC100_PA_VIC2         (0xE4200000)
 #define S5PC100_VA_VIC          S3C_VA_IRQ
-#define S5PC100_PA_VIC_OFFSET   0x100000
 #define S5PC100_VA_VIC_OFFSET   0x10000
-#define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
-#define S5P_PA_VIC0             S5PC1XX_PA_VIC(0)
-#define S5P_PA_VIC1             S5PC1XX_PA_VIC(1)
-#define S5P_PA_VIC2             S5PC1XX_PA_VIC(2)
 
 
 #define S5PC100_PA_ONENAND      (0xE7100000)
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 020c3f98f81..880fb075092 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -235,8 +235,6 @@ static void __init smdkc100_machine_init(void)
 
 MACHINE_START(SMDKC100, "SMDKC100")
         /* Maintainer: Byungho Min <bhmin@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index d3a38955c74..5315fec3db8 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -53,11 +53,6 @@ config S5PV210_SETUP_SDHCI_GPIO
         help
           Common setup code for SDHCI gpio.
 
-config S5PC110_DEV_ONENAND
-        bool
-        help
-          Compile in platform device definition for OneNAND1 controller
-
 menu "S5PC110 Machines"
 
 config MACH_AQUILA
@@ -71,7 +66,7 @@ config MACH_AQUILA
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
-        select S5PC110_DEV_ONENAND
+        select S5P_DEV_ONENAND
         select S5PV210_SETUP_FB_24BPP
         select S5PV210_SETUP_SDHCI
         help
@@ -88,7 +83,7 @@ config MACH_GONI
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
-        select S5PC110_DEV_ONENAND
+        select S5P_DEV_ONENAND
         select S5PV210_SETUP_FB_24BPP
         select S5PV210_SETUP_SDHCI
         help
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 05048c5aa4c..70454891240 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_GONI)		+= mach-goni.o
 
 obj-y                           += dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
-obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
 
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)    += setup-fb-24bpp.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index cfecd70657c..d562670e1b0 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -173,11 +173,6 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 }
 
-static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
-}
-
 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 77f456c91ad..2f16bfc0a11 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-s5pv210/cpu.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ *              http://www.samsung.com
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 #include <linux/platform_device.h>
+#include <linux/sched.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -50,6 +51,21 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PV210_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)VA_VIC2,
                 .pfn            = __phys_to_pfn(S5PV210_PA_VIC2),
                 .length         = SZ_16K,
@@ -60,6 +76,11 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5P_VA_SROMC,
                 .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
index 7872f5c3dfc..169fe654a59 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
@@ -21,13 +21,12 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = S3C_VA_UART
+        .macro addruart, rp, rv
+                ldr     \rp, = S3C_PA_UART
+                ldr     \rv, = S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
 #endif
         .endm
 
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index dd4fb6bf14b..bd9afd52466 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -17,7 +17,10 @@
 #include <plat/map-s5p.h>
 
 #define S5PC110_PA_ONENAND      (0xB0000000)
+#define S5P_PA_ONENAND          S5PC110_PA_ONENAND
+
 #define S5PC110_PA_ONENAND_DMA  (0xB0600000)
+#define S5P_PA_ONENAND_DMA      S5PC110_PA_ONENAND_DMA
 
 #define S5PV210_PA_CHIPID       (0xE0000000)
 #define S5P_PA_CHIPID           S5PV210_PA_CHIPID
@@ -26,7 +29,6 @@
 #define S5P_PA_SYSCON           S5PV210_PA_SYSCON
 
 #define S5PV210_PA_GPIO         (0xE0200000)
-#define S5P_PA_GPIO             S5PV210_PA_GPIO
 
 /* SPI */
 #define S5PV210_PA_SPI0         0xE1300000
@@ -72,16 +74,9 @@
 #define S5PV210_PA_HSMMC(x)     (0xEB000000 + ((x) * 0x100000))
 
 #define S5PV210_PA_VIC0         (0xF2000000)
-#define S5P_PA_VIC0             S5PV210_PA_VIC0
-
 #define S5PV210_PA_VIC1         (0xF2100000)
-#define S5P_PA_VIC1             S5PV210_PA_VIC1
-
 #define S5PV210_PA_VIC2         (0xF2200000)
-#define S5P_PA_VIC2             S5PV210_PA_VIC2
-
 #define S5PV210_PA_VIC3         (0xF2300000)
-#define S5P_PA_VIC3             S5PV210_PA_VIC3
 
 #define S5PV210_PA_SDRAM        (0x20000000)
 #define S5P_PA_SDRAM            S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 0dda8012d6b..00883087363 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -477,7 +477,7 @@ static struct platform_device *aquila_devices[] __initdata = {
         &aquila_i2c_gpio_pmic,
         &aquila_device_gpiokeys,
         &s3c_device_fb,
-        &s5pc110_device_onenand,
+        &s5p_device_onenand,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
@@ -516,8 +516,6 @@ MACHINE_START(AQUILA, "Aquila")
         /* Maintainers:
            Marek Szyprowski <m.szyprowski@samsung.com>
            Kyungmin Park <kyungmin.park@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 53754d7d364..d9ecf57fc2a 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -456,7 +456,7 @@ static void goni_setup_sdhci(void)
 
 static struct platform_device *goni_devices[] __initdata = {
         &s3c_device_fb,
-        &s5pc110_device_onenand,
+        &s5p_device_onenand,
         &goni_i2c_gpio_pmic,
         &goni_device_gpiokeys,
         &s5p_device_fimc0,
@@ -491,8 +491,6 @@ static void __init goni_machine_init(void)
 
 MACHINE_START(GONI, "GONI")
         /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 8211bb87c54..cea9bca79d8 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -127,8 +127,6 @@ static void __init smdkc110_machine_init(void)
 
 MACHINE_START(SMDKC110, "SMDKC110")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index fbbc0a3c373..83189ae9da9 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -165,8 +165,6 @@ static void __init smdkv210_machine_init(void)
 
 MACHINE_START(SMDKV210, "SMDKV210")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index e5b261a99ab..4add39853ff 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -31,9 +31,14 @@ extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
 /* Initial IO mappings */
 static struct map_desc s5pv310_iodesc[] __initdata = {
         {
-                .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
-                .pfn            = __phys_to_pfn(S5PV310_PA_COREPERI),
-                .length         = SZ_8K,
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_CMU,
+                .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
+                .length         = SZ_128K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
@@ -41,19 +46,24 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
+                .pfn            = __phys_to_pfn(S5PV310_PA_COREPERI),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S5P_VA_L2CC,
                 .pfn            = __phys_to_pfn(S5PV310_PA_L2CC),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PV310_PA_GPIO1),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_CMU,
-                .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
-                .length         = SZ_128K,
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
                 .type           = MT_DEVICE,
         },
 };
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
index 6fb3893486b..b0d920c474d 100644
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
@@ -20,13 +20,12 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1
-                ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = S3C_VA_UART
+        .macro addruart, rp, rv
+                ldreq   \rp, = S3C_PA_UART
+                ldrne   \rv, = S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+                add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
 #endif
         .endm
 
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 4cdedda6e65..471fc3bb199 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -68,6 +68,8 @@
 
 #define IRQ_IIC                 COMBINER_IRQ(27, 0)
 
+#define IRQ_ONENAND_AUDI        COMBINER_IRQ(34, 0)
+
 /* Set the default NR_IRQS */
 
 #define NR_IRQS                 COMBINER_IRQ(MAX_COMBINER_NR, 0)
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 213e1101a3b..aff6d23624b 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -25,6 +25,12 @@
 
 #define S5PV310_PA_SYSRAM               (0x02025000)
 
+#define S5PC210_PA_ONENAND              (0x0C000000)
+#define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
+
+#define S5PC210_PA_ONENAND_DMA          (0x0C600000)
+#define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
+
 #define S5PV310_PA_CHIPID               (0x10000000)
 #define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
 
@@ -46,7 +52,6 @@
 #define S5PV310_PA_GPIO1                (0x11400000)
 #define S5PV310_PA_GPIO2                (0x11000000)
 #define S5PV310_PA_GPIO3                (0x03860000)
-#define S5P_PA_GPIO                     S5PV310_PA_GPIO1
 
 #define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba88a1..b7ec252384f 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()                 \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x03;                         \
-        })
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 0d6ab77709d..46215a14b3b 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -82,8 +82,6 @@ static void __init smdkv310_machine_init(void)
 MACHINE_START(SMDKV310, "SMDKV310")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pv310_init_irq,
         .map_io         = smdkv310_map_io,
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
index 2388cb94793..d7c2ec770f8 100644
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ b/arch/arm/mach-s5pv310/mach-universal_c210.c
@@ -76,8 +76,6 @@ static void __init universal_machine_init(void)
 
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .phys_io        = S3C_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pv310_init_irq,
         .map_io         = universal_map_io,
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index fd4c52b7ccb..5da8c35aa0d 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -90,8 +90,8 @@ config SA1100_JORNADA720
         # FIXME: select CPU_FREQ_SA11x0
         help
           Say Y here if you want to build a kernel for the HP Jornada 720
-          handheld computer.  See <http://www.hp.com/jornada/products/720>
-          for details.
+          handheld computer.  See 
+          <http://h10025.www1.hp.com/ewfrf/wc/product?product=61677&cc=us&lc=en&dlc=en&product=61677#> 
 
 config SA1100_JORNADA720_SSP
         bool "HP Jornada 720 Extended SSP driver"
@@ -145,7 +145,7 @@ config SA1100_SIMPAD
           FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a
           PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same
           like CL4 in additional it has a PCMCIA-Slot. For more information
-          visit <http://www.my-siemens.com/> or <http://www.siemens.ch/>.
+          visit <http://www.usa.siemens.com/> or <http://www.siemens.ch/>.
 
 config SA1100_SSP
         tristate "Generic PIO SSP"
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 169e5b87dbf..5778274a826 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -447,8 +447,6 @@ static void __init assabet_map_io(void)
 
 
 MACHINE_START(ASSABET, "Intel-Assabet")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .fixup          = fixup_assabet,
         .map_io         = assabet_map_io,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index 259cb2c15ff..4f19ff868b0 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -302,8 +302,6 @@ static void __init badge4_map_io(void)
 }
 
 MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = badge4_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index bc950ef418a..98d780608c7 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -135,8 +135,6 @@ static void __init cerf_init(void)
 
 MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
         /* Maintainer: support@intrinsyc.com */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .map_io         = cerf_map_io,
         .init_irq       = cerf_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 16e682d5dbb..d43c5ef58eb 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -379,8 +379,6 @@ static void __init collie_map_io(void)
 }
 
 MACHINE_START(COLLIE, "Sharp-Collie")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .map_io         = collie_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index ef817876a5d..c0a13ef5436 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -13,7 +13,7 @@
  * This software has been developed while working on the LART
  * computing board (http://www.lartmaker.nl/), which is
  * sponsored by the Mobile Multi-media Communications
- * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications
+ * (http://www.mobimedia.org/) and Ubiquitous Communications
  * (http://www.ubicom.tudelft.nl/) projects.
  *
  * The authors can be reached at:
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index 0c7cea0dc01..03d7376cf8a 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -84,8 +84,6 @@ static void __init h3100_mach_init(void)
 }
 
 MACHINE_START(H3100, "Compaq iPAQ H3100")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = h3100_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index af3b71459f8..965f64a836f 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -125,8 +125,6 @@ static void __init h3600_mach_init(void)
 }
 
 MACHINE_START(H3600, "Compaq iPAQ H3600")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = h3600_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 51568dfc8e9..db5e434a17d 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -195,8 +195,6 @@ static void __init hackkit_init(void)
  */
 
 MACHINE_START(HACKKIT, "HackKit Cpu Board")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = hackkit_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 336adccea54..0cd0fc9635b 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,33 +12,37 @@
 */
 #include <mach/hardware.h>
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x80000000        @ physical base address
-                movne   \rx, #0xf8000000        @ virtual address
+                .macro  addruart, rp, rv
+                mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                moveq   \rp, #0x80000000        @ physical base address
+                movne   \rp, #0xf8000000        @ virtual address
 
                 @ We probe for the active serial port here, coherently with
                 @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
                 @ We assume r1 can be clobbered.
 
                 @ see if Ser3 is active
-                add     \rx, \rx, #0x00050000
-                ldr     r1, [\rx, #UTCR3]
-                tst     r1, #UTCR3_TXE
+                add     \rp, \rp, #0x00050000
+                ldr     \rv, [\rp, #UTCR3]
+                tst     \rv, #UTCR3_TXE
 
                 @ if Ser3 is inactive, then try Ser1
-                addeq   \rx, \rx, #(0x00010000 - 0x00050000)
-                ldreq   r1, [\rx, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
+                addeq   \rp, \rp, #(0x00010000 - 0x00050000)
+                ldreq   \rv, [\rp, #UTCR3]
+                tsteq   \rv, #UTCR3_TXE
 
                 @ if Ser1 is inactive, then try Ser2
-                addeq   \rx, \rx, #(0x00030000 - 0x00010000)
-                ldreq   r1, [\rx, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
+                addeq   \rp, \rp, #(0x00030000 - 0x00010000)
+                ldreq   \rv, [\rp, #UTCR3]
+                tsteq   \rv, #UTCR3_TXE
+
+                @ clear top bits, and generate both phys and virt addresses
+                lsl     \rp, \rp, #8
+                lsr     \rp, \rp, #8
+                orr     \rv, \rp, #0xf8000000   @ virtual
+                orr     \rp, \rp, #0x80000000   @ physical
 
-                @ if all ports are inactive, then there is nothing we can do
-                moveq   pc, lr
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index d3ec620618f..491ac9f20fb 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -364,8 +364,6 @@ static void __init jornada720_mach_init(void)
 
 MACHINE_START(JORNADA720, "HP Jornada 720")
         /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = jornada720_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 68069d6dc07..7b9556b5905 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -61,8 +61,6 @@ static void __init lart_map_io(void)
 }
 
 MACHINE_START(LART, "LART")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = lart_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 1ccd6018d3a..42b80400c10 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -146,8 +146,6 @@ static void __init pleb_map_io(void)
 }
 
 MACHINE_START(PLEB, "PLEB")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .map_io         = pleb_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 85e82bb73d7..7917b240557 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -82,8 +82,6 @@ static void __init shannon_map_io(void)
 }
 
 MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = shannon_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 49cfd64663a..27692d0ffbe 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -228,8 +228,6 @@ arch_initcall(simpad_init);
 
 MACHINE_START(SIMPAD, "Simpad")
         /* Maintainer: Holger Freyther */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = simpad_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 358d875ace1..5cf7f94c1f3 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -152,8 +152,6 @@ static struct sys_timer shark_timer = {
 
 MACHINE_START(SHARK, "Shark")
         /* Maintainer: Alexander Schulz */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = ((0xe0000000) >> 18) & 0xfffc,
         .boot_params    = 0x08003000,
         .map_io         = shark_map_io,
         .init_irq       = shark_init_irq,
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 5ea24d4d1ba..a473f55dc71 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -11,9 +11,10 @@
  *
 */
 
-                .macro  addruart, rx, tmp
-                mov     \rx, #0xe0000000
-                orr     \rx, \rx, #0x000003f8
+                .macro  addruart, rp, rv
+                mov     \rp, #0xe0000000
+                orr     \rp, \rp, #0x000003f8
+                mov     \rv, \rp
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
index f6c6837c545..8e845b6a7cb 100644
--- a/arch/arm/mach-shark/include/mach/vmalloc.h
+++ b/arch/arm/mach-shark/include/mach/vmalloc.h
@@ -1,4 +1,4 @@
 /*
  * arch/arm/mach-shark/include/mach/vmalloc.h
  */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       0xd0000000
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 95935c83c30..14923989ea0 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1105,8 +1105,6 @@ static struct sys_timer ap4evb_timer = {
 };
 
 MACHINE_START(AP4EVB, "ap4evb")
-        .phys_io        = 0xe6000000,
-        .io_pg_offst    = ((0xe6000000) >> 18) & 0xfffc,
         .map_io         = ap4evb_map_io,
         .init_irq       = sh7372_init_irq,
         .init_machine   = ap4evb_init,
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index a5525901e91..3b83d6320be 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -365,8 +365,6 @@ static struct sys_timer g3evm_timer = {
 };
 
 MACHINE_START(G3EVM, "g3evm")
-        .phys_io        = 0xe6000000,
-        .io_pg_offst    = ((0xe6000000) >> 18) & 0xfffc,
         .map_io         = g3evm_map_io,
         .init_irq       = sh7367_init_irq,
         .init_machine   = g3evm_init,
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 2c3ff6f7f34..5b3b582ef3f 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -392,8 +392,6 @@ static struct sys_timer g4evm_timer = {
 };
 
 MACHINE_START(G4EVM, "g4evm")
-        .phys_io        = 0xe6000000,
-        .io_pg_offst    = ((0xe6000000) >> 18) & 0xfffc,
         .map_io         = g4evm_map_io,
         .init_irq       = sh7377_init_irq,
         .init_machine   = g4evm_init,
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
index 90d8fe6f10f..06158848afd 100644
--- a/arch/arm/mach-stmp378x/stmp378x_devb.c
+++ b/arch/arm/mach-stmp378x/stmp378x_devb.c
@@ -324,8 +324,6 @@ static void __init stmp378x_devb_init(void)
 }
 
 MACHINE_START(STMP378X, "STMP378X")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf0000000) >> 18) & 0xfffc,
         .boot_params    = 0x40000100,
         .map_io         = stmp378x_map_io,
         .init_irq       = stmp378x_init_irq,
diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
index 394f21ab59e..311d8552d36 100644
--- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c
+++ b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
@@ -91,8 +91,6 @@ static void __init stmp37xx_devb_init(void)
 }
 
 MACHINE_START(STMP37XX, "STMP37XX")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf0000000) >> 18) & 0xfffc,
         .boot_params    = 0x40000100,
         .map_io         = stmp37xx_map_io,
         .init_irq       = stmp37xx_init_irq,
diff --git a/arch/arm/mach-tcc8k/Kconfig b/arch/arm/mach-tcc8k/Kconfig
new file mode 100644
index 00000000000..ad86415d157
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_TCC8K
+
+comment "TCC8000 systems:"
+
+config MACH_TCC8000_SDK
+        bool "Telechips TCC8000-SDK development kit"
+        default y
+        help
+          Support for the Telechips TCC8000-SDK board.
+
+endif
diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
new file mode 100644
index 00000000000..9bacf31e49b
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for TCC8K boards and common files.
+#
+
+# Common support
+obj-y += clock.o irq.o time.o io.o devices.o
+
+# Board specific support
+obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o
diff --git a/arch/arm/mach-tcc8k/Makefile.boot b/arch/arm/mach-tcc8k/Makefile.boot
new file mode 100644
index 00000000000..f135c9deae1
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y           := 0x20008000
+params_phys-y           := 0x20000100
+initrd_phys-y           := 0x20800000
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
new file mode 100644
index 00000000000..7991415e666
--- /dev/null
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include <mach/clock.h>
+
+#include "common.h"
+
+#define XI_FREQUENCY    12000000
+#define XTI_FREQUENCY   32768
+
+#ifdef CONFIG_MTD_NAND_TCC
+/* NAND */
+static struct tcc_nand_platform_data tcc8k_sdk_nand_data = {
+        .width = 1,
+        .hw_ecc = 0,
+};
+#endif
+
+static void __init tcc8k_init(void)
+{
+#ifdef CONFIG_MTD_NAND_TCC
+        tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data;
+        platform_device_register(&tcc_nand_device);
+#endif
+}
+
+static void __init tcc8k_init_timer(void)
+{
+        tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY);
+}
+
+static struct sys_timer tcc8k_timer = {
+        .init   = tcc8k_init_timer,
+};
+
+static void __init tcc8k_map_io(void)
+{
+        tcc8k_map_common_io();
+}
+
+MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
+        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .map_io         = tcc8k_map_io,
+        .init_irq       = tcc8k_init_irq,
+        .init_machine   = tcc8k_init,
+        .timer          = &tcc8k_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
new file mode 100644
index 00000000000..ba32a15127a
--- /dev/null
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -0,0 +1,567 @@
+/*
+ * Lowlevel clock handling for Telechips TCC8xxx SoCs
+ *
+ * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/irqs.h>
+#include <mach/tcc8k-regs.h>
+
+#include "common.h"
+
+#define BCLKCTR0        (CKC_BASE + BCLKCTR0_OFFS)
+#define BCLKCTR1        (CKC_BASE + BCLKCTR1_OFFS)
+
+#define ACLKREF         (CKC_BASE + ACLKREF_OFFS)
+#define ACLKUART0       (CKC_BASE + ACLKUART0_OFFS)
+#define ACLKUART1       (CKC_BASE + ACLKUART1_OFFS)
+#define ACLKUART2       (CKC_BASE + ACLKUART2_OFFS)
+#define ACLKUART3       (CKC_BASE + ACLKUART3_OFFS)
+#define ACLKUART4       (CKC_BASE + ACLKUART4_OFFS)
+#define ACLKI2C         (CKC_BASE + ACLKI2C_OFFS)
+#define ACLKADC         (CKC_BASE + ACLKADC_OFFS)
+#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKLCD         (CKC_BASE + ACLKLCD_OFFS)
+#define ACLKSDH0        (CKC_BASE + ACLKSDH0_OFFS)
+#define ACLKSDH1        (CKC_BASE + ACLKSDH1_OFFS)
+#define ACLKSPI0        (CKC_BASE + ACLKSPI0_OFFS)
+#define ACLKSPI1        (CKC_BASE + ACLKSPI1_OFFS)
+#define ACLKSPDIF       (CKC_BASE + ACLKSPDIF_OFFS)
+#define ACLKC3DEC       (CKC_BASE + ACLKC3DEC_OFFS)
+#define ACLKCAN0        (CKC_BASE + ACLKCAN0_OFFS)
+#define ACLKCAN1        (CKC_BASE + ACLKCAN1_OFFS)
+#define ACLKGSB0        (CKC_BASE + ACLKGSB0_OFFS)
+#define ACLKGSB1        (CKC_BASE + ACLKGSB1_OFFS)
+#define ACLKGSB2        (CKC_BASE + ACLKGSB2_OFFS)
+#define ACLKGSB3        (CKC_BASE + ACLKGSB3_OFFS)
+#define ACLKUSBH        (CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKTCT         (CKC_BASE + ACLKTCT_OFFS)
+#define ACLKTCX         (CKC_BASE + ACLKTCX_OFFS)
+#define ACLKTCZ         (CKC_BASE + ACLKTCZ_OFFS)
+
+/* Crystal frequencies */
+static unsigned long xi_rate, xti_rate;
+
+static void __iomem *pll_cfg_addr(int pll)
+{
+        switch (pll) {
+        case 0: return (CKC_BASE + PLL0CFG_OFFS);
+        case 1: return (CKC_BASE + PLL1CFG_OFFS);
+        case 2: return (CKC_BASE + PLL2CFG_OFFS);
+        default:
+                BUG();
+        }
+}
+
+static int pll_enable(int pll, int enable)
+{
+        u32 reg;
+        void __iomem *addr = pll_cfg_addr(pll);
+
+        reg = __raw_readl(addr);
+        if (enable)
+                reg &= ~PLLxCFG_PD;
+        else
+                reg |= PLLxCFG_PD;
+
+        __raw_writel(reg, addr);
+        return 0;
+}
+
+static int xi_enable(int enable)
+{
+        u32 reg;
+
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+        if (enable)
+                reg |= CLKCTRL_XE;
+        else
+                reg &= ~CLKCTRL_XE;
+
+        __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
+        return 0;
+}
+
+static int root_clk_enable(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return pll_enable(0, 1);
+        case CLK_SRC_PLL1: return pll_enable(1, 1);
+        case CLK_SRC_PLL2: return pll_enable(2, 1);
+        case CLK_SRC_XI: return xi_enable(1);
+        default:
+                BUG();
+        }
+        return 0;
+}
+
+static int root_clk_disable(enum root_clks root_src)
+{
+        switch (root_src) {
+        case CLK_SRC_PLL0: return pll_enable(0, 0);
+        case CLK_SRC_PLL1: return pll_enable(1, 0);
+        case CLK_SRC_PLL2: return pll_enable(2, 0);
+        case CLK_SRC_XI: return xi_enable(0);
+        default:
+                BUG();
+        }
+        return 0;
+}
+
+static int enable_clk(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->root_id != CLK_SRC_NOROOT)
+                return root_clk_enable(clk->root_id);
+
+        if (clk->aclkreg) {
+                reg = __raw_readl(clk->aclkreg);
+                reg |= ACLK_EN;
+                __raw_writel(reg, clk->aclkreg);
+        }
+        if (clk->bclkctr) {
+                reg = __raw_readl(clk->bclkctr);
+                reg |= 1 << clk->bclk_shift;
+                __raw_writel(reg, clk->bclkctr);
+        }
+        return 0;
+}
+
+static void disable_clk(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->root_id != CLK_SRC_NOROOT) {
+                root_clk_disable(clk->root_id);
+                return;
+        }
+
+        if (clk->bclkctr) {
+                reg = __raw_readl(clk->bclkctr);
+                reg &= ~(1 << clk->bclk_shift);
+                __raw_writel(reg, clk->bclkctr);
+        }
+        if (clk->aclkreg) {
+                reg = __raw_readl(clk->aclkreg);
+                reg &= ~ACLK_EN;
+                __raw_writel(reg, clk->aclkreg);
+        }
+}
+
+static unsigned long get_rate_pll(int pll)
+{
+        u32 reg;
+        unsigned long s, m, p;
+        void __iomem *addr = pll_cfg_addr(pll);
+
+        reg = __raw_readl(addr);
+        s = (reg >> 16) & 0x07;
+        m = (reg >> 8) & 0xff;
+        p = reg & 0x3f;
+
+        return (m * xi_rate) / (p * (1 << s));
+}
+
+static unsigned long get_rate_pll_div(int pll)
+{
+        u32 reg;
+        unsigned long div = 0;
+        void __iomem *addr;
+
+        switch (pll) {
+        case 0:
+                addr = CKC_BASE + CLKDIVC0_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC0_P0E)
+                        div = (reg >> 24) & 0x3f;
+                break;
+        case 1:
+                addr = CKC_BASE + CLKDIVC0_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC0_P1E)
+                        div = (reg >> 16) & 0x3f;
+                break;
+        case 2:
+                addr = CKC_BASE + CLKDIVC1_OFFS;
+                reg = __raw_readl(addr);
+                if (reg & CLKDIVC1_P2E)
+                        div = __raw_readl(addr) & 0x3f;
+                break;
+        }
+        return get_rate_pll(pll) / (div + 1);
+}
+
+static unsigned long get_rate_xi_div(void)
+{
+        unsigned long div = 0;
+        u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+        if (reg & CLKDIVC0_XE)
+                div = (reg >> 8) & 0x3f;
+
+        return xi_rate / (div + 1);
+}
+
+static unsigned long get_rate_xti_div(void)
+{
+        unsigned long div = 0;
+        u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+        if (reg & CLKDIVC0_XTE)
+                div = reg & 0x3f;
+
+        return xti_rate / (div + 1);
+}
+
+static unsigned long root_clk_get_rate(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return get_rate_pll(0);
+        case CLK_SRC_PLL1: return get_rate_pll(1);
+        case CLK_SRC_PLL2: return get_rate_pll(2);
+        case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
+        case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
+        case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
+        case CLK_SRC_XI: return xi_rate;
+        case CLK_SRC_XTI: return xti_rate;
+        case CLK_SRC_XIDIV: return get_rate_xi_div();
+        case CLK_SRC_XTIDIV: return get_rate_xti_div();
+        default: return 0;
+        }
+}
+
+static unsigned long aclk_get_rate(struct clk *clk)
+{
+        u32 reg;
+        unsigned long div;
+        unsigned int src;
+
+        reg = __raw_readl(clk->aclkreg);
+        div = reg & 0x0fff;
+        src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
+        return root_clk_get_rate(src) / (div + 1);
+}
+
+static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
+{
+        unsigned long div, src, freq, r1, r2;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+        freq = root_clk_get_rate(src);
+        div = freq / rate + 1;
+        r1 = freq / div;
+        r2 = freq / (div + 1);
+        if (r2 >= rate)
+                return div + 1;
+        if ((rate - r2) < (r1 - rate))
+                return div + 1;
+
+        return div;
+}
+
+static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int src;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+
+        return root_clk_get_rate(src) / aclk_best_div(clk, rate);
+}
+
+static int aclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
+        reg |= aclk_best_div(clk, rate);
+        return 0;
+}
+
+static unsigned long get_rate_sys(struct clk *clk)
+{
+        unsigned int src;
+
+        src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
+                return root_clk_get_rate(src);
+}
+
+static unsigned long get_rate_bus(struct clk *clk)
+{
+        unsigned int div;
+
+        div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
+        return get_rate_sys(clk) / (div + 1);
+}
+
+static unsigned long get_rate_cpu(struct clk *clk)
+{
+        unsigned int reg, div, fsys, fbus;
+
+        fbus = get_rate_bus(clk);
+        reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+        if (reg & (1 << 29))
+                return fbus;
+        fsys = get_rate_sys(clk);
+        div = (reg >> 16) & 0x0f;
+        return fbus + ((fsys - fbus) * (div + 1)) / 16;
+}
+
+static unsigned long get_rate_root(struct clk *clk)
+{
+        return root_clk_get_rate(clk->root_id);
+}
+
+static int aclk_set_parent(struct clk *clock, struct clk *parent)
+{
+        u32 reg;
+
+        if (clock->parent == parent)
+                return 0;
+
+        clock->parent = parent;
+
+        if (!parent)
+                return 0;
+
+        if (parent->root_id == CLK_SRC_NOROOT)
+                return 0;
+        reg = __raw_readl(clock->aclkreg);
+        reg &= ~ACLK_SEL_MASK;
+        reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
+        __raw_writel(reg, clock->aclkreg);
+
+        return 0;
+}
+
+#define DEFINE_ROOT_CLOCK(name, ri, p)  \
+        static struct clk name = {              \
+                .root_id = ri,                  \
+                .get_rate = get_rate_root,                      \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .parent = p,                    \
+        };
+
+#define DEFINE_SPECIAL_CLOCK(name, gr, p)       \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .get_rate = gr,                 \
+                .parent = p,                    \
+        };
+
+#define DEFINE_ACLOCK(name, bc, bs, ar)         \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .bclkctr = bc,                  \
+                .bclk_shift = bs,               \
+                .aclkreg = ar,                  \
+                .get_rate = aclk_get_rate,      \
+                .set_rate = aclk_set_rate,      \
+                .round_rate = aclk_round_rate,  \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .set_parent = aclk_set_parent,  \
+        };
+
+#define DEFINE_BCLOCK(name, bc, bs, gr, p)      \
+        static struct clk name = {              \
+                .root_id = CLK_SRC_NOROOT,      \
+                .bclkctr = bc,                  \
+                .bclk_shift = bs,               \
+                .get_rate = gr,                 \
+                .enable = enable_clk,           \
+                .disable = disable_clk,         \
+                .parent = p,                    \
+        };
+
+DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
+DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
+DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
+DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
+DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
+DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
+DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
+DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
+DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
+DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
+
+/* The following 3 clocks are special and are initialized explicitly later */
+DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
+DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
+DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
+
+DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
+DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
+DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
+DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
+DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
+DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
+DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
+DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
+DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
+DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
+DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
+DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
+DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
+DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
+DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
+DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
+DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
+DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
+DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
+DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
+DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
+DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
+DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
+DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
+DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
+DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
+
+DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
+DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
+DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
+DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
+DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
+DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
+DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
+DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
+DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
+DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
+DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
+DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
+DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
+DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
+DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
+DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
+DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
+DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
+DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
+DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
+DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
+DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK(NULL, "bus", bus)
+        _REGISTER_CLOCK(NULL, "cpu", cpu)
+        _REGISTER_CLOCK(NULL, "tct", tct)
+        _REGISTER_CLOCK(NULL, "tcx", tcx)
+        _REGISTER_CLOCK(NULL, "tcz", tcz)
+        _REGISTER_CLOCK(NULL, "ref", ref)
+        _REGISTER_CLOCK(NULL, "dai0", dai0)
+        _REGISTER_CLOCK(NULL, "pic", pic)
+        _REGISTER_CLOCK(NULL, "tc", tc)
+        _REGISTER_CLOCK(NULL, "gpio", gpio)
+        _REGISTER_CLOCK(NULL, "usbd", usbd)
+        _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
+        _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
+        _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
+        _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
+        _REGISTER_CLOCK(NULL, "ecc", ecc)
+        _REGISTER_CLOCK(NULL, "adc", adc)
+        _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
+        _REGISTER_CLOCK(NULL, "gdma0", gdma0)
+        _REGISTER_CLOCK(NULL, "lcd", lcd)
+        _REGISTER_CLOCK(NULL, "rtc", rtc)
+        _REGISTER_CLOCK(NULL, "nfc", nfc)
+        _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
+        _REGISTER_CLOCK(NULL, "g2d", g2d)
+        _REGISTER_CLOCK(NULL, "gdma1", gdma1)
+        _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
+        _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
+        _REGISTER_CLOCK(NULL, "mscl", mscl)
+        _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
+        _REGISTER_CLOCK(NULL, "bdma", bdma)
+        _REGISTER_CLOCK(NULL, "adma0", adma0)
+        _REGISTER_CLOCK(NULL, "spdif", spdif)
+        _REGISTER_CLOCK(NULL, "scfg", scfg)
+        _REGISTER_CLOCK(NULL, "cid", cid)
+        _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
+        _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
+        _REGISTER_CLOCK(NULL, "dai1", dai1)
+        _REGISTER_CLOCK(NULL, "adma1", adma1)
+        _REGISTER_CLOCK(NULL, "c3dec", c3dec)
+        _REGISTER_CLOCK("tcc-can.0", NULL, can0)
+        _REGISTER_CLOCK("tcc-can.1", NULL, can1)
+        _REGISTER_CLOCK(NULL, "gps", gps)
+        _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
+        _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
+        _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
+        _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
+        _REGISTER_CLOCK(NULL, "gdma2", gdma2)
+        _REGISTER_CLOCK(NULL, "gdma3", gdma3)
+        _REGISTER_CLOCK(NULL, "ddrc", ddrc)
+        _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
+};
+
+static struct clk *root_clk_by_index(enum root_clks src)
+{
+        switch (src) {
+        case CLK_SRC_PLL0: return &pll0;
+        case CLK_SRC_PLL1: return &pll1;
+        case CLK_SRC_PLL2: return &pll2;
+        case CLK_SRC_PLL0DIV: return &pll0div;
+        case CLK_SRC_PLL1DIV: return &pll1div;
+        case CLK_SRC_PLL2DIV: return &pll2div;
+        case CLK_SRC_XI: return &xi;
+        case CLK_SRC_XTI: return &xti;
+        case CLK_SRC_XIDIV: return &xidiv;
+        case CLK_SRC_XTIDIV: return &xtidiv;
+        default: return NULL;
+        }
+}
+
+static void find_aclk_parent(struct clk *clk)
+{
+        unsigned int src;
+        struct clk *clock;
+
+        if (!clk->aclkreg)
+                return;
+
+        src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+        src &= CLK_SRC_MASK;
+
+        clock = root_clk_by_index(src);
+        if (!clock)
+                return;
+
+        clk->parent = clock;
+        clk->set_parent = aclk_set_parent;
+}
+
+void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
+{
+        int i;
+
+        xi_rate = xi_freq;
+        xti_rate = xti_freq;
+
+        /* fixup parents and add the clock */
+        for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+                find_aclk_parent(lookups[i].clk);
+                clkdev_add(&lookups[i]);
+        }
+        tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
+}
diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h
new file mode 100644
index 00000000000..705690add39
--- /dev/null
+++ b/arch/arm/mach-tcc8k/common.h
@@ -0,0 +1,15 @@
+#ifndef MACH_TCC8K_COMMON_H
+#define MACH_TCC8K_COMMON_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device tcc_nand_device;
+
+struct clk;
+
+extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
+extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq);
+extern void tcc8k_init_irq(void);
+extern void tcc8k_map_common_io(void);
+
+#endif
diff --git a/arch/arm/mach-tcc8k/devices.c b/arch/arm/mach-tcc8k/devices.c
new file mode 100644
index 00000000000..6722ad7c283
--- /dev/null
+++ b/arch/arm/mach-tcc8k/devices.c
@@ -0,0 +1,239 @@
+/*
+ * linux/arch/arm/mach-tcc8k/devices.c
+ *
+ * Copyright (C) Telechips, Inc.
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of GPL v2.
+ *
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+static u64 tcc8k_dmamask = DMA_BIT_MASK(32);
+
+#ifdef CONFIG_MTD_NAND_TCC
+/* NAND controller */
+static struct resource tcc_nand_resources[] = {
+        {
+                .start  = (resource_size_t)NFC_BASE,
+                .end    = (resource_size_t)NFC_BASE + 0x7f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = INT_NFC,
+                .end    = INT_NFC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device tcc_nand_device = {
+        .name = "tcc_nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(tcc_nand_resources),
+        .resource = tcc_nand_resources,
+};
+#endif
+
+#ifdef CONFIG_MMC_TCC8K
+/* MMC controller */
+static struct resource tcc8k_mmc0_resource[] = {
+        {
+                .start = INT_SD0,
+                .end   = INT_SD0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource tcc8k_mmc1_resource[] = {
+        {
+                .start = INT_SD1,
+                .end   = INT_SD1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device tcc8k_mmc0_device = {
+        .name           = "tcc-mmc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(tcc8k_mmc0_resource),
+        .resource       = tcc8k_mmc0_resource,
+        .dev            = {
+                .dma_mask               = &tcc8k_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+
+struct platform_device tcc8k_mmc1_device = {
+        .name           = "tcc-mmc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(tcc8k_mmc1_resource),
+        .resource       = tcc8k_mmc1_resource,
+        .dev            = {
+                .dma_mask               = &tcc8k_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+
+static inline void tcc8k_init_mmc(void)
+{
+        u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS);
+
+        reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS;
+        __raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS);
+
+        platform_device_register(&tcc8k_mmc0_device);
+        platform_device_register(&tcc8k_mmc1_device);
+}
+#else
+static inline void tcc8k_init_mmc(void) { }
+#endif
+
+#ifdef CONFIG_USB_OHCI_HCD
+static int tcc8k_ohci_init(struct device *dev)
+{
+        u32 reg;
+
+        /* Use GPIO PK19 as VBUS control output */
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS);
+        reg &= ~(1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS);
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS);
+        reg &= ~(1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS);
+
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS);
+        reg |= (1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS);
+        /* Turn on VBUS */
+        reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS);
+        reg |= (1 << 19);
+        __raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS);
+
+        return 0;
+}
+
+static struct resource tcc8k_ohci0_resources[] = {
+        [0] = {
+                .start = (resource_size_t)USBH0_BASE,
+                .end   = (resource_size_t)USBH0_BASE + 0x5c,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = INT_USBH0,
+                .end   = INT_USBH0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource tcc8k_ohci1_resources[] = {
+        [0] = {
+                .start = (resource_size_t)USBH1_BASE,
+                .end   = (resource_size_t)USBH1_BASE + 0x5c,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = INT_USBH1,
+                .end   = INT_USBH1,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct tccohci_platform_data tcc8k_ohci0_platform_data = {
+        .controller     = 0,
+        .port_mode      = PMM_PERPORT_MODE,
+        .init           = tcc8k_ohci_init,
+};
+
+static struct tccohci_platform_data tcc8k_ohci1_platform_data = {
+        .controller     = 1,
+        .port_mode      = PMM_PERPORT_MODE,
+        .init           = tcc8k_ohci_init,
+};
+
+static struct platform_device ohci0_device = {
+        .name = "tcc-ohci",
+        .id = 0,
+        .dev = {
+                .dma_mask = &tcc8k_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tcc8k_ohci0_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(tcc8k_ohci0_resources),
+        .resource       = tcc8k_ohci0_resources,
+};
+
+static struct platform_device ohci1_device = {
+        .name = "tcc-ohci",
+        .id = 1,
+        .dev = {
+                .dma_mask = &tcc8k_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &tcc8k_ohci1_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(tcc8k_ohci1_resources),
+        .resource       = tcc8k_ohci1_resources,
+};
+
+static void __init tcc8k_init_usbhost(void)
+{
+        platform_device_register(&ohci0_device);
+        platform_device_register(&ohci1_device);
+}
+#else
+static void __init tcc8k_init_usbhost(void) { }
+#endif
+
+/* USB device controller*/
+#ifdef CONFIG_USB_GADGET_TCC8K
+static struct resource udc_resources[] = {
+        [0] = {
+                .start = INT_USBD,
+                .end   = INT_USBD,
+                .flags = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start = INT_UDMA,
+                .end   = INT_UDMA,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tcc8k_udc_device = {
+        .name = "tcc-udc",
+        .id = 0,
+        .resource = udc_resources,
+        .num_resources = ARRAY_SIZE(udc_resources),
+        .dev = {
+                 .dma_mask = &tcc8k_dmamask,
+                 .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static void __init tcc8k_init_usb_gadget(void)
+{
+        platform_device_register(&tcc8k_udc_device);
+}
+#else
+static void __init tcc8k_init_usb_gadget(void) { }
+#endif  /* CONFIG_USB_GADGET_TCC83X */
+
+static int __init tcc8k_init_devices(void)
+{
+        tcc8k_init_mmc();
+        tcc8k_init_usbhost();
+        tcc8k_init_usb_gadget();
+        return 0;
+}
+
+arch_initcall(tcc8k_init_devices);
diff --git a/arch/arm/mach-tcc8k/io.c b/arch/arm/mach-tcc8k/io.c
new file mode 100644
index 00000000000..9b39d7fa658
--- /dev/null
+++ b/arch/arm/mach-tcc8k/io.c
@@ -0,0 +1,62 @@
+/*
+ * linux/arch/arm/mach-tcc8k/io.c
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * derived from TCC83xx io.c
+ * Copyright (C) Telechips, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/tcc8k-regs.h>
+
+/*
+ * The machine specific code may provide the extra mapping besides the
+ * default mapping provided here.
+ */
+static struct map_desc tcc8k_io_desc[] __initdata = {
+        {
+                .virtual        = (unsigned long)CS1_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CS1_BASE),
+                .length         = CS1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)AHB_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(AHB_PERI_BASE),
+                .length         = AHB_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)APB0_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(APB0_PERI_BASE),
+                .length         = APB0_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)APB1_PERI_BASE_VIRT,
+                .pfn            = __phys_to_pfn(APB1_PERI_BASE),
+                .length         = APB1_PERI_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)EXT_MEM_CTRL_BASE_VIRT,
+                .pfn            = __phys_to_pfn(EXT_MEM_CTRL_BASE),
+                .length         = EXT_MEM_CTRL_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/*
+ * Maps common IO regions for tcc8k.
+ *
+ */
+void __init tcc8k_map_common_io(void)
+{
+        iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc));
+}
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
new file mode 100644
index 00000000000..34575c4963f
--- /dev/null
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) Telechips, Inc.
+ * Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU GPL version 2.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+/* Disable IRQ */
+static void tcc8000_mask_ack_irq0(unsigned int irq)
+{
+        PIC0_IEN &= ~(1 << irq);
+        PIC0_CREQ |=  (1 << irq);
+}
+
+static void tcc8000_mask_ack_irq1(unsigned int irq)
+{
+        PIC1_IEN &= ~(1 << (irq - 32));
+        PIC1_CREQ |= (1 << (irq - 32));
+}
+
+static void tcc8000_mask_irq0(unsigned int irq)
+{
+        PIC0_IEN &= ~(1 << irq);
+}
+
+static void tcc8000_mask_irq1(unsigned int irq)
+{
+        PIC1_IEN &= ~(1 << (irq - 32));
+}
+
+static void tcc8000_ack_irq0(unsigned int irq)
+{
+        PIC0_CREQ |=  (1 << irq);
+}
+
+static void tcc8000_ack_irq1(unsigned int irq)
+{
+        PIC1_CREQ |= (1 << (irq - 32));
+}
+
+/* Enable IRQ */
+static void tcc8000_unmask_irq0(unsigned int irq)
+{
+        PIC0_IEN |= (1 << irq);
+        PIC0_INTOEN |= (1 << irq);
+}
+
+static void tcc8000_unmask_irq1(unsigned int irq)
+{
+        PIC1_IEN |= (1 << (irq - 32));
+        PIC1_INTOEN |= (1 << (irq - 32));
+}
+
+static struct irq_chip tcc8000_irq_chip0 = {
+        .name           = "tcc_irq0",
+        .mask           = tcc8000_mask_irq0,
+        .ack            = tcc8000_ack_irq0,
+        .mask_ack       = tcc8000_mask_ack_irq0,
+        .unmask         = tcc8000_unmask_irq0,
+};
+
+static struct irq_chip tcc8000_irq_chip1 = {
+        .name           = "tcc_irq1",
+        .mask           = tcc8000_mask_irq1,
+        .ack            = tcc8000_ack_irq1,
+        .mask_ack       = tcc8000_mask_ack_irq1,
+        .unmask         = tcc8000_unmask_irq1,
+};
+
+void __init tcc8k_init_irq(void)
+{
+        int irqno;
+
+        /* Mask and clear all interrupts */
+        PIC0_IEN = 0x00000000;
+        PIC0_CREQ = 0xffffffff;
+        PIC1_IEN = 0x00000000;
+        PIC1_CREQ = 0xffffffff;
+
+        PIC0_MEN0 = 0x00000003;
+        PIC1_MEN1 = 0x00000003;
+        PIC1_MEN = 0x00000003;
+
+        /* let all IRQs be level triggered */
+        PIC0_TMODE = 0xffffffff;
+        PIC1_TMODE = 0xffffffff;
+        /* all IRQs are IRQs (not FIQs) */
+        PIC0_IRQSEL = 0xffffffff;
+        PIC1_IRQSEL = 0xffffffff;
+
+        for (irqno = 0; irqno < NR_IRQS; irqno++) {
+                if (irqno < 32)
+                        set_irq_chip(irqno, &tcc8000_irq_chip0);
+                else
+                        set_irq_chip(irqno, &tcc8000_irq_chip1);
+                set_irq_handler(irqno, handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c
new file mode 100644
index 00000000000..78d06008841
--- /dev/null
+++ b/arch/arm/mach-tcc8k/time.c
@@ -0,0 +1,149 @@
+/*
+ * TCC8000 system timer setup
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL version 2.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/tcc8k-regs.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+static void __iomem *timer_base;
+
+static cycle_t tcc_get_cycles(struct clocksource *cs)
+{
+        return __raw_readl(timer_base + TC32MCNT_OFFS);
+}
+
+static struct clocksource clocksource_tcc = {
+        .name           = "tcc_tc32",
+        .rating         = 200,
+        .read           = tcc_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 28,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int tcc_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
+
+        __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
+        return 0;
+}
+
+static void tcc_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        unsigned long tc32irq;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+                tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
+                tc32irq |= TC32IRQ_IRQEN0;
+                __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
+                tc32irq &= ~TC32IRQ_IRQEN0;
+                __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
+                break;
+        case CLOCK_EVT_MODE_PERIODIC:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        /* Acknowledge TC32 interrupt by reading TC32IRQ */
+        __raw_readl(timer_base + TC32IRQ_OFFS);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_tcc = {
+        .name           = "tcc_timer1",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = tcc_set_mode,
+        .set_next_event = tcc_set_next_event,
+        .rating         = 200,
+};
+
+static struct irqaction tcc8k_timer_irq = {
+        .name           = "TC32_timer",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = tcc8k_timer_interrupt,
+        .dev_id         = &clockevent_tcc,
+};
+
+static int __init tcc_clockevent_init(struct clk *clock)
+{
+        unsigned int c = clk_get_rate(clock);
+
+        clocksource_tcc.mult = clocksource_hz2mult(c,
+                                        clocksource_tcc.shift);
+        clocksource_register(&clocksource_tcc);
+
+        clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
+                                        clockevent_tcc.shift);
+        clockevent_tcc.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
+        clockevent_tcc.min_delta_ns =
+                        clockevent_delta2ns(0xff, &clockevent_tcc);
+
+        clockevent_tcc.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&clockevent_tcc);
+
+        return 0;
+}
+
+void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
+{
+        u32 reg;
+
+        timer_base = base;
+        tcc8k_timer_irq.irq = irq;
+
+        /* Enable clocks */
+        clk_enable(clock);
+
+        /* Initialize 32-bit timer */
+        reg = __raw_readl(timer_base + TC32EN_OFFS);
+        reg &= ~TC32EN_ENABLE; /* Disable timer */
+        __raw_writel(reg, timer_base + TC32EN_OFFS);
+        /* Free running timer, counting from 0 to 0xffffffff */
+        __raw_writel(0, timer_base + TC32EN_OFFS);
+        __raw_writel(0, timer_base + TC32LDV_OFFS);
+        reg = __raw_readl(timer_base + TC32IRQ_OFFS);
+        reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
+        __raw_writel(reg, timer_base + TC32IRQ_OFFS);
+
+        __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
+
+        tcc_clockevent_init(clock);
+        setup_irq(irq, &tcc8k_timer_irq);
+}
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index a57713c1954..acd9552f8ad 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -16,6 +16,10 @@ config ARCH_TEGRA_2x_SOC
 
 endchoice
 
+config TEGRA_PCI
+        bool "PCI Express support"
+        select PCI
+
 comment "Tegra board type"
 
 config MACH_HARMONY
@@ -47,4 +51,11 @@ config TEGRA_DEBUG_UARTE
 
 endchoice
 
+config TEGRA_SYSTEM_DMA
+        bool "Enable system DMA driver for NVIDIA Tegra SoCs"
+        default y
+        help
+          Adds system DMA functionality for NVIDIA Tegra SoCs, used by
+          several Tegra device drivers
+
 endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 51e9370eed9..cdbc68e4c0c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,14 +1,21 @@
 obj-y                                   += common.o
 obj-y                                   += io.o
-obj-y                                   += irq.o
+obj-y                                   += irq.o legacy_irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
 obj-y                                   += pinmux.o
+obj-y                                   += fuse.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_dvfs.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-t2-tables.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
+obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
+obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
 obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
 obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
+obj-${CONFIG_MACH_HARMONY}              += board-harmony-pcie.o
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
new file mode 100644
index 00000000000..f7e7d4514b6
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-tegra/board-harmony-pcie.c
+ *
+ * Copyright (C) 2010 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/pinmux.h>
+#include "board.h"
+
+#ifdef CONFIG_TEGRA_PCI
+
+static int __init harmony_pcie_init(void)
+{
+        int err;
+
+        if (!machine_is_harmony())
+                return 0;
+
+        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
+        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
+        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
+
+        err = tegra_pcie_init(true, true);
+        if (err)
+                goto err_pcie;
+
+        return 0;
+
+err_pcie:
+        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE);
+        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE);
+        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
+
+        return err;
+}
+
+subsys_initcall(harmony_pcie_init);
+
+#endif
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 9e305de56be..b9dbdb1289d 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -115,8 +115,6 @@ static void __init tegra_harmony_init(void)
 
 MACHINE_START(HARMONY, "harmony")
         .boot_params  = 0x00000100,
-        .phys_io        = IO_APB_PHYS,
-        .io_pg_offst    = ((IO_APB_VIRT) >> 18) & 0xfffc,
         .fixup          = tegra_harmony_fixup,
         .init_irq       = tegra_init_irq,
         .init_machine   = tegra_harmony_init,
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 3d06354136f..0de565ca37c 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -27,6 +27,7 @@ void __init tegra_common_init(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_init_clock(void);
+int __init tegra_pcie_init(bool init_port0, bool init_port1);
 
 extern struct sys_timer tegra_timer;
 #endif
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 03ad578349b..ae19f95585b 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -24,13 +24,80 @@
 #include <linux/debugfs.h>
 #include <linux/slab.h>
 #include <linux/seq_file.h>
+#include <linux/regulator/consumer.h>
 #include <asm/clkdev.h>
 
 #include "clock.h"
+#include "board.h"
+#include "fuse.h"
 
 static LIST_HEAD(clocks);
 
 static DEFINE_SPINLOCK(clock_lock);
+static DEFINE_MUTEX(dvfs_lock);
+
+static int clk_is_dvfs(struct clk *c)
+{
+        return (c->dvfs != NULL);
+};
+
+static int dvfs_set_rate(struct dvfs *d, unsigned long rate)
+{
+        struct dvfs_table *t;
+
+        if (d->table == NULL)
+                return -ENODEV;
+
+        for (t = d->table; t->rate != 0; t++) {
+                if (rate <= t->rate) {
+                        if (!d->reg)
+                                return 0;
+
+                        return regulator_set_voltage(d->reg,
+                                t->millivolts * 1000,
+                                d->max_millivolts * 1000);
+                }
+        }
+
+        return -EINVAL;
+}
+
+static void dvfs_init(struct clk *c)
+{
+        int process_id;
+        int i;
+        struct dvfs_table *table;
+
+        process_id = c->dvfs->cpu ? tegra_core_process_id() :
+                tegra_cpu_process_id();
+
+        for (i = 0; i < c->dvfs->process_id_table_length; i++)
+                if (process_id == c->dvfs->process_id_table[i].process_id)
+                        c->dvfs->table = c->dvfs->process_id_table[i].table;
+
+        if (c->dvfs->table == NULL) {
+                pr_err("Failed to find dvfs table for clock %s process %d\n",
+                        c->name, process_id);
+                return;
+        }
+
+        c->dvfs->max_millivolts = 0;
+        for (table = c->dvfs->table; table->rate != 0; table++)
+                if (c->dvfs->max_millivolts < table->millivolts)
+                        c->dvfs->max_millivolts = table->millivolts;
+
+        c->dvfs->reg = regulator_get(NULL, c->dvfs->reg_id);
+
+        if (IS_ERR(c->dvfs->reg)) {
+                pr_err("Failed to get regulator %s for clock %s\n",
+                        c->dvfs->reg_id, c->name);
+                c->dvfs->reg = NULL;
+                return;
+        }
+
+        if (c->refcnt > 0)
+                dvfs_set_rate(c->dvfs, c->rate);
+}
 
 struct clk *tegra_get_clock_by_name(const char *name)
 {
@@ -48,14 +115,31 @@ struct clk *tegra_get_clock_by_name(const char *name)
         return ret;
 }
 
+static void clk_recalculate_rate(struct clk *c)
+{
+        u64 rate;
+
+        if (!c->parent)
+                return;
+
+        rate = c->parent->rate;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate = rate * c->mul;
+                do_div(rate, c->div);
+        }
+
+        if (rate > c->max_rate)
+                pr_warn("clocks: Set clock %s to rate %llu, max is %lu\n",
+                        c->name, rate, c->max_rate);
+
+        c->rate = rate;
+}
+
 int clk_reparent(struct clk *c, struct clk *parent)
 {
         pr_debug("%s: %s\n", __func__, c->name);
-        if (c->refcnt && c->parent)
-                clk_disable_locked(c->parent);
         c->parent = parent;
-        if (c->refcnt && c->parent)
-                clk_enable_locked(c->parent);
         list_del(&c->sibling);
         list_add_tail(&c->sibling, &parent->children);
         return 0;
@@ -67,8 +151,7 @@ static void propagate_rate(struct clk *c)
         pr_debug("%s: %s\n", __func__, c->name);
         list_for_each_entry(clkp, &c->children, sibling) {
                 pr_debug("   %s\n", clkp->name);
-                if (clkp->ops->recalculate_rate)
-                        clkp->ops->recalculate_rate(clkp);
+                clk_recalculate_rate(clkp);
                 propagate_rate(clkp);
         }
 }
@@ -77,6 +160,8 @@ void clk_init(struct clk *c)
 {
         unsigned long flags;
 
+        pr_debug("%s: %s\n", __func__, c->name);
+
         spin_lock_irqsave(&clock_lock, flags);
 
         INIT_LIST_HEAD(&c->children);
@@ -85,6 +170,8 @@ void clk_init(struct clk *c)
         if (c->ops && c->ops->init)
                 c->ops->init(c);
 
+        clk_recalculate_rate(c);
+
         list_add(&c->node, &clocks);
 
         if (c->parent)
@@ -122,13 +209,38 @@ int clk_enable_locked(struct clk *c)
         return 0;
 }
 
+int clk_enable_cansleep(struct clk *c)
+{
+        int ret;
+        unsigned long flags;
+
+        mutex_lock(&dvfs_lock);
+
+        if (clk_is_dvfs(c) && c->refcnt > 0)
+                dvfs_set_rate(c->dvfs, c->rate);
+
+        spin_lock_irqsave(&clock_lock, flags);
+        ret = clk_enable_locked(c);
+        spin_unlock_irqrestore(&clock_lock, flags);
+
+        mutex_unlock(&dvfs_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable_cansleep);
+
 int clk_enable(struct clk *c)
 {
         int ret;
         unsigned long flags;
+
+        if (clk_is_dvfs(c))
+                BUG();
+
         spin_lock_irqsave(&clock_lock, flags);
         ret = clk_enable_locked(c);
         spin_unlock_irqrestore(&clock_lock, flags);
+
         return ret;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -152,9 +264,30 @@ void clk_disable_locked(struct clk *c)
         c->refcnt--;
 }
 
+void clk_disable_cansleep(struct clk *c)
+{
+        unsigned long flags;
+
+        mutex_lock(&dvfs_lock);
+
+        spin_lock_irqsave(&clock_lock, flags);
+        clk_disable_locked(c);
+        spin_unlock_irqrestore(&clock_lock, flags);
+
+        if (clk_is_dvfs(c) && c->refcnt == 0)
+                dvfs_set_rate(c->dvfs, c->rate);
+
+        mutex_unlock(&dvfs_lock);
+}
+EXPORT_SYMBOL(clk_disable_cansleep);
+
 void clk_disable(struct clk *c)
 {
         unsigned long flags;
+
+        if (clk_is_dvfs(c))
+                BUG();
+
         spin_lock_irqsave(&clock_lock, flags);
         clk_disable_locked(c);
         spin_unlock_irqrestore(&clock_lock, flags);
@@ -175,6 +308,8 @@ int clk_set_parent_locked(struct clk *c, struct clk *parent)
         if (ret)
                 return ret;
 
+        clk_recalculate_rate(c);
+
         propagate_rate(c);
 
         return 0;
@@ -197,22 +332,69 @@ struct clk *clk_get_parent(struct clk *c)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
-int clk_set_rate(struct clk *c, unsigned long rate)
+int clk_set_rate_locked(struct clk *c, unsigned long rate)
+{
+        int ret;
+
+        if (rate > c->max_rate)
+                rate = c->max_rate;
+
+        if (!c->ops || !c->ops->set_rate)
+                return -ENOSYS;
+
+        ret = c->ops->set_rate(c, rate);
+
+        if (ret)
+                return ret;
+
+        clk_recalculate_rate(c);
+
+        propagate_rate(c);
+
+        return 0;
+}
+
+int clk_set_rate_cansleep(struct clk *c, unsigned long rate)
 {
         int ret = 0;
         unsigned long flags;
 
+        pr_debug("%s: %s\n", __func__, c->name);
+
+        mutex_lock(&dvfs_lock);
+
+        if (rate > c->rate)
+                ret = dvfs_set_rate(c->dvfs, rate);
+        if (ret)
+                goto out;
+
         spin_lock_irqsave(&clock_lock, flags);
+        ret = clk_set_rate_locked(c, rate);
+        spin_unlock_irqrestore(&clock_lock, flags);
 
-        pr_debug("%s: %s\n", __func__, c->name);
+        if (ret)
+                goto out;
 
-        if (c->ops && c->ops->set_rate)
-                ret = c->ops->set_rate(c, rate);
-        else
-                ret = -ENOSYS;
+        ret = dvfs_set_rate(c->dvfs, rate);
 
-        propagate_rate(c);
+out:
+        mutex_unlock(&dvfs_lock);
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate_cansleep);
+
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+        int ret = 0;
+        unsigned long flags;
+
+        pr_debug("%s: %s\n", __func__, c->name);
+
+        if (clk_is_dvfs(c))
+                BUG();
 
+        spin_lock_irqsave(&clock_lock, flags);
+        ret = clk_set_rate_locked(c, rate);
         spin_unlock_irqrestore(&clock_lock, flags);
 
         return ret;
@@ -235,6 +417,20 @@ unsigned long clk_get_rate(struct clk *c)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+long clk_round_rate(struct clk *c, unsigned long rate)
+{
+        pr_debug("%s: %s\n", __func__, c->name);
+
+        if (!c->ops || !c->ops->round_rate)
+                return -ENOSYS;
+
+        if (rate > c->max_rate)
+                rate = c->max_rate;
+
+        return c->ops->round_rate(c, rate);
+}
+EXPORT_SYMBOL(clk_round_rate);
+
 static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
 {
         struct clk *c;
@@ -308,13 +504,28 @@ void tegra_periph_reset_assert(struct clk *c)
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
-int __init tegra_init_clock(void)
+void __init tegra_init_clock(void)
 {
         tegra2_init_clocks();
+}
+
+int __init tegra_init_dvfs(void)
+{
+        struct clk *c, *safe;
+
+        mutex_lock(&dvfs_lock);
+
+        list_for_each_entry_safe(c, safe, &clocks, node)
+                if (c->dvfs)
+                        dvfs_init(c);
+
+        mutex_unlock(&dvfs_lock);
 
         return 0;
 }
 
+late_initcall(tegra_init_dvfs);
+
 #ifdef CONFIG_DEBUG_FS
 static struct dentry *clk_debugfs_root;
 
@@ -324,7 +535,7 @@ static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
         struct clk *child;
         struct clk *safe;
         const char *state = "uninit";
-        char div[5] = {0};
+        char div[8] = {0};
 
         if (c->state == ON)
                 state = "on";
@@ -332,16 +543,26 @@ static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
                 state = "off";
 
         if (c->mul != 0 && c->div != 0) {
-                BUG_ON(c->mul > 2);
-                if (c->mul > c->div)
-                        snprintf(div, sizeof(div), "x%d", c->mul / c->div);
-                else
+                if (c->mul > c->div) {
+                        int mul = c->mul / c->div;
+                        int mul2 = (c->mul * 10 / c->div) % 10;
+                        int mul3 = (c->mul * 10) % c->div;
+                        if (mul2 == 0 && mul3 == 0)
+                                snprintf(div, sizeof(div), "x%d", mul);
+                        else if (mul3 == 0)
+                                snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
+                        else
+                                snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
+                } else {
                         snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
                                 (c->div % c->mul) ? ".5" : "");
+                }
         }
 
-        seq_printf(s, "%*s%-*s %-6s %-3d %-5s %-10lu\n",
-                level * 3 + 1, c->set ? "" : "*",
+        seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
+                level * 3 + 1, "",
+                c->rate > c->max_rate ? '!' : ' ',
+                !c->set ? '*' : ' ',
                 30 - level * 3, c->name,
                 state, c->refcnt, div, c->rate);
         list_for_each_entry_safe(child, safe, &c->children, sibling) {
@@ -353,8 +574,8 @@ static int clock_tree_show(struct seq_file *s, void *data)
 {
         struct clk *c;
         unsigned long flags;
-        seq_printf(s, " clock                          state  ref div   rate      \n");
-        seq_printf(s, "-----------------------------------------------------------\n");
+        seq_printf(s, "   clock                          state  ref div      rate\n");
+        seq_printf(s, "--------------------------------------------------------------\n");
         spin_lock_irqsave(&clock_lock, flags);
         list_for_each_entry(c, &clocks, node)
                 if (c->parent == NULL)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index af7c70e2a3b..94fd859770f 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -27,18 +27,43 @@
 #define DIV_U71                 (1 << 1)
 #define DIV_U71_FIXED           (1 << 2)
 #define DIV_2                   (1 << 3)
-#define PLL_FIXED               (1 << 4)
-#define PLL_HAS_CPCON           (1 << 5)
-#define MUX                     (1 << 6)
-#define PLLD                    (1 << 7)
-#define PERIPH_NO_RESET         (1 << 8)
-#define PERIPH_NO_ENB           (1 << 9)
-#define PERIPH_EMC_ENB          (1 << 10)
-#define PERIPH_MANUAL_RESET     (1 << 11)
-#define PLL_ALT_MISC_REG        (1 << 12)
+#define DIV_U16                 (1 << 4)
+#define PLL_FIXED               (1 << 5)
+#define PLL_HAS_CPCON           (1 << 6)
+#define MUX                     (1 << 7)
+#define PLLD                    (1 << 8)
+#define PERIPH_NO_RESET         (1 << 9)
+#define PERIPH_NO_ENB           (1 << 10)
+#define PERIPH_EMC_ENB          (1 << 11)
+#define PERIPH_MANUAL_RESET     (1 << 12)
+#define PLL_ALT_MISC_REG        (1 << 13)
+#define PLLU                    (1 << 14)
 #define ENABLE_ON_INIT          (1 << 28)
 
 struct clk;
+struct regulator;
+
+struct dvfs_table {
+        unsigned long rate;
+        int millivolts;
+};
+
+struct dvfs_process_id_table {
+        int process_id;
+        struct dvfs_table *table;
+};
+
+
+struct dvfs {
+        struct regulator *reg;
+        struct dvfs_table *table;
+        int max_millivolts;
+
+        int process_id_table_length;
+        const char *reg_id;
+        bool cpu;
+        struct dvfs_process_id_table process_id_table[];
+};
 
 struct clk_mux_sel {
         struct clk      *input;
@@ -58,12 +83,9 @@ struct clk_ops {
         void            (*init)(struct clk *);
         int             (*enable)(struct clk *);
         void            (*disable)(struct clk *);
-        void            (*recalc)(struct clk *);
         int             (*set_parent)(struct clk *, struct clk *);
         int             (*set_rate)(struct clk *, unsigned long);
-        unsigned long   (*get_rate)(struct clk *);
         long            (*round_rate)(struct clk *, unsigned long);
-        unsigned long   (*recalculate_rate)(struct clk *);
 };
 
 enum clk_state {
@@ -85,6 +107,7 @@ struct clk {
         struct clk                      *parent;
         struct clk_lookup               lookup;
         unsigned long                   rate;
+        unsigned long                   max_rate;
         u32                             flags;
         u32                             refcnt;
         const char                      *name;
@@ -103,10 +126,6 @@ struct clk {
         unsigned long                   cf_max;
         unsigned long                   vco_min;
         unsigned long                   vco_max;
-        u32                             m;
-        u32                             n;
-        u32                             p;
-        u32                             cpcon;
         const struct clk_pll_table      *pll_table;
 
         /* DIV */
@@ -117,6 +136,12 @@ struct clk {
         const struct clk_mux_sel        *inputs;
         u32                             sel;
         u32                             reg_mask;
+
+        /* Virtual cpu clock */
+        struct clk                      *main;
+        struct clk                      *backup;
+
+        struct dvfs                     *dvfs;
 };
 
 
@@ -141,6 +166,7 @@ unsigned long clk_measure_input_freq(void);
 void clk_disable_locked(struct clk *c);
 int clk_enable_locked(struct clk *c);
 int clk_set_parent_locked(struct clk *c, struct clk *parent);
+int clk_set_rate_locked(struct clk *c, unsigned long rate);
 int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 039a514b61e..7c91e2b9d64 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -19,13 +19,17 @@
 
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
 #include <mach/iomap.h>
+#include <mach/dma.h>
 
 #include "board.h"
 #include "clock.h"
+#include "fuse.h"
 
 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
         /* name         parent          rate            enabled */
@@ -35,8 +39,8 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
         { "pll_p_out2", "pll_p",        48000000,       true },
         { "pll_p_out3", "pll_p",        72000000,       true },
         { "pll_p_out4", "pll_p",        108000000,      true },
-        { "sys",        "pll_p_out4",   108000000,      true },
-        { "hclk",       "sys",          108000000,      true },
+        { "sclk",       "pll_p_out4",   108000000,      true },
+        { "hclk",       "sclk",         108000000,      true },
         { "pclk",       "hclk",         54000000,       true },
         { NULL,         NULL,           0,              0},
 };
@@ -51,11 +55,16 @@ void __init tegra_init_cache(void)
 
         l2x0_init(p, 0x6C080001, 0x8200c3fe);
 #endif
+
 }
 
 void __init tegra_common_init(void)
 {
+        tegra_init_fuse();
         tegra_init_clock();
         tegra_clk_init_from_table(common_clk_init_table);
         tegra_init_cache();
+#ifdef CONFIG_TEGRA_SYSTEM_DMA
+        tegra_dma_init();
+#endif
 }
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
new file mode 100644
index 00000000000..fea5719c707
--- /dev/null
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -0,0 +1,185 @@
+/*
+ * arch/arm/mach-tegra/cpu-tegra.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/system.h>
+
+#include <mach/hardware.h>
+#include <mach/clk.h>
+
+/* Frequency table index must be sequential starting at 0 */
+static struct cpufreq_frequency_table freq_table[] = {
+        { 0, 312000 },
+        { 1, 456000 },
+        { 2, 608000 },
+        { 3, 760000 },
+        { 4, 816000 },
+        { 5, 912000 },
+        { 6, 1000000 },
+        { 7, CPUFREQ_TABLE_END },
+};
+
+#define NUM_CPUS        2
+
+static struct clk *cpu_clk;
+
+static unsigned long target_cpu_speed[NUM_CPUS];
+
+int tegra_verify_speed(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+unsigned int tegra_getspeed(unsigned int cpu)
+{
+        unsigned long rate;
+
+        if (cpu >= NUM_CPUS)
+                return 0;
+
+        rate = clk_get_rate(cpu_clk) / 1000;
+        return rate;
+}
+
+static int tegra_update_cpu_speed(void)
+{
+        int i;
+        unsigned long rate = 0;
+        int ret = 0;
+        struct cpufreq_freqs freqs;
+
+        for_each_online_cpu(i)
+                rate = max(rate, target_cpu_speed[i]);
+
+        freqs.old = tegra_getspeed(0);
+        freqs.new = rate;
+
+        if (freqs.old == freqs.new)
+                return ret;
+
+        for_each_online_cpu(freqs.cpu)
+                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+#ifdef CONFIG_CPU_FREQ_DEBUG
+        printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
+               freqs.old, freqs.new);
+#endif
+
+        ret = clk_set_rate_cansleep(cpu_clk, freqs.new * 1000);
+        if (ret) {
+                pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
+                        freqs.new);
+                return ret;
+        }
+
+        for_each_online_cpu(freqs.cpu)
+                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        return 0;
+}
+
+static int tegra_target(struct cpufreq_policy *policy,
+                       unsigned int target_freq,
+                       unsigned int relation)
+{
+        int idx;
+        unsigned int freq;
+
+        cpufreq_frequency_table_target(policy, freq_table, target_freq,
+                relation, &idx);
+
+        freq = freq_table[idx].frequency;
+
+        target_cpu_speed[policy->cpu] = freq;
+
+        return tegra_update_cpu_speed();
+}
+
+static int tegra_cpu_init(struct cpufreq_policy *policy)
+{
+        if (policy->cpu >= NUM_CPUS)
+                return -EINVAL;
+
+        cpu_clk = clk_get_sys(NULL, "cpu");
+        if (IS_ERR(cpu_clk))
+                return PTR_ERR(cpu_clk);
+
+        cpufreq_frequency_table_cpuinfo(policy, freq_table);
+        cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+        policy->cur = tegra_getspeed(policy->cpu);
+        target_cpu_speed[policy->cpu] = policy->cur;
+
+        /* FIXME: what's the actual transition time? */
+        policy->cpuinfo.transition_latency = 300 * 1000;
+
+        policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+        cpumask_copy(policy->related_cpus, cpu_possible_mask);
+
+        return 0;
+}
+
+static int tegra_cpu_exit(struct cpufreq_policy *policy)
+{
+        cpufreq_frequency_table_cpuinfo(policy, freq_table);
+        clk_put(cpu_clk);
+        return 0;
+}
+
+static struct freq_attr *tegra_cpufreq_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+
+static struct cpufreq_driver tegra_cpufreq_driver = {
+        .verify         = tegra_verify_speed,
+        .target         = tegra_target,
+        .get            = tegra_getspeed,
+        .init           = tegra_cpu_init,
+        .exit           = tegra_cpu_exit,
+        .name           = "tegra",
+        .attr           = tegra_cpufreq_attr,
+};
+
+static int __init tegra_cpufreq_init(void)
+{
+        return cpufreq_register_driver(&tegra_cpufreq_driver);
+}
+
+static void __exit tegra_cpufreq_exit(void)
+{
+        cpufreq_unregister_driver(&tegra_cpufreq_driver);
+}
+
+
+MODULE_AUTHOR("Colin Cross <ccross@android.com>");
+MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
+MODULE_LICENSE("GPL");
+module_init(tegra_cpufreq_init);
+module_exit(tegra_cpufreq_exit);
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
new file mode 100644
index 00000000000..edda6ec5e92
--- /dev/null
+++ b/arch/arm/mach-tegra/dma.c
@@ -0,0 +1,752 @@
+/*
+ * arch/arm/mach-tegra/dma.c
+ *
+ * System DMA driver for NVIDIA Tegra SoCs
+ *
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+
+#define APB_DMA_GEN                             0x000
+#define GEN_ENABLE                              (1<<31)
+
+#define APB_DMA_CNTRL                           0x010
+
+#define APB_DMA_IRQ_MASK                        0x01c
+
+#define APB_DMA_IRQ_MASK_SET                    0x020
+
+#define APB_DMA_CHAN_CSR                        0x000
+#define CSR_ENB                                 (1<<31)
+#define CSR_IE_EOC                              (1<<30)
+#define CSR_HOLD                                (1<<29)
+#define CSR_DIR                                 (1<<28)
+#define CSR_ONCE                                (1<<27)
+#define CSR_FLOW                                (1<<21)
+#define CSR_REQ_SEL_SHIFT                       16
+#define CSR_REQ_SEL_MASK                        (0x1F<<CSR_REQ_SEL_SHIFT)
+#define CSR_REQ_SEL_INVALID                     (31<<CSR_REQ_SEL_SHIFT)
+#define CSR_WCOUNT_SHIFT                        2
+#define CSR_WCOUNT_MASK                         0xFFFC
+
+#define APB_DMA_CHAN_STA                                0x004
+#define STA_BUSY                                (1<<31)
+#define STA_ISE_EOC                             (1<<30)
+#define STA_HALT                                (1<<29)
+#define STA_PING_PONG                           (1<<28)
+#define STA_COUNT_SHIFT                         2
+#define STA_COUNT_MASK                          0xFFFC
+
+#define APB_DMA_CHAN_AHB_PTR                            0x010
+
+#define APB_DMA_CHAN_AHB_SEQ                            0x014
+#define AHB_SEQ_INTR_ENB                        (1<<31)
+#define AHB_SEQ_BUS_WIDTH_SHIFT                 28
+#define AHB_SEQ_BUS_WIDTH_MASK                  (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT)
+#define AHB_SEQ_BUS_WIDTH_8                     (0<<AHB_SEQ_BUS_WIDTH_SHIFT)
+#define AHB_SEQ_BUS_WIDTH_16                    (1<<AHB_SEQ_BUS_WIDTH_SHIFT)
+#define AHB_SEQ_BUS_WIDTH_32                    (2<<AHB_SEQ_BUS_WIDTH_SHIFT)
+#define AHB_SEQ_BUS_WIDTH_64                    (3<<AHB_SEQ_BUS_WIDTH_SHIFT)
+#define AHB_SEQ_BUS_WIDTH_128                   (4<<AHB_SEQ_BUS_WIDTH_SHIFT)
+#define AHB_SEQ_DATA_SWAP                       (1<<27)
+#define AHB_SEQ_BURST_MASK                      (0x7<<24)
+#define AHB_SEQ_BURST_1                         (4<<24)
+#define AHB_SEQ_BURST_4                         (5<<24)
+#define AHB_SEQ_BURST_8                         (6<<24)
+#define AHB_SEQ_DBL_BUF                         (1<<19)
+#define AHB_SEQ_WRAP_SHIFT                      16
+#define AHB_SEQ_WRAP_MASK                       (0x7<<AHB_SEQ_WRAP_SHIFT)
+
+#define APB_DMA_CHAN_APB_PTR                            0x018
+
+#define APB_DMA_CHAN_APB_SEQ                            0x01c
+#define APB_SEQ_BUS_WIDTH_SHIFT                 28
+#define APB_SEQ_BUS_WIDTH_MASK                  (0x7<<APB_SEQ_BUS_WIDTH_SHIFT)
+#define APB_SEQ_BUS_WIDTH_8                     (0<<APB_SEQ_BUS_WIDTH_SHIFT)
+#define APB_SEQ_BUS_WIDTH_16                    (1<<APB_SEQ_BUS_WIDTH_SHIFT)
+#define APB_SEQ_BUS_WIDTH_32                    (2<<APB_SEQ_BUS_WIDTH_SHIFT)
+#define APB_SEQ_BUS_WIDTH_64                    (3<<APB_SEQ_BUS_WIDTH_SHIFT)
+#define APB_SEQ_BUS_WIDTH_128                   (4<<APB_SEQ_BUS_WIDTH_SHIFT)
+#define APB_SEQ_DATA_SWAP                       (1<<27)
+#define APB_SEQ_WRAP_SHIFT                      16
+#define APB_SEQ_WRAP_MASK                       (0x7<<APB_SEQ_WRAP_SHIFT)
+
+#define TEGRA_SYSTEM_DMA_CH_NR                  16
+#define TEGRA_SYSTEM_DMA_AVP_CH_NUM             4
+#define TEGRA_SYSTEM_DMA_CH_MIN                 0
+#define TEGRA_SYSTEM_DMA_CH_MAX \
+        (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1)
+
+#define NV_DMA_MAX_TRASFER_SIZE 0x10000
+
+const unsigned int ahb_addr_wrap_table[8] = {
+        0, 32, 64, 128, 256, 512, 1024, 2048
+};
+
+const unsigned int apb_addr_wrap_table[8] = {0, 1, 2, 4, 8, 16, 32, 64};
+
+const unsigned int bus_width_table[5] = {8, 16, 32, 64, 128};
+
+#define TEGRA_DMA_NAME_SIZE 16
+struct tegra_dma_channel {
+        struct list_head        list;
+        int                     id;
+        spinlock_t              lock;
+        char                    name[TEGRA_DMA_NAME_SIZE];
+        void  __iomem           *addr;
+        int                     mode;
+        int                     irq;
+
+        /* Register shadow */
+        u32                     csr;
+        u32                     ahb_seq;
+        u32                     ahb_ptr;
+        u32                     apb_seq;
+        u32                     apb_ptr;
+};
+
+#define  NV_DMA_MAX_CHANNELS  32
+
+static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
+static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
+
+static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+static void tegra_dma_init_hw(struct tegra_dma_channel *ch);
+static void tegra_dma_stop(struct tegra_dma_channel *ch);
+
+void tegra_dma_flush(struct tegra_dma_channel *ch)
+{
+}
+EXPORT_SYMBOL(tegra_dma_flush);
+
+void tegra_dma_dequeue(struct tegra_dma_channel *ch)
+{
+        struct tegra_dma_req *req;
+
+        req = list_entry(ch->list.next, typeof(*req), node);
+
+        tegra_dma_dequeue_req(ch, req);
+        return;
+}
+
+void tegra_dma_stop(struct tegra_dma_channel *ch)
+{
+        unsigned int csr;
+        unsigned int status;
+
+        csr = ch->csr;
+        csr &= ~CSR_IE_EOC;
+        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
+
+        csr &= ~CSR_ENB;
+        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
+
+        status = readl(ch->addr + APB_DMA_CHAN_STA);
+        if (status & STA_ISE_EOC)
+                writel(status, ch->addr + APB_DMA_CHAN_STA);
+}
+
+int tegra_dma_cancel(struct tegra_dma_channel *ch)
+{
+        unsigned int csr;
+        unsigned long irq_flags;
+
+        spin_lock_irqsave(&ch->lock, irq_flags);
+        while (!list_empty(&ch->list))
+                list_del(ch->list.next);
+
+        csr = ch->csr;
+        csr &= ~CSR_REQ_SEL_MASK;
+        csr |= CSR_REQ_SEL_INVALID;
+
+        /* Set the enable as that is not shadowed */
+        csr |= CSR_ENB;
+        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
+
+        tegra_dma_stop(ch);
+
+        spin_unlock_irqrestore(&ch->lock, irq_flags);
+        return 0;
+}
+
+int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *_req)
+{
+        unsigned int csr;
+        unsigned int status;
+        struct tegra_dma_req *req = NULL;
+        int found = 0;
+        unsigned long irq_flags;
+        int to_transfer;
+        int req_transfer_count;
+
+        spin_lock_irqsave(&ch->lock, irq_flags);
+        list_for_each_entry(req, &ch->list, node) {
+                if (req == _req) {
+                        list_del(&req->node);
+                        found = 1;
+                        break;
+                }
+        }
+        if (!found) {
+                spin_unlock_irqrestore(&ch->lock, irq_flags);
+                return 0;
+        }
+
+        /* STOP the DMA and get the transfer count.
+         * Getting the transfer count is tricky.
+         *  - Change the source selector to invalid to stop the DMA from
+         *    FIFO to memory.
+         *  - Read the status register to know the number of pending
+         *    bytes to be transfered.
+         *  - Finally stop or program the DMA to the next buffer in the
+         *    list.
+         */
+        csr = ch->csr;
+        csr &= ~CSR_REQ_SEL_MASK;
+        csr |= CSR_REQ_SEL_INVALID;
+
+        /* Set the enable as that is not shadowed */
+        csr |= CSR_ENB;
+        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
+
+        /* Get the transfer count */
+        status = readl(ch->addr + APB_DMA_CHAN_STA);
+        to_transfer = (status & STA_COUNT_MASK) >> STA_COUNT_SHIFT;
+        req_transfer_count = (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT;
+        req_transfer_count += 1;
+        to_transfer += 1;
+
+        req->bytes_transferred = req_transfer_count;
+
+        if (status & STA_BUSY)
+                req->bytes_transferred -= to_transfer;
+
+        /* In continous transfer mode, DMA only tracks the count of the
+         * half DMA buffer. So, if the DMA already finished half the DMA
+         * then add the half buffer to the completed count.
+         *
+         *      FIXME: There can be a race here. What if the req to
+         *      dequue happens at the same time as the DMA just moved to
+         *      the new buffer and SW didn't yet received the interrupt?
+         */
+        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS)
+                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
+                        req->bytes_transferred += req_transfer_count;
+
+        req->bytes_transferred *= 4;
+
+        tegra_dma_stop(ch);
+        if (!list_empty(&ch->list)) {
+                /* if the list is not empty, queue the next request */
+                struct tegra_dma_req *next_req;
+                next_req = list_entry(ch->list.next,
+                        typeof(*next_req), node);
+                tegra_dma_update_hw(ch, next_req);
+        }
+        req->status = -TEGRA_DMA_REQ_ERROR_ABORTED;
+
+        spin_unlock_irqrestore(&ch->lock, irq_flags);
+
+        /* Callback should be called without any lock */
+        req->complete(req);
+        return 0;
+}
+EXPORT_SYMBOL(tegra_dma_dequeue_req);
+
+bool tegra_dma_is_empty(struct tegra_dma_channel *ch)
+{
+        unsigned long irq_flags;
+        bool is_empty;
+
+        spin_lock_irqsave(&ch->lock, irq_flags);
+        if (list_empty(&ch->list))
+                is_empty = true;
+        else
+                is_empty = false;
+        spin_unlock_irqrestore(&ch->lock, irq_flags);
+        return is_empty;
+}
+EXPORT_SYMBOL(tegra_dma_is_empty);
+
+bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *_req)
+{
+        unsigned long irq_flags;
+        struct tegra_dma_req *req;
+
+        spin_lock_irqsave(&ch->lock, irq_flags);
+        list_for_each_entry(req, &ch->list, node) {
+                if (req == _req) {
+                        spin_unlock_irqrestore(&ch->lock, irq_flags);
+                        return true;
+                }
+        }
+        spin_unlock_irqrestore(&ch->lock, irq_flags);
+        return false;
+}
+EXPORT_SYMBOL(tegra_dma_is_req_inflight);
+
+int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req)
+{
+        unsigned long irq_flags;
+        int start_dma = 0;
+
+        if (req->size > NV_DMA_MAX_TRASFER_SIZE ||
+                req->source_addr & 0x3 || req->dest_addr & 0x3) {
+                pr_err("Invalid DMA request for channel %d\n", ch->id);
+                return -EINVAL;
+        }
+
+        spin_lock_irqsave(&ch->lock, irq_flags);
+
+        req->bytes_transferred = 0;
+        req->status = 0;
+        req->buffer_status = 0;
+        if (list_empty(&ch->list))
+                start_dma = 1;
+
+        list_add_tail(&req->node, &ch->list);
+
+        if (start_dma)
+                tegra_dma_update_hw(ch, req);
+
+        spin_unlock_irqrestore(&ch->lock, irq_flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(tegra_dma_enqueue_req);
+
+struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
+{
+        int channel;
+        struct tegra_dma_channel *ch;
+
+        /* first channel is the shared channel */
+        if (mode & TEGRA_DMA_SHARED) {
+                channel = TEGRA_SYSTEM_DMA_CH_MIN;
+        } else {
+                channel = find_first_zero_bit(channel_usage,
+                        ARRAY_SIZE(dma_channels));
+                if (channel >= ARRAY_SIZE(dma_channels))
+                        return NULL;
+        }
+        __set_bit(channel, channel_usage);
+        ch = &dma_channels[channel];
+        ch->mode = mode;
+        return ch;
+}
+EXPORT_SYMBOL(tegra_dma_allocate_channel);
+
+void tegra_dma_free_channel(struct tegra_dma_channel *ch)
+{
+        if (ch->mode & TEGRA_DMA_SHARED)
+                return;
+        tegra_dma_cancel(ch);
+        __clear_bit(ch->id, channel_usage);
+}
+EXPORT_SYMBOL(tegra_dma_free_channel);
+
+static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req)
+{
+        if (req->to_memory) {
+                ch->apb_ptr = req->source_addr;
+                ch->ahb_ptr = req->dest_addr;
+        } else {
+                ch->apb_ptr = req->dest_addr;
+                ch->ahb_ptr = req->source_addr;
+        }
+        writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
+        writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
+
+        req->status = TEGRA_DMA_REQ_INFLIGHT;
+        return;
+}
+
+static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req)
+{
+        int ahb_addr_wrap;
+        int apb_addr_wrap;
+        int ahb_bus_width;
+        int apb_bus_width;
+        int index;
+        unsigned long csr;
+
+
+        ch->csr |= CSR_FLOW;
+        ch->csr &= ~CSR_REQ_SEL_MASK;
+        ch->csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
+        ch->ahb_seq &= ~AHB_SEQ_BURST_MASK;
+        ch->ahb_seq |= AHB_SEQ_BURST_1;
+
+        /* One shot mode is always single buffered,
+         * continuous mode is always double buffered
+         * */
+        if (ch->mode & TEGRA_DMA_MODE_ONESHOT) {
+                ch->csr |= CSR_ONCE;
+                ch->ahb_seq &= ~AHB_SEQ_DBL_BUF;
+                ch->csr &= ~CSR_WCOUNT_MASK;
+                ch->csr |= ((req->size>>2) - 1) << CSR_WCOUNT_SHIFT;
+        } else {
+                ch->csr &= ~CSR_ONCE;
+                ch->ahb_seq |= AHB_SEQ_DBL_BUF;
+
+                /* In double buffered mode, we set the size to half the
+                 * requested size and interrupt when half the buffer
+                 * is full */
+                ch->csr &= ~CSR_WCOUNT_MASK;
+                ch->csr |= ((req->size>>3) - 1) << CSR_WCOUNT_SHIFT;
+        }
+
+        if (req->to_memory) {
+                ch->csr &= ~CSR_DIR;
+                ch->apb_ptr = req->source_addr;
+                ch->ahb_ptr = req->dest_addr;
+
+                apb_addr_wrap = req->source_wrap;
+                ahb_addr_wrap = req->dest_wrap;
+                apb_bus_width = req->source_bus_width;
+                ahb_bus_width = req->dest_bus_width;
+
+        } else {
+                ch->csr |= CSR_DIR;
+                ch->apb_ptr = req->dest_addr;
+                ch->ahb_ptr = req->source_addr;
+
+                apb_addr_wrap = req->dest_wrap;
+                ahb_addr_wrap = req->source_wrap;
+                apb_bus_width = req->dest_bus_width;
+                ahb_bus_width = req->source_bus_width;
+        }
+
+        apb_addr_wrap >>= 2;
+        ahb_addr_wrap >>= 2;
+
+        /* set address wrap for APB size */
+        index = 0;
+        do  {
+                if (apb_addr_wrap_table[index] == apb_addr_wrap)
+                        break;
+                index++;
+        } while (index < ARRAY_SIZE(apb_addr_wrap_table));
+        BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table));
+        ch->apb_seq &= ~APB_SEQ_WRAP_MASK;
+        ch->apb_seq |= index << APB_SEQ_WRAP_SHIFT;
+
+        /* set address wrap for AHB size */
+        index = 0;
+        do  {
+                if (ahb_addr_wrap_table[index] == ahb_addr_wrap)
+                        break;
+                index++;
+        } while (index < ARRAY_SIZE(ahb_addr_wrap_table));
+        BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table));
+        ch->ahb_seq &= ~AHB_SEQ_WRAP_MASK;
+        ch->ahb_seq |= index << AHB_SEQ_WRAP_SHIFT;
+
+        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
+                if (bus_width_table[index] == ahb_bus_width)
+                        break;
+        }
+        BUG_ON(index == ARRAY_SIZE(bus_width_table));
+        ch->ahb_seq &= ~AHB_SEQ_BUS_WIDTH_MASK;
+        ch->ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT;
+
+        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
+                if (bus_width_table[index] == apb_bus_width)
+                        break;
+        }
+        BUG_ON(index == ARRAY_SIZE(bus_width_table));
+        ch->apb_seq &= ~APB_SEQ_BUS_WIDTH_MASK;
+        ch->apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT;
+
+        ch->csr |= CSR_IE_EOC;
+
+        /* update hw registers with the shadow */
+        writel(ch->csr, ch->addr + APB_DMA_CHAN_CSR);
+        writel(ch->apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ);
+        writel(ch->apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
+        writel(ch->ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ);
+        writel(ch->ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
+
+        csr = ch->csr | CSR_ENB;
+        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
+
+        req->status = TEGRA_DMA_REQ_INFLIGHT;
+}
+
+static void tegra_dma_init_hw(struct tegra_dma_channel *ch)
+{
+        /* One shot with an interrupt to CPU after transfer */
+        ch->csr = CSR_ONCE | CSR_IE_EOC;
+        ch->ahb_seq = AHB_SEQ_BUS_WIDTH_32 | AHB_SEQ_INTR_ENB;
+        ch->apb_seq = APB_SEQ_BUS_WIDTH_32 | 1 << APB_SEQ_WRAP_SHIFT;
+}
+
+static void handle_oneshot_dma(struct tegra_dma_channel *ch)
+{
+        struct tegra_dma_req *req;
+
+        spin_lock(&ch->lock);
+        if (list_empty(&ch->list)) {
+                spin_unlock(&ch->lock);
+                return;
+        }
+
+        req = list_entry(ch->list.next, typeof(*req), node);
+        if (req) {
+                int bytes_transferred;
+
+                bytes_transferred =
+                        (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT;
+                bytes_transferred += 1;
+                bytes_transferred <<= 2;
+
+                list_del(&req->node);
+                req->bytes_transferred = bytes_transferred;
+                req->status = TEGRA_DMA_REQ_SUCCESS;
+
+                spin_unlock(&ch->lock);
+                /* Callback should be called without any lock */
+                pr_debug("%s: transferred %d bytes\n", __func__,
+                        req->bytes_transferred);
+                req->complete(req);
+                spin_lock(&ch->lock);
+        }
+
+        if (!list_empty(&ch->list)) {
+                req = list_entry(ch->list.next, typeof(*req), node);
+                /* the complete function we just called may have enqueued
+                   another req, in which case dma has already started */
+                if (req->status != TEGRA_DMA_REQ_INFLIGHT)
+                        tegra_dma_update_hw(ch, req);
+        }
+        spin_unlock(&ch->lock);
+}
+
+static void handle_continuous_dma(struct tegra_dma_channel *ch)
+{
+        struct tegra_dma_req *req;
+
+        spin_lock(&ch->lock);
+        if (list_empty(&ch->list)) {
+                spin_unlock(&ch->lock);
+                return;
+        }
+
+        req = list_entry(ch->list.next, typeof(*req), node);
+        if (req) {
+                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) {
+                        /* Load the next request into the hardware, if available
+                         * */
+                        if (!list_is_last(&req->node, &ch->list)) {
+                                struct tegra_dma_req *next_req;
+
+                                next_req = list_entry(req->node.next,
+                                        typeof(*next_req), node);
+                                tegra_dma_update_hw_partial(ch, next_req);
+                        }
+                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL;
+                        req->status = TEGRA_DMA_REQ_SUCCESS;
+                        /* DMA lock is NOT held when callback is called */
+                        spin_unlock(&ch->lock);
+                        if (likely(req->threshold))
+                                req->threshold(req);
+                        return;
+
+                } else if (req->buffer_status ==
+                        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) {
+                        /* Callback when the buffer is completely full (i.e on
+                         * the second  interrupt */
+                        int bytes_transferred;
+
+                        bytes_transferred =
+                                (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT;
+                        bytes_transferred += 1;
+                        bytes_transferred <<= 3;
+
+                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
+                        req->bytes_transferred = bytes_transferred;
+                        req->status = TEGRA_DMA_REQ_SUCCESS;
+                        list_del(&req->node);
+
+                        /* DMA lock is NOT held when callbak is called */
+                        spin_unlock(&ch->lock);
+                        req->complete(req);
+                        return;
+
+                } else {
+                        BUG();
+                }
+        }
+        spin_unlock(&ch->lock);
+}
+
+static irqreturn_t dma_isr(int irq, void *data)
+{
+        struct tegra_dma_channel *ch = data;
+        unsigned long status;
+
+        status = readl(ch->addr + APB_DMA_CHAN_STA);
+        if (status & STA_ISE_EOC)
+                writel(status, ch->addr + APB_DMA_CHAN_STA);
+        else {
+                pr_warning("Got a spurious ISR for DMA channel %d\n", ch->id);
+                return IRQ_HANDLED;
+        }
+        return IRQ_WAKE_THREAD;
+}
+
+static irqreturn_t dma_thread_fn(int irq, void *data)
+{
+        struct tegra_dma_channel *ch = data;
+
+        if (ch->mode & TEGRA_DMA_MODE_ONESHOT)
+                handle_oneshot_dma(ch);
+        else
+                handle_continuous_dma(ch);
+
+
+        return IRQ_HANDLED;
+}
+
+int __init tegra_dma_init(void)
+{
+        int ret = 0;
+        int i;
+        unsigned int irq;
+        void __iomem *addr;
+
+        addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
+        writel(GEN_ENABLE, addr + APB_DMA_GEN);
+        writel(0, addr + APB_DMA_CNTRL);
+        writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX),
+               addr + APB_DMA_IRQ_MASK_SET);
+
+        memset(channel_usage, 0, sizeof(channel_usage));
+        memset(dma_channels, 0, sizeof(dma_channels));
+
+        /* Reserve all the channels we are not supposed to touch */
+        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_MIN; i++)
+                __set_bit(i, channel_usage);
+
+        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
+                struct tegra_dma_channel *ch = &dma_channels[i];
+
+                __clear_bit(i, channel_usage);
+
+                ch->id = i;
+                snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i);
+
+                ch->addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
+                        TEGRA_APB_DMA_CH0_SIZE * i);
+
+                spin_lock_init(&ch->lock);
+                INIT_LIST_HEAD(&ch->list);
+                tegra_dma_init_hw(ch);
+
+                irq = INT_APB_DMA_CH0 + i;
+                ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0,
+                        dma_channels[i].name, ch);
+                if (ret) {
+                        pr_err("Failed to register IRQ %d for DMA %d\n",
+                                irq, i);
+                        goto fail;
+                }
+                ch->irq = irq;
+        }
+        /* mark the shared channel allocated */
+        __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage);
+
+        for (i = TEGRA_SYSTEM_DMA_CH_MAX+1; i < NV_DMA_MAX_CHANNELS; i++)
+                __set_bit(i, channel_usage);
+
+        return ret;
+fail:
+        writel(0, addr + APB_DMA_GEN);
+        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
+                struct tegra_dma_channel *ch = &dma_channels[i];
+                if (ch->irq)
+                        free_irq(ch->irq, ch);
+        }
+        return ret;
+}
+
+#ifdef CONFIG_PM
+static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3];
+
+void tegra_dma_suspend(void)
+{
+        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
+        u32 *ctx = apb_dma;
+        int i;
+
+        *ctx++ = readl(addr + APB_DMA_GEN);
+        *ctx++ = readl(addr + APB_DMA_CNTRL);
+        *ctx++ = readl(addr + APB_DMA_IRQ_MASK);
+
+        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
+                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
+                                  TEGRA_APB_DMA_CH0_SIZE * i);
+
+                *ctx++ = readl(addr + APB_DMA_CHAN_CSR);
+                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_PTR);
+                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_SEQ);
+                *ctx++ = readl(addr + APB_DMA_CHAN_APB_PTR);
+                *ctx++ = readl(addr + APB_DMA_CHAN_APB_SEQ);
+        }
+}
+
+void tegra_dma_resume(void)
+{
+        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
+        u32 *ctx = apb_dma;
+        int i;
+
+        writel(*ctx++, addr + APB_DMA_GEN);
+        writel(*ctx++, addr + APB_DMA_CNTRL);
+        writel(*ctx++, addr + APB_DMA_IRQ_MASK);
+
+        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
+                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
+                                  TEGRA_APB_DMA_CH0_SIZE * i);
+
+                writel(*ctx++, addr + APB_DMA_CHAN_CSR);
+                writel(*ctx++, addr + APB_DMA_CHAN_AHB_PTR);
+                writel(*ctx++, addr + APB_DMA_CHAN_AHB_SEQ);
+                writel(*ctx++, addr + APB_DMA_CHAN_APB_PTR);
+                writel(*ctx++, addr + APB_DMA_CHAN_APB_SEQ);
+        }
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
new file mode 100644
index 00000000000..1fa26d9a1a6
--- /dev/null
+++ b/arch/arm/mach-tegra/fuse.c
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/mach-tegra/fuse.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+
+#include "fuse.h"
+
+#define FUSE_UID_LOW            0x108
+#define FUSE_UID_HIGH           0x10c
+#define FUSE_SKU_INFO           0x110
+#define FUSE_SPARE_BIT          0x200
+
+static inline u32 fuse_readl(unsigned long offset)
+{
+        return readl(IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
+}
+
+static inline void fuse_writel(u32 value, unsigned long offset)
+{
+        writel(value, IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
+}
+
+void tegra_init_fuse(void)
+{
+        u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+        reg |= 1 << 28;
+        writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+
+        pr_info("Tegra SKU: %d CPU Process: %d Core Process: %d\n",
+                tegra_sku_id(), tegra_cpu_process_id(),
+                tegra_core_process_id());
+}
+
+unsigned long long tegra_chip_uid(void)
+{
+        unsigned long long lo, hi;
+
+        lo = fuse_readl(FUSE_UID_LOW);
+        hi = fuse_readl(FUSE_UID_HIGH);
+        return (hi << 32ull) | lo;
+}
+
+int tegra_sku_id(void)
+{
+        int sku_id;
+        u32 reg = fuse_readl(FUSE_SKU_INFO);
+        sku_id = reg & 0xFF;
+        return sku_id;
+}
+
+int tegra_cpu_process_id(void)
+{
+        int cpu_process_id;
+        u32 reg = fuse_readl(FUSE_SPARE_BIT);
+        cpu_process_id = (reg >> 6) & 3;
+        return cpu_process_id;
+}
+
+int tegra_core_process_id(void)
+{
+        int core_process_id;
+        u32 reg = fuse_readl(FUSE_SPARE_BIT);
+        core_process_id = (reg >> 12) & 3;
+        return core_process_id;
+}
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
new file mode 100644
index 00000000000..584b2e27dbd
--- /dev/null
+++ b/arch/arm/mach-tegra/fuse.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-tegra/fuse.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+unsigned long long tegra_chip_uid(void);
+int tegra_sku_id(void);
+int tegra_cpu_process_id(void);
+int tegra_core_process_id(void);
+void tegra_init_fuse(void);
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index fe78fba25f3..0775265e69f 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -19,6 +19,7 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
 
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -60,6 +61,13 @@ struct tegra_gpio_bank {
         int bank;
         int irq;
         spinlock_t lvl_lock[4];
+#ifdef CONFIG_PM
+        u32 cnf[4];
+        u32 out[4];
+        u32 oe[4];
+        u32 int_enb[4];
+        u32 int_lvl[4];
+#endif
 };
 
 
@@ -131,7 +139,7 @@ static struct gpio_chip tegra_gpio_chip = {
         .direction_output       = tegra_gpio_direction_output,
         .set                    = tegra_gpio_set,
         .base                   = 0,
-        .ngpio                  = ARCH_NR_GPIOS,
+        .ngpio                  = TEGRA_NR_GPIOS,
 };
 
 static void tegra_gpio_irq_ack(unsigned int irq)
@@ -244,6 +252,76 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 }
 
+#ifdef CONFIG_PM
+void tegra_gpio_resume(void)
+{
+        unsigned long flags;
+        int b, p, i;
+
+        local_irq_save(flags);
+
+        for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
+                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
+
+                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
+                        unsigned int gpio = (b<<5) | (p<<3);
+                        __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
+                        __raw_writel(bank->out[p], GPIO_OUT(gpio));
+                        __raw_writel(bank->oe[p], GPIO_OE(gpio));
+                        __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
+                        __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
+                }
+        }
+
+        local_irq_restore(flags);
+
+        for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
+                struct irq_desc *desc = irq_to_desc(i);
+                if (!desc || (desc->status & IRQ_WAKEUP))
+                        continue;
+                enable_irq(i);
+        }
+}
+
+void tegra_gpio_suspend(void)
+{
+        unsigned long flags;
+        int b, p, i;
+
+        for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
+                struct irq_desc *desc = irq_to_desc(i);
+                if (!desc)
+                        continue;
+                if (desc->status & IRQ_WAKEUP) {
+                        int gpio = i - INT_GPIO_BASE;
+                        pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7);
+                        continue;
+                }
+                disable_irq(i);
+        }
+
+        local_irq_save(flags);
+        for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
+                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
+
+                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
+                        unsigned int gpio = (b<<5) | (p<<3);
+                        bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
+                        bank->out[p] = __raw_readl(GPIO_OUT(gpio));
+                        bank->oe[p] = __raw_readl(GPIO_OE(gpio));
+                        bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
+                        bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
+                }
+        }
+        local_irq_restore(flags);
+}
+
+static int tegra_gpio_wake_enable(unsigned int irq, unsigned int enable)
+{
+        struct tegra_gpio_bank *bank = get_irq_chip_data(irq);
+        return set_irq_wake(bank->irq, enable);
+}
+#endif
 
 static struct irq_chip tegra_gpio_irq_chip = {
         .name           = "GPIO",
@@ -251,6 +329,9 @@ static struct irq_chip tegra_gpio_irq_chip = {
         .mask           = tegra_gpio_irq_mask,
         .unmask         = tegra_gpio_irq_unmask,
         .set_type       = tegra_gpio_irq_set_type,
+#ifdef CONFIG_PM
+        .set_wake       = tegra_gpio_wake_enable,
+#endif
 };
 
 
@@ -274,7 +355,7 @@ static int __init tegra_gpio_init(void)
 
         gpiochip_add(&tegra_gpio_chip);
 
-        for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + ARCH_NR_GPIOS); i++) {
+        for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
                 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
 
                 lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class);
@@ -312,15 +393,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
         for (i = 0; i < 7; i++) {
                 for (j = 0; j < 4; j++) {
                         int gpio = tegra_gpio_compose(i, j, 0);
-                        seq_printf(s, "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
-                               i, j,
-                               __raw_readl(GPIO_CNF(gpio)),
-                               __raw_readl(GPIO_OE(gpio)),
-                               __raw_readl(GPIO_OUT(gpio)),
-                               __raw_readl(GPIO_IN(gpio)),
-                               __raw_readl(GPIO_INT_STA(gpio)),
-                               __raw_readl(GPIO_INT_ENB(gpio)),
-                               __raw_readl(GPIO_INT_LVL(gpio)));
+                        seq_printf(s,
+                                "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
+                                i, j,
+                                __raw_readl(GPIO_CNF(gpio)),
+                                __raw_readl(GPIO_OE(gpio)),
+                                __raw_readl(GPIO_OUT(gpio)),
+                                __raw_readl(GPIO_IN(gpio)),
+                                __raw_readl(GPIO_INT_STA(gpio)),
+                                __raw_readl(GPIO_INT_ENB(gpio)),
+                                __raw_readl(GPIO_INT_LVL(gpio)));
                 }
         }
         return 0;
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index 2896f25ebfb..d7723955dac 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -23,4 +23,9 @@
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
+int clk_enable_cansleep(struct clk *clk);
+void clk_disable_cansleep(struct clk *clk);
+int clk_set_rate_cansleep(struct clk *clk, unsigned long rate);
+int clk_set_parent_cansleep(struct clk *clk, struct clk *parent);
+
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 55a39564b43..8ea3bffb4e0 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -20,24 +20,28 @@
 
 #include <mach/io.h>
 
-        .macro  addruart,rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                 @ MMU enabled?
-        ldreq   \rx, =IO_APB_PHYS       @ physical
-        ldrne   \rx, =IO_APB_VIRT        @ virtual
+        .macro  addruart, rp, rv
+        ldreq   \rp, =IO_APB_PHYS       @ physical
+        ldrne   \rv, =IO_APB_VIRT        @ virtual
 #if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
 #error "A debug UART must be selected in the kernel config to use DEBUG_LL"
 #elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-        orr     \rx, \rx, #0x6000
+        orr     \rp, \rp, #0x6000
+        orr     \rv, \rv, #0x6000
 #elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-        ldr     \tmp, =0x6040
-        orr     \rx, \rx, \tmp
+        orr     \rp, \rp, #0x6000
+        orr     \rp, \rp, #0x40
+        orr     \rv, \rv, #0x6000
+        orr     \rv, \rv, #0x40
 #elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-        orr     \rx, \rx, #0x6200
+        orr     \rp, \rp, #0x6200
+        orr     \rv, \rv, #0x6200
 #elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-        orr     \rx, \rx, #0x6300
+        orr     \rp, \rp, #0x6300
+        orr     \rv, \rv, #0x6300
 #elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-        orr     \rx, \rx, #0x6400
+        orr     \rp, \rp, #0x6400
+        orr     \rv, \rv, #0x6400
 #endif
         .endm
 
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
new file mode 100644
index 00000000000..39011bd9a92
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -0,0 +1,155 @@
+/*
+ * arch/arm/mach-tegra/include/mach/dma.h
+ *
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_DMA_H
+#define __MACH_TEGRA_DMA_H
+
+#include <linux/list.h>
+
+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
+
+struct tegra_dma_req;
+struct tegra_dma_channel;
+
+#define TEGRA_DMA_REQ_SEL_CNTR                  0
+#define TEGRA_DMA_REQ_SEL_I2S_2                 1
+#define TEGRA_DMA_REQ_SEL_I2S_1                 2
+#define TEGRA_DMA_REQ_SEL_SPD_I                 3
+#define TEGRA_DMA_REQ_SEL_UI_I                  4
+#define TEGRA_DMA_REQ_SEL_MIPI                  5
+#define TEGRA_DMA_REQ_SEL_I2S2_2                6
+#define TEGRA_DMA_REQ_SEL_I2S2_1                7
+#define TEGRA_DMA_REQ_SEL_UARTA                 8
+#define TEGRA_DMA_REQ_SEL_UARTB                 9
+#define TEGRA_DMA_REQ_SEL_UARTC                 10
+#define TEGRA_DMA_REQ_SEL_SPI                   11
+#define TEGRA_DMA_REQ_SEL_AC97                  12
+#define TEGRA_DMA_REQ_SEL_ACMODEM               13
+#define TEGRA_DMA_REQ_SEL_SL4B                  14
+#define TEGRA_DMA_REQ_SEL_SL2B1                 15
+#define TEGRA_DMA_REQ_SEL_SL2B2                 16
+#define TEGRA_DMA_REQ_SEL_SL2B3                 17
+#define TEGRA_DMA_REQ_SEL_SL2B4                 18
+#define TEGRA_DMA_REQ_SEL_UARTD                 19
+#define TEGRA_DMA_REQ_SEL_UARTE                 20
+#define TEGRA_DMA_REQ_SEL_I2C                   21
+#define TEGRA_DMA_REQ_SEL_I2C2                  22
+#define TEGRA_DMA_REQ_SEL_I2C3                  23
+#define TEGRA_DMA_REQ_SEL_DVC_I2C               24
+#define TEGRA_DMA_REQ_SEL_OWR                   25
+#define TEGRA_DMA_REQ_SEL_INVALID               31
+
+enum tegra_dma_mode {
+        TEGRA_DMA_SHARED = 1,
+        TEGRA_DMA_MODE_CONTINOUS = 2,
+        TEGRA_DMA_MODE_ONESHOT = 4,
+};
+
+enum tegra_dma_req_error {
+        TEGRA_DMA_REQ_SUCCESS = 0,
+        TEGRA_DMA_REQ_ERROR_ABORTED,
+        TEGRA_DMA_REQ_INFLIGHT,
+};
+
+enum tegra_dma_req_buff_status {
+        TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
+        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
+        TEGRA_DMA_REQ_BUF_STATUS_FULL,
+};
+
+struct tegra_dma_req {
+        struct list_head node;
+        unsigned int modid;
+        int instance;
+
+        /* Called when the req is complete and from the DMA ISR context.
+         * When this is called the req structure is no longer queued by
+         * the DMA channel.
+         *
+         * State of the DMA depends on the number of req it has. If there are
+         * no DMA requests queued up, then it will STOP the DMA. It there are
+         * more requests in the DMA, then it will queue the next request.
+         */
+        void (*complete)(struct tegra_dma_req *req);
+
+        /*  This is a called from the DMA ISR context when the DMA is still in
+         *  progress and is actively filling same buffer.
+         *
+         *  In case of continous mode receive, this threshold is 1/2 the buffer
+         *  size. In other cases, this will not even be called as there is no
+         *  hardware support for it.
+         *
+         * In the case of continous mode receive, if there is next req already
+         * queued, DMA programs the HW to use that req when this req is
+         * completed. If there is no "next req" queued, then DMA ISR doesn't do
+         * anything before calling this callback.
+         *
+         *      This is mainly used by the cases, where the clients has queued
+         *      only one req and want to get some sort of DMA threshold
+         *      callback to program the next buffer.
+         *
+         */
+        void (*threshold)(struct tegra_dma_req *req);
+
+        /* 1 to copy to memory.
+         * 0 to copy from the memory to device FIFO */
+        int to_memory;
+
+        void *virt_addr;
+
+        unsigned long source_addr;
+        unsigned long dest_addr;
+        unsigned long dest_wrap;
+        unsigned long source_wrap;
+        unsigned long source_bus_width;
+        unsigned long dest_bus_width;
+        unsigned long req_sel;
+        unsigned int size;
+
+        /* Updated by the DMA driver on the conpletion of the request. */
+        int bytes_transferred;
+        int status;
+
+        /* DMA completion tracking information */
+        int buffer_status;
+
+        /* Client specific data */
+        void *dev;
+};
+
+int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+void tegra_dma_dequeue(struct tegra_dma_channel *ch);
+void tegra_dma_flush(struct tegra_dma_channel *ch);
+
+bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
+
+struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
+void tegra_dma_free_channel(struct tegra_dma_channel *ch);
+
+int __init tegra_dma_init(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
index 540e822e50f..e31f486d69a 100644
--- a/arch/arm/mach-tegra/include/mach/gpio.h
+++ b/arch/arm/mach-tegra/include/mach/gpio.h
@@ -22,7 +22,7 @@
 
 #include <mach/irqs.h>
 
-#define ARCH_NR_GPIOS           INT_GPIO_NR
+#define TEGRA_NR_GPIOS          INT_GPIO_NR
 
 #include <asm-generic/gpio.h>
 
@@ -35,7 +35,7 @@
 
 static inline int gpio_to_irq(unsigned int gpio)
 {
-        if (gpio < ARCH_NR_GPIOS)
+        if (gpio < TEGRA_NR_GPIOS)
                 return INT_GPIO_BASE + gpio;
         return -EINVAL;
 }
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
index 6014edf60d9..56e43b3a5b9 100644
--- a/arch/arm/mach-tegra/include/mach/hardware.h
+++ b/arch/arm/mach-tegra/include/mach/hardware.h
@@ -21,4 +21,8 @@
 #ifndef __MACH_TEGRA_HARDWARE_H
 #define __MACH_TEGRA_HARDWARE_H
 
+#define PCIBIOS_MIN_IO                  0x1000
+#define PCIBIOS_MIN_MEM                 0
+#define pcibios_assign_all_busses()     1
+
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 35edfc32ffc..f0981b1ac59 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -21,7 +21,7 @@
 #ifndef __MACH_TEGRA_IO_H
 #define __MACH_TEGRA_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#define IO_SPACE_LIMIT 0xffff
 
 /* On TEGRA, many peripherals are very closely packed in
  * two 256MB io windows (that actually only use about 64KB
@@ -33,6 +33,10 @@
  *
  */
 
+#define IO_IRAM_PHYS    0x40000000
+#define IO_IRAM_VIRT    0xFE400000
+#define IO_IRAM_SIZE    SZ_256K
+
 #define IO_CPU_PHYS     0x50040000
 #define IO_CPU_VIRT     0xFE000000
 #define IO_CPU_SIZE     SZ_16K
@@ -55,6 +59,8 @@
                 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :       \
         IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?             \
                 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :       \
+        IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?           \
+                IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :     \
         0)
 
 #ifndef __ASSEMBLER__
@@ -67,10 +73,20 @@ void tegra_iounmap(volatile void __iomem *addr);
 
 #define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
 
+#ifdef CONFIG_TEGRA_PCI
+extern void __iomem *tegra_pcie_io_base;
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
+}
+#else
 static inline void __iomem *__io(unsigned long addr)
 {
         return (void __iomem *)addr;
 }
+#endif
+
 #define __io(a)         __io(a)
 #define __mem_pci(a)    (a)
 
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 1741f7dd7a9..44a4f4bcf91 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -23,9 +23,15 @@
 
 #include <asm/sizes.h>
 
+#define TEGRA_IRAM_BASE                 0x40000000
+#define TEGRA_IRAM_SIZE                 SZ_256K
+
 #define TEGRA_ARM_PERIF_BASE            0x50040000
 #define TEGRA_ARM_PERIF_SIZE            SZ_8K
 
+#define TEGRA_ARM_PL310_BASE            0x50043000
+#define TEGRA_ARM_PL310_SIZE            SZ_4K
+
 #define TEGRA_ARM_INT_DIST_BASE         0x50041000
 #define TEGRA_ARM_INT_DIST_SIZE         SZ_4K
 
@@ -68,7 +74,22 @@
 #define TEGRA_FLOW_CTRL_BASE            0x60007000
 #define TEGRA_FLOW_CTRL_SIZE            20
 
-#define TEGRA_STATMON_BASE              0x6000C4000
+#define TEGRA_AHB_DMA_BASE              0x60008000
+#define TEGRA_AHB_DMA_SIZE              SZ_4K
+
+#define TEGRA_AHB_DMA_CH0_BASE          0x60009000
+#define TEGRA_AHB_DMA_CH0_SIZE          32
+
+#define TEGRA_APB_DMA_BASE              0x6000A000
+#define TEGRA_APB_DMA_SIZE              SZ_4K
+
+#define TEGRA_APB_DMA_CH0_BASE          0x6000B000
+#define TEGRA_APB_DMA_CH0_SIZE          32
+
+#define TEGRA_AHB_GIZMO_BASE            0x6000C004
+#define TEGRA_AHB_GIZMO_SIZE            0x10C
+
+#define TEGRA_STATMON_BASE              0x6000C400
 #define TEGRA_STATMON_SIZE              SZ_1K
 
 #define TEGRA_GPIO_BASE                 0x6000D000
@@ -137,7 +158,7 @@
 #define TEGRA_I2C3_BASE                 0x7000C500
 #define TEGRA_I2C3_SIZE                 SZ_256
 
-#define TEGRA_OWR_BASE                  0x7000D000
+#define TEGRA_OWR_BASE                  0x7000C600
 #define TEGRA_OWR_SIZE                  80
 
 #define TEGRA_DVC_BASE                  0x7000D000
@@ -182,12 +203,12 @@
 #define TEGRA_USB_BASE                  0xC5000000
 #define TEGRA_USB_SIZE                  SZ_16K
 
-#define TEGRA_USB1_BASE                 0xC5004000
-#define TEGRA_USB1_SIZE                 SZ_16K
-
-#define TEGRA_USB2_BASE                 0xC5008000
+#define TEGRA_USB2_BASE                 0xC5004000
 #define TEGRA_USB2_SIZE                 SZ_16K
 
+#define TEGRA_USB3_BASE                 0xC5008000
+#define TEGRA_USB3_SIZE                 SZ_16K
+
 #define TEGRA_SDMMC1_BASE               0xC8000000
 #define TEGRA_SDMMC1_SIZE               SZ_512
 
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index 20f640edaa0..71bbf342295 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -25,6 +25,7 @@
 
 #define IRQ_LOCALTIMER                  29
 
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 /* Primary Interrupt Controller */
 #define INT_PRI_BASE                    (INT_GIC_BASE + 32)
 #define INT_TMR1                        (INT_PRI_BASE + 0)
@@ -169,5 +170,6 @@
 #define INT_GPIO_NR                     (28 * 8)
 
 #define NR_IRQS                         (INT_GPIO_BASE + INT_GPIO_NR)
+#endif
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
new file mode 100644
index 00000000000..db1eb3dd04c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-tegra/include/mach/legacy_irq.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
+#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
+
+void tegra_legacy_mask_irq(unsigned int irq);
+void tegra_legacy_unmask_irq(unsigned int irq);
+void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
+void tegra_legacy_force_irq_set(unsigned int irq);
+void tegra_legacy_force_irq_clr(unsigned int irq);
+int tegra_legacy_force_irq_status(unsigned int irq);
+void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
+unsigned long tegra_legacy_vfiq(int nr);
+unsigned long tegra_legacy_class(int nr);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
new file mode 100644
index 00000000000..e5b9d740f97
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
@@ -0,0 +1,174 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_T2_H
+#define __MACH_TEGRA_PINMUX_T2_H
+
+enum tegra_pingroup {
+        TEGRA_PINGROUP_ATA = 0,
+        TEGRA_PINGROUP_ATB,
+        TEGRA_PINGROUP_ATC,
+        TEGRA_PINGROUP_ATD,
+        TEGRA_PINGROUP_ATE,
+        TEGRA_PINGROUP_CDEV1,
+        TEGRA_PINGROUP_CDEV2,
+        TEGRA_PINGROUP_CRTP,
+        TEGRA_PINGROUP_CSUS,
+        TEGRA_PINGROUP_DAP1,
+        TEGRA_PINGROUP_DAP2,
+        TEGRA_PINGROUP_DAP3,
+        TEGRA_PINGROUP_DAP4,
+        TEGRA_PINGROUP_DDC,
+        TEGRA_PINGROUP_DTA,
+        TEGRA_PINGROUP_DTB,
+        TEGRA_PINGROUP_DTC,
+        TEGRA_PINGROUP_DTD,
+        TEGRA_PINGROUP_DTE,
+        TEGRA_PINGROUP_DTF,
+        TEGRA_PINGROUP_GMA,
+        TEGRA_PINGROUP_GMB,
+        TEGRA_PINGROUP_GMC,
+        TEGRA_PINGROUP_GMD,
+        TEGRA_PINGROUP_GME,
+        TEGRA_PINGROUP_GPU,
+        TEGRA_PINGROUP_GPU7,
+        TEGRA_PINGROUP_GPV,
+        TEGRA_PINGROUP_HDINT,
+        TEGRA_PINGROUP_I2CP,
+        TEGRA_PINGROUP_IRRX,
+        TEGRA_PINGROUP_IRTX,
+        TEGRA_PINGROUP_KBCA,
+        TEGRA_PINGROUP_KBCB,
+        TEGRA_PINGROUP_KBCC,
+        TEGRA_PINGROUP_KBCD,
+        TEGRA_PINGROUP_KBCE,
+        TEGRA_PINGROUP_KBCF,
+        TEGRA_PINGROUP_LCSN,
+        TEGRA_PINGROUP_LD0,
+        TEGRA_PINGROUP_LD1,
+        TEGRA_PINGROUP_LD10,
+        TEGRA_PINGROUP_LD11,
+        TEGRA_PINGROUP_LD12,
+        TEGRA_PINGROUP_LD13,
+        TEGRA_PINGROUP_LD14,
+        TEGRA_PINGROUP_LD15,
+        TEGRA_PINGROUP_LD16,
+        TEGRA_PINGROUP_LD17,
+        TEGRA_PINGROUP_LD2,
+        TEGRA_PINGROUP_LD3,
+        TEGRA_PINGROUP_LD4,
+        TEGRA_PINGROUP_LD5,
+        TEGRA_PINGROUP_LD6,
+        TEGRA_PINGROUP_LD7,
+        TEGRA_PINGROUP_LD8,
+        TEGRA_PINGROUP_LD9,
+        TEGRA_PINGROUP_LDC,
+        TEGRA_PINGROUP_LDI,
+        TEGRA_PINGROUP_LHP0,
+        TEGRA_PINGROUP_LHP1,
+        TEGRA_PINGROUP_LHP2,
+        TEGRA_PINGROUP_LHS,
+        TEGRA_PINGROUP_LM0,
+        TEGRA_PINGROUP_LM1,
+        TEGRA_PINGROUP_LPP,
+        TEGRA_PINGROUP_LPW0,
+        TEGRA_PINGROUP_LPW1,
+        TEGRA_PINGROUP_LPW2,
+        TEGRA_PINGROUP_LSC0,
+        TEGRA_PINGROUP_LSC1,
+        TEGRA_PINGROUP_LSCK,
+        TEGRA_PINGROUP_LSDA,
+        TEGRA_PINGROUP_LSDI,
+        TEGRA_PINGROUP_LSPI,
+        TEGRA_PINGROUP_LVP0,
+        TEGRA_PINGROUP_LVP1,
+        TEGRA_PINGROUP_LVS,
+        TEGRA_PINGROUP_OWC,
+        TEGRA_PINGROUP_PMC,
+        TEGRA_PINGROUP_PTA,
+        TEGRA_PINGROUP_RM,
+        TEGRA_PINGROUP_SDB,
+        TEGRA_PINGROUP_SDC,
+        TEGRA_PINGROUP_SDD,
+        TEGRA_PINGROUP_SDIO1,
+        TEGRA_PINGROUP_SLXA,
+        TEGRA_PINGROUP_SLXC,
+        TEGRA_PINGROUP_SLXD,
+        TEGRA_PINGROUP_SLXK,
+        TEGRA_PINGROUP_SPDI,
+        TEGRA_PINGROUP_SPDO,
+        TEGRA_PINGROUP_SPIA,
+        TEGRA_PINGROUP_SPIB,
+        TEGRA_PINGROUP_SPIC,
+        TEGRA_PINGROUP_SPID,
+        TEGRA_PINGROUP_SPIE,
+        TEGRA_PINGROUP_SPIF,
+        TEGRA_PINGROUP_SPIG,
+        TEGRA_PINGROUP_SPIH,
+        TEGRA_PINGROUP_UAA,
+        TEGRA_PINGROUP_UAB,
+        TEGRA_PINGROUP_UAC,
+        TEGRA_PINGROUP_UAD,
+        TEGRA_PINGROUP_UCA,
+        TEGRA_PINGROUP_UCB,
+        TEGRA_PINGROUP_UDA,
+        /* these pin groups only have pullup and pull down control */
+        TEGRA_PINGROUP_CK32,
+        TEGRA_PINGROUP_DDRC,
+        TEGRA_PINGROUP_PMCA,
+        TEGRA_PINGROUP_PMCB,
+        TEGRA_PINGROUP_PMCC,
+        TEGRA_PINGROUP_PMCD,
+        TEGRA_PINGROUP_PMCE,
+        TEGRA_PINGROUP_XM2C,
+        TEGRA_PINGROUP_XM2D,
+        TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_drive_pingroup {
+        TEGRA_DRIVE_PINGROUP_AO1 = 0,
+        TEGRA_DRIVE_PINGROUP_AO2,
+        TEGRA_DRIVE_PINGROUP_AT1,
+        TEGRA_DRIVE_PINGROUP_AT2,
+        TEGRA_DRIVE_PINGROUP_CDEV1,
+        TEGRA_DRIVE_PINGROUP_CDEV2,
+        TEGRA_DRIVE_PINGROUP_CSUS,
+        TEGRA_DRIVE_PINGROUP_DAP1,
+        TEGRA_DRIVE_PINGROUP_DAP2,
+        TEGRA_DRIVE_PINGROUP_DAP3,
+        TEGRA_DRIVE_PINGROUP_DAP4,
+        TEGRA_DRIVE_PINGROUP_DBG,
+        TEGRA_DRIVE_PINGROUP_LCD1,
+        TEGRA_DRIVE_PINGROUP_LCD2,
+        TEGRA_DRIVE_PINGROUP_SDMMC2,
+        TEGRA_DRIVE_PINGROUP_SDMMC3,
+        TEGRA_DRIVE_PINGROUP_SPI,
+        TEGRA_DRIVE_PINGROUP_UAA,
+        TEGRA_DRIVE_PINGROUP_UAB,
+        TEGRA_DRIVE_PINGROUP_UART2,
+        TEGRA_DRIVE_PINGROUP_UART3,
+        TEGRA_DRIVE_PINGROUP_VI1,
+        TEGRA_DRIVE_PINGROUP_VI2,
+        TEGRA_DRIVE_PINGROUP_XM2A,
+        TEGRA_DRIVE_PINGROUP_XM2C,
+        TEGRA_DRIVE_PINGROUP_XM2D,
+        TEGRA_DRIVE_PINGROUP_XM2CLK,
+        TEGRA_DRIVE_PINGROUP_MEMCOMP,
+        TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index 41c8ce5b7c2..defd8775def 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -17,126 +17,11 @@
 #ifndef __MACH_TEGRA_PINMUX_H
 #define __MACH_TEGRA_PINMUX_H
 
-enum tegra_pingroup {
-        TEGRA_PINGROUP_ATA = 0,
-        TEGRA_PINGROUP_ATB,
-        TEGRA_PINGROUP_ATC,
-        TEGRA_PINGROUP_ATD,
-        TEGRA_PINGROUP_ATE,
-        TEGRA_PINGROUP_CDEV1,
-        TEGRA_PINGROUP_CDEV2,
-        TEGRA_PINGROUP_CRTP,
-        TEGRA_PINGROUP_CSUS,
-        TEGRA_PINGROUP_DAP1,
-        TEGRA_PINGROUP_DAP2,
-        TEGRA_PINGROUP_DAP3,
-        TEGRA_PINGROUP_DAP4,
-        TEGRA_PINGROUP_DDC,
-        TEGRA_PINGROUP_DTA,
-        TEGRA_PINGROUP_DTB,
-        TEGRA_PINGROUP_DTC,
-        TEGRA_PINGROUP_DTD,
-        TEGRA_PINGROUP_DTE,
-        TEGRA_PINGROUP_DTF,
-        TEGRA_PINGROUP_GMA,
-        TEGRA_PINGROUP_GMB,
-        TEGRA_PINGROUP_GMC,
-        TEGRA_PINGROUP_GMD,
-        TEGRA_PINGROUP_GME,
-        TEGRA_PINGROUP_GPU,
-        TEGRA_PINGROUP_GPU7,
-        TEGRA_PINGROUP_GPV,
-        TEGRA_PINGROUP_HDINT,
-        TEGRA_PINGROUP_I2CP,
-        TEGRA_PINGROUP_IRRX,
-        TEGRA_PINGROUP_IRTX,
-        TEGRA_PINGROUP_KBCA,
-        TEGRA_PINGROUP_KBCB,
-        TEGRA_PINGROUP_KBCC,
-        TEGRA_PINGROUP_KBCD,
-        TEGRA_PINGROUP_KBCE,
-        TEGRA_PINGROUP_KBCF,
-        TEGRA_PINGROUP_LCSN,
-        TEGRA_PINGROUP_LD0,
-        TEGRA_PINGROUP_LD1,
-        TEGRA_PINGROUP_LD10,
-        TEGRA_PINGROUP_LD11,
-        TEGRA_PINGROUP_LD12,
-        TEGRA_PINGROUP_LD13,
-        TEGRA_PINGROUP_LD14,
-        TEGRA_PINGROUP_LD15,
-        TEGRA_PINGROUP_LD16,
-        TEGRA_PINGROUP_LD17,
-        TEGRA_PINGROUP_LD2,
-        TEGRA_PINGROUP_LD3,
-        TEGRA_PINGROUP_LD4,
-        TEGRA_PINGROUP_LD5,
-        TEGRA_PINGROUP_LD6,
-        TEGRA_PINGROUP_LD7,
-        TEGRA_PINGROUP_LD8,
-        TEGRA_PINGROUP_LD9,
-        TEGRA_PINGROUP_LDC,
-        TEGRA_PINGROUP_LDI,
-        TEGRA_PINGROUP_LHP0,
-        TEGRA_PINGROUP_LHP1,
-        TEGRA_PINGROUP_LHP2,
-        TEGRA_PINGROUP_LHS,
-        TEGRA_PINGROUP_LM0,
-        TEGRA_PINGROUP_LM1,
-        TEGRA_PINGROUP_LPP,
-        TEGRA_PINGROUP_LPW0,
-        TEGRA_PINGROUP_LPW1,
-        TEGRA_PINGROUP_LPW2,
-        TEGRA_PINGROUP_LSC0,
-        TEGRA_PINGROUP_LSC1,
-        TEGRA_PINGROUP_LSCK,
-        TEGRA_PINGROUP_LSDA,
-        TEGRA_PINGROUP_LSDI,
-        TEGRA_PINGROUP_LSPI,
-        TEGRA_PINGROUP_LVP0,
-        TEGRA_PINGROUP_LVP1,
-        TEGRA_PINGROUP_LVS,
-        TEGRA_PINGROUP_OWC,
-        TEGRA_PINGROUP_PMC,
-        TEGRA_PINGROUP_PTA,
-        TEGRA_PINGROUP_RM,
-        TEGRA_PINGROUP_SDB,
-        TEGRA_PINGROUP_SDC,
-        TEGRA_PINGROUP_SDD,
-        TEGRA_PINGROUP_SDIO1,
-        TEGRA_PINGROUP_SLXA,
-        TEGRA_PINGROUP_SLXC,
-        TEGRA_PINGROUP_SLXD,
-        TEGRA_PINGROUP_SLXK,
-        TEGRA_PINGROUP_SPDI,
-        TEGRA_PINGROUP_SPDO,
-        TEGRA_PINGROUP_SPIA,
-        TEGRA_PINGROUP_SPIB,
-        TEGRA_PINGROUP_SPIC,
-        TEGRA_PINGROUP_SPID,
-        TEGRA_PINGROUP_SPIE,
-        TEGRA_PINGROUP_SPIF,
-        TEGRA_PINGROUP_SPIG,
-        TEGRA_PINGROUP_SPIH,
-        TEGRA_PINGROUP_UAA,
-        TEGRA_PINGROUP_UAB,
-        TEGRA_PINGROUP_UAC,
-        TEGRA_PINGROUP_UAD,
-        TEGRA_PINGROUP_UCA,
-        TEGRA_PINGROUP_UCB,
-        TEGRA_PINGROUP_UDA,
-        /* these pin groups only have pullup and pull down control */
-        TEGRA_PINGROUP_CK32,
-        TEGRA_PINGROUP_DDRC,
-        TEGRA_PINGROUP_PMCA,
-        TEGRA_PINGROUP_PMCB,
-        TEGRA_PINGROUP_PMCC,
-        TEGRA_PINGROUP_PMCD,
-        TEGRA_PINGROUP_PMCE,
-        TEGRA_PINGROUP_XM2C,
-        TEGRA_PINGROUP_XM2D,
-        TEGRA_MAX_PINGROUP,
-};
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#include "pinmux-t2.h"
+#else
+#error "Undefined Tegra architecture"
+#endif
 
 enum tegra_mux_func {
         TEGRA_MUX_RSVD = 0x8000,
@@ -205,6 +90,7 @@ enum tegra_mux_func {
         TEGRA_MUX_VI,
         TEGRA_MUX_VI_SENSOR_CLK,
         TEGRA_MUX_XIO,
+        TEGRA_MUX_SAFE,
         TEGRA_MAX_MUX,
 };
 
@@ -219,6 +105,18 @@ enum tegra_tristate {
         TEGRA_TRI_TRISTATE = 1,
 };
 
+enum tegra_vddio {
+        TEGRA_VDDIO_BB = 0,
+        TEGRA_VDDIO_LCD,
+        TEGRA_VDDIO_VI,
+        TEGRA_VDDIO_UART,
+        TEGRA_VDDIO_DDR,
+        TEGRA_VDDIO_NAND,
+        TEGRA_VDDIO_SYS,
+        TEGRA_VDDIO_AUDIO,
+        TEGRA_VDDIO_SD,
+};
+
 struct tegra_pingroup_config {
         enum tegra_pingroup     pingroup;
         enum tegra_mux_func     func;
@@ -270,38 +168,6 @@ enum tegra_pull_strength {
         TEGRA_MAX_PULL,
 };
 
-enum tegra_drive_pingroup {
-        TEGRA_DRIVE_PINGROUP_AO1 = 0,
-        TEGRA_DRIVE_PINGROUP_AO2,
-        TEGRA_DRIVE_PINGROUP_AT1,
-        TEGRA_DRIVE_PINGROUP_AT2,
-        TEGRA_DRIVE_PINGROUP_CDEV1,
-        TEGRA_DRIVE_PINGROUP_CDEV2,
-        TEGRA_DRIVE_PINGROUP_CSUS,
-        TEGRA_DRIVE_PINGROUP_DAP1,
-        TEGRA_DRIVE_PINGROUP_DAP2,
-        TEGRA_DRIVE_PINGROUP_DAP3,
-        TEGRA_DRIVE_PINGROUP_DAP4,
-        TEGRA_DRIVE_PINGROUP_DBG,
-        TEGRA_DRIVE_PINGROUP_LCD1,
-        TEGRA_DRIVE_PINGROUP_LCD2,
-        TEGRA_DRIVE_PINGROUP_SDMMC2,
-        TEGRA_DRIVE_PINGROUP_SDMMC3,
-        TEGRA_DRIVE_PINGROUP_SPI,
-        TEGRA_DRIVE_PINGROUP_UAA,
-        TEGRA_DRIVE_PINGROUP_UAB,
-        TEGRA_DRIVE_PINGROUP_UART2,
-        TEGRA_DRIVE_PINGROUP_UART3,
-        TEGRA_DRIVE_PINGROUP_VI1,
-        TEGRA_DRIVE_PINGROUP_VI2,
-        TEGRA_DRIVE_PINGROUP_XM2A,
-        TEGRA_DRIVE_PINGROUP_XM2C,
-        TEGRA_DRIVE_PINGROUP_XM2D,
-        TEGRA_DRIVE_PINGROUP_XM2CLK,
-        TEGRA_DRIVE_PINGROUP_MEMCOMP,
-        TEGRA_MAX_DRIVE_PINGROUP,
-};
-
 enum tegra_drive {
         TEGRA_DRIVE_DIV_8 = 0,
         TEGRA_DRIVE_DIV_4,
@@ -331,18 +197,44 @@ struct tegra_drive_pingroup_config {
         enum tegra_slew slew_falling;
 };
 
-int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func);
-int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate);
-int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd);
+struct tegra_drive_pingroup_desc {
+        const char *name;
+        s16 reg;
+};
+
+struct tegra_pingroup_desc {
+        const char *name;
+        int funcs[4];
+        int func_safe;
+        int vddio;
+        s16 tri_reg;    /* offset into the TRISTATE_REG_* register bank */
+        s16 mux_reg;    /* offset into the PIN_MUX_CTL_* register bank */
+        s16 pupd_reg;   /* offset into the PULL_UPDOWN_REG_* register bank */
+        s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
+        s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
+        s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
+};
+
+extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
+extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
 
-void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
-        enum tegra_mux_func func, enum tegra_pullupdown pupd,
+int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
         enum tegra_tristate tristate);
+int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
+        enum tegra_pullupdown pupd);
 
-void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len);
+void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
+        int len);
 
 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
         int len);
-
+void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
+        int len);
+void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
+        int len);
+void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
+        int len, enum tegra_tristate tristate);
+void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
+        int len, enum tegra_pullupdown pupd);
 #endif
 
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab79a7..e4a34a35a54 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()                 \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 9fe2c5c683d..31848a9592f 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -49,6 +49,12 @@ static struct map_desc tegra_io_desc[] __initdata = {
                 .length = IO_CPU_SIZE,
                 .type = MT_DEVICE,
         },
+        {
+                .virtual = IO_IRAM_VIRT,
+                .pfn = __phys_to_pfn(IO_IRAM_PHYS),
+                .length = IO_IRAM_SIZE,
+                .type = MT_DEVICE,
+        },
 };
 
 void __init tegra_map_common_io(void)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1fdbe708d43..50a8dfb9a0c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,6 +4,8 @@
  * Author:
  *      Colin Cross <ccross@google.com>
  *
+ * Copyright (C) 2010, NVIDIA Corporation
+ *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
@@ -27,8 +29,143 @@
 
 #include "board.h"
 
+#define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
+#define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
+#define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
+
+#define APBDMA_IRQ_STA_CPU  0x14
+#define APBDMA_IRQ_MASK_SET 0x20
+#define APBDMA_IRQ_MASK_CLR 0x24
+
+#define ICTLR_CPU_IER           0x20
+#define ICTLR_CPU_IER_SET       0x24
+#define ICTLR_CPU_IER_CLR       0x28
+#define ICTLR_CPU_IEP_CLASS     0x2c
+#define ICTLR_COP_IER           0x30
+#define ICTLR_COP_IER_SET       0x34
+#define ICTLR_COP_IER_CLR       0x38
+#define ICTLR_COP_IEP_CLASS     0x3c
+
+static void (*gic_mask_irq)(unsigned int irq);
+static void (*gic_unmask_irq)(unsigned int irq);
+
+#define irq_to_ictlr(irq) (((irq)-32) >> 5)
+static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE);
+#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100)
+
+static void tegra_mask(unsigned int irq)
+{
+        void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq));
+        gic_mask_irq(irq);
+        writel(1<<(irq&31), addr+ICTLR_CPU_IER_CLR);
+}
+
+static void tegra_unmask(unsigned int irq)
+{
+        void __iomem *addr = ictlr_to_virt(irq_to_ictlr(irq));
+        gic_unmask_irq(irq);
+        writel(1<<(irq&31), addr+ICTLR_CPU_IER_SET);
+}
+
+#ifdef CONFIG_PM
+
+static int tegra_set_wake(unsigned int irq, unsigned int on)
+{
+        return 0;
+}
+#endif
+
+static struct irq_chip tegra_irq = {
+        .name           = "PPI",
+        .mask           = tegra_mask,
+        .unmask         = tegra_unmask,
+#ifdef CONFIG_PM
+        .set_wake       = tegra_set_wake,
+#endif
+};
+
 void __init tegra_init_irq(void)
 {
+        struct irq_chip *gic;
+        unsigned int i;
+
+        for (i = 0; i < PPI_NR; i++) {
+                writel(~0, ictlr_to_virt(i) + ICTLR_CPU_IER_CLR);
+                writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS);
+        }
+
         gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29);
         gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+
+        gic = get_irq_chip(29);
+        gic_unmask_irq = gic->unmask;
+        gic_mask_irq = gic->mask;
+        tegra_irq.ack = gic->ack;
+#ifdef CONFIG_SMP
+        tegra_irq.set_affinity = gic->set_affinity;
+#endif
+
+        for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) {
+                set_irq_chip(i, &tegra_irq);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+}
+
+#ifdef CONFIG_PM
+static u32 cop_ier[PPI_NR];
+static u32 cpu_ier[PPI_NR];
+static u32 cpu_iep[PPI_NR];
+
+void tegra_irq_suspend(void)
+{
+        unsigned long flags;
+        int i;
+
+        for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) {
+                struct irq_desc *desc = irq_to_desc(i);
+                if (!desc)
+                        continue;
+                if (desc->status & IRQ_WAKEUP) {
+                        pr_debug("irq %d is wakeup\n", i);
+                        continue;
+                }
+                disable_irq(i);
+        }
+
+        local_irq_save(flags);
+        for (i = 0; i < PPI_NR; i++) {
+                void __iomem *ictlr = ictlr_to_virt(i);
+                cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
+                cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
+                cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
+                writel(~0, ictlr + ICTLR_COP_IER_CLR);
+        }
+        local_irq_restore(flags);
+}
+
+void tegra_irq_resume(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < PPI_NR; i++) {
+                void __iomem *ictlr = ictlr_to_virt(i);
+                writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
+                writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+                writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
+                writel(0, ictlr + ICTLR_COP_IEP_CLASS);
+                writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
+                writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
+        }
+        local_irq_restore(flags);
+
+        for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) {
+                struct irq_desc *desc = irq_to_desc(i);
+                if (!desc || (desc->status & IRQ_WAKEUP))
+                        continue;
+                enable_irq(i);
+        }
 }
+#endif
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
new file mode 100644
index 00000000000..7cc8601c19f
--- /dev/null
+++ b/arch/arm/mach-tegra/legacy_irq.c
@@ -0,0 +1,114 @@
+/*
+ * arch/arm/mach-tegra/legacy_irq.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <mach/iomap.h>
+#include <mach/legacy_irq.h>
+
+#define ICTLR_CPU_IER           0x20
+#define ICTLR_CPU_IER_SET       0x24
+#define ICTLR_CPU_IER_CLR       0x28
+#define ICTLR_CPU_IEP_CLASS     0x2C
+#define ICTLR_CPU_IEP_VFIQ      0x08
+#define ICTLR_CPU_IEP_FIR       0x14
+#define ICTLR_CPU_IEP_FIR_SET   0x18
+#define ICTLR_CPU_IEP_FIR_CLR   0x1c
+
+static void __iomem *ictlr_reg_base[] = {
+        IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+};
+
+/* When going into deep sleep, the CPU is powered down, taking the GIC with it
+   In order to wake, the wake interrupts need to be enabled in the legacy
+   interrupt controller. */
+void tegra_legacy_unmask_irq(unsigned int irq)
+{
+        void __iomem *base;
+        pr_debug("%s: %d\n", __func__, irq);
+
+        irq -= 32;
+        base = ictlr_reg_base[irq>>5];
+        writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
+}
+
+void tegra_legacy_mask_irq(unsigned int irq)
+{
+        void __iomem *base;
+        pr_debug("%s: %d\n", __func__, irq);
+
+        irq -= 32;
+        base = ictlr_reg_base[irq>>5];
+        writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
+}
+
+void tegra_legacy_force_irq_set(unsigned int irq)
+{
+        void __iomem *base;
+        pr_debug("%s: %d\n", __func__, irq);
+
+        irq -= 32;
+        base = ictlr_reg_base[irq>>5];
+        writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
+}
+
+void tegra_legacy_force_irq_clr(unsigned int irq)
+{
+        void __iomem *base;
+        pr_debug("%s: %d\n", __func__, irq);
+
+        irq -= 32;
+        base = ictlr_reg_base[irq>>5];
+        writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
+}
+
+int tegra_legacy_force_irq_status(unsigned int irq)
+{
+        void __iomem *base;
+        pr_debug("%s: %d\n", __func__, irq);
+
+        irq -= 32;
+        base = ictlr_reg_base[irq>>5];
+        return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
+}
+
+void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
+{
+        void __iomem *base;
+        pr_debug("%s: %d\n", __func__, irq);
+
+        irq -= 32;
+        base = ictlr_reg_base[irq>>5];
+        writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
+}
+
+unsigned long tegra_legacy_vfiq(int nr)
+{
+        void __iomem *base;
+        base = ictlr_reg_base[nr];
+        return readl(base + ICTLR_CPU_IEP_VFIQ);
+}
+
+unsigned long tegra_legacy_class(int nr)
+{
+        void __iomem *base;
+        base = ictlr_reg_base[nr];
+        return readl(base + ICTLR_CPU_IEP_CLASS);
+}
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
new file mode 100644
index 00000000000..53f5fa37014
--- /dev/null
+++ b/arch/arm/mach-tegra/pcie.c
@@ -0,0 +1,915 @@
+/*
+ * arch/arm/mach-tegra/pci.c
+ *
+ * PCIe host controller driver for TEGRA(2) SOCs
+ *
+ * Copyright (c) 2010, CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on NVIDIA PCIe driver
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * Bits taken from arch/arm/mach-dove/pcie.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include <asm/sizes.h>
+#include <asm/mach/pci.h>
+
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/clk.h>
+
+/* register definitions */
+#define AFI_OFFSET      0x3800
+#define PADS_OFFSET     0x3000
+#define RP0_OFFSET      0x0000
+#define RP1_OFFSET      0x1000
+
+#define AFI_AXI_BAR0_SZ 0x00
+#define AFI_AXI_BAR1_SZ 0x04
+#define AFI_AXI_BAR2_SZ 0x08
+#define AFI_AXI_BAR3_SZ 0x0c
+#define AFI_AXI_BAR4_SZ 0x10
+#define AFI_AXI_BAR5_SZ 0x14
+
+#define AFI_AXI_BAR0_START      0x18
+#define AFI_AXI_BAR1_START      0x1c
+#define AFI_AXI_BAR2_START      0x20
+#define AFI_AXI_BAR3_START      0x24
+#define AFI_AXI_BAR4_START      0x28
+#define AFI_AXI_BAR5_START      0x2c
+
+#define AFI_FPCI_BAR0   0x30
+#define AFI_FPCI_BAR1   0x34
+#define AFI_FPCI_BAR2   0x38
+#define AFI_FPCI_BAR3   0x3c
+#define AFI_FPCI_BAR4   0x40
+#define AFI_FPCI_BAR5   0x44
+
+#define AFI_CACHE_BAR0_SZ       0x48
+#define AFI_CACHE_BAR0_ST       0x4c
+#define AFI_CACHE_BAR1_SZ       0x50
+#define AFI_CACHE_BAR1_ST       0x54
+
+#define AFI_MSI_BAR_SZ          0x60
+#define AFI_MSI_FPCI_BAR_ST     0x64
+#define AFI_MSI_AXI_BAR_ST      0x68
+
+#define AFI_CONFIGURATION               0xac
+#define  AFI_CONFIGURATION_EN_FPCI      (1 << 0)
+
+#define AFI_FPCI_ERROR_MASKS    0xb0
+
+#define AFI_INTR_MASK           0xb4
+#define  AFI_INTR_MASK_INT_MASK (1 << 0)
+#define  AFI_INTR_MASK_MSI_MASK (1 << 8)
+
+#define AFI_INTR_CODE           0xb8
+#define  AFI_INTR_CODE_MASK     0xf
+#define  AFI_INTR_MASTER_ABORT  4
+#define  AFI_INTR_LEGACY        6
+
+#define AFI_INTR_SIGNATURE      0xbc
+#define AFI_SM_INTR_ENABLE      0xc4
+
+#define AFI_AFI_INTR_ENABLE             0xc8
+#define  AFI_INTR_EN_INI_SLVERR         (1 << 0)
+#define  AFI_INTR_EN_INI_DECERR         (1 << 1)
+#define  AFI_INTR_EN_TGT_SLVERR         (1 << 2)
+#define  AFI_INTR_EN_TGT_DECERR         (1 << 3)
+#define  AFI_INTR_EN_TGT_WRERR          (1 << 4)
+#define  AFI_INTR_EN_DFPCI_DECERR       (1 << 5)
+#define  AFI_INTR_EN_AXI_DECERR         (1 << 6)
+#define  AFI_INTR_EN_FPCI_TIMEOUT       (1 << 7)
+
+#define AFI_PCIE_CONFIG                                 0x0f8
+#define  AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE          (1 << 1)
+#define  AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE          (1 << 2)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK       (0xf << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE     (0x0 << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL       (0x1 << 20)
+
+#define AFI_FUSE                        0x104
+#define  AFI_FUSE_PCIE_T0_GEN2_DIS      (1 << 2)
+
+#define AFI_PEX0_CTRL                   0x110
+#define AFI_PEX1_CTRL                   0x118
+#define  AFI_PEX_CTRL_RST               (1 << 0)
+#define  AFI_PEX_CTRL_REFCLK_EN         (1 << 3)
+
+#define RP_VEND_XP      0x00000F00
+#define  RP_VEND_XP_DL_UP       (1 << 30)
+
+#define RP_LINK_CONTROL_STATUS                  0x00000090
+#define  RP_LINK_CONTROL_STATUS_LINKSTAT_MASK   0x3fff0000
+
+#define PADS_CTL_SEL            0x0000009C
+
+#define PADS_CTL                0x000000A0
+#define  PADS_CTL_IDDQ_1L       (1 << 0)
+#define  PADS_CTL_TX_DATA_EN_1L (1 << 6)
+#define  PADS_CTL_RX_DATA_EN_1L (1 << 10)
+
+#define PADS_PLL_CTL                            0x000000B8
+#define  PADS_PLL_CTL_RST_B4SM                  (1 << 1)
+#define  PADS_PLL_CTL_LOCKDET                   (1 << 8)
+#define  PADS_PLL_CTL_REFCLK_MASK               (0x3 << 16)
+#define  PADS_PLL_CTL_REFCLK_INTERNAL_CML       (0 << 16)
+#define  PADS_PLL_CTL_REFCLK_INTERNAL_CMOS      (1 << 16)
+#define  PADS_PLL_CTL_REFCLK_EXTERNAL           (2 << 16)
+#define  PADS_PLL_CTL_TXCLKREF_MASK             (0x1 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_DIV10            (0 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_DIV5             (1 << 20)
+
+/* PMC access is required for PCIE xclk (un)clamping */
+#define PMC_SCRATCH42           0x144
+#define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
+
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+#define pmc_writel(value, reg) \
+        __raw_writel(value, (u32)reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+        __raw_readl((u32)reg_pmc_base + (reg))
+
+/*
+ * Tegra2 defines 1GB in the AXI address map for PCIe.
+ *
+ * That address space is split into different regions, with sizes and
+ * offsets as follows:
+ *
+ * 0x80000000 - 0x80003fff - PCI controller registers
+ * 0x80004000 - 0x80103fff - PCI configuration space
+ * 0x80104000 - 0x80203fff - PCI extended configuration space
+ * 0x80203fff - 0x803fffff - unused
+ * 0x80400000 - 0x8040ffff - downstream IO
+ * 0x80410000 - 0x8fffffff - unused
+ * 0x90000000 - 0x9fffffff - non-prefetchable memory
+ * 0xa0000000 - 0xbfffffff - prefetchable memory
+ */
+#define TEGRA_PCIE_BASE         0x80000000
+
+#define PCIE_REGS_SZ            SZ_16K
+#define PCIE_CFG_OFF            PCIE_REGS_SZ
+#define PCIE_CFG_SZ             SZ_1M
+#define PCIE_EXT_CFG_OFF        (PCIE_CFG_SZ + PCIE_CFG_OFF)
+#define PCIE_EXT_CFG_SZ         SZ_1M
+#define PCIE_IOMAP_SZ           (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
+
+#define MMIO_BASE               (TEGRA_PCIE_BASE + SZ_4M)
+#define MMIO_SIZE               SZ_64K
+#define MEM_BASE_0              (TEGRA_PCIE_BASE + SZ_256M)
+#define MEM_SIZE_0              SZ_128M
+#define MEM_BASE_1              (MEM_BASE_0 + MEM_SIZE_0)
+#define MEM_SIZE_1              SZ_128M
+#define PREFETCH_MEM_BASE_0     (MEM_BASE_1 + MEM_SIZE_1)
+#define PREFETCH_MEM_SIZE_0     SZ_128M
+#define PREFETCH_MEM_BASE_1     (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
+#define PREFETCH_MEM_SIZE_1     SZ_128M
+
+#define  PCIE_CONF_BUS(b)       ((b) << 16)
+#define  PCIE_CONF_DEV(d)       ((d) << 11)
+#define  PCIE_CONF_FUNC(f)      ((f) << 8)
+#define  PCIE_CONF_REG(r)       \
+        (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
+
+struct tegra_pcie_port {
+        int                     index;
+        u8                      root_bus_nr;
+        void __iomem            *base;
+
+        bool                    link_up;
+
+        char                    io_space_name[16];
+        char                    mem_space_name[16];
+        char                    prefetch_space_name[20];
+        struct resource         res[3];
+};
+
+struct tegra_pcie_info {
+        struct tegra_pcie_port  port[2];
+        int                     num_ports;
+
+        void __iomem            *regs;
+        struct resource         res_mmio;
+
+        struct clk              *pex_clk;
+        struct clk              *afi_clk;
+        struct clk              *pcie_xclk;
+        struct clk              *pll_e;
+};
+
+static struct tegra_pcie_info tegra_pcie = {
+        .res_mmio = {
+                .name = "PCI IO",
+                .start = MMIO_BASE,
+                .end = MMIO_BASE + MMIO_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+void __iomem *tegra_pcie_io_base;
+EXPORT_SYMBOL(tegra_pcie_io_base);
+
+static inline void afi_writel(u32 value, unsigned long offset)
+{
+        writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
+}
+
+static inline u32 afi_readl(unsigned long offset)
+{
+        return readl(offset + AFI_OFFSET + tegra_pcie.regs);
+}
+
+static inline void pads_writel(u32 value, unsigned long offset)
+{
+        writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
+}
+
+static inline u32 pads_readl(unsigned long offset)
+{
+        return readl(offset + PADS_OFFSET + tegra_pcie.regs);
+}
+
+static struct tegra_pcie_port *bus_to_port(int bus)
+{
+        int i;
+
+        for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
+                int rbus = tegra_pcie.port[i].root_bus_nr;
+                if (rbus != -1 && rbus == bus)
+                        break;
+        }
+
+        return i >= 0 ? tegra_pcie.port + i : NULL;
+}
+
+static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
+                                int where, int size, u32 *val)
+{
+        struct tegra_pcie_port *pp = bus_to_port(bus->number);
+        void __iomem *addr;
+
+        if (pp) {
+                if (devfn != 0) {
+                        *val = 0xffffffff;
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+                }
+
+                addr = pp->base + (where & ~0x3);
+        } else {
+                addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
+                                          PCIE_CONF_DEV(PCI_SLOT(devfn)) +
+                                          PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
+                                          PCIE_CONF_REG(where));
+        }
+
+        *val = readl(addr);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
+                                 int where, int size, u32 val)
+{
+        struct tegra_pcie_port *pp = bus_to_port(bus->number);
+        void __iomem *addr;
+
+        u32 mask;
+        u32 tmp;
+
+        if (pp) {
+                if (devfn != 0)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+
+                addr = pp->base + (where & ~0x3);
+        } else {
+                addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
+                                          PCIE_CONF_DEV(PCI_SLOT(devfn)) +
+                                          PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
+                                          PCIE_CONF_REG(where));
+        }
+
+        if (size == 4) {
+                writel(val, addr);
+                return PCIBIOS_SUCCESSFUL;
+        }
+
+        if (size == 2)
+                mask = ~(0xffff << ((where & 0x3) * 8));
+        else if (size == 1)
+                mask = ~(0xff << ((where & 0x3) * 8));
+        else
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        tmp = readl(addr) & mask;
+        tmp |= val << ((where & 0x3) * 8);
+        writel(tmp, addr);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops tegra_pcie_ops = {
+        .read   = tegra_pcie_read_conf,
+        .write  = tegra_pcie_write_conf,
+};
+
+static void __devinit tegra_pcie_fixup_bridge(struct pci_dev *dev)
+{
+        u16 reg;
+
+        if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
+                pci_read_config_word(dev, PCI_COMMAND, &reg);
+                reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+                        PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+                pci_write_config_word(dev, PCI_COMMAND, reg);
+        }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
+
+/* Tegra PCIE root complex wrongly reports device class */
+static void __devinit tegra_pcie_fixup_class(struct pci_dev *dev)
+{
+        dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
+
+/* Tegra PCIE requires relaxed ordering */
+static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
+{
+        u16 val16;
+        int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+
+        if (pos <= 0) {
+                dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
+                return;
+        }
+
+        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
+        val16 |= PCI_EXP_DEVCTL_RELAX_EN;
+        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
+
+static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct tegra_pcie_port *pp;
+
+        if (nr >= tegra_pcie.num_ports)
+                return 0;
+
+        pp = tegra_pcie.port + nr;
+        pp->root_bus_nr = sys->busnr;
+
+        /*
+         * IORESOURCE_IO
+         */
+        snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+                 "PCIe %d I/O", pp->index);
+        pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+        pp->res[0].name = pp->io_space_name;
+        if (pp->index == 0) {
+                pp->res[0].start = PCIBIOS_MIN_IO;
+                pp->res[0].end = pp->res[0].start + SZ_32K - 1;
+        } else {
+                pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
+                pp->res[0].end = IO_SPACE_LIMIT;
+        }
+        pp->res[0].flags = IORESOURCE_IO;
+        if (request_resource(&ioport_resource, &pp->res[0]))
+                panic("Request PCIe IO resource failed\n");
+        sys->resource[0] = &pp->res[0];
+
+        /*
+         * IORESOURCE_MEM
+         */
+        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+                 "PCIe %d MEM", pp->index);
+        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+        pp->res[1].name = pp->mem_space_name;
+        if (pp->index == 0) {
+                pp->res[1].start = MEM_BASE_0;
+                pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
+        } else {
+                pp->res[1].start = MEM_BASE_1;
+                pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
+        }
+        pp->res[1].flags = IORESOURCE_MEM;
+        if (request_resource(&iomem_resource, &pp->res[1]))
+                panic("Request PCIe Memory resource failed\n");
+        sys->resource[1] = &pp->res[1];
+
+        /*
+         * IORESOURCE_MEM | IORESOURCE_PREFETCH
+         */
+        snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
+                 "PCIe %d PREFETCH MEM", pp->index);
+        pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
+        pp->res[2].name = pp->prefetch_space_name;
+        if (pp->index == 0) {
+                pp->res[2].start = PREFETCH_MEM_BASE_0;
+                pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
+        } else {
+                pp->res[2].start = PREFETCH_MEM_BASE_1;
+                pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
+        }
+        pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+        if (request_resource(&iomem_resource, &pp->res[2]))
+                panic("Request PCIe Prefetch Memory resource failed\n");
+        sys->resource[2] = &pp->res[2];
+
+        return 1;
+}
+
+static int tegra_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return INT_PCIE_INTR;
+}
+
+static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
+                                                  struct pci_sys_data *sys)
+{
+        struct tegra_pcie_port *pp;
+
+        if (nr >= tegra_pcie.num_ports)
+                return 0;
+
+        pp = tegra_pcie.port + nr;
+        pp->root_bus_nr = sys->busnr;
+
+        return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys);
+}
+
+static struct hw_pci tegra_pcie_hw __initdata = {
+        .nr_controllers = 2,
+        .setup          = tegra_pcie_setup,
+        .scan           = tegra_pcie_scan_bus,
+        .swizzle        = pci_std_swizzle,
+        .map_irq        = tegra_pcie_map_irq,
+};
+
+
+static irqreturn_t tegra_pcie_isr(int irq, void *arg)
+{
+        const char *err_msg[] = {
+                "Unknown",
+                "AXI slave error",
+                "AXI decode error",
+                "Target abort",
+                "Master abort",
+                "Invalid write",
+                "Response decoding error",
+                "AXI response decoding error",
+                "Transcation timeout",
+        };
+
+        u32 code, signature;
+
+        code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
+        signature = afi_readl(AFI_INTR_SIGNATURE);
+        afi_writel(0, AFI_INTR_CODE);
+
+        if (code == AFI_INTR_LEGACY)
+                return IRQ_NONE;
+
+        if (code >= ARRAY_SIZE(err_msg))
+                code = 0;
+
+        /*
+         * do not pollute kernel log with master abort reports since they
+         * happen a lot during enumeration
+         */
+        if (code == AFI_INTR_MASTER_ABORT)
+                pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
+        else
+                pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
+
+        return IRQ_HANDLED;
+}
+
+static void tegra_pcie_setup_translations(void)
+{
+        u32 fpci_bar;
+        u32 size;
+        u32 axi_address;
+
+        /* Bar 0: config Bar */
+        fpci_bar = ((u32)0xfdff << 16);
+        size = PCIE_CFG_SZ;
+        axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
+        afi_writel(axi_address, AFI_AXI_BAR0_START);
+        afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
+        afi_writel(fpci_bar, AFI_FPCI_BAR0);
+
+        /* Bar 1: extended config Bar */
+        fpci_bar = ((u32)0xfe1 << 20);
+        size = PCIE_EXT_CFG_SZ;
+        axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
+        afi_writel(axi_address, AFI_AXI_BAR1_START);
+        afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
+        afi_writel(fpci_bar, AFI_FPCI_BAR1);
+
+        /* Bar 2: downstream IO bar */
+        fpci_bar = ((__u32)0xfdfc << 16);
+        size = MMIO_SIZE;
+        axi_address = MMIO_BASE;
+        afi_writel(axi_address, AFI_AXI_BAR2_START);
+        afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
+        afi_writel(fpci_bar, AFI_FPCI_BAR2);
+
+        /* Bar 3: prefetchable memory BAR */
+        fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
+        size =  PREFETCH_MEM_SIZE_0 +  PREFETCH_MEM_SIZE_1;
+        axi_address = PREFETCH_MEM_BASE_0;
+        afi_writel(axi_address, AFI_AXI_BAR3_START);
+        afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
+        afi_writel(fpci_bar, AFI_FPCI_BAR3);
+
+        /* Bar 4: non prefetchable memory BAR */
+        fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
+        size = MEM_SIZE_0 + MEM_SIZE_1;
+        axi_address = MEM_BASE_0;
+        afi_writel(axi_address, AFI_AXI_BAR4_START);
+        afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
+        afi_writel(fpci_bar, AFI_FPCI_BAR4);
+
+        /* Bar 5: NULL out the remaining BAR as it is not used */
+        fpci_bar = 0;
+        size = 0;
+        axi_address = 0;
+        afi_writel(axi_address, AFI_AXI_BAR5_START);
+        afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
+        afi_writel(fpci_bar, AFI_FPCI_BAR5);
+
+        /* map all upstream transactions as uncached */
+        afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
+        afi_writel(0, AFI_CACHE_BAR0_SZ);
+        afi_writel(0, AFI_CACHE_BAR1_ST);
+        afi_writel(0, AFI_CACHE_BAR1_SZ);
+
+        /* No MSI */
+        afi_writel(0, AFI_MSI_FPCI_BAR_ST);
+        afi_writel(0, AFI_MSI_BAR_SZ);
+        afi_writel(0, AFI_MSI_AXI_BAR_ST);
+        afi_writel(0, AFI_MSI_BAR_SZ);
+}
+
+static void tegra_pcie_enable_controller(void)
+{
+        u32 val, reg;
+        int i;
+
+        /* Enable slot clock and pulse the reset signals */
+        for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
+                val = afi_readl(reg) |  AFI_PEX_CTRL_REFCLK_EN;
+                afi_writel(val, reg);
+                val &= ~AFI_PEX_CTRL_RST;
+                afi_writel(val, reg);
+
+                val = afi_readl(reg) | AFI_PEX_CTRL_RST;
+                afi_writel(val, reg);
+        }
+
+        /* Enable dual controller and both ports */
+        val = afi_readl(AFI_PCIE_CONFIG);
+        val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
+                 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
+                 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
+        val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
+        afi_writel(val, AFI_PCIE_CONFIG);
+
+        val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
+        afi_writel(val, AFI_FUSE);
+
+        /* Initialze internal PHY, enable up to 16 PCIE lanes */
+        pads_writel(0x0, PADS_CTL_SEL);
+
+        /* override IDDQ to 1 on all 4 lanes */
+        val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
+        pads_writel(val, PADS_CTL);
+
+        /*
+         * set up PHY PLL inputs select PLLE output as refclock,
+         * set TX ref sel to div10 (not div5)
+         */
+        val = pads_readl(PADS_PLL_CTL);
+        val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
+        val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
+        pads_writel(val, PADS_PLL_CTL);
+
+        /* take PLL out of reset  */
+        val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
+        pads_writel(val, PADS_PLL_CTL);
+
+        /*
+         * Hack, set the clock voltage to the DEFAULT provided by hw folks.
+         * This doesn't exist in the documentation
+         */
+        pads_writel(0xfa5cfa5c, 0xc8);
+
+        /* Wait for the PLL to lock */
+        do {
+                val = pads_readl(PADS_PLL_CTL);
+        } while (!(val & PADS_PLL_CTL_LOCKDET));
+
+        /* turn off IDDQ override */
+        val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
+        pads_writel(val, PADS_CTL);
+
+        /* enable TX/RX data */
+        val = pads_readl(PADS_CTL);
+        val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
+        pads_writel(val, PADS_CTL);
+
+        /* Take the PCIe interface module out of reset */
+        tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
+
+        /* Finally enable PCIe */
+        val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
+        afi_writel(val, AFI_CONFIGURATION);
+
+        val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
+               AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
+               AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
+        afi_writel(val, AFI_AFI_INTR_ENABLE);
+        afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
+
+        /* FIXME: No MSI for now, only INT */
+        afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
+
+        /* Disable all execptions */
+        afi_writel(0, AFI_FPCI_ERROR_MASKS);
+
+        return;
+}
+
+static void tegra_pcie_xclk_clamp(bool clamp)
+{
+        u32 reg;
+
+        reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
+
+        if (clamp)
+                reg |= PMC_SCRATCH42_PCX_CLAMP;
+
+        pmc_writel(reg, PMC_SCRATCH42);
+}
+
+static int tegra_pcie_power_on(void)
+{
+        tegra_pcie_xclk_clamp(true);
+        tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
+        tegra_pcie_xclk_clamp(false);
+
+        clk_enable(tegra_pcie.afi_clk);
+        clk_enable(tegra_pcie.pex_clk);
+        return clk_enable(tegra_pcie.pll_e);
+}
+
+static void tegra_pcie_power_off(void)
+{
+        tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
+        tegra_periph_reset_assert(tegra_pcie.afi_clk);
+        tegra_periph_reset_assert(tegra_pcie.pex_clk);
+
+        tegra_pcie_xclk_clamp(true);
+}
+
+static int tegra_pcie_clocks_get(void)
+{
+        int err;
+
+        tegra_pcie.pex_clk = clk_get(NULL, "pex");
+        if (IS_ERR(tegra_pcie.pex_clk))
+                return PTR_ERR(tegra_pcie.pex_clk);
+
+        tegra_pcie.afi_clk = clk_get(NULL, "afi");
+        if (IS_ERR(tegra_pcie.afi_clk)) {
+                err = PTR_ERR(tegra_pcie.afi_clk);
+                goto err_afi_clk;
+        }
+
+        tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
+        if (IS_ERR(tegra_pcie.pcie_xclk)) {
+                err =  PTR_ERR(tegra_pcie.pcie_xclk);
+                goto err_pcie_xclk;
+        }
+
+        tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
+        if (IS_ERR(tegra_pcie.pll_e)) {
+                err = PTR_ERR(tegra_pcie.pll_e);
+                goto err_pll_e;
+        }
+
+        return 0;
+
+err_pll_e:
+        clk_put(tegra_pcie.pcie_xclk);
+err_pcie_xclk:
+        clk_put(tegra_pcie.afi_clk);
+err_afi_clk:
+        clk_put(tegra_pcie.pex_clk);
+
+        return err;
+}
+
+static void tegra_pcie_clocks_put(void)
+{
+        clk_put(tegra_pcie.pll_e);
+        clk_put(tegra_pcie.pcie_xclk);
+        clk_put(tegra_pcie.afi_clk);
+        clk_put(tegra_pcie.pex_clk);
+}
+
+static int __init tegra_pcie_get_resources(void)
+{
+        struct resource *res_mmio = &tegra_pcie.res_mmio;
+        int err;
+
+        err = tegra_pcie_clocks_get();
+        if (err) {
+                pr_err("PCIE: failed to get clocks: %d\n", err);
+                return err;
+        }
+
+        err = tegra_pcie_power_on();
+        if (err) {
+                pr_err("PCIE: failed to power up: %d\n", err);
+                goto err_pwr_on;
+        }
+
+        tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
+        if (tegra_pcie.regs == NULL) {
+                pr_err("PCIE: Failed to map PCI/AFI registers\n");
+                err = -ENOMEM;
+                goto err_map_reg;
+        }
+
+        err = request_resource(&iomem_resource, res_mmio);
+        if (err) {
+                pr_err("PCIE: Failed to request resources: %d\n", err);
+                goto err_req_io;
+        }
+
+        tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
+                                             resource_size(res_mmio));
+        if (tegra_pcie_io_base == NULL) {
+                pr_err("PCIE: Failed to map IO\n");
+                err = -ENOMEM;
+                goto err_map_io;
+        }
+
+        err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
+                          IRQF_SHARED, "PCIE", &tegra_pcie);
+        if (err) {
+                pr_err("PCIE: Failed to register IRQ: %d\n", err);
+                goto err_irq;
+        }
+        set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
+
+        return 0;
+
+err_irq:
+        iounmap(tegra_pcie_io_base);
+err_map_io:
+        release_resource(&tegra_pcie.res_mmio);
+err_req_io:
+        iounmap(tegra_pcie.regs);
+err_map_reg:
+        tegra_pcie_power_off();
+err_pwr_on:
+        tegra_pcie_clocks_put();
+
+        return err;
+}
+
+/*
+ * FIXME: If there are no PCIe cards attached, then calling this function
+ * can result in the increase of the bootup time as there are big timeout
+ * loops.
+ */
+#define TEGRA_PCIE_LINKUP_TIMEOUT       200     /* up to 1.2 seconds */
+static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
+                                  u32 reset_reg)
+{
+        u32 reg;
+        int retries = 3;
+        int timeout;
+
+        do {
+                timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
+                while (timeout) {
+                        reg = readl(pp->base + RP_VEND_XP);
+
+                        if (reg & RP_VEND_XP_DL_UP)
+                                break;
+
+                        mdelay(1);
+                        timeout--;
+                }
+
+                if (!timeout)  {
+                        pr_err("PCIE: port %d: link down, retrying\n", idx);
+                        goto retry;
+                }
+
+                timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
+                while (timeout) {
+                        reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
+
+                        if (reg & 0x20000000)
+                                return true;
+
+                        mdelay(1);
+                        timeout--;
+                }
+
+retry:
+                /* Pulse the PEX reset */
+                reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
+                afi_writel(reg, reset_reg);
+                mdelay(1);
+                reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
+                afi_writel(reg, reset_reg);
+
+                retries--;
+        } while (retries);
+
+        return false;
+}
+
+static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
+{
+        struct tegra_pcie_port *pp;
+
+        pp = tegra_pcie.port + tegra_pcie.num_ports;
+
+        pp->index = -1;
+        pp->base = tegra_pcie.regs + offset;
+        pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
+
+        if (!pp->link_up) {
+                pp->base = NULL;
+                printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
+                return;
+        }
+
+        tegra_pcie.num_ports++;
+        pp->index = index;
+        pp->root_bus_nr = -1;
+        memset(pp->res, 0, sizeof(pp->res));
+}
+
+int __init tegra_pcie_init(bool init_port0, bool init_port1)
+{
+        int err;
+
+        if (!(init_port0 || init_port1))
+                return -ENODEV;
+
+        err = tegra_pcie_get_resources();
+        if (err)
+                return err;
+
+        tegra_pcie_enable_controller();
+
+        /* setup the AFI address translations */
+        tegra_pcie_setup_translations();
+
+        if (init_port0)
+                tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
+
+        if (init_port1)
+                tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
+
+        pci_common_init(&tegra_pcie_hw);
+
+        return 0;
+}
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c
new file mode 100644
index 00000000000..a6ea34e782d
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux-t2-tables.c
@@ -0,0 +1,260 @@
+/*
+ * linux/arch/arm/mach-tegra/pinmux-t2-tables.c
+ *
+ * Common pinmux configurations for Tegra 2 SoCs
+ *
+ * Copyright (C) 2010 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+
+#define DRIVE_PINGROUP(pg_name, r)                              \
+        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
+                .name = #pg_name,                               \
+                .reg = r                                        \
+        }
+
+const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+        DRIVE_PINGROUP(AO1,             0x868),
+        DRIVE_PINGROUP(AO2,             0x86c),
+        DRIVE_PINGROUP(AT1,             0x870),
+        DRIVE_PINGROUP(AT2,             0x874),
+        DRIVE_PINGROUP(CDEV1,           0x878),
+        DRIVE_PINGROUP(CDEV2,           0x87c),
+        DRIVE_PINGROUP(CSUS,            0x880),
+        DRIVE_PINGROUP(DAP1,            0x884),
+        DRIVE_PINGROUP(DAP2,            0x888),
+        DRIVE_PINGROUP(DAP3,            0x88c),
+        DRIVE_PINGROUP(DAP4,            0x890),
+        DRIVE_PINGROUP(DBG,             0x894),
+        DRIVE_PINGROUP(LCD1,            0x898),
+        DRIVE_PINGROUP(LCD2,            0x89c),
+        DRIVE_PINGROUP(SDMMC2,          0x8a0),
+        DRIVE_PINGROUP(SDMMC3,          0x8a4),
+        DRIVE_PINGROUP(SPI,             0x8a8),
+        DRIVE_PINGROUP(UAA,             0x8ac),
+        DRIVE_PINGROUP(UAB,             0x8b0),
+        DRIVE_PINGROUP(UART2,           0x8b4),
+        DRIVE_PINGROUP(UART3,           0x8b8),
+        DRIVE_PINGROUP(VI1,             0x8bc),
+        DRIVE_PINGROUP(VI2,             0x8c0),
+        DRIVE_PINGROUP(XM2A,            0x8c4),
+        DRIVE_PINGROUP(XM2C,            0x8c8),
+        DRIVE_PINGROUP(XM2D,            0x8cc),
+        DRIVE_PINGROUP(XM2CLK,          0x8d0),
+        DRIVE_PINGROUP(MEMCOMP,         0x8d4),
+};
+
+#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe,          \
+                 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)    \
+        [TEGRA_PINGROUP_ ## pg_name] = {                        \
+                .name = #pg_name,                               \
+                .vddio = TEGRA_VDDIO_ ## vdd,                   \
+                .funcs = {                                      \
+                        TEGRA_MUX_ ## f0,                       \
+                        TEGRA_MUX_ ## f1,                       \
+                        TEGRA_MUX_ ## f2,                       \
+                        TEGRA_MUX_ ## f3,                       \
+                },                                              \
+                .func_safe = TEGRA_MUX_ ## f_safe,              \
+                .tri_reg = tri_r,                               \
+                .tri_bit = tri_b,                               \
+                .mux_reg = mux_r,                               \
+                .mux_bit = mux_b,                               \
+                .pupd_reg = pupd_r,                             \
+                .pupd_bit = pupd_b,                             \
+        }
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+        PINGROUP(ATA,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x14, 0,  0x80, 24, 0xA0, 0),
+        PINGROUP(ATB,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 1,  0x80, 16, 0xA0, 2),
+        PINGROUP(ATC,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 2,  0x80, 22, 0xA0, 4),
+        PINGROUP(ATD,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 3,  0x80, 20, 0xA0, 6),
+        PINGROUP(ATE,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x18, 25, 0x80, 12, 0xA0, 8),
+        PINGROUP(CDEV1, AUDIO, OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    OSC,       0x14, 4,  0x88, 2,  0xA8, 0),
+        PINGROUP(CDEV2, AUDIO, OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     OSC,       0x14, 5,  0x88, 4,  0xA8, 2),
+        PINGROUP(CRTP,  LCD,   CRT,       RSVD,      RSVD,      RSVD,          RSVD,      0x20, 14, 0x98, 20, 0xA4, 24),
+        PINGROUP(CSUS,  VI,    PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6,  0x88, 6,  0xAC, 24),
+        PINGROUP(DAP1,  AUDIO, DAP1,      RSVD,      GMI,       SDIO2,         DAP1,      0x14, 7,  0x88, 20, 0xA0, 10),
+        PINGROUP(DAP2,  AUDIO, DAP2,      TWC,       RSVD,      GMI,           DAP2,      0x14, 8,  0x88, 22, 0xA0, 12),
+        PINGROUP(DAP3,  BB,    DAP3,      RSVD,      RSVD,      RSVD,          DAP3,      0x14, 9,  0x88, 24, 0xA0, 14),
+        PINGROUP(DAP4,  UART,  DAP4,      RSVD,      GMI,       RSVD,          DAP4,      0x14, 10, 0x88, 26, 0xA0, 16),
+        PINGROUP(DDC,   LCD,   I2C2,      RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 31, 0x88, 0,  0xB0, 28),
+        PINGROUP(DTA,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD4,     0x14, 11, 0x84, 20, 0xA0, 18),
+        PINGROUP(DTB,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 12, 0x84, 22, 0xA0, 20),
+        PINGROUP(DTC,   VI,    RSVD,      RSVD,      VI,        RSVD,          RSVD1,     0x14, 13, 0x84, 26, 0xA0, 22),
+        PINGROUP(DTD,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD1,     0x14, 14, 0x84, 28, 0xA0, 24),
+        PINGROUP(DTE,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 15, 0x84, 30, 0xA0, 26),
+        PINGROUP(DTF,   VI,    I2C3,      RSVD,      VI,        RSVD,          RSVD4,     0x20, 12, 0x98, 30, 0xA0, 28),
+        PINGROUP(GMA,   NAND,  UARTE,     SPI3,      GMI,       SDIO4,         SPI3,      0x14, 28, 0x84, 0,  0xB0, 20),
+        PINGROUP(GMB,   NAND,  IDE,       NAND,      GMI,       GMI_INT,       GMI,       0x18, 29, 0x88, 28, 0xB0, 22),
+        PINGROUP(GMC,   NAND,  UARTD,     SPI4,      GMI,       SFLASH,        SPI4,      0x14, 29, 0x84, 2,  0xB0, 24),
+        PINGROUP(GMD,   NAND,  RSVD,      NAND,      GMI,       SFLASH,        GMI,       0x18, 30, 0x88, 30, 0xB0, 26),
+        PINGROUP(GME,   NAND,  RSVD,      DAP5,      GMI,       SDIO4,         GMI,       0x18, 0,  0x8C, 0,  0xA8, 24),
+        PINGROUP(GPU,   UART,  PWM,       UARTA,     GMI,       RSVD,          RSVD4,     0x14, 16, 0x8C, 4,  0xA4, 20),
+        PINGROUP(GPU7,  SYS,   RTCK,      RSVD,      RSVD,      RSVD,          RTCK,      0x20, 11, 0x98, 28, 0xA4, 6),
+        PINGROUP(GPV,   SD,    PCIE,      RSVD,      RSVD,      RSVD,          PCIE,      0x14, 17, 0x8C, 2,  0xA0, 30),
+        PINGROUP(HDINT, LCD,   HDMI,      RSVD,      RSVD,      RSVD,          HDMI,      0x1C, 23, 0x84, 4,  0xAC, 22),
+        PINGROUP(I2CP,  SYS,   I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 18, 0x88, 8,  0xA4, 2),
+        PINGROUP(IRRX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 20, 0x88, 18, 0xA8, 22),
+        PINGROUP(IRTX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 19, 0x88, 16, 0xA8, 20),
+        PINGROUP(KBCA,  SYS,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, KBC,       0x14, 22, 0x88, 10, 0xA4, 8),
+        PINGROUP(KBCB,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x14, 21, 0x88, 12, 0xA4, 10),
+        PINGROUP(KBCC,  SYS,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL, KBC,       0x18, 26, 0x88, 14, 0xA4, 12),
+        PINGROUP(KBCD,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x20, 10, 0x98, 26, 0xA4, 14),
+        PINGROUP(KBCE,  SYS,   KBC,       NAND,      OWR,       RSVD,          KBC,       0x14, 26, 0x80, 28, 0xB0, 2),
+        PINGROUP(KBCF,  SYS,   KBC,       NAND,      TRACE,     MIO,           KBC,       0x14, 27, 0x80, 26, 0xB0, 0),
+        PINGROUP(LCSN,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 31, 0x90, 12, 0xAC, 20),
+        PINGROUP(LD0,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 0,  0x94, 0,  0xAC, 12),
+        PINGROUP(LD1,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 1,  0x94, 2,  0xAC, 12),
+        PINGROUP(LD10,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 10, 0x94, 20, 0xAC, 12),
+        PINGROUP(LD11,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 11, 0x94, 22, 0xAC, 12),
+        PINGROUP(LD12,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 12, 0x94, 24, 0xAC, 12),
+        PINGROUP(LD13,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 13, 0x94, 26, 0xAC, 12),
+        PINGROUP(LD14,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 14, 0x94, 28, 0xAC, 12),
+        PINGROUP(LD15,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 15, 0x94, 30, 0xAC, 12),
+        PINGROUP(LD16,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 16, 0x98, 0,  0xAC, 12),
+        PINGROUP(LD17,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 17, 0x98, 2,  0xAC, 12),
+        PINGROUP(LD2,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 2,  0x94, 4,  0xAC, 12),
+        PINGROUP(LD3,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 3,  0x94, 6,  0xAC, 12),
+        PINGROUP(LD4,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 4,  0x94, 8,  0xAC, 12),
+        PINGROUP(LD5,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 5,  0x94, 10, 0xAC, 12),
+        PINGROUP(LD6,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 6,  0x94, 12, 0xAC, 12),
+        PINGROUP(LD7,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 7,  0x94, 14, 0xAC, 12),
+        PINGROUP(LD8,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 8,  0x94, 16, 0xAC, 12),
+        PINGROUP(LD9,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 9,  0x94, 18, 0xAC, 12),
+        PINGROUP(LDC,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 30, 0x90, 14, 0xAC, 20),
+        PINGROUP(LDI,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 6,  0x98, 16, 0xAC, 18),
+        PINGROUP(LHP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 18, 0x98, 10, 0xAC, 16),
+        PINGROUP(LHP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 19, 0x98, 4,  0xAC, 14),
+        PINGROUP(LHP2,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 20, 0x98, 6,  0xAC, 14),
+        PINGROUP(LHS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x20, 7,  0x90, 22, 0xAC, 22),
+        PINGROUP(LM0,   LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 24, 0x90, 26, 0xAC, 22),
+        PINGROUP(LM1,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      CRT,           RSVD3,     0x1C, 25, 0x90, 28, 0xAC, 22),
+        PINGROUP(LPP,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 8,  0x98, 14, 0xAC, 18),
+        PINGROUP(LPW0,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 3,  0x90, 0,  0xAC, 20),
+        PINGROUP(LPW1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 4,  0x90, 2,  0xAC, 20),
+        PINGROUP(LPW2,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 5,  0x90, 4,  0xAC, 20),
+        PINGROUP(LSC0,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 27, 0x90, 18, 0xAC, 22),
+        PINGROUP(LSC1,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 28, 0x90, 20, 0xAC, 20),
+        PINGROUP(LSCK,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 29, 0x90, 16, 0xAC, 20),
+        PINGROUP(LSDA,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 1,  0x90, 8,  0xAC, 20),
+        PINGROUP(LSDI,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          DISPLAYA,  0x20, 2,  0x90, 6,  0xAC, 20),
+        PINGROUP(LSPI,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       HDMI,          DISPLAYA,  0x20, 0,  0x90, 10, 0xAC, 22),
+        PINGROUP(LVP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 21, 0x90, 30, 0xAC, 22),
+        PINGROUP(LVP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 22, 0x98, 8,  0xAC, 16),
+        PINGROUP(LVS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 26, 0x90, 24, 0xAC, 22),
+        PINGROUP(OWC,   SYS,   OWR,       RSVD,      RSVD,      RSVD,          OWR,       0x14, 31, 0x84, 8,  0xB0, 30),
+        PINGROUP(PMC,   SYS,   PWR_ON,    PWR_INTR,  RSVD,      RSVD,          PWR_ON,    0x14, 23, 0x98, 18, -1,   -1),
+        PINGROUP(PTA,   NAND,  I2C2,      HDMI,      GMI,       RSVD,          RSVD4,     0x14, 24, 0x98, 22, 0xA4, 4),
+        PINGROUP(RM,    UART,  I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 25, 0x80, 14, 0xA4, 0),
+        PINGROUP(SDB,   SD,    UARTA,     PWM,       SDIO3,     SPI2,          PWM,       0x20, 15, 0x8C, 10, -1,   -1),
+        PINGROUP(SDC,   SD,    PWM,       TWC,       SDIO3,     SPI3,          TWC,       0x18, 1,  0x8C, 12, 0xAC, 28),
+        PINGROUP(SDD,   SD,    UARTA,     PWM,       SDIO3,     SPI3,          PWM,       0x18, 2,  0x8C, 14, 0xAC, 30),
+        PINGROUP(SDIO1, BB,    SDIO1,     RSVD,      UARTE,     UARTA,         RSVD2,     0x14, 30, 0x80, 30, 0xB0, 18),
+        PINGROUP(SLXA,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 3,  0x84, 6,  0xA4, 22),
+        PINGROUP(SLXC,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 5,  0x84, 10, 0xA4, 26),
+        PINGROUP(SLXD,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 6,  0x84, 12, 0xA4, 28),
+        PINGROUP(SLXK,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 7,  0x84, 14, 0xA4, 30),
+        PINGROUP(SPDI,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 8,  0x8C, 8,  0xA4, 16),
+        PINGROUP(SPDO,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 9,  0x8C, 6,  0xA4, 18),
+        PINGROUP(SPIA,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 10, 0x8C, 30, 0xA8, 4),
+        PINGROUP(SPIB,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 11, 0x8C, 28, 0xA8, 6),
+        PINGROUP(SPIC,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 12, 0x8C, 26, 0xA8, 8),
+        PINGROUP(SPID,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 13, 0x8C, 24, 0xA8, 10),
+        PINGROUP(SPIE,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 14, 0x8C, 22, 0xA8, 12),
+        PINGROUP(SPIF,  AUDIO, SPI3,      SPI1,      SPI2,      RSVD,          RSVD4,     0x18, 15, 0x8C, 20, 0xA8, 14),
+        PINGROUP(SPIG,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 16, 0x8C, 18, 0xA8, 16),
+        PINGROUP(SPIH,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 17, 0x8C, 16, 0xA8, 18),
+        PINGROUP(UAA,   BB,    SPI3,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 18, 0x80, 0,  0xAC, 0),
+        PINGROUP(UAB,   BB,    SPI2,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 19, 0x80, 2,  0xAC, 2),
+        PINGROUP(UAC,   BB,    OWR,       RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 20, 0x80, 4,  0xAC, 4),
+        PINGROUP(UAD,   UART,  IRDA,      SPDIF,     UARTA,     SPI4,          SPDIF,     0x18, 21, 0x80, 6,  0xAC, 6),
+        PINGROUP(UCA,   UART,  UARTC,     RSVD,      GMI,       RSVD,          RSVD4,     0x18, 22, 0x84, 16, 0xAC, 8),
+        PINGROUP(UCB,   UART,  UARTC,     PWM,       GMI,       RSVD,          RSVD4,     0x18, 23, 0x84, 18, 0xAC, 10),
+        PINGROUP(UDA,   BB,    SPI1,      RSVD,      UARTD,     ULPI,          RSVD2,     0x20, 13, 0x80, 8,  0xB0, 16),
+        /* these pin groups only have pullup and pull down control */
+        PINGROUP(CK32,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 14),
+        PINGROUP(DDRC,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xAC, 26),
+        PINGROUP(PMCA,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 4),
+        PINGROUP(PMCB,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 6),
+        PINGROUP(PMCC,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 8),
+        PINGROUP(PMCD,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 10),
+        PINGROUP(PMCE,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 12),
+        PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
+        PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
+};
+
+#ifdef CONFIG_PM
+#define TRISTATE_REG_A         0x14
+#define TRISTATE_REG_NUM       4
+#define PIN_MUX_CTL_REG_A      0x80
+#define PIN_MUX_CTL_REG_NUM    8
+#define PULLUPDOWN_REG_A       0xa0
+#define PULLUPDOWN_REG_NUM     5
+
+static u32 pinmux_reg[TRISTATE_REG_NUM + PIN_MUX_CTL_REG_NUM +
+                     PULLUPDOWN_REG_NUM];
+
+static inline unsigned long pg_readl(unsigned long offset)
+{
+        return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+}
+
+static inline void pg_writel(unsigned long value, unsigned long offset)
+{
+        writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+}
+
+void tegra_pinmux_suspend(void)
+{
+        unsigned int i;
+        u32 *ctx = pinmux_reg;
+
+        for (i = 0; i < TRISTATE_REG_NUM; i++)
+                *ctx++ = pg_readl(TRISTATE_REG_A + i*4);
+
+        for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
+                *ctx++ = pg_readl(PIN_MUX_CTL_REG_A + i*4);
+
+        for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
+                *ctx++ = pg_readl(PULLUPDOWN_REG_A + i*4);
+}
+
+void tegra_pinmux_resume(void)
+{
+        unsigned int i;
+        u32 *ctx = pinmux_reg;
+
+        for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
+                pg_writel(*ctx++, PIN_MUX_CTL_REG_A + i*4);
+
+        for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
+                pg_writel(*ctx++, PULLUPDOWN_REG_A + i*4);
+
+        for (i = 0; i < TRISTATE_REG_NUM; i++)
+                pg_writel(*ctx++, TRISTATE_REG_A + i*4);
+}
+#endif
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 13ae10237e8..f80d507671b 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -14,7 +14,8 @@
  *
  */
 
-
+#include <linux/init.h>
+#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/spinlock.h>
@@ -23,21 +24,6 @@
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
 
-
-#define TEGRA_TRI_STATE(x)      (0x14 + (4 * (x)))
-#define TEGRA_PP_MUX_CTL(x)     (0x80 + (4 * (x)))
-#define TEGRA_PP_PU_PD(x)       (0xa0 + (4 * (x)))
-
-#define REG_A 0
-#define REG_B 1
-#define REG_C 2
-#define REG_D 3
-#define REG_E 4
-#define REG_F 5
-#define REG_G 6
-
-#define REG_N -1
-
 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
 #define LPMD(reg)       (((reg) >> 4) & 0x3)
@@ -46,154 +32,8 @@
 #define SLWR(reg)       (((reg) >> 28) & 0x3)
 #define SLWF(reg)       (((reg) >> 30) & 0x3)
 
-struct tegra_pingroup_desc {
-        const char *name;
-        int funcs[4];
-        s8 tri_reg;     /* offset into the TRISTATE_REG_* register bank */
-        s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
-        s8 mux_reg;     /* offset into the PIN_MUX_CTL_* register bank */
-        s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
-        s8 pupd_reg;    /* offset into the PULL_UPDOWN_REG_* register bank */
-        s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
-};
-
-#define PINGROUP(pg_name, f0, f1, f2, f3,                       \
-                 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)    \
-        [TEGRA_PINGROUP_ ## pg_name] = {                        \
-                .name = #pg_name,                               \
-                .funcs = {                                      \
-                        TEGRA_MUX_ ## f0,                       \
-                        TEGRA_MUX_ ## f1,                       \
-                        TEGRA_MUX_ ## f2,                       \
-                        TEGRA_MUX_ ## f3,                       \
-                },                                              \
-                .tri_reg = REG_ ## tri_r,                       \
-                .tri_bit = tri_b,                               \
-                .mux_reg = REG_ ## mux_r,                       \
-                .mux_bit = mux_b,                               \
-                .pupd_reg = REG_ ## pupd_r,                     \
-                .pupd_bit = pupd_b,                             \
-        }
-
-static const struct tegra_pingroup_desc pingroups[TEGRA_MAX_PINGROUP] = {
-        PINGROUP(ATA,   IDE,       NAND,      GMI,       RSVD,          A, 0,  A, 24, A, 0),
-        PINGROUP(ATB,   IDE,       NAND,      GMI,       SDIO4,         A, 1,  A, 16, A, 2),
-        PINGROUP(ATC,   IDE,       NAND,      GMI,       SDIO4,         A, 2,  A, 22, A, 4),
-        PINGROUP(ATD,   IDE,       NAND,      GMI,       SDIO4,         A, 3,  A, 20, A, 6),
-        PINGROUP(ATE,   IDE,       NAND,      GMI,       RSVD,          B, 25, A, 12, A, 8),
-        PINGROUP(CDEV1, OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    A, 4,  C, 2,  C, 0),
-        PINGROUP(CDEV2, OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     A, 5,  C, 4,  C, 2),
-        PINGROUP(CRTP,  CRT,       RSVD,      RSVD,      RSVD,          D, 14, G, 20, B, 24),
-        PINGROUP(CSUS,  PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, A, 6,  C, 6,  D, 24),
-        PINGROUP(DAP1,  DAP1,      RSVD,      GMI,       SDIO2,         A, 7,  C, 20, A, 10),
-        PINGROUP(DAP2,  DAP2,      TWC,       RSVD,      GMI,           A, 8,  C, 22, A, 12),
-        PINGROUP(DAP3,  DAP3,      RSVD,      RSVD,      RSVD,          A, 9,  C, 24, A, 14),
-        PINGROUP(DAP4,  DAP4,      RSVD,      GMI,       RSVD,          A, 10, C, 26, A, 16),
-        PINGROUP(DDC,   I2C2,      RSVD,      RSVD,      RSVD,          B, 31, C, 0,  E, 28),
-        PINGROUP(DTA,   RSVD,      SDIO2,     VI,        RSVD,          A, 11, B, 20, A, 18),
-        PINGROUP(DTB,   RSVD,      RSVD,      VI,        SPI1,          A, 12, B, 22, A, 20),
-        PINGROUP(DTC,   RSVD,      RSVD,      VI,        RSVD,          A, 13, B, 26, A, 22),
-        PINGROUP(DTD,   RSVD,      SDIO2,     VI,        RSVD,          A, 14, B, 28, A, 24),
-        PINGROUP(DTE,   RSVD,      RSVD,      VI,        SPI1,          A, 15, B, 30, A, 26),
-        PINGROUP(DTF,   I2C3,      RSVD,      VI,        RSVD,          D, 12, G, 30, A, 28),
-        PINGROUP(GMA,   UARTE,     SPI3,      GMI,       SDIO4,         A, 28, B, 0,  E, 20),
-        PINGROUP(GMB,   IDE,       NAND,      GMI,       GMI_INT,       B, 29, C, 28, E, 22),
-        PINGROUP(GMC,   UARTD,     SPI4,      GMI,       SFLASH,        A, 29, B, 2,  E, 24),
-        PINGROUP(GMD,   RSVD,      NAND,      GMI,       SFLASH,        B, 30, C, 30, E, 26),
-        PINGROUP(GME,   RSVD,      DAP5,      GMI,       SDIO4,         B, 0,  D, 0,  C, 24),
-        PINGROUP(GPU,   PWM,       UARTA,     GMI,       RSVD,          A, 16, D, 4,  B, 20),
-        PINGROUP(GPU7,  RTCK,      RSVD,      RSVD,      RSVD,          D, 11, G, 28, B, 6),
-        PINGROUP(GPV,   PCIE,      RSVD,      RSVD,      RSVD,          A, 17, D, 2,  A, 30),
-        PINGROUP(HDINT, HDMI,      RSVD,      RSVD,      RSVD,          C, 23, B, 4,  D, 22),
-        PINGROUP(I2CP,  I2C,       RSVD,      RSVD,      RSVD,          A, 18, C, 8,  B, 2),
-        PINGROUP(IRRX,  UARTA,     UARTB,     GMI,       SPI4,          A, 20, C, 18, C, 22),
-        PINGROUP(IRTX,  UARTA,     UARTB,     GMI,       SPI4,          A, 19, C, 16, C, 20),
-        PINGROUP(KBCA,  KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, A, 22, C, 10, B, 8),
-        PINGROUP(KBCB,  KBC,       NAND,      SDIO2,     MIO,           A, 21, C, 12, B, 10),
-        PINGROUP(KBCC,  KBC,       NAND,      TRACE,     EMC_TEST1_DLL, B, 26, C, 14, B, 12),
-        PINGROUP(KBCD,  KBC,       NAND,      SDIO2,     MIO,           D, 10, G, 26, B, 14),
-        PINGROUP(KBCE,  KBC,       NAND,      OWR,       RSVD,          A, 26, A, 28, E, 2),
-        PINGROUP(KBCF,  KBC,       NAND,      TRACE,     MIO,           A, 27, A, 26, E, 0),
-        PINGROUP(LCSN,  DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          C, 31, E, 12, D, 20),
-        PINGROUP(LD0,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 0,  F, 0,  D, 12),
-        PINGROUP(LD1,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 1,  F, 2,  D, 12),
-        PINGROUP(LD10,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 10, F, 20, D, 12),
-        PINGROUP(LD11,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 11, F, 22, D, 12),
-        PINGROUP(LD12,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 12, F, 24, D, 12),
-        PINGROUP(LD13,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 13, F, 26, D, 12),
-        PINGROUP(LD14,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 14, F, 28, D, 12),
-        PINGROUP(LD15,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 15, F, 30, D, 12),
-        PINGROUP(LD16,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 16, G, 0,  D, 12),
-        PINGROUP(LD17,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 17, G, 2,  D, 12),
-        PINGROUP(LD2,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 2,  F, 4,  D, 12),
-        PINGROUP(LD3,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 3,  F, 6,  D, 12),
-        PINGROUP(LD4,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 4,  F, 8,  D, 12),
-        PINGROUP(LD5,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 5,  F, 10, D, 12),
-        PINGROUP(LD6,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 6,  F, 12, D, 12),
-        PINGROUP(LD7,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 7,  F, 14, D, 12),
-        PINGROUP(LD8,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 8,  F, 16, D, 12),
-        PINGROUP(LD9,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 9,  F, 18, D, 12),
-        PINGROUP(LDC,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 30, E, 14, D, 20),
-        PINGROUP(LDI,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 6,  G, 16, D, 18),
-        PINGROUP(LHP0,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 18, G, 10, D, 16),
-        PINGROUP(LHP1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 19, G, 4,  D, 14),
-        PINGROUP(LHP2,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 20, G, 6,  D, 14),
-        PINGROUP(LHS,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          D, 7,  E, 22, D, 22),
-        PINGROUP(LM0,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          C, 24, E, 26, D, 22),
-        PINGROUP(LM1,   DISPLAYA,  DISPLAYB,  RSVD,      CRT,           C, 25, E, 28, D, 22),
-        PINGROUP(LPP,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 8,  G, 14, D, 18),
-        PINGROUP(LPW0,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 3,  E, 0,  D, 20),
-        PINGROUP(LPW1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 4,  E, 2,  D, 20),
-        PINGROUP(LPW2,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 5,  E, 4,  D, 20),
-        PINGROUP(LSC0,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 27, E, 18, D, 22),
-        PINGROUP(LSC1,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          C, 28, E, 20, D, 20),
-        PINGROUP(LSCK,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          C, 29, E, 16, D, 20),
-        PINGROUP(LSDA,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 1,  E, 8,  D, 20),
-        PINGROUP(LSDI,  DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          D, 2,  E, 6,  D, 20),
-        PINGROUP(LSPI,  DISPLAYA,  DISPLAYB,  XIO,       HDMI,          D, 0,  E, 10, D, 22),
-        PINGROUP(LVP0,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 21, E, 30, D, 22),
-        PINGROUP(LVP1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 22, G, 8,  D, 16),
-        PINGROUP(LVS,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 26, E, 24, D, 22),
-        PINGROUP(OWC,   OWR,       RSVD,      RSVD,      RSVD,          A, 31, B, 8,  E, 30),
-        PINGROUP(PMC,   PWR_ON,    PWR_INTR,  RSVD,      RSVD,          A, 23, G, 18, N, -1),
-        PINGROUP(PTA,   I2C2,      HDMI,      GMI,       RSVD,          A, 24, G, 22, B, 4),
-        PINGROUP(RM,    I2C,       RSVD,      RSVD,      RSVD,          A, 25, A, 14, B, 0),
-        PINGROUP(SDB,   UARTA,     PWM,       SDIO3,     SPI2,          D, 15, D, 10, N, -1),
-        PINGROUP(SDC,   PWM,       TWC,       SDIO3,     SPI3,          B, 1,  D, 12, D, 28),
-        PINGROUP(SDD,   UARTA,     PWM,       SDIO3,     SPI3,          B, 2,  D, 14, D, 30),
-        PINGROUP(SDIO1, SDIO1,     RSVD,      UARTE,     UARTA,         A, 30, A, 30, E, 18),
-        PINGROUP(SLXA,  PCIE,      SPI4,      SDIO3,     SPI2,          B, 3,  B, 6,  B, 22),
-        PINGROUP(SLXC,  SPDIF,     SPI4,      SDIO3,     SPI2,          B, 5,  B, 10, B, 26),
-        PINGROUP(SLXD,  SPDIF,     SPI4,      SDIO3,     SPI2,          B, 6,  B, 12, B, 28),
-        PINGROUP(SLXK,  PCIE,      SPI4,      SDIO3,     SPI2,          B, 7,  B, 14, B, 30),
-        PINGROUP(SPDI,  SPDIF,     RSVD,      I2C,       SDIO2,         B, 8,  D, 8,  B, 16),
-        PINGROUP(SPDO,  SPDIF,     RSVD,      I2C,       SDIO2,         B, 9,  D, 6,  B, 18),
-        PINGROUP(SPIA,  SPI1,      SPI2,      SPI3,      GMI,           B, 10, D, 30, C, 4),
-        PINGROUP(SPIB,  SPI1,      SPI2,      SPI3,      GMI,           B, 11, D, 28, C, 6),
-        PINGROUP(SPIC,  SPI1,      SPI2,      SPI3,      GMI,           B, 12, D, 26, C, 8),
-        PINGROUP(SPID,  SPI2,      SPI1,      SPI2_ALT,  GMI,           B, 13, D, 24, C, 10),
-        PINGROUP(SPIE,  SPI2,      SPI1,      SPI2_ALT,  GMI,           B, 14, D, 22, C, 12),
-        PINGROUP(SPIF,  SPI3,      SPI1,      SPI2,      RSVD,          B, 15, D, 20, C, 14),
-        PINGROUP(SPIG,  SPI3,      SPI2,      SPI2_ALT,  I2C,           B, 16, D, 18, C, 16),
-        PINGROUP(SPIH,  SPI3,      SPI2,      SPI2_ALT,  I2C,           B, 17, D, 16, C, 18),
-        PINGROUP(UAA,   SPI3,      MIPI_HS,   UARTA,     ULPI,          B, 18, A, 0,  D, 0),
-        PINGROUP(UAB,   SPI2,      MIPI_HS,   UARTA,     ULPI,          B, 19, A, 2,  D, 2),
-        PINGROUP(UAC,   OWR,       RSVD,      RSVD,      RSVD,          B, 20, A, 4,  D, 4),
-        PINGROUP(UAD,   IRDA,      SPDIF,     UARTA,     SPI4,          B, 21, A, 6,  D, 6),
-        PINGROUP(UCA,   UARTC,     RSVD,      GMI,       RSVD,          B, 22, B, 16, D, 8),
-        PINGROUP(UCB,   UARTC,     PWM,       GMI,       RSVD,          B, 23, B, 18, D, 10),
-        PINGROUP(UDA,   SPI1,      RSVD,      UARTD,     ULPI,          D, 13, A, 8,  E, 16),
-        /* these pin groups only have pullup and pull down control */
-        PINGROUP(CK32,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 14),
-        PINGROUP(DDRC,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  D, 26),
-        PINGROUP(PMCA,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 4),
-        PINGROUP(PMCB,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 6),
-        PINGROUP(PMCC,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 8),
-        PINGROUP(PMCD,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 10),
-        PINGROUP(PMCE,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 12),
-        PINGROUP(XM2C,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  C, 30),
-        PINGROUP(XM2D,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  C, 28),
-};
+static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
+static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
 
 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@@ -256,48 +96,7 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_VI] = "VI",
         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
         [TEGRA_MUX_XIO] = "XIO",
-};
-
-struct tegra_drive_pingroup_desc {
-        const char *name;
-        s16 reg;
-};
-
-#define DRIVE_PINGROUP(pg_name, r)                              \
-        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
-                .name = #pg_name,                               \
-                .reg = r                                        \
-        }
-
-static const struct tegra_drive_pingroup_desc drive_pingroups[TEGRA_MAX_PINGROUP] = {
-        DRIVE_PINGROUP(AO1,             0x868),
-        DRIVE_PINGROUP(AO2,             0x86c),
-        DRIVE_PINGROUP(AT1,             0x870),
-        DRIVE_PINGROUP(AT2,             0x874),
-        DRIVE_PINGROUP(CDEV1,           0x878),
-        DRIVE_PINGROUP(CDEV2,           0x87c),
-        DRIVE_PINGROUP(CSUS,            0x880),
-        DRIVE_PINGROUP(DAP1,            0x884),
-        DRIVE_PINGROUP(DAP2,            0x888),
-        DRIVE_PINGROUP(DAP3,            0x88c),
-        DRIVE_PINGROUP(DAP4,            0x890),
-        DRIVE_PINGROUP(DBG,             0x894),
-        DRIVE_PINGROUP(LCD1,            0x898),
-        DRIVE_PINGROUP(LCD2,            0x89c),
-        DRIVE_PINGROUP(SDMMC2,  0x8a0),
-        DRIVE_PINGROUP(SDMMC3,  0x8a4),
-        DRIVE_PINGROUP(SPI,             0x8a8),
-        DRIVE_PINGROUP(UAA,             0x8ac),
-        DRIVE_PINGROUP(UAB,             0x8b0),
-        DRIVE_PINGROUP(UART2,           0x8b4),
-        DRIVE_PINGROUP(UART3,           0x8b8),
-        DRIVE_PINGROUP(VI1,             0x8bc),
-        DRIVE_PINGROUP(VI2,             0x8c0),
-        DRIVE_PINGROUP(XM2A,            0x8c4),
-        DRIVE_PINGROUP(XM2C,            0x8c8),
-        DRIVE_PINGROUP(XM2D,            0x8cc),
-        DRIVE_PINGROUP(XM2CLK,  0x8d0),
-        DRIVE_PINGROUP(MEMCOMP, 0x8d4),
+        [TEGRA_MUX_SAFE] = "<safe>",
 };
 
 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
@@ -381,22 +180,27 @@ static inline void pg_writel(unsigned long value, unsigned long offset)
         writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
 }
 
-int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func)
+static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
 {
         int mux = -1;
         int i;
         unsigned long reg;
         unsigned long flags;
+        enum tegra_pingroup pg = config->pingroup;
+        enum tegra_mux_func func = config->func;
 
         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
                 return -ERANGE;
 
-        if (pingroups[pg].mux_reg == REG_N)
+        if (pingroups[pg].mux_reg < 0)
                 return -EINVAL;
 
         if (func < 0)
                 return -ERANGE;
 
+        if (func == TEGRA_MUX_SAFE)
+                func = pingroups[pg].func_safe;
+
         if (func & TEGRA_MUX_RSVD) {
                 mux = func & 0x3;
         } else {
@@ -413,10 +217,10 @@ int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func)
 
         spin_lock_irqsave(&mux_lock, flags);
 
-        reg = pg_readl(TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg));
+        reg = pg_readl(pingroups[pg].mux_reg);
         reg &= ~(0x3 << pingroups[pg].mux_bit);
         reg |= mux << pingroups[pg].mux_bit;
-        pg_writel(reg, TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg));
+        pg_writel(reg, pingroups[pg].mux_reg);
 
         spin_unlock_irqrestore(&mux_lock, flags);
 
@@ -432,16 +236,16 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
                 return -ERANGE;
 
-        if (pingroups[pg].tri_reg == REG_N)
+        if (pingroups[pg].tri_reg < 0)
                 return -EINVAL;
 
         spin_lock_irqsave(&mux_lock, flags);
 
-        reg = pg_readl(TEGRA_TRI_STATE(pingroups[pg].tri_reg));
+        reg = pg_readl(pingroups[pg].tri_reg);
         reg &= ~(0x1 << pingroups[pg].tri_bit);
         if (tristate)
                 reg |= 1 << pingroups[pg].tri_bit;
-        pg_writel(reg, TEGRA_TRI_STATE(pingroups[pg].tri_reg));
+        pg_writel(reg, pingroups[pg].tri_reg);
 
         spin_unlock_irqrestore(&mux_lock, flags);
 
@@ -457,7 +261,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
                 return -ERANGE;
 
-        if (pingroups[pg].pupd_reg == REG_N)
+        if (pingroups[pg].pupd_reg < 0)
                 return -EINVAL;
 
         if (pupd != TEGRA_PUPD_NORMAL &&
@@ -468,38 +272,39 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
 
         spin_lock_irqsave(&mux_lock, flags);
 
-        reg = pg_readl(TEGRA_PP_PU_PD(pingroups[pg].pupd_reg));
+        reg = pg_readl(pingroups[pg].pupd_reg);
         reg &= ~(0x3 << pingroups[pg].pupd_bit);
         reg |= pupd << pingroups[pg].pupd_bit;
-        pg_writel(reg, TEGRA_PP_PU_PD(pingroups[pg].pupd_reg));
+        pg_writel(reg, pingroups[pg].pupd_reg);
 
         spin_unlock_irqrestore(&mux_lock, flags);
 
         return 0;
 }
 
-void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
-                                 enum tegra_mux_func func,
-                                 enum tegra_pullupdown pupd,
-                                 enum tegra_tristate tristate)
+static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
 {
+        enum tegra_pingroup pingroup = config->pingroup;
+        enum tegra_mux_func func     = config->func;
+        enum tegra_pullupdown pupd   = config->pupd;
+        enum tegra_tristate tristate = config->tristate;
         int err;
 
-        if (pingroups[pingroup].mux_reg != REG_N) {
-                err = tegra_pinmux_set_func(pingroup, func);
+        if (pingroups[pingroup].mux_reg >= 0) {
+                err = tegra_pinmux_set_func(config);
                 if (err < 0)
                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
                                pingroup_name(pingroup), func_name(func), err);
         }
 
-        if (pingroups[pingroup].pupd_reg != REG_N) {
+        if (pingroups[pingroup].pupd_reg >= 0) {
                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
                 if (err < 0)
                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
                                pingroup_name(pingroup), pupd_name(pupd), err);
         }
 
-        if (pingroups[pingroup].tri_reg != REG_N) {
+        if (pingroups[pingroup].tri_reg >= 0) {
                 err = tegra_pinmux_set_tristate(pingroup, tristate);
                 if (err < 0)
                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
@@ -507,17 +312,12 @@ void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
         }
 }
 
-
-
-void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len)
+void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
 {
         int i;
 
         for (i = 0; i < len; i++)
-                tegra_pinmux_config_pingroup(config[i].pingroup,
-                                             config[i].func,
-                                             config[i].pupd,
-                                             config[i].tristate);
+                tegra_pinmux_config_pingroup(&config[i]);
 }
 
 static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
@@ -784,6 +584,86 @@ void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
                                                      config[i].slew_falling);
 }
 
+void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
+        int len)
+{
+        int i;
+        struct tegra_pingroup_config c;
+
+        for (i = 0; i < len; i++) {
+                int err;
+                c = config[i];
+                if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
+                        WARN_ON(1);
+                        continue;
+                }
+                c.func = pingroups[c.pingroup].func_safe;
+                err = tegra_pinmux_set_func(&c);
+                if (err < 0)
+                        pr_err("%s: tegra_pinmux_set_func returned %d setting "
+                               "%s to %s\n", __func__, err,
+                               pingroup_name(c.pingroup), func_name(c.func));
+        }
+}
+
+void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
+        int len)
+{
+        int i;
+
+        for (i = 0; i < len; i++) {
+                int err;
+                if (config[i].pingroup < 0 ||
+                    config[i].pingroup >= TEGRA_MAX_PINGROUP) {
+                        WARN_ON(1);
+                        continue;
+                }
+                err = tegra_pinmux_set_func(&config[i]);
+                if (err < 0)
+                        pr_err("%s: tegra_pinmux_set_func returned %d setting "
+                               "%s to %s\n", __func__, err,
+                               pingroup_name(config[i].pingroup),
+                               func_name(config[i].func));
+        }
+}
+
+void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
+        int len, enum tegra_tristate tristate)
+{
+        int i;
+        int err;
+        enum tegra_pingroup pingroup;
+
+        for (i = 0; i < len; i++) {
+                pingroup = config[i].pingroup;
+                if (pingroups[pingroup].tri_reg >= 0) {
+                        err = tegra_pinmux_set_tristate(pingroup, tristate);
+                        if (err < 0)
+                                pr_err("pinmux: can't set pingroup %s tristate"
+                                        " to %s: %d\n", pingroup_name(pingroup),
+                                        tri_name(tristate), err);
+                }
+        }
+}
+
+void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
+        int len, enum tegra_pullupdown pupd)
+{
+        int i;
+        int err;
+        enum tegra_pingroup pingroup;
+
+        for (i = 0; i < len; i++) {
+                pingroup = config[i].pingroup;
+                if (pingroups[pingroup].pupd_reg >= 0) {
+                        err = tegra_pinmux_set_pullupdown(pingroup, pupd);
+                        if (err < 0)
+                                pr_err("pinmux: can't set pingroup %s pullupdown"
+                                        " to %s: %d\n", pingroup_name(pingroup),
+                                        pupd_name(pupd), err);
+                }
+        }
+}
 
 #ifdef  CONFIG_DEBUG_FS
 
@@ -812,11 +692,11 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
                 len = strlen(pingroups[i].name);
                 dbg_pad_field(s, 5 - len);
 
-                if (pingroups[i].mux_reg == REG_N) {
+                if (pingroups[i].mux_reg < 0) {
                         seq_printf(s, "TEGRA_MUX_NONE");
                         len = strlen("NONE");
                 } else {
-                        mux = (pg_readl(TEGRA_PP_MUX_CTL(pingroups[i].mux_reg)) >>
+                        mux = (pg_readl(pingroups[i].mux_reg) >>
                                pingroups[i].mux_bit) & 0x3;
                         if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
@@ -829,21 +709,21 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
                 }
                 dbg_pad_field(s, 13-len);
 
-                if (pingroups[i].mux_reg == REG_N) {
+                if (pingroups[i].pupd_reg < 0) {
                         seq_printf(s, "TEGRA_PUPD_NORMAL");
                         len = strlen("NORMAL");
                 } else {
-                        pupd = (pg_readl(TEGRA_PP_PU_PD(pingroups[i].pupd_reg)) >>
+                        pupd = (pg_readl(pingroups[i].pupd_reg) >>
                                 pingroups[i].pupd_bit) & 0x3;
                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
                         len = strlen(pupd_name(pupd));
                 }
                 dbg_pad_field(s, 9 - len);
 
-                if (pingroups[i].tri_reg == REG_N) {
+                if (pingroups[i].tri_reg < 0) {
                         seq_printf(s, "TEGRA_TRI_NORMAL");
                 } else {
-                        tri = (pg_readl(TEGRA_TRI_STATE(pingroups[i].tri_reg)) >>
+                        tri = (pg_readl(pingroups[i].tri_reg) >>
                                pingroups[i].tri_bit) & 0x1;
 
                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 426163231ff..ae3b308e22a 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -30,14 +30,21 @@
 #include <mach/iomap.h>
 
 #include "clock.h"
+#include "fuse.h"
+#include "tegra2_dvfs.h"
 
 #define RST_DEVICES                     0x004
 #define RST_DEVICES_SET                 0x300
 #define RST_DEVICES_CLR                 0x304
+#define RST_DEVICES_NUM                 3
 
 #define CLK_OUT_ENB                     0x010
 #define CLK_OUT_ENB_SET                 0x320
 #define CLK_OUT_ENB_CLR                 0x324
+#define CLK_OUT_ENB_NUM                 3
+
+#define CLK_MASK_ARM                    0x44
+#define MISC_CLK_ENB                    0x48
 
 #define OSC_CTRL                        0x50
 #define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
@@ -45,6 +52,7 @@
 #define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
 #define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
 #define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
+#define OSC_CTRL_MASK                   0x3f2
 
 #define OSC_FREQ_DET                    0x58
 #define OSC_FREQ_DET_TRIG               (1<<31)
@@ -53,10 +61,17 @@
 #define OSC_FREQ_DET_BUSY               (1<<31)
 #define OSC_FREQ_DET_CNT_MASK           0xFFFF
 
+#define PERIPH_CLK_SOURCE_I2S1          0x100
+#define PERIPH_CLK_SOURCE_EMC           0x19c
+#define PERIPH_CLK_SOURCE_OSC           0x1fc
+#define PERIPH_CLK_SOURCE_NUM \
+        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
+
 #define PERIPH_CLK_SOURCE_MASK          (3<<30)
 #define PERIPH_CLK_SOURCE_SHIFT         30
 #define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
-#define PERIPH_CLK_SOURCE_DIV_MASK      0xFF
+#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
+#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
 #define PERIPH_CLK_SOURCE_DIV_SHIFT     0
 
 #define PLL_BASE                        0x0
@@ -79,8 +94,9 @@
 #define PLL_OUT_RESET_DISABLE           (1<<0)
 
 #define PLL_MISC(c)                     (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+#define PLL_MISC_LOCK_ENABLE(c)         (((c)->flags & PLLU) ? (1<<22) : (1<<18))
+
 #define PLL_MISC_DCCON_SHIFT            20
-#define PLL_MISC_LOCK_ENABLE            (1<<18)
 #define PLL_MISC_CPCON_SHIFT            8
 #define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
 #define PLL_MISC_LFCON_SHIFT            4
@@ -88,10 +104,14 @@
 #define PLL_MISC_VCOCON_SHIFT           0
 #define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
 
+#define PLLU_BASE_POST_DIV              (1<<20)
+
 #define PLLD_MISC_CLKENABLE             (1<<30)
 #define PLLD_MISC_DIV_RST               (1<<23)
 #define PLLD_MISC_DCCON_SHIFT           12
 
+#define PLLE_MISC_READY                 (1 << 15)
+
 #define PERIPH_CLK_TO_ENB_REG(c)        ((c->clk_num / 32) * 4)
 #define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->clk_num / 32) * 8)
 #define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->clk_num % 32))
@@ -143,30 +163,37 @@ unsigned long clk_measure_input_freq(void)
         }
 }
 
-static int clk_div71_get_divider(struct clk *c, unsigned long rate)
+static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
 {
-        unsigned long divider_u71;
+        s64 divider_u71 = parent_rate * 2;
+        divider_u71 += rate - 1;
+        do_div(divider_u71, rate);
 
-        divider_u71 = DIV_ROUND_UP(c->rate * 2, rate);
+        if (divider_u71 - 2 < 0)
+                return 0;
 
-        if (divider_u71 - 2 > 255 || divider_u71 - 2 < 0)
+        if (divider_u71 - 2 > 255)
                 return -EINVAL;
 
         return divider_u71 - 2;
 }
 
-static unsigned long tegra2_clk_recalculate_rate(struct clk *c)
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
 {
-        unsigned long rate;
-        rate = c->parent->rate;
+        s64 divider_u16;
 
-        if (c->mul != 0 && c->div != 0)
-                c->rate = rate * c->mul / c->div;
-        else
-                c->rate = rate;
-        return c->rate;
-}
+        divider_u16 = parent_rate;
+        divider_u16 += rate - 1;
+        do_div(divider_u16, rate);
+
+        if (divider_u16 - 1 < 0)
+                return 0;
 
+        if (divider_u16 - 1 > 255)
+                return -EINVAL;
+
+        return divider_u16 - 1;
+}
 
 /* clk_m functions */
 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
@@ -244,7 +271,6 @@ static void tegra2_super_clk_init(struct clk *c)
         }
         BUG_ON(sel->input == NULL);
         c->parent = sel->input;
-        tegra2_clk_recalculate_rate(c);
 }
 
 static int tegra2_super_clk_enable(struct clk *c)
@@ -266,6 +292,7 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
         u32 val;
         const struct clk_mux_sel *sel;
         int shift;
+
         val = clk_readl(c->reg + SUPER_CLK_MUX);;
         BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
                 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
@@ -273,11 +300,18 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
                 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
         for (sel = c->inputs; sel->input != NULL; sel++) {
                 if (sel->input == p) {
-                        clk_reparent(c, p);
                         val &= ~(SUPER_SOURCE_MASK << shift);
                         val |= sel->value << shift;
+
+                        if (c->refcnt)
+                                clk_enable_locked(p);
+
                         clk_writel(val, c->reg);
-                        c->rate = c->parent->rate;
+
+                        if (c->refcnt && c->parent)
+                                clk_disable_locked(c->parent);
+
+                        clk_reparent(c, p);
                         return 0;
                 }
         }
@@ -289,7 +323,61 @@ static struct clk_ops tegra_super_ops = {
         .enable                 = tegra2_super_clk_enable,
         .disable                = tegra2_super_clk_disable,
         .set_parent             = tegra2_super_clk_set_parent,
-        .recalculate_rate       = tegra2_clk_recalculate_rate,
+};
+
+/* virtual cpu clock functions */
+/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
+   To change the frequency of these clocks, the parent pll may need to be
+   reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
+   and then the clock moved back to the pll.  To hide this sequence, a virtual
+   clock handles it.
+ */
+static void tegra2_cpu_clk_init(struct clk *c)
+{
+}
+
+static int tegra2_cpu_clk_enable(struct clk *c)
+{
+        return 0;
+}
+
+static void tegra2_cpu_clk_disable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        /* oops - don't disable the CPU clock! */
+        BUG();
+}
+
+static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        int ret;
+        ret = clk_set_parent_locked(c->parent, c->backup);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock %s\n", c->backup->name);
+                return ret;
+        }
+
+        ret = clk_set_rate_locked(c->main, rate);
+        if (ret) {
+                pr_err("Failed to change cpu pll to %lu\n", rate);
+                return ret;
+        }
+
+        ret = clk_set_parent_locked(c->parent, c->main);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock %s\n", c->main->name);
+                return ret;
+        }
+
+        return 0;
+}
+
+static struct clk_ops tegra_cpu_ops = {
+        .init     = tegra2_cpu_clk_init,
+        .enable   = tegra2_cpu_clk_enable,
+        .disable  = tegra2_cpu_clk_disable,
+        .set_rate = tegra2_cpu_clk_set_rate,
 };
 
 /* bus clock functions */
@@ -299,7 +387,6 @@ static void tegra2_bus_clk_init(struct clk *c)
         c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
         c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
         c->mul = 1;
-        tegra2_clk_recalculate_rate(c);
 }
 
 static int tegra2_bus_clk_enable(struct clk *c)
@@ -340,27 +427,15 @@ static struct clk_ops tegra_bus_ops = {
         .enable                 = tegra2_bus_clk_enable,
         .disable                = tegra2_bus_clk_disable,
         .set_rate               = tegra2_bus_clk_set_rate,
-        .recalculate_rate       = tegra2_clk_recalculate_rate,
 };
 
 /* PLL Functions */
-static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c)
-{
-        u64 rate;
-        rate = c->parent->rate;
-        rate *= c->n;
-        do_div(rate, c->m);
-        if (c->p == 2)
-                rate >>= 1;
-        c->rate = rate;
-        return c->rate;
-}
-
 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
 {
         ktime_t before;
 
         before = ktime_get();
+
         while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
                 if (ktime_us_delta(ktime_get(), before) > 5000) {
                         pr_err("Timed out waiting for lock bit on pll %s",
@@ -380,24 +455,19 @@ static void tegra2_pll_clk_init(struct clk *c)
 
         if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
                 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
-                c->n = 1;
-                c->m = 0;
-                c->p = 1;
+                c->mul = 1;
+                c->div = 1;
         } else if (val & PLL_BASE_BYPASS) {
-                c->n = 1;
-                c->m = 1;
-                c->p = 1;
+                c->mul = 1;
+                c->div = 1;
         } else {
-                c->n = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->m = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                c->p = (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
         }
-
-        val = clk_readl(c->reg + PLL_MISC(c));
-        if (c->flags & PLL_HAS_CPCON)
-                c->cpcon = (val & PLL_MISC_CPCON_MASK) >> PLL_MISC_CPCON_SHIFT;
-
-        tegra2_pll_clk_recalculate_rate(c);
 }
 
 static int tegra2_pll_clk_enable(struct clk *c)
@@ -411,7 +481,7 @@ static int tegra2_pll_clk_enable(struct clk *c)
         clk_writel(val, c->reg + PLL_BASE);
 
         val = clk_readl(c->reg + PLL_MISC(c));
-        val |= PLL_MISC_LOCK_ENABLE;
+        val |= PLL_MISC_LOCK_ENABLE(c);
         clk_writel(val, c->reg + PLL_MISC(c));
 
         tegra2_pll_clk_wait_for_lock(c);
@@ -441,33 +511,36 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
         input_rate = c->parent->rate;
         for (sel = c->pll_table; sel->input_rate != 0; sel++) {
                 if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        c->n = sel->n;
-                        c->m = sel->m;
-                        c->p = sel->p;
-                        c->cpcon = sel->cpcon;
+                        c->mul = sel->n;
+                        c->div = sel->m * sel->p;
 
                         val = clk_readl(c->reg + PLL_BASE);
                         if (c->flags & PLL_FIXED)
                                 val |= PLL_BASE_OVERRIDE;
                         val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
                                  PLL_BASE_DIVM_MASK);
-                        val |= (c->m << PLL_BASE_DIVM_SHIFT) |
-                                (c->n << PLL_BASE_DIVN_SHIFT);
-                        BUG_ON(c->p > 2);
-                        if (c->p == 2)
-                                val |= 1 << PLL_BASE_DIVP_SHIFT;
+                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+                                (sel->n << PLL_BASE_DIVN_SHIFT);
+                        BUG_ON(sel->p < 1 || sel->p > 2);
+                        if (c->flags & PLLU) {
+                                if (sel->p == 1)
+                                        val |= PLLU_BASE_POST_DIV;
+                        } else {
+                                if (sel->p == 2)
+                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
+                        }
                         clk_writel(val, c->reg + PLL_BASE);
 
                         if (c->flags & PLL_HAS_CPCON) {
-                                val = c->cpcon << PLL_MISC_CPCON_SHIFT;
-                                val |= PLL_MISC_LOCK_ENABLE;
+                                val = clk_readl(c->reg + PLL_MISC(c));
+                                val &= ~PLL_MISC_CPCON_MASK;
+                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
                                 clk_writel(val, c->reg + PLL_MISC(c));
                         }
 
                         if (c->state == ON)
                                 tegra2_pll_clk_enable(c);
 
-                        c->rate = rate;
                         return 0;
                 }
         }
@@ -479,7 +552,46 @@ static struct clk_ops tegra_pll_ops = {
         .enable                 = tegra2_pll_clk_enable,
         .disable                = tegra2_pll_clk_disable,
         .set_rate               = tegra2_pll_clk_set_rate,
-        .recalculate_rate       = tegra2_pll_clk_recalculate_rate,
+};
+
+static void tegra2_pllx_clk_init(struct clk *c)
+{
+        tegra2_pll_clk_init(c);
+
+        if (tegra_sku_id() == 7)
+                c->max_rate = 750000000;
+}
+
+static struct clk_ops tegra_pllx_ops = {
+        .init     = tegra2_pllx_clk_init,
+        .enable   = tegra2_pll_clk_enable,
+        .disable  = tegra2_pll_clk_disable,
+        .set_rate = tegra2_pll_clk_set_rate,
+};
+
+static int tegra2_plle_clk_enable(struct clk *c)
+{
+        u32 val;
+
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        mdelay(1);
+
+        val = clk_readl(c->reg + PLL_BASE);
+        if (!(val & PLLE_MISC_READY))
+                return -EBUSY;
+
+        val = clk_readl(c->reg + PLL_BASE);
+        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
+        clk_writel(val, c->reg + PLL_BASE);
+
+        return 0;
+}
+
+static struct clk_ops tegra_plle_ops = {
+        .init       = tegra2_pll_clk_init,
+        .enable     = tegra2_plle_clk_enable,
+        .set_rate   = tegra2_pll_clk_set_rate,
 };
 
 /* Clock divider ops */
@@ -503,8 +615,6 @@ static void tegra2_pll_div_clk_init(struct clk *c)
                 c->div = 1;
                 c->mul = 1;
         }
-
-        tegra2_clk_recalculate_rate(c);
 }
 
 static int tegra2_pll_div_clk_enable(struct clk *c)
@@ -565,7 +675,7 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
         int divider_u71;
         pr_debug("%s: %s %lu\n", __func__, c->name, rate);
         if (c->flags & DIV_U71) {
-                divider_u71 = clk_div71_get_divider(c->parent, rate);
+                divider_u71 = clk_div71_get_divider(c->parent->rate, rate);
                 if (divider_u71 >= 0) {
                         val = clk_readl(c->reg);
                         new_val = val >> c->reg_shift;
@@ -580,25 +690,37 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
                         clk_writel(val, c->reg);
                         c->div = divider_u71 + 2;
                         c->mul = 2;
-                        tegra2_clk_recalculate_rate(c);
                         return 0;
                 }
         } else if (c->flags & DIV_2) {
-                if (c->parent->rate == rate * 2) {
-                        c->rate = rate;
+                if (c->parent->rate == rate * 2)
                         return 0;
-                }
         }
         return -EINVAL;
 }
 
+static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+{
+        int divider;
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(c->parent->rate, rate);
+                if (divider < 0)
+                        return divider;
+                return c->parent->rate * 2 / (divider + 2);
+        } else if (c->flags & DIV_2) {
+                return c->parent->rate / 2;
+        }
+        return -EINVAL;
+}
 
 static struct clk_ops tegra_pll_div_ops = {
         .init                   = tegra2_pll_div_clk_init,
         .enable                 = tegra2_pll_div_clk_enable,
         .disable                = tegra2_pll_div_clk_disable,
         .set_rate               = tegra2_pll_div_clk_set_rate,
-        .recalculate_rate       = tegra2_clk_recalculate_rate,
+        .round_rate             = tegra2_pll_div_clk_round_rate,
 };
 
 /* Periph clk ops */
@@ -621,9 +743,13 @@ static void tegra2_periph_clk_init(struct clk *c)
         }
 
         if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIV_MASK;
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
                 c->div = divu71 + 2;
                 c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
         } else {
                 c->div = 1;
                 c->mul = 1;
@@ -637,7 +763,6 @@ static void tegra2_periph_clk_init(struct clk *c)
                 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
                                 PERIPH_CLK_TO_ENB_BIT(c))
                         c->state = OFF;
-        tegra2_clk_recalculate_rate(c);
 }
 
 static int tegra2_periph_clk_enable(struct clk *c)
@@ -692,12 +817,19 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
         pr_debug("%s: %s %s\n", __func__, c->name, p->name);
         for (sel = c->inputs; sel->input != NULL; sel++) {
                 if (sel->input == p) {
-                        clk_reparent(c, p);
                         val = clk_readl(c->reg);
                         val &= ~PERIPH_CLK_SOURCE_MASK;
                         val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
+
+                        if (c->refcnt)
+                                clk_enable_locked(p);
+
                         clk_writel(val, c->reg);
-                        c->rate = c->parent->rate;
+
+                        if (c->refcnt && c->parent)
+                                clk_disable_locked(c->parent);
+
+                        clk_reparent(c, p);
                         return 0;
                 }
         }
@@ -708,20 +840,55 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
 {
         u32 val;
-        int divider_u71;
+        int divider;
         pr_debug("%s: %lu\n", __func__, rate);
         if (c->flags & DIV_U71) {
-                divider_u71 = clk_div71_get_divider(c->parent, rate);
-                if (divider_u71 >= 0) {
+                divider = clk_div71_get_divider(c->parent->rate, rate);
+                if (divider >= 0) {
                         val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIV_MASK;
-                        val |= divider_u71;
+                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
+                        val |= divider;
                         clk_writel(val, c->reg);
-                        c->div = divider_u71 + 2;
+                        c->div = divider + 2;
                         c->mul = 2;
-                        tegra2_clk_recalculate_rate(c);
                         return 0;
                 }
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(c->parent->rate, rate);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
+                        val |= divider;
+                        clk_writel(val, c->reg);
+                        c->div = divider + 1;
+                        c->mul = 1;
+                        return 0;
+                }
+        } else if (c->parent->rate <= rate) {
+                c->div = 1;
+                c->mul = 1;
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static long tegra2_periph_clk_round_rate(struct clk *c,
+        unsigned long rate)
+{
+        int divider;
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(c->parent->rate, rate);
+                if (divider < 0)
+                        return divider;
+
+                return c->parent->rate * 2 / (divider + 2);
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(c->parent->rate, rate);
+                if (divider < 0)
+                        return divider;
+                return c->parent->rate / (divider + 1);
         }
         return -EINVAL;
 }
@@ -732,7 +899,7 @@ static struct clk_ops tegra_periph_clk_ops = {
         .disable                = &tegra2_periph_clk_disable,
         .set_parent             = &tegra2_periph_clk_set_parent,
         .set_rate               = &tegra2_periph_clk_set_rate,
-        .recalculate_rate       = &tegra2_clk_recalculate_rate,
+        .round_rate             = &tegra2_periph_clk_round_rate,
 };
 
 /* Clock doubler ops */
@@ -744,21 +911,108 @@ static void tegra2_clk_double_init(struct clk *c)
         if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
                         PERIPH_CLK_TO_ENB_BIT(c)))
                 c->state = OFF;
-        tegra2_clk_recalculate_rate(c);
 };
 
+static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
+{
+        if (rate != 2 * c->parent->rate)
+                return -EINVAL;
+        c->mul = 2;
+        c->div = 1;
+        return 0;
+}
+
 static struct clk_ops tegra_clk_double_ops = {
         .init                   = &tegra2_clk_double_init,
         .enable                 = &tegra2_periph_clk_enable,
         .disable                = &tegra2_periph_clk_disable,
-        .recalculate_rate       = &tegra2_clk_recalculate_rate,
+        .set_rate               = &tegra2_clk_double_set_rate,
+};
+
+static void tegra2_audio_sync_clk_init(struct clk *c)
+{
+        int source;
+        const struct clk_mux_sel *sel;
+        u32 val = clk_readl(c->reg);
+        c->state = (val & (1<<4)) ? OFF : ON;
+        source = val & 0xf;
+        for (sel = c->inputs; sel->input != NULL; sel++)
+                if (sel->value == source)
+                        break;
+        BUG_ON(sel->input == NULL);
+        c->parent = sel->input;
+}
+
+static int tegra2_audio_sync_clk_enable(struct clk *c)
+{
+        clk_writel(0, c->reg);
+        return 0;
+}
+
+static void tegra2_audio_sync_clk_disable(struct clk *c)
+{
+        clk_writel(1, c->reg);
+}
+
+static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        const struct clk_mux_sel *sel;
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        val = clk_readl(c->reg);
+                        val &= ~0xf;
+                        val |= sel->value;
+
+                        if (c->refcnt)
+                                clk_enable_locked(p);
+
+                        clk_writel(val, c->reg);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable_locked(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        unsigned long parent_rate;
+        if (!c->parent) {
+                pr_err("%s: clock has no parent\n", __func__);
+                return -EINVAL;
+        }
+        parent_rate = c->parent->rate;
+        if (rate != parent_rate) {
+                pr_err("%s: %s/%ld differs from parent %s/%ld\n",
+                        __func__,
+                        c->name, rate,
+                        c->parent->name, parent_rate);
+                return -EINVAL;
+        }
+        c->rate = parent_rate;
+        return 0;
+}
+
+static struct clk_ops tegra_audio_sync_clk_ops = {
+        .init       = tegra2_audio_sync_clk_init,
+        .enable     = tegra2_audio_sync_clk_enable,
+        .disable    = tegra2_audio_sync_clk_disable,
+        .set_rate   = tegra2_audio_sync_clk_set_rate,
+        .set_parent = tegra2_audio_sync_clk_set_parent,
 };
 
 /* Clock definitions */
 static struct clk tegra_clk_32k = {
         .name = "clk_32k",
-        .rate = 32678,
+        .rate = 32768,
         .ops  = NULL,
+        .max_rate = 32768,
 };
 
 static struct clk_pll_table tegra_pll_s_table[] = {
@@ -782,6 +1036,7 @@ static struct clk tegra_pll_s = {
         .vco_min   = 12000000,
         .vco_max   = 26000000,
         .pll_table = tegra_pll_s_table,
+        .max_rate  = 26000000,
 };
 
 static struct clk_mux_sel tegra_clk_m_sel[] = {
@@ -797,6 +1052,7 @@ static struct clk tegra_clk_m = {
         .reg       = 0x1fc,
         .reg_mask  = (1<<28),
         .reg_shift = 28,
+        .max_rate  = 26000000,
 };
 
 static struct clk_pll_table tegra_pll_c_table[] = {
@@ -816,6 +1072,7 @@ static struct clk tegra_pll_c = {
         .vco_min   = 20000000,
         .vco_max   = 1400000000,
         .pll_table = tegra_pll_c_table,
+        .max_rate  = 600000000,
 };
 
 static struct clk tegra_pll_c_out1 = {
@@ -825,9 +1082,18 @@ static struct clk tegra_pll_c_out1 = {
         .parent    = &tegra_pll_c,
         .reg       = 0x84,
         .reg_shift = 0,
+        .max_rate  = 600000000,
 };
 
 static struct clk_pll_table tegra_pll_m_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
@@ -844,6 +1110,7 @@ static struct clk tegra_pll_m = {
         .vco_min   = 20000000,
         .vco_max   = 1200000000,
         .pll_table = tegra_pll_m_table,
+        .max_rate  = 800000000,
 };
 
 static struct clk tegra_pll_m_out1 = {
@@ -853,6 +1120,7 @@ static struct clk tegra_pll_m_out1 = {
         .parent    = &tegra_pll_m,
         .reg       = 0x94,
         .reg_shift = 0,
+        .max_rate  = 600000000,
 };
 
 static struct clk_pll_table tegra_pll_p_table[] = {
@@ -880,6 +1148,7 @@ static struct clk tegra_pll_p = {
         .vco_min   = 20000000,
         .vco_max   = 1400000000,
         .pll_table = tegra_pll_p_table,
+        .max_rate  = 432000000,
 };
 
 static struct clk tegra_pll_p_out1 = {
@@ -889,6 +1158,7 @@ static struct clk tegra_pll_p_out1 = {
         .parent    = &tegra_pll_p,
         .reg       = 0xa4,
         .reg_shift = 0,
+        .max_rate  = 432000000,
 };
 
 static struct clk tegra_pll_p_out2 = {
@@ -898,6 +1168,7 @@ static struct clk tegra_pll_p_out2 = {
         .parent    = &tegra_pll_p,
         .reg       = 0xa4,
         .reg_shift = 16,
+        .max_rate  = 432000000,
 };
 
 static struct clk tegra_pll_p_out3 = {
@@ -907,6 +1178,7 @@ static struct clk tegra_pll_p_out3 = {
         .parent    = &tegra_pll_p,
         .reg       = 0xa8,
         .reg_shift = 0,
+        .max_rate  = 432000000,
 };
 
 static struct clk tegra_pll_p_out4 = {
@@ -916,6 +1188,7 @@ static struct clk tegra_pll_p_out4 = {
         .parent    = &tegra_pll_p,
         .reg       = 0xa8,
         .reg_shift = 16,
+        .max_rate  = 432000000,
 };
 
 static struct clk_pll_table tegra_pll_a_table[] = {
@@ -923,6 +1196,7 @@ static struct clk_pll_table tegra_pll_a_table[] = {
         { 28800000, 73728000, 64, 25, 1, 1},
         { 28800000, 11289600, 49, 25, 1, 1},
         { 28800000, 12288000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
         { 0, 0, 0, 0, 0, 0 },
 };
 
@@ -939,6 +1213,7 @@ static struct clk tegra_pll_a = {
         .vco_min   = 20000000,
         .vco_max   = 1400000000,
         .pll_table = tegra_pll_a_table,
+        .max_rate  = 56448000,
 };
 
 static struct clk tegra_pll_a_out0 = {
@@ -948,6 +1223,7 @@ static struct clk tegra_pll_a_out0 = {
         .parent    = &tegra_pll_a,
         .reg       = 0xb4,
         .reg_shift = 0,
+        .max_rate  = 56448000,
 };
 
 static struct clk_pll_table tegra_pll_d_table[] = {
@@ -971,6 +1247,7 @@ static struct clk tegra_pll_d = {
         .vco_min   = 40000000,
         .vco_max   = 1000000000,
         .pll_table = tegra_pll_d_table,
+        .max_rate  = 1000000000,
 };
 
 static struct clk tegra_pll_d_out0 = {
@@ -978,19 +1255,20 @@ static struct clk tegra_pll_d_out0 = {
         .ops       = &tegra_pll_div_ops,
         .flags     = DIV_2 | PLLD,
         .parent    = &tegra_pll_d,
+        .max_rate  = 500000000,
 };
 
 static struct clk_pll_table tegra_pll_u_table[] = {
-        { 12000000, 480000000, 960, 12, 1, 0},
-        { 13000000, 480000000, 960, 13, 1, 0},
-        { 19200000, 480000000, 200, 4,  1, 0},
-        { 26000000, 480000000, 960, 26, 1, 0},
+        { 12000000, 480000000, 960, 12, 2, 0},
+        { 13000000, 480000000, 960, 13, 2, 0},
+        { 19200000, 480000000, 200, 4,  2, 0},
+        { 26000000, 480000000, 960, 26, 2, 0},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct clk tegra_pll_u = {
         .name      = "pll_u",
-        .flags     = 0,
+        .flags     = PLLU,
         .ops       = &tegra_pll_ops,
         .reg       = 0xc0,
         .input_min = 2000000,
@@ -1001,24 +1279,59 @@ static struct clk tegra_pll_u = {
         .vco_min   = 480000000,
         .vco_max   = 960000000,
         .pll_table = tegra_pll_u_table,
+        .max_rate  = 480000000,
 };
 
 static struct clk_pll_table tegra_pll_x_table[] = {
+        /* 1 GHz */
         { 12000000, 1000000000, 1000, 12, 1, 12},
         { 13000000, 1000000000, 1000, 13, 1, 12},
         { 19200000, 1000000000, 625,  12, 1, 8},
         { 26000000, 1000000000, 1000, 26, 1, 12},
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
+
+        /* 912 MHz */
+        { 12000000, 912000000,  912,  12, 1, 12},
+        { 13000000, 912000000,  912,  13, 1, 12},
+        { 19200000, 912000000,  760,  16, 1, 8},
+        { 26000000, 912000000,  912,  26, 1, 12},
+
+        /* 816 MHz */
+        { 12000000, 816000000,  816,  12, 1, 12},
+        { 13000000, 816000000,  816,  13, 1, 12},
+        { 19200000, 816000000,  680,  16, 1, 8},
+        { 26000000, 816000000,  816,  26, 1, 12},
+
+        /* 760 MHz */
+        { 12000000, 760000000,  760,  12, 1, 12},
+        { 13000000, 760000000,  760,  13, 1, 12},
+        { 19200000, 760000000,  950,  24, 1, 8},
+        { 26000000, 760000000,  760,  26, 1, 12},
+
+        /* 608 MHz */
+        { 12000000, 608000000,  760,  12, 1, 12},
+        { 13000000, 608000000,  760,  13, 1, 12},
+        { 19200000, 608000000,  380,  12, 1, 8},
+        { 26000000, 608000000,  760,  26, 1, 12},
+
+        /* 456 MHz */
+        { 12000000, 456000000,  456,  12, 1, 12},
+        { 13000000, 456000000,  456,  13, 1, 12},
+        { 19200000, 456000000,  380,  16, 1, 8},
+        { 26000000, 456000000,  456,  26, 1, 12},
+
+        /* 312 MHz */
+        { 12000000, 312000000,  312,  12, 1, 12},
+        { 13000000, 312000000,  312,  13, 1, 12},
+        { 19200000, 312000000,  260,  16, 1, 8},
+        { 26000000, 312000000,  312,  26, 1, 12},
+
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct clk tegra_pll_x = {
         .name      = "pll_x",
         .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
-        .ops       = &tegra_pll_ops,
+        .ops       = &tegra_pllx_ops,
         .reg       = 0xe0,
         .input_min = 2000000,
         .input_max = 31000000,
@@ -1028,6 +1341,24 @@ static struct clk tegra_pll_x = {
         .vco_min   = 20000000,
         .vco_max   = 1200000000,
         .pll_table = tegra_pll_x_table,
+        .max_rate  = 1000000000,
+};
+
+static struct clk_pll_table tegra_pll_e_table[] = {
+        { 12000000, 100000000,  200,  24, 1, 0 },
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_e = {
+        .name      = "pll_e",
+        .flags     = PLL_ALT_MISC_REG,
+        .ops       = &tegra_plle_ops,
+        .input_min = 12000000,
+        .input_max = 12000000,
+        .max_rate  = 100000000,
+        .parent    = &tegra_clk_m,
+        .reg       = 0xe8,
+        .pll_table = tegra_pll_e_table,
 };
 
 static struct clk tegra_clk_d = {
@@ -1038,19 +1369,77 @@ static struct clk tegra_clk_d = {
         .reg       = 0x34,
         .reg_shift = 12,
         .parent    = &tegra_clk_m,
+        .max_rate  = 52000000,
+};
+
+/* initialized before peripheral clocks */
+static struct clk_mux_sel mux_audio_sync_clk[8+1];
+static const struct audio_sources {
+        const char *name;
+        int value;
+} mux_audio_sync_clk_sources[] = {
+        { .name = "spdif_in", .value = 0 },
+        { .name = "i2s1", .value = 1 },
+        { .name = "i2s2", .value = 2 },
+        { .name = "pll_a_out0", .value = 4 },
+#if 0 /* FIXME: not implemented */
+        { .name = "ac97", .value = 3 },
+        { .name = "ext_audio_clk2", .value = 5 },
+        { .name = "ext_audio_clk1", .value = 6 },
+        { .name = "ext_vimclk", .value = 7 },
+#endif
+        { 0, 0 }
+};
+
+static struct clk tegra_clk_audio = {
+        .name      = "audio",
+        .inputs    = mux_audio_sync_clk,
+        .reg       = 0x38,
+        .max_rate  = 24000000,
+        .ops       = &tegra_audio_sync_clk_ops
 };
 
-/* FIXME: need tegra_audio
 static struct clk tegra_clk_audio_2x = {
-        .name      = "clk_d",
+        .name      = "audio_2x",
         .flags     = PERIPH_NO_RESET,
+        .max_rate  = 48000000,
         .ops       = &tegra_clk_double_ops,
         .clk_num   = 89,
         .reg       = 0x34,
         .reg_shift = 8,
-        .parent    = &tegra_audio,
+        .parent    = &tegra_clk_audio,
+};
+
+struct clk_lookup tegra_audio_clk_lookups[] = {
+        { .con_id = "audio", .clk = &tegra_clk_audio },
+        { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
+};
+
+/* This is called after peripheral clocks are initialized, as the
+ * audio_sync clock depends on some of the peripheral clocks.
+ */
+
+static void init_audio_sync_clock_mux(void)
+{
+        int i;
+        struct clk_mux_sel *sel = mux_audio_sync_clk;
+        const struct audio_sources *src = mux_audio_sync_clk_sources;
+        struct clk_lookup *lookup;
+
+        for (i = 0; src->name; i++, sel++, src++) {
+                sel->input = tegra_get_clock_by_name(src->name);
+                if (!sel->input)
+                        pr_err("%s: could not find clk %s\n", __func__,
+                                src->name);
+                sel->value = src->value;
+        }
+
+        lookup = tegra_audio_clk_lookups;
+        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
+                clk_init(lookup->clk);
+                clkdev_add(lookup);
+        }
 }
-*/
 
 static struct clk_mux_sel mux_cclk[] = {
         { .input = &tegra_clk_m,        .value = 0},
@@ -1077,27 +1466,40 @@ static struct clk_mux_sel mux_sclk[] = {
         { 0, 0},
 };
 
-static struct clk tegra_clk_cpu = {
-        .name   = "cpu",
+static struct clk tegra_clk_cclk = {
+        .name   = "cclk",
         .inputs = mux_cclk,
         .reg    = 0x20,
         .ops    = &tegra_super_ops,
+        .max_rate = 1000000000,
 };
 
-static struct clk tegra_clk_sys = {
-        .name   = "sys",
+static struct clk tegra_clk_sclk = {
+        .name   = "sclk",
         .inputs = mux_sclk,
         .reg    = 0x28,
         .ops    = &tegra_super_ops,
+        .max_rate = 600000000,
+};
+
+static struct clk tegra_clk_virtual_cpu = {
+        .name      = "cpu",
+        .parent    = &tegra_clk_cclk,
+        .main      = &tegra_pll_x,
+        .backup    = &tegra_clk_m,
+        .ops       = &tegra_cpu_ops,
+        .max_rate  = 1000000000,
+        .dvfs      = &tegra_dvfs_virtual_cpu_dvfs,
 };
 
 static struct clk tegra_clk_hclk = {
         .name           = "hclk",
         .flags          = DIV_BUS,
-        .parent         = &tegra_clk_sys,
+        .parent         = &tegra_clk_sclk,
         .reg            = 0x30,
         .reg_shift      = 4,
         .ops            = &tegra_bus_ops,
+        .max_rate       = 240000000,
 };
 
 static struct clk tegra_clk_pclk = {
@@ -1107,6 +1509,7 @@ static struct clk tegra_clk_pclk = {
         .reg            = 0x30,
         .reg_shift      = 0,
         .ops            = &tegra_bus_ops,
+        .max_rate       = 108000000,
 };
 
 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
@@ -1133,10 +1536,9 @@ static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
         { 0, 0},
 };
 
-static struct clk_mux_sel mux_plla_audio_pllp_clkm[] = {
-        {.input = &tegra_pll_a, .value = 0},
-        /* FIXME: no mux defined for tegra_audio
-        {.input = &tegra_audio, .value = 1},*/
+static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
+        {.input = &tegra_pll_a_out0, .value = 0},
+        {.input = &tegra_clk_audio_2x, .value = 1},
         {.input = &tegra_pll_p, .value = 2},
         {.input = &tegra_clk_m, .value = 3},
         { 0, 0},
@@ -1153,8 +1555,7 @@ static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
         {.input = &tegra_pll_p,     .value = 0},
         {.input = &tegra_pll_c,     .value = 1},
-        /* FIXME: no mux defined for tegra_audio
-        {.input = &tegra_audio,     .value = 2},*/
+        {.input = &tegra_clk_audio,     .value = 2},
         {.input = &tegra_clk_m,     .value = 3},
         {.input = &tegra_clk_32k,   .value = 4},
         { 0, 0},
@@ -1187,7 +1588,7 @@ static struct clk_mux_sel mux_clk_32k[] = {
         { 0, 0},
 };
 
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _inputs, _flags) \
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
         {                                               \
                 .name      = _name,                     \
                 .lookup    = {                          \
@@ -1199,72 +1600,79 @@ static struct clk_mux_sel mux_clk_32k[] = {
                 .reg       = _reg,                      \
                 .inputs    = _inputs,                   \
                 .flags     = _flags,                    \
+                .max_rate  = _max,                      \
         }
 
 struct clk tegra_periph_clks[] = {
-        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      mux_clk_32k,                    PERIPH_NO_RESET),
-        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      mux_clk_m,                      0),
-        PERIPH_CLK("i2s1",      "i2s.0",                NULL,   11,     0x100,  mux_plla_audio_pllp_clkm,       MUX | DIV_U71),
-        PERIPH_CLK("i2s2",      "i2s.1",                NULL,   18,     0x104,  mux_plla_audio_pllp_clkm,       MUX | DIV_U71),
+        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET),
+        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("i2s1",      "i2s.0",                NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
+        PERIPH_CLK("i2s2",      "i2s.1",                NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
         /* FIXME: spdif has 2 clocks but 1 enable */
-        PERIPH_CLK("spdif_out", "spdif_out",            NULL,   10,     0x108,  mux_plla_audio_pllp_clkm,       MUX | DIV_U71),
-        PERIPH_CLK("spdif_in",  "spdif_in",             NULL,   10,     0x10c,  mux_pllp_pllc_pllm,             MUX | DIV_U71),
-        PERIPH_CLK("pwm",       "pwm",                  NULL,   17,     0x110,  mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
-        PERIPH_CLK("spi",       "spi",                  NULL,   43,     0x114,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("xio",       "xio",                  NULL,   45,     0x120,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("twc",       "twc",                  NULL,   16,     0x12c,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("ide",       "ide",                  NULL,   25,     0x144,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("ndflash",   "tegra_nand",           NULL,   13,     0x160,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+        PERIPH_CLK("spdif_out", "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
+        PERIPH_CLK("spdif_in",  "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71),
+        PERIPH_CLK("pwm",       "pwm",                  NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71),
+        PERIPH_CLK("spi",       "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("xio",       "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("twc",       "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("ide",       "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("ndflash",   "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
         /* FIXME: vfir shares an enable with uartb */
-        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x160,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x160,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
+        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
         /* FIXME: what is la? */
-        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("owr",       "owr",                  NULL,   71,     0x1cc,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("dvc",       "tegra-i2c.3",          NULL,   47,     0x128,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("i2c1_i2c",  "tegra-i2c.0",          "i2c",  0,      0,      mux_pllp_out3,                  0),
-        PERIPH_CLK("i2c2_i2c",  "tegra-i2c.1",          "i2c",  0,      0,      mux_pllp_out3,                  0),
-        PERIPH_CLK("i2c3_i2c",  "tegra-i2c.2",          "i2c",  0,      0,      mux_pllp_out3,                  0),
-        PERIPH_CLK("dvc_i2c",   "tegra-i2c.3",          "i2c",  0,      0,      mux_pllp_out3,                  0),
-        PERIPH_CLK("uarta",     "uart.0",               NULL,   6,      0x178,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("uartb",     "uart.1",               NULL,   7,      0x17c,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("uartc",     "uart.2",               NULL,   55,     0x1a0,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("uartd",     "uart.3",               NULL,   65,     0x1c0,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("uarte",     "uart.4",               NULL,   66,     0x1c4,  mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  mux_pllm_pllc_pllp_plla,        MUX | DIV_U71 | PERIPH_MANUAL_RESET),
-        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
+        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
+        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
+        PERIPH_CLK("dvc",       "tegra-i2c.3",          NULL,   47,     0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
+        PERIPH_CLK("i2c1_i2c",  "tegra-i2c.0",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
+        PERIPH_CLK("i2c2_i2c",  "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
+        PERIPH_CLK("i2c3_i2c",  "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
+        PERIPH_CLK("dvc_i2c",   "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
+        PERIPH_CLK("uarta",     "uart.0",               NULL,   6,      0x178,  216000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uartb",     "uart.1",               NULL,   7,      0x17c,  216000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uartc",     "uart.2",               NULL,   55,     0x1a0,  216000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uartd",     "uart.3",               NULL,   65,     0x1c0,  216000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uarte",     "uart.4",               NULL,   66,     0x1c4,  216000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
+        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
         /* FIXME: vi and vi_sensor share an enable */
-        PERIPH_CLK("vi",        "vi",                   NULL,   20,     0x148,  mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
-        PERIPH_CLK("vi_sensor", "vi_sensor",            NULL,   20,     0x1a8,  mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
-        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
-        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
-        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+        PERIPH_CLK("vi",        "vi",                   NULL,   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
+        PERIPH_CLK("vi_sensor", "vi_sensor",            NULL,   20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
+        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
+        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
+        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
         /* FIXME: cve and tvo share an enable   */
-        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("disp1",     "tegrafb.0",            NULL,   27,     0x138,  mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("disp2",     "tegrafb.1",            NULL,   26,     0x13c,  mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
-        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      mux_clk_m,                      0),
-        PERIPH_CLK("usb2",      "usb.1",                NULL,   58,     0,      mux_clk_m,                      0),
-        PERIPH_CLK("usb3",      "usb.2",                NULL,   59,     0,      mux_clk_m,                      0),
-        PERIPH_CLK("emc",       "emc",                  NULL,   57,     0x19c,  mux_pllm_pllc_pllp_clkm,        MUX | DIV_U71 | PERIPH_EMC_ENB),
-        PERIPH_CLK("dsi",       "dsi",                  NULL,   48,     0,      mux_plld,                       0),
+        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("disp1",     "tegrafb.0",            NULL,   27,     0x138,  190000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
+        PERIPH_CLK("disp2",     "tegrafb.1",            NULL,   26,     0x13c,  190000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
+        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("emc",       "emc",                  NULL,   57,     0x19c,  800000000, mux_pllm_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_EMC_ENB),
+        PERIPH_CLK("dsi",       "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0), /* scales with voltage */
+        PERIPH_CLK("csi",       "csi",                  NULL,   52,     0,      72000000,  mux_pllp_out3,               0),
+        PERIPH_CLK("isp",       "isp",                  NULL,   23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
+        PERIPH_CLK("csus",      "csus",                 NULL,   92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
+        PERIPH_CLK("pex",       NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
+        PERIPH_CLK("afi",       NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
+        PERIPH_CLK("pcie_xclk", NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
 };
 
 #define CLK_DUPLICATE(_name, _dev, _con)                \
@@ -1286,6 +1694,9 @@ struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("uartc",  "tegra_uart.2", NULL),
         CLK_DUPLICATE("uartd",  "tegra_uart.3", NULL),
         CLK_DUPLICATE("uarte",  "tegra_uart.4", NULL),
+        CLK_DUPLICATE("host1x", "tegrafb.0", "host1x"),
+        CLK_DUPLICATE("host1x", "tegrafb.1", "host1x"),
+        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
 };
 
 #define CLK(dev, con, ck)       \
@@ -1315,11 +1726,13 @@ struct clk_lookup tegra_clk_lookups[] = {
         CLK(NULL,       "pll_d_out0",   &tegra_pll_d_out0),
         CLK(NULL,       "pll_u",        &tegra_pll_u),
         CLK(NULL,       "pll_x",        &tegra_pll_x),
-        CLK(NULL,       "cpu",          &tegra_clk_cpu),
-        CLK(NULL,       "sys",          &tegra_clk_sys),
+        CLK(NULL,       "pll_e",        &tegra_pll_e),
+        CLK(NULL,       "cclk",         &tegra_clk_cclk),
+        CLK(NULL,       "sclk",         &tegra_clk_sclk),
         CLK(NULL,       "hclk",         &tegra_clk_hclk),
         CLK(NULL,       "pclk",         &tegra_clk_pclk),
         CLK(NULL,       "clk_d",        &tegra_clk_d),
+        CLK(NULL,       "cpu",          &tegra_clk_virtual_cpu),
 };
 
 void __init tegra2_init_clocks(void)
@@ -1356,4 +1769,75 @@ void __init tegra2_init_clocks(void)
                                 cd->name);
                 }
         }
+
+        init_audio_sync_clock_mux();
+}
+
+#ifdef CONFIG_PM
+static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
+                           PERIPH_CLK_SOURCE_NUM + 3];
+
+void tegra_clk_suspend(void)
+{
+        unsigned long off, i;
+        u32 *ctx = clk_rst_suspend;
+
+        *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
+
+        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
+                        off += 4) {
+                if (off == PERIPH_CLK_SOURCE_EMC)
+                        continue;
+                *ctx++ = clk_readl(off);
+        }
+
+        off = RST_DEVICES;
+        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
+                *ctx++ = clk_readl(off);
+
+        off = CLK_OUT_ENB;
+        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
+                *ctx++ = clk_readl(off);
+
+        *ctx++ = clk_readl(MISC_CLK_ENB);
+        *ctx++ = clk_readl(CLK_MASK_ARM);
+}
+
+void tegra_clk_resume(void)
+{
+        unsigned long off, i;
+        const u32 *ctx = clk_rst_suspend;
+        u32 val;
+
+        val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
+        val |= *ctx++;
+        clk_writel(val, OSC_CTRL);
+
+        /* enable all clocks before configuring clock sources */
+        clk_writel(0xbffffff9ul, CLK_OUT_ENB);
+        clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
+        clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
+        wmb();
+
+        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
+                        off += 4) {
+                if (off == PERIPH_CLK_SOURCE_EMC)
+                        continue;
+                clk_writel(*ctx++, off);
+        }
+        wmb();
+
+        off = RST_DEVICES;
+        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
+                clk_writel(*ctx++, off);
+        wmb();
+
+        off = CLK_OUT_ENB;
+        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
+                clk_writel(*ctx++, off);
+        wmb();
+
+        clk_writel(*ctx++, MISC_CLK_ENB);
+        clk_writel(*ctx++, CLK_MASK_ARM);
 }
+#endif
diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c
new file mode 100644
index 00000000000..5529c238dd7
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra2_dvfs.c
@@ -0,0 +1,86 @@
+/*
+ * arch/arm/mach-tegra/tegra2_dvfs.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include "clock.h"
+#include "tegra2_dvfs.h"
+
+static struct dvfs_table virtual_cpu_process_0[] = {
+        {314000000,  750},
+        {456000000,  825},
+        {608000000,  900},
+        {760000000,  975},
+        {817000000,  1000},
+        {912000000,  1050},
+        {1000000000, 1100},
+        {0, 0},
+};
+
+static struct dvfs_table virtual_cpu_process_1[] = {
+        {314000000,  750},
+        {456000000,  825},
+        {618000000,  900},
+        {770000000,  975},
+        {827000000,  1000},
+        {922000000,  1050},
+        {1000000000, 1100},
+        {0, 0},
+};
+
+static struct dvfs_table virtual_cpu_process_2[] = {
+        {494000000,  750},
+        {675000000,  825},
+        {817000000,  875},
+        {922000000,  925},
+        {1000000000, 975},
+        {0, 0},
+};
+
+static struct dvfs_table virtual_cpu_process_3[] = {
+        {730000000,  750},
+        {760000000,  775},
+        {845000000,  800},
+        {1000000000, 875},
+        {0, 0},
+};
+
+struct dvfs tegra_dvfs_virtual_cpu_dvfs = {
+        .reg_id = "vdd_cpu",
+        .process_id_table = {
+                {
+                        .process_id = 0,
+                        .table = virtual_cpu_process_0,
+                },
+                {
+                        .process_id = 1,
+                        .table = virtual_cpu_process_1,
+                },
+                {
+                        .process_id = 2,
+                        .table = virtual_cpu_process_2,
+                },
+                {
+                        .process_id = 3,
+                        .table = virtual_cpu_process_3,
+                },
+        },
+        .process_id_table_length = 4,
+        .cpu = 1,
+};
diff --git a/arch/arm/mach-tegra/tegra2_dvfs.h b/arch/arm/mach-tegra/tegra2_dvfs.h
new file mode 100644
index 00000000000..f8c1adba96a
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra2_dvfs.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-tegra/tegra2_dvfs.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+extern struct dvfs tegra_dvfs_virtual_cpu_dvfs;
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 5f55012b7c9..03f79361259 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -46,7 +46,6 @@ static ssize_t dummy_looptest(struct device *dev,
          * struct, this is just used here to alter the behaviour of the chip
          * in order to perform tests.
          */
-        struct pl022_config_chip *chip_info = spi->controller_data;
         int status;
         u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD,
                         0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05,
@@ -72,7 +71,7 @@ static ssize_t dummy_looptest(struct device *dev,
          * Force chip to 8 bit mode
          * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
          */
-        chip_info->data_size = SSP_DATA_BITS_8;
+        spi->bits_per_word = 8;
         /* You should NOT DO THIS EITHER */
         spi->master->setup(spi);
 
@@ -159,7 +158,7 @@ static ssize_t dummy_looptest(struct device *dev,
          * Force chip to 16 bit mode
          * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
          */
-        chip_info->data_size = SSP_DATA_BITS_16;
+        spi->bits_per_word = 16;
         /* You should NOT DO THIS EITHER */
         spi->master->setup(spi);
 
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
index 92c12420256..df715707bea 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -10,13 +10,12 @@
  */
 #include <mach/hardware.h>
 
-        .macro  addruart, rx, tmp
+        .macro  addruart, rp, rv
         /* If we move the address using MMU, use this. */
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                 @ MMU enabled?
-        ldreq   \rx,      = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
-        ldrne   \rx,      = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
-        orr     \rx, \rx, #0x00003000
+        ldr     \rp,      = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
+        ldr     \rv,      = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
+        orr     \rp, \rp, #0x00003000
+        orr     \rv, \rv, #0x00003000
         .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index f0e887bea30..edb2c0d255c 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -30,8 +30,6 @@ static void select_dummy_chip(u32 chipselect)
 }
 
 struct pl022_config_chip dummy_chip_info = {
-        /* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */
-        .lbm = LOOPBACK_ENABLED,
         /*
          * available POLLING_TRANSFER and INTERRUPT_TRANSFER,
          * DMA_TRANSFER does not work
@@ -42,14 +40,8 @@ struct pl022_config_chip dummy_chip_info = {
         .hierarchy = SSP_MASTER,
         /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
         .slave_tx_disable = 0,
-        /* LSB first */
-        .endian_tx = SSP_TX_LSB,
-        .endian_rx = SSP_RX_LSB,
-        .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */
         .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
         .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
-        .clk_phase = SSP_CLK_SECOND_EDGE,
-        .clk_pol = SSP_CLK_POL_IDLE_LOW,
         .ctrl_len = SSP_BITS_12,
         .wait_state = SSP_MWIRE_WAIT_ZERO,
         .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -75,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = {
                 .bus_num        = 0, /* Only one bus on this chip */
                 .chip_select    = 0,
                 /* Means SPI_CS_HIGH, change if e.g low CS */
-                .mode           = 0,
+                .mode           = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP,
         },
 #endif
 };
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index bfcda982088..07c35a84642 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -61,8 +61,6 @@ static void __init u300_init_machine(void)
 
 MACHINE_START(U300, MACH_U300_STRING)
         /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .phys_io        = U300_AHB_PER_PHYS_BASE,
-        .io_pg_offst    = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = BOOT_PARAMS_OFFSET,
         .map_io         = u300_map_io,
         .reserve        = u300_reserve,
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 6625e5bbf4d..2dd44a0b461 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -21,9 +21,7 @@ config MACH_U8500_MOP
         bool "U8500 Development platform"
         select UX500_SOC_DB8500
         help
-          Include support for mop500 development platform
-          based on U8500 architecture. The platform is based
-          on early drop silicon version of 8500.
+          Include support for the mop500 development platform.
 
 config MACH_U5500
         bool "U5500 Development platform"
@@ -39,4 +37,18 @@ config UX500_DEBUG_UART
           Choose the UART on which kernel low-level debug messages should be
           output.
 
+config U5500_MODEM_IRQ
+        bool "Modem IRQ support"
+        depends on MACH_U5500
+        default y
+        help
+          Add support for handling IRQ:s from modem side
+
+config U5500_MBOX
+        bool "Mailbox support"
+        depends on MACH_U5500 && U5500_MODEM_IRQ
+        default y
+        help
+          Add support for U5500 mailbox communication with modem side
+
 endif
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 4556aea9c3c..9e27a84433c 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -4,8 +4,12 @@
 
 obj-y                           := clock.o cpu.o devices.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o devices-db5500.o
-obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
-obj-$(CONFIG_MACH_U8500_MOP)    += board-mop500.o
+obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o prcmu.o
+obj-$(CONFIG_MACH_U8500_MOP)    += board-mop500.o board-mop500-sdi.o
 obj-$(CONFIG_MACH_U5500)        += board-u5500.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
+obj-$(CONFIG_REGULATOR_AB8500)  += board-mop500-regulators.o
+obj-$(CONFIG_U5500_MODEM_IRQ)   += modem_irq.o
+obj-$(CONFIG_U5500_MBOX)        += mbox.o
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
new file mode 100644
index 00000000000..1187f1fc2e5
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ * MOP500 board specific initialization for regulators
+ */
+#include <linux/kernel.h>
+#include <linux/regulator/machine.h>
+
+/* supplies to the display/camera */
+static struct regulator_init_data ab8500_vaux1_regulator = {
+        .constraints = {
+                .name = "V-DISPLAY",
+                .min_uV = 2500000,
+                .max_uV = 2900000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+                                        REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supplies to the on-board eMMC */
+static struct regulator_init_data ab8500_vaux2_regulator = {
+        .constraints = {
+                .name = "V-eMMC1",
+                .min_uV = 1100000,
+                .max_uV = 3300000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+                                        REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for VAUX3, supplies to SDcard slots */
+static struct regulator_init_data ab8500_vaux3_regulator = {
+        .constraints = {
+                .name = "V-MMC-SD",
+                .min_uV = 1100000,
+                .max_uV = 3300000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+                                        REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for tvout, gpadc, TVOUT LDO */
+static struct regulator_init_data ab8500_vtvout_init = {
+        .constraints = {
+                .name = "V-TVOUT",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for ab8500-vaudio, VAUDIO LDO */
+static struct regulator_init_data ab8500_vaudio_init = {
+        .constraints = {
+                .name = "V-AUD",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for v-anamic1 VAMic1-LDO */
+static struct regulator_init_data ab8500_vamic1_init = {
+        .constraints = {
+                .name = "V-AMIC1",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
+static struct regulator_init_data ab8500_vamic2_init = {
+        .constraints = {
+                .name = "V-AMIC2",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for v-dmic, VDMIC LDO */
+static struct regulator_init_data ab8500_vdmic_init = {
+        .constraints = {
+                .name = "V-DMIC",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for v-intcore12, VINTCORE12 LDO */
+static struct regulator_init_data ab8500_vintcore_init = {
+        .constraints = {
+                .name = "V-INTCORE",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+/* supply for U8500 CSI/DSI, VANA LDO */
+static struct regulator_init_data ab8500_vana_init = {
+        .constraints = {
+                .name = "V-CSI/DSI",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
new file mode 100644
index 00000000000..bac995665b5
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/mmci.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+
+#include <plat/pincfg.h>
+#include <mach/devices.h>
+#include <mach/hardware.h>
+
+#include "pins-db8500.h"
+#include "board-mop500.h"
+
+static pin_cfg_t mop500_sdi_pins[] = {
+        /* SDI4 (on-board eMMC) */
+        GPIO197_MC4_DAT3,
+        GPIO198_MC4_DAT2,
+        GPIO199_MC4_DAT1,
+        GPIO200_MC4_DAT0,
+        GPIO201_MC4_CMD,
+        GPIO202_MC4_FBCLK,
+        GPIO203_MC4_CLK,
+        GPIO204_MC4_DAT7,
+        GPIO205_MC4_DAT6,
+        GPIO206_MC4_DAT5,
+        GPIO207_MC4_DAT4,
+};
+
+static pin_cfg_t mop500_sdi2_pins[] = {
+        /* SDI2 (POP eMMC) */
+        GPIO128_MC2_CLK,
+        GPIO129_MC2_CMD,
+        GPIO130_MC2_FBCLK,
+        GPIO131_MC2_DAT0,
+        GPIO132_MC2_DAT1,
+        GPIO133_MC2_DAT2,
+        GPIO134_MC2_DAT3,
+        GPIO135_MC2_DAT4,
+        GPIO136_MC2_DAT5,
+        GPIO137_MC2_DAT6,
+        GPIO138_MC2_DAT7,
+};
+
+/*
+ * SDI 2 (POP eMMC, not on DB8500ed)
+ */
+
+static struct mmci_platform_data mop500_sdi2_data = {
+        .ocr_mask       = MMC_VDD_165_195,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+        .gpio_cd        = -1,
+        .gpio_wp        = -1,
+};
+
+/*
+ * SDI 4 (on-board eMMC)
+ */
+
+static struct mmci_platform_data mop500_sdi4_data = {
+        .ocr_mask       = MMC_VDD_29_30,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_MMC_HIGHSPEED,
+        .gpio_cd        = -1,
+        .gpio_wp        = -1,
+};
+
+void mop500_sdi_init(void)
+{
+        nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
+
+        u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data;
+        u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data;
+
+        if (!cpu_is_u8500ed()) {
+                nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
+                amba_device_register(&u8500_sdi2_device, &iomem_resource);
+        }
+
+        /* On-board eMMC */
+        amba_device_register(&u8500_sdi4_device, &iomem_resource);
+}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0e8fd135a57..cac83a69488 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -18,18 +18,22 @@
 #include <linux/amba/pl022.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/ab8500.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <plat/pincfg.h>
 #include <plat/i2c.h>
+#include <plat/ske.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
+#include <mach/irqs.h>
 
 #include "pins-db8500.h"
+#include "board-mop500.h"
 
 static pin_cfg_t mop500_pins[] = {
         /* SSP0 */
@@ -47,6 +51,24 @@ static pin_cfg_t mop500_pins[] = {
         GPIO11_I2C2_SCL,
         GPIO229_I2C3_SDA,
         GPIO230_I2C3_SCL,
+
+        /* SKE keypad */
+        GPIO153_KP_I7,
+        GPIO154_KP_I6,
+        GPIO155_KP_I5,
+        GPIO156_KP_I4,
+        GPIO157_KP_O7,
+        GPIO158_KP_O6,
+        GPIO159_KP_O5,
+        GPIO160_KP_O4,
+        GPIO161_KP_I3,
+        GPIO162_KP_I2,
+        GPIO163_KP_I1,
+        GPIO164_KP_I0,
+        GPIO165_KP_O3,
+        GPIO166_KP_O2,
+        GPIO167_KP_O1,
+        GPIO168_KP_O0,
 };
 
 static void ab4500_spi_cs_control(u32 command)
@@ -55,19 +77,13 @@ static void ab4500_spi_cs_control(u32 command)
 }
 
 struct pl022_config_chip ab4500_chip_info = {
-        .lbm = LOOPBACK_DISABLED,
         .com_mode = INTERRUPT_TRANSFER,
         .iface = SSP_INTERFACE_MOTOROLA_SPI,
         /* we can act as master only */
         .hierarchy = SSP_MASTER,
         .slave_tx_disable = 0,
-        .endian_rx = SSP_RX_MSB,
-        .endian_tx = SSP_TX_MSB,
-        .data_size = SSP_DATA_BITS_24,
         .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
         .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
-        .clk_phase = SSP_CLK_SECOND_EDGE,
-        .clk_pol = SSP_CLK_POL_IDLE_HIGH,
         .cs_control = ab4500_spi_cs_control,
 };
 
@@ -75,15 +91,33 @@ static struct ab8500_platform_data ab8500_platdata = {
         .irq_base       = MOP500_AB8500_IRQ_BASE,
 };
 
-static struct spi_board_info u8500_spi_devices[] = {
+static struct resource ab8500_resources[] = {
+        [0] = {
+                .start = IRQ_AB8500,
+                .end = IRQ_AB8500,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+struct platform_device ab8500_device = {
+        .name = "ab8500-i2c",
+        .id = 0,
+        .dev = {
+                .platform_data = &ab8500_platdata,
+        },
+        .num_resources = 1,
+        .resource = ab8500_resources,
+};
+
+static struct spi_board_info ab8500_spi_devices[] = {
         {
-                .modalias = "ab8500",
+                .modalias = "ab8500-spi",
                 .controller_data = &ab4500_chip_info,
                 .platform_data = &ab8500_platdata,
                 .max_speed_hz = 12000000,
                 .bus_num = 0,
                 .chip_select = 0,
-                .mode = SPI_MODE_0,
+                .mode = SPI_MODE_3,
                 .irq = IRQ_DB8500_AB8500,
         },
 };
@@ -134,12 +168,120 @@ static struct amba_device *amba_devs[] __initdata = {
         &u8500_ssp0_device,
 };
 
+static const unsigned int ux500_keymap[] = {
+        KEY(2, 5, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(3, 5, KEY_VOLUMEDOWN),
+        KEY(1, 3, KEY_3),
+        KEY(5, 2, KEY_RIGHT),
+        KEY(5, 0, KEY_9),
+
+        KEY(0, 5, KEY_MENU),
+        KEY(7, 6, KEY_ENTER),
+        KEY(4, 5, KEY_0),
+        KEY(6, 7, KEY_2),
+        KEY(3, 4, KEY_UP),
+        KEY(3, 3, KEY_DOWN),
+
+        KEY(6, 4, KEY_SEND),
+        KEY(6, 2, KEY_BACK),
+        KEY(4, 2, KEY_VOLUMEUP),
+        KEY(5, 5, KEY_1),
+        KEY(4, 3, KEY_LEFT),
+        KEY(3, 2, KEY_7),
+};
+
+static const struct matrix_keymap_data ux500_keymap_data = {
+        .keymap         = ux500_keymap,
+        .keymap_size    = ARRAY_SIZE(ux500_keymap),
+};
+
+/*
+ * Nomadik SKE keypad
+ */
+#define ROW_PIN_I0      164
+#define ROW_PIN_I1      163
+#define ROW_PIN_I2      162
+#define ROW_PIN_I3      161
+#define ROW_PIN_I4      156
+#define ROW_PIN_I5      155
+#define ROW_PIN_I6      154
+#define ROW_PIN_I7      153
+#define COL_PIN_O0      168
+#define COL_PIN_O1      167
+#define COL_PIN_O2      166
+#define COL_PIN_O3      165
+#define COL_PIN_O4      160
+#define COL_PIN_O5      159
+#define COL_PIN_O6      158
+#define COL_PIN_O7      157
+
+#define SKE_KPD_MAX_ROWS        8
+#define SKE_KPD_MAX_COLS        8
+
+static int ske_kp_rows[] = {
+        ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
+        ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
+};
+
+/*
+ * ske_set_gpio_row: request and set gpio rows
+ */
+static int ske_set_gpio_row(int gpio)
+{
+        int ret;
+
+        ret = gpio_request(gpio, "ske-kp");
+        if (ret < 0) {
+                pr_err("ske_set_gpio_row: gpio request failed\n");
+                return ret;
+        }
+
+        ret = gpio_direction_output(gpio, 1);
+        if (ret < 0) {
+                pr_err("ske_set_gpio_row: gpio direction failed\n");
+                gpio_free(gpio);
+        }
+
+        return ret;
+}
+
+/*
+ * ske_kp_init - enable the gpio configuration
+ */
+static int ske_kp_init(void)
+{
+        int ret, i;
+
+        for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
+                ret = ske_set_gpio_row(ske_kp_rows[i]);
+                if (ret < 0) {
+                        pr_err("ske_kp_init: failed init\n");
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static struct ske_keypad_platform_data ske_keypad_board = {
+        .init           = ske_kp_init,
+        .keymap_data    = &ux500_keymap_data,
+        .no_autorepeat  = true,
+        .krow           = SKE_KPD_MAX_ROWS,     /* 8x8 matrix */
+        .kcol           = SKE_KPD_MAX_COLS,
+        .debounce_ms    = 40,                   /* in millsecs */
+};
+
+
+
 /* add any platform devices here - TODO */
 static struct platform_device *platform_devs[] __initdata = {
         &u8500_i2c0_device,
         &ux500_i2c1_device,
         &ux500_i2c2_device,
         &ux500_i2c3_device,
+        &ux500_ske_keypad_device,
 };
 
 static void __init u8500_init_machine(void)
@@ -154,6 +296,7 @@ static void __init u8500_init_machine(void)
         ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
         ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
         ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data;
+        ux500_ske_keypad_device.dev.platform_data = &ske_keypad_board;
 
         u8500_ssp0_device.dev.platform_data = &ssp0_platform_data;
 
@@ -163,14 +306,18 @@ static void __init u8500_init_machine(void)
 
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
-        spi_register_board_info(u8500_spi_devices,
-                        ARRAY_SIZE(u8500_spi_devices));
+        mop500_sdi_init();
+
+        /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */
+        if (cpu_is_u8500ed() || cpu_is_u8500v10())
+                spi_register_board_info(ab8500_spi_devices,
+                        ARRAY_SIZE(ab8500_spi_devices));
+        else /* If HW is v.1.1 or later use I2C to access AB8500 */
+                platform_device_register(&ab8500_device);
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
         /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
-        .phys_io        = U8500_UART2_BASE,
-        .io_pg_offst    = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x100,
         .map_io         = u8500_map_io,
         .init_irq       = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
new file mode 100644
index 00000000000..2d240322fa6
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __BOARD_MOP500_H
+#define __BOARD_MOP500_H
+
+extern void mop500_sdi_init(void);
+
+#endif
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 4430e69cf53..1ca094a45e7 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -31,8 +31,6 @@ static void __init u5500_init_machine(void)
 }
 
 MACHINE_START(U8500, "ST-Ericsson U5500 Platform")
-        .phys_io        = UX500_UART0_BASE,
-        .io_pg_offst    = (IO_ADDRESS(UX500_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = u5500_map_io,
         .init_irq       = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index d8ab7f184fe..1675047daf2 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -477,6 +477,7 @@ static struct clk_lookup u8500_common_clks[] = {
         CLK(sdi5,       "sdi5",         NULL),
         CLK(uart2,      "uart2",        NULL),
         CLK(ske,        "ske",          NULL),
+        CLK(ske,        "nmk-ske-keypad",       NULL),
         CLK(sdi2,       "sdi2",         NULL),
         CLK(i2c0,       "nmk-i2c.0",    NULL),
         CLK(fsmc,       "fsmc",         NULL),
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index e9278f6d67a..2f87075e9d6 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -14,6 +14,7 @@
 #include <mach/hardware.h>
 #include <mach/devices.h>
 #include <mach/setup.h>
+#include <mach/irqs.h>
 
 static struct map_desc u5500_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
@@ -24,6 +25,90 @@ static struct map_desc u5500_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
 };
 
+static struct resource mbox0_resources[] = {
+        {
+                .name = "mbox_peer",
+                .start = U5500_MBOX0_PEER_START,
+                .end = U5500_MBOX0_PEER_END,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "mbox_local",
+                .start = U5500_MBOX0_LOCAL_START,
+                .end = U5500_MBOX0_LOCAL_END,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "mbox_irq",
+                .start = MBOX_PAIR0_VIRT_IRQ,
+                .end = MBOX_PAIR0_VIRT_IRQ,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource mbox1_resources[] = {
+        {
+                .name = "mbox_peer",
+                .start = U5500_MBOX1_PEER_START,
+                .end = U5500_MBOX1_PEER_END,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "mbox_local",
+                .start = U5500_MBOX1_LOCAL_START,
+                .end = U5500_MBOX1_LOCAL_END,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "mbox_irq",
+                .start = MBOX_PAIR1_VIRT_IRQ,
+                .end = MBOX_PAIR1_VIRT_IRQ,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource mbox2_resources[] = {
+        {
+                .name = "mbox_peer",
+                .start = U5500_MBOX2_PEER_START,
+                .end = U5500_MBOX2_PEER_END,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "mbox_local",
+                .start = U5500_MBOX2_LOCAL_START,
+                .end = U5500_MBOX2_LOCAL_END,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "mbox_irq",
+                .start = MBOX_PAIR2_VIRT_IRQ,
+                .end = MBOX_PAIR2_VIRT_IRQ,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device mbox0_device = {
+        .id = 0,
+        .name = "mbox",
+        .resource = mbox0_resources,
+        .num_resources = ARRAY_SIZE(mbox0_resources),
+};
+
+static struct platform_device mbox1_device = {
+        .id = 1,
+        .name = "mbox",
+        .resource = mbox1_resources,
+        .num_resources = ARRAY_SIZE(mbox1_resources),
+};
+
+static struct platform_device mbox2_device = {
+        .id = 2,
+        .name = "mbox",
+        .resource = mbox2_resources,
+        .num_resources = ARRAY_SIZE(mbox2_resources),
+};
+
 static struct platform_device *u5500_platform_devs[] __initdata = {
         &u5500_gpio_devs[0],
         &u5500_gpio_devs[1],
@@ -33,6 +118,9 @@ static struct platform_device *u5500_platform_devs[] __initdata = {
         &u5500_gpio_devs[5],
         &u5500_gpio_devs[6],
         &u5500_gpio_devs[7],
+        &mbox0_device,
+        &mbox1_device,
+        &mbox2_device,
 };
 
 void __init u5500_map_io(void)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index f21c444edd9..4acab7544b3 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -38,10 +38,12 @@ static struct platform_device *platform_devs[] __initdata = {
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
+        __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M),
 };
 
 static struct map_desc u8500ed_io_desc[] __initdata = {
@@ -53,6 +55,69 @@ static struct map_desc u8500v1_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
 };
 
+/*
+ * Functions to differentiate between later ASICs
+ * We look into the end of the ROM to locate the hardcoded ASIC ID.
+ * This is only needed to differentiate between minor revisions and
+ * process variants of an ASIC, the major revisions are encoded in
+ * the cpuid.
+ */
+#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4)
+#define U8500_ASIC_ID_LOC_V2    (U8500_BOOT_ROM_BASE + 0x1DBF4)
+#define U8500_ASIC_REV_ED       0x01
+#define U8500_ASIC_REV_V10      0xA0
+#define U8500_ASIC_REV_V11      0xA1
+#define U8500_ASIC_REV_V20      0xB0
+
+/**
+ * struct db8500_asic_id - fields of the ASIC ID
+ * @process: the manufacturing process, 0x40 is 40 nm
+ *  0x00 is "standard"
+ * @partnumber: hithereto 0x8500 for DB8500
+ * @revision: version code in the series
+ * This field definion is not formally defined but makes
+ * sense.
+ */
+struct db8500_asic_id {
+        u8 process;
+        u16 partnumber;
+        u8 revision;
+};
+
+/* This isn't going to change at runtime */
+static struct db8500_asic_id db8500_id;
+
+static void __init get_db8500_asic_id(void)
+{
+        u32 asicid;
+
+        if (cpu_is_u8500v1() || cpu_is_u8500ed())
+                asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1));
+        else if (cpu_is_u8500v2())
+                asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2));
+        else
+                BUG();
+
+        db8500_id.process = (asicid >> 24);
+        db8500_id.partnumber = (asicid >> 16) & 0xFFFFU;
+        db8500_id.revision = asicid & 0xFFU;
+}
+
+bool cpu_is_u8500v10(void)
+{
+        return (db8500_id.revision == U8500_ASIC_REV_V10);
+}
+
+bool cpu_is_u8500v11(void)
+{
+        return (db8500_id.revision == U8500_ASIC_REV_V11);
+}
+
+bool cpu_is_u8500v20(void)
+{
+        return (db8500_id.revision == U8500_ASIC_REV_V20);
+}
+
 void __init u8500_map_io(void)
 {
         ux500_map_io();
@@ -63,6 +128,9 @@ void __init u8500_map_io(void)
                 iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
         else
                 iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
+
+        /* Read out the ASIC ID as early as we can */
+        get_db8500_asic_id();
 }
 
 /*
@@ -70,6 +138,20 @@ void __init u8500_map_io(void)
  */
 void __init u8500_init_devices(void)
 {
+        /* Display some ASIC boilerplate */
+        pr_info("DB8500: process: %02x, revision ID: 0x%02x\n",
+                db8500_id.process, db8500_id.revision);
+        if (cpu_is_u8500ed())
+                pr_info("DB8500: Early Drop (ED)\n");
+        else if (cpu_is_u8500v10())
+                pr_info("DB8500: version 1.0\n");
+        else if (cpu_is_u8500v11())
+                pr_info("DB8500: version 1.1\n");
+        else if (cpu_is_u8500v20())
+                pr_info("DB8500: version 2.0\n");
+        else
+                pr_warning("ASIC: UNKNOWN SILICON VERSION!\n");
+
         ux500_init_devices();
 
         if (cpu_is_u8500ed())
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 9280d256111..cbbe69a76a7 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -110,6 +110,82 @@ struct platform_device u8500_i2c4_device = {
         .num_resources  = ARRAY_SIZE(u8500_i2c4_resources),
 };
 
+/*
+ * SD/MMC
+ */
+
+struct amba_device u8500_sdi0_device = {
+        .dev            = {
+                .init_name = "sdi0",
+        },
+        .res            = {
+                .start  = U8500_SDI0_BASE,
+                .end    = U8500_SDI0_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .irq            = {IRQ_DB8500_SDMMC0, NO_IRQ},
+};
+
+struct amba_device u8500_sdi1_device = {
+        .dev            = {
+                .init_name = "sdi1",
+        },
+        .res            = {
+                .start  = U8500_SDI1_BASE,
+                .end    = U8500_SDI1_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .irq            = {IRQ_DB8500_SDMMC1, NO_IRQ},
+};
+
+struct amba_device u8500_sdi2_device = {
+        .dev            = {
+                .init_name = "sdi2",
+        },
+        .res            = {
+                .start  = U8500_SDI2_BASE,
+                .end    = U8500_SDI2_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .irq            = {IRQ_DB8500_SDMMC2, NO_IRQ},
+};
+
+struct amba_device u8500_sdi3_device = {
+        .dev            = {
+                .init_name = "sdi3",
+        },
+        .res            = {
+                .start  = U8500_SDI3_BASE,
+                .end    = U8500_SDI3_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .irq            = {IRQ_DB8500_SDMMC3, NO_IRQ},
+};
+
+struct amba_device u8500_sdi4_device = {
+        .dev            = {
+                .init_name = "sdi4",
+        },
+        .res            = {
+                .start  = U8500_SDI4_BASE,
+                .end    = U8500_SDI4_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .irq            = {IRQ_DB8500_SDMMC4, NO_IRQ},
+};
+
+struct amba_device u8500_sdi5_device = {
+        .dev            = {
+                .init_name = "sdi5",
+        },
+        .res            = {
+                .start  = U8500_SDI5_BASE,
+                .end    = U8500_SDI5_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        .irq            = {IRQ_DB8500_SDMMC5, NO_IRQ},
+};
+
 static struct resource dma40_resources[] = {
         [0] = {
                 .start = U8500_DMA_BASE,
@@ -170,23 +246,23 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  * Mapping between destination event lines and physical device address.
  * The event line is tied to a device and therefor the address is constant.
  */
-static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV];
+static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV];
 
 /* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV];
+static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV];
 
 /* Reserved event lines for memcpy only */
 static int dma40_memcpy_event[] = {
-        STEDMA40_MEMCPY_TX_0,
-        STEDMA40_MEMCPY_TX_1,
-        STEDMA40_MEMCPY_TX_2,
-        STEDMA40_MEMCPY_TX_3,
-        STEDMA40_MEMCPY_TX_4,
-        STEDMA40_MEMCPY_TX_5,
+        DB8500_DMA_MEMCPY_TX_0,
+        DB8500_DMA_MEMCPY_TX_1,
+        DB8500_DMA_MEMCPY_TX_2,
+        DB8500_DMA_MEMCPY_TX_3,
+        DB8500_DMA_MEMCPY_TX_4,
+        DB8500_DMA_MEMCPY_TX_5,
 };
 
 static struct stedma40_platform_data dma40_plat_data = {
-        .dev_len = STEDMA40_NR_DEV,
+        .dev_len = DB8500_DMA_NR_DEV,
         .dev_rx = dma40_rx_map,
         .dev_tx = dma40_tx_map,
         .memcpy = dma40_memcpy_event,
@@ -216,3 +292,23 @@ void dma40_u8500ed_fixup(void)
         dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED;
         dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1;
 }
+
+struct resource keypad_resources[] = {
+        [0] = {
+                .start = U8500_SKE_BASE,
+                .end = U8500_SKE_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_DB8500_KB,
+                .end = IRQ_DB8500_KB,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device ux500_ske_keypad_device = {
+        .name = "nmk-ske-keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(keypad_resources),
+        .resource = keypad_resources,
+};
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
new file mode 100644
index 00000000000..b782a03024b
--- /dev/null
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *      Based on ARM realview platform
+ *
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+#include <asm/cacheflush.h>
+
+extern volatile int pen_release;
+
+static DECLARE_COMPLETION(cpu_killed);
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+        flush_cache_all();
+
+        /* we put the platform to just WFI */
+        for (;;) {
+                __asm__ __volatile__("dsb\n\t" "wfi\n\t"
+                                : : : "memory");
+                if (pen_release == cpu) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+        }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+#ifdef DEBUG
+        unsigned int this_cpu = hard_smp_processor_id();
+
+        if (cpu != this_cpu) {
+                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
+                           this_cpu, cpu);
+                BUG();
+        }
+#endif
+
+        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+        complete(&cpu_killed);
+
+        /* directly enter low power state, skipping secure registers */
+        platform_do_lowpower(cpu);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 545c80fc802..3eafc0e24ba 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -100,4 +100,18 @@
 #define U5500_GPIOBANK6_BASE    (U5500_GPIO4_BASE + 0x80)
 #define U5500_GPIOBANK7_BASE    (U5500_GPIO4_BASE + 0x100)
 
+#define U5500_MBOX_BASE         (U5500_MODEM_BASE + 0xFFD1000)
+#define U5500_MBOX0_PEER_START  (U5500_MBOX_BASE + 0x40)
+#define U5500_MBOX0_PEER_END    (U5500_MBOX_BASE + 0x5F)
+#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
+#define U5500_MBOX0_LOCAL_END   (U5500_MBOX_BASE + 0x7F)
+#define U5500_MBOX1_PEER_START  (U5500_MBOX_BASE + 0x80)
+#define U5500_MBOX1_PEER_END    (U5500_MBOX_BASE + 0x9F)
+#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
+#define U5500_MBOX1_LOCAL_END   (U5500_MBOX_BASE + 0xBF)
+#define U5500_MBOX2_PEER_START  (U5500_MBOX_BASE + 0x00)
+#define U5500_MBOX2_PEER_END    (U5500_MBOX_BASE + 0x1F)
+#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
+#define U5500_MBOX2_LOCAL_END   (U5500_MBOX_BASE + 0x3F)
+
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index f000218210c..f07d0986409 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -30,8 +30,6 @@
 #define U8500_ICN_BASE          0x81000000
 
 #define U8500_BOOT_ROM_BASE     0x90000000
-/* ASIC ID is at 0xff4 offset within this region */
-#define U8500_ASIC_ID_BASE      0x9001F000
 
 #define U8500_PER6_BASE         0xa03c0000
 #define U8500_PER5_BASE         0xa03e0000
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index c5203b7ea55..be7c0f14e31 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -18,11 +18,9 @@
 #define UX500_UART(n)   __UX500_UART(n)
 #define UART_BASE       UX500_UART(CONFIG_UX500_DEBUG_UART)
 
-        .macro  addruart, rx, tmp
-        mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =UART_BASE                         @ no, physical address
-        ldrne   \rx, =IO_ADDRESS(UART_BASE)             @ yes, virtual address
+        .macro  addruart, rp, rv
+        ldr     \rp, =UART_BASE                         @ no, physical address
+        ldr     \rv, =IO_ADDRESS(UART_BASE)             @ yes, virtual address
         .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index c2b2f257494..b91a4d1211a 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -26,6 +26,14 @@ extern struct platform_device ux500_i2c3_device;
 extern struct platform_device u8500_i2c0_device;
 extern struct platform_device u8500_i2c4_device;
 extern struct platform_device u8500_dma40_device;
+extern struct platform_device ux500_ske_keypad_device;
+
+extern struct amba_device u8500_sdi0_device;
+extern struct amba_device u8500_sdi1_device;
+extern struct amba_device u8500_sdi2_device;
+extern struct amba_device u8500_sdi3_device;
+extern struct amba_device u8500_sdi4_device;
+extern struct amba_device u8500_sdi5_device;
 
 void dma40_u8500ed_fixup(void);
 
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 8656379a830..32e883a8f2a 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -104,16 +104,35 @@ static inline bool cpu_is_u8500(void)
 #endif
 }
 
+#define CPUID_DB8500ED  0x410fc090
+#define CPUID_DB8500V1  0x411fc091
+#define CPUID_DB8500V2  0x412fc091
+
 static inline bool cpu_is_u8500ed(void)
 {
-        return cpu_is_u8500() && (read_cpuid_id() & 15) == 0;
+        return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED);
 }
 
 static inline bool cpu_is_u8500v1(void)
 {
-        return cpu_is_u8500() && (read_cpuid_id() & 15) == 1;
+        return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1);
+}
+
+static inline bool cpu_is_u8500v2(void)
+{
+        return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2);
 }
 
+#ifdef CONFIG_UX500_SOC_DB8500
+bool cpu_is_u8500v10(void);
+bool cpu_is_u8500v11(void);
+bool cpu_is_u8500v20(void);
+#else
+static inline bool cpu_is_u8500v10(void) { return false; }
+static inline bool cpu_is_u8500v11(void) { return false; }
+static inline bool cpu_is_u8500v20(void) { return false; }
+#endif
+
 static inline bool cpu_is_u5500(void)
 {
 #ifdef CONFIG_UX500_SOC_DB5500
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
index 6fbfe5e2065..bfa123dbec3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -61,6 +61,7 @@
 #define IRQ_DB5500_SDMMC0               (IRQ_SHPI_START + 60)
 #define IRQ_DB5500_HSEM                 (IRQ_SHPI_START + 61)
 #define IRQ_DB5500_SBAG                 (IRQ_SHPI_START + 63)
+#define IRQ_DB5500_MODEM                (IRQ_SHPI_START + 65)
 #define IRQ_DB5500_SPI1                 (IRQ_SHPI_START + 96)
 #define IRQ_DB5500_MSP2                 (IRQ_SHPI_START + 98)
 #define IRQ_DB5500_SRPTIMER             (IRQ_SHPI_START + 101)
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 10385bdc2b7..693aa57de88 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -40,7 +40,8 @@
 #define IRQ_HSIR_CH1_OVRRUN     (IRQ_SHPI_START + 33)
 #define IRQ_HSIR_CH2_OVRRUN     (IRQ_SHPI_START + 34)
 #define IRQ_HSIR_CH3_OVRRUN     (IRQ_SHPI_START + 35)
-#define IRQ_AB4500              (IRQ_SHPI_START + 40)
+#define IRQ_AB8500              (IRQ_SHPI_START + 40)
+#define IRQ_PRCMU               (IRQ_SHPI_START + 47)
 #define IRQ_DISP                (IRQ_SHPI_START + 48)
 #define IRQ_SiPI3               (IRQ_SHPI_START + 49)
 #define IRQ_I2C4                (IRQ_SHPI_START + 51)
@@ -83,6 +84,19 @@
 #include <mach/irqs-board-mop500.h>
 #endif
 
-#define NR_IRQS                         IRQ_BOARD_END
+/*
+ * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual
+ * IRQ:s representing modem IRQ:s can be allocated
+ */
+#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1)
+#define IRQ_MODEM_EVENTS_NBR 72
+#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
+
+/* List of virtual IRQ:s that are allocated from the range above */
+#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
+#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
+#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
+
+#define NR_IRQS                         IRQ_MODEM_EVENTS_END
 
 #endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox.h
new file mode 100644
index 00000000000..7f9da4d2fbd
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mbox.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
+ * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __INC_STE_MBOX_H
+#define __INC_STE_MBOX_H
+
+#define MBOX_BUF_SIZE 16
+#define MBOX_NAME_SIZE 8
+
+/**
+  * mbox_recv_cb_t - Definition of the mailbox callback.
+  * @mbox_msg:  The mailbox message.
+  * @priv:      The clients private data as specified in the call to mbox_setup.
+  *
+  * This function will be called upon reception of new mailbox messages.
+  */
+typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
+
+/**
+  * struct mbox - Mailbox instance struct
+  * @list:              Linked list head.
+  * @pdev:              Pointer to device struct.
+  * @cb:                Callback function. Will be called
+  *                     when new data is received.
+  * @client_data:       Clients private data. Will be sent back
+  *                     in the callback function.
+  * @virtbase_peer:     Virtual address for outgoing mailbox.
+  * @virtbase_local:    Virtual address for incoming mailbox.
+  * @buffer:            Then internal queue for outgoing messages.
+  * @name:              Name of this mailbox.
+  * @buffer_available:  Completion variable to achieve "blocking send".
+  *                     This variable will be signaled when there is
+  *                     internal buffer space available.
+  * @client_blocked:    To keep track if any client is currently
+  *                     blocked.
+  * @lock:              Spinlock to protect this mailbox instance.
+  * @write_index:       Index in internal buffer to write to.
+  * @read_index:        Index in internal buffer to read from.
+  * @allocated:         Indicates whether this particular mailbox
+  *                     id has been allocated by someone.
+  */
+struct mbox {
+        struct list_head list;
+        struct platform_device *pdev;
+        mbox_recv_cb_t *cb;
+        void *client_data;
+        void __iomem *virtbase_peer;
+        void __iomem *virtbase_local;
+        u32 buffer[MBOX_BUF_SIZE];
+        char name[MBOX_NAME_SIZE];
+        struct completion buffer_available;
+        u8 client_blocked;
+        spinlock_t lock;
+        u8 write_index;
+        u8 read_index;
+        bool allocated;
+};
+
+/**
+  * mbox_setup - Set up a mailbox and return its instance.
+  * @mbox_id:   The ID number of the mailbox. 0 or 1 for modem CPU,
+  *             2 for modem DSP.
+  * @mbox_cb:   Pointer to the callback function to be called when a new message
+  *             is received.
+  * @priv:      Client user data which will be returned in the callback.
+  *
+  * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
+  */
+struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
+
+/**
+  * mbox_send - Send a mailbox message.
+  * @mbox:      Mailbox instance (returned by mbox_setup)
+  * @mbox_msg:  The mailbox message to send.
+  * @block:     Specifies whether this call will block until send is possible,
+  *             or return an error if the mailbox buffer is full.
+  *
+  * Returns 0 on success or a negative error code on error. -ENOMEM indicates
+  * that the internal buffer is full and you have to try again later (or
+  * specify "block" in order to block until send is possible).
+  */
+int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
+
+#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
new file mode 100644
index 00000000000..8885f39a642
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2009 ST-Ericsson SA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+#ifndef __MACH_PRCMU_REGS_H
+#define __MACH_PRCMU_REGS_H
+
+#include <mach/hardware.h>
+
+#define _PRCMU_BASE             IO_ADDRESS(U8500_PRCMU_BASE)
+
+#define PRCM_ARM_PLLDIVPS       (_PRCMU_BASE + 0x118)
+#define PRCM_ARM_CHGCLKREQ      (_PRCMU_BASE + 0x114)
+#define PRCM_PLLARM_ENABLE      (_PRCMU_BASE + 0x98)
+#define PRCM_ARMCLKFIX_MGT      (_PRCMU_BASE + 0x0)
+#define PRCM_A9_RESETN_CLR      (_PRCMU_BASE + 0x1f4)
+#define PRCM_A9_RESETN_SET      (_PRCMU_BASE + 0x1f0)
+#define PRCM_ARM_LS_CLAMP       (_PRCMU_BASE + 0x30c)
+#define PRCM_SRAM_A9            (_PRCMU_BASE + 0x308)
+
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)
+#define PRCMU_IOCR              (_PRCMU_BASE + 0x310)
+
+/* CPU mailbox registers */
+#define PRCM_MBOX_CPU_VAL       (_PRCMU_BASE + 0x0fc)
+#define PRCM_MBOX_CPU_SET       (_PRCMU_BASE + 0x100)
+#define PRCM_MBOX_CPU_CLR       (_PRCMU_BASE + 0x104)
+
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ        (_PRCMU_BASE + 0x328)
+#define PRCM_A9_MASK_ACK        (_PRCMU_BASE + 0x32c)
+#define PRCM_ARMITMSK31TO0      (_PRCMU_BASE + 0x11c)
+#define PRCM_ARMITMSK63TO32     (_PRCMU_BASE + 0x120)
+#define PRCM_ARMITMSK95TO64     (_PRCMU_BASE + 0x124)
+#define PRCM_ARMITMSK127TO96    (_PRCMU_BASE + 0x128)
+#define PRCM_POWER_STATE_VAL    (_PRCMU_BASE + 0x25C)
+#define PRCM_ARMITVAL31TO0      (_PRCMU_BASE + 0x260)
+#define PRCM_ARMITVAL63TO32     (_PRCMU_BASE + 0x264)
+#define PRCM_ARMITVAL95TO64     (_PRCMU_BASE + 0x268)
+#define PRCM_ARMITVAL127TO96    (_PRCMU_BASE + 0x26C)
+
+#define PRCM_HOSTACCESS_REQ     (_PRCMU_BASE + 0x334)
+#define ARM_WAKEUP_MODEM        0x1
+
+#define PRCM_ARM_IT1_CLEAR      (_PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL        (_PRCMU_BASE + 0x494)
+#define PRCM_HOLD_EVT           (_PRCMU_BASE + 0x174)
+
+#define PRCM_ITSTATUS0          (_PRCMU_BASE + 0x148)
+#define PRCM_ITSTATUS1          (_PRCMU_BASE + 0x150)
+#define PRCM_ITSTATUS2          (_PRCMU_BASE + 0x158)
+#define PRCM_ITSTATUS3          (_PRCMU_BASE + 0x160)
+#define PRCM_ITSTATUS4          (_PRCMU_BASE + 0x168)
+#define PRCM_ITSTATUS5          (_PRCMU_BASE + 0x484)
+#define PRCM_ITCLEAR5           (_PRCMU_BASE + 0x488)
+#define PRCM_ARMIT_MASKXP70_IT  (_PRCMU_BASE + 0x1018)
+
+/* System reset register */
+#define PRCM_APE_SOFTRST        (_PRCMU_BASE + 0x228)
+
+/* Level shifter and clamp control registers */
+#define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)
+#define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)
+
+/* PRCMU clock/PLL/reset registers */
+#define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
+#define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
+#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + 0x044)
+#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + 0x064)
+#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + 0x058)
+#define PRCM_TVCLK_MGT             (_PRCMU_BASE + 0x07c)
+#define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
+#define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
+#define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
+#define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
+
+/* ePOD and memory power signal control registers */
+#define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
+#define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)
+
+/* Debug power control unit registers */
+#define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)
+
+/* Miscellaneous unit registers */
+#define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
+
+#endif /* __MACH_PRCMU__REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
new file mode 100644
index 00000000000..549843ff6db
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCMU f/w APIs
+ */
+#ifndef __MACH_PRCMU_H
+#define __MACH_PRCMU_H
+
+int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index e978dbd9e21..54bbe648bf5 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -38,4 +38,11 @@ extern struct sys_timer ux500_timer;
         .type           = MT_DEVICE,            \
 }
 
+#define __MEM_DEV_DESC(x, sz)   {               \
+        .virtual        = IO_ADDRESS(x),        \
+        .pfn            = __phys_to_pfn(x),     \
+        .length         = sz,                   \
+        .type           = MT_MEMORY,            \
+}
+
 #endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc9725..197e8417375 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()                         \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox.c
new file mode 100644
index 00000000000..63435389c54
--- /dev/null
+++ b/arch/arm/mach-ux500/mbox.c
@@ -0,0 +1,567 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
+ * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+/*
+ * Mailbox nomenclature:
+ *
+ *       APE           MODEM
+ *           mbox pairX
+ *   ..........................
+ *   .                       .
+ *   .           peer        .
+ *   .     send  ----        .
+ *   .      -->  |  |        .
+ *   .           |  |        .
+ *   .           ----        .
+ *   .                       .
+ *   .           local       .
+ *   .     rec   ----        .
+ *   .           |  | <--    .
+ *   .           |  |        .
+ *   .           ----        .
+ *   .........................
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/completion.h>
+#include <mach/mbox.h>
+
+#define MBOX_NAME "mbox"
+
+#define MBOX_FIFO_DATA        0x000
+#define MBOX_FIFO_ADD         0x004
+#define MBOX_FIFO_REMOVE      0x008
+#define MBOX_FIFO_THRES_FREE  0x00C
+#define MBOX_FIFO_THRES_OCCUP 0x010
+#define MBOX_FIFO_STATUS      0x014
+
+#define MBOX_DISABLE_IRQ 0x4
+#define MBOX_ENABLE_IRQ  0x0
+#define MBOX_LATCH 1
+
+/* Global list of all mailboxes */
+static struct list_head mboxs = LIST_HEAD_INIT(mboxs);
+
+static struct mbox *get_mbox_with_id(u8 id)
+{
+        u8 i;
+        struct list_head *pos = &mboxs;
+        for (i = 0; i <= id; i++)
+                pos = pos->next;
+
+        return (struct mbox *) list_entry(pos, struct mbox, list);
+}
+
+int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block)
+{
+        int res = 0;
+
+        spin_lock(&mbox->lock);
+
+        dev_dbg(&(mbox->pdev->dev),
+                "About to buffer 0x%X to mailbox 0x%X."
+                " ri = %d, wi = %d\n",
+                mbox_msg, (u32)mbox, mbox->read_index,
+                mbox->write_index);
+
+        /* Check if write buffer is full */
+        while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) {
+                if (!block) {
+                        dev_dbg(&(mbox->pdev->dev),
+                        "Buffer full in non-blocking call! "
+                        "Returning -ENOMEM!\n");
+                        res = -ENOMEM;
+                        goto exit;
+                }
+                spin_unlock(&mbox->lock);
+                dev_dbg(&(mbox->pdev->dev),
+                        "Buffer full in blocking call! Sleeping...\n");
+                mbox->client_blocked = 1;
+                wait_for_completion(&mbox->buffer_available);
+                dev_dbg(&(mbox->pdev->dev),
+                        "Blocking send was woken up! Trying again...\n");
+                spin_lock(&mbox->lock);
+        }
+
+        mbox->buffer[mbox->write_index] = mbox_msg;
+        mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE;
+
+        /*
+         * Indicate that we want an IRQ as soon as there is a slot
+         * in the FIFO
+         */
+        writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
+
+exit:
+        spin_unlock(&mbox->lock);
+        return res;
+}
+EXPORT_SYMBOL(mbox_send);
+
+#if defined(CONFIG_DEBUG_FS)
+/*
+ * Expected input: <value> <nbr sends>
+ * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times
+ */
+static ssize_t mbox_write_fifo(struct device *dev,
+                               struct device_attribute *attr,
+                               const char *buf,
+                               size_t count)
+{
+        unsigned long mbox_mess;
+        unsigned long nbr_sends;
+        unsigned long i;
+        char int_buf[16];
+        char *token;
+        char *val;
+
+        struct mbox *mbox = (struct mbox *) dev->platform_data;
+
+        strncpy((char *) &int_buf, buf, sizeof(int_buf));
+        token = (char *) &int_buf;
+
+        /* Parse message */
+        val = strsep(&token, " ");
+        if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0))
+                mbox_mess = 0xDEADBEEF;
+
+        val = strsep(&token, " ");
+        if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0))
+                nbr_sends = 1;
+
+        dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n",
+                mbox_mess, nbr_sends, (u32) mbox);
+
+        for (i = 0; i < nbr_sends; i++)
+                mbox_send(mbox, mbox_mess, true);
+
+        return count;
+}
+
+static ssize_t mbox_read_fifo(struct device *dev,
+                              struct device_attribute *attr,
+                              char *buf)
+{
+        int mbox_value;
+        struct mbox *mbox = (struct mbox *) dev->platform_data;
+
+        if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0)
+                return sprintf(buf, "Mailbox is empty\n");
+
+        mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
+        writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
+
+        return sprintf(buf, "0x%X\n", mbox_value);
+}
+
+static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
+
+static int mbox_show(struct seq_file *s, void *data)
+{
+        struct list_head *pos;
+        u8 mbox_index = 0;
+
+        list_for_each(pos, &mboxs) {
+                struct mbox *m =
+                        (struct mbox *) list_entry(pos, struct mbox, list);
+                if (m == NULL) {
+                        seq_printf(s,
+                                   "Unable to retrieve mailbox %d\n",
+                                   mbox_index);
+                        continue;
+                }
+
+                spin_lock(&m->lock);
+                if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) {
+                        seq_printf(s, "MAILBOX %d not setup or corrupt\n",
+                                   mbox_index);
+                        spin_unlock(&m->lock);
+                        continue;
+                }
+
+                seq_printf(s,
+                "===========================\n"
+                " MAILBOX %d\n"
+                " PEER MAILBOX DUMP\n"
+                "---------------------------\n"
+                "FIFO:                 0x%X (%d)\n"
+                "Free     Threshold:   0x%.2X (%d)\n"
+                "Occupied Threshold:   0x%.2X (%d)\n"
+                "Status:               0x%.2X (%d)\n"
+                "   Free spaces  (ot):    %d (%d)\n"
+                "   Occup spaces (ot):    %d (%d)\n"
+                "===========================\n"
+                " LOCAL MAILBOX DUMP\n"
+                "---------------------------\n"
+                "FIFO:                 0x%.X (%d)\n"
+                "Free     Threshold:   0x%.2X (%d)\n"
+                "Occupied Threshold:   0x%.2X (%d)\n"
+                "Status:               0x%.2X (%d)\n"
+                "   Free spaces  (ot):    %d (%d)\n"
+                "   Occup spaces (ot):    %d (%d)\n"
+                "===========================\n"
+                "write_index: %d\n"
+                "read_index : %d\n"
+                "===========================\n"
+                "\n",
+                mbox_index,
+                readl(m->virtbase_peer + MBOX_FIFO_DATA),
+                readl(m->virtbase_peer + MBOX_FIFO_DATA),
+                readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
+                readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
+                readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
+                readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
+                readl(m->virtbase_peer + MBOX_FIFO_STATUS),
+                readl(m->virtbase_peer + MBOX_FIFO_STATUS),
+                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7,
+                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1,
+                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7,
+                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1,
+                readl(m->virtbase_local + MBOX_FIFO_DATA),
+                readl(m->virtbase_local + MBOX_FIFO_DATA),
+                readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
+                readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
+                readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
+                readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
+                readl(m->virtbase_local + MBOX_FIFO_STATUS),
+                readl(m->virtbase_local + MBOX_FIFO_STATUS),
+                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7,
+                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1,
+                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7,
+                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1,
+                m->write_index, m->read_index);
+                mbox_index++;
+                spin_unlock(&m->lock);
+        }
+
+        return 0;
+}
+
+static int mbox_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, mbox_show, NULL);
+}
+
+static const struct file_operations mbox_operations = {
+        .owner = THIS_MODULE,
+        .open = mbox_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+#endif
+
+static irqreturn_t mbox_irq(int irq, void *arg)
+{
+        u32 mbox_value;
+        int nbr_occup;
+        int nbr_free;
+        struct mbox *mbox = (struct mbox *) arg;
+
+        spin_lock(&mbox->lock);
+
+        dev_dbg(&(mbox->pdev->dev),
+                "mbox IRQ [%d] received. ri = %d, wi = %d\n",
+                irq, mbox->read_index, mbox->write_index);
+
+        /*
+         * Check if we have any outgoing messages, and if there is space for
+         * them in the FIFO.
+         */
+        if (mbox->read_index != mbox->write_index) {
+                /*
+                 * Check by reading FREE for LOCAL since that indicates
+                 * OCCUP for PEER
+                 */
+                nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS)
+                            >> 4) & 0x7;
+                dev_dbg(&(mbox->pdev->dev),
+                        "Status indicates %d empty spaces in the FIFO!\n",
+                        nbr_free);
+
+                while ((nbr_free > 0) &&
+                       (mbox->read_index != mbox->write_index)) {
+                        /* Write the message and latch it into the FIFO */
+                        writel(mbox->buffer[mbox->read_index],
+                               (mbox->virtbase_peer + MBOX_FIFO_DATA));
+                        writel(MBOX_LATCH,
+                               (mbox->virtbase_peer + MBOX_FIFO_ADD));
+                        dev_dbg(&(mbox->pdev->dev),
+                                "Wrote message 0x%X to addr 0x%X\n",
+                                mbox->buffer[mbox->read_index],
+                                (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA));
+
+                        nbr_free--;
+                        mbox->read_index =
+                                (mbox->read_index + 1) % MBOX_BUF_SIZE;
+                }
+
+                /*
+                 * Check if we still want IRQ:s when there is free
+                 * space to send
+                 */
+                if (mbox->read_index != mbox->write_index) {
+                        dev_dbg(&(mbox->pdev->dev),
+                                "Still have messages to send, but FIFO full. "
+                                "Request IRQ again!\n");
+                        writel(MBOX_ENABLE_IRQ,
+                               mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
+                } else {
+                        dev_dbg(&(mbox->pdev->dev),
+                                "No more messages to send. "
+                                "Do not request IRQ again!\n");
+                        writel(MBOX_DISABLE_IRQ,
+                               mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
+                }
+
+                /*
+                 * Check if we can signal any blocked clients that it is OK to
+                 * start buffering again
+                 */
+                if (mbox->client_blocked &&
+                    (((mbox->write_index + 1) % MBOX_BUF_SIZE)
+                     != mbox->read_index)) {
+                        dev_dbg(&(mbox->pdev->dev),
+                                "Waking up blocked client\n");
+                        complete(&mbox->buffer_available);
+                        mbox->client_blocked = 0;
+                }
+        }
+
+        /* Check if we have any incoming messages */
+        nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7;
+        if (nbr_occup == 0)
+                goto exit;
+
+        if (mbox->cb == NULL) {
+                dev_dbg(&(mbox->pdev->dev), "No receive callback registered, "
+                        "leaving %d incoming messages in fifo!\n", nbr_occup);
+                goto exit;
+        }
+
+        /* Read and acknowledge the message */
+        mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
+        writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
+
+        /* Notify consumer of new mailbox message */
+        dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n",
+                mbox_value);
+        mbox->cb(mbox_value, mbox->client_data);
+
+exit:
+        dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n",
+                mbox->read_index, mbox->write_index);
+        spin_unlock(&mbox->lock);
+
+        return IRQ_HANDLED;
+}
+
+/* Setup is executed once for each mbox pair */
+struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv)
+{
+        struct resource *resource;
+        int irq;
+        int res;
+        struct mbox *mbox;
+
+        mbox = get_mbox_with_id(mbox_id);
+        if (mbox == NULL) {
+                dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n",
+                        mbox_id);
+                goto exit;
+        }
+
+        /*
+         * Check if mailbox has been allocated to someone else,
+         * otherwise allocate it
+         */
+        if (mbox->allocated) {
+                dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n",
+                        mbox_id);
+                mbox = NULL;
+                goto exit;
+        }
+        mbox->allocated = true;
+
+        dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n",
+                mbox_id, (u32)mbox);
+
+        mbox->client_data = priv;
+        mbox->cb = mbox_cb;
+
+        /* Get addr for peer mailbox and ioremap it */
+        resource = platform_get_resource_byname(mbox->pdev,
+                                                IORESOURCE_MEM,
+                                                "mbox_peer");
+        if (resource == NULL) {
+                dev_err(&(mbox->pdev->dev),
+                        "Unable to retrieve mbox peer resource\n");
+                mbox = NULL;
+                goto exit;
+        }
+        dev_dbg(&(mbox->pdev->dev),
+                "Resource name: %s start: 0x%X, end: 0x%X\n",
+                resource->name, resource->start, resource->end);
+        mbox->virtbase_peer =
+                ioremap(resource->start, resource->end - resource->start);
+        if (!mbox->virtbase_peer) {
+                dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n");
+                mbox = NULL;
+                goto exit;
+        }
+        dev_dbg(&(mbox->pdev->dev),
+                "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n",
+                resource->start, resource->end, (u32) mbox->virtbase_peer);
+
+        /* Get addr for local mailbox and ioremap it */
+        resource = platform_get_resource_byname(mbox->pdev,
+                                                IORESOURCE_MEM,
+                                                "mbox_local");
+        if (resource == NULL) {
+                dev_err(&(mbox->pdev->dev),
+                        "Unable to retrieve mbox local resource\n");
+                mbox = NULL;
+                goto exit;
+        }
+        dev_dbg(&(mbox->pdev->dev),
+                "Resource name: %s start: 0x%X, end: 0x%X\n",
+                resource->name, resource->start, resource->end);
+        mbox->virtbase_local =
+                ioremap(resource->start, resource->end - resource->start);
+        if (!mbox->virtbase_local) {
+                dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n");
+                mbox = NULL;
+                goto exit;
+        }
+        dev_dbg(&(mbox->pdev->dev),
+                "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n",
+                resource->start, resource->end, (u32) mbox->virtbase_peer);
+
+        init_completion(&mbox->buffer_available);
+        mbox->client_blocked = 0;
+
+        /* Get IRQ for mailbox and allocate it */
+        irq = platform_get_irq_byname(mbox->pdev, "mbox_irq");
+        if (irq < 0) {
+                dev_err(&(mbox->pdev->dev),
+                        "Unable to retrieve mbox irq resource\n");
+                mbox = NULL;
+                goto exit;
+        }
+
+        dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq);
+        res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox);
+        if (res < 0) {
+                dev_err(&(mbox->pdev->dev),
+                        "Unable to allocate mbox irq %d\n", irq);
+                mbox = NULL;
+                goto exit;
+        }
+
+        /* Set up mailbox to not launch IRQ on free space in mailbox */
+        writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
+
+        /*
+         * Set up mailbox to launch IRQ on new message if we have
+         * a callback set. If not, do not raise IRQ, but keep message
+         * in FIFO for manual retrieval
+         */
+        if (mbox_cb != NULL)
+                writel(MBOX_ENABLE_IRQ,
+                       mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
+        else
+                writel(MBOX_DISABLE_IRQ,
+                       mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
+
+#if defined(CONFIG_DEBUG_FS)
+        res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo);
+        if (res != 0)
+                dev_warn(&(mbox->pdev->dev),
+                         "Unable to create mbox sysfs entry");
+
+        (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL,
+                                   NULL, &mbox_operations);
+#endif
+
+        dev_info(&(mbox->pdev->dev),
+                 "Mailbox driver with index %d initated!\n", mbox_id);
+
+exit:
+        return mbox;
+}
+EXPORT_SYMBOL(mbox_setup);
+
+
+int __init mbox_probe(struct platform_device *pdev)
+{
+        struct mbox local_mbox;
+        struct mbox *mbox;
+        int res = 0;
+        dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev);
+
+        memset(&local_mbox, 0x0, sizeof(struct mbox));
+
+        /* Associate our mbox data with the platform device */
+        res = platform_device_add_data(pdev,
+                                       (void *) &local_mbox,
+                                       sizeof(struct mbox));
+        if (res != 0) {
+                dev_err(&(pdev->dev),
+                        "Unable to allocate driver platform data!\n");
+                goto exit;
+        }
+
+        mbox = (struct mbox *) pdev->dev.platform_data;
+        mbox->pdev = pdev;
+        mbox->write_index = 0;
+        mbox->read_index = 0;
+
+        INIT_LIST_HEAD(&(mbox->list));
+        list_add_tail(&(mbox->list), &mboxs);
+
+        sprintf(mbox->name, "%s", MBOX_NAME);
+        spin_lock_init(&mbox->lock);
+
+        dev_info(&(pdev->dev), "Mailbox driver loaded\n");
+
+exit:
+        return res;
+}
+
+static struct platform_driver mbox_driver = {
+        .driver = {
+                .name = MBOX_NAME,
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init mbox_init(void)
+{
+        return platform_driver_probe(&mbox_driver, mbox_probe);
+}
+
+module_init(mbox_init);
+
+void __exit mbox_exit(void)
+{
+        platform_driver_unregister(&mbox_driver);
+}
+
+module_exit(mbox_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MBOX driver");
diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem_irq.c
new file mode 100644
index 00000000000..3187f887116
--- /dev/null
+++ b/arch/arm/mach-ux500/modem_irq.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
+ * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#define MODEM_INTCON_BASE_ADDR 0xBFFD3000
+#define MODEM_INTCON_SIZE 0xFFF
+
+#define DEST_IRQ41_OFFSET 0x2A4
+#define DEST_IRQ43_OFFSET 0x2AC
+#define DEST_IRQ45_OFFSET 0x2B4
+
+#define PRIO_IRQ41_OFFSET 0x6A4
+#define PRIO_IRQ43_OFFSET 0x6AC
+#define PRIO_IRQ45_OFFSET 0x6B4
+
+#define ALLOW_IRQ_OFFSET 0x104
+
+#define MODEM_INTCON_CPU_NBR 0x1
+#define MODEM_INTCON_PRIO_HIGH 0x0
+
+#define MODEM_INTCON_ALLOW_IRQ41 0x0200
+#define MODEM_INTCON_ALLOW_IRQ43 0x0800
+#define MODEM_INTCON_ALLOW_IRQ45 0x2000
+
+#define MODEM_IRQ_REG_OFFSET 0x4
+
+struct modem_irq {
+        void __iomem *modem_intcon_base;
+};
+
+
+static void setup_modem_intcon(void __iomem *modem_intcon_base)
+{
+        /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */
+        writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET);
+        writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET);
+        writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET);
+
+        /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */
+        writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET);
+        writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET);
+        writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET);
+
+        /* IC_ALLOW_ARRAY - IRQ enable */
+        writel(MODEM_INTCON_ALLOW_IRQ41 |
+                   MODEM_INTCON_ALLOW_IRQ43 |
+                   MODEM_INTCON_ALLOW_IRQ45,
+                   modem_intcon_base + ALLOW_IRQ_OFFSET);
+}
+
+static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
+{
+        int real_irq;
+        int virt_irq;
+        struct modem_irq *mi = (struct modem_irq *)data;
+
+        /* Read modem side IRQ number from modem IRQ controller */
+        real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
+        virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
+
+        pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
+                 "which will be 0x%X (%d) which translates to "
+                 "virtual IRQ 0x%X (%d)!\n",
+                   (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
+                   real_irq,
+                   real_irq & 0xFF,
+                   real_irq & 0xFF,
+                   virt_irq,
+                   virt_irq);
+
+        if (virt_irq != 0)
+                generic_handle_irq(virt_irq);
+
+        pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
+
+        return IRQ_HANDLED;
+}
+
+static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
+{
+        set_irq_chip(irq, modem_irq_chip);
+        set_irq_handler(irq, handle_simple_irq);
+        set_irq_flags(irq, IRQF_VALID);
+
+        pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
+}
+
+static int modem_irq_init(void)
+{
+        int err;
+        static struct irq_chip  modem_irq_chip;
+        struct modem_irq *mi;
+
+        pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
+                   IRQ_DB5500_MODEM);
+
+        mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL);
+        if (!mi) {
+                pr_err("modem_irq: Could not allocate device\n");
+                return -ENOMEM;
+        }
+
+        mi->modem_intcon_base =
+                ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE);
+        pr_debug("modem_irq: ioremapped modem_intcon_base from "
+                 "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR,
+                 (u32)mi->modem_intcon_base);
+
+        setup_modem_intcon(mi->modem_intcon_base);
+
+        modem_irq_chip = dummy_irq_chip;
+        modem_irq_chip.name = "modem_irq";
+
+        /* Create the virtual IRQ:s needed */
+        create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip);
+        create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip);
+        create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip);
+
+        err = request_threaded_irq(IRQ_DB5500_MODEM, NULL,
+                                   modem_cpu_irq_handler, IRQF_ONESHOT,
+                                   "modem_irq", mi);
+        if (err)
+                pr_err("modem_irq: Could not register IRQ %d\n",
+                       IRQ_DB5500_MODEM);
+
+        return 0;
+}
+
+arch_initcall(modem_irq_init);
diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h
new file mode 100644
index 00000000000..bf50c21fe69
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db5500.h
@@ -0,0 +1,620 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ */
+
+#ifndef __MACH_DB5500_PINS_H
+#define __MACH_DB5500_PINS_H
+
+#define GPIO0_GPIO              PIN_CFG(0, GPIO)
+#define GPIO0_SM_CS3n           PIN_CFG(0, ALT_A)
+
+#define GPIO1_GPIO              PIN_CFG(1, GPIO)
+#define GPIO1_SM_A3             PIN_CFG(1, ALT_A)
+
+#define GPIO2_GPIO              PIN_CFG(2, GPIO)
+#define GPIO2_SM_A4             PIN_CFG(2, ALT_A)
+#define GPIO2_SM_AVD            PIN_CFG(2, ALT_B)
+
+#define GPIO3_GPIO              PIN_CFG(3, GPIO)
+#define GPIO3_I2C1_SCL          PIN_CFG(3, ALT_A)
+
+#define GPIO4_GPIO              PIN_CFG(4, GPIO)
+#define GPIO4_I2C1_SDA          PIN_CFG(4, ALT_A)
+
+#define GPIO5_GPIO              PIN_CFG(5, GPIO)
+#define GPIO5_MC0_DAT0          PIN_CFG(5, ALT_A)
+#define GPIO5_SM_ADQ8           PIN_CFG(5, ALT_B)
+
+#define GPIO6_GPIO              PIN_CFG(6, GPIO)
+#define GPIO6_MC0_DAT1          PIN_CFG(6, ALT_A)
+#define GPIO6_SM_ADQ0           PIN_CFG(6, ALT_B)
+
+#define GPIO7_GPIO              PIN_CFG(7, GPIO)
+#define GPIO7_MC0_DAT2          PIN_CFG(7, ALT_A)
+#define GPIO7_SM_ADQ9           PIN_CFG(7, ALT_B)
+
+#define GPIO8_GPIO              PIN_CFG(8, GPIO)
+#define GPIO8_MC0_DAT3          PIN_CFG(8, ALT_A)
+#define GPIO8_SM_ADQ1           PIN_CFG(8, ALT_B)
+
+#define GPIO9_GPIO              PIN_CFG(9, GPIO)
+#define GPIO9_MC0_DAT4          PIN_CFG(9, ALT_A)
+#define GPIO9_SM_ADQ10          PIN_CFG(9, ALT_B)
+
+#define GPIO10_GPIO             PIN_CFG(10, GPIO)
+#define GPIO10_MC0_DAT5         PIN_CFG(10, ALT_A)
+#define GPIO10_SM_ADQ2          PIN_CFG(10, ALT_B)
+
+#define GPIO11_GPIO             PIN_CFG(11, GPIO)
+#define GPIO11_MC0_DAT6         PIN_CFG(11, ALT_A)
+#define GPIO11_SM_ADQ11         PIN_CFG(11, ALT_B)
+
+#define GPIO12_GPIO             PIN_CFG(12, GPIO)
+#define GPIO12_MC0_DAT7         PIN_CFG(12, ALT_A)
+#define GPIO12_SM_ADQ3          PIN_CFG(12, ALT_B)
+
+#define GPIO13_GPIO             PIN_CFG(13, GPIO)
+#define GPIO13_MC0_CMD          PIN_CFG(13, ALT_A)
+#define GPIO13_SM_BUSY0n        PIN_CFG(13, ALT_B)
+#define GPIO13_SM_WAIT0n        PIN_CFG(13, ALT_C)
+
+#define GPIO14_GPIO             PIN_CFG(14, GPIO)
+#define GPIO14_MC0_CLK          PIN_CFG(14, ALT_A)
+#define GPIO14_SM_CS1n          PIN_CFG(14, ALT_B)
+#define GPIO14_SM_CKO           PIN_CFG(14, ALT_C)
+
+#define GPIO15_GPIO             PIN_CFG(15, GPIO)
+#define GPIO15_SM_A5            PIN_CFG(15, ALT_A)
+#define GPIO15_SM_CLE           PIN_CFG(15, ALT_B)
+
+#define GPIO16_GPIO             PIN_CFG(16, GPIO)
+#define GPIO16_MC2_CMD          PIN_CFG(16, ALT_A)
+#define GPIO16_SM_OEn           PIN_CFG(16, ALT_B)
+
+#define GPIO17_GPIO             PIN_CFG(17, GPIO)
+#define GPIO17_MC2_CLK          PIN_CFG(17, ALT_A)
+#define GPIO17_SM_WEn           PIN_CFG(17, ALT_B)
+
+#define GPIO18_GPIO             PIN_CFG(18, GPIO)
+#define GPIO18_SM_A6            PIN_CFG(18, ALT_A)
+#define GPIO18_SM_ALE           PIN_CFG(18, ALT_B)
+#define GPIO18_SM_AVDn          PIN_CFG(18, ALT_C)
+
+#define GPIO19_GPIO             PIN_CFG(19, GPIO)
+#define GPIO19_MC2_DAT1         PIN_CFG(19, ALT_A)
+#define GPIO19_SM_ADQ4          PIN_CFG(19, ALT_B)
+
+#define GPIO20_GPIO             PIN_CFG(20, GPIO)
+#define GPIO20_MC2_DAT3         PIN_CFG(20, ALT_A)
+#define GPIO20_SM_ADQ5          PIN_CFG(20, ALT_B)
+
+#define GPIO21_GPIO             PIN_CFG(21, GPIO)
+#define GPIO21_MC2_DAT5         PIN_CFG(21, ALT_A)
+#define GPIO21_SM_ADQ6          PIN_CFG(21, ALT_B)
+
+#define GPIO22_GPIO             PIN_CFG(22, GPIO)
+#define GPIO22_MC2_DAT7         PIN_CFG(22, ALT_A)
+#define GPIO22_SM_ADQ7          PIN_CFG(22, ALT_B)
+
+#define GPIO23_GPIO             PIN_CFG(23, GPIO)
+#define GPIO23_MC2_DAT0         PIN_CFG(23, ALT_A)
+#define GPIO23_SM_ADQ12         PIN_CFG(23, ALT_B)
+#define GPIO23_MC0_DAT1         PIN_CFG(23, ALT_C)
+
+#define GPIO24_GPIO             PIN_CFG(24, GPIO)
+#define GPIO24_MC2_DAT2         PIN_CFG(24, ALT_A)
+#define GPIO24_SM_ADQ13         PIN_CFG(24, ALT_B)
+#define GPIO24_MC0_DAT3         PIN_CFG(24, ALT_C)
+
+#define GPIO25_GPIO             PIN_CFG(25, GPIO)
+#define GPIO25_MC2_DAT4         PIN_CFG(25, ALT_A)
+#define GPIO25_SM_ADQ14         PIN_CFG(25, ALT_B)
+#define GPIO25_MC0_CMD          PIN_CFG(25, ALT_C)
+
+#define GPIO26_GPIO             PIN_CFG(26, GPIO)
+#define GPIO26_MC2_DAT6         PIN_CFG(26, ALT_A)
+#define GPIO26_SM_ADQ15         PIN_CFG(26, ALT_B)
+
+#define GPIO27_GPIO             PIN_CFG(27, GPIO)
+#define GPIO27_SM_CS0n          PIN_CFG(27, ALT_A)
+#define GPIO27_SM_PS0n          PIN_CFG(27, ALT_B)
+
+#define GPIO28_GPIO             PIN_CFG(28, GPIO)
+#define GPIO28_U0_TXD           PIN_CFG(28, ALT_A)
+#define GPIO28_SM_A0            PIN_CFG(28, ALT_B)
+
+#define GPIO29_GPIO             PIN_CFG(29, GPIO)
+#define GPIO29_U0_RXD           PIN_CFG(29, ALT_A)
+#define GPIO29_SM_A1            PIN_CFG(29, ALT_B)
+#define GPIO29_PWM_0            PIN_CFG(29, ALT_C)
+
+#define GPIO30_GPIO             PIN_CFG(30, GPIO)
+#define GPIO30_MC0_DAT5         PIN_CFG(30, ALT_A)
+#define GPIO30_SM_A2            PIN_CFG(30, ALT_B)
+#define GPIO30_PWM_1            PIN_CFG(30, ALT_C)
+
+#define GPIO31_GPIO             PIN_CFG(31, GPIO)
+#define GPIO31_MC0_DAT7         PIN_CFG(31, ALT_A)
+#define GPIO31_SM_CS2n          PIN_CFG(31, ALT_B)
+#define GPIO31_PWM_2            PIN_CFG(31, ALT_C)
+
+#define GPIO32_GPIO             PIN_CFG(32, GPIO)
+#define GPIO32_MSP0_TCK         PIN_CFG(32, ALT_A)
+#define GPIO32_ACCI2S0_SCK      PIN_CFG(32, ALT_B)
+
+#define GPIO33_GPIO             PIN_CFG(33, GPIO)
+#define GPIO33_MSP0_TFS         PIN_CFG(33, ALT_A)
+#define GPIO33_ACCI2S0_WS       PIN_CFG(33, ALT_B)
+
+#define GPIO34_GPIO             PIN_CFG(34, GPIO)
+#define GPIO34_MSP0_TXD         PIN_CFG(34, ALT_A)
+#define GPIO34_ACCI2S0_DLD      PIN_CFG(34, ALT_B)
+
+#define GPIO35_GPIO             PIN_CFG(35, GPIO)
+#define GPIO35_MSP0_RXD         PIN_CFG(35, ALT_A)
+#define GPIO35_ACCI2S0_ULD      PIN_CFG(35, ALT_B)
+
+#define GPIO64_GPIO             PIN_CFG(64, GPIO)
+#define GPIO64_USB_DAT0         PIN_CFG(64, ALT_A)
+#define GPIO64_U0_TXD           PIN_CFG(64, ALT_B)
+
+#define GPIO65_GPIO             PIN_CFG(65, GPIO)
+#define GPIO65_USB_DAT1         PIN_CFG(65, ALT_A)
+#define GPIO65_U0_RXD           PIN_CFG(65, ALT_B)
+
+#define GPIO66_GPIO             PIN_CFG(66, GPIO)
+#define GPIO66_USB_DAT2         PIN_CFG(66, ALT_A)
+
+#define GPIO67_GPIO             PIN_CFG(67, GPIO)
+#define GPIO67_USB_DAT3         PIN_CFG(67, ALT_A)
+
+#define GPIO68_GPIO             PIN_CFG(68, GPIO)
+#define GPIO68_USB_DAT4         PIN_CFG(68, ALT_A)
+
+#define GPIO69_GPIO             PIN_CFG(69, GPIO)
+#define GPIO69_USB_DAT5         PIN_CFG(69, ALT_A)
+
+#define GPIO70_GPIO             PIN_CFG(70, GPIO)
+#define GPIO70_USB_DAT6         PIN_CFG(70, ALT_A)
+
+#define GPIO71_GPIO             PIN_CFG(71, GPIO)
+#define GPIO71_USB_DAT7         PIN_CFG(71, ALT_A)
+
+#define GPIO72_GPIO             PIN_CFG(72, GPIO)
+#define GPIO72_USB_STP          PIN_CFG(72, ALT_A)
+
+#define GPIO73_GPIO             PIN_CFG(73, GPIO)
+#define GPIO73_USB_DIR          PIN_CFG(73, ALT_A)
+
+#define GPIO74_GPIO             PIN_CFG(74, GPIO)
+#define GPIO74_USB_NXT          PIN_CFG(74, ALT_A)
+
+#define GPIO75_GPIO             PIN_CFG(75, GPIO)
+#define GPIO75_USB_XCLK         PIN_CFG(75, ALT_A)
+
+#define GPIO76_GPIO             PIN_CFG(76, GPIO)
+
+#define GPIO77_GPIO             PIN_CFG(77, GPIO)
+#define GPIO77_ACCTX_ON         PIN_CFG(77, ALT_A)
+
+#define GPIO78_GPIO             PIN_CFG(78, GPIO)
+#define GPIO78_IRQn             PIN_CFG(78, ALT_A)
+
+#define GPIO79_GPIO             PIN_CFG(79, GPIO)
+#define GPIO79_ACCSIM_Clk       PIN_CFG(79, ALT_A)
+
+#define GPIO80_GPIO             PIN_CFG(80, GPIO)
+#define GPIO80_ACCSIM_Da        PIN_CFG(80, ALT_A)
+
+#define GPIO81_GPIO             PIN_CFG(81, GPIO)
+#define GPIO81_ACCSIM_Reset     PIN_CFG(81, ALT_A)
+
+#define GPIO82_GPIO             PIN_CFG(82, GPIO)
+#define GPIO82_ACCSIM_DDir      PIN_CFG(82, ALT_A)
+
+#define GPIO96_GPIO             PIN_CFG(96, GPIO)
+#define GPIO96_MSP1_TCK         PIN_CFG(96, ALT_A)
+#define GPIO96_PRCMU_DEBUG3     PIN_CFG(96, ALT_B)
+#define GPIO96_PRCMU_DEBUG7     PIN_CFG(96, ALT_C)
+
+#define GPIO97_GPIO             PIN_CFG(97, GPIO)
+#define GPIO97_MSP1_TFS         PIN_CFG(97, ALT_A)
+#define GPIO97_PRCMU_DEBUG2     PIN_CFG(97, ALT_B)
+#define GPIO97_PRCMU_DEBUG6     PIN_CFG(97, ALT_C)
+
+#define GPIO98_GPIO             PIN_CFG(98, GPIO)
+#define GPIO98_MSP1_TXD         PIN_CFG(98, ALT_A)
+#define GPIO98_PRCMU_DEBUG1     PIN_CFG(98, ALT_B)
+#define GPIO98_PRCMU_DEBUG5     PIN_CFG(98, ALT_C)
+
+#define GPIO99_GPIO             PIN_CFG(99, GPIO)
+#define GPIO99_MSP1_RXD         PIN_CFG(99, ALT_A)
+#define GPIO99_PRCMU_DEBUG0     PIN_CFG(99, ALT_B)
+#define GPIO99_PRCMU_DEBUG4     PIN_CFG(99, ALT_C)
+
+#define GPIO100_GPIO            PIN_CFG(100, GPIO)
+#define GPIO100_I2C0_SCL        PIN_CFG(100, ALT_A)
+
+#define GPIO101_GPIO            PIN_CFG(101, GPIO)
+#define GPIO101_I2C0_SDA        PIN_CFG(101, ALT_A)
+
+#define GPIO128_GPIO            PIN_CFG(128, GPIO)
+#define GPIO128_KP_I0           PIN_CFG(128, ALT_A)
+#define GPIO128_BUSMON_D0       PIN_CFG(128, ALT_B)
+
+#define GPIO129_GPIO            PIN_CFG(129, GPIO)
+#define GPIO129_KP_O0           PIN_CFG(129, ALT_A)
+#define GPIO129_BUSMON_D1       PIN_CFG(129, ALT_B)
+
+#define GPIO130_GPIO            PIN_CFG(130, GPIO)
+#define GPIO130_KP_I1           PIN_CFG(130, ALT_A)
+#define GPIO130_BUSMON_D2       PIN_CFG(130, ALT_B)
+
+#define GPIO131_GPIO            PIN_CFG(131, GPIO)
+#define GPIO131_KP_O1           PIN_CFG(131, ALT_A)
+#define GPIO131_BUSMON_D3       PIN_CFG(131, ALT_B)
+
+#define GPIO132_GPIO            PIN_CFG(132, GPIO)
+#define GPIO132_KP_I2           PIN_CFG(132, ALT_A)
+#define GPIO132_ETM_D15         PIN_CFG(132, ALT_B)
+#define GPIO132_STMAPE_CLK      PIN_CFG(132, ALT_C)
+
+#define GPIO133_GPIO            PIN_CFG(133, GPIO)
+#define GPIO133_KP_O2           PIN_CFG(133, ALT_A)
+#define GPIO133_ETM_D14         PIN_CFG(133, ALT_B)
+#define GPIO133_U0_RXD          PIN_CFG(133, ALT_C)
+
+#define GPIO134_GPIO            PIN_CFG(134, GPIO)
+#define GPIO134_KP_I3           PIN_CFG(134, ALT_A)
+#define GPIO134_ETM_D13         PIN_CFG(134, ALT_B)
+#define GPIO134_STMAPE_DAT0     PIN_CFG(134, ALT_C)
+
+#define GPIO135_GPIO            PIN_CFG(135, GPIO)
+#define GPIO135_KP_O3           PIN_CFG(135, ALT_A)
+#define GPIO135_ETM_D12         PIN_CFG(135, ALT_B)
+#define GPIO135_STMAPE_DAT1     PIN_CFG(135, ALT_C)
+
+#define GPIO136_GPIO            PIN_CFG(136, GPIO)
+#define GPIO136_KP_I4           PIN_CFG(136, ALT_A)
+#define GPIO136_ETM_D11         PIN_CFG(136, ALT_B)
+#define GPIO136_STMAPE_DAT2     PIN_CFG(136, ALT_C)
+
+#define GPIO137_GPIO            PIN_CFG(137, GPIO)
+#define GPIO137_KP_O4           PIN_CFG(137, ALT_A)
+#define GPIO137_ETM_D10         PIN_CFG(137, ALT_B)
+#define GPIO137_STMAPE_DAT3     PIN_CFG(137, ALT_C)
+
+#define GPIO138_GPIO            PIN_CFG(138, GPIO)
+#define GPIO138_KP_I5           PIN_CFG(138, ALT_A)
+#define GPIO138_ETM_D9          PIN_CFG(138, ALT_B)
+#define GPIO138_U0_TXD          PIN_CFG(138, ALT_C)
+
+#define GPIO139_GPIO            PIN_CFG(139, GPIO)
+#define GPIO139_KP_O5           PIN_CFG(139, ALT_A)
+#define GPIO139_ETM_D8          PIN_CFG(139, ALT_B)
+#define GPIO139_BUSMON_D11      PIN_CFG(139, ALT_C)
+
+#define GPIO140_GPIO            PIN_CFG(140, GPIO)
+#define GPIO140_KP_I6           PIN_CFG(140, ALT_A)
+#define GPIO140_ETM_D7          PIN_CFG(140, ALT_B)
+#define GPIO140_STMAPE_CLK      PIN_CFG(140, ALT_C)
+
+#define GPIO141_GPIO            PIN_CFG(141, GPIO)
+#define GPIO141_KP_O6           PIN_CFG(141, ALT_A)
+#define GPIO141_ETM_D6          PIN_CFG(141, ALT_B)
+#define GPIO141_U0_RXD          PIN_CFG(141, ALT_C)
+
+#define GPIO142_GPIO            PIN_CFG(142, GPIO)
+#define GPIO142_KP_I7           PIN_CFG(142, ALT_A)
+#define GPIO142_ETM_D5          PIN_CFG(142, ALT_B)
+#define GPIO142_STMAPE_DAT0     PIN_CFG(142, ALT_C)
+
+#define GPIO143_GPIO            PIN_CFG(143, GPIO)
+#define GPIO143_KP_O7           PIN_CFG(143, ALT_A)
+#define GPIO143_ETM_D4          PIN_CFG(143, ALT_B)
+#define GPIO143_STMAPE_DAT1     PIN_CFG(143, ALT_C)
+
+#define GPIO144_GPIO            PIN_CFG(144, GPIO)
+#define GPIO144_I2C3_SCL        PIN_CFG(144, ALT_A)
+#define GPIO144_ETM_D3          PIN_CFG(144, ALT_B)
+#define GPIO144_STMAPE_DAT2     PIN_CFG(144, ALT_C)
+
+#define GPIO145_GPIO            PIN_CFG(145, GPIO)
+#define GPIO145_I2C3_SDA        PIN_CFG(145, ALT_A)
+#define GPIO145_ETM_D2          PIN_CFG(145, ALT_B)
+#define GPIO145_STMAPE_DAT3     PIN_CFG(145, ALT_C)
+
+#define GPIO146_GPIO            PIN_CFG(146, GPIO)
+#define GPIO146_PWM_0           PIN_CFG(146, ALT_A)
+#define GPIO146_ETM_D1          PIN_CFG(146, ALT_B)
+
+#define GPIO147_GPIO            PIN_CFG(147, GPIO)
+#define GPIO147_PWM_1           PIN_CFG(147, ALT_A)
+#define GPIO147_ETM_D0          PIN_CFG(147, ALT_B)
+
+#define GPIO148_GPIO            PIN_CFG(148, GPIO)
+#define GPIO148_PWM_2           PIN_CFG(148, ALT_A)
+#define GPIO148_ETM_CLK         PIN_CFG(148, ALT_B)
+
+#define GPIO160_GPIO            PIN_CFG(160, GPIO)
+#define GPIO160_CLKOUT_REQn     PIN_CFG(160, ALT_A)
+
+#define GPIO161_GPIO            PIN_CFG(161, GPIO)
+#define GPIO161_CLKOUT_0        PIN_CFG(161, ALT_A)
+
+#define GPIO162_GPIO            PIN_CFG(162, GPIO)
+#define GPIO162_CLKOUT_1        PIN_CFG(162, ALT_A)
+
+#define GPIO163_GPIO            PIN_CFG(163, GPIO)
+
+#define GPIO164_GPIO            PIN_CFG(164, GPIO)
+#define GPIO164_GPS_START       PIN_CFG(164, ALT_A)
+
+#define GPIO165_GPIO            PIN_CFG(165, GPIO)
+#define GPIO165_SPI1_CS2n       PIN_CFG(165, ALT_A)
+#define GPIO165_U3_RXD          PIN_CFG(165, ALT_B)
+#define GPIO165_BUSMON_D20      PIN_CFG(165, ALT_C)
+
+#define GPIO166_GPIO            PIN_CFG(166, GPIO)
+#define GPIO166_SPI1_CS1n       PIN_CFG(166, ALT_A)
+#define GPIO166_U3_TXD          PIN_CFG(166, ALT_B)
+#define GPIO166_BUSMON_D21      PIN_CFG(166, ALT_C)
+
+#define GPIO167_GPIO            PIN_CFG(167, GPIO)
+#define GPIO167_SPI1_CS0n       PIN_CFG(167, ALT_A)
+#define GPIO167_U3_RTSn         PIN_CFG(167, ALT_B)
+#define GPIO167_BUSMON_D22      PIN_CFG(167, ALT_C)
+
+#define GPIO168_GPIO            PIN_CFG(168, GPIO)
+#define GPIO168_SPI1_RXD        PIN_CFG(168, ALT_A)
+#define GPIO168_U3_CTSn         PIN_CFG(168, ALT_B)
+#define GPIO168_BUSMON_D23      PIN_CFG(168, ALT_C)
+
+#define GPIO169_GPIO            PIN_CFG(169, GPIO)
+#define GPIO169_SPI1_TXD        PIN_CFG(169, ALT_A)
+#define GPIO169_DDR_RC          PIN_CFG(169, ALT_B)
+#define GPIO169_BUSMON_D24      PIN_CFG(169, ALT_C)
+
+#define GPIO170_GPIO            PIN_CFG(170, GPIO)
+#define GPIO170_SPI1_CLK        PIN_CFG(170, ALT_A)
+
+#define GPIO171_GPIO            PIN_CFG(171, GPIO)
+#define GPIO171_MC3_DAT0        PIN_CFG(171, ALT_A)
+#define GPIO171_SPI3_RXD        PIN_CFG(171, ALT_B)
+#define GPIO171_BUSMON_D25      PIN_CFG(171, ALT_C)
+
+#define GPIO172_GPIO            PIN_CFG(172, GPIO)
+#define GPIO172_MC3_DAT1        PIN_CFG(172, ALT_A)
+#define GPIO172_SPI3_CS1n       PIN_CFG(172, ALT_B)
+#define GPIO172_BUSMON_D26      PIN_CFG(172, ALT_C)
+
+#define GPIO173_GPIO            PIN_CFG(173, GPIO)
+#define GPIO173_MC3_DAT2        PIN_CFG(173, ALT_A)
+#define GPIO173_SPI3_CS2n       PIN_CFG(173, ALT_B)
+#define GPIO173_BUSMON_D27      PIN_CFG(173, ALT_C)
+
+#define GPIO174_GPIO            PIN_CFG(174, GPIO)
+#define GPIO174_MC3_DAT3        PIN_CFG(174, ALT_A)
+#define GPIO174_SPI3_CS0n       PIN_CFG(174, ALT_B)
+#define GPIO174_BUSMON_D28      PIN_CFG(174, ALT_C)
+
+#define GPIO175_GPIO            PIN_CFG(175, GPIO)
+#define GPIO175_MC3_CMD         PIN_CFG(175, ALT_A)
+#define GPIO175_SPI3_TXD        PIN_CFG(175, ALT_B)
+#define GPIO175_BUSMON_D29      PIN_CFG(175, ALT_C)
+
+#define GPIO176_GPIO            PIN_CFG(176, GPIO)
+#define GPIO176_MC3_CLK         PIN_CFG(176, ALT_A)
+#define GPIO176_SPI3_CLK        PIN_CFG(176, ALT_B)
+
+#define GPIO177_GPIO            PIN_CFG(177, GPIO)
+#define GPIO177_U2_RXD          PIN_CFG(177, ALT_A)
+#define GPIO177_I2C3_SCL        PIN_CFG(177, ALT_B)
+#define GPIO177_BUSMON_D30      PIN_CFG(177, ALT_C)
+
+#define GPIO178_GPIO            PIN_CFG(178, GPIO)
+#define GPIO178_U2_TXD          PIN_CFG(178, ALT_A)
+#define GPIO178_I2C3_SDA        PIN_CFG(178, ALT_B)
+#define GPIO178_BUSMON_D31      PIN_CFG(178, ALT_C)
+
+#define GPIO179_GPIO            PIN_CFG(179, GPIO)
+#define GPIO179_U2_CTSn         PIN_CFG(179, ALT_A)
+#define GPIO179_U3_RXD          PIN_CFG(179, ALT_B)
+#define GPIO179_BUSMON_D32      PIN_CFG(179, ALT_C)
+
+#define GPIO180_GPIO            PIN_CFG(180, GPIO)
+#define GPIO180_U2_RTSn         PIN_CFG(180, ALT_A)
+#define GPIO180_U3_TXD          PIN_CFG(180, ALT_B)
+#define GPIO180_BUSMON_D33      PIN_CFG(180, ALT_C)
+
+#define GPIO185_GPIO            PIN_CFG(185, GPIO)
+#define GPIO185_SPI3_CS2n       PIN_CFG(185, ALT_A)
+#define GPIO185_MC4_DAT0        PIN_CFG(185, ALT_B)
+
+#define GPIO186_GPIO            PIN_CFG(186, GPIO)
+#define GPIO186_SPI3_CS1n       PIN_CFG(186, ALT_A)
+#define GPIO186_MC4_DAT1        PIN_CFG(186, ALT_B)
+
+#define GPIO187_GPIO            PIN_CFG(187, GPIO)
+#define GPIO187_SPI3_CS0n       PIN_CFG(187, ALT_A)
+#define GPIO187_MC4_DAT2        PIN_CFG(187, ALT_B)
+
+#define GPIO188_GPIO            PIN_CFG(188, GPIO)
+#define GPIO188_SPI3_RXD        PIN_CFG(188, ALT_A)
+#define GPIO188_MC4_DAT3        PIN_CFG(188, ALT_B)
+
+#define GPIO189_GPIO            PIN_CFG(189, GPIO)
+#define GPIO189_SPI3_TXD        PIN_CFG(189, ALT_A)
+#define GPIO189_MC4_CMD         PIN_CFG(189, ALT_B)
+
+#define GPIO190_GPIO            PIN_CFG(190, GPIO)
+#define GPIO190_SPI3_CLK        PIN_CFG(190, ALT_A)
+#define GPIO190_MC4_CLK         PIN_CFG(190, ALT_B)
+
+#define GPIO191_GPIO            PIN_CFG(191, GPIO)
+#define GPIO191_MC1_DAT0        PIN_CFG(191, ALT_A)
+#define GPIO191_MC4_DAT4        PIN_CFG(191, ALT_B)
+#define GPIO191_STMAPE_DAT0     PIN_CFG(191, ALT_C)
+
+#define GPIO192_GPIO            PIN_CFG(192, GPIO)
+#define GPIO192_MC1_DAT1        PIN_CFG(192, ALT_A)
+#define GPIO192_MC4_DAT5        PIN_CFG(192, ALT_B)
+#define GPIO192_STMAPE_DAT1     PIN_CFG(192, ALT_C)
+
+#define GPIO193_GPIO            PIN_CFG(193, GPIO)
+#define GPIO193_MC1_DAT2        PIN_CFG(193, ALT_A)
+#define GPIO193_MC4_DAT6        PIN_CFG(193, ALT_B)
+#define GPIO193_STMAPE_DAT2     PIN_CFG(193, ALT_C)
+
+#define GPIO194_GPIO            PIN_CFG(194, GPIO)
+#define GPIO194_MC1_DAT3        PIN_CFG(194, ALT_A)
+#define GPIO194_MC4_DAT7        PIN_CFG(194, ALT_B)
+#define GPIO194_STMAPE_DAT3     PIN_CFG(194, ALT_C)
+
+#define GPIO195_GPIO            PIN_CFG(195, GPIO)
+#define GPIO195_MC1_CLK         PIN_CFG(195, ALT_A)
+#define GPIO195_STMAPE_CLK      PIN_CFG(195, ALT_B)
+#define GPIO195_BUSMON_CLK      PIN_CFG(195, ALT_C)
+
+#define GPIO196_GPIO            PIN_CFG(196, GPIO)
+#define GPIO196_MC1_CMD         PIN_CFG(196, ALT_A)
+#define GPIO196_U0_RXD          PIN_CFG(196, ALT_B)
+#define GPIO196_BUSMON_D38      PIN_CFG(196, ALT_C)
+
+#define GPIO197_GPIO            PIN_CFG(197, GPIO)
+#define GPIO197_MC1_CMDDIR      PIN_CFG(197, ALT_A)
+#define GPIO197_BUSMON_D39      PIN_CFG(197, ALT_B)
+
+#define GPIO198_GPIO            PIN_CFG(198, GPIO)
+#define GPIO198_MC1_FBCLK       PIN_CFG(198, ALT_A)
+
+#define GPIO199_GPIO            PIN_CFG(199, GPIO)
+#define GPIO199_MC1_DAT0DIR     PIN_CFG(199, ALT_A)
+#define GPIO199_BUSMON_D40      PIN_CFG(199, ALT_B)
+
+#define GPIO200_GPIO            PIN_CFG(200, GPIO)
+#define GPIO200_U1_TXD          PIN_CFG(200, ALT_A)
+#define GPIO200_ACCU0_RTSn      PIN_CFG(200, ALT_B)
+
+#define GPIO201_GPIO            PIN_CFG(201, GPIO)
+#define GPIO201_U1_RXD          PIN_CFG(201, ALT_A)
+#define GPIO201_ACCU0_CTSn      PIN_CFG(201, ALT_B)
+
+#define GPIO202_GPIO            PIN_CFG(202, GPIO)
+#define GPIO202_U1_CTSn         PIN_CFG(202, ALT_A)
+#define GPIO202_ACCU0_RXD       PIN_CFG(202, ALT_B)
+
+#define GPIO203_GPIO            PIN_CFG(203, GPIO)
+#define GPIO203_U1_RTSn         PIN_CFG(203, ALT_A)
+#define GPIO203_ACCU0_TXD       PIN_CFG(203, ALT_B)
+
+#define GPIO204_GPIO            PIN_CFG(204, GPIO)
+#define GPIO204_SPI0_CS2n       PIN_CFG(204, ALT_A)
+#define GPIO204_ACCGPIO_000     PIN_CFG(204, ALT_B)
+#define GPIO204_LCD_VSI1        PIN_CFG(204, ALT_C)
+
+#define GPIO205_GPIO            PIN_CFG(205, GPIO)
+#define GPIO205_SPI0_CS1n       PIN_CFG(205, ALT_A)
+#define GPIO205_ACCGPIO_001     PIN_CFG(205, ALT_B)
+#define GPIO205_LCD_D3          PIN_CFG(205, ALT_C)
+
+#define GPIO206_GPIO            PIN_CFG(206, GPIO)
+#define GPIO206_SPI0_CS0n       PIN_CFG(206, ALT_A)
+#define GPIO206_ACCGPIO_002     PIN_CFG(206, ALT_B)
+#define GPIO206_LCD_D2          PIN_CFG(206, ALT_C)
+
+#define GPIO207_GPIO            PIN_CFG(207, GPIO)
+#define GPIO207_SPI0_RXD        PIN_CFG(207, ALT_A)
+#define GPIO207_ACCGPIO_003     PIN_CFG(207, ALT_B)
+#define GPIO207_LCD_D1          PIN_CFG(207, ALT_C)
+
+#define GPIO208_GPIO            PIN_CFG(208, GPIO)
+#define GPIO208_SPI0_TXD        PIN_CFG(208, ALT_A)
+#define GPIO208_ACCGPIO_004     PIN_CFG(208, ALT_B)
+#define GPIO208_LCD_D0          PIN_CFG(208, ALT_C)
+
+#define GPIO209_GPIO            PIN_CFG(209, GPIO)
+#define GPIO209_SPI0_CLK        PIN_CFG(209, ALT_A)
+#define GPIO209_ACCGPIO_005     PIN_CFG(209, ALT_B)
+#define GPIO209_LCD_CLK         PIN_CFG(209, ALT_C)
+
+#define GPIO210_GPIO            PIN_CFG(210, GPIO)
+#define GPIO210_LCD_VSO         PIN_CFG(210, ALT_A)
+#define GPIO210_PRCMU_PWRCTRL1  PIN_CFG(210, ALT_B)
+
+#define GPIO211_GPIO            PIN_CFG(211, GPIO)
+#define GPIO211_LCD_VSI0        PIN_CFG(211, ALT_A)
+#define GPIO211_PRCMU_PWRCTRL2  PIN_CFG(211, ALT_B)
+
+#define GPIO212_GPIO            PIN_CFG(212, GPIO)
+#define GPIO212_SPI2_CS2n       PIN_CFG(212, ALT_A)
+#define GPIO212_LCD_HSO         PIN_CFG(212, ALT_B)
+
+#define GPIO213_GPIO            PIN_CFG(213, GPIO)
+#define GPIO213_SPI2_CS1n       PIN_CFG(213, ALT_A)
+#define GPIO213_LCD_DE          PIN_CFG(213, ALT_B)
+#define GPIO213_BUSMON_D16      PIN_CFG(213, ALT_C)
+
+#define GPIO214_GPIO            PIN_CFG(214, GPIO)
+#define GPIO214_SPI2_CS0n       PIN_CFG(214, ALT_A)
+#define GPIO214_LCD_D7          PIN_CFG(214, ALT_B)
+#define GPIO214_BUSMON_D17      PIN_CFG(214, ALT_C)
+
+#define GPIO215_GPIO            PIN_CFG(215, GPIO)
+#define GPIO215_SPI2_RXD        PIN_CFG(215, ALT_A)
+#define GPIO215_LCD_D6          PIN_CFG(215, ALT_B)
+#define GPIO215_BUSMON_D18      PIN_CFG(215, ALT_C)
+
+#define GPIO216_GPIO            PIN_CFG(216, GPIO)
+#define GPIO216_SPI2_CLK        PIN_CFG(216, ALT_A)
+#define GPIO216_LCD_D5          PIN_CFG(216, ALT_B)
+
+#define GPIO217_GPIO            PIN_CFG(217, GPIO)
+#define GPIO217_SPI2_TXD        PIN_CFG(217, ALT_A)
+#define GPIO217_LCD_D4          PIN_CFG(217, ALT_B)
+#define GPIO217_BUSMON_D19      PIN_CFG(217, ALT_C)
+
+#define GPIO218_GPIO            PIN_CFG(218, GPIO)
+#define GPIO218_I2C2_SCL        PIN_CFG(218, ALT_A)
+#define GPIO218_LCD_VSO         PIN_CFG(218, ALT_B)
+
+#define GPIO219_GPIO            PIN_CFG(219, GPIO)
+#define GPIO219_I2C2_SDA        PIN_CFG(219, ALT_A)
+#define GPIO219_LCD_D3          PIN_CFG(219, ALT_B)
+
+#define GPIO220_GPIO            PIN_CFG(220, GPIO)
+#define GPIO220_MSP2_TCK        PIN_CFG(220, ALT_A)
+#define GPIO220_LCD_D2          PIN_CFG(220, ALT_B)
+
+#define GPIO221_GPIO            PIN_CFG(221, GPIO)
+#define GPIO221_MSP2_TFS        PIN_CFG(221, ALT_A)
+#define GPIO221_LCD_D1          PIN_CFG(221, ALT_B)
+
+#define GPIO222_GPIO            PIN_CFG(222, GPIO)
+#define GPIO222_MSP2_TXD        PIN_CFG(222, ALT_A)
+#define GPIO222_LCD_D0          PIN_CFG(222, ALT_B)
+
+#define GPIO223_GPIO            PIN_CFG(223, GPIO)
+#define GPIO223_MSP2_RXD        PIN_CFG(223, ALT_A)
+#define GPIO223_LCD_CLK         PIN_CFG(223, ALT_B)
+
+#define GPIO224_GPIO            PIN_CFG(224, GPIO)
+#define GPIO224_PRCMU_PWRCTRL0  PIN_CFG(224, ALT_A)
+#define GPIO224_LCD_VSI1        PIN_CFG(224, ALT_B)
+
+#define GPIO225_GPIO            PIN_CFG(225, GPIO)
+#define GPIO225_PRCMU_PWRCTRL1  PIN_CFG(225, ALT_A)
+#define GPIO225_IRDA_RXD        PIN_CFG(225, ALT_B)
+
+#define GPIO226_GPIO            PIN_CFG(226, GPIO)
+#define GPIO226_PRCMU_PWRCTRL2  PIN_CFG(226, ALT_A)
+#define GPIO226_IRRC_DAT        PIN_CFG(226, ALT_B)
+
+#define GPIO227_GPIO            PIN_CFG(227, GPIO)
+#define GPIO227_IRRC_DAT        PIN_CFG(227, ALT_A)
+#define GPIO227_IRDA_TXD        PIN_CFG(227, ALT_B)
+
+#endif
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index 9055d5d3233..f923764ee16 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -96,57 +96,57 @@
 #define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
 
 #define GPIO18_GPIO             PIN_CFG(18, GPIO)
-#define GPIO18_MC0_CMDDIR       PIN_CFG(18, ALT_A)
+#define GPIO18_MC0_CMDDIR       PIN_CFG_PULL(18, ALT_A, UP)
 #define GPIO18_U2_RXD           PIN_CFG(18, ALT_B)
 #define GPIO18_MS_IEP           PIN_CFG(18, ALT_C)
 
 #define GPIO19_GPIO             PIN_CFG(19, GPIO)
-#define GPIO19_MC0_DAT0DIR      PIN_CFG(19, ALT_A)
+#define GPIO19_MC0_DAT0DIR      PIN_CFG_PULL(19, ALT_A, UP)
 #define GPIO19_U2_TXD           PIN_CFG(19, ALT_B)
 #define GPIO19_MS_DAT0DIR       PIN_CFG(19, ALT_C)
 
 #define GPIO20_GPIO             PIN_CFG(20, GPIO)
-#define GPIO20_MC0_DAT2DIR      PIN_CFG(20, ALT_A)
+#define GPIO20_MC0_DAT2DIR      PIN_CFG_PULL(20, ALT_A, UP)
 #define GPIO20_UARTMOD_TXD      PIN_CFG(20, ALT_B)
 #define GPIO20_IP_TRIGOUT       PIN_CFG(20, ALT_C)
 
 #define GPIO21_GPIO             PIN_CFG(21, GPIO)
-#define GPIO21_MC0_DAT31DIR     PIN_CFG(21, ALT_A)
+#define GPIO21_MC0_DAT31DIR     PIN_CFG_PULL(21, ALT_A, UP)
 #define GPIO21_MSP0_SCK         PIN_CFG(21, ALT_B)
 #define GPIO21_MS_DAT31DIR      PIN_CFG(21, ALT_C)
 
 #define GPIO22_GPIO             PIN_CFG(22, GPIO)
-#define GPIO22_MC0_FBCLK        PIN_CFG(22, ALT_A)
+#define GPIO22_MC0_FBCLK        PIN_CFG_PULL(22, ALT_A, UP)
 #define GPIO22_UARTMOD_RXD      PIN_CFG(22, ALT_B)
 #define GPIO22_MS_FBCLK         PIN_CFG(22, ALT_C)
 
 #define GPIO23_GPIO             PIN_CFG(23, GPIO)
-#define GPIO23_MC0_CLK          PIN_CFG(23, ALT_A)
+#define GPIO23_MC0_CLK          PIN_CFG_PULL(23, ALT_A, UP)
 #define GPIO23_STMMOD_CLK       PIN_CFG(23, ALT_B)
 #define GPIO23_MS_CLK           PIN_CFG(23, ALT_C)
 
 #define GPIO24_GPIO             PIN_CFG(24, GPIO)
-#define GPIO24_MC0_CMD          PIN_CFG(24, ALT_A)
+#define GPIO24_MC0_CMD          PIN_CFG_PULL(24, ALT_A, UP)
 #define GPIO24_UARTMOD_RXD      PIN_CFG(24, ALT_B)
 #define GPIO24_MS_BS            PIN_CFG(24, ALT_C)
 
 #define GPIO25_GPIO             PIN_CFG(25, GPIO)
-#define GPIO25_MC0_DAT0         PIN_CFG(25, ALT_A)
+#define GPIO25_MC0_DAT0         PIN_CFG_PULL(25, ALT_A, UP)
 #define GPIO25_STMMOD_DAT0      PIN_CFG(25, ALT_B)
 #define GPIO25_MS_DAT0          PIN_CFG(25, ALT_C)
 
 #define GPIO26_GPIO             PIN_CFG(26, GPIO)
-#define GPIO26_MC0_DAT1         PIN_CFG(26, ALT_A)
+#define GPIO26_MC0_DAT1         PIN_CFG_PULL(26, ALT_A, UP)
 #define GPIO26_STMMOD_DAT1      PIN_CFG(26, ALT_B)
 #define GPIO26_MS_DAT1          PIN_CFG(26, ALT_C)
 
 #define GPIO27_GPIO             PIN_CFG(27, GPIO)
-#define GPIO27_MC0_DAT2         PIN_CFG(27, ALT_A)
+#define GPIO27_MC0_DAT2         PIN_CFG_PULL(27, ALT_A, UP)
 #define GPIO27_STMMOD_DAT2      PIN_CFG(27, ALT_B)
 #define GPIO27_MS_DAT2          PIN_CFG(27, ALT_C)
 
 #define GPIO28_GPIO             PIN_CFG(28, GPIO)
-#define GPIO28_MC0_DAT3         PIN_CFG(28, ALT_A)
+#define GPIO28_MC0_DAT3         PIN_CFG_PULL(28, ALT_A, UP)
 #define GPIO28_STMMOD_DAT3      PIN_CFG(28, ALT_B)
 #define GPIO28_MS_DAT3          PIN_CFG(28, ALT_C)
 
@@ -357,48 +357,48 @@
 #define GPIO97_MC5_DAT7         PIN_CFG(97, ALT_C)
 
 #define GPIO128_GPIO            PIN_CFG(128, GPIO)
-#define GPIO128_MC2_CLK         PIN_CFG(128, ALT_A)
+#define GPIO128_MC2_CLK         PIN_CFG_PULL(128, ALT_A, UP)
 #define GPIO128_SM_CKO          PIN_CFG(128, ALT_B)
 
 #define GPIO129_GPIO            PIN_CFG(129, GPIO)
-#define GPIO129_MC2_CMD         PIN_CFG(129, ALT_A)
+#define GPIO129_MC2_CMD         PIN_CFG_PULL(129, ALT_A, UP)
 #define GPIO129_SM_WAIT0n       PIN_CFG(129, ALT_B)
 
 #define GPIO130_GPIO            PIN_CFG(130, GPIO)
-#define GPIO130_MC2_FBCLK       PIN_CFG(130, ALT_A)
+#define GPIO130_MC2_FBCLK       PIN_CFG_PULL(130, ALT_A, UP)
 #define GPIO130_SM_FBCLK        PIN_CFG(130, ALT_B)
 #define GPIO130_MC2_RSTN        PIN_CFG(130, ALT_C)
 
 #define GPIO131_GPIO            PIN_CFG(131, GPIO)
-#define GPIO131_MC2_DAT0        PIN_CFG(131, ALT_A)
+#define GPIO131_MC2_DAT0        PIN_CFG_PULL(131, ALT_A, UP)
 #define GPIO131_SM_ADQ8         PIN_CFG(131, ALT_B)
 
 #define GPIO132_GPIO            PIN_CFG(132, GPIO)
-#define GPIO132_MC2_DAT1        PIN_CFG(132, ALT_A)
+#define GPIO132_MC2_DAT1        PIN_CFG_PULL(132, ALT_A, UP)
 #define GPIO132_SM_ADQ9         PIN_CFG(132, ALT_B)
 
 #define GPIO133_GPIO            PIN_CFG(133, GPIO)
-#define GPIO133_MC2_DAT2        PIN_CFG(133, ALT_A)
+#define GPIO133_MC2_DAT2        PIN_CFG_PULL(133, ALT_A, UP)
 #define GPIO133_SM_ADQ10        PIN_CFG(133, ALT_B)
 
 #define GPIO134_GPIO            PIN_CFG(134, GPIO)
-#define GPIO134_MC2_DAT3        PIN_CFG(134, ALT_A)
+#define GPIO134_MC2_DAT3        PIN_CFG_PULL(134, ALT_A, UP)
 #define GPIO134_SM_ADQ11        PIN_CFG(134, ALT_B)
 
 #define GPIO135_GPIO            PIN_CFG(135, GPIO)
-#define GPIO135_MC2_DAT4        PIN_CFG(135, ALT_A)
+#define GPIO135_MC2_DAT4        PIN_CFG_PULL(135, ALT_A, UP)
 #define GPIO135_SM_ADQ12        PIN_CFG(135, ALT_B)
 
 #define GPIO136_GPIO            PIN_CFG(136, GPIO)
-#define GPIO136_MC2_DAT5        PIN_CFG(136, ALT_A)
+#define GPIO136_MC2_DAT5        PIN_CFG_PULL(136, ALT_A, UP)
 #define GPIO136_SM_ADQ13        PIN_CFG(136, ALT_B)
 
 #define GPIO137_GPIO            PIN_CFG(137, GPIO)
-#define GPIO137_MC2_DAT6        PIN_CFG(137, ALT_A)
+#define GPIO137_MC2_DAT6        PIN_CFG_PULL(137, ALT_A, UP)
 #define GPIO137_SM_ADQ14        PIN_CFG(137, ALT_B)
 
 #define GPIO138_GPIO            PIN_CFG(138, GPIO)
-#define GPIO138_MC2_DAT7        PIN_CFG(138, ALT_A)
+#define GPIO138_MC2_DAT7        PIN_CFG_PULL(138, ALT_A, UP)
 #define GPIO138_SM_ADQ15        PIN_CFG(138, ALT_B)
 
 #define GPIO139_GPIO            PIN_CFG(139, GPIO)
@@ -459,82 +459,82 @@
 #define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
 
 #define GPIO153_GPIO            PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7           PIN_CFG(153, ALT_A)
+#define GPIO153_KP_I7           PIN_CFG_PULL(153, ALT_A, DOWN)
 #define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
 #define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
 
 #define GPIO154_GPIO            PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6           PIN_CFG(154, ALT_A)
+#define GPIO154_KP_I6           PIN_CFG_PULL(154, ALT_A, DOWN)
 #define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
 #define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
 
 #define GPIO155_GPIO            PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5           PIN_CFG(155, ALT_A)
+#define GPIO155_KP_I5           PIN_CFG_PULL(155, ALT_A, DOWN)
 #define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
 #define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
 
 #define GPIO156_GPIO            PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4           PIN_CFG(156, ALT_A)
+#define GPIO156_KP_I4           PIN_CFG_PULL(156, ALT_A, DOWN)
 #define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
 #define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
 
 #define GPIO157_GPIO            PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7           PIN_CFG(157, ALT_A)
+#define GPIO157_KP_O7           PIN_CFG_PULL(157, ALT_A, UP)
 #define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
 #define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
 
 #define GPIO158_GPIO            PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6           PIN_CFG(158, ALT_A)
+#define GPIO158_KP_O6           PIN_CFG_PULL(158, ALT_A, UP)
 #define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
 #define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
 
 #define GPIO159_GPIO            PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5           PIN_CFG(159, ALT_A)
+#define GPIO159_KP_O5           PIN_CFG_PULL(159, ALT_A, UP)
 #define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
 #define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
 
 #define GPIO160_GPIO            PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4           PIN_CFG(160, ALT_A)
+#define GPIO160_KP_O4           PIN_CFG_PULL(160, ALT_A, UP)
 #define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
 #define GPIO160_NONE            PIN_CFG(160, ALT_C)
 
 #define GPIO161_GPIO            PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3           PIN_CFG(161, ALT_A)
+#define GPIO161_KP_I3           PIN_CFG_PULL(161, ALT_A, DOWN)
 #define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
 #define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
 
 #define GPIO162_GPIO            PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2           PIN_CFG(162, ALT_A)
+#define GPIO162_KP_I2           PIN_CFG_PULL(162, ALT_A, DOWN)
 #define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
 #define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
 
 #define GPIO163_GPIO            PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1           PIN_CFG(163, ALT_A)
+#define GPIO163_KP_I1           PIN_CFG_PULL(163, ALT_A, DOWN)
 #define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
 #define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
 
 #define GPIO164_GPIO            PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0           PIN_CFG(164, ALT_A)
+#define GPIO164_KP_I0           PIN_CFG_PULL(164, ALT_A, UP)
 #define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
 #define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
 
 #define GPIO165_GPIO            PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3           PIN_CFG(165, ALT_A)
+#define GPIO165_KP_O3           PIN_CFG_PULL(165, ALT_A, UP)
 #define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
 #define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
 
 #define GPIO166_GPIO            PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2           PIN_CFG(166, ALT_A)
+#define GPIO166_KP_O2           PIN_CFG_PULL(166, ALT_A, UP)
 #define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
 #define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
 
 #define GPIO167_GPIO            PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1           PIN_CFG(167, ALT_A)
+#define GPIO167_KP_O1           PIN_CFG_PULL(167, ALT_A, UP)
 #define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
 #define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
 
 #define GPIO168_GPIO            PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0           PIN_CFG(168, ALT_A)
+#define GPIO168_KP_O0           PIN_CFG_PULL(168, ALT_A, UP)
 #define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
 #define GPIO168_NONE            PIN_CFG(168, ALT_C)
 
@@ -569,39 +569,39 @@
 #define GPIO196_MSP2_RXD        PIN_CFG(196, ALT_A)
 
 #define GPIO197_GPIO            PIN_CFG(197, GPIO)
-#define GPIO197_MC4_DAT3        PIN_CFG(197, ALT_A)
+#define GPIO197_MC4_DAT3        PIN_CFG_PULL(197, ALT_A, UP)
 
 #define GPIO198_GPIO            PIN_CFG(198, GPIO)
-#define GPIO198_MC4_DAT2        PIN_CFG(198, ALT_A)
+#define GPIO198_MC4_DAT2        PIN_CFG_PULL(198, ALT_A, UP)
 
 #define GPIO199_GPIO            PIN_CFG(199, GPIO)
-#define GPIO199_MC4_DAT1        PIN_CFG(199, ALT_A)
+#define GPIO199_MC4_DAT1        PIN_CFG_PULL(199, ALT_A, UP)
 
 #define GPIO200_GPIO            PIN_CFG(200, GPIO)
-#define GPIO200_MC4_DAT0        PIN_CFG(200, ALT_A)
+#define GPIO200_MC4_DAT0        PIN_CFG_PULL(200, ALT_A, UP)
 
 #define GPIO201_GPIO            PIN_CFG(201, GPIO)
-#define GPIO201_MC4_CMD         PIN_CFG(201, ALT_A)
+#define GPIO201_MC4_CMD         PIN_CFG_PULL(201, ALT_A, UP)
 
 #define GPIO202_GPIO            PIN_CFG(202, GPIO)
-#define GPIO202_MC4_FBCLK       PIN_CFG(202, ALT_A)
+#define GPIO202_MC4_FBCLK       PIN_CFG_PULL(202, ALT_A, UP)
 #define GPIO202_PWL             PIN_CFG(202, ALT_B)
 #define GPIO202_MC4_RSTN        PIN_CFG(202, ALT_C)
 
 #define GPIO203_GPIO            PIN_CFG(203, GPIO)
-#define GPIO203_MC4_CLK         PIN_CFG(203, ALT_A)
+#define GPIO203_MC4_CLK         PIN_CFG_PULL(203, ALT_A, UP)
 
 #define GPIO204_GPIO            PIN_CFG(204, GPIO)
-#define GPIO204_MC4_DAT7        PIN_CFG(204, ALT_A)
+#define GPIO204_MC4_DAT7        PIN_CFG_PULL(204, ALT_A, UP)
 
 #define GPIO205_GPIO            PIN_CFG(205, GPIO)
-#define GPIO205_MC4_DAT6        PIN_CFG(205, ALT_A)
+#define GPIO205_MC4_DAT6        PIN_CFG_PULL(205, ALT_A, UP)
 
 #define GPIO206_GPIO            PIN_CFG(206, GPIO)
-#define GPIO206_MC4_DAT5        PIN_CFG(206, ALT_A)
+#define GPIO206_MC4_DAT5        PIN_CFG_PULL(206, ALT_A, UP)
 
 #define GPIO207_GPIO            PIN_CFG(207, GPIO)
-#define GPIO207_MC4_DAT4        PIN_CFG(207, ALT_A)
+#define GPIO207_MC4_DAT4        PIN_CFG_PULL(207, ALT_A, UP)
 
 #define GPIO208_GPIO            PIN_CFG(208, GPIO)
 #define GPIO208_MC1_CLK         PIN_CFG(208, ALT_A)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 438ef16aec9..9e4c678de78 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -78,6 +78,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
         outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
 
+        smp_cross_call(cpumask_of(cpu));
+
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
                 if (pen_release == -1)
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
new file mode 100644
index 00000000000..293274d1342
--- /dev/null
+++ b/arch/arm/mach-ux500/prcmu.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) ST Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ *
+ * U8500 PRCMU driver.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/completion.h>
+#include <linux/jiffies.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+
+#include <mach/hardware.h>
+#include <mach/prcmu-regs.h>
+
+#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE)
+
+#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44)
+#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4)
+
+#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
+#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
+#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
+#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
+
+#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
+#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
+
+#define I2C_WRITE(slave) ((slave) << 1)
+#define I2C_READ(slave) (((slave) << 1) | BIT(0))
+#define I2C_STOP_EN BIT(3)
+
+enum ack_mb5_status {
+        I2C_WR_OK = 0x01,
+        I2C_RD_OK = 0x02,
+};
+
+#define MBOX_BIT BIT
+#define NUM_MBOX 8
+
+static struct {
+        struct mutex lock;
+        struct completion work;
+        bool failed;
+        struct {
+                u8 status;
+                u8 value;
+        } ack;
+} mb5_transfer;
+
+/**
+ * prcmu_abb_read() - Read register value(s) from the ABB.
+ * @slave:      The I2C slave address.
+ * @reg:        The (start) register address.
+ * @value:      The read out value(s).
+ * @size:       The number of registers to read.
+ *
+ * Reads register value(s) from the ABB.
+ * @size has to be 1 for the current firmware version.
+ */
+int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        int r;
+
+        if (size != 1)
+                return -EINVAL;
+
+        r = mutex_lock_interruptible(&mb5_transfer.lock);
+        if (r)
+                return r;
+
+        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+                cpu_relax();
+
+        writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
+        writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
+        writeb(reg, REQ_MB5_I2C_REG);
+
+        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
+        if (!wait_for_completion_timeout(&mb5_transfer.work,
+                        msecs_to_jiffies(500))) {
+                pr_err("prcmu: prcmu_abb_read timed out.\n");
+                r = -EIO;
+                goto unlock_and_return;
+        }
+        r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
+        if (!r)
+                *value = mb5_transfer.ack.value;
+
+unlock_and_return:
+        mutex_unlock(&mb5_transfer.lock);
+        return r;
+}
+EXPORT_SYMBOL(prcmu_abb_read);
+
+/**
+ * prcmu_abb_write() - Write register value(s) to the ABB.
+ * @slave:      The I2C slave address.
+ * @reg:        The (start) register address.
+ * @value:      The value(s) to write.
+ * @size:       The number of registers to write.
+ *
+ * Reads register value(s) from the ABB.
+ * @size has to be 1 for the current firmware version.
+ */
+int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        int r;
+
+        if (size != 1)
+                return -EINVAL;
+
+        r = mutex_lock_interruptible(&mb5_transfer.lock);
+        if (r)
+                return r;
+
+
+        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+                cpu_relax();
+
+        writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
+        writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
+        writeb(reg, REQ_MB5_I2C_REG);
+        writeb(*value, REQ_MB5_I2C_VAL);
+
+        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
+        if (!wait_for_completion_timeout(&mb5_transfer.work,
+                        msecs_to_jiffies(500))) {
+                pr_err("prcmu: prcmu_abb_write timed out.\n");
+                r = -EIO;
+                goto unlock_and_return;
+        }
+        r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
+
+unlock_and_return:
+        mutex_unlock(&mb5_transfer.lock);
+        return r;
+}
+EXPORT_SYMBOL(prcmu_abb_write);
+
+static void read_mailbox_0(void)
+{
+        writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
+}
+
+static void read_mailbox_1(void)
+{
+        writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
+}
+
+static void read_mailbox_2(void)
+{
+        writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
+}
+
+static void read_mailbox_3(void)
+{
+        writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
+}
+
+static void read_mailbox_4(void)
+{
+        writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
+}
+
+static void read_mailbox_5(void)
+{
+        mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
+        mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
+        complete(&mb5_transfer.work);
+        writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
+}
+
+static void read_mailbox_6(void)
+{
+        writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
+}
+
+static void read_mailbox_7(void)
+{
+        writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
+}
+
+static void (* const read_mailbox[NUM_MBOX])(void) = {
+        read_mailbox_0,
+        read_mailbox_1,
+        read_mailbox_2,
+        read_mailbox_3,
+        read_mailbox_4,
+        read_mailbox_5,
+        read_mailbox_6,
+        read_mailbox_7
+};
+
+static irqreturn_t prcmu_irq_handler(int irq, void *data)
+{
+        u32 bits;
+        u8 n;
+
+        bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
+        if (unlikely(!bits))
+                return IRQ_NONE;
+
+        for (n = 0; bits; n++) {
+                if (bits & MBOX_BIT(n)) {
+                        bits -= MBOX_BIT(n);
+                        read_mailbox[n]();
+                }
+        }
+        return IRQ_HANDLED;
+}
+
+static int __init prcmu_init(void)
+{
+        mutex_init(&mb5_transfer.lock);
+        init_completion(&mb5_transfer.work);
+
+        /* Clean up the mailbox interrupts after pre-kernel code. */
+        writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
+
+        return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL);
+}
+
+arch_initcall(prcmu_init);
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
new file mode 100644
index 00000000000..cb2110c3285
--- /dev/null
+++ b/arch/arm/mach-ux500/ste-dma40-db5500.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ * DB5500-SoC-specific configuration for DMA40
+ */
+
+#ifndef STE_DMA40_DB5500_H
+#define STE_DMA40_DB5500_H
+
+#define DB5500_DMA_NR_DEV 64
+
+enum dma_src_dev_type {
+        DB5500_DMA_DEV0_SPI0_RX = 0,
+        DB5500_DMA_DEV1_SPI1_RX = 1,
+        DB5500_DMA_DEV2_SPI2_RX = 2,
+        DB5500_DMA_DEV3_SPI3_RX = 3,
+        DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4,
+        DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5,
+        DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6,
+        DB5500_DMA_DEV7_IRDA_RFS = 7,
+        DB5500_DMA_DEV8_IRDA_FIFO_RX = 8,
+        DB5500_DMA_DEV9_MSP0_RX = 9,
+        DB5500_DMA_DEV10_MSP1_RX = 10,
+        DB5500_DMA_DEV11_MSP2_RX = 11,
+        DB5500_DMA_DEV12_UART0_RX = 12,
+        DB5500_DMA_DEV13_UART1_RX = 13,
+        DB5500_DMA_DEV14_UART2_RX = 14,
+        DB5500_DMA_DEV15_UART3_RX = 15,
+        DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16,
+        DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17,
+        DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18,
+        DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19,
+        DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20,
+        DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21,
+        DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22,
+        DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23,
+        DB5500_DMA_DEV24_SDMMC0_RX = 24,
+        DB5500_DMA_DEV25_SDMMC1_RX = 25,
+        DB5500_DMA_DEV26_SDMMC2_RX = 26,
+        DB5500_DMA_DEV27_SDMMC3_RX = 27,
+        DB5500_DMA_DEV28_SDMMC4_RX = 28,
+        /* 29 - 32 not used */
+        DB5500_DMA_DEV33_SDMMC0_RX = 33,
+        DB5500_DMA_DEV34_SDMMC1_RX = 34,
+        DB5500_DMA_DEV35_SDMMC2_RX = 35,
+        DB5500_DMA_DEV36_SDMMC3_RX = 36,
+        DB5500_DMA_DEV37_SDMMC4_RX = 37,
+        DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38,
+        DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39,
+        DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40,
+        DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41,
+        DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42,
+        DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
+        DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
+        DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
+        /* 46 not used */
+        DB5500_DMA_DEV47_MCDE_RX = 47,
+        DB5500_DMA_DEV48_CRYPTO1_RX = 48,
+        /* 49, 50 not used */
+        DB5500_DMA_DEV49_I2C1_RX = 51,
+        DB5500_DMA_DEV50_I2C3_RX = 52,
+        DB5500_DMA_DEV51_I2C2_RX = 53,
+        /* 54 - 60 not used */
+        DB5500_DMA_DEV61_CRYPTO0_RX = 61,
+        /* 62, 63 not used */
+};
+
+enum dma_dest_dev_type {
+        DB5500_DMA_DEV0_SPI0_TX = 0,
+        DB5500_DMA_DEV1_SPI1_TX = 1,
+        DB5500_DMA_DEV2_SPI2_TX = 2,
+        DB5500_DMA_DEV3_SPI3_TX = 3,
+        DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4,
+        DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5,
+        DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6,
+        DB5500_DMA_DEV7_IRRC_TX = 7,
+        DB5500_DMA_DEV8_IRDA_FIFO_TX = 8,
+        DB5500_DMA_DEV9_MSP0_TX = 9,
+        DB5500_DMA_DEV10_MSP1_TX = 10,
+        DB5500_DMA_DEV11_MSP2_TX = 11,
+        DB5500_DMA_DEV12_UART0_TX = 12,
+        DB5500_DMA_DEV13_UART1_TX = 13,
+        DB5500_DMA_DEV14_UART2_TX = 14,
+        DB5500_DMA_DEV15_UART3_TX = 15,
+        DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16,
+        DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17,
+        DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18,
+        DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19,
+        DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20,
+        DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21,
+        DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22,
+        DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23,
+        DB5500_DMA_DEV24_SDMMC0_TX = 24,
+        DB5500_DMA_DEV25_SDMMC1_TX = 25,
+        DB5500_DMA_DEV26_SDMMC2_TX = 26,
+        DB5500_DMA_DEV27_SDMMC3_TX = 27,
+        DB5500_DMA_DEV28_SDMMC4_TX = 28,
+        /* 29 - 31 not used */
+        DB5500_DMA_DEV32_FSMC_TX = 32,
+        DB5500_DMA_DEV33_SDMMC0_TX = 33,
+        DB5500_DMA_DEV34_SDMMC1_TX = 34,
+        DB5500_DMA_DEV35_SDMMC2_TX = 35,
+        DB5500_DMA_DEV36_SDMMC3_TX = 36,
+        DB5500_DMA_DEV37_SDMMC4_TX = 37,
+        DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38,
+        DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39,
+        DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40,
+        DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41,
+        DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42,
+        DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43,
+        DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44,
+        DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45,
+        /* 46 not used */
+        DB5500_DMA_DEV47_STM_TX = 47,
+        DB5500_DMA_DEV48_CRYPTO1_TX = 48,
+        DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49,
+        DB5500_DMA_DEV50_HASH1_TX = 50,
+        DB5500_DMA_DEV51_I2C1_TX = 51,
+        DB5500_DMA_DEV52_I2C3_TX = 52,
+        DB5500_DMA_DEV53_I2C2_TX = 53,
+        /* 54, 55 not used */
+        DB5500_DMA_MEMCPY_TX_1 = 56,
+        DB5500_DMA_MEMCPY_TX_2 = 57,
+        DB5500_DMA_MEMCPY_TX_3 = 58,
+        DB5500_DMA_MEMCPY_TX_4 = 59,
+        DB5500_DMA_MEMCPY_TX_5 = 60,
+        DB5500_DMA_DEV61_CRYPTO0_TX = 61,
+        DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62,
+        DB5500_DMA_DEV63_HASH0_TX = 63,
+};
+
+#endif
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index 9d9d3797b3b..a616419bea7 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -10,145 +10,135 @@
 #ifndef STE_DMA40_DB8500_H
 #define STE_DMA40_DB8500_H
 
-#define STEDMA40_NR_DEV 64
+#define DB8500_DMA_NR_DEV 64
 
 enum dma_src_dev_type {
-        STEDMA40_DEV_SPI0_RX = 0,
-        STEDMA40_DEV_SD_MMC0_RX = 1,
-        STEDMA40_DEV_SD_MMC1_RX = 2,
-        STEDMA40_DEV_SD_MMC2_RX = 3,
-        STEDMA40_DEV_I2C1_RX = 4,
-        STEDMA40_DEV_I2C3_RX = 5,
-        STEDMA40_DEV_I2C2_RX = 6,
-        STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */
-        STEDMA40_DEV_SSP0_RX = 8,
-        STEDMA40_DEV_SSP1_RX = 9,
-        STEDMA40_DEV_MCDE_RX = 10,
-        STEDMA40_DEV_UART2_RX = 11,
-        STEDMA40_DEV_UART1_RX = 12,
-        STEDMA40_DEV_UART0_RX = 13,
-        STEDMA40_DEV_MSP2_RX = 14,
-        STEDMA40_DEV_I2C0_RX = 15,
-        STEDMA40_DEV_USB_OTG_IEP_8 = 16,
-        STEDMA40_DEV_USB_OTG_IEP_1_9 = 17,
-        STEDMA40_DEV_USB_OTG_IEP_2_10 = 18,
-        STEDMA40_DEV_USB_OTG_IEP_3_11 = 19,
-        STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
-        STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
-        STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
-        STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
-        STEDMA40_DEV_SRC_SXA0_RX_TX = 24,
-        STEDMA40_DEV_SRC_SXA1_RX_TX = 25,
-        STEDMA40_DEV_SRC_SXA2_RX_TX = 26,
-        STEDMA40_DEV_SRC_SXA3_RX_TX = 27,
-        STEDMA40_DEV_SD_MM2_RX = 28,
-        STEDMA40_DEV_SD_MM0_RX = 29,
-        STEDMA40_DEV_MSP1_RX = 30,
-        /*
-         * This channel is either SlimBus or MSP,
-         * never both at the same time.
-         */
-        STEDMA40_SLIM0_CH0_RX = 31,
-        STEDMA40_DEV_MSP0_RX = 31,
-        STEDMA40_DEV_SD_MM1_RX = 32,
-        STEDMA40_DEV_SPI2_RX = 33,
-        STEDMA40_DEV_I2C3_RX2 = 34,
-        STEDMA40_DEV_SPI1_RX = 35,
-        STEDMA40_DEV_USB_OTG_IEP_4_12 = 36,
-        STEDMA40_DEV_USB_OTG_IEP_5_13 = 37,
-        STEDMA40_DEV_USB_OTG_IEP_6_14 = 38,
-        STEDMA40_DEV_USB_OTG_IEP_7_15 = 39,
-        STEDMA40_DEV_SPI3_RX = 40,
-        STEDMA40_DEV_SD_MM3_RX = 41,
-        STEDMA40_DEV_SD_MM4_RX = 42,
-        STEDMA40_DEV_SD_MM5_RX = 43,
-        STEDMA40_DEV_SRC_SXA4_RX_TX = 44,
-        STEDMA40_DEV_SRC_SXA5_RX_TX = 45,
-        STEDMA40_DEV_SRC_SXA6_RX_TX = 46,
-        STEDMA40_DEV_SRC_SXA7_RX_TX = 47,
-        STEDMA40_DEV_CAC1_RX = 48,
-        /* RX channels 49 and 50 are unused */
-        STEDMA40_DEV_MSHC_RX = 51,
-        STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52,
-        STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53,
-        STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54,
-        STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55,
-        /* RX channels 56 thru 60 are unused */
-        STEDMA40_DEV_CAC0_RX = 61,
-        /* RX channels 62 and 63 are unused */
+        DB8500_DMA_DEV0_SPI0_RX = 0,
+        DB8500_DMA_DEV1_SD_MMC0_RX = 1,
+        DB8500_DMA_DEV2_SD_MMC1_RX = 2,
+        DB8500_DMA_DEV3_SD_MMC2_RX = 3,
+        DB8500_DMA_DEV4_I2C1_RX = 4,
+        DB8500_DMA_DEV5_I2C3_RX = 5,
+        DB8500_DMA_DEV6_I2C2_RX = 6,
+        DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
+        DB8500_DMA_DEV8_SSP0_RX = 8,
+        DB8500_DMA_DEV9_SSP1_RX = 9,
+        DB8500_DMA_DEV10_MCDE_RX = 10,
+        DB8500_DMA_DEV11_UART2_RX = 11,
+        DB8500_DMA_DEV12_UART1_RX = 12,
+        DB8500_DMA_DEV13_UART0_RX = 13,
+        DB8500_DMA_DEV14_MSP2_RX = 14,
+        DB8500_DMA_DEV15_I2C0_RX = 15,
+        DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
+        DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
+        DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
+        DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
+        DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
+        DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
+        DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
+        DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
+        DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
+        DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
+        DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
+        DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
+        DB8500_DMA_DEV28_SD_MM2_RX = 28,
+        DB8500_DMA_DEV29_SD_MM0_RX = 29,
+        DB8500_DMA_DEV30_MSP1_RX = 30,
+        /* On DB8500v2, MSP3 RX replaces MSP1 RX */
+        DB8500_DMA_DEV30_MSP3_RX = 30,
+        DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
+        DB8500_DMA_DEV32_SD_MM1_RX = 32,
+        DB8500_DMA_DEV33_SPI2_RX = 33,
+        DB8500_DMA_DEV34_I2C3_RX2 = 34,
+        DB8500_DMA_DEV35_SPI1_RX = 35,
+        DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
+        DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
+        DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
+        DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
+        DB8500_DMA_DEV40_SPI3_RX = 40,
+        DB8500_DMA_DEV41_SD_MM3_RX = 41,
+        DB8500_DMA_DEV42_SD_MM4_RX = 42,
+        DB8500_DMA_DEV43_SD_MM5_RX = 43,
+        DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
+        DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
+        DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
+        DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
+        DB8500_DMA_DEV48_CAC1_RX = 48,
+        /* 49, 50 and 51 are not used */
+        DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
+        DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
+        DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
+        DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
+        /* 56, 57, 58, 59 and 60 are not used */
+        DB8500_DMA_DEV61_CAC0_RX = 61,
+        /* 62 and 63 are not used */
 };
 
 enum dma_dest_dev_type {
-        STEDMA40_DEV_SPI0_TX = 0,
-        STEDMA40_DEV_SD_MMC0_TX = 1,
-        STEDMA40_DEV_SD_MMC1_TX = 2,
-        STEDMA40_DEV_SD_MMC2_TX = 3,
-        STEDMA40_DEV_I2C1_TX = 4,
-        STEDMA40_DEV_I2C3_TX = 5,
-        STEDMA40_DEV_I2C2_TX = 6,
-        STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */
-        STEDMA40_DEV_SSP0_TX = 8,
-        STEDMA40_DEV_SSP1_TX = 9,
-        /* TX channel 10 is unused */
-        STEDMA40_DEV_UART2_TX = 11,
-        STEDMA40_DEV_UART1_TX = 12,
-        STEDMA40_DEV_UART0_TX= 13,
-        STEDMA40_DEV_MSP2_TX = 14,
-        STEDMA40_DEV_I2C0_TX = 15,
-        STEDMA40_DEV_USB_OTG_OEP_8 = 16,
-        STEDMA40_DEV_USB_OTG_OEP_1_9 = 17,
-        STEDMA40_DEV_USB_OTG_OEP_2_10= 18,
-        STEDMA40_DEV_USB_OTG_OEP_3_11 = 19,
-        STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
-        STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
-        STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
-        STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
-        STEDMA40_DEV_DST_SXA0_RX_TX = 24,
-        STEDMA40_DEV_DST_SXA1_RX_TX = 25,
-        STEDMA40_DEV_DST_SXA2_RX_TX = 26,
-        STEDMA40_DEV_DST_SXA3_RX_TX = 27,
-        STEDMA40_DEV_SD_MM2_TX = 28,
-        STEDMA40_DEV_SD_MM0_TX = 29,
-        STEDMA40_DEV_MSP1_TX = 30,
-        /*
-         * This channel is either SlimBus or MSP,
-         * never both at the same time.
-         */
-        STEDMA40_SLIM0_CH0_TX = 31,
-        STEDMA40_DEV_MSP0_TX = 31,
-        STEDMA40_DEV_SD_MM1_TX = 32,
-        STEDMA40_DEV_SPI2_TX = 33,
-        /* Secondary I2C3 channel */
-        STEDMA40_DEV_I2C3_TX2 = 34,
-        STEDMA40_DEV_SPI1_TX = 35,
-        STEDMA40_DEV_USB_OTG_OEP_4_12 = 36,
-        STEDMA40_DEV_USB_OTG_OEP_5_13 = 37,
-        STEDMA40_DEV_USB_OTG_OEP_6_14 = 38,
-        STEDMA40_DEV_USB_OTG_OEP_7_15 = 39,
-        STEDMA40_DEV_SPI3_TX = 40,
-        STEDMA40_DEV_SD_MM3_TX = 41,
-        STEDMA40_DEV_SD_MM4_TX = 42,
-        STEDMA40_DEV_SD_MM5_TX = 43,
-        STEDMA40_DEV_DST_SXA4_RX_TX = 44,
-        STEDMA40_DEV_DST_SXA5_RX_TX = 45,
-        STEDMA40_DEV_DST_SXA6_RX_TX = 46,
-        STEDMA40_DEV_DST_SXA7_RX_TX = 47,
-        STEDMA40_DEV_CAC1_TX = 48,
-        STEDMA40_DEV_CAC1_TX_HAC1_TX = 49,
-        STEDMA40_DEV_HAC1_TX = 50,
-        STEDMA40_MEMCPY_TX_0 = 51,
-        STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52,
-        STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53,
-        STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54,
-        STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55,
-        STEDMA40_MEMCPY_TX_1 = 56,
-        STEDMA40_MEMCPY_TX_2 = 57,
-        STEDMA40_MEMCPY_TX_3 = 58,
-        STEDMA40_MEMCPY_TX_4 = 59,
-        STEDMA40_MEMCPY_TX_5 = 60,
-        STEDMA40_DEV_CAC0_TX = 61,
-        STEDMA40_DEV_CAC0_TX_HAC0_TX = 62,
-        STEDMA40_DEV_HAC0_TX = 63,
+        DB8500_DMA_DEV0_SPI0_TX = 0,
+        DB8500_DMA_DEV1_SD_MMC0_TX = 1,
+        DB8500_DMA_DEV2_SD_MMC1_TX = 2,
+        DB8500_DMA_DEV3_SD_MMC2_TX = 3,
+        DB8500_DMA_DEV4_I2C1_TX = 4,
+        DB8500_DMA_DEV5_I2C3_TX = 5,
+        DB8500_DMA_DEV6_I2C2_TX = 6,
+        DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
+        DB8500_DMA_DEV8_SSP0_TX = 8,
+        DB8500_DMA_DEV9_SSP1_TX = 9,
+        /* 10 is not used*/
+        DB8500_DMA_DEV11_UART2_TX = 11,
+        DB8500_DMA_DEV12_UART1_TX = 12,
+        DB8500_DMA_DEV13_UART0_TX = 13,
+        DB8500_DMA_DEV14_MSP2_TX = 14,
+        DB8500_DMA_DEV15_I2C0_TX = 15,
+        DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
+        DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
+        DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
+        DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
+        DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
+        DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
+        DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
+        DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
+        DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
+        DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
+        DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
+        DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
+        DB8500_DMA_DEV28_SD_MM2_TX = 28,
+        DB8500_DMA_DEV29_SD_MM0_TX = 29,
+        DB8500_DMA_DEV30_MSP1_TX = 30,
+        DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
+        DB8500_DMA_DEV32_SD_MM1_TX = 32,
+        DB8500_DMA_DEV33_SPI2_TX = 33,
+        DB8500_DMA_DEV34_I2C3_TX2 = 34,
+        DB8500_DMA_DEV35_SPI1_TX = 35,
+        DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
+        DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
+        DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
+        DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
+        DB8500_DMA_DEV40_SPI3_TX = 40,
+        DB8500_DMA_DEV41_SD_MM3_TX = 41,
+        DB8500_DMA_DEV42_SD_MM4_TX = 42,
+        DB8500_DMA_DEV43_SD_MM5_TX = 43,
+        DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
+        DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
+        DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
+        DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
+        DB8500_DMA_DEV48_CAC1_TX  = 48,
+        DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
+        DB8500_DMA_DEV50_HAC1_TX = 50,
+        DB8500_DMA_MEMCPY_TX_0 = 51,
+        DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
+        DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
+        DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
+        DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
+        DB8500_DMA_MEMCPY_TX_1 = 56,
+        DB8500_DMA_MEMCPY_TX_2 = 57,
+        DB8500_DMA_MEMCPY_TX_3 = 58,
+        DB8500_DMA_MEMCPY_TX_4 = 59,
+        DB8500_DMA_MEMCPY_TX_5 = 60,
+        DB8500_DMA_DEV61_CAC0_TX = 61,
+        DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
+        DB8500_DMA_DEV63_HAC0_TX = 63,
 };
 
 #endif
diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S
index 6fea7199c62..eb2cf7dc5c4 100644
--- a/arch/arm/mach-versatile/include/mach/debug-macro.S
+++ b/arch/arm/mach-versatile/include/mach/debug-macro.S
@@ -11,13 +11,11 @@
  *
 */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xf1000000   @ virtual base
-                orr     \rx, \rx, #0x001F0000
-                orr     \rx, \rx, #0x00001000
+                .macro  addruart, rp, rv
+                mov     \rp,      #0x001F0000
+                orr     \rp, \rp, #0x00001000
+                orr     \rv, \rp, #0xf1000000   @ virtual base
+                orr     \rp, \rp,  #0x10000000  @ physical base
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
index 427e3612db5..ebd8a2543d3 100644
--- a/arch/arm/mach-versatile/include/mach/vmalloc.h
+++ b/arch/arm/mach-versatile/include/mach/vmalloc.h
@@ -18,4 +18,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
+#define VMALLOC_END             0xd8000000
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index bb8ec7724f7..aa9730fb13b 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -35,8 +35,6 @@
 
 MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = 0x101f1000,
-        .io_pg_offst    = ((0xf11f1000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = versatile_map_io,
         .init_irq       = versatile_init_irq,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 239cd30fc4f..bf469642a3f 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -108,8 +108,6 @@ static void __init versatile_pb_init(void)
 
 MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = 0x101f1000,
-        .io_pg_offst    = ((0xf11f1000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = versatile_map_io,
         .init_irq       = versatile_init_irq,
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index efb127022d4..c2e405a9e02 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -68,7 +68,7 @@ static void __init ct_ca9x4_init_irq(void)
 }
 
 #if 0
-static void ct_ca9x4_timer_init(void)
+static void __init ct_ca9x4_timer_init(void)
 {
         writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
         writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
@@ -222,7 +222,7 @@ static struct platform_device pmu_device = {
         .resource       = pmu_resources,
 };
 
-static void ct_ca9x4_init(void)
+static void __init ct_ca9x4_init(void)
 {
         int i;
 
@@ -245,8 +245,6 @@ static void ct_ca9x4_init(void)
 }
 
 MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
-        .phys_io        = V2M_UART0 & SECTION_MASK,
-        .io_pg_offst    = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .map_io         = ct_ca9x4_map_io,
         .init_irq       = ct_ca9x4_init_irq,
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index 5167e2aceeb..050d65e02a4 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -12,12 +12,10 @@
 
 #define DEBUG_LL_UART_OFFSET    0x00009000
 
-                .macro  addruart,rx,tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xf8000000   @ virtual base
-                orr     \rx, \rx, #DEBUG_LL_UART_OFFSET
+                .macro  addruart,rp,rv
+                mov     \rp, #DEBUG_LL_UART_OFFSET
+                orr     \rv, \rp, #0xf8000000   @ virtual base
+                orr     \rp, \rp, #0x10000000   @ physical base
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621ed08..5a6da4fd247 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()                         \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
+#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 817f0ad38a0..7eaa232180a 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -48,7 +48,7 @@ void __init v2m_map_io(struct map_desc *tile, size_t num)
 }
 
 
-static void v2m_timer_init(void)
+static void __init v2m_timer_init(void)
 {
         writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
         writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c
index ec05bda946f..30fccde94fb 100644
--- a/arch/arm/mach-w90x900/mach-nuc910evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc910evb.c
@@ -34,8 +34,6 @@ static void __init nuc910evb_init(void)
 
 MACHINE_START(W90P910EVB, "W90P910EVB")
         /* Maintainer: Wan ZongShun */
-        .phys_io        = W90X900_PA_UART,
-        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
         .boot_params    = 0,
         .map_io         = nuc910evb_map_io,
         .init_irq       = nuc900_init_irq,
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index 04d295f89eb..590c99b96dc 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -37,8 +37,6 @@ static void __init nuc950evb_init(void)
 
 MACHINE_START(W90P950EVB, "W90P950EVB")
         /* Maintainer: Wan ZongShun */
-        .phys_io        = W90X900_PA_UART,
-        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
         .boot_params    = 0,
         .map_io         = nuc950evb_map_io,
         .init_irq       = nuc900_init_irq,
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c
index e3a46f19f2b..e09c645d61b 100644
--- a/arch/arm/mach-w90x900/mach-nuc960evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc960evb.c
@@ -34,8 +34,6 @@ static void __init nuc960evb_init(void)
 
 MACHINE_START(W90N960EVB, "W90N960EVB")
         /* Maintainer: Wan ZongShun */
-        .phys_io        = W90X900_PA_UART,
-        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
         .boot_params    = 0,
         .map_io         = nuc960evb_map_io,
         .init_irq       = nuc900_init_irq,
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 86aa689ef1a..99fa688dfad 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -21,18 +21,22 @@
 #define D_CACHE_LINE_SIZE       32
 #define BTB_FLUSH_SIZE          8
 
-#ifdef CONFIG_ARM_ERRATA_411920
 /*
- * Invalidate the entire I cache (this code is a workaround for the ARM1136
- * erratum 411920 - Invalidate Instruction Cache operation can fail. This
- * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
+ *      v6_flush_icache_all()
+ *
+ *      Flush the whole I-cache.
  *
- * Registers:
- *   r0 - set to 0
- *   r1 - corrupted
+ *      ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
+ *      This erratum is present in 1136, 1156 and 1176. It does not affect the
+ *      MPCore.
+ *
+ *      Registers:
+ *      r0 - set to 0
+ *      r1 - corrupted
  */
-ENTRY(v6_icache_inval_all)
+ENTRY(v6_flush_icache_all)
         mov     r0, #0
+#ifdef CONFIG_ARM_ERRATA_411920
         mrs     r1, cpsr
         cpsid   ifa                             @ disable interrupts
         mcr     p15, 0, r0, c7, c5, 0           @ invalidate entire I-cache
@@ -43,8 +47,11 @@ ENTRY(v6_icache_inval_all)
         .rept   11                              @ ARM Ltd recommends at least
         nop                                     @ 11 NOPs
         .endr
-        mov     pc, lr
+#else
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I-cache
 #endif
+        mov     pc, lr
+ENDPROC(v6_flush_icache_all)
 
 /*
  *      v6_flush_cache_all()
@@ -60,7 +67,7 @@ ENTRY(v6_flush_kern_cache_all)
 #ifndef CONFIG_ARM_ERRATA_411920
         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
 #else
-        b       v6_icache_inval_all
+        b       v6_flush_icache_all
 #endif
 #else
         mcr     p15, 0, r0, c7, c15, 0          @ Cache clean+invalidate
@@ -138,7 +145,7 @@ ENTRY(v6_coherent_user_range)
 #ifndef CONFIG_ARM_ERRATA_411920
         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
 #else
-        b       v6_icache_inval_all
+        b       v6_flush_icache_all
 #endif
 #else
         mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
@@ -312,6 +319,7 @@ ENDPROC(v6_dma_unmap_area)
 
         .type   v6_cache_fns, #object
 ENTRY(v6_cache_fns)
+        .long   v6_flush_icache_all
         .long   v6_flush_kern_cache_all
         .long   v6_flush_user_cache_all
         .long   v6_flush_user_cache_range
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157e116..a3ebf7a4f49 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -18,6 +18,21 @@
 #include "proc-macros.S"
 
 /*
+ *      v7_flush_icache_all()
+ *
+ *      Flush the whole I-cache.
+ *
+ *      Registers:
+ *      r0 - set to 0
+ */
+ENTRY(v7_flush_icache_all)
+        mov     r0, #0
+        ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)          @ invalidate I-cache inner shareable
+        ALT_UP(mcr      p15, 0, r0, c7, c5, 0)          @ I+BTB cache invalidate
+        mov     pc, lr
+ENDPROC(v7_flush_icache_all)
+
+/*
  *      v7_flush_dcache_all()
  *
  *      Flush the whole D-cache.
@@ -91,11 +106,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
         bl      v7_flush_dcache_all
         mov     r0, #0
-#ifdef CONFIG_SMP
-        mcr     p15, 0, r0, c7, c1, 0           @ invalidate I-cache inner shareable
-#else
-        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
-#endif
+        ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)  @ invalidate I-cache inner shareable
+        ALT_UP(mcr      p15, 0, r0, c7, c5, 0)  @ I+BTB cache invalidate
  ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
  THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
         mov     pc, lr
@@ -171,11 +183,8 @@ ENTRY(v7_coherent_user_range)
         cmp     r0, r1
         blo     1b
         mov     r0, #0
-#ifdef CONFIG_SMP
-        mcr     p15, 0, r0, c7, c1, 6           @ invalidate BTB Inner Shareable
-#else
-        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
-#endif
+        ALT_SMP(mcr     p15, 0, r0, c7, c1, 6)  @ invalidate BTB Inner Shareable
+        ALT_UP(mcr      p15, 0, r0, c7, c5, 6)  @ invalidate BTB
         dsb
         isb
         mov     pc, lr
@@ -309,6 +318,7 @@ ENDPROC(v7_dma_unmap_area)
 
         .type   v7_cache_fns, #object
 ENTRY(v7_cache_fns)
+        .long   v7_flush_icache_all
         .long   v7_flush_kern_cache_all
         .long   v7_flush_user_cache_all
         .long   v7_flush_user_cache_range
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51ad507..b8061519ce7 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
-        if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                 __flush_dcache_page(page_mapping(from), from);
 
         spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa1044f7..bdba6c65c90 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
         unsigned int offset = CACHE_COLOUR(vaddr);
         unsigned long kfrom, kto;
 
-        if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                 __flush_dcache_page(page_mapping(from), from);
 
         /* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0ae209..649bbcd325b 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
-        if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                 __flush_dcache_page(page_mapping(from), from);
 
         spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4bc43e535d3..e4dd0646e85 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -523,6 +523,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
                 outer_inv_range(paddr, paddr + size);
 
         dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+        /*
+         * Mark the D-cache clean for this page to avoid extra flushing.
+         */
+        if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
+                set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906dec1ca..8440d952ba6 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -28,6 +28,7 @@
 
 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
+#if __LINUX_ARM_ARCH__ < 6
 /*
  * We take the easy way out of this problem - we make the
  * PTE uncacheable.  However, we leave the write buffer on.
@@ -141,7 +142,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -168,10 +169,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
                 return;
 
         mapping = page_mapping(page);
-#ifndef CONFIG_SMP
-        if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &page->flags))
                 __flush_dcache_page(mapping, page);
-#endif
         if (mapping) {
                 if (cache_is_vivt())
                         make_coherent(mapping, vma, addr, ptep, pfn);
@@ -179,6 +178,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
                         __flush_icache_all();
         }
 }
+#endif  /* __LINUX_ARM_ARCH__ < 6 */
 
 /*
  * Check whether the write buffer has physical address aliasing
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 23b0b03af5e..1e21e125fe3 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -581,6 +581,19 @@ static struct fsr_info ifsr_info[] = {
         { do_bad,               SIGBUS,  0,             "unknown 31"                       },
 };
 
+void __init
+hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
+                 int sig, int code, const char *name)
+{
+        if (nr < 0 || nr >= ARRAY_SIZE(ifsr_info))
+                BUG();
+
+        ifsr_info[nr].fn   = fn;
+        ifsr_info[nr].sig  = sig;
+        ifsr_info[nr].code = code;
+        ifsr_info[nr].name = name;
+}
+
 asmlinkage void __exception
 do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
 {
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6844cb9b50..391ffae7509 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
+#include <asm/smp_plat.h>
 
 #include "mm.h"
 
@@ -39,6 +40,18 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
             : "cc");
 }
 
+static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len)
+{
+        unsigned long colour = CACHE_COLOUR(vaddr);
+        unsigned long offset = vaddr & (PAGE_SIZE - 1);
+        unsigned long to;
+
+        set_pte_ext(TOP_PTE(ALIAS_FLUSH_START) + colour, pfn_pte(pfn, PAGE_KERNEL), 0);
+        to = ALIAS_FLUSH_START + (colour << PAGE_SHIFT) + offset;
+        flush_tlb_kernel_page(to);
+        flush_icache_range(to, to + len);
+}
+
 void flush_cache_mm(struct mm_struct *mm)
 {
         if (cache_is_vivt()) {
@@ -89,16 +102,16 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
         if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
                 __flush_icache_all();
 }
+
 #else
-#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+#define flush_pfn_alias(pfn,vaddr)              do { } while (0)
+#define flush_icache_alias(pfn,vaddr,len)       do { } while (0)
 #endif
 
-#ifdef CONFIG_SMP
 static void flush_ptrace_access_other(void *args)
 {
         __flush_icache_all();
 }
-#endif
 
 static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -118,15 +131,16 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                 return;
         }
 
-        /* VIPT non-aliasing cache */
+        /* VIPT non-aliasing D-cache */
         if (vma->vm_flags & VM_EXEC) {
                 unsigned long addr = (unsigned long)kaddr;
-                __cpuc_coherent_kern_range(addr, addr + len);
-#ifdef CONFIG_SMP
+                if (icache_is_vipt_aliasing())
+                        flush_icache_alias(page_to_pfn(page), uaddr, len);
+                else
+                        __cpuc_coherent_kern_range(addr, addr + len);
                 if (cache_ops_need_broadcast())
                         smp_call_function(flush_ptrace_access_other,
                                           NULL, 1);
-#endif
         }
 }
 
@@ -215,6 +229,36 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
         flush_dcache_mmap_unlock(mapping);
 }
 
+#if __LINUX_ARM_ARCH__ >= 6
+void __sync_icache_dcache(pte_t pteval)
+{
+        unsigned long pfn;
+        struct page *page;
+        struct address_space *mapping;
+
+        if (!pte_present_user(pteval))
+                return;
+        if (cache_is_vipt_nonaliasing() && !pte_exec(pteval))
+                /* only flush non-aliasing VIPT caches for exec mappings */
+                return;
+        pfn = pte_pfn(pteval);
+        if (!pfn_valid(pfn))
+                return;
+
+        page = pfn_to_page(pfn);
+        if (cache_is_vipt_aliasing())
+                mapping = page_mapping(page);
+        else
+                mapping = NULL;
+
+        if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+                __flush_dcache_page(mapping, page);
+        /* pte_exec() already checked above for non-aliasing VIPT cache */
+        if (cache_is_vipt_nonaliasing() || pte_exec(pteval))
+                __flush_icache_all();
+}
+#endif
+
 /*
  * Ensure cache coherency between kernel mapping and userspace mapping
  * of this page.
@@ -246,17 +290,16 @@ void flush_dcache_page(struct page *page)
 
         mapping = page_mapping(page);
 
-#ifndef CONFIG_SMP
-        if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
-                set_bit(PG_dcache_dirty, &page->flags);
-        else
-#endif
-        {
+        if (!cache_ops_need_broadcast() &&
+            mapping && !mapping_mapped(mapping))
+                clear_bit(PG_dcache_clean, &page->flags);
+        else {
                 __flush_dcache_page(mapping, page);
                 if (mapping && cache_is_vivt())
                         __flush_dcache_aliases(mapping, page);
                 else if (mapping)
                         __flush_icache_all();
+                set_bit(PG_dcache_clean, &page->flags);
         }
 }
 EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 7185b00650f..7fd9b5eb177 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -150,6 +150,7 @@ static void __init find_limits(struct meminfo *mi,
 static void __init arm_bootmem_init(struct meminfo *mi,
         unsigned long start_pfn, unsigned long end_pfn)
 {
+        struct memblock_region *reg;
         unsigned int boot_pages;
         phys_addr_t bitmap;
         pg_data_t *pgdat;
@@ -180,13 +181,13 @@ static void __init arm_bootmem_init(struct meminfo *mi,
         /*
          * Reserve the memblock reserved regions in bootmem.
          */
-        for (i = 0; i < memblock.reserved.cnt; i++) {
-                phys_addr_t start = memblock_start_pfn(&memblock.reserved, i);
-                if (start >= start_pfn &&
-                    memblock_end_pfn(&memblock.reserved, i) <= end_pfn)
+        for_each_memblock(reserved, reg) {
+                phys_addr_t start = memblock_region_reserved_base_pfn(reg);
+                phys_addr_t end = memblock_region_reserved_end_pfn(reg);
+                if (start >= start_pfn && end <= end_pfn)
                         reserve_bootmem_node(pgdat, __pfn_to_phys(start),
-                                memblock_size_bytes(&memblock.reserved, i),
-                                BOOTMEM_DEFAULT);
+                                             (end - start) << PAGE_SHIFT,
+                                             BOOTMEM_DEFAULT);
         }
 }
 
@@ -237,20 +238,7 @@ static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min,
 #ifndef CONFIG_SPARSEMEM
 int pfn_valid(unsigned long pfn)
 {
-        struct memblock_region *mem = &memblock.memory;
-        unsigned int left = 0, right = mem->cnt;
-
-        do {
-                unsigned int mid = (right + left) / 2;
-
-                if (pfn < memblock_start_pfn(mem, mid))
-                        right = mid;
-                else if (pfn >= memblock_end_pfn(mem, mid))
-                        left = mid + 1;
-                else
-                        return 1;
-        } while (left < right);
-        return 0;
+        return memblock_is_memory(pfn << PAGE_SHIFT);
 }
 EXPORT_SYMBOL(pfn_valid);
 
@@ -260,10 +248,11 @@ static void arm_memory_present(void)
 #else
 static void arm_memory_present(void)
 {
-        int i;
-        for (i = 0; i < memblock.memory.cnt; i++)
-                memory_present(0, memblock_start_pfn(&memblock.memory, i),
-                                  memblock_end_pfn(&memblock.memory, i));
+        struct memblock_region *reg;
+
+        for_each_memblock(memory, reg)
+                memory_present(0, memblock_region_memory_base_pfn(reg),
+                               memblock_region_memory_end_pfn(reg));
 }
 #endif
 
@@ -277,7 +266,7 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 
         /* Register the kernel text, kernel data and initrd with memblock. */
 #ifdef CONFIG_XIP_KERNEL
-        memblock_reserve(__pa(_data), _end - _data);
+        memblock_reserve(__pa(_sdata), _end - _sdata);
 #else
         memblock_reserve(__pa(_stext), _end - _stext);
 #endif
@@ -545,7 +534,7 @@ void __init mem_init(void)
 
                         MLK_ROUNDUP(__init_begin, __init_end),
                         MLK_ROUNDUP(_text, _etext),
-                        MLK_ROUNDUP(_data, _edata));
+                        MLK_ROUNDUP(_sdata, _edata));
 
 #undef MLK
 #undef MLM
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index ab506272b2d..17e7b0b57e4 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -204,8 +204,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         /*
          * Don't allow RAM to be mapped - this causes problems with ARMv6+
          */
-        if (WARN_ON(pfn_valid(pfn)))
-                return NULL;
+        if (pfn_valid(pfn)) {
+                printk(KERN_WARNING "BUG: Your driver calls ioremap() on system memory.  This leads\n"
+                       KERN_WARNING "to architecturally unpredictable behaviour on ARMv6+, and ioremap()\n"
+                       KERN_WARNING "will fail in the next kernel release.  Please fix your driver.\n");
+                WARN_ON(1);
+        }
 
         type = get_mem_type(mtype);
         if (!type)
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 4f5b39687df..b0a98305055 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -144,3 +144,25 @@ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
 {
         return !(pfn + (size >> PAGE_SHIFT) > 0x00100000);
 }
+
+#ifdef CONFIG_STRICT_DEVMEM
+
+#include <linux/ioport.h>
+
+/*
+ * devmem_is_allowed() checks to see if /dev/mem access to a certain
+ * address is valid. The argument is a physical page number.
+ * We mimic x86 here by disallowing access to system RAM as well as
+ * device-exclusive MMIO regions. This effectively disable read()/write()
+ * on /dev/mem.
+ */
+int devmem_is_allowed(unsigned long pfn)
+{
+        if (iomem_is_exclusive(pfn << PAGE_SHIFT))
+                return 0;
+        if (!page_is_ram(pfn))
+                return 1;
+        return 0;
+}
+
+#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6a3a2d0cd6d..c32f731d56d 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -248,7 +248,7 @@ static struct mem_type mem_types[] = {
         },
         [MT_MEMORY] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_USER | L_PTE_EXEC,
+                                L_PTE_WRITE | L_PTE_EXEC,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
@@ -259,7 +259,7 @@ static struct mem_type mem_types[] = {
         },
         [MT_MEMORY_NONCACHED] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
+                                L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
@@ -310,9 +310,8 @@ static void __init build_mem_type_table(void)
                         cachepolicy = CPOLICY_WRITEBACK;
                 ecc_mask = 0;
         }
-#ifdef CONFIG_SMP
-        cachepolicy = CPOLICY_WRITEALLOC;
-#endif
+        if (is_smp())
+                cachepolicy = CPOLICY_WRITEALLOC;
 
         /*
          * Strip out features not present on earlier architectures.
@@ -406,13 +405,11 @@ static void __init build_mem_type_table(void)
         cp = &cache_policies[cachepolicy];
         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
-#ifndef CONFIG_SMP
         /*
          * Only use write-through for non-SMP systems
          */
-        if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
+        if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-#endif
 
         /*
          * Enable CPU-specific coherency if supported.
@@ -436,22 +433,23 @@ static void __init build_mem_type_table(void)
                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 
-#ifdef CONFIG_SMP
-                /*
-                 * Mark memory with the "shared" attribute for SMP systems
-                 */
-                user_pgprot |= L_PTE_SHARED;
-                kern_pgprot |= L_PTE_SHARED;
-                vecs_pgprot |= L_PTE_SHARED;
-                mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
-                mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
-                mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
-                mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-                mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-                mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
-                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-                mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
-#endif
+                if (is_smp()) {
+                        /*
+                         * Mark memory with the "shared" attribute
+                         * for SMP systems
+                         */
+                        user_pgprot |= L_PTE_SHARED;
+                        kern_pgprot |= L_PTE_SHARED;
+                        vecs_pgprot |= L_PTE_SHARED;
+                        mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
+                }
         }
 
         /*
@@ -829,8 +827,7 @@ static void __init sanity_check_meminfo(void)
                          * rather difficult.
                          */
                         reason = "with VIPT aliasing cache";
-#ifdef CONFIG_SMP
-                } else if (tlb_ops_need_broadcast()) {
+                } else if (is_smp() && tlb_ops_need_broadcast()) {
                         /*
                          * kmap_high needs to occasionally flush TLB entries,
                          * however, if the TLB entries need to be broadcast
@@ -840,7 +837,6 @@ static void __init sanity_check_meminfo(void)
                          *   (must not be called with irqs off)
                          */
                         reason = "without hardware TLB ops broadcasting";
-#endif
                 }
                 if (reason) {
                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 203a4e944d9..a6f5f8475b9 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -430,7 +430,7 @@ ENTRY(cpu_arm1020_set_pte_ext)
 #endif /* CONFIG_MMU */
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm1020_setup, #function
 __arm1020_setup:
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 1a511e76590..afc06b9c313 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -412,7 +412,7 @@ ENTRY(cpu_arm1020e_set_pte_ext)
 #endif /* CONFIG_MMU */
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm1020e_setup, #function
 __arm1020e_setup:
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 1ffa4eb9c34..8915e0ba3fe 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -394,7 +394,7 @@ ENTRY(cpu_arm1022_set_pte_ext)
 #endif /* CONFIG_MMU */
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm1022_setup, #function
 __arm1022_setup:
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 5697c34b95b..ff446c5d476 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -384,7 +384,7 @@ ENTRY(cpu_arm1026_set_pte_ext)
         mov     pc, lr
 
 
-        __INIT
+        __CPUINIT
 
         .type   __arm1026_setup, #function
 __arm1026_setup:
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 64e0b327c7c..6a7be1863ed 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -238,7 +238,7 @@ ENTRY(cpu_arm7_reset)
                 mcr     p15, 0, r1, c1, c0, 0           @ turn off MMU etc
                 mov     pc, r0
 
-                __INIT
+                __CPUINIT
 
                 .type   __arm6_setup, #function
 __arm6_setup:   mov     r0, #0
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 9d96824134f..c285395f44b 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -113,7 +113,7 @@ ENTRY(cpu_arm720_reset)
                 mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
                 mov     pc, r0
 
-        __INIT
+        __CPUINIT
 
         .type   __arm710_setup, #function
 __arm710_setup:
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 6c1a9ab059a..38b27dcba72 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -55,7 +55,7 @@ ENTRY(cpu_arm740_reset)
         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
         mov     pc, r0
 
-        __INIT
+        __CPUINIT
 
         .type   __arm740_setup, #function
 __arm740_setup:
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 6a850dbba22..0c9786de20a 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -46,7 +46,7 @@ ENTRY(cpu_arm7tdmi_proc_fin)
 ENTRY(cpu_arm7tdmi_reset)
                 mov     pc, r0
 
-                __INIT
+                __CPUINIT
 
                 .type   __arm7tdmi_setup, #function
 __arm7tdmi_setup:
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 86f80aa5621..fecf570939f 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -375,7 +375,7 @@ ENTRY(cpu_arm920_set_pte_ext)
 #endif
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm920_setup, #function
 __arm920_setup:
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index f76ce9b6288..e3cbf87c948 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -379,7 +379,7 @@ ENTRY(cpu_arm922_set_pte_ext)
 #endif /* CONFIG_MMU */
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm922_setup, #function
 __arm922_setup:
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 657bd3f7c15..572424c867b 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -428,7 +428,7 @@ ENTRY(cpu_arm925_set_pte_ext)
 #endif /* CONFIG_MMU */
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm925_setup, #function
 __arm925_setup:
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 73f1f3c6891..63d168b4ebe 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -389,7 +389,7 @@ ENTRY(cpu_arm926_set_pte_ext)
 #endif
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm926_setup, #function
 __arm926_setup:
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index fffb061a45a..f6a62822418 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -264,7 +264,7 @@ ENTRY(arm940_cache_fns)
         .long   arm940_dma_unmap_area
         .long   arm940_dma_flush_range
 
-        __INIT
+        __CPUINIT
 
         .type   __arm940_setup, #function
 __arm940_setup:
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 249a6053760..ea2e7f2eb95 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -317,7 +317,7 @@ ENTRY(cpu_arm946_dcache_clean_area)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __arm946_setup, #function
 __arm946_setup:
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index db475667fac..db67e3134d7 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -46,7 +46,7 @@ ENTRY(cpu_arm9tdmi_proc_fin)
 ENTRY(cpu_arm9tdmi_reset)
                 mov     pc, r0
 
-                __INIT
+                __CPUINIT
 
                 .type   __arm9tdmi_setup, #function
 __arm9tdmi_setup:
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 7803fdf7002..7c9ad621f0e 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -134,7 +134,7 @@ ENTRY(cpu_fa526_set_pte_ext)
 #endif
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __fa526_setup, #function
 __fa526_setup:
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index b304d0104a4..578da69200c 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -494,7 +494,7 @@ ENTRY(cpu_feroceon_set_pte_ext)
 #endif
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __feroceon_setup, #function
 __feroceon_setup:
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 5f6892fcc16..4458ee6aa71 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -338,7 +338,7 @@ ENTRY(cpu_mohawk_set_pte_ext)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __mohawk_setup, #function
 __mohawk_setup:
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index a201eb04b5e..5aa8d59c2e8 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -156,7 +156,7 @@ ENTRY(cpu_sa110_set_pte_ext)
 #endif
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __sa110_setup, #function
 __sa110_setup:
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 7ddc4805bf9..2ac4e6f1071 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -169,7 +169,7 @@ ENTRY(cpu_sa1100_set_pte_ext)
 #endif
         mov     pc, lr
 
-        __INIT
+        __CPUINIT
 
         .type   __sa1100_setup, #function
 __sa1100_setup:
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac851519..59a7e1ffe7b 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT      (2 << 3)
 #define TTB_RGN_WB      (3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS       TTB_RGN_WBWA
-#define PMD_FLAGS       PMD_SECT_WB
-#else
-#define TTB_FLAGS       TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS       PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP    TTB_RGN_WBWA
+#define PMD_FLAGS_UP    PMD_SECT_WB
+#define TTB_FLAGS_SMP   TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
         mov     pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
         mov     r2, #0
         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
-        orr     r0, r0, #TTB_FLAGS
+        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
@@ -137,7 +135,7 @@ cpu_pj4_name:
 
         .align
 
-        __INIT
+        __CPUINIT
 
 /*
  *      __v6_setup
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
+        ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)  @ Enable SMP/nAMP mode
+        ALT_UP(nop)
         orr     r0, r0, #0x20
-        mcr     p15, 0, r0, c1, c0, 1
+        ALT_SMP(mcr     p15, 0, r0, c1, c0, 1)
+        ALT_UP(nop)
 #endif
 
         mov     r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
-        orr     r4, r4, #TTB_FLAGS
+        ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 #endif /* CONFIG_MMU */
         adr     r5, v6_crval
@@ -192,6 +193,8 @@ __v6_setup:
 v6_crval:
         crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 
+        __INITDATA
+
         .type   v6_processor_functions, #object
 ENTRY(v6_processor_functions)
         .word   v6_early_abort
@@ -205,6 +208,8 @@ ENTRY(v6_processor_functions)
         .word   cpu_v6_set_pte_ext
         .size   v6_processor_functions, . - v6_processor_functions
 
+        .section ".rodata"
+
         .type   cpu_arch_name, #object
 cpu_arch_name:
         .asciz  "armv6"
@@ -225,10 +230,16 @@ cpu_elf_name:
 __v6_proc_info:
         .long   0x0007b000
         .long   0x0007f000
-        .long   PMD_TYPE_SECT | \
+        ALT_SMP(.long \
+                PMD_TYPE_SECT | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ | \
-                PMD_FLAGS
+                PMD_FLAGS_SMP)
+        ALT_UP(.long \
+                PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS_UP)
         .long   PMD_TYPE_SECT | \
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
@@ -249,10 +260,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
         .long   0x560f5810
         .long   0xff0ffff0
-        .long   PMD_TYPE_SECT | \
+        ALT_SMP(.long \
+                PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS_SMP)
+        ALT_UP(.long \
+                PMD_TYPE_SECT | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ | \
-                PMD_FLAGS
+                PMD_FLAGS_UP)
         .long   PMD_TYPE_SECT | \
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7563ff0141b..53cbe222515 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT     ((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB     ((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS       TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS       PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP    TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP    PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS       TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS       PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP   TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
         mov     pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
         mov     r2, #0
         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
-        orr     r0, r0, #TTB_FLAGS
+        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 #endif
@@ -169,7 +168,7 @@ cpu_v7_name:
         .ascii  "ARMv7 Processor"
         .align
 
-        __INIT
+        __CPUINIT
 
 /*
  *      __v7_setup
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
-        mrc     p15, 0, r0, c1, c0, 1
+        ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
+        ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
         orreq   r0, r0, #(1 << 6) | (1 << 0)    @ Enable SMP/nAMP mode and
         mcreq   p15, 0, r0, c1, c0, 1           @ TLB ops broadcasting
@@ -253,6 +253,14 @@ __v7_setup:
         orreq   r10, r10, #1 << 22              @ set bit #22
         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_743622
+        teq     r6, #0x20                       @ present in r2p0
+        teqne   r6, #0x21                       @ present in r2p1
+        teqne   r6, #0x22                       @ present in r2p2
+        mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orreq   r10, r10, #1 << 6               @ set bit #6
+        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
 
 3:      mov     r10, #0
 #ifdef HARVARD_CACHE
@@ -262,7 +270,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
         mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
-        orr     r4, r4, #TTB_FLAGS
+        ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
         mov     r10, #0x1f                      @ domains 0, 1 = manager
         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
@@ -324,6 +333,8 @@ v7_crval:
 __v7_setup_stack:
         .space  4 * 11                          @ 11 registers
 
+        __INITDATA
+
         .type   v7_processor_functions, #object
 ENTRY(v7_processor_functions)
         .word   v7_early_abort
@@ -337,6 +348,8 @@ ENTRY(v7_processor_functions)
         .word   cpu_v7_set_pte_ext
         .size   v7_processor_functions, . - v7_processor_functions
 
+        .section ".rodata"
+
         .type   cpu_arch_name, #object
 cpu_arch_name:
         .asciz  "armv7"
@@ -354,10 +367,16 @@ cpu_elf_name:
 __v7_ca9mp_proc_info:
         .long   0x410fc090              @ Required ID value
         .long   0xff0ffff0              @ Mask for ID
-        .long   PMD_TYPE_SECT | \
+        ALT_SMP(.long \
+                PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS_SMP)
+        ALT_UP(.long \
+                PMD_TYPE_SECT | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ | \
-                PMD_FLAGS
+                PMD_FLAGS_UP)
         .long   PMD_TYPE_SECT | \
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
@@ -365,7 +384,7 @@ __v7_ca9mp_proc_info:
         b       __v7_ca9mp_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
         .long   cpu_v7_name
         .long   v7_processor_functions
         .long   v7wbi_tlb_fns
@@ -380,10 +399,16 @@ __v7_ca9mp_proc_info:
 __v7_proc_info:
         .long   0x000f0000              @ Required ID value
         .long   0x000f0000              @ Mask for ID
-        .long   PMD_TYPE_SECT | \
+        ALT_SMP(.long \
+                PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ | \
+                PMD_FLAGS_SMP)
+        ALT_UP(.long \
+                PMD_TYPE_SECT | \
                 PMD_SECT_AP_WRITE | \
                 PMD_SECT_AP_READ | \
-                PMD_FLAGS
+                PMD_FLAGS_UP)
         .long   PMD_TYPE_SECT | \
                 PMD_SECT_XN | \
                 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 361a51e4903..cad07e40304 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -404,7 +404,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
 
         .align
 
-        __INIT
+        __CPUINIT
 
         .type   __xsc3_setup, #function
 __xsc3_setup:
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 14075979bcb..cb245edb2c2 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -506,7 +506,7 @@ ENTRY(cpu_xscale_set_pte_ext)
 
         .align
 
-        __INIT
+        __CPUINIT
 
         .type   __xscale_setup, #function
 __xscale_setup:
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a9546..53cd5b45467 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
         orr     r0, r3, r0, lsl #PAGE_SHIFT     @ Create initial MVA
         mov     r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-        mcr     p15, 0, r0, c8, c3, 1           @ TLB invalidate U MVA (shareable) 
-#else
-        mcr     p15, 0, r0, c8, c7, 1           @ TLB invalidate U MVA
-#endif
+        ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+        ALT_UP(mcr      p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
+
         add     r0, r0, #PAGE_SZ
         cmp     r0, r1
         blo     1b
         mov     ip, #0
-#ifdef CONFIG_SMP
-        mcr     p15, 0, ip, c7, c1, 6           @ flush BTAC/BTB Inner Shareable
-#else
-        mcr     p15, 0, ip, c7, c5, 6           @ flush BTAC/BTB
-#endif
+        ALT_SMP(mcr     p15, 0, ip, c7, c1, 6)  @ flush BTAC/BTB Inner Shareable
+        ALT_UP(mcr      p15, 0, ip, c7, c5, 6)  @ flush BTAC/BTB
         dsb
         mov     pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
         mov     r0, r0, lsl #PAGE_SHIFT
         mov     r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-        mcr     p15, 0, r0, c8, c3, 1           @ TLB invalidate U MVA (shareable)
-#else
-        mcr     p15, 0, r0, c8, c7, 1           @ TLB invalidate U MVA
-#endif
+        ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+        ALT_UP(mcr      p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
         add     r0, r0, #PAGE_SZ
         cmp     r0, r1
         blo     1b
         mov     r2, #0
-#ifdef CONFIG_SMP
-        mcr     p15, 0, r2, c7, c1, 6           @ flush BTAC/BTB Inner Shareable
-#else
-        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
-#endif
+        ALT_SMP(mcr     p15, 0, r2, c7, c1, 6)  @ flush BTAC/BTB Inner Shareable
+        ALT_UP(mcr      p15, 0, r2, c7, c5, 6)  @ flush BTAC/BTB
         dsb
         isb
         mov     pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
         .long   v7wbi_flush_user_tlb_range
         .long   v7wbi_flush_kern_tlb_range
-        .long   v7wbi_tlb_flags
+        ALT_SMP(.long   v7wbi_tlb_flags_smp)
+        ALT_UP(.long    v7wbi_tlb_flags_up)
         .size   v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/nwfpe/milieu.h b/arch/arm/nwfpe/milieu.h
index a3892ab2dca..09a4f2ddeb7 100644
--- a/arch/arm/nwfpe/milieu.h
+++ b/arch/arm/nwfpe/milieu.h
@@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980.  The original version
 of this code was written as part of a project to build a fixed-point vector
 processor in collaboration with the University of California at Berkeley,
 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
-arithmetic/softfloat.html'.
+is available through the Web page
+http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt
 
 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
diff --git a/arch/arm/nwfpe/softfloat-macros b/arch/arm/nwfpe/softfloat-macros
index 5a060f95a58..cf2a6173149 100644
--- a/arch/arm/nwfpe/softfloat-macros
+++ b/arch/arm/nwfpe/softfloat-macros
@@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980.  The original version
 of this code was written as part of a project to build a fixed-point vector
 processor in collaboration with the University of California at Berkeley,
 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
-arithmetic/softfloat.html'.
+is available through the web page
+http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt
 
 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
diff --git a/arch/arm/nwfpe/softfloat-specialize b/arch/arm/nwfpe/softfloat-specialize
index d4a4c8e0663..679a0269dd2 100644
--- a/arch/arm/nwfpe/softfloat-specialize
+++ b/arch/arm/nwfpe/softfloat-specialize
@@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980.  The original version
 of this code was written as part of a project to build a fixed-point vector
 processor in collaboration with the University of California at Berkeley,
 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
-arithmetic/softfloat.html'.
+is available through the Web page
+http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt
 
 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
diff --git a/arch/arm/nwfpe/softfloat.c b/arch/arm/nwfpe/softfloat.c
index 0f9656e482b..ffa6b438786 100644
--- a/arch/arm/nwfpe/softfloat.c
+++ b/arch/arm/nwfpe/softfloat.c
@@ -11,8 +11,8 @@ National Science Foundation under grant MIP-9311980.  The original version
 of this code was written as part of a project to build a fixed-point vector
 processor in collaboration with the University of California at Berkeley,
 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
-arithmetic/softfloat.html'.
+is available through the web page
+http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt
 
 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h
index 13e479c5da5..df4d243a2b7 100644
--- a/arch/arm/nwfpe/softfloat.h
+++ b/arch/arm/nwfpe/softfloat.h
@@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980.  The original version
 of this code was written as part of a project to build a fixed-point vector
 processor in collaboration with the University of California at Berkeley,
 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
-arithmetic/softfloat.html'.
+is available through the Web page
+http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt
 
 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile
index e666eafed15..b2215c61cdf 100644
--- a/arch/arm/oprofile/Makefile
+++ b/arch/arm/oprofile/Makefile
@@ -6,4 +6,8 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
                 oprofilefs.o oprofile_stats.o \
                 timer_int.o )
 
+ifeq ($(CONFIG_HW_PERF_EVENTS),y)
+DRIVER_OBJS += $(addprefix ../../../drivers/oprofile/, oprofile_perf.o)
+endif
+
 oprofile-y                              := $(DRIVER_OBJS) common.o
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 0691176899f..8aa974491df 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -25,138 +25,10 @@
 #include <asm/ptrace.h>
 
 #ifdef CONFIG_HW_PERF_EVENTS
-/*
- * Per performance monitor configuration as set via oprofilefs.
- */
-struct op_counter_config {
-        unsigned long count;
-        unsigned long enabled;
-        unsigned long event;
-        unsigned long unit_mask;
-        unsigned long kernel;
-        unsigned long user;
-        struct perf_event_attr attr;
-};
-
-static int op_arm_enabled;
-static DEFINE_MUTEX(op_arm_mutex);
-
-static struct op_counter_config *counter_config;
-static struct perf_event **perf_events[nr_cpumask_bits];
-static int perf_num_counters;
-
-/*
- * Overflow callback for oprofile.
- */
-static void op_overflow_handler(struct perf_event *event, int unused,
-                        struct perf_sample_data *data, struct pt_regs *regs)
-{
-        int id;
-        u32 cpu = smp_processor_id();
-
-        for (id = 0; id < perf_num_counters; ++id)
-                if (perf_events[cpu][id] == event)
-                        break;
-
-        if (id != perf_num_counters)
-                oprofile_add_sample(regs, id);
-        else
-                pr_warning("oprofile: ignoring spurious overflow "
-                                "on cpu %u\n", cpu);
-}
-
-/*
- * Called by op_arm_setup to create perf attributes to mirror the oprofile
- * settings in counter_config. Attributes are created as `pinned' events and
- * so are permanently scheduled on the PMU.
- */
-static void op_perf_setup(void)
-{
-        int i;
-        u32 size = sizeof(struct perf_event_attr);
-        struct perf_event_attr *attr;
-
-        for (i = 0; i < perf_num_counters; ++i) {
-                attr = &counter_config[i].attr;
-                memset(attr, 0, size);
-                attr->type              = PERF_TYPE_RAW;
-                attr->size              = size;
-                attr->config            = counter_config[i].event;
-                attr->sample_period     = counter_config[i].count;
-                attr->pinned            = 1;
-        }
-}
-
-static int op_create_counter(int cpu, int event)
-{
-        int ret = 0;
-        struct perf_event *pevent;
-
-        if (!counter_config[event].enabled || (perf_events[cpu][event] != NULL))
-                return ret;
-
-        pevent = perf_event_create_kernel_counter(&counter_config[event].attr,
-                                                  cpu, -1,
-                                                  op_overflow_handler);
-
-        if (IS_ERR(pevent)) {
-                ret = PTR_ERR(pevent);
-        } else if (pevent->state != PERF_EVENT_STATE_ACTIVE) {
-                pr_warning("oprofile: failed to enable event %d "
-                                "on CPU %d\n", event, cpu);
-                ret = -EBUSY;
-        } else {
-                perf_events[cpu][event] = pevent;
-        }
-
-        return ret;
-}
-
-static void op_destroy_counter(int cpu, int event)
-{
-        struct perf_event *pevent = perf_events[cpu][event];
-
-        if (pevent) {
-                perf_event_release_kernel(pevent);
-                perf_events[cpu][event] = NULL;
-        }
-}
-
-/*
- * Called by op_arm_start to create active perf events based on the
- * perviously configured attributes.
- */
-static int op_perf_start(void)
-{
-        int cpu, event, ret = 0;
-
-        for_each_online_cpu(cpu) {
-                for (event = 0; event < perf_num_counters; ++event) {
-                        ret = op_create_counter(cpu, event);
-                        if (ret)
-                                goto out;
-                }
-        }
-
-out:
-        return ret;
-}
-
-/*
- * Called by op_arm_stop at the end of a profiling run.
- */
-static void op_perf_stop(void)
+char *op_name_from_perf_id(void)
 {
-        int cpu, event;
+        enum arm_perf_pmu_ids id = armpmu_get_pmu_id();
 
-        for_each_online_cpu(cpu)
-                for (event = 0; event < perf_num_counters; ++event)
-                        op_destroy_counter(cpu, event);
-}
-
-
-static char *op_name_from_perf_id(enum arm_perf_pmu_ids id)
-{
         switch (id) {
         case ARM_PERF_PMU_ID_XSCALE1:
                 return "arm/xscale1";
@@ -175,116 +47,6 @@ static char *op_name_from_perf_id(enum arm_perf_pmu_ids id)
         }
 }
 
-static int op_arm_create_files(struct super_block *sb, struct dentry *root)
-{
-        unsigned int i;
-
-        for (i = 0; i < perf_num_counters; i++) {
-                struct dentry *dir;
-                char buf[4];
-
-                snprintf(buf, sizeof buf, "%d", i);
-                dir = oprofilefs_mkdir(sb, root, buf);
-                oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
-                oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
-                oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
-                oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
-                oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
-                oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
-        }
-
-        return 0;
-}
-
-static int op_arm_setup(void)
-{
-        spin_lock(&oprofilefs_lock);
-        op_perf_setup();
-        spin_unlock(&oprofilefs_lock);
-        return 0;
-}
-
-static int op_arm_start(void)
-{
-        int ret = -EBUSY;
-
-        mutex_lock(&op_arm_mutex);
-        if (!op_arm_enabled) {
-                ret = 0;
-                op_perf_start();
-                op_arm_enabled = 1;
-        }
-        mutex_unlock(&op_arm_mutex);
-        return ret;
-}
-
-static void op_arm_stop(void)
-{
-        mutex_lock(&op_arm_mutex);
-        if (op_arm_enabled)
-                op_perf_stop();
-        op_arm_enabled = 0;
-        mutex_unlock(&op_arm_mutex);
-}
-
-#ifdef CONFIG_PM
-static int op_arm_suspend(struct platform_device *dev, pm_message_t state)
-{
-        mutex_lock(&op_arm_mutex);
-        if (op_arm_enabled)
-                op_perf_stop();
-        mutex_unlock(&op_arm_mutex);
-        return 0;
-}
-
-static int op_arm_resume(struct platform_device *dev)
-{
-        mutex_lock(&op_arm_mutex);
-        if (op_arm_enabled && op_perf_start())
-                op_arm_enabled = 0;
-        mutex_unlock(&op_arm_mutex);
-        return 0;
-}
-
-static struct platform_driver oprofile_driver = {
-        .driver         = {
-                .name           = "arm-oprofile",
-        },
-        .resume         = op_arm_resume,
-        .suspend        = op_arm_suspend,
-};
-
-static struct platform_device *oprofile_pdev;
-
-static int __init init_driverfs(void)
-{
-        int ret;
-
-        ret = platform_driver_register(&oprofile_driver);
-        if (ret)
-                goto out;
-
-        oprofile_pdev = platform_device_register_simple(
-                                oprofile_driver.driver.name, 0, NULL, 0);
-        if (IS_ERR(oprofile_pdev)) {
-                ret = PTR_ERR(oprofile_pdev);
-                platform_driver_unregister(&oprofile_driver);
-        }
-
-out:
-        return ret;
-}
-
-static void  exit_driverfs(void)
-{
-        platform_device_unregister(oprofile_pdev);
-        platform_driver_unregister(&oprofile_driver);
-}
-#else
-static int __init init_driverfs(void) { return 0; }
-#define exit_driverfs() do { } while (0)
-#endif /* CONFIG_PM */
-
 static int report_trace(struct stackframe *frame, void *d)
 {
         unsigned int *depth = d;
@@ -349,72 +111,14 @@ static void arm_backtrace(struct pt_regs * const regs, unsigned int depth)
 
 int __init oprofile_arch_init(struct oprofile_operations *ops)
 {
-        int cpu, ret = 0;
-
-        perf_num_counters = armpmu_get_max_events();
-
-        counter_config = kcalloc(perf_num_counters,
-                        sizeof(struct op_counter_config), GFP_KERNEL);
-
-        if (!counter_config) {
-                pr_info("oprofile: failed to allocate %d "
-                                "counters\n", perf_num_counters);
-                return -ENOMEM;
-        }
-
-        ret = init_driverfs();
-        if (ret) {
-                kfree(counter_config);
-                return ret;
-        }
-
-        for_each_possible_cpu(cpu) {
-                perf_events[cpu] = kcalloc(perf_num_counters,
-                                sizeof(struct perf_event *), GFP_KERNEL);
-                if (!perf_events[cpu]) {
-                        pr_info("oprofile: failed to allocate %d perf events "
-                                        "for cpu %d\n", perf_num_counters, cpu);
-                        while (--cpu >= 0)
-                                kfree(perf_events[cpu]);
-                        return -ENOMEM;
-                }
-        }
-
         ops->backtrace          = arm_backtrace;
-        ops->create_files       = op_arm_create_files;
-        ops->setup              = op_arm_setup;
-        ops->start              = op_arm_start;
-        ops->stop               = op_arm_stop;
-        ops->shutdown           = op_arm_stop;
-        ops->cpu_type           = op_name_from_perf_id(armpmu_get_pmu_id());
-
-        if (!ops->cpu_type)
-                ret = -ENODEV;
-        else
-                pr_info("oprofile: using %s\n", ops->cpu_type);
 
-        return ret;
+        return oprofile_perf_init(ops);
 }
 
-void oprofile_arch_exit(void)
+void __exit oprofile_arch_exit(void)
 {
-        int cpu, id;
-        struct perf_event *event;
-
-        if (*perf_events) {
-                exit_driverfs();
-                for_each_possible_cpu(cpu) {
-                        for (id = 0; id < perf_num_counters; ++id) {
-                                event = perf_events[cpu][id];
-                                if (event != NULL)
-                                        perf_event_release_kernel(event);
-                        }
-                        kfree(perf_events[cpu]);
-                }
-        }
-
-        if (counter_config)
-                kfree(counter_config);
+        oprofile_perf_exit();
 }
 #else
 int __init oprofile_arch_init(struct oprofile_operations *ops)
@@ -422,5 +126,5 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         pr_info("oprofile: hardware counters not available\n");
         return -ENODEV;
 }
-void oprofile_arch_exit(void) {}
+void __exit oprofile_arch_exit(void) {}
 #endif /* CONFIG_HW_PERF_EVENTS */
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 6785db4179b..64e3a64520e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -92,6 +92,18 @@ config MXC_DEBUG_BOARD
           data/address de-multiplexing and decode, signal level shift,
           interrupt control and various board functions.
 
+config HAVE_EPIT
+        bool
+
+config MXC_USE_EPIT
+        bool "Use EPIT instead of GPT"
+        depends on HAVE_EPIT
+        help
+          Use EPIT as the system timer on systems that have it. Normally you
+          don't have a reason to do so as the EPIT has the same features and
+          uses the same clocks as the GPT. Anyway, on some systems the GPT
+          may be in use for other purposes.
+
 config MXC_ULPI
         bool
 
@@ -110,4 +122,8 @@ config ARCH_MXC_AUDMUX_V1
 config ARCH_MXC_AUDMUX_V2
         bool
 
+config IRAM_ALLOC
+        bool
+        select GENERIC_ALLOCATOR
+
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 78d405ed861..06875b4dd70 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -10,9 +10,11 @@ obj-$(CONFIG_MXC_TZIC) += tzic.o
 
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
+obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
+obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index f9e7cdbd000..0be1ac7f421 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -137,6 +137,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 static const struct file_operations audmux_debugfs_fops = {
         .open = audmux_open_file,
         .read = audmux_read_file,
+        .llseek = default_llseek,
 };
 
 static void audmux_debugfs_init(void)
@@ -186,7 +187,13 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 static int mxc_audmux_v2_init(void)
 {
         int ret;
-
+#if defined(CONFIG_ARCH_MX5)
+        if (cpu_is_mx51()) {
+                audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
+                ret = 0;
+                return ret;
+        }
+#endif
 #if defined(CONFIG_ARCH_MX3)
         if (cpu_is_mx31())
                 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 9ab784b776f..404799487f1 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,3 +1,10 @@
+config IMX_HAVE_PLATFORM_ESDHC
+        bool
+
+config IMX_HAVE_PLATFORM_FEC
+        bool
+        default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
+
 config IMX_HAVE_PLATFORM_FLEXCAN
         select HAVE_CAN_FLEXCAN
         bool
@@ -5,6 +12,9 @@ config IMX_HAVE_PLATFORM_FLEXCAN
 config IMX_HAVE_PLATFORM_IMX_I2C
         bool
 
+config IMX_HAVE_PLATFORM_IMX_SSI
+        bool
+
 config IMX_HAVE_PLATFORM_IMX_UART
         bool
 
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 347da5161f7..0a3c1f08941 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,8 +1,9 @@
-ifdef CONFIG_CAN_FLEXCAN
-# the ifdef can be removed once the flexcan driver has been merged
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) +=  platform-flexcan.o
-endif
+obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-y += platform-imx-dma.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c
new file mode 100644
index 00000000000..2605bfa0dfb
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-esdhc.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include <mach/esdhc.h>
+
+#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR,  \
+                .irq = soc ## _INT_ESDHC ## hwid,                       \
+        }
+
+#define imx_esdhc_imx_data_entry(soc, id, hwid) \
+        [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
+#define imx25_esdhc_data_entry(_id, _hwid)                              \
+        imx_esdhc_imx_data_entry(MX25, _id, _hwid)
+        imx25_esdhc_data_entry(0, 1),
+        imx25_esdhc_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
+#define imx35_esdhc_data_entry(_id, _hwid)                           \
+        imx_esdhc_imx_data_entry(MX35, _id, _hwid)
+        imx35_esdhc_data_entry(0, 1),
+        imx35_esdhc_data_entry(1, 2),
+        imx35_esdhc_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
+#define imx51_esdhc_data_entry(_id, _hwid)                              \
+        imx_esdhc_imx_data_entry(MX51, _id, _hwid)
+        imx51_esdhc_data_entry(0, 1),
+        imx51_esdhc_data_entry(1, 2),
+        imx51_esdhc_data_entry(2, 3),
+        imx51_esdhc_data_entry(3, 4),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_esdhc(
+                const struct imx_esdhc_imx_data *data,
+                const struct esdhc_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_16K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
+                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
new file mode 100644
index 00000000000..11d087f4e21
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_fec_data_entry_single(soc)                                  \
+        {                                                               \
+                .iobase = soc ## _FEC_BASE_ADDR,                        \
+                .irq = soc ## _INT_FEC,                                 \
+        }
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_fec_data imx25_fec_data __initconst =
+        imx_fec_data_entry_single(MX25);
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_fec_data imx27_fec_data __initconst =
+        imx_fec_data_entry_single(MX27);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_fec_data imx35_fec_data __initconst =
+        imx_fec_data_entry_single(MX35);
+#endif
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_fec_data imx51_fec_data __initconst =
+        imx_fec_data_entry_single(MX51);
+#endif
+
+struct platform_device *__init imx_add_fec(
+                const struct imx_fec_data *data,
+                const struct fec_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("fec", 0 /* -1? */,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
new file mode 100644
index 00000000000..02d98901805
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#ifdef SDMA_IS_MERGED
+#include <mach/sdma.h>
+#else
+struct sdma_platform_data {
+        int sdma_version;
+        char *cpu_name;
+        int to_version;
+};
+#endif
+
+struct imx_imx_sdma_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+        struct sdma_platform_data pdata;
+};
+
+#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\
+        {                                                               \
+                .iobase = soc ## _SDMA ## _BASE_ADDR,                   \
+                .irq = soc ## _INT_SDMA,                                \
+                .pdata = {                                              \
+                        .sdma_version = _sdma_version,                  \
+                        .cpu_name = _cpu_name,                          \
+                        .to_version = _to_version,                      \
+                },                                                      \
+        }
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
+        imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_ARCH_MX31
+struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
+        imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
+        imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
+        imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
+                const struct imx_imx_sdma_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-sdma", -1,
+                        res, ARRAY_SIZE(res),
+                        &data->pdata, sizeof(data->pdata));
+}
+
+static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
+{
+        return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
+}
+
+static int __init imxXX_add_imx_dma(void)
+{
+        struct platform_device *ret;
+
+#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27)
+        if (cpu_is_mx21() || cpu_is_mx27())
+                ret = imx_add_imx_dma();
+        else
+#endif
+
+#if defined(CONFIG_ARCH_MX25)
+        if (cpu_is_mx25())
+                ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
+        else
+#endif
+
+#if defined(CONFIG_ARCH_MX31)
+        if (cpu_is_mx31()) {
+                imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4;
+                ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
+        } else
+#endif
+
+#if defined(CONFIG_ARCH_MX35)
+        if (cpu_is_mx35()) {
+                imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4;
+                ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
+        } else
+#endif
+
+#if defined(CONFIG_ARCH_MX51)
+        if (cpu_is_mx51())
+                ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
+        else
+#endif
+                ret = ERR_PTR(-ENODEV);
+
+        if (IS_ERR(ret))
+                return PTR_ERR(ret);
+
+        return 0;
+}
+arch_initcall(imxXX_add_imx_dma);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index d0af9f7d8ae..679588453aa 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -6,24 +6,95 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_imx_i2c(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)           \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_I2C ## _hwid,                        \
+        }
+
+#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX1
+const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
+        imx_imx_i2c_data_entry_single(MX1, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX1 */
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
+        imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
+#define imx25_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
+        imx25_imx_i2c_data_entry(0, 1),
+        imx25_imx_i2c_data_entry(1, 2),
+        imx25_imx_i2c_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
+#define imx27_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx27_imx_i2c_data_entry(0, 1),
+        imx27_imx_i2c_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
+#define imx31_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
+        imx31_imx_i2c_data_entry(0, 1),
+        imx31_imx_i2c_data_entry(1, 2),
+        imx31_imx_i2c_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
+#define imx35_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
+        imx35_imx_i2c_data_entry(0, 1),
+        imx35_imx_i2c_data_entry(1, 2),
+        imx35_imx_i2c_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
+#define imx51_imx_i2c_data_entry(_id, _hwid)                            \
+        imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
+        imx51_imx_i2c_data_entry(0, 1),
+        imx51_imx_i2c_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_imx_i2c(
+                const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
+        return imx_add_platform_device("imx-i2c", data->id,
+                        res, ARRAY_SIZE(res),
                         pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
new file mode 100644
index 00000000000..38a7a0b8f2f
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = {                                                       \
+                .id = _id,                                              \
+                .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_SSI ## _hwid,                        \
+                .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0,         \
+                .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0,         \
+                .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1,         \
+                .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1,         \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
+#define imx21_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K)
+        imx21_imx_ssi_data_entry(0, 1),
+        imx21_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
+#define imx25_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
+        imx25_imx_ssi_data_entry(0, 1),
+        imx25_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
+#define imx27_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx27_imx_ssi_data_entry(0, 1),
+        imx27_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
+#define imx31_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
+        imx31_imx_ssi_data_entry(0, 1),
+        imx31_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
+#define imx35_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
+        imx35_imx_ssi_data_entry(0, 1),
+        imx35_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
+#define imx51_imx_ssi_data_entry(_id, _hwid)                            \
+        imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
+        imx51_imx_ssi_data_entry(0, 1),
+        imx51_imx_ssi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_imx_ssi(
+                const struct imx_imx_ssi_data *data,
+                const struct imx_ssi_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+#define DMARES(_name) {                                                 \
+        .name = #_name,                                                 \
+        .start = data->dma ## _name,                                    \
+        .end = data->dma ## _name,                                      \
+        .flags = IORESOURCE_DMA,                                        \
+}
+                DMARES(tx0),
+                DMARES(rx0),
+                DMARES(tx1),
+                DMARES(rx1),
+        };
+
+        return imx_add_platform_device("imx-ssi", data->id,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index fa3dff1433e..2039640adf2 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -6,55 +6,148 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_imx_uart_3irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irqrx, resource_size_t irqtx,
-                resource_size_t irqrts,
+#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size)            \
+        [_id] = {                                                       \
+                .id = _id,                                              \
+                .iobase = soc ## _UART ## _hwid ## _BASE_ADDR,          \
+                .iosize = _size,                                        \
+                .irqrx = soc ## _INT_UART ## _hwid ## RX,               \
+                .irqtx = soc ## _INT_UART ## _hwid ## TX,               \
+                .irqrts = soc ## _INT_UART ## _hwid ## RTS,             \
+        }
+
+#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size)            \
+        [_id] = {                                                       \
+                .id = _id,                                              \
+                .iobase = soc ## _UART ## _hwid ## _BASE_ADDR,          \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_UART ## _hwid,                       \
+        }
+
+#ifdef CONFIG_SOC_IMX1
+const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = {
+#define imx1_imx_uart_data_entry(_id, _hwid)                            \
+        imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
+        imx1_imx_uart_data_entry(0, 1),
+        imx1_imx_uart_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX1 */
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
+#define imx21_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K)
+        imx21_imx_uart_data_entry(0, 1),
+        imx21_imx_uart_data_entry(1, 2),
+        imx21_imx_uart_data_entry(2, 3),
+        imx21_imx_uart_data_entry(3, 4),
+};
+#endif
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
+#define imx25_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
+        imx25_imx_uart_data_entry(0, 1),
+        imx25_imx_uart_data_entry(1, 2),
+        imx25_imx_uart_data_entry(2, 3),
+        imx25_imx_uart_data_entry(3, 4),
+        imx25_imx_uart_data_entry(4, 5),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
+#define imx27_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx27_imx_uart_data_entry(0, 1),
+        imx27_imx_uart_data_entry(1, 2),
+        imx27_imx_uart_data_entry(2, 3),
+        imx27_imx_uart_data_entry(3, 4),
+        imx27_imx_uart_data_entry(4, 5),
+        imx27_imx_uart_data_entry(5, 6),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
+#define imx31_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
+        imx31_imx_uart_data_entry(0, 1),
+        imx31_imx_uart_data_entry(1, 2),
+        imx31_imx_uart_data_entry(2, 3),
+        imx31_imx_uart_data_entry(3, 4),
+        imx31_imx_uart_data_entry(4, 5),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
+#define imx35_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
+        imx35_imx_uart_data_entry(0, 1),
+        imx35_imx_uart_data_entry(1, 2),
+        imx35_imx_uart_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
+#define imx51_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
+        imx51_imx_uart_data_entry(0, 1),
+        imx51_imx_uart_data_entry(1, 2),
+        imx51_imx_uart_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_imx_uart_3irq(
+                const struct imx_imx_uart_3irq_data *data,
                 const struct imxuart_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irqrx,
-                        .end = irqrx,
+                        .start = data->irqrx,
+                        .end = data->irqrx,
                         .flags = IORESOURCE_IRQ,
                 }, {
-                        .start = irqtx,
-                        .end = irqtx,
+                        .start = data->irqtx,
+                        .end = data->irqtx,
                         .flags = IORESOURCE_IRQ,
                 }, {
-                        .start = irqrts,
-                        .end = irqrx,
+                        .start = data->irqrts,
+                        .end = data->irqrx,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
+        return imx_add_platform_device("imx-uart", data->id, res,
+                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
 
-struct platform_device *__init imx_add_imx_uart_1irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
+struct platform_device *__init imx_add_imx_uart_1irq(
+                const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+        return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res),
                         pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 1c286418d12..3fdcc32e3d6 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -7,38 +7,77 @@
  * Free Software Foundation.
  */
 #include <asm/sizes.h>
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata,
-                resource_size_t iosize)
+#define imx_mxc_nand_data_entry_single(soc, _size)                      \
+        {                                                               \
+                .iobase = soc ## _NFC_BASE_ADDR,                        \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_NFC                                  \
+        }
+
+#define imx_mxc_nandv3_data_entry_single(soc, _size)                    \
+        {                                                               \
+                .id = -1,                                               \
+                .iobase = soc ## _NFC_BASE_ADDR,                        \
+                .iosize = _size,                                        \
+                .axibase = soc ## _NFC_AXI_BASE_ADDR,                   \
+                .irq = soc ## _INT_NFC                                  \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX21, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX25, SZ_8K);
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX27, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX31, SZ_4K);
+#endif
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
+        imx_mxc_nand_data_entry_single(MX35, SZ_8K);
+#endif
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
+        imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
+#endif
+
+struct platform_device *__init imx_add_mxc_nand(
+                const struct imx_mxc_nand_data *data,
+                const struct mxc_nand_platform_data *pdata)
 {
-        static int id = 0;
-        
+        /* AXI has to come first, that's how the mxc_nand driver expect it */
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->axibase,
+                        .end = data->axibase + SZ_16K - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
-
-        return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
+        return imx_add_platform_device("mxc_nand", data->id,
+                        res + !data->axibase,
+                        ARRAY_SIZE(res) - !data->axibase,
                         pdata, sizeof(*pdata));
 }
-
-struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata)
-{
-        return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
-}
-
-struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata)
-{
-        return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
-}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 2831a6d3eb4..e48340ec331 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -6,25 +6,96 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include <asm/sizes.h>
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_spi_imx(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
+        {                                                               \
+                .devid = _devid,                                        \
+                .id = _id,                                              \
+                .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR,       \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_ ## type ## hwid,                    \
+        }
+
+#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size)        \
+        [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
+#define imx21_cspi_data_entry(_id, _hwid)                            \
+        imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
+        imx21_cspi_data_entry(0, 1),
+        imx21_cspi_data_entry(1, 2),
+#endif
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
+#define imx25_cspi_data_entry(_id, _hwid)                               \
+        imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
+        imx25_cspi_data_entry(0, 1),
+        imx25_cspi_data_entry(1, 2),
+        imx25_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
+#define imx27_cspi_data_entry(_id, _hwid)                               \
+        imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
+        imx27_cspi_data_entry(0, 1),
+        imx27_cspi_data_entry(1, 2),
+        imx27_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
+#define imx31_cspi_data_entry(_id, _hwid)                               \
+        imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
+        imx31_cspi_data_entry(0, 1),
+        imx31_cspi_data_entry(1, 2),
+        imx31_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
+#define imx35_cspi_data_entry(_id, _hwid)                           \
+        imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
+        imx35_cspi_data_entry(0, 1),
+        imx35_cspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+#ifdef CONFIG_ARCH_MX51
+const struct imx_spi_imx_data imx51_cspi_data __initconst =
+        imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
+
+const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
+#define imx51_ecspi_data_entry(_id, _hwid)                              \
+        imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
+        imx51_ecspi_data_entry(0, 1),
+        imx51_ecspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
+struct platform_device *__init imx_add_spi_imx(
+                const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
+        return imx_add_platform_device(data->devid, data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 35a064ff02b..9915607683d 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -249,8 +249,8 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
 #ifdef CONFIG_ARCH_MX51
         if (cpu_is_mx51()) {
                 void __iomem *usb_base;
-                u32 usbotg_base;
-                u32 usbother_base;
+                void __iomem *usbotg_base;
+                void __iomem *usbother_base;
                 int ret = 0;
 
                 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
new file mode 100644
index 00000000000..ee9582f4972
--- /dev/null
+++ b/arch/arm/plat-mxc/epit.c
@@ -0,0 +1,242 @@
+/*
+ *  linux/arch/arm/plat-mxc/epit.c
+ *
+ *  Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#define EPITCR          0x00
+#define EPITSR          0x04
+#define EPITLR          0x08
+#define EPITCMPR        0x0c
+#define EPITCNR         0x10
+
+#define EPITCR_EN                       (1 << 0)
+#define EPITCR_ENMOD                    (1 << 1)
+#define EPITCR_OCIEN                    (1 << 2)
+#define EPITCR_RLD                      (1 << 3)
+#define EPITCR_PRESC(x)                 (((x) & 0xfff) << 4)
+#define EPITCR_SWR                      (1 << 16)
+#define EPITCR_IOVW                     (1 << 17)
+#define EPITCR_DBGEN                    (1 << 18)
+#define EPITCR_WAITEN                   (1 << 19)
+#define EPITCR_RES                      (1 << 20)
+#define EPITCR_STOPEN                   (1 << 21)
+#define EPITCR_OM_DISCON                (0 << 22)
+#define EPITCR_OM_TOGGLE                (1 << 22)
+#define EPITCR_OM_CLEAR                 (2 << 22)
+#define EPITCR_OM_SET                   (3 << 22)
+#define EPITCR_CLKSRC_OFF               (0 << 24)
+#define EPITCR_CLKSRC_PERIPHERAL        (1 << 24)
+#define EPITCR_CLKSRC_REF_HIGH          (1 << 24)
+#define EPITCR_CLKSRC_REF_LOW           (3 << 24)
+
+#define EPITSR_OCIF                     (1 << 0)
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+
+#include <mach/hardware.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+
+static struct clock_event_device clockevent_epit;
+static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+
+static void __iomem *timer_base;
+
+static inline void epit_irq_disable(void)
+{
+        u32 val;
+
+        val = __raw_readl(timer_base + EPITCR);
+        val &= ~EPITCR_OCIEN;
+        __raw_writel(val, timer_base + EPITCR);
+}
+
+static inline void epit_irq_enable(void)
+{
+        u32 val;
+
+        val = __raw_readl(timer_base + EPITCR);
+        val |= EPITCR_OCIEN;
+        __raw_writel(val, timer_base + EPITCR);
+}
+
+static void epit_irq_acknowledge(void)
+{
+        __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
+}
+
+static cycle_t epit_read(struct clocksource *cs)
+{
+        return 0 - __raw_readl(timer_base + EPITCNR);
+}
+
+static struct clocksource clocksource_epit = {
+        .name           = "epit",
+        .rating         = 200,
+        .read           = epit_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init epit_clocksource_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+
+        clocksource_epit.mult = clocksource_hz2mult(c,
+                                        clocksource_epit.shift);
+        clocksource_register(&clocksource_epit);
+
+        return 0;
+}
+
+/* clock event */
+
+static int epit_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long tcmp;
+
+        tcmp = __raw_readl(timer_base + EPITCNR);
+
+        __raw_writel(tcmp - evt, timer_base + EPITCMPR);
+
+        return 0;
+}
+
+static void epit_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        unsigned long flags;
+
+        /*
+         * The timer interrupt generation is disabled at least
+         * for enough time to call epit_set_next_event()
+         */
+        local_irq_save(flags);
+
+        /* Disable interrupt in GPT module */
+        epit_irq_disable();
+
+        if (mode != clockevent_mode) {
+                /* Set event time into far-far future */
+
+                /* Clear pending interrupt */
+                epit_irq_acknowledge();
+        }
+
+        /* Remember timer mode */
+        clockevent_mode = mode;
+        local_irq_restore(flags);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                printk(KERN_ERR "epit_set_mode: Periodic mode is not "
+                                "supported for i.MX EPIT\n");
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        /*
+         * Do not put overhead of interrupt enable/disable into
+         * epit_set_next_event(), the core has about 4 minutes
+         * to call epit_set_next_event() or shutdown clock after
+         * mode switching
+         */
+                local_irq_save(flags);
+                epit_irq_enable();
+                local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &clockevent_epit;
+
+        epit_irq_acknowledge();
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction epit_timer_irq = {
+        .name           = "i.MX EPIT Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = epit_timer_interrupt,
+};
+
+static struct clock_event_device clockevent_epit = {
+        .name           = "epit",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = epit_set_mode,
+        .set_next_event = epit_set_next_event,
+        .rating         = 200,
+};
+
+static int __init epit_clockevent_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+
+        clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
+                                        clockevent_epit.shift);
+        clockevent_epit.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &clockevent_epit);
+        clockevent_epit.min_delta_ns =
+                        clockevent_delta2ns(0x800, &clockevent_epit);
+
+        clockevent_epit.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&clockevent_epit);
+
+        return 0;
+}
+
+void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
+{
+        clk_enable(timer_clk);
+
+        timer_base = base;
+
+        /*
+         * Initialise to a known state (all timers off, and timing reset)
+         */
+        __raw_writel(0x0, timer_base + EPITCR);
+
+        __raw_writel(0xffffffff, timer_base + EPITLR);
+        __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
+                        timer_base + EPITCR);
+
+        /* init and register the timer to the framework */
+        epit_clocksource_init(timer_clk);
+        epit_clockevent_init(timer_clk);
+
+        /* Make irqs happen */
+        setup_irq(irq, &epit_timer_irq);
+}
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 57ec4a896a5..9d38da077ed 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -235,7 +235,7 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
         unsigned long flags;
 
         spin_lock_irqsave(&port->lock, flags);
-        l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
+        l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset);
         __raw_writel(l, reg);
         spin_unlock_irqrestore(&port->lock, flags);
 }
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
new file mode 100644
index 00000000000..94b60dd4713
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+
+#include <mach/hardware.h>
+
+/*
+ * These symbols are used by drivers/net/cs89x0.c.
+ * This is ugly as hell, but we have to provide them until
+ * someone fixed the driver.
+ */
+
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
+/* Offsets for the PBC Controller register */
+
+/* Ethernet Controller IO base address */
+#define PBC_CS8900A_IOBASE      0x020000
+
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 2941472582d..7a1e1f89ff0 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -32,6 +32,7 @@ extern void mx31_init_irq(void);
 extern void mx35_init_irq(void);
 extern void mx51_init_irq(void);
 extern void mxc91231_init_irq(void);
+extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
 extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
 extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 25606409aab..d56213fb901 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -62,11 +62,9 @@
 #define UART_PADDR      MXC91231_UART2_BASE_ADDR
 #define UART_VADDR      MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
 #endif
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =UART_PADDR        @ physical
-                ldrne   \rx, =UART_VADDR        @ virtual
+                .macro  addruart, rp, rv
+                ldr     \rp, =UART_PADDR        @ physical
+                ldr     \rv, =UART_VADDR        @ virtual
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index c5f68c58730..86d7575a564 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -14,47 +14,105 @@ struct platform_device *imx_add_platform_device(const char *name, int id,
                 const struct resource *res, unsigned int num_resources,
                 const void *data, size_t size_data);
 
-#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE)
+#include <linux/fec.h>
+struct imx_fec_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_fec(
+                const struct imx_fec_data *data,
+                const struct fec_platform_data *pdata);
+
 #include <linux/can/platform/flexcan.h>
 struct platform_device *__init imx_add_flexcan(int id,
                 resource_size_t iobase, resource_size_t iosize,
                 resource_size_t irq,
                 const struct flexcan_platform_data *pdata);
-#else
-/* the ifdef can be removed once the flexcan driver has been merged */
-struct flexcan_platform_data;
-static inline struct platform_device *__init imx_add_flexcan(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
-                const struct flexcan_platform_data *pdata)
-{
-        return NULL;
-}
-#endif
 
 #include <mach/i2c.h>
-struct platform_device *__init imx_add_imx_i2c(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+struct imx_imx_i2c_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx_i2c(
+                const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata);
 
+#include <mach/ssi.h>
+struct imx_imx_ssi_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+        resource_size_t dmatx0;
+        resource_size_t dmarx0;
+        resource_size_t dmatx1;
+        resource_size_t dmarx1;
+};
+struct platform_device *__init imx_add_imx_ssi(
+                const struct imx_imx_ssi_data *data,
+                const struct imx_ssi_platform_data *pdata);
+
 #include <mach/imx-uart.h>
-struct platform_device *__init imx_add_imx_uart_3irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irqrx, resource_size_t irqtx,
-                resource_size_t irqrts,
+struct imx_imx_uart_3irq_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irqrx;
+        resource_size_t irqtx;
+        resource_size_t irqrts;
+};
+struct platform_device *__init imx_add_imx_uart_3irq(
+                const struct imx_imx_uart_3irq_data *data,
                 const struct imxuart_platform_data *pdata);
-struct platform_device *__init imx_add_imx_uart_1irq(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
+
+struct imx_imx_uart_1irq_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx_uart_1irq(
+                const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata);
 
 #include <mach/mxc_nand.h>
-struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata);
-struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
-                int irq, const struct mxc_nand_platform_data *pdata);
+struct imx_mxc_nand_data {
+        /*
+         * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
+         * machines but don't change existing devices as the nand device usually
+         * appears in the kernel command line to pass its partitioning.
+         */
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t axibase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_mxc_nand(
+                const struct imx_mxc_nand_data *data,
+                const struct mxc_nand_platform_data *pdata);
 
 #include <mach/spi.h>
-struct platform_device *__init imx_add_spi_imx(int id,
-                resource_size_t iobase, resource_size_t iosize, int irq,
+struct imx_spi_imx_data {
+        const char *devid;
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        int irq;
+};
+struct platform_device *__init imx_add_spi_imx(
+                const struct imx_spi_imx_data *data,
                 const struct spi_imx_master *pdata);
+
+#include <mach/esdhc.h>
+struct imx_esdhc_imx_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_esdhc(
+                const struct imx_esdhc_imx_data *data,
+                const struct esdhc_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
new file mode 100644
index 00000000000..a48a9aaa56b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#ifndef __ASM_ARCH_IMX_ESDHC_H
+#define __ASM_ARCH_IMX_ESDHC_H
+
+struct esdhc_platform_data {
+        unsigned int wp_gpio;   /* write protect pin */
+};
+#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index 656acb45d43..a21d3313f99 100644
--- a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -28,19 +28,22 @@
  * its own devices, it calls baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
  * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
- * eukrea_cpuimx35_init() or eukrea_cpuimx51_init().
+ * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
+ * or eukrea_cpuimx51sd_init().
  *
  * This example here is for the development board. Refer
  * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
  * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
  * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
  * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
+ * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
  */
 
 extern void eukrea_mbimxsd25_baseboard_init(void);
 extern void eukrea_mbimx27_baseboard_init(void);
 extern void eukrea_mbimxsd35_baseboard_init(void);
 extern void eukrea_mbimx51_baseboard_init(void);
+extern void eukrea_mbimxsd51_baseboard_init(void);
 
 #endif
 
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 21bfa46785b..e46b1c2836d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -45,6 +45,18 @@ typedef enum iomux_config {
                                 PAD_CTL_PKE | PAD_CTL_HYS)
 #define MX51_GPIO_PAD_CTRL              (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
                                 PAD_CTL_SRE_FAST)
+#define MX51_ECSPI_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
+                                PAD_CTL_SRE_FAST)
+#define MX51_SDHCI_PAD_CTRL     (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
+                                PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \
+                                PAD_CTL_DVS)
+
+#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+                                        PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -106,14 +118,20 @@ typedef enum iomux_config {
 #define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__FEC_MDIO              IOMUX_PAD(0x468, 0x0d4, 3, 0x0,   0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
 #define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__FEC_RDAT1             IOMUX_PAD(0x46c, 0x0d8, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__FEC_RDAT2             IOMUX_PAD(0x47c, 0x0e8, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__FEC_RDAT3             IOMUX_PAD(0x480, 0x0ec, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
@@ -126,18 +144,32 @@ typedef enum iomux_config {
 #define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__FEC_RXCLK           IOMUX_PAD(0x504, 0x128, 1, 0x0,   0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB6__FEC_RDAT0           IOMUX_PAD(0x5DC, 0x134, 1, 0x0,   0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_RB7__FEC_TDAT0           IOMUX_PAD(0x5E0, 0x138, 1, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13C, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__FEC_TDAT1           IOMUX_PAD(0x528, 0x140, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__FEC_TDAT2           IOMUX_PAD(0x52C, 0x144, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__FEC_TDAT3           IOMUX_PAD(0x530, 0x148, 2, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14C, 1, 0x0,   0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x0,   0, MX51_PAD_CTRL_4)
 #define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53C, 0x154, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
@@ -185,15 +217,25 @@ typedef enum iomux_config {
 #define MX51_PAD_I2C1_CLK__HSI2C_CLK            IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_I2C1_DAT__HSI2C_DAT            IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD       IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD       IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK         IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS         IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60C, 0x21C, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
 #define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
@@ -236,14 +278,14 @@ typedef enum iomux_config {
 #define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
@@ -294,32 +336,50 @@ typedef enum iomux_config {
 #define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO_1_0             IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO_1_1             IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO_1_2             IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0             IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1             IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2             IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_2__I2C2_SCL             IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
                                                         0x9b8,   3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO_1_3             IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3             IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_3__I2C2_SDA             IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
                                                         0x9bc,   3, MX51_I2C_PAD_CTRL)
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO_1_4             IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO_1_5             IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO_1_6             IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO_1_7             IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO_1_8             IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_9__GPIO_1_9             IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4             IOMUX_PAD(0x804, 0x3D8, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5             IOMUX_PAD(0x808, 0x3DC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6             IOMUX_PAD(0x80C, 0x3E0, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7             IOMUX_PAD(0x810, 0x3E4, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8             IOMUX_PAD(0x814, 0x3E8, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9             IOMUX_PAD(0x818, 0x3EC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
new file mode 100644
index 00000000000..022690c3370
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iram.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/errno.h>
+
+#ifdef CONFIG_IRAM_ALLOC
+
+int __init iram_init(unsigned long base, unsigned long size);
+void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
+void iram_free(unsigned long dma_addr, unsigned int size);
+
+#else
+
+static inline int __init iram_init(unsigned long base, unsigned long size)
+{
+        return -ENOMEM;
+}
+
+static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
+{
+        return NULL;
+}
+
+static inline void iram_free(unsigned long base, unsigned long size) {}
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index ed98b9c9f38..8bc59720b6e 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -120,7 +120,7 @@
 #define MX21_INT_GPT1           26
 #define MX21_INT_WDOG           27
 #define MX21_INT_PCMCIA         28
-#define MX21_INT_NANDFC         29
+#define MX21_INT_NFC            29
 #define MX21_INT_BMI            30
 #define MX21_INT_CSI            31
 #define MX21_INT_DMACH0         32
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4a6f800990f..cf46a45b0d4 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -50,8 +50,11 @@
 #define MX25_SSI1_BASE_ADDR             0x50034000
 #define MX25_NFC_BASE_ADDR              0xbb000000
 #define MX25_DRYICE_BASE_ADDR           0x53ffc000
+#define MX25_ESDHC1_BASE_ADDR           0x53fb4000
+#define MX25_ESDHC2_BASE_ADDR           0x53fb8000
 #define MX25_LCDC_BASE_ADDR             0x53fbc000
 #define MX25_KPP_BASE_ADDR              0x43fa8000
+#define MX25_SDMA_BASE_ADDR             0x53fd4000
 #define MX25_OTG_BASE_ADDR              0x53ff4000
 #define MX25_CSI_BASE_ADDR              0x53ff8000
 
@@ -59,6 +62,8 @@
 #define MX25_INT_I2C1           3
 #define MX25_INT_I2C2           4
 #define MX25_INT_UART4          5
+#define MX25_INT_ESDHC2         8
+#define MX25_INT_ESDHC1         9
 #define MX25_INT_I2C3           10
 #define MX25_INT_SSI2           11
 #define MX25_INT_SSI1           12
@@ -69,7 +74,8 @@
 #define MX25_INT_KPP            24
 #define MX25_INT_DRYICE         25
 #define MX25_INT_UART2          32
-#define MX25_INT_NANDFC         33
+#define MX25_INT_NFC            33
+#define MX25_INT_SDMA           34
 #define MX25_INT_LCDC           39
 #define MX25_INT_UART5          40
 #define MX25_INT_CAN1           43
@@ -77,4 +83,13 @@
 #define MX25_INT_UART1          45
 #define MX25_INT_FEC            57
 
+#define MX25_DMA_REQ_SSI2_RX1   22
+#define MX25_DMA_REQ_SSI2_TX1   23
+#define MX25_DMA_REQ_SSI2_RX0   24
+#define MX25_DMA_REQ_SSI2_TX0   25
+#define MX25_DMA_REQ_SSI1_RX1   26
+#define MX25_DMA_REQ_SSI1_TX1   27
+#define MX25_DMA_REQ_SSI1_RX0   28
+#define MX25_DMA_REQ_SSI1_TX0   29
+
 #endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index a8ab2e02a8c..2237ba2e535 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_INT_GPT1           26
 #define MX27_INT_WDOG           27
 #define MX27_INT_PCMCIA         28
-#define MX27_INT_NANDFC         29
+#define MX27_INT_NFC            29
 #define MX27_INT_ATA            30
 #define MX27_INT_CSI            31
 #define MX27_INT_DMACH0         32
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index afee3ab9d62..03e2afabc9f 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_POWER_FAIL     30
 #define MX31_INT_CCM_DVFS       31
 #define MX31_INT_UART2          32
-#define MX31_INT_NANDFC         33
+#define MX31_INT_NFC            33
 #define MX31_INT_SDMA           34
 #define MX31_INT_USB1           35
 #define MX31_INT_USB2           36
@@ -197,6 +197,15 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_EXT_WDOG       62
 #define MX31_INT_EXT_TV         63
 
+#define MX31_DMA_REQ_SSI2_RX1   22
+#define MX31_DMA_REQ_SSI2_TX1   23
+#define MX31_DMA_REQ_SSI2_RX0   24
+#define MX31_DMA_REQ_SSI2_TX0   25
+#define MX31_DMA_REQ_SSI1_RX1   26
+#define MX31_DMA_REQ_SSI1_TX1   27
+#define MX31_DMA_REQ_SSI1_RX0   28
+#define MX31_DMA_REQ_SSI1_TX0   29
+
 #define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
 
 /* silicon revisions specific to i.MX31 */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index af3038c12e3..ff905cb3245 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,5 +1,6 @@
 #ifndef __MACH_MX35_H__
 #define __MACH_MX35_H__
+
 /*
  * IRAM
  */
@@ -52,6 +53,9 @@
 #define MX35_GPIO3_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xa4000)
 #define MX35_SCC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xac000)
 #define MX35_RNGA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_ESDHC1_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xb4000)
+#define MX35_ESDHC2_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xb8000)
+#define MX35_ESDHC3_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xbc000)
 #define MX35_IPU_CTRL_BASE_ADDR                 (MX35_AIPS2_BASE_ADDR + 0xc0000)
 #define MX35_AUDMUX_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xc4000)
 #define MX35_GPIO1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xcc000)
@@ -63,6 +67,8 @@
 #define MX35_CAN1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe4000)
 #define MX35_CAN2_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe8000)
 #define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_IIM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xf0000)
+
 #define MX35_OTG_BASE_ADDR              0x53ff4000
 
 #define MX35_ROMP_BASE_ADDR             0x60000000
@@ -122,9 +128,9 @@
 #define MX35_INT_I2C3           3
 #define MX35_INT_I2C2           4
 #define MX35_INT_RTIC           6
-#define MX35_INT_MMC_SDHC1      7
-#define MX35_INT_MMC_SDHC2      8
-#define MX35_INT_MMC_SDHC3      9
+#define MX35_INT_ESDHC1         7
+#define MX35_INT_ESDHC2         8
+#define MX35_INT_ESDHC3         9
 #define MX35_INT_I2C1           10
 #define MX35_INT_SSI1           11
 #define MX35_INT_SSI2           12
@@ -145,7 +151,7 @@
 #define MX35_INT_GPT            29
 #define MX35_INT_POWER_FAIL     30
 #define MX35_INT_UART2          32
-#define MX35_INT_NANDFC         33
+#define MX35_INT_NFC            33
 #define MX35_INT_SDMA           34
 #define MX35_INT_USBHS          35
 #define MX35_INT_USBOTG         37
@@ -173,22 +179,18 @@
 #define MX35_INT_EXT_WDOG       62
 #define MX35_INT_EXT_TV         63
 
+#define MX35_DMA_REQ_SSI2_RX1   22
+#define MX35_DMA_REQ_SSI2_TX1   23
+#define MX35_DMA_REQ_SSI2_RX0   24
+#define MX35_DMA_REQ_SSI2_TX0   25
+#define MX35_DMA_REQ_SSI1_RX1   26
+#define MX35_DMA_REQ_SSI1_TX1   27
+#define MX35_DMA_REQ_SSI1_RX0   28
+#define MX35_DMA_REQ_SSI1_TX0   29
+
 #define MX35_PROD_SIGNATURE             0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
-#define MX35_CHIP_REV_1_0               0x10
-#define MX35_CHIP_REV_1_1               0x11
-#define MX35_CHIP_REV_1_2               0x12
-#define MX35_CHIP_REV_1_3               0x13
-#define MX35_CHIP_REV_2_0               0x20
-#define MX35_CHIP_REV_2_1               0x21
-#define MX35_CHIP_REV_2_2               0x22
-#define MX35_CHIP_REV_2_3               0x23
-#define MX35_CHIP_REV_3_0               0x30
-#define MX35_CHIP_REV_3_1               0x31
-#define MX35_CHIP_REV_3_2               0x32
-
-#define MX35_SYSTEM_REV_MIN             MX35_CHIP_REV_1_0
+#define MX35_SYSTEM_REV_MIN             MX3x_CHIP_REV_1_0
 #define MX35_SYSTEM_REV_NUM             3
 
 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 7a356de385f..d1bd26d7b8a 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -240,7 +240,7 @@
 
 #define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
+/* silicon revisions specific to i.MX31 and i.MX35 */
 #define MX3x_CHIP_REV_1_0               0x10
 #define MX3x_CHIP_REV_1_1               0x11
 #define MX3x_CHIP_REV_1_2               0x12
@@ -267,6 +267,14 @@ static inline int mx31_revision(void)
 {
         return mx31_cpu_rev;
 }
+
+extern unsigned int mx35_cpu_rev;
+extern void mx35_read_cpu_rev(void);
+
+static inline int mx35_revision(void)
+{
+        return mx35_cpu_rev;
+}
 #endif
 
 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
@@ -389,19 +397,6 @@ static inline int mx31_revision(void)
 #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
 #define MXC_INT_EXT_TV MX3x_INT_EXT_TV
 #define PROD_SIGNATURE MX3x_PROD_SIGNATURE
-#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
-#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
-#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
-#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
-#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
-#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
-#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
-#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
-#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
-#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
-#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
-#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
-#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
 #endif
 
 #endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 5aad344d565..2af7a1056fc 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
+#ifndef __MACH_MX51_H__
+#define __MACH_MX51_H__
 
 /*
  * MX51 memory map:
@@ -7,24 +7,23 @@
  *
  * Virt         Phys            Size    What
  * ---------------------------------------------------------------------------
- * FA3E0000     1FFE0000        128K    IRAM (SCCv2 RAM)
+ * fa3e0000     1ffe0000        128K    IRAM (SCCv2 RAM)
  *              30000000        256M    GPU
  *              40000000        512M    IPU
- * FA200000     60000000        1M      DEBUG
- * FB100000     70000000        1M      SPBA 0
- * FB000000     73F00000        1M      AIPS 1
- * FB200000     83F00000        1M      AIPS 2
- *              8FFFC000        16K     TZIC (interrupt controller)
+ * fa200000     60000000        1M      DEBUG
+ * fb100000     70000000        1M      SPBA 0
+ * fb000000     73f00000        1M      AIPS 1
+ * fb200000     83f00000        1M      AIPS 2
+ *              8fffc000        16K     TZIC (interrupt controller)
  *              90000000        256M    CSD0 SDRAM/DDR
- *              A0000000        256M    CSD1 SDRAM/DDR
- *              B0000000        128M    CS0 Flash
- *              B8000000        128M    CS1 Flash
- *              C0000000        128M    CS2 Flash
- *              C8000000        64M     CS3 Flash
- *              CC000000        32M     CS4 SRAM
- *              CE000000        32M     CS5 SRAM
- *              CFFF0000        64K     NFC (NAND Flash AXI)
- *
+ *              a0000000        256M    CSD1 SDRAM/DDR
+ *              b0000000        128M    CS0 Flash
+ *              b8000000        128M    CS1 Flash
+ *              c0000000        128M    CS2 Flash
+ *              c8000000        64M     CS3 Flash
+ *              cc000000        32M     CS4 SRAM
+ *              ce000000        32M     CS5 SRAM
+ *              cfff0000        64K     NFC (NAND Flash AXI)
  */
 
 /*
@@ -36,65 +35,151 @@
 /*
  * IRAM
  */
-#define MX51_IRAM_BASE_ADDR             0x1FFE0000      /* internal ram */
-#define MX51_IRAM_BASE_ADDR_VIRT        0xFA3E0000
+#define MX51_IRAM_BASE_ADDR             0x1ffe0000      /* internal ram */
+#define MX51_IRAM_BASE_ADDR_VIRT        0xfa3e0000
 #define MX51_IRAM_PARTITIONS            16
-#define MX51_IRAM_PARTITIONS_TO1        12
 #define MX51_IRAM_SIZE          (MX51_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
 
+#define MX51_GPU_BASE_ADDR              0x20000000
+#define MX51_GPU_CTRL_BASE_ADDR         0x30000000
+#define MX51_IPU_CTRL_BASE_ADDR         0x40000000
+
+#define MX51_DEBUG_BASE_ADDR            0x60000000
+#define MX51_DEBUG_BASE_ADDR_VIRT       0xfa200000
+#define MX51_DEBUG_SIZE                 SZ_1M
+
+#define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x01000)
+#define MX51_ETM_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x02000)
+#define MX51_TPIU_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x03000)
+#define MX51_CTI0_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x04000)
+#define MX51_CTI1_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x05000)
+#define MX51_CTI2_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x06000)
+#define MX51_CTI3_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x07000)
+#define MX51_CORTEX_DBG_BASE_ADDR       (MX51_DEBUG_BASE_ADDR + 0x08000)
+
 /*
- * NFC
+ * SPBA global module enabled #0
  */
-#define MX51_NFC_AXI_BASE_ADDR          0xCFFF0000      /* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE               SZ_64K
+#define MX51_SPBA0_BASE_ADDR            0x70000000
+#define MX51_SPBA0_BASE_ADDR_VIRT       0xfb100000
+#define MX51_SPBA0_SIZE                 SZ_1M
+
+#define MX51_ESDHC1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x04000)
+#define MX51_ESDHC2_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x08000)
+#define MX51_UART3_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x0c000)
+#define MX51_ECSPI1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_SSI2_BASE_ADDR             (MX51_SPBA0_BASE_ADDR + 0x14000)
+#define MX51_ESDHC3_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x20000)
+#define MX51_ESDHC4_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x24000)
+#define MX51_SPDIF_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x28000)
+#define MX51_ATA_DMA_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x30000)
+#define MX51_SLIM_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x34000)
+#define MX51_HSI2C_DMA_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x38000)
+#define MX51_SPBA_CTRL_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x3c000)
 
 /*
- * Graphics Memory of GPU
+ * AIPS 1
  */
-#define MX51_GPU_BASE_ADDR              0x20000000
-#define MX51_GPU2D_BASE_ADDR            0xD0000000
+#define MX51_AIPS1_BASE_ADDR            0x73f00000
+#define MX51_AIPS1_BASE_ADDR_VIRT       0xfb000000
+#define MX51_AIPS1_SIZE                 SZ_1M
+
+#define MX51_OTG_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
+#define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
+#define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
+#define MX51_GPIO4_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x90000)
+#define MX51_KPP_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x94000)
+#define MX51_WDOG_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0x98000)
+#define MX51_WDOG2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x9c000)
+#define MX51_GPT1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa0000)
+#define MX51_SRTC_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa4000)
+#define MX51_IOMUXC_BASE_ADDR           (MX51_AIPS1_BASE_ADDR + 0xa8000)
+#define MX51_EPIT1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xac000)
+#define MX51_EPIT2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xb0000)
+#define MX51_PWM1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb4000)
+#define MX51_PWM2_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xb8000)
+#define MX51_UART1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xbc000)
+#define MX51_UART2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0xc0000)
+#define MX51_SRC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd0000)
+#define MX51_CCM_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd4000)
+#define MX51_GPC_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0xd8000)
 
-#define MX51_TZIC_BASE_ADDR_TO1         0x8FFFC000
-#define MX51_TZIC_BASE_ADDR             0xE0000000
+/*
+ * AIPS 2
+ */
+#define MX51_AIPS2_BASE_ADDR            0x83f00000
+#define MX51_AIPS2_BASE_ADDR_VIRT       0xfb200000
+#define MX51_AIPS2_SIZE                 SZ_1M
 
-#define MX51_DEBUG_BASE_ADDR            0x60000000
-#define MX51_DEBUG_BASE_ADDR_VIRT       0xFA200000
-#define MX51_DEBUG_SIZE                 SZ_1M
-#define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x00001000)
-#define MX51_ETM_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x00002000)
-#define MX51_TPIU_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00003000)
-#define MX51_CTI0_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00004000)
-#define MX51_CTI1_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00005000)
-#define MX51_CTI2_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00006000)
-#define MX51_CTI3_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x00007000)
-#define MX51_CORTEX_DBG_BASE_ADDR       (MX51_DEBUG_BASE_ADDR + 0x00008000)
+#define MX51_PLL1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x80000)
+#define MX51_PLL2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x84000)
+#define MX51_PLL3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x88000)
+#define MX51_AHBMAX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0x94000)
+#define MX51_IIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x98000)
+#define MX51_CSU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0x9c000)
+#define MX51_ARM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xa0000)
+#define MX51_OWIRE_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xa4000)
+#define MX51_FIRI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xa8000)
+#define MX51_ECSPI2_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_SDMA_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xb0000)
+#define MX51_SCC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xb4000)
+#define MX51_ROMCP_BASE_ADDR            (MX51_AIPS2_BASE_ADDR + 0xb8000)
+#define MX51_RTIC_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xbc000)
+#define MX51_CSPI_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_I2C2_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc4000)
+#define MX51_I2C1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xc8000)
+#define MX51_SSI1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xcc000)
+#define MX51_AUDMUX_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd0000)
+#define MX51_M4IF_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xd8000)
+#define MX51_ESDCTL_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xd9000)
+#define MX51_WEIM_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xda000)
+#define MX51_NFC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdb000)
+#define MX51_EMI_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xdbf00)
+#define MX51_MIPI_HSC_BASE_ADDR         (MX51_AIPS2_BASE_ADDR + 0xdc000)
+#define MX51_ATA_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe0000)
+#define MX51_SIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe4000)
+#define MX51_SSI3BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe8000)
+#define MX51_FEC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xec000)
+#define MX51_TVE_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf0000)
+#define MX51_VPU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf4000)
+#define MX51_SAHARA_BASE_ADDR           (MX51_AIPS2_BASE_ADDR + 0xf8000)
+
+#define MX51_CSD0_BASE_ADDR             0x90000000
+#define MX51_CSD1_BASE_ADDR             0xa0000000
+#define MX51_CS0_BASE_ADDR              0xb0000000
+#define MX51_CS1_BASE_ADDR              0xb8000000
+#define MX51_CS2_BASE_ADDR              0xc0000000
+#define MX51_CS3_BASE_ADDR              0xc8000000
+#define MX51_CS4_BASE_ADDR              0xcc000000
+#define MX51_CS5_BASE_ADDR              0xce000000
 
 /*
- * SPBA global module enabled #0
+ * NFC
  */
-#define MX51_SPBA0_BASE_ADDR            0x70000000
-#define MX51_SPBA0_BASE_ADDR_VIRT       0xFB100000
-#define MX51_SPBA0_SIZE                 SZ_1M
+#define MX51_NFC_AXI_BASE_ADDR          0xcfff0000      /* NAND flash AXI */
+#define MX51_NFC_AXI_SIZE               SZ_64K
+
+#define MX51_GPU2D_BASE_ADDR            0xd0000000
+#define MX51_TZIC_BASE_ADDR             0xe0000000
 
-#define MX51_MMC_SDHC1_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00004000)
-#define MX51_MMC_SDHC2_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00008000)
-#define MX51_UART3_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX51_CSPI1_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x00010000)
-#define MX51_SSI2_BASE_ADDR             (MX51_SPBA0_BASE_ADDR + 0x00014000)
-#define MX51_MMC_SDHC3_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00020000)
-#define MX51_MMC_SDHC4_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00024000)
-#define MX51_SPDIF_BASE_ADDR            (MX51_SPBA0_BASE_ADDR + 0x00028000)
-#define MX51_ATA_DMA_BASE_ADDR          (MX51_SPBA0_BASE_ADDR + 0x00030000)
-#define MX51_SLIM_DMA_BASE_ADDR         (MX51_SPBA0_BASE_ADDR + 0x00034000)
-#define MX51_HSI2C_DMA_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x00038000)
-#define MX51_SPBA_CTRL_BASE_ADDR        (MX51_SPBA0_BASE_ADDR + 0x0003C000)
+#define MX51_IO_ADDRESS(x) (                                            \
+        IMX_IO_ADDRESS(x, MX51_IRAM) ?:                                 \
+        IMX_IO_ADDRESS(x, MX51_DEBUG) ?:                                \
+        IMX_IO_ADDRESS(x, MX51_SPBA0) ?:                                \
+        IMX_IO_ADDRESS(x, MX51_AIPS1) ?:                                \
+        IMX_IO_ADDRESS(x, MX51_AIPS2))
+
+/* This is currently used in <mach/debug-macro.S>, but should go away */
+#define MX51_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
 
 /*
  * defines for SPBA modules
  */
 #define MX51_SPBA_SDHC1 0x04
 #define MX51_SPBA_SDHC2 0x08
-#define MX51_SPBA_UART3 0x0C
+#define MX51_SPBA_UART3 0x0c
 #define MX51_SPBA_CSPI1 0x10
 #define MX51_SPBA_SSI2  0x14
 #define MX51_SPBA_SDHC3 0x20
@@ -103,35 +188,7 @@
 #define MX51_SPBA_ATA   0x30
 #define MX51_SPBA_SLIM  0x34
 #define MX51_SPBA_HSI2C 0x38
-#define MX51_SPBA_CTRL  0x3C
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR    0x73F00000
-#define MX51_AIPS1_BASE_ADDR_VIRT       0xFB000000
-#define MX51_AIPS1_SIZE         SZ_1M
-
-#define MX51_OTG_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x00080000)
-#define MX51_GPIO1_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x00084000)
-#define MX51_GPIO2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x00088000)
-#define MX51_GPIO3_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX51_GPIO4_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x00090000)
-#define MX51_KPP_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x00094000)
-#define MX51_WDOG_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x00098000)
-#define MX51_WDOG2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX51_GPT1_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX51_SRTC_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX51_IOMUXC_BASE_ADDR   (MX51_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX51_EPIT1_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX51_EPIT2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX51_PWM1_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX51_PWM2_BASE_ADDR     (MX51_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX51_UART1_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX51_UART2_BASE_ADDR    (MX51_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX51_SRC_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX51_CCM_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX51_GPC_BASE_ADDR      (MX51_AIPS1_BASE_ADDR + 0x000D8000)
+#define MX51_SPBA_CTRL  0x3c
 
 /*
  * Defines for modules using static and dynamic DMA channels
@@ -164,282 +221,186 @@
 #define MX51_MXC_DMA_CHANNEL_ATA_TX     MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_MEMORY     MXC_DMA_DYNAMIC_CHANNEL
 
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR            0x83F00000
-#define MX51_AIPS2_BASE_ADDR_VIRT       0xFB200000
-#define MX51_AIPS2_SIZE                 SZ_1M
-
-#define MX51_PLL1_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x00080000)
-#define MX51_PLL2_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x00084000)
-#define MX51_PLL3_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x00088000)
-#define MX51_AHBMAX_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x00094000)
-#define MX51_IIM_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x00098000)
-#define MX51_CSU_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX51_ARM_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX51_OWIRE_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX51_FIRI_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX51_CSPI2_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX51_SDMA_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX51_SCC_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX51_ROMCP_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX51_RTIC_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX51_CSPI3_BASE_ADDR    (MX51_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX51_I2C2_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX51_I2C1_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX51_SSI1_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX51_AUDMUX_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX51_M4IF_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX51_ESDCTL_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX51_WEIM_BASE_ADDR     (MX51_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX51_NFC_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX51_EMI_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX51_ATA_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000E0000)
-#define MX51_SIM_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX51_SSI3BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX51_MXC_FEC_BASE_ADDR  (MX51_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX51_TVE_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX51_VPU_BASE_ADDR      (MX51_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX51_SAHARA_BASE_ADDR   (MX51_AIPS2_BASE_ADDR + 0x000F8000)
-
-/*
- * Memory regions and CS
- */
-#define MX51_GPU_CTRL_BASE_ADDR         0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR         0x40000000
-#define MX51_CSD0_BASE_ADDR             0x90000000
-#define MX51_CSD1_BASE_ADDR             0xA0000000
-#define MX51_CS0_BASE_ADDR              0xB0000000
-#define MX51_CS1_BASE_ADDR              0xB8000000
-#define MX51_CS2_BASE_ADDR              0xC0000000
-#define MX51_CS3_BASE_ADDR              0xC8000000
-#define MX51_CS4_BASE_ADDR              0xCC000000
-#define MX51_CS5_BASE_ADDR              0xCE000000
-
-/* Does given address belongs to the specified memory region? */
-#define ADDRESS_IN_REGION(addr, start, size)                    \
-        (((addr) >= (start)) && ((addr) < (start)+(size)))
-
-/* Does given address belongs to the specified named `module'? */
-#define MX51_IS_MODULE(addr, module)                           \
-        ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
-                                MX51_ ## module ## _SIZE)
-/*
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
- */
-
-#define MX51_IO_ADDRESS(x)                                      \
-        (void __iomem *)                                        \
-        (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) :    \
-        MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
-        0xDEADBEEF)
-
-/*
- * define the address mapping macros: in physical address order
- */
-#define MX51_IRAM_IO_ADDRESS(x)  \
-        (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
-
-#define MX51_DEBUG_IO_ADDRESS(x)  \
-        (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
-
-#define MX51_SPBA0_IO_ADDRESS(x)  \
-        (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
-
-#define MX51_AIPS1_IO_ADDRESS(x)  \
-        (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
-
-#define MX51_AIPS2_IO_ADDRESS(x)  \
-        (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
-
 #define MX51_IS_MEM_DEVICE_NONSHARED(x)         0
 
 /*
  * DMA request assignments
  */
-#define MX51_DMA_REQ_SSI3_TX1   47
-#define MX51_DMA_REQ_SSI3_RX1   46
-#define MX51_DMA_REQ_SPDIF      45
-#define MX51_DMA_REQ_UART3_TX   44
-#define MX51_DMA_REQ_UART3_RX   43
-#define MX51_DMA_REQ_SLIM_B_TX  42
-#define MX51_DMA_REQ_SDHC4      41
-#define MX51_DMA_REQ_SDHC3      40
-#define MX51_DMA_REQ_CSPI_TX    39
-#define MX51_DMA_REQ_CSPI_RX    38
-#define MX51_DMA_REQ_SSI3_TX2   37
-#define MX51_DMA_REQ_IPU        36
-#define MX51_DMA_REQ_SSI3_RX2   35
-#define MX51_DMA_REQ_EPIT2      34
-#define MX51_DMA_REQ_CTI2_1     33
-#define MX51_DMA_REQ_EMI_WR     32
-#define MX51_DMA_REQ_CTI2_0     31
-#define MX51_DMA_REQ_EMI_RD     30
-#define MX51_DMA_REQ_SSI1_TX1   29
-#define MX51_DMA_REQ_SSI1_RX1   28
-#define MX51_DMA_REQ_SSI1_TX2   27
-#define MX51_DMA_REQ_SSI1_RX2   26
-#define MX51_DMA_REQ_SSI2_TX1   25
-#define MX51_DMA_REQ_SSI2_RX1   24
-#define MX51_DMA_REQ_SSI2_TX2   23
-#define MX51_DMA_REQ_SSI2_RX2   22
-#define MX51_DMA_REQ_SDHC2      21
-#define MX51_DMA_REQ_SDHC1      20
-#define MX51_DMA_REQ_UART1_TX   19
-#define MX51_DMA_REQ_UART1_RX   18
-#define MX51_DMA_REQ_UART2_TX   17
-#define MX51_DMA_REQ_UART2_RX   16
-#define MX51_DMA_REQ_GPU        15
-#define MX51_DMA_REQ_EXTREQ1    14
-#define MX51_DMA_REQ_FIRI_TX    13
-#define MX51_DMA_REQ_FIRI_RX    12
-#define MX51_DMA_REQ_HS_I2C_RX  11
-#define MX51_DMA_REQ_HS_I2C_TX  10
-#define MX51_DMA_REQ_CSPI2_TX   9
-#define MX51_DMA_REQ_CSPI2_RX   8
-#define MX51_DMA_REQ_CSPI1_TX   7
-#define MX51_DMA_REQ_CSPI1_RX   6
-#define MX51_DMA_REQ_SLIM_B     5
-#define MX51_DMA_REQ_ATA_TX_END 4
-#define MX51_DMA_REQ_ATA_TX     3
-#define MX51_DMA_REQ_ATA_RX     2
-#define MX51_DMA_REQ_GPC        1
-#define MX51_DMA_REQ_VPU        0
+#define MX51_DMA_REQ_VPU                0
+#define MX51_DMA_REQ_GPC                1
+#define MX51_DMA_REQ_ATA_RX             2
+#define MX51_DMA_REQ_ATA_TX             3
+#define MX51_DMA_REQ_ATA_TX_END         4
+#define MX51_DMA_REQ_SLIM_B             5
+#define MX51_DMA_REQ_CSPI1_RX           6
+#define MX51_DMA_REQ_CSPI1_TX           7
+#define MX51_DMA_REQ_CSPI2_RX           8
+#define MX51_DMA_REQ_CSPI2_TX           9
+#define MX51_DMA_REQ_HS_I2C_TX          10
+#define MX51_DMA_REQ_HS_I2C_RX          11
+#define MX51_DMA_REQ_FIRI_RX            12
+#define MX51_DMA_REQ_FIRI_TX            13
+#define MX51_DMA_REQ_EXTREQ1            14
+#define MX51_DMA_REQ_GPU                15
+#define MX51_DMA_REQ_UART2_RX           16
+#define MX51_DMA_REQ_UART2_TX           17
+#define MX51_DMA_REQ_UART1_RX           18
+#define MX51_DMA_REQ_UART1_TX           19
+#define MX51_DMA_REQ_SDHC1              20
+#define MX51_DMA_REQ_SDHC2              21
+#define MX51_DMA_REQ_SSI2_RX1           22
+#define MX51_DMA_REQ_SSI2_TX1           23
+#define MX51_DMA_REQ_SSI2_RX0           24
+#define MX51_DMA_REQ_SSI2_TX0           25
+#define MX51_DMA_REQ_SSI1_RX1           26
+#define MX51_DMA_REQ_SSI1_TX1           27
+#define MX51_DMA_REQ_SSI1_RX0           28
+#define MX51_DMA_REQ_SSI1_TX0           29
+#define MX51_DMA_REQ_EMI_RD             30
+#define MX51_DMA_REQ_CTI2_0             31
+#define MX51_DMA_REQ_EMI_WR             32
+#define MX51_DMA_REQ_CTI2_1             33
+#define MX51_DMA_REQ_EPIT2              34
+#define MX51_DMA_REQ_SSI3_RX2           35
+#define MX51_DMA_REQ_IPU                36
+#define MX51_DMA_REQ_SSI3_TX2           37
+#define MX51_DMA_REQ_CSPI_RX            38
+#define MX51_DMA_REQ_CSPI_TX            39
+#define MX51_DMA_REQ_SDHC3              40
+#define MX51_DMA_REQ_SDHC4              41
+#define MX51_DMA_REQ_SLIM_B_TX          42
+#define MX51_DMA_REQ_UART3_RX           43
+#define MX51_DMA_REQ_UART3_TX           44
+#define MX51_DMA_REQ_SPDIF              45
+#define MX51_DMA_REQ_SSI3_RX1           46
+#define MX51_DMA_REQ_SSI3_TX1           47
 
 /*
  * Interrupt numbers
  */
-#define MX51_MXC_INT_BASE       0
-#define MX51_MXC_INT_RESV0      0
-#define MX51_MXC_INT_MMC_SDHC1  1
-#define MX51_MXC_INT_MMC_SDHC2  2
-#define MX51_MXC_INT_MMC_SDHC3  3
-#define MX51_MXC_INT_MMC_SDHC4  4
-#define MX51_MXC_INT_RESV5      5
-#define MX51_MXC_INT_SDMA       6
-#define MX51_MXC_INT_IOMUX      7
-#define MX51_MXC_INT_NFC        8
-#define MX51_MXC_INT_VPU        9
-#define MX51_MXC_INT_IPU_ERR    10
-#define MX51_MXC_INT_IPU_SYN    11
-#define MX51_MXC_INT_GPU        12
-#define MX51_MXC_INT_RESV13     13
-#define MX51_MXC_INT_USB_H1     14
-#define MX51_MXC_INT_EMI        15
-#define MX51_MXC_INT_USB_H2     16
-#define MX51_MXC_INT_USB_H3     17
-#define MX51_MXC_INT_USB_OTG    18
-#define MX51_MXC_INT_SAHARA_H0  19
-#define MX51_MXC_INT_SAHARA_H1  20
-#define MX51_MXC_INT_SCC_SMN    21
-#define MX51_MXC_INT_SCC_STZ    22
-#define MX51_MXC_INT_SCC_SCM    23
-#define MX51_MXC_INT_SRTC_NTZ   24
-#define MX51_MXC_INT_SRTC_TZ    25
-#define MX51_MXC_INT_RTIC       26
-#define MX51_MXC_INT_CSU        27
-#define MX51_MXC_INT_SLIM_B     28
-#define MX51_MXC_INT_SSI1       29
-#define MX51_MXC_INT_SSI2       30
-#define MX51_MXC_INT_UART1      31
-#define MX51_MXC_INT_UART2      32
-#define MX51_MXC_INT_UART3      33
-#define MX51_MXC_INT_RESV34     34
-#define MX51_MXC_INT_RESV35     35
-#define MX51_MXC_INT_CSPI1      36
-#define MX51_MXC_INT_CSPI2      37
-#define MX51_MXC_INT_CSPI       38
-#define MX51_MXC_INT_GPT        39
-#define MX51_MXC_INT_EPIT1      40
-#define MX51_MXC_INT_EPIT2      41
-#define MX51_MXC_INT_GPIO1_INT7 42
-#define MX51_MXC_INT_GPIO1_INT6 43
-#define MX51_MXC_INT_GPIO1_INT5 44
-#define MX51_MXC_INT_GPIO1_INT4 45
-#define MX51_MXC_INT_GPIO1_INT3 46
-#define MX51_MXC_INT_GPIO1_INT2 47
-#define MX51_MXC_INT_GPIO1_INT1 48
-#define MX51_MXC_INT_GPIO1_INT0 49
-#define MX51_MXC_INT_GPIO1_LOW  50
-#define MX51_MXC_INT_GPIO1_HIGH 51
-#define MX51_MXC_INT_GPIO2_LOW  52
-#define MX51_MXC_INT_GPIO2_HIGH 53
-#define MX51_MXC_INT_GPIO3_LOW  54
-#define MX51_MXC_INT_GPIO3_HIGH 55
-#define MX51_MXC_INT_GPIO4_LOW  56
-#define MX51_MXC_INT_GPIO4_HIGH 57
-#define MX51_MXC_INT_WDOG1      58
-#define MX51_MXC_INT_WDOG2      59
-#define MX51_MXC_INT_KPP        60
-#define MX51_MXC_INT_PWM1       61
-#define MX51_MXC_INT_I2C1       62
-#define MX51_MXC_INT_I2C2       63
-#define MX51_MXC_INT_HS_I2C     64
-#define MX51_MXC_INT_RESV65     65
-#define MX51_MXC_INT_RESV66     66
-#define MX51_MXC_INT_SIM_IPB    67
-#define MX51_MXC_INT_SIM_DAT    68
-#define MX51_MXC_INT_IIM        69
-#define MX51_MXC_INT_ATA        70
-#define MX51_MXC_INT_CCM1       71
-#define MX51_MXC_INT_CCM2       72
-#define MX51_MXC_INT_GPC1       73
-#define MX51_MXC_INT_GPC2       74
-#define MX51_MXC_INT_SRC        75
-#define MX51_MXC_INT_NM         76
-#define MX51_MXC_INT_PMU        77
-#define MX51_MXC_INT_CTI_IRQ    78
-#define MX51_MXC_INT_CTI1_TG0   79
-#define MX51_MXC_INT_CTI1_TG1   80
-#define MX51_MXC_INT_MCG_ERR    81
-#define MX51_MXC_INT_MCG_TMR    82
-#define MX51_MXC_INT_MCG_FUNC   83
-#define MX51_MXC_INT_GPU2_IRQ   84
-#define MX51_MXC_INT_GPU2_BUSY  85
-#define MX51_MXC_INT_RESV86     86
-#define MX51_MXC_INT_FEC        87
-#define MX51_MXC_INT_OWIRE      88
-#define MX51_MXC_INT_CTI1_TG2   89
-#define MX51_MXC_INT_SJC        90
-#define MX51_MXC_INT_SPDIF      91
-#define MX51_MXC_INT_TVE        92
-#define MX51_MXC_INT_FIRI       93
-#define MX51_MXC_INT_PWM2       94
-#define MX51_MXC_INT_SLIM_EXP   95
-#define MX51_MXC_INT_SSI3       96
-#define MX51_MXC_INT_EMI_BOOT   97
-#define MX51_MXC_INT_CTI1_TG3   98
-#define MX51_MXC_INT_SMC_RX     99
-#define MX51_MXC_INT_VPU_IDLE   100
-#define MX51_MXC_INT_EMI_NFC    101
-#define MX51_MXC_INT_GPU_IDLE   102
+#define MX51_MXC_INT_BASE               0
+#define MX51_MXC_INT_RESV0              0
+#define MX51_INT_ESDHC1                 1
+#define MX51_INT_ESDHC2                 2
+#define MX51_INT_ESDHC3                 3
+#define MX51_INT_ESDHC4                 4
+#define MX51_MXC_INT_RESV5              5
+#define MX51_INT_SDMA                   6
+#define MX51_MXC_INT_IOMUX              7
+#define MX51_INT_NFC                    8
+#define MX51_MXC_INT_VPU                9
+#define MX51_MXC_INT_IPU_ERR            10
+#define MX51_MXC_INT_IPU_SYN            11
+#define MX51_MXC_INT_GPU                12
+#define MX51_MXC_INT_RESV13             13
+#define MX51_MXC_INT_USB_H1             14
+#define MX51_MXC_INT_EMI                15
+#define MX51_MXC_INT_USB_H2             16
+#define MX51_MXC_INT_USB_H3             17
+#define MX51_MXC_INT_USB_OTG            18
+#define MX51_MXC_INT_SAHARA_H0          19
+#define MX51_MXC_INT_SAHARA_H1          20
+#define MX51_MXC_INT_SCC_SMN            21
+#define MX51_MXC_INT_SCC_STZ            22
+#define MX51_MXC_INT_SCC_SCM            23
+#define MX51_MXC_INT_SRTC_NTZ           24
+#define MX51_MXC_INT_SRTC_TZ            25
+#define MX51_MXC_INT_RTIC               26
+#define MX51_MXC_INT_CSU                27
+#define MX51_MXC_INT_SLIM_B             28
+#define MX51_INT_SSI1                   29
+#define MX51_INT_SSI2                   30
+#define MX51_INT_UART1                  31
+#define MX51_INT_UART2                  32
+#define MX51_INT_UART3                  33
+#define MX51_MXC_INT_RESV34             34
+#define MX51_MXC_INT_RESV35             35
+#define MX51_INT_ECSPI1                 36
+#define MX51_INT_ECSPI2                 37
+#define MX51_INT_CSPI                   38
+#define MX51_MXC_INT_GPT                39
+#define MX51_MXC_INT_EPIT1              40
+#define MX51_MXC_INT_EPIT2              41
+#define MX51_MXC_INT_GPIO1_INT7         42
+#define MX51_MXC_INT_GPIO1_INT6         43
+#define MX51_MXC_INT_GPIO1_INT5         44
+#define MX51_MXC_INT_GPIO1_INT4         45
+#define MX51_MXC_INT_GPIO1_INT3         46
+#define MX51_MXC_INT_GPIO1_INT2         47
+#define MX51_MXC_INT_GPIO1_INT1         48
+#define MX51_MXC_INT_GPIO1_INT0         49
+#define MX51_MXC_INT_GPIO1_LOW          50
+#define MX51_MXC_INT_GPIO1_HIGH         51
+#define MX51_MXC_INT_GPIO2_LOW          52
+#define MX51_MXC_INT_GPIO2_HIGH         53
+#define MX51_MXC_INT_GPIO3_LOW          54
+#define MX51_MXC_INT_GPIO3_HIGH         55
+#define MX51_MXC_INT_GPIO4_LOW          56
+#define MX51_MXC_INT_GPIO4_HIGH         57
+#define MX51_MXC_INT_WDOG1              58
+#define MX51_MXC_INT_WDOG2              59
+#define MX51_MXC_INT_KPP                60
+#define MX51_MXC_INT_PWM1               61
+#define MX51_INT_I2C1                   62
+#define MX51_INT_I2C2                   63
+#define MX51_MXC_INT_HS_I2C             64
+#define MX51_MXC_INT_RESV65             65
+#define MX51_MXC_INT_RESV66             66
+#define MX51_MXC_INT_SIM_IPB            67
+#define MX51_MXC_INT_SIM_DAT            68
+#define MX51_MXC_INT_IIM                69
+#define MX51_MXC_INT_ATA                70
+#define MX51_MXC_INT_CCM1               71
+#define MX51_MXC_INT_CCM2               72
+#define MX51_MXC_INT_GPC1               73
+#define MX51_MXC_INT_GPC2               74
+#define MX51_MXC_INT_SRC                75
+#define MX51_MXC_INT_NM                 76
+#define MX51_MXC_INT_PMU                77
+#define MX51_MXC_INT_CTI_IRQ            78
+#define MX51_MXC_INT_CTI1_TG0           79
+#define MX51_MXC_INT_CTI1_TG1           80
+#define MX51_MXC_INT_MCG_ERR            81
+#define MX51_MXC_INT_MCG_TMR            82
+#define MX51_MXC_INT_MCG_FUNC           83
+#define MX51_MXC_INT_GPU2_IRQ           84
+#define MX51_MXC_INT_GPU2_BUSY          85
+#define MX51_MXC_INT_RESV86             86
+#define MX51_INT_FEC                    87
+#define MX51_MXC_INT_OWIRE              88
+#define MX51_MXC_INT_CTI1_TG2           89
+#define MX51_MXC_INT_SJC                90
+#define MX51_MXC_INT_SPDIF              91
+#define MX51_MXC_INT_TVE                92
+#define MX51_MXC_INT_FIRI               93
+#define MX51_MXC_INT_PWM2               94
+#define MX51_MXC_INT_SLIM_EXP           95
+#define MX51_MXC_INT_SSI3               96
+#define MX51_MXC_INT_EMI_BOOT           97
+#define MX51_MXC_INT_CTI1_TG3           98
+#define MX51_MXC_INT_SMC_RX             99
+#define MX51_MXC_INT_VPU_IDLE           100
+#define MX51_MXC_INT_EMI_NFC            101
+#define MX51_MXC_INT_GPU_IDLE           102
 
 /* silicon revisions specific to i.MX51 */
-#define MX51_CHIP_REV_1_0       0x10
-#define MX51_CHIP_REV_1_1       0x11
-#define MX51_CHIP_REV_1_2       0x12
-#define MX51_CHIP_REV_1_3       0x13
-#define MX51_CHIP_REV_2_0       0x20
-#define MX51_CHIP_REV_2_1       0x21
-#define MX51_CHIP_REV_2_2       0x22
-#define MX51_CHIP_REV_2_3       0x23
-#define MX51_CHIP_REV_3_0       0x30
-#define MX51_CHIP_REV_3_1       0x31
-#define MX51_CHIP_REV_3_2       0x32
-
-/* Mandatory defines used globally */
+#define MX51_CHIP_REV_1_0               0x10
+#define MX51_CHIP_REV_1_1               0x11
+#define MX51_CHIP_REV_1_2               0x12
+#define MX51_CHIP_REV_1_3               0x13
+#define MX51_CHIP_REV_2_0               0x20
+#define MX51_CHIP_REV_2_1               0x21
+#define MX51_CHIP_REV_2_2               0x22
+#define MX51_CHIP_REV_2_3               0x23
+#define MX51_CHIP_REV_3_0               0x30
+#define MX51_CHIP_REV_3_1               0x31
+#define MX51_CHIP_REV_3_2               0x32
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-
 extern int mx51_revision(void);
 #endif
 
-#endif  /*  __ASM_ARCH_MXC_MX51_H__ */
+/* tape-out 1 defines */
+#define MX51_TZIC_BASE_ADDR_TO1         0x8fffc000
+
+#endif  /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 4acd1143a9b..95be51bfe9a 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
 /*
  *  Copyright (C) 1999 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,8 +28,34 @@ static inline void arch_idle(void)
                 mxc91231_prepare_idle();
         }
 #endif
-
-        cpu_do_idle();
+        /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
+        if (cpu_is_mx31() || cpu_is_mx35()) {
+                unsigned long reg = 0;
+                __asm__ __volatile__(
+                        /* disable I and D cache */
+                        "mrc p15, 0, %0, c1, c0, 0\n"
+                        "bic %0, %0, #0x00001000\n"
+                        "bic %0, %0, #0x00000004\n"
+                        "mcr p15, 0, %0, c1, c0, 0\n"
+                        /* invalidate I cache */
+                        "mov %0, #0\n"
+                        "mcr p15, 0, %0, c7, c5, 0\n"
+                        /* clear and invalidate D cache */
+                        "mov %0, #0\n"
+                        "mcr p15, 0, %0, c7, c14, 0\n"
+                        /* WFI */
+                        "mov %0, #0\n"
+                        "mcr p15, 0, %0, c7, c0, 4\n"
+                        "nop\n" "nop\n" "nop\n" "nop\n"
+                        "nop\n" "nop\n" "nop\n"
+                        /* enable I and D cache */
+                        "mrc p15, 0, %0, c1, c0, 0\n"
+                        "orr %0, %0, #0x00001000\n"
+                        "orr %0, %0, #0x00000004\n"
+                        "mcr p15, 0, %0, c1, c0, 0\n"
+                        : "=r" (reg));
+        } else
+                cpu_do_idle();
 }
 
 void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d9bd37e4667..9dd9c2085aa 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -99,6 +99,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
                 uart_base = MX3X_UART2_BASE_ADDR;
                 break;
         case MACH_TYPE_MX51_BABBAGE:
+        case MACH_TYPE_EUKREA_CPUIMX51SD:
                 uart_base = MX51_UART1_BASE_ADDR;
                 break;
         default:
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
new file mode 100644
index 00000000000..074c3869626
--- /dev/null
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/genalloc.h>
+#include <mach/iram.h>
+
+static unsigned long iram_phys_base;
+static void __iomem *iram_virt_base;
+static struct gen_pool *iram_pool;
+
+static inline void __iomem *iram_phys_to_virt(unsigned long p)
+{
+        return iram_virt_base + (p - iram_phys_base);
+}
+
+void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
+{
+        if (!iram_pool)
+                return NULL;
+
+        *dma_addr = gen_pool_alloc(iram_pool, size);
+        pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr);
+        if (!*dma_addr)
+                return NULL;
+        return iram_phys_to_virt(*dma_addr);
+}
+EXPORT_SYMBOL(iram_alloc);
+
+void iram_free(unsigned long addr, unsigned int size)
+{
+        if (!iram_pool)
+                return;
+
+        gen_pool_free(iram_pool, addr, size);
+}
+EXPORT_SYMBOL(iram_free);
+
+int __init iram_init(unsigned long base, unsigned long size)
+{
+        iram_phys_base = base;
+
+        iram_pool = gen_pool_create(PAGE_SHIFT, -1);
+        if (!iram_pool)
+                return -ENOMEM;
+
+        gen_pool_add(iram_pool, base, size, -1);
+        iram_virt_base = ioremap(iram_phys_base, size);
+        if (!iram_virt_base)
+                return -EIO;
+
+        pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base);
+        return 0;
+}
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 977c8f9a07a..85e6fd212a4 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -102,6 +102,22 @@ static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
         writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
 }
 
+static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
+                                  unsigned offset, int val)
+{
+        if (val)
+                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
+        else
+                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
+}
+
+static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
+                                  unsigned offset, int val)
+{
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
+        __nmk_gpio_set_output(nmk_chip, offset, val);
+}
+
 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                              pin_cfg_t cfg)
 {
@@ -118,20 +134,29 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
                 [3] /* illegal */       = "??"
         };
         static const char *slpmnames[] = {
-                [NMK_GPIO_SLPM_INPUT]           = "input",
-                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change",
+                [NMK_GPIO_SLPM_INPUT]           = "input/wakeup",
+                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change/no-wakeup",
         };
 
         int pin = PIN_NUM(cfg);
         int pull = PIN_PULL(cfg);
         int af = PIN_ALT(cfg);
         int slpm = PIN_SLPM(cfg);
+        int output = PIN_DIR(cfg);
+        int val = PIN_VAL(cfg);
 
-        dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n",
-                pin, afnames[af], pullnames[pull], slpmnames[slpm]);
+        dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n",
+                pin, afnames[af], pullnames[pull], slpmnames[slpm],
+                output ? "output " : "input",
+                output ? (val ? "high" : "low") : "");
+
+        if (output)
+                __nmk_gpio_make_output(nmk_chip, offset, val);
+        else {
+                __nmk_gpio_make_input(nmk_chip, offset);
+                __nmk_gpio_set_pull(nmk_chip, offset, pull);
+        }
 
-        __nmk_gpio_make_input(nmk_chip, offset);
-        __nmk_gpio_set_pull(nmk_chip, offset, pull);
         __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
         __nmk_gpio_set_mode(nmk_chip, offset, af);
 }
@@ -200,6 +225,10 @@ EXPORT_SYMBOL(nmk_config_pins);
  * changed to an input (with pullup/down enabled) in sleep and deep sleep.  If
  * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
  * configured even when in sleep and deep sleep.
+ *
+ * On DB8500v2 onwards, this setting loses the previous meaning and instead
+ * indicates if wakeup detection is enabled on the pin.  Note that
+ * enable_irq_wake() will automatically enable wakeup detection.
  */
 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
 {
@@ -367,7 +396,27 @@ static void nmk_gpio_irq_unmask(unsigned int irq)
 
 static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
 {
-        return nmk_gpio_irq_modify(irq, WAKE, on);
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        int gpio;
+
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        if (!nmk_chip)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+#ifdef CONFIG_ARCH_U8500
+        if (cpu_is_u8500v2()) {
+                __nmk_gpio_set_slpm(nmk_chip, gpio,
+                                    on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
+                                       : NMK_GPIO_SLPM_WAKEUP_DISABLE);
+        }
+#endif
+        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
 }
 
 static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
@@ -495,12 +544,8 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
 {
         struct nmk_gpio_chip *nmk_chip =
                 container_of(chip, struct nmk_gpio_chip, chip);
-        u32 bit = 1 << offset;
 
-        if (val)
-                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
-        else
-                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
+        __nmk_gpio_set_output(nmk_chip, offset, val);
 }
 
 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
@@ -509,8 +554,7 @@ static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
         struct nmk_gpio_chip *nmk_chip =
                 container_of(chip, struct nmk_gpio_chip, chip);
 
-        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
-        nmk_gpio_set_output(chip, offset, val);
+        __nmk_gpio_make_output(nmk_chip, offset, val);
 
         return 0;
 }
@@ -534,7 +578,7 @@ static struct gpio_chip nmk_gpio_template = {
         .can_sleep              = 0,
 };
 
-static int __init nmk_gpio_probe(struct platform_device *dev)
+static int __devinit nmk_gpio_probe(struct platform_device *dev)
 {
         struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
         struct nmk_gpio_chip *nmk_chip;
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index aba355101f4..67b113d639d 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -65,7 +65,9 @@ enum nmk_gpio_pull {
 /* Sleep mode */
 enum nmk_gpio_slpm {
         NMK_GPIO_SLPM_INPUT,
+        NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
         NMK_GPIO_SLPM_NOCHANGE,
+        NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
 };
 
 extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 7eed11c1038..8c5ae3f2acf 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -19,12 +19,16 @@
  *      bit  9..10 - Alternate Function Selection
  *      bit 11..12 - Pull up/down state
  *      bit     13 - Sleep mode behaviour
+ *      bit     14 - (sleep mode) Direction
+ *      bit     15 - (sleep mode) Value (if output)
  *
  * to facilitate the definition, the following macros are provided
  *
  * PIN_CFG_DEFAULT - default config (0):
  *                   pull up/down = disabled
- *                   sleep mode = input
+ *                   sleep mode = input/wakeup
+ *                   (sleep mode) direction = input
+ *                   (sleep mode) value = low
  *
  * PIN_CFG         - default config with alternate function
  * PIN_CFG_PULL    - default config with alternate function and pull up/down
@@ -53,8 +57,36 @@ typedef unsigned long pin_cfg_t;
 #define PIN_SLPM_SHIFT          13
 #define PIN_SLPM_MASK           (0x1 << PIN_SLPM_SHIFT)
 #define PIN_SLPM(x)             (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
-#define PIN_SLPM_INPUT          (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_MAKE_INPUT     (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
 #define PIN_SLPM_NOCHANGE       (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+/* These two replace the above in DB8500v2+ */
+#define PIN_SLPM_WAKEUP_ENABLE  (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+
+#define PIN_DIR_SHIFT           14
+#define PIN_DIR_MASK            (0x1 << PIN_DIR_SHIFT)
+#define PIN_DIR(x)              (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
+#define PIN_DIR_INPUT           (0 << PIN_DIR_SHIFT)
+#define PIN_DIR_OUTPUT          (1 << PIN_DIR_SHIFT)
+
+#define PIN_VAL_SHIFT           15
+#define PIN_VAL_MASK            (0x1 << PIN_VAL_SHIFT)
+#define PIN_VAL(x)              (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
+#define PIN_VAL_LOW             (0 << PIN_VAL_SHIFT)
+#define PIN_VAL_HIGH            (1 << PIN_VAL_SHIFT)
+
+/* Shortcuts.  Use these instead of separate DIR and VAL.  */
+#define PIN_INPUT               PIN_DIR_INPUT
+#define PIN_OUTPUT_LOW          (PIN_DIR_OUTPUT | PIN_VAL_LOW)
+#define PIN_OUTPUT_HIGH         (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
+
+/*
+ * These are the same as the ones above, but should make more sense to the
+ * reader when seen along with a setting a pin to AF mode.
+ */
+#define PIN_SLPM_INPUT          PIN_INPUT
+#define PIN_SLPM_OUTPUT_LOW     PIN_OUTPUT_LOW
+#define PIN_SLPM_OUTPUT_HIGH    PIN_OUTPUT_HIGH
 
 #define PIN_CFG_DEFAULT         (PIN_PULL_NONE | PIN_SLPM_INPUT)
 
diff --git a/arch/arm/plat-nomadik/include/plat/ske.h b/arch/arm/plat-nomadik/include/plat/ske.h
new file mode 100644
index 00000000000..31382fbc07d
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/ske.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Naveen Kumar Gaddipati <naveen.gaddipati@stericsson.com>
+ *
+ * ux500 Scroll key and Keypad Encoder (SKE) header
+ */
+
+#ifndef __SKE_H
+#define __SKE_H
+
+#include <linux/input/matrix_keypad.h>
+
+/* register definitions for SKE peripheral */
+#define SKE_CR          0x00
+#define SKE_VAL0        0x04
+#define SKE_VAL1        0x08
+#define SKE_DBCR        0x0C
+#define SKE_IMSC        0x10
+#define SKE_RIS         0x14
+#define SKE_MIS         0x18
+#define SKE_ICR         0x1C
+
+/*
+ * Keypad module
+ */
+
+/**
+ * struct keypad_platform_data - structure for platform specific data
+ * @init:       pointer to keypad init function
+ * @exit:       pointer to keypad deinitialisation function
+ * @keymap_data: matrix scan code table for keycodes
+ * @krow:       maximum number of rows
+ * @kcol:       maximum number of columns
+ * @debounce_ms: platform specific debounce time
+ * @no_autorepeat: flag for auto repetition
+ * @wakeup_enable: allow waking up the system
+ */
+struct ske_keypad_platform_data {
+        int (*init)(void);
+        int (*exit)(void);
+        const struct matrix_keymap_data *keymap_data;
+        u8 krow;
+        u8 kcol;
+        u8 debounce_ms;
+        bool no_autorepeat;
+        bool wakeup_enable;
+};
+#endif  /*__SKE_KPD_H*/
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index e39a417a368..92c5bb7909f 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -19,7 +19,7 @@ config ARCH_OMAP2PLUS
         bool "TI OMAP2/3/4"
         select COMMON_CLKDEV
         help
-          "Systems based on omap24xx, omap34xx or omap44xx"
+          "Systems based on OMAP2, OMAP3 or OMAP4"
 
 endchoice
 
@@ -33,7 +33,7 @@ config OMAP_DEBUG_DEVICES
 config OMAP_DEBUG_LEDS
         bool
         depends on OMAP_DEBUG_DEVICES
-        default y if LEDS
+        default y if LEDS_CLASS
 
 config OMAP_RESET_CLOCKS
         bool "Reset unused clocks during boot"
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 9405831b746..a4a12859fdd 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
-         usb.o fb.o io.o
+         usb.o fb.o io.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
@@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
 # OMAP mailbox framework
 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
 
-obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
\ No newline at end of file
+obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 7190cbd9262..fc62fb5fc20 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -60,7 +60,7 @@ void clk_disable(struct clk *clk)
 
         spin_lock_irqsave(&clockfw_lock, flags);
         if (clk->usecount == 0) {
-                printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
+                pr_err("Trying disable clock %s with 0 usecount\n",
                        clk->name);
                 WARN_ON(1);
                 goto out;
@@ -397,6 +397,7 @@ static int __init clk_disable_unused(void)
         struct clk *ck;
         unsigned long flags;
 
+        pr_info("clock: disabling unused clocks to save power\n");
         list_for_each_entry(ck, &clocks, node) {
                 if (ck->ops == &clkops_null)
                         continue;
@@ -418,7 +419,7 @@ late_initcall(clk_disable_unused);
 int __init clk_init(struct clk_functions * custom_clocks)
 {
         if (!custom_clocks) {
-                printk(KERN_ERR "No custom clock functions registered\n");
+                pr_err("No custom clock functions registered\n");
                 BUG();
         }
 
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 3008e710448..221a675ebba 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -11,38 +11,15 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/console.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/omapfb.h>
 
-#include <mach/hardware.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-
 #include <plat/common.h>
 #include <plat/board.h>
-#include <plat/control.h>
-#include <plat/mux.h>
-#include <plat/fpga.h>
-#include <plat/serial.h>
 #include <plat/vram.h>
 
-#include <plat/clock.h>
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-# include "../mach-omap2/sdrc.h"
-#endif
 
 #define NO_LENGTH_CHECK 0xffffffff
 
@@ -88,270 +65,3 @@ void __init omap_reserve(void)
         omapfb_reserve_sdram_memblock();
         omap_vram_reserve_sdram_memblock();
 }
-
-/*
- * 32KHz clocksource ... always available, on pretty most chips except
- * OMAP 730 and 1510.  Other timers could be used as clocksources, with
- * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
- * but systems won't necessarily want to spend resources that way.
- */
-
-#define OMAP16XX_TIMER_32K_SYNCHRONIZED         0xfffbc410
-
-#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
-
-#include <linux/clocksource.h>
-
-/*
- * offset_32k holds the init time counter value. It is then subtracted
- * from every counter read to achieve a counter that counts time from the
- * kernel boot (needed for sched_clock()).
- */
-static u32 offset_32k __read_mostly;
-
-#ifdef CONFIG_ARCH_OMAP16XX
-static cycle_t omap16xx_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
-}
-#else
-#define omap16xx_32k_read       NULL
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2420
-static cycle_t omap2420_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap2420_32k_read       NULL
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2430
-static cycle_t omap2430_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap2430_32k_read       NULL
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static cycle_t omap34xx_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap34xx_32k_read       NULL
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-static cycle_t omap44xx_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap44xx_32k_read       NULL
-#endif
-
-/*
- * Kernel assumes that sched_clock can be called early but may not have
- * things ready yet.
- */
-static cycle_t omap_32k_read_dummy(struct clocksource *cs)
-{
-        return 0;
-}
-
-static struct clocksource clocksource_32k = {
-        .name           = "32k_counter",
-        .rating         = 250,
-        .read           = omap_32k_read_dummy,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 10,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-/*
- * Returns current time from boot in nsecs. It's OK for this to wrap
- * around for now, as it's just a relative time stamp.
- */
-unsigned long long sched_clock(void)
-{
-        return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
-                                  clocksource_32k.mult, clocksource_32k.shift);
-}
-
-/**
- * read_persistent_clock -  Return time from a persistent clock.
- *
- * Reads the time from a source which isn't disabled during PM, the
- * 32k sync timer.  Convert the cycles elapsed since last read into
- * nsecs and adds to a monotonically increasing timespec.
- */
-static struct timespec persistent_ts;
-static cycles_t cycles, last_cycles;
-void read_persistent_clock(struct timespec *ts)
-{
-        unsigned long long nsecs;
-        cycles_t delta;
-        struct timespec *tsp = &persistent_ts;
-
-        last_cycles = cycles;
-        cycles = clocksource_32k.read(&clocksource_32k);
-        delta = cycles - last_cycles;
-
-        nsecs = clocksource_cyc2ns(delta,
-                                   clocksource_32k.mult, clocksource_32k.shift);
-
-        timespec_add_ns(tsp, nsecs);
-        *ts = *tsp;
-}
-
-static int __init omap_init_clocksource_32k(void)
-{
-        static char err[] __initdata = KERN_ERR
-                        "%s: can't register clocksource!\n";
-
-        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
-                struct clk *sync_32k_ick;
-
-                if (cpu_is_omap16xx())
-                        clocksource_32k.read = omap16xx_32k_read;
-                else if (cpu_is_omap2420())
-                        clocksource_32k.read = omap2420_32k_read;
-                else if (cpu_is_omap2430())
-                        clocksource_32k.read = omap2430_32k_read;
-                else if (cpu_is_omap34xx())
-                        clocksource_32k.read = omap34xx_32k_read;
-                else if (cpu_is_omap44xx())
-                        clocksource_32k.read = omap44xx_32k_read;
-                else
-                        return -ENODEV;
-
-                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
-                if (sync_32k_ick)
-                        clk_enable(sync_32k_ick);
-
-                clocksource_32k.mult = clocksource_hz2mult(32768,
-                                            clocksource_32k.shift);
-
-                offset_32k = clocksource_32k.read(&clocksource_32k);
-
-                if (clocksource_register(&clocksource_32k))
-                        printk(err, clocksource_32k.name);
-        }
-        return 0;
-}
-arch_initcall(omap_init_clocksource_32k);
-
-#endif  /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
-
-/* Global address base setup code */
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-
-static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
-{
-        omap2_set_globals_tap(omap2_globals);
-        omap2_set_globals_sdrc(omap2_globals);
-        omap2_set_globals_control(omap2_globals);
-        omap2_set_globals_prcm(omap2_globals);
-        omap2_set_globals_uart(omap2_globals);
-}
-
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2420)
-
-static struct omap_globals omap242x_globals = {
-        .class  = OMAP242X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
-        .sdrc   = OMAP2420_SDRC_BASE,
-        .sms    = OMAP2420_SMS_BASE,
-        .ctrl   = OMAP2420_CTRL_BASE,
-        .prm    = OMAP2420_PRM_BASE,
-        .cm     = OMAP2420_CM_BASE,
-        .uart1_phys     = OMAP2_UART1_BASE,
-        .uart2_phys     = OMAP2_UART2_BASE,
-        .uart3_phys     = OMAP2_UART3_BASE,
-};
-
-void __init omap2_set_globals_242x(void)
-{
-        __omap2_set_globals(&omap242x_globals);
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2430)
-
-static struct omap_globals omap243x_globals = {
-        .class  = OMAP243X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
-        .sdrc   = OMAP243X_SDRC_BASE,
-        .sms    = OMAP243X_SMS_BASE,
-        .ctrl   = OMAP243X_CTRL_BASE,
-        .prm    = OMAP2430_PRM_BASE,
-        .cm     = OMAP2430_CM_BASE,
-        .uart1_phys     = OMAP2_UART1_BASE,
-        .uart2_phys     = OMAP2_UART2_BASE,
-        .uart3_phys     = OMAP2_UART3_BASE,
-};
-
-void __init omap2_set_globals_243x(void)
-{
-        __omap2_set_globals(&omap243x_globals);
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3)
-
-static struct omap_globals omap3_globals = {
-        .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
-        .sdrc   = OMAP343X_SDRC_BASE,
-        .sms    = OMAP343X_SMS_BASE,
-        .ctrl   = OMAP343X_CTRL_BASE,
-        .prm    = OMAP3430_PRM_BASE,
-        .cm     = OMAP3430_CM_BASE,
-        .uart1_phys     = OMAP3_UART1_BASE,
-        .uart2_phys     = OMAP3_UART2_BASE,
-        .uart3_phys     = OMAP3_UART3_BASE,
-        .uart4_phys     = OMAP3_UART4_BASE,     /* Only on 3630 */
-};
-
-void __init omap2_set_globals_3xxx(void)
-{
-        __omap2_set_globals(&omap3_globals);
-}
-
-void __init omap3_map_io(void)
-{
-        omap2_set_globals_3xxx();
-        omap34xx_map_common_io();
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP4)
-static struct omap_globals omap4_globals = {
-        .class  = OMAP443X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-        .ctrl   = OMAP443X_CTRL_BASE,
-        .prm    = OMAP4430_PRM_BASE,
-        .cm     = OMAP4430_CM_BASE,
-        .cm2    = OMAP4430_CM2_BASE,
-        .uart1_phys     = OMAP4_UART1_BASE,
-        .uart2_phys     = OMAP4_UART2_BASE,
-        .uart3_phys     = OMAP4_UART3_BASE,
-        .uart4_phys     = OMAP4_UART4_BASE,
-};
-
-void __init omap2_set_globals_443x(void)
-{
-        omap2_set_globals_tap(&omap4_globals);
-        omap2_set_globals_control(&omap4_globals);
-        omap2_set_globals_prcm(&omap4_globals);
-        omap2_set_globals_uart(&omap4_globals);
-}
-#endif
-
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
new file mode 100644
index 00000000000..155fe43a672
--- /dev/null
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -0,0 +1,183 @@
+/*
+ * OMAP 32ksynctimer/counter_32k-related code
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2010 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+#include <plat/board.h>
+
+#include <plat/clock.h>
+
+
+/*
+ * 32KHz clocksource ... always available, on pretty most chips except
+ * OMAP 730 and 1510.  Other timers could be used as clocksources, with
+ * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
+ * but systems won't necessarily want to spend resources that way.
+ */
+
+#define OMAP16XX_TIMER_32K_SYNCHRONIZED         0xfffbc410
+
+#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
+
+#include <linux/clocksource.h>
+
+/*
+ * offset_32k holds the init time counter value. It is then subtracted
+ * from every counter read to achieve a counter that counts time from the
+ * kernel boot (needed for sched_clock()).
+ */
+static u32 offset_32k __read_mostly;
+
+#ifdef CONFIG_ARCH_OMAP16XX
+static cycle_t omap16xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
+}
+#else
+#define omap16xx_32k_read       NULL
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2420
+static cycle_t omap2420_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap2420_32k_read       NULL
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+static cycle_t omap2430_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap2430_32k_read       NULL
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static cycle_t omap34xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap34xx_32k_read       NULL
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+static cycle_t omap44xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap44xx_32k_read       NULL
+#endif
+
+/*
+ * Kernel assumes that sched_clock can be called early but may not have
+ * things ready yet.
+ */
+static cycle_t omap_32k_read_dummy(struct clocksource *cs)
+{
+        return 0;
+}
+
+static struct clocksource clocksource_32k = {
+        .name           = "32k_counter",
+        .rating         = 250,
+        .read           = omap_32k_read_dummy,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 10,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/*
+ * Returns current time from boot in nsecs. It's OK for this to wrap
+ * around for now, as it's just a relative time stamp.
+ */
+unsigned long long sched_clock(void)
+{
+        return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
+                                  clocksource_32k.mult, clocksource_32k.shift);
+}
+
+/**
+ * read_persistent_clock -  Return time from a persistent clock.
+ *
+ * Reads the time from a source which isn't disabled during PM, the
+ * 32k sync timer.  Convert the cycles elapsed since last read into
+ * nsecs and adds to a monotonically increasing timespec.
+ */
+static struct timespec persistent_ts;
+static cycles_t cycles, last_cycles;
+void read_persistent_clock(struct timespec *ts)
+{
+        unsigned long long nsecs;
+        cycles_t delta;
+        struct timespec *tsp = &persistent_ts;
+
+        last_cycles = cycles;
+        cycles = clocksource_32k.read(&clocksource_32k);
+        delta = cycles - last_cycles;
+
+        nsecs = clocksource_cyc2ns(delta,
+                                   clocksource_32k.mult, clocksource_32k.shift);
+
+        timespec_add_ns(tsp, nsecs);
+        *ts = *tsp;
+}
+
+static int __init omap_init_clocksource_32k(void)
+{
+        static char err[] __initdata = KERN_ERR
+                        "%s: can't register clocksource!\n";
+
+        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
+                struct clk *sync_32k_ick;
+
+                if (cpu_is_omap16xx())
+                        clocksource_32k.read = omap16xx_32k_read;
+                else if (cpu_is_omap2420())
+                        clocksource_32k.read = omap2420_32k_read;
+                else if (cpu_is_omap2430())
+                        clocksource_32k.read = omap2430_32k_read;
+                else if (cpu_is_omap34xx())
+                        clocksource_32k.read = omap34xx_32k_read;
+                else if (cpu_is_omap44xx())
+                        clocksource_32k.read = omap44xx_32k_read;
+                else
+                        return -ENODEV;
+
+                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
+                if (sync_32k_ick)
+                        clk_enable(sync_32k_ick);
+
+                clocksource_32k.mult = clocksource_hz2mult(32768,
+                                            clocksource_32k.shift);
+
+                offset_32k = clocksource_32k.read(&clocksource_32k);
+
+                if (clocksource_register(&clocksource_32k))
+                        printk(err, clocksource_32k.name);
+        }
+        return 0;
+}
+arch_initcall(omap_init_clocksource_32k);
+
+#endif  /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
+
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 6d3d3336005..11c54ec8d47 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -40,7 +40,7 @@ static struct clk *mpu_clk;
 
 /* TODO: Add support for SDRAM timing changes */
 
-int omap_verify_speed(struct cpufreq_policy *policy)
+static int omap_verify_speed(struct cpufreq_policy *policy)
 {
         if (freq_table)
                 return cpufreq_frequency_table_verify(policy, freq_table);
@@ -58,7 +58,7 @@ int omap_verify_speed(struct cpufreq_policy *policy)
         return 0;
 }
 
-unsigned int omap_getspeed(unsigned int cpu)
+static unsigned int omap_getspeed(unsigned int cpu)
 {
         unsigned long rate;
 
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index d1920be7833..1e2383eae63 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -21,7 +21,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/control.h>
 #include <plat/board.h>
 #include <plat/mmc.h>
 #include <mach/gpio.h>
@@ -232,46 +231,6 @@ static void omap_init_uwire(void)
 static inline void omap_init_uwire(void) {}
 #endif
 
-/*-------------------------------------------------------------------------*/
-
-#if     defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
-
-static struct resource wdt_resources[] = {
-        {
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap_wdt_device = {
-        .name      = "omap_wdt",
-        .id          = -1,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-        .resource       = wdt_resources,
-};
-
-static void omap_init_wdt(void)
-{
-        if (cpu_is_omap16xx())
-                wdt_resources[0].start = 0xfffeb000;
-        else if (cpu_is_omap2420())
-                wdt_resources[0].start = 0x48022000; /* WDT2 */
-        else if (cpu_is_omap2430())
-                wdt_resources[0].start = 0x49016000; /* WDT2 */
-        else if (cpu_is_omap343x())
-                wdt_resources[0].start = 0x48314000; /* WDT2 */
-        else if (cpu_is_omap44xx())
-                wdt_resources[0].start = 0x4a314000;
-        else
-                return;
-
-        wdt_resources[0].end = wdt_resources[0].start + 0x4f;
-
-        (void) platform_device_register(&omap_wdt_device);
-}
-#else
-static inline void omap_init_wdt(void) {}
-#endif
-
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -300,7 +259,6 @@ static int __init omap_init_devices(void)
         omap_init_rng();
         omap_init_mcpdm();
         omap_init_uwire();
-        omap_init_wdt();
         return 0;
 }
 arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index ec7eddf9e52..f5c5b8da9a8 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -30,6 +30,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/delay.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
@@ -996,11 +997,17 @@ void omap_start_dma(int lch)
         l = dma_read(CCR(lch));
 
         /*
-         * Errata: On ES2.0 BUFFERING disable must be set.
-         * This will always fail on ES1.0
+         * Errata: Inter Frame DMA buffering issue (All OMAP2420 and
+         * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and
+         * bursting is enabled. This might result in data gets stalled in
+         * FIFO at the end of the block.
+         * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
+         * guarantee no data will stay in the DMA FIFO in case inter frame
+         * buffering occurs.
          */
-        if (cpu_is_omap24xx())
-                l |= OMAP_DMA_CCR_EN;
+        if (cpu_is_omap2420() ||
+            (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0)))
+                l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 
         l |= OMAP_DMA_CCR_EN;
         dma_write(l, CCR(lch));
@@ -1018,8 +1025,39 @@ void omap_stop_dma(int lch)
                 dma_write(0, CICR(lch));
 
         l = dma_read(CCR(lch));
-        l &= ~OMAP_DMA_CCR_EN;
-        dma_write(l, CCR(lch));
+        /* OMAP3 Errata i541: sDMA FIFO draining does not finish */
+        if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
+                int i = 0;
+                u32 sys_cf;
+
+                /* Configure No-Standby */
+                l = dma_read(OCP_SYSCONFIG);
+                sys_cf = l;
+                l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
+                l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
+                dma_write(l , OCP_SYSCONFIG);
+
+                l = dma_read(CCR(lch));
+                l &= ~OMAP_DMA_CCR_EN;
+                dma_write(l, CCR(lch));
+
+                /* Wait for sDMA FIFO drain */
+                l = dma_read(CCR(lch));
+                while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
+                                        OMAP_DMA_CCR_WR_ACTIVE))) {
+                        udelay(5);
+                        i++;
+                        l = dma_read(CCR(lch));
+                }
+                if (i >= 100)
+                        printk(KERN_ERR "DMA drain did not complete on "
+                                        "lch %d\n", lch);
+                /* Restore OCP_SYSCONFIG */
+                dma_write(sys_cf, OCP_SYSCONFIG);
+        } else {
+                l &= ~OMAP_DMA_CCR_EN;
+                dma_write(l, CCR(lch));
+        }
 
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch = lch;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 44bafdab2dc..1d706cf63ca 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
          * When the functional clock disappears, too quick writes seem
          * to cause an abort. XXX Is this still necessary?
          */
-        __delay(150000);
+        __delay(300000);
 
         return ret;
 }
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index f2a1483bdad..c9e5d7298c4 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -36,6 +36,8 @@
 #include <plat/board.h>
 #include <plat/sram.h>
 
+#include "fb.h"
+
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
 static struct omapfb_platform_data omapfb_config;
@@ -173,11 +175,7 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
 
 static int valid_sdram(unsigned long addr, unsigned long size)
 {
-        struct memblock_property res;
-
-        res.base = addr;
-        res.size = size;
-        return !memblock_find(&res) && res.base == addr && res.size == size;
+        return memblock_is_region_memory(addr, size);
 }
 
 static int reserve_sdram(unsigned long addr, unsigned long size)
diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h
new file mode 100644
index 00000000000..d765d0bd852
--- /dev/null
+++ b/arch/arm/plat-omap/fb.h
@@ -0,0 +1,10 @@
+#ifndef __PLAT_OMAP_FB_H__
+#define __PLAT_OMAP_FB_H__
+
+extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+                                         unsigned long sram_vstart,
+                                         unsigned long sram_size,
+                                         unsigned long pstart_avail,
+                                         unsigned long size_avail);
+
+#endif /* __PLAT_OMAP_FB_H__ */
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7951eefe1a0..c05c653d167 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -2084,9 +2084,10 @@ void omap2_gpio_prepare_for_idle(int power_state)
 
         for (i = min; i < gpio_bank_count; i++) {
                 struct gpio_bank *bank = &gpio_bank[i];
-                u32 l1, l2;
+                u32 l1 = 0, l2 = 0;
+                int j;
 
-                if (bank->dbck_enable_mask)
+                for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
                         clk_disable(bank->dbck);
 
                 if (power_state > PWRDM_POWER_OFF)
@@ -2151,9 +2152,10 @@ void omap2_gpio_resume_after_idle(void)
                 min = 1;
         for (i = min; i < gpio_bank_count; i++) {
                 struct gpio_bank *bank = &gpio_bank[i];
-                u32 l, gen, gen0, gen1;
+                u32 l = 0, gen, gen0, gen1;
+                int j;
 
-                if (bank->dbck_enable_mask)
+                for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
                         clk_enable(bank->dbck);
 
                 if (!workaround_enabled)
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 9776b41ad76..a9d69a09920 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -47,6 +47,7 @@ struct omap_globals {
         unsigned long   sdrc;           /* SDRAM Controller */
         unsigned long   sms;            /* SDRAM Memory Scheduler */
         unsigned long   ctrl;           /* System Control Module */
+        unsigned long   ctrl_pad;       /* PAD Control Module */
         unsigned long   prm;            /* Power and Reset Management */
         unsigned long   cm;             /* Clock Management */
         unsigned long   cm2;
@@ -66,7 +67,6 @@ void omap2_set_globals_tap(struct omap_globals *);
 void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
-void omap2_set_globals_uart(struct omap_globals *);
 
 void omap3_map_io(void);
 
@@ -91,7 +91,8 @@ void omap3_map_io(void);
 })
 
 extern struct device *omap2_get_mpuss_device(void);
-extern struct device *omap2_get_dsp_device(void);
+extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
+extern struct device *omap4_get_dsp_device(void);
 
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e2ae530fce..3fd8b405572 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -68,10 +68,9 @@ unsigned int omap_rev(void);
 #define OMAP_REVBITS_00         0x00
 #define OMAP_REVBITS_01         0x01
 #define OMAP_REVBITS_02         0x02
-#define OMAP_REVBITS_10         0x10
-#define OMAP_REVBITS_20         0x20
-#define OMAP_REVBITS_30         0x30
-#define OMAP_REVBITS_40         0x40
+#define OMAP_REVBITS_03         0x03
+#define OMAP_REVBITS_04         0x04
+#define OMAP_REVBITS_05         0x05
 
 /*
  * Get the CPU revision for OMAP devices
@@ -363,23 +362,24 @@ IS_OMAP_TYPE(3517, 0x3517)
 
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
-#define OMAP2420_REV_ES1_0      0x24200024
-#define OMAP2420_REV_ES2_0      0x24201024
+#define OMAP2420_REV_ES1_0      OMAP242X_CLASS
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
 
 #define OMAP243X_CLASS          0x24300024
-#define OMAP2430_REV_ES1_0      0x24300024
+#define OMAP2430_REV_ES1_0      OMAP243X_CLASS
 
 #define OMAP343X_CLASS          0x34300034
-#define OMAP3430_REV_ES1_0      0x34300034
-#define OMAP3430_REV_ES2_0      0x34301034
-#define OMAP3430_REV_ES2_1      0x34302034
-#define OMAP3430_REV_ES3_0      0x34303034
-#define OMAP3430_REV_ES3_1      0x34304034
-#define OMAP3430_REV_ES3_1_2    0x34305034
-
-#define OMAP3630_REV_ES1_0      0x36300034
-#define OMAP3630_REV_ES1_1      0x36300134
-#define OMAP3630_REV_ES1_2      0x36300234
+#define OMAP3430_REV_ES1_0      OMAP343X_CLASS
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
+
+#define OMAP363X_CLASS          0x36300034
+#define OMAP3630_REV_ES1_0      OMAP363X_CLASS
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
 
 #define OMAP35XX_CLASS          0x35000034
 #define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
@@ -390,7 +390,8 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
 
 #define OMAP443X_CLASS          0x44300044
-#define OMAP4430_REV_ES1_0      0x44300044
+#define OMAP4430_REV_ES1_0      OMAP443X_CLASS
+#define OMAP4430_REV_ES2_0      0x44301044
 
 /*
  * omap_chip bits
@@ -417,10 +418,12 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP4430ES1             (1 << 8)
 #define CHIP_IS_OMAP3630ES1_1           (1 << 9)
 #define CHIP_IS_OMAP3630ES1_2           (1 << 10)
+#define CHIP_IS_OMAP4430ES2             (1 << 11)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1)
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 | \
+                                                 CHIP_IS_OMAP4430ES2)
 
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index af3a03941ad..0cce4ca83aa 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -319,6 +319,8 @@
 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
+#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
+#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
 /*----------------------------------------------------------------------------*/
 
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
@@ -335,6 +337,10 @@
 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 
 #define OMAP_DMA_CCR_EN                 (1 << 7)
+#define OMAP_DMA_CCR_RD_ACTIVE          (1 << 9)
+#define OMAP_DMA_CCR_WR_ACTIVE          (1 << 10)
+#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC   (1 << 24)
+#define OMAP_DMA_CCR_BUFFERING_DISABLE  (1 << 25)
 
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a8..dfa3aff9761 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -45,6 +45,8 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 
 struct omap_dm_timer;
+extern struct omap_dm_timer *gptimer_wakeup;
+extern struct sys_timer omap_timer;
 struct clk;
 
 int omap_dm_timer_init(void);
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
new file mode 100644
index 00000000000..872de0bf1e6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+ *
+ * Copyright (C) 2009 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
+
+struct omap_smsc911x_platform_data {
+        int     cs;
+        int     gpio_irq;
+        int     gpio_reset;
+        u32     flags;
+};
+
+#if defined(CONFIG_SMSC911X) || \
+        defined(CONFIG_SMSC911X_MODULE)
+
+extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
+
+#else
+
+static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
+{
+}
+
+#endif
+#endif
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 87f6bf2ea4f..36a0befd616 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,6 +18,8 @@
  * 02110-1301 USA
  *
  */
+#ifndef __ASM__ARCH_OMAP_I2C_H
+#define __ASM__ARCH_OMAP_I2C_H
 
 #include <linux/i2c.h>
 
@@ -36,3 +38,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 
 void __init omap1_i2c_mux_pins(int bus_id);
 void __init omap2_i2c_mux_pins(int bus_id);
+
+#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index c01d9f08a19..65e20a68671 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -345,6 +345,8 @@
 #define INT_34XX_MMC3_IRQ       94
 #define INT_34XX_GPT12_IRQ      95
 
+#define INT_36XX_UART4_IRQ      80
+
 #define INT_35XX_HECC0_IRQ              24
 #define INT_35XX_HECC1_IRQ              28
 #define INT_35XX_EMAC_C0_RXTHRESH_IRQ   67
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index b4ff6a11a8f..b87d83ccd54 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -30,6 +30,13 @@
 #include <mach/hardware.h>
 #include <plat/clock.h>
 
+/* macro for building platform_device for McBSP ports */
+#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
+static struct platform_device omap_mcbsp##port_nr = {   \
+        .name   = "omap-mcbsp-dai",                     \
+        .id     = OMAP_MCBSP##port_nr,                  \
+}
+
 #define OMAP7XX_MCBSP1_BASE     0xfffb1000
 #define OMAP7XX_MCBSP2_BASE     0xfffb1800
 
@@ -312,6 +319,18 @@
 #define RFSREN                  0x0002
 #define RSYNCERREN              0x0001
 
+/* CLKR signal muxing options */
+#define CLKR_SRC_CLKR           0
+#define CLKR_SRC_CLKX           1
+
+/* FSR signal muxing options */
+#define FSR_SRC_FSR             0
+#define FSR_SRC_FSX             1
+
+/* McBSP functional clock sources */
+#define MCBSP_CLKS_PRCM_SRC     0
+#define MCBSP_CLKS_PAD_SRC      1
+
 /* we don't do multichannel for now */
 struct omap_mcbsp_reg_cfg {
         u16 spcr2;
@@ -398,6 +417,7 @@ struct omap_mcbsp_spi_cfg {
 struct omap_mcbsp_ops {
         void (*request)(unsigned int);
         void (*free)(unsigned int);
+        int (*set_clks_src)(u8, u8);
 };
 
 struct omap_mcbsp_platform_data {
@@ -464,6 +484,9 @@ struct omap_mcbsp {
 extern struct omap_mcbsp **mcbsp_ptr;
 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 
+#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
+#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
+
 int omap_mcbsp_init(void);
 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                                         int size);
@@ -502,6 +525,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
 
 
+/* McBSP functional clock source changing function */
+extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
 /* SPI specific API */
 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
 
@@ -510,6 +535,10 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 
+/* McBSP signal muxing API */
+void omap2_mcbsp1_mux_clkr_src(u8 mux);
+void omap2_mcbsp1_mux_fsr_src(u8 mux);
+
 #ifdef CONFIG_ARCH_OMAP3
 /* Sidetone specific API */
 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 9b89ec601ee..f57f36abb07 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -71,12 +71,17 @@ struct omap_mmc_platform_data {
 
         u64 dma_mask;
 
+        /* Register offset deviation */
+        u16 reg_offset;
+
         struct omap_mmc_slot_data {
 
-                /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
-                 * 8 wire signaling is also optional, and is used with HSMMC
+                /*
+                 * 4/8 wires and any additional host capabilities
+                 * need to OR'd all capabilities (ref. linux/mmc/host.h)
                  */
-                u8 wires;
+                u8  wires;      /* Used for the MMC driver on omap1 and 2420 */
+                u32 caps;       /* Used for the MMC driver on 2430 and later */
 
                 /*
                  * nomux means "standard" muxing is wrong on this board, and
@@ -104,6 +109,7 @@ struct omap_mmc_platform_data {
 
                 /* we can put the features above into this variable */
 #define HSMMC_HAS_PBIAS         (1 << 0)
+#define HSMMC_HAS_UPDATED_RESET (1 << 1)
                 unsigned features;
 
                 int switch_pin;                 /* gpio (card detect) */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
new file mode 100644
index 00000000000..c8dae02f070
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -0,0 +1,128 @@
+/*
+ * Driver for OMAP-UART controller.
+ * Based on drivers/serial/8250.c
+ *
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ * Authors:
+ *      Govindraj R     <govindraj.raja@ti.com>
+ *      Thara Gopinath  <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __OMAP_SERIAL_H__
+#define __OMAP_SERIAL_H__
+
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <plat/mux.h>
+
+#define DRIVER_NAME     "omap-hsuart"
+
+/*
+ * Use tty device name as ttyO, [O -> OMAP]
+ * in bootargs we specify as console=ttyO0 if uart1
+ * is used as console uart.
+ */
+#define OMAP_SERIAL_NAME        "ttyO"
+
+#define OMAP_MDR1_DISABLE       0x07
+#define OMAP_MDR1_MODE13X       0x03
+#define OMAP_MDR1_MODE16X       0x00
+#define OMAP_MODE13X_SPEED      230400
+
+/*
+ * LCR = 0XBF: Switch to Configuration Mode B.
+ * In configuration mode b allow access
+ * to EFR,DLL,DLH.
+ * Reference OMAP TRM Chapter 17
+ * Section: 1.4.3 Mode Selection
+ */
+#define OMAP_UART_LCR_CONF_MDB  0XBF
+
+/* WER = 0x7F
+ * Enable module level wakeup in WER reg
+ */
+#define OMAP_UART_WER_MOD_WKUP  0X7F
+
+/* Enable XON/XOFF flow control on output */
+#define OMAP_UART_SW_TX         0x04
+
+/* Enable XON/XOFF flow control on input */
+#define OMAP_UART_SW_RX         0x04
+
+#define OMAP_UART_SYSC_RESET    0X07
+#define OMAP_UART_TCR_TRIG      0X0F
+#define OMAP_UART_SW_CLR        0XF0
+#define OMAP_UART_FIFO_CLR      0X06
+
+#define OMAP_UART_DMA_CH_FREE   -1
+
+#define RX_TIMEOUT              (3 * HZ)
+#define OMAP_MAX_HSUART_PORTS   4
+
+#define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
+
+struct omap_uart_port_info {
+        bool                    dma_enabled;    /* To specify DMA Mode */
+        unsigned int            uartclk;        /* UART clock rate */
+        void __iomem            *membase;       /* ioremap cookie or NULL */
+        resource_size_t         mapbase;        /* resource base */
+        unsigned long           irqflags;       /* request_irq flags */
+        upf_t                   flags;          /* UPF_* flags */
+};
+
+struct uart_omap_dma {
+        u8                      uart_dma_tx;
+        u8                      uart_dma_rx;
+        int                     rx_dma_channel;
+        int                     tx_dma_channel;
+        dma_addr_t              rx_buf_dma_phys;
+        dma_addr_t              tx_buf_dma_phys;
+        unsigned int            uart_base;
+        /*
+         * Buffer for rx dma.It is not required for tx because the buffer
+         * comes from port structure.
+         */
+        unsigned char           *rx_buf;
+        unsigned int            prev_rx_dma_pos;
+        int                     tx_buf_size;
+        int                     tx_dma_used;
+        int                     rx_dma_used;
+        spinlock_t              tx_lock;
+        spinlock_t              rx_lock;
+        /* timer to poll activity on rx dma */
+        struct timer_list       rx_timer;
+        int                     rx_buf_size;
+        int                     rx_timeout;
+};
+
+struct uart_omap_port {
+        struct uart_port        port;
+        struct uart_omap_dma    uart_dma;
+        struct platform_device  *pdev;
+
+        unsigned char           ier;
+        unsigned char           lcr;
+        unsigned char           mcr;
+        unsigned char           fcr;
+        unsigned char           efr;
+
+        int                     use_dma;
+        /*
+         * Some bits in registers are cleared on a read, so they must
+         * be saved whenever the register is read but the bits will not
+         * be immediately processed.
+         */
+        unsigned int            lsr_break_flag;
+        unsigned char           msr_saved_flags;
+        char                    name[20];
+        unsigned long           port_activity;
+};
+
+#endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 7055672a8c6..92df9e27cc5 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -40,7 +40,7 @@
 #define OMAP24XX_IC_BASE        (L4_24XX_BASE + 0xfe000)
 #define OMAP24XX_IVA_INTC_BASE  0x40000000
 
-#define OMAP2420_CTRL_BASE      L4_24XX_BASE
+#define OMAP242X_CTRL_BASE      L4_24XX_BASE
 #define OMAP2420_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
 #define OMAP2420_PRCM_BASE      (L4_24XX_BASE + 0x8000)
 #define OMAP2420_CM_BASE        (L4_24XX_BASE + 0x8000)
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
new file mode 100644
index 00000000000..2b1d9bc1eeb
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -0,0 +1,14 @@
+#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
+#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+struct omap4_keypad_platform_data {
+        const struct matrix_keymap_data *keymap_data;
+
+        u8 rows;
+        u8 cols;
+};
+
+extern int omap4_keyboard_init(struct omap4_keypad_platform_data *);
+#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 25cd9ac3b09..28e2d1a7843 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,6 +36,8 @@
 
 #include <plat/omap_hwmod.h>
 
+extern struct device omap_device_parent;
+
 /* omap_device._state values */
 #define OMAP_DEVICE_STATE_UNKNOWN       0
 #define OMAP_DEVICE_STATE_ENABLED       1
@@ -62,7 +64,6 @@
  *
  */
 struct omap_device {
-        u32                             magic;
         struct platform_device          pdev;
         struct omap_hwmod               **hwmods;
         struct omap_device_pm_latency   *pm_lats;
@@ -82,7 +83,6 @@ int omap_device_shutdown(struct platform_device *pdev);
 
 /* Core code interface */
 
-bool omap_device_is_valid(struct omap_device *od);
 int omap_device_count_resources(struct omap_device *od);
 int omap_device_fill_resources(struct omap_device *od, struct resource *res);
 
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index a4e508dfaba..7eaa8edf3b1 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -14,19 +14,16 @@
  *
  * These headers and macros are used to define OMAP on-chip module
  * data and their integration with other OMAP modules and Linux.
- *
- * References:
- * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
- * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
- * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
- * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
- * - Open Core Protocol Specification 2.2
+ * Copious documentation and references can also be found in the
+ * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
+ * writing).
  *
  * To do:
  * - add interconnect error log structures
  * - add pinmuxing
  * - init_conn_id_bit (CONNID_BIT_VECTOR)
  * - implement default hwmod SMS/SDRC flags?
+ * - remove unused fields
  *
  */
 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
@@ -35,6 +32,7 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
+#include <linux/mutex.h>
 #include <plat/cpu.h>
 
 struct omap_device;
@@ -96,7 +94,7 @@ struct omap_hwmod_irq_info {
 /**
  * struct omap_hwmod_dma_info - DMA channels used by the hwmod
  * @name: name of the DMA channel (module local name)
- * @dma_ch: DMA channel ID
+ * @dma_req: DMA request ID
  *
  * @name should be something short, e.g., "tx" or "rx".  It is for use
  * by platform_get_resource_byname().  It is defined locally to the
@@ -104,7 +102,20 @@ struct omap_hwmod_irq_info {
  */
 struct omap_hwmod_dma_info {
         const char      *name;
-        u16             dma_ch;
+        u16             dma_req;
+};
+
+/**
+ * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
+ * @name: name of the reset line (module local name)
+ * @rst_shift: Offset of the reset bit
+ *
+ * @name should be something short, e.g., "cpu0" or "rst". It is defined
+ * locally to the hwmod.
+ */
+struct omap_hwmod_rst_info {
+        const char      *name;
+        u8              rst_shift;
 };
 
 /**
@@ -237,8 +248,9 @@ struct omap_hwmod_ocp_if {
 #define SYSC_HAS_CLOCKACTIVITY  (1 << 4)
 #define SYSC_HAS_SIDLEMODE      (1 << 5)
 #define SYSC_HAS_MIDLEMODE      (1 << 6)
-#define SYSS_MISSING            (1 << 7)
+#define SYSS_HAS_RESET_STATUS   (1 << 7)
 #define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
+#define SYSC_HAS_RESET_STATUS   (1 << 9)
 
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH      0x0
@@ -327,10 +339,12 @@ struct omap_hwmod_omap2_prcm {
 /**
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
  * @clkctrl_reg: PRCM address of the clock control register
+ * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM
  * @submodule_wkdep_bit: bit shift of the WKDEP range
  */
 struct omap_hwmod_omap4_prcm {
         void __iomem    *clkctrl_reg;
+        void __iomem    *rstctrl_reg;
         u8              submodule_wkdep_bit;
 };
 
@@ -352,6 +366,11 @@ struct omap_hwmod_omap4_prcm {
  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
  * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
  *     only for few initiator modules on OMAP2 & 3.
+ * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
+ *     This is needed for devices like DSS that require optional clocks enabled
+ *     in order to complete the reset. Optional clocks will be disabled
+ *     again after the reset.
+ * HWMOD_16BIT_REG: Module has 16bit registers
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -360,6 +379,8 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
 #define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
 #define HWMOD_NO_IDLEST                         (1 << 6)
+#define HWMOD_CONTROL_OPT_CLKS_IN_RESET         (1 << 7)
+#define HWMOD_16BIT_REG                         (1 << 8)
 
 /*
  * omap_hwmod._int_flags definitions
@@ -410,7 +431,7 @@ struct omap_hwmod_class {
  * @class: struct omap_hwmod_class * to the class of this hwmod
  * @od: struct omap_device currently associated with this hwmod (internal use)
  * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
- * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
+ * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
  * @prcm: PRCM data pertaining to this hwmod
  * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
@@ -424,7 +445,7 @@ struct omap_hwmod_class {
  * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
  * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
  * @mpu_irqs_cnt: number of @mpu_irqs
- * @sdma_chs_cnt: number of @sdma_chs
+ * @sdma_reqs_cnt: number of @sdma_reqs
  * @opt_clks_cnt: number of @opt_clks
  * @master_cnt: number of @master entries
  * @slaves_cnt: number of @slave entries
@@ -433,6 +454,7 @@ struct omap_hwmod_class {
  * @_state: internal-use hwmod state
  * @flags: hwmod flags (documented below)
  * @omap_chip: OMAP chips this hwmod is present on
+ * @_mutex: mutex serializing operations on this hwmod
  * @node: list node for hwmod list (internal use)
  *
  * @main_clk refers to this module's "main clock," which for our
@@ -448,7 +470,8 @@ struct omap_hwmod {
         struct omap_hwmod_class         *class;
         struct omap_device              *od;
         struct omap_hwmod_irq_info      *mpu_irqs;
-        struct omap_hwmod_dma_info      *sdma_chs;
+        struct omap_hwmod_dma_info      *sdma_reqs;
+        struct omap_hwmod_rst_info      *rst_lines;
         union {
                 struct omap_hwmod_omap2_prcm omap2;
                 struct omap_hwmod_omap4_prcm omap4;
@@ -461,6 +484,7 @@ struct omap_hwmod {
         void                            *dev_attr;
         u32                             _sysc_cache;
         void __iomem                    *_mpu_rt_va;
+        struct mutex                    _mutex;
         struct list_head                node;
         u16                             flags;
         u8                              _mpu_port_index;
@@ -468,7 +492,8 @@ struct omap_hwmod {
         u8                              msuspendmux_shift;
         u8                              response_lat;
         u8                              mpu_irqs_cnt;
-        u8                              sdma_chs_cnt;
+        u8                              sdma_reqs_cnt;
+        u8                              rst_lines_cnt;
         u8                              opt_clks_cnt;
         u8                              masters_cnt;
         u8                              slaves_cnt;
@@ -492,6 +517,10 @@ int omap_hwmod_idle(struct omap_hwmod *oh);
 int _omap_hwmod_idle(struct omap_hwmod *oh);
 int omap_hwmod_shutdown(struct omap_hwmod *oh);
 
+int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
+int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
+int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
+
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 
@@ -500,8 +529,8 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
 
-void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
-u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
+void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
+u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
 
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
@@ -534,5 +563,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
 extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
+extern int omap44xx_hwmod_init(void);
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fb6ec74fe39..9ca420dcd2f 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -32,6 +32,7 @@
 
 /* Powerdomain allowable state bitfields */
 #define PWRSTS_ON               (1 << PWRDM_POWER_ON)
+#define PWRSTS_OFF              (1 << PWRDM_POWER_OFF)
 #define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_ON))
 
@@ -161,5 +162,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm);
 int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
 int pwrdm_pre_transition(void);
 int pwrdm_post_transition(void);
+int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 9fbd91419cd..ab77442e42a 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -38,6 +38,8 @@ u32 prm_read_mod_reg(s16 module, u16 idx);
 void prm_write_mod_reg(u32 val, s16 module, u16 idx);
 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
+u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
 u32 cm_read_mod_reg(s16 module, u16 idx);
 void cm_write_mod_reg(u32 val, s16 module, u16 idx);
 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 7b76f50564b..efd87c8dda6 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -147,6 +147,7 @@ struct memory_timings {
 };
 
 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
+struct omap_sdrc_params *rx51_get_sdram_timings(void);
 
 u32 omap2xxx_sdrc_dll_is_unlocked(void);
 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c5a25..ecd6a488c49 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_mpidr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
         gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()                 \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
-
 #endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 16a1b458d53..5905100b29a 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,7 +11,6 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
 
-extern int __init omap_sram_init(void);
 extern void * omap_sram_push(void * start, unsigned long size);
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
 
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ddf723be48d..9036e374e0a 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -139,10 +139,14 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_OMAP2(1, omap3evm);
                 DEBUG_LL_OMAP3(1, omap_3430sdp);
                 DEBUG_LL_OMAP3(1, omap_3630sdp);
+                DEBUG_LL_OMAP3(1, omap3530_lv_som);
+                DEBUG_LL_OMAP3(1, omap3_torpedo);
 
                 /* omap3 based boards using UART3 */
                 DEBUG_LL_OMAP3(3, cm_t35);
+                DEBUG_LL_OMAP3(3, cm_t3517);
                 DEBUG_LL_OMAP3(3, igep0020);
+                DEBUG_LL_OMAP3(3, igep0030);
                 DEBUG_LL_OMAP3(3, nokia_rx51);
                 DEBUG_LL_OMAP3(3, omap3517evm);
                 DEBUG_LL_OMAP3(3, omap3_beagle);
@@ -153,6 +157,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 
                 /* omap4 based boards using UART3 */
                 DEBUG_LL_OMAP4(3, omap_4430sdp);
+                DEBUG_LL_OMAP4(3, omap4_panda);
 
                 /* zoom2/3 external uart */
                 DEBUG_LL_ZOOM(omap_zoom2);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 2a9427c8cc4..59c7fe731f2 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata)
 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
 void omap2_usbfs_init(struct omap_usb_config *pdata);
 #else
-static inline omap2_usbfs_init(struct omap_usb_config *pdata)
+static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
 {
 }
 #endif
@@ -218,6 +218,27 @@ static inline omap2_usbfs_init(struct omap_usb_config *pdata)
 #       define  USBT2TLL5PI             (1 << 17)
 #       define  USB0PUENACTLOI          (1 << 16)
 #       define  USBSTANDBYCTRL          (1 << 15)
+/* AM35x */
+/* USB 2.0 PHY Control */
+#define CONF2_PHY_GPIOMODE      (1 << 23)
+#define CONF2_OTGMODE           (3 << 14)
+#define CONF2_NO_OVERRIDE       (0 << 14)
+#define CONF2_FORCE_HOST        (1 << 14)
+#define CONF2_FORCE_DEVICE      (2 << 14)
+#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+#define CONF2_SESENDEN          (1 << 13)
+#define CONF2_VBDTCTEN          (1 << 12)
+#define CONF2_REFFREQ_24MHZ     (2 << 8)
+#define CONF2_REFFREQ_26MHZ     (7 << 8)
+#define CONF2_REFFREQ_13MHZ     (6 << 8)
+#define CONF2_REFFREQ           (0xf << 8)
+#define CONF2_PHYCLKGD          (1 << 7)
+#define CONF2_VBUSSENSE         (1 << 6)
+#define CONF2_PHY_PLLON         (1 << 5)
+#define CONF2_RESET             (1 << 4)
+#define CONF2_PHYPWRDN          (1 << 3)
+#define CONF2_OTGPWRDN          (1 << 2)
+#define CONF2_DATPOL            (1 << 1)
 
 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c
index e6c0d536899..f07cf2f08e0 100644
--- a/arch/arm/plat-omap/iommu-debug.c
+++ b/arch/arm/plat-omap/iommu-debug.c
@@ -328,12 +328,14 @@ static int debug_open_generic(struct inode *inode, struct file *file)
                 .open = debug_open_generic,                             \
                 .read = debug_read_##name,                              \
                 .write = debug_write_##name,                            \
+                .llseek = generic_file_llseek,                          \
         };
 
 #define DEBUG_FOPS_RO(name)                                             \
         static const struct file_operations debug_##name##_fops = {     \
                 .open = debug_open_generic,                             \
                 .read = debug_read_##name,                              \
+                .llseek = generic_file_llseek,                          \
         };
 
 DEBUG_FOPS_RO(ver);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index a202a2ce6e3..6cd151b31bc 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -320,6 +320,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
                 if ((start <= da) && (da < start + bytes)) {
                         dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
                                 __func__, start, da, bytes);
+                        iotlb_load_cr(obj, &cr);
                         iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
                 }
         }
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e31496e35b0..eac4b978e9f 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -33,7 +33,7 @@
 struct omap_mcbsp **mcbsp_ptr;
 int omap_mcbsp_count, omap_mcbsp_cache_size;
 
-void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
+static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
         if (cpu_class_is_omap1()) {
                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
@@ -47,7 +47,7 @@ void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
         }
 }
 
-int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
+static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 {
         if (cpu_class_is_omap1()) {
                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
@@ -62,12 +62,12 @@ int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 }
 
 #ifdef CONFIG_ARCH_OMAP3
-void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
+static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
 }
 
-int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
+static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
 {
         return __raw_readl(mcbsp->st_data->io_base_st + reg);
 }
@@ -80,9 +80,6 @@ int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
 #define MCBSP_READ_CACHE(mcbsp, reg) \
                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
 
-#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
-#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
-
 #define MCBSP_ST_READ(mcbsp, reg) \
                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
@@ -156,7 +153,7 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
                 /* Writing zero to RSYNC_ERR clears the IRQ */
                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
         } else {
-                complete(&mcbsp_rx->tx_irq_completion);
+                complete(&mcbsp_rx->rx_irq_completion);
         }
 
         return IRQ_HANDLED;
@@ -878,7 +875,7 @@ EXPORT_SYMBOL(omap_mcbsp_free);
 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 {
         struct omap_mcbsp *mcbsp;
-        int idle;
+        int enable_srg = 0;
         u16 w;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -893,10 +890,13 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 
-        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
-                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
+        /* Only enable SRG, if McBSP is master */
+        w = MCBSP_READ_CACHE(mcbsp, PCR0);
+        if (w & (FSXM | FSRM | CLKXM | CLKRM))
+                enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                                MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 
-        if (idle) {
+        if (enable_srg) {
                 /* Start the sample generator */
                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
@@ -919,7 +919,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
          */
         udelay(500);
 
-        if (idle) {
+        if (enable_srg) {
                 /* Start frame sync */
                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
@@ -1645,7 +1645,7 @@ static const struct attribute_group sidetone_attr_group = {
         .attrs = (struct attribute **)sidetone_attrs,
 };
 
-int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
 {
         struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
         struct omap_mcbsp_st_data *st_data;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index d2b160942cc..abe933cd8f0 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -82,6 +82,7 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 
 #include <plat/omap_device.h>
 #include <plat/omap_hwmod.h>
@@ -90,12 +91,6 @@
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
 
-/*
- * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device
- * obtained via container_of() is in fact a struct omap_device
- */
-#define OMAP_DEVICE_MAGIC                0xf00dcafe
-
 /* Private functions */
 
 /**
@@ -243,6 +238,44 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
         return container_of(pdev, struct omap_device, pdev);
 }
 
+/**
+ * _add_optional_clock_alias - Add clock alias for hwmod optional clocks
+ * @od: struct omap_device *od
+ *
+ * For every optional clock present per hwmod per omap_device, this function
+ * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
+ * if an entry is already present in it with the form <dev-id=NULL, con-id=role>
+ *
+ * The function is called from inside omap_device_build_ss(), after
+ * omap_device_register.
+ *
+ * This allows drivers to get a pointer to its optional clocks based on its role
+ * by calling clk_get(<dev*>, <role>).
+ *
+ * No return value.
+ */
+static void _add_optional_clock_alias(struct omap_device *od,
+                                      struct omap_hwmod *oh)
+{
+        int i;
+
+        for (i = 0; i < oh->opt_clks_cnt; i++) {
+                struct omap_hwmod_opt_clk *oc;
+                int r;
+
+                oc = &oh->opt_clks[i];
+
+                if (!oc->_clk)
+                        continue;
+
+                r = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
+                                  (char *)oc->clk, &od->pdev.dev);
+                if (r)
+                        pr_err("omap_device: %s: clk_add_alias for %s failed\n",
+                               dev_name(&od->pdev.dev), oc->role);
+        }
+}
+
 
 /* Public functions for use by core code */
 
@@ -257,12 +290,11 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
  */
 int omap_device_count_resources(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
         int c = 0;
         int i;
 
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
-                c += omap_hwmod_count_resources(oh);
+        for (i = 0; i < od->hwmods_cnt; i++)
+                c += omap_hwmod_count_resources(od->hwmods[i]);
 
         pr_debug("omap_device: %s: counted %d total resources across %d "
                  "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
@@ -289,12 +321,11 @@ int omap_device_count_resources(struct omap_device *od)
  */
 int omap_device_fill_resources(struct omap_device *od, struct resource *res)
 {
-        struct omap_hwmod *oh;
         int c = 0;
         int i, r;
 
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) {
-                r = omap_hwmod_fill_resources(oh, res);
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                r = omap_hwmod_fill_resources(od->hwmods[i], res);
                 res += r;
                 c += r;
         }
@@ -414,15 +445,15 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
         od->pm_lats = pm_lats;
         od->pm_lats_cnt = pm_lats_cnt;
 
-        od->magic = OMAP_DEVICE_MAGIC;
-
         if (is_early_device)
                 ret = omap_early_device_register(od);
         else
                 ret = omap_device_register(od);
 
-        for (i = 0; i < oh_cnt; i++)
+        for (i = 0; i < oh_cnt; i++) {
                 hwmods[i]->od = od;
+                _add_optional_clock_alias(od, hwmods[i]);
+        }
 
         if (ret)
                 goto odbs_exit4;
@@ -473,6 +504,7 @@ int omap_device_register(struct omap_device *od)
 {
         pr_debug("omap_device: %s: registering\n", od->pdev.name);
 
+        od->pdev.dev.parent = &omap_device_parent;
         return platform_device_register(&od->pdev);
 }
 
@@ -566,7 +598,6 @@ int omap_device_shutdown(struct platform_device *pdev)
 {
         int ret, i;
         struct omap_device *od;
-        struct omap_hwmod *oh;
 
         od = _find_by_pdev(pdev);
 
@@ -579,8 +610,8 @@ int omap_device_shutdown(struct platform_device *pdev)
 
         ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
 
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
-                omap_hwmod_shutdown(oh);
+        for (i = 0; i < od->hwmods_cnt; i++)
+                omap_hwmod_shutdown(od->hwmods[i]);
 
         od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
 
@@ -627,18 +658,6 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
 }
 
 /**
- * omap_device_is_valid - Check if pointer is a valid omap_device
- * @od: struct omap_device *
- *
- * Return whether struct omap_device pointer @od points to a valid
- * omap_device.
- */
-bool omap_device_is_valid(struct omap_device *od)
-{
-        return (od && od->magic == OMAP_DEVICE_MAGIC);
-}
-
-/**
  * omap_device_get_pwrdm - return the powerdomain * associated with @od
  * @od: struct omap_device *
  *
@@ -692,11 +711,10 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od)
  */
 int omap_device_enable_hwmods(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
         int i;
 
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
-                omap_hwmod_enable(oh);
+        for (i = 0; i < od->hwmods_cnt; i++)
+                omap_hwmod_enable(od->hwmods[i]);
 
         /* XXX pass along return value here? */
         return 0;
@@ -710,11 +728,10 @@ int omap_device_enable_hwmods(struct omap_device *od)
  */
 int omap_device_idle_hwmods(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
         int i;
 
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
-                omap_hwmod_idle(oh);
+        for (i = 0; i < od->hwmods_cnt; i++)
+                omap_hwmod_idle(od->hwmods[i]);
 
         /* XXX pass along return value here? */
         return 0;
@@ -729,11 +746,10 @@ int omap_device_idle_hwmods(struct omap_device *od)
  */
 int omap_device_disable_clocks(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
         int i;
 
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
-                omap_hwmod_disable_clocks(oh);
+        for (i = 0; i < od->hwmods_cnt; i++)
+                omap_hwmod_disable_clocks(od->hwmods[i]);
 
         /* XXX pass along return value here? */
         return 0;
@@ -748,12 +764,22 @@ int omap_device_disable_clocks(struct omap_device *od)
  */
 int omap_device_enable_clocks(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
         int i;
 
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
-                omap_hwmod_enable_clocks(oh);
+        for (i = 0; i < od->hwmods_cnt; i++)
+                omap_hwmod_enable_clocks(od->hwmods[i]);
 
         /* XXX pass along return value here? */
         return 0;
 }
+
+struct device omap_device_parent = {
+        .init_name      = "omap",
+        .parent         = &platform_bus,
+};
+
+static int __init omap_device_init(void)
+{
+        return device_register(&omap_device_parent);
+}
+core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 10b3b4c6337..e2c8eebe6b3 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/omapfb.h>
 
 #include <asm/tlb.h>
 #include <asm/cacheflush.h>
@@ -30,8 +31,8 @@
 #include <plat/cpu.h>
 #include <plat/vram.h>
 
-#include <plat/control.h>
-
+#include "sram.h"
+#include "fb.h"
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 # include "../mach-omap2/prm.h"
 # include "../mach-omap2/cm.h"
@@ -53,7 +54,7 @@
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
 #else
 #define SRAM_BOOTLOADER_SZ      0x80
@@ -68,7 +69,6 @@
 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
-#define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
 
 #define GP_DEVICE               0x300
 
@@ -79,12 +79,6 @@ static unsigned long omap_sram_base;
 static unsigned long omap_sram_size;
 static unsigned long omap_sram_ceil;
 
-extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
-                                         unsigned long sram_vstart,
-                                         unsigned long sram_size,
-                                         unsigned long pstart_avail,
-                                         unsigned long size_avail);
-
 /*
  * Depending on the target RAMFS firewall setup, the public usable amount of
  * SRAM varies.  The default accessible size for all device types is 2k. A GP
@@ -93,16 +87,7 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  */
 static int is_sram_locked(void)
 {
-        int type = 0;
-
-        if (cpu_is_omap44xx())
-                /* Not yet supported */
-                return 0;
-
-        if (cpu_is_omap242x())
-                type = omap_rev() & OMAP2_DEVICETYPE_MASK;
-
-        if (type == GP_DEVICE) {
+        if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
                 /* RAMFW: R/W access to all initiators for all qualifier sets */
                 if (cpu_is_omap242x()) {
                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
@@ -127,7 +112,7 @@ static int is_sram_locked(void)
  * to secure SRAM will hang the system. Also the SRAM is not
  * yet mapped at this point.
  */
-void __init omap_detect_sram(void)
+static void __init omap_detect_sram(void)
 {
         unsigned long reserved;
 
@@ -213,7 +198,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = {
 /*
  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
  */
-void __init omap_map_sram(void)
+static void __init omap_map_sram(void)
 {
         unsigned long base;
 
@@ -330,7 +315,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP2420
-int __init omap242x_sram_init(void)
+static int __init omap242x_sram_init(void)
 {
         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
                                         omap242x_sram_ddr_init_sz);
@@ -351,7 +336,7 @@ static inline int omap242x_sram_init(void)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP2430
-int __init omap243x_sram_init(void)
+static int __init omap243x_sram_init(void)
 {
         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
                                         omap243x_sram_ddr_init_sz);
@@ -407,7 +392,7 @@ void omap3_sram_restore_context(void)
 }
 #endif /* CONFIG_PM */
 
-int __init omap34xx_sram_init(void)
+static int __init omap34xx_sram_init(void)
 {
         _omap3_sram_configure_core_dpll =
                 omap_sram_push(omap3_sram_configure_core_dpll,
@@ -423,7 +408,7 @@ static inline int omap34xx_sram_init(void)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-int __init omap44xx_sram_init(void)
+static int __init omap44xx_sram_init(void)
 {
         printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
 
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
new file mode 100644
index 00000000000..29b43ef97f2
--- /dev/null
+++ b/arch/arm/plat-omap/sram.h
@@ -0,0 +1,6 @@
+#ifndef __PLAT_OMAP_SRAM_H__
+#define __PLAT_OMAP_SRAM_H__
+
+extern int __init omap_sram_init(void);
+
+#endif /* __PLAT_OMAP_SRAM_H__ */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index 7b4eadc6df3..abcc36eb124 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -25,6 +25,13 @@
  *
  * 4. matrix key and direct key will use the same debounce_interval by
  *    default, which should be sufficient in most cases
+ *
+ * pxa168 keypad platform specific parameter
+ *
+ * NOTE:
+ * clear_wakeup_event callback is a workaround required to clear the
+ * keypad interrupt. The keypad wake must be cleared in addition to
+ * reading the MI/DI bits in the KPC register.
  */
 struct pxa27x_keypad_platform_data {
 
@@ -52,6 +59,9 @@ struct pxa27x_keypad_platform_data {
 
         /* key debounce interval */
         unsigned int    debounce_interval;
+
+        /* clear wakeup event requirement for pxa168 */
+        void            (*clear_wakeup_event)(void);
 };
 
 extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 452e18438b4..2f91057a0c0 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -247,7 +247,7 @@ static struct resource s3c_iis_resource[] = {
 static u64 s3c_device_iis_dmamask = 0xffffffffUL;
 
 struct platform_device s3c_device_iis = {
-        .name             = "s3c2410-iis",
+        .name             = "s3c24xx-iis",
         .id               = -1,
         .num_resources    = ARRAY_SIZE(s3c_iis_resource),
         .resource         = s3c_iis_resource,
@@ -259,6 +259,21 @@ struct platform_device s3c_device_iis = {
 
 EXPORT_SYMBOL(s3c_device_iis);
 
+/* ASoC PCM DMA */
+
+static u64 s3c_device_audio_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_pcm = {
+        .name             = "s3c24xx-pcm-audio",
+        .id               = -1,
+        .dev              = {
+                .dma_mask = &s3c_device_audio_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+EXPORT_SYMBOL(s3c_device_pcm);
+
 /* RTC */
 
 static struct resource s3c_rtc_resource[] = {
@@ -481,19 +496,30 @@ static struct resource s3c_ac97_resource[] = {
         },
 };
 
-static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
-
 struct platform_device s3c_device_ac97 = {
         .name             = "s3c-ac97",
         .id               = -1,
         .num_resources    = ARRAY_SIZE(s3c_ac97_resource),
         .resource         = s3c_ac97_resource,
         .dev              = {
-                .dma_mask = &s3c_device_ac97_dmamask,
+                .dma_mask = &s3c_device_audio_dmamask,
                 .coherent_dma_mask = 0xffffffffUL
         }
 };
 
 EXPORT_SYMBOL(s3c_device_ac97);
 
+/* ASoC I2S */
+
+struct platform_device s3c2412_device_iis = {
+        .name             = "s3c2412-iis",
+        .id               = -1,
+        .dev              = {
+                .dma_mask = &s3c_device_audio_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+EXPORT_SYMBOL(s3c2412_device_iis);
+
 #endif // CONFIG_CPU_S32440
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index c6a855db2fb..25960966af7 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
+        depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
         default y
         select ARM_VIC if !ARCH_S5PV310
         select ARM_GIC if ARCH_S5PV310
@@ -30,7 +30,7 @@ config S5P_EXT_INT
         bool
         help
           Use the external interrupts (other than GPIO interrupts.)
-          Note: Do not choose this for S5P6440.
+          Note: Do not choose this for S5P6440 and S5P6450.
 
 config S5P_DEV_FIMC0
         bool
@@ -46,3 +46,8 @@ config S5P_DEV_FIMC2
         bool
         help
           Compile in platform device definitions for FIMC controller 2
+
+config S5P_DEV_ONENAND
+        bool
+        help
+          Compile in platform device definition for OneNAND controller
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index b2e02967395..f3e917e27da 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 obj-$(CONFIG_S5P_DEV_FIMC0)     += dev-fimc0.o
 obj-$(CONFIG_S5P_DEV_FIMC1)     += dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
+obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index b5e255265f2..8aaf4e6b60c 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -74,6 +74,13 @@ struct clk clk_fout_epll = {
         .ctrlbit        = (1 << 31),
 };
 
+/* DPLL clock output */
+struct clk clk_fout_dpll = {
+        .name           = "fout_dpll",
+        .id             = -1,
+        .ctrlbit        = (1 << 31),
+};
+
 /* VPLL clock output */
 struct clk clk_fout_vpll = {
         .name           = "fout_vpll",
@@ -122,6 +129,17 @@ struct clksrc_sources clk_src_epll = {
         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
 };
 
+/* Possible clock sources for DPLL Mux */
+static struct clk *clk_src_dpll_list[] = {
+        [0] = &clk_fin_dpll,
+        [1] = &clk_fout_dpll,
+};
+
+struct clksrc_sources clk_src_dpll = {
+        .sources        = clk_src_dpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_dpll_list),
+};
+
 struct clk clk_vpll = {
         .name           = "vpll",
         .id             = -1,
@@ -145,6 +163,7 @@ static struct clk *s5p_clks[] __initdata = {
         &clk_fout_apll,
         &clk_fout_mpll,
         &clk_fout_epll,
+        &clk_fout_dpll,
         &clk_fout_vpll,
         &clk_arm,
         &clk_vpll,
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index b07a078fd28..74f7f5a5446 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -19,6 +19,7 @@
 #include <plat/cpu.h>
 #include <plat/s5p6440.h>
 #include <plat/s5p6442.h>
+#include <plat/s5p6450.h>
 #include <plat/s5pc100.h>
 #include <plat/s5pv210.h>
 #include <plat/s5pv310.h>
@@ -27,6 +28,7 @@
 
 static const char name_s5p6440[] = "S5P6440";
 static const char name_s5p6442[] = "S5P6442";
+static const char name_s5p6450[] = "S5P6450";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
 static const char name_s5pv310[] = "S5PV310";
@@ -38,7 +40,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .map_io         = s5p6440_map_io,
                 .init_clocks    = s5p6440_init_clocks,
                 .init_uarts     = s5p6440_init_uarts,
-                .init           = s5p6440_init,
+                .init           = s5p64x0_init,
                 .name           = name_s5p6440,
         }, {
                 .idcode         = 0x36442000,
@@ -49,6 +51,14 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = s5p6442_init,
                 .name           = name_s5p6442,
         }, {
+                .idcode         = 0x36450000,
+                .idmask         = 0xffffff00,
+                .map_io         = s5p6450_map_io,
+                .init_clocks    = s5p6450_init_clocks,
+                .init_uarts     = s5p6450_init_uarts,
+                .init           = s5p64x0_init,
+                .name           = name_s5p6450,
+        }, {
                 .idcode         = 0x43100000,
                 .idmask         = 0xfffff000,
                 .map_io         = s5pc100_map_io,
@@ -89,33 +99,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
                 .length         = SZ_64K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-#ifdef CONFIG_ARM_VIC
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5P_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5P_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-#endif
-        }, {
                 .virtual        = (unsigned long)S3C_VA_TIMER,
                 .pfn            = __phys_to_pfn(S5P_PA_TIMER),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5P_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
                 .pfn            = __phys_to_pfn(S3C_PA_WDT),
                 .length         = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/plat-s5p/dev-onenand.c
index f8ede33ee82..6db926202ca 100644
--- a/arch/arm/mach-s5pv210/dev-onenand.c
+++ b/arch/arm/plat-s5p/dev-onenand.c
@@ -1,10 +1,12 @@
-/*
- * linux/arch/arm/mach-s5pv210/dev-onenand.c
+/* linux/arch/arm/plat-s5p/dev-onenand.c
+ *
+ * Copyright 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  *  Copyright (c) 2008-2010 Samsung Electronics
  *  Kyungmin Park <kyungmin.park@samsung.com>
  *
- * S5PC110 series device definition for OneNAND devices
+ * S5P series device definition for OneNAND devices
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,15 +21,15 @@
 #include <mach/irqs.h>
 #include <mach/map.h>
 
-static struct resource s5pc110_onenand_resources[] = {
+static struct resource s5p_onenand_resources[] = {
         [0] = {
-                .start  = S5PC110_PA_ONENAND,
-                .end    = S5PC110_PA_ONENAND + SZ_128K - 1,
+                .start  = S5P_PA_ONENAND,
+                .end    = S5P_PA_ONENAND + SZ_128K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = S5PC110_PA_ONENAND_DMA,
-                .end    = S5PC110_PA_ONENAND_DMA + SZ_8K - 1,
+                .start  = S5P_PA_ONENAND_DMA,
+                .end    = S5P_PA_ONENAND_DMA + SZ_8K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
@@ -37,19 +39,19 @@ static struct resource s5pc110_onenand_resources[] = {
         },
 };
 
-struct platform_device s5pc110_device_onenand = {
+struct platform_device s5p_device_onenand = {
         .name           = "s5pc110-onenand",
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5pc110_onenand_resources),
-        .resource       = s5pc110_onenand_resources,
+        .num_resources  = ARRAY_SIZE(s5p_onenand_resources),
+        .resource       = s5p_onenand_resources,
 };
 
-void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata)
+void s5p_onenand_set_platdata(struct onenand_platform_data *pdata)
 {
         struct onenand_platform_data *pd;
 
         pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
         if (!pd)
                 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
-        s5pc110_device_onenand.dev.platform_data = pd;
+        s5p_device_onenand.dev.platform_data = pd;
 }
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index a89331ef4ae..6a734288617 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -119,6 +119,56 @@ static struct resource s5p_uart3_resource[] = {
 #endif
 };
 
+static struct resource s5p_uart4_resource[] = {
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
+        [0] = {
+                .start  = S5P_PA_UART4,
+                .end    = S5P_PA_UART4 + S5P_SZ_UART,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX4,
+                .end    = IRQ_S5P_UART_RX4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX4,
+                .end    = IRQ_S5P_UART_TX4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR4,
+                .end    = IRQ_S5P_UART_ERR4,
+                .flags  = IORESOURCE_IRQ,
+        },
+#endif
+};
+
+static struct resource s5p_uart5_resource[] = {
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
+        [0] = {
+                .start  = S5P_PA_UART5,
+                .end    = S5P_PA_UART5 + S5P_SZ_UART,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX5,
+                .end    = IRQ_S5P_UART_RX5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX5,
+                .end    = IRQ_S5P_UART_TX5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR5,
+                .end    = IRQ_S5P_UART_ERR5,
+                .flags  = IORESOURCE_IRQ,
+        },
+#endif
+};
+
 struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
         [0] = {
                 .resources      = s5p_uart0_resource,
@@ -136,4 +186,12 @@ struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
                 .resources      = s5p_uart3_resource,
                 .nr_resources   = ARRAY_SIZE(s5p_uart3_resource),
         },
+        [4] = {
+                .resources      = s5p_uart4_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart4_resource),
+        },
+        [5] = {
+                .resources      = s5p_uart5_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart5_resource),
+        },
 };
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index 4e8fe08cb70..bf28fadee7a 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -47,6 +47,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
 }
 
 #define PLL46XX_KDIV_MASK       (0xFFFF)
+#define PLL4650C_KDIV_MASK      (0xFFF)
 #define PLL46XX_MDIV_MASK       (0x1FF)
 #define PLL46XX_PDIV_MASK       (0x3F)
 #define PLL46XX_SDIV_MASK       (0x7)
@@ -57,6 +58,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
 enum pll46xx_type_t {
         pll_4600,
         pll_4650,
+        pll_4650c,
 };
 
 static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
@@ -72,6 +74,11 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
         sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
         kdiv = pll_con1 & PLL46XX_KDIV_MASK;
 
+        if (pll_type == pll_4650c)
+                kdiv = pll_con1 & PLL4650C_KDIV_MASK;
+        else
+                kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
         tmp = baseclk;
 
         if (pll_type == pll_4600) {
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 09418b1101f..17036c89840 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
  *
- * Copyright 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  * Header file for s5p clock support
  *
@@ -20,6 +20,7 @@
 #define clk_fin_apll clk_ext_xtal_mux
 #define clk_fin_mpll clk_ext_xtal_mux
 #define clk_fin_epll clk_ext_xtal_mux
+#define clk_fin_dpll clk_ext_xtal_mux
 #define clk_fin_vpll clk_ext_xtal_mux
 #define clk_fin_hpll clk_ext_xtal_mux
 
@@ -30,6 +31,7 @@ extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
 extern struct clk clk_fout_mpll;
 extern struct clk clk_fout_epll;
+extern struct clk clk_fout_dpll;
 extern struct clk clk_fout_vpll;
 extern struct clk clk_arm;
 extern struct clk clk_vpll;
@@ -37,8 +39,8 @@ extern struct clk clk_vpll;
 extern struct clksrc_sources clk_src_apll;
 extern struct clksrc_sources clk_src_mpll;
 extern struct clksrc_sources clk_src_epll;
+extern struct clksrc_sources clk_src_dpll;
 
-extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable);
 extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
 
 #endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h
index a4cd75afeb3..528585d2caf 100644
--- a/arch/arm/plat-s5p/include/plat/s5p6440.h
+++ b/arch/arm/plat-s5p/include/plat/s5p6440.h
@@ -12,24 +12,23 @@
 
  /* Common init code for S5P6440 related SoCs */
 
-extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s5p6440_register_clocks(void);
 extern void s5p6440_setup_clocks(void);
 
 #ifdef CONFIG_CPU_S5P6440
 
-extern  int s5p6440_init(void);
+extern  int s5p64x0_init(void);
 extern void s5p6440_init_irq(void);
 extern void s5p6440_map_io(void);
 extern void s5p6440_init_clocks(int xtal);
 
-#define s5p6440_init_uarts s5p6440_common_init_uarts
+extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
 #else
 #define s5p6440_init_clocks NULL
 #define s5p6440_init_uarts NULL
 #define s5p6440_map_io NULL
-#define s5p6440_init NULL
+#define s5p64x0_init NULL
 #endif
 
 /* S5P6440 timer */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-s5p/include/plat/s5p6450.h
new file mode 100644
index 00000000000..640a41c26be
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p6450.h
@@ -0,0 +1,36 @@
+/* arch/arm/plat-s5p/include/plat/s5p6450.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p6450 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5P6450 related SoCs */
+
+extern void s5p6450_register_clocks(void);
+extern void s5p6450_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5P6450
+
+extern  int s5p64x0_init(void);
+extern void s5p6450_init_irq(void);
+extern void s5p6450_map_io(void);
+extern void s5p6450_init_clocks(int xtal);
+
+extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+#else
+#define s5p6450_init_clocks NULL
+#define s5p6450_init_uarts NULL
+#define s5p6450_map_io NULL
+#define s5p64x0_init NULL
+#endif
+
+/* S5P6450 timer */
+
+extern struct sys_timer s5p6450_timer;
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 04d9521ddc9..e8f2be2d67f 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -435,7 +435,6 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
 static int s3c_adc_resume(struct platform_device *pdev)
 {
         struct adc_device *adc = platform_get_drvdata(pdev);
-        unsigned long flags;
 
         clk_enable(adc->clk);
         enable_irq(adc->irq);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 90a20512d68..e8d20b0bc50 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -48,6 +48,9 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
+#include <linux/serial_core.h>
+#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
+
 /* clock information */
 
 static LIST_HEAD(clocks);
@@ -65,6 +68,28 @@ static int clk_null_enable(struct clk *clk, int enable)
         return 0;
 }
 
+static int dev_is_s3c_uart(struct device *dev)
+{
+        struct platform_device **pdev = s3c24xx_uart_devs;
+        int i;
+        for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
+                if (*pdev && dev == &(*pdev)->dev)
+                        return 1;
+        return 0;
+}
+
+/*
+ * Serial drivers call get_clock() very early, before platform bus
+ * has been set up, this requires a special check to let them get
+ * a proper clock
+ */
+
+static int dev_is_platform_device(struct device *dev)
+{
+        return dev->bus == &platform_bus_type ||
+               (dev->bus == NULL && dev_is_s3c_uart(dev));
+}
+
 /* Clock API calls */
 
 struct clk *clk_get(struct device *dev, const char *id)
@@ -73,7 +98,7 @@ struct clk *clk_get(struct device *dev, const char *id)
         struct clk *clk = ERR_PTR(-ENOENT);
         int idno;
 
-        if (dev == NULL || dev->bus != &platform_bus_type)
+        if (dev == NULL || !dev_is_platform_device(dev))
                 idno = -1;
         else
                 idno = to_platform_device(dev)->id;
diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h
index e8382c7be10..b258a08de59 100644
--- a/arch/arm/plat-samsung/include/plat/adc.h
+++ b/arch/arm/plat-samsung/include/plat/adc.h
@@ -1,7 +1,7 @@
 /* arch/arm/plat-samsung/include/plat/adc.h
  *
  * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simnte.co.uk/
+ *      http://armlinux.simtec.co.uk/   
  *      Ben Dooks <ben@simtec.co.uk>
  *
  * S3C ADC driver information
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 6412933d6fb..9addb3dfb4b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -79,7 +79,7 @@ extern struct sysdev_class s3c2442_sysclass;
 extern struct sysdev_class s3c2443_sysclass;
 extern struct sysdev_class s3c6410_sysclass;
 extern struct sysdev_class s3c64xx_sysclass;
-extern struct sysdev_class s5p6440_sysclass;
+extern struct sysdev_class s5p64x0_sysclass;
 extern struct sysdev_class s5p6442_sysclass;
 extern struct sysdev_class s5pv210_sysclass;
 
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 85f6f23a510..c8b94279bad 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -32,6 +32,8 @@ extern struct platform_device s3c64xx_device_iisv4;
 extern struct platform_device s3c64xx_device_spi0;
 extern struct platform_device s3c64xx_device_spi1;
 
+extern struct platform_device s3c_device_pcm;
+
 extern struct platform_device s3c64xx_device_pcm0;
 extern struct platform_device s3c64xx_device_pcm1;
 
@@ -67,13 +69,15 @@ extern struct platform_device s5pv210_device_spi0;
 extern struct platform_device s5pv210_device_spi1;
 extern struct platform_device s5p6440_device_spi0;
 extern struct platform_device s5p6440_device_spi1;
+extern struct platform_device s5p6450_device_spi0;
+extern struct platform_device s5p6450_device_spi1;
 
 extern struct platform_device s3c_device_hwmon;
 
 extern struct platform_device s3c_device_nand;
 extern struct platform_device s3c_device_onenand;
 extern struct platform_device s3c64xx_device_onenand1;
-extern struct platform_device s5pc110_device_onenand;
+extern struct platform_device s5p_device_onenand;
 
 extern struct platform_device s3c_device_usbgadget;
 extern struct platform_device s3c_device_usb_hsotg;
@@ -95,6 +99,9 @@ extern struct platform_device s5p6442_device_spi;
 extern struct platform_device s5p6440_device_pcm;
 extern struct platform_device s5p6440_device_iis;
 
+extern struct platform_device s5p6450_device_iis0;
+extern struct platform_device s5p6450_device_pcm0;
+
 extern struct platform_device s5pc100_device_ac97;
 extern struct platform_device s5pc100_device_pcm0;
 extern struct platform_device s5pc100_device_pcm1;
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
index 5fe6721b57f..81074421312 100644
--- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
@@ -32,6 +32,12 @@ enum dma_ch {
         DMACH_UART2_TX,
         DMACH_UART3_RX,
         DMACH_UART3_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_UART5_RX,
+        DMACH_UART5_TX,
+        DMACH_USI_RX,
+        DMACH_USI_TX,
         DMACH_IRDA,
         DMACH_I2S0_RX,
         DMACH_I2S0_TX,
@@ -64,6 +70,20 @@ enum dma_ch {
         DMACH_MSM_REQ2,
         DMACH_MSM_REQ1,
         DMACH_MSM_REQ0,
+        DMACH_SLIMBUS0_RX,
+        DMACH_SLIMBUS0_TX,
+        DMACH_SLIMBUS0AUX_RX,
+        DMACH_SLIMBUS0AUX_TX,
+        DMACH_SLIMBUS1_RX,
+        DMACH_SLIMBUS1_TX,
+        DMACH_SLIMBUS2_RX,
+        DMACH_SLIMBUS2_TX,
+        DMACH_SLIMBUS3_RX,
+        DMACH_SLIMBUS3_TX,
+        DMACH_SLIMBUS4_RX,
+        DMACH_SLIMBUS4_TX,
+        DMACH_SLIMBUS5_RX,
+        DMACH_SLIMBUS5_TX,
         /* END Marker, also used to denote a reserved channel */
         DMACH_MAX,
 };
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index e5aba8f95b7..ff1a561b326 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -32,6 +32,8 @@ struct s3c64xx_spi_csinfo {
  * struct s3c64xx_spi_info - SPI Controller defining structure
  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
  * @src_clk_name: Platform name of the corresponding clock.
+ * @clk_from_cmu: If the SPI clock/prescalar control block is present
+ *     by the platform's clock-management-unit and not in SPI controller.
  * @num_cs: Number of CS this controller emulates.
  * @cfg_gpio: Configure pins for this SPI controller.
  * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
@@ -41,6 +43,7 @@ struct s3c64xx_spi_csinfo {
 struct s3c64xx_spi_info {
         int src_clk_nr;
         char *src_clk_name;
+        bool clk_from_cmu;
 
         int num_cs;
 
@@ -65,7 +68,7 @@ struct s3c64xx_spi_info {
 extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
-extern void s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
+extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 
 #endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 37fa593884e..e91270e4f64 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -14,11 +14,9 @@
 #include <linux/amba/serial.h>
 #include <mach/spear.h>
 
-                .macro  addruart, rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                                 @ MMU enabled?
-                moveq   \rx, #SPEAR_DBG_UART_BASE               @ Physical base
-                movne   \rx, #VA_SPEAR_DBG_UART_BASE            @ Virtual base
+                .macro  addruart, rp, rv
+                mov     \rp, #SPEAR_DBG_UART_BASE               @ Physical base
+                mov     \rv, #VA_SPEAR_DBG_UART_BASE            @ Virtual base
                 .endm
 
                 .macro  senduart, rd, rx
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
index 1b9348bf0e4..d3a0985c968 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
+++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
@@ -16,13 +16,10 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x80000000        @ physical base address
-                addeq   \rx, \rx, #0x00070000
-                movne   \rx, #0xf0000000        @ virtual base
-                addne   \rx, \rx, #0x00070000
+                .macro  addruart, rp, rv
+                mov     \rp,      #0x00070000
+                add     \rv, \rp, #0xf0000000   @ virtual base
+                add     \rp, \rp, #0x80000000   @ physical base
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/plat-tcc/Kconfig b/arch/arm/plat-tcc/Kconfig
new file mode 100644
index 00000000000..1bf499570f4
--- /dev/null
+++ b/arch/arm/plat-tcc/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_TCC_926
+
+menu "Telechips ARM926-based CPUs"
+
+choice
+        prompt "Telechips CPU type:"
+        default ARCH_TCC8K
+
+config ARCH_TCC8K
+        bool TCC8000
+        select USB_ARCH_HAS_OHCI
+        help
+          Support for Telechips TCC8000 systems
+
+endchoice
+
+source "arch/arm/mach-tcc8k/Kconfig"
+
+endmenu
+endif
diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile
new file mode 100644
index 00000000000..eceabc869b8
--- /dev/null
+++ b/arch/arm/plat-tcc/Makefile
@@ -0,0 +1,3 @@
+# "Telechips Platform Common Modules"
+
+obj-y := clock.o system.o
diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c
new file mode 100644
index 00000000000..f3ced10d527
--- /dev/null
+++ b/arch/arm/plat-tcc/clock.c
@@ -0,0 +1,179 @@
+/*
+ * Clock framework for Telechips SoCs
+ * Based on arch/arm/plat-mxc/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2010 Hans J. Koch, hjk@linutronix.de
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+static void __clk_disable(struct clk *clk)
+{
+        BUG_ON(clk->refcount == 0);
+
+        if (!(--clk->refcount) && clk->disable) {
+                /* Unconditionally disable the clock in hardware */
+                clk->disable(clk);
+                /* recursively disable parents */
+                if (clk->parent)
+                        __clk_disable(clk->parent);
+        }
+}
+
+static int __clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (clk->refcount++ == 0 && clk->enable) {
+                if (clk->parent)
+                        ret = __clk_enable(clk->parent);
+                if (ret)
+                        return ret;
+                else
+                        return clk->enable(clk);
+        }
+
+        return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (!clk)
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        ret = __clk_enable(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+        if (!clk)
+                return;
+
+        mutex_lock(&clocks_mutex);
+        __clk_disable(clk);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (!clk)
+                return 0UL;
+
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (!clk)
+                return 0;
+        if (!clk->round_rate)
+                return 0;
+
+        return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        if (!clk)
+                return ret;
+        if (!clk->set_rate || !rate)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_rate(clk, rate);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        struct clk *old;
+        int ret = -EINVAL;
+
+        if (!clk)
+                return ret;
+        if (!clk->set_parent || !parent)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        old = clk->parent;
+        if (clk->refcount)
+                __clk_enable(parent);
+        ret = clk->set_parent(clk, parent);
+        if (ret)
+                old = parent;
+        if (clk->refcount)
+                __clk_disable(old);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        if (!clk)
+                return NULL;
+
+        return clk->parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
new file mode 100644
index 00000000000..04b37a89801
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h
new file mode 100644
index 00000000000..a12f58ad71a
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clock.h
@@ -0,0 +1,48 @@
+/*
+ * Low level clock header file for Telechips TCC architecture
+ * (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_TCC_CLOCK_H__
+#define __ASM_ARCH_TCC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+
+struct clk {
+        struct clk *parent;
+        /* id number of a root clock, 0 for normal clocks */
+        int root_id;
+        /* Reference count of clock enable/disable */
+        int refcount;
+        /* Address of associated BCLKCTRx register. Must be set. */
+        void __iomem *bclkctr;
+        /* Bit position for BCLKCTRx. Must be set. */
+        int bclk_shift;
+        /* Address of ACLKxxx register, if any. */
+        void __iomem *aclkreg;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-tcc/include/mach/debug-macro.S b/arch/arm/plat-tcc/include/mach/debug-macro.S
new file mode 100644
index 00000000000..7662f736e42
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/debug-macro.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 1994-1999 Russell King
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+                .macro  addruart, rp, rv
+                moveq   \rp, #0x90000000        @ physical base address
+                movne   \rv, #0xF1000000        @ virtual base
+                orr     \rp, \rp, #0x00007000   @ UART0
+                orr     \rv, \rv, #0x00007000   @ UART0
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #0x44]
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:
+                ldr \rd, [\rx, #0x14]
+                tst \rd, #0x20
+
+                beq 1001b
+                .endm
diff --git a/arch/arm/plat-tcc/include/mach/entry-macro.S b/arch/arm/plat-tcc/include/mach/entry-macro.S
new file mode 100644
index 00000000000..748f401e4b6
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/entry-macro.S
@@ -0,0 +1,68 @@
+/*
+ * include/asm-arm/arch-tcc83x/entry-macro.S
+ *
+ * Author : <linux@telechips.com>
+ * Created: June 10, 2008
+ * Description: Low-level IRQ helper macros for Telechips-based platforms
+ *
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                ldr     \base, =0xF2003000 @ base address of PIC registers
+
+                @@ read MREQ register of PIC0
+
+                mov     \irqnr, #0
+                ldr     \irqstat, [\base, #0x00000014 ] @ lower 32 interrupts
+                cmp     \irqstat, #0
+                bne     1001f
+
+                @@ read MREQ register of PIC1
+
+                ldr     \irqstat, [\base, #0x00000094]  @ upper 32 interrupts
+                cmp     \irqstat, #0
+                beq     1002f
+                mov     \irqnr, #0x20
+
+1001:
+                movs    \tmp, \irqstat, lsl #16
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+
+                movs    \tmp, \irqstat, lsl #8
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #8
+
+                movs    \tmp, \irqstat, lsl #4
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #4
+
+                movs    \tmp, \irqstat, lsl #2
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #2
+
+                movs    \tmp, \irqstat, lsl #1
+                addeq   \irqnr, \irqnr, #1
+                orrs    \base, \base, #1
+1002:
+                @@ exit here, Z flag unset if IRQ
+
+        .endm
diff --git a/arch/arm/plat-tcc/include/mach/hardware.h b/arch/arm/plat-tcc/include/mach/hardware.h
new file mode 100644
index 00000000000..e70d126ccaf
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/hardware.h
@@ -0,0 +1,43 @@
+/*
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ * Rewritten by:    <linux@telechips.com>
+ * Description: Hardware definitions for TCC8300 processors and boards
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Modifications for mainline (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU Pulic License version 2.
+ */
+
+#ifndef __ASM_ARCH_TCC_HARDWARE_H
+#define __ASM_ARCH_TCC_HARDWARE_H
+
+#include <asm/sizes.h>
+#ifndef __ASSEMBLER__
+#include <asm/types.h>
+#endif
+#include <mach/io.h>
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE         0xfffece00
+#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
+
+/* DPLL control registers */
+#define DPLL_CTL                0xfffecf00
+
+#endif  /* __ASM_ARCH_TCC_HARDWARE_H */
diff --git a/arch/arm/plat-tcc/include/mach/io.h b/arch/arm/plat-tcc/include/mach/io.h
new file mode 100644
index 00000000000..3e911d3ea0f
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/io.h
@@ -0,0 +1,23 @@
+/*
+ * IO definitions for TCC8000 processors and boards
+ *
+ * Copyright (C) 1997-1999 Russell King
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GNU Public License version 2.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 __typesafe_io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/irqs.h b/arch/arm/plat-tcc/include/mach/irqs.h
new file mode 100644
index 00000000000..da863894d49
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/irqs.h
@@ -0,0 +1,83 @@
+/*
+ * IRQ definitions for TCC8xxx
+ *
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#ifndef __ASM_ARCH_TCC_IRQS_H
+#define __ASM_ARCH_TCC_IRQS_H
+
+#define NR_IRQS 64
+
+/* PIC0 interrupts */
+#define INT_ADMA1       0
+#define INT_BDMA        1
+#define INT_ADMA0       2
+#define INT_GDMA1       3
+#define INT_I2S0RX      4
+#define INT_I2S0TX      5
+#define INT_TC          6
+#define INT_UART0       7
+#define INT_USBD        8
+#define INT_SPI0TX      9
+#define INT_UDMA        10
+#define INT_LIRQ        11
+#define INT_GDMA2       12
+#define INT_GDMA0       13
+#define INT_TC32        14
+#define INT_LCD         15
+#define INT_ADC         16
+#define INT_I2C         17
+#define INT_RTCP        18
+#define INT_RTCA        19
+#define INT_NFC         20
+#define INT_SD0         21
+#define INT_GSB0        22
+#define INT_PK          23
+#define INT_USBH0       24
+#define INT_USBH1       25
+#define INT_G2D         26
+#define INT_ECC         27
+#define INT_SPI0RX      28
+#define INT_UART1       29
+#define INT_MSCL        30
+#define INT_GSB1        31
+/* PIC1 interrupts */
+#define INT_E0          32
+#define INT_E1          33
+#define INT_E2          34
+#define INT_E3          35
+#define INT_E4          36
+#define INT_E5          37
+#define INT_E6          38
+#define INT_E7          39
+#define INT_UART2       40
+#define INT_UART3       41
+#define INT_SPI1TX      42
+#define INT_SPI1RX      43
+#define INT_GSB2        44
+#define INT_SPDIF       45
+#define INT_CDIF        46
+#define INT_VBON        47
+#define INT_VBOFF       48
+#define INT_SD1         49
+#define INT_UART4       50
+#define INT_GDMA3       51
+#define INT_I2S1RX      52
+#define INT_I2S1TX      53
+#define INT_CAN0        54
+#define INT_CAN1        55
+#define INT_GSB3        56
+#define INT_KRST        57
+#define INT_UNUSED      58
+#define INT_SD0D3       59
+#define INT_SD1D3       60
+#define INT_GPS0        61
+#define INT_GPS1        62
+#define INT_GPS2        63
+
+#endif  /* ASM_ARCH_TCC_IRQS_H */
diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h
new file mode 100644
index 00000000000..cd91ba8a670
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/memory.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x20000000)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/system.h b/arch/arm/plat-tcc/include/mach/system.h
new file mode 100644
index 00000000000..909e6035d84
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/system.h
@@ -0,0 +1,31 @@
+/*
+ * Author: <linux@telechips.com>
+ * Created: June 10, 2008
+ * Description: LINUX SYSTEM FUNCTIONS for TCC83x
+ *
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/clk.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+extern void plat_tcc_reboot(void);
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        plat_tcc_reboot();
+}
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
new file mode 100644
index 00000000000..1d942829533
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
@@ -0,0 +1,807 @@
+/*
+ * Telechips TCC8000 register definitions
+ *
+ * (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPLv2.
+ */
+
+#ifndef TCC8K_REGS_H
+#define TCC8K_REGS_H
+
+#include <linux/types.h>
+
+#define EXT_SDRAM_BASE          0x20000000
+#define INT_SRAM_BASE           0x30000000
+#define INT_SRAM_SIZE           SZ_32K
+#define CS0_BASE                0x40000000
+#define CS1_BASE                0x50000000
+#define CS1_SIZE                SZ_64K
+#define CS2_BASE                0x60000000
+#define CS3_BASE                0x70000000
+#define AHB_PERI_BASE           0x80000000
+#define AHB_PERI_SIZE           SZ_64K
+#define APB0_PERI_BASE          0x90000000
+#define APB0_PERI_SIZE          SZ_128K
+#define APB1_PERI_BASE          0x98000000
+#define APB1_PERI_SIZE          SZ_128K
+#define DATA_TCM_BASE           0xa0000000
+#define DATA_TCM_SIZE           SZ_8K
+#define EXT_MEM_CTRL_BASE       0xf0000000
+#define EXT_MEM_CTRL_SIZE       SZ_4K
+
+#define CS1_BASE_VIRT           (void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT      (void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT     (void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT     (void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT  (void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT      (void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT      (void __iomem *)0xf6000000
+
+#define __REG(x)     (*((volatile u32 *)(x)))
+
+/* USB Device Controller Registers */
+#define UDC_BASE        (AHB_PERI_BASE_VIRT + 0x8000)
+#define UDC_BASE_PHYS   (AHB_PERI_BASE + 0x8000)
+
+#define UDC_IR_OFFS             0x00
+#define UDC_EIR_OFFS            0x04
+#define UDC_EIER_OFFS           0x08
+#define UDC_FAR_OFFS            0x0c
+#define UDC_FNR_OFFS            0x10
+#define UDC_EDR_OFFS            0x14
+#define UDC_RT_OFFS             0x18
+#define UDC_SSR_OFFS            0x1c
+#define UDC_SCR_OFFS            0x20
+#define UDC_EP0SR_OFFS          0x24
+#define UDC_EP0CR_OFFS          0x28
+
+#define UDC_ESR_OFFS            0x2c
+#define UDC_ECR_OFFS            0x30
+#define UDC_BRCR_OFFS           0x34
+#define UDC_BWCR_OFFS           0x38
+#define UDC_MPR_OFFS            0x3c
+#define UDC_DCR_OFFS            0x40
+#define UDC_DTCR_OFFS           0x44
+#define UDC_DFCR_OFFS           0x48
+#define UDC_DTTCR1_OFFS         0x4c
+#define UDC_DTTCR2_OFFS         0x50
+#define UDC_ESR2_OFFS           0x54
+
+#define UDC_SCR2_OFFS           0x58
+#define UDC_EP0BUF_OFFS         0x60
+#define UDC_EP1BUF_OFFS         0x64
+#define UDC_EP2BUF_OFFS         0x68
+#define UDC_EP3BUF_OFFS         0x6c
+#define UDC_PLICR_OFFS          0xa0
+#define UDC_PCR_OFFS            0xa4
+
+#define UDC_UPCR0_OFFS          0xc8
+#define UDC_UPCR1_OFFS          0xcc
+#define UDC_UPCR2_OFFS          0xd0
+#define UDC_UPCR3_OFFS          0xd4
+
+/* Bits in UDC_EIR */
+#define UDC_EIR_EP0I            (1 << 0)
+#define UDC_EIR_EP1I            (1 << 1)
+#define UDC_EIR_EP2I            (1 << 2)
+#define UDC_EIR_EP3I            (1 << 3)
+#define UDC_EIR_EPI_MASK        0x0f
+
+/* Bits in UDC_EIER */
+#define UDC_EIER_EP0IE          (1 << 0)
+#define UDC_EIER_EP1IE          (1 << 1)
+#define UDC_EIER_EP2IE          (1 << 2)
+#define UDC_EIER_EP3IE          (1 << 3)
+
+/* Bits in UDC_FNR */
+#define UDC_FNR_FN_MASK         0x7ff
+#define UDC_FNR_SM              (1 << 13)
+#define UDC_FNR_FTL             (1 << 14)
+
+/* Bits in UDC_SSR */
+#define UDC_SSR_HFRES           (1 << 0)
+#define UDC_SSR_HFSUSP          (1 << 1)
+#define UDC_SSR_HFRM            (1 << 2)
+#define UDC_SSR_SDE             (1 << 3)
+#define UDC_SSR_HSP             (1 << 4)
+#define UDC_SSR_DM              (1 << 5)
+#define UDC_SSR_DP              (1 << 6)
+#define UDC_SSR_TBM             (1 << 7)
+#define UDC_SSR_VBON            (1 << 8)
+#define UDC_SSR_VBOFF           (1 << 9)
+#define UDC_SSR_EOERR           (1 << 10)
+#define UDC_SSR_DCERR           (1 << 11)
+#define UDC_SSR_TCERR           (1 << 12)
+#define UDC_SSR_BSERR           (1 << 13)
+#define UDC_SSR_TMERR           (1 << 14)
+#define UDC_SSR_BAERR           (1 << 15)
+
+/* Bits in UDC_SCR */
+#define UDC_SCR_HRESE           (1 << 0)
+#define UDC_SCR_HSSPE           (1 << 1)
+#define UDC_SCR_RRDE            (1 << 5)
+#define UDC_SCR_SPDEN           (1 << 6)
+#define UDC_SCR_DIEN            (1 << 12)
+
+/* Bits in UDC_EP0SR */
+#define UDC_EP0SR_RSR           (1 << 0)
+#define UDC_EP0SR_TST           (1 << 1)
+#define UDC_EP0SR_SHT           (1 << 4)
+#define UDC_EP0SR_LWO           (1 << 6)
+
+/* Bits in UDC_EP0CR */
+#define UDC_EP0CR_ESS           (1 << 1)
+
+/* Bits in UDC_ESR */
+#define UDC_ESR_RPS             (1 << 0)
+#define UDC_ESR_TPS             (1 << 1)
+#define UDC_ESR_LWO             (1 << 4)
+#define UDC_ESR_FFS             (1 << 6)
+
+/* Bits in UDC_ECR */
+#define UDC_ECR_ESS             (1 << 1)
+#define UDC_ECR_CDP             (1 << 2)
+
+#define UDC_ECR_FLUSH           (1 << 6)
+#define UDC_ECR_DUEN            (1 << 7)
+
+/* Bits in UDC_UPCR0 */
+#define UDC_UPCR0_VBD           (1 << 1)
+#define UDC_UPCR0_VBDS          (1 << 6)
+#define UDC_UPCR0_RCD_12        (0x0 << 9)
+#define UDC_UPCR0_RCD_24        (0x1 << 9)
+#define UDC_UPCR0_RCD_48        (0x2 << 9)
+#define UDC_UPCR0_RCS_EXT       (0x1 << 11)
+#define UDC_UPCR0_RCS_XTAL      (0x0 << 11)
+
+/* Bits in UDC_UPCR1 */
+#define UDC_UPCR1_CDT(x)        ((x) << 0)
+#define UDC_UPCR1_OTGT(x)       ((x) << 3)
+#define UDC_UPCR1_SQRXT(x)      ((x) << 8)
+#define UDC_UPCR1_TXFSLST(x)    ((x) << 12)
+
+/* Bits in UDC_UPCR2 */
+#define UDC_UPCR2_TP            (1 << 0)
+#define UDC_UPCR2_TXRT(x)       ((x) << 2)
+#define UDC_UPCR2_TXVRT(x)      ((x) << 5)
+#define UDC_UPCR2_OPMODE(x)     ((x) << 9)
+#define UDC_UPCR2_XCVRSEL(x)    ((x) << 12)
+#define UDC_UPCR2_TM            (1 << 14)
+
+/* USB Host Controller registers */
+#define USBH0_BASE      (AHB_PERI_BASE_VIRT + 0xb000)
+#define USBH1_BASE      (AHB_PERI_BASE_VIRT + 0xb800)
+
+#define OHCI_INT_ENABLE_OFFS    0x10
+
+#define RH_DESCRIPTOR_A_OFFS    0x48
+#define RH_DESCRIPTOR_B_OFFS    0x4c
+
+#define USBHTCFG0_OFFS          0x100
+#define USBHHCFG0_OFFS          0x104
+#define USBHHCFG1_OFFS          0x104
+
+/* DMA controller registers */
+#define DMAC0_BASE      (AHB_PERI_BASE + 0x4000)
+#define DMAC1_BASE      (AHB_PERI_BASE + 0xa000)
+#define DMAC2_BASE      (AHB_PERI_BASE + 0x4800)
+#define DMAC3_BASE      (AHB_PERI_BASE + 0xa800)
+
+#define DMAC_CH_OFFSET(ch)      (ch * 0x30)
+
+#define ST_SADR_OFFS            0x00
+#define SPARAM_OFFS             0x04
+#define C_SADR_OFFS             0x0c
+#define ST_DADR_OFFS            0x10
+#define DPARAM_OFFS             0x14
+#define C_DADR_OFFS             0x1c
+#define HCOUNT_OFFS             0x20
+#define CHCTRL_OFFS             0x24
+#define RPTCTRL_OFFS            0x28
+#define EXTREQ_A_OFFS           0x2c
+
+/* Bits in CHCTRL register */
+#define CHCTRL_EN               (1 << 0)
+
+#define CHCTRL_IEN              (1 << 2)
+#define CHCTRL_FLAG             (1 << 3)
+#define CHCTRL_WSIZE8           (0 << 4)
+#define CHCTRL_WSIZE16          (1 << 4)
+#define CHCTRL_WSIZE32          (2 << 4)
+
+#define CHCTRL_BSIZE1           (0 << 6)
+#define CHCTRL_BSIZE2           (1 << 6)
+#define CHCTRL_BSIZE4           (2 << 6)
+#define CHCTRL_BSIZE8           (3 << 6)
+
+#define CHCTRL_TYPE_SINGLE_E    (0 << 8)
+#define CHCTRL_TYPE_HW          (1 << 8)
+#define CHCTRL_TYPE_SW          (2 << 8)
+#define CHCTRL_TYPE_SINGLE_L    (3 << 8)
+
+#define CHCTRL_BST              (1 << 10)
+
+/* Use DMA controller 0, channel 2 for USB */
+#define USB_DMA_BASE            (DMAC0_BASE + DMAC_CH_OFFSET(2))
+
+/* NAND flash controller registers */
+#define NFC_BASE        (AHB_PERI_BASE_VIRT + 0xd000)
+#define NFC_BASE_PHYS   (AHB_PERI_BASE + 0xd000)
+
+#define NFC_CMD_OFFS            0x00
+#define NFC_LADDR_OFFS          0x04
+#define NFC_BADDR_OFFS          0x08
+#define NFC_SADDR_OFFS          0x0c
+#define NFC_WDATA_OFFS          0x10
+#define NFC_LDATA_OFFS          0x20
+#define NFC_SDATA_OFFS          0x40
+#define NFC_CTRL_OFFS           0x50
+#define NFC_PSTART_OFFS         0x54
+#define NFC_RSTART_OFFS         0x58
+#define NFC_DSIZE_OFFS          0x5c
+#define NFC_IREQ_OFFS           0x60
+#define NFC_RST_OFFS            0x64
+#define NFC_CTRL1_OFFS          0x68
+#define NFC_MDATA_OFFS          0x70
+
+#define NFC_WDATA_PHYS_ADDR     (NFC_BASE_PHYS + NFC_WDATA_OFFS)
+
+/* Bits in NFC_CTRL */
+#define NFC_CTRL_BHLD_MASK      (0xf << 0)
+#define NFC_CTRL_BPW_MASK       (0xf << 4)
+#define NFC_CTRL_BSTP_MASK      (0xf << 8)
+#define NFC_CTRL_CADDR_MASK     (0x7 << 12)
+#define NFC_CTRL_CADDR_1        (0x0 << 12)
+#define NFC_CTRL_CADDR_2        (0x1 << 12)
+#define NFC_CTRL_CADDR_3        (0x2 << 12)
+#define NFC_CTRL_CADDR_4        (0x3 << 12)
+#define NFC_CTRL_CADDR_5        (0x4 << 12)
+#define NFC_CTRL_MSK            (1 << 15)
+#define NFC_CTRL_PSIZE256       (0 << 16)
+#define NFC_CTRL_PSIZE512       (1 << 16)
+#define NFC_CTRL_PSIZE1024      (2 << 16)
+#define NFC_CTRL_PSIZE2048      (3 << 16)
+#define NFC_CTRL_PSIZE4096      (4 << 16)
+#define NFC_CTRL_PSIZE_MASK     (7 << 16)
+#define NFC_CTRL_BSIZE1         (0 << 19)
+#define NFC_CTRL_BSIZE2         (1 << 19)
+#define NFC_CTRL_BSIZE4         (2 << 19)
+#define NFC_CTRL_BSIZE8         (3 << 19)
+#define NFC_CTRL_BSIZE_MASK     (3 << 19)
+#define NFC_CTRL_RDY            (1 << 21)
+#define NFC_CTRL_CS0SEL         (1 << 22)
+#define NFC_CTRL_CS1SEL         (1 << 23)
+#define NFC_CTRL_CS2SEL         (1 << 24)
+#define NFC_CTRL_CS3SEL         (1 << 25)
+#define NFC_CTRL_CSMASK         (0xf << 22)
+#define NFC_CTRL_BW             (1 << 26)
+#define NFC_CTRL_FS             (1 << 27)
+#define NFC_CTRL_DEN            (1 << 28)
+#define NFC_CTRL_READ_IEN       (1 << 29)
+#define NFC_CTRL_PROG_IEN       (1 << 30)
+#define NFC_CTRL_RDY_IEN        (1 << 31)
+
+/* Bits in NFC_IREQ */
+#define NFC_IREQ_IRQ0           (1 << 0)
+#define NFC_IREQ_IRQ1           (1 << 1)
+#define NFC_IREQ_IRQ2           (1 << 2)
+
+#define NFC_IREQ_FLAG0          (1 << 4)
+#define NFC_IREQ_FLAG1          (1 << 5)
+#define NFC_IREQ_FLAG2          (1 << 6)
+
+/* MMC controller registers */
+#define MMC0_BASE       (AHB_PERI_BASE_VIRT + 0xe000)
+#define MMC1_BASE       (AHB_PERI_BASE_VIRT + 0xe800)
+
+/* UART base addresses */
+
+#define UART0_BASE      (APB0_PERI_BASE_VIRT + 0x07000)
+#define UART0_BASE_PHYS (APB0_PERI_BASE + 0x07000)
+#define UART1_BASE      (APB0_PERI_BASE_VIRT + 0x08000)
+#define UART1_BASE_PHYS (APB0_PERI_BASE + 0x08000)
+#define UART2_BASE      (APB0_PERI_BASE_VIRT + 0x09000)
+#define UART2_BASE_PHYS (APB0_PERI_BASE + 0x09000)
+#define UART3_BASE      (APB0_PERI_BASE_VIRT + 0x0a000)
+#define UART3_BASE_PHYS (APB0_PERI_BASE + 0x0a000)
+#define UART4_BASE      (APB0_PERI_BASE_VIRT + 0x15000)
+#define UART4_BASE_PHYS (APB0_PERI_BASE + 0x15000)
+
+#define UART_BASE       UART0_BASE
+#define UART_BASE_PHYS  UART0_BASE_PHYS
+
+/* ECC controller */
+#define ECC_CTR_BASE    (APB0_PERI_BASE_VIRT + 0xd000)
+
+#define ECC_CTRL_OFFS           0x00
+#define ECC_BASE_OFFS           0x04
+#define ECC_MASK_OFFS           0x08
+#define ECC_CLEAR_OFFS          0x0c
+#define ECC4_0_OFFS             0x10
+#define ECC4_1_OFFS             0x14
+
+#define ECC_EADDR0_OFFS         0x50
+
+#define ECC_ERRNUM_OFFS         0x90
+#define ECC_IREQ_OFFS           0x94
+
+/* Bits in ECC_CTRL */
+#define ECC_CTRL_ECC4_DIEN      (1 << 28)
+#define ECC_CTRL_ECC8_DIEN      (1 << 29)
+#define ECC_CTRL_ECC12_DIEN     (1 << 30)
+#define ECC_CTRL_ECC_DISABLE    0x0
+#define ECC_CTRL_ECC_SLC_ENC    0x8
+#define ECC_CTRL_ECC_SLC_DEC    0x9
+#define ECC_CTRL_ECC4_ENC       0xa
+#define ECC_CTRL_ECC4_DEC       0xb
+#define ECC_CTRL_ECC8_ENC       0xc
+#define ECC_CTRL_ECC8_DEC       0xd
+#define ECC_CTRL_ECC12_ENC      0xe
+#define ECC_CTRL_ECC12_DEC      0xf
+
+/* Bits in ECC_IREQ */
+#define ECC_IREQ_E4DI           (1 << 4)
+
+#define ECC_IREQ_E4DF           (1 << 20)
+#define ECC_IREQ_E4EF           (1 << 21)
+
+/* Interrupt controller */
+
+#define PIC0_BASE       (APB1_PERI_BASE_VIRT + 0x3000)
+#define PIC0_BASE_PHYS  (APB1_PERI_BASE + 0x3000)
+
+#define PIC0_IEN_OFFS           0x00
+#define PIC0_CREQ_OFFS          0x04
+#define PIC0_IREQ_OFFS          0x08
+#define PIC0_IRQSEL_OFFS        0x0c
+#define PIC0_SRC_OFFS           0x10
+#define PIC0_MREQ_OFFS          0x14
+#define PIC0_TSTREQ_OFFS        0x18
+#define PIC0_POL_OFFS           0x1c
+#define PIC0_IRQ_OFFS           0x20
+#define PIC0_FIQ_OFFS           0x24
+#define PIC0_MIRQ_OFFS          0x28
+#define PIC0_MFIQ_OFFS          0x2c
+#define PIC0_TMODE_OFFS         0x30
+#define PIC0_SYNC_OFFS          0x34
+#define PIC0_WKUP_OFFS          0x38
+#define PIC0_TMODEA_OFFS        0x3c
+#define PIC0_INTOEN_OFFS        0x40
+#define PIC0_MEN0_OFFS          0x44
+#define PIC0_MEN_OFFS           0x48
+
+#define PIC0_IEN                __REG(PIC0_BASE + PIC0_IEN_OFFS)
+#define PIC0_IEN_PHYS           __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS)
+#define PIC0_CREQ               __REG(PIC0_BASE + PIC0_CREQ_OFFS)
+#define PIC0_CREQ_PHYS          __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS)
+#define PIC0_IREQ               __REG(PIC0_BASE + PIC0_IREQ_OFFS)
+#define PIC0_IRQSEL             __REG(PIC0_BASE + PIC0_IRQSEL_OFFS)
+#define PIC0_IRQSEL_PHYS        __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS)
+#define PIC0_SRC                __REG(PIC0_BASE + PIC0_SRC_OFFS)
+#define PIC0_MREQ               __REG(PIC0_BASE + PIC0_MREQ_OFFS)
+#define PIC0_TSTREQ             __REG(PIC0_BASE + PIC0_TSTREQ_OFFS)
+#define PIC0_POL                __REG(PIC0_BASE + PIC0_POL_OFFS)
+#define PIC0_IRQ                __REG(PIC0_BASE + PIC0_IRQ_OFFS)
+#define PIC0_FIQ                __REG(PIC0_BASE + PIC0_FIQ_OFFS)
+#define PIC0_MIRQ               __REG(PIC0_BASE + PIC0_MIRQ_OFFS)
+#define PIC0_MFIQ               __REG(PIC0_BASE + PIC0_MFIQ_OFFS)
+#define PIC0_TMODE              __REG(PIC0_BASE + PIC0_TMODE_OFFS)
+#define PIC0_TMODE_PHYS         __REG(PIC0_BASE_PHYS + PIC0_TMODE_OFFS)
+#define PIC0_SYNC               __REG(PIC0_BASE + PIC0_SYNC_OFFS)
+#define PIC0_WKUP               __REG(PIC0_BASE + PIC0_WKUP_OFFS)
+#define PIC0_TMODEA             __REG(PIC0_BASE + PIC0_TMODEA_OFFS)
+#define PIC0_INTOEN             __REG(PIC0_BASE + PIC0_INTOEN_OFFS)
+#define PIC0_MEN0               __REG(PIC0_BASE + PIC0_MEN0_OFFS)
+#define PIC0_MEN                __REG(PIC0_BASE + PIC0_MEN_OFFS)
+
+#define PIC1_BASE       (APB1_PERI_BASE_VIRT + 0x3080)
+
+#define PIC1_IEN_OFFS           0x00
+#define PIC1_CREQ_OFFS          0x04
+#define PIC1_IREQ_OFFS          0x08
+#define PIC1_IRQSEL_OFFS        0x0c
+#define PIC1_SRC_OFFS           0x10
+#define PIC1_MREQ_OFFS          0x14
+#define PIC1_TSTREQ_OFFS        0x18
+#define PIC1_POL_OFFS           0x1c
+#define PIC1_IRQ_OFFS           0x20
+#define PIC1_FIQ_OFFS           0x24
+#define PIC1_MIRQ_OFFS          0x28
+#define PIC1_MFIQ_OFFS          0x2c
+#define PIC1_TMODE_OFFS         0x30
+#define PIC1_SYNC_OFFS          0x34
+#define PIC1_WKUP_OFFS          0x38
+#define PIC1_TMODEA_OFFS        0x3c
+#define PIC1_INTOEN_OFFS        0x40
+#define PIC1_MEN1_OFFS          0x44
+#define PIC1_MEN_OFFS           0x48
+
+#define PIC1_IEN        __REG(PIC1_BASE + PIC1_IEN_OFFS)
+#define PIC1_CREQ       __REG(PIC1_BASE + PIC1_CREQ_OFFS)
+#define PIC1_IREQ       __REG(PIC1_BASE + PIC1_IREQ_OFFS)
+#define PIC1_IRQSEL     __REG(PIC1_BASE + PIC1_IRQSEL_OFFS)
+#define PIC1_SRC        __REG(PIC1_BASE + PIC1_SRC_OFFS)
+#define PIC1_MREQ       __REG(PIC1_BASE + PIC1_MREQ_OFFS)
+#define PIC1_TSTREQ     __REG(PIC1_BASE + PIC1_TSTREQ_OFFS)
+#define PIC1_POL        __REG(PIC1_BASE + PIC1_POL_OFFS)
+#define PIC1_IRQ        __REG(PIC1_BASE + PIC1_IRQ_OFFS)
+#define PIC1_FIQ        __REG(PIC1_BASE + PIC1_FIQ_OFFS)
+#define PIC1_MIRQ       __REG(PIC1_BASE + PIC1_MIRQ_OFFS)
+#define PIC1_MFIQ       __REG(PIC1_BASE + PIC1_MFIQ_OFFS)
+#define PIC1_TMODE      __REG(PIC1_BASE + PIC1_TMODE_OFFS)
+#define PIC1_SYNC       __REG(PIC1_BASE + PIC1_SYNC_OFFS)
+#define PIC1_WKUP       __REG(PIC1_BASE + PIC1_WKUP_OFFS)
+#define PIC1_TMODEA     __REG(PIC1_BASE + PIC1_TMODEA_OFFS)
+#define PIC1_INTOEN     __REG(PIC1_BASE + PIC1_INTOEN_OFFS)
+#define PIC1_MEN1       __REG(PIC1_BASE + PIC1_MEN1_OFFS)
+#define PIC1_MEN        __REG(PIC1_BASE + PIC1_MEN_OFFS)
+
+/* Timer registers */
+#define TIMER_BASE              (APB1_PERI_BASE_VIRT + 0x4000)
+#define TIMER_BASE_PHYS         (APB1_PERI_BASE + 0x4000)
+
+#define TWDCFG_OFFS             0x70
+
+#define TC32EN_OFFS             0x80
+#define TC32LDV_OFFS            0x84
+#define TC32CMP0_OFFS           0x88
+#define TC32CMP1_OFFS           0x8c
+#define TC32PCNT_OFFS           0x90
+#define TC32MCNT_OFFS           0x94
+#define TC32IRQ_OFFS            0x98
+
+/* Bits in TC32EN */
+#define TC32EN_PRESCALE_MASK    0x00ffffff
+#define TC32EN_ENABLE           (1 << 24)
+#define TC32EN_LOADZERO         (1 << 25)
+#define TC32EN_STOPMODE         (1 << 26)
+#define TC32EN_LDM0             (1 << 28)
+#define TC32EN_LDM1             (1 << 29)
+
+/* Bits in TC32IRQ */
+#define TC32IRQ_MSTAT_MASK      0x0000001f
+#define TC32IRQ_RSTAT_MASK      (0x1f << 8)
+#define TC32IRQ_IRQEN0          (1 << 16)
+#define TC32IRQ_IRQEN1          (1 << 17)
+#define TC32IRQ_IRQEN2          (1 << 18)
+#define TC32IRQ_IRQEN3          (1 << 19)
+#define TC32IRQ_IRQEN4          (1 << 20)
+#define TC32IRQ_RSYNC           (1 << 30)
+#define TC32IRQ_IRQCLR          (1 << 31)
+
+/* GPIO registers */
+#define GPIOPD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPD_DAT_OFFS         0x00
+#define GPIOPD_DOE_OFFS         0x04
+#define GPIOPD_FS0_OFFS         0x08
+#define GPIOPD_FS1_OFFS         0x0c
+#define GPIOPD_FS2_OFFS         0x10
+#define GPIOPD_RPU_OFFS         0x30
+#define GPIOPD_RPD_OFFS         0x34
+#define GPIOPD_DV0_OFFS         0x38
+#define GPIOPD_DV1_OFFS         0x3c
+
+#define GPIOPS_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPS_DAT_OFFS         0x40
+#define GPIOPS_DOE_OFFS         0x44
+#define GPIOPS_FS0_OFFS         0x48
+#define GPIOPS_FS1_OFFS         0x4c
+#define GPIOPS_FS2_OFFS         0x50
+#define GPIOPS_FS3_OFFS         0x54
+#define GPIOPS_RPU_OFFS         0x70
+#define GPIOPS_RPD_OFFS         0x74
+#define GPIOPS_DV0_OFFS         0x78
+#define GPIOPS_DV1_OFFS         0x7c
+
+#define GPIOPS_FS1_SDH0_BITS    0x000000ff
+#define GPIOPS_FS1_SDH1_BITS    0x0000ff00
+
+#define GPIOPU_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOPU_DAT_OFFS         0x80
+#define GPIOPU_DOE_OFFS         0x84
+#define GPIOPU_FS0_OFFS         0x88
+#define GPIOPU_FS1_OFFS         0x8c
+#define GPIOPU_FS2_OFFS         0x90
+#define GPIOPU_RPU_OFFS         0xb0
+#define GPIOPU_RPD_OFFS         0xb4
+#define GPIOPU_DV0_OFFS         0xb8
+#define GPIOPU_DV1_OFFS         0xbc
+
+#define GPIOPU_FS0_TXD0         (1 << 0)
+#define GPIOPU_FS0_RXD0         (1 << 1)
+#define GPIOPU_FS0_CTS0         (1 << 2)
+#define GPIOPU_FS0_RTS0         (1 << 3)
+#define GPIOPU_FS0_TXD1         (1 << 4)
+#define GPIOPU_FS0_RXD1         (1 << 5)
+#define GPIOPU_FS0_CTS1         (1 << 6)
+#define GPIOPU_FS0_RTS1         (1 << 7)
+#define GPIOPU_FS0_TXD2         (1 << 8)
+#define GPIOPU_FS0_RXD2         (1 << 9)
+#define GPIOPU_FS0_CTS2         (1 << 10)
+#define GPIOPU_FS0_RTS2         (1 << 11)
+#define GPIOPU_FS0_TXD3         (1 << 12)
+#define GPIOPU_FS0_RXD3         (1 << 13)
+#define GPIOPU_FS0_CTS3         (1 << 14)
+#define GPIOPU_FS0_RTS3         (1 << 15)
+#define GPIOPU_FS0_TXD4         (1 << 16)
+#define GPIOPU_FS0_RXD4         (1 << 17)
+#define GPIOPU_FS0_CTS4         (1 << 18)
+#define GPIOPU_FS0_RTS4         (1 << 19)
+
+#define GPIOFC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOFC_DAT_OFFS         0xc0
+#define GPIOFC_DOE_OFFS         0xc4
+#define GPIOFC_FS0_OFFS         0xc8
+#define GPIOFC_FS1_OFFS         0xcc
+#define GPIOFC_FS2_OFFS         0xd0
+#define GPIOFC_FS3_OFFS         0xd4
+#define GPIOFC_RPU_OFFS         0xf0
+#define GPIOFC_RPD_OFFS         0xf4
+#define GPIOFC_DV0_OFFS         0xf8
+#define GPIOFC_DV1_OFFS         0xfc
+
+#define GPIOFD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOFD_DAT_OFFS         0x100
+#define GPIOFD_DOE_OFFS         0x104
+#define GPIOFD_FS0_OFFS         0x108
+#define GPIOFD_FS1_OFFS         0x10c
+#define GPIOFD_FS2_OFFS         0x110
+#define GPIOFD_RPU_OFFS         0x130
+#define GPIOFD_RPD_OFFS         0x134
+#define GPIOFD_DV0_OFFS         0x138
+#define GPIOFD_DV1_OFFS         0x13c
+
+#define GPIOLC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOLC_DAT_OFFS         0x140
+#define GPIOLC_DOE_OFFS         0x144
+#define GPIOLC_FS0_OFFS         0x148
+#define GPIOLC_FS1_OFFS         0x14c
+#define GPIOLC_RPU_OFFS         0x170
+#define GPIOLC_RPD_OFFS         0x174
+#define GPIOLC_DV0_OFFS         0x178
+#define GPIOLC_DV1_OFFS         0x17c
+
+#define GPIOLD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOLD_DAT_OFFS         0x180
+#define GPIOLD_DOE_OFFS         0x184
+#define GPIOLD_FS0_OFFS         0x188
+#define GPIOLD_FS1_OFFS         0x18c
+#define GPIOLD_FS2_OFFS         0x190
+#define GPIOLD_RPU_OFFS         0x1b0
+#define GPIOLD_RPD_OFFS         0x1b4
+#define GPIOLD_DV0_OFFS         0x1b8
+#define GPIOLD_DV1_OFFS         0x1bc
+
+#define GPIOAD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOAD_DAT_OFFS         0x1c0
+#define GPIOAD_DOE_OFFS         0x1c4
+#define GPIOAD_FS0_OFFS         0x1c8
+#define GPIOAD_RPU_OFFS         0x1f0
+#define GPIOAD_RPD_OFFS         0x1f4
+#define GPIOAD_DV0_OFFS         0x1f8
+#define GPIOAD_DV1_OFFS         0x1fc
+
+#define GPIOXC_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOXC_DAT_OFFS         0x200
+#define GPIOXC_DOE_OFFS         0x204
+#define GPIOXC_FS0_OFFS         0x208
+#define GPIOXC_RPU_OFFS         0x230
+#define GPIOXC_RPD_OFFS         0x234
+#define GPIOXC_DV0_OFFS         0x238
+#define GPIOXC_DV1_OFFS         0x23c
+
+#define GPIOXC_FS0              __REG(GPIOXC_BASE + GPIOXC_FS0_OFFS)
+
+#define GPIOXC_FS0_CS0          (1 << 26)
+#define GPIOXC_FS0_CS1          (1 << 27)
+
+#define GPIOXD_BASE             (APB1_PERI_BASE_VIRT + 0x5000)
+
+#define GPIOXD_DAT_OFFS         0x240
+#define GPIOXD_FS0_OFFS         0x248
+#define GPIOXD_RPU_OFFS         0x270
+#define GPIOXD_RPD_OFFS         0x274
+#define GPIOXD_DV0_OFFS         0x278
+#define GPIOXD_DV1_OFFS         0x27c
+
+#define GPIOPK_BASE             (APB1_PERI_BASE_VIRT + 0x1c000)
+
+#define GPIOPK_RST_OFFS         0x008
+#define GPIOPK_DAT_OFFS         0x100
+#define GPIOPK_DOE_OFFS         0x104
+#define GPIOPK_FS0_OFFS         0x108
+#define GPIOPK_FS1_OFFS         0x10c
+#define GPIOPK_FS2_OFFS         0x110
+#define GPIOPK_IRQST_OFFS       0x210
+#define GPIOPK_IRQEN_OFFS       0x214
+#define GPIOPK_IRQPOL_OFFS      0x218
+#define GPIOPK_IRQTM0_OFFS      0x21c
+#define GPIOPK_IRQTM1_OFFS      0x220
+#define GPIOPK_CTL_OFFS         0x22c
+
+#define PMGPIO_BASE             (APB1_PERI_BASE_VIRT + 0x10000)
+#define BACKUP_RAM_BASE         PMGPIO_BASE
+
+#define PMGPIO_DAT_OFFS         0x800
+#define PMGPIO_DOE_OFFS         0x804
+#define PMGPIO_FS0_OFFS         0x808
+#define PMGPIO_RPU_OFFS         0x810
+#define PMGPIO_RPD_OFFS         0x814
+#define PMGPIO_DV0_OFFS         0x818
+#define PMGPIO_DV1_OFFS         0x81c
+#define PMGPIO_EE0_OFFS         0x820
+#define PMGPIO_EE1_OFFS         0x824
+#define PMGPIO_CTL_OFFS         0x828
+#define PMGPIO_DI_OFFS          0x82c
+#define PMGPIO_STR_OFFS         0x830
+#define PMGPIO_STF_OFFS         0x834
+#define PMGPIO_POL_OFFS         0x838
+#define PMGPIO_APB_OFFS         0x800
+
+/* Clock controller registers */
+#define CKC_BASE        ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
+
+#define CLKCTRL_OFFS            0x00
+#define PLL0CFG_OFFS            0x04
+#define PLL1CFG_OFFS            0x08
+#define CLKDIVC0_OFFS           0x0c
+
+#define BCLKCTR0_OFFS           0x14
+#define SWRESET0_OFFS           0x18
+
+#define BCLKCTR1_OFFS           0x60
+#define SWRESET1_OFFS           0x64
+#define PWDCTL_OFFS             0x68
+#define PLL2CFG_OFFS            0x6c
+#define CLKDIVC1_OFFS           0x70
+
+#define ACLKREF_OFFS            0x80
+#define ACLKI2C_OFFS            0x84
+#define ACLKSPI0_OFFS           0x88
+#define ACLKSPI1_OFFS           0x8c
+#define ACLKUART0_OFFS          0x90
+#define ACLKUART1_OFFS          0x94
+#define ACLKUART2_OFFS          0x98
+#define ACLKUART3_OFFS          0x9c
+#define ACLKUART4_OFFS          0xa0
+#define ACLKTCT_OFFS            0xa4
+#define ACLKTCX_OFFS            0xa8
+#define ACLKTCZ_OFFS            0xac
+#define ACLKADC_OFFS            0xb0
+#define ACLKDAI0_OFFS           0xb4
+#define ACLKDAI1_OFFS           0xb8
+#define ACLKLCD_OFFS            0xbc
+#define ACLKSPDIF_OFFS          0xc0
+#define ACLKUSBH_OFFS           0xc4
+#define ACLKSDH0_OFFS           0xc8
+#define ACLKSDH1_OFFS           0xcc
+#define ACLKC3DEC_OFFS          0xd0
+#define ACLKEXT_OFFS            0xd4
+#define ACLKCAN0_OFFS           0xd8
+#define ACLKCAN1_OFFS           0xdc
+#define ACLKGSB0_OFFS           0xe0
+#define ACLKGSB1_OFFS           0xe4
+#define ACLKGSB2_OFFS           0xe8
+#define ACLKGSB3_OFFS           0xec
+
+#define PLLxCFG_PD              (1 << 31)
+
+/* CLKCTRL bits */
+#define CLKCTRL_XE              (1 << 31)
+
+/* CLKDIVCx bits */
+#define CLKDIVC0_XTE            (1 << 7)
+#define CLKDIVC0_XE             (1 << 15)
+#define CLKDIVC0_P1E            (1 << 23)
+#define CLKDIVC0_P0E            (1 << 31)
+
+#define CLKDIVC1_P2E            (1 << 7)
+
+/* BCLKCTR0 clock bits */
+#define BCLKCTR0_USBD           (1 << 4)
+#define BCLKCTR0_ECC            (1 << 9)
+#define BCLKCTR0_USBH0          (1 << 11)
+#define BCLKCTR0_NFC            (1 << 16)
+
+/* BCLKCTR1 clock bits */
+#define BCLKCTR1_USBH1          (1 << 20)
+
+/* SWRESET0 bits */
+#define SWRESET0_USBD           (1 << 4)
+#define SWRESET0_USBH0          (1 << 11)
+
+/* SWRESET1 bits */
+#define SWRESET1_USBH1          (1 << 20)
+
+/* System clock sources.
+ * Note: These are the clock sources that serve as parents for
+ * all other clocks. They have no parents themselves.
+ *
+ * These values are used for struct clk->root_id. All clocks
+ * that are not system clock sources have this value set to
+ * CLK_SRC_NOROOT.
+ * The values for system clocks start with CLK_SRC_PLL0 == 0
+ * because this gives us exactly the values needed for the lower
+ * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
+ * defined as -1 to not disturb the order.
+ */
+enum root_clks {
+        CLK_SRC_NOROOT = -1,
+        CLK_SRC_PLL0 = 0,
+        CLK_SRC_PLL1,
+        CLK_SRC_PLL0DIV,
+        CLK_SRC_PLL1DIV,
+        CLK_SRC_XI,
+        CLK_SRC_XIDIV,
+        CLK_SRC_XTI,
+        CLK_SRC_XTIDIV,
+        CLK_SRC_PLL2,
+        CLK_SRC_PLL2DIV,
+        CLK_SRC_PK0,
+        CLK_SRC_PK1,
+        CLK_SRC_PK2,
+        CLK_SRC_PK3,
+        CLK_SRC_PK4,
+        CLK_SRC_48MHZ
+};
+
+#define CLK_SRC_MASK            0xf
+
+/* Bits in ACLK* registers */
+#define ACLK_EN         (1 << 28)
+#define ACLK_SEL_SHIFT          24
+#define ACLK_SEL_MASK           0x0f000000
+#define ACLK_DIV_MASK           0x00000fff
+
+/* System configuration registers */
+
+#define SCFG_BASE               (APB1_PERI_BASE_VIRT + 0x13000)
+
+#define BMI_OFFS                0x00
+#define AHBCON0_OFFS            0x04
+#define APBPWE_OFFS             0x08
+#define DTCMWAIT_OFFS           0x0c
+#define ECCSEL_OFFS             0x10
+#define AHBCON1_OFFS            0x14
+#define SDHCFG_OFFS             0x18
+#define REMAP_OFFS              0x20
+#define LCDSIAE_OFFS            0x24
+#define XMCCFG_OFFS             0xe0
+#define IMCCFG_OFFS             0xe4
+
+/* Values for ECCSEL */
+#define ECCSEL_EXTMEM           0x0
+#define ECCSEL_DTCM             0x1
+#define ECCSEL_INT_SRAM         0x2
+#define ECCSEL_AHB              0x3
+
+/* Bits in XMCCFG */
+#define XMCCFG_NFCE             (1 << 1)
+#define XMCCFG_FDXD             (1 << 2)
+
+/* External memory controller registers */
+
+#define EMC_BASE                EXT_MEM_CTRL_BASE
+
+#define SDCFG_OFFS              0x00
+#define SDFSM_OFFS              0x04
+#define MCFG_OFFS               0x08
+
+#define CSCFG0_OFFS             0x10
+#define CSCFG1_OFFS             0x14
+#define CSCFG2_OFFS             0x18
+#define CSCFG3_OFFS             0x1c
+
+#define MCFG_SDEN               (1 << 4)
+
+#endif /* TCC8K_REGS_H */
diff --git a/arch/arm/plat-tcc/include/mach/timex.h b/arch/arm/plat-tcc/include/mach/timex.h
new file mode 100644
index 00000000000..057acbe651d
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/timex.h
@@ -0,0 +1,5 @@
+/*
+ * A definition needed by arch core code.
+ *
+ */
+#define CLOCK_TICK_RATE         (HZ * 100000UL)
diff --git a/arch/arm/plat-tcc/include/mach/uncompress.h b/arch/arm/plat-tcc/include/mach/uncompress.h
new file mode 100644
index 00000000000..7a3e33a27a3
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/uncompress.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
+ *
+ * This file is licensed under the terms of the GPL version 2.
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/types.h>
+
+#include <mach/tcc8k-regs.h>
+
+unsigned int system_rev;
+
+#define ID_MASK                 0x7fff
+
+static void putc(int c)
+{
+        u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2));
+        u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2));
+
+        while (!(*uart_lsr & UART_LSR_THRE))
+                barrier();
+        *uart_tx = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h
new file mode 100644
index 00000000000..99414d9c2b9
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/*
+ * Author: <linux@telechips.com>
+ * Created: June 10, 2008
+ *
+ * Copyright (C) 2000 Russell King.
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/plat-tcc/system.c b/arch/arm/plat-tcc/system.c
new file mode 100644
index 00000000000..cc208fae3e7
--- /dev/null
+++ b/arch/arm/plat-tcc/system.c
@@ -0,0 +1,25 @@
+/*
+ * System functions for Telechips TCCxxxx SoCs
+ *
+ * Copyright (C) Hans J. Koch <hjk@linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#include <linux/io.h>
+
+#include <mach/tcc8k-regs.h>
+
+/* System reboot */
+void plat_tcc_reboot(void)
+{
+        /* Make sure clocks are on */
+        __raw_writel(0xffffffff, CKC_BASE + BCLKCTR0_OFFS);
+
+        /* Enable watchdog reset */
+        __raw_writel(0x49, TIMER_BASE + TWDCFG_OFFS);
+        /* Wait for reset */
+        while(1)
+                ;
+}