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-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts6
-rw-r--r--arch/arm/mach-tegra/board-paz00.c8
-rw-r--r--arch/arm/mach-tegra/board-paz00.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h10
4 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 1a1d7023b69..825d2957da0 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -46,11 +46,11 @@
46 }; 46 };
47 47
48 serial@70006200 { 48 serial@70006200 {
49 status = "disable"; 49 clock-frequency = <216000000>;
50 }; 50 };
51 51
52 serial@70006300 { 52 serial@70006300 {
53 clock-frequency = <216000000>; 53 status = "disable";
54 }; 54 };
55 55
56 serial@70006400 { 56 serial@70006400 {
@@ -60,7 +60,7 @@
60 sdhci@c8000000 { 60 sdhci@c8000000 {
61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
63 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 63 power-gpios = <&gpio 169 0>; /* gpio PV1 */
64 }; 64 };
65 65
66 sdhci@c8000200 { 66 sdhci@c8000200 {
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fcf4f377b1d..330afdfa247 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
60 .uartclk = 216000000, 60 .uartclk = 216000000,
61 }, { 61 }, {
62 /* serial port on mini-pcie */ 62 /* serial port on mini-pcie */
63 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 63 .membase = IO_ADDRESS(TEGRA_UARTC_BASE),
64 .mapbase = TEGRA_UARTD_BASE, 64 .mapbase = TEGRA_UARTC_BASE,
65 .irq = INT_UARTD, 65 .irq = INT_UARTC,
66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, 66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
67 .type = PORT_TEGRA, 67 .type = PORT_TEGRA,
68 .iotype = UPIO_MEM, 68 .iotype = UPIO_MEM,
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { 174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
175 /* name parent rate enabled */ 175 /* name parent rate enabled */
176 { "uarta", "pll_p", 216000000, true }, 176 { "uarta", "pll_p", 216000000, true },
177 { "uartd", "pll_p", 216000000, true }, 177 { "uartc", "pll_p", 216000000, true },
178 178
179 { "pll_p_out4", "pll_p", 24000000, true }, 179 { "pll_p_out4", "pll_p", 24000000, true },
180 { "usbd", "clk_m", 12000000, false }, 180 { "usbd", "clk_m", 12000000, false },
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index ffa83f580db..3c9f8da37ea 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -22,7 +22,7 @@
22/* SDCARD */ 22/* SDCARD */
23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1
26 26
27/* ULPI */ 27/* ULPI */
28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index d0132e8031a..3c9339058be 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -23,11 +23,6 @@
23 23
24#include <linux/list.h> 24#include <linux/list.h>
25 25
26#if defined(CONFIG_TEGRA_SYSTEM_DMA)
27
28struct tegra_dma_req;
29struct tegra_dma_channel;
30
31#define TEGRA_DMA_REQ_SEL_CNTR 0 26#define TEGRA_DMA_REQ_SEL_CNTR 0
32#define TEGRA_DMA_REQ_SEL_I2S_2 1 27#define TEGRA_DMA_REQ_SEL_I2S_2 1
33#define TEGRA_DMA_REQ_SEL_I2S_1 2 28#define TEGRA_DMA_REQ_SEL_I2S_1 2
@@ -56,6 +51,11 @@ struct tegra_dma_channel;
56#define TEGRA_DMA_REQ_SEL_OWR 25 51#define TEGRA_DMA_REQ_SEL_OWR 25
57#define TEGRA_DMA_REQ_SEL_INVALID 31 52#define TEGRA_DMA_REQ_SEL_INVALID 31
58 53
54#if defined(CONFIG_TEGRA_SYSTEM_DMA)
55
56struct tegra_dma_req;
57struct tegra_dma_channel;
58
59enum tegra_dma_mode { 59enum tegra_dma_mode {
60 TEGRA_DMA_SHARED = 1, 60 TEGRA_DMA_SHARED = 1,
61 TEGRA_DMA_MODE_CONTINOUS = 2, 61 TEGRA_DMA_MODE_CONTINOUS = 2,