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-rw-r--r--arch/arm/plat-pxa/include/plat/dma.h85
-rw-r--r--arch/arm/plat-pxa/include/plat/gpio.h62
-rw-r--r--arch/arm/plat-pxa/include/plat/mfp.h399
3 files changed, 546 insertions, 0 deletions
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h
new file mode 100644
index 00000000000..a7b91dc0685
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/dma.h
@@ -0,0 +1,85 @@
1#ifndef __PLAT_DMA_H
2#define __PLAT_DMA_H
3
4#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
5
6#define DCSR(n) DMAC_REG((n) << 2)
7#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
8#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
9#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
10#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
11#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
12#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
13#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
14 (((n) & 0x3f) << 2))
15
16#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
17#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
18#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
19#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
20#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
21#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
22#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
23#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
24
25#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
26#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
27#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
28#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
29#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
30#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
31#define DCSR_EORINTR (1 << 9) /* The end of Receive */
32
33#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
34#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
35
36#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
37#define DDADR_STOP (1 << 0) /* Stop (read / write) */
38
39#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
40#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
41#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
42#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
43#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
44#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
45#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
46#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
47#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
48#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
49#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
50#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
51#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
52#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
53
54/*
55 * Descriptor structure for PXA's DMA engine
56 * Note: this structure must always be aligned to a 16-byte boundary.
57 */
58
59typedef struct pxa_dma_desc {
60 volatile u32 ddadr; /* Points to the next descriptor + flags */
61 volatile u32 dsadr; /* DSADR value for the current transfer */
62 volatile u32 dtadr; /* DTADR value for the current transfer */
63 volatile u32 dcmd; /* DCMD value for the current transfer */
64} pxa_dma_desc;
65
66typedef enum {
67 DMA_PRIO_HIGH = 0,
68 DMA_PRIO_MEDIUM = 1,
69 DMA_PRIO_LOW = 2
70} pxa_dma_prio;
71
72/*
73 * DMA registration
74 */
75
76int __init pxa_init_dma(int irq, int num_ch);
77
78int pxa_request_dma (char *name,
79 pxa_dma_prio prio,
80 void (*irq_handler)(int, void *),
81 void *data);
82
83void pxa_free_dma (int dma_ch);
84
85#endif /* __PLAT_DMA_H */
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
new file mode 100644
index 00000000000..44248cb926a
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -0,0 +1,62 @@
1#ifndef __PLAT_GPIO_H
2#define __PLAT_GPIO_H
3
4/*
5 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
6 * one set of registers. The register offsets are organized below:
7 *
8 * GPLR GPDR GPSR GPCR GRER GFER GEDR
9 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
10 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
11 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
12 *
13 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
14 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
15 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
16 *
17 * NOTE:
18 * BANK 3 is only available on PXA27x and later processors.
19 * BANK 4 and 5 are only available on PXA935
20 */
21
22#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
23
24#define GPLR_OFFSET 0x00
25#define GPDR_OFFSET 0x0C
26#define GPSR_OFFSET 0x18
27#define GPCR_OFFSET 0x24
28#define GRER_OFFSET 0x30
29#define GFER_OFFSET 0x3C
30#define GEDR_OFFSET 0x48
31
32static inline int gpio_get_value(unsigned gpio)
33{
34 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
35 return GPLR(gpio) & GPIO_bit(gpio);
36 else
37 return __gpio_get_value(gpio);
38}
39
40static inline void gpio_set_value(unsigned gpio, int value)
41{
42 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
43 if (value)
44 GPSR(gpio) = GPIO_bit(gpio);
45 else
46 GPCR(gpio) = GPIO_bit(gpio);
47 } else
48 __gpio_set_value(gpio, value);
49}
50
51#define gpio_cansleep __gpio_cansleep
52
53/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
54 * Those cases currently cause holes in the GPIO number space, the
55 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
56 */
57extern int pxa_last_gpio;
58
59typedef int (*set_wake_t)(unsigned int irq, unsigned int on);
60
61extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
62#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
new file mode 100644
index 00000000000..64019464c8d
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -0,0 +1,399 @@
1/*
2 * arch/arm/plat-pxa/include/plat/mfp.h
3 *
4 * Common Multi-Function Pin Definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * 2007-8-21: eric miao <eric.miao@marvell.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_PLAT_MFP_H
17#define __ASM_PLAT_MFP_H
18
19#define mfp_to_gpio(m) ((m) % 128)
20
21/* list of all the configurable MFP pins */
22enum {
23 MFP_PIN_INVALID = -1,
24
25 MFP_PIN_GPIO0 = 0,
26 MFP_PIN_GPIO1,
27 MFP_PIN_GPIO2,
28 MFP_PIN_GPIO3,
29 MFP_PIN_GPIO4,
30 MFP_PIN_GPIO5,
31 MFP_PIN_GPIO6,
32 MFP_PIN_GPIO7,
33 MFP_PIN_GPIO8,
34 MFP_PIN_GPIO9,
35 MFP_PIN_GPIO10,
36 MFP_PIN_GPIO11,
37 MFP_PIN_GPIO12,
38 MFP_PIN_GPIO13,
39 MFP_PIN_GPIO14,
40 MFP_PIN_GPIO15,
41 MFP_PIN_GPIO16,
42 MFP_PIN_GPIO17,
43 MFP_PIN_GPIO18,
44 MFP_PIN_GPIO19,
45 MFP_PIN_GPIO20,
46 MFP_PIN_GPIO21,
47 MFP_PIN_GPIO22,
48 MFP_PIN_GPIO23,
49 MFP_PIN_GPIO24,
50 MFP_PIN_GPIO25,
51 MFP_PIN_GPIO26,
52 MFP_PIN_GPIO27,
53 MFP_PIN_GPIO28,
54 MFP_PIN_GPIO29,
55 MFP_PIN_GPIO30,
56 MFP_PIN_GPIO31,
57 MFP_PIN_GPIO32,
58 MFP_PIN_GPIO33,
59 MFP_PIN_GPIO34,
60 MFP_PIN_GPIO35,
61 MFP_PIN_GPIO36,
62 MFP_PIN_GPIO37,
63 MFP_PIN_GPIO38,
64 MFP_PIN_GPIO39,
65 MFP_PIN_GPIO40,
66 MFP_PIN_GPIO41,
67 MFP_PIN_GPIO42,
68 MFP_PIN_GPIO43,
69 MFP_PIN_GPIO44,
70 MFP_PIN_GPIO45,
71 MFP_PIN_GPIO46,
72 MFP_PIN_GPIO47,
73 MFP_PIN_GPIO48,
74 MFP_PIN_GPIO49,
75 MFP_PIN_GPIO50,
76 MFP_PIN_GPIO51,
77 MFP_PIN_GPIO52,
78 MFP_PIN_GPIO53,
79 MFP_PIN_GPIO54,
80 MFP_PIN_GPIO55,
81 MFP_PIN_GPIO56,
82 MFP_PIN_GPIO57,
83 MFP_PIN_GPIO58,
84 MFP_PIN_GPIO59,
85 MFP_PIN_GPIO60,
86 MFP_PIN_GPIO61,
87 MFP_PIN_GPIO62,
88 MFP_PIN_GPIO63,
89 MFP_PIN_GPIO64,
90 MFP_PIN_GPIO65,
91 MFP_PIN_GPIO66,
92 MFP_PIN_GPIO67,
93 MFP_PIN_GPIO68,
94 MFP_PIN_GPIO69,
95 MFP_PIN_GPIO70,
96 MFP_PIN_GPIO71,
97 MFP_PIN_GPIO72,
98 MFP_PIN_GPIO73,
99 MFP_PIN_GPIO74,
100 MFP_PIN_GPIO75,
101 MFP_PIN_GPIO76,
102 MFP_PIN_GPIO77,
103 MFP_PIN_GPIO78,
104 MFP_PIN_GPIO79,
105 MFP_PIN_GPIO80,
106 MFP_PIN_GPIO81,
107 MFP_PIN_GPIO82,
108 MFP_PIN_GPIO83,
109 MFP_PIN_GPIO84,
110 MFP_PIN_GPIO85,
111 MFP_PIN_GPIO86,
112 MFP_PIN_GPIO87,
113 MFP_PIN_GPIO88,
114 MFP_PIN_GPIO89,
115 MFP_PIN_GPIO90,
116 MFP_PIN_GPIO91,
117 MFP_PIN_GPIO92,
118 MFP_PIN_GPIO93,
119 MFP_PIN_GPIO94,
120 MFP_PIN_GPIO95,
121 MFP_PIN_GPIO96,
122 MFP_PIN_GPIO97,
123 MFP_PIN_GPIO98,
124 MFP_PIN_GPIO99,
125 MFP_PIN_GPIO100,
126 MFP_PIN_GPIO101,
127 MFP_PIN_GPIO102,
128 MFP_PIN_GPIO103,
129 MFP_PIN_GPIO104,
130 MFP_PIN_GPIO105,
131 MFP_PIN_GPIO106,
132 MFP_PIN_GPIO107,
133 MFP_PIN_GPIO108,
134 MFP_PIN_GPIO109,
135 MFP_PIN_GPIO110,
136 MFP_PIN_GPIO111,
137 MFP_PIN_GPIO112,
138 MFP_PIN_GPIO113,
139 MFP_PIN_GPIO114,
140 MFP_PIN_GPIO115,
141 MFP_PIN_GPIO116,
142 MFP_PIN_GPIO117,
143 MFP_PIN_GPIO118,
144 MFP_PIN_GPIO119,
145 MFP_PIN_GPIO120,
146 MFP_PIN_GPIO121,
147 MFP_PIN_GPIO122,
148 MFP_PIN_GPIO123,
149 MFP_PIN_GPIO124,
150 MFP_PIN_GPIO125,
151 MFP_PIN_GPIO126,
152 MFP_PIN_GPIO127,
153 MFP_PIN_GPIO0_2,
154 MFP_PIN_GPIO1_2,
155 MFP_PIN_GPIO2_2,
156 MFP_PIN_GPIO3_2,
157 MFP_PIN_GPIO4_2,
158 MFP_PIN_GPIO5_2,
159 MFP_PIN_GPIO6_2,
160 MFP_PIN_GPIO7_2,
161 MFP_PIN_GPIO8_2,
162 MFP_PIN_GPIO9_2,
163 MFP_PIN_GPIO10_2,
164 MFP_PIN_GPIO11_2,
165 MFP_PIN_GPIO12_2,
166 MFP_PIN_GPIO13_2,
167 MFP_PIN_GPIO14_2,
168 MFP_PIN_GPIO15_2,
169 MFP_PIN_GPIO16_2,
170 MFP_PIN_GPIO17_2,
171
172 MFP_PIN_ULPI_STP,
173 MFP_PIN_ULPI_NXT,
174 MFP_PIN_ULPI_DIR,
175
176 MFP_PIN_nXCVREN,
177 MFP_PIN_DF_CLE_nOE,
178 MFP_PIN_DF_nADV1_ALE,
179 MFP_PIN_DF_SCLK_E,
180 MFP_PIN_DF_SCLK_S,
181 MFP_PIN_nBE0,
182 MFP_PIN_nBE1,
183 MFP_PIN_DF_nADV2_ALE,
184 MFP_PIN_DF_INT_RnB,
185 MFP_PIN_DF_nCS0,
186 MFP_PIN_DF_nCS1,
187 MFP_PIN_nLUA,
188 MFP_PIN_nLLA,
189 MFP_PIN_DF_nWE,
190 MFP_PIN_DF_ALE_nWE,
191 MFP_PIN_DF_nRE_nOE,
192 MFP_PIN_DF_ADDR0,
193 MFP_PIN_DF_ADDR1,
194 MFP_PIN_DF_ADDR2,
195 MFP_PIN_DF_ADDR3,
196 MFP_PIN_DF_IO0,
197 MFP_PIN_DF_IO1,
198 MFP_PIN_DF_IO2,
199 MFP_PIN_DF_IO3,
200 MFP_PIN_DF_IO4,
201 MFP_PIN_DF_IO5,
202 MFP_PIN_DF_IO6,
203 MFP_PIN_DF_IO7,
204 MFP_PIN_DF_IO8,
205 MFP_PIN_DF_IO9,
206 MFP_PIN_DF_IO10,
207 MFP_PIN_DF_IO11,
208 MFP_PIN_DF_IO12,
209 MFP_PIN_DF_IO13,
210 MFP_PIN_DF_IO14,
211 MFP_PIN_DF_IO15,
212 MFP_PIN_DF_nCS0_SM_nCS2,
213 MFP_PIN_DF_nCS1_SM_nCS3,
214 MFP_PIN_SM_nCS0,
215 MFP_PIN_SM_nCS1,
216 MFP_PIN_DF_WEn,
217 MFP_PIN_DF_REn,
218 MFP_PIN_DF_CLE_SM_OEn,
219 MFP_PIN_DF_ALE_SM_WEn,
220 MFP_PIN_DF_RDY0,
221 MFP_PIN_DF_RDY1,
222
223 MFP_PIN_SM_SCLK,
224 MFP_PIN_SM_BE0,
225 MFP_PIN_SM_BE1,
226 MFP_PIN_SM_ADV,
227 MFP_PIN_SM_ADVMUX,
228 MFP_PIN_SM_RDY,
229
230 MFP_PIN_MMC1_DAT7,
231 MFP_PIN_MMC1_DAT6,
232 MFP_PIN_MMC1_DAT5,
233 MFP_PIN_MMC1_DAT4,
234 MFP_PIN_MMC1_DAT3,
235 MFP_PIN_MMC1_DAT2,
236 MFP_PIN_MMC1_DAT1,
237 MFP_PIN_MMC1_DAT0,
238 MFP_PIN_MMC1_CMD,
239 MFP_PIN_MMC1_CLK,
240 MFP_PIN_MMC1_CD,
241 MFP_PIN_MMC1_WP,
242
243 /* additional pins on PXA930 */
244 MFP_PIN_GSIM_UIO,
245 MFP_PIN_GSIM_UCLK,
246 MFP_PIN_GSIM_UDET,
247 MFP_PIN_GSIM_nURST,
248 MFP_PIN_PMIC_INT,
249 MFP_PIN_RDY,
250
251 MFP_PIN_MAX,
252};
253
254/*
255 * a possible MFP configuration is represented by a 32-bit integer
256 *
257 * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
258 * bit 10..12 - Alternate Function Selection
259 * bit 13..15 - Drive Strength
260 * bit 16..18 - Low Power Mode State
261 * bit 19..20 - Low Power Mode Edge Detection
262 * bit 21..22 - Run Mode Pull State
263 *
264 * to facilitate the definition, the following macros are provided
265 *
266 * MFP_CFG_DEFAULT - default MFP configuration value, with
267 * alternate function = 0,
268 * drive strength = fast 3mA (MFP_DS03X)
269 * low power mode = default
270 * edge detection = none
271 *
272 * MFP_CFG - default MFPR value with alternate function
273 * MFP_CFG_DRV - default MFPR value with alternate function and
274 * pin drive strength
275 * MFP_CFG_LPM - default MFPR value with alternate function and
276 * low power mode
277 * MFP_CFG_X - default MFPR value with alternate function,
278 * pin drive strength and low power mode
279 */
280
281typedef unsigned long mfp_cfg_t;
282
283#define MFP_PIN(x) ((x) & 0x3ff)
284
285#define MFP_AF0 (0x0 << 10)
286#define MFP_AF1 (0x1 << 10)
287#define MFP_AF2 (0x2 << 10)
288#define MFP_AF3 (0x3 << 10)
289#define MFP_AF4 (0x4 << 10)
290#define MFP_AF5 (0x5 << 10)
291#define MFP_AF6 (0x6 << 10)
292#define MFP_AF7 (0x7 << 10)
293#define MFP_AF_MASK (0x7 << 10)
294#define MFP_AF(x) (((x) >> 10) & 0x7)
295
296#define MFP_DS01X (0x0 << 13)
297#define MFP_DS02X (0x1 << 13)
298#define MFP_DS03X (0x2 << 13)
299#define MFP_DS04X (0x3 << 13)
300#define MFP_DS06X (0x4 << 13)
301#define MFP_DS08X (0x5 << 13)
302#define MFP_DS10X (0x6 << 13)
303#define MFP_DS13X (0x7 << 13)
304#define MFP_DS_MASK (0x7 << 13)
305#define MFP_DS(x) (((x) >> 13) & 0x7)
306
307#define MFP_LPM_DEFAULT (0x0 << 16)
308#define MFP_LPM_DRIVE_LOW (0x1 << 16)
309#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
310#define MFP_LPM_PULL_LOW (0x3 << 16)
311#define MFP_LPM_PULL_HIGH (0x4 << 16)
312#define MFP_LPM_FLOAT (0x5 << 16)
313#define MFP_LPM_INPUT (0x6 << 16)
314#define MFP_LPM_STATE_MASK (0x7 << 16)
315#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
316
317#define MFP_LPM_EDGE_NONE (0x0 << 19)
318#define MFP_LPM_EDGE_RISE (0x1 << 19)
319#define MFP_LPM_EDGE_FALL (0x2 << 19)
320#define MFP_LPM_EDGE_BOTH (0x3 << 19)
321#define MFP_LPM_EDGE_MASK (0x3 << 19)
322#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
323
324#define MFP_PULL_NONE (0x0 << 21)
325#define MFP_PULL_LOW (0x1 << 21)
326#define MFP_PULL_HIGH (0x2 << 21)
327#define MFP_PULL_BOTH (0x3 << 21)
328#define MFP_PULL_MASK (0x3 << 21)
329#define MFP_PULL(x) (((x) >> 21) & 0x3)
330
331#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
332 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
333
334#define MFP_CFG(pin, af) \
335 ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
336 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
337
338#define MFP_CFG_DRV(pin, af, drv) \
339 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
340 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
341
342#define MFP_CFG_LPM(pin, af, lpm) \
343 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
344 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
345
346#define MFP_CFG_X(pin, af, drv, lpm) \
347 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
348 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
349
350#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
351/*
352 * each MFP pin will have a MFPR register, since the offset of the
353 * register varies between processors, the processor specific code
354 * should initialize the pin offsets by mfp_init()
355 *
356 * mfp_init_base() - accepts a virtual base for all MFPR registers and
357 * initialize the MFP table to a default state
358 *
359 * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
360 * represents a range of MFP pins from "start" to "end", with the offset
361 * begining at "offset", to define a single pin, let "end" = -1.
362 *
363 * use
364 *
365 * MFP_ADDR_X() to define a range of pins
366 * MFP_ADDR() to define a single pin
367 * MFP_ADDR_END to signal the end of pin offset definitions
368 */
369struct mfp_addr_map {
370 unsigned int start;
371 unsigned int end;
372 unsigned long offset;
373};
374
375#define MFP_ADDR_X(start, end, offset) \
376 { MFP_PIN_##start, MFP_PIN_##end, offset }
377
378#define MFP_ADDR(pin, offset) \
379 { MFP_PIN_##pin, -1, offset }
380
381#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
382
383void __init mfp_init_base(unsigned long mfpr_base);
384void __init mfp_init_addr(struct mfp_addr_map *map);
385
386/*
387 * mfp_{read, write}() - for direct read/write access to the MFPR register
388 * mfp_config() - for configuring a group of MFPR registers
389 * mfp_config_lpm() - configuring all low power MFPR registers for suspend
390 * mfp_config_run() - configuring all run time MFPR registers after resume
391 */
392unsigned long mfp_read(int mfp);
393void mfp_write(int mfp, unsigned long mfpr_val);
394void mfp_config(unsigned long *mfp_cfgs, int num);
395void mfp_config_run(void);
396void mfp_config_lpm(void);
397#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
398
399#endif /* __ASM_PLAT_MFP_H */
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