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-rw-r--r--arch/arm/plat-omap/Kconfig8
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/clock.c1
-rw-r--r--arch/arm/plat-omap/common.c3
-rw-r--r--arch/arm/plat-omap/counter_32k.c1
-rw-r--r--arch/arm/plat-omap/dma.c4
-rw-r--r--arch/arm/plat-omap/dmtimer.c21
-rw-r--r--arch/arm/plat-omap/fb.c334
-rw-r--r--arch/arm/plat-omap/fb.h10
-rw-r--r--arch/arm/plat-omap/include/plat/blizzard.h12
-rw-r--r--arch/arm/plat-omap/include/plat/board-ams-delta.h49
-rw-r--r--arch/arm/plat-omap/include/plat/board.h2
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h9
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h29
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h6
-rw-r--r--arch/arm/plat-omap/include/plat/hwa742.h8
-rw-r--r--arch/arm/plat-omap/include/plat/io.h277
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h10
-rw-r--r--arch/arm/plat-omap/include/plat/keypad.h2
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h333
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap-secure.h8
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h9
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h9
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h1
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h1
-rw-r--r--arch/arm/plat-omap/include/plat/system.h15
-rw-r--r--arch/arm/plat-omap/include/plat/tc.h17
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h1
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h41
-rw-r--r--arch/arm/plat-omap/include/plat/vram.h21
-rw-r--r--arch/arm/plat-omap/mailbox.c2
-rw-r--r--arch/arm/plat-omap/mcbsp.c1361
-rw-r--r--arch/arm/plat-omap/mux.c5
-rw-r--r--arch/arm/plat-omap/omap-pm-noop.c2
-rw-r--r--arch/arm/plat-omap/omap_device.c44
-rw-r--r--arch/arm/plat-omap/sram.c23
-rw-r--r--arch/arm/plat-omap/usb.c4
38 files changed, 192 insertions, 2496 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index aa59f4247dc..8f81503a4df 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -110,14 +110,6 @@ config OMAP_MUX_WARNINGS
110 to change the pin multiplexing setup. When there are no warnings 110 to change the pin multiplexing setup. When there are no warnings
111 printed, it's safe to deselect OMAP_MUX for your product. 111 printed, it's safe to deselect OMAP_MUX for your product.
112 112
113config OMAP_MCBSP
114 bool "McBSP support"
115 depends on ARCH_OMAP
116 default y
117 help
118 Say Y here if you want support for the OMAP Multichannel
119 Buffered Serial Port.
120
121config OMAP_MBOX_FWK 113config OMAP_MBOX_FWK
122 tristate "Mailbox framework support" 114 tristate "Mailbox framework support"
123 depends on ARCH_OMAP 115 depends on ARCH_OMAP
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 9a584614e7e..c0fe2757b69 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -17,8 +17,6 @@ obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
17obj-$(CONFIG_ARCH_OMAP3) += omap_device.o 17obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
18obj-$(CONFIG_ARCH_OMAP4) += omap_device.o 18obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
19 19
20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
21
22obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 20obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
23obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o 21obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
24obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 22obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 567e4b54f24..56b6f8b7053 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -20,7 +20,6 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/mutex.h> 21#include <linux/mutex.h>
22#include <linux/cpufreq.h> 22#include <linux/cpufreq.h>
23#include <linux/debugfs.h>
24#include <linux/io.h> 23#include <linux/io.h>
25 24
26#include <plat/clock.h> 25#include <plat/clock.h>
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 06383b51e65..f1e46ea6b81 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -15,7 +15,6 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
18#include <linux/omapfb.h>
19 18
20#include <plat/common.h> 19#include <plat/common.h>
21#include <plat/board.h> 20#include <plat/board.h>
@@ -65,10 +64,10 @@ const void *__init omap_get_var_config(u16 tag, size_t *len)
65 64
66void __init omap_reserve(void) 65void __init omap_reserve(void)
67{ 66{
68 omapfb_reserve_sdram_memblock();
69 omap_vram_reserve_sdram_memblock(); 67 omap_vram_reserve_sdram_memblock();
70 omap_dsp_reserve_sdram_memblock(); 68 omap_dsp_reserve_sdram_memblock();
71 omap_secure_ram_reserve_memblock(); 69 omap_secure_ram_reserve_memblock();
70 omap_barrier_reserve_memblock();
72} 71}
73 72
74void __init omap_init_consistent_dma_size(void) 73void __init omap_init_consistent_dma_size(void)
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5f0f2292b7f..5068fe5a691 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -21,6 +21,7 @@
21 21
22#include <asm/sched_clock.h> 22#include <asm/sched_clock.h>
23 23
24#include <plat/hardware.h>
24#include <plat/common.h> 25#include <plat/common.h>
25#include <plat/board.h> 26#include <plat/board.h>
26 27
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 002fb4d96bb..74300ae29b7 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -164,6 +164,8 @@ static inline void set_gdma_dev(int req, int dev)
164} 164}
165#else 165#else
166#define set_gdma_dev(req, dev) do {} while (0) 166#define set_gdma_dev(req, dev) do {} while (0)
167#define omap_readl(reg) 0
168#define omap_writel(val, reg) do {} while (0)
167#endif 169#endif
168 170
169void omap_set_dma_priority(int lch, int dst_port, int priority) 171void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -2125,7 +2127,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2125 2127
2126static struct platform_driver omap_system_dma_driver = { 2128static struct platform_driver omap_system_dma_driver = {
2127 .probe = omap_system_dma_probe, 2129 .probe = omap_system_dma_probe,
2128 .remove = omap_system_dma_remove, 2130 .remove = __devexit_p(omap_system_dma_remove),
2129 .driver = { 2131 .driver = {
2130 .name = "omap_dma_system" 2132 .name = "omap_dma_system"
2131 }, 2133 },
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index af3b92be845..652139c0339 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,8 @@
43 43
44#include <plat/dmtimer.h> 44#include <plat/dmtimer.h>
45 45
46#include <mach/hardware.h>
47
46static LIST_HEAD(omap_timer_list); 48static LIST_HEAD(omap_timer_list);
47static DEFINE_SPINLOCK(dm_timer_lock); 49static DEFINE_SPINLOCK(dm_timer_lock);
48 50
@@ -80,9 +82,9 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
80 82
81static void omap_timer_restore_context(struct omap_dm_timer *timer) 83static void omap_timer_restore_context(struct omap_dm_timer *timer)
82{ 84{
83 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET, 85 __raw_writel(timer->context.tiocp_cfg,
84 timer->context.tiocp_cfg); 86 timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
85 if (timer->revision > 1) 87 if (timer->revision == 1)
86 __raw_writel(timer->context.tistat, timer->sys_stat); 88 __raw_writel(timer->context.tistat, timer->sys_stat);
87 89
88 __raw_writel(timer->context.tisr, timer->irq_stat); 90 __raw_writel(timer->context.tisr, timer->irq_stat);
@@ -357,6 +359,19 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
357 359
358 __omap_dm_timer_stop(timer, timer->posted, rate); 360 __omap_dm_timer_stop(timer, timer->posted, rate);
359 361
362 if (timer->loses_context && timer->get_context_loss_count)
363 timer->ctx_loss_count =
364 timer->get_context_loss_count(&timer->pdev->dev);
365
366 /*
367 * Since the register values are computed and written within
368 * __omap_dm_timer_stop, we need to use read to retrieve the
369 * context.
370 */
371 timer->context.tclr =
372 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
373 timer->context.tisr = __raw_readl(timer->irq_stat);
374 omap_dm_timer_disable(timer);
360 return 0; 375 return 0;
361} 376}
362EXPORT_SYMBOL_GPL(omap_dm_timer_stop); 377EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index c9e5d7298c4..dd6f92c99e5 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -34,15 +34,11 @@
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#include <plat/board.h> 36#include <plat/board.h>
37#include <plat/sram.h>
38
39#include "fb.h"
40 37
41#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) 38#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
42 39
40static bool omapfb_lcd_configured;
43static struct omapfb_platform_data omapfb_config; 41static struct omapfb_platform_data omapfb_config;
44static int config_invalid;
45static int configured_regions;
46 42
47static u64 omap_fb_dma_mask = ~(u32)0; 43static u64 omap_fb_dma_mask = ~(u32)0;
48 44
@@ -57,302 +53,21 @@ static struct platform_device omap_fb_device = {
57 .num_resources = 0, 53 .num_resources = 0,
58}; 54};
59 55
60void omapfb_set_platform_data(struct omapfb_platform_data *data) 56void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
61{
62}
63
64static inline int ranges_overlap(unsigned long start1, unsigned long size1,
65 unsigned long start2, unsigned long size2)
66{
67 return (start1 >= start2 && start1 < start2 + size2) ||
68 (start2 >= start1 && start2 < start1 + size1);
69}
70
71static inline int range_included(unsigned long start1, unsigned long size1,
72 unsigned long start2, unsigned long size2)
73{
74 return start1 >= start2 && start1 + size1 <= start2 + size2;
75}
76
77
78/* Check if there is an overlapping region. */
79static int fbmem_region_reserved(unsigned long start, size_t size)
80{
81 struct omapfb_mem_region *rg;
82 int i;
83
84 rg = &omapfb_config.mem_desc.region[0];
85 for (i = 0; i < OMAPFB_PLANE_NUM; i++, rg++) {
86 if (!rg->paddr)
87 /* Empty slot. */
88 continue;
89 if (ranges_overlap(start, size, rg->paddr, rg->size))
90 return 1;
91 }
92 return 0;
93}
94
95/*
96 * Get the region_idx`th region from board config/ATAG and convert it to
97 * our internal format.
98 */
99static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
100{ 57{
101 const struct omap_fbmem_config *conf; 58 omapfb_config.lcd = *config;
102 u32 paddr; 59 omapfb_lcd_configured = true;
103
104 conf = omap_get_nr_config(OMAP_TAG_FBMEM,
105 struct omap_fbmem_config, region_idx);
106 if (conf == NULL)
107 return -ENOENT;
108
109 paddr = conf->start;
110 /*
111 * Low bits encode the page allocation mode, if high bits
112 * are zero. Otherwise we need a page aligned fixed
113 * address.
114 */
115 memset(rg, 0, sizeof(*rg));
116 rg->type = paddr & ~PAGE_MASK;
117 rg->paddr = paddr & PAGE_MASK;
118 rg->size = PAGE_ALIGN(conf->size);
119 return 0;
120} 60}
121 61
122static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type, 62static int __init omap_init_fb(void)
123 unsigned long mem_start,
124 unsigned long mem_size)
125{
126 /*
127 * Check if the configuration specifies the type explicitly.
128 * type = 0 && paddr = 0, a default don't care case maps to
129 * the SDRAM type.
130 */
131 if (rg->type || !rg->paddr)
132 return 0;
133 if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) {
134 rg->type = mem_type;
135 return 0;
136 }
137 /* Can't determine it. */
138 return -1;
139}
140
141static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
142 unsigned long start_avail, unsigned size_avail)
143{ 63{
144 unsigned long paddr = rg->paddr;
145 size_t size = rg->size;
146
147 if (rg->type > OMAPFB_MEMTYPE_MAX) {
148 printk(KERN_ERR
149 "Invalid start address for FB region %d\n", region_idx);
150 return -EINVAL;
151 }
152
153 if (!rg->size) {
154 printk(KERN_ERR "Zero size for FB region %d\n", region_idx);
155 return -EINVAL;
156 }
157
158 if (!paddr)
159 /* Allocate this dynamically, leave paddr 0 for now. */
160 return 0;
161
162 /* 64 /*
163 * Fixed region for the given RAM range. Check if it's already 65 * If the board file has not set the lcd config with
164 * reserved by the FB code or someone else. 66 * omapfb_set_lcd_config(), don't bother registering the omapfb device
165 */ 67 */
166 if (fbmem_region_reserved(paddr, size) || 68 if (!omapfb_lcd_configured)
167 !range_included(paddr, size, start_avail, size_avail)) {
168 printk(KERN_ERR "Trying to use reserved memory "
169 "for FB region %d\n", region_idx);
170 return -EINVAL;
171 }
172
173 return 0;
174}
175
176static int valid_sdram(unsigned long addr, unsigned long size)
177{
178 return memblock_is_region_memory(addr, size);
179}
180
181static int reserve_sdram(unsigned long addr, unsigned long size)
182{
183 if (memblock_is_region_reserved(addr, size))
184 return -EBUSY;
185 if (memblock_reserve(addr, size))
186 return -ENOMEM;
187 return 0;
188}
189
190/*
191 * Called from map_io. We need to call to this early enough so that we
192 * can reserve the fixed SDRAM regions before VM could get hold of them.
193 */
194void __init omapfb_reserve_sdram_memblock(void)
195{
196 unsigned long reserved = 0;
197 int i;
198
199 if (config_invalid)
200 return;
201
202 for (i = 0; ; i++) {
203 struct omapfb_mem_region rg;
204
205 if (get_fbmem_region(i, &rg) < 0)
206 break;
207
208 if (i == OMAPFB_PLANE_NUM) {
209 pr_err("Extraneous FB mem configuration entries\n");
210 config_invalid = 1;
211 return;
212 }
213
214 /* Check if it's our memory type. */
215 if (rg.type != OMAPFB_MEMTYPE_SDRAM)
216 continue;
217
218 /* Check if the region falls within SDRAM */
219 if (rg.paddr && !valid_sdram(rg.paddr, rg.size))
220 continue;
221
222 if (rg.size == 0) {
223 pr_err("Zero size for FB region %d\n", i);
224 config_invalid = 1;
225 return;
226 }
227
228 if (rg.paddr) {
229 if (reserve_sdram(rg.paddr, rg.size)) {
230 pr_err("Trying to use reserved memory for FB region %d\n",
231 i);
232 config_invalid = 1;
233 return;
234 }
235 reserved += rg.size;
236 }
237
238 if (omapfb_config.mem_desc.region[i].size) {
239 pr_err("FB region %d already set\n", i);
240 config_invalid = 1;
241 return;
242 }
243
244 omapfb_config.mem_desc.region[i] = rg;
245 configured_regions++;
246 }
247 omapfb_config.mem_desc.region_cnt = i;
248 if (reserved)
249 pr_info("Reserving %lu bytes SDRAM for frame buffer\n",
250 reserved);
251}
252
253/*
254 * Called at sram init time, before anything is pushed to the SRAM stack.
255 * Because of the stack scheme, we will allocate everything from the
256 * start of the lowest address region to the end of SRAM. This will also
257 * include padding for page alignment and possible holes between regions.
258 *
259 * As opposed to the SDRAM case, we'll also do any dynamic allocations at
260 * this point, since the driver built as a module would have problem with
261 * freeing / reallocating the regions.
262 */
263unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
264 unsigned long sram_vstart,
265 unsigned long sram_size,
266 unsigned long pstart_avail,
267 unsigned long size_avail)
268{
269 struct omapfb_mem_region rg;
270 unsigned long pend_avail;
271 unsigned long reserved;
272 int i;
273
274 if (config_invalid)
275 return 0; 69 return 0;
276 70
277 reserved = 0;
278 pend_avail = pstart_avail + size_avail;
279 for (i = 0; ; i++) {
280 if (get_fbmem_region(i, &rg) < 0)
281 break;
282 if (i == OMAPFB_PLANE_NUM) {
283 printk(KERN_ERR
284 "Extraneous FB mem configuration entries\n");
285 config_invalid = 1;
286 return 0;
287 }
288
289 /* Check if it's our memory type. */
290 if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SRAM,
291 sram_pstart, sram_size) < 0 ||
292 (rg.type != OMAPFB_MEMTYPE_SRAM))
293 continue;
294 BUG_ON(omapfb_config.mem_desc.region[i].size);
295
296 if (check_fbmem_region(i, &rg, pstart_avail, size_avail) < 0) {
297 config_invalid = 1;
298 return 0;
299 }
300
301 if (!rg.paddr) {
302 /* Dynamic allocation */
303 if ((size_avail & PAGE_MASK) < rg.size) {
304 printk("Not enough SRAM for FB region %d\n",
305 i);
306 config_invalid = 1;
307 return 0;
308 }
309 size_avail = (size_avail - rg.size) & PAGE_MASK;
310 rg.paddr = pstart_avail + size_avail;
311 }
312 /* Reserve everything above the start of the region. */
313 if (pend_avail - rg.paddr > reserved)
314 reserved = pend_avail - rg.paddr;
315 size_avail = pend_avail - reserved - pstart_avail;
316
317 /*
318 * We have a kernel mapping for this already, so the
319 * driver won't have to make one.
320 */
321 rg.vaddr = (void *)(sram_vstart + rg.paddr - sram_pstart);
322 omapfb_config.mem_desc.region[i] = rg;
323 configured_regions++;
324 }
325 omapfb_config.mem_desc.region_cnt = i;
326 if (reserved)
327 pr_info("Reserving %lu bytes SRAM for frame buffer\n",
328 reserved);
329 return reserved;
330}
331
332void omapfb_set_ctrl_platform_data(void *data)
333{
334 omapfb_config.ctrl_platform_data = data;
335}
336
337static int __init omap_init_fb(void)
338{
339 const struct omap_lcd_config *conf;
340
341 if (config_invalid)
342 return 0;
343 if (configured_regions != omapfb_config.mem_desc.region_cnt) {
344 printk(KERN_ERR "Invalid FB mem configuration entries\n");
345 return 0;
346 }
347 conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
348 if (conf == NULL) {
349 if (configured_regions)
350 /* FB mem config, but no LCD config? */
351 printk(KERN_ERR "Missing LCD configuration\n");
352 return 0;
353 }
354 omapfb_config.lcd = *conf;
355
356 return platform_device_register(&omap_fb_device); 71 return platform_device_register(&omap_fb_device);
357} 72}
358 73
@@ -374,11 +89,6 @@ static struct platform_device omap_fb_device = {
374 .num_resources = 0, 89 .num_resources = 0,
375}; 90};
376 91
377void omapfb_set_platform_data(struct omapfb_platform_data *data)
378{
379 omapfb_config = *data;
380}
381
382static int __init omap_init_fb(void) 92static int __init omap_init_fb(void)
383{ 93{
384 return platform_device_register(&omap_fb_device); 94 return platform_device_register(&omap_fb_device);
@@ -386,36 +96,10 @@ static int __init omap_init_fb(void)
386 96
387arch_initcall(omap_init_fb); 97arch_initcall(omap_init_fb);
388 98
389void omapfb_reserve_sdram_memblock(void)
390{
391}
392
393unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
394 unsigned long sram_vstart,
395 unsigned long sram_size,
396 unsigned long start_avail,
397 unsigned long size_avail)
398{
399 return 0;
400}
401
402#else 99#else
403 100
404void omapfb_set_platform_data(struct omapfb_platform_data *data) 101void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
405{
406}
407
408void omapfb_reserve_sdram_memblock(void)
409{
410}
411
412unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
413 unsigned long sram_vstart,
414 unsigned long sram_size,
415 unsigned long start_avail,
416 unsigned long size_avail)
417{ 102{
418 return 0;
419} 103}
420 104
421#endif 105#endif
diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h
deleted file mode 100644
index d765d0bd852..00000000000
--- a/arch/arm/plat-omap/fb.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef __PLAT_OMAP_FB_H__
2#define __PLAT_OMAP_FB_H__
3
4extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
5 unsigned long sram_vstart,
6 unsigned long sram_size,
7 unsigned long pstart_avail,
8 unsigned long size_avail);
9
10#endif /* __PLAT_OMAP_FB_H__ */
diff --git a/arch/arm/plat-omap/include/plat/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
deleted file mode 100644
index 56e7f2e7d12..00000000000
--- a/arch/arm/plat-omap/include/plat/blizzard.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _BLIZZARD_H
2#define _BLIZZARD_H
3
4struct blizzard_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected:1;
10};
11
12#endif
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906..ad6f865d1f1 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
@@ -28,33 +28,8 @@
28 28
29#if defined (CONFIG_MACH_AMS_DELTA) 29#if defined (CONFIG_MACH_AMS_DELTA)
30 30
31#define AMS_DELTA_LATCH1_PHYS 0x01000000
32#define AMS_DELTA_LATCH1_VIRT 0xEA000000
33#define AMS_DELTA_MODEM_PHYS 0x04000000
34#define AMS_DELTA_MODEM_VIRT 0xEB000000
35#define AMS_DELTA_LATCH2_PHYS 0x08000000
36#define AMS_DELTA_LATCH2_VIRT 0xEC000000
37
38#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
39#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
40#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
41#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
42#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
43#define AMS_DELTA_LATCH1_LED_VOICE 0x20
44
45#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
46#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
47#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
48#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
49#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
50#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
51#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
52#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
53#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
54#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
55#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400 31#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
56#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800 32#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
57#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
58#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000 33#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
59 34
60#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0 35#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
@@ -66,9 +41,29 @@
66#define AMS_DELTA_GPIO_PIN_CONFIG 11 41#define AMS_DELTA_GPIO_PIN_CONFIG 11
67#define AMS_DELTA_GPIO_PIN_NAND_RB 12 42#define AMS_DELTA_GPIO_PIN_NAND_RB 12
68 43
44#define AMS_DELTA_GPIO_PIN_LCD_VBLEN 240
45#define AMS_DELTA_GPIO_PIN_LCD_NDISP 241
46#define AMS_DELTA_GPIO_PIN_NAND_NCE 242
47#define AMS_DELTA_GPIO_PIN_NAND_NRE 243
48#define AMS_DELTA_GPIO_PIN_NAND_NWP 244
49#define AMS_DELTA_GPIO_PIN_NAND_NWE 245
50#define AMS_DELTA_GPIO_PIN_NAND_ALE 246
51#define AMS_DELTA_GPIO_PIN_NAND_CLE 247
52#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR 248
53#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT 249
54#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN 250
55#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC 251
56#define AMS_DELTA_GPIO_PIN_MODEM_NRESET 252
57#define AMS_DELTA_GPIO_PIN_MODEM_CODEC 253
58
59#define AMS_DELTA_LATCH2_GPIO_BASE AMS_DELTA_GPIO_PIN_LCD_VBLEN
60#define AMS_DELTA_LATCH2_NGPIO 16
61
69#ifndef __ASSEMBLY__ 62#ifndef __ASSEMBLY__
70void ams_delta_latch1_write(u8 mask, u8 value); 63void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value);
71void ams_delta_latch2_write(u16 mask, u16 value); 64#define ams_delta_latch2_write(mask, value) \
65 ams_delta_latch_write(AMS_DELTA_LATCH2_GPIO_BASE, \
66 AMS_DELTA_LATCH2_NGPIO, (mask), (value))
72#endif 67#endif
73 68
74#endif /* CONFIG_MACH_AMS_DELTA */ 69#endif /* CONFIG_MACH_AMS_DELTA */
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 97126dfd288..d5eb4c87db9 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -28,9 +28,7 @@ enum {
28 28
29/* Different peripheral ids */ 29/* Different peripheral ids */
30#define OMAP_TAG_CLOCK 0x4f01 30#define OMAP_TAG_CLOCK 0x4f01
31#define OMAP_TAG_LCD 0x4f05
32#define OMAP_TAG_GPIO_SWITCH 0x4f06 31#define OMAP_TAG_GPIO_SWITCH 0x4f06
33#define OMAP_TAG_FBMEM 0x4f08
34#define OMAP_TAG_STI_CONSOLE 0x4f09 32#define OMAP_TAG_STI_CONSOLE 0x4f09
35#define OMAP_TAG_CAMERA_SENSOR 0x4f0a 33#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
36 34
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 6b51086fce1..dc6a86bf217 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -250,7 +250,6 @@ IS_AM_SUBCLASS(335x, 0x335)
250 * cpu_is_omap2423(): True for OMAP2423 250 * cpu_is_omap2423(): True for OMAP2423
251 * cpu_is_omap2430(): True for OMAP2430 251 * cpu_is_omap2430(): True for OMAP2430
252 * cpu_is_omap3430(): True for OMAP3430 252 * cpu_is_omap3430(): True for OMAP3430
253 * cpu_is_omap4430(): True for OMAP4430
254 * cpu_is_omap3505(): True for OMAP3505 253 * cpu_is_omap3505(): True for OMAP3505
255 * cpu_is_omap3517(): True for OMAP3517 254 * cpu_is_omap3517(): True for OMAP3517
256 */ 255 */
@@ -299,7 +298,6 @@ IS_OMAP_TYPE(3517, 0x3517)
299#define cpu_is_omap3505() 0 298#define cpu_is_omap3505() 0
300#define cpu_is_omap3517() 0 299#define cpu_is_omap3517() 0
301#define cpu_is_omap3430() 0 300#define cpu_is_omap3430() 0
302#define cpu_is_omap4430() 0
303#define cpu_is_omap3630() 0 301#define cpu_is_omap3630() 0
304 302
305/* 303/*
@@ -451,7 +449,12 @@ IS_OMAP_TYPE(3517, 0x3517)
451#define OMAP447X_CLASS 0x44700044 449#define OMAP447X_CLASS 0x44700044
452#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) 450#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
453 451
454void omap2_check_revision(void); 452void omap2xxx_check_revision(void);
453void omap3xxx_check_revision(void);
454void omap4xxx_check_revision(void);
455void omap3xxx_check_features(void);
456void ti81xx_check_features(void);
457void omap4xxx_check_features(void);
455 458
456/* 459/*
457 * Runtime detection of OMAP3 features 460 * Runtime detection of OMAP3 features
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0aed0..cb75b657b04 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -162,13 +162,6 @@
162 IH_MPUIO_BASE + ((nr) & 0x0f) : \ 162 IH_MPUIO_BASE + ((nr) & 0x0f) : \
163 IH_GPIO_BASE + (nr)) 163 IH_GPIO_BASE + (nr))
164 164
165#define METHOD_MPUIO 0
166#define METHOD_GPIO_1510 1
167#define METHOD_GPIO_1610 2
168#define METHOD_GPIO_7XX 3
169#define METHOD_GPIO_24XX 5
170#define METHOD_GPIO_44XX 6
171
172struct omap_gpio_dev_attr { 165struct omap_gpio_dev_attr {
173 int bank_width; /* GPIO bank width */ 166 int bank_width; /* GPIO bank width */
174 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 167 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs {
184 u16 irqstatus; 177 u16 irqstatus;
185 u16 irqstatus2; 178 u16 irqstatus2;
186 u16 irqenable; 179 u16 irqenable;
180 u16 irqenable2;
187 u16 set_irqenable; 181 u16 set_irqenable;
188 u16 clr_irqenable; 182 u16 clr_irqenable;
189 u16 debounce; 183 u16 debounce;
190 u16 debounce_en; 184 u16 debounce_en;
185 u16 ctrl;
186 u16 wkup_en;
187 u16 leveldetect0;
188 u16 leveldetect1;
189 u16 risingdetect;
190 u16 fallingdetect;
191 u16 irqctrl;
192 u16 edgectrl1;
193 u16 edgectrl2;
194 u16 pinctrl;
191 195
192 bool irqenable_inv; 196 bool irqenable_inv;
193}; 197};
@@ -198,19 +202,20 @@ struct omap_gpio_platform_data {
198 int bank_width; /* GPIO bank width */ 202 int bank_width; /* GPIO bank width */
199 int bank_stride; /* Only needed for omap1 MPUIO */ 203 int bank_stride; /* Only needed for omap1 MPUIO */
200 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 204 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
205 bool loses_context; /* whether the bank would ever lose context */
206 bool is_mpuio; /* whether the bank is of type MPUIO */
207 u32 non_wakeup_gpios;
201 208
202 struct omap_gpio_reg_offs *regs; 209 struct omap_gpio_reg_offs *regs;
203};
204 210
205/* TODO: Analyze removing gpio_bank_count usage from driver code */ 211 /* Return context loss count due to PM states changing */
206extern int gpio_bank_count; 212 int (*get_context_loss_count)(struct device *dev);
213};
207 214
208extern void omap2_gpio_prepare_for_idle(int off_mode); 215extern void omap2_gpio_prepare_for_idle(int off_mode);
209extern void omap2_gpio_resume_after_idle(void); 216extern void omap2_gpio_resume_after_idle(void);
210extern void omap_set_gpio_debounce(int gpio, int enable); 217extern void omap_set_gpio_debounce(int gpio, int enable);
211extern void omap_set_gpio_debounce_time(int gpio, int enable); 218extern void omap_set_gpio_debounce_time(int gpio, int enable);
212extern void omap_gpio_save_context(void);
213extern void omap_gpio_restore_context(void);
214/*-------------------------------------------------------------------------*/ 219/*-------------------------------------------------------------------------*/
215 220
216/* Wrappers for "new style" GPIO calls, using the new infrastructure 221/* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c..537b05ae1f5 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -43,6 +43,12 @@
43#endif 43#endif
44#include <plat/serial.h> 44#include <plat/serial.h>
45 45
46#ifdef __ASSEMBLER__
47#define IOMEM(x) (x)
48#else
49#define IOMEM(x) ((void __force __iomem *)(x))
50#endif
51
46/* 52/*
47 * --------------------------------------------------------------------------- 53 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors 54 * Common definitions for all OMAP processors
diff --git a/arch/arm/plat-omap/include/plat/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
deleted file mode 100644
index 886248d32b4..00000000000
--- a/arch/arm/plat-omap/include/plat/hwa742.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef _HWA742_H
2#define _HWA742_H
3
4struct hwa742_platform_data {
5 unsigned te_connected:1;
6};
7
8#endif
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
deleted file mode 100644
index 0696bae1818..00000000000
--- a/arch/arm/plat-omap/include/plat/io.h
+++ /dev/null
@@ -1,277 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/io.h
3 *
4 * IO definitions for TI OMAP processors and boards
5 *
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 * Modifications:
33 * 06-12-1997 RMK Created.
34 * 07-04-1999 RMK Major cleanup
35 */
36
37#ifndef __ASM_ARM_ARCH_IO_H
38#define __ASM_ARM_ARCH_IO_H
39
40#include <mach/hardware.h>
41
42#define IO_SPACE_LIMIT 0xffffffff
43
44/*
45 * We don't actually have real ISA nor PCI buses, but there is so many
46 * drivers out there that might just work if we fake them...
47 */
48#define __io(a) __typesafe_io(a)
49#define __mem_pci(a) (a)
50
51/*
52 * ----------------------------------------------------------------------------
53 * I/O mapping
54 * ----------------------------------------------------------------------------
55 */
56
57#ifdef __ASSEMBLER__
58#define IOMEM(x) (x)
59#else
60#define IOMEM(x) ((void __force __iomem *)(x))
61#endif
62
63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
65
66#define OMAP2_L3_IO_OFFSET 0x90000000
67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
68
69
70#define OMAP2_L4_IO_OFFSET 0xb2000000
71#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
72
73#define OMAP4_L3_IO_OFFSET 0xb4000000
74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
75
76#define AM33XX_L4_WK_IO_OFFSET 0xb5000000
77#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
78
79#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
80#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
81
82#define OMAP4_GPMC_IO_OFFSET 0xa9000000
83#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
84
85#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
86#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
87
88/*
89 * ----------------------------------------------------------------------------
90 * Omap1 specific IO mapping
91 * ----------------------------------------------------------------------------
92 */
93
94#define OMAP1_IO_PHYS 0xFFFB0000
95#define OMAP1_IO_SIZE 0x40000
96#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
97
98/*
99 * ----------------------------------------------------------------------------
100 * Omap2 specific IO mapping
101 * ----------------------------------------------------------------------------
102 */
103
104/* We map both L3 and L4 on OMAP2 */
105#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
106#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
107#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
108#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
109#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
110#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
111
112#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
113#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
114#define L4_WK_243X_SIZE SZ_1M
115#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
116#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
117 /* 0x6e000000 --> 0xfe000000 */
118#define OMAP243X_GPMC_SIZE SZ_1M
119#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
120 /* 0x6D000000 --> 0xfd000000 */
121#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
122#define OMAP243X_SDRC_SIZE SZ_1M
123#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
124 /* 0x6c000000 --> 0xfc000000 */
125#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
126#define OMAP243X_SMS_SIZE SZ_1M
127
128/* 2420 IVA */
129#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
130 /* 0x58000000 --> 0xfc100000 */
131#define DSP_MEM_2420_VIRT 0xfc100000
132#define DSP_MEM_2420_SIZE 0x28000
133#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
134 /* 0x59000000 --> 0xfc128000 */
135#define DSP_IPI_2420_VIRT 0xfc128000
136#define DSP_IPI_2420_SIZE SZ_4K
137#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
138 /* 0x5a000000 --> 0xfc129000 */
139#define DSP_MMU_2420_VIRT 0xfc129000
140#define DSP_MMU_2420_SIZE SZ_4K
141
142/* 2430 IVA2.1 - currently unmapped */
143
144/*
145 * ----------------------------------------------------------------------------
146 * Omap3 specific IO mapping
147 * ----------------------------------------------------------------------------
148 */
149
150/* We map both L3 and L4 on OMAP3 */
151#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
152#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
153#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
154
155#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
156#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
157#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
158
159/*
160 * ----------------------------------------------------------------------------
161 * AM33XX specific IO mapping
162 * ----------------------------------------------------------------------------
163 */
164#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
165#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
166#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
167
168/*
169 * Need to look at the Size 4M for L4.
170 * VPOM3430 was not working for Int controller
171 */
172
173#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
174 /* 0x49000000 --> 0xfb000000 */
175#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
176#define L4_PER_34XX_SIZE SZ_1M
177
178#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
179 /* 0x54000000 --> 0xfe800000 */
180#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
181#define L4_EMU_34XX_SIZE SZ_8M
182
183#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
184 /* 0x6e000000 --> 0xfe000000 */
185#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
186#define OMAP34XX_GPMC_SIZE SZ_1M
187
188#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
189 /* 0x6c000000 --> 0xfc000000 */
190#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
191#define OMAP343X_SMS_SIZE SZ_1M
192
193#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
194 /* 0x6D000000 --> 0xfd000000 */
195#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
196#define OMAP343X_SDRC_SIZE SZ_1M
197
198/* 3430 IVA - currently unmapped */
199
200/*
201 * ----------------------------------------------------------------------------
202 * Omap4 specific IO mapping
203 * ----------------------------------------------------------------------------
204 */
205
206/* We map both L3 and L4 on OMAP4 */
207#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
208#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
209#define L3_44XX_SIZE SZ_1M
210
211#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
212#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
213#define L4_44XX_SIZE SZ_4M
214
215#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
216 /* 0x48000000 --> 0xfa000000 */
217#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
218#define L4_PER_44XX_SIZE SZ_4M
219
220#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
221 /* 0x49000000 --> 0xfb000000 */
222#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
223#define L4_ABE_44XX_SIZE SZ_1M
224
225#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
226 /* 0x54000000 --> 0xfe800000 */
227#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
228#define L4_EMU_44XX_SIZE SZ_8M
229
230#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
231 /* 0x50000000 --> 0xf9000000 */
232#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
233#define OMAP44XX_GPMC_SIZE SZ_1M
234
235
236#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
237 /* 0x4c000000 --> 0xfd100000 */
238#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
239#define OMAP44XX_EMIF1_SIZE SZ_1M
240
241#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
242 /* 0x4d000000 --> 0xfd200000 */
243#define OMAP44XX_EMIF2_SIZE SZ_1M
244#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
245
246#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
247 /* 0x4e000000 --> 0xfd300000 */
248#define OMAP44XX_DMM_SIZE SZ_1M
249#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
250/*
251 * ----------------------------------------------------------------------------
252 * Omap specific register access
253 * ----------------------------------------------------------------------------
254 */
255
256#ifndef __ASSEMBLER__
257
258/*
259 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
260 */
261
262extern u8 omap_readb(u32 pa);
263extern u16 omap_readw(u32 pa);
264extern u32 omap_readl(u32 pa);
265extern void omap_writeb(u8 v, u32 pa);
266extern void omap_writew(u16 v, u32 pa);
267extern void omap_writel(u32 v, u32 pa);
268
269struct omap_sdrc_params;
270extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
271 struct omap_sdrc_params *sdrc_cs1);
272
273extern void __init omap_init_consistent_dma_size(void);
274
275#endif
276
277#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2efd6454bce..37bbbbb981b 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,8 +428,16 @@
428#define OMAP_GPMC_NR_IRQS 8 428#define OMAP_GPMC_NR_IRQS 8
429#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) 429#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
430 430
431/* PRCM IRQ handler */
432#ifdef CONFIG_ARCH_OMAP2PLUS
433#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
434#define OMAP_PRCM_NR_IRQS 64
435#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
436#else
437#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
438#endif
431 439
432#define NR_IRQS OMAP_GPMC_IRQ_END 440#define NR_IRQS OMAP_PRCM_IRQ_END
433 441
434#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 442#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
435 443
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 793ce9d5329..a6b21eddb21 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -12,6 +12,8 @@
12 12
13#ifndef CONFIG_ARCH_OMAP1 13#ifndef CONFIG_ARCH_OMAP1
14#warning Please update the board to use matrix-keypad driver 14#warning Please update the board to use matrix-keypad driver
15#define omap_readw(reg) 0
16#define omap_writew(val, reg) do {} while (0)
15#endif 17#endif
16#include <linux/input/matrix_keypad.h> 18#include <linux/input/matrix_keypad.h>
17 19
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 8fa74e2c9d6..18814127809 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -27,271 +27,10 @@
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29 29
30/* macro for building platform_device for McBSP ports */
31#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
32static struct platform_device omap_mcbsp##port_nr = { \
33 .name = "omap-mcbsp-dai", \
34 .id = port_nr - 1, \
35}
36
37#define MCBSP_CONFIG_TYPE2 0x2 30#define MCBSP_CONFIG_TYPE2 0x2
38#define MCBSP_CONFIG_TYPE3 0x3 31#define MCBSP_CONFIG_TYPE3 0x3
39#define MCBSP_CONFIG_TYPE4 0x4 32#define MCBSP_CONFIG_TYPE4 0x4
40 33
41/* McBSP register numbers. Register address offset = num * reg_step */
42enum {
43 /* Common registers */
44 OMAP_MCBSP_REG_SPCR2 = 4,
45 OMAP_MCBSP_REG_SPCR1,
46 OMAP_MCBSP_REG_RCR2,
47 OMAP_MCBSP_REG_RCR1,
48 OMAP_MCBSP_REG_XCR2,
49 OMAP_MCBSP_REG_XCR1,
50 OMAP_MCBSP_REG_SRGR2,
51 OMAP_MCBSP_REG_SRGR1,
52 OMAP_MCBSP_REG_MCR2,
53 OMAP_MCBSP_REG_MCR1,
54 OMAP_MCBSP_REG_RCERA,
55 OMAP_MCBSP_REG_RCERB,
56 OMAP_MCBSP_REG_XCERA,
57 OMAP_MCBSP_REG_XCERB,
58 OMAP_MCBSP_REG_PCR0,
59 OMAP_MCBSP_REG_RCERC,
60 OMAP_MCBSP_REG_RCERD,
61 OMAP_MCBSP_REG_XCERC,
62 OMAP_MCBSP_REG_XCERD,
63 OMAP_MCBSP_REG_RCERE,
64 OMAP_MCBSP_REG_RCERF,
65 OMAP_MCBSP_REG_XCERE,
66 OMAP_MCBSP_REG_XCERF,
67 OMAP_MCBSP_REG_RCERG,
68 OMAP_MCBSP_REG_RCERH,
69 OMAP_MCBSP_REG_XCERG,
70 OMAP_MCBSP_REG_XCERH,
71
72 /* OMAP1-OMAP2420 registers */
73 OMAP_MCBSP_REG_DRR2 = 0,
74 OMAP_MCBSP_REG_DRR1,
75 OMAP_MCBSP_REG_DXR2,
76 OMAP_MCBSP_REG_DXR1,
77
78 /* OMAP2430 and onwards */
79 OMAP_MCBSP_REG_DRR = 0,
80 OMAP_MCBSP_REG_DXR = 2,
81 OMAP_MCBSP_REG_SYSCON = 35,
82 OMAP_MCBSP_REG_THRSH2,
83 OMAP_MCBSP_REG_THRSH1,
84 OMAP_MCBSP_REG_IRQST = 40,
85 OMAP_MCBSP_REG_IRQEN,
86 OMAP_MCBSP_REG_WAKEUPEN,
87 OMAP_MCBSP_REG_XCCR,
88 OMAP_MCBSP_REG_RCCR,
89 OMAP_MCBSP_REG_XBUFFSTAT,
90 OMAP_MCBSP_REG_RBUFFSTAT,
91 OMAP_MCBSP_REG_SSELCR,
92};
93
94/* OMAP3 sidetone control registers */
95#define OMAP_ST_REG_REV 0x00
96#define OMAP_ST_REG_SYSCONFIG 0x10
97#define OMAP_ST_REG_IRQSTATUS 0x18
98#define OMAP_ST_REG_IRQENABLE 0x1C
99#define OMAP_ST_REG_SGAINCR 0x24
100#define OMAP_ST_REG_SFIRCR 0x28
101#define OMAP_ST_REG_SSELCR 0x2C
102
103/************************** McBSP SPCR1 bit definitions ***********************/
104#define RRST 0x0001
105#define RRDY 0x0002
106#define RFULL 0x0004
107#define RSYNC_ERR 0x0008
108#define RINTM(value) ((value)<<4) /* bits 4:5 */
109#define ABIS 0x0040
110#define DXENA 0x0080
111#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
112#define RJUST(value) ((value)<<13) /* bits 13:14 */
113#define ALB 0x8000
114#define DLB 0x8000
115
116/************************** McBSP SPCR2 bit definitions ***********************/
117#define XRST 0x0001
118#define XRDY 0x0002
119#define XEMPTY 0x0004
120#define XSYNC_ERR 0x0008
121#define XINTM(value) ((value)<<4) /* bits 4:5 */
122#define GRST 0x0040
123#define FRST 0x0080
124#define SOFT 0x0100
125#define FREE 0x0200
126
127/************************** McBSP PCR bit definitions *************************/
128#define CLKRP 0x0001
129#define CLKXP 0x0002
130#define FSRP 0x0004
131#define FSXP 0x0008
132#define DR_STAT 0x0010
133#define DX_STAT 0x0020
134#define CLKS_STAT 0x0040
135#define SCLKME 0x0080
136#define CLKRM 0x0100
137#define CLKXM 0x0200
138#define FSRM 0x0400
139#define FSXM 0x0800
140#define RIOEN 0x1000
141#define XIOEN 0x2000
142#define IDLE_EN 0x4000
143
144/************************** McBSP RCR1 bit definitions ************************/
145#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
146#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
147
148/************************** McBSP XCR1 bit definitions ************************/
149#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
150#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
151
152/*************************** McBSP RCR2 bit definitions ***********************/
153#define RDATDLY(value) (value) /* Bits 0:1 */
154#define RFIG 0x0004
155#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
156#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
157#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
158#define RPHASE 0x8000
159
160/*************************** McBSP XCR2 bit definitions ***********************/
161#define XDATDLY(value) (value) /* Bits 0:1 */
162#define XFIG 0x0004
163#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
164#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
165#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
166#define XPHASE 0x8000
167
168/************************* McBSP SRGR1 bit definitions ************************/
169#define CLKGDV(value) (value) /* Bits 0:7 */
170#define FWID(value) ((value)<<8) /* Bits 8:15 */
171
172/************************* McBSP SRGR2 bit definitions ************************/
173#define FPER(value) (value) /* Bits 0:11 */
174#define FSGM 0x1000
175#define CLKSM 0x2000
176#define CLKSP 0x4000
177#define GSYNC 0x8000
178
179/************************* McBSP MCR1 bit definitions *************************/
180#define RMCM 0x0001
181#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
182#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
183#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
184
185/************************* McBSP MCR2 bit definitions *************************/
186#define XMCM(value) (value) /* Bits 0:1 */
187#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
188#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
189#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
190
191/*********************** McBSP XCCR bit definitions *************************/
192#define EXTCLKGATE 0x8000
193#define PPCONNECT 0x4000
194#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
195#define XFULL_CYCLE 0x0800
196#define DILB 0x0020
197#define XDMAEN 0x0008
198#define XDISABLE 0x0001
199
200/********************** McBSP RCCR bit definitions *************************/
201#define RFULL_CYCLE 0x0800
202#define RDMAEN 0x0008
203#define RDISABLE 0x0001
204
205/********************** McBSP SYSCONFIG bit definitions ********************/
206#define CLOCKACTIVITY(value) ((value)<<8)
207#define SIDLEMODE(value) ((value)<<3)
208#define ENAWAKEUP 0x0004
209#define SOFTRST 0x0002
210
211/********************** McBSP SSELCR bit definitions ***********************/
212#define SIDETONEEN 0x0400
213
214/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
215#define ST_AUTOIDLE 0x0001
216
217/********************** McBSP Sidetone SGAINCR bit definitions *************/
218#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
219#define ST_CH0GAIN(value) (value) /* Bits 0:15 */
220
221/********************** McBSP Sidetone SFIRCR bit definitions **************/
222#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
223
224/********************** McBSP Sidetone SSELCR bit definitions **************/
225#define ST_COEFFWRDONE 0x0004
226#define ST_COEFFWREN 0x0002
227#define ST_SIDETONEEN 0x0001
228
229/********************** McBSP DMA operating modes **************************/
230#define MCBSP_DMA_MODE_ELEMENT 0
231#define MCBSP_DMA_MODE_THRESHOLD 1
232#define MCBSP_DMA_MODE_FRAME 2
233
234/********************** McBSP WAKEUPEN bit definitions *********************/
235#define XEMPTYEOFEN 0x4000
236#define XRDYEN 0x0400
237#define XEOFEN 0x0200
238#define XFSXEN 0x0100
239#define XSYNCERREN 0x0080
240#define RRDYEN 0x0008
241#define REOFEN 0x0004
242#define RFSREN 0x0002
243#define RSYNCERREN 0x0001
244
245/* CLKR signal muxing options */
246#define CLKR_SRC_CLKR 0
247#define CLKR_SRC_CLKX 1
248
249/* FSR signal muxing options */
250#define FSR_SRC_FSR 0
251#define FSR_SRC_FSX 1
252
253/* McBSP functional clock sources */
254#define MCBSP_CLKS_PRCM_SRC 0
255#define MCBSP_CLKS_PAD_SRC 1
256
257/* we don't do multichannel for now */
258struct omap_mcbsp_reg_cfg {
259 u16 spcr2;
260 u16 spcr1;
261 u16 rcr2;
262 u16 rcr1;
263 u16 xcr2;
264 u16 xcr1;
265 u16 srgr2;
266 u16 srgr1;
267 u16 mcr2;
268 u16 mcr1;
269 u16 pcr0;
270 u16 rcerc;
271 u16 rcerd;
272 u16 xcerc;
273 u16 xcerd;
274 u16 rcere;
275 u16 rcerf;
276 u16 xcere;
277 u16 xcerf;
278 u16 rcerg;
279 u16 rcerh;
280 u16 xcerg;
281 u16 xcerh;
282 u16 xccr;
283 u16 rccr;
284};
285
286typedef enum {
287 OMAP_MCBSP_WORD_8 = 0,
288 OMAP_MCBSP_WORD_12,
289 OMAP_MCBSP_WORD_16,
290 OMAP_MCBSP_WORD_20,
291 OMAP_MCBSP_WORD_24,
292 OMAP_MCBSP_WORD_32,
293} omap_mcbsp_word_length;
294
295/* Platform specific configuration */ 34/* Platform specific configuration */
296struct omap_mcbsp_ops { 35struct omap_mcbsp_ops {
297 void (*request)(unsigned int); 36 void (*request)(unsigned int);
@@ -312,43 +51,6 @@ struct omap_mcbsp_platform_data {
312 int (*mux_signal)(struct device *dev, const char *signal, const char *src); 51 int (*mux_signal)(struct device *dev, const char *signal, const char *src);
313}; 52};
314 53
315struct omap_mcbsp_st_data {
316 void __iomem *io_base_st;
317 bool running;
318 bool enabled;
319 s16 taps[128]; /* Sidetone filter coefficients */
320 int nr_taps; /* Number of filter coefficients in use */
321 s16 ch0gain;
322 s16 ch1gain;
323};
324
325struct omap_mcbsp {
326 struct device *dev;
327 unsigned long phys_base;
328 unsigned long phys_dma_base;
329 void __iomem *io_base;
330 u8 id;
331 u8 free;
332
333 int rx_irq;
334 int tx_irq;
335
336 /* DMA stuff */
337 u8 dma_rx_sync;
338 u8 dma_tx_sync;
339
340 /* Protect the field .free, while checking if the mcbsp is in use */
341 spinlock_t lock;
342 struct omap_mcbsp_platform_data *pdata;
343 struct clk *fclk;
344 struct omap_mcbsp_st_data *st_data;
345 int dma_op_mode;
346 u16 max_tx_thres;
347 u16 max_rx_thres;
348 void *reg_cache;
349 int reg_cache_size;
350};
351
352/** 54/**
353 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod 55 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
354 * @sidetone: name of the sidetone device 56 * @sidetone: name of the sidetone device
@@ -357,39 +59,4 @@ struct omap_mcbsp_dev_attr {
357 const char *sidetone; 59 const char *sidetone;
358}; 60};
359 61
360extern struct omap_mcbsp **mcbsp_ptr;
361extern int omap_mcbsp_count;
362
363int omap_mcbsp_init(void);
364void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
365void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
366void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
367u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
368u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
369u16 omap_mcbsp_get_fifo_size(unsigned int id);
370u16 omap_mcbsp_get_tx_delay(unsigned int id);
371u16 omap_mcbsp_get_rx_delay(unsigned int id);
372int omap_mcbsp_get_dma_op_mode(unsigned int id);
373int omap_mcbsp_request(unsigned int id);
374void omap_mcbsp_free(unsigned int id);
375void omap_mcbsp_start(unsigned int id, int tx, int rx);
376void omap_mcbsp_stop(unsigned int id, int tx, int rx);
377
378/* McBSP functional clock source changing function */
379extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
380
381/* McBSP signal muxing API */
382void omap2_mcbsp1_mux_clkr_src(u8 mux);
383void omap2_mcbsp1_mux_fsr_src(u8 mux);
384
385int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
386int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
387
388/* Sidetone specific API */
389int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
390int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
391int omap_st_enable(unsigned int id);
392int omap_st_disable(unsigned int id);
393int omap_st_is_enabled(unsigned int id);
394
395#endif 62#endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 3d51b18131c..a357eb26bd2 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -18,9 +18,6 @@ struct omap2_mcspi_dev_attr {
18 18
19struct omap2_mcspi_device_config { 19struct omap2_mcspi_device_config {
20 unsigned turbo_mode:1; 20 unsigned turbo_mode:1;
21
22 /* Do we want one channel enabled at the same time? */
23 unsigned single_channel:1;
24}; 21};
25 22
26#endif 23#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 64f9d1c7f1b..8c7994ce986 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,11 +3,17 @@
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5 5
6#ifdef CONFIG_ARCH_OMAP2PLUS 6#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
7extern int omap_secure_ram_reserve_memblock(void); 7extern int omap_secure_ram_reserve_memblock(void);
8#else 8#else
9static inline void omap_secure_ram_reserve_memblock(void) 9static inline void omap_secure_ram_reserve_memblock(void)
10{ } 10{ }
11#endif 11#endif
12 12
13#ifdef CONFIG_OMAP4_ERRATA_I688
14extern int omap_barrier_reserve_memblock(void);
15#else
16static inline void omap_barrier_reserve_memblock(void)
17{ }
18#endif
13#endif /* __OMAP_SECURE_H__ */ 19#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 9fe6c878323..8ad0a377a54 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,15 +1,6 @@
1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H 1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H 2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
3 3
4#include <linux/input/matrix_keypad.h>
5
6struct omap4_keypad_platform_data {
7 const struct matrix_keymap_data *keymap_data;
8
9 u8 rows;
10 u8 cols;
11};
12
13extern int omap4_keyboard_init(struct omap4_keypad_platform_data *, 4extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
14 struct omap_board_data *); 5 struct omap_board_data *);
15#endif 6#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 51423d2727a..4327b2c90c3 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,7 +36,7 @@
36 36
37#include <plat/omap_hwmod.h> 37#include <plat/omap_hwmod.h>
38 38
39extern struct device omap_device_parent; 39extern struct dev_pm_domain omap_device_pm_domain;
40 40
41/* omap_device._state values */ 41/* omap_device._state values */
42#define OMAP_DEVICE_STATE_UNKNOWN 0 42#define OMAP_DEVICE_STATE_UNKNOWN 0
@@ -100,6 +100,13 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
100 struct omap_device_pm_latency *pm_lats, 100 struct omap_device_pm_latency *pm_lats,
101 int pm_lats_cnt, int is_early_device); 101 int pm_lats_cnt, int is_early_device);
102 102
103struct omap_device *omap_device_alloc(struct platform_device *pdev,
104 struct omap_hwmod **ohs, int oh_cnt,
105 struct omap_device_pm_latency *pm_lats,
106 int pm_lats_cnt);
107void omap_device_delete(struct omap_device *od);
108int omap_device_register(struct platform_device *pdev);
109
103void __iomem *omap_device_get_rt_va(struct omap_device *od); 110void __iomem *omap_device_get_rt_va(struct omap_device *od);
104struct device *omap_device_get_by_hwmod_name(const char *oh_name); 111struct device *omap_device_get_by_hwmod_name(const char *oh_name);
105 112
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 198d1e6a4a6..b073e5f2b19 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -110,7 +110,6 @@ struct omap_board_data;
110struct omap_uart_port_info; 110struct omap_uart_port_info;
111 111
112extern void omap_serial_init(void); 112extern void omap_serial_init(void);
113extern int omap_uart_can_sleep(void);
114extern void omap_serial_board_init(struct omap_uart_port_info *platform_data); 113extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
115extern void omap_serial_init_port(struct omap_board_data *bdata, 114extern void omap_serial_init_port(struct omap_board_data *bdata,
116 struct omap_uart_port_info *platform_data); 115 struct omap_uart_port_info *platform_data);
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 75aa1b2bef5..227ae265755 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -101,4 +101,5 @@ static inline void omap_push_sram_idle(void) {}
101#else 101#else
102#define OMAP4_SRAM_PA 0x40300000 102#define OMAP4_SRAM_PA 0x40300000
103#endif 103#endif
104#define AM33XX_SRAM_PA 0x40300000
104#endif 105#endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
deleted file mode 100644
index 8e5ebd74b12..00000000000
--- a/arch/arm/plat-omap/include/plat/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copied from arch/arm/mach-sa1100/include/mach/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
4 */
5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H
7
8#include <asm/proc-fns.h>
9
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
14
15#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9..1b4b2da8620 100644
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
@@ -84,23 +84,6 @@
84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) 84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) 85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
86 86
87/* Almost all documentation for chip and board memory maps assumes
88 * BM is clear. Most devel boards have a switch to control booting
89 * from NOR flash (using external chipselect 3) rather than mask ROM,
90 * which uses BM to interchange the physical CS0 and CS3 addresses.
91 */
92static inline u32 omap_cs0_phys(void)
93{
94 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
95 ? OMAP_CS3_PHYS : 0;
96}
97
98static inline u32 omap_cs3_phys(void)
99{
100 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
101 ? 0 : OMAP_CS3_PHYS;
102}
103
104#endif /* __ASSEMBLER__ */ 87#endif /* __ASSEMBLER__ */
105 88
106#endif /* __ASM_ARCH_TC_H */ 89#endif /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 6ee90495ca4..cc3f11ba7a9 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -160,6 +160,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
160 DEBUG_LL_OMAP3(3, igep0020); 160 DEBUG_LL_OMAP3(3, igep0020);
161 DEBUG_LL_OMAP3(3, igep0030); 161 DEBUG_LL_OMAP3(3, igep0030);
162 DEBUG_LL_OMAP3(3, nokia_rm680); 162 DEBUG_LL_OMAP3(3, nokia_rm680);
163 DEBUG_LL_OMAP3(3, nokia_rm696);
163 DEBUG_LL_OMAP3(3, nokia_rx51); 164 DEBUG_LL_OMAP3(3, nokia_rx51);
164 DEBUG_LL_OMAP3(3, omap3517evm); 165 DEBUG_LL_OMAP3(3, omap3517evm);
165 DEBUG_LL_OMAP3(3, omap3_beagle); 166 DEBUG_LL_OMAP3(3, omap3_beagle);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index dc864b580da..d0fc9f4dc15 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,6 +3,7 @@
3#ifndef __ASM_ARCH_OMAP_USB_H 3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H 4#define __ASM_ARCH_OMAP_USB_H
5 5
6#include <linux/io.h>
6#include <linux/usb/musb.h> 7#include <linux/usb/musb.h>
7#include <plat/board.h> 8#include <plat/board.h>
8 9
@@ -105,6 +106,46 @@ extern int omap4430_phy_set_clk(struct device *dev, int on);
105extern int omap4430_phy_init(struct device *dev); 106extern int omap4430_phy_init(struct device *dev);
106extern int omap4430_phy_exit(struct device *dev); 107extern int omap4430_phy_exit(struct device *dev);
107extern int omap4430_phy_suspend(struct device *dev, int suspend); 108extern int omap4430_phy_suspend(struct device *dev, int suspend);
109
110/*
111 * NOTE: Please update omap USB drivers to use ioremap + read/write
112 */
113
114#define OMAP2_L4_IO_OFFSET 0xb2000000
115#define IOMEM(x) ((void __force __iomem *)(x))
116#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
117
118static inline u8 omap_readb(u32 pa)
119{
120 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
121}
122
123static inline u16 omap_readw(u32 pa)
124{
125 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
126}
127
128static inline u32 omap_readl(u32 pa)
129{
130 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
131}
132
133static inline void omap_writeb(u8 v, u32 pa)
134{
135 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
136}
137
138
139static inline void omap_writew(u16 v, u32 pa)
140{
141 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
142}
143
144static inline void omap_writel(u32 v, u32 pa)
145{
146 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
147}
148
108#endif 149#endif
109 150
110extern void am35x_musb_reset(void); 151extern void am35x_musb_reset(void);
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
index 0aa4ecd12c7..4d65b7d06e6 100644
--- a/arch/arm/plat-omap/include/plat/vram.h
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -23,40 +23,21 @@
23 23
24#include <linux/types.h> 24#include <linux/types.h>
25 25
26#define OMAP_VRAM_MEMTYPE_SDRAM 0
27#define OMAP_VRAM_MEMTYPE_SRAM 1
28#define OMAP_VRAM_MEMTYPE_MAX 1
29
30extern int omap_vram_add_region(unsigned long paddr, size_t size); 26extern int omap_vram_add_region(unsigned long paddr, size_t size);
31extern int omap_vram_free(unsigned long paddr, size_t size); 27extern int omap_vram_free(unsigned long paddr, size_t size);
32extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr); 28extern int omap_vram_alloc(size_t size, unsigned long *paddr);
33extern int omap_vram_reserve(unsigned long paddr, size_t size); 29extern int omap_vram_reserve(unsigned long paddr, size_t size);
34extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram, 30extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
35 unsigned long *largest_free_block); 31 unsigned long *largest_free_block);
36 32
37#ifdef CONFIG_OMAP2_VRAM 33#ifdef CONFIG_OMAP2_VRAM
38extern void omap_vram_set_sdram_vram(u32 size, u32 start); 34extern void omap_vram_set_sdram_vram(u32 size, u32 start);
39extern void omap_vram_set_sram_vram(u32 size, u32 start);
40 35
41extern void omap_vram_reserve_sdram_memblock(void); 36extern void omap_vram_reserve_sdram_memblock(void);
42extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
43 unsigned long sram_vstart,
44 unsigned long sram_size,
45 unsigned long pstart_avail,
46 unsigned long size_avail);
47#else 37#else
48static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { } 38static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
49static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
50 39
51static inline void omap_vram_reserve_sdram_memblock(void) { } 40static inline void omap_vram_reserve_sdram_memblock(void) { }
52static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
53 unsigned long sram_vstart,
54 unsigned long sram_size,
55 unsigned long pstart_avail,
56 unsigned long size_avail)
57{
58 return 0;
59}
60#endif 41#endif
61 42
62#endif 43#endif
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ad80112c227..ad32621aa52 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -307,7 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
307 if (!--mbox->use_count) { 307 if (!--mbox->use_count) {
308 free_irq(mbox->irq, mbox); 308 free_irq(mbox->irq, mbox);
309 tasklet_kill(&mbox->txq->tasklet); 309 tasklet_kill(&mbox->txq->tasklet);
310 flush_work_sync(&mbox->rxq->work); 310 flush_work_sync(&mbox->rxq->work);
311 mbox_queue_free(mbox->txq); 311 mbox_queue_free(mbox->txq);
312 mbox_queue_free(mbox->rxq); 312 mbox_queue_free(mbox->rxq);
313 } 313 }
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
deleted file mode 100644
index 4b15cd7926d..00000000000
--- a/arch/arm/plat-omap/mcbsp.c
+++ /dev/null
@@ -1,1361 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25
26#include <plat/mcbsp.h>
27#include <linux/pm_runtime.h>
28
29struct omap_mcbsp **mcbsp_ptr;
30int omap_mcbsp_count;
31
32#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
33#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
34
35static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
36{
37 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
38
39 if (mcbsp->pdata->reg_size == 2) {
40 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
41 __raw_writew((u16)val, addr);
42 } else {
43 ((u32 *)mcbsp->reg_cache)[reg] = val;
44 __raw_writel(val, addr);
45 }
46}
47
48static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
49{
50 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
51
52 if (mcbsp->pdata->reg_size == 2) {
53 return !from_cache ? __raw_readw(addr) :
54 ((u16 *)mcbsp->reg_cache)[reg];
55 } else {
56 return !from_cache ? __raw_readl(addr) :
57 ((u32 *)mcbsp->reg_cache)[reg];
58 }
59}
60
61static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
62{
63 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
64}
65
66static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
67{
68 return __raw_readl(mcbsp->st_data->io_base_st + reg);
69}
70
71#define MCBSP_READ(mcbsp, reg) \
72 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
73#define MCBSP_WRITE(mcbsp, reg, val) \
74 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
75#define MCBSP_READ_CACHE(mcbsp, reg) \
76 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
77
78#define MCBSP_ST_READ(mcbsp, reg) \
79 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
80#define MCBSP_ST_WRITE(mcbsp, reg, val) \
81 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
82
83static void omap_mcbsp_dump_reg(u8 id)
84{
85 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
86
87 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
88 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
89 MCBSP_READ(mcbsp, DRR2));
90 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
91 MCBSP_READ(mcbsp, DRR1));
92 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
93 MCBSP_READ(mcbsp, DXR2));
94 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
95 MCBSP_READ(mcbsp, DXR1));
96 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
97 MCBSP_READ(mcbsp, SPCR2));
98 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
99 MCBSP_READ(mcbsp, SPCR1));
100 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
101 MCBSP_READ(mcbsp, RCR2));
102 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
103 MCBSP_READ(mcbsp, RCR1));
104 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
105 MCBSP_READ(mcbsp, XCR2));
106 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
107 MCBSP_READ(mcbsp, XCR1));
108 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
109 MCBSP_READ(mcbsp, SRGR2));
110 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
111 MCBSP_READ(mcbsp, SRGR1));
112 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
113 MCBSP_READ(mcbsp, PCR0));
114 dev_dbg(mcbsp->dev, "***********************\n");
115}
116
117static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
118{
119 struct omap_mcbsp *mcbsp_tx = dev_id;
120 u16 irqst_spcr2;
121
122 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
123 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
124
125 if (irqst_spcr2 & XSYNC_ERR) {
126 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
127 irqst_spcr2);
128 /* Writing zero to XSYNC_ERR clears the IRQ */
129 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
130 }
131
132 return IRQ_HANDLED;
133}
134
135static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
136{
137 struct omap_mcbsp *mcbsp_rx = dev_id;
138 u16 irqst_spcr1;
139
140 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
141 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
142
143 if (irqst_spcr1 & RSYNC_ERR) {
144 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
145 irqst_spcr1);
146 /* Writing zero to RSYNC_ERR clears the IRQ */
147 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
148 }
149
150 return IRQ_HANDLED;
151}
152
153/*
154 * omap_mcbsp_config simply write a config to the
155 * appropriate McBSP.
156 * You either call this function or set the McBSP registers
157 * by yourself before calling omap_mcbsp_start().
158 */
159void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
160{
161 struct omap_mcbsp *mcbsp;
162
163 if (!omap_mcbsp_check_valid_id(id)) {
164 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
165 return;
166 }
167 mcbsp = id_to_mcbsp_ptr(id);
168
169 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
170 mcbsp->id, mcbsp->phys_base);
171
172 /* We write the given config */
173 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
174 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
175 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
176 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
177 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
178 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
179 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
180 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
181 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
182 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
183 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
184 if (mcbsp->pdata->has_ccr) {
185 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
186 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
187 }
188}
189EXPORT_SYMBOL(omap_mcbsp_config);
190
191/**
192 * omap_mcbsp_dma_params - returns the dma channel number
193 * @id - mcbsp id
194 * @stream - indicates the direction of data flow (rx or tx)
195 *
196 * Returns the dma channel number for the rx channel or tx channel
197 * based on the value of @stream for the requested mcbsp given by @id
198 */
199int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
200{
201 struct omap_mcbsp *mcbsp;
202
203 if (!omap_mcbsp_check_valid_id(id)) {
204 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
205 return -ENODEV;
206 }
207 mcbsp = id_to_mcbsp_ptr(id);
208
209 if (stream)
210 return mcbsp->dma_rx_sync;
211 else
212 return mcbsp->dma_tx_sync;
213}
214EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
215
216/**
217 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
218 * @id - mcbsp id
219 * @stream - indicates the direction of data flow (rx or tx)
220 *
221 * Returns the address of mcbsp data transmit register or data receive register
222 * to be used by DMA for transferring/receiving data based on the value of
223 * @stream for the requested mcbsp given by @id
224 */
225int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
226{
227 struct omap_mcbsp *mcbsp;
228 int data_reg;
229
230 if (!omap_mcbsp_check_valid_id(id)) {
231 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
232 return -ENODEV;
233 }
234 mcbsp = id_to_mcbsp_ptr(id);
235
236 if (mcbsp->pdata->reg_size == 2) {
237 if (stream)
238 data_reg = OMAP_MCBSP_REG_DRR1;
239 else
240 data_reg = OMAP_MCBSP_REG_DXR1;
241 } else {
242 if (stream)
243 data_reg = OMAP_MCBSP_REG_DRR;
244 else
245 data_reg = OMAP_MCBSP_REG_DXR;
246 }
247
248 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
249}
250EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
251
252static void omap_st_on(struct omap_mcbsp *mcbsp)
253{
254 unsigned int w;
255
256 if (mcbsp->pdata->enable_st_clock)
257 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
258
259 /* Enable McBSP Sidetone */
260 w = MCBSP_READ(mcbsp, SSELCR);
261 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
262
263 /* Enable Sidetone from Sidetone Core */
264 w = MCBSP_ST_READ(mcbsp, SSELCR);
265 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
266}
267
268static void omap_st_off(struct omap_mcbsp *mcbsp)
269{
270 unsigned int w;
271
272 w = MCBSP_ST_READ(mcbsp, SSELCR);
273 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
274
275 w = MCBSP_READ(mcbsp, SSELCR);
276 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
277
278 if (mcbsp->pdata->enable_st_clock)
279 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
280}
281
282static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
283{
284 u16 val, i;
285
286 val = MCBSP_ST_READ(mcbsp, SSELCR);
287
288 if (val & ST_COEFFWREN)
289 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
290
291 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
292
293 for (i = 0; i < 128; i++)
294 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
295
296 i = 0;
297
298 val = MCBSP_ST_READ(mcbsp, SSELCR);
299 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
300 val = MCBSP_ST_READ(mcbsp, SSELCR);
301
302 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
303
304 if (i == 1000)
305 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
306}
307
308static void omap_st_chgain(struct omap_mcbsp *mcbsp)
309{
310 u16 w;
311 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
312
313 w = MCBSP_ST_READ(mcbsp, SSELCR);
314
315 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
316 ST_CH1GAIN(st_data->ch1gain));
317}
318
319int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
320{
321 struct omap_mcbsp *mcbsp;
322 struct omap_mcbsp_st_data *st_data;
323 int ret = 0;
324
325 if (!omap_mcbsp_check_valid_id(id)) {
326 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
327 return -ENODEV;
328 }
329
330 mcbsp = id_to_mcbsp_ptr(id);
331 st_data = mcbsp->st_data;
332
333 if (!st_data)
334 return -ENOENT;
335
336 spin_lock_irq(&mcbsp->lock);
337 if (channel == 0)
338 st_data->ch0gain = chgain;
339 else if (channel == 1)
340 st_data->ch1gain = chgain;
341 else
342 ret = -EINVAL;
343
344 if (st_data->enabled)
345 omap_st_chgain(mcbsp);
346 spin_unlock_irq(&mcbsp->lock);
347
348 return ret;
349}
350EXPORT_SYMBOL(omap_st_set_chgain);
351
352int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
353{
354 struct omap_mcbsp *mcbsp;
355 struct omap_mcbsp_st_data *st_data;
356 int ret = 0;
357
358 if (!omap_mcbsp_check_valid_id(id)) {
359 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
360 return -ENODEV;
361 }
362
363 mcbsp = id_to_mcbsp_ptr(id);
364 st_data = mcbsp->st_data;
365
366 if (!st_data)
367 return -ENOENT;
368
369 spin_lock_irq(&mcbsp->lock);
370 if (channel == 0)
371 *chgain = st_data->ch0gain;
372 else if (channel == 1)
373 *chgain = st_data->ch1gain;
374 else
375 ret = -EINVAL;
376 spin_unlock_irq(&mcbsp->lock);
377
378 return ret;
379}
380EXPORT_SYMBOL(omap_st_get_chgain);
381
382static int omap_st_start(struct omap_mcbsp *mcbsp)
383{
384 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
385
386 if (st_data && st_data->enabled && !st_data->running) {
387 omap_st_fir_write(mcbsp, st_data->taps);
388 omap_st_chgain(mcbsp);
389
390 if (!mcbsp->free) {
391 omap_st_on(mcbsp);
392 st_data->running = 1;
393 }
394 }
395
396 return 0;
397}
398
399int omap_st_enable(unsigned int id)
400{
401 struct omap_mcbsp *mcbsp;
402 struct omap_mcbsp_st_data *st_data;
403
404 if (!omap_mcbsp_check_valid_id(id)) {
405 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
406 return -ENODEV;
407 }
408
409 mcbsp = id_to_mcbsp_ptr(id);
410 st_data = mcbsp->st_data;
411
412 if (!st_data)
413 return -ENODEV;
414
415 spin_lock_irq(&mcbsp->lock);
416 st_data->enabled = 1;
417 omap_st_start(mcbsp);
418 spin_unlock_irq(&mcbsp->lock);
419
420 return 0;
421}
422EXPORT_SYMBOL(omap_st_enable);
423
424static int omap_st_stop(struct omap_mcbsp *mcbsp)
425{
426 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
427
428 if (st_data && st_data->running) {
429 if (!mcbsp->free) {
430 omap_st_off(mcbsp);
431 st_data->running = 0;
432 }
433 }
434
435 return 0;
436}
437
438int omap_st_disable(unsigned int id)
439{
440 struct omap_mcbsp *mcbsp;
441 struct omap_mcbsp_st_data *st_data;
442 int ret = 0;
443
444 if (!omap_mcbsp_check_valid_id(id)) {
445 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
446 return -ENODEV;
447 }
448
449 mcbsp = id_to_mcbsp_ptr(id);
450 st_data = mcbsp->st_data;
451
452 if (!st_data)
453 return -ENODEV;
454
455 spin_lock_irq(&mcbsp->lock);
456 omap_st_stop(mcbsp);
457 st_data->enabled = 0;
458 spin_unlock_irq(&mcbsp->lock);
459
460 return ret;
461}
462EXPORT_SYMBOL(omap_st_disable);
463
464int omap_st_is_enabled(unsigned int id)
465{
466 struct omap_mcbsp *mcbsp;
467 struct omap_mcbsp_st_data *st_data;
468
469 if (!omap_mcbsp_check_valid_id(id)) {
470 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
471 return -ENODEV;
472 }
473
474 mcbsp = id_to_mcbsp_ptr(id);
475 st_data = mcbsp->st_data;
476
477 if (!st_data)
478 return -ENODEV;
479
480
481 return st_data->enabled;
482}
483EXPORT_SYMBOL(omap_st_is_enabled);
484
485/*
486 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
487 * The threshold parameter is 1 based, and it is converted (threshold - 1)
488 * for the THRSH2 register.
489 */
490void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
491{
492 struct omap_mcbsp *mcbsp;
493
494 if (!omap_mcbsp_check_valid_id(id)) {
495 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
496 return;
497 }
498 mcbsp = id_to_mcbsp_ptr(id);
499 if (mcbsp->pdata->buffer_size == 0)
500 return;
501
502 if (threshold && threshold <= mcbsp->max_tx_thres)
503 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
504}
505EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
506
507/*
508 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
509 * The threshold parameter is 1 based, and it is converted (threshold - 1)
510 * for the THRSH1 register.
511 */
512void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
513{
514 struct omap_mcbsp *mcbsp;
515
516 if (!omap_mcbsp_check_valid_id(id)) {
517 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
518 return;
519 }
520 mcbsp = id_to_mcbsp_ptr(id);
521 if (mcbsp->pdata->buffer_size == 0)
522 return;
523
524 if (threshold && threshold <= mcbsp->max_rx_thres)
525 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
526}
527EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
528
529/*
530 * omap_mcbsp_get_max_tx_thres just return the current configured
531 * maximum threshold for transmission
532 */
533u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
534{
535 struct omap_mcbsp *mcbsp;
536
537 if (!omap_mcbsp_check_valid_id(id)) {
538 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
539 return -ENODEV;
540 }
541 mcbsp = id_to_mcbsp_ptr(id);
542
543 return mcbsp->max_tx_thres;
544}
545EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
546
547/*
548 * omap_mcbsp_get_max_rx_thres just return the current configured
549 * maximum threshold for reception
550 */
551u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
552{
553 struct omap_mcbsp *mcbsp;
554
555 if (!omap_mcbsp_check_valid_id(id)) {
556 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
557 return -ENODEV;
558 }
559 mcbsp = id_to_mcbsp_ptr(id);
560
561 return mcbsp->max_rx_thres;
562}
563EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
564
565u16 omap_mcbsp_get_fifo_size(unsigned int id)
566{
567 struct omap_mcbsp *mcbsp;
568
569 if (!omap_mcbsp_check_valid_id(id)) {
570 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
571 return -ENODEV;
572 }
573 mcbsp = id_to_mcbsp_ptr(id);
574
575 return mcbsp->pdata->buffer_size;
576}
577EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
578
579/*
580 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
581 */
582u16 omap_mcbsp_get_tx_delay(unsigned int id)
583{
584 struct omap_mcbsp *mcbsp;
585 u16 buffstat;
586
587 if (!omap_mcbsp_check_valid_id(id)) {
588 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
589 return -ENODEV;
590 }
591 mcbsp = id_to_mcbsp_ptr(id);
592 if (mcbsp->pdata->buffer_size == 0)
593 return 0;
594
595 /* Returns the number of free locations in the buffer */
596 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
597
598 /* Number of slots are different in McBSP ports */
599 return mcbsp->pdata->buffer_size - buffstat;
600}
601EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
602
603/*
604 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
605 * to reach the threshold value (when the DMA will be triggered to read it)
606 */
607u16 omap_mcbsp_get_rx_delay(unsigned int id)
608{
609 struct omap_mcbsp *mcbsp;
610 u16 buffstat, threshold;
611
612 if (!omap_mcbsp_check_valid_id(id)) {
613 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
614 return -ENODEV;
615 }
616 mcbsp = id_to_mcbsp_ptr(id);
617 if (mcbsp->pdata->buffer_size == 0)
618 return 0;
619
620 /* Returns the number of used locations in the buffer */
621 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
622 /* RX threshold */
623 threshold = MCBSP_READ(mcbsp, THRSH1);
624
625 /* Return the number of location till we reach the threshold limit */
626 if (threshold <= buffstat)
627 return 0;
628 else
629 return threshold - buffstat;
630}
631EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
632
633/*
634 * omap_mcbsp_get_dma_op_mode just return the current configured
635 * operating mode for the mcbsp channel
636 */
637int omap_mcbsp_get_dma_op_mode(unsigned int id)
638{
639 struct omap_mcbsp *mcbsp;
640 int dma_op_mode;
641
642 if (!omap_mcbsp_check_valid_id(id)) {
643 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
644 return -ENODEV;
645 }
646 mcbsp = id_to_mcbsp_ptr(id);
647
648 dma_op_mode = mcbsp->dma_op_mode;
649
650 return dma_op_mode;
651}
652EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
653
654int omap_mcbsp_request(unsigned int id)
655{
656 struct omap_mcbsp *mcbsp;
657 void *reg_cache;
658 int err;
659
660 if (!omap_mcbsp_check_valid_id(id)) {
661 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
662 return -ENODEV;
663 }
664 mcbsp = id_to_mcbsp_ptr(id);
665
666 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
667 if (!reg_cache) {
668 return -ENOMEM;
669 }
670
671 spin_lock(&mcbsp->lock);
672 if (!mcbsp->free) {
673 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
674 mcbsp->id);
675 err = -EBUSY;
676 goto err_kfree;
677 }
678
679 mcbsp->free = false;
680 mcbsp->reg_cache = reg_cache;
681 spin_unlock(&mcbsp->lock);
682
683 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
684 mcbsp->pdata->ops->request(id);
685
686 pm_runtime_get_sync(mcbsp->dev);
687
688 /* Enable wakeup behavior */
689 if (mcbsp->pdata->has_wakeup)
690 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
691
692 /*
693 * Make sure that transmitter, receiver and sample-rate generator are
694 * not running before activating IRQs.
695 */
696 MCBSP_WRITE(mcbsp, SPCR1, 0);
697 MCBSP_WRITE(mcbsp, SPCR2, 0);
698
699 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
700 0, "McBSP", (void *)mcbsp);
701 if (err != 0) {
702 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
703 "for McBSP%d\n", mcbsp->tx_irq,
704 mcbsp->id);
705 goto err_clk_disable;
706 }
707
708 if (mcbsp->rx_irq) {
709 err = request_irq(mcbsp->rx_irq,
710 omap_mcbsp_rx_irq_handler,
711 0, "McBSP", (void *)mcbsp);
712 if (err != 0) {
713 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
714 "for McBSP%d\n", mcbsp->rx_irq,
715 mcbsp->id);
716 goto err_free_irq;
717 }
718 }
719
720 return 0;
721err_free_irq:
722 free_irq(mcbsp->tx_irq, (void *)mcbsp);
723err_clk_disable:
724 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
725 mcbsp->pdata->ops->free(id);
726
727 /* Disable wakeup behavior */
728 if (mcbsp->pdata->has_wakeup)
729 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
730
731 pm_runtime_put_sync(mcbsp->dev);
732
733 spin_lock(&mcbsp->lock);
734 mcbsp->free = true;
735 mcbsp->reg_cache = NULL;
736err_kfree:
737 spin_unlock(&mcbsp->lock);
738 kfree(reg_cache);
739
740 return err;
741}
742EXPORT_SYMBOL(omap_mcbsp_request);
743
744void omap_mcbsp_free(unsigned int id)
745{
746 struct omap_mcbsp *mcbsp;
747 void *reg_cache;
748
749 if (!omap_mcbsp_check_valid_id(id)) {
750 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
751 return;
752 }
753 mcbsp = id_to_mcbsp_ptr(id);
754
755 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
756 mcbsp->pdata->ops->free(id);
757
758 /* Disable wakeup behavior */
759 if (mcbsp->pdata->has_wakeup)
760 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
761
762 pm_runtime_put_sync(mcbsp->dev);
763
764 if (mcbsp->rx_irq)
765 free_irq(mcbsp->rx_irq, (void *)mcbsp);
766 free_irq(mcbsp->tx_irq, (void *)mcbsp);
767
768 reg_cache = mcbsp->reg_cache;
769
770 spin_lock(&mcbsp->lock);
771 if (mcbsp->free)
772 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
773 else
774 mcbsp->free = true;
775 mcbsp->reg_cache = NULL;
776 spin_unlock(&mcbsp->lock);
777
778 if (reg_cache)
779 kfree(reg_cache);
780}
781EXPORT_SYMBOL(omap_mcbsp_free);
782
783/*
784 * Here we start the McBSP, by enabling transmitter, receiver or both.
785 * If no transmitter or receiver is active prior calling, then sample-rate
786 * generator and frame sync are started.
787 */
788void omap_mcbsp_start(unsigned int id, int tx, int rx)
789{
790 struct omap_mcbsp *mcbsp;
791 int enable_srg = 0;
792 u16 w;
793
794 if (!omap_mcbsp_check_valid_id(id)) {
795 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
796 return;
797 }
798 mcbsp = id_to_mcbsp_ptr(id);
799
800 if (mcbsp->st_data)
801 omap_st_start(mcbsp);
802
803 /* Only enable SRG, if McBSP is master */
804 w = MCBSP_READ_CACHE(mcbsp, PCR0);
805 if (w & (FSXM | FSRM | CLKXM | CLKRM))
806 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
807 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
808
809 if (enable_srg) {
810 /* Start the sample generator */
811 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
812 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
813 }
814
815 /* Enable transmitter and receiver */
816 tx &= 1;
817 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
818 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
819
820 rx &= 1;
821 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
822 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
823
824 /*
825 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
826 * REVISIT: 100us may give enough time for two CLKSRG, however
827 * due to some unknown PM related, clock gating etc. reason it
828 * is now at 500us.
829 */
830 udelay(500);
831
832 if (enable_srg) {
833 /* Start frame sync */
834 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
835 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
836 }
837
838 if (mcbsp->pdata->has_ccr) {
839 /* Release the transmitter and receiver */
840 w = MCBSP_READ_CACHE(mcbsp, XCCR);
841 w &= ~(tx ? XDISABLE : 0);
842 MCBSP_WRITE(mcbsp, XCCR, w);
843 w = MCBSP_READ_CACHE(mcbsp, RCCR);
844 w &= ~(rx ? RDISABLE : 0);
845 MCBSP_WRITE(mcbsp, RCCR, w);
846 }
847
848 /* Dump McBSP Regs */
849 omap_mcbsp_dump_reg(id);
850}
851EXPORT_SYMBOL(omap_mcbsp_start);
852
853void omap_mcbsp_stop(unsigned int id, int tx, int rx)
854{
855 struct omap_mcbsp *mcbsp;
856 int idle;
857 u16 w;
858
859 if (!omap_mcbsp_check_valid_id(id)) {
860 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
861 return;
862 }
863
864 mcbsp = id_to_mcbsp_ptr(id);
865
866 /* Reset transmitter */
867 tx &= 1;
868 if (mcbsp->pdata->has_ccr) {
869 w = MCBSP_READ_CACHE(mcbsp, XCCR);
870 w |= (tx ? XDISABLE : 0);
871 MCBSP_WRITE(mcbsp, XCCR, w);
872 }
873 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
874 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
875
876 /* Reset receiver */
877 rx &= 1;
878 if (mcbsp->pdata->has_ccr) {
879 w = MCBSP_READ_CACHE(mcbsp, RCCR);
880 w |= (rx ? RDISABLE : 0);
881 MCBSP_WRITE(mcbsp, RCCR, w);
882 }
883 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
884 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
885
886 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
887 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
888
889 if (idle) {
890 /* Reset the sample rate generator */
891 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
892 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
893 }
894
895 if (mcbsp->st_data)
896 omap_st_stop(mcbsp);
897}
898EXPORT_SYMBOL(omap_mcbsp_stop);
899
900int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
901{
902 struct omap_mcbsp *mcbsp;
903 const char *src;
904
905 if (!omap_mcbsp_check_valid_id(id)) {
906 pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
907 return -EINVAL;
908 }
909 mcbsp = id_to_mcbsp_ptr(id);
910
911 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
912 src = "clks_ext";
913 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
914 src = "clks_fclk";
915 else
916 return -EINVAL;
917
918 if (mcbsp->pdata->set_clk_src)
919 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
920 else
921 return -EINVAL;
922}
923EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
924
925void omap2_mcbsp1_mux_clkr_src(u8 mux)
926{
927 struct omap_mcbsp *mcbsp;
928 const char *src;
929
930 if (mux == CLKR_SRC_CLKR)
931 src = "clkr";
932 else if (mux == CLKR_SRC_CLKX)
933 src = "clkx";
934 else
935 return;
936
937 mcbsp = id_to_mcbsp_ptr(0);
938 if (mcbsp->pdata->mux_signal)
939 mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
940}
941EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
942
943void omap2_mcbsp1_mux_fsr_src(u8 mux)
944{
945 struct omap_mcbsp *mcbsp;
946 const char *src;
947
948 if (mux == FSR_SRC_FSR)
949 src = "fsr";
950 else if (mux == FSR_SRC_FSX)
951 src = "fsx";
952 else
953 return;
954
955 mcbsp = id_to_mcbsp_ptr(0);
956 if (mcbsp->pdata->mux_signal)
957 mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
958}
959EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
960
961#define max_thres(m) (mcbsp->pdata->buffer_size)
962#define valid_threshold(m, val) ((val) <= max_thres(m))
963#define THRESHOLD_PROP_BUILDER(prop) \
964static ssize_t prop##_show(struct device *dev, \
965 struct device_attribute *attr, char *buf) \
966{ \
967 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
968 \
969 return sprintf(buf, "%u\n", mcbsp->prop); \
970} \
971 \
972static ssize_t prop##_store(struct device *dev, \
973 struct device_attribute *attr, \
974 const char *buf, size_t size) \
975{ \
976 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
977 unsigned long val; \
978 int status; \
979 \
980 status = strict_strtoul(buf, 0, &val); \
981 if (status) \
982 return status; \
983 \
984 if (!valid_threshold(mcbsp, val)) \
985 return -EDOM; \
986 \
987 mcbsp->prop = val; \
988 return size; \
989} \
990 \
991static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
992
993THRESHOLD_PROP_BUILDER(max_tx_thres);
994THRESHOLD_PROP_BUILDER(max_rx_thres);
995
996static const char *dma_op_modes[] = {
997 "element", "threshold", "frame",
998};
999
1000static ssize_t dma_op_mode_show(struct device *dev,
1001 struct device_attribute *attr, char *buf)
1002{
1003 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1004 int dma_op_mode, i = 0;
1005 ssize_t len = 0;
1006 const char * const *s;
1007
1008 dma_op_mode = mcbsp->dma_op_mode;
1009
1010 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1011 if (dma_op_mode == i)
1012 len += sprintf(buf + len, "[%s] ", *s);
1013 else
1014 len += sprintf(buf + len, "%s ", *s);
1015 }
1016 len += sprintf(buf + len, "\n");
1017
1018 return len;
1019}
1020
1021static ssize_t dma_op_mode_store(struct device *dev,
1022 struct device_attribute *attr,
1023 const char *buf, size_t size)
1024{
1025 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1026 const char * const *s;
1027 int i = 0;
1028
1029 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1030 if (sysfs_streq(buf, *s))
1031 break;
1032
1033 if (i == ARRAY_SIZE(dma_op_modes))
1034 return -EINVAL;
1035
1036 spin_lock_irq(&mcbsp->lock);
1037 if (!mcbsp->free) {
1038 size = -EBUSY;
1039 goto unlock;
1040 }
1041 mcbsp->dma_op_mode = i;
1042
1043unlock:
1044 spin_unlock_irq(&mcbsp->lock);
1045
1046 return size;
1047}
1048
1049static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1050
1051static const struct attribute *additional_attrs[] = {
1052 &dev_attr_max_tx_thres.attr,
1053 &dev_attr_max_rx_thres.attr,
1054 &dev_attr_dma_op_mode.attr,
1055 NULL,
1056};
1057
1058static const struct attribute_group additional_attr_group = {
1059 .attrs = (struct attribute **)additional_attrs,
1060};
1061
1062static ssize_t st_taps_show(struct device *dev,
1063 struct device_attribute *attr, char *buf)
1064{
1065 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1066 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1067 ssize_t status = 0;
1068 int i;
1069
1070 spin_lock_irq(&mcbsp->lock);
1071 for (i = 0; i < st_data->nr_taps; i++)
1072 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1073 st_data->taps[i]);
1074 if (i)
1075 status += sprintf(&buf[status], "\n");
1076 spin_unlock_irq(&mcbsp->lock);
1077
1078 return status;
1079}
1080
1081static ssize_t st_taps_store(struct device *dev,
1082 struct device_attribute *attr,
1083 const char *buf, size_t size)
1084{
1085 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1086 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1087 int val, tmp, status, i = 0;
1088
1089 spin_lock_irq(&mcbsp->lock);
1090 memset(st_data->taps, 0, sizeof(st_data->taps));
1091 st_data->nr_taps = 0;
1092
1093 do {
1094 status = sscanf(buf, "%d%n", &val, &tmp);
1095 if (status < 0 || status == 0) {
1096 size = -EINVAL;
1097 goto out;
1098 }
1099 if (val < -32768 || val > 32767) {
1100 size = -EINVAL;
1101 goto out;
1102 }
1103 st_data->taps[i++] = val;
1104 buf += tmp;
1105 if (*buf != ',')
1106 break;
1107 buf++;
1108 } while (1);
1109
1110 st_data->nr_taps = i;
1111
1112out:
1113 spin_unlock_irq(&mcbsp->lock);
1114
1115 return size;
1116}
1117
1118static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1119
1120static const struct attribute *sidetone_attrs[] = {
1121 &dev_attr_st_taps.attr,
1122 NULL,
1123};
1124
1125static const struct attribute_group sidetone_attr_group = {
1126 .attrs = (struct attribute **)sidetone_attrs,
1127};
1128
1129static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
1130 struct resource *res)
1131{
1132 struct omap_mcbsp_st_data *st_data;
1133 int err;
1134
1135 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1136 if (!st_data) {
1137 err = -ENOMEM;
1138 goto err1;
1139 }
1140
1141 st_data->io_base_st = ioremap(res->start, resource_size(res));
1142 if (!st_data->io_base_st) {
1143 err = -ENOMEM;
1144 goto err2;
1145 }
1146
1147 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1148 if (err)
1149 goto err3;
1150
1151 mcbsp->st_data = st_data;
1152 return 0;
1153
1154err3:
1155 iounmap(st_data->io_base_st);
1156err2:
1157 kfree(st_data);
1158err1:
1159 return err;
1160
1161}
1162
1163static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1164{
1165 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1166
1167 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1168 iounmap(st_data->io_base_st);
1169 kfree(st_data);
1170}
1171
1172/*
1173 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1174 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1175 */
1176static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1177{
1178 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1179 struct omap_mcbsp *mcbsp;
1180 int id = pdev->id - 1;
1181 struct resource *res;
1182 int ret = 0;
1183
1184 if (!pdata) {
1185 dev_err(&pdev->dev, "McBSP device initialized without"
1186 "platform data\n");
1187 ret = -EINVAL;
1188 goto exit;
1189 }
1190
1191 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1192
1193 if (id >= omap_mcbsp_count) {
1194 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1195 ret = -EINVAL;
1196 goto exit;
1197 }
1198
1199 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1200 if (!mcbsp) {
1201 ret = -ENOMEM;
1202 goto exit;
1203 }
1204
1205 spin_lock_init(&mcbsp->lock);
1206 mcbsp->id = id + 1;
1207 mcbsp->free = true;
1208
1209 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1210 if (!res) {
1211 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1212 if (!res) {
1213 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1214 "resource\n", __func__, pdev->id);
1215 ret = -ENOMEM;
1216 goto exit;
1217 }
1218 }
1219 mcbsp->phys_base = res->start;
1220 mcbsp->reg_cache_size = resource_size(res);
1221 mcbsp->io_base = ioremap(res->start, resource_size(res));
1222 if (!mcbsp->io_base) {
1223 ret = -ENOMEM;
1224 goto err_ioremap;
1225 }
1226
1227 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1228 if (!res)
1229 mcbsp->phys_dma_base = mcbsp->phys_base;
1230 else
1231 mcbsp->phys_dma_base = res->start;
1232
1233 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1234 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1235
1236 /* From OMAP4 there will be a single irq line */
1237 if (mcbsp->tx_irq == -ENXIO)
1238 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1239
1240 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1241 if (!res) {
1242 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1243 __func__, pdev->id);
1244 ret = -ENODEV;
1245 goto err_res;
1246 }
1247 mcbsp->dma_rx_sync = res->start;
1248
1249 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1250 if (!res) {
1251 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1252 __func__, pdev->id);
1253 ret = -ENODEV;
1254 goto err_res;
1255 }
1256 mcbsp->dma_tx_sync = res->start;
1257
1258 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1259 if (IS_ERR(mcbsp->fclk)) {
1260 ret = PTR_ERR(mcbsp->fclk);
1261 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1262 goto err_res;
1263 }
1264
1265 mcbsp->pdata = pdata;
1266 mcbsp->dev = &pdev->dev;
1267 mcbsp_ptr[id] = mcbsp;
1268 platform_set_drvdata(pdev, mcbsp);
1269 pm_runtime_enable(mcbsp->dev);
1270
1271 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1272 if (mcbsp->pdata->buffer_size) {
1273 /*
1274 * Initially configure the maximum thresholds to a safe value.
1275 * The McBSP FIFO usage with these values should not go under
1276 * 16 locations.
1277 * If the whole FIFO without safety buffer is used, than there
1278 * is a possibility that the DMA will be not able to push the
1279 * new data on time, causing channel shifts in runtime.
1280 */
1281 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1282 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1283
1284 ret = sysfs_create_group(&mcbsp->dev->kobj,
1285 &additional_attr_group);
1286 if (ret) {
1287 dev_err(mcbsp->dev,
1288 "Unable to create additional controls\n");
1289 goto err_thres;
1290 }
1291 } else {
1292 mcbsp->max_tx_thres = -EINVAL;
1293 mcbsp->max_rx_thres = -EINVAL;
1294 }
1295
1296 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1297 if (res) {
1298 ret = omap_st_add(mcbsp, res);
1299 if (ret) {
1300 dev_err(mcbsp->dev,
1301 "Unable to create sidetone controls\n");
1302 goto err_st;
1303 }
1304 }
1305
1306 return 0;
1307
1308err_st:
1309 if (mcbsp->pdata->buffer_size)
1310 sysfs_remove_group(&mcbsp->dev->kobj,
1311 &additional_attr_group);
1312err_thres:
1313 clk_put(mcbsp->fclk);
1314err_res:
1315 iounmap(mcbsp->io_base);
1316err_ioremap:
1317 kfree(mcbsp);
1318exit:
1319 return ret;
1320}
1321
1322static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1323{
1324 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1325
1326 platform_set_drvdata(pdev, NULL);
1327 if (mcbsp) {
1328
1329 if (mcbsp->pdata && mcbsp->pdata->ops &&
1330 mcbsp->pdata->ops->free)
1331 mcbsp->pdata->ops->free(mcbsp->id);
1332
1333 if (mcbsp->pdata->buffer_size)
1334 sysfs_remove_group(&mcbsp->dev->kobj,
1335 &additional_attr_group);
1336
1337 if (mcbsp->st_data)
1338 omap_st_remove(mcbsp);
1339
1340 clk_put(mcbsp->fclk);
1341
1342 iounmap(mcbsp->io_base);
1343 kfree(mcbsp);
1344 }
1345
1346 return 0;
1347}
1348
1349static struct platform_driver omap_mcbsp_driver = {
1350 .probe = omap_mcbsp_probe,
1351 .remove = __devexit_p(omap_mcbsp_remove),
1352 .driver = {
1353 .name = "omap-mcbsp",
1354 },
1355};
1356
1357int __init omap_mcbsp_init(void)
1358{
1359 /* Register the McBSP driver */
1360 return platform_driver_register(&omap_mcbsp_driver);
1361}
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 0d4aa0d5876..cff8712122b 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -26,8 +26,11 @@
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <asm/system.h>
30#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30
31#include <asm/system.h>
32
33#include <plat/cpu.h>
31#include <plat/mux.h> 34#include <plat/mux.h>
32 35
33#ifdef CONFIG_OMAP_MUX 36#ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 3dc3801aace..5a97b4d98d4 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -319,7 +319,7 @@ int omap_pm_get_dev_context_loss_count(struct device *dev)
319 if (WARN_ON(!dev)) 319 if (WARN_ON(!dev))
320 return -ENODEV; 320 return -ENODEV;
321 321
322 if (dev->parent == &omap_device_parent) { 322 if (dev->pm_domain == &omap_device_pm_domain) {
323 count = omap_device_get_context_loss_count(pdev); 323 count = omap_device_get_context_loss_count(pdev);
324 } else { 324 } else {
325 WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device", 325 WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index e8d98693d2d..6de28ea3cd6 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * omap_device implementation 3 * omap_device implementation
3 * 4 *
@@ -97,14 +98,7 @@
97#define USE_WAKEUP_LAT 0 98#define USE_WAKEUP_LAT 0
98#define IGNORE_WAKEUP_LAT 1 99#define IGNORE_WAKEUP_LAT 1
99 100
100static int omap_device_register(struct platform_device *pdev);
101static int omap_early_device_register(struct platform_device *pdev); 101static int omap_early_device_register(struct platform_device *pdev);
102static struct omap_device *omap_device_alloc(struct platform_device *pdev,
103 struct omap_hwmod **ohs, int oh_cnt,
104 struct omap_device_pm_latency *pm_lats,
105 int pm_lats_cnt);
106static void omap_device_delete(struct omap_device *od);
107
108 102
109static struct omap_device_pm_latency omap_default_latency[] = { 103static struct omap_device_pm_latency omap_default_latency[] = {
110 { 104 {
@@ -320,8 +314,6 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
320} 314}
321 315
322 316
323static struct dev_pm_domain omap_device_pm_domain;
324
325/** 317/**
326 * omap_device_build_from_dt - build an omap_device with multiple hwmods 318 * omap_device_build_from_dt - build an omap_device with multiple hwmods
327 * @pdev_name: name of the platform_device driver to use 319 * @pdev_name: name of the platform_device driver to use
@@ -509,7 +501,7 @@ static int omap_device_fill_resources(struct omap_device *od,
509 * 501 *
510 * Returns an struct omap_device pointer or ERR_PTR() on error; 502 * Returns an struct omap_device pointer or ERR_PTR() on error;
511 */ 503 */
512static struct omap_device *omap_device_alloc(struct platform_device *pdev, 504struct omap_device *omap_device_alloc(struct platform_device *pdev,
513 struct omap_hwmod **ohs, int oh_cnt, 505 struct omap_hwmod **ohs, int oh_cnt,
514 struct omap_device_pm_latency *pm_lats, 506 struct omap_device_pm_latency *pm_lats,
515 int pm_lats_cnt) 507 int pm_lats_cnt)
@@ -591,7 +583,7 @@ oda_exit1:
591 return ERR_PTR(ret); 583 return ERR_PTR(ret);
592} 584}
593 585
594static void omap_device_delete(struct omap_device *od) 586void omap_device_delete(struct omap_device *od)
595{ 587{
596 if (!od) 588 if (!od)
597 return; 589 return;
@@ -619,7 +611,7 @@ static void omap_device_delete(struct omap_device *od)
619 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, 611 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
620 * passes along the return value of omap_device_build_ss(). 612 * passes along the return value of omap_device_build_ss().
621 */ 613 */
622struct platform_device *omap_device_build(const char *pdev_name, int pdev_id, 614struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id,
623 struct omap_hwmod *oh, void *pdata, 615 struct omap_hwmod *oh, void *pdata,
624 int pdata_len, 616 int pdata_len,
625 struct omap_device_pm_latency *pm_lats, 617 struct omap_device_pm_latency *pm_lats,
@@ -652,7 +644,7 @@ struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
652 * platform_device record. Returns an ERR_PTR() on error, or passes 644 * platform_device record. Returns an ERR_PTR() on error, or passes
653 * along the return value of omap_device_register(). 645 * along the return value of omap_device_register().
654 */ 646 */
655struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id, 647struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id,
656 struct omap_hwmod **ohs, int oh_cnt, 648 struct omap_hwmod **ohs, int oh_cnt,
657 void *pdata, int pdata_len, 649 void *pdata, int pdata_len,
658 struct omap_device_pm_latency *pm_lats, 650 struct omap_device_pm_latency *pm_lats,
@@ -717,7 +709,7 @@ odbs_exit:
717 * platform_early_add_device() on the underlying platform_device. 709 * platform_early_add_device() on the underlying platform_device.
718 * Returns 0 by default. 710 * Returns 0 by default.
719 */ 711 */
720static int omap_early_device_register(struct platform_device *pdev) 712static int __init omap_early_device_register(struct platform_device *pdev)
721{ 713{
722 struct platform_device *devices[1]; 714 struct platform_device *devices[1];
723 715
@@ -762,14 +754,12 @@ static int _od_suspend_noirq(struct device *dev)
762 struct omap_device *od = to_omap_device(pdev); 754 struct omap_device *od = to_omap_device(pdev);
763 int ret; 755 int ret;
764 756
765 if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
766 return pm_generic_suspend_noirq(dev);
767
768 ret = pm_generic_suspend_noirq(dev); 757 ret = pm_generic_suspend_noirq(dev);
769 758
770 if (!ret && !pm_runtime_status_suspended(dev)) { 759 if (!ret && !pm_runtime_status_suspended(dev)) {
771 if (pm_generic_runtime_suspend(dev) == 0) { 760 if (pm_generic_runtime_suspend(dev) == 0) {
772 omap_device_idle(pdev); 761 if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
762 omap_device_idle(pdev);
773 od->flags |= OMAP_DEVICE_SUSPENDED; 763 od->flags |= OMAP_DEVICE_SUSPENDED;
774 } 764 }
775 } 765 }
@@ -782,13 +772,11 @@ static int _od_resume_noirq(struct device *dev)
782 struct platform_device *pdev = to_platform_device(dev); 772 struct platform_device *pdev = to_platform_device(dev);
783 struct omap_device *od = to_omap_device(pdev); 773 struct omap_device *od = to_omap_device(pdev);
784 774
785 if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
786 return pm_generic_resume_noirq(dev);
787
788 if ((od->flags & OMAP_DEVICE_SUSPENDED) && 775 if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
789 !pm_runtime_status_suspended(dev)) { 776 !pm_runtime_status_suspended(dev)) {
790 od->flags &= ~OMAP_DEVICE_SUSPENDED; 777 od->flags &= ~OMAP_DEVICE_SUSPENDED;
791 omap_device_enable(pdev); 778 if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
779 omap_device_enable(pdev);
792 pm_generic_runtime_resume(dev); 780 pm_generic_runtime_resume(dev);
793 } 781 }
794 782
@@ -799,7 +787,7 @@ static int _od_resume_noirq(struct device *dev)
799#define _od_resume_noirq NULL 787#define _od_resume_noirq NULL
800#endif 788#endif
801 789
802static struct dev_pm_domain omap_device_pm_domain = { 790struct dev_pm_domain omap_device_pm_domain = {
803 .ops = { 791 .ops = {
804 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume, 792 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
805 _od_runtime_idle) 793 _od_runtime_idle)
@@ -817,11 +805,10 @@ static struct dev_pm_domain omap_device_pm_domain = {
817 * platform_device_register() on the underlying platform_device. 805 * platform_device_register() on the underlying platform_device.
818 * Returns the return value of platform_device_register(). 806 * Returns the return value of platform_device_register().
819 */ 807 */
820static int omap_device_register(struct platform_device *pdev) 808int omap_device_register(struct platform_device *pdev)
821{ 809{
822 pr_debug("omap_device: %s: registering\n", pdev->name); 810 pr_debug("omap_device: %s: registering\n", pdev->name);
823 811
824 pdev->dev.parent = &omap_device_parent;
825 pdev->dev.pm_domain = &omap_device_pm_domain; 812 pdev->dev.pm_domain = &omap_device_pm_domain;
826 return platform_device_add(pdev); 813 return platform_device_add(pdev);
827} 814}
@@ -1130,11 +1117,6 @@ int omap_device_enable_clocks(struct omap_device *od)
1130 return 0; 1117 return 0;
1131} 1118}
1132 1119
1133struct device omap_device_parent = {
1134 .init_name = "omap",
1135 .parent = &platform_bus,
1136};
1137
1138static struct notifier_block platform_nb = { 1120static struct notifier_block platform_nb = {
1139 .notifier_call = _omap_device_notifier_call, 1121 .notifier_call = _omap_device_notifier_call,
1140}; 1122};
@@ -1142,6 +1124,6 @@ static struct notifier_block platform_nb = {
1142static int __init omap_device_init(void) 1124static int __init omap_device_init(void)
1143{ 1125{
1144 bus_register_notifier(&platform_bus_type, &platform_nb); 1126 bus_register_notifier(&platform_bus_type, &platform_nb);
1145 return device_register(&omap_device_parent); 1127 return 0;
1146} 1128}
1147core_initcall(omap_device_init); 1129core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4243bdcc87b..eec98afa0f8 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -31,11 +31,10 @@
31 31
32#include "sram.h" 32#include "sram.h"
33 33
34/* XXX These "sideways" includes are a sign that something is wrong */ 34/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
35#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 35#include "../mach-omap2/iomap.h"
36# include "../mach-omap2/prm2xxx_3xxx.h" 36#include "../mach-omap2/prm2xxx_3xxx.h"
37# include "../mach-omap2/sdrc.h" 37#include "../mach-omap2/sdrc.h"
38#endif
39 38
40#define OMAP1_SRAM_PA 0x20000000 39#define OMAP1_SRAM_PA 0x20000000
41#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) 40#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
@@ -86,7 +85,7 @@ static int is_sram_locked(void)
86 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ 85 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
87 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ 86 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
88 } 87 }
89 if (cpu_is_omap34xx()) { 88 if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
90 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ 89 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
91 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ 90 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
92 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ 91 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
@@ -124,7 +123,10 @@ static void __init omap_detect_sram(void)
124 omap_sram_size = 0x800; /* 2K */ 123 omap_sram_size = 0x800; /* 2K */
125 } 124 }
126 } else { 125 } else {
127 if (cpu_is_omap34xx()) { 126 if (cpu_is_am33xx()) {
127 omap_sram_start = AM33XX_SRAM_PA;
128 omap_sram_size = 0x10000; /* 64K */
129 } else if (cpu_is_omap34xx()) {
128 omap_sram_start = OMAP3_SRAM_PA; 130 omap_sram_start = OMAP3_SRAM_PA;
129 omap_sram_size = 0x10000; /* 64K */ 131 omap_sram_size = 0x10000; /* 64K */
130 } else if (cpu_is_omap44xx()) { 132 } else if (cpu_is_omap44xx()) {
@@ -368,6 +370,11 @@ static inline int omap34xx_sram_init(void)
368 return 0; 370 return 0;
369} 371}
370 372
373static inline int am33xx_sram_init(void)
374{
375 return 0;
376}
377
371int __init omap_sram_init(void) 378int __init omap_sram_init(void)
372{ 379{
373 omap_detect_sram(); 380 omap_detect_sram();
@@ -379,6 +386,8 @@ int __init omap_sram_init(void)
379 omap242x_sram_init(); 386 omap242x_sram_init();
380 else if (cpu_is_omap2430()) 387 else if (cpu_is_omap2430())
381 omap243x_sram_init(); 388 omap243x_sram_init();
389 else if (cpu_is_am33xx())
390 am33xx_sram_init();
382 else if (cpu_is_omap34xx()) 391 else if (cpu_is_omap34xx())
383 omap34xx_sram_init(); 392 omap34xx_sram_init();
384 393
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index f3570884883..d2bbfd1cb0b 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -29,6 +29,10 @@
29#include <plat/usb.h> 29#include <plat/usb.h>
30#include <plat/board.h> 30#include <plat/board.h>
31 31
32#include <mach/hardware.h>
33
34#include "../mach-omap2/common.h"
35
32#ifdef CONFIG_ARCH_OMAP_OTG 36#ifdef CONFIG_ARCH_OMAP_OTG
33 37
34void __init 38void __init
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 11:17:19 -0400