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-rw-r--r--arch/arm/plat-omap/include/plat/common.h5
-rw-r--r--arch/arm/plat-omap/include/plat/control.h381
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h41
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h6
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h2
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smsc911x.h35
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h4
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h2
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h29
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h12
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h128
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h14
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h4
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h62
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h2
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h2
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h1
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h12
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h1
-rw-r--r--arch/arm/plat-omap/include/plat/timer-gp.h17
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h5
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h23
23 files changed, 336 insertions, 454 deletions
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 9776b41ad76..a9d69a09920 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -47,6 +47,7 @@ struct omap_globals {
47 unsigned long sdrc; /* SDRAM Controller */ 47 unsigned long sdrc; /* SDRAM Controller */
48 unsigned long sms; /* SDRAM Memory Scheduler */ 48 unsigned long sms; /* SDRAM Memory Scheduler */
49 unsigned long ctrl; /* System Control Module */ 49 unsigned long ctrl; /* System Control Module */
50 unsigned long ctrl_pad; /* PAD Control Module */
50 unsigned long prm; /* Power and Reset Management */ 51 unsigned long prm; /* Power and Reset Management */
51 unsigned long cm; /* Clock Management */ 52 unsigned long cm; /* Clock Management */
52 unsigned long cm2; 53 unsigned long cm2;
@@ -66,7 +67,6 @@ void omap2_set_globals_tap(struct omap_globals *);
66void omap2_set_globals_sdrc(struct omap_globals *); 67void omap2_set_globals_sdrc(struct omap_globals *);
67void omap2_set_globals_control(struct omap_globals *); 68void omap2_set_globals_control(struct omap_globals *);
68void omap2_set_globals_prcm(struct omap_globals *); 69void omap2_set_globals_prcm(struct omap_globals *);
69void omap2_set_globals_uart(struct omap_globals *);
70 70
71void omap3_map_io(void); 71void omap3_map_io(void);
72 72
@@ -91,7 +91,8 @@ void omap3_map_io(void);
91}) 91})
92 92
93extern struct device *omap2_get_mpuss_device(void); 93extern struct device *omap2_get_mpuss_device(void);
94extern struct device *omap2_get_dsp_device(void); 94extern struct device *omap2_get_iva_device(void);
95extern struct device *omap2_get_l3_device(void); 95extern struct device *omap2_get_l3_device(void);
96extern struct device *omap4_get_dsp_device(void);
96 97
97#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 98#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
deleted file mode 100644
index 131bf405c2f..00000000000
--- a/arch/arm/plat-omap/include/plat/control.h
+++ /dev/null
@@ -1,381 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2009 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h>
20
21#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24#define OMAP243X_CTRL_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26#define OMAP343X_CTRL_REGADDR(reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
31#define OMAP243X_CTRL_REGADDR(reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
33#define OMAP343X_CTRL_REGADDR(reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
35#endif /* __ASSEMBLY__ */
36
37/*
38 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
39 * OMAP24XX and OMAP34XX.
40 */
41
42/* Control submodule offsets */
43
44#define OMAP2_CONTROL_INTERFACE 0x000
45#define OMAP2_CONTROL_PADCONFS 0x030
46#define OMAP2_CONTROL_GENERAL 0x270
47#define OMAP343X_CONTROL_MEM_WKUP 0x600
48#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
49#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
50
51/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
52
53#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
54
55/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
56#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
57#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
58#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
59#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
60#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
61#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
62#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
63#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
64#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
65#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
66#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
67#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
68
69/* 242x-only CONTROL_GENERAL register offsets */
70#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
71#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
72
73/* 243x-only CONTROL_GENERAL register offsets */
74/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
75#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
76#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
77#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
78#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
79#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
80#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
81
82/* 24xx-only CONTROL_GENERAL register offsets */
83#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
84#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
85#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
86#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
87#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
88#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
89#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
90#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
91#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
92#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
93#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
94#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
95#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
96#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
97#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
98#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
99#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
100#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
101#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
102#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
103#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
104#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
105#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
106#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
107#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
108#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
109#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
110#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
111#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
114
115#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
116
117/* 34xx-only CONTROL_GENERAL register offsets */
118#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
119#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
120#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
121#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
122#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
123#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
124#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
125#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
126#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
127#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
128#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
129#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
130#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
131#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
132#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
133#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
134#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
135#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
136#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
137#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
138#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
139#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
140#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
141#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
142#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
143#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
144#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
145#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
149#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
150 + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
151#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
152#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
153#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
154#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
155#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
156#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
157#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
158#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
159#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
160#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
161#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
162
163/* AM35XX only CONTROL_GENERAL register offsets */
164#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
165#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
166#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314)
167#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320)
168#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324)
169#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328)
170#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C)
171
172/* 34xx PADCONF register offsets */
173#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
174 (i)*2)
175#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
176#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
177#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
178#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
179#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
180#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
181#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
182#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
183#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
184#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
185#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
186#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
187#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
188#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
189#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
190#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
191#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
192#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
193
194/* 34xx GENERAL_WKUP regist offsets */
195#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
196 0x008 + (i))
197#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
198#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
199#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
200#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
201#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
202
203/* 34xx D2D idle-related pins, handled by PM core */
204#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
205#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
206
207/* 44xx control status register offset */
208#define OMAP44XX_CONTROL_STATUS 0x2c4
209
210/* 44xx-only CONTROL_GENERAL register offsets */
211#define OMAP44XX_CONTROL_MMC1 0x628
212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
213/*
214 * REVISIT: This list of registers is not comprehensive - there are more
215 * that should be added.
216 */
217
218/*
219 * Control module register bit defines - these should eventually go into
220 * their own regbits file. Some of these will be complicated, depending
221 * on the device type (general-purpose, emulator, test, secure, bad, other)
222 * and the security mode (secure, non-secure, don't care)
223 */
224/* CONTROL_DEVCONF0 bits */
225#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
226#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
227#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
228#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
229
230/* CONTROL_DEVCONF1 bits */
231#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
232#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
233#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
234#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
235#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
236
237/* CONTROL_STATUS bits */
238#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
239#define OMAP2_SYSBOOT_5_MASK (1 << 5)
240#define OMAP2_SYSBOOT_4_MASK (1 << 4)
241#define OMAP2_SYSBOOT_3_MASK (1 << 3)
242#define OMAP2_SYSBOOT_2_MASK (1 << 2)
243#define OMAP2_SYSBOOT_1_MASK (1 << 1)
244#define OMAP2_SYSBOOT_0_MASK (1 << 0)
245
246/* CONTROL_PBIAS_LITE bits */
247#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
248#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
249#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
250#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
251#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
252#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
253#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
254#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
256#define OMAP2_PBIASLITEVMODE0 (1 << 0)
257
258/* CONTROL_PBIAS_LITE bits for OMAP4 */
259#define OMAP4_MMC1_PWRDNZ (1 << 26)
260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
266
267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
274
275/* CONTROL_PROG_IO1 bits */
276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
277
278/* CONTROL_IVA2_BOOTMOD bits */
279#define OMAP3_IVA2_BOOTMOD_SHIFT 0
280#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
281#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
282
283/* CONTROL_PADCONF_X bits */
284#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
285#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
286
287#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
288#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
289#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
290
291/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
292#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
293#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
294#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
295#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
296#define AM35XX_USBOTG_FCLK_SHIFT 8
297#define AM35XX_CPGMAC_FCLK_SHIFT 9
298#define AM35XX_VPFE_FCLK_SHIFT 10
299
300/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
301#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
302#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
303#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
304#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
305#define AM35XX_USBOTGSS_INT_CLR BIT(4)
306#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
307#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
308#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
309
310/*AM35XX CONTROL_IP_SW_RESET bits*/
311#define AM35XX_USBOTGSS_SW_RST BIT(0)
312#define AM35XX_CPGMACSS_SW_RST BIT(1)
313#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
314#define AM35XX_HECC_SW_RST BIT(3)
315#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
316
317/*
318 * CONTROL OMAP STATUS register to identify OMAP3 features
319 */
320#define OMAP3_CONTROL_OMAP_STATUS 0x044c
321
322#define OMAP3_SGX_SHIFT 13
323#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
324#define FEAT_SGX_FULL 0
325#define FEAT_SGX_HALF 1
326#define FEAT_SGX_NONE 2
327
328#define OMAP3_IVA_SHIFT 12
329#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
330#define FEAT_IVA 0
331#define FEAT_IVA_NONE 1
332
333#define OMAP3_L2CACHE_SHIFT 10
334#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
335#define FEAT_L2CACHE_NONE 0
336#define FEAT_L2CACHE_64KB 1
337#define FEAT_L2CACHE_128KB 2
338#define FEAT_L2CACHE_256KB 3
339
340#define OMAP3_ISP_SHIFT 5
341#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
342#define FEAT_ISP 0
343#define FEAT_ISP_NONE 1
344
345#define OMAP3_NEON_SHIFT 4
346#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
347#define FEAT_NEON 0
348#define FEAT_NEON_NONE 1
349
350
351#ifndef __ASSEMBLY__
352#ifdef CONFIG_ARCH_OMAP2PLUS
353extern void __iomem *omap_ctrl_base_get(void);
354extern u8 omap_ctrl_readb(u16 offset);
355extern u16 omap_ctrl_readw(u16 offset);
356extern u32 omap_ctrl_readl(u16 offset);
357extern void omap_ctrl_writeb(u8 val, u16 offset);
358extern void omap_ctrl_writew(u16 val, u16 offset);
359extern void omap_ctrl_writel(u32 val, u16 offset);
360
361extern void omap3_save_scratchpad_contents(void);
362extern void omap3_clear_scratchpad_contents(void);
363extern u32 *get_restore_pointer(void);
364extern u32 *get_es3_restore_pointer(void);
365extern u32 omap3_arm_context[128];
366extern void omap3_control_save_context(void);
367extern void omap3_control_restore_context(void);
368
369#else
370#define omap_ctrl_base_get() 0
371#define omap_ctrl_readb(x) 0
372#define omap_ctrl_readw(x) 0
373#define omap_ctrl_readl(x) 0
374#define omap_ctrl_writeb(x, y) WARN_ON(1)
375#define omap_ctrl_writew(x, y) WARN_ON(1)
376#define omap_ctrl_writel(x, y) WARN_ON(1)
377#endif
378#endif /* __ASSEMBLY__ */
379
380#endif /* __ASM_ARCH_CONTROL_H */
381
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e2ae530fce..3fd8b405572 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -68,10 +68,9 @@ unsigned int omap_rev(void);
68#define OMAP_REVBITS_00 0x00 68#define OMAP_REVBITS_00 0x00
69#define OMAP_REVBITS_01 0x01 69#define OMAP_REVBITS_01 0x01
70#define OMAP_REVBITS_02 0x02 70#define OMAP_REVBITS_02 0x02
71#define OMAP_REVBITS_10 0x10 71#define OMAP_REVBITS_03 0x03
72#define OMAP_REVBITS_20 0x20 72#define OMAP_REVBITS_04 0x04
73#define OMAP_REVBITS_30 0x30 73#define OMAP_REVBITS_05 0x05
74#define OMAP_REVBITS_40 0x40
75 74
76/* 75/*
77 * Get the CPU revision for OMAP devices 76 * Get the CPU revision for OMAP devices
@@ -363,23 +362,24 @@ IS_OMAP_TYPE(3517, 0x3517)
363 362
364/* Various silicon revisions for omap2 */ 363/* Various silicon revisions for omap2 */
365#define OMAP242X_CLASS 0x24200024 364#define OMAP242X_CLASS 0x24200024
366#define OMAP2420_REV_ES1_0 0x24200024 365#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
367#define OMAP2420_REV_ES2_0 0x24201024 366#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
368 367
369#define OMAP243X_CLASS 0x24300024 368#define OMAP243X_CLASS 0x24300024
370#define OMAP2430_REV_ES1_0 0x24300024 369#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
371 370
372#define OMAP343X_CLASS 0x34300034 371#define OMAP343X_CLASS 0x34300034
373#define OMAP3430_REV_ES1_0 0x34300034 372#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
374#define OMAP3430_REV_ES2_0 0x34301034 373#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
375#define OMAP3430_REV_ES2_1 0x34302034 374#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
376#define OMAP3430_REV_ES3_0 0x34303034 375#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
377#define OMAP3430_REV_ES3_1 0x34304034 376#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
378#define OMAP3430_REV_ES3_1_2 0x34305034 377#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
379 378
380#define OMAP3630_REV_ES1_0 0x36300034 379#define OMAP363X_CLASS 0x36300034
381#define OMAP3630_REV_ES1_1 0x36300134 380#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
382#define OMAP3630_REV_ES1_2 0x36300234 381#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
382#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
383 383
384#define OMAP35XX_CLASS 0x35000034 384#define OMAP35XX_CLASS 0x35000034
385#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) 385#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
@@ -390,7 +390,8 @@ IS_OMAP_TYPE(3517, 0x3517)
390#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) 390#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
391 391
392#define OMAP443X_CLASS 0x44300044 392#define OMAP443X_CLASS 0x44300044
393#define OMAP4430_REV_ES1_0 0x44300044 393#define OMAP4430_REV_ES1_0 OMAP443X_CLASS
394#define OMAP4430_REV_ES2_0 0x44301044
394 395
395/* 396/*
396 * omap_chip bits 397 * omap_chip bits
@@ -417,10 +418,12 @@ IS_OMAP_TYPE(3517, 0x3517)
417#define CHIP_IS_OMAP4430ES1 (1 << 8) 418#define CHIP_IS_OMAP4430ES1 (1 << 8)
418#define CHIP_IS_OMAP3630ES1_1 (1 << 9) 419#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
419#define CHIP_IS_OMAP3630ES1_2 (1 << 10) 420#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
421#define CHIP_IS_OMAP4430ES2 (1 << 11)
420 422
421#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 423#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
422 424
423#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) 425#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
426 CHIP_IS_OMAP4430ES2)
424 427
425/* 428/*
426 * "GE" here represents "greater than or equal to" in terms of ES 429 * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index af3a03941ad..0cce4ca83aa 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -319,6 +319,8 @@
319#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ 319#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
320#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ 320#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
321 321
322#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
323#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */
322/*----------------------------------------------------------------------------*/ 324/*----------------------------------------------------------------------------*/
323 325
324#define OMAP1_DMA_TOUT_IRQ (1 << 0) 326#define OMAP1_DMA_TOUT_IRQ (1 << 0)
@@ -335,6 +337,10 @@
335#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) 337#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
336 338
337#define OMAP_DMA_CCR_EN (1 << 7) 339#define OMAP_DMA_CCR_EN (1 << 7)
340#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
341#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
342#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
343#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
338 344
339#define OMAP_DMA_DATA_TYPE_S8 0x00 345#define OMAP_DMA_DATA_TYPE_S8 0x00
340#define OMAP_DMA_DATA_TYPE_S16 0x01 346#define OMAP_DMA_DATA_TYPE_S16 0x01
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a8..dfa3aff9761 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -45,6 +45,8 @@
45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
46 46
47struct omap_dm_timer; 47struct omap_dm_timer;
48extern struct omap_dm_timer *gptimer_wakeup;
49extern struct sys_timer omap_timer;
48struct clk; 50struct clk;
49 51
50int omap_dm_timer_init(void); 52int omap_dm_timer_init(void);
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
new file mode 100644
index 00000000000..872de0bf1e6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
@@ -0,0 +1,35 @@
1/*
2 * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
3 *
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
6 *
7 * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
15
16struct omap_smsc911x_platform_data {
17 int cs;
18 int gpio_irq;
19 int gpio_reset;
20 u32 flags;
21};
22
23#if defined(CONFIG_SMSC911X) || \
24 defined(CONFIG_SMSC911X_MODULE)
25
26extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
27
28#else
29
30static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
31{
32}
33
34#endif
35#endif
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 87f6bf2ea4f..36a0befd616 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,6 +18,8 @@
18 * 02110-1301 USA 18 * 02110-1301 USA
19 * 19 *
20 */ 20 */
21#ifndef __ASM__ARCH_OMAP_I2C_H
22#define __ASM__ARCH_OMAP_I2C_H
21 23
22#include <linux/i2c.h> 24#include <linux/i2c.h>
23 25
@@ -36,3 +38,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
36 38
37void __init omap1_i2c_mux_pins(int bus_id); 39void __init omap1_i2c_mux_pins(int bus_id);
38void __init omap2_i2c_mux_pins(int bus_id); 40void __init omap2_i2c_mux_pins(int bus_id);
41
42#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index c01d9f08a19..65e20a68671 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -345,6 +345,8 @@
345#define INT_34XX_MMC3_IRQ 94 345#define INT_34XX_MMC3_IRQ 94
346#define INT_34XX_GPT12_IRQ 95 346#define INT_34XX_GPT12_IRQ 95
347 347
348#define INT_36XX_UART4_IRQ 80
349
348#define INT_35XX_HECC0_IRQ 24 350#define INT_35XX_HECC0_IRQ 24
349#define INT_35XX_HECC1_IRQ 28 351#define INT_35XX_HECC1_IRQ 28
350#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 352#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index b4ff6a11a8f..b87d83ccd54 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -30,6 +30,13 @@
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <plat/clock.h> 31#include <plat/clock.h>
32 32
33/* macro for building platform_device for McBSP ports */
34#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
35static struct platform_device omap_mcbsp##port_nr = { \
36 .name = "omap-mcbsp-dai", \
37 .id = OMAP_MCBSP##port_nr, \
38}
39
33#define OMAP7XX_MCBSP1_BASE 0xfffb1000 40#define OMAP7XX_MCBSP1_BASE 0xfffb1000
34#define OMAP7XX_MCBSP2_BASE 0xfffb1800 41#define OMAP7XX_MCBSP2_BASE 0xfffb1800
35 42
@@ -312,6 +319,18 @@
312#define RFSREN 0x0002 319#define RFSREN 0x0002
313#define RSYNCERREN 0x0001 320#define RSYNCERREN 0x0001
314 321
322/* CLKR signal muxing options */
323#define CLKR_SRC_CLKR 0
324#define CLKR_SRC_CLKX 1
325
326/* FSR signal muxing options */
327#define FSR_SRC_FSR 0
328#define FSR_SRC_FSX 1
329
330/* McBSP functional clock sources */
331#define MCBSP_CLKS_PRCM_SRC 0
332#define MCBSP_CLKS_PAD_SRC 1
333
315/* we don't do multichannel for now */ 334/* we don't do multichannel for now */
316struct omap_mcbsp_reg_cfg { 335struct omap_mcbsp_reg_cfg {
317 u16 spcr2; 336 u16 spcr2;
@@ -398,6 +417,7 @@ struct omap_mcbsp_spi_cfg {
398struct omap_mcbsp_ops { 417struct omap_mcbsp_ops {
399 void (*request)(unsigned int); 418 void (*request)(unsigned int);
400 void (*free)(unsigned int); 419 void (*free)(unsigned int);
420 int (*set_clks_src)(u8, u8);
401}; 421};
402 422
403struct omap_mcbsp_platform_data { 423struct omap_mcbsp_platform_data {
@@ -464,6 +484,9 @@ struct omap_mcbsp {
464extern struct omap_mcbsp **mcbsp_ptr; 484extern struct omap_mcbsp **mcbsp_ptr;
465extern int omap_mcbsp_count, omap_mcbsp_cache_size; 485extern int omap_mcbsp_count, omap_mcbsp_cache_size;
466 486
487#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
488#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
489
467int omap_mcbsp_init(void); 490int omap_mcbsp_init(void);
468void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 491void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
469 int size); 492 int size);
@@ -502,6 +525,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
502int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); 525int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
503 526
504 527
528/* McBSP functional clock source changing function */
529extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
505/* SPI specific API */ 530/* SPI specific API */
506void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); 531void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
507 532
@@ -510,6 +535,10 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
510int omap_mcbsp_pollwrite(unsigned int id, u16 buf); 535int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
511int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); 536int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
512 537
538/* McBSP signal muxing API */
539void omap2_mcbsp1_mux_clkr_src(u8 mux);
540void omap2_mcbsp1_mux_fsr_src(u8 mux);
541
513#ifdef CONFIG_ARCH_OMAP3 542#ifdef CONFIG_ARCH_OMAP3
514/* Sidetone specific API */ 543/* Sidetone specific API */
515int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 544int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 9b89ec601ee..f57f36abb07 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -71,12 +71,17 @@ struct omap_mmc_platform_data {
71 71
72 u64 dma_mask; 72 u64 dma_mask;
73 73
74 /* Register offset deviation */
75 u16 reg_offset;
76
74 struct omap_mmc_slot_data { 77 struct omap_mmc_slot_data {
75 78
76 /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; 79 /*
77 * 8 wire signaling is also optional, and is used with HSMMC 80 * 4/8 wires and any additional host capabilities
81 * need to OR'd all capabilities (ref. linux/mmc/host.h)
78 */ 82 */
79 u8 wires; 83 u8 wires; /* Used for the MMC driver on omap1 and 2420 */
84 u32 caps; /* Used for the MMC driver on 2430 and later */
80 85
81 /* 86 /*
82 * nomux means "standard" muxing is wrong on this board, and 87 * nomux means "standard" muxing is wrong on this board, and
@@ -104,6 +109,7 @@ struct omap_mmc_platform_data {
104 109
105 /* we can put the features above into this variable */ 110 /* we can put the features above into this variable */
106#define HSMMC_HAS_PBIAS (1 << 0) 111#define HSMMC_HAS_PBIAS (1 << 0)
112#define HSMMC_HAS_UPDATED_RESET (1 << 1)
107 unsigned features; 113 unsigned features;
108 114
109 int switch_pin; /* gpio (card detect) */ 115 int switch_pin; /* gpio (card detect) */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
new file mode 100644
index 00000000000..c8dae02f070
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -0,0 +1,128 @@
1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __OMAP_SERIAL_H__
18#define __OMAP_SERIAL_H__
19
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <plat/mux.h>
24
25#define DRIVER_NAME "omap-hsuart"
26
27/*
28 * Use tty device name as ttyO, [O -> OMAP]
29 * in bootargs we specify as console=ttyO0 if uart1
30 * is used as console uart.
31 */
32#define OMAP_SERIAL_NAME "ttyO"
33
34#define OMAP_MDR1_DISABLE 0x07
35#define OMAP_MDR1_MODE13X 0x03
36#define OMAP_MDR1_MODE16X 0x00
37#define OMAP_MODE13X_SPEED 230400
38
39/*
40 * LCR = 0XBF: Switch to Configuration Mode B.
41 * In configuration mode b allow access
42 * to EFR,DLL,DLH.
43 * Reference OMAP TRM Chapter 17
44 * Section: 1.4.3 Mode Selection
45 */
46#define OMAP_UART_LCR_CONF_MDB 0XBF
47
48/* WER = 0x7F
49 * Enable module level wakeup in WER reg
50 */
51#define OMAP_UART_WER_MOD_WKUP 0X7F
52
53/* Enable XON/XOFF flow control on output */
54#define OMAP_UART_SW_TX 0x04
55
56/* Enable XON/XOFF flow control on input */
57#define OMAP_UART_SW_RX 0x04
58
59#define OMAP_UART_SYSC_RESET 0X07
60#define OMAP_UART_TCR_TRIG 0X0F
61#define OMAP_UART_SW_CLR 0XF0
62#define OMAP_UART_FIFO_CLR 0X06
63
64#define OMAP_UART_DMA_CH_FREE -1
65
66#define RX_TIMEOUT (3 * HZ)
67#define OMAP_MAX_HSUART_PORTS 4
68
69#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
70
71struct omap_uart_port_info {
72 bool dma_enabled; /* To specify DMA Mode */
73 unsigned int uartclk; /* UART clock rate */
74 void __iomem *membase; /* ioremap cookie or NULL */
75 resource_size_t mapbase; /* resource base */
76 unsigned long irqflags; /* request_irq flags */
77 upf_t flags; /* UPF_* flags */
78};
79
80struct uart_omap_dma {
81 u8 uart_dma_tx;
82 u8 uart_dma_rx;
83 int rx_dma_channel;
84 int tx_dma_channel;
85 dma_addr_t rx_buf_dma_phys;
86 dma_addr_t tx_buf_dma_phys;
87 unsigned int uart_base;
88 /*
89 * Buffer for rx dma.It is not required for tx because the buffer
90 * comes from port structure.
91 */
92 unsigned char *rx_buf;
93 unsigned int prev_rx_dma_pos;
94 int tx_buf_size;
95 int tx_dma_used;
96 int rx_dma_used;
97 spinlock_t tx_lock;
98 spinlock_t rx_lock;
99 /* timer to poll activity on rx dma */
100 struct timer_list rx_timer;
101 int rx_buf_size;
102 int rx_timeout;
103};
104
105struct uart_omap_port {
106 struct uart_port port;
107 struct uart_omap_dma uart_dma;
108 struct platform_device *pdev;
109
110 unsigned char ier;
111 unsigned char lcr;
112 unsigned char mcr;
113 unsigned char fcr;
114 unsigned char efr;
115
116 int use_dma;
117 /*
118 * Some bits in registers are cleared on a read, so they must
119 * be saved whenever the register is read but the bits will not
120 * be immediately processed.
121 */
122 unsigned int lsr_break_flag;
123 unsigned char msr_saved_flags;
124 char name[20];
125 unsigned long port_activity;
126};
127
128#endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 7055672a8c6..92df9e27cc5 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -40,7 +40,7 @@
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42 42
43#define OMAP2420_CTRL_BASE L4_24XX_BASE 43#define OMAP242X_CTRL_BASE L4_24XX_BASE
44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) 45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) 46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
new file mode 100644
index 00000000000..2b1d9bc1eeb
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -0,0 +1,14 @@
1#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
2#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
3
4#include <linux/input/matrix_keypad.h>
5
6struct omap4_keypad_platform_data {
7 const struct matrix_keymap_data *keymap_data;
8
9 u8 rows;
10 u8 cols;
11};
12
13extern int omap4_keyboard_init(struct omap4_keypad_platform_data *);
14#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 25cd9ac3b09..28e2d1a7843 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,6 +36,8 @@
36 36
37#include <plat/omap_hwmod.h> 37#include <plat/omap_hwmod.h>
38 38
39extern struct device omap_device_parent;
40
39/* omap_device._state values */ 41/* omap_device._state values */
40#define OMAP_DEVICE_STATE_UNKNOWN 0 42#define OMAP_DEVICE_STATE_UNKNOWN 0
41#define OMAP_DEVICE_STATE_ENABLED 1 43#define OMAP_DEVICE_STATE_ENABLED 1
@@ -62,7 +64,6 @@
62 * 64 *
63 */ 65 */
64struct omap_device { 66struct omap_device {
65 u32 magic;
66 struct platform_device pdev; 67 struct platform_device pdev;
67 struct omap_hwmod **hwmods; 68 struct omap_hwmod **hwmods;
68 struct omap_device_pm_latency *pm_lats; 69 struct omap_device_pm_latency *pm_lats;
@@ -82,7 +83,6 @@ int omap_device_shutdown(struct platform_device *pdev);
82 83
83/* Core code interface */ 84/* Core code interface */
84 85
85bool omap_device_is_valid(struct omap_device *od);
86int omap_device_count_resources(struct omap_device *od); 86int omap_device_count_resources(struct omap_device *od);
87int omap_device_fill_resources(struct omap_device *od, struct resource *res); 87int omap_device_fill_resources(struct omap_device *od, struct resource *res);
88 88
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index a4e508dfaba..7eaa8edf3b1 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -14,19 +14,16 @@
14 * 14 *
15 * These headers and macros are used to define OMAP on-chip module 15 * These headers and macros are used to define OMAP on-chip module
16 * data and their integration with other OMAP modules and Linux. 16 * data and their integration with other OMAP modules and Linux.
17 * 17 * Copious documentation and references can also be found in the
18 * References: 18 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
19 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) 19 * writing).
20 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
21 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
22 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
23 * - Open Core Protocol Specification 2.2
24 * 20 *
25 * To do: 21 * To do:
26 * - add interconnect error log structures 22 * - add interconnect error log structures
27 * - add pinmuxing 23 * - add pinmuxing
28 * - init_conn_id_bit (CONNID_BIT_VECTOR) 24 * - init_conn_id_bit (CONNID_BIT_VECTOR)
29 * - implement default hwmod SMS/SDRC flags? 25 * - implement default hwmod SMS/SDRC flags?
26 * - remove unused fields
30 * 27 *
31 */ 28 */
32#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H 29#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
@@ -35,6 +32,7 @@
35#include <linux/kernel.h> 32#include <linux/kernel.h>
36#include <linux/list.h> 33#include <linux/list.h>
37#include <linux/ioport.h> 34#include <linux/ioport.h>
35#include <linux/mutex.h>
38#include <plat/cpu.h> 36#include <plat/cpu.h>
39 37
40struct omap_device; 38struct omap_device;
@@ -96,7 +94,7 @@ struct omap_hwmod_irq_info {
96/** 94/**
97 * struct omap_hwmod_dma_info - DMA channels used by the hwmod 95 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
98 * @name: name of the DMA channel (module local name) 96 * @name: name of the DMA channel (module local name)
99 * @dma_ch: DMA channel ID 97 * @dma_req: DMA request ID
100 * 98 *
101 * @name should be something short, e.g., "tx" or "rx". It is for use 99 * @name should be something short, e.g., "tx" or "rx". It is for use
102 * by platform_get_resource_byname(). It is defined locally to the 100 * by platform_get_resource_byname(). It is defined locally to the
@@ -104,7 +102,20 @@ struct omap_hwmod_irq_info {
104 */ 102 */
105struct omap_hwmod_dma_info { 103struct omap_hwmod_dma_info {
106 const char *name; 104 const char *name;
107 u16 dma_ch; 105 u16 dma_req;
106};
107
108/**
109 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
110 * @name: name of the reset line (module local name)
111 * @rst_shift: Offset of the reset bit
112 *
113 * @name should be something short, e.g., "cpu0" or "rst". It is defined
114 * locally to the hwmod.
115 */
116struct omap_hwmod_rst_info {
117 const char *name;
118 u8 rst_shift;
108}; 119};
109 120
110/** 121/**
@@ -237,8 +248,9 @@ struct omap_hwmod_ocp_if {
237#define SYSC_HAS_CLOCKACTIVITY (1 << 4) 248#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
238#define SYSC_HAS_SIDLEMODE (1 << 5) 249#define SYSC_HAS_SIDLEMODE (1 << 5)
239#define SYSC_HAS_MIDLEMODE (1 << 6) 250#define SYSC_HAS_MIDLEMODE (1 << 6)
240#define SYSS_MISSING (1 << 7) 251#define SYSS_HAS_RESET_STATUS (1 << 7)
241#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ 252#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
253#define SYSC_HAS_RESET_STATUS (1 << 9)
242 254
243/* omap_hwmod_sysconfig.clockact flags */ 255/* omap_hwmod_sysconfig.clockact flags */
244#define CLOCKACT_TEST_BOTH 0x0 256#define CLOCKACT_TEST_BOTH 0x0
@@ -327,10 +339,12 @@ struct omap_hwmod_omap2_prcm {
327/** 339/**
328 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data 340 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
329 * @clkctrl_reg: PRCM address of the clock control register 341 * @clkctrl_reg: PRCM address of the clock control register
342 * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM
330 * @submodule_wkdep_bit: bit shift of the WKDEP range 343 * @submodule_wkdep_bit: bit shift of the WKDEP range
331 */ 344 */
332struct omap_hwmod_omap4_prcm { 345struct omap_hwmod_omap4_prcm {
333 void __iomem *clkctrl_reg; 346 void __iomem *clkctrl_reg;
347 void __iomem *rstctrl_reg;
334 u8 submodule_wkdep_bit; 348 u8 submodule_wkdep_bit;
335}; 349};
336 350
@@ -352,6 +366,11 @@ struct omap_hwmod_omap4_prcm {
352 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 366 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
353 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case 367 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
354 * only for few initiator modules on OMAP2 & 3. 368 * only for few initiator modules on OMAP2 & 3.
369 * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
370 * This is needed for devices like DSS that require optional clocks enabled
371 * in order to complete the reset. Optional clocks will be disabled
372 * again after the reset.
373 * HWMOD_16BIT_REG: Module has 16bit registers
355 */ 374 */
356#define HWMOD_SWSUP_SIDLE (1 << 0) 375#define HWMOD_SWSUP_SIDLE (1 << 0)
357#define HWMOD_SWSUP_MSTANDBY (1 << 1) 376#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -360,6 +379,8 @@ struct omap_hwmod_omap4_prcm {
360#define HWMOD_NO_OCP_AUTOIDLE (1 << 4) 379#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
361#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) 380#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
362#define HWMOD_NO_IDLEST (1 << 6) 381#define HWMOD_NO_IDLEST (1 << 6)
382#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
383#define HWMOD_16BIT_REG (1 << 8)
363 384
364/* 385/*
365 * omap_hwmod._int_flags definitions 386 * omap_hwmod._int_flags definitions
@@ -410,7 +431,7 @@ struct omap_hwmod_class {
410 * @class: struct omap_hwmod_class * to the class of this hwmod 431 * @class: struct omap_hwmod_class * to the class of this hwmod
411 * @od: struct omap_device currently associated with this hwmod (internal use) 432 * @od: struct omap_device currently associated with this hwmod (internal use)
412 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) 433 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
413 * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) 434 * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
414 * @prcm: PRCM data pertaining to this hwmod 435 * @prcm: PRCM data pertaining to this hwmod
415 * @main_clk: main clock: OMAP clock name 436 * @main_clk: main clock: OMAP clock name
416 * @_clk: pointer to the main struct clk (filled in at runtime) 437 * @_clk: pointer to the main struct clk (filled in at runtime)
@@ -424,7 +445,7 @@ struct omap_hwmod_class {
424 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) 445 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
425 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift 446 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
426 * @mpu_irqs_cnt: number of @mpu_irqs 447 * @mpu_irqs_cnt: number of @mpu_irqs
427 * @sdma_chs_cnt: number of @sdma_chs 448 * @sdma_reqs_cnt: number of @sdma_reqs
428 * @opt_clks_cnt: number of @opt_clks 449 * @opt_clks_cnt: number of @opt_clks
429 * @master_cnt: number of @master entries 450 * @master_cnt: number of @master entries
430 * @slaves_cnt: number of @slave entries 451 * @slaves_cnt: number of @slave entries
@@ -433,6 +454,7 @@ struct omap_hwmod_class {
433 * @_state: internal-use hwmod state 454 * @_state: internal-use hwmod state
434 * @flags: hwmod flags (documented below) 455 * @flags: hwmod flags (documented below)
435 * @omap_chip: OMAP chips this hwmod is present on 456 * @omap_chip: OMAP chips this hwmod is present on
457 * @_mutex: mutex serializing operations on this hwmod
436 * @node: list node for hwmod list (internal use) 458 * @node: list node for hwmod list (internal use)
437 * 459 *
438 * @main_clk refers to this module's "main clock," which for our 460 * @main_clk refers to this module's "main clock," which for our
@@ -448,7 +470,8 @@ struct omap_hwmod {
448 struct omap_hwmod_class *class; 470 struct omap_hwmod_class *class;
449 struct omap_device *od; 471 struct omap_device *od;
450 struct omap_hwmod_irq_info *mpu_irqs; 472 struct omap_hwmod_irq_info *mpu_irqs;
451 struct omap_hwmod_dma_info *sdma_chs; 473 struct omap_hwmod_dma_info *sdma_reqs;
474 struct omap_hwmod_rst_info *rst_lines;
452 union { 475 union {
453 struct omap_hwmod_omap2_prcm omap2; 476 struct omap_hwmod_omap2_prcm omap2;
454 struct omap_hwmod_omap4_prcm omap4; 477 struct omap_hwmod_omap4_prcm omap4;
@@ -461,6 +484,7 @@ struct omap_hwmod {
461 void *dev_attr; 484 void *dev_attr;
462 u32 _sysc_cache; 485 u32 _sysc_cache;
463 void __iomem *_mpu_rt_va; 486 void __iomem *_mpu_rt_va;
487 struct mutex _mutex;
464 struct list_head node; 488 struct list_head node;
465 u16 flags; 489 u16 flags;
466 u8 _mpu_port_index; 490 u8 _mpu_port_index;
@@ -468,7 +492,8 @@ struct omap_hwmod {
468 u8 msuspendmux_shift; 492 u8 msuspendmux_shift;
469 u8 response_lat; 493 u8 response_lat;
470 u8 mpu_irqs_cnt; 494 u8 mpu_irqs_cnt;
471 u8 sdma_chs_cnt; 495 u8 sdma_reqs_cnt;
496 u8 rst_lines_cnt;
472 u8 opt_clks_cnt; 497 u8 opt_clks_cnt;
473 u8 masters_cnt; 498 u8 masters_cnt;
474 u8 slaves_cnt; 499 u8 slaves_cnt;
@@ -492,6 +517,10 @@ int omap_hwmod_idle(struct omap_hwmod *oh);
492int _omap_hwmod_idle(struct omap_hwmod *oh); 517int _omap_hwmod_idle(struct omap_hwmod *oh);
493int omap_hwmod_shutdown(struct omap_hwmod *oh); 518int omap_hwmod_shutdown(struct omap_hwmod *oh);
494 519
520int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
521int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
522int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
523
495int omap_hwmod_enable_clocks(struct omap_hwmod *oh); 524int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
496int omap_hwmod_disable_clocks(struct omap_hwmod *oh); 525int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
497 526
@@ -500,8 +529,8 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
500int omap_hwmod_reset(struct omap_hwmod *oh); 529int omap_hwmod_reset(struct omap_hwmod *oh);
501void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); 530void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
502 531
503void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); 532void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
504u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); 533u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
505 534
506int omap_hwmod_count_resources(struct omap_hwmod *oh); 535int omap_hwmod_count_resources(struct omap_hwmod *oh);
507int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); 536int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
@@ -534,5 +563,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
534extern int omap2420_hwmod_init(void); 563extern int omap2420_hwmod_init(void);
535extern int omap2430_hwmod_init(void); 564extern int omap2430_hwmod_init(void);
536extern int omap3xxx_hwmod_init(void); 565extern int omap3xxx_hwmod_init(void);
566extern int omap44xx_hwmod_init(void);
537 567
538#endif 568#endif
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fb6ec74fe39..9ca420dcd2f 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -32,6 +32,7 @@
32 32
33/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
34#define PWRSTS_ON (1 << PWRDM_POWER_ON) 34#define PWRSTS_ON (1 << PWRDM_POWER_ON)
35#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 36#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_ON)) 37 (1 << PWRDM_POWER_ON))
37 38
@@ -161,5 +162,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm);
161int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); 162int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
162int pwrdm_pre_transition(void); 163int pwrdm_pre_transition(void);
163int pwrdm_post_transition(void); 164int pwrdm_post_transition(void);
165int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
164 166
165#endif 167#endif
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 9fbd91419cd..ab77442e42a 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -38,6 +38,8 @@ u32 prm_read_mod_reg(s16 module, u16 idx);
38void prm_write_mod_reg(u32 val, s16 module, u16 idx); 38void prm_write_mod_reg(u32 val, s16 module, u16 idx);
39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
40u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); 40u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
41u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
42u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
41u32 cm_read_mod_reg(s16 module, u16 idx); 43u32 cm_read_mod_reg(s16 module, u16 idx);
42void cm_write_mod_reg(u32 val, s16 module, u16 idx); 44void cm_write_mod_reg(u32 val, s16 module, u16 idx);
43u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 45u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 7b76f50564b..efd87c8dda6 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -147,6 +147,7 @@ struct memory_timings {
147}; 147};
148 148
149extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); 149extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
150struct omap_sdrc_params *rx51_get_sdram_timings(void);
150 151
151u32 omap2xxx_sdrc_dll_is_unlocked(void); 152u32 omap2xxx_sdrc_dll_is_unlocked(void);
152u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); 153u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c5a25..ecd6a488c49 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
18#define OMAP_ARCH_SMP_H 18#define OMAP_ARCH_SMP_H
19 19
20#include <asm/hardware/gic.h> 20#include <asm/hardware/gic.h>
21#include <asm/smp_mpidr.h>
21 22
22/* Needed for secondary core boot */ 23/* Needed for secondary core boot */
23extern void omap_secondary_startup(void); 24extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
33 gic_raise_softirq(mask, 1); 34 gic_raise_softirq(mask, 1);
34} 35}
35 36
36/*
37 * Read MPIDR: Multiprocessor affinity register
38 */
39#define hard_smp_processor_id() \
40 ({ \
41 unsigned int cpunum; \
42 __asm__("mrc p15, 0, %0, c0, c0, 5" \
43 : "=r" (cpunum)); \
44 cpunum &= 0x0F; \
45 })
46
47#endif 37#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 16a1b458d53..5905100b29a 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,7 +11,6 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14extern int __init omap_sram_init(void);
15extern void * omap_sram_push(void * start, unsigned long size); 14extern void * omap_sram_push(void * start, unsigned long size);
16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
17 16
diff --git a/arch/arm/plat-omap/include/plat/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
deleted file mode 100644
index c88d346b59d..00000000000
--- a/arch/arm/plat-omap/include/plat/timer-gp.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * OMAP2/3 GPTIMER support.headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
12#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
13
14int __init omap2_gp_clockevent_set_gptimer(u8 id);
15
16#endif
17
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ddf723be48d..9036e374e0a 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -139,10 +139,14 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
139 DEBUG_LL_OMAP2(1, omap3evm); 139 DEBUG_LL_OMAP2(1, omap3evm);
140 DEBUG_LL_OMAP3(1, omap_3430sdp); 140 DEBUG_LL_OMAP3(1, omap_3430sdp);
141 DEBUG_LL_OMAP3(1, omap_3630sdp); 141 DEBUG_LL_OMAP3(1, omap_3630sdp);
142 DEBUG_LL_OMAP3(1, omap3530_lv_som);
143 DEBUG_LL_OMAP3(1, omap3_torpedo);
142 144
143 /* omap3 based boards using UART3 */ 145 /* omap3 based boards using UART3 */
144 DEBUG_LL_OMAP3(3, cm_t35); 146 DEBUG_LL_OMAP3(3, cm_t35);
147 DEBUG_LL_OMAP3(3, cm_t3517);
145 DEBUG_LL_OMAP3(3, igep0020); 148 DEBUG_LL_OMAP3(3, igep0020);
149 DEBUG_LL_OMAP3(3, igep0030);
146 DEBUG_LL_OMAP3(3, nokia_rx51); 150 DEBUG_LL_OMAP3(3, nokia_rx51);
147 DEBUG_LL_OMAP3(3, omap3517evm); 151 DEBUG_LL_OMAP3(3, omap3517evm);
148 DEBUG_LL_OMAP3(3, omap3_beagle); 152 DEBUG_LL_OMAP3(3, omap3_beagle);
@@ -153,6 +157,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
153 157
154 /* omap4 based boards using UART3 */ 158 /* omap4 based boards using UART3 */
155 DEBUG_LL_OMAP4(3, omap_4430sdp); 159 DEBUG_LL_OMAP4(3, omap_4430sdp);
160 DEBUG_LL_OMAP4(3, omap4_panda);
156 161
157 /* zoom2/3 external uart */ 162 /* zoom2/3 external uart */
158 DEBUG_LL_ZOOM(omap_zoom2); 163 DEBUG_LL_ZOOM(omap_zoom2);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 2a9427c8cc4..59c7fe731f2 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata)
105#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) 105#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
106void omap2_usbfs_init(struct omap_usb_config *pdata); 106void omap2_usbfs_init(struct omap_usb_config *pdata);
107#else 107#else
108static inline omap2_usbfs_init(struct omap_usb_config *pdata) 108static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
109{ 109{
110} 110}
111#endif 111#endif
@@ -218,6 +218,27 @@ static inline omap2_usbfs_init(struct omap_usb_config *pdata)
218# define USBT2TLL5PI (1 << 17) 218# define USBT2TLL5PI (1 << 17)
219# define USB0PUENACTLOI (1 << 16) 219# define USB0PUENACTLOI (1 << 16)
220# define USBSTANDBYCTRL (1 << 15) 220# define USBSTANDBYCTRL (1 << 15)
221/* AM35x */
222/* USB 2.0 PHY Control */
223#define CONF2_PHY_GPIOMODE (1 << 23)
224#define CONF2_OTGMODE (3 << 14)
225#define CONF2_NO_OVERRIDE (0 << 14)
226#define CONF2_FORCE_HOST (1 << 14)
227#define CONF2_FORCE_DEVICE (2 << 14)
228#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
229#define CONF2_SESENDEN (1 << 13)
230#define CONF2_VBDTCTEN (1 << 12)
231#define CONF2_REFFREQ_24MHZ (2 << 8)
232#define CONF2_REFFREQ_26MHZ (7 << 8)
233#define CONF2_REFFREQ_13MHZ (6 << 8)
234#define CONF2_REFFREQ (0xf << 8)
235#define CONF2_PHYCLKGD (1 << 7)
236#define CONF2_VBUSSENSE (1 << 6)
237#define CONF2_PHY_PLLON (1 << 5)
238#define CONF2_RESET (1 << 4)
239#define CONF2_PHYPWRDN (1 << 3)
240#define CONF2_OTGPWRDN (1 << 2)
241#define CONF2_DATPOL (1 << 1)
221 242
222#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) 243#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
223u32 omap1_usb0_init(unsigned nwires, unsigned is_device); 244u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 23:26:09 -0400