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-rw-r--r--arch/arm/plat-omap/include/plat/board-ams-delta.h49
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h9
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h51
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h6
-rw-r--r--arch/arm/plat-omap/include/plat/io.h277
-rw-r--r--arch/arm/plat-omap/include/plat/keypad.h2
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h9
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h2
-rw-r--r--arch/arm/plat-omap/include/plat/remoteproc.h57
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h1
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h1
-rw-r--r--arch/arm/plat-omap/include/plat/system.h15
-rw-r--r--arch/arm/plat-omap/include/plat/tc.h17
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h1
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h41
16 files changed, 164 insertions, 377 deletions
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906..ad6f865d1f1 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
@@ -28,33 +28,8 @@
28 28
29#if defined (CONFIG_MACH_AMS_DELTA) 29#if defined (CONFIG_MACH_AMS_DELTA)
30 30
31#define AMS_DELTA_LATCH1_PHYS 0x01000000
32#define AMS_DELTA_LATCH1_VIRT 0xEA000000
33#define AMS_DELTA_MODEM_PHYS 0x04000000
34#define AMS_DELTA_MODEM_VIRT 0xEB000000
35#define AMS_DELTA_LATCH2_PHYS 0x08000000
36#define AMS_DELTA_LATCH2_VIRT 0xEC000000
37
38#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
39#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
40#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
41#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
42#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
43#define AMS_DELTA_LATCH1_LED_VOICE 0x20
44
45#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
46#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
47#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
48#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
49#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
50#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
51#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
52#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
53#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
54#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
55#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400 31#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
56#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800 32#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
57#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
58#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000 33#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
59 34
60#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0 35#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
@@ -66,9 +41,29 @@
66#define AMS_DELTA_GPIO_PIN_CONFIG 11 41#define AMS_DELTA_GPIO_PIN_CONFIG 11
67#define AMS_DELTA_GPIO_PIN_NAND_RB 12 42#define AMS_DELTA_GPIO_PIN_NAND_RB 12
68 43
44#define AMS_DELTA_GPIO_PIN_LCD_VBLEN 240
45#define AMS_DELTA_GPIO_PIN_LCD_NDISP 241
46#define AMS_DELTA_GPIO_PIN_NAND_NCE 242
47#define AMS_DELTA_GPIO_PIN_NAND_NRE 243
48#define AMS_DELTA_GPIO_PIN_NAND_NWP 244
49#define AMS_DELTA_GPIO_PIN_NAND_NWE 245
50#define AMS_DELTA_GPIO_PIN_NAND_ALE 246
51#define AMS_DELTA_GPIO_PIN_NAND_CLE 247
52#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR 248
53#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT 249
54#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN 250
55#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC 251
56#define AMS_DELTA_GPIO_PIN_MODEM_NRESET 252
57#define AMS_DELTA_GPIO_PIN_MODEM_CODEC 253
58
59#define AMS_DELTA_LATCH2_GPIO_BASE AMS_DELTA_GPIO_PIN_LCD_VBLEN
60#define AMS_DELTA_LATCH2_NGPIO 16
61
69#ifndef __ASSEMBLY__ 62#ifndef __ASSEMBLY__
70void ams_delta_latch1_write(u8 mask, u8 value); 63void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value);
71void ams_delta_latch2_write(u16 mask, u16 value); 64#define ams_delta_latch2_write(mask, value) \
65 ams_delta_latch_write(AMS_DELTA_LATCH2_GPIO_BASE, \
66 AMS_DELTA_LATCH2_NGPIO, (mask), (value))
72#endif 67#endif
73 68
74#endif /* CONFIG_MACH_AMS_DELTA */ 69#endif /* CONFIG_MACH_AMS_DELTA */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 6b51086fce1..dc6a86bf217 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -250,7 +250,6 @@ IS_AM_SUBCLASS(335x, 0x335)
250 * cpu_is_omap2423(): True for OMAP2423 250 * cpu_is_omap2423(): True for OMAP2423
251 * cpu_is_omap2430(): True for OMAP2430 251 * cpu_is_omap2430(): True for OMAP2430
252 * cpu_is_omap3430(): True for OMAP3430 252 * cpu_is_omap3430(): True for OMAP3430
253 * cpu_is_omap4430(): True for OMAP4430
254 * cpu_is_omap3505(): True for OMAP3505 253 * cpu_is_omap3505(): True for OMAP3505
255 * cpu_is_omap3517(): True for OMAP3517 254 * cpu_is_omap3517(): True for OMAP3517
256 */ 255 */
@@ -299,7 +298,6 @@ IS_OMAP_TYPE(3517, 0x3517)
299#define cpu_is_omap3505() 0 298#define cpu_is_omap3505() 0
300#define cpu_is_omap3517() 0 299#define cpu_is_omap3517() 0
301#define cpu_is_omap3430() 0 300#define cpu_is_omap3430() 0
302#define cpu_is_omap4430() 0
303#define cpu_is_omap3630() 0 301#define cpu_is_omap3630() 0
304 302
305/* 303/*
@@ -451,7 +449,12 @@ IS_OMAP_TYPE(3517, 0x3517)
451#define OMAP447X_CLASS 0x44700044 449#define OMAP447X_CLASS 0x44700044
452#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) 450#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
453 451
454void omap2_check_revision(void); 452void omap2xxx_check_revision(void);
453void omap3xxx_check_revision(void);
454void omap4xxx_check_revision(void);
455void omap3xxx_check_features(void);
456void ti81xx_check_features(void);
457void omap4xxx_check_features(void);
455 458
456/* 459/*
457 * Runtime detection of OMAP3 features 460 * Runtime detection of OMAP3 features
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0aed0..b8a96c6a1a3 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -162,13 +162,6 @@
162 IH_MPUIO_BASE + ((nr) & 0x0f) : \ 162 IH_MPUIO_BASE + ((nr) & 0x0f) : \
163 IH_GPIO_BASE + (nr)) 163 IH_GPIO_BASE + (nr))
164 164
165#define METHOD_MPUIO 0
166#define METHOD_GPIO_1510 1
167#define METHOD_GPIO_1610 2
168#define METHOD_GPIO_7XX 3
169#define METHOD_GPIO_24XX 5
170#define METHOD_GPIO_44XX 6
171
172struct omap_gpio_dev_attr { 165struct omap_gpio_dev_attr {
173 int bank_width; /* GPIO bank width */ 166 int bank_width; /* GPIO bank width */
174 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 167 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs {
184 u16 irqstatus; 177 u16 irqstatus;
185 u16 irqstatus2; 178 u16 irqstatus2;
186 u16 irqenable; 179 u16 irqenable;
180 u16 irqenable2;
187 u16 set_irqenable; 181 u16 set_irqenable;
188 u16 clr_irqenable; 182 u16 clr_irqenable;
189 u16 debounce; 183 u16 debounce;
190 u16 debounce_en; 184 u16 debounce_en;
185 u16 ctrl;
186 u16 wkup_en;
187 u16 leveldetect0;
188 u16 leveldetect1;
189 u16 risingdetect;
190 u16 fallingdetect;
191 u16 irqctrl;
192 u16 edgectrl1;
193 u16 edgectrl2;
194 u16 pinctrl;
191 195
192 bool irqenable_inv; 196 bool irqenable_inv;
193}; 197};
@@ -198,45 +202,30 @@ struct omap_gpio_platform_data {
198 int bank_width; /* GPIO bank width */ 202 int bank_width; /* GPIO bank width */
199 int bank_stride; /* Only needed for omap1 MPUIO */ 203 int bank_stride; /* Only needed for omap1 MPUIO */
200 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 204 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
205 bool loses_context; /* whether the bank would ever lose context */
206 bool is_mpuio; /* whether the bank is of type MPUIO */
207 u32 non_wakeup_gpios;
201 208
202 struct omap_gpio_reg_offs *regs; 209 struct omap_gpio_reg_offs *regs;
203};
204 210
205/* TODO: Analyze removing gpio_bank_count usage from driver code */ 211 /* Return context loss count due to PM states changing */
206extern int gpio_bank_count; 212 int (*get_context_loss_count)(struct device *dev);
213};
207 214
208extern void omap2_gpio_prepare_for_idle(int off_mode); 215extern void omap2_gpio_prepare_for_idle(int off_mode);
209extern void omap2_gpio_resume_after_idle(void); 216extern void omap2_gpio_resume_after_idle(void);
210extern void omap_set_gpio_debounce(int gpio, int enable); 217extern void omap_set_gpio_debounce(int gpio, int enable);
211extern void omap_set_gpio_debounce_time(int gpio, int enable); 218extern void omap_set_gpio_debounce_time(int gpio, int enable);
212extern void omap_gpio_save_context(void);
213extern void omap_gpio_restore_context(void);
214/*-------------------------------------------------------------------------*/ 219/*-------------------------------------------------------------------------*/
215 220
216/* Wrappers for "new style" GPIO calls, using the new infrastructure 221/*
222 * Wrappers for "new style" GPIO calls, using the new infrastructure
217 * which lets us plug in FPGA, I2C, and other implementations. 223 * which lets us plug in FPGA, I2C, and other implementations.
218 * * 224 *
219 * The original OMAP-specific calls should eventually be removed. 225 * The original OMAP-specific calls should eventually be removed.
220 */ 226 */
221 227
222#include <linux/errno.h> 228#include <linux/errno.h>
223#include <asm-generic/gpio.h> 229#include <asm-generic/gpio.h>
224 230
225static inline int irq_to_gpio(unsigned irq)
226{
227 int tmp;
228
229 /* omap1 SOC mpuio */
230 if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
231 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
232
233 /* SOC gpio */
234 tmp = irq - IH_GPIO_BASE;
235 if (tmp < OMAP_MAX_GPIO_LINES)
236 return tmp;
237
238 /* we don't supply reverse mappings for non-SOC gpios */
239 return -EIO;
240}
241
242#endif 231#endif
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c..537b05ae1f5 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -43,6 +43,12 @@
43#endif 43#endif
44#include <plat/serial.h> 44#include <plat/serial.h>
45 45
46#ifdef __ASSEMBLER__
47#define IOMEM(x) (x)
48#else
49#define IOMEM(x) ((void __force __iomem *)(x))
50#endif
51
46/* 52/*
47 * --------------------------------------------------------------------------- 53 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors 54 * Common definitions for all OMAP processors
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
deleted file mode 100644
index 0696bae1818..00000000000
--- a/arch/arm/plat-omap/include/plat/io.h
+++ /dev/null
@@ -1,277 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/io.h
3 *
4 * IO definitions for TI OMAP processors and boards
5 *
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 * Modifications:
33 * 06-12-1997 RMK Created.
34 * 07-04-1999 RMK Major cleanup
35 */
36
37#ifndef __ASM_ARM_ARCH_IO_H
38#define __ASM_ARM_ARCH_IO_H
39
40#include <mach/hardware.h>
41
42#define IO_SPACE_LIMIT 0xffffffff
43
44/*
45 * We don't actually have real ISA nor PCI buses, but there is so many
46 * drivers out there that might just work if we fake them...
47 */
48#define __io(a) __typesafe_io(a)
49#define __mem_pci(a) (a)
50
51/*
52 * ----------------------------------------------------------------------------
53 * I/O mapping
54 * ----------------------------------------------------------------------------
55 */
56
57#ifdef __ASSEMBLER__
58#define IOMEM(x) (x)
59#else
60#define IOMEM(x) ((void __force __iomem *)(x))
61#endif
62
63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
65
66#define OMAP2_L3_IO_OFFSET 0x90000000
67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
68
69
70#define OMAP2_L4_IO_OFFSET 0xb2000000
71#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
72
73#define OMAP4_L3_IO_OFFSET 0xb4000000
74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
75
76#define AM33XX_L4_WK_IO_OFFSET 0xb5000000
77#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
78
79#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
80#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
81
82#define OMAP4_GPMC_IO_OFFSET 0xa9000000
83#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
84
85#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
86#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
87
88/*
89 * ----------------------------------------------------------------------------
90 * Omap1 specific IO mapping
91 * ----------------------------------------------------------------------------
92 */
93
94#define OMAP1_IO_PHYS 0xFFFB0000
95#define OMAP1_IO_SIZE 0x40000
96#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
97
98/*
99 * ----------------------------------------------------------------------------
100 * Omap2 specific IO mapping
101 * ----------------------------------------------------------------------------
102 */
103
104/* We map both L3 and L4 on OMAP2 */
105#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
106#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
107#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
108#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
109#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
110#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
111
112#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
113#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
114#define L4_WK_243X_SIZE SZ_1M
115#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
116#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
117 /* 0x6e000000 --> 0xfe000000 */
118#define OMAP243X_GPMC_SIZE SZ_1M
119#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
120 /* 0x6D000000 --> 0xfd000000 */
121#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
122#define OMAP243X_SDRC_SIZE SZ_1M
123#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
124 /* 0x6c000000 --> 0xfc000000 */
125#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
126#define OMAP243X_SMS_SIZE SZ_1M
127
128/* 2420 IVA */
129#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
130 /* 0x58000000 --> 0xfc100000 */
131#define DSP_MEM_2420_VIRT 0xfc100000
132#define DSP_MEM_2420_SIZE 0x28000
133#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
134 /* 0x59000000 --> 0xfc128000 */
135#define DSP_IPI_2420_VIRT 0xfc128000
136#define DSP_IPI_2420_SIZE SZ_4K
137#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
138 /* 0x5a000000 --> 0xfc129000 */
139#define DSP_MMU_2420_VIRT 0xfc129000
140#define DSP_MMU_2420_SIZE SZ_4K
141
142/* 2430 IVA2.1 - currently unmapped */
143
144/*
145 * ----------------------------------------------------------------------------
146 * Omap3 specific IO mapping
147 * ----------------------------------------------------------------------------
148 */
149
150/* We map both L3 and L4 on OMAP3 */
151#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
152#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
153#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
154
155#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
156#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
157#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
158
159/*
160 * ----------------------------------------------------------------------------
161 * AM33XX specific IO mapping
162 * ----------------------------------------------------------------------------
163 */
164#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
165#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
166#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
167
168/*
169 * Need to look at the Size 4M for L4.
170 * VPOM3430 was not working for Int controller
171 */
172
173#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
174 /* 0x49000000 --> 0xfb000000 */
175#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
176#define L4_PER_34XX_SIZE SZ_1M
177
178#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
179 /* 0x54000000 --> 0xfe800000 */
180#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
181#define L4_EMU_34XX_SIZE SZ_8M
182
183#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
184 /* 0x6e000000 --> 0xfe000000 */
185#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
186#define OMAP34XX_GPMC_SIZE SZ_1M
187
188#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
189 /* 0x6c000000 --> 0xfc000000 */
190#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
191#define OMAP343X_SMS_SIZE SZ_1M
192
193#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
194 /* 0x6D000000 --> 0xfd000000 */
195#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
196#define OMAP343X_SDRC_SIZE SZ_1M
197
198/* 3430 IVA - currently unmapped */
199
200/*
201 * ----------------------------------------------------------------------------
202 * Omap4 specific IO mapping
203 * ----------------------------------------------------------------------------
204 */
205
206/* We map both L3 and L4 on OMAP4 */
207#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
208#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
209#define L3_44XX_SIZE SZ_1M
210
211#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
212#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
213#define L4_44XX_SIZE SZ_4M
214
215#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
216 /* 0x48000000 --> 0xfa000000 */
217#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
218#define L4_PER_44XX_SIZE SZ_4M
219
220#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
221 /* 0x49000000 --> 0xfb000000 */
222#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
223#define L4_ABE_44XX_SIZE SZ_1M
224
225#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
226 /* 0x54000000 --> 0xfe800000 */
227#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
228#define L4_EMU_44XX_SIZE SZ_8M
229
230#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
231 /* 0x50000000 --> 0xf9000000 */
232#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
233#define OMAP44XX_GPMC_SIZE SZ_1M
234
235
236#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
237 /* 0x4c000000 --> 0xfd100000 */
238#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
239#define OMAP44XX_EMIF1_SIZE SZ_1M
240
241#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
242 /* 0x4d000000 --> 0xfd200000 */
243#define OMAP44XX_EMIF2_SIZE SZ_1M
244#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
245
246#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
247 /* 0x4e000000 --> 0xfd300000 */
248#define OMAP44XX_DMM_SIZE SZ_1M
249#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
250/*
251 * ----------------------------------------------------------------------------
252 * Omap specific register access
253 * ----------------------------------------------------------------------------
254 */
255
256#ifndef __ASSEMBLER__
257
258/*
259 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
260 */
261
262extern u8 omap_readb(u32 pa);
263extern u16 omap_readw(u32 pa);
264extern u32 omap_readl(u32 pa);
265extern void omap_writeb(u8 v, u32 pa);
266extern void omap_writew(u16 v, u32 pa);
267extern void omap_writel(u32 v, u32 pa);
268
269struct omap_sdrc_params;
270extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
271 struct omap_sdrc_params *sdrc_cs1);
272
273extern void __init omap_init_consistent_dma_size(void);
274
275#endif
276
277#endif
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 793ce9d5329..a6b21eddb21 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -12,6 +12,8 @@
12 12
13#ifndef CONFIG_ARCH_OMAP1 13#ifndef CONFIG_ARCH_OMAP1
14#warning Please update the board to use matrix-keypad driver 14#warning Please update the board to use matrix-keypad driver
15#define omap_readw(reg) 0
16#define omap_writew(val, reg) do {} while (0)
15#endif 17#endif
16#include <linux/input/matrix_keypad.h> 18#include <linux/input/matrix_keypad.h>
17 19
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 3d51b18131c..a357eb26bd2 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -18,9 +18,6 @@ struct omap2_mcspi_dev_attr {
18 18
19struct omap2_mcspi_device_config { 19struct omap2_mcspi_device_config {
20 unsigned turbo_mode:1; 20 unsigned turbo_mode:1;
21
22 /* Do we want one channel enabled at the same time? */
23 unsigned single_channel:1;
24}; 21};
25 22
26#endif 23#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 51423d2727a..4327b2c90c3 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,7 +36,7 @@
36 36
37#include <plat/omap_hwmod.h> 37#include <plat/omap_hwmod.h>
38 38
39extern struct device omap_device_parent; 39extern struct dev_pm_domain omap_device_pm_domain;
40 40
41/* omap_device._state values */ 41/* omap_device._state values */
42#define OMAP_DEVICE_STATE_UNKNOWN 0 42#define OMAP_DEVICE_STATE_UNKNOWN 0
@@ -100,6 +100,13 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
100 struct omap_device_pm_latency *pm_lats, 100 struct omap_device_pm_latency *pm_lats,
101 int pm_lats_cnt, int is_early_device); 101 int pm_lats_cnt, int is_early_device);
102 102
103struct omap_device *omap_device_alloc(struct platform_device *pdev,
104 struct omap_hwmod **ohs, int oh_cnt,
105 struct omap_device_pm_latency *pm_lats,
106 int pm_lats_cnt);
107void omap_device_delete(struct omap_device *od);
108int omap_device_register(struct platform_device *pdev);
109
103void __iomem *omap_device_get_rt_va(struct omap_device *od); 110void __iomem *omap_device_get_rt_va(struct omap_device *od);
104struct device *omap_device_get_by_hwmod_name(const char *oh_name); 111struct device *omap_device_get_by_hwmod_name(const char *oh_name);
105 112
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 647010109af..9e8e63d52aa 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -484,7 +484,6 @@ struct omap_hwmod_class {
484 * @main_clk: main clock: OMAP clock name 484 * @main_clk: main clock: OMAP clock name
485 * @_clk: pointer to the main struct clk (filled in at runtime) 485 * @_clk: pointer to the main struct clk (filled in at runtime)
486 * @opt_clks: other device clocks that drivers can request (0..*) 486 * @opt_clks: other device clocks that drivers can request (0..*)
487 * @vdd_name: voltage domain name
488 * @voltdm: pointer to voltage domain (filled in at runtime) 487 * @voltdm: pointer to voltage domain (filled in at runtime)
489 * @masters: ptr to array of OCP ifs that this hwmod can initiate on 488 * @masters: ptr to array of OCP ifs that this hwmod can initiate on
490 * @slaves: ptr to array of OCP ifs that this hwmod can respond on 489 * @slaves: ptr to array of OCP ifs that this hwmod can respond on
@@ -528,7 +527,6 @@ struct omap_hwmod {
528 struct omap_hwmod_opt_clk *opt_clks; 527 struct omap_hwmod_opt_clk *opt_clks;
529 char *clkdm_name; 528 char *clkdm_name;
530 struct clockdomain *clkdm; 529 struct clockdomain *clkdm;
531 char *vdd_name;
532 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ 530 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
533 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ 531 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
534 void *dev_attr; 532 void *dev_attr;
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
new file mode 100644
index 00000000000..b10eac89e2e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/remoteproc.h
@@ -0,0 +1,57 @@
1/*
2 * Remote Processor - omap-specific bits
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Copyright (C) 2011 Google, Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _PLAT_REMOTEPROC_H
18#define _PLAT_REMOTEPROC_H
19
20struct rproc_ops;
21struct platform_device;
22
23/*
24 * struct omap_rproc_pdata - omap remoteproc's platform data
25 * @name: the remoteproc's name
26 * @oh_name: omap hwmod device
27 * @oh_name_opt: optional, secondary omap hwmod device
28 * @firmware: name of firmware file to load
29 * @mbox_name: name of omap mailbox device to use with this rproc
30 * @ops: start/stop rproc handlers
31 * @device_enable: omap-specific handler for enabling a device
32 * @device_shutdown: omap-specific handler for shutting down a device
33 */
34struct omap_rproc_pdata {
35 const char *name;
36 const char *oh_name;
37 const char *oh_name_opt;
38 const char *firmware;
39 const char *mbox_name;
40 const struct rproc_ops *ops;
41 int (*device_enable) (struct platform_device *pdev);
42 int (*device_shutdown) (struct platform_device *pdev);
43};
44
45#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
46
47void __init omap_rproc_reserve_cma(void);
48
49#else
50
51void __init omap_rproc_reserve_cma(void)
52{
53}
54
55#endif
56
57#endif /* _PLAT_REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 198d1e6a4a6..b073e5f2b19 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -110,7 +110,6 @@ struct omap_board_data;
110struct omap_uart_port_info; 110struct omap_uart_port_info;
111 111
112extern void omap_serial_init(void); 112extern void omap_serial_init(void);
113extern int omap_uart_can_sleep(void);
114extern void omap_serial_board_init(struct omap_uart_port_info *platform_data); 113extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
115extern void omap_serial_init_port(struct omap_board_data *bdata, 114extern void omap_serial_init_port(struct omap_board_data *bdata,
116 struct omap_uart_port_info *platform_data); 115 struct omap_uart_port_info *platform_data);
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 75aa1b2bef5..227ae265755 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -101,4 +101,5 @@ static inline void omap_push_sram_idle(void) {}
101#else 101#else
102#define OMAP4_SRAM_PA 0x40300000 102#define OMAP4_SRAM_PA 0x40300000
103#endif 103#endif
104#define AM33XX_SRAM_PA 0x40300000
104#endif 105#endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
deleted file mode 100644
index 8e5ebd74b12..00000000000
--- a/arch/arm/plat-omap/include/plat/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copied from arch/arm/mach-sa1100/include/mach/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
4 */
5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H
7
8#include <asm/proc-fns.h>
9
10static inline void arch_idle(void)
11{
12 cpu_do_idle();
13}
14
15#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9..1b4b2da8620 100644
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
@@ -84,23 +84,6 @@
84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) 84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) 85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
86 86
87/* Almost all documentation for chip and board memory maps assumes
88 * BM is clear. Most devel boards have a switch to control booting
89 * from NOR flash (using external chipselect 3) rather than mask ROM,
90 * which uses BM to interchange the physical CS0 and CS3 addresses.
91 */
92static inline u32 omap_cs0_phys(void)
93{
94 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
95 ? OMAP_CS3_PHYS : 0;
96}
97
98static inline u32 omap_cs3_phys(void)
99{
100 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
101 ? 0 : OMAP_CS3_PHYS;
102}
103
104#endif /* __ASSEMBLER__ */ 87#endif /* __ASSEMBLER__ */
105 88
106#endif /* __ASM_ARCH_TC_H */ 89#endif /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 6ee90495ca4..cc3f11ba7a9 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -160,6 +160,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
160 DEBUG_LL_OMAP3(3, igep0020); 160 DEBUG_LL_OMAP3(3, igep0020);
161 DEBUG_LL_OMAP3(3, igep0030); 161 DEBUG_LL_OMAP3(3, igep0030);
162 DEBUG_LL_OMAP3(3, nokia_rm680); 162 DEBUG_LL_OMAP3(3, nokia_rm680);
163 DEBUG_LL_OMAP3(3, nokia_rm696);
163 DEBUG_LL_OMAP3(3, nokia_rx51); 164 DEBUG_LL_OMAP3(3, nokia_rx51);
164 DEBUG_LL_OMAP3(3, omap3517evm); 165 DEBUG_LL_OMAP3(3, omap3517evm);
165 DEBUG_LL_OMAP3(3, omap3_beagle); 166 DEBUG_LL_OMAP3(3, omap3_beagle);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index dc864b580da..d0fc9f4dc15 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,6 +3,7 @@
3#ifndef __ASM_ARCH_OMAP_USB_H 3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H 4#define __ASM_ARCH_OMAP_USB_H
5 5
6#include <linux/io.h>
6#include <linux/usb/musb.h> 7#include <linux/usb/musb.h>
7#include <plat/board.h> 8#include <plat/board.h>
8 9
@@ -105,6 +106,46 @@ extern int omap4430_phy_set_clk(struct device *dev, int on);
105extern int omap4430_phy_init(struct device *dev); 106extern int omap4430_phy_init(struct device *dev);
106extern int omap4430_phy_exit(struct device *dev); 107extern int omap4430_phy_exit(struct device *dev);
107extern int omap4430_phy_suspend(struct device *dev, int suspend); 108extern int omap4430_phy_suspend(struct device *dev, int suspend);
109
110/*
111 * NOTE: Please update omap USB drivers to use ioremap + read/write
112 */
113
114#define OMAP2_L4_IO_OFFSET 0xb2000000
115#define IOMEM(x) ((void __force __iomem *)(x))
116#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
117
118static inline u8 omap_readb(u32 pa)
119{
120 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
121}
122
123static inline u16 omap_readw(u32 pa)
124{
125 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
126}
127
128static inline u32 omap_readl(u32 pa)
129{
130 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
131}
132
133static inline void omap_writeb(u8 v, u32 pa)
134{
135 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
136}
137
138
139static inline void omap_writew(u16 v, u32 pa)
140{
141 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
142}
143
144static inline void omap_writel(u32 v, u32 pa)
145{
146 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
147}
148
108#endif 149#endif
109 150
110extern void am35x_musb_reset(void); 151extern void am35x_musb_reset(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 04:11:32 -0400