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-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S58
1 files changed, 1 insertions, 57 deletions
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 066d464d322..842fbcb0d6c 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,72 +9,16 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <mach/hardware.h> 12/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
13 13
14#define AVIC_NIMASK 0x04
15
16 @ this macro disables fast irq (not implemented)
17 .macro disable_fiq 14 .macro disable_fiq
18 .endm 15 .endm
19 16
20 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
21#ifndef CONFIG_MXC_TZIC
22 ldr \base, =avic_base
23 ldr \base, [\base]
24#ifdef CONFIG_MXC_IRQ_PRIOR
25 ldr r4, [\base, #AVIC_NIMASK]
26#endif
27#elif defined CONFIG_MXC_TZIC
28 ldr \base, =tzic_base
29 ldr \base, [\base]
30#endif /* CONFIG_MXC_TZIC */
31 .endm 18 .endm
32 19
33 .macro arch_ret_to_user, tmp1, tmp2 20 .macro arch_ret_to_user, tmp1, tmp2
34 .endm 21 .endm
35 22
36 @ this macro checks which interrupt occurred
37 @ and returns its number in irqnr
38 @ and returns if an interrupt occurred in irqstat
39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40#ifndef CONFIG_MXC_TZIC
41 @ Load offset & priority of the highest priority
42 @ interrupt pending from AVIC_NIVECSR
43 ldr \irqstat, [\base, #0x40]
44 @ Shift to get the decoded IRQ number, using ASR so
45 @ 'no interrupt pending' becomes 0xffffffff
46 mov \irqnr, \irqstat, asr #16
47 @ set zero flag if IRQ + 1 == 0
48 adds \tmp, \irqnr, #1
49#ifdef CONFIG_MXC_IRQ_PRIOR
50 bicne \tmp, \irqstat, #0xFFFFFFE0
51 strne \tmp, [\base, #AVIC_NIMASK]
52 streq r4, [\base, #AVIC_NIMASK]
53#endif
54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
56 @ interrupt pending.
57 @ 0x080 is INTSEC0 register
58 @ 0xD80 is HIPND0 register
59 mov \irqnr, #0
601000: add \irqstat, \base, \irqnr, lsr #3
61 ldr \tmp, [\irqstat, #0xd80]
62 ldr \irqstat, [\irqstat, #0x080]
63 ands \tmp, \tmp, \irqstat
64 bne 1001f
65 add \irqnr, \irqnr, #32
66 cmp \irqnr, #128
67 blo 1000b
68 b 2001f
691001: mov \irqstat, #1
701002: tst \tmp, \irqstat
71 bne 2002f
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
74 bne 1002b
752001:
76 mov \irqnr, #0
772002:
78 movs \irqnr, \irqnr
79#endif
80 .endm 24 .endm