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-rw-r--r--arch/arm/mm/abort-ev4.S17
-rw-r--r--arch/arm/mm/abort-ev4t.S17
-rw-r--r--arch/arm/mm/abort-ev5t.S19
-rw-r--r--arch/arm/mm/abort-ev5tj.S25
-rw-r--r--arch/arm/mm/abort-ev6.S25
-rw-r--r--arch/arm/mm/abort-ev7.S25
-rw-r--r--arch/arm/mm/abort-lv4t.S141
-rw-r--r--arch/arm/mm/abort-macro.S34
-rw-r--r--arch/arm/mm/abort-nommu.S10
-rw-r--r--arch/arm/mm/alignment.c3
-rw-r--r--arch/arm/mm/cache-l2x0.c19
-rw-r--r--arch/arm/mm/context.c17
-rw-r--r--arch/arm/mm/dma-mapping.c35
-rw-r--r--arch/arm/mm/fault.c4
-rw-r--r--arch/arm/mm/init.c26
-rw-r--r--arch/arm/mm/mm.h6
-rw-r--r--arch/arm/mm/mmu.c5
-rw-r--r--arch/arm/mm/nommu.c4
-rw-r--r--arch/arm/mm/pabort-legacy.S10
-rw-r--r--arch/arm/mm/pabort-v6.S10
-rw-r--r--arch/arm/mm/pabort-v7.S11
-rw-r--r--arch/arm/mm/proc-arm6_7.S90
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S2
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S2
-rw-r--r--arch/arm/mm/proc-sa1100.S4
-rw-r--r--arch/arm/mm/proc-v7.S26
-rw-r--r--arch/arm/mm/tlb-fa.S4
-rw-r--r--arch/arm/mm/tlb-v6.S4
-rw-r--r--arch/arm/mm/tlb-v7.S6
29 files changed, 319 insertions, 282 deletions
diff --git a/arch/arm/mm/abort-ev4.S b/arch/arm/mm/abort-ev4.S
index 4f18f9e87ba..54473cd4aba 100644
--- a/arch/arm/mm/abort-ev4.S
+++ b/arch/arm/mm/abort-ev4.S
@@ -3,14 +3,11 @@
3/* 3/*
4 * Function: v4_early_abort 4 * Function: v4_early_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r2 = pt_regs
7 * : r3 = saved SPSR 7 * : r4 = aborted context pc
8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = address of abort 10 * Returns : r4 - r11, r13 preserved
10 * : r1 = FSR, bit 11 = write
11 * : r2-r8 = corrupted
12 * : r9 = preserved
13 * : sp = pointer to registers
14 * 11 *
15 * Purpose : obtain information about current aborted instruction. 12 * Purpose : obtain information about current aborted instruction.
16 * Note: we read user space. This means we might cause a data 13 * Note: we read user space. This means we might cause a data
@@ -21,10 +18,8 @@
21ENTRY(v4_early_abort) 18ENTRY(v4_early_abort)
22 mrc p15, 0, r1, c5, c0, 0 @ get FSR 19 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR 20 mrc p15, 0, r0, c6, c0, 0 @ get FAR
24 ldr r3, [r2] @ read aborted ARM instruction 21 ldr r3, [r4] @ read aborted ARM instruction
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 22 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r3, #1 << 20 @ L = 1 -> write? 23 tst r3, #1 << 20 @ L = 1 -> write?
27 orreq r1, r1, #1 << 11 @ yes. 24 orreq r1, r1, #1 << 11 @ yes.
28 mov pc, lr 25 b do_DataAbort
29
30
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index b6282548f92..9da704e7b86 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v4t_early_abort 5 * Function: v4t_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r3 = saved SPSR 8 * : r4 = aborted context pc
9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -22,9 +19,9 @@
22ENTRY(v4t_early_abort) 19ENTRY(v4t_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 do_thumb_abort 22 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
26 ldreq r3, [r2] @ read aborted ARM instruction 23 ldreq r3, [r4] @ read aborted ARM instruction
27 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 24 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
28 tst r3, #1 << 20 @ check write 25 tst r3, #1 << 20 @ check write
29 orreq r1, r1, #1 << 11 26 orreq r1, r1, #1 << 11
30 mov pc, lr 27 b do_DataAbort
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 02251b526c0..a0908d4653a 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v5t_early_abort 5 * Function: v5t_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r3 = saved SPSR 8 * : r4 = aborted context pc
9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -22,10 +19,10 @@
22ENTRY(v5t_early_abort) 19ENTRY(v5t_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 do_thumb_abort 22 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
26 ldreq r3, [r2] @ read aborted ARM instruction 23 ldreq r3, [r4] @ read aborted ARM instruction
27 bic r1, r1, #1 << 11 @ clear bits 11 of FSR 24 bic r1, r1, #1 << 11 @ clear bits 11 of FSR
28 do_ldrd_abort 25 do_ldrd_abort tmp=ip, insn=r3
29 tst r3, #1 << 20 @ check write 26 tst r3, #1 << 20 @ check write
30 orreq r1, r1, #1 << 11 27 orreq r1, r1, #1 << 11
31 mov pc, lr 28 b do_DataAbort
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bce68d601c8..4006b7a6126 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v5tj_early_abort 5 * Function: v5tj_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r3 = saved SPSR 8 * : r4 = aborted context pc
9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -23,13 +20,11 @@ ENTRY(v5tj_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 22 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r3, #PSR_J_BIT @ Java? 23 tst r5, #PSR_J_BIT @ Java?
27 movne pc, lr 24 bne do_DataAbort
28 do_thumb_abort 25 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
29 ldreq r3, [r2] @ read aborted ARM instruction 26 ldreq r3, [r4] @ read aborted ARM instruction
30 do_ldrd_abort 27 do_ldrd_abort tmp=ip, insn=r3
31 tst r3, #1 << 20 @ L = 0 -> write 28 tst r3, #1 << 20 @ L = 0 -> write
32 orreq r1, r1, #1 << 11 @ yes. 29 orreq r1, r1, #1 << 11 @ yes.
33 mov pc, lr 30 b do_DataAbort
34
35
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 1478aa52214..ff1f7cc11f8 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -4,14 +4,11 @@
4/* 4/*
5 * Function: v6_early_abort 5 * Function: v6_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r3 = saved SPSR 8 * : r4 = aborted context pc
9 * : r5 = aborted context psr
9 * 10 *
10 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
11 * : r1 = FSR, bit 11 = write
12 * : r2-r8 = corrupted
13 * : r9 = preserved
14 * : sp = pointer to registers
15 * 12 *
16 * Purpose : obtain information about current aborted instruction. 13 * Purpose : obtain information about current aborted instruction.
17 * Note: we read user space. This means we might cause a data 14 * Note: we read user space. This means we might cause a data
@@ -33,16 +30,14 @@ ENTRY(v6_early_abort)
33 * The test below covers all the write situations, including Java bytecodes 30 * The test below covers all the write situations, including Java bytecodes
34 */ 31 */
35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR 32 bic r1, r1, #1 << 11 @ clear bit 11 of FSR
36 tst r3, #PSR_J_BIT @ Java? 33 tst r5, #PSR_J_BIT @ Java?
37 movne pc, lr 34 bne do_DataAbort
38 do_thumb_abort 35 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
39 ldreq r3, [r2] @ read aborted ARM instruction 36 ldreq r3, [r4] @ read aborted ARM instruction
40#ifdef CONFIG_CPU_ENDIAN_BE8 37#ifdef CONFIG_CPU_ENDIAN_BE8
41 reveq r3, r3 38 reveq r3, r3
42#endif 39#endif
43 do_ldrd_abort 40 do_ldrd_abort tmp=ip, insn=r3
44 tst r3, #1 << 20 @ L = 0 -> write 41 tst r3, #1 << 20 @ L = 0 -> write
45 orreq r1, r1, #1 << 11 @ yes. 42 orreq r1, r1, #1 << 11 @ yes.
46 mov pc, lr 43 b do_DataAbort
47
48
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index ec88b157d3b..703375277ba 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -3,14 +3,11 @@
3/* 3/*
4 * Function: v7_early_abort 4 * Function: v7_early_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r2 = pt_regs
7 * : r3 = saved SPSR 7 * : r4 = aborted context pc
8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = address of abort 10 * Returns : r4 - r11, r13 preserved
10 * : r1 = FSR, bit 11 = write
11 * : r2-r8 = corrupted
12 * : r9 = preserved
13 * : sp = pointer to registers
14 * 11 *
15 * Purpose : obtain information about current aborted instruction. 12 * Purpose : obtain information about current aborted instruction.
16 */ 13 */
@@ -37,18 +34,18 @@ ENTRY(v7_early_abort)
37 ldr r3, =0x40d @ On permission fault 34 ldr r3, =0x40d @ On permission fault
38 and r3, r1, r3 35 and r3, r1, r3
39 cmp r3, #0x0d 36 cmp r3, #0x0d
40 movne pc, lr 37 bne do_DataAbort
41 38
42 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR 39 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
43 isb 40 isb
44 mrc p15, 0, r2, c7, c4, 0 @ Read the PAR 41 mrc p15, 0, ip, c7, c4, 0 @ Read the PAR
45 and r3, r2, #0x7b @ On translation fault 42 and r3, ip, #0x7b @ On translation fault
46 cmp r3, #0x0b 43 cmp r3, #0x0b
47 movne pc, lr 44 bne do_DataAbort
48 bic r1, r1, #0xf @ Fix up FSR FS[5:0] 45 bic r1, r1, #0xf @ Fix up FSR FS[5:0]
49 and r2, r2, #0x7e 46 and ip, ip, #0x7e
50 orr r1, r1, r2, LSR #1 47 orr r1, r1, ip, LSR #1
51#endif 48#endif
52 49
53 mov pc, lr 50 b do_DataAbort
54ENDPROC(v7_early_abort) 51ENDPROC(v7_early_abort)
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index 9fb7b0e25ea..f3982580c27 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -3,14 +3,11 @@
3/* 3/*
4 * Function: v4t_late_abort 4 * Function: v4t_late_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r2 = pt_regs
7 * : r3 = saved SPSR 7 * : r4 = aborted context pc
8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = address of abort 10 * Returns : r4-r5, r10-r11, r13 preserved
10 * : r1 = FSR, bit 11 = write
11 * : r2-r8 = corrupted
12 * : r9 = preserved
13 * : sp = pointer to registers
14 * 11 *
15 * Purpose : obtain information about current aborted instruction. 12 * Purpose : obtain information about current aborted instruction.
16 * Note: we read user space. This means we might cause a data 13 * Note: we read user space. This means we might cause a data
@@ -18,7 +15,7 @@
18 * picture. Unfortunately, this does happen. We live with it. 15 * picture. Unfortunately, this does happen. We live with it.
19 */ 16 */
20ENTRY(v4t_late_abort) 17ENTRY(v4t_late_abort)
21 tst r3, #PSR_T_BIT @ check for thumb mode 18 tst r5, #PSR_T_BIT @ check for thumb mode
22#ifdef CONFIG_CPU_CP15_MMU 19#ifdef CONFIG_CPU_CP15_MMU
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
@@ -28,7 +25,7 @@ ENTRY(v4t_late_abort)
28 mov r1, #0 25 mov r1, #0
29#endif 26#endif
30 bne .data_thumb_abort 27 bne .data_thumb_abort
31 ldr r8, [r2] @ read arm instruction 28 ldr r8, [r4] @ read arm instruction
32 tst r8, #1 << 20 @ L = 1 -> write? 29 tst r8, #1 << 20 @ L = 1 -> write?
33 orreq r1, r1, #1 << 11 @ yes. 30 orreq r1, r1, #1 << 11 @ yes.
34 and r7, r8, #15 << 24 31 and r7, r8, #15 << 24
@@ -47,86 +44,84 @@ ENTRY(v4t_late_abort)
47/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> 44/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
48/* a */ b .data_unknown 45/* a */ b .data_unknown
49/* b */ b .data_unknown 46/* b */ b .data_unknown
50/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m 47/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
51/* d */ mov pc, lr @ ldc rd, [rn, #m] 48/* d */ b do_DataAbort @ ldc rd, [rn, #m]
52/* e */ b .data_unknown 49/* e */ b .data_unknown
53/* f */ 50/* f */
54.data_unknown: @ Part of jumptable 51.data_unknown: @ Part of jumptable
55 mov r0, r2 52 mov r0, r4
56 mov r1, r8 53 mov r1, r8
57 mov r2, sp 54 b baddataabort
58 bl baddataabort
59 b ret_from_exception
60 55
61.data_arm_ldmstm: 56.data_arm_ldmstm:
62 tst r8, #1 << 21 @ check writeback bit 57 tst r8, #1 << 21 @ check writeback bit
63 moveq pc, lr @ no writeback -> no fixup 58 beq do_DataAbort @ no writeback -> no fixup
64 mov r7, #0x11 59 mov r7, #0x11
65 orr r7, r7, #0x1100 60 orr r7, r7, #0x1100
66 and r6, r8, r7 61 and r6, r8, r7
67 and r2, r8, r7, lsl #1 62 and r9, r8, r7, lsl #1
68 add r6, r6, r2, lsr #1 63 add r6, r6, r9, lsr #1
69 and r2, r8, r7, lsl #2 64 and r9, r8, r7, lsl #2
70 add r6, r6, r2, lsr #2 65 add r6, r6, r9, lsr #2
71 and r2, r8, r7, lsl #3 66 and r9, r8, r7, lsl #3
72 add r6, r6, r2, lsr #3 67 add r6, r6, r9, lsr #3
73 add r6, r6, r6, lsr #8 68 add r6, r6, r6, lsr #8
74 add r6, r6, r6, lsr #4 69 add r6, r6, r6, lsr #4
75 and r6, r6, #15 @ r6 = no. of registers to transfer. 70 and r6, r6, #15 @ r6 = no. of registers to transfer.
76 and r5, r8, #15 << 16 @ Extract 'n' from instruction 71 and r9, r8, #15 << 16 @ Extract 'n' from instruction
77 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 72 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
78 tst r8, #1 << 23 @ Check U bit 73 tst r8, #1 << 23 @ Check U bit
79 subne r7, r7, r6, lsl #2 @ Undo increment 74 subne r7, r7, r6, lsl #2 @ Undo increment
80 addeq r7, r7, r6, lsl #2 @ Undo decrement 75 addeq r7, r7, r6, lsl #2 @ Undo decrement
81 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 76 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
82 mov pc, lr 77 b do_DataAbort
83 78
84.data_arm_lateldrhpre: 79.data_arm_lateldrhpre:
85 tst r8, #1 << 21 @ Check writeback bit 80 tst r8, #1 << 21 @ Check writeback bit
86 moveq pc, lr @ No writeback -> no fixup 81 beq do_DataAbort @ No writeback -> no fixup
87.data_arm_lateldrhpost: 82.data_arm_lateldrhpost:
88 and r5, r8, #0x00f @ get Rm / low nibble of immediate value 83 and r9, r8, #0x00f @ get Rm / low nibble of immediate value
89 tst r8, #1 << 22 @ if (immediate offset) 84 tst r8, #1 << 22 @ if (immediate offset)
90 andne r6, r8, #0xf00 @ { immediate high nibble 85 andne r6, r8, #0xf00 @ { immediate high nibble
91 orrne r6, r5, r6, lsr #4 @ combine nibbles } else 86 orrne r6, r9, r6, lsr #4 @ combine nibbles } else
92 ldreq r6, [sp, r5, lsl #2] @ { load Rm value } 87 ldreq r6, [r2, r9, lsl #2] @ { load Rm value }
93.data_arm_apply_r6_and_rn: 88.data_arm_apply_r6_and_rn:
94 and r5, r8, #15 << 16 @ Extract 'n' from instruction 89 and r9, r8, #15 << 16 @ Extract 'n' from instruction
95 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 90 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
96 tst r8, #1 << 23 @ Check U bit 91 tst r8, #1 << 23 @ Check U bit
97 subne r7, r7, r6 @ Undo incrmenet 92 subne r7, r7, r6 @ Undo incrmenet
98 addeq r7, r7, r6 @ Undo decrement 93 addeq r7, r7, r6 @ Undo decrement
99 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 94 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
100 mov pc, lr 95 b do_DataAbort
101 96
102.data_arm_lateldrpreconst: 97.data_arm_lateldrpreconst:
103 tst r8, #1 << 21 @ check writeback bit 98 tst r8, #1 << 21 @ check writeback bit
104 moveq pc, lr @ no writeback -> no fixup 99 beq do_DataAbort @ no writeback -> no fixup
105.data_arm_lateldrpostconst: 100.data_arm_lateldrpostconst:
106 movs r2, r8, lsl #20 @ Get offset 101 movs r6, r8, lsl #20 @ Get offset
107 moveq pc, lr @ zero -> no fixup 102 beq do_DataAbort @ zero -> no fixup
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction 103 and r9, r8, #15 << 16 @ Extract 'n' from instruction
109 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 104 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
110 tst r8, #1 << 23 @ Check U bit 105 tst r8, #1 << 23 @ Check U bit
111 subne r7, r7, r2, lsr #20 @ Undo increment 106 subne r7, r7, r6, lsr #20 @ Undo increment
112 addeq r7, r7, r2, lsr #20 @ Undo decrement 107 addeq r7, r7, r6, lsr #20 @ Undo decrement
113 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 108 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
114 mov pc, lr 109 b do_DataAbort
115 110
116.data_arm_lateldrprereg: 111.data_arm_lateldrprereg:
117 tst r8, #1 << 21 @ check writeback bit 112 tst r8, #1 << 21 @ check writeback bit
118 moveq pc, lr @ no writeback -> no fixup 113 beq do_DataAbort @ no writeback -> no fixup
119.data_arm_lateldrpostreg: 114.data_arm_lateldrpostreg:
120 and r7, r8, #15 @ Extract 'm' from instruction 115 and r7, r8, #15 @ Extract 'm' from instruction
121 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm' 116 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
122 mov r5, r8, lsr #7 @ get shift count 117 mov r9, r8, lsr #7 @ get shift count
123 ands r5, r5, #31 118 ands r9, r9, #31
124 and r7, r8, #0x70 @ get shift type 119 and r7, r8, #0x70 @ get shift type
125 orreq r7, r7, #8 @ shift count = 0 120 orreq r7, r7, #8 @ shift count = 0
126 add pc, pc, r7 121 add pc, pc, r7
127 nop 122 nop
128 123
129 mov r6, r6, lsl r5 @ 0: LSL #!0 124 mov r6, r6, lsl r9 @ 0: LSL #!0
130 b .data_arm_apply_r6_and_rn 125 b .data_arm_apply_r6_and_rn
131 b .data_arm_apply_r6_and_rn @ 1: LSL #0 126 b .data_arm_apply_r6_and_rn @ 1: LSL #0
132 nop 127 nop
@@ -134,7 +129,7 @@ ENTRY(v4t_late_abort)
134 nop 129 nop
135 b .data_unknown @ 3: MUL? 130 b .data_unknown @ 3: MUL?
136 nop 131 nop
137 mov r6, r6, lsr r5 @ 4: LSR #!0 132 mov r6, r6, lsr r9 @ 4: LSR #!0
138 b .data_arm_apply_r6_and_rn 133 b .data_arm_apply_r6_and_rn
139 mov r6, r6, lsr #32 @ 5: LSR #32 134 mov r6, r6, lsr #32 @ 5: LSR #32
140 b .data_arm_apply_r6_and_rn 135 b .data_arm_apply_r6_and_rn
@@ -142,7 +137,7 @@ ENTRY(v4t_late_abort)
142 nop 137 nop
143 b .data_unknown @ 7: MUL? 138 b .data_unknown @ 7: MUL?
144 nop 139 nop
145 mov r6, r6, asr r5 @ 8: ASR #!0 140 mov r6, r6, asr r9 @ 8: ASR #!0
146 b .data_arm_apply_r6_and_rn 141 b .data_arm_apply_r6_and_rn
147 mov r6, r6, asr #32 @ 9: ASR #32 142 mov r6, r6, asr #32 @ 9: ASR #32
148 b .data_arm_apply_r6_and_rn 143 b .data_arm_apply_r6_and_rn
@@ -150,7 +145,7 @@ ENTRY(v4t_late_abort)
150 nop 145 nop
151 b .data_unknown @ B: MUL? 146 b .data_unknown @ B: MUL?
152 nop 147 nop
153 mov r6, r6, ror r5 @ C: ROR #!0 148 mov r6, r6, ror r9 @ C: ROR #!0
154 b .data_arm_apply_r6_and_rn 149 b .data_arm_apply_r6_and_rn
155 mov r6, r6, rrx @ D: RRX 150 mov r6, r6, rrx @ D: RRX
156 b .data_arm_apply_r6_and_rn 151 b .data_arm_apply_r6_and_rn
@@ -159,7 +154,7 @@ ENTRY(v4t_late_abort)
159 b .data_unknown @ F: MUL? 154 b .data_unknown @ F: MUL?
160 155
161.data_thumb_abort: 156.data_thumb_abort:
162 ldrh r8, [r2] @ read instruction 157 ldrh r8, [r4] @ read instruction
163 tst r8, #1 << 11 @ L = 1 -> write? 158 tst r8, #1 << 11 @ L = 1 -> write?
164 orreq r1, r1, #1 << 8 @ yes 159 orreq r1, r1, #1 << 8 @ yes
165 and r7, r8, #15 << 12 160 and r7, r8, #15 << 12
@@ -172,10 +167,10 @@ ENTRY(v4t_late_abort)
172/* 3 */ b .data_unknown 167/* 3 */ b .data_unknown
173/* 4 */ b .data_unknown 168/* 4 */ b .data_unknown
174/* 5 */ b .data_thumb_reg 169/* 5 */ b .data_thumb_reg
175/* 6 */ mov pc, lr 170/* 6 */ b do_DataAbort
176/* 7 */ mov pc, lr 171/* 7 */ b do_DataAbort
177/* 8 */ mov pc, lr 172/* 8 */ b do_DataAbort
178/* 9 */ mov pc, lr 173/* 9 */ b do_DataAbort
179/* A */ b .data_unknown 174/* A */ b .data_unknown
180/* B */ b .data_thumb_pushpop 175/* B */ b .data_thumb_pushpop
181/* C */ b .data_thumb_ldmstm 176/* C */ b .data_thumb_ldmstm
@@ -185,41 +180,41 @@ ENTRY(v4t_late_abort)
185 180
186.data_thumb_reg: 181.data_thumb_reg:
187 tst r8, #1 << 9 182 tst r8, #1 << 9
188 moveq pc, lr 183 beq do_DataAbort
189 tst r8, #1 << 10 @ If 'S' (signed) bit is set 184 tst r8, #1 << 10 @ If 'S' (signed) bit is set
190 movne r1, #0 @ it must be a load instr 185 movne r1, #0 @ it must be a load instr
191 mov pc, lr 186 b do_DataAbort
192 187
193.data_thumb_pushpop: 188.data_thumb_pushpop:
194 tst r8, #1 << 10 189 tst r8, #1 << 10
195 beq .data_unknown 190 beq .data_unknown
196 and r6, r8, #0x55 @ hweight8(r8) + R bit 191 and r6, r8, #0x55 @ hweight8(r8) + R bit
197 and r2, r8, #0xaa 192 and r9, r8, #0xaa
198 add r6, r6, r2, lsr #1 193 add r6, r6, r9, lsr #1
199 and r2, r6, #0xcc 194 and r9, r6, #0xcc
200 and r6, r6, #0x33 195 and r6, r6, #0x33
201 add r6, r6, r2, lsr #2 196 add r6, r6, r9, lsr #2
202 movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit) 197 movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)
203 adc r6, r6, r6, lsr #4 @ high + low nibble + R bit 198 adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
204 and r6, r6, #15 @ number of regs to transfer 199 and r6, r6, #15 @ number of regs to transfer
205 ldr r7, [sp, #13 << 2] 200 ldr r7, [r2, #13 << 2]
206 tst r8, #1 << 11 201 tst r8, #1 << 11
207 addeq r7, r7, r6, lsl #2 @ increment SP if PUSH 202 addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
208 subne r7, r7, r6, lsl #2 @ decrement SP if POP 203 subne r7, r7, r6, lsl #2 @ decrement SP if POP
209 str r7, [sp, #13 << 2] 204 str r7, [r2, #13 << 2]
210 mov pc, lr 205 b do_DataAbort
211 206
212.data_thumb_ldmstm: 207.data_thumb_ldmstm:
213 and r6, r8, #0x55 @ hweight8(r8) 208 and r6, r8, #0x55 @ hweight8(r8)
214 and r2, r8, #0xaa 209 and r9, r8, #0xaa
215 add r6, r6, r2, lsr #1 210 add r6, r6, r9, lsr #1
216 and r2, r6, #0xcc 211 and r9, r6, #0xcc
217 and r6, r6, #0x33 212 and r6, r6, #0x33
218 add r6, r6, r2, lsr #2 213 add r6, r6, r9, lsr #2
219 add r6, r6, r6, lsr #4 214 add r6, r6, r6, lsr #4
220 and r5, r8, #7 << 8 215 and r9, r8, #7 << 8
221 ldr r7, [sp, r5, lsr #6] 216 ldr r7, [r2, r9, lsr #6]
222 and r6, r6, #15 @ number of regs to transfer 217 and r6, r6, #15 @ number of regs to transfer
223 sub r7, r7, r6, lsl #2 @ always decrement 218 sub r7, r7, r6, lsl #2 @ always decrement
224 str r7, [sp, r5, lsr #6] 219 str r7, [r2, r9, lsr #6]
225 mov pc, lr 220 b do_DataAbort
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index d7cb1bfa51a..52162d59407 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -9,34 +9,32 @@
9 * 9 *
10 */ 10 */
11 11
12 .macro do_thumb_abort 12 .macro do_thumb_abort, fsr, pc, psr, tmp
13 tst r3, #PSR_T_BIT 13 tst \psr, #PSR_T_BIT
14 beq not_thumb 14 beq not_thumb
15 ldrh r3, [r2] @ Read aborted Thumb instruction 15 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
16 and r3, r3, # 0xfe00 @ Mask opcode field 16 and \tmp, \tmp, # 0xfe00 @ Mask opcode field
17 cmp r3, # 0x5600 @ Is it ldrsb? 17 cmp \tmp, # 0x5600 @ Is it ldrsb?
18 orreq r3, r3, #1 << 11 @ Set L-bit if yes 18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
19 tst r3, #1 << 11 @ L = 0 -> write 19 tst \tmp, #1 << 11 @ L = 0 -> write
20 orreq r1, r1, #1 << 11 @ yes. 20 orreq \psr, \psr, #1 << 11 @ yes.
21 mov pc, lr 21 b do_DataAbort
22not_thumb: 22not_thumb:
23 .endm 23 .endm
24 24
25/* 25/*
26 * We check for the following insturction encoding for LDRD. 26 * We check for the following instruction encoding for LDRD.
27 * 27 *
28 * [27:25] == 0 28 * [27:25] == 000
29 * [7:4] == 1101 29 * [7:4] == 1101
30 * [20] == 0 30 * [20] == 0
31 */ 31 */
32 .macro do_ldrd_abort 32 .macro do_ldrd_abort, tmp, insn
33 tst r3, #0x0e000000 @ [27:25] == 0 33 tst \insn, #0x0e100000 @ [27:25,20] == 0
34 bne not_ldrd 34 bne not_ldrd
35 and r2, r3, #0x000000f0 @ [7:4] == 1101 35 and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
36 cmp r2, #0x000000d0 36 cmp \tmp, #0x000000d0
37 bne not_ldrd 37 beq do_DataAbort
38 tst r3, #1 << 20 @ [20] == 0
39 moveq pc, lr
40not_ldrd: 38not_ldrd:
41 .endm 39 .endm
42 40
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
index 625e580945b..119cb479c2a 100644
--- a/arch/arm/mm/abort-nommu.S
+++ b/arch/arm/mm/abort-nommu.S
@@ -3,11 +3,11 @@
3/* 3/*
4 * Function: nommu_early_abort 4 * Function: nommu_early_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r2 = pt_regs
7 * : r3 = saved SPSR 7 * : r4 = aborted context pc
8 * : r5 = aborted context psr
8 * 9 *
9 * Returns : r0 = 0 (abort address) 10 * Returns : r4 - r11, r13 preserved
10 * : r1 = 0 (FSR)
11 * 11 *
12 * Note: There is no FSR/FAR on !CPU_CP15_MMU cores. 12 * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
13 * Just fill zero into the registers. 13 * Just fill zero into the registers.
@@ -16,5 +16,5 @@
16ENTRY(nommu_early_abort) 16ENTRY(nommu_early_abort)
17 mov r0, #0 @ clear r0, r1 (no FSR/FAR) 17 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
18 mov r1, #0 18 mov r1, #0
19 mov pc, lr 19 b do_DataAbort
20ENDPROC(nommu_early_abort) 20ENDPROC(nommu_early_abort)
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 724ba3bce72..be7c638b648 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -727,6 +727,9 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
727 int isize = 4; 727 int isize = 4;
728 int thumb2_32b = 0; 728 int thumb2_32b = 0;
729 729
730 if (interrupts_enabled(regs))
731 local_irq_enable();
732
730 instrptr = instruction_pointer(regs); 733 instrptr = instruction_pointer(regs);
731 734
732 fs = get_fs(); 735 fs = get_fs();
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index ef59099a546..44c086710d2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -120,17 +120,22 @@ static void l2x0_cache_sync(void)
120 spin_unlock_irqrestore(&l2x0_lock, flags); 120 spin_unlock_irqrestore(&l2x0_lock, flags);
121} 121}
122 122
123static void l2x0_flush_all(void) 123static void __l2x0_flush_all(void)
124{ 124{
125 unsigned long flags;
126
127 /* clean all ways */
128 spin_lock_irqsave(&l2x0_lock, flags);
129 debug_writel(0x03); 125 debug_writel(0x03);
130 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); 126 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
131 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); 127 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
132 cache_sync(); 128 cache_sync();
133 debug_writel(0x00); 129 debug_writel(0x00);
130}
131
132static void l2x0_flush_all(void)
133{
134 unsigned long flags;
135
136 /* clean all ways */
137 spin_lock_irqsave(&l2x0_lock, flags);
138 __l2x0_flush_all();
134 spin_unlock_irqrestore(&l2x0_lock, flags); 139 spin_unlock_irqrestore(&l2x0_lock, flags);
135} 140}
136 141
@@ -266,7 +271,9 @@ static void l2x0_disable(void)
266 unsigned long flags; 271 unsigned long flags;
267 272
268 spin_lock_irqsave(&l2x0_lock, flags); 273 spin_lock_irqsave(&l2x0_lock, flags);
269 writel(0, l2x0_base + L2X0_CTRL); 274 __l2x0_flush_all();
275 writel_relaxed(0, l2x0_base + L2X0_CTRL);
276 dsb();
270 spin_unlock_irqrestore(&l2x0_lock, flags); 277 spin_unlock_irqrestore(&l2x0_lock, flags);
271} 278}
272 279
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 8bfae964b13..b0ee9ba3cfa 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -24,7 +24,9 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
24 24
25/* 25/*
26 * We fork()ed a process, and we need a new context for the child 26 * We fork()ed a process, and we need a new context for the child
27 * to run in. 27 * to run in. We reserve version 0 for initial tasks so we will
28 * always allocate an ASID. The ASID 0 is reserved for the TTBR
29 * register changing sequence.
28 */ 30 */
29void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) 31void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
30{ 32{
@@ -34,11 +36,8 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
34 36
35static void flush_context(void) 37static void flush_context(void)
36{ 38{
37 u32 ttb; 39 /* set the reserved ASID before flushing the TLB */
38 /* Copy TTBR1 into TTBR0 */ 40 asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0));
39 asm volatile("mrc p15, 0, %0, c2, c0, 1\n"
40 "mcr p15, 0, %0, c2, c0, 0"
41 : "=r" (ttb));
42 isb(); 41 isb();
43 local_flush_tlb_all(); 42 local_flush_tlb_all();
44 if (icache_is_vivt_asid_tagged()) { 43 if (icache_is_vivt_asid_tagged()) {
@@ -94,7 +93,7 @@ static void reset_context(void *info)
94 return; 93 return;
95 94
96 smp_rmb(); 95 smp_rmb();
97 asid = cpu_last_asid + cpu; 96 asid = cpu_last_asid + cpu + 1;
98 97
99 flush_context(); 98 flush_context();
100 set_mm_context(mm, asid); 99 set_mm_context(mm, asid);
@@ -144,13 +143,13 @@ void __new_context(struct mm_struct *mm)
144 * to start a new version and flush the TLB. 143 * to start a new version and flush the TLB.
145 */ 144 */
146 if (unlikely((asid & ~ASID_MASK) == 0)) { 145 if (unlikely((asid & ~ASID_MASK) == 0)) {
147 asid = cpu_last_asid + smp_processor_id(); 146 asid = cpu_last_asid + smp_processor_id() + 1;
148 flush_context(); 147 flush_context();
149#ifdef CONFIG_SMP 148#ifdef CONFIG_SMP
150 smp_wmb(); 149 smp_wmb();
151 smp_call_function(reset_context, NULL, 1); 150 smp_call_function(reset_context, NULL, 1);
152#endif 151#endif
153 cpu_last_asid += NR_CPUS - 1; 152 cpu_last_asid += NR_CPUS;
154 } 153 }
155 154
156 set_mm_context(mm, asid); 155 set_mm_context(mm, asid);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 82a093cee09..0a0a1e7c20d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -25,9 +25,11 @@
25#include <asm/tlbflush.h> 25#include <asm/tlbflush.h>
26#include <asm/sizes.h> 26#include <asm/sizes.h>
27 27
28#include "mm.h"
29
28static u64 get_coherent_dma_mask(struct device *dev) 30static u64 get_coherent_dma_mask(struct device *dev)
29{ 31{
30 u64 mask = ISA_DMA_THRESHOLD; 32 u64 mask = (u64)arm_dma_limit;
31 33
32 if (dev) { 34 if (dev) {
33 mask = dev->coherent_dma_mask; 35 mask = dev->coherent_dma_mask;
@@ -41,10 +43,10 @@ static u64 get_coherent_dma_mask(struct device *dev)
41 return 0; 43 return 0;
42 } 44 }
43 45
44 if ((~mask) & ISA_DMA_THRESHOLD) { 46 if ((~mask) & (u64)arm_dma_limit) {
45 dev_warn(dev, "coherent DMA mask %#llx is smaller " 47 dev_warn(dev, "coherent DMA mask %#llx is smaller "
46 "than system GFP_DMA mask %#llx\n", 48 "than system GFP_DMA mask %#llx\n",
47 mask, (unsigned long long)ISA_DMA_THRESHOLD); 49 mask, (u64)arm_dma_limit);
48 return 0; 50 return 0;
49 } 51 }
50 } 52 }
@@ -657,6 +659,33 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
657} 659}
658EXPORT_SYMBOL(dma_sync_sg_for_device); 660EXPORT_SYMBOL(dma_sync_sg_for_device);
659 661
662/*
663 * Return whether the given device DMA address mask can be supported
664 * properly. For example, if your device can only drive the low 24-bits
665 * during bus mastering, then you would pass 0x00ffffff as the mask
666 * to this function.
667 */
668int dma_supported(struct device *dev, u64 mask)
669{
670 if (mask < (u64)arm_dma_limit)
671 return 0;
672 return 1;
673}
674EXPORT_SYMBOL(dma_supported);
675
676int dma_set_mask(struct device *dev, u64 dma_mask)
677{
678 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
679 return -EIO;
680
681#ifndef CONFIG_DMABOUNCE
682 *dev->dma_mask = dma_mask;
683#endif
684
685 return 0;
686}
687EXPORT_SYMBOL(dma_set_mask);
688
660#define PREALLOC_DMA_DEBUG_ENTRIES 4096 689#define PREALLOC_DMA_DEBUG_ENTRIES 4096
661 690
662static int __init dma_debug_do_init(void) 691static int __init dma_debug_do_init(void)
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index ee769234157..55657c222d7 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -285,6 +285,10 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
285 tsk = current; 285 tsk = current;
286 mm = tsk->mm; 286 mm = tsk->mm;
287 287
288 /* Enable interrupts if they were enabled in the parent context. */
289 if (interrupts_enabled(regs))
290 local_irq_enable();
291
288 /* 292 /*
289 * If we're in an interrupt or have no user 293 * If we're in an interrupt or have no user
290 * context, we must not take the fault.. 294 * context, we must not take the fault..
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index fdc87f9bda5..e5ab4362322 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -212,6 +212,14 @@ static void __init arm_bootmem_init(unsigned long start_pfn,
212} 212}
213 213
214#ifdef CONFIG_ZONE_DMA 214#ifdef CONFIG_ZONE_DMA
215/*
216 * The DMA mask corresponding to the maximum bus address allocatable
217 * using GFP_DMA. The default here places no restriction on DMA
218 * allocations. This must be the smallest DMA mask in the system,
219 * so a successful GFP_DMA allocation will always satisfy this.
220 */
221u32 arm_dma_limit;
222
215static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole, 223static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole,
216 unsigned long dma_size) 224 unsigned long dma_size)
217{ 225{
@@ -278,6 +286,8 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
278 */ 286 */
279 arm_adjust_dma_zone(zone_size, zhole_size, 287 arm_adjust_dma_zone(zone_size, zhole_size,
280 ARM_DMA_ZONE_SIZE >> PAGE_SHIFT); 288 ARM_DMA_ZONE_SIZE >> PAGE_SHIFT);
289
290 arm_dma_limit = PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1;
281#endif 291#endif
282 292
283 free_area_init_node(0, zone_size, min, zhole_size); 293 free_area_init_node(0, zone_size, min, zhole_size);
@@ -331,6 +341,12 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
331#endif 341#endif
332#ifdef CONFIG_BLK_DEV_INITRD 342#ifdef CONFIG_BLK_DEV_INITRD
333 if (phys_initrd_size && 343 if (phys_initrd_size &&
344 !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
345 pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
346 phys_initrd_start, phys_initrd_size);
347 phys_initrd_start = phys_initrd_size = 0;
348 }
349 if (phys_initrd_size &&
334 memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) { 350 memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
335 pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n", 351 pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
336 phys_initrd_start, phys_initrd_size); 352 phys_initrd_start, phys_initrd_size);
@@ -644,9 +660,10 @@ void __init mem_init(void)
644 " pkmap : 0x%08lx - 0x%08lx (%4ld MB)\n" 660 " pkmap : 0x%08lx - 0x%08lx (%4ld MB)\n"
645#endif 661#endif
646 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" 662 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n"
647 " .init : 0x%p" " - 0x%p" " (%4d kB)\n"
648 " .text : 0x%p" " - 0x%p" " (%4d kB)\n" 663 " .text : 0x%p" " - 0x%p" " (%4d kB)\n"
649 " .data : 0x%p" " - 0x%p" " (%4d kB)\n", 664 " .init : 0x%p" " - 0x%p" " (%4d kB)\n"
665 " .data : 0x%p" " - 0x%p" " (%4d kB)\n"
666 " .bss : 0x%p" " - 0x%p" " (%4d kB)\n",
650 667
651 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + 668 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
652 (PAGE_SIZE)), 669 (PAGE_SIZE)),
@@ -666,9 +683,10 @@ void __init mem_init(void)
666#endif 683#endif
667 MLM(MODULES_VADDR, MODULES_END), 684 MLM(MODULES_VADDR, MODULES_END),
668 685
669 MLK_ROUNDUP(__init_begin, __init_end),
670 MLK_ROUNDUP(_text, _etext), 686 MLK_ROUNDUP(_text, _etext),
671 MLK_ROUNDUP(_sdata, _edata)); 687 MLK_ROUNDUP(__init_begin, __init_end),
688 MLK_ROUNDUP(_sdata, _edata),
689 MLK_ROUNDUP(__bss_start, __bss_stop));
672 690
673#undef MLK 691#undef MLK
674#undef MLM 692#undef MLM
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 5b3d7d54365..010566799c8 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -23,5 +23,11 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
23 23
24#endif 24#endif
25 25
26#ifdef CONFIG_ZONE_DMA
27extern u32 arm_dma_limit;
28#else
29#define arm_dma_limit ((u32)~0)
30#endif
31
26void __init bootmem_init(void); 32void __init bootmem_init(void);
27void arm_mm_memblock_reserve(void); 33void arm_mm_memblock_reserve(void);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 9d9e736c2b4..594d677b92c 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -759,7 +759,7 @@ early_param("vmalloc", early_vmalloc);
759 759
760static phys_addr_t lowmem_limit __initdata = 0; 760static phys_addr_t lowmem_limit __initdata = 0;
761 761
762static void __init sanity_check_meminfo(void) 762void __init sanity_check_meminfo(void)
763{ 763{
764 int i, j, highmem = 0; 764 int i, j, highmem = 0;
765 765
@@ -1032,8 +1032,9 @@ void __init paging_init(struct machine_desc *mdesc)
1032{ 1032{
1033 void *zero_page; 1033 void *zero_page;
1034 1034
1035 memblock_set_current_limit(lowmem_limit);
1036
1035 build_mem_type_table(); 1037 build_mem_type_table();
1036 sanity_check_meminfo();
1037 prepare_page_table(); 1038 prepare_page_table();
1038 map_lowmem(); 1039 map_lowmem();
1039 devicemaps_init(mdesc); 1040 devicemaps_init(mdesc);
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 687d02319a4..941a98c9e8a 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -27,6 +27,10 @@ void __init arm_mm_memblock_reserve(void)
27 memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE); 27 memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
28} 28}
29 29
30void __init sanity_check_meminfo(void)
31{
32}
33
30/* 34/*
31 * paging_init() sets up the page tables, initialises the zone memory 35 * paging_init() sets up the page tables, initialises the zone memory
32 * maps, and sets up the zero page, bad page and bad page tables. 36 * maps, and sets up the zero page, bad page and bad page tables.
diff --git a/arch/arm/mm/pabort-legacy.S b/arch/arm/mm/pabort-legacy.S
index 87970eba88e..8bbff025269 100644
--- a/arch/arm/mm/pabort-legacy.S
+++ b/arch/arm/mm/pabort-legacy.S
@@ -4,16 +4,18 @@
4/* 4/*
5 * Function: legacy_pabort 5 * Function: legacy_pabort
6 * 6 *
7 * Params : r0 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r4 = address of aborted instruction
9 * : r5 = psr for parent context
8 * 10 *
9 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
10 * : r1 = Simulated IFSR with section translation fault status
11 * 12 *
12 * Purpose : obtain information about current prefetch abort. 13 * Purpose : obtain information about current prefetch abort.
13 */ 14 */
14 15
15 .align 5 16 .align 5
16ENTRY(legacy_pabort) 17ENTRY(legacy_pabort)
18 mov r0, r4
17 mov r1, #5 19 mov r1, #5
18 mov pc, lr 20 b do_PrefetchAbort
19ENDPROC(legacy_pabort) 21ENDPROC(legacy_pabort)
diff --git a/arch/arm/mm/pabort-v6.S b/arch/arm/mm/pabort-v6.S
index 06e3d1ef211..9627646ce78 100644
--- a/arch/arm/mm/pabort-v6.S
+++ b/arch/arm/mm/pabort-v6.S
@@ -4,16 +4,18 @@
4/* 4/*
5 * Function: v6_pabort 5 * Function: v6_pabort
6 * 6 *
7 * Params : r0 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r4 = address of aborted instruction
9 * : r5 = psr for parent context
8 * 10 *
9 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
10 * : r1 = IFSR
11 * 12 *
12 * Purpose : obtain information about current prefetch abort. 13 * Purpose : obtain information about current prefetch abort.
13 */ 14 */
14 15
15 .align 5 16 .align 5
16ENTRY(v6_pabort) 17ENTRY(v6_pabort)
18 mov r0, r4
17 mrc p15, 0, r1, c5, c0, 1 @ get IFSR 19 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
18 mov pc, lr 20 b do_PrefetchAbort
19ENDPROC(v6_pabort) 21ENDPROC(v6_pabort)
diff --git a/arch/arm/mm/pabort-v7.S b/arch/arm/mm/pabort-v7.S
index a8b3b300a18..875761f44f3 100644
--- a/arch/arm/mm/pabort-v7.S
+++ b/arch/arm/mm/pabort-v7.S
@@ -2,12 +2,13 @@
2#include <asm/assembler.h> 2#include <asm/assembler.h>
3 3
4/* 4/*
5 * Function: v6_pabort 5 * Function: v7_pabort
6 * 6 *
7 * Params : r0 = address of aborted instruction 7 * Params : r2 = pt_regs
8 * : r4 = address of aborted instruction
9 * : r5 = psr for parent context
8 * 10 *
9 * Returns : r0 = address of abort 11 * Returns : r4 - r11, r13 preserved
10 * : r1 = IFSR
11 * 12 *
12 * Purpose : obtain information about current prefetch abort. 13 * Purpose : obtain information about current prefetch abort.
13 */ 14 */
@@ -16,5 +17,5 @@
16ENTRY(v7_pabort) 17ENTRY(v7_pabort)
17 mrc p15, 0, r0, c6, c0, 2 @ get IFAR 18 mrc p15, 0, r0, c6, c0, 2 @ get IFAR
18 mrc p15, 0, r1, c5, c0, 1 @ get IFSR 19 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
19 mov pc, lr 20 b do_PrefetchAbort
20ENDPROC(v7_pabort) 21ENDPROC(v7_pabort)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 5f79dc4ce3f..50e3543d03b 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -29,19 +29,19 @@ ENTRY(cpu_arm7_dcache_clean_area)
29/* 29/*
30 * Function: arm6_7_data_abort () 30 * Function: arm6_7_data_abort ()
31 * 31 *
32 * Params : r2 = address of aborted instruction 32 * Params : r2 = pt_regs
33 * : sp = pointer to registers 33 * : r4 = aborted context pc
34 * : r5 = aborted context psr
34 * 35 *
35 * Purpose : obtain information about current aborted instruction 36 * Purpose : obtain information about current aborted instruction
36 * 37 *
37 * Returns : r0 = address of abort 38 * Returns : r4-r5, r10-r11, r13 preserved
38 * : r1 = FSR
39 */ 39 */
40 40
41ENTRY(cpu_arm7_data_abort) 41ENTRY(cpu_arm7_data_abort)
42 mrc p15, 0, r1, c5, c0, 0 @ get FSR 42 mrc p15, 0, r1, c5, c0, 0 @ get FSR
43 mrc p15, 0, r0, c6, c0, 0 @ get FAR 43 mrc p15, 0, r0, c6, c0, 0 @ get FAR
44 ldr r8, [r2] @ read arm instruction 44 ldr r8, [r4] @ read arm instruction
45 tst r8, #1 << 20 @ L = 0 -> write? 45 tst r8, #1 << 20 @ L = 0 -> write?
46 orreq r1, r1, #1 << 11 @ yes. 46 orreq r1, r1, #1 << 11 @ yes.
47 and r7, r8, #15 << 24 47 and r7, r8, #15 << 24
@@ -49,7 +49,7 @@ ENTRY(cpu_arm7_data_abort)
49 nop 49 nop
50 50
51/* 0 */ b .data_unknown 51/* 0 */ b .data_unknown
52/* 1 */ mov pc, lr @ swp 52/* 1 */ b do_DataAbort @ swp
53/* 2 */ b .data_unknown 53/* 2 */ b .data_unknown
54/* 3 */ b .data_unknown 54/* 3 */ b .data_unknown
55/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m 55/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
@@ -60,87 +60,85 @@ ENTRY(cpu_arm7_data_abort)
60/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist> 60/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
61/* a */ b .data_unknown 61/* a */ b .data_unknown
62/* b */ b .data_unknown 62/* b */ b .data_unknown
63/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m 63/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
64/* d */ mov pc, lr @ ldc rd, [rn, #m] 64/* d */ b do_DataAbort @ ldc rd, [rn, #m]
65/* e */ b .data_unknown 65/* e */ b .data_unknown
66/* f */ 66/* f */
67.data_unknown: @ Part of jumptable 67.data_unknown: @ Part of jumptable
68 mov r0, r2 68 mov r0, r4
69 mov r1, r8 69 mov r1, r8
70 mov r2, sp 70 b baddataabort
71 bl baddataabort
72 b ret_from_exception
73 71
74ENTRY(cpu_arm6_data_abort) 72ENTRY(cpu_arm6_data_abort)
75 mrc p15, 0, r1, c5, c0, 0 @ get FSR 73 mrc p15, 0, r1, c5, c0, 0 @ get FSR
76 mrc p15, 0, r0, c6, c0, 0 @ get FAR 74 mrc p15, 0, r0, c6, c0, 0 @ get FAR
77 ldr r8, [r2] @ read arm instruction 75 ldr r8, [r4] @ read arm instruction
78 tst r8, #1 << 20 @ L = 0 -> write? 76 tst r8, #1 << 20 @ L = 0 -> write?
79 orreq r1, r1, #1 << 11 @ yes. 77 orreq r1, r1, #1 << 11 @ yes.
80 and r7, r8, #14 << 24 78 and r7, r8, #14 << 24
81 teq r7, #8 << 24 @ was it ldm/stm 79 teq r7, #8 << 24 @ was it ldm/stm
82 movne pc, lr 80 bne do_DataAbort
83 81
84.data_arm_ldmstm: 82.data_arm_ldmstm:
85 tst r8, #1 << 21 @ check writeback bit 83 tst r8, #1 << 21 @ check writeback bit
86 moveq pc, lr @ no writeback -> no fixup 84 beq do_DataAbort @ no writeback -> no fixup
87 mov r7, #0x11 85 mov r7, #0x11
88 orr r7, r7, #0x1100 86 orr r7, r7, #0x1100
89 and r6, r8, r7 87 and r6, r8, r7
90 and r2, r8, r7, lsl #1 88 and r9, r8, r7, lsl #1
91 add r6, r6, r2, lsr #1 89 add r6, r6, r9, lsr #1
92 and r2, r8, r7, lsl #2 90 and r9, r8, r7, lsl #2
93 add r6, r6, r2, lsr #2 91 add r6, r6, r9, lsr #2
94 and r2, r8, r7, lsl #3 92 and r9, r8, r7, lsl #3
95 add r6, r6, r2, lsr #3 93 add r6, r6, r9, lsr #3
96 add r6, r6, r6, lsr #8 94 add r6, r6, r6, lsr #8
97 add r6, r6, r6, lsr #4 95 add r6, r6, r6, lsr #4
98 and r6, r6, #15 @ r6 = no. of registers to transfer. 96 and r6, r6, #15 @ r6 = no. of registers to transfer.
99 and r5, r8, #15 << 16 @ Extract 'n' from instruction 97 and r9, r8, #15 << 16 @ Extract 'n' from instruction
100 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 98 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
101 tst r8, #1 << 23 @ Check U bit 99 tst r8, #1 << 23 @ Check U bit
102 subne r7, r7, r6, lsl #2 @ Undo increment 100 subne r7, r7, r6, lsl #2 @ Undo increment
103 addeq r7, r7, r6, lsl #2 @ Undo decrement 101 addeq r7, r7, r6, lsl #2 @ Undo decrement
104 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 102 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
105 mov pc, lr 103 b do_DataAbort
106 104
107.data_arm_apply_r6_and_rn: 105.data_arm_apply_r6_and_rn:
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction 106 and r9, r8, #15 << 16 @ Extract 'n' from instruction
109 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 107 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
110 tst r8, #1 << 23 @ Check U bit 108 tst r8, #1 << 23 @ Check U bit
111 subne r7, r7, r6 @ Undo incrmenet 109 subne r7, r7, r6 @ Undo incrmenet
112 addeq r7, r7, r6 @ Undo decrement 110 addeq r7, r7, r6 @ Undo decrement
113 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 111 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
114 mov pc, lr 112 b do_DataAbort
115 113
116.data_arm_lateldrpreconst: 114.data_arm_lateldrpreconst:
117 tst r8, #1 << 21 @ check writeback bit 115 tst r8, #1 << 21 @ check writeback bit
118 moveq pc, lr @ no writeback -> no fixup 116 beq do_DataAbort @ no writeback -> no fixup
119.data_arm_lateldrpostconst: 117.data_arm_lateldrpostconst:
120 movs r2, r8, lsl #20 @ Get offset 118 movs r6, r8, lsl #20 @ Get offset
121 moveq pc, lr @ zero -> no fixup 119 beq do_DataAbort @ zero -> no fixup
122 and r5, r8, #15 << 16 @ Extract 'n' from instruction 120 and r9, r8, #15 << 16 @ Extract 'n' from instruction
123 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' 121 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
124 tst r8, #1 << 23 @ Check U bit 122 tst r8, #1 << 23 @ Check U bit
125 subne r7, r7, r2, lsr #20 @ Undo increment 123 subne r7, r7, r6, lsr #20 @ Undo increment
126 addeq r7, r7, r2, lsr #20 @ Undo decrement 124 addeq r7, r7, r6, lsr #20 @ Undo decrement
127 str r7, [sp, r5, lsr #14] @ Put register 'Rn' 125 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
128 mov pc, lr 126 b do_DataAbort
129 127
130.data_arm_lateldrprereg: 128.data_arm_lateldrprereg:
131 tst r8, #1 << 21 @ check writeback bit 129 tst r8, #1 << 21 @ check writeback bit
132 moveq pc, lr @ no writeback -> no fixup 130 beq do_DataAbort @ no writeback -> no fixup
133.data_arm_lateldrpostreg: 131.data_arm_lateldrpostreg:
134 and r7, r8, #15 @ Extract 'm' from instruction 132 and r7, r8, #15 @ Extract 'm' from instruction
135 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm' 133 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
136 mov r5, r8, lsr #7 @ get shift count 134 mov r9, r8, lsr #7 @ get shift count
137 ands r5, r5, #31 135 ands r9, r9, #31
138 and r7, r8, #0x70 @ get shift type 136 and r7, r8, #0x70 @ get shift type
139 orreq r7, r7, #8 @ shift count = 0 137 orreq r7, r7, #8 @ shift count = 0
140 add pc, pc, r7 138 add pc, pc, r7
141 nop 139 nop
142 140
143 mov r6, r6, lsl r5 @ 0: LSL #!0 141 mov r6, r6, lsl r9 @ 0: LSL #!0
144 b .data_arm_apply_r6_and_rn 142 b .data_arm_apply_r6_and_rn
145 b .data_arm_apply_r6_and_rn @ 1: LSL #0 143 b .data_arm_apply_r6_and_rn @ 1: LSL #0
146 nop 144 nop
@@ -148,7 +146,7 @@ ENTRY(cpu_arm6_data_abort)
148 nop 146 nop
149 b .data_unknown @ 3: MUL? 147 b .data_unknown @ 3: MUL?
150 nop 148 nop
151 mov r6, r6, lsr r5 @ 4: LSR #!0 149 mov r6, r6, lsr r9 @ 4: LSR #!0
152 b .data_arm_apply_r6_and_rn 150 b .data_arm_apply_r6_and_rn
153 mov r6, r6, lsr #32 @ 5: LSR #32 151 mov r6, r6, lsr #32 @ 5: LSR #32
154 b .data_arm_apply_r6_and_rn 152 b .data_arm_apply_r6_and_rn
@@ -156,7 +154,7 @@ ENTRY(cpu_arm6_data_abort)
156 nop 154 nop
157 b .data_unknown @ 7: MUL? 155 b .data_unknown @ 7: MUL?
158 nop 156 nop
159 mov r6, r6, asr r5 @ 8: ASR #!0 157 mov r6, r6, asr r9 @ 8: ASR #!0
160 b .data_arm_apply_r6_and_rn 158 b .data_arm_apply_r6_and_rn
161 mov r6, r6, asr #32 @ 9: ASR #32 159 mov r6, r6, asr #32 @ 9: ASR #32
162 b .data_arm_apply_r6_and_rn 160 b .data_arm_apply_r6_and_rn
@@ -164,7 +162,7 @@ ENTRY(cpu_arm6_data_abort)
164 nop 162 nop
165 b .data_unknown @ B: MUL? 163 b .data_unknown @ B: MUL?
166 nop 164 nop
167 mov r6, r6, ror r5 @ C: ROR #!0 165 mov r6, r6, ror r9 @ C: ROR #!0
168 b .data_arm_apply_r6_and_rn 166 b .data_arm_apply_r6_and_rn
169 mov r6, r6, rrx @ D: RRX 167 mov r6, r6, rrx @ D: RRX
170 b .data_arm_apply_r6_and_rn 168 b .data_arm_apply_r6_and_rn
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index e4c165ca669..537ffcb0646 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -146,7 +146,7 @@ __arm7tdmi_proc_info:
146 .long 0 146 .long 0
147 .long 0 147 .long 0
148 .long v4_cache_fns 148 .long v4_cache_fns
149 .size __arm7tdmi_proc_info, . - __arm7dmi_proc_info 149 .size __arm7tdmi_proc_info, . - __arm7tdmi_proc_info
150 150
151 .type __triscenda7_proc_info, #object 151 .type __triscenda7_proc_info, #object
152__triscenda7_proc_info: 152__triscenda7_proc_info:
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 7b7ebd4d096..546b54da100 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -116,7 +116,7 @@ __arm9tdmi_proc_info:
116 .long 0 116 .long 0
117 .long 0 117 .long 0
118 .long v4_cache_fns 118 .long v4_cache_fns
119 .size __arm9tdmi_proc_info, . - __arm9dmi_proc_info 119 .size __arm9tdmi_proc_info, . - __arm9tdmi_proc_info
120 120
121 .type __p2001_proc_info, #object 121 .type __p2001_proc_info, #object
122__p2001_proc_info: 122__p2001_proc_info:
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 184a9c997e3..e9c47271732 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -34,7 +34,7 @@
34 */ 34 */
35#define DCACHELINESIZE 32 35#define DCACHELINESIZE 32
36 36
37 __INIT 37 .section .text
38 38
39/* 39/*
40 * cpu_sa1100_proc_init() 40 * cpu_sa1100_proc_init()
@@ -45,8 +45,6 @@ ENTRY(cpu_sa1100_proc_init)
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
46 mov pc, lr 46 mov pc, lr
47 47
48 .section .text
49
50/* 48/*
51 * cpu_sa1100_proc_fin() 49 * cpu_sa1100_proc_fin()
52 * 50 *
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3b566ec83d..089c0b5e454 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -108,16 +108,18 @@ ENTRY(cpu_v7_switch_mm)
108#ifdef CONFIG_ARM_ERRATA_430973 108#ifdef CONFIG_ARM_ERRATA_430973
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110#endif 110#endif
111 mrc p15, 0, r2, c2, c0, 1 @ load TTB 1 111#ifdef CONFIG_ARM_ERRATA_754322
112 mcr p15, 0, r2, c2, c0, 0 @ into TTB 0 112 dsb
113#endif
114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
115 isb
1161: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 isb 117 isb
114#ifdef CONFIG_ARM_ERRATA_754322 118#ifdef CONFIG_ARM_ERRATA_754322
115 dsb 119 dsb
116#endif 120#endif
117 mcr p15, 0, r1, c13, c0, 1 @ set context ID 121 mcr p15, 0, r1, c13, c0, 1 @ set context ID
118 isb 122 isb
119 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
120 isb
121#endif 123#endif
122 mov pc, lr 124 mov pc, lr
123ENDPROC(cpu_v7_switch_mm) 125ENDPROC(cpu_v7_switch_mm)
@@ -208,19 +210,21 @@ cpu_v7_name:
208 210
209/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 211/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
210.globl cpu_v7_suspend_size 212.globl cpu_v7_suspend_size
211.equ cpu_v7_suspend_size, 4 * 8 213.equ cpu_v7_suspend_size, 4 * 9
212#ifdef CONFIG_PM_SLEEP 214#ifdef CONFIG_PM_SLEEP
213ENTRY(cpu_v7_do_suspend) 215ENTRY(cpu_v7_do_suspend)
214 stmfd sp!, {r4 - r11, lr} 216 stmfd sp!, {r4 - r11, lr}
215 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 217 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
216 mrc p15, 0, r5, c13, c0, 1 @ Context ID 218 mrc p15, 0, r5, c13, c0, 1 @ Context ID
219 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID
220 stmia r0!, {r4 - r6}
217 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 221 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
218 mrc p15, 0, r7, c2, c0, 0 @ TTB 0 222 mrc p15, 0, r7, c2, c0, 0 @ TTB 0
219 mrc p15, 0, r8, c2, c0, 1 @ TTB 1 223 mrc p15, 0, r8, c2, c0, 1 @ TTB 1
220 mrc p15, 0, r9, c1, c0, 0 @ Control register 224 mrc p15, 0, r9, c1, c0, 0 @ Control register
221 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register 225 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
222 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control 226 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
223 stmia r0, {r4 - r11} 227 stmia r0, {r6 - r11}
224 ldmfd sp!, {r4 - r11, pc} 228 ldmfd sp!, {r4 - r11, pc}
225ENDPROC(cpu_v7_do_suspend) 229ENDPROC(cpu_v7_do_suspend)
226 230
@@ -228,9 +232,11 @@ ENTRY(cpu_v7_do_resume)
228 mov ip, #0 232 mov ip, #0
229 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 233 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
230 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 234 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
231 ldmia r0, {r4 - r11} 235 ldmia r0!, {r4 - r6}
232 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 236 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
233 mcr p15, 0, r5, c13, c0, 1 @ Context ID 237 mcr p15, 0, r5, c13, c0, 1 @ Context ID
238 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
239 ldmia r0, {r6 - r11}
234 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 240 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
235 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 241 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
236 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 242 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
@@ -416,9 +422,9 @@ ENTRY(v7_processor_functions)
416 .word cpu_v7_dcache_clean_area 422 .word cpu_v7_dcache_clean_area
417 .word cpu_v7_switch_mm 423 .word cpu_v7_switch_mm
418 .word cpu_v7_set_pte_ext 424 .word cpu_v7_set_pte_ext
419 .word 0 425 .word cpu_v7_suspend_size
420 .word 0 426 .word cpu_v7_do_suspend
421 .word 0 427 .word cpu_v7_do_resume
422 .size v7_processor_functions, . - v7_processor_functions 428 .size v7_processor_functions, . - v7_processor_functions
423 429
424 .section ".rodata" 430 .section ".rodata"
diff --git a/arch/arm/mm/tlb-fa.S b/arch/arm/mm/tlb-fa.S
index 9694f1f6f48..d887a31faaa 100644
--- a/arch/arm/mm/tlb-fa.S
+++ b/arch/arm/mm/tlb-fa.S
@@ -46,7 +46,6 @@ ENTRY(fa_flush_user_tlb_range)
46 add r0, r0, #PAGE_SZ 46 add r0, r0, #PAGE_SZ
47 cmp r0, r1 47 cmp r0, r1
48 blo 1b 48 blo 1b
49 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 49 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
51 mov pc, lr 50 mov pc, lr
52 51
@@ -60,9 +59,8 @@ ENTRY(fa_flush_kern_tlb_range)
60 add r0, r0, #PAGE_SZ 59 add r0, r0, #PAGE_SZ
61 cmp r0, r1 60 cmp r0, r1
62 blo 1b 61 blo 1b
63 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
64 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 62 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
65 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush 63 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
66 mov pc, lr 64 mov pc, lr
67 65
68 __INITDATA 66 __INITDATA
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 73d7d89b04c..ffe06a69a6e 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -54,7 +54,6 @@ ENTRY(v6wbi_flush_user_tlb_range)
54 add r0, r0, #PAGE_SZ 54 add r0, r0, #PAGE_SZ
55 cmp r0, r1 55 cmp r0, r1
56 blo 1b 56 blo 1b
57 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier 57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
59 mov pc, lr 58 mov pc, lr
60 59
@@ -83,9 +82,8 @@ ENTRY(v6wbi_flush_kern_tlb_range)
83 add r0, r0, #PAGE_SZ 82 add r0, r0, #PAGE_SZ
84 cmp r0, r1 83 cmp r0, r1
85 blo 1b 84 blo 1b
86 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
87 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier 85 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
88 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush 86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
89 mov pc, lr 87 mov pc, lr
90 88
91 __INIT 89 __INIT
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index 53cd5b45467..86bb7166450 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -48,9 +48,6 @@ ENTRY(v7wbi_flush_user_tlb_range)
48 add r0, r0, #PAGE_SZ 48 add r0, r0, #PAGE_SZ
49 cmp r0, r1 49 cmp r0, r1
50 blo 1b 50 blo 1b
51 mov ip, #0
52 ALT_SMP(mcr p15, 0, ip, c7, c1, 6) @ flush BTAC/BTB Inner Shareable
53 ALT_UP(mcr p15, 0, ip, c7, c5, 6) @ flush BTAC/BTB
54 dsb 51 dsb
55 mov pc, lr 52 mov pc, lr
56ENDPROC(v7wbi_flush_user_tlb_range) 53ENDPROC(v7wbi_flush_user_tlb_range)
@@ -75,9 +72,6 @@ ENTRY(v7wbi_flush_kern_tlb_range)
75 add r0, r0, #PAGE_SZ 72 add r0, r0, #PAGE_SZ
76 cmp r0, r1 73 cmp r0, r1
77 blo 1b 74 blo 1b
78 mov r2, #0
79 ALT_SMP(mcr p15, 0, r2, c7, c1, 6) @ flush BTAC/BTB Inner Shareable
80 ALT_UP(mcr p15, 0, r2, c7, c5, 6) @ flush BTAC/BTB
81 dsb 75 dsb
82 isb 76 isb
83 mov pc, lr 77 mov pc, lr
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 23:36:09 -0400