diff options
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
-rw-r--r-- | arch/arm/mm/proc-v7.S | 57 |
1 files changed, 41 insertions, 16 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7563ff0141b..53cbe222515 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -30,15 +30,13 @@ | |||
30 | #define TTB_IRGN_WT ((1 << 0) | (0 << 6)) | 30 | #define TTB_IRGN_WT ((1 << 0) | (0 << 6)) |
31 | #define TTB_IRGN_WB ((1 << 0) | (1 << 6)) | 31 | #define TTB_IRGN_WB ((1 << 0) | (1 << 6)) |
32 | 32 | ||
33 | #ifndef CONFIG_SMP | ||
34 | /* PTWs cacheable, inner WB not shareable, outer WB not shareable */ | 33 | /* PTWs cacheable, inner WB not shareable, outer WB not shareable */ |
35 | #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB | 34 | #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB |
36 | #define PMD_FLAGS PMD_SECT_WB | 35 | #define PMD_FLAGS_UP PMD_SECT_WB |
37 | #else | 36 | |
38 | /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ | 37 | /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ |
39 | #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA | 38 | #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA |
40 | #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S | 39 | #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S |
41 | #endif | ||
42 | 40 | ||
43 | ENTRY(cpu_v7_proc_init) | 41 | ENTRY(cpu_v7_proc_init) |
44 | mov pc, lr | 42 | mov pc, lr |
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm) | |||
105 | #ifdef CONFIG_MMU | 103 | #ifdef CONFIG_MMU |
106 | mov r2, #0 | 104 | mov r2, #0 |
107 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | 105 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id |
108 | orr r0, r0, #TTB_FLAGS | 106 | ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) |
107 | ALT_UP(orr r0, r0, #TTB_FLAGS_UP) | ||
109 | #ifdef CONFIG_ARM_ERRATA_430973 | 108 | #ifdef CONFIG_ARM_ERRATA_430973 |
110 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB | 109 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
111 | #endif | 110 | #endif |
@@ -169,7 +168,7 @@ cpu_v7_name: | |||
169 | .ascii "ARMv7 Processor" | 168 | .ascii "ARMv7 Processor" |
170 | .align | 169 | .align |
171 | 170 | ||
172 | __INIT | 171 | __CPUINIT |
173 | 172 | ||
174 | /* | 173 | /* |
175 | * __v7_setup | 174 | * __v7_setup |
@@ -188,7 +187,8 @@ cpu_v7_name: | |||
188 | */ | 187 | */ |
189 | __v7_ca9mp_setup: | 188 | __v7_ca9mp_setup: |
190 | #ifdef CONFIG_SMP | 189 | #ifdef CONFIG_SMP |
191 | mrc p15, 0, r0, c1, c0, 1 | 190 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) |
191 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP | ||
192 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? | 192 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
193 | orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and | 193 | orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and |
194 | mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting | 194 | mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting |
@@ -253,6 +253,14 @@ __v7_setup: | |||
253 | orreq r10, r10, #1 << 22 @ set bit #22 | 253 | orreq r10, r10, #1 << 22 @ set bit #22 |
254 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | 254 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register |
255 | #endif | 255 | #endif |
256 | #ifdef CONFIG_ARM_ERRATA_743622 | ||
257 | teq r6, #0x20 @ present in r2p0 | ||
258 | teqne r6, #0x21 @ present in r2p1 | ||
259 | teqne r6, #0x22 @ present in r2p2 | ||
260 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register | ||
261 | orreq r10, r10, #1 << 6 @ set bit #6 | ||
262 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | ||
263 | #endif | ||
256 | 264 | ||
257 | 3: mov r10, #0 | 265 | 3: mov r10, #0 |
258 | #ifdef HARVARD_CACHE | 266 | #ifdef HARVARD_CACHE |
@@ -262,7 +270,8 @@ __v7_setup: | |||
262 | #ifdef CONFIG_MMU | 270 | #ifdef CONFIG_MMU |
263 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs | 271 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
264 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register | 272 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register |
265 | orr r4, r4, #TTB_FLAGS | 273 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
274 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | ||
266 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 275 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
267 | mov r10, #0x1f @ domains 0, 1 = manager | 276 | mov r10, #0x1f @ domains 0, 1 = manager |
268 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | 277 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register |
@@ -324,6 +333,8 @@ v7_crval: | |||
324 | __v7_setup_stack: | 333 | __v7_setup_stack: |
325 | .space 4 * 11 @ 11 registers | 334 | .space 4 * 11 @ 11 registers |
326 | 335 | ||
336 | __INITDATA | ||
337 | |||
327 | .type v7_processor_functions, #object | 338 | .type v7_processor_functions, #object |
328 | ENTRY(v7_processor_functions) | 339 | ENTRY(v7_processor_functions) |
329 | .word v7_early_abort | 340 | .word v7_early_abort |
@@ -337,6 +348,8 @@ ENTRY(v7_processor_functions) | |||
337 | .word cpu_v7_set_pte_ext | 348 | .word cpu_v7_set_pte_ext |
338 | .size v7_processor_functions, . - v7_processor_functions | 349 | .size v7_processor_functions, . - v7_processor_functions |
339 | 350 | ||
351 | .section ".rodata" | ||
352 | |||
340 | .type cpu_arch_name, #object | 353 | .type cpu_arch_name, #object |
341 | cpu_arch_name: | 354 | cpu_arch_name: |
342 | .asciz "armv7" | 355 | .asciz "armv7" |
@@ -354,10 +367,16 @@ cpu_elf_name: | |||
354 | __v7_ca9mp_proc_info: | 367 | __v7_ca9mp_proc_info: |
355 | .long 0x410fc090 @ Required ID value | 368 | .long 0x410fc090 @ Required ID value |
356 | .long 0xff0ffff0 @ Mask for ID | 369 | .long 0xff0ffff0 @ Mask for ID |
357 | .long PMD_TYPE_SECT | \ | 370 | ALT_SMP(.long \ |
371 | PMD_TYPE_SECT | \ | ||
372 | PMD_SECT_AP_WRITE | \ | ||
373 | PMD_SECT_AP_READ | \ | ||
374 | PMD_FLAGS_SMP) | ||
375 | ALT_UP(.long \ | ||
376 | PMD_TYPE_SECT | \ | ||
358 | PMD_SECT_AP_WRITE | \ | 377 | PMD_SECT_AP_WRITE | \ |
359 | PMD_SECT_AP_READ | \ | 378 | PMD_SECT_AP_READ | \ |
360 | PMD_FLAGS | 379 | PMD_FLAGS_UP) |
361 | .long PMD_TYPE_SECT | \ | 380 | .long PMD_TYPE_SECT | \ |
362 | PMD_SECT_XN | \ | 381 | PMD_SECT_XN | \ |
363 | PMD_SECT_AP_WRITE | \ | 382 | PMD_SECT_AP_WRITE | \ |
@@ -365,7 +384,7 @@ __v7_ca9mp_proc_info: | |||
365 | b __v7_ca9mp_setup | 384 | b __v7_ca9mp_setup |
366 | .long cpu_arch_name | 385 | .long cpu_arch_name |
367 | .long cpu_elf_name | 386 | .long cpu_elf_name |
368 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | 387 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS |
369 | .long cpu_v7_name | 388 | .long cpu_v7_name |
370 | .long v7_processor_functions | 389 | .long v7_processor_functions |
371 | .long v7wbi_tlb_fns | 390 | .long v7wbi_tlb_fns |
@@ -380,10 +399,16 @@ __v7_ca9mp_proc_info: | |||
380 | __v7_proc_info: | 399 | __v7_proc_info: |
381 | .long 0x000f0000 @ Required ID value | 400 | .long 0x000f0000 @ Required ID value |
382 | .long 0x000f0000 @ Mask for ID | 401 | .long 0x000f0000 @ Mask for ID |
383 | .long PMD_TYPE_SECT | \ | 402 | ALT_SMP(.long \ |
403 | PMD_TYPE_SECT | \ | ||
404 | PMD_SECT_AP_WRITE | \ | ||
405 | PMD_SECT_AP_READ | \ | ||
406 | PMD_FLAGS_SMP) | ||
407 | ALT_UP(.long \ | ||
408 | PMD_TYPE_SECT | \ | ||
384 | PMD_SECT_AP_WRITE | \ | 409 | PMD_SECT_AP_WRITE | \ |
385 | PMD_SECT_AP_READ | \ | 410 | PMD_SECT_AP_READ | \ |
386 | PMD_FLAGS | 411 | PMD_FLAGS_UP) |
387 | .long PMD_TYPE_SECT | \ | 412 | .long PMD_TYPE_SECT | \ |
388 | PMD_SECT_XN | \ | 413 | PMD_SECT_XN | \ |
389 | PMD_SECT_AP_WRITE | \ | 414 | PMD_SECT_AP_WRITE | \ |