1 files changed, 69 insertions, 27 deletions

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index d32f02b6186..ea33896449b 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -33,30 +33,37 @@ ENTRY(v7_flush_icache_all)
 ENDPROC(v7_flush_icache_all)
 
 /*
- *      v7_flush_dcache_all()
+ *      v7_op_dcache_all op
  *
- *      Flush the whole D-cache.
+ *      op=c14, Flush the whole D-cache.
+ *      op=c10, Clean the whole D-cache.
  *
  *      Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
  *
  *      - mm    - mm_struct describing address space
  */
-ENTRY(v7_flush_dcache_all)
+.macro v7_op_dcache_all op                      @ op=c10 clean, op=c14 flush
         dmb                                     @ ensure ordering with previous memory accesses
         mrc     p15, 1, r0, c0, c0, 1           @ read clidr
         ands    r3, r0, #0x7000000              @ extract loc from clidr
         mov     r3, r3, lsr #23                 @ left align loc bit field
-        beq     finished                        @ if loc is 0, then no need to clean
+        beq     1005f                           @ if loc is 0, then no need to clean
         mov     r10, #0                         @ start clean at cache level 0
-loop1:
+1001:
         add     r2, r10, r10, lsr #1            @ work out 3x current cache level
         mov     r1, r0, lsr r2                  @ extract cache type bits from clidr
         and     r1, r1, #7                      @ mask of the bits for current cache only
         cmp     r1, #2                          @ see what cache we have at this level
-        blt     skip                            @ skip if no cache, or just i-cache
+        blt     1004f                           @ skip if no cache, or just i-cache
+#ifdef CONFIG_PREEMPT
+        save_and_disable_irqs_notrace r9        @ make cssr&csidr read atomic
+#endif
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
         isb                                     @ isb to sych the new cssr&csidr
         mrc     p15, 1, r1, c0, c0, 0           @ read the new csidr
+#ifdef CONFIG_PREEMPT
+        restore_irqs_notrace r9
+#endif
         and     r2, r1, #7                      @ extract the length of the cache lines
         add     r2, r2, #4                      @ add 4 (line length offset)
         ldr     r4, =0x3ff
@@ -64,32 +71,40 @@ loop1:
         clz     r5, r4                          @ find bit position of way size increment
         ldr     r7, =0x7fff
         ands    r7, r7, r1, lsr #13             @ extract max number of the index size
-loop2:
+1002:
         mov     r9, r4                          @ create working copy of max way size
-loop3:
+1003:
  ARM(   orr     r11, r10, r9, lsl r5    )       @ factor way and cache number into r11
  THUMB( lsl     r6, r9, r5              )
  THUMB( orr     r11, r10, r6            )       @ factor way and cache number into r11
  ARM(   orr     r11, r11, r7, lsl r2    )       @ factor index number into r11
  THUMB( lsl     r6, r7, r2              )
  THUMB( orr     r11, r11, r6            )       @ factor index number into r11
-        mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
+        mcr     p15, 0, r11, c7, \op, 2         @ op=c10/c14, clean/flush by set/way
         subs    r9, r9, #1                      @ decrement the way
-        bge     loop3
+        bge     1003b
         subs    r7, r7, #1                      @ decrement the index
-        bge     loop2
-skip:
+        bge     1002b
+1004:
         add     r10, r10, #2                    @ increment cache number
         cmp     r3, r10
-        bgt     loop1
-finished:
+        bgt     1001b
+1005:
         mov     r10, #0                         @ swith back to cache level 0
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
         dsb
         isb
         mov     pc, lr
+.endm
+
+ENTRY(v7_flush_dcache_all)
+        v7_op_dcache_all c14
 ENDPROC(v7_flush_dcache_all)
 
+ENTRY(v7_clean_dcache_all)
+        v7_op_dcache_all c10
+ENDPROC(v7_clean_dcache_all)
+
 /*
  *      v7_flush_cache_all()
  *
@@ -114,6 +129,24 @@ ENTRY(v7_flush_kern_cache_all)
 ENDPROC(v7_flush_kern_cache_all)
 
 /*
+ *       v7_clean_kern_cache_all()
+ */
+ENTRY(v7_clean_kern_cache_all)
+ ARM(   stmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
+        bl      v7_clean_dcache_all
+        mov     r0, #0
+#ifdef CONFIG_SMP
+        mcr     p15, 0, r0, c7, c1, 0           @ invalidate I-cache inner shareable
+#else
+        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
+#endif
+ ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
+        mov     pc, lr
+ENDPROC(v7_clean_kern_cache_all)
+
+/*
  *      v7_flush_cache_all()
  *
  *      Flush all TLB entries in a particular address space
@@ -174,6 +207,10 @@ ENTRY(v7_coherent_user_range)
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r12, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
  USER(  mcr     p15, 0, r12, c7, c11, 1 )       @ clean D line to the point of unification
         add     r12, r12, r2
@@ -223,6 +260,10 @@ ENTRY(v7_flush_kern_dcache_area)
         add     r1, r0, r1
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
         add     r0, r0, r2
@@ -247,6 +288,10 @@ v7_dma_inv_range:
         sub     r3, r2, #1
         tst     r0, r3
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
         mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
 
         tst     r1, r3
@@ -270,6 +315,10 @@ v7_dma_clean_range:
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c10, 1          @ clean D / U line
         add     r0, r0, r2
@@ -288,6 +337,10 @@ ENTRY(v7_dma_flush_range)
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
         add     r0, r0, r2
@@ -325,16 +378,5 @@ ENDPROC(v7_dma_unmap_area)
 
         __INITDATA
 
-        .type   v7_cache_fns, #object
-ENTRY(v7_cache_fns)
-        .long   v7_flush_icache_all
-        .long   v7_flush_kern_cache_all
-        .long   v7_flush_user_cache_all
-        .long   v7_flush_user_cache_range
-        .long   v7_coherent_kern_range
-        .long   v7_coherent_user_range
-        .long   v7_flush_kern_dcache_area
-        .long   v7_dma_map_area
-        .long   v7_dma_unmap_area
-        .long   v7_dma_flush_range
-        .size   v7_cache_fns, . - v7_cache_fns
+        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+        define_cache_functions v7