diff options
Diffstat (limited to 'arch/arm/mach-ux500/include')
-rw-r--r-- | arch/arm/mach-ux500/include/mach/entry-macro.S | 68 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/smp.h | 5 |
2 files changed, 4 insertions, 69 deletions
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S index 60ea88db828..a37f585a3ec 100644 --- a/arch/arm/mach-ux500/include/mach/entry-macro.S +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S | |||
@@ -11,7 +11,8 @@ | |||
11 | * warranty of any kind, whether express or implied. | 11 | * warranty of any kind, whether express or implied. |
12 | */ | 12 | */ |
13 | #include <mach/hardware.h> | 13 | #include <mach/hardware.h> |
14 | #include <asm/hardware/gic.h> | 14 | #define HAVE_GET_IRQNR_PREAMBLE |
15 | #include <asm/hardware/entry-macro-gic.S> | ||
15 | 16 | ||
16 | .macro disable_fiq | 17 | .macro disable_fiq |
17 | .endm | 18 | .endm |
@@ -22,68 +23,3 @@ | |||
22 | 23 | ||
23 | .macro arch_ret_to_user, tmp1, tmp2 | 24 | .macro arch_ret_to_user, tmp1, tmp2 |
24 | .endm | 25 | .endm |
25 | |||
26 | /* | ||
27 | * The interrupt numbering scheme is defined in the | ||
28 | * interrupt controller spec. To wit: | ||
29 | * | ||
30 | * Interrupts 0-15 are IPI | ||
31 | * 16-28 are reserved | ||
32 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
33 | * 32-1020 are global | ||
34 | * 1021-1022 are reserved | ||
35 | * 1023 is "spurious" (no interrupt) | ||
36 | * | ||
37 | * For now, we ignore all local interrupts so only return an | ||
38 | * interrupt if it's between 30 and 1020. The test_for_ipi | ||
39 | * routine below will pick up on IPIs. | ||
40 | * | ||
41 | * A simple read from the controller will tell us the number | ||
42 | * of the highest priority enabled interrupt. We then just | ||
43 | * need to check whether it is in the valid range for an | ||
44 | * IRQ (30-1020 inclusive). | ||
45 | */ | ||
46 | |||
47 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
48 | |||
49 | /* bits 12-10 = src CPU, 9-0 = int # */ | ||
50 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
51 | |||
52 | ldr \tmp, =1021 | ||
53 | |||
54 | bic \irqnr, \irqstat, #0x1c00 | ||
55 | |||
56 | cmp \irqnr, #29 | ||
57 | cmpcc \irqnr, \irqnr | ||
58 | cmpne \irqnr, \tmp | ||
59 | cmpcs \irqnr, \irqnr | ||
60 | |||
61 | .endm | ||
62 | |||
63 | /* We assume that irqstat (the raw value of the IRQ | ||
64 | * acknowledge register) is preserved from the macro above. | ||
65 | * If there is an IPI, we immediately signal end of | ||
66 | * interrupt on the controller, since this requires the | ||
67 | * original irqstat value which we won't easily be able | ||
68 | * to recreate later. | ||
69 | */ | ||
70 | |||
71 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
72 | bic \irqnr, \irqstat, #0x1c00 | ||
73 | cmp \irqnr, #16 | ||
74 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
75 | cmpcs \irqnr, \irqnr | ||
76 | .endm | ||
77 | |||
78 | /* As above, this assumes that irqstat and base | ||
79 | * are preserved.. | ||
80 | */ | ||
81 | |||
82 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
83 | bic \irqnr, \irqstat, #0x1c00 | ||
84 | mov \tmp, #0 | ||
85 | cmp \irqnr, #29 | ||
86 | moveq \tmp, #1 | ||
87 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
88 | cmp \tmp, #0 | ||
89 | .endm | ||
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h index 197e8417375..ca2b15b1b3b 100644 --- a/arch/arm/mach-ux500/include/mach/smp.h +++ b/arch/arm/mach-ux500/include/mach/smp.h | |||
@@ -10,7 +10,6 @@ | |||
10 | #define ASMARM_ARCH_SMP_H | 10 | #define ASMARM_ARCH_SMP_H |
11 | 11 | ||
12 | #include <asm/hardware/gic.h> | 12 | #include <asm/hardware/gic.h> |
13 | #include <asm/smp_mpidr.h> | ||
14 | 13 | ||
15 | /* This is required to wakeup the secondary core */ | 14 | /* This is required to wakeup the secondary core */ |
16 | extern void u8500_secondary_startup(void); | 15 | extern void u8500_secondary_startup(void); |
@@ -18,8 +17,8 @@ extern void u8500_secondary_startup(void); | |||
18 | /* | 17 | /* |
19 | * We use IRQ1 as the IPI | 18 | * We use IRQ1 as the IPI |
20 | */ | 19 | */ |
21 | static inline void smp_cross_call(const struct cpumask *mask) | 20 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
22 | { | 21 | { |
23 | gic_raise_softirq(mask, 1); | 22 | gic_raise_softirq(mask, ipi); |
24 | } | 23 | } |
25 | #endif | 24 | #endif |