aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h')
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h189
1 files changed, 68 insertions, 121 deletions
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
index 6c42d2a47c1..50d90ea1b13 100644
--- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
+++ b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * STMP PINCTRL Register Definitions 2 * stmp378x: PINCTRL register definitions
3 * 3 *
4 * Copyright (c) 2008 Freescale Semiconductor 4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
@@ -18,126 +18,73 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
21 23
22#ifndef __ARCH_ARM___PINCTRL_H 24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
23#define __ARCH_ARM___PINCTRL_H 1 25#define REGS_PINCTRL_PHYS 0x80018000
26#define REGS_PINCTRL_SIZE 0x2000
24 27
25#include <mach/stmp3xxx_regs.h> 28#define HW_PINCTRL_MUXSEL0 0x100
29#define HW_PINCTRL_MUXSEL1 0x110
30#define HW_PINCTRL_MUXSEL2 0x120
31#define HW_PINCTRL_MUXSEL3 0x130
32#define HW_PINCTRL_MUXSEL4 0x140
33#define HW_PINCTRL_MUXSEL5 0x150
34#define HW_PINCTRL_MUXSEL6 0x160
35#define HW_PINCTRL_MUXSEL7 0x170
26 36
27#define REGS_PINCTRL_BASE (REGS_BASE + 0x18000) 37#define HW_PINCTRL_DRIVE0 0x200
28#define REGS_PINCTRL_BASE_PHYS (0x80018000) 38#define HW_PINCTRL_DRIVE1 0x210
29#define REGS_PINCTRL_SIZE 0x00002000 39#define HW_PINCTRL_DRIVE2 0x220
30HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0x00000000) 40#define HW_PINCTRL_DRIVE3 0x230
31#define HW_PINCTRL_CTRL_ADDR (REGS_PINCTRL_BASE + 0x00000000) 41#define HW_PINCTRL_DRIVE4 0x240
32#define BM_PINCTRL_CTRL_SFTRST 0x80000000 42#define HW_PINCTRL_DRIVE5 0x250
33#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 43#define HW_PINCTRL_DRIVE6 0x260
34#define BM_PINCTRL_CTRL_PRESENT3 0x08000000 44#define HW_PINCTRL_DRIVE7 0x270
35#define BM_PINCTRL_CTRL_PRESENT2 0x04000000 45#define HW_PINCTRL_DRIVE8 0x280
36#define BM_PINCTRL_CTRL_PRESENT1 0x02000000 46#define HW_PINCTRL_DRIVE9 0x290
37#define BM_PINCTRL_CTRL_PRESENT0 0x01000000 47#define HW_PINCTRL_DRIVE10 0x2A0
38#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 48#define HW_PINCTRL_DRIVE11 0x2B0
39#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 49#define HW_PINCTRL_DRIVE12 0x2C0
40#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 50#define HW_PINCTRL_DRIVE13 0x2D0
41HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x00000100) 51#define HW_PINCTRL_DRIVE14 0x2E0
42#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x00000100) 52
43HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x00000110) 53#define HW_PINCTRL_PULL0 0x400
44#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x00000110) 54#define HW_PINCTRL_PULL1 0x410
45HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x00000120) 55#define HW_PINCTRL_PULL2 0x420
46#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x00000120) 56#define HW_PINCTRL_PULL3 0x430
47HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x00000130) 57
48#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x00000130) 58#define HW_PINCTRL_DOUT0 0x500
49HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x00000140) 59#define HW_PINCTRL_DOUT1 0x510
50#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x00000140) 60#define HW_PINCTRL_DOUT2 0x520
51HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x00000150) 61
52#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x00000150) 62#define HW_PINCTRL_DIN0 0x600
53HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x00000160) 63#define HW_PINCTRL_DIN1 0x610
54#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x00000160) 64#define HW_PINCTRL_DIN2 0x620
55HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x00000170) 65
56#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x00000170) 66#define HW_PINCTRL_DOE0 0x700
57HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x00000200) 67#define HW_PINCTRL_DOE1 0x710
58#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x00000200) 68#define HW_PINCTRL_DOE2 0x720
59HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x00000210) 69
60#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x00000210) 70#define HW_PINCTRL_PIN2IRQ0 0x800
61HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x00000220) 71#define HW_PINCTRL_PIN2IRQ1 0x810
62#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x00000220) 72#define HW_PINCTRL_PIN2IRQ2 0x820
63HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x00000230) 73
64#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x00000230) 74#define HW_PINCTRL_IRQEN0 0x900
65HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x00000240) 75#define HW_PINCTRL_IRQEN1 0x910
66#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x00000240) 76#define HW_PINCTRL_IRQEN2 0x920
67HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x00000250) 77
68#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x00000250) 78#define HW_PINCTRL_IRQLEVEL0 0xA00
69HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x00000260) 79#define HW_PINCTRL_IRQLEVEL1 0xA10
70#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x00000260) 80#define HW_PINCTRL_IRQLEVEL2 0xA20
71HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x00000270) 81
72#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x00000270) 82#define HW_PINCTRL_IRQPOL0 0xB00
73HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x00000280) 83#define HW_PINCTRL_IRQPOL1 0xB10
74#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x00000280) 84#define HW_PINCTRL_IRQPOL2 0xB20
75HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x00000290) 85
76#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x00000290) 86#define HW_PINCTRL_IRQSTAT0 0xC00
77HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x000002a0) 87#define HW_PINCTRL_IRQSTAT1 0xC10
78#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x000002a0) 88#define HW_PINCTRL_IRQSTAT2 0xC20
79HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x000002b0) 89
80#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x000002b0) 90#endif
81HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x000002c0)
82#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x000002c0)
83HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x000002d0)
84#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x000002d0)
85HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x000002e0)
86#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x000002e0)
87HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x00000400)
88#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x00000400)
89HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x00000410)
90#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x00000410)
91HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x00000420)
92#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x00000420)
93HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x00000430)
94#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x00000430)
95HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x00000500)
96#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x00000500)
97HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x00000510)
98#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x00000510)
99HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x00000520)
100#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x00000520)
101HW_REGISTER(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x00000600)
102#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x00000600)
103HW_REGISTER(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x00000610)
104#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x00000610)
105HW_REGISTER(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x00000620)
106#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x00000620)
107HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x00000700)
108#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x00000700)
109HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x00000710)
110#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x00000710)
111HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x00000720)
112#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x00000720)
113HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x00000800)
114#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x00000800)
115HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x00000810)
116#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x00000810)
117HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x00000820)
118#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x00000820)
119HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x00000900)
120#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x00000900)
121HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x00000910)
122#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x00000910)
123HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x00000920)
124#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x00000920)
125HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x00000a00)
126#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x00000a00)
127HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x00000a10)
128#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x00000a10)
129HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x00000a20)
130#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x00000a20)
131HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0x00000b00)
132#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0x00000b00)
133HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0x00000b10)
134#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0x00000b10)
135HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0x00000b20)
136#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0x00000b20)
137HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0x00000c00)
138#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0x00000c00)
139HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0x00000c10)
140#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0x00000c10)
141HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0x00000c20)
142#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0x00000c20)
143#endif /* __ARCH_ARM___PINCTRL_H */