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-rw-r--r--arch/arm/mach-spear6xx/Makefile.boot2
-rw-r--r--arch/arm/mach-spear6xx/clock.c80
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c372
3 files changed, 413 insertions, 41 deletions
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221d..af493da37ab 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
1zreladdr-y += 0x00008000 1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
4
5dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index a86499a8a15..adadef2b27b 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk;
623 623
624/* array of all spear 6xx clock lookups */ 624/* array of all spear 6xx clock lookups */
625static struct clk_lookup spear_clk_lookups[] = { 625static struct clk_lookup spear_clk_lookups[] = {
626 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, 626 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
627 /* root clks */ 627 /* root clks */
628 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, 628 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
629 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, 629 CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
630 /* clock derived from 32 KHz os clk */ 630 /* clock derived from 32 KHz os clk */
631 { .dev_id = "rtc-spear", .clk = &rtc_clk}, 631 CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
632 /* clock derived from 30 MHz os clk */ 632 /* clock derived from 30 MHz os clk */
633 { .con_id = "pll1_clk", .clk = &pll1_clk}, 633 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
634 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, 634 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
635 { .dev_id = "wdt", .clk = &wdt_clk}, 635 CLKDEV_INIT("wdt", NULL, &wdt_clk),
636 /* clock derived from pll1 clk */ 636 /* clock derived from pll1 clk */
637 { .con_id = "cpu_clk", .clk = &cpu_clk}, 637 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
638 { .con_id = "ahb_clk", .clk = &ahb_clk}, 638 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
639 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, 639 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
640 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, 640 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
641 { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk}, 641 CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
642 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, 642 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
643 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, 643 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
644 { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk}, 644 CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
645 { .dev_id = "d0000000.serial", .clk = &uart0_clk}, 645 CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
646 { .dev_id = "d0080000.serial", .clk = &uart1_clk}, 646 CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
647 { .dev_id = "firda", .clk = &firda_clk}, 647 CLKDEV_INIT("firda", NULL, &firda_clk),
648 { .dev_id = "clcd", .clk = &clcd_clk}, 648 CLKDEV_INIT("clcd", NULL, &clcd_clk),
649 { .dev_id = "gpt0", .clk = &gpt0_clk}, 649 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
650 { .dev_id = "gpt1", .clk = &gpt1_clk}, 650 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
651 { .dev_id = "gpt2", .clk = &gpt2_clk}, 651 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
652 { .dev_id = "gpt3", .clk = &gpt3_clk}, 652 CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
653 /* clock derived from pll3 clk */ 653 /* clock derived from pll3 clk */
654 { .dev_id = "designware_udc", .clk = &usbd_clk}, 654 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
655 { .con_id = "usbh.0_clk", .clk = &usbh0_clk}, 655 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
656 { .con_id = "usbh.1_clk", .clk = &usbh1_clk}, 656 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
657 /* clock derived from ahb clk */ 657 /* clock derived from ahb clk */
658 { .con_id = "apb_clk", .clk = &apb_clk}, 658 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
659 { .dev_id = "d0200000.i2c", .clk = &i2c_clk}, 659 CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
660 { .dev_id = "dma", .clk = &dma_clk}, 660 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
661 { .dev_id = "jpeg", .clk = &jpeg_clk}, 661 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
662 { .dev_id = "gmac", .clk = &gmac_clk}, 662 CLKDEV_INIT("gmac", NULL, &gmac_clk),
663 { .dev_id = "smi", .clk = &smi_clk}, 663 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
664 { .dev_id = "fsmc-nand", .clk = &fsmc_clk}, 664 CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
665 /* clock derived from apb clk */ 665 /* clock derived from apb clk */
666 { .dev_id = "adc", .clk = &adc_clk}, 666 CLKDEV_INIT("adc", NULL, &adc_clk),
667 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, 667 CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
668 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, 668 CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
669 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, 669 CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
670 { .dev_id = "f0100000.gpio", .clk = &gpio0_clk}, 670 CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
671 { .dev_id = "fc980000.gpio", .clk = &gpio1_clk}, 671 CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
672 { .dev_id = "d8100000.gpio", .clk = &gpio2_clk}, 672 CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
673}; 673};
674 674
675void __init spear6xx_clk_init(void) 675void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c..5b9e30f54cd 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h> 18#include <linux/of_address.h>
18#include <linux/of_irq.h> 19#include <linux/of_irq.h>
19#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <asm/hardware/pl080.h>
20#include <asm/hardware/vic.h> 22#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <plat/pl080.h>
22#include <mach/generic.h> 25#include <mach/generic.h>
23#include <mach/hardware.h> 26#include <mach/hardware.h>
24 27
28/* dmac device registration */
29static struct pl08x_channel_data spear600_dma_info[] = {
30 {
31 .bus_id = "ssp1_rx",
32 .min_signal = 0,
33 .max_signal = 0,
34 .muxval = 0,
35 .cctl = 0,
36 .periph_buses = PL08X_AHB1,
37 }, {
38 .bus_id = "ssp1_tx",
39 .min_signal = 1,
40 .max_signal = 1,
41 .muxval = 0,
42 .cctl = 0,
43 .periph_buses = PL08X_AHB1,
44 }, {
45 .bus_id = "uart0_rx",
46 .min_signal = 2,
47 .max_signal = 2,
48 .muxval = 0,
49 .cctl = 0,
50 .periph_buses = PL08X_AHB1,
51 }, {
52 .bus_id = "uart0_tx",
53 .min_signal = 3,
54 .max_signal = 3,
55 .muxval = 0,
56 .cctl = 0,
57 .periph_buses = PL08X_AHB1,
58 }, {
59 .bus_id = "uart1_rx",
60 .min_signal = 4,
61 .max_signal = 4,
62 .muxval = 0,
63 .cctl = 0,
64 .periph_buses = PL08X_AHB1,
65 }, {
66 .bus_id = "uart1_tx",
67 .min_signal = 5,
68 .max_signal = 5,
69 .muxval = 0,
70 .cctl = 0,
71 .periph_buses = PL08X_AHB1,
72 }, {
73 .bus_id = "ssp2_rx",
74 .min_signal = 6,
75 .max_signal = 6,
76 .muxval = 0,
77 .cctl = 0,
78 .periph_buses = PL08X_AHB2,
79 }, {
80 .bus_id = "ssp2_tx",
81 .min_signal = 7,
82 .max_signal = 7,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB2,
86 }, {
87 .bus_id = "ssp0_rx",
88 .min_signal = 8,
89 .max_signal = 8,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_tx",
95 .min_signal = 9,
96 .max_signal = 9,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "i2c_rx",
102 .min_signal = 10,
103 .max_signal = 10,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_tx",
109 .min_signal = 11,
110 .max_signal = 11,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "irda",
116 .min_signal = 12,
117 .max_signal = 12,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "adc",
123 .min_signal = 13,
124 .max_signal = 13,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB2,
128 }, {
129 .bus_id = "to_jpeg",
130 .min_signal = 14,
131 .max_signal = 14,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "from_jpeg",
137 .min_signal = 15,
138 .max_signal = 15,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "ras0_rx",
144 .min_signal = 0,
145 .max_signal = 0,
146 .muxval = 1,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_tx",
151 .min_signal = 1,
152 .max_signal = 1,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras1_rx",
158 .min_signal = 2,
159 .max_signal = 2,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_tx",
165 .min_signal = 3,
166 .max_signal = 3,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras2_rx",
172 .min_signal = 4,
173 .max_signal = 4,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_tx",
179 .min_signal = 5,
180 .max_signal = 5,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras3_rx",
186 .min_signal = 6,
187 .max_signal = 6,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_tx",
193 .min_signal = 7,
194 .max_signal = 7,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras4_rx",
200 .min_signal = 8,
201 .max_signal = 8,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_tx",
207 .min_signal = 9,
208 .max_signal = 9,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras5_rx",
214 .min_signal = 10,
215 .max_signal = 10,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_tx",
221 .min_signal = 11,
222 .max_signal = 11,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras6_rx",
228 .min_signal = 12,
229 .max_signal = 12,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_tx",
235 .min_signal = 13,
236 .max_signal = 13,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras7_rx",
242 .min_signal = 14,
243 .max_signal = 14,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_tx",
249 .min_signal = 15,
250 .max_signal = 15,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ext0_rx",
256 .min_signal = 0,
257 .max_signal = 0,
258 .muxval = 2,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB2,
261 }, {
262 .bus_id = "ext0_tx",
263 .min_signal = 1,
264 .max_signal = 1,
265 .muxval = 2,
266 .cctl = 0,
267 .periph_buses = PL08X_AHB2,
268 }, {
269 .bus_id = "ext1_rx",
270 .min_signal = 2,
271 .max_signal = 2,
272 .muxval = 2,
273 .cctl = 0,
274 .periph_buses = PL08X_AHB2,
275 }, {
276 .bus_id = "ext1_tx",
277 .min_signal = 3,
278 .max_signal = 3,
279 .muxval = 2,
280 .cctl = 0,
281 .periph_buses = PL08X_AHB2,
282 }, {
283 .bus_id = "ext2_rx",
284 .min_signal = 4,
285 .max_signal = 4,
286 .muxval = 2,
287 .cctl = 0,
288 .periph_buses = PL08X_AHB2,
289 }, {
290 .bus_id = "ext2_tx",
291 .min_signal = 5,
292 .max_signal = 5,
293 .muxval = 2,
294 .cctl = 0,
295 .periph_buses = PL08X_AHB2,
296 }, {
297 .bus_id = "ext3_rx",
298 .min_signal = 6,
299 .max_signal = 6,
300 .muxval = 2,
301 .cctl = 0,
302 .periph_buses = PL08X_AHB2,
303 }, {
304 .bus_id = "ext3_tx",
305 .min_signal = 7,
306 .max_signal = 7,
307 .muxval = 2,
308 .cctl = 0,
309 .periph_buses = PL08X_AHB2,
310 }, {
311 .bus_id = "ext4_rx",
312 .min_signal = 8,
313 .max_signal = 8,
314 .muxval = 2,
315 .cctl = 0,
316 .periph_buses = PL08X_AHB2,
317 }, {
318 .bus_id = "ext4_tx",
319 .min_signal = 9,
320 .max_signal = 9,
321 .muxval = 2,
322 .cctl = 0,
323 .periph_buses = PL08X_AHB2,
324 }, {
325 .bus_id = "ext5_rx",
326 .min_signal = 10,
327 .max_signal = 10,
328 .muxval = 2,
329 .cctl = 0,
330 .periph_buses = PL08X_AHB2,
331 }, {
332 .bus_id = "ext5_tx",
333 .min_signal = 11,
334 .max_signal = 11,
335 .muxval = 2,
336 .cctl = 0,
337 .periph_buses = PL08X_AHB2,
338 }, {
339 .bus_id = "ext6_rx",
340 .min_signal = 12,
341 .max_signal = 12,
342 .muxval = 2,
343 .cctl = 0,
344 .periph_buses = PL08X_AHB2,
345 }, {
346 .bus_id = "ext6_tx",
347 .min_signal = 13,
348 .max_signal = 13,
349 .muxval = 2,
350 .cctl = 0,
351 .periph_buses = PL08X_AHB2,
352 }, {
353 .bus_id = "ext7_rx",
354 .min_signal = 14,
355 .max_signal = 14,
356 .muxval = 2,
357 .cctl = 0,
358 .periph_buses = PL08X_AHB2,
359 }, {
360 .bus_id = "ext7_tx",
361 .min_signal = 15,
362 .max_signal = 15,
363 .muxval = 2,
364 .cctl = 0,
365 .periph_buses = PL08X_AHB2,
366 },
367};
368
369struct pl08x_platform_data pl080_plat_data = {
370 .memcpy_channel = {
371 .bus_id = "memcpy",
372 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
373 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
374 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
375 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
376 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
377 PL080_CONTROL_PROT_SYS),
378 },
379 .lli_buses = PL08X_AHB1,
380 .mem_buses = PL08X_AHB1,
381 .get_signal = pl080_get_signal,
382 .put_signal = pl080_put_signal,
383 .slave_channels = spear600_dma_info,
384 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
385};
386
25/* Following will create static virtual/physical mappings */ 387/* Following will create static virtual/physical mappings */
26static struct map_desc spear6xx_io_desc[] __initdata = { 388static struct map_desc spear6xx_io_desc[] __initdata = {
27 { 389 {
@@ -92,9 +454,17 @@ struct sys_timer spear6xx_timer = {
92 .init = spear6xx_timer_init, 454 .init = spear6xx_timer_init,
93}; 455};
94 456
457/* Add auxdata to pass platform data */
458struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
459 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
460 &pl080_plat_data),
461 {}
462};
463
95static void __init spear600_dt_init(void) 464static void __init spear600_dt_init(void)
96{ 465{
97 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 466 of_platform_populate(NULL, of_default_bus_match_table,
467 spear6xx_auxdata_lookup, NULL);
98} 468}
99 469
100static const char *spear600_dt_board_compat[] = { 470static const char *spear600_dt_board_compat[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 23:24:36 -0500