1 files changed, 163 insertions, 0 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
new file mode 100644
index 00000000000..38d767a1aba
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -0,0 +1,163 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/misc_regs.h
+ *
+ * Miscellaneous registers definitions for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __MACH_MISC_REGS_H
+#define __MACH_MISC_REGS_H
+#include <mach/spear.h>
+#define MISC_BASE               VA_SPEAR3XX_ICM3_MISC_REG_BASE
+#define SOC_CFG_CTR             ((unsigned int *)(MISC_BASE + 0x000))
+#define DIAG_CFG_CTR            ((unsigned int *)(MISC_BASE + 0x004))
+#define PLL1_CTR                ((unsigned int *)(MISC_BASE + 0x008))
+#define PLL1_FRQ                ((unsigned int *)(MISC_BASE + 0x00C))
+#define PLL1_MOD                ((unsigned int *)(MISC_BASE + 0x010))
+#define PLL2_CTR                ((unsigned int *)(MISC_BASE + 0x014))
+/* PLL_CTR register masks */
+#define PLL_ENABLE              2
+#define PLL_MODE_SHIFT          4
+#define PLL_MODE_MASK           0x3
+#define PLL_MODE_NORMAL         0
+#define PLL_MODE_FRACTION       1
+#define PLL_MODE_DITH_DSB       2
+#define PLL_MODE_DITH_SSB       3
+#define PLL2_FRQ                ((unsigned int *)(MISC_BASE + 0x018))
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT         0
+#define PLL_DIV_N_MASK          0xFF
+#define PLL_DIV_P_SHIFT         8
+#define PLL_DIV_P_MASK          0x7
+#define PLL_NORM_FDBK_M_SHIFT   24
+#define PLL_NORM_FDBK_M_MASK    0xFF
+#define PLL_DITH_FDBK_M_SHIFT   16
+#define PLL_DITH_FDBK_M_MASK    0xFFFF
+#define PLL2_MOD                ((unsigned int *)(MISC_BASE + 0x01C))
+#define PLL_CLK_CFG             ((unsigned int *)(MISC_BASE + 0x020))
+#define CORE_CLK_CFG            ((unsigned int *)(MISC_BASE + 0x024))
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT    10
+#define PLL_HCLK_RATIO_MASK     0x3
+#define HCLK_PCLK_RATIO_SHIFT   8
+#define HCLK_PCLK_RATIO_MASK    0x3
+#define PERIP_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x028))
+/* PERIP_CLK_CFG register masks */
+#define UART_CLK_SHIFT          4
+#define UART_CLK_MASK           0x1
+#define FIRDA_CLK_SHIFT         5
+#define FIRDA_CLK_MASK          0x3
+#define GPT0_CLK_SHIFT          8
+#define GPT1_CLK_SHIFT          11
+#define GPT2_CLK_SHIFT          12
+#define GPT_CLK_MASK            0x1
+#define AUX_CLK_PLL3_MASK       0
+#define AUX_CLK_PLL1_MASK       1
+#define PERIP1_CLK_ENB          ((unsigned int *)(MISC_BASE + 0x02C))
+/* PERIP1_CLK_ENB register masks */
+#define UART_CLK_ENB            3
+#define SSP_CLK_ENB             5
+#define I2C_CLK_ENB             7
+#define JPEG_CLK_ENB            8
+#define FIRDA_CLK_ENB           10
+#define GPT1_CLK_ENB            11
+#define GPT2_CLK_ENB            12
+#define ADC_CLK_ENB             15
+#define RTC_CLK_ENB             17
+#define GPIO_CLK_ENB            18
+#define DMA_CLK_ENB             19
+#define SMI_CLK_ENB             21
+#define GMAC_CLK_ENB            23
+#define USBD_CLK_ENB            24
+#define USBH_CLK_ENB            25
+#define C3_CLK_ENB              31
+#define SOC_CORE_ID             ((unsigned int *)(MISC_BASE + 0x030))
+#define RAS_CLK_ENB             ((unsigned int *)(MISC_BASE + 0x034))
+#define PERIP1_SOF_RST          ((unsigned int *)(MISC_BASE + 0x038))
+/* PERIP1_SOF_RST register masks */
+#define JPEG_SOF_RST            8
+#define SOC_USER_ID             ((unsigned int *)(MISC_BASE + 0x03C))
+#define RAS_SOF_RST             ((unsigned int *)(MISC_BASE + 0x040))
+#define PRSC1_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x044))
+#define PRSC2_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x048))
+#define PRSC3_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x04C))
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT        0
+#define GPT_MSCALE_MASK         0xFFF
+#define GPT_NSCALE_SHIFT        12
+#define GPT_NSCALE_MASK         0xF
+#define AMEM_CLK_CFG            ((unsigned int *)(MISC_BASE + 0x050))
+#define EXPI_CLK_CFG            ((unsigned int *)(MISC_BASE + 0x054))
+#define CLCD_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x05C))
+#define FIRDA_CLK_SYNT          ((unsigned int *)(MISC_BASE + 0x060))
+#define UART_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x064))
+#define GMAC_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x068))
+#define RAS1_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x06C))
+#define RAS2_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x070))
+#define RAS3_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x074))
+#define RAS4_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x078))
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_EQ_SEL_SHIFT        30
+#define AUX_EQ_SEL_MASK         1
+#define AUX_EQ1_SEL             0
+#define AUX_EQ2_SEL             1
+#define AUX_XSCALE_SHIFT        16
+#define AUX_XSCALE_MASK         0xFFF
+#define AUX_YSCALE_SHIFT        0
+#define AUX_YSCALE_MASK         0xFFF
+#define ICM1_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x07C))
+#define ICM2_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x080))
+#define ICM3_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x084))
+#define ICM4_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x088))
+#define ICM5_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x08C))
+#define ICM6_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x090))
+#define ICM7_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x094))
+#define ICM8_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x098))
+#define ICM9_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x09C))
+#define DMA_CHN_CFG             ((unsigned int *)(MISC_BASE + 0x0A0))
+#define USB2_PHY_CFG            ((unsigned int *)(MISC_BASE + 0x0A4))
+#define GMAC_CFG_CTR            ((unsigned int *)(MISC_BASE + 0x0A8))
+#define EXPI_CFG_CTR            ((unsigned int *)(MISC_BASE + 0x0AC))
+#define PRC1_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0C0))
+#define PRC2_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0C4))
+#define PRC3_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0C8))
+#define PRC4_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0CC))
+#define PRC1_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0D0))
+#define PRC2_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0D4))
+#define PRC3_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0D8))
+#define PRC4_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0DC))
+#define PWRDOWN_CFG_CTR         ((unsigned int *)(MISC_BASE + 0x0E0))
+#define COMPSSTL_1V8_CFG        ((unsigned int *)(MISC_BASE + 0x0E4))
+#define COMPSSTL_2V5_CFG        ((unsigned int *)(MISC_BASE + 0x0E8))
+#define COMPCOR_3V3_CFG         ((unsigned int *)(MISC_BASE + 0x0EC))
+#define SSTLPAD_CFG_CTR         ((unsigned int *)(MISC_BASE + 0x0F0))
+#define BIST1_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x0F4))
+#define BIST2_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x0F8))
+#define BIST3_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x0FC))
+#define BIST4_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x100))
+#define BIST5_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x104))
+#define BIST1_STS_RES           ((unsigned int *)(MISC_BASE + 0x108))
+#define BIST2_STS_RES           ((unsigned int *)(MISC_BASE + 0x10C))
+#define BIST3_STS_RES           ((unsigned int *)(MISC_BASE + 0x110))
+#define BIST4_STS_RES           ((unsigned int *)(MISC_BASE + 0x114))
+#define BIST5_STS_RES           ((unsigned int *)(MISC_BASE + 0x118))
+#define SYSERR_CFG_CTR          ((unsigned int *)(MISC_BASE + 0x11C))
+#endif /* __MACH_MISC_REGS_H */

diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h new file mode 100644 index 00000000000..38d767a1aba --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -0,0 +1,163 @@
	1	/*
	2	* arch/arm/mach-spear3xx/include/mach/misc_regs.h
	3	*
	4	* Miscellaneous registers definitions for SPEAr3xx machine family
	5	*
	6	* Copyright (C) 2009 ST Microelectronics
	7	* Viresh Kumar<viresh.kumar@st.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#ifndef __MACH_MISC_REGS_H
	15	#define __MACH_MISC_REGS_H
	16
	17	#include <mach/spear.h>
	18
	19	#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE
	20
	21	#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000))
	22	#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004))
	23	#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008))
	24	#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C))
	25	#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010))
	26	#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014))
	27	/* PLL_CTR register masks */
	28	#define PLL_ENABLE 2
	29	#define PLL_MODE_SHIFT 4
	30	#define PLL_MODE_MASK 0x3
	31	#define PLL_MODE_NORMAL 0
	32	#define PLL_MODE_FRACTION 1
	33	#define PLL_MODE_DITH_DSB 2
	34	#define PLL_MODE_DITH_SSB 3
	35
	36	#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018))
	37	/* PLL FRQ register masks */
	38	#define PLL_DIV_N_SHIFT 0
	39	#define PLL_DIV_N_MASK 0xFF
	40	#define PLL_DIV_P_SHIFT 8
	41	#define PLL_DIV_P_MASK 0x7
	42	#define PLL_NORM_FDBK_M_SHIFT 24
	43	#define PLL_NORM_FDBK_M_MASK 0xFF
	44	#define PLL_DITH_FDBK_M_SHIFT 16
	45	#define PLL_DITH_FDBK_M_MASK 0xFFFF
	46
	47	#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C))
	48	#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020))
	49	#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024))
	50	/* CORE CLK CFG register masks */
	51	#define PLL_HCLK_RATIO_SHIFT 10
	52	#define PLL_HCLK_RATIO_MASK 0x3
	53	#define HCLK_PCLK_RATIO_SHIFT 8
	54	#define HCLK_PCLK_RATIO_MASK 0x3
	55
	56	#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028))
	57	/* PERIP_CLK_CFG register masks */
	58	#define UART_CLK_SHIFT 4
	59	#define UART_CLK_MASK 0x1
	60	#define FIRDA_CLK_SHIFT 5
	61	#define FIRDA_CLK_MASK 0x3
	62	#define GPT0_CLK_SHIFT 8
	63	#define GPT1_CLK_SHIFT 11
	64	#define GPT2_CLK_SHIFT 12
	65	#define GPT_CLK_MASK 0x1
	66	#define AUX_CLK_PLL3_MASK 0
	67	#define AUX_CLK_PLL1_MASK 1
	68
	69	#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C))
	70	/* PERIP1_CLK_ENB register masks */
	71	#define UART_CLK_ENB 3
	72	#define SSP_CLK_ENB 5
	73	#define I2C_CLK_ENB 7
	74	#define JPEG_CLK_ENB 8
	75	#define FIRDA_CLK_ENB 10
	76	#define GPT1_CLK_ENB 11
	77	#define GPT2_CLK_ENB 12
	78	#define ADC_CLK_ENB 15
	79	#define RTC_CLK_ENB 17
	80	#define GPIO_CLK_ENB 18
	81	#define DMA_CLK_ENB 19
	82	#define SMI_CLK_ENB 21
	83	#define GMAC_CLK_ENB 23
	84	#define USBD_CLK_ENB 24
	85	#define USBH_CLK_ENB 25
	86	#define C3_CLK_ENB 31
	87
	88	#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030))
	89	#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034))
	90	#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038))
	91	/* PERIP1_SOF_RST register masks */
	92	#define JPEG_SOF_RST 8
	93
	94	#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C))
	95	#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040))
	96	#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044))
	97	#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048))
	98	#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C))
	99	/* gpt synthesizer register masks */
	100	#define GPT_MSCALE_SHIFT 0
	101	#define GPT_MSCALE_MASK 0xFFF
	102	#define GPT_NSCALE_SHIFT 12
	103	#define GPT_NSCALE_MASK 0xF
	104
	105	#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050))
	106	#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054))
	107	#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C))
	108	#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060))
	109	#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064))
	110	#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068))
	111	#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C))
	112	#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070))
	113	#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074))
	114	#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078))
	115	/* aux clk synthesiser register masks for irda to ras4 */
	116	#define AUX_EQ_SEL_SHIFT 30
	117	#define AUX_EQ_SEL_MASK 1
	118	#define AUX_EQ1_SEL 0
	119	#define AUX_EQ2_SEL 1
	120	#define AUX_XSCALE_SHIFT 16
	121	#define AUX_XSCALE_MASK 0xFFF
	122	#define AUX_YSCALE_SHIFT 0
	123	#define AUX_YSCALE_MASK 0xFFF
	124
	125	#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C))
	126	#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080))
	127	#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084))
	128	#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088))
	129	#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C))
	130	#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090))
	131	#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094))
	132	#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098))
	133	#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C))
	134	#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0))
	135	#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4))
	136	#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8))
	137	#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC))
	138	#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0))
	139	#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4))
	140	#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8))
	141	#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC))
	142	#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0))
	143	#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4))
	144	#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8))
	145	#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC))
	146	#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0))
	147	#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4))
	148	#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8))
	149	#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC))
	150	#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0))
	151	#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4))
	152	#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8))
	153	#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC))
	154	#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100))
	155	#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104))
	156	#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108))
	157	#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C))
	158	#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110))
	159	#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114))
	160	#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118))
	161	#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C))
	162
	163	#endif /* __MACH_MISC_REGS_H */