1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 162b791b898..ef0a95e592c 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -24,28 +24,28 @@
 #include <mach/common.h>
 /* SH7367 registers */
-#define RTFRQCR    0xe6150000
+#define RTFRQCR    IOMEM(0xe6150000)
-#define SYFRQCR    0xe6150004
+#define SYFRQCR    IOMEM(0xe6150004)
-#define CMFRQCR    0xe61500E0
+#define CMFRQCR    IOMEM(0xe61500E0)
-#define VCLKCR1    0xe6150008
+#define VCLKCR1    IOMEM(0xe6150008)
-#define VCLKCR2    0xe615000C
+#define VCLKCR2    IOMEM(0xe615000C)
-#define VCLKCR3    0xe615001C
+#define VCLKCR3    IOMEM(0xe615001C)
-#define SCLKACR    0xe6150010
+#define SCLKACR    IOMEM(0xe6150010)
-#define SCLKBCR    0xe6150014
+#define SCLKBCR    IOMEM(0xe6150014)
-#define SUBUSBCKCR 0xe6158080
+#define SUBUSBCKCR IOMEM(0xe6158080)
-#define SPUCKCR    0xe6150084
+#define SPUCKCR    IOMEM(0xe6150084)
-#define MSUCKCR    0xe6150088
+#define MSUCKCR    IOMEM(0xe6150088)
-#define MVI3CKCR   0xe6150090
+#define MVI3CKCR   IOMEM(0xe6150090)
-#define VOUCKCR    0xe6150094
+#define VOUCKCR    IOMEM(0xe6150094)
-#define MFCK1CR    0xe6150098
+#define MFCK1CR    IOMEM(0xe6150098)
-#define MFCK2CR    0xe615009C
+#define MFCK2CR    IOMEM(0xe615009C)
-#define PLLC1CR    0xe6150028
+#define PLLC1CR    IOMEM(0xe6150028)
-#define PLLC2CR    0xe615002C
+#define PLLC2CR    IOMEM(0xe615002C)
-#define RTMSTPCR0  0xe6158030
+#define RTMSTPCR0  IOMEM(0xe6158030)
-#define RTMSTPCR2  0xe6158038
+#define RTMSTPCR2  IOMEM(0xe6158038)
-#define SYMSTPCR0  0xe6158040
+#define SYMSTPCR0  IOMEM(0xe6158040)
-#define SYMSTPCR2  0xe6158048
+#define SYMSTPCR2  IOMEM(0xe6158048)
-#define CMMSTPCR0  0xe615804c
+#define CMMSTPCR0  IOMEM(0xe615804c)
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {

diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index 162b791b898..ef0a95e592c 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -24,28 +24,28 @@
24	#include <mach/common.h>	24	#include <mach/common.h>
25		25
26	/* SH7367 registers */	26	/* SH7367 registers */
27	#define RTFRQCR 0xe6150000	27	#define RTFRQCR IOMEM(0xe6150000)
28	#define SYFRQCR 0xe6150004	28	#define SYFRQCR IOMEM(0xe6150004)
29	#define CMFRQCR 0xe61500E0	29	#define CMFRQCR IOMEM(0xe61500E0)
30	#define VCLKCR1 0xe6150008	30	#define VCLKCR1 IOMEM(0xe6150008)
31	#define VCLKCR2 0xe615000C	31	#define VCLKCR2 IOMEM(0xe615000C)
32	#define VCLKCR3 0xe615001C	32	#define VCLKCR3 IOMEM(0xe615001C)
33	#define SCLKACR 0xe6150010	33	#define SCLKACR IOMEM(0xe6150010)
34	#define SCLKBCR 0xe6150014	34	#define SCLKBCR IOMEM(0xe6150014)
35	#define SUBUSBCKCR 0xe6158080	35	#define SUBUSBCKCR IOMEM(0xe6158080)
36	#define SPUCKCR 0xe6150084	36	#define SPUCKCR IOMEM(0xe6150084)
37	#define MSUCKCR 0xe6150088	37	#define MSUCKCR IOMEM(0xe6150088)
38	#define MVI3CKCR 0xe6150090	38	#define MVI3CKCR IOMEM(0xe6150090)
39	#define VOUCKCR 0xe6150094	39	#define VOUCKCR IOMEM(0xe6150094)
40	#define MFCK1CR 0xe6150098	40	#define MFCK1CR IOMEM(0xe6150098)
41	#define MFCK2CR 0xe615009C	41	#define MFCK2CR IOMEM(0xe615009C)
42	#define PLLC1CR 0xe6150028	42	#define PLLC1CR IOMEM(0xe6150028)
43	#define PLLC2CR 0xe615002C	43	#define PLLC2CR IOMEM(0xe615002C)
44	#define RTMSTPCR0 0xe6158030	44	#define RTMSTPCR0 IOMEM(0xe6158030)
45	#define RTMSTPCR2 0xe6158038	45	#define RTMSTPCR2 IOMEM(0xe6158038)
46	#define SYMSTPCR0 0xe6158040	46	#define SYMSTPCR0 IOMEM(0xe6158040)
47	#define SYMSTPCR2 0xe6158048	47	#define SYMSTPCR2 IOMEM(0xe6158048)
48	#define CMMSTPCR0 0xe615804c	48	#define CMMSTPCR0 IOMEM(0xe615804c)
49		49
50	/* Fixed 32 KHz root clock from EXTALR pin */	50	/* Fixed 32 KHz root clock from EXTALR pin */
51	static struct clk r_clk = {	51	static struct clk r_clk = {