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-rw-r--r--arch/arm/mach-sa1100/Makefile2
-rw-r--r--arch/arm/mach-sa1100/assabet.c185
-rw-r--r--arch/arm/mach-sa1100/badge4.c40
-rw-r--r--arch/arm/mach-sa1100/cerf.c13
-rw-r--r--arch/arm/mach-sa1100/clock.c91
-rw-r--r--arch/arm/mach-sa1100/collie.c46
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1100.c2
-rw-r--r--arch/arm/mach-sa1100/dma.c348
-rw-r--r--arch/arm/mach-sa1100/generic.c162
-rw-r--r--arch/arm/mach-sa1100/generic.h6
-rw-r--r--arch/arm/mach-sa1100/h3100.c23
-rw-r--r--arch/arm/mach-sa1100/h3600.c32
-rw-r--r--arch/arm/mach-sa1100/h3xxx.c13
-rw-r--r--arch/arm/mach-sa1100/hackkit.c7
-rw-r--r--arch/arm/mach-sa1100/include/mach/SA-1100.h229
-rw-r--r--arch/arm/mach-sa1100/include/mach/dma.h117
-rw-r--r--arch/arm/mach-sa1100/include/mach/irqs.h8
-rw-r--r--arch/arm/mach-sa1100/include/mach/neponset.h52
-rw-r--r--arch/arm/mach-sa1100/include/mach/shannon.h2
-rw-r--r--arch/arm/mach-sa1100/irq.c7
-rw-r--r--arch/arm/mach-sa1100/jornada720.c39
-rw-r--r--arch/arm/mach-sa1100/jornada720_ssp.c2
-rw-r--r--arch/arm/mach-sa1100/lart.c79
-rw-r--r--arch/arm/mach-sa1100/nanoengine.c11
-rw-r--r--arch/arm/mach-sa1100/neponset.c545
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c8
-rw-r--r--arch/arm/mach-sa1100/pleb.c24
-rw-r--r--arch/arm/mach-sa1100/shannon.c24
-rw-r--r--arch/arm/mach-sa1100/simpad.c11
-rw-r--r--arch/arm/mach-sa1100/sleep.S37
30 files changed, 777 insertions, 1388 deletions
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index ed7408d3216..60b97ec0167 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o 6obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o
7obj-m := 7obj-m :=
8obj-n := 8obj-n :=
9obj- := 9obj- :=
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index b5955ad3594..e708a93a7dd 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -21,6 +21,8 @@
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/mm.h> 22#include <linux/mm.h>
23 23
24#include <video/sa1100fb.h>
25
24#include <mach/hardware.h> 26#include <mach/hardware.h>
25#include <asm/mach-types.h> 27#include <asm/mach-types.h>
26#include <asm/irq.h> 28#include <asm/irq.h>
@@ -41,13 +43,13 @@
41#include "generic.h" 43#include "generic.h"
42 44
43#define ASSABET_BCR_DB1110 \ 45#define ASSABET_BCR_DB1110 \
44 (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ 46 (ASSABET_BCR_SPK_OFF | \
45 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ 47 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
46 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ 48 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
47 ASSABET_BCR_IRDA_MD0) 49 ASSABET_BCR_IRDA_MD0)
48 50
49#define ASSABET_BCR_DB1111 \ 51#define ASSABET_BCR_DB1111 \
50 (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ 52 (ASSABET_BCR_SPK_OFF | \
51 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ 53 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
52 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ 54 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
53 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \ 55 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
@@ -77,34 +79,6 @@ static void assabet_ucb1x00_reset(enum ucb1x00_reset state)
77} 79}
78 80
79 81
80static void assabet_backlight_power(int on)
81{
82#ifndef ASSABET_PAL_VIDEO
83 if (on)
84 ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
85 else
86#endif
87 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
88}
89
90/*
91 * Turn on/off the backlight. When turning the backlight on,
92 * we wait 500us after turning it on so we don't cause the
93 * supplies to droop when we enable the LCD controller (and
94 * cause a hard reset.)
95 */
96static void assabet_lcd_power(int on)
97{
98#ifndef ASSABET_PAL_VIDEO
99 if (on) {
100 ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
101 udelay(500);
102 } else
103#endif
104 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
105}
106
107
108/* 82/*
109 * Assabet flash support code. 83 * Assabet flash support code.
110 */ 84 */
@@ -160,15 +134,8 @@ static struct flash_platform_data assabet_flash_data = {
160}; 134};
161 135
162static struct resource assabet_flash_resources[] = { 136static struct resource assabet_flash_resources[] = {
163 { 137 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
164 .start = SA1100_CS0_PHYS, 138 DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
165 .end = SA1100_CS0_PHYS + SZ_32M - 1,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .start = SA1100_CS1_PHYS,
169 .end = SA1100_CS1_PHYS + SZ_32M - 1,
170 .flags = IORESOURCE_MEM,
171 }
172}; 139};
173 140
174 141
@@ -218,13 +185,115 @@ static struct mcp_plat_data assabet_mcp_data = {
218 .codec_pdata = &assabet_ucb1x00_data, 185 .codec_pdata = &assabet_ucb1x00_data,
219}; 186};
220 187
188static void assabet_lcd_set_visual(u32 visual)
189{
190 u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
191
192 if (machine_is_assabet()) {
193#if 1 // phase 4 or newer Assabet's
194 if (is_true_color)
195 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
196 else
197 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
198#else
199 // older Assabet's
200 if (is_true_color)
201 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
202 else
203 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
204#endif
205 }
206}
207
208#ifndef ASSABET_PAL_VIDEO
209static void assabet_lcd_backlight_power(int on)
210{
211 if (on)
212 ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
213 else
214 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
215}
216
217/*
218 * Turn on/off the backlight. When turning the backlight on, we wait
219 * 500us after turning it on so we don't cause the supplies to droop
220 * when we enable the LCD controller (and cause a hard reset.)
221 */
222static void assabet_lcd_power(int on)
223{
224 if (on) {
225 ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
226 udelay(500);
227 } else
228 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
229}
230
231/*
232 * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
233 * takes an RGB666 signal, but we provide it with an RGB565 signal
234 * instead (def_rgb_16).
235 */
236static struct sa1100fb_mach_info lq039q2ds54_info = {
237 .pixclock = 171521, .bpp = 16,
238 .xres = 320, .yres = 240,
239
240 .hsync_len = 5, .vsync_len = 1,
241 .left_margin = 61, .upper_margin = 3,
242 .right_margin = 9, .lower_margin = 0,
243
244 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
245
246 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
247 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
248
249 .backlight_power = assabet_lcd_backlight_power,
250 .lcd_power = assabet_lcd_power,
251 .set_visual = assabet_lcd_set_visual,
252};
253#else
254static void assabet_pal_backlight_power(int on)
255{
256 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
257}
258
259static void assabet_pal_power(int on)
260{
261 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
262}
263
264static struct sa1100fb_mach_info pal_info = {
265 .pixclock = 67797, .bpp = 16,
266 .xres = 640, .yres = 512,
267
268 .hsync_len = 64, .vsync_len = 6,
269 .left_margin = 125, .upper_margin = 70,
270 .right_margin = 115, .lower_margin = 36,
271
272 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
273 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
274
275 .backlight_power = assabet_pal_backlight_power,
276 .lcd_power = assabet_pal_power,
277 .set_visual = assabet_lcd_set_visual,
278};
279#endif
280
281#ifdef CONFIG_ASSABET_NEPONSET
282static struct resource neponset_resources[] = {
283 DEFINE_RES_MEM(0x10000000, 0x08000000),
284 DEFINE_RES_MEM(0x18000000, 0x04000000),
285 DEFINE_RES_MEM(0x40000000, SZ_8K),
286 DEFINE_RES_IRQ(IRQ_GPIO25),
287};
288#endif
289
221static void __init assabet_init(void) 290static void __init assabet_init(void)
222{ 291{
223 /* 292 /*
224 * Ensure that the power supply is in "high power" mode. 293 * Ensure that the power supply is in "high power" mode.
225 */ 294 */
226 GPDR |= GPIO_GPIO16;
227 GPSR = GPIO_GPIO16; 295 GPSR = GPIO_GPIO16;
296 GPDR |= GPIO_GPIO16;
228 297
229 /* 298 /*
230 * Ensure that these pins are set as outputs and are driving 299 * Ensure that these pins are set as outputs and are driving
@@ -232,8 +301,16 @@ static void __init assabet_init(void)
232 * the WS latch in the CPLD, and we don't float causing 301 * the WS latch in the CPLD, and we don't float causing
233 * excessive power drain. --rmk 302 * excessive power drain. --rmk
234 */ 303 */
235 GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
236 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; 304 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
305 GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
306
307 /*
308 * Also set GPIO27 as an output; this is used to clock UART3
309 * via the FPGA and as otherwise has no pullups or pulldowns,
310 * so stop it floating.
311 */
312 GPCR = GPIO_GPIO27;
313 GPDR |= GPIO_GPIO27;
237 314
238 /* 315 /*
239 * Set up registers for sleep mode. 316 * Set up registers for sleep mode.
@@ -247,9 +324,6 @@ static void __init assabet_init(void)
247 324
248 sa11x0_ppc_configure_mcp(); 325 sa11x0_ppc_configure_mcp();
249 326
250 sa1100fb_lcd_power = assabet_lcd_power;
251 sa1100fb_backlight_power = assabet_backlight_power;
252
253 if (machine_has_neponset()) { 327 if (machine_has_neponset()) {
254 /* 328 /*
255 * Angel sets this, but other bootloaders may not. 329 * Angel sets this, but other bootloaders may not.
@@ -262,9 +336,17 @@ static void __init assabet_init(void)
262#ifndef CONFIG_ASSABET_NEPONSET 336#ifndef CONFIG_ASSABET_NEPONSET
263 printk( "Warning: Neponset detected but full support " 337 printk( "Warning: Neponset detected but full support "
264 "hasn't been configured in the kernel\n" ); 338 "hasn't been configured in the kernel\n" );
339#else
340 platform_device_register_simple("neponset", 0,
341 neponset_resources, ARRAY_SIZE(neponset_resources));
265#endif 342#endif
266 } 343 }
267 344
345#ifndef ASSABET_PAL_VIDEO
346 sa11x0_register_lcd(&lq039q2ds54_info);
347#else
348 sa11x0_register_lcd(&pal_video);
349#endif
268 sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources, 350 sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
269 ARRAY_SIZE(assabet_flash_resources)); 351 ARRAY_SIZE(assabet_flash_resources));
270 sa11x0_register_irda(&assabet_irda_data); 352 sa11x0_register_irda(&assabet_irda_data);
@@ -428,21 +510,8 @@ static void __init assabet_map_io(void)
428 */ 510 */
429 Ser1SDCR0 |= SDCR0_SUS; 511 Ser1SDCR0 |= SDCR0_SUS;
430 512
431 if (machine_has_neponset()) { 513 if (!machine_has_neponset())
432#ifdef CONFIG_ASSABET_NEPONSET
433 extern void neponset_map_io(void);
434
435 /*
436 * We map Neponset registers even if it isn't present since
437 * many drivers will try to probe their stuff (and fail).
438 * This is still more friendly than a kernel paging request
439 * crash.
440 */
441 neponset_map_io();
442#endif
443 } else {
444 sa1100_register_uart_fns(&assabet_port_fns); 514 sa1100_register_uart_fns(&assabet_port_fns);
445 }
446 515
447 /* 516 /*
448 * When Neponset is attached, the first UART should be 517 * When Neponset is attached, the first UART should be
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b07a2c024cb..5839c9d8bb9 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -39,20 +39,28 @@
39#include "generic.h" 39#include "generic.h"
40 40
41static struct resource sa1111_resources[] = { 41static struct resource sa1111_resources[] = {
42 [0] = { 42 [0] = DEFINE_RES_MEM(BADGE4_SA1111_BASE, 0x2000),
43 .start = BADGE4_SA1111_BASE, 43 [1] = DEFINE_RES_IRQ(BADGE4_IRQ_GPIO_SA1111),
44 .end = BADGE4_SA1111_BASE + 0x00001fff,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = BADGE4_IRQ_GPIO_SA1111,
49 .end = BADGE4_IRQ_GPIO_SA1111,
50 .flags = IORESOURCE_IRQ,
51 },
52}; 44};
53 45
46static int badge4_sa1111_enable(void *data, unsigned devid)
47{
48 if (devid == SA1111_DEVID_USB)
49 badge4_set_5V(BADGE4_5V_USB, 1);
50 return 0;
51}
52
53static void badge4_sa1111_disable(void *data, unsigned devid)
54{
55 if (devid == SA1111_DEVID_USB)
56 badge4_set_5V(BADGE4_5V_USB, 0);
57}
58
54static struct sa1111_platform_data sa1111_info = { 59static struct sa1111_platform_data sa1111_info = {
55 .irq_base = IRQ_BOARD_END, 60 .irq_base = IRQ_BOARD_END,
61 .disable_devs = SA1111_DEVID_PS2_MSE,
62 .enable = badge4_sa1111_enable,
63 .disable = badge4_sa1111_disable,
56}; 64};
57 65
58static u64 sa1111_dmamask = 0xffffffffUL; 66static u64 sa1111_dmamask = 0xffffffffUL;
@@ -121,11 +129,8 @@ static struct flash_platform_data badge4_flash_data = {
121 .nr_parts = ARRAY_SIZE(badge4_partitions), 129 .nr_parts = ARRAY_SIZE(badge4_partitions),
122}; 130};
123 131
124static struct resource badge4_flash_resource = { 132static struct resource badge4_flash_resource =
125 .start = SA1100_CS0_PHYS, 133 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_64M);
126 .end = SA1100_CS0_PHYS + SZ_64M - 1,
127 .flags = IORESOURCE_MEM,
128};
129 134
130static int five_v_on __initdata = 0; 135static int five_v_on __initdata = 0;
131 136
@@ -269,11 +274,6 @@ static struct map_desc badge4_io_desc[] __initdata = {
269 .pfn = __phys_to_pfn(0x10000000), 274 .pfn = __phys_to_pfn(0x10000000),
270 .length = 0x00100000, 275 .length = 0x00100000,
271 .type = MT_DEVICE 276 .type = MT_DEVICE
272 }, { /* SA-1111 */
273 .virtual = 0xf4000000,
274 .pfn = __phys_to_pfn(0x48000000),
275 .length = 0x00100000,
276 .type = MT_DEVICE
277 } 277 }
278}; 278};
279 279
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index bc11879f80c..8015604cfc2 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -33,11 +33,7 @@
33#include "generic.h" 33#include "generic.h"
34 34
35static struct resource cerfuart2_resources[] = { 35static struct resource cerfuart2_resources[] = {
36 [0] = { 36 [0] = DEFINE_RES_MEM(0x80030000, SZ_64K),
37 .start = 0x80030000,
38 .end = 0x8003ffff,
39 .flags = IORESOURCE_MEM,
40 },
41}; 37};
42 38
43static struct platform_device cerfuart2_device = { 39static struct platform_device cerfuart2_device = {
@@ -87,11 +83,8 @@ static struct flash_platform_data cerf_flash_data = {
87 .nr_parts = ARRAY_SIZE(cerf_partitions), 83 .nr_parts = ARRAY_SIZE(cerf_partitions),
88}; 84};
89 85
90static struct resource cerf_flash_resource = { 86static struct resource cerf_flash_resource =
91 .start = SA1100_CS0_PHYS, 87 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
92 .end = SA1100_CS0_PHYS + SZ_32M - 1,
93 .flags = IORESOURCE_MEM,
94};
95 88
96static void __init cerf_init_irq(void) 89static void __init cerf_init_irq(void)
97{ 90{
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index d6df9f6c9f7..dab3c6347a8 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,39 +11,17 @@
11#include <linux/clk.h> 11#include <linux/clk.h>
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <linux/mutex.h> 13#include <linux/mutex.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
16 14
17#include <mach/hardware.h> 15#include <mach/hardware.h>
18 16
19struct clkops { 17/*
20 void (*enable)(struct clk *); 18 * Very simple clock implementation - we only have one clock to deal with.
21 void (*disable)(struct clk *); 19 */
22 unsigned long (*getrate)(struct clk *);
23};
24
25struct clk { 20struct clk {
26 const struct clkops *ops;
27 unsigned long rate;
28 unsigned int enabled; 21 unsigned int enabled;
29}; 22};
30 23
31#define INIT_CLKREG(_clk, _devname, _conname) \ 24static void clk_gpio27_enable(void)
32 { \
33 .clk = _clk, \
34 .dev_id = _devname, \
35 .con_id = _conname, \
36 }
37
38#define DEFINE_CLK(_name, _ops, _rate) \
39struct clk clk_##_name = { \
40 .ops = _ops, \
41 .rate = _rate, \
42 }
43
44static DEFINE_SPINLOCK(clocks_lock);
45
46static void clk_gpio27_enable(struct clk *clk)
47{ 25{
48 /* 26 /*
49 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: 27 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -54,22 +32,38 @@ static void clk_gpio27_enable(struct clk *clk)
54 TUCR = TUCR_3_6864MHz; 32 TUCR = TUCR_3_6864MHz;
55} 33}
56 34
57static void clk_gpio27_disable(struct clk *clk) 35static void clk_gpio27_disable(void)
58{ 36{
59 TUCR = 0; 37 TUCR = 0;
60 GPDR &= ~GPIO_32_768kHz; 38 GPDR &= ~GPIO_32_768kHz;
61 GAFR &= ~GPIO_32_768kHz; 39 GAFR &= ~GPIO_32_768kHz;
62} 40}
63 41
42static struct clk clk_gpio27;
43
44static DEFINE_SPINLOCK(clocks_lock);
45
46struct clk *clk_get(struct device *dev, const char *id)
47{
48 const char *devname = dev_name(dev);
49
50 return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
51}
52EXPORT_SYMBOL(clk_get);
53
54void clk_put(struct clk *clk)
55{
56}
57EXPORT_SYMBOL(clk_put);
58
64int clk_enable(struct clk *clk) 59int clk_enable(struct clk *clk)
65{ 60{
66 unsigned long flags; 61 unsigned long flags;
67 62
68 spin_lock_irqsave(&clocks_lock, flags); 63 spin_lock_irqsave(&clocks_lock, flags);
69 if (clk->enabled++ == 0) 64 if (clk->enabled++ == 0)
70 clk->ops->enable(clk); 65 clk_gpio27_enable();
71 spin_unlock_irqrestore(&clocks_lock, flags); 66 spin_unlock_irqrestore(&clocks_lock, flags);
72
73 return 0; 67 return 0;
74} 68}
75EXPORT_SYMBOL(clk_enable); 69EXPORT_SYMBOL(clk_enable);
@@ -82,48 +76,13 @@ void clk_disable(struct clk *clk)
82 76
83 spin_lock_irqsave(&clocks_lock, flags); 77 spin_lock_irqsave(&clocks_lock, flags);
84 if (--clk->enabled == 0) 78 if (--clk->enabled == 0)
85 clk->ops->disable(clk); 79 clk_gpio27_disable();
86 spin_unlock_irqrestore(&clocks_lock, flags); 80 spin_unlock_irqrestore(&clocks_lock, flags);
87} 81}
88EXPORT_SYMBOL(clk_disable); 82EXPORT_SYMBOL(clk_disable);
89 83
90unsigned long clk_get_rate(struct clk *clk) 84unsigned long clk_get_rate(struct clk *clk)
91{ 85{
92 unsigned long rate; 86 return 3686400;
93
94 rate = clk->rate;
95 if (clk->ops->getrate)
96 rate = clk->ops->getrate(clk);
97
98 return rate;
99} 87}
100EXPORT_SYMBOL(clk_get_rate); 88EXPORT_SYMBOL(clk_get_rate);
101
102const struct clkops clk_gpio27_ops = {
103 .enable = clk_gpio27_enable,
104 .disable = clk_gpio27_disable,
105};
106
107static void clk_dummy_enable(struct clk *clk) { }
108static void clk_dummy_disable(struct clk *clk) { }
109
110const struct clkops clk_dummy_ops = {
111 .enable = clk_dummy_enable,
112 .disable = clk_dummy_disable,
113};
114
115static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400);
116static DEFINE_CLK(dummy, &clk_dummy_ops, 0);
117
118static struct clk_lookup sa11xx_clkregs[] = {
119 INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL),
120 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
121};
122
123static int __init sa11xx_clk_init(void)
124{
125 clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
126 return 0;
127}
128
129postcore_initcall(sa11xx_clk_init);
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 0e735978515..d4339d63947 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -29,6 +29,8 @@
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/pda_power.h> 30#include <linux/pda_power.h>
31 31
32#include <video/sa1100fb.h>
33
32#include <mach/hardware.h> 34#include <mach/hardware.h>
33#include <asm/mach-types.h> 35#include <asm/mach-types.h>
34#include <asm/irq.h> 36#include <asm/irq.h>
@@ -49,11 +51,7 @@
49#include "generic.h" 51#include "generic.h"
50 52
51static struct resource collie_scoop_resources[] = { 53static struct resource collie_scoop_resources[] = {
52 [0] = { 54 [0] = DEFINE_RES_MEM(0x40800000, SZ_4K),
53 .start = 0x40800000,
54 .end = 0x40800fff,
55 .flags = IORESOURCE_MEM,
56 },
57}; 55};
58 56
59static struct scoop_config collie_scoop_setup = { 57static struct scoop_config collie_scoop_setup = {
@@ -143,8 +141,6 @@ static struct pda_power_pdata collie_power_data = {
143static struct resource collie_power_resource[] = { 141static struct resource collie_power_resource[] = {
144 { 142 {
145 .name = "ac", 143 .name = "ac",
146 .start = gpio_to_irq(COLLIE_GPIO_AC_IN),
147 .end = gpio_to_irq(COLLIE_GPIO_AC_IN),
148 .flags = IORESOURCE_IRQ | 144 .flags = IORESOURCE_IRQ |
149 IORESOURCE_IRQ_HIGHEDGE | 145 IORESOURCE_IRQ_HIGHEDGE |
150 IORESOURCE_IRQ_LOWEDGE, 146 IORESOURCE_IRQ_LOWEDGE,
@@ -228,16 +224,8 @@ device_initcall(collie_uart_init);
228 224
229 225
230static struct resource locomo_resources[] = { 226static struct resource locomo_resources[] = {
231 [0] = { 227 [0] = DEFINE_RES_MEM(0x40000000, SZ_8K),
232 .start = 0x40000000, 228 [1] = DEFINE_RES_IRQ(IRQ_GPIO25),
233 .end = 0x40001fff,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = IRQ_GPIO25,
238 .end = IRQ_GPIO25,
239 .flags = IORESOURCE_IRQ,
240 },
241}; 229};
242 230
243static struct locomo_platform_data locomo_info = { 231static struct locomo_platform_data locomo_info = {
@@ -310,11 +298,21 @@ static struct flash_platform_data collie_flash_data = {
310}; 298};
311 299
312static struct resource collie_flash_resources[] = { 300static struct resource collie_flash_resources[] = {
313 { 301 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
314 .start = SA1100_CS0_PHYS, 302};
315 .end = SA1100_CS0_PHYS + SZ_32M - 1, 303
316 .flags = IORESOURCE_MEM, 304static struct sa1100fb_mach_info collie_lcd_info = {
317 } 305 .pixclock = 171521, .bpp = 16,
306 .xres = 320, .yres = 240,
307
308 .hsync_len = 5, .vsync_len = 1,
309 .left_margin = 11, .upper_margin = 2,
310 .right_margin = 30, .lower_margin = 0,
311
312 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
313
314 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
315 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
318}; 316};
319 317
320static void __init collie_init(void) 318static void __init collie_init(void)
@@ -346,6 +344,9 @@ static void __init collie_init(void)
346 344
347 GPSR |= _COLLIE_GPIO_UCB1x00_RESET; 345 GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
348 346
347 collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
348 collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
349
349 sa11x0_ppc_configure_mcp(); 350 sa11x0_ppc_configure_mcp();
350 351
351 352
@@ -356,6 +357,7 @@ static void __init collie_init(void)
356 printk(KERN_WARNING "collie: Unable to register LoCoMo device\n"); 357 printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
357 } 358 }
358 359
360 sa11x0_register_lcd(&collie_lcd_info);
359 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, 361 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
360 ARRAY_SIZE(collie_flash_resources)); 362 ARRAY_SIZE(collie_flash_resources));
361 sa11x0_register_mcp(&collie_mcp_data); 363 sa11x0_register_mcp(&collie_mcp_data);
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index aaa8acf76b7..19b2053f5af 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -228,7 +228,7 @@ static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
228 return 0; 228 return 0;
229} 229}
230 230
231static struct cpufreq_driver sa1100_driver = { 231static struct cpufreq_driver sa1100_driver __refdata = {
232 .flags = CPUFREQ_STICKY, 232 .flags = CPUFREQ_STICKY,
233 .verify = sa11x0_verify_speed, 233 .verify = sa11x0_verify_speed,
234 .target = sa1100_target, 234 .target = sa1100_target,
diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c
deleted file mode 100644
index ad660350c29..00000000000
--- a/arch/arm/mach-sa1100/dma.c
+++ /dev/null
@@ -1,348 +0,0 @@
1/*
2 * arch/arm/mach-sa1100/dma.c
3 *
4 * Support functions for the SA11x0 internal DMA channels.
5 *
6 * Copyright (C) 2000, 2001 by Nicolas Pitre
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/init.h>
16#include <linux/spinlock.h>
17#include <linux/errno.h>
18
19#include <asm/system.h>
20#include <asm/irq.h>
21#include <mach/hardware.h>
22#include <mach/dma.h>
23
24
25#undef DEBUG
26#ifdef DEBUG
27#define DPRINTK( s, arg... ) printk( "dma<%p>: " s, regs , ##arg )
28#else
29#define DPRINTK( x... )
30#endif
31
32
33typedef struct {
34 const char *device_id; /* device name */
35 u_long device; /* this channel device, 0 if unused*/
36 dma_callback_t callback; /* to call when DMA completes */
37 void *data; /* ... with private data ptr */
38} sa1100_dma_t;
39
40static sa1100_dma_t dma_chan[SA1100_DMA_CHANNELS];
41
42static DEFINE_SPINLOCK(dma_list_lock);
43
44
45static irqreturn_t dma_irq_handler(int irq, void *dev_id)
46{
47 dma_regs_t *dma_regs = dev_id;
48 sa1100_dma_t *dma = dma_chan + (((u_int)dma_regs >> 5) & 7);
49 int status = dma_regs->RdDCSR;
50
51 if (status & (DCSR_ERROR)) {
52 printk(KERN_CRIT "DMA on \"%s\" caused an error\n", dma->device_id);
53 dma_regs->ClrDCSR = DCSR_ERROR;
54 }
55
56 dma_regs->ClrDCSR = status & (DCSR_DONEA | DCSR_DONEB);
57 if (dma->callback) {
58 if (status & DCSR_DONEA)
59 dma->callback(dma->data);
60 if (status & DCSR_DONEB)
61 dma->callback(dma->data);
62 }
63 return IRQ_HANDLED;
64}
65
66
67/**
68 * sa1100_request_dma - allocate one of the SA11x0's DMA channels
69 * @device: The SA11x0 peripheral targeted by this request
70 * @device_id: An ascii name for the claiming device
71 * @callback: Function to be called when the DMA completes
72 * @data: A cookie passed back to the callback function
73 * @dma_regs: Pointer to the location of the allocated channel's identifier
74 *
75 * This function will search for a free DMA channel and returns the
76 * address of the hardware registers for that channel as the channel
77 * identifier. This identifier is written to the location pointed by
78 * @dma_regs. The list of possible values for @device are listed into
79 * arch/arm/mach-sa1100/include/mach/dma.h as a dma_device_t enum.
80 *
81 * Note that reading from a port and writing to the same port are
82 * actually considered as two different streams requiring separate
83 * DMA registrations.
84 *
85 * The @callback function is called from interrupt context when one
86 * of the two possible DMA buffers in flight has terminated. That
87 * function has to be small and efficient while posponing more complex
88 * processing to a lower priority execution context.
89 *
90 * If no channels are available, or if the desired @device is already in
91 * use by another DMA channel, then an error code is returned. This
92 * function must be called before any other DMA calls.
93 **/
94
95int sa1100_request_dma (dma_device_t device, const char *device_id,
96 dma_callback_t callback, void *data,
97 dma_regs_t **dma_regs)
98{
99 sa1100_dma_t *dma = NULL;
100 dma_regs_t *regs;
101 int i, err;
102
103 *dma_regs = NULL;
104
105 err = 0;
106 spin_lock(&dma_list_lock);
107 for (i = 0; i < SA1100_DMA_CHANNELS; i++) {
108 if (dma_chan[i].device == device) {
109 err = -EBUSY;
110 break;
111 } else if (!dma_chan[i].device && !dma) {
112 dma = &dma_chan[i];
113 }
114 }
115 if (!err) {
116 if (dma)
117 dma->device = device;
118 else
119 err = -ENOSR;
120 }
121 spin_unlock(&dma_list_lock);
122 if (err)
123 return err;
124
125 i = dma - dma_chan;
126 regs = (dma_regs_t *)&DDAR(i);
127 err = request_irq(IRQ_DMA0 + i, dma_irq_handler, IRQF_DISABLED,
128 device_id, regs);
129 if (err) {
130 printk(KERN_ERR
131 "%s: unable to request IRQ %d for %s\n",
132 __func__, IRQ_DMA0 + i, device_id);
133 dma->device = 0;
134 return err;
135 }
136
137 *dma_regs = regs;
138 dma->device_id = device_id;
139 dma->callback = callback;
140 dma->data = data;
141
142 regs->ClrDCSR =
143 (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
144 DCSR_IE | DCSR_ERROR | DCSR_RUN);
145 regs->DDAR = device;
146
147 return 0;
148}
149
150
151/**
152 * sa1100_free_dma - free a SA11x0 DMA channel
153 * @regs: identifier for the channel to free
154 *
155 * This clears all activities on a given DMA channel and releases it
156 * for future requests. The @regs identifier is provided by a
157 * successful call to sa1100_request_dma().
158 **/
159
160void sa1100_free_dma(dma_regs_t *regs)
161{
162 int i;
163
164 for (i = 0; i < SA1100_DMA_CHANNELS; i++)
165 if (regs == (dma_regs_t *)&DDAR(i))
166 break;
167 if (i >= SA1100_DMA_CHANNELS) {
168 printk(KERN_ERR "%s: bad DMA identifier\n", __func__);
169 return;
170 }
171
172 if (!dma_chan[i].device) {
173 printk(KERN_ERR "%s: Trying to free free DMA\n", __func__);
174 return;
175 }
176
177 regs->ClrDCSR =
178 (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
179 DCSR_IE | DCSR_ERROR | DCSR_RUN);
180 free_irq(IRQ_DMA0 + i, regs);
181 dma_chan[i].device = 0;
182}
183
184
185/**
186 * sa1100_start_dma - submit a data buffer for DMA
187 * @regs: identifier for the channel to use
188 * @dma_ptr: buffer physical (or bus) start address
189 * @size: buffer size
190 *
191 * This function hands the given data buffer to the hardware for DMA
192 * access. If another buffer is already in flight then this buffer
193 * will be queued so the DMA engine will switch to it automatically
194 * when the previous one is done. The DMA engine is actually toggling
195 * between two buffers so at most 2 successful calls can be made before
196 * one of them terminates and the callback function is called.
197 *
198 * The @regs identifier is provided by a successful call to
199 * sa1100_request_dma().
200 *
201 * The @size must not be larger than %MAX_DMA_SIZE. If a given buffer
202 * is larger than that then it's the caller's responsibility to split
203 * it into smaller chunks and submit them separately. If this is the
204 * case then a @size of %CUT_DMA_SIZE is recommended to avoid ending
205 * up with too small chunks. The callback function can be used to chain
206 * submissions of buffer chunks.
207 *
208 * Error return values:
209 * %-EOVERFLOW: Given buffer size is too big.
210 * %-EBUSY: Both DMA buffers are already in use.
211 * %-EAGAIN: Both buffers were busy but one of them just completed
212 * but the interrupt handler has to execute first.
213 *
214 * This function returs 0 on success.
215 **/
216
217int sa1100_start_dma(dma_regs_t *regs, dma_addr_t dma_ptr, u_int size)
218{
219 unsigned long flags;
220 u_long status;
221 int ret;
222
223 if (dma_ptr & 3)
224 printk(KERN_WARNING "DMA: unaligned start address (0x%08lx)\n",
225 (unsigned long)dma_ptr);
226
227 if (size > MAX_DMA_SIZE)
228 return -EOVERFLOW;
229
230 local_irq_save(flags);
231 status = regs->RdDCSR;
232
233 /* If both DMA buffers are started, there's nothing else we can do. */
234 if ((status & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB)) {
235 DPRINTK("start: st %#x busy\n", status);
236 ret = -EBUSY;
237 goto out;
238 }
239
240 if (((status & DCSR_BIU) && (status & DCSR_STRTB)) ||
241 (!(status & DCSR_BIU) && !(status & DCSR_STRTA))) {
242 if (status & DCSR_DONEA) {
243 /* give a chance for the interrupt to be processed */
244 ret = -EAGAIN;
245 goto out;
246 }
247 regs->DBSA = dma_ptr;
248 regs->DBTA = size;
249 regs->SetDCSR = DCSR_STRTA | DCSR_IE | DCSR_RUN;
250 DPRINTK("start a=%#x s=%d on A\n", dma_ptr, size);
251 } else {
252 if (status & DCSR_DONEB) {
253 /* give a chance for the interrupt to be processed */
254 ret = -EAGAIN;
255 goto out;
256 }
257 regs->DBSB = dma_ptr;
258 regs->DBTB = size;
259 regs->SetDCSR = DCSR_STRTB | DCSR_IE | DCSR_RUN;
260 DPRINTK("start a=%#x s=%d on B\n", dma_ptr, size);
261 }
262 ret = 0;
263
264out:
265 local_irq_restore(flags);
266 return ret;
267}
268
269
270/**
271 * sa1100_get_dma_pos - return current DMA position
272 * @regs: identifier for the channel to use
273 *
274 * This function returns the current physical (or bus) address for the
275 * given DMA channel. If the channel is running i.e. not in a stopped
276 * state then the caller must disable interrupts prior calling this
277 * function and process the returned value before re-enabling them to
278 * prevent races with the completion interrupt handler and the callback
279 * function. The validation of the returned value is the caller's
280 * responsibility as well -- the hardware seems to return out of range
281 * values when the DMA engine completes a buffer.
282 *
283 * The @regs identifier is provided by a successful call to
284 * sa1100_request_dma().
285 **/
286
287dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs)
288{
289 int status;
290
291 /*
292 * We must determine whether buffer A or B is active.
293 * Two possibilities: either we are in the middle of
294 * a buffer, or the DMA controller just switched to the
295 * next toggle but the interrupt hasn't been serviced yet.
296 * The former case is straight forward. In the later case,
297 * we'll do like if DMA is just at the end of the previous
298 * toggle since all registers haven't been reset yet.
299 * This goes around the edge case and since we're always
300 * a little behind anyways it shouldn't make a big difference.
301 * If DMA has been stopped prior calling this then the
302 * position is exact.
303 */
304 status = regs->RdDCSR;
305 if ((!(status & DCSR_BIU) && (status & DCSR_STRTA)) ||
306 ( (status & DCSR_BIU) && !(status & DCSR_STRTB)))
307 return regs->DBSA;
308 else
309 return regs->DBSB;
310}
311
312
313/**
314 * sa1100_reset_dma - reset a DMA channel
315 * @regs: identifier for the channel to use
316 *
317 * This function resets and reconfigure the given DMA channel. This is
318 * particularly useful after a sleep/wakeup event.
319 *
320 * The @regs identifier is provided by a successful call to
321 * sa1100_request_dma().
322 **/
323
324void sa1100_reset_dma(dma_regs_t *regs)
325{
326 int i;
327
328 for (i = 0; i < SA1100_DMA_CHANNELS; i++)
329 if (regs == (dma_regs_t *)&DDAR(i))
330 break;
331 if (i >= SA1100_DMA_CHANNELS) {
332 printk(KERN_ERR "%s: bad DMA identifier\n", __func__);
333 return;
334 }
335
336 regs->ClrDCSR =
337 (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB |
338 DCSR_IE | DCSR_ERROR | DCSR_RUN);
339 regs->DDAR = dma_chan[i].device;
340}
341
342
343EXPORT_SYMBOL(sa1100_request_dma);
344EXPORT_SYMBOL(sa1100_free_dma);
345EXPORT_SYMBOL(sa1100_start_dma);
346EXPORT_SYMBOL(sa1100_get_dma_pos);
347EXPORT_SYMBOL(sa1100_reset_dma);
348
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9379c53d301..97e9bdf7f29 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -14,11 +14,14 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/delay.h> 16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
17#include <linux/pm.h> 18#include <linux/pm.h>
18#include <linux/cpufreq.h> 19#include <linux/cpufreq.h>
19#include <linux/ioport.h> 20#include <linux/ioport.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
21 22
23#include <video/sa1100fb.h>
24
22#include <asm/div64.h> 25#include <asm/div64.h>
23#include <mach/hardware.h> 26#include <mach/hardware.h>
24#include <asm/system.h> 27#include <asm/system.h>
@@ -149,16 +152,8 @@ static void sa11x0_register_device(struct platform_device *dev, void *data)
149 152
150 153
151static struct resource sa11x0udc_resources[] = { 154static struct resource sa11x0udc_resources[] = {
152 [0] = { 155 [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
153 .start = __PREG(Ser0UDCCR), 156 [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
154 .end = __PREG(Ser0UDCCR) + 0xffff,
155 .flags = IORESOURCE_MEM,
156 },
157 [1] = {
158 .start = IRQ_Ser0UDC,
159 .end = IRQ_Ser0UDC,
160 .flags = IORESOURCE_IRQ,
161 },
162}; 157};
163 158
164static u64 sa11x0udc_dma_mask = 0xffffffffUL; 159static u64 sa11x0udc_dma_mask = 0xffffffffUL;
@@ -175,16 +170,8 @@ static struct platform_device sa11x0udc_device = {
175}; 170};
176 171
177static struct resource sa11x0uart1_resources[] = { 172static struct resource sa11x0uart1_resources[] = {
178 [0] = { 173 [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
179 .start = __PREG(Ser1UTCR0), 174 [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
180 .end = __PREG(Ser1UTCR0) + 0xffff,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = IRQ_Ser1UART,
185 .end = IRQ_Ser1UART,
186 .flags = IORESOURCE_IRQ,
187 },
188}; 175};
189 176
190static struct platform_device sa11x0uart1_device = { 177static struct platform_device sa11x0uart1_device = {
@@ -195,16 +182,8 @@ static struct platform_device sa11x0uart1_device = {
195}; 182};
196 183
197static struct resource sa11x0uart3_resources[] = { 184static struct resource sa11x0uart3_resources[] = {
198 [0] = { 185 [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
199 .start = __PREG(Ser3UTCR0), 186 [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
200 .end = __PREG(Ser3UTCR0) + 0xffff,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = IRQ_Ser3UART,
205 .end = IRQ_Ser3UART,
206 .flags = IORESOURCE_IRQ,
207 },
208}; 187};
209 188
210static struct platform_device sa11x0uart3_device = { 189static struct platform_device sa11x0uart3_device = {
@@ -215,21 +194,9 @@ static struct platform_device sa11x0uart3_device = {
215}; 194};
216 195
217static struct resource sa11x0mcp_resources[] = { 196static struct resource sa11x0mcp_resources[] = {
218 [0] = { 197 [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
219 .start = __PREG(Ser4MCCR0), 198 [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
220 .end = __PREG(Ser4MCCR0) + 0xffff, 199 [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = __PREG(Ser4MCCR1),
225 .end = __PREG(Ser4MCCR1) + 4 - 1,
226 .flags = IORESOURCE_MEM,
227 },
228 [2] = {
229 .start = IRQ_Ser4MCP,
230 .end = IRQ_Ser4MCP,
231 .flags = IORESOURCE_IRQ,
232 },
233}; 200};
234 201
235static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 202static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
@@ -261,16 +228,8 @@ void sa11x0_register_mcp(struct mcp_plat_data *data)
261} 228}
262 229
263static struct resource sa11x0ssp_resources[] = { 230static struct resource sa11x0ssp_resources[] = {
264 [0] = { 231 [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
265 .start = 0x80070000, 232 [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
266 .end = 0x8007ffff,
267 .flags = IORESOURCE_MEM,
268 },
269 [1] = {
270 .start = IRQ_Ser4SSP,
271 .end = IRQ_Ser4SSP,
272 .flags = IORESOURCE_IRQ,
273 },
274}; 233};
275 234
276static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 235static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
@@ -287,16 +246,8 @@ static struct platform_device sa11x0ssp_device = {
287}; 246};
288 247
289static struct resource sa11x0fb_resources[] = { 248static struct resource sa11x0fb_resources[] = {
290 [0] = { 249 [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
291 .start = 0xb0100000, 250 [1] = DEFINE_RES_IRQ(IRQ_LCD),
292 .end = 0xb010ffff,
293 .flags = IORESOURCE_MEM,
294 },
295 [1] = {
296 .start = IRQ_LCD,
297 .end = IRQ_LCD,
298 .flags = IORESOURCE_IRQ,
299 },
300}; 251};
301 252
302static struct platform_device sa11x0fb_device = { 253static struct platform_device sa11x0fb_device = {
@@ -309,6 +260,11 @@ static struct platform_device sa11x0fb_device = {
309 .resource = sa11x0fb_resources, 260 .resource = sa11x0fb_resources,
310}; 261};
311 262
263void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
264{
265 sa11x0_register_device(&sa11x0fb_device, inf);
266}
267
312static struct platform_device sa11x0pcmcia_device = { 268static struct platform_device sa11x0pcmcia_device = {
313 .name = "sa11x0-pcmcia", 269 .name = "sa11x0-pcmcia",
314 .id = -1, 270 .id = -1,
@@ -329,23 +285,10 @@ void sa11x0_register_mtd(struct flash_platform_data *flash,
329} 285}
330 286
331static struct resource sa11x0ir_resources[] = { 287static struct resource sa11x0ir_resources[] = {
332 { 288 DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
333 .start = __PREG(Ser2UTCR0), 289 DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
334 .end = __PREG(Ser2UTCR0) + 0x24 - 1, 290 DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
335 .flags = IORESOURCE_MEM, 291 DEFINE_RES_IRQ(IRQ_Ser2ICP),
336 }, {
337 .start = __PREG(Ser2HSCR0),
338 .end = __PREG(Ser2HSCR0) + 0x1c - 1,
339 .flags = IORESOURCE_MEM,
340 }, {
341 .start = __PREG(Ser2HSCR2),
342 .end = __PREG(Ser2HSCR2) + 0x04 - 1,
343 .flags = IORESOURCE_MEM,
344 }, {
345 .start = IRQ_Ser2ICP,
346 .end = IRQ_Ser2ICP,
347 .flags = IORESOURCE_IRQ,
348 }
349}; 292};
350 293
351static struct platform_device sa11x0ir_device = { 294static struct platform_device sa11x0ir_device = {
@@ -360,29 +303,32 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
360 sa11x0_register_device(&sa11x0ir_device, irda); 303 sa11x0_register_device(&sa11x0ir_device, irda);
361} 304}
362 305
363static struct resource sa11x0rtc_resources[] = {
364 [0] = {
365 .start = 0x90010000,
366 .end = 0x900100ff,
367 .flags = IORESOURCE_MEM,
368 },
369 [1] = {
370 .start = IRQ_RTC1Hz,
371 .end = IRQ_RTC1Hz,
372 .flags = IORESOURCE_IRQ,
373 },
374 [2] = {
375 .start = IRQ_RTCAlrm,
376 .end = IRQ_RTCAlrm,
377 .flags = IORESOURCE_IRQ,
378 },
379};
380
381static struct platform_device sa11x0rtc_device = { 306static struct platform_device sa11x0rtc_device = {
382 .name = "sa1100-rtc", 307 .name = "sa1100-rtc",
383 .id = -1, 308 .id = -1,
384 .resource = sa11x0rtc_resources, 309};
385 .num_resources = ARRAY_SIZE(sa11x0rtc_resources), 310
311static struct resource sa11x0dma_resources[] = {
312 DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
313 DEFINE_RES_IRQ(IRQ_DMA0),
314 DEFINE_RES_IRQ(IRQ_DMA1),
315 DEFINE_RES_IRQ(IRQ_DMA2),
316 DEFINE_RES_IRQ(IRQ_DMA3),
317 DEFINE_RES_IRQ(IRQ_DMA4),
318 DEFINE_RES_IRQ(IRQ_DMA5),
319};
320
321static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
322
323static struct platform_device sa11x0dma_device = {
324 .name = "sa11x0-dma",
325 .id = -1,
326 .dev = {
327 .dma_mask = &sa11x0dma_dma_mask,
328 .coherent_dma_mask = 0xffffffff,
329 },
330 .num_resources = ARRAY_SIZE(sa11x0dma_resources),
331 .resource = sa11x0dma_resources,
386}; 332};
387 333
388static struct platform_device *sa11x0_devices[] __initdata = { 334static struct platform_device *sa11x0_devices[] __initdata = {
@@ -391,8 +337,8 @@ static struct platform_device *sa11x0_devices[] __initdata = {
391 &sa11x0uart3_device, 337 &sa11x0uart3_device,
392 &sa11x0ssp_device, 338 &sa11x0ssp_device,
393 &sa11x0pcmcia_device, 339 &sa11x0pcmcia_device,
394 &sa11x0fb_device,
395 &sa11x0rtc_device, 340 &sa11x0rtc_device,
341 &sa11x0dma_device,
396}; 342};
397 343
398static int __init sa1100_init(void) 344static int __init sa1100_init(void)
@@ -403,12 +349,6 @@ static int __init sa1100_init(void)
403 349
404arch_initcall(sa1100_init); 350arch_initcall(sa1100_init);
405 351
406void (*sa1100fb_backlight_power)(int on);
407void (*sa1100fb_lcd_power)(int on);
408
409EXPORT_SYMBOL(sa1100fb_backlight_power);
410EXPORT_SYMBOL(sa1100fb_lcd_power);
411
412 352
413/* 353/*
414 * Common I/O mapping: 354 * Common I/O mapping:
@@ -463,7 +403,7 @@ void __init sa1100_map_io(void)
463 * the MBGNT signal false to ensure the SA1111 doesn't own the 403 * the MBGNT signal false to ensure the SA1111 doesn't own the
464 * SDRAM bus. 404 * SDRAM bus.
465 */ 405 */
466void __init sa1110_mb_disable(void) 406void sa1110_mb_disable(void)
467{ 407{
468 unsigned long flags; 408 unsigned long flags;
469 409
@@ -482,7 +422,7 @@ void __init sa1110_mb_disable(void)
482 * If the system is going to use the SA-1111 DMA engines, set up 422 * If the system is going to use the SA-1111 DMA engines, set up
483 * the memory bus request/grant pins. 423 * the memory bus request/grant pins.
484 */ 424 */
485void __devinit sa1110_mb_enable(void) 425void sa1110_mb_enable(void)
486{ 426{
487 unsigned long flags; 427 unsigned long flags;
488 428
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index 9236ff42bd1..9eb3b3cd5a6 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -16,9 +16,6 @@ extern void sa11x0_restart(char, const char *);
16 mi->bank[__nr].start = (__start), \ 16 mi->bank[__nr].start = (__start), \
17 mi->bank[__nr].size = (__size) 17 mi->bank[__nr].size = (__size)
18 18
19extern void (*sa1100fb_backlight_power)(int on);
20extern void (*sa1100fb_lcd_power)(int on);
21
22extern void sa1110_mb_enable(void); 19extern void sa1110_mb_enable(void);
23extern void sa1110_mb_disable(void); 20extern void sa1110_mb_disable(void);
24 21
@@ -41,3 +38,6 @@ void sa11x0_register_irda(struct irda_platform_data *irda);
41struct mcp_plat_data; 38struct mcp_plat_data;
42void sa11x0_ppc_configure_mcp(void); 39void sa11x0_ppc_configure_mcp(void);
43void sa11x0_register_mcp(struct mcp_plat_data *data); 40void sa11x0_register_mcp(struct mcp_plat_data *data);
41
42struct sa1100fb_mach_info;
43void sa11x0_register_lcd(struct sa1100fb_mach_info *inf);
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index 1e6b3c105ba..f23e7d0b2fb 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -14,6 +14,8 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16 16
17#include <video/sa1100fb.h>
18
17#include <asm/mach-types.h> 19#include <asm/mach-types.h>
18#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
19#include <asm/mach/irda.h> 21#include <asm/mach/irda.h>
@@ -36,13 +38,28 @@ static void h3100_lcd_power(int enable)
36 } 38 }
37} 39}
38 40
41static struct sa1100fb_mach_info h3100_lcd_info = {
42 .pixclock = 406977, .bpp = 4,
43 .xres = 320, .yres = 240,
44
45 .hsync_len = 26, .vsync_len = 41,
46 .left_margin = 4, .upper_margin = 0,
47 .right_margin = 4, .lower_margin = 0,
48
49 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
50 .cmap_greyscale = 1,
51 .cmap_inverse = 1,
52
53 .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
54 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
55
56 .lcd_power = h3100_lcd_power,
57};
39 58
40static void __init h3100_map_io(void) 59static void __init h3100_map_io(void)
41{ 60{
42 h3xxx_map_io(); 61 h3xxx_map_io();
43 62
44 sa1100fb_lcd_power = h3100_lcd_power;
45
46 /* Older bootldrs put GPIO2-9 in alternate mode on the 63 /* Older bootldrs put GPIO2-9 in alternate mode on the
47 assumption that they are used for video */ 64 assumption that they are used for video */
48 GAFR &= ~0x000001fb; 65 GAFR &= ~0x000001fb;
@@ -80,6 +97,8 @@ static void __init h3100_mach_init(void)
80{ 97{
81 h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio)); 98 h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio));
82 h3xxx_mach_init(); 99 h3xxx_mach_init();
100
101 sa11x0_register_lcd(&h3100_lcd_info);
83 sa11x0_register_irda(&h3100_irda_data); 102 sa11x0_register_irda(&h3100_irda_data);
84} 103}
85 104
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 6b58e7460ec..2feac56ec90 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -14,6 +14,8 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16 16
17#include <video/sa1100fb.h>
18
17#include <asm/mach-types.h> 19#include <asm/mach-types.h>
18#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
19#include <asm/mach/irda.h> 21#include <asm/mach/irda.h>
@@ -56,11 +58,35 @@ err2: gpio_free(H3XXX_EGPIO_LCD_ON);
56err1: return; 58err1: return;
57} 59}
58 60
61static const struct sa1100fb_rgb h3600_rgb_16 = {
62 .red = { .offset = 12, .length = 4, },
63 .green = { .offset = 7, .length = 4, },
64 .blue = { .offset = 1, .length = 4, },
65 .transp = { .offset = 0, .length = 0, },
66};
67
68static struct sa1100fb_mach_info h3600_lcd_info = {
69 .pixclock = 174757, .bpp = 16,
70 .xres = 320, .yres = 240,
71
72 .hsync_len = 3, .vsync_len = 3,
73 .left_margin = 12, .upper_margin = 10,
74 .right_margin = 17, .lower_margin = 1,
75
76 .cmap_static = 1,
77
78 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
79 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
80
81 .rgb[RGB_16] = &h3600_rgb_16,
82
83 .lcd_power = h3600_lcd_power,
84};
85
86
59static void __init h3600_map_io(void) 87static void __init h3600_map_io(void)
60{ 88{
61 h3xxx_map_io(); 89 h3xxx_map_io();
62
63 sa1100fb_lcd_power = h3600_lcd_power;
64} 90}
65 91
66/* 92/*
@@ -121,6 +147,8 @@ static void __init h3600_mach_init(void)
121{ 147{
122 h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio)); 148 h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio));
123 h3xxx_mach_init(); 149 h3xxx_mach_init();
150
151 sa11x0_register_lcd(&h3600_lcd_info);
124 sa11x0_register_irda(&h3600_irda_data); 152 sa11x0_register_irda(&h3600_irda_data);
125} 153}
126 154
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index b0784c974c2..63150e1ffe9 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -109,11 +109,8 @@ static struct flash_platform_data h3xxx_flash_data = {
109 .nr_parts = ARRAY_SIZE(h3xxx_partitions), 109 .nr_parts = ARRAY_SIZE(h3xxx_partitions),
110}; 110};
111 111
112static struct resource h3xxx_flash_resource = { 112static struct resource h3xxx_flash_resource =
113 .start = SA1100_CS0_PHYS, 113 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
114 .end = SA1100_CS0_PHYS + SZ_32M - 1,
115 .flags = IORESOURCE_MEM,
116};
117 114
118 115
119/* 116/*
@@ -186,11 +183,7 @@ static struct sa1100_port_fns h3xxx_port_fns __initdata = {
186 */ 183 */
187 184
188static struct resource egpio_resources[] = { 185static struct resource egpio_resources[] = {
189 [0] = { 186 [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4),
190 .start = H3600_EGPIO_PHYS,
191 .end = H3600_EGPIO_PHYS + 0x4 - 1,
192 .flags = IORESOURCE_MEM,
193 },
194}; 187};
195 188
196static struct htc_egpio_chip egpio_chips[] = { 189static struct htc_egpio_chip egpio_chips[] = {
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index c01bb36db94..37d381ad546 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -179,11 +179,8 @@ static struct flash_platform_data hackkit_flash_data = {
179 .nr_parts = ARRAY_SIZE(hackkit_partitions), 179 .nr_parts = ARRAY_SIZE(hackkit_partitions),
180}; 180};
181 181
182static struct resource hackkit_flash_resource = { 182static struct resource hackkit_flash_resource =
183 .start = SA1100_CS0_PHYS, 183 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
184 .end = SA1100_CS0_PHYS + SZ_32M,
185 .flags = IORESOURCE_MEM,
186};
187 184
188static void __init hackkit_init(void) 185static void __init hackkit_init(void)
189{ 186{
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index bae8296f5db..3f2d1b60188 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -1590,224 +1590,9 @@
1590 1590
1591/* 1591/*
1592 * Direct Memory Access (DMA) control registers 1592 * Direct Memory Access (DMA) control registers
1593 *
1594 * Registers
1595 * DDAR0 Direct Memory Access (DMA) Device Address Register
1596 * channel 0 (read/write).
1597 * DCSR0 Direct Memory Access (DMA) Control and Status
1598 * Register channel 0 (read/write).
1599 * DBSA0 Direct Memory Access (DMA) Buffer Start address
1600 * register A channel 0 (read/write).
1601 * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
1602 * register A channel 0 (read/write).
1603 * DBSB0 Direct Memory Access (DMA) Buffer Start address
1604 * register B channel 0 (read/write).
1605 * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
1606 * register B channel 0 (read/write).
1607 *
1608 * DDAR1 Direct Memory Access (DMA) Device Address Register
1609 * channel 1 (read/write).
1610 * DCSR1 Direct Memory Access (DMA) Control and Status
1611 * Register channel 1 (read/write).
1612 * DBSA1 Direct Memory Access (DMA) Buffer Start address
1613 * register A channel 1 (read/write).
1614 * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
1615 * register A channel 1 (read/write).
1616 * DBSB1 Direct Memory Access (DMA) Buffer Start address
1617 * register B channel 1 (read/write).
1618 * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
1619 * register B channel 1 (read/write).
1620 *
1621 * DDAR2 Direct Memory Access (DMA) Device Address Register
1622 * channel 2 (read/write).
1623 * DCSR2 Direct Memory Access (DMA) Control and Status
1624 * Register channel 2 (read/write).
1625 * DBSA2 Direct Memory Access (DMA) Buffer Start address
1626 * register A channel 2 (read/write).
1627 * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
1628 * register A channel 2 (read/write).
1629 * DBSB2 Direct Memory Access (DMA) Buffer Start address
1630 * register B channel 2 (read/write).
1631 * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
1632 * register B channel 2 (read/write).
1633 *
1634 * DDAR3 Direct Memory Access (DMA) Device Address Register
1635 * channel 3 (read/write).
1636 * DCSR3 Direct Memory Access (DMA) Control and Status
1637 * Register channel 3 (read/write).
1638 * DBSA3 Direct Memory Access (DMA) Buffer Start address
1639 * register A channel 3 (read/write).
1640 * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
1641 * register A channel 3 (read/write).
1642 * DBSB3 Direct Memory Access (DMA) Buffer Start address
1643 * register B channel 3 (read/write).
1644 * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
1645 * register B channel 3 (read/write).
1646 *
1647 * DDAR4 Direct Memory Access (DMA) Device Address Register
1648 * channel 4 (read/write).
1649 * DCSR4 Direct Memory Access (DMA) Control and Status
1650 * Register channel 4 (read/write).
1651 * DBSA4 Direct Memory Access (DMA) Buffer Start address
1652 * register A channel 4 (read/write).
1653 * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
1654 * register A channel 4 (read/write).
1655 * DBSB4 Direct Memory Access (DMA) Buffer Start address
1656 * register B channel 4 (read/write).
1657 * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
1658 * register B channel 4 (read/write).
1659 *
1660 * DDAR5 Direct Memory Access (DMA) Device Address Register
1661 * channel 5 (read/write).
1662 * DCSR5 Direct Memory Access (DMA) Control and Status
1663 * Register channel 5 (read/write).
1664 * DBSA5 Direct Memory Access (DMA) Buffer Start address
1665 * register A channel 5 (read/write).
1666 * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
1667 * register A channel 5 (read/write).
1668 * DBSB5 Direct Memory Access (DMA) Buffer Start address
1669 * register B channel 5 (read/write).
1670 * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
1671 * register B channel 5 (read/write).
1672 */ 1593 */
1673 1594#define DMA_SIZE (6 * 0x20)
1674#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ 1595#define DMA_PHYS 0xb0000000
1675
1676#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
1677#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
1678#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
1679#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
1680#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
1681#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
1682#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
1683#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
1684
1685#define DDAR_RW 0x00000001 /* device data Read/Write */
1686#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
1687 /* (memory -> device) */
1688#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
1689 /* (device -> memory) */
1690#define DDAR_E 0x00000002 /* big/little Endian device */
1691#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
1692#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
1693#define DDAR_BS 0x00000004 /* device Burst Size */
1694#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
1695#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
1696#define DDAR_DW 0x00000008 /* device Data Width */
1697#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
1698#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
1699#define DDAR_DS Fld (4, 4) /* Device Select */
1700#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
1701 (0x0 << FShft (DDAR_DS))
1702#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
1703 (0x1 << FShft (DDAR_DS))
1704#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
1705 (0x2 << FShft (DDAR_DS))
1706#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
1707 (0x3 << FShft (DDAR_DS))
1708#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
1709 (0x4 << FShft (DDAR_DS))
1710#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
1711 (0x5 << FShft (DDAR_DS))
1712#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
1713 (0x6 << FShft (DDAR_DS))
1714#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
1715 (0x7 << FShft (DDAR_DS))
1716#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
1717 (0x8 << FShft (DDAR_DS))
1718#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
1719 (0x9 << FShft (DDAR_DS))
1720#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
1721 /* (audio) */ \
1722 (0xA << FShft (DDAR_DS))
1723#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
1724 /* (audio) */ \
1725 (0xB << FShft (DDAR_DS))
1726#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
1727 /* (telecom) */ \
1728 (0xC << FShft (DDAR_DS))
1729#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
1730 /* (telecom) */ \
1731 (0xD << FShft (DDAR_DS))
1732#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
1733 (0xE << FShft (DDAR_DS))
1734#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
1735 (0xF << FShft (DDAR_DS))
1736#define DDAR_DA Fld (24, 8) /* Device Address */
1737#define DDAR_DevAdd(Add) /* Device Address */ \
1738 (((Add) & 0xF0000000) | \
1739 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
1740#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
1741 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1742 DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1743#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
1744 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1745 DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1746#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
1747 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1748 DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
1749#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
1750 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1751 DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
1752#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
1753 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1754 DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
1755#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
1756 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1757 DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
1758#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
1759 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1760 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
1761#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
1762 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1763 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
1764#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
1765 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1766 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
1767#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
1768 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1769 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
1770#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
1771 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1772 DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
1773#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
1774 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1775 DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
1776#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
1777 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1778 DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1779#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
1780 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1781 DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1782#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
1783 /* (telecom) */ \
1784 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1785 DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1786#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
1787 /* (telecom) */ \
1788 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1789 DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1790#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
1791 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1792 DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
1793#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
1794 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1795 DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
1796
1797#define DCSR_RUN 0x00000001 /* DMA running */
1798#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
1799#define DCSR_ERROR 0x00000004 /* DMA ERROR */
1800#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
1801#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
1802#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
1803#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
1804#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
1805#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
1806#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
1807
1808#define DBT_TC Fld (13, 0) /* Transfer Count */
1809#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
1810#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
1811 1596
1812 1597
1813/* 1598/*
@@ -1903,16 +1688,6 @@
1903#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ 1688#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
1904 /* (Alternative) */ 1689 /* (Alternative) */
1905 1690
1906#define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */
1907#define LCSR __REG(0xB0100004) /* LCD Status Reg. */
1908#define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */
1909#define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */
1910#define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */
1911#define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */
1912#define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */
1913#define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */
1914#define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */
1915
1916#define LCCR0_LEN 0x00000001 /* LCD ENable */ 1691#define LCCR0_LEN 0x00000001 /* LCD ENable */
1917#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ 1692#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
1918#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 1693#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
diff --git a/arch/arm/mach-sa1100/include/mach/dma.h b/arch/arm/mach-sa1100/include/mach/dma.h
deleted file mode 100644
index dda1b351310..00000000000
--- a/arch/arm/mach-sa1100/include/mach/dma.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * arch/arm/mach-sa1100/include/mach/dma.h
3 *
4 * Generic SA1100 DMA support
5 *
6 * Copyright (C) 2000 Nicolas Pitre
7 *
8 */
9
10#ifndef __ASM_ARCH_DMA_H
11#define __ASM_ARCH_DMA_H
12
13#include "hardware.h"
14
15
16/*
17 * The SA1100 has six internal DMA channels.
18 */
19#define SA1100_DMA_CHANNELS 6
20
21/*
22 * Maximum physical DMA buffer size
23 */
24#define MAX_DMA_SIZE 0x1fff
25#define CUT_DMA_SIZE 0x1000
26
27/*
28 * All possible SA1100 devices a DMA channel can be attached to.
29 */
30typedef enum {
31 DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */
32 DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */
33 DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */
34 DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */
35 DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */
36 DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */
37 DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */
38 DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */
39 DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */
40 DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */
41 DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */
42 DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */
43 DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */
44 DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */
45 DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */
46 DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */
47 DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */
48 DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */
49} dma_device_t;
50
51typedef struct {
52 volatile u_long DDAR;
53 volatile u_long SetDCSR;
54 volatile u_long ClrDCSR;
55 volatile u_long RdDCSR;
56 volatile dma_addr_t DBSA;
57 volatile u_long DBTA;
58 volatile dma_addr_t DBSB;
59 volatile u_long DBTB;
60} dma_regs_t;
61
62typedef void (*dma_callback_t)(void *data);
63
64/*
65 * DMA function prototypes
66 */
67
68extern int sa1100_request_dma( dma_device_t device, const char *device_id,
69 dma_callback_t callback, void *data,
70 dma_regs_t **regs );
71extern void sa1100_free_dma( dma_regs_t *regs );
72extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
73extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
74extern void sa1100_reset_dma(dma_regs_t *regs);
75
76/**
77 * sa1100_stop_dma - stop DMA in progress
78 * @regs: identifier for the channel to use
79 *
80 * This stops DMA without clearing buffer pointers. Unlike
81 * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
82 * or sa1100_get_dma_pos().
83 *
84 * The @regs identifier is provided by a successful call to
85 * sa1100_request_dma().
86 **/
87
88#define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
89
90/**
91 * sa1100_resume_dma - resume DMA on a stopped channel
92 * @regs: identifier for the channel to use
93 *
94 * This resumes DMA on a channel previously stopped with
95 * sa1100_stop_dma().
96 *
97 * The @regs identifier is provided by a successful call to
98 * sa1100_request_dma().
99 **/
100
101#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
102
103/**
104 * sa1100_clear_dma - clear DMA pointers
105 * @regs: identifier for the channel to use
106 *
107 * This clear any DMA state so the DMA engine is ready to restart
108 * with new buffers through sa1100_start_dma(). Any buffers in flight
109 * are discarded.
110 *
111 * The @regs identifier is provided by a successful call to
112 * sa1100_request_dma().
113 **/
114
115#define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
116
117#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index d18f21abef8..9e07634a467 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -82,11 +82,3 @@
82#else 82#else
83#define NR_IRQS (IRQ_BOARD_START) 83#define NR_IRQS (IRQ_BOARD_START)
84#endif 84#endif
85
86/*
87 * Board specific IRQs. Define them here.
88 * Do not surround them with ifdefs.
89 */
90#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0)
91#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1)
92#define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2)
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
index ffe2bc45eed..5516a52a329 100644
--- a/arch/arm/mach-sa1100/include/mach/neponset.h
+++ b/arch/arm/mach-sa1100/include/mach/neponset.h
@@ -15,54 +15,6 @@
15/* 15/*
16 * Neponset definitions: 16 * Neponset definitions:
17 */ 17 */
18
19#define NEPONSET_CPLD_BASE (0x10000000)
20#define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
21#define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
22
23#define _IRR 0x10000024 /* Interrupt Reason Register */
24#define _AUD_CTL 0x100000c0 /* Audio controls (RW) */
25#define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */
26#define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */
27#define _NCR_0 0x100000a0 /* Control Register (RW) */
28#define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */
29#define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */
30#define _SWPK 0x10000020 /* Switch pack (RO) */
31#define _WHOAMI 0x10000000 /* System ID Register (RO) */
32
33#define _LEDS 0x10000010 /* LEDs [31:0] (WO) */
34
35#define IRR (*((volatile u_char *) Nep_p2v(_IRR)))
36#define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
37#define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
38#define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
39#define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0)))
40#define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
41#define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
42#define SWPK (*((volatile u_char *) Nep_p2v(_SWPK)))
43#define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI)))
44
45#define LEDS (*((volatile Word *) Nep_p2v(_LEDS)))
46
47#define IRR_ETHERNET (1<<0)
48#define IRR_USAR (1<<1)
49#define IRR_SA1111 (1<<2)
50
51#define AUD_SEL_1341 (1<<0)
52#define AUD_MUTE_1341 (1<<1)
53
54#define MDM_CTL0_RTS1 (1 << 0)
55#define MDM_CTL0_DTR1 (1 << 1)
56#define MDM_CTL0_RTS2 (1 << 2)
57#define MDM_CTL0_DTR2 (1 << 3)
58
59#define MDM_CTL1_CTS1 (1 << 0)
60#define MDM_CTL1_DSR1 (1 << 1)
61#define MDM_CTL1_DCD1 (1 << 2)
62#define MDM_CTL1_CTS2 (1 << 3)
63#define MDM_CTL1_DSR2 (1 << 4)
64#define MDM_CTL1_DCD2 (1 << 5)
65
66#define NCR_GP01_OFF (1<<0) 18#define NCR_GP01_OFF (1<<0)
67#define NCR_TP_PWR_EN (1<<1) 19#define NCR_TP_PWR_EN (1<<1)
68#define NCR_MS_PWR_EN (1<<2) 20#define NCR_MS_PWR_EN (1<<2)
@@ -71,4 +23,8 @@
71#define NCR_A0VPP (1<<5) 23#define NCR_A0VPP (1<<5)
72#define NCR_A1VPP (1<<6) 24#define NCR_A1VPP (1<<6)
73 25
26void neponset_ncr_frob(unsigned int, unsigned int);
27#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
28#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
29
74#endif 30#endif
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index ec27d6e1214..a0d1114c45e 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -21,7 +21,7 @@
21#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ 21#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */
22#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ 22#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */
23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ 23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
24#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ 24#define SHANNON_GPIO_DISP_EN 22 /* out */
25/* XXX GPIO 23 unaccounted for */ 25/* XXX GPIO 23 unaccounted for */
26#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ 26#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */
27#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 27#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index dfbf824a69f..5d12a305f53 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -221,11 +221,8 @@ static struct irq_chip sa1100_normal_chip = {
221 .irq_set_wake = sa1100_set_wake, 221 .irq_set_wake = sa1100_set_wake,
222}; 222};
223 223
224static struct resource irq_resource = { 224static struct resource irq_resource =
225 .name = "irqs", 225 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
226 .start = 0x90050000,
227 .end = 0x9005ffff,
228};
229 226
230static struct sa1100irq_state { 227static struct sa1100irq_state {
231 unsigned int saved; 228 unsigned int saved;
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index ee121d6f048..8be8130baf6 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -46,7 +46,7 @@
46 46
47/* memory space (line 52 of HP's doc) */ 47/* memory space (line 52 of HP's doc) */
48#define SA1111REGSTART 0x40000000 48#define SA1111REGSTART 0x40000000
49#define SA1111REGLEN 0x00001fff 49#define SA1111REGLEN 0x00002000
50#define EPSONREGSTART 0x48000000 50#define EPSONREGSTART 0x48000000
51#define EPSONREGLEN 0x00100000 51#define EPSONREGLEN 0x00100000
52#define EPSONFBSTART 0x48200000 52#define EPSONFBSTART 0x48200000
@@ -174,16 +174,8 @@ static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
174}; 174};
175 175
176static struct resource s1d13xxxfb_resources[] = { 176static struct resource s1d13xxxfb_resources[] = {
177 [0] = { 177 [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
178 .start = EPSONFBSTART, 178 [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
179 .end = EPSONFBSTART + EPSONFBLEN,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
183 .start = EPSONREGSTART,
184 .end = EPSONREGSTART + EPSONREGLEN,
185 .flags = IORESOURCE_MEM,
186 }
187}; 179};
188 180
189static struct platform_device s1d13xxxfb_device = { 181static struct platform_device s1d13xxxfb_device = {
@@ -197,20 +189,13 @@ static struct platform_device s1d13xxxfb_device = {
197}; 189};
198 190
199static struct resource sa1111_resources[] = { 191static struct resource sa1111_resources[] = {
200 [0] = { 192 [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
201 .start = SA1111REGSTART, 193 [1] = DEFINE_RES_IRQ(IRQ_GPIO1),
202 .end = SA1111REGSTART + SA1111REGLEN,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = IRQ_GPIO1,
207 .end = IRQ_GPIO1,
208 .flags = IORESOURCE_IRQ,
209 },
210}; 194};
211 195
212static struct sa1111_platform_data sa1111_info = { 196static struct sa1111_platform_data sa1111_info = {
213 .irq_base = IRQ_BOARD_END, 197 .irq_base = IRQ_BOARD_END,
198 .disable_devs = SA1111_DEVID_PS2_MSE,
214}; 199};
215 200
216static u64 sa1111_dmamask = 0xffffffffUL; 201static u64 sa1111_dmamask = 0xffffffffUL;
@@ -284,11 +269,6 @@ static struct map_desc jornada720_io_desc[] __initdata = {
284 .pfn = __phys_to_pfn(EPSONFBSTART), 269 .pfn = __phys_to_pfn(EPSONFBSTART),
285 .length = EPSONFBLEN, 270 .length = EPSONFBLEN,
286 .type = MT_DEVICE 271 .type = MT_DEVICE
287 }, { /* SA-1111 */
288 .virtual = 0xf4000000,
289 .pfn = __phys_to_pfn(SA1111REGSTART),
290 .length = SA1111REGLEN,
291 .type = MT_DEVICE
292 } 272 }
293}; 273};
294 274
@@ -352,11 +332,8 @@ static struct flash_platform_data jornada720_flash_data = {
352 .nr_parts = ARRAY_SIZE(jornada720_partitions), 332 .nr_parts = ARRAY_SIZE(jornada720_partitions),
353}; 333};
354 334
355static struct resource jornada720_flash_resource = { 335static struct resource jornada720_flash_resource =
356 .start = SA1100_CS0_PHYS, 336 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
357 .end = SA1100_CS0_PHYS + SZ_32M - 1,
358 .flags = IORESOURCE_MEM,
359};
360 337
361static void __init jornada720_mach_init(void) 338static void __init jornada720_mach_init(void)
362{ 339{
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index f50b00bd18a..b412fc09c80 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -198,3 +198,5 @@ static int __init jornada_ssp_init(void)
198{ 198{
199 return platform_driver_register(&jornadassp_driver); 199 return platform_driver_register(&jornadassp_driver);
200} 200}
201
202module_init(jornada_ssp_init);
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index eba64b78150..570f75fb73a 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -6,6 +6,8 @@
6#include <linux/kernel.h> 6#include <linux/kernel.h>
7#include <linux/tty.h> 7#include <linux/tty.h>
8 8
9#include <video/sa1100fb.h>
10
9#include <mach/hardware.h> 11#include <mach/hardware.h>
10#include <asm/setup.h> 12#include <asm/setup.h>
11#include <asm/mach-types.h> 13#include <asm/mach-types.h>
@@ -26,8 +28,85 @@ static struct mcp_plat_data lart_mcp_data = {
26 .sclk_rate = 11981000, 28 .sclk_rate = 11981000,
27}; 29};
28 30
31#ifdef LART_GREY_LCD
32static struct sa1100fb_mach_info lart_grey_info = {
33 .pixclock = 150000, .bpp = 4,
34 .xres = 320, .yres = 240,
35
36 .hsync_len = 1, .vsync_len = 1,
37 .left_margin = 4, .upper_margin = 0,
38 .right_margin = 2, .lower_margin = 0,
39
40 .cmap_greyscale = 1,
41 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
42
43 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
44 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
45};
46#endif
47#ifdef LART_COLOR_LCD
48static struct sa1100fb_mach_info lart_color_info = {
49 .pixclock = 150000, .bpp = 16,
50 .xres = 320, .yres = 240,
51
52 .hsync_len = 2, .vsync_len = 3,
53 .left_margin = 69, .upper_margin = 14,
54 .right_margin = 8, .lower_margin = 4,
55
56 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
57 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
58};
59#endif
60#ifdef LART_VIDEO_OUT
61static struct sa1100fb_mach_info lart_video_info = {
62 .pixclock = 39721, .bpp = 16,
63 .xres = 640, .yres = 480,
64
65 .hsync_len = 95, .vsync_len = 2,
66 .left_margin = 40, .upper_margin = 32,
67 .right_margin = 24, .lower_margin = 11,
68
69 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
70
71 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
72 .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
73};
74#endif
75
76#ifdef LART_KIT01_LCD
77static struct sa1100fb_mach_info lart_kit01_info = {
78 .pixclock = 63291, .bpp = 16,
79 .xres = 640, .yres = 480,
80
81 .hsync_len = 64, .vsync_len = 3,
82 .left_margin = 122, .upper_margin = 45,
83 .right_margin = 10, .lower_margin = 10,
84
85 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
86 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
87};
88#endif
89
29static void __init lart_init(void) 90static void __init lart_init(void)
30{ 91{
92 struct sa1100fb_mach_info *inf = NULL;
93
94#ifdef LART_GREY_LCD
95 inf = &lart_grey_info;
96#endif
97#ifdef LART_COLOR_LCD
98 inf = &lart_color_info;
99#endif
100#ifdef LART_VIDEO_OUT
101 inf = &lart_video_info;
102#endif
103#ifdef LART_KIT01_LCD
104 inf = &lart_kit01_info;
105#endif
106
107 if (inf)
108 sa11x0_register_lcd(inf);
109
31 sa11x0_ppc_configure_mcp(); 110 sa11x0_ppc_configure_mcp();
32 sa11x0_register_mcp(&lart_mcp_data); 111 sa11x0_register_mcp(&lart_mcp_data);
33} 112}
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 85f6ee67222..3923911000d 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -58,15 +58,8 @@ static struct flash_platform_data nanoengine_flash_data = {
58}; 58};
59 59
60static struct resource nanoengine_flash_resources[] = { 60static struct resource nanoengine_flash_resources[] = {
61 { 61 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M),
62 .start = SA1100_CS0_PHYS, 62 DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M),
63 .end = SA1100_CS0_PHYS + SZ_32M - 1,
64 .flags = IORESOURCE_MEM,
65 }, {
66 .start = SA1100_CS1_PHYS,
67 .end = SA1100_CS1_PHYS + SZ_32M - 1,
68 .flags = IORESOURCE_MEM,
69 }
70}; 63};
71 64
72static struct map_desc nanoengine_io_desc[] __initdata = { 65static struct map_desc nanoengine_io_desc[] __initdata = {
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index b4fa53a1427..3297aa22cd7 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -1,89 +1,103 @@
1/* 1/*
2 * linux/arch/arm/mach-sa1100/neponset.c 2 * linux/arch/arm/mach-sa1100/neponset.c
3 *
4 */ 3 */
5#include <linux/kernel.h> 4#include <linux/err.h>
6#include <linux/init.h> 5#include <linux/init.h>
7#include <linux/tty.h>
8#include <linux/ioport.h> 6#include <linux/ioport.h>
9#include <linux/serial_core.h> 7#include <linux/irq.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/pm.h>
12#include <linux/serial_core.h>
13#include <linux/slab.h>
11 14
12#include <mach/hardware.h>
13#include <asm/mach-types.h> 15#include <asm/mach-types.h>
14#include <asm/irq.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
16#include <asm/mach/irq.h>
17#include <asm/mach/serial_sa1100.h> 17#include <asm/mach/serial_sa1100.h>
18#include <mach/assabet.h>
19#include <mach/neponset.h>
20#include <asm/hardware/sa1111.h> 18#include <asm/hardware/sa1111.h>
21#include <asm/sizes.h> 19#include <asm/sizes.h>
22 20
23/* 21#include <mach/hardware.h>
24 * Install handler for Neponset IRQ. Note that we have to loop here 22#include <mach/assabet.h>
25 * since the ETHERNET and USAR IRQs are level based, and we need to 23#include <mach/neponset.h>
26 * ensure that the IRQ signal is deasserted before returning. This
27 * is rather unfortunate.
28 */
29static void
30neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
31{
32 unsigned int irr;
33
34 while (1) {
35 /*
36 * Acknowledge the parent IRQ.
37 */
38 desc->irq_data.chip->irq_ack(&desc->irq_data);
39
40 /*
41 * Read the interrupt reason register. Let's have all
42 * active IRQ bits high. Note: there is a typo in the
43 * Neponset user's guide for the SA1111 IRR level.
44 */
45 irr = IRR ^ (IRR_ETHERNET | IRR_USAR);
46
47 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
48 break;
49
50 /*
51 * Since there is no individual mask, we have to
52 * mask the parent IRQ. This is safe, since we'll
53 * recheck the register for any pending IRQs.
54 */
55 if (irr & (IRR_ETHERNET | IRR_USAR)) {
56 desc->irq_data.chip->irq_mask(&desc->irq_data);
57 24
58 /* 25#define NEP_IRQ_SMC91X 0
59 * Ack the interrupt now to prevent re-entering 26#define NEP_IRQ_USAR 1
60 * this neponset handler. Again, this is safe 27#define NEP_IRQ_SA1111 2
61 * since we'll check the IRR register prior to 28#define NEP_IRQ_NR 3
62 * leaving. 29
63 */ 30#define WHOAMI 0x00
64 desc->irq_data.chip->irq_ack(&desc->irq_data); 31#define LEDS 0x10
32#define SWPK 0x20
33#define IRR 0x24
34#define KP_Y_IN 0x80
35#define KP_X_OUT 0x90
36#define NCR_0 0xa0
37#define MDM_CTL_0 0xb0
38#define MDM_CTL_1 0xb4
39#define AUD_CTL 0xc0
40
41#define IRR_ETHERNET (1 << 0)
42#define IRR_USAR (1 << 1)
43#define IRR_SA1111 (1 << 2)
44
45#define MDM_CTL0_RTS1 (1 << 0)
46#define MDM_CTL0_DTR1 (1 << 1)
47#define MDM_CTL0_RTS2 (1 << 2)
48#define MDM_CTL0_DTR2 (1 << 3)
49
50#define MDM_CTL1_CTS1 (1 << 0)
51#define MDM_CTL1_DSR1 (1 << 1)
52#define MDM_CTL1_DCD1 (1 << 2)
53#define MDM_CTL1_CTS2 (1 << 3)
54#define MDM_CTL1_DSR2 (1 << 4)
55#define MDM_CTL1_DCD2 (1 << 5)
56
57#define AUD_SEL_1341 (1 << 0)
58#define AUD_MUTE_1341 (1 << 1)
65 59
66 if (irr & IRR_ETHERNET) { 60extern void sa1110_mb_disable(void);
67 generic_handle_irq(IRQ_NEPONSET_SMC9196);
68 }
69 61
70 if (irr & IRR_USAR) { 62struct neponset_drvdata {
71 generic_handle_irq(IRQ_NEPONSET_USAR); 63 void __iomem *base;
72 } 64 struct platform_device *sa1111;
65 struct platform_device *smc91x;
66 unsigned irq_base;
67#ifdef CONFIG_PM_SLEEP
68 u32 ncr0;
69 u32 mdm_ctl_0;
70#endif
71};
73 72
74 desc->irq_data.chip->irq_unmask(&desc->irq_data); 73static void __iomem *nep_base;
75 }
76 74
77 if (irr & IRR_SA1111) { 75void neponset_ncr_frob(unsigned int mask, unsigned int val)
78 generic_handle_irq(IRQ_NEPONSET_SA1111); 76{
79 } 77 void __iomem *base = nep_base;
78
79 if (base) {
80 unsigned long flags;
81 unsigned v;
82
83 local_irq_save(flags);
84 v = readb_relaxed(base + NCR_0);
85 writeb_relaxed((v & ~mask) | val, base + NCR_0);
86 local_irq_restore(flags);
87 } else {
88 WARN(1, "nep_base unset\n");
80 } 89 }
81} 90}
82 91
83static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) 92static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
84{ 93{
85 u_int mdm_ctl0 = MDM_CTL_0; 94 void __iomem *base = nep_base;
95 u_int mdm_ctl0;
96
97 if (!base)
98 return;
86 99
100 mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
87 if (port->mapbase == _Ser1UTCR0) { 101 if (port->mapbase == _Ser1UTCR0) {
88 if (mctrl & TIOCM_RTS) 102 if (mctrl & TIOCM_RTS)
89 mdm_ctl0 &= ~MDM_CTL0_RTS2; 103 mdm_ctl0 &= ~MDM_CTL0_RTS2;
@@ -106,14 +120,19 @@ static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
106 mdm_ctl0 |= MDM_CTL0_DTR1; 120 mdm_ctl0 |= MDM_CTL0_DTR1;
107 } 121 }
108 122
109 MDM_CTL_0 = mdm_ctl0; 123 writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
110} 124}
111 125
112static u_int neponset_get_mctrl(struct uart_port *port) 126static u_int neponset_get_mctrl(struct uart_port *port)
113{ 127{
128 void __iomem *base = nep_base;
114 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; 129 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
115 u_int mdm_ctl1 = MDM_CTL_1; 130 u_int mdm_ctl1;
116 131
132 if (!base)
133 return ret;
134
135 mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
117 if (port->mapbase == _Ser1UTCR0) { 136 if (port->mapbase == _Ser1UTCR0) {
118 if (mdm_ctl1 & MDM_CTL1_DCD2) 137 if (mdm_ctl1 & MDM_CTL1_DCD2)
119 ret &= ~TIOCM_CD; 138 ret &= ~TIOCM_CD;
@@ -138,209 +157,279 @@ static struct sa1100_port_fns neponset_port_fns __devinitdata = {
138 .get_mctrl = neponset_get_mctrl, 157 .get_mctrl = neponset_get_mctrl,
139}; 158};
140 159
141static int __devinit neponset_probe(struct platform_device *dev) 160/*
161 * Install handler for Neponset IRQ. Note that we have to loop here
162 * since the ETHERNET and USAR IRQs are level based, and we need to
163 * ensure that the IRQ signal is deasserted before returning. This
164 * is rather unfortunate.
165 */
166static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
142{ 167{
143 sa1100_register_uart_fns(&neponset_port_fns); 168 struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
169 unsigned int irr;
144 170
145 /* 171 while (1) {
146 * Install handler for GPIO25. 172 /*
147 */ 173 * Acknowledge the parent IRQ.
148 irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); 174 */
149 irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler); 175 desc->irq_data.chip->irq_ack(&desc->irq_data);
150 176
151 /* 177 /*
152 * We would set IRQ_GPIO25 to be a wake-up IRQ, but 178 * Read the interrupt reason register. Let's have all
153 * unfortunately something on the Neponset activates 179 * active IRQ bits high. Note: there is a typo in the
154 * this IRQ on sleep (ethernet?) 180 * Neponset user's guide for the SA1111 IRR level.
155 */ 181 */
156#if 0 182 irr = readb_relaxed(d->base + IRR);
157 enable_irq_wake(IRQ_GPIO25); 183 irr ^= IRR_ETHERNET | IRR_USAR;
158#endif
159 184
160 /* 185 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
161 * Setup other Neponset IRQs. SA1111 will be done by the 186 break;
162 * generic SA1111 code.
163 */
164 irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
165 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
166 irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
167 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
168 187
169 /* 188 /*
170 * Disable GPIO 0/1 drivers so the buttons work on the module. 189 * Since there is no individual mask, we have to
171 */ 190 * mask the parent IRQ. This is safe, since we'll
172 NCR_0 = NCR_GP01_OFF; 191 * recheck the register for any pending IRQs.
192 */
193 if (irr & (IRR_ETHERNET | IRR_USAR)) {
194 desc->irq_data.chip->irq_mask(&desc->irq_data);
173 195
174 return 0; 196 /*
175} 197 * Ack the interrupt now to prevent re-entering
198 * this neponset handler. Again, this is safe
199 * since we'll check the IRR register prior to
200 * leaving.
201 */
202 desc->irq_data.chip->irq_ack(&desc->irq_data);
176 203
177#ifdef CONFIG_PM 204 if (irr & IRR_ETHERNET)
205 generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
178 206
179/* 207 if (irr & IRR_USAR)
180 * LDM power management. 208 generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
181 */
182static unsigned int neponset_saved_state;
183 209
184static int neponset_suspend(struct platform_device *dev, pm_message_t state) 210 desc->irq_data.chip->irq_unmask(&desc->irq_data);
185{ 211 }
186 /*
187 * Save state.
188 */
189 neponset_saved_state = NCR_0;
190 212
191 return 0; 213 if (irr & IRR_SA1111)
214 generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
215 }
192} 216}
193 217
194static int neponset_resume(struct platform_device *dev) 218/* Yes, we really do not have any kind of masking or unmasking */
219static void nochip_noop(struct irq_data *irq)
195{ 220{
196 NCR_0 = neponset_saved_state;
197
198 return 0;
199} 221}
200 222
201#else 223static struct irq_chip nochip = {
202#define neponset_suspend NULL 224 .name = "neponset",
203#define neponset_resume NULL 225 .irq_ack = nochip_noop,
204#endif 226 .irq_mask = nochip_noop,
205 227 .irq_unmask = nochip_noop,
206static struct platform_driver neponset_device_driver = {
207 .probe = neponset_probe,
208 .suspend = neponset_suspend,
209 .resume = neponset_resume,
210 .driver = {
211 .name = "neponset",
212 },
213};
214
215static struct resource neponset_resources[] = {
216 [0] = {
217 .start = 0x10000000,
218 .end = 0x17ffffff,
219 .flags = IORESOURCE_MEM,
220 },
221};
222
223static struct platform_device neponset_device = {
224 .name = "neponset",
225 .id = 0,
226 .num_resources = ARRAY_SIZE(neponset_resources),
227 .resource = neponset_resources,
228};
229
230static struct resource sa1111_resources[] = {
231 [0] = {
232 .start = 0x40000000,
233 .end = 0x40001fff,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = IRQ_NEPONSET_SA1111,
238 .end = IRQ_NEPONSET_SA1111,
239 .flags = IORESOURCE_IRQ,
240 },
241}; 228};
242 229
243static struct sa1111_platform_data sa1111_info = { 230static struct sa1111_platform_data sa1111_info = {
244 .irq_base = IRQ_BOARD_END, 231 .irq_base = IRQ_BOARD_END,
232 .disable_devs = SA1111_DEVID_PS2_MSE,
245}; 233};
246 234
247static u64 sa1111_dmamask = 0xffffffffUL; 235static int __devinit neponset_probe(struct platform_device *dev)
236{
237 struct neponset_drvdata *d;
238 struct resource *nep_res, *sa1111_res, *smc91x_res;
239 struct resource sa1111_resources[] = {
240 DEFINE_RES_MEM(0x40000000, SZ_8K),
241 { .flags = IORESOURCE_IRQ },
242 };
243 struct platform_device_info sa1111_devinfo = {
244 .parent = &dev->dev,
245 .name = "sa1111",
246 .id = 0,
247 .res = sa1111_resources,
248 .num_res = ARRAY_SIZE(sa1111_resources),
249 .data = &sa1111_info,
250 .size_data = sizeof(sa1111_info),
251 .dma_mask = 0xffffffffUL,
252 };
253 struct resource smc91x_resources[] = {
254 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
255 0x02000000, "smc91x-regs"),
256 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
257 0x02000000, "smc91x-attrib"),
258 { .flags = IORESOURCE_IRQ },
259 };
260 struct platform_device_info smc91x_devinfo = {
261 .parent = &dev->dev,
262 .name = "smc91x",
263 .id = 0,
264 .res = smc91x_resources,
265 .num_res = ARRAY_SIZE(smc91x_resources),
266 };
267 int ret, irq;
268
269 if (nep_base)
270 return -EBUSY;
271
272 irq = ret = platform_get_irq(dev, 0);
273 if (ret < 0)
274 goto err_alloc;
275
276 nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
277 smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
278 sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
279 if (!nep_res || !smc91x_res || !sa1111_res) {
280 ret = -ENXIO;
281 goto err_alloc;
282 }
248 283
249static struct platform_device sa1111_device = { 284 d = kzalloc(sizeof(*d), GFP_KERNEL);
250 .name = "sa1111", 285 if (!d) {
251 .id = 0, 286 ret = -ENOMEM;
252 .dev = { 287 goto err_alloc;
253 .dma_mask = &sa1111_dmamask, 288 }
254 .coherent_dma_mask = 0xffffffff,
255 .platform_data = &sa1111_info,
256 },
257 .num_resources = ARRAY_SIZE(sa1111_resources),
258 .resource = sa1111_resources,
259};
260 289
261static struct resource smc91x_resources[] = { 290 d->base = ioremap(nep_res->start, SZ_4K);
262 [0] = { 291 if (!d->base) {
263 .name = "smc91x-regs", 292 ret = -ENOMEM;
264 .start = SA1100_CS3_PHYS, 293 goto err_ioremap;
265 .end = SA1100_CS3_PHYS + 0x01ffffff, 294 }
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269 .start = IRQ_NEPONSET_SMC9196,
270 .end = IRQ_NEPONSET_SMC9196,
271 .flags = IORESOURCE_IRQ,
272 },
273 [2] = {
274 .name = "smc91x-attrib",
275 .start = SA1100_CS3_PHYS + 0x02000000,
276 .end = SA1100_CS3_PHYS + 0x03ffffff,
277 .flags = IORESOURCE_MEM,
278 },
279};
280 295
281static struct platform_device smc91x_device = { 296 if (readb_relaxed(d->base + WHOAMI) != 0x11) {
282 .name = "smc91x", 297 dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
283 .id = 0, 298 readb_relaxed(d->base + WHOAMI));
284 .num_resources = ARRAY_SIZE(smc91x_resources), 299 ret = -ENODEV;
285 .resource = smc91x_resources, 300 goto err_id;
286}; 301 }
287 302
288static struct platform_device *devices[] __initdata = { 303 ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
289 &neponset_device, 304 if (ret <= 0) {
290 &sa1111_device, 305 dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
291 &smc91x_device, 306 NEP_IRQ_NR, ret);
292}; 307 if (ret == 0)
308 ret = -ENOMEM;
309 goto err_irq_alloc;
310 }
293 311
294extern void sa1110_mb_disable(void); 312 d->irq_base = ret;
295 313
296static int __init neponset_init(void) 314 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
297{ 315 handle_simple_irq);
298 platform_driver_register(&neponset_device_driver); 316 set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
317 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
318 handle_simple_irq);
319 set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
320 irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
299 321
300 /* 322 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
301 * The Neponset is only present on the Assabet machine type. 323 irq_set_handler_data(irq, d);
302 */ 324 irq_set_chained_handler(irq, neponset_irq_handler);
303 if (!machine_is_assabet())
304 return -ENODEV;
305 325
306 /* 326 /*
307 * Ensure that the memory bus request/grant signals are setup, 327 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
308 * and the grant is held in its inactive state, whether or not 328 * something on the Neponset activates this IRQ on sleep (eth?)
309 * we actually have a Neponset attached.
310 */ 329 */
330#if 0
331 enable_irq_wake(irq);
332#endif
333
334 dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
335 d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
336 nep_base = d->base;
337
338 sa1100_register_uart_fns(&neponset_port_fns);
339
340 /* Ensure that the memory bus request/grant signals are setup */
311 sa1110_mb_disable(); 341 sa1110_mb_disable();
312 342
313 if (!machine_has_neponset()) { 343 /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
314 printk(KERN_DEBUG "Neponset expansion board not present\n"); 344 writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
315 return -ENODEV;
316 }
317 345
318 if (WHOAMI != 0x11) { 346 sa1111_resources[0].parent = sa1111_res;
319 printk(KERN_WARNING "Neponset board detected, but " 347 sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
320 "wrong ID: %02x\n", WHOAMI); 348 sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
321 return -ENODEV; 349 d->sa1111 = platform_device_register_full(&sa1111_devinfo);
322 } 350
351 smc91x_resources[0].parent = smc91x_res;
352 smc91x_resources[1].parent = smc91x_res;
353 smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
354 smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
355 d->smc91x = platform_device_register_full(&smc91x_devinfo);
356
357 platform_set_drvdata(dev, d);
323 358
324 return platform_add_devices(devices, ARRAY_SIZE(devices)); 359 return 0;
360
361 err_irq_alloc:
362 err_id:
363 iounmap(d->base);
364 err_ioremap:
365 kfree(d);
366 err_alloc:
367 return ret;
325} 368}
326 369
327subsys_initcall(neponset_init); 370static int __devexit neponset_remove(struct platform_device *dev)
371{
372 struct neponset_drvdata *d = platform_get_drvdata(dev);
373 int irq = platform_get_irq(dev, 0);
374
375 if (!IS_ERR(d->sa1111))
376 platform_device_unregister(d->sa1111);
377 if (!IS_ERR(d->smc91x))
378 platform_device_unregister(d->smc91x);
379 irq_set_chained_handler(irq, NULL);
380 irq_free_descs(d->irq_base, NEP_IRQ_NR);
381 nep_base = NULL;
382 iounmap(d->base);
383 kfree(d);
328 384
329static struct map_desc neponset_io_desc[] __initdata = { 385 return 0;
330 { /* System Registers */ 386}
331 .virtual = 0xf3000000, 387
332 .pfn = __phys_to_pfn(0x10000000), 388#ifdef CONFIG_PM_SLEEP
333 .length = SZ_1M, 389static int neponset_suspend(struct device *dev)
334 .type = MT_DEVICE 390{
335 }, { /* SA-1111 */ 391 struct neponset_drvdata *d = dev_get_drvdata(dev);
336 .virtual = 0xf4000000, 392
337 .pfn = __phys_to_pfn(0x40000000), 393 d->ncr0 = readb_relaxed(d->base + NCR_0);
338 .length = SZ_1M, 394 d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);
339 .type = MT_DEVICE 395
340 } 396 return 0;
397}
398
399static int neponset_resume(struct device *dev)
400{
401 struct neponset_drvdata *d = dev_get_drvdata(dev);
402
403 writeb_relaxed(d->ncr0, d->base + NCR_0);
404 writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);
405
406 return 0;
407}
408
409static const struct dev_pm_ops neponset_pm_ops = {
410 .suspend_noirq = neponset_suspend,
411 .resume_noirq = neponset_resume,
412 .freeze_noirq = neponset_suspend,
413 .restore_noirq = neponset_resume,
414};
415#define PM_OPS &neponset_pm_ops
416#else
417#define PM_OPS NULL
418#endif
419
420static struct platform_driver neponset_device_driver = {
421 .probe = neponset_probe,
422 .remove = __devexit_p(neponset_remove),
423 .driver = {
424 .name = "neponset",
425 .owner = THIS_MODULE,
426 .pm = PM_OPS,
427 },
341}; 428};
342 429
343void __init neponset_map_io(void) 430static int __init neponset_init(void)
344{ 431{
345 iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc)); 432 return platform_driver_register(&neponset_device_driver);
346} 433}
434
435subsys_initcall(neponset_init);
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index 0d01ca78892..41bb018b310 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -135,12 +135,8 @@ struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys
135 &sys->resources); 135 &sys->resources);
136} 136}
137 137
138static struct resource pci_io_ports = { 138static struct resource pci_io_ports =
139 .name = "PCI IO", 139 DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
140 .start = 0x400,
141 .end = 0x7FF,
142 .flags = IORESOURCE_IO,
143};
144 140
145static struct resource pci_non_prefetchable_memory = { 141static struct resource pci_non_prefetchable_memory = {
146 .name = "PCI non-prefetchable", 142 .name = "PCI non-prefetchable",
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 9307df05353..ca5d33b6041 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -37,17 +37,9 @@
37#define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21 37#define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21
38 38
39static struct resource smc91x_resources[] = { 39static struct resource smc91x_resources[] = {
40 [0] = { 40 [0] = DEFINE_RES_MEM(PLEB_ETH0_P, 0x04000000),
41 .start = PLEB_ETH0_P,
42 .end = PLEB_ETH0_P | 0x03ffffff,
43 .flags = IORESOURCE_MEM,
44 },
45#if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */ 41#if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */
46 [1] = { 42 [1] = DEFINE_RES_IRQ(IRQ_GPIO_ETH0_IRQ),
47 .start = IRQ_GPIO_ETH0_IRQ,
48 .end = IRQ_GPIO_ETH0_IRQ,
49 .flags = IORESOURCE_IRQ,
50 },
51#endif 43#endif
52}; 44};
53 45
@@ -70,16 +62,8 @@ static struct platform_device *devices[] __initdata = {
70 * the two SA1100 lowest chip select outputs. 62 * the two SA1100 lowest chip select outputs.
71 */ 63 */
72static struct resource pleb_flash_resources[] = { 64static struct resource pleb_flash_resources[] = {
73 [0] = { 65 [0] = DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_8M),
74 .start = SA1100_CS0_PHYS, 66 [1] = DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_8M),
75 .end = SA1100_CS0_PHYS + SZ_8M - 1,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = SA1100_CS1_PHYS,
80 .end = SA1100_CS1_PHYS + SZ_8M - 1,
81 .flags = IORESOURCE_MEM,
82 }
83}; 67};
84 68
85 69
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 3efb4ac6224..08bb1228961 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -9,6 +9,8 @@
9#include <linux/mtd/mtd.h> 9#include <linux/mtd/mtd.h>
10#include <linux/mtd/partitions.h> 10#include <linux/mtd/partitions.h>
11 11
12#include <video/sa1100fb.h>
13
12#include <mach/hardware.h> 14#include <mach/hardware.h>
13#include <asm/mach-types.h> 15#include <asm/mach-types.h>
14#include <asm/setup.h> 16#include <asm/setup.h>
@@ -46,20 +48,32 @@ static struct flash_platform_data shannon_flash_data = {
46 .nr_parts = ARRAY_SIZE(shannon_partitions), 48 .nr_parts = ARRAY_SIZE(shannon_partitions),
47}; 49};
48 50
49static struct resource shannon_flash_resource = { 51static struct resource shannon_flash_resource =
50 .start = SA1100_CS0_PHYS, 52 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_4M);
51 .end = SA1100_CS0_PHYS + SZ_4M - 1,
52 .flags = IORESOURCE_MEM,
53};
54 53
55static struct mcp_plat_data shannon_mcp_data = { 54static struct mcp_plat_data shannon_mcp_data = {
56 .mccr0 = MCCR0_ADM, 55 .mccr0 = MCCR0_ADM,
57 .sclk_rate = 11981000, 56 .sclk_rate = 11981000,
58}; 57};
59 58
59static struct sa1100fb_mach_info shannon_lcd_info = {
60 .pixclock = 152500, .bpp = 8,
61 .xres = 640, .yres = 480,
62
63 .hsync_len = 4, .vsync_len = 3,
64 .left_margin = 2, .upper_margin = 0,
65 .right_margin = 1, .lower_margin = 0,
66
67 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
68
69 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
70 .lccr3 = LCCR3_ACBsDiv(512),
71};
72
60static void __init shannon_init(void) 73static void __init shannon_init(void)
61{ 74{
62 sa11x0_ppc_configure_mcp(); 75 sa11x0_ppc_configure_mcp();
76 sa11x0_register_lcd(&shannon_lcd_info);
63 sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); 77 sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
64 sa11x0_register_mcp(&shannon_mcp_data); 78 sa11x0_register_mcp(&shannon_mcp_data);
65} 79}
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 81506562ee2..3da4c1f11cf 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -177,15 +177,8 @@ static struct flash_platform_data simpad_flash_data = {
177 177
178 178
179static struct resource simpad_flash_resources [] = { 179static struct resource simpad_flash_resources [] = {
180 { 180 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_16M),
181 .start = SA1100_CS0_PHYS, 181 DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_16M),
182 .end = SA1100_CS0_PHYS + SZ_16M -1,
183 .flags = IORESOURCE_MEM,
184 }, {
185 .start = SA1100_CS1_PHYS,
186 .end = SA1100_CS1_PHYS + SZ_16M -1,
187 .flags = IORESOURCE_MEM,
188 }
189}; 182};
190 183
191static struct ucb1x00_plat_data simpad_ucb1x00_data = { 184static struct ucb1x00_plat_data simpad_ucb1x00_data = {
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index e8223315b44..30cc6721665 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -26,27 +26,36 @@
26 * 26 *
27 * Causes sa11x0 to enter sleep state 27 * Causes sa11x0 to enter sleep state
28 * 28 *
29 * Must be aligned to a cacheline.
29 */ 30 */
30 31 .balign 32
31ENTRY(sa1100_finish_suspend) 32ENTRY(sa1100_finish_suspend)
32 @ disable clock switching 33 @ disable clock switching
33 mcr p15, 0, r1, c15, c2, 2 34 mcr p15, 0, r1, c15, c2, 2
34 35
35 @ Adjust memory timing before lowering CPU clock 36 ldr r6, =MDREFR
36 @ Clock speed adjustment without changing memory timing makes 37 ldr r4, [r6]
37 @ CPU hang in some cases 38 orr r4, r4, #MDREFR_K1DB2
38 ldr r0, =MDREFR 39 ldr r5, =PPCR
39 ldr r1, [r0] 40
40 orr r1, r1, #MDREFR_K1DB2 41 @ Pre-load __udelay into the I-cache
41 str r1, [r0] 42 mov r0, #1
43 bl __udelay
44 mov r0, r0
45
46 @ The following must all exist in a single cache line to
47 @ avoid accessing memory until this sequence is complete,
48 @ otherwise we occasionally hang.
49
50 @ Adjust memory timing before lowering CPU clock
51 str r4, [r6]
42 52
43 @ delay 90us and set CPU PLL to lowest speed 53 @ delay 90us and set CPU PLL to lowest speed
44 @ fixes resume problem on high speed SA1110 54 @ fixes resume problem on high speed SA1110
45 mov r0, #90 55 mov r0, #90
46 bl __udelay 56 bl __udelay
47 ldr r0, =PPCR
48 mov r1, #0 57 mov r1, #0
49 str r1, [r0] 58 str r1, [r5]
50 mov r0, #90 59 mov r0, #90
51 bl __udelay 60 bl __udelay
52 61
@@ -85,12 +94,10 @@ ENTRY(sa1100_finish_suspend)
85 bic r5, r5, #FMsk(MSC_RT) 94 bic r5, r5, #FMsk(MSC_RT)
86 bic r5, r5, #FMsk(MSC_RT)<<16 95 bic r5, r5, #FMsk(MSC_RT)<<16
87 96
88 ldr r6, =MDREFR
89
90 ldr r7, [r6] 97 ldr r7, [r6]
91bic r7, r7, #0x0000FF00 98 bic r7, r7, #0x0000FF00
92bic r7, r7, #0x000000F0 99 bic r7, r7, #0x000000F0
93orr r8, r7, #MDREFR_SLFRSH 100 orr r8, r7, #MDREFR_SLFRSH
94 101
95 ldr r9, =MDCNFG 102 ldr r9, =MDCNFG
96 ldr r10, [r9] 103 ldr r10, [r9]
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 21:26:35 -0400